Protection Principle and Technology of the VSC-Based DC Grid [1st ed.] 9789811566431, 9789811566448

Table of contents :
Front Matter ....Pages i-x
Introduction (Bin Li, Jiawei He)....Pages 1-11
Working Principle and Basic Control Strategy of the VSC-HVDC Grid (Bin Li, Jiawei He)....Pages 13-39
DC Fault Characteristics of the VSC-HVDC System (Bin Li, Jiawei He)....Pages 41-63
High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid (Bin Li, Jiawei He)....Pages 65-101
High-Speed Differential Protection for the VSC-HVDC Grid (Bin Li, Jiawei He)....Pages 103-125
Traveling-Wave Based Direction Protection for the Multi-terminal HVDC Grid (Bin Li, Jiawei He)....Pages 127-153
DC Fault Current Limiting Technique Based on the H-bridge Topology (Bin Li, Jiawei He)....Pages 155-182
DC Fault Current Limiting Technique Based on the Current Commutation (Bin Li, Jiawei He)....Pages 183-213
Restart Control Strategy for the MMC-Based HVDC System (Bin Li, Jiawei He)....Pages 215-243
The DCCB Reclosing Strategy in VSC-HVDC Grid (Bin Li, Jiawei He)....Pages 245-274

Citation preview

Power Systems

Bin Li Jiawei He

Protection Principle and Technology of the VSC-Based DC Grid

Power Systems

Electrical power has been the technological foundation of industrial societies for many years. Although the systems designed to provide and apply electrical energy have reached a high degree of maturity, unforeseen problems are constantly encountered, necessitating the design of more efficient and reliable systems based on novel technologies. The book series Power Systems is aimed at providing detailed, accurate and sound technical information about these new developments in electrical power engineering. It includes topics on power generation, storage and transmission as well as electrical machines. The monographs and advanced textbooks in this series address researchers, lecturers, industrial engineers and senior students in electrical engineering. **Power Systems is indexed in Scopus**

More information about this series at http://www.springer.com/series/4622

Bin Li Jiawei He •

Protection Principle and Technology of the VSC-Based DC Grid

123

Bin Li School of Electrical and Information Engineering Tianjin University Tianjin, China

Jiawei He School of Electrical and Information Engineering Tianjin University Tianjin, China

ISSN 1612-1287 ISSN 1860-4676 (electronic) Power Systems ISBN 978-981-15-6643-1 ISBN 978-981-15-6644-8 (eBook) https://doi.org/10.1007/978-981-15-6644-8 © Springer Nature Singapore Pte Ltd. 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Contents

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Development of the HVDC Transmission Technology . . . 1.2 Outline of the HVDC Transmission Technology . . . . . . . . 1.2.1 Technical Superiority of the HVDC Transmission System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 The Typical HVDC Transmission Types . . . . . . . 1.3 Development of the VSC-HVDC Grid . . . . . . . . . . . . . . . 1.3.1 The Forms of the VSC-Based DC System . . . . . . 1.3.2 The Challenge of the DC Fault Protection in DC Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Working Principle and Basic Control Strategy of the VSC-HVDC Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Working Principle of the Two-Level VSC . . . . . . . . . . 2.1.1 Basic Topology of the Two-Level VSC . . . . . . 2.1.2 PWM Modulation Principle . . . . . . . . . . . . . . 2.1.3 Mathematical Model of the Two-Level VSC . . 2.2 Working Principle of Diode-Clamped Three-Level VSC 2.3 The Working Principle of the MMC . . . . . . . . . . . . . . 2.3.1 Topology of the MMC . . . . . . . . . . . . . . . . . . 2.3.2 Working Principle of the MMC . . . . . . . . . . . 2.3.3 Nearest Level Modulation . . . . . . . . . . . . . . . . 2.3.4 Mathematical Model of the MMC . . . . . . . . . . 2.4 Control Strategy of the VSC-Based DC Grid . . . . . . . . 2.4.1 The Valve-Level Control . . . . . . . . . . . . . . . . 2.4.2 The Station-Level Control . . . . . . . . . . . . . . . . 2.4.3 The System-Level Control . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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DC Fault Characteristics of the VSC-HVDC System . . . . . . 3.1 DC Fault Characteristics in the Two-Level VSC Based DC System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1.1 Pole-to-Pole Fault . . . . . . . . . . . . . . . . . . . . . . . 3.1.2 Pole-to-Ground Fault . . . . . . . . . . . . . . . . . . . . 3.1.3 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 DC Fault Characteristics in the MMC-Based DC System 3.2.1 Pole-to-Pole Fault . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Pole-to-Ground Fault . . . . . . . . . . . . . . . . . . . . 3.2.3 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 The Development of the Single-Ended Selective Protection for DC Line in VSC-HVDC Grid . . . . . . . . . . . . . . . . . . . . 4.1.1 The Line Protection in the LCC-HVDC System . . . . 4.1.2 The Line Protection in the VSC-HVDC Grid . . . . . . 4.1.3 The Direction Criterion for Excluding the Backward Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 The Conventional Traveling-Wave-Based Protection in the LCC-HVDC System . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 The Traveling Wave Characteristic of the Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.2 The Conventional Traveling-Wave-Based Protection in LCC-HVDC System . . . . . . . . . . . . . . . . . . . . . . 4.3 Analysis of the Frequency-Domain Traveling-Wave Boundary Characteristics After Different Fault Conditions . . . . . . . . . . 4.3.1 The Boundary Element in the VSC-HVDC Grid . . . 4.3.2 Transient Voltage Characteristic of the Internal and Forward External DC Faults . . . . . . . . . . . . . . . 4.3.3 Transient Voltage Characteristic of the Forward and Backward Faults . . . . . . . . . . . . . . . . . . . . . . . 4.4 A Novel Fast Single-Ended Protection Based on the Transient Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1 The Wavelet Transform . . . . . . . . . . . . . . . . . . . . . 4.4.2 The Novel Protection Scheme . . . . . . . . . . . . . . . . . 4.4.3 Protection Algorithm . . . . . . . . . . . . . . . . . . . . . . . 4.5 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1 Comparison and Discussion Between the Novel Fault Identification Criterion and the Existing Methods . . . 4.5.2 Comparison and Discussion Between the Novel Direction Criterion and the Existing Methods . . . . . . 4.5.3 The Improved Protection Algorithm . . . . . . . . . . . .

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The Operation Performance of the Novel Protection Under Different Conditions . . . . . . . . . . . . . . . . . . . . . Other Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

91 4.5.5 94 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5

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High-Speed Differential Protection for the VSC-HVDC Grid . . . 5.1 The Bergeron Model of the DC Transmission Line . . . . . . . . 5.1.1 The Distributed Characteristic of the Transmission Line Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 The Bergeron Model . . . . . . . . . . . . . . . . . . . . . . . 5.2 The Frequency-Domain Equivalent Model of the DC Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 The Traditional Current Differential Protection for the DC Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 The DC Pole-Current Differential Protection Based on the Bergeron Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 The Relationship Between the Differential Current and the Fault Point Current . . . . . . . . . . . . . . . . . . . 5.4.2 The Proposed DC Pole-Current Differential Protection Based on the Bergeron Model . . . . . . . . . 5.4.3 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 The Influence of the Parameters Frequency-Dependent Characteristics on the Differential Protection and the Improved Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 The Influence of the Line Parameters FrequencyDependent Characteristics on the Performance of the Current Differential Protection Based on the Bergeron Model . . . . . . . . . . . . . . . . . . . . . . 5.5.2 The Improved Strategy . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Traveling-Wave Based Direction Protection for the Multi-terminal HVDC Grid . . . . . . . . . . . . . . . . . . . . . . 6.1 The Existing Direction Protections in DC Grid . . . . . . . . . . 6.2 The Development of the Single-Ended Selective Protection for DC Line in VSC-HVDC Grid . . . . . . . . . . . . . . . . . . . 6.2.1 The TW Theory . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.2 Principle of the Traditional TW Based Direction Criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.3 The Applicability Analysis of the Traditional TW Based Direction Criterion in Multi-terminal HVDC Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 The Proposed Improved TW Based Direction Criterion . . . .

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Contents

6.3.1

The Basic Principle of the Improved Direction Criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 The Designed Improved Direction Criterion Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Complexity Evaluation of Wavelet Transform Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 The Influence of the DC Reactor on Reflection Coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Real-Time Simulation Case Studies . . . . . . . . . . . . . . . . . . 6.4.1 The Feasibility of the Traditional Direction Criteria 6.4.2 The Superiorities of the Improved Transient TW Based Direction Criterion . . . . . . . . . . . . . . . . . . . 6.4.3 Operation Performance of the Improved Direction Criterion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DC Fault Current Limiting Technique Based on the H-bridge Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Requirements on the Fault Current Limitation in DC Grid . 7.2 The H-bridge FCL Topology and Working Principle in DC Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Working Principle of the H-bridge FCL in the DC System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Coordination with the DCCB . . . . . . . . . . . . . . . . 7.3 The H-bridge Solid-State Circuit Breaker with Self-adaptive Fault Current Limiting Capability . . . . . . . . . . . . . . . . . . . 7.3.1 Topology and Working Principle of the H-bridge SSCB with Self-adaptive Fault Current Limiting Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3.2 Comparison with the Existing Methods . . . . . . . . . 7.4 Parameter Design and Hybrid Configuration for the Multi-terminal DC Grid . . . . . . . . . . . . . . . . . . . . . 7.4.1 Parameter Design of the Proposed SSCB . . . . . . . . 7.4.2 Hybrid Configuration of the DCCBs in the Multi-terminal DC Grid . . . . . . . . . . . . . . . . 7.4.3 Power Loss Analysis . . . . . . . . . . . . . . . . . . . . . . 7.5 Experiment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Test Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6 Simulation Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.6.1 Power Flow Shifting . . . . . . . . . . . . . . . . . . . . . . . 7.6.2 Fault Ride-Through of the Healthy Part of the System . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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DC Fault Current Limiting Technique Based on the Current Commutation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 The Proposed FCL Based on Current Commutation . . . . . 8.1.1 Topology of the Proposed FCL . . . . . . . . . . . . . . 8.1.2 Working Principle of the Proposed FCL . . . . . . . 8.1.3 The Control Strategy of the Proposed FCL . . . . . 8.1.4 Parameter Design of the Proposed FCL . . . . . . . . 8.2 Experiment Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2.1 DC Fault Without Fault Current Limitation . . . . . 8.2.2 DC Fault with DC Reactor Directly Installed . . . . 8.2.3 DC Fault with the Proposed FCL . . . . . . . . . . . . 8.2.4 Power Flow Shifting with Different FCLs . . . . . . 8.3 Simulation Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 DC Fault Overcurrent . . . . . . . . . . . . . . . . . . . . . 8.3.2 Healthy Network Ride-Through After DC Fault with the Proposed FCL . . . . . . . . . . . . . . . . . . . . 8.3.3 Power Flow Shifting with Different Fault Current Limiting Methods . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 Practical Application Discussion . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Restart Control Strategy for the MMC-Based HVDC System . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 MMC Sub-module with DC Fault Current Eliminating Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.1 The Problem of the Half-Bridge SM . . . . . . . . . . . . 9.2.2 The Topology and Working Principle of the MMC SM with DC Fault Current Eliminating Capability . . 9.3 Conventional Restart Control Strategy of the HVDC System Based on MMC with Self-eliminating Capability . . . . . . . . . 9.4 A Novel Restart Control Strategy for the MMC-Based HVDC Transmission System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.1 Uncontrolled Rectifier Operation Mode of the Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Proposed Restart Control Strategy . . . . . . . . . . . . . . 9.5 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Pole-to-Ground Fault . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Pole-to-Pole Fault . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.3 Feasibility in the Symmetric Monopolar Dc System . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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10 The DCCB Reclosing Strategy in VSC-HVDC Grid . . . . . . . . . . 10.1 Working Principle of DCCBs . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 The Working Principle of Mechanical DCCB . . . . . 10.1.2 The Working Principle of the Hybrid DCCB . . . . . . 10.2 Analysis of the Fault Line Residual Voltage Steady-State Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Equivalent Circuit of the Hybrid DCCB . . . . . . . . . 10.2.2 Equivalent Circuit of the DC Overhead Line . . . . . . 10.2.3 The Residual Voltage Steady-State Characteristic of the Fault Line . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Working Principle of the Proposed DCCB Reclosing Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 Reclosing Cooperation Between the DCCBs on the Fault Line . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Influence of the Transient Process Under Permanent Fault Condition and the Improved Measure . . . . . . . 10.3.4 Transient Current Analysis . . . . . . . . . . . . . . . . . . . 10.4 Case Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Damage of Reclosing the DCCB Directly . . . . . . . . 10.4.2 The Residual Voltage Characteristics . . . . . . . . . . . . 10.4.3 Performance of the Proposed Reclosing Strategy . . . 10.4.4 Robustness of the Proposed Reclosing Strategy . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Chapter 1

Introduction

1.1 Development of the HVDC Transmission Technology When the electric power was firstly applied, it was transferred based on the direct current. However, the early dc generator at the sending end and the dc motor at the receiving end are directly connected in series, so the reliability is very poor. In addition, it is difficult to transform the voltage in dc systems, and thus cannot realize the long-distance power transmission. At the end of the 19th century, the three-phase ac generator, induction motor and ac transformer were proposed successively. In view of the obvious advantages in the fields of power generation, transmission, distribution and power consumption, as well as the voltage transformation, the ac transmission and ac power system quickly occupied the dominant position in the electric power system. In the middle and late 20th century, the dc transmission technique began to attract high attention, with the rapid development of the high-voltage and large-capacity converter technology. The dc transmission technique has outstanding application prospect in the fields of long-distance and large-capacity power transmission, power grids interconnection, submarine cable transmission, and so on, because of the advantages including low transmission loss, large transmission capacity, no frequency stability problem, et al. [1]. However, at present, the power generation and consumption in the power system are mostly based on the alternating current. In order to apply the dc transmission, the power conversion technique must be researched. Therefore, the development of the dc transmission technology is highly related to the development of the converter technology, especially the high-voltage and large-capacity converter. While the main driving force of the converter technology innovation is the revolutionary breakthrough of the power electronic switches. In 1954, the world’s first industrial HVDC project (from Sweden to Gotland Island) was put into commercial operation. Up to 1977, there were 12 dc projects, using the mercury arc valve technique, being put into operation in the world. This period is also known as the mercury-conversion-valve period. However, the mercury

© Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_1

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2

1 Introduction

arc valve has some drawbacks, such as complex manufacturing technology, expensive price, high fault probability of the reverse arc, which limit the development of the dc transmission technology. In the 1970s, the operation performance and reliability of the dc transmission system are improved significantly, with the development of the high-voltage and large-capacity thyristors. In 1970, Sweden first built a 10 MW/50 kV thyristor-based converter valve experimental project on Gotland Island. In 1972, Canada built the world’s first dc transmission project completely using the thyristor-based converters. Due to its obvious technical advantages, the thyristor-based converter quickly replaced the mercury-arc-valve based converter, and the dc transmission technology came into a fast development period. In China, the HVDC transmission technique was also researched and applied widely. The advantages of the HVDC transmission technique, on the long-distance and large-capacity power transmission, interconnection of the power systems and so on, are verified. However, the thyristor does not have the self-turned-off capability, so the thyristorbased converter has a great dependence on the ac-side system, which becomes the main constraint. This is also the reason why the HVDC transmission system is also named as the line commutated converter based HVDC (LCC-HVDC). In the 1990s, a new type of full-controlled semiconductor device, namely, the insulated gate bipolar transistor (IGBT), began to be used in the dc transmission area [2, 3]. With the development of the high-voltage IGBT, it is possible to use the fullcontrolled switches to form the voltage source converter (VSC) for dc transmission and distribution. In 1997, the HVDC project based on the voltage source converter— Hershey experimental project was put into operation. The International Council on Large Electric systems (CIGRE) and the Institute of Electrical and Electronics Engineers (IEEE) named this new HVDC technology as the VSC-based HVDC (VSCHVDC) technology [4]. In China, this kind of HVDC is named as the flexible HVDC. The on and off states of the full-controlled power electronic switch can be controlled completely, thus can overcome the essential drawbacks of the LCC-HVDC system (mainly referring to the commutation failure). The control of the two-level VSC and three-level VSC is very simple, but they have the drawbacks including high harmonic content, large switching loss and so on. Meanwhile, the voltage tolerance and current tolerance of the IGBT are not very high, thus being difficult to be applied in the high-voltage and large-capacity power transmission area. At the beginning of the 21st century, the modular multilevel converter (MMC) topology was proposed, which significantly improved the operation efficiency of the VSC-HVDC transmission system, and promoted the development and application of the VSC-HVDC transmission technology. In 2010, the MMC-based HVDC transmission project—Trans Bay Cable project, was put into operation in America [5]. Since then, the theoretical research and engineering application based on the MMC technique have been developed rapidly. In 2011, the Shanghai Nanhui ±30 kV MMC-based dc project in China was put into operation. After that, a number of VSC-HVDC transmission projects have been successfully put into operation in China. At the same time, the development and application of modular multilevel structure in the field of dc transformer will further promote the development of the VSC-based dc transmission technology.

1.2 Outline of the HVDC Transmission Technology

3

1.2 Outline of the HVDC Transmission Technology 1.2.1 Technical Superiority of the HVDC Transmission System The HVDC transmission system mainly consists of the rectifier station, inverter station and dc transmission line. The topology of the 12-pulse LCC-HVDC transmission system is shown as Fig. 1.1. At the power transmission side, the ac power is rectified to the dc power, and the station realizing the power rectification is named as the rectifier station. At the power receiving side, the dc power is converted to ac power for the ac load, and the station realizing the power inversion is named as the inverter station. In the LCC-HVDC system, the thyristors are used to compose the converter. As we know, the thyristor has the unidirectional conducting characteristic, which means the current can only flow from the thyristor anode to the cathode. Therefore, the current in the LCC-HVDC system can only flow from the rectifier side to the inverter side. In the dc system, the dc voltage at the rectifier side should be a little larger than the inverter side, to guarantee the power transmission on the dc line, i.e., Id =

UdR − UdI RL

(1.1)

where the subscript R represents the rectifier side, and the subscript I represents the inverter side. U dR is the dc voltage at the rectifier side, and U dI is the dc voltage at the inverter side. In addition, RL is the equivalent resistance of the dc line. Obviously, the transmission powers of the ac transmission system and dc transmission system can be respectively expressed as rectifier station

dc line

inverter station Y Y

Y Y

Y

Y

grounding pole Y Y Y

Fig. 1.1 The typical LCC-HVDC system topology

Y Y Y

4

1 Introduction

Pac =

√ 3VN Iac cos ϕ = 3Vϕ,N Iac cos ϕ Pdc = Vdc Idc = 2Vd Idc

(1.2) (1.3)

where Pac and Pdc are the transmission powers of the ac transmission system and dc transmission system respectively. V N is the rated line voltage of the ac transmission system, V ϕ,N the rated phase voltage, I ac the rated current, and cosϕ is the power factor. V dc is the dc pole-to-pole voltage of the dc transmission system, V d the pole-to-ground voltage, and I dc is the dc line current. Supposing that the cross-sectional area and the insulation level of the ac transmission line and the dc transmission line are the same, it can be recognized that: (1) The current RMS on the ac line is the same as that on the dc line, namely, I dc = I ac . (2)√The voltage tolerance of the ac line is the same as that of the dc line, namely, V d = 2 · V ϕ ,N . Therefore, it can be obtained that √ 2 2 Pdc 2Vd Idc = = Pac 3Vϕ,N Iac cosϕ 3cosϕ

(1.4)

In the ac √ transmission system, the power factor cosϕ is generally close to 1. When cosϕ = 2 2/3 ≈ 0.9428, Pdc /Pac = 1. This means the transmission power of the dc line with two wires (Pdc ) is the same as that of the ac line with three wires (Pac ). From the aspect of the construction investment, the metal wire and insulating material required for unit length of dc line is one third less than that of the ac line. Moreover, in the case of overhead line application scene, the required corridor of the dc line can also be narrower, due to the smaller load of dc line tower. From the aspect of the operation cost, the transmission loss of the dc line is one third less than that of the ac line, because the wires number of dc line is one third less. In addition, the ac wire has larger power loss than that of the dc wire, due to the ac current skin effect. Moreover, the distributed capacitor current of the ac line is also much larger than that of the dc line, which leads to larger power loss. In addition, compared with the ac transmission, the dc transmission has some other advantages, including higher operation stability, interconnection of the asynchronous grids, and so on.

1.2.2 The Typical HVDC Transmission Types 1.2.2.1

The LCC-HVDC

Generally, the HVDC system based on thyristor-based converter is named as the traditional HVDC system, which also named as the line commutated converter HVDC (LCC-HVDC) system. The LCC-HVDC system has the advantages including long transmission distance, large transmission capacity, low transmission power loss,

1.2 Outline of the HVDC Transmission Technology

5

interconnection of the asynchronous grids, and so on. At present, the LCC-HVDC technology is very mature, and lots of practical projects have been put into operation around the world. However, the LCC-HVDC system also has some technical disadvantages. For example, the normal operation of the thyristor needs the ac power grid to provide commutation voltage. So the commutation failure will occur when it is connected with a weak ac power grid. In addition, the thyristor-based converter requires large reactive power, which means a large number of filters and capacitors should be installed at the ac side. Obviously, it increases the investment of the converter station, and may lead the ac bus voltage to increase. Moreover, during the power flow reverse, the dc voltage polarity should be reversed. Under this condition, the charging and discharging problem of the transmission line cannot be neglected.

1.2.2.2

The VSC-HVDC

With the rapid development of the power semiconductor devices, such as the largecapacity IGBT, the pulse width modulation (PWM) and multi-level control technologies begin to be used in the HVDC transmission area, promoting the application of the VSC-HVDC transmission system. The main difference between the VSC-HVDC and the LCC-HVDC is the converter station. At present, the typical VSC topologies mainly include the two-level VSC and the MMC, as shown in Fig. 1.2. The VSC uses the full-controlled IGBT switch, which avoids the commutation failure problem of the LCC-HVDC system. In addition, the VSC can control the active power and reactive power respectively, and can also operate in the STATCOM mode, to provide the reactive power for ac system. During the power flow reverse, the VSC-based dc system only needs to change the current direction, without changing the voltage polarity. Moreover, the filters and reactive compensation equipments can be reduced significantly in the VSC station, because the waveform quality of the VSC is much better than the LCC, and the VSC itself can control the reactive power. The VSC-HVDC also has some drawbacks. For example, the operation power loss of the VSC is larger than the LCC. The fault damage in the VSC-HVDC system is much more serious than that in the LCC-HVDC system, and the VSC itself does not have the dc fault handling capability. The technical characteristics of the LCC-HVDC system and the VSC-HVDC system are listed in Table 1.1. The MMC topology is shown as Fig. 1.2b. It uses the step wave to approach the sine wave during voltage modulation. When the voltage level number is large enough, the converter output ac voltage can be very close to the sine wave, thus reducing the harmonic component effectively. Compared with the two-level VSC or the three-level VSC, the switching loss of the IGBT can be significantly reduced when the step wave modulation is used. The modular design of the MMC avoids the IGBT series-connection problems, thus can be used in the higher voltage system. In addition, the capacitors in the MMC are distributedly installed in each sub-module, and there will be arm reactors in the converter, which can limit the dc fault current to a certain extent. But the MMC requires more IGBTs, resulting in higher investment.

6

1 Introduction

Il

Idc +

uabc R

L

C

va

vb

Udc N

vc

C

iabc −

+

SM1

SM1

SM1

SM2

SM2

SM2

+

C0

USM SMn

SMn

−

SMn

SM

arm reactor

uabc R

L

L0 phase unit

Udc

iabc

bridge arm

SM1

SM1

SM1

SM2

SM2

SM2

SMn

SMn

SMn −

Fig. 1.2 The typical VSC topologies

The topology and control are also more complex, which leads to new problems, such as the sub-module capacitor voltages balance control and the circulation control.

1.3 Development of the VSC-HVDC Grid Table 1.1 The technical characteristics of the LCC-HVDC and VSC-HVDC

Technical characters

7 LCC-HVDC

VSC-HVDC

Basic element

Thyristor

IGBT

Harmonic component

Large low-frequency harmonic component

Small high-frequency harmonic component

Reactive power/active power

Consume large reactive power

Controlled

Power loss

0.7%

1.6%

Capacity and voltage rating

6400 MW (±1000 kV)

>400–800 MW (300 kV)

Power flow reverse

Dc voltage polarity reverses

Current direction changes

DC fault handling

Adjust trigger angle

Uncontrolled

DC fault current

Small

Large

1.3 Development of the VSC-HVDC Grid 1.3.1 The Forms of the VSC-Based DC System 1.3.1.1

Multi-terminal HVDC Transmission System

In general, most of the HVDC projects are point-to-point, to realize the long-distance and large-capacity power transmission. In recent years, the multi-terminal HVDC transmission system has developed rapidly. The multi-terminal HVDC transmission system generally has more than three converter stations, which connect with each other in series, in parallel or in hybrid mode. This kind of transmission system can realize the multi-source power supply and multi-terminal power receiving. At present, some multi-terminal HVDC transmission system projects have been put into operation, such as the Italy—Corsica—Sardinia three-terminal DC system, Canada Quebec—New England five-terminal DC system, Japan Shinano threeterminal back-to-back DC system and Canada Nelson River four-terminal DC system, etc. In China, the 1000 MW, ±200 kV, Zhoushan five-terminal flexible DC transmission project, as shown in Fig. 1.3, was put into operation in 2014 [6].

1.3.1.2

DC Grid

With the development of the multi-terminal HVDC system, the converter station terminals number increases significantly, and the interconnection between different terminals through the dc lines becomes much closer, thus coming into a new dc system form, which is named as the dc grid. Compared with the multi-terminal dc

8

1 Introduction

±200 kV VSC ±50 kV LCC 110 kV AC 220 kV AC

Fig. 1.3 Zhoushan five-terminal flexible DC transmission project

system, the dc grid has lower investment, more operation states, and higher operation reliability. In Europe, the “Super Grid” concept was proposed, which is based on the dc grid. It connects the large-scale renewable energy power in remote areas and transfers it to the power consumption centers. In America, the dc transmission backbone-grid is proposed, to realize the large-scale interconnection of power grids. In China, the ±500 kV Zhangbei DC grid project, as shown in Fig. 1.4, is under construction [7]. In this project, three sending converter stations are built in Zhangbei, Kangbao and Fengning respectively. The capacity of Zhangbei station is 3000 MW, while those of Kangbao station and Fengning station are both 1500 MW. The 3000 MW receiving station is built in Beijing. In addition, the dc circuit breaker (DCCB) will be installed at each line terminal, cooperating with the high-speed selective dc protection. Obviously, the dc grid has become the development trend of the HVDC technology, and

Fig. 1.4 The Zhangbei DC grid project

1.3 Development of the VSC-HVDC Grid Zhejiang Zhoushan Five-terminal ±200kV, 1000MW

Shanghai Nanhui Two-terminal ±30kV, 18MW

Yunnan Luxi Two-terminal ±320kV, 1000MW

2015.12

2013.12 2011.5

9

2014.7 Guangdong Nan‫׳‬ao Three-terminal ±160kV, 200MW

2019.6 2016.3

Fujian Xiamen Two-termianl ±320kV, 1000MW

Wudongde Hybrid three-terminal ±800kV, 8000MW

under construction Yu‫׳‬e (Sichuan-Hubei) Two-terminal ±500kV, 5000MW

Zhangbei Four-terminal meshed ±500kV, 9000MW

Fig. 1.5 The development of the VSC-HVDC transmission systems in China

has attracted great attention around the world, both in the theoretical research and practical application.

1.3.1.3

The Development of the VSC-HVDC System in China

In recent years, the theoretical research and engineering application of the VSCHVDC technique have fast developed in China, as shown in Fig. 1.5. In 2011, the first VSC-HVDC transmission project in China was put into operation in Nanhui, Shanghai. This is a ±30 kV, 18 MW, two-terminal system, which effectively integrates the Nanhui wind farm into the Shanghai Power Grid. In 2013, the ±160 kV, 200 MW three-terminal VSC-HVDC transmission system was put into operation in Nan’ao Guangdong. It is the first multi-terminal VSC-HVDC system in the world, which realizes the integration and transmission of multiple wind farms. In 2014, the ±200 kV, 1000 MW five-terminal VSC-HVDC system was put into operation in Zhoushan, Zhejiang, which has the largest number of converter terminals (until 2014). From 2016 to 2019, several VSC-HVDC projects were put into operation respectively. The voltage and capacity were increased significantly. At present, the ±800 kV, 8000 MW Wudongde hybrid three-terminal system, and the ±500 kV, 9000 MW Zhangbei DC grid are under construction, which indicate that the voltage level and transmission capacity of the VSC-HVDC system become larger, meanwhile, the system topology and the operation mode become more complex.

1.3.2 The Challenge of the DC Fault Protection in DC Grid It should be pointed out that, there are still some technical difficulties, which limit the rapid development of the dc grid. And it is universally acknowledged that, the protection and handling of the dc fault are the key techniques for operation security and power supply reliability of the dc grid. (1) The damage of dc fault is great: In dc grid, a dc fault at any position may lead to a large-scale power outage. In most of the existing VSC-based dc grids, the dc cable is used to transmit the power, to reduce the fault probability. However, with the increasing of the voltage level and system capacity, it is obvious that the

10

1 Introduction

overhead line will be widely applied. How to deal with the dc fault becomes one of the key problems in the dc grid, because the fault probability of the overhead line is much higher than that of the dc cable. (2) The challenge of the protection in dc grid: The fault propagation speed in VSCbased dc grid is very high, thus requiring the dc protection can detect the fault and distinguish the fault line quickly in several milliseconds. Obviously, the traditional protections in ac system and LCC-HVDC system cannot satisfy the requirement of the VSC-based dc grid. For example, the distance protection and overcurrent protection in ac system cannot identify the fault line with selectivity. The traveling-wave protection in LCC-HVDC system does not have the capability against high transition resistance. For using in the VSC-based dc grid, this problem must be considered, because of the higher requirement on the power supply reliability. (3) The challenge of the dc isolation: The lack of natural-zero-crossing point of the dc fault current makes it difficult to be isolated. How to quickly isolate the fault line is the key technology for fault ride-through of the dc grid. At present, the dc fault isolating methods mainly include the converter self-eliminating technique and the DCCB technique. The typical half-bridge MMC cannot eliminate the dc fault current by itself. Therefore, some improved topologies have been proposed, which can eliminate the dc fault current by inserting the reverse capacitors voltage. This kind of isolating method is generally named as the converter selfeliminating technique. In dc grid, it is most ideal to isolate the fault line with selectivity by the DCCB. So the DCCB technology becomes one of the key techniques in the VSC-based dc grid. (4) The fault ride-through of the dc grid: After the dc fault, the fault line will be distinguished by the dc protection and then cut off by the DCCB. During the dc fault handling period, the whole system suffers the damage of the dc fault, including the healthy network and fault part. The fault ride-through of the dc grid mainly refers to that the healthy network in the dc grid can operate continuously during the fault handling period. However, the dc fault propagation speed is very high. For the fault ride-through of the healthy network, it even may require the dc fault line can be cut off in hundreds of microseconds. Obviously, the existing dc protection and dc fault isolation speed still cannot match the dc fault propagation speed. The dc fault current limiting method can limit the dc fault current effectively, thus reducing the requirement on the operating speeds of the dc protection and dc fault isolation, and guaranteeing the fault ride-through of the dc grid. Therefore, the dc fault current limiting technique becomes the key technique for the fault ride-through of the dc grid. In summary, the dc fault protection and fault handling are the key technologies in the VSC-based dc grid. In this book, the core techniques of the dc protection and fault handling are researched, mainly including the dc fault analysis, dc protection, dc fault current limitation, dc fault isolation, and dc fault recovery.

References

11

References 1. Kalair, A., Abas, N., & Khan, N. (2016). Comparative study of HVAC and HVDC transmission systems. Renewable and Sustainable Energy Reviews, 59, 1653–1675. 2. Ooi, B. T., & Wang, X. (1991). Boost-type PWM HVDC transmission system. IEEE Transactions on Power Delivery, 6(4), 1557–1563. 3. Ooi, B. T., & Wang, X. (2002). Voltage angle lock loop control of the boost type PWM converter for HVDC application. IEEE Transactions on Power Electronics, 5(2), 229–235. 4. Asplund, G., Eriksson, K., Jiang, H., et al. (1998). DC transmission based on voltage source converters. In Proceedings of 37th Sessions, Paris. 5. Teeuwsen, S. P. (2011). Modeling the trans bay cable project as voltage-sourced converter with modular multilevel converter design. In IEEE Power and Energy Society General Meeting, Detroit. 6. Tang, G., He, Z., Pang, H., et al. (2015, June). Basic topology and key devices of the five-terminal DC grid. CSEE Journal of Power and Energy Systems, 1(2), 22–35. 7. Tang, G., Pang, H., He, Z., & Wei, X. (2018). Research on key technology and equipment for Zhangbei 500 kV DC grid. In Proceedings of the IPEC, Niigata, Japan (pp. 2343–2351).

Chapter 2

Working Principle and Basic Control Strategy of the VSC-HVDC Grid

In the VSC-HVDC grid, the converter is the core equipment for energy conversion and control between ac side and dc side. The voltage source converter (VSC) based on the full-controlled power electronic switches has varied topologies and control strategies. According to the used modulation principles, the VSC type mainly includes the PWM based VSC (two-level VSC and three-level VSC) and the modular multilevel converter (MMC).

2.1 Working Principle of the Two-Level VSC 2.1.1 Basic Topology of the Two-Level VSC The three-phase two-level VSC realizes the AC/DC conversion based on the PWM principle [1]. And the basic topology of the two-level VSC is shown as Fig. 2.1. The VSC station mainly consists of the conversion transformer, conversion reactor, ac filter, converter and dc capacitor. The conversion transformer and conversion reactor are the link of the energy conversion between ac side and dc side. Generally, one of the two sides of the transformer is designed to be grounded, such as Yn/Y or Yn/, to eliminate the mutual influence of zero sequence components after the dc fault or ac fault. The conversion reactor increases the electrical distance between the ac system and the converter, which is the basis of the VSC ac-side output phase control, thus to realize the control of active power and reactive power. The function of the ac filter is to filter out the harmonic components in the square wave generated by PWM of the VSC. The filter interacts with the conversion reactor, conversion transformer and the system impedance, to create a low-impedance path for the high-frequency harmonic components. Therefore, the sine wave can be obtained. The topology of the converter circuit is the same as that of three-phase voltagetype bridge inverter circuit. Each phase consists of upper and lower bridge arms, © Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_2

13

14

2 Working Principle and Basic Control Strategy …

idc

il

+

uabc

R

L

C va vb

udc N vc

iabc

C −

Fig. 2.1 Topology of the three-phase two-level VSC

which are turned on and off by two switch groups. Generally, the switch device is composed of the IGBT and anti-parallel diode. At the dc-side outlet of the converter, there are two series-connected capacitors, which are used to guarantee the stability of the dc voltage. Generally, the connection point of the two capacitors is grounded, and considered as the voltage reference point. Therefore, if the voltage between the positive and negative poles is U dc , the positive and negative pole-to-ground voltages are +U dc /2 and −U dc /2 respectively.

2.1.2 PWM Modulation Principle The two-level VSC generally uses PWM to realize AC/DC conversion. And the bipolar modulation is adopted, because the VSC ac-side output voltage has two voltage levels for the dc-side voltage reference point. And when the standard sine wave is used as the modulation wave, the PWM is named as sine PWM (SPWM). In addition, the high-frequency triangular wave or sawtooth wave is selected as the carrier wave. The working principle of the SPWM can be described as Fig. 2.2. As shown in Fig. 2.2, the phase a, phase b and phase c use the same triangular carrier wave. And the sine waves ura , urb , and urc , which have the phase difference of 120° among each other, are selected as the SPWM modulation wave. The switches of the arms in the converter are controlled according to the comparison between the modulation wave and the carrier wave. Taking phase a for instance, when ura >uc , the IGBTs in the upper arm of phase a are turned on, and those in the lower arm are turned off. So the ac-side output voltage of phase a is equal to U dc /2. On the contrary, when ura < uc , the IGBTs in the upper arm of phase a are turned off, and those in the lower arm are turned on. So the ac-side output voltage of phase a is equal to −U dc /2. During the modulation, the gate signals on the IGBTs in upper and lower arms are always opposite, so the IGBTs will not be turned on synchronously. In addition, it

2.1 Working Principle of the Two-Level VSC

ura uc

15

urb

urc

amplitude

1 0

t

-1

amplitude

Udc /2 0

t

-Udc /2 Fig. 2.2 The working principle of the SPWM

should be noted that, the arm current may flow through the IGBT or the anti-parallel diode, when the on signal is given. The arms corresponding to the phase b and c are controlled on this principle as well. By the above modulation, the rectangular pulse waveform is obtained at the converter ac side. And the sine waveform can be obtained after filtering. According to the theoretical analysis, when the PWM is used, the harmonic components are mainly distributed around the high-frequency switching frequency and its integral-multiple frequencies. Therefore, the design difficulty of the filter is reduced significantly.

2.1.3 Mathematical Model of the Two-Level VSC The mathematical model is the basis for the VSC control strategy. As shown in Fig. 2.1, L is the equivalent inductance between the ac system and the converter, R is the equivalent resistance of the converter. The system-side ac voltage uabc and the converter-output ac voltage vabc satisfy di a + Ri a = u a − va dt di b + Ri b = u b − vb L dt di c + Ri c = u c − vc L dt du dc /2 C = i dc − il dt L

(2.1)

16

2 Working Principle and Basic Control Strategy …

namely, 1 di abc = (u abc − vabc − Ri abc ) dt L du dc = 2(i dc − il ). C dt

(2.2)

By the Parker Transformation, i.e., i dq0 = Pi abc

(2.3)

where ⎤ ⎡ cos ωt cos(ωt − 120◦ ) cos(ωt + 120◦ ) 2⎣ P= − sin ωt − sin(ωt − 120◦ ) − sin(ωt + 120◦ ) ⎦ 3 1 1 1 2

2

(2.4)

2

the equation in the abc coordinate system can be transformed to the equation in the dq0 coordinate system, i.e., di dq0 dP di abc = i abc + P dt dt dt

(2.5)

namely, ⎡ di ⎤ d

⎤⎡i ⎤ ⎡ ⎢ dt ⎥ a − sin ωt − sin(ωt − 120◦ ) − sin(ωt + 120◦ ) ⎢ ⎥ 2 ⎢ di q ⎥ ⎢ ⎥ ⎢ ⎥ = ω⎣ − cos ωt − cos(ωt − 120◦ ) − cos(ωt + 120◦ ) ⎦ ⎣ i b ⎦ ⎢ dt ⎥ 3 ⎣ ⎦ 0 0 0 ic di 0 dt ⎛⎡ ⎤ ⎡ ⎤ ⎡ ⎤⎞ ua va ia 1 ⎜⎢ ⎥ ⎢ ⎥ ⎢ ⎥⎟ +P · ⎝⎣ u b ⎦ − ⎣ vb ⎦ − R ⎣ i b ⎦⎠. L uc vc ic

(2.6)

Furthermore, it can be transformed to ⎡ di ⎤ d

⎡ ⎤ ⎡ ⎤ ⎡ ⎤ ⎤ ⎡ ⎢ dt ⎥ ud vd id iq ⎢ ⎥ 1⎢ ⎥ 1⎢ ⎥ 1⎢ ⎥ ⎢ di q ⎥ ⎥ ⎢ ⎢ ⎥ = ⎣ u q ⎦ − ⎣ vq ⎦ − ⎣ i q ⎦ + ω⎣ −i d ⎦. ⎢ dt ⎥ L L L ⎣ ⎦ u0 v0 i0 0 di 0 dt

(2.7)

2.1 Working Principle of the Two-Level VSC

17

During normal operation, the ac three-phase voltage and current are symmetrical. So the zero-axis component can be neglected, to obtain the dq mathematical model of the current transient response at the converter ac side, i.e., ⎧ di d ⎪ = u d − vd − Ri d + ωLi q ⎨ L dt ⎪ ⎩ L di q = u − v − Ri − ωLi . q q q d dt

(2.8)

2.2 Working Principle of Diode-Clamped Three-Level VSC The topology of the diode-clamped three-level VSC is shown in Fig. 2.3. The diodeclamped three-level VSC consists of three-phase six arms. Each phase is composed of four series-connected switches and two clamping diodes. And each series-connected switch is composed of the IGBT and the anti-parallel diode. Similar to the two-level VSC, at the dc output of the converter, there are two series-connected capacitors, guaranteeing the stability of the dc voltage. And the connection point of the two capacitors is grounded, which is considered as the voltage reference point. Taking phase a for instance, the IGBTs and anti-parallel diodes are named as T1 , DT1 , T2 , DT2 , T3 , DT3 , T4 , and DT4 respectively. The working principle can be described as following. State 1: Turn on T1 and T2 in the upper arm, and turn off T3 and T4 in the lower arm. When the converter is operating in the rectifier mode, the current flows from

il

idc +

usabc R

T1

DT1

T2

DT2

L

va

isabc T3

DT3

T4

DT4

C

D1

vb

udc N

vc

D2

C −

Fig. 2.3 Topology of the diode-clamped three-level VSC

18

2 Working Principle and Basic Control Strategy …

the ac side to the dc side through the anti-parallel diodes DT1 and DT2 . And when the converter is operating in the inverter mode, the current flows from the dc side to the ac side through IGBT T1 and T2 . In this state, the ac-side voltage is equal to the dc positive pole-to-ground voltage +U dc /2. State 2: Turn on T2 and T3 , and turn off T1 and T4 . Regardless of the rectifier mode or inverter mode, the ac side is connected to the dc-side zero voltage point N, when the impedance of the power electronic device is neglected. Therefore, the ac-side voltage of the converter is zero. State 3: Turn on T3 and T4 in the lower arm, and turn off T1 and T2 in the upper arm. When the converter is operating in the inverter mode, the current flows from the dc side to the ac side through the anti-parallel diodes DT3 and DT4 . And when the converter is operating in the rectifier mode, the current flows from the dc side to the ac side through IGBT T3 and T4 . In this state, the ac-side voltage is equal to the dc negative pole-to-ground voltage −U dc /2 (Fig. 2.4). According to the working principle of the diode-clamped three-level VSC, the ac-side output voltage of the converter can be expressed as Fig. 2.5, where the square wave modulation is used. In Fig. 2.5, va , vb and vc are the converter ac-side output voltages, while α is the trigger delay angle. Compared with two-level VSC, the threelevel VSC outputs three voltage levels, so the waveform distortion of the output voltages is smaller. However, the required number of power electronic switches in the three-level VSC is larger than that of the two-level VSC. Especially, with the voltage level increasing, the required number of the clamped diodes will increase further. Fig. 2.4 Working principle of the diode-clamped three-level VSC

il

idc

state1 +

usabc R

T1

DT1

T2

DT2 D1

L

va

state2

C udc N

isabc T3

DT3

T4

DT4

D2 state3

C −

2.3 The Working Principle of the MMC

19

va Udc /2 0

α

π

2π

α

π

2π

α

π

2π

-Udc /2 vb Udc /2 0 -Udc /2 vc Udc /2 0 -Udc /2 Fig. 2.5 AC-side output voltages of the diode-clamped three-level VSC with the square-wave modulation

2.3 The Working Principle of the MMC 2.3.1 Topology of the MMC The topology of the MMC is shown as Fig. 2.6 [2]. There are six arms in the converter, while each arm consists of N series-connected submodules (SMs) and one reactor. One upper arm and one lower arm form one phase unit. By adjusting the on-state SM number in each arm, the converter circuit operating state can be changed, to realize the flexible change of the ac-side output voltage. In addition, the withstand voltage of the converter arm is dependent on the SM number, and the withstand voltage of the detailed switch is dependent on the SM capacitor. Therefore, the problem of uneven voltage distribution caused by the series connection of switches can be overcomed, which is beneficial to increase the voltage grade, i.e., the application in the HVDC transmission area. The topology of the MMC SM is shown as Fig. 2.7. T1 and T2 represent the IGBT, D1 and D2 the anti-parallel diodes, and C 0 is the capacitor. In addition, uC is the SM capacitor voltage, usm the voltage at the SM port, ism the current flowing through

20

2 Working Principle and Basic Control Strategy …

idc + upa iabc

SM1

SM1

SM1

SM2

SM2

SM2

SM3

SM3

SM3

SMN

SMN

SMN

+

ipa udc

uvabc

+ una -

ina SM1

SM1

SM1

SM2

SM2

SM2

SM3

SM3

SM3

SMN

SMN

SMN

-

Fig. 2.6 Topology of the MMC

Fig. 2.7 Topology of the SM

T1

D1

ism

C

+ usm

T2

+ uC -

D2

-

the SM, whose reference direction are shown in Fig. 2.7. The SMs are connected in series with each other to form the converter arm. And the dc voltages are supported by the connected-in SM capacitors. There are three operating states of the SM. And in each operating state, there are two operating modes according to the current direction, as shown in Table 2.1. (1) Operating state 1—Turn off T1 and T2 . This state is named as the “blocking state”. According to different current directions, this state includes two operating modes, which are named as mode 1 and mode 4. Mode 1: The current flows into the SM through port A. In the SM, the current flows through the anti-parallel diode D1 and the capacitor C. So the capacitor

2.3 The Working Principle of the MMC

21

Table 2.1 The operating states and operating modes of the SM Operating state

ism > 0

State 1 (blocking state)

ism < 0

T1 A + usm

C T2

-

B

–

D2

T1

B

C T2

A + usm

D2

–

A + usm

-

B

+ uC

–

D2 mode 5

T1 C

mode 3

C T2

D1

T2

D1

ism

-

+ uC

–

mode 4

B

ism

+ uC

D2

T1 + uC

mode 2

State 3 (off state)

-

-

C

B

usm

D1

ism

D1

T2

-

A +

B

ism

usm

usm

–

D2

T1

A +

+ uC

mode 1

State 2 (on state) A +

T1

D1

ism

D1

ism

C T2

+ uC

–

D2 mode 6

is charged by the current. And the SM generally operates in this mode during the system starting period. Mode 4: The current outflows the SM through port A. In the SM, the current flows through the anti-parallel diode D2 , and the capacitor C is bypassed. The SM generally operates in this mode during the system abnormal operating state or fault condition, so as to protect the converter. (2) Operating state 2—Turn on T1 and turn off T2 . This state is named as the “on state”. Similarly, this state has two operating modes, which are named as mode 2 and mode 5. Mode 2: The current flows into the SM through port A. In the SM, the current flows through the anti-parallel diode D1 and the capacitor C. So the capacitor is charged by the current. Mode 5: The current outflows the SM through port A. In the SM, the current flows through the capacitor C and the anti-parallel diode D1 . And the capacitor is discharging.

22

2 Working Principle and Basic Control Strategy …

Table 2.2 The 3 operating states and 6 operating modes of the SM State

Mode

T1

T2

D1

D2

ism

usm

Capacitor

Blocking

1

0

0

1

0

>0

uC

Charge

4

0

0

0

1

0

uC

Charge

5

0

0

1

0

0

0

Bypassed

6

0

0

0

1

0 and k u > 0). Suppose the proportionality coefficients k p = 1 and k u = k i , where k i (i = 1, 2, …) are the droop coefficients of the stations (k i = −1/k). Under the steady state, the station applying droop control satisfies P = Pref + ki (Udcref − Udc )

(2.34)

According to (2.33) and (2.34), the droop controller is equivalent to a constant active power controller whose reference value changes with the system operation state. And the reference value of the active power can be calculated according to (2.34), which is related to the dc voltage of the system and the droop coefficient of the corresponding controller. For an n-terminal VSC-based dc grid, suppose the number of stations applying the droop control is m, and the other (n-m) stations apply the constant active power control. Meanwhile, suppose the dc voltage change values at different converter stations are the same, namely, U. After an unbalanced active power P occurs in the system, it can be obtained that P =

m  i=1

Pi = −Udc

m 

m Pi  ki = ki ki i=1 i=1

(2.35)

where Pi (Pi = Piref − Pi ) represents the unbalanced active power assigned to the station Si , (i = 1, 2, …, m). Furthermore,

38

2 Working Principle and Basic Control Strategy …

Pki Pi = m i=1 ki .

(2.36)

According to (2.36), the unbalance power assigned to the station Si is in positive proportion with its droop coefficient. Therefore, the conventional droop sets the droop coefficient according to the station capacity, i.e., Pimax ki = ∀i = j kj P jmax

(2.37)

where Pimax is the rated capacity of the station Si . According to (2.37), the station with larger capacity has larger droop coefficient, which therefore will undertake more unbalance power. So the droop coefficient can be calculated by, ki =

Pimax α(Udcmax − Udcref )

(2.38)

where U dcmax is the dc voltage upper limit, and U dcref is the rated dc voltage. In addition, α is the coefficient of the voltage fluctuation range, e.g., 0.9, which is used to keep the voltage fluctuation with the droop control in the allowed range. When several stations apply the droop control, the system stable operation point is very sensitive to the parameters of each droop control converter station. The droop control determines the system operation state by joint action of multiple converter stations, thus having strong flexibility and stability.

References 1. Rodriguez, J., Lai, J. S., & Peng, F. Z. (2007). Multilevel inverters: A survey of topologies, controls, and applications. IEEE Transactions on Industrial Electronics, 49(4), 724–738. 2. Lesnicar, A., & Marquardt, R. (2003, June). An innovative modular multilevel converter topology suitable for a wide power range. Presented at IEEE Power Tech Conference, Bologna, Italy. 3. Meshram, P. M., & Borghate, V. B. (2015). A simplified nearest level control (NLC) voltage balancing method for modular multilevel converter (MMC). IEEE Transactions on Power Electronics, 30(1), 450–462. 4. Li, B., Zhang, W., & He, J. (2019). Inertia emulation and dynamic voltage support scheme for MMC-based dc systems. IET Renewable Power Generation, 13(1), 146–154. 5. Akagi, H., Kanazawa, Y., & Nabae, A. (2008). Instantaneous reactive power compensators comprising switching devices without energy storage components. IEEE Transactions on Industry Applications, 20(3), 625–630. 6. Lu, W., & Ooi, B. T. (2007). Optimal acquisition and aggregation of offshore wind power by multiterminal voltage-source HVDC. IEEE Power Engineering Review, 22(8), 71–72. 7. Lu, W., & Ooi, B. T. (2005). Premium quality power park based on multi-terminal HVDC. IEEE Transactions on Power Delivery, 20(2), 978–983.

References

39

8. Sakamoto, K., Yajima, M., Ishikawa, T., et al. (1998). Development of a control system for a high-performance self-commutated AC/DC converter. IEEE Transactions on Power & Energy, 117, 225–232. 9. Nakajima, T., & Irokawa, S. (1999). A control system for HVDC transmission by voltage sourced converters. In Proceedings of the IEEE Power Engineering Society Summer Meeting, Edmonton, Alta (pp. 1113–1119).

Chapter 3

DC Fault Characteristics of the VSC-HVDC System

3.1 DC Fault Characteristics in the Two-Level VSC Based DC System In the dc system, the two-level VSC is widely applied, in which the typical dc fault types mainly include the pole-to-pole fault and pole-to-ground fault [1–4].

3.1.1 Pole-to-Pole Fault The pole-to-pole fault is the most serious fault in the VSC-based dc system, while the corresponding equivalent circuit is shown as Fig. 3.1. In Fig. 3.1, usabc represents the phase voltages of the ac system, while Rs and L s denote the equivalent resistance and inductance of ac system. The VSC consists of six series-connected IGBT units, and D1 –D6 represent the diodes parallel connected with the IGBTs. C is the capacitor parallel connected at the converter dc side, while R and L are the equivalent resistance and inductance of the dc line. In addition, the equivalent capacitor of the dc line is much smaller than the converter-dc-side parallel-connected capacitor C, thus being neglected. After dc pole-to-pole fault, the fault process can be divided into four stages as following.

3.1.1.1

Discharge of the DC Capacitor

At the initial stage of the pole-to-pole fault, the dc voltage udc is larger than the ac-side line voltage, so the dc fault current is mainly fed by the discharge of the dc capacitor, while the current fed from the ac side is only the arm reactor freewheeling current. The equivalent circuit of this stage can be simplified as Fig. 3.2. The corresponding transient response can be expressed as © Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_3

41

42

3 DC Fault Characteristics of the VSC-HVDC System

idc R/2 L/2 usabc

Ls

Rs

D3

D1

D5 +

udc

C

−

isabc

D6

D4

D2 R/2 L/2

Fig. 3.1 Equivalent circuit of the dc pole-to-pole fault

Fig. 3.2 Equivalent circuit of the capacitor discharge stage

L

R idc + udc -

LC

C

d2 u dc du dc + u dc = 0. + RC 2 dt dt

(3.1)

Generally, the equivalent√resistance of dc line is very small, thus the damping characteristic satisfies R < 2 (L/C), so the eigenvalues of (3.1) are a pair of conjugate complex values, i.e., λ1,2

R ± =− 2L



R 2L

2 −

1 = −σ ± jω LC

(3.2)

where ⎧ ⎨ σ = R/2L  ⎩ ω = 1/LC − (R/2L)2 . Supposing that the dc voltage and dc current at fault moment are U 0 and I 0 respectively, the time-domain solutions of udc and idc are

3.1 DC Fault Characteristics in the Two-Level VSC Based DC System

43

⎧ −σ t  ⎪ ⎨ u dc = Ae sin(ω t + θ )

C −σ t ⎪ ⎩ i dc = A e sin(ω t + θ − β) L

(3.3)

where  ⎧   ⎪ U0 σ I0 2 ⎪ ⎪ − ⎨ A = U02 + ω ω C     ⎪ ⎪ I0 U0 ⎪ ⎩ θ = arcsin , θ − β = arcsin . √ A A C/L According to (3.3), the dc capacitor discharge stage is a second-order underdamping oscillation process: the dc current increases extremely fast and the dc voltage oscillates across zero quickly.

3.1.1.2

Diodes Natural Commutation and Conduction Stage

When the dc voltage udc decreases below ac-side line voltage, the ac source begins to feed fault current to the fault point through the diodes in the converter. During this stage, the conduction of the diodes follow the natural commutation principle, thus being named as the diodes natural commutation and conduction stage. During this stage, both ac source and dc capacitor feed fault current to the fault point. The conduction of the diodes continuously changes with the ac voltage changing. So the transient process changes continuously, which means the transient solution should be calculated continuously. Taking the condition when D1 and D2 conduct for instance, the flowing path of fault current can be expressed as Fig. 3.3. Correspondingly, the transient response can be expressed as idc

D1 usabc

D3

Ls

Rs

isabc

D6

L/2

R/2

L/2

D5

+ udc − D4

R/2

C

D2

Fig. 3.3 Fault current flowing path during diode natural commutation and conduction stage

44

3 DC Fault Characteristics of the VSC-HVDC System

⎡ di ⎤ sa ⎡ ⎤ ⎡ ⎤⎡ ⎤ 1 ⎢ dt ⎥ Rs 1 i sa − 0 − ⎢ ⎢ ⎥ ⎥ ⎢ di dc ⎥ ⎢ L s R 12L s ⎥⎢ ⎥ ⎢ 2L s ⎥ ⎢ ⎥ = ⎣ 0 − L L ⎦⎣ i dc ⎦ + ⎢ ⎥u sac ⎢ dt ⎥ ⎣ 0⎦ 1 1 ⎣ ⎦ −C 0 u dc C du dc 0 dt

(3.4)

where isa , idc , and udc are the state quantities. The transient time-domain solutions of voltages and currents can be obtained by solving (3.4).

3.1.1.3

Diodes Synchronously Conduction

When the dc voltage udc oscillately decays to across zero, the reverse electromotive force of line inductance makes all the diodes in the converter conduct synchronously. During this period, the dc voltage is clamped at (approximately) zero by the conducting diodes, so the dc capacitor does not discharge anymore. And the dc side of the fault circuit can be equivalent to a first-order RL transient circuit. For the ac side, the diodes in the converter do not show unidirectional characteristic anymore, so it can be considered as a three-phase short circuit fault happening at the converter position. According to the superposition principle, this stage can be divided to ac-side three-phase short circuit and discharge of the dc fault line inductance, as shown in Fig. 3.4. Suppose that the moment dc voltage crossing zero is zero moment (namely t = 0), voltage of phase A usa = U m sin(ωt + ϕ 0 ), the initial value of phase A current is I a0 , and the initial value of dc line current is I 0  . According to Fig. 3.4, the fault currents of ac side and dc side can be calculated as i sa = Im sin(ωt + ϕ0 − ϕ) + [Ia0 − Ipm sin(ϕ0 − ϕ)]e− L s t Rs

usa

Rs

D1

Ls isa

usb

Rs

Ls isb

usc

Rs

Ls isc

(3.5)

idc

D4 D3 D6 D5

D1

D3

D5

L

D4

D6

D2

R

D2

(a) equivalent circuit of the ac side

(b) equivalent circuit of the dc side

Fig. 3.4 Equivalent circuit of the diodes synchronously conduction stage

3.1 DC Fault Characteristics in the Two-Level VSC Based DC System

i dc = I0 e− L t R

45

(3.6)

where ⎧ Um ⎪ ⎪ ⎪ Im =  2 ⎨ Rs + (ωL s )2   ⎪ ωL s ⎪ ⎪ . ⎩ ϕ = arctan Rs According to Fig. 3.4, the currents through the freewheeling diodes can be expressed as ⎧ 1 1 ⎪ ⎨ i D1 = i dc + i sa 3 2 ⎪ ⎩ i = 1i − 1i . D4 dc sa 3 2

(3.7)

As analyzed above, the dc current idc is a decay value during this period, and the three-phase short circuit fault current occurs at the ac side. Meanwhile, the freewheeling diodes suffer from the synchronous shock of the dc overcurrent and ac overcurrent, resulting in a serious damage.

3.1.1.4

Uncontrolled Rectifier Operation Stage

With the decrease of dc current, the freewheeling diodes begin to show the unidirectional characteristic, and thus the fault process comes into the uncontrolled rectifier operation stage finally. In this stage, the dc current is always not across zero, which is the essential reason why the arc extinguishing after dc fault is very difficult.

3.1.2 Pole-to-Ground Fault For the pole-to-ground fault, the positive pole-to-ground fault shown as Fig. 3.5a is analyzed for instance. In Fig. 3.5a, usabc represents the phase voltages of the ac system, Rs and L s denote the equivalent resistance and inductance of ac system, while udcp and udcn represent the positive and negative pole-to-ground voltages respectively. In addition, Rf is the fault transition resistance, C the capacitors parallel connected at the converter dc side, while R and L are the equivalent resistance and inductance of the dc line respectively. To simplify the theoretical analysis, it is supposed that the IGBTs in the converter are blocked immediately after the fault.

46

3 DC Fault Characteristics of the VSC-HVDC System idc +

udcp

usabc

−

Ll

C

+

udcn

isabc

Rl

Rf

C

−

(a) idc

C

Rl

idc

Ll

 udcp 

Rf

Ls usabc

C

 

Rl

udcp

(b)

Ll

Rf

(c)

Fig. 3.5 Equivalent circuit of the pole-to-ground fault

3.1.2.1

Discharge of the DC Capacitor

According to Fig. 3.5a, the dc fault current mainly fed by the dc capacitor at the fault pole, because the fault pole-to-ground voltage udcp is larger than ac phase voltage during initial stage of the fault. And the current fed from the ac side is only the freewheeling current of the ac reactor, which can be approximately neglected. Therefore, the equivalent circuit of this stage can be simplified to Fig. 3.5b, and the transient response can be expressed as LC

du dcp d2 u dcp + u dcp = 0 + RC dt 2 dt

(3.8)

where R = Rl + Rf and L = L l . Different from the dc pole-to-pole fault, the transition resistance should be considered for the pole-to-ground fault, which will affect the damping characteristic of the fault circuit. √ (1) R < 2 (L/C) √ When the transition resistance is not very large, and R < 2 (L/C), the eigenvalues of (3.8) are a pair of conjugate complex values, namely λ1,2

R ± =− 2L



R 2L

2 −

1 = −σ ± jω LC

(3.9)

3.1 DC Fault Characteristics in the Two-Level VSC Based DC System

47

where ⎧ ⎨ σ = R/2L  ⎩ ω = 1/LC − (R/2L)2 . Supposing that the initial values of the pole-to-ground voltage and dc current at fault moment are U p0 and I 0 respectively, the time-domain solutions of udcp and idc can be calculated as ⎧ −σ t  ⎪ ⎨ u dcp = Ae sin(ω t + θ )

(3.10) C −σ t ⎪ ⎩ i dc = A e sin(ω t + θ − β) L where  ⎧   ⎪ Up0 σ I0 2 ⎪ ⎪ 2 ⎪ A = U + − ⎪ p0 ⎪ ω ω C ⎪ ⎪ ⎨   Up0 θ = arcsin ⎪ ⎪ A ⎪ ⎪   ⎪ ⎪ I0 ⎪ ⎪ ⎩ θ − β = arcsin . √ A C/L √ (2) R > 2 (L/C) √ When the transition resistance is very large, and R > 2 (L/C), the eigenvalues of (3.8) are a pair of negative real values, namely λ1,2

R =− ± 2L



R 2L

2 −

1 . LC

(3.11)

And the corresponding solutions are u dcp = A1 eλ1 t + A2 eλ2 t   i dc = −C A1 λ1 eλ1 t + A2 λ2 eλ2 t where A1 =

I0 /C + λ2 Up0 I0 /C + λ1 Up0 , A2 = λ2 −λ1 λ1 −λ2

(3.12)

48

3 DC Fault Characteristics of the VSC-HVDC System

3.1.2.2

Current Fed from the AC Side

With the dc voltage decreasing, the ac-side source begins to feed fault current to the fault point, which can be equivalent to Fig. 3.5c. During this stage, it is difficult to obtain the time-domain analytical solutions of the voltage and current. However, the numerical solutions can be obtained from (3.13) by the numerical calculation method. ⎤⎡ ⎤ ⎡ ⎤ ⎡ du dcp ⎤ ⎡ 0 − C1 C1 0 u dcp dt Rl +R f ⎥⎣ 1 ⎦ ⎣ ⎣ didc ⎦ = ⎢ − 0 (3.13) + i 0 ⎦u s ⎣ ⎦ dc Ll Ll dt di s 1 is Ls 0 0 − Ls dt

3.1.3 Case Study The two-terminal two-level VSC-based dc system simulation model, shown as Fig. 3.6, is built. And the corresponding parameters are listed as Table 3.1. The pole-to-pole and pole-to-ground faults are simulated to verify the correctness of the theoretical analysis.

+

udc -

ac system

dc line

station

station

ac system

Fig. 3.6 The two-terminal two-level VSC-based dc system simulation model

Table 3.1 Parameters of the simulation model

Parameters

Value

Rated dc voltage/kV

±5

Rated capacity/MVA

10

DC capacitor/F

0.02

AC reactor/mH

10

Equivalent resistance of the line/(/km)

0.0139

Equivalent inductance of the line/(mH/km)

0.159

3.1 DC Fault Characteristics in the Two-Level VSC Based DC System

3.1.3.1

49

Pole-to-Pole Fault

In this case, the pole-to-pole fault is set to happen at t = 5 s, 10 km from the converter station. According to the system parameters listed in Table 3.1, the dc voltage and dc current after fault can be calculated. (1) dc voltage During the dc capacitor discharge stage and diodes natural commutation and conduction stage, the fault characteristic mainly performs as the RLC transient process. Substituting the system parameters into (3.3), the dc voltage during the former two stages can be calculated as u dc = 10640e−43.71t sin(171.86t + 1.36)

(3.14)

In addition, during the diodes synchronously conduction stage, the dc voltage is clamped at zero approximately by the conducting diodes. (2) dc current During the dc capacitor discharge stage and diodes natural commutation and conduction stage, the dc fault current mainly fed by the discharge of the dc capacitor. Therefore, the dc fault current can be calculated as i dc = 18868e−43.71t sin(171.86t + 0.04)

(3.15)

Differently, during the diodes synchronously conduction stage, the dc fault current mainly consists of the freewheeling current of the line inductance, which can be expressed as i dc = 10919e−87.42t

(3.16)

The simulation results and calculation results of the pole-to-pole fault are shown as Fig. 3.7. Obviously, the theoretical calculation results are very close to the simulation results, verifying the correctness of the theoretical analysis.

3.1.3.2

Pole-to-Ground Fault

For the pole-to-ground fault, the over damping and under damping conditions are simulated, to verify the correctness of the theoretical analysis. (1) Over damping condition In this case, the pole-to-ground fault with Rf = 0.6  is set to happen at t = 5 s 10 km from the converter station. The corresponding simulation results are shown as Fig. 3.8.

(a) dc voltage (kV)

50

3 DC Fault Characteristics of the VSC-HVDC System 12

capacitor discharge stage

10

udc (simulation result)

8

diodes natural commutation and conduction stage diodes synchronously conduction uncontrolled rectifier operation stage

6

udc (calculation result)

4 2 0

(b) dc current (kA)

14 12 10 8

idc (calculation result)

6

idc (simulation result)

4 2

(c) arm current (kA)

0 6 5

iarm_a

4

iarm_c

iarm_b

3 2 1 0

(d) ac current(kA)

3

ia

2

ib

ic

1 0 -1 -2 -3

4.98

4.99

5

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

5.1

Time(s)

Fig. 3.7 Simulation results of the pole-to-pole fault

As the simulation results showing, the positive pole-to-ground voltage udcp decreases quickly after the fault, due to the discharge of the capacitor. At the initial stage of the fault, the dc voltage is larger than the ac phase voltage, so the fault current fed from the ac side is very small, which can be neglected. Until the moment t 2 , the dc voltage decreases below the ac phase voltage, so the ac-side source begins to feed fault current to the fault point. However, at the initial period of this stage, the dc fault current is still mainly fed by the discharge capacitor. Obviously, the fault initial stage is focused for fault analysis, because the overcurrent problem and under voltage problem occur during this period.

(a) dc voltage (kV)

3.1 DC Fault Characteristics in the Two-Level VSC Based DC System t1

6 4

t2 u (simulation result) dcp udcp (calculation result)

51

usa usb usc

2 0 -2 -4

ac-side source feeding current

-6

capacitor discharge stage

(b) dc current (kA)

6

idcp (simulation result)

5

idcp (calculation result)

4 3 2 1 0

(c) arm current (kA)

2

iarm_a iarm_b iarm_c

1

0

(d) ac current(kA)

2

ia

ib

ic

1

0

-1 4.98

4.99

5

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

5.1

Time(s)

Fig. 3.8 Simulation result of the positive pole-to-ground fault with transition resistance

In sum, the discharge of the dc capacitor at the fault pole can be considered as the main characteristic of the pole-to-ground fault, to evaluate the dc fault current and voltage. Correspondingly, the fault pole-to-ground voltage and dc current can be calculated as u dcp = −1218e−382.6t + 6144e−82.2t

(3.17)

i dc = −9320e−382.6t + 10101e−82.2t

(3.18)

52

3 DC Fault Characteristics of the VSC-HVDC System

Use (3.17) and (3.18) to evaluate the fault pole-to-ground voltage and dc fault current during the initial period (20 ms) of the pole-to-ground fault. As Fig. 3.8a, b showing, the theoretical calculation results estimate the dc voltage and current correctly. This means it is feasible to take the capacitor discharge as the main characteristic of the pole-to-ground fault, for protection design, equipment selection and so on. (2) Under damping condition In this case, the metallic pole-to-ground fault is set to happen at t = 5 s, 10 km from the converter station. The corresponding simulation results are shown as Fig. 3.9. Similarly, the dc capacitor discharge is considered as the main characteristic during the initial period, to evaluate the fault pole-to-ground voltage and dc fault current, i.e., u dcp = 5032e−43.71t sin(171.86t + 1.37)

(3.19)

i dc = 17847e−43.71t sin(171.86t + 0.0438)

(3.20)

As shown in Fig. 3.9, the theoretical calculation results estimate the dc voltage and current correctly.

3.2 DC Fault Characteristics in the MMC-Based DC System Different from the two-level VSC, the MMC has advantages including better power quality, lower switching loss, lower requirement on the switches operation synchronicity and so on. Therefore, it has wider application prospect in the HVDC grid. In this section, the characteristics of the typical dc faults, including the poleto-pole fault and pole-to-ground fault, in the MMC-based dc system are analyzed in detail [5–9].

3.2.1 Pole-to-Pole Fault In the MMC-based dc system, the dc fault current increases quickly after pole-topole fault. To protect the converter, the sub-modules (SMs) in the converter will be blocked when the fault is detected. Therefore, the fault process of the pole-to-pole fault can be divided according to the blocking of the SMs.

3.2 DC Fault Characteristics in the MMC-Based DC System

53

(b) dc current (kA)

(a) dc voltage (kV)

capacitor discharge stage 6 5 4 3 2 1 0 -1 -2 -3 -4 -5

usa usb usc

udcp (simulation result) udcp (calculation result)

14 12 10 8 6 4 2 0 -2

idcp (simulation result) idcp (calculation result)

-4

(c) arm current (kA)

4

iarm_a iarm_b iarm_c

3 2 1 0

(d) ac current(kA)

4

ia

3

ib

ic

2 1 0 -1 4.98

4.99

5

5.01

5.02

5.03

5.04

5.05

5.06

5.07

5.08

5.09

5.1

Time(s)

Fig. 3.9 Simulation result of the metallic positive pole-to-ground fault

3.2.1.1

Before the SMs Being Blocked

The equivalent fault circuit before the SMs being blocked are shown as Fig. 3.10. During this stage, the dc fault current is mainly fed by the discharge of SM capacitors, and the SMs in the converter are still controlled by the normal operation control strategy. Therefore, in each phase, there are N SMs in on state and N SMs in off state (supposing that the voltage level of the converter is N + 1), where the capacitors in the on-state SMs discharge to the fault point. That means the easiest method is to simplify this stage to the equivalent circuit shown as Fig. 3.11a.

54

3 DC Fault Characteristics of the VSC-HVDC System

on-state SM

off-state SM

+

+

+

-

-

-

+

+

+

-

-

-

+

+

+

-

-

-

+

+

+

-

-

-

us isabc

Fig. 3.10 The equivalent circuit of the fault before the SMs being blocked

In fact, because of the SM capacitors balance control strategy, the on-state SMs constantly change during this stage. It is more reasonable to divide the SM capacitors to two groups (N SMs in each group), namely the on-state group and the off-state group. The capacitors in the on-state group discharge to the fault point, and the capacitors in the off-state group are bypassed, as shown in Fig. 3.11b. Due to the discharge process, the voltages of the capacitors in the on-state group will decrease. Therefore, according to the balance control strategy, the SM capacitors in the onstate group will be replaced by the SM capacitors in the off-state group constantly. In another word, the capacitors with larger energy will be connected into the discharge circuit constantly. It means that the actual discharge of the MMC is more serious than the condition shown as Fig. 3.11a. In addition, the actual discharge is weaker than the condition shown as Fig. 3.11c, where two SM capacitors groups (N capacitors in each group) are connected in parallel. In sum, the actual discharge degree of the SM capacitors is situated between the two conditions shown as Fig. 3.11a, c. To reflect the most serious damage of the fault, the discharge process shown as Fig. 3.11c is used to evaluate the fault current and voltage. Furthermore, Fig. 3.11c can be simplified to Fig. 3.11d. According to Fig. 3.11d, the transient response of this stage can be expressed as

3.2 DC Fault Characteristics in the MMC-Based DC System Ll/2

55 Ll/2

Rl/2

Ll/2

Rl/2

Rl/2

C/N

C/N 2L

2L 2R

2R (a)

Ll/2

Rl/2

Ll/2

Rl/2

(b) Ll/2

2C/N

6C/N

2L

2L/3

2R

2R/3 Ll/2

Rl/2

+ uc -

Rl/2

idc

Ll/2

(c)

Rl/2

(d)

Fig. 3.11 The simplified circuit of the fault before the SMs being blocked

L e Ce

d2 u c du c + uc = 0 + Re C e dt 2 dt

(3.21)

where L e = 2L/3 + L√ l , Re = 2R/3 + Rl , and C e = 6C/N . Generally, Re < 2 L e /Ce , so the SM capacitors discharge is a second-order under damping oscillation process. And the eigenvalues of (3.21) are a pair of conjugate complex values, i.e., λ1,2

Re =− ± 2L e



Re 2L e

2 −

1 = −σ ± jω L e Ce

(3.22)

 where σ = Re /2L e and ω = 1/L e Ce − (Re /2L e )2 . Suppose that the dc voltage and dc current at fault moment are U 0 and I 0 respectively. And the initial voltage of the series SM capacitors can also be approximately set as U 0 . The time-domain solutions of uc and idc can be calculated as ⎧ u = Ae−σ t sin(ω t + θ ) ⎪ ⎨ c  Ce −σ t ⎪ e sin(ω t + θ − β) ⎩ i dc = A Le

(3.23)

56

3 DC Fault Characteristics of the VSC-HVDC System

where  ⎧   ⎪ U0 σ I0 2 ⎪ ⎪ − ⎨ A = U02 + ω ω C e     ⎪ ⎪ I0 U0 ⎪ ⎩ θ = arcsin . , θ − β = arcsin √ A A Ce /L e According to (3.23), the capacitor voltage decreases quickly, and the dc current increases quickly during this stage. In addition, the dc fault current is affected by the SM capacitor, SM numbers and arm reactor. The dc fault current will be larger with larger SM capacitor, smaller SM numbers and smaller arm reactor. This characteristic is in accordance with the physical characteristic: The larger SM capacitor means the larger energy stored in the capacitor before the fault, so the discharge current is larger after the fault. The smaller SM number means that the value of C e is larger, so the discharge current will be larger because the energy in the capacitor is larger. In addition, the arm reactor can limit the dc fault current, so the smaller the reactor is, the larger the fault current will be.

3.2.1.2

Initial Stage After the SMs Being Blocked

With the fault current increasing, the SMs in the converter will be blocked when the arm current exceeds the threshold value of the IGBT self protection. At the initial stage after the SMs being blocked, the fault current can be divided to two parts, i.e., the current fed from the ac-side source and the freewheeling current of the arm reactor, as shown in Fig. 3.12a. Due to the freewheeling current of the arm reactor, the freewheeling diodes in the converter do not show unidirectional characteristic to the ac-side source. Therefore, for the ac-side source, it can be considered that a three-phase short circuit fault happens at the converter position, as shown in Fig. 3.12b. Obviously, the dc line is the neutral line for the ac-side source under this condition. This means the ac-side-sourcefeeding current will not flow to the dc side, and the dc fault current only consists of the freewheeling current of the arm reactor, which decays with the RL transient characteristic. According to the superposition principle, the ac-side-source-feeding current and the arm reactor freewheeling current can be divided to Fig. 3.12b, c. Suppose the initial value of dc current of this stage is I 0  , and the ac-side source voltage usk = U m sin(ωt + ϕ 0 ). The ac-side fault current and dc fault current can be calculated as i sk =

Um sin(ωt + ϕ0 − ϕ) |Z | i dc = I0 e−t/τ

(3.24) (3.25)

3.2 DC Fault Characteristics in the MMC-Based DC System

57

Rl/2

Ll/2

Rl/2

Ll/2

R

Rs

Ls

L

(a) equivalent circuit of the initial stage after SMs being blocked usk Rs isk

Ls

R

L

Ll/2

Rl/2

isk/2 isk/2

2L idc 2R

Ll/2

(b) ac-side-source-feeding current

Rl/2

(c) arm reactor freewheeling current

Fig. 3.12 Equivalent circuit of the initial stage after the SMs being blocked

   s +L/2) , and τ = where |Z | = (Rs + R/2)2 + ω2 (L s + L/2)2 , ϕ = arctan ω(L Rs +R/2 (2L/3 + L l )/(2R/3 + Rl ). In addition, the arm currents can be expressed as ⎧ il Um i sk 1 ⎪ ⎪ + = sin(ωt + ϕ0 − ϕ) + I0 e−t/τ ⎨ i kup = 2 3 2|Z | 3 i U i 1 ⎪ sk l m ⎪ ⎩ i kdown = − + = − sin(ωt + ϕ0 − ϕ) + I0 e−t/τ 2 3 2|Z | 3

(3.26)

58

3.2.1.3

3 DC Fault Characteristics of the VSC-HVDC System

Steady State After the SMs Being Blocked

With the decay of the arm reactor freewheeling current, the arm currents cross zero, so the diodes begin to show the unidirectional characteristic to the ac-side source. Therefore, the MMC finally operates as an uncontrolled rectifier. During this stage, the load impedance for the rectifier is only the fault line impedance, which means the fault current is still quite large.

3.2.2 Pole-to-Ground Fault The characteristics of the pole-to-ground in the MMC-based (monopole) dc system are slightly different with different grounding modes. At present, the grounding mode in the MMC-based dc system can be divided to two types, i.e., dc-side grounding mode and ac-side ground mode, as shown in Fig. 3.13. When the dc system is grounded at the dc side as shown in Fig. 3.13a, there is no flowing path for the fault current from ac-side system or converter to the fault point, so there is no fault current. Differently, when the dc system is grounded at the ac side, the flowing path, for the fault current from ac-side system or converter to the fault point, exists. However, as shown in Fig. 3.13b, c, a large grounding resistor is installed under this condition, which limits the pole-to-ground fault current to a very small level. Therefore, after the pole-to-ground fault, the fault current is very small, and the fault damage mainly caused by the overvoltage.

(a) grounding at dc side

(b) grounding at the transformer neutral point through a large resistor

(c) grounding through Y-connected reactor unit and large resistor at ac side

Fig. 3.13 Grounding modes in the MMC-based dc system

3.2 DC Fault Characteristics in the MMC-Based DC System

59

After the pole-to-ground fault, the fault pole-to-ground voltage immediately decreases to zero. And due to the control strategy of the MMC, the healthy pole-toground voltage increases to twice the rated value, thus resulting in damage to the insulation of the healthy pole. For the converter ac side, the voltage us satisfies u s = u dcp − u sp = u sn +u dcn

(3.27)

where udcp and udcn represent the positive and negative pole-to-ground voltages, while usp and usn represent the total capacitor voltages of upper arm and lower arm. Therefore, after a positive pole-to-ground fault, there is a negative biased voltage, − U dc /2, on the ac-side voltage. On the contrary, after a negative pole-to-ground fault, there is a positive biased voltage, U dc /2, on the ac-side voltage. Similarly, it will lead to overvoltage damage to the valve-side winding of the transformer.

3.2.3 Case Study The two-terminal MMC-based dc system simulation model is built based on the PSCAD/EMTDC, as shown in Fig. 3.14. And the system parameters are listed in Table 3.2. The pole-to-pole fault and pole-to-ground fault are simulated to verify the correctness of the theoretical analysis.

MMC2

MMC1

Fig. 3.14 The two-terminal MMC-based dc system simulation model

Table 3.2 Parameters of the simulation model

Parameters

Value

Rated dc voltage/kV

±200

Rated capacity/MVA

300

Rated ac voltage/kV

200

SM numbers per arm

101

SM capacitor/μF

9750

Arm reactor/mH

37.6

Equivalent resistance of the dc line/(/km)

0.055

Equivalent inductance of the dc line/(mH/km)

1.29

Length of the line/km

100

60

3 DC Fault Characteristics of the VSC-HVDC System

3.2.3.1

Pole-to-Pole Fault

In this case, the pole-to-pole fault is set to happen at t = 1 s, 10 km from the converter station, and the converter is set to be blocked 3 ms after the fault. According to the theoretical analysis and Table 3.2, the transient solution of dc current can be calculated as following. (1) Before the SMs being blocked According to Table 3.2, it can be calculated that Re = 2R/3 + Rl = 0.01 × 100/3 + 0.55 × 2 = 1.7667 , L e = 2L/3 + L l = 0.0376 × 2/3 + 0.0129 × 2 = 0.0509 H, −4 and C e = 6C/N = 6×9750 × 10−6 /100 = 5.85 × 10 F.  Therefore, σ = Re /2L e = 17.355, ω = 1/L e Ce − (Re /2L e )2 = 182.43 rad/s. Considering that U 0 = 408 kV and I 0 = 0.722 kA, the dc current during this stage can be calculated as i dc = 43.88e−17.355t sin(182.43t + 0.0165) (kA)

(3.28)

(2) Initial stage after the SMs being blocked According to Table 3.2 and (3.28), it can be calculated that τ = 0.0288 and I 0  = 22.2595 kA. So the dc current during this stage can be calculated as i dc = 22.2595e−t/0.0288

(3.29)

Figure 3.15 shows the simulation result and calculation result of the pole-to-pole fault. As shown in Fig. 3.15, the calculation result is very close to the simulation result, verifying the correctness of the theoretical analysis.

3.2.3.2

Pole-to-Ground Fault

In this case, the metallic positive pole-to-ground fault is set to happen at t = 1 s, 10 km from the converter station, and the corresponding simulation results are shown in Fig. 3.16. As shown in Fig. 3.16a, after the positive pole-to-ground fault, the fault pole-toground voltage udcp decreases to zero quickly. However, the dc voltage udc still keeps around the rated value 400 kV. So the healthy pole-to-ground voltage udcn increases to twice the rated value (about −200 kV × 2 = −400 kV). Meanwhile, there is a negative biased voltage, −200 kV, on the ac-side voltage. In addition, there are no overcurrents occurring at the ac side, dc side and in the converter after the fault.

3.2 DC Fault Characteristics in the MMC-Based DC System

(a) dc voltage (kV)

500 400 300

before the SMs being blocked initial stage after the SMs being blocked

udc

200 100

61

untrolled rectifier operation state

udcP

0 -100

udcN

-200 -300

(b) dc current (kA)

25 20

idc (calculation result)

15

idc (simulation result)

10 5 0

(c) arm current (kA)

12 10

iarma iarmb iarmc

8 6 4 2 0

(d) ac current(kA)

-2 10 8 6 4 2 0 -2 -4 -6 -8 -10 0.98

isa isb isc

0.99

1

1.01

1.02

1.03

1.04

1.05

1.06

1.07

1.08

Time(s)

Fig. 3.15 Simulation and calculation results of the pole-to-pole fault in the MMC-based dc system

The above simulation results are highly accordance with the theoretical analysis. And it can be concluded that, after the pole-to-ground fault, the main damage to the system is the insulation problem (healthy pole line and valve-side winding of the transformer) caused by the overvoltage.

(a) dc voltage (kV)

62

3 DC Fault Characteristics of the VSC-HVDC System 500 400 300 200 100 0 -100 -200 -300 -400 -500

udc

udcp

udcn

(b) dc current (kA)

2

1

0

iarma iarmb iarmc

(c) arm current (kA)

1

0

-1

(d) ac current(kA)

2

isa isb isc

1 0 -1 -2

(e) ac voltage(kV)

200 100

Esa Esb Esc

0 -100 -200 -300 -400

0.98

1

1.02

1.04

1.06

1.08

1.1

Time(s)

Fig. 3.16 Simulation results of the positive pole-to-ground fault in the monopole MMC-based dc system

References

63

References 1. Li, B., & He, J. (2015, June). DC fault analysis and current limiting technique for VSC-based dc distribution system. Proceedings of the CSEE, 35(12), 3026–3036 (in Chinese). 2. Yang, J., Fletcher, J. E., O’Reilly, J., et al. (2012). Short-circuit and ground fault analyses and location in VSC-Based dc network cables. IEEE Transactions on Industrial Electronics, 59(10), 3827–3837. 3. Yang, J., Fletcher, J. E., O’Reilly, J., et al. (2010). Multiterminal DC wind farm collection grid internal fault analysis and protection design. IEEE Transactions on Power Delivery, 25(4), 2308–2316. 4. Li, B., Liu, Y., Li, B., et al. Development process and analytical method of the pole-to-pole DC fault in the MMC-MVDC system. IET Power Electronics, 10(15), 2085–2091. 5. Wang, S., Zhou, X., Tang, G., et al. (2011, January). Analysis of submodule overcurrent caused by DC pole-to-pole fault in modular multilevel converter HVDC system. Proceedings of the CSEE, 31(1), 1–7. 6. Li, B., He, J., Tian, J., et al. (2017). DC fault analysis for MMC-based system. Journal of Modern Power Systems and Clean Energy, 5(2), 275–282. 7. Zhao, C., Li, T., Yu, L., et al. ( 2014, July). DC pole-to-ground fault characteristic analysis and converter fault recovery strategy of MMC-HVDC. Proceedings of the CSEE, 34(21), 3518–3526. 8. Zhang, J., & Zhao, C. (2014, July). Simulation and analysis of DC-link fault characteristics for MMC-HVDC. Electric Power Automation Equipment, 34(7), 32–37. 9. Gao, Y., Bazargan, M., Xu, L., et al. (2013). DC fault analysis of MMC based HVDC system for large offshore wind farm integration. In Proceedings of the 2nd IET Renewable Power Generation Conference, Beijing (pp. 1–4).

Chapter 4

High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

Compared with the line commutated converter (LCC) based HVDC transmission system, the dc fault propagation speed in the VSC-HVDC grid is much faster, which will damage the whole system in a few milliseconds [1]. In addition, in multi-terminal dc grid, only the fault line is expected to be cut off in consideration of the power supply reliability. Therefore, the fast and selective fault protection and isolation are indispensable [2]. At present, the selective protection for the dc line still needs to be researched further to satisfy the requirement of the VSC-HVDC grid, especially the acting speed and acting reliability. For enough acting speed, only the local information is expected to be used for the protection to identify the fault line. Therefore, in the dc grid, the single-ended protection is applied as the main protection for the dc line.

4.1 The Development of the Single-Ended Selective Protection for DC Line in VSC-HVDC Grid 4.1.1 The Line Protection in the LCC-HVDC System The dc line protection for LCC-HVDC transmission system is relative mature and has extensive experience in practical application, which is of great significance for the VSC-HVDC grid. At present, the single-ended traveling-wave-based protection schemes have been used as the main protection for the dc line in LCC-HVDC transmission system [3–6]. Thereamong, the traveling-wave-based dc protection proposed by ABB mainly uses the pole-mode wave and its derivative to identify the dc fault, meanwhile, it uses the earth-mode wave and its derivative to select the fault pole [3, 4]. This scheme can protect the whole range of the line, however, the robustness against high transition resistance and disturbance still needs to be improved. Siemens

© Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_4

65

66

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

proposed the protection based on the integration of the traveling wave, which can improve the anti-interference ability of the protection, but slow the acting speed [5]. In addition, there is another single-ended protection in practical engineering, whose main criterion is based on the rate of change of voltage (ROCOV) [6]. Actually, this protection is also dependent on the fault traveling wave generated by the fault point, and the ROCOV also reflects the traveling wave change rate. Therefore, in a sense, the protection based on the ROCOV also belongs to the traveling-wave protection. However, these conventional traveling-wave-based protection schemes cannot be directly applied in the VSC-HVDC grid, because the acting reliability under highresistance fault condition cannot be guaranteed. The reason will be analyzed in the following of this chapter in detail.

4.1.2 The Line Protection in the VSC-HVDC Grid Referenced from the protections for LCC-HVDC system, the protections for the dc line in VSC-HVDC grid are researched in recent years. Reference [7] researched the protection criterion based on the ROCOV for using in the VSC-HVDC grid, whose operation speed is accelerated by raising the sampling frequency. However, the robustness of the ROCOV based protection against high transition resistance is not discussed further. Reference [8] presented a protection scheme using the voltage wavelet, voltage change rate, and current wavelet, but the theoretical analysis is absent. In addition, it cannot protect the whole line, because the boundary element is not considered. Reference [9] proposed the protection scheme based on the ROCOV at the line side of the dc reactor to detect and locate the faults. And it excludes the backward faults by comparing the ROCOVs on both sides of the dc reactor. Based on [9], the Ref. [10] proposed a protection scheme based on the change rate of dc reactor voltage, which is applicable to the meshed multi-terminal HVDC grid with dc reactors installed at both ends of each line. In fact, the change rate of the dc reactor voltage is equivalent to the second derivative of the dc current, and this is the essential reason why the fault can be detected faster. Reference [11] proposed a non-unit protection scheme based on the reflection of the traveling wave at inductive terminations, which uses the voltage magnitude and derivative to distinguish the forward internal and external faults, while the backward fault is excluded by the current derivative. The above researches discussed the application of the traveling-wave-based protections in the VSC-HVDC grid. However, all of the above single-ended protections cannot distinguish the internal high-resistance fault from the external serious fault. Reference [12] proposed a protection scheme to identify the fault according to the ratio of the transient voltages, and overcomed the high-resistance problem by using the remote-end data. Reference [13] proposed the transient voltage-based dc protection for modular multilevel converter (MMC) based dc grid. The transient component of dc voltage is used to identify the internal and external faults. It only uses the local information, thus can operate extremely fast. In addition, it has a

4.1 The Development of the Single-Ended …

67

good capability against high transition resistance, due to the application of the highfrequency transient components. The application of the transient variables provides a good idea for the dc protection of improving the capability against transition resistance, so the detailed theoretical principle and implementation technique are worth more research.

4.1.3 The Direction Criterion for Excluding the Backward Fault In fact, the direction criterion is needed in most of the above single-ended protections to exclude the backward faults. At present, the direction criteria for dc system are mainly based on the dc current variation (i) or the dc current change rate (di/dt) [11, 14]. In theory, the value of i is larger than 0 when the fault is forward, while it is smaller than 0 after the backward fault. However, in order to avoid the mal-operation caused by the disturbances, such as the oscillations in the dc grid, a threshold value is needed in the i based direction criterion. In another word, the fault is identified as forward only when i is larger than a positive threshold value. Under high-resistance fault condition, the value of i will be very small, so the criterion cannot identify the fault as forward correctly. This means the i based direction criterion has weak capability against high transition resistance. Similarly, the di/dt based direction criterion identifies the fault as forward when the value of di/dt is larger than a positive threshold value. However, due to the charging and discharging process of the line distributed capacitors, the value of di/dt oscillates between the positive value and negative value both after the forward and backward faults. Therefore, the acting reliability cannot be guaranteed [14]. Therefore, the high-speed and high-reliability direction criterion also needs to be researched further. According to the above analysis, in this chapter, the working principle of the conventional traveling-wave-based protection is discussed in Sect. 4.2 firstly. Then the frequency-domain traveling-wave characteristics under different faults in the VSC-HVDC grid are analyzed, to explain why the conventional traveling-wavebased protections have weak capability against high transition resistance. And based on the theoretical analysis, the single-ended transient-voltage-based protection, which uses transient voltage energy to identify the internal fault and forward external fault, and uses transient voltage amplitudes ratio to judge the fault direction, is discussed in detail in Sect. 4.4. For application in the multi-terminal VSC-HVDC grid, the proposed novel protection has high acting speed and strong robustness against high transition resistance.

68

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

4.2 The Conventional Traveling-Wave-Based Protection in the LCC-HVDC System At present, the researches on the dc line protection for VSC-HVDC grid mainly learn from the protection in LCC-HVDC system. As introduced above, in the LCCHVDC system, the single-ended traveling-wave-based protections are used as the main protection for the dc line, thus being discussed in detail in this section.

4.2.1 The Traveling Wave Characteristic of the Transmission Line 4.2.1.1

The Traveling Wave on the Transmission Line

A transmission line can be divided to numerous segments with the length dx, in another word, the transmission line has the distributed parameter characteristic. It can be equivalent to Fig. 4.1, where L, r, C, and g respectively represent the seriesconnected inductance, series-connected resistance, parallel-connected capacitance and parallel-connected conductance of the unit-length line. The distributed parameter characteristic of the transmission line makes the system power and disturbance propagate on the line at a certain speed, thus being named as the traveling wave. According to Fig. 4.1, the response characteristic of the voltage u and current i on the line can be expressed as ⎧ 2 ∂ u ∂ 2u ⎪ ⎪ ⎨ 2 = LC 2 ∂x ∂t 2 ⎪ ∂ i ∂ 2i ⎪ ⎩ = LC ∂x2 ∂t 2

(4.1)

where x represents the position on the line. And the power loss on the line is neglected, namely, r = 0, g = 0.

i

Ldx

rdx

a gdx

u

… b

dx Fig. 4.1 The distributed parameter model of the transmission line

Cdx

…

4.2 The Conventional Traveling-Wave-Based Protection in the LCC-HVDC System

69

The Darumbell solution of (4.1) can be expressed as   ⎧ x x + ⎪ + u− t + ⎨ u(x, t) = u t − v v 1 − x x 1 + ⎪ ⎩ i(x, t) = u t − − u t+ Zc v Zc v

(4.2)

√ √ where Z c = L/C, is the wave impedance of the lossless line. v = 1/ LC, is the propagation speed of the traveling wave. According to (4.2), the voltage u consists of the forward traveling wave component u+ and the backward traveling wave component u− . Similarly, the current i consists of the forward traveling wave component u+ /Z c and the backward traveling wave component u− /Z c .

4.2.1.2

The Reflection and Refraction of the Traveling Wave

The traveling wave reflection and refraction will occur at the connection point of two lines with different wave impedances or at the connection point of the parameterdistributed line and the lumped component, as shown in Fig. 4.2. As shown in Fig. 4.2, at point A, the voltage and current satisfy 

u2+ = u1+ + u1− i2+ = i1− − i1+

(4.3)

⎧ + + ⎪ ⎨ u2 = i2 Z2 + u1 = i1+ Z1 ⎪ ⎩ − u1 = i1− Z1

(4.4)

and

At the connection point, the reflection coefficient is defined as the ratio of the reflection wave and the incident wave. At point A, the voltage wave (moving from Line1 to Line2 ) reflection coefficient k u can be calculated as ku = u1+ /u1− =

Z2 − Z1 Z2 + Z1

(4.5)

Similarly, the current wave reflection coefficient k i can be calculated as Fig. 4.2 The reflection and refraction of the traveling wave

+

Z1 Line1

u1- i1- A u2 i2+ u1+ i1+

Z2 Line2

70

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

Z2 − Z1 Z2 + Z1

ki = i1+ /i1− =

(4.6)

According to (4.5)–(4.6), the voltage wave reflection coefficient and current wave reflection coefficient are the same. The refraction coefficient is defined as the ratio of the refraction wave and the incident wave. At point A, the voltage wave (moving from Line1 to Line2 ) refraction coefficient ρ u can be calculated as ρu = u2+ /u1− =

2Z2 Z2 + Z1

(4.7)

And the current wave refraction coefficient ρ i can be calculated as ρi = i2+ /i1− = ρu ·

4.2.1.3

Z1 2Z1 = Z2 Z2 + Z1

(4.8)

The Analysis Method of the Traveling Wave Propagation Characteristic on the DC Transmission Line

The single-circuit dc line is symmetrical, as shown in Fig. 4.3. Therefore, the self impedance and self admittance of the positive pole and negative pole are the same. In addition, the mutual impedance and mutual admittance between the positive and negative poles should be introduced to reflect the coupling influence. For the single pole line, the voltage and current satisfy ⎧ ∂u ∂i ⎪ + L + ri = 0 ⎨ ∂x ∂t ⎪ ⎩ ∂i + C ∂u + gu = 0 ∂x ∂t

(4.9)

In frequency domain, it can be expressed as Fig. 4.3 The dc pole lines configuration diagram

lighting wire

positive pole

lighting wire

Negative pole

4.2 The Conventional Traveling-Wave-Based Protection in the LCC-HVDC System

⎧ dU ⎪ = −ZI ⎨ dx ⎪ ⎩ dI = −YU dx

71

(4.10)

where Z = sL + r is the series-connected impedance, and Y = sC + g is the parallelconnected admittance. For the dc line with two pole lines (4.10) should be expressed as 

IP d UP Zs Zm = − Zm Zs dx UN IN

 UP d IP Ys Ym − = Ym Ys dx IN UN

(4.11)

(4.12)

where Z s , Z m , Y s and Y m are the self impedance, mutual impedance, self admittance and mutual admittance respectively. U P and I P are the voltage and current of the positive pole, while U N and I N are the voltage and current of the negative pole. Based on (4.11) and (4.12), the second-order differential equation of the voltage and current can be obtained as 

UP d2 UP Zs Ys + Zm Ym Zs Ym + Zm Ys − 2 = (4.13) Zs Ym + Zm Ys Zs Ys + Zm Ym dx UN UN 

IP d2 IP Zs Ys + Zm Ym Zs Ym + Zm Ys − 2 = (4.14) Zs Ym + Zm Ys Zs Ys + Zm Ym dx IN IN Due to the coupling between the positive pole and negative pole, it is hard to obtain the solutions of (4.13) and (4.14) directly. The decoupling calculation method must be applied. Therefore, the eigenvector matrix Q and eigenvalue matrix  are introduced, where  1 1 1 Q= √ 2 1 −1

(4.15)

0 (Zs + Zm )(Ys + Ym ) . Λ= 0 (Zs − Zm )(Ys − Ym )

(4.16)



Then in (4.13) and (4.14), the parameter matrix consisting of Z s , Z m , Y s and Y m can be expressed as 

Zs Ys + Zm Ym Zs Ym + Zm Ys Zs Ym + Zm Ys Zs Ys + Zm Ym



= Q−1 ΛQ

(4.17)

72

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

In addition, the 0-mode components U 0 , I 0 , and the 1-mode components U 1 , I 1 should also be introduced, which satisfy



UP U0 =Q UN U1



IP I0 =Q IN I1

(4.18)

(4.19)

Therefore, (4.13) and (4.14) can be equivalent to 

U0 d2 U0 (Zs + Zm )(Ys + Ym ) − 2 = (Zs − Zm )(Ys − Ym ) U1 dx U1 

I0 d2 I0 (Zs + Zm )(Ys + Ym ) − 2 = (Zs − Zm )(Ys − Ym ) I1 dx I1

(4.20)

(4.21)

The general solutions of (4.20) and (4.21) can be calculated as ⎧ −γ x γ x ⎨ U0 (x) = F0 e 0 + B0 e 0 B F ⎩ I0 (x) = 0 e−γ0 x − 0 eγ0 x Z0 Z0 ⎧ −γ x γ x ⎨ U1 (x) = F1 e 1 + B1 e 1 B F ⎩ I1 (x) = 1 e−γ1 x − 1 eγ1 x Z1 Z1

(4.22)

(4.23)

where ⎧

⎪ Z0 = (Zs + Zm )/(Ys + Ym ) ⎪ ⎪ ⎪

⎪ ⎨ γ0 = (Zs + Zm )(Ys + Ym )

⎪ Z1 = (Zs − Zm )/(Ys − Ym ) ⎪ ⎪ ⎪

⎪ ⎩ γ1 = (Zs − Zm )(Ys − Ym ) Z 0 and γ 0 are the 0-mode impedance and propagation constant. Z 1 and γ 1 are the 1-mode impedance and propagation constant. F 0 and B0 represent the 0-mode forward voltage traveling wave amplitude and backward voltage traveling wave amplitude respectively. F 1 and B1 represent the 1-mode forward voltage traveling wave amplitude and backward voltage traveling wave amplitude respectively. For U 0 (x) in (4.22), F0 e−γ0 x is in frequency domain, which corresponds to f 0 (t-x/v) in time domain. It means F0 e−γ0 x represents the forward traveling wave component

4.2 The Conventional Traveling-Wave-Based Protection in the LCC-HVDC System

73

of the voltage. Similarly, B0 e−γ0 x represents the backward traveling wave component of the voltage. For I 0 (x), U 1 (x) and I 1 (x), the same conclusion can be obtained. According to (4.15), (4.18) and (4.19), the 0-mode components on the two pole lines have the same amplitude and the same polarity. Therefore, the 0-mode components flow between the pole line and the ground wire, thus also being named as the ground-mode component. Differently, the 1-mode components on the two pole lines have the same amplitude but different polarities. It means the 1-mode components flow between the positive pole and the negative pole, thus also being named as the line-mode component. The 0-mode component and 1-mode component are not coupled with each other, thus can be respectively calculated like the single pole line.

4.2.2 The Conventional Traveling-Wave-Based Protection in LCC-HVDC System 4.2.2.1

The Traveling-Wave-Based Protection of ABB

(1) The pole-mode wave and ground-mode wave In the traveling-wave-based protection of ABB, the pole-mode wave and groundmode wave are defined as P = Id1 · Zc1 − Ud1

(4.24)

G = Id0 · Zc0 − Ud0

(4.25)

where I d1 , U d1 and Z c1 represent the line-mode current, line-mode voltage and linemode impedance respectively. I d0 , U d0 and Z c0 represent the ground-mode current, ground-mode voltage and ground-mode impedance respectively. According to (4.22) and (4.23), P = −2β1 eγ1 x , and G = −2β0 eγ0 x . It means that the pole-mode wave and ground-mode wave represent the backward traveling wave in line mode and ground mode respectively. (2) The protection criterion The detailed traveling-wave-based protection criterion proposed by ABB is ⎧ dP/dt > 1 ⎪ ⎪ ⎪ ⎨ P > 2 ⎪ dG/dt > 3 ⎪ ⎪ ⎩ G > 4

(4.26)

74

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

where 1 –4 are the threshold values, which are generally determined according to the simulation results [15]. During normal operation, the change value and change rate of the pole-mode wave are both very small. While after the fault, the above variables will increase quickly. This is the fundamental basis for the traveling-wave-based protection in HVDC system. Considering that there are boundary components such as the filters at the dc line terminals, the above variables after external faults will be much smaller than those after the internal faults. So the internal fault and external fault can be identified by appropriate threshold values. In addition, the ground-mode wave can be used to select the fault pole. If the fault is a positive-pole fault, the ground-mode wave G will be larger than a positive threshold value. If the fault is a positive-pole fault, the ground-mode wave G will be smaller than a negative threshold value. And if the fault is a pole-to-pole fault, the absolute value of the ground-mode wave G will be very small.

4.2.2.2

The Traveling-Wave-Based Protection of Siemens

The working principle of the traveling-wave-based protection proposed by Siemens can be described as: After the fault, the fault traveling wave propagates to the protection position. The dc voltage observed by the protection fast decreases. At the rectifier side, the dc current increases quickly, and at the inverter side, the dc current decreases quickly. Therefore, the dc fault can be detected according to the rate of change of the voltage (ROCOV, namely, du/dt) and the traveling wave b(t) [b(t) = I d · Z c − U d ] [15]. The detailed criterion of the protection is: After du/dt < −δ (δ is a threshold value), calculate the integral value of b(i) = b(i) − b(m) for 10 ms, where b(m) is the latest sampling value before the fault, and b(i) is the sampling value at the point i after fault. If the integral value is larger than a positive threshold value, the fault is identified as positive-pole fault. And if the integral value is smaller than a negative threshold value, the fault is identified as negative-pole fault. In addition, in some practical projects, such as the Tianshengqiao-Guangzhou HVDC Project in China, the traveling-wave-based protection is designed based on du/dt, u, and i directly, namely, ⎧ du/dt > 1 ⎪ ⎪ ⎪ ⎨ u >  2 ⎪ i >  3 (rectifier side) ⎪ ⎪ ⎩ i < 4 (inverter side)

(4.27)

where du/dt is used to start the protection after faults, u and i are used to identify the fault line [15]. In fact, the change of the dc voltage after faults is also caused by the fault traveling wave generated by the fault source. Therefore, essentially, the ROCOV based protection also belongs to the traveling-wave-based protection.

4.3 Analysis of the Frequency-Domain Traveling-Wave …

75

4.3 Analysis of the Frequency-Domain Traveling-Wave Boundary Characteristics After Different Fault Conditions In this section, the frequency-domain traveling-wave boundary characteristics after different fault conditions are analyzed, to discuss the applicability of the conventional traveling-wave-based protection in VSC-HVDC grid and provide theoretical basis for the novel protection principle.

4.3.1 The Boundary Element in the VSC-HVDC Grid As we know, the dc fault in the VSC-HVDC grid propagates extremely fast. Obviously, the fast rising dc fault current will seriously damage the equipments in the dc grid, such as the converter, the dc line and so on. Therefore, in the practical engineering, the dc reactors will be installed to limit the dc fault current, and thus lowering the requirement on the acting speed of dc protection and DCCBs [9, 10]. Moreover, in the multi-terminal dc grid, the dc reactor will be installed at both ends of each dc line, as the four-terminal dc grid shown in Fig. 4.4. For example, the Zhangbei DC Grid Project in China plans to install 100–200 mH dc reactor at each dc line end, for the purpose of dc fault current limitation and healthy network ride-through. The dc reactors installed at the dc line ends provide natural boundary for dc protection to identify the internal and external faults. At present, most of the singleended dc protection strategies are designed depending on the existence of the dc reactors [9–12]. And in this chapter, the proposed novel protection strategy is also based on the boundary effect of the dc reactors.

f2

M

MMC1

idcM

uM_bus uM_line

f1

f7

f3

N

f4 MMC2

Line1

f8

f9

P

f6

f5 Line4

Line2

Q MMC4

MMC3 Line3

Fig. 4.4 The four-terminal meshed VSC-HVDC grid

76

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

4.3.2 Transient Voltage Characteristic of the Internal and Forward External DC Faults When a dc fault occurs, the voltage of the fault point will drop to zero instantaneously. And the voltage of the fault point can be equivalent to the sum of the normal operation voltage U dc and the fault additional voltage U f , where U dc + U f = 0, namely, U f = −U dc . Therefore, according to the superposition theory, the frequency-domain fault superposition circuits of the internal and (forward) external faults in multi-terminal dc grid can be equivalent to Fig. 4.5a and b respectively (taking the protection M of Line1 as shown in Fig. 4.4 for instance). It should be noted that the line-mode parameters are used in the equivalent circuit, where the earth-mode parameters are applicative as well. Figure 4.5a is the frequency-domain fault superposition circuit of the internal line-end high-resistance fault. As shown in Fig. 4.5a, when a transition resistor is  introduced, the line voltage U f (ω) at the fault position should be expressed as |Uf (ω)|

    Z //jωL + Z //jωL + Z   1 CN1   1    = U (ω)  f   Rg + Z1 // jωL + ZCN1 // jωL + Z1

(4.28)

where U f (ω) denotes the additional fault voltage component of the fault point under the angular frequency ω. Z 1 and Z 1  are the line-mode wave impedances of Line1 and Line2 respectively, which can be calculated as described in Sect. 4.2.1.3. Rg represents M jωL IdcM

ZCM1 jωL'

jωL N

Z1

Rg

Uf'

UM_line

+

Uf

Z1

ZCN1 jωL' Z1'

-

ZCN2

ZCM2

(a)

jωL'

jωL N U f'

UM_line

Z1

ZCN1 jωL' Z1'

Uf

-

ZCM1

Z1

+

M jωL IdcM

ZCN2

ZCM2

(b) Fig. 4.5 The frequency-domain fault superposition circuits of the internal and external faults in the multi-terminal dc grid: a internal line-end fault with transition resistance, b external nearby metallic fault

4.3 Analysis of the Frequency-Domain Traveling-Wave …

77

the fault transition resistance, and L  denotes the dc reactor on the adjacent line. Z CN1 represents the equivalent impedance of the MMC [16] which can be calculated by ZCN1 = j(2ωLr /3 − N /3ωC)

(4.29)

where C is the value of the MMC sub-module capacitors, L r is the value of the arm reactor, and N is the number of the sub-modules in each arm. Obviously, the fault additional voltage source U f generates a forward traveling wave at the fault moment. This means the backward traveling wave component in (4.22), (4.23) can be neglected when analyzing the voltage distribution characteristic along the line during initial stage of the fault. Therefore, for the protection M, the line-mode transient voltage U M_line (ω), at the line side of the dc reactor, can be expressed as         |UM_ line (ω)| = Uf (ω)e−γ1 l +Kf Uf (ω)e−γ1 l     =Kg Uf (ω)e−γ1 l +Kf Kg Uf (ω)e−γ1 l

(4.30)

where K f is the reflection coefficient at the dc bus, l denotes the distance from the fault point to the protection M, and K g is defined as    Z //jωL + Z //jωL + Z    1 CN 1   1     Kg =   Rg + Z1 // jωL + ZCN 1 // jωL + Z1 

(4.31)

Similarly, as shown in Fig. 4.5b, U M_line (ω) after the forward external nearby metallic fault can be calculated as         |UM_ line (ω)| = Uf (ω)e−γ1 l +Kf Uf (ω)e−γ1 l     = KL Uf (ω)e−γ1 l +Kf KL Uf (ω)e−γ1 l (4.32) where K L = |Z1 /(jωL + Z1 )|. According to (4.30) and (4.32), the ratio of U M_line (ω) after the internal line-end high-resistance fault to U M_line (ω) after the external nearby metallic fault is K g /K L . Therefore, the voltage characteristic difference between the internal line-end highresistance fault and external nearby metallic fault mainly depends on the values of K g and K L . In order to ensure the reliability of the protection criterion which is based on the difference of the transient voltage, K g > K L must be guaranteed. Obviously, the values of K g and K L will change with different frequencies, because the values of Z 1 , Z 1  , Z CN1 and ωL are all dependent on the frequency. Taking the overhead line Line1 shown in Table 4.1 for instance, its frequency-dependent wave impedances (line-mode and earth-mode) can be obtained by the rational fitting method [17] as shown in Fig. 4.6a, b (wave impedances of Line3 and Line4 are the same because of the same line parameters). Similarly, the wave impedances of Line2 can be calculated. Then the values of K g and K L under different frequencies and

78

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

Table 4.1 Overhead line parameters Conductor

Ground wire

Parameter

Line1,3,4

Line2

Hight (m)

30

58

DC resistance (/km)

0.03206

0.02291

Horizontal spacing (m)

10

20

Outer radius (mm)

20.36

47.35

Sag (m)

10

18

Hight (m)

40

64

DC resistance (/km)

2.8645

0.5807

Horizontal spacing (m)

10

22

Outer radius (mm)

5.5245

15.75

Sag (m)

10

13

different dc reactor values can be calculated as shown in Fig. 4.6c, where the value of Rg is set as 300 , the value of the dc reactor on the adjacent line L  is set as 100 mH, the value of the MMC sub-module capacitors is 15,000 μF, and the number of the sub-modules in each arm is 220. As shown in Fig. 4.6c, for each L, there is a critical frequency which makes K g > K L . For example, when L = 50 mH, K g > K L is satisfied when the frequency is larger than 1840 Hz. This means U M_line (ω) of the internal line-end fault with a 300  resistor is smaller than that of the external nearby metallic fault when f < 1840 Hz. Therefore, the transient voltage components under 1840 Hz cannot be used to identify the internal fault and external fault. This is the essential reason why the conventional traveling-wave-based protections, such as the pole-mode wave based protection and the ROCOV based protection, which use the full-band voltage, cannot extinguish the internal high-resistance fault from the external serious fault. In addition, K L and K g will change faster as the value of the dc reactor L increases. And thus, the critical frequency which makes K g > K L will be smaller correspondingly. As shown in Fig. 4.6c, taking Rg = 300  for instance, the critical frequencies are 1840 Hz, 932 Hz and 190 Hz respectively when L is 50 mH, 100 mH and 500 mH. Therefore, it indicates that the larger the dc reactor and the higher the frequency are, the more obvious the difference between K g and K L will be. According to the analysis above, this chapter proposed a novel single-ended transient-voltage-based protection which extracts the high-frequency voltage component for fault identification, to improve the acting reliability and sensitivity, especially under the high transition resistance condition.

4.3 Analysis of the Frequency-Domain Traveling-Wave …

magnitude/Ω

1300

0

angle/rad

-0.1

1100

angle(Z0)

-0.2

900

-0.3

abs(Z0)

-0.4

700 500 300

79

angle(Z1)

-0.5

abs(Z1)

-0.6

10-0 101 102 103 104 105 106

-0.7

10-0 101 102 103 104 105 106

f/Hz

f/Hz

(a)

(b) KL(L=50mH) KL(L=100mH) KL(L=500mH)

1.2 1

Kg(L=50mH) Kg(L=100mH) Kg(L=500mH)

0.8 f=932Hz 0.6

f=190Hz

0.4 f=1840Hz

0.2 0

10-0

101

102

103

104

105

f/Hz

(c) Fig. 4.6 The voltage characteristic difference between the internal and external fault: a the amplitude of the wave impedances with different frequencies, b the phase angle of the wave impedances with different frequencies, c the values of K g and K L with different frequencies and different dc reactor values L

4.3.3 Transient Voltage Characteristic of the Forward and Backward Faults Generally, as the main criterion of the single-ended protection (for identifying the internal fault and the forward external fault) itself does not have the fault direction identification capability, the fault direction criterion is needed to exclude the backward fault. For example, the ROCOV based protection always uses the di/dt criterion to identify the fault direction.

80

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

Similarly, the criterion based on the transient voltage amplitude (energy) only functions to identify the internal fault and forward external fault, without distinguishing the forward and backward faults. For example, after the backward metallic fault, the attenuation of the traveling wave voltage from the fault point to the protection M is only caused by the dc reactor. But after the forward internal line-end high-resistance fault, the attenuation is caused by the transition resistor and the dc line. The attenuation of the transition resistor and the dc line may be stronger than that of the dc reactor. In other words, the direction criterion is also needed for the transient-voltage-based protection to exclude the backward fault. However, the conventional dc fault direction criterion, such as the di/dt based criterion, has obvious drawbacks for using in the VSC-HVDC grid. This section analyzes the transient voltage characteristics of the forward and backward faults, providing theoretical basis for the novel dc fault direction criterion. For the protection M, the frequency-domain fault superposition circuit after the backward and forward faults can be equivalent to Fig. 4.7a and b respectively. As shown in Fig. 4.7a, ignoring the backward traveling wave, the transient voltages on the two sides of the dc reactor during the initial stage of the backward fault have the relationship shown as UM_ line (ω) = UM_ bus (ω) − jωLIdcM (ω)=UM_ bus (ω) − jωLUM_ line (ω)/Z1 (4.33) where U M_line (ω), U M_bus (ω) represent the transient voltages on the line side and bus side of the dc reactor respectively under the angular frequency ω. M jωL IdcM

ZCM1

+

Uf

-

jωL'

jωL N

Z1

UM_bus UM_line

UN_line UN_bus

Z1

ZCN1 jωL' Z1' ZCN2

ZCM2

(a) M jωL IdcM

ZCM1 jωL'

Z1

Z1

+

UM_bus UM_line Uf

jωL N

UN_line UN_bus

-

ZCN1 jωL' Z1'

Z1

ZCN2

ZCM2

(b) Fig. 4.7 The frequency-domain fault superposition circuits of the forward and backward faults in the multi-terminal dc grid: a the backward fault of the protection M, b the forward fault of the protection M

4.3 Analysis of the Frequency-Domain Traveling-Wave …

81

Therefore, the amplitude ratio of U M_line (ω) to U M_bus (ω), namely |U M_line |/|U M_bus |, can be calculated as Ku = |Z1 /(Z1 + jωL)|

(4.34)

Similarly, the transient voltages on the two sides of the dc reactor during the initial stage of the forward fault satisfy UM_line (ω) = UM_ bus (ω) − jωLIdcM (ω)   UM_bus (ω) UM_bus (ω) = UM_bus (ω) + jωL + ZCM1 jωL + Z1

(4.35)

where L  denotes the dc reactor on the adjacent line; Z CM1 represents the equivalent impedance of the MMC [16] which can similarly be calculated by (4.29). According to the transmission characteristic of the traveling wave, Eq. (4.35) is correct before the initial fault reflected traveling wave on the adjacent line arrives at the protection M. Hence, the amplitude ratio of the line-side transient voltage to the bus-side transient voltage can be calculated by       Ku = 1 + jωL/ZCM 1 + jωL/ jωL + Z1 

(4.36)

According to (4.34) and (4.36), the value of K u will change with different wave impedances Z 1 , dc reactor values and converter impedances, which are all affected by the frequency significantly. Therefore, the frequency-dependent characteristic curves of K u are displayed in Fig. 4.8, where the value of the dc reactor on adjacent line is set as 100 mH, the value of the MMC sub-module capacitors 15,000 μF, and the number of the sub-modules in each arm is 220. | U M_line | / | U M_bus |

1.2

| U M_line | / | U M_bus | 6

1.02

1.01

1 1

0.8

L=500mH

5 1

L=500mH

4 0.98

0.6

0 21.4 49.2 72.1 100

3

0.99

10

18.5

28.5 31.2

101

102

L=100mH

0.4

L=100mH

L=50mH

2

0.2 0

40

1

L=50mH

10-0

101

102

103

(a)

104

105

106 f/Hz

0

10-0

103

(b)

104

105

106 f/Hz

Fig. 4.8 The frequency-dependent characteristic curve of Ku after the backward and forward faults: a the backward fault, b the forward fault

82

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

As shown in Fig. 4.8a, for the backward fault, there is a critical frequency which makes K u = 1. When the frequency is larger than this critical frequency, K u always keeps below 1. And the larger the frequency is, the smaller K u will be. For example, when L = 50 mH, the critical frequency is 72.1 Hz. And K u < 1 is always satisfied when f > 72.1 Hz. Differently, for the forward fault, K u always keeps above 1 when the frequency is larger than the critical frequency. As shown in Fig. 4.8b, K u > 1 is always satisfied when f > 31.2 Hz (L = 50 mH for instance as well). In addition, also shown in Fig. 4.8, the larger the dc reactor is, the smaller the critical frequency will be. According to the analysis above, when the frequency is larger than the critical frequency, the value of K u has the characteristic shown as 

forward fault: Ku >1 backward fault: Ku K L , which means the frequency range should keep above the critical frequency. And since the larger the frequency is, the more obvious the difference between K g and K L will be, the level j is generally selected as 1. As analyzed in Sect. 4.3, the high-frequency transient voltage after the internal faults is larger than that of the external faults. Therefore, finally, the internal fault or external fault can be identified by 

internal fault: Ej > Eset external fault: Ej ≤ Eset

(4.41)

where E set is the threshold value of the proposed transient-voltage-energy-based criterion. Similar to the traveling wave protection and the ROCOV based protection, the threshold value is generally determined by the simulation result, where the core principle is to exclude the most serious external fault (forward external nearby metallic fault), and to guarantee the reliable action of the weakest internal fault (internal remote fault with a high transition resistor). (2) Direction criterion As mentioned above, the direction criterion is needed for the single-ended protection to exclude the backward fault, because the transient-voltage energy after the backward nearby metallic fault may be close to or larger than that of the internal weak fault, such as the remote fault with a high transition resistor. Therefore, a novel fast direction criterion is proposed for the dc grid, which is based on the highfrequency transient component amplitudes ratio of the voltages on the two sides of the dc reactor. The proposed direction criterion also uses wavelet transform to extract the detail coefficients of the reactor-line-side voltage U line and the reactor-bus-side

4.4 Novel Fast Single-Ended Protection Based on the Transient Voltages

85

voltage U bus . According to the analysis in Sect. 5.2, the high frequency component of U line is larger than that of U bus after the forward fault, and vice versa. Hence, the fault direction can be determined by 

forward fault: max|dj_ line (k)|/max|dj_ bus (k)| > kset backward fault: max|dj_ line (k)|/max|dj_ bus (k)| ≤ kset

(4.42)

where d j_line (k) and d j_bus (k) are the detail coefficients of U line and U bus at level j respectively. And generally, j is selected as 1. In addition, k set in (4.42) is the reliability coefficient, which is a little larger than 1.

4.4.3 Protection Algorithm (1) The improved algorithm of wavelet transform In practical engineering, due to the limitation of data storage capability and the requirement on protection acting speed, only the data in a subset short data window will be intercepted for one wavelet transform. When the filter array is moved to the boundary of the data window, the false data must be introduced to calculate the corresponding approximation coefficient and detail coefficient. Therefore, this part of the approximation coefficients and detail coefficients are not true, and they cannot be used for the proposed criteria. This phenomenon is named as the boundary effect. In order to eliminate the boundary effect of the wavelet algorithm, this section proposes the principle to select the data window, as shown in Fig. 4.10. In Fig. 4.10, the protection starting moment(t 4 ) is set as the reference, and then the sampling data from the time t 4 − t 1 to t 4 + t 2 will be intercepted, namely from t 1 to t 7 . Next, the data in the period from t 1 to t 7 will be processed by the wavelet transform, but the obtained detail coefficients corresponding to the period t 1 ~ t 1 + t (named as t 2 ) and t 7 ~ t 7 − t (named as t 6 ) are not used to eliminate the boundary effect. In another word, only the detail coefficients corresponding to the period t 2 –t 6 are used

t1

t2

fault time t3

protection starting time t4 Δt2 Δt1

block time t5 t6 t7

To eliminate the boundary effect of the wavelet algorithm

Δt

To eliminate the effect of the converter blocking

Δt

Fig. 4.10 The detail coefficient window selection principle for the proposed novel protection

86

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

for (4.40)–(4.42). In addition, if the converter blocked time t 5 is before t 6 , the useful detail coefficients window for fault identification criterion and direction criterion should be shorted to t 2 −t 5 . In addition, according to the working principle of the Mallat algorithm, the binary sampling will be applied after filtering. In fact, the detail coefficients represent the high-frequency components of the pre-level approximation coefficients, and the binary sampling may lead to the loss of the high-frequency information, and then cause the maloperation of the proposed protection method. Therefore, in order to eliminate the negative influence of the binary sampling, two adjacent data windows (moving one data point to get the next data window) are processed by the wavelet transform method described above. And then the detail coefficients from these two adjacent data windows are combined in (4.40)–(4.42). By this method, the information loss problem caused by the binary sampling of the Mallat algorithm can be avoided effectively. (2) Flowchart of the novel single-ended dc protection strategy The flowchart of the proposed single-ended protection is shown in Fig. 4.11. After faults, the protection will be started quickly by the starting criteria (du/dt and di/dt in this strategy). It should be noted that here the du/dt and di/dt based criteria are only Fig. 4.11 Flowchart of the proposed single-ended dc protection strategy for the multi-terminal VSC-HVDC grid

Obtain the voltage and current data du/dtˈdi/dt N Protection start˛ Y Select first data window and obtain max|dj_line1|ǃmax|dj_bus1|ǃEj1 Get the adjacent data window and obtain max|dj_line2|ǃmax|dj_bus2|ǃEj2 max|dj_line|=max[max|dj_line1|,max|dj_line2|] max|dj_bus|=max[max|dj_bus1|,max|dj_bus2|] Ej=max[Ej1,Ej2]

max|d j_line | max|d j_bus |

> kset ˛

N

Backward fault

Y

E j > Eset˛ Y Internal fault End

N

External fault

4.4 Novel Fast Single-Ended Protection Based on the Transient Voltages

87

used to start the protection after fault, with no need for the selectivity requirement, so the corresponding threshold value can be very small (only need to be larger than the value that would occur during normal operation). Then the needed data are sampled and processed by the method described above. If the fault is a backward one, it will be determined as the external fault by the direction criterion (4.42). If the fault is a forward one, the internal fault or external fault will be identified by the transient-voltage energy based criterion (4.41). In conclusion, the novel protection strategy can identify the backward fault, forward internal fault and forward external fault effectively. Moreover, compared with the typical dc singleended protection (generally the traveling wave protections, such as the pole-mode wave based protection and the dc voltage change-rate based protection), the proposed dc protection strategy has higher ability against high transition resistance.

4.5 Case Study The four-terminal VSC-HVDC grid shown in Fig. 4.4 is built on the PSCAD/EMTDC platform. The corresponding simulation parameters are listed in Table 4.2, and the parameters of the frequency-dependent dc overhead lines are given in Table 4.2. In the case studies, the protection M on Line1 is observed to verify the acting property and advantages of the proposed novel protection. And the measurement locations are marked in the system topology as shown in Fig. 4.4. In addition, the sampling frequency of the protection is set as 10 kHz. Table 4.2 Parameters of the four-terminal VSC-HVDC grid

Parameter

Value

Rated dc voltage/kV

±500

Rated ac voltage/kV

200

The arm reactor/mH (S1 –S4 )

80, 80, 80, 80

The sub-module capacitor/μF (S1 –S4 )

15,000, 15,000, 15,000, 15,000

Length of the dc line/km

400, 300, 400, 300

Sub-module number in each arm

220

DC reactor/mH

100

Rated power/MVA (S1 –S4 )

1500, 1500, 1500, 1500

88

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

4.5.1 Comparison and Discussion Between the Novel Fault Identification Criterion and the Existing Methods In this case, the dc fault (pole-to-ground fault for instance) at the line end (f 3 ) with 300  transition resistor and the external nearby metallic fault (f 4 ) are set to happen at t = 3 s respectively. The ROCOV based criterion, the pole-mode wave based criterion, as well as the proposed criterion are respectively used to identify the faults. The corresponding simulation results are shown in Fig. 4.12. 600

(a)

500 400

fault time

300

f3 ( 300 Ω) f4 ( metallic fault)

200 100

x 10 6

2

(b)

1.6 1.2 0.8 0.4

(c)

0 1500 1000 500 0 2.5

x 10 6

(d)

2 1.5 1 0.5 0

(e)

6000 4000 2000 0 2.998

3

3.002

3.004

3.006

3.008

time (s)

Fig. 4.12 Acting property of different fault identification criteria after the internal (f 3 ) and external (f 4 ) faults: a the dc voltage uM_line (kV), b |du/dt| of uM_line (kV/s), c the amplitude of the pole-mode wave P at the dc reactor line side (kV), d |dP/dt| (kV/s), e the transient energy of uM_line (kV2 )

4.5 Case Study

89

The ROCOV based criterion identifies the fault as the internal fault once the absolute value of the ROCOV, namely |du/dt|, is larger than the pre-set threshold value. In order to ensure the selectivity of the protection, the pre-set threshold value should be larger than |du/dt| after the external fault and smaller than that after the internal fault. However, as shown in Fig. 4.12b, the maximum value of |du/dt| after the internal line-end fault f 3 with 300  transition resistor is 1.37 * 106 kV/s, which is smaller than the maximum value 1.66 * 106 kV/s after the external nearby metallic fault f 4 . That is to say, the ROCOV based protection cannot identify the internal high-resistance fault and external metallic fault. In other words, it cannot guarantee the selectivity and reliability under the high-resistance fault condition. Similarly, the criteria based on the absolute value of pole-mode wave (|P|) or its derivative (|dP/dt|) can identify the fault as internal when they are larger than the corresponding pre-set threshold values. And the setting principle of the pre-set threshold value is the same as the ROCOV-based one. However, the value of |P| after f 3 with 300  transition resistor is smaller than that after metallic fault f 4 , as shown in Fig. 4.12c. Similarly, the maximum value of |dP/dt| after f 3 with 300  transition resistor is 1.9 * 106 kV/s, which is smaller than that after metallic fault f 4 (2.23 * 106 kV/s), as shown in Fig. 4.12d. It verifies that the pole-mode wave based criteria are also lack of high-resistance endurance capability. Differently, as shown in Fig. 4.12e, after f 3 with 300  transition resistor, the transient voltage energy peak value is 5368 (j of the wavelet transform is 1), which is much larger than that of the metallic fault f 4 (2820). It verifies that the transientvoltage-energy based fault identification criterion can identify the internal weak fault (high-resistance) and external serious fault with high sensitivity.

4.5.2 Comparison and Discussion Between the Novel Direction Criterion and the Existing Methods Generally, the single-ended protections need the direction criterion to exclude the backward fault, because the fault identification criteria themselves do not have the direction identifying capability. For example, as shown in Fig. 4.13a, the maximum value of |du/dt| after the internal fault f 3 (300 ) is 1.37 * 106 kV/s, which is smaller than that under the backward fault f 2 (metallic) (2.3 * 106 kV/s). As shown in Fig. 4.13b, the proposed transient-voltage-energy based criterion itself also cannot distinguish the backward fault from the internal fault. Similarly, as shown in Fig. 4.13c, the integral of the transient energy after the internal fault f 3 (300 ) is also smaller than that after the backward fault f 2 (metallic). The above simulation results indicate that it is difficult to distinguish the backward fault from the internal fault if only based on the transient voltage. Hence, the reliable fault direction criterion is necessary. In the conventional dc single-ended protection, such as the ROCOV based protection, the dc current change value (i) or its change rate (di/dt) based criteria will

90

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid 2.5

x 10 6 f3 ( 300 Ω)

(b)

(a)

2

f2 ( metallic fault)

1.5 fault time

1 0.5 0 7000 6000 5000 4000 3000 2000 1000 0 8000

(c)

6000 4000 2000 0 2.999 1

2.9995

3

3.0005 3.001

3.0015

3.002 3.0025 3.003

(d)

0 -1 fault time

-2 -3 2000

(e)

0 -2000 -4000 -6000

2.999

3

3.001

3.002

3.003

3.004

3.005

3.006

80

(f)

60 fault time

40

transient amplitude of uM_bus

transient amplitude of uM_line

20 0 250

(g)

200

transient amplitude of uM_bus

150 100

transient amplitude of uM_line

50 0

2.999 2.9995

3

3.0005

3.001

3.0015 3.002 3.0025

3.003

time (s)

Fig. 4.13 The necessity of the fault direction criterion and the acting property of different fault identification criteria after forward (f 3 ) and backward (f 2 ) faults: a |du/dt| of uM_line (kV/s), b the transient energy of uM_line (kV2 ), c the integral of the transient energy of uM_line (kV2 ), d i of idcM (kA), e di/dt of idcM (kA/s), f the transient amplitude of uM_line and uM_bus after f 3 (kV), g the transient amplitudes of uM_line and uM_bus after f 2 (kV)

4.5 Case Study

91

be introduced to identify the fault direction [11]. But as shown in Fig. 4.13d, the dc current change value is not very large after remote high resistor fault, which may even be close to zero. This means the current-change-value based direction criterion cannot endure the high transition resistance. In addition, as shown in Fig. 4.13e, the current change rate value di/dt has an oscillation around zero, thus also being not suitable for fault direction judgement. Figure 4.13f, g are the transient voltage amplitudes ratio after the internal fault f 3 with 300  transition resistor and backward metallic fault f 2 respectively. After fault f 3 , the reactor-line-side transient voltage amplitude is much larger than that of the reactor bus side. And after metallic fault f 2 , the reactor-line-side transient voltage amplitude is much smaller than that of the reactor bus side. In other words, the proposed direction criterion has high reliability and sensitivity for fault direction determination.

4.5.3 The Improved Protection Algorithm As discussed in Sect. 5.3, different starting points of the data window will lead to different calculating results by the Mallat algorithm, thus leading to different acting results of the protection. Figure 4.14a shows the Mallat algorithm calculating results of f 3 with 300  resistor and metallic f 4 , for two adjacent sampling data windows (suppose the start point for the two adjacent sampling data windows are k and k + 1 respectively.). As the simulation results show, for the data window starting from point k, the transient voltage energy of f 3 is larger than that of f 4 which can be obtained by the solid line in Fig. 4.14a. But for the data window starting from point k + 1, the result is opposite as the dotted lines in Fig. 4.14a. For the integral of the transient voltage as shown in Fig. 4.14b, the same conclusion can be obtained. Obviously, in practical engineering, the extracted data window starting point is random after different faults, because the starting moment is dependent on the start criterion. It means the criterion using the detail coefficient of wavelet transform directly may mal-operate. In fact, this problem is caused by the binary sampling step (all of the wavelet transforms have this step in engineering application) as analyzed in Sect. 5.3.3. Therefore, the calculated detail coefficients of two adjacent data windows are combined for the protection. As shown in Fig. 4.14c, when the calculated results of the two adjacent data windows are combined, the correct acting result of the protection can be guaranteed.

4.5.4 The Operation Performance of the Novel Protection Under Different Conditions Table 4.3 shows the acting results of the proposed protection for overhead lines, including the fault identification criterion and direction criterion, for different kinds

92

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

(a)

6000 4000

f3 ( 300 Ω) f4 ( metallic fault)

fault time

2000 0 8000

(b)

6000 4000 2000 0 6000

(c)

4000 2000 0 2.998

3

3.002

3.004

3.006

3.008

time (s) Fig. 4.14 The influence of the data window starting point on the protection: a the transient energy of uM_line in two adjacent data windows after the internal (f 3 ) and external (f 4 ) faults (kV2 ), b the integral of the transient energy of uM_line in two adjacent data windows after f 3 and f 4 (kV2 ), c the combination of transient energy of uM_line in two adjacent data windows after f 3 and f 4 (kV2 )

of faults. Here, E set of the dc pole-to-ground fault is set as 3384, while E set of the dc pole-to-pole fault is set as 6103. In addition, k set of both the dc pole-to-ground fault and the dc pole-to-pole fault is set as 1.1, and the data window length is 2 ms. As the simulation results showing, for all the internal faults, even the remote high transition resistance fault, the proposed protection strategy can identify the faults as the internal ones reliably and sensitively. And for all the external faults, the proposed protection strategy can identify them as the external ones. It verifies that the proposed protection has high reliability, high sensitivity and high acting speed.

Ac fault

Dc pole-to-pole fault

f1

Dc pole-to-ground fault

0

f2

0

0

f4

f9

0

f3

0

0

f7

f8

0

f1

0

f2

73.27

300

8.18

12.32

66.63

71.32

184.83

296.3

237.12

78

53.11

96.42

150

0

139.57

107.01

300

0

149.53

150

127.24

300 248.06

166.02

150

0

237.07

|d j_Line |

0

Fault resistance ()

f4

f3

f7

Fault location

Fault type

2.13

36.92

237.06

19.09

50.31

79.22

65.76

237.05

13.92

19.71

25.9

37.38

28.49

39.82

66.07

36.09

46.97

66.78

|d j_Bus |

3.84

0.33

0.28

3.74

3.67

3.74

3.61

0.33

3.81

3.72

3.72

3.73

3.76

3.76

3.75

3.53

3.53

3.55

max|dj_ line (k)| max|dj_ con (k)|

Table 4.3 Performances of the novel protection under different fault conditions

Forward

Backward

Backward

Forward

Forward

Forward

Forward

Backward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Direction

67

151.8

4439

5086

34,163

87,796

56,227

6085

2820

5368

9298

19,481

11,451

22,359

61,533

16,189

27,562

56,202

Ej

External

External

External

External

Internal

Internal

Internal

External

External

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Fault identification

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

Correct operation?

4.5 Case Study 93

94

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

4.5.5 Other Discussions (1) The Influence of the Breaker Opening on Other Breakers of the Non-faulted Line When the internal fault occurs, the corresponding DCCBs at the two terminals of the fault line should be tripped to isolate the fault quickly. The opening of the breakers will lead to severe interference, so its influence on the other breakers should be considered. As we know, all the breakers will be tripped only when the corresponding protection identifies the fault as an internal one. While for the proposed protection strategy, it will not be affected by the interference caused by the opening of breakers, which means the opening of the fault-line DCCBs will not lead to the mal-operation of the breakers on the other lines (namely the non-fault lines). To illustrate this problem, the corresponding simulation case study is carried out, taking the metallic pole-to-ground fault f 7 happening at t = 3 s on Line1 for instance. After the fault f 7 , the protection M and N will identify the fault as an internal fault quickly, and then trip the breakers at M and N quickly. Figure 4.15a shows the dc current of the fault line, which means the fault line is cut off by the corresponding DCCBs quickly after the fault. In order to analyze the influence of the opening of breakers on the protection and breaker of other lines, the protections P and Q at 4

(a)

3

fault time

2

(c)

(b)

1 0 120 100 80 60 40 20 0 3000

transient amplitude of uP_bus transient amplitude of uP_line

f7 ( metallic fault) f4 ( metallic fault)

2000 1000 0 2.998 3

3.004

3.008

3.012

3.016

3.02

time (s) Fig. 4.15 The influence of the breaker opening on the other lines: a dc current of the fault line (kA), b the transient voltage amplitudes of uP_line and uP_bus after metallic fault f 7 (kV), c the transient energy of uQ_line (kV2 )

4.5 Case Study

95

Line2 in Fig. 4.4 are observed and the measurement locations of the dc current and dc voltage are similar to the protection M in Fig. 4.4. For the protection P, the fault f 7 is a backward fault. As shown in Fig. 4.15b, after the fault f 7 , the maximum value of the bus-side transient voltage is larger than that of the line-side [the first peak in Fig. 4.15b], so the fault is identified as backward. After the breakers on the fault line are tripped (about 3 ms after the fault), although the opening of the breakers will lead to severe interference, this interference is also backward for the protection P. So as the simulation result showing, the maximum value of the bus-side transient voltage is still larger than that of the line-side. It means P still identifies the fault as backward, and will not act mistakenly to trip the corresponding DCCB. For the protection Q, the fault f 7 is a forward external fault. According to the setting principle of the threshold value proposed in Sect. 5.3.2, E set of protection Q should be larger than the maximum transient voltage energy of the metallic fault f 4 (2943). As shown in Fig. 4.15c, during the whole process of the fault, including the opening of the breakers, the measured transient voltage energy at Q is much smaller than 2943. This means the protection Q will not mal-operate under the severe interference caused by the opening of the breakers either, thus not leading to the maloperation of the corresponding DCCB. This is because although the opening of the breaker will lead to the interference, generally, this kind of interference will not be stronger than the interference caused by the metallic fault. According to the discussion above, the protections and DCCBs of Line2 will not be influenced by the opening of the breakers on Line1 , so do the protections and DCCBs on the other lines. (2) The Performance of the MMC Station during the Fault Period The MMC is the most vulnerable elements to dc faults in the dc grid, so the performance of the MMC during fault period, including the occurrence of the fault and the isolation of the fault, is observed in this section. Figure 4.16 shows the simulation results after the pole-to-ground fault at f 7 . After the fault, the protection acts to trip the corresponding DCCBs, so the fault line current can be cleared quickly as shown in Fig. 4.16a. Meanwhile, as shown in Fig. 4.16b, due to the quick action of the protection and DCCB, the arm currents in the MMC do not exceed the selfprotection threshold value 3.7 kA [2]. Therefore, as shown in Fig. 4.16b–f, the MMC can operate continuously after the fault, and recover to the steady state quickly after the fault being isolated. But it should be noted that, the dc reactor for fault current limitation cannot be too large, because it will lead to some negative influences on the system and DCCB [2, 19]. Therefore, in some serious fault conditions, such as the metallic fault at f 1 , the MMC (MMC1 ) may be blocked quickly after the fault as shown in Fig. 4.17, although the protection and DCCB act quickly (millisecond level). Considering the reliability requirement and existing technique, it is not realistic to improve the acting speed of the protection and DCCB further. Therefore, the effective dc fault current limiting

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

(d)

(c)

(b)

(a)

96 3.5 3 2.5 2 1.5 1 0.5 0 -0.5 1.5 1 0.5 0 -0.5 -1 -1.5 -2 700 600 500 400 300 200 100 0

fault time

2 1.5 1 0.5 0 -0.5 -1 -1.5 2.4

(e)

2.3 2.2 2.1

(f)

2 3 2 1 0 -1 -2 -3

2.8

3

3.2

3.4

3.6

3.8

4

time (s) Fig. 4.16 The performance of the station MMC1 after line midpoint metallic fault f 7 : a dc current of the fault line (kA), b arm currents (kA), c dc voltage (kV), d dc current of the converter station export (kA), e sub-module capacitor voltages in the MMC (kV), f ac currents (kA)

(a)

4.5 Case Study

97 10 8 6 4 2 0 -2 6

fault time

(b)

4 2 0 -2

(c)

8 6 4 2 0 -2 2.4

(d)

2.3 2.2 2.1

(e)

2 6 4 2 0 -2 -4 -6

2.97

2.98

2.99

3

3.01

3.02

3.03

3.04

3.05

time (s) Fig. 4.17 The performance of the station MMC1 after line export metallic fault f 1 : a dc current of the fault line (kA), b arm currents (kA), c dc current of the converter station export (kA), d sub-module capacitor voltages in the MMC (kV), e ac currents (kA)

technique is also necessary for the VSC-HVDC grid, which will be discussed in detail in other chapters.

98

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

Table 4.4 Cable parameters Outer radius (mm)

ρ (m)

ε

μ

Core

22

1.68e−8

–

1

Insulator 1

39.5

–

4.1

1

Sheath

44

2.27e−7

–

1

Insulator 2

47.5

–

2.3

1

(3) The performance of the novel protection for cables The discussion above is mainly for the overhead line application scenario. In this section, the applicability of the proposed protection for the dc cable is verified. Therefore, the lines in the four-terminal dc grid are replaced by the cables, where the length of the cables Line1 – Line4 are 100 km, 200 km, 100 km, 200 km respectively. And the cable parameters are listed in Table 4.4. The other parameters of the module remain unchanged. On this basis, the simulation results of the proposed fault identification criterion and fault direction criterion for different faults are listed in Table 4.5 (also protection M for instance). According to the principle in Sect. 5.3.2, E set of the protection M for dc pole-to-ground fault is set as 3.47, while that for dc pole-to-pole fault is set as 3.5. As the simulation results showing, the proposed protection strategy can identify the internal and external faults reliably and sensitively, even under the high-resistance condition. It verifies that the proposed protection has high applicability for the dc grid with cables.

Ac fault

Dc pole-to-pole fault

f1

Dc pole-to-ground fault

0

f2

0

0

f4

f9

0

f3

0

0

f7

f8

0

f1

0

f2

3.83

300

0.26

0.65

4.67

1.71

64.66

182.56

237.04

4.67

1.7

7.23

150

0

64.46

5.45

300

0

10.58

150

13.21

300 182.56

25.03

150

0

236.95

|d j_Line |

0

Fault resistance ()

f4

f3

f7

Fault location

Fault type

Table 4.5 Performances of the novel protection on the cable

0.06

32.94

237.09

0.45

16.75

47.18

61.45

237.06

0.45

0.99

1.87

16.7

1.4

2.74

47.18

3.41

6.48

61.43

|d j_Bus |

4.2

0.02

0.02

3.77

3.86

3.87

3.86

0.02

3.76

3.85

3.85

3.86

3.88

3.87

3.87

3.87

3.86

3.86

max|dj_ line (k)| max|dj_ con (k)|

Forward

Backward

Backward

Forward

Forward

Forward

Forward

Backward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Forward

Direction

0.07

1.04

21.82

2.92

4181

33,329

56,189

21.81

2.89

14.67

52.33

4155

29.66

111.93

33,329

174.4

626.32

56,148

Ej

External

External

External

External

Internal

Internal

Internal

External

External

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Internal

Fault identification

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

√

Correct operation?

4.5 Case Study 99

100

4 High-Speed Single-Ended DC Line Protection for the VSC-HVDC Grid

References 1. Li, B., He, J., Tian, J., et al. (2017, March). DC fault analysis for modular multilevel converterbased system. Journal of Modern Power Systems and Clean Energy, 5(2), 275–282. 2. He, J., Li, B., & Li, Y. (2018, May). Analysis of the fault current limiting requirement and design of the bridge-type FCL in the multi-terminal DC grid. IET Power Electronics, 11(6), 968–976. 3. Kong, F., Hao, Z., Zhang, S., et al. (2014, October). Development of a novel protection device for bipolar HVDC transmission lines. IEEE Transactions on Power Delivery, 29(5), 2270–2278. 4. Ma, Y. J., Li, H. F., Hu, J. B., et al. (2013, December). Analysis of travelling wave protection criterion performance for double-circuit HVDC. Presented at Power and Energy Engineering Conference, Kowloon, China. 5. Li, Z., Zou, G. B., Tong, B. B., et al. (2015, July). Novel traveling wave protection method for high voltage DC transmission line. Presented at IEEE Power &Energy Society General Meeting, Denver, CO, USA. 6. Li, A., Cai, Z., Sun, Q., Li, X., Ren, D., & Yang, Z. (2009, July). Study on the dynamic performance characteristics of HVDC control and protections for the HVDC line fault. Presented at IEEE Power Energy Society General Meeting (pp. 1–5). 7. Descloux, J., Raison, B., & Curis, J. B. (2014, July). Protection algorithm based on differential voltage measurement for MTDC grids. Presented at IET International Conference on Developments in Power System Protection, Copenhagen, Denmark (pp. 1–5). 8. De kerf, K., Srivastava, K., Reza, M., et al. (2011, April). Wavelet-based protection strategy for DC faults in multi-terminal VSC HVDC systems. IET Generation, Transmission & Distribution, 5(4), 496–503. 9. Sneath, J., & Rajapakse, A. D. (2016, June). Fault detection and interruption in an earthed HVDC grid using ROCOV and hybrid DC breakers. IEEE Transactions on Power Delivery, 31(3), 973–981. 10. Li, R., Xu, L., & Yao, L. Z. (2017, June). DC fault detection and location in meshed multiterminal HVDC systems based on DC reactor voltage change rate. IEEE Transactions on Power Delivery, 32(3), 1516–1524. 11. Leterme, W., Beerten, J., & Van Hertem, D. (2016, April). Nonunit protection of HVDC grids with inductive DC cable termination. IEEE Transactions on Power Delivery, 31(2), 820–828. 12. Liu, J., Tai, N. L., & Fan, C. J. (2017, June). Transient-voltage-based protection scheme for DC line faults in the multiterminal VSC-HVDC system. IEEE Transactions on Power Delivery, 32(3), 1483–1494. 13. Xiang, W., Yang, S. Z., Xu, L., et al. (2019, February). A transient voltage-based DC fault line protection scheme for MMC-based DC grid embedding DC breakers. IEEE Transactions on Power Delivery, 34(1), 334–345. 14. Geddada, N., Yeap, Y. M., & Ukil, A. (2018, June). Experimental validation of fault identification in VSC-based DC grid system. IEEE Transactions on Industrial Electronics, 65(6), 4799–4800. 15. Zheng, W., Zhang, N., & Yang, G. Y. (2015, December). Comparative and improvement investigation on the DC transmission line traveling wave protections of Siemens and ABB. Power System Protection and Control, 43(24), 149–154. 16. Xue, Y. L., Xu, Z., Zhang, Z. R., et al. (2014, August). Analysis on converter impedancefrequency characteristics of the MMC-HVDC system. Proceedings of the CSEE, 34(24), 4040– 4048. 17. Marti, J. R. (1982, January). Accurate modelling of frequency-dependent transmission lines in electromagnetic transient simulations. IEEE Transactions on Power Apparatus and Systems, 101(1), 147–157. 18. Bo, Z. Q. (1998, October). A new non-communication protection technique for transmission lines. IEEE Transactions on Power Delivery, 13(4), 1073–1078.

References

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19. Li, B., He, J., Li, Y., et al. (2019, April). A novel solid-state circuit breaker with self-adapt fault current limiting capability for LVDC distribution network. IEEE Transactions on Power Electronics, 34(4), 3516–3529.

Chapter 5

High-Speed Differential Protection for the VSC-HVDC Grid

In the LCC-HVDC transmission system, the dc current differential protection is generally used as the backup protection for the dc line. However, a long-time delay is introduced in the detailed differential criterion, to eliminate the negative influence of the unbalanced current mainly caused by the line distributed capacitor current, and guarantee the selectivity of the protection. It leads the operation time of the dc current differential protection to be hundreds-of-milliseconds level, which cannot satisfy the requirement of the VSC-based dc grid. In the UHVAC transmission system, the current differential protection based on the Bergeron model is proposed to eliminate the influence of distributed capacitor current [1]. In the VSC-based dc grid, this concept can also be used to design the dc current differential protection, which is discussed in detail in this chapter. Meanwhile, it should be noted that the Bergeron model of the transmission line is the parameter-fixed model, which does not consider the influence of the line parameter frequency-dependent characteristic. This will reduce the calculation accuracy of the differential current, thus limiting the performance of the protection. To solve this problem, the frequency-dependent characteristic of the line parameters is analyzed [2]. And the improved strategy, which can reduce the influence of frequency-dependent characteristic, is proposed.

5.1 The Bergeron Model of the DC Transmission Line 5.1.1 The Distributed Characteristic of the Transmission Line Parameters The parameters of the transmission line, including the resistance R, inductance L, capacitance C and conductance G are evenly distributed along the line. If the distributed parameters are replaced by the lumped parameters, the corresponding

© Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_5

103

104

5 High-Speed Differential Protection for the VSC-HVDC Grid

Fig. 5.1 The evenly distributed parameter model of the line

u(x,t)

u(x+dx,t) dx

i(x,t)

R·dx

L·dx

i(x+dx,t)

C·dx

G·dx x

calculation accuracy will be reduced. And the longer the line is, the larger the error will be. The distributed parameters of the transmission line can be expressed as Fig. 5.1, where dx represents the infinitesimal length, while R, L, C and G denote the resistance, inductance, capacitance and conductance of the unit-length line. According to the KVL and KCL, the voltage and current of the line satisfy u(x + dx, t) = u(x, t) − R0 dx · i(x, t) − L 0 dx ·

∂i(x, t) ∂t

(5.1)

i(x + dx, t) = i(x, t) − G 0 dx · u(x, t) − C0 dx ·

∂u(x, t) ∂t

(5.2)

Therefore, 

− ∂∂ux = R0 i + L 0 ∂i ∂t − ∂∂ix = G 0 u + C0 ∂u . ∂t

(5.3)

Equation (5.3) is named as the equation of the uniform transmission line, also named as telegraph equation. In addition, the subscript 0 of R, L, C and G in (5.3) represents that the line parameters are all constant. The telegraph equation indicates that the evenly distributed resistance and inductance cause the change of the line voltage, while the evenly distributed capacitance and conductance cause the change of line current.

5.1.2 The Bergeron Model The Bergeron model of the transmission line is a constant-coefficient distributed parameter model, which neglects the transmission loss and the line parameters frequency-dependent characteristic. It considers the influence of the distributed

5.1 The Bergeron Model of the DC Transmission Line

105

capacitance and inductance, and shows the time-domain relationship of voltage and current on the uniform transmission line. When the line loss is neglected, Eq. (5.3) can be expressed as ⎧ ∂u ∂i ⎪ = L0 ⎨− ∂x ∂t ∂u ∂i ⎪ ⎩− = C0 . ∂x ∂t

(5.4)

In (5.4), there is a coupling relationship between the voltage and current. By the further derivation, the second-order wave equation of the lossless uniform transmission line can be expressed as ⎧ 2 1 ∂ 2u ∂ u ⎪ ⎪ ⎨ 2 = 2 2 ∂x v ∂t 2 ⎪ ∂ i 1 ∂ 2i ⎪ ⎩ = ∂x2 v2 ∂t 2

(5.5)

√ where v = 1 L 0 C0 , is the propagation velocity of the traveling wave on the lossless uniform transmission line. The solutions on (5.5) are   ⎧ x x ⎪ + u t − t + u(x, t) = u 1 2 ⎨ v v  1  x x 1 ⎪ ⎩ i(x, t) = − u1 t − u2 t + ZC v ZC v

(5.6)

 where Z C = L 0 C0 is the wave impedance of lossless line, while u 1 and u 2 represent the forward voltage traveling wave and backward voltage traveling wave respectively. According to (5.6), the Bergeron model of the lossless uniform transmission line can be expressed as i j (t) =

u j (t) + Ijk (t − τ ) ZC

(5.7)

i k (t) =

u k (t) + Ikj (t − τ ) ZC

(5.8)

where uj and ij are the voltage and current at terminal j of the transmission line. uk and ik are the voltage and current at terminal k. The forward direction is set as from bus to line. τ = l/v is the propagation delay of the traveling wave on the line with the length of l. I jk and I kj are the equivalent current sources, which represent the traveling wave propagated from the opposite terminal, i.e., Ijk (t − τ ) = −

u k (t − τ ) − i k (t − τ ) ZC

(5.9)

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5 High-Speed Differential Protection for the VSC-HVDC Grid

j

k ij(t)

uj(t)

Ijk(t-τ)

uk(t) ZC

ik(t)

Ikj(t-τ)

ZC

Fig. 5.2 The Bergeron model of the single lossless uniform transmission line

j

R/4

j''

j' ZC

ZC

R/2

k '' ZC

k'

R/4

k

ZC

Fig. 5.3 The Bergeron model of the single transmission line considering the transmission loss

Ikj (t − τ ) = −

u j (t − τ ) − i j (t − τ ). ZC

(5.10)

According to (5.7)–(5.10), the Bergeron model equivalent circuit of the single lossless uniform transmission line can be expressed as Fig. 5.2. The above derivation is developed for the lossless transmission line. To reflect the influence of the distributed resistance, the sectional lumped resistors can be introduced to simplify the calculation, as shown in Fig. 5.3. According to the practical engineering experience, although this simplification will lead to some calculation error, the calculation accuracy is enough for the practical application requirement. Correspondingly, the mathematical expression of the Bergeron model, which considers the transmission loss, can be expressed as    Z C + rl/4 1 rl u k (t + τ ) − i k (t + τ ) Z C + i j (t) = 2Z C ZC 4    Z C − rl/4 1 rl u k (t − τ )+i k (t − τ ) Z C − − 2Z C ZC 4

  1 rl rl u k (t) − i k (t) . − · 2Z C 2Z C 4

(5.11)

Equation (5.11) shows the calculation method of j-terminal current ij (t) by the kterminal voltage and current. Similarly, the k-terminal current can also be calculated according to the j-terminal voltage and current in the same way.

5.2 The Frequency-Domain Equivalent Model …

107

5.2 The Frequency-Domain Equivalent Model of the DC Transmission Line Due to the skin effect of the transmission line and the ground circuit, the equivalent resistance and inductance of the line are not constant actually, which change with the frequency. This means the parameters of the transmission line have the frequencydependent characteristic. In other words, R and L in (5.1)–(5.2) cannot be described as the constant values R = R0 and L = L 0 , which should be expressed as R = R(ω) and L = L(ω). The frequency-domain telegraph equation of the transmission line can be expressed as ⎧ dU ⎪ = ZI ⎨− dx ⎪ ⎩ − dI = Y U dx

(5.12)

where U and I are the frequency-domain voltage and current along the line, Z = R(ω) + jωL(ω) and Y = G + jωC are the frequency-domain series impedance matrix and parallel admittance matrix respectively. Decoupling the first-order differential equation (5.12), the decoupled second-order differential equation can be obtained ⎧ 2 ⎪ ⎪ d U = ZYU ⎨ dx 2 2 ⎪ ⎪ d I ⎩ = Z Y I. dx 2

(5.13)

The solutions of (5.13) can be expressed as Ux = A1 e−γ x + A2 eγ x Ix =

1 (A1 e−γ x − A2 eγ x ) ZC

(5.14) (5.15)

where the wave impedance Z C and the propagation coefficient γ are both frequencydependent,  Z C (ω) = γ (ω) =

√

ZY =





R(ω) + jωL(ω) G + jωC

(5.16)

(R(ω) + jωL(ω)) · (G + jωC).

(5.17)

Z = Y

According to (5.14) and (5.15), the frequency-domain equivalent model of the transmission line can be expressed as

108

5 High-Speed Differential Protection for the VSC-HVDC Grid

j

Fig. 5.4 The frequency-domain model of the transmission line

k

Ij

Uj

Ihj

Uk ZC

ZC

Ik

Ihk

Ij =

Uj + Ijkf ZC

(5.18)

Ik =

Uk + Ikjf ZC

(5.19)

where the equivalent current sources I jkf and I kjf are  Uk Ijkf = − + Ik e−γ l ZC  Uj Ikjf = − + Ij e−γ l . ZC

(5.20) (5.21)

According to (5.18)–(5.21), the frequency-domain equivalent model circuit of the transmission line can be expressed as Fig. 5.4. When the line loss and frequencydependent characteristic are all neglected, the wave impedance Z C and the propagation coefficient γ are both constant, while e−γ l is only the delay function. Under this condition, Fig. 5.4 is completely the same as Fig. 5.2. Differently, Z C and γ change with the frequency, when the line loss and line parameters frequency-dependent characteristic are considered. The frequency-dependent model can correctly reflect the transient response of the electrical variables along the line. However, its computation load is very huge.

5.3 The Traditional Current Differential Protection for the DC Line The traditional dc current differential protection uses the time-domain sampled current to calculate the differential current directly, i.e., 

i diff ≥ Iset T ≥ Tset .

(5.22)

5.3 The Traditional Current Differential Protection for the DC Line

109

During the normal steady operation, the current on the dc line is a through current, which means idiff is equal to zero in theory. So the differential criterion does not act. On the contrary, after an internal fault, the currents at the two terminals of the fault line both flow to the fault point. Therefore, the differential current idiff increases quickly to exceed the threshold value I set , and the protection identifies the fault as an internal fault. However, because of the existence of the transmission line distributed capacitors, the capacitor current will be very large during the transient process, especially when the transmission line is very long. In other words, any condition which leads the line voltage to change, such as the external fault, the system starting and so on, will result in a large capacitor current. When the capacitor current is larger than the threshold value I set in (5.22), the differential protection will identify the above conditions as the internal fault by mistake. To eliminate the negative influence of the capacitor current (unbalanced current), a long-time delay (hundreds-of-milliseconds level to second level) is introduced in the traditional dc current differential protection. This means the operation time of the traditional dc current differential protection is at least hundreds-of-milliseconds level. For the requirement of the VSC-based dc grid, the novel dc current differential protection, with higher operation speed and operation reliability still needs to be researched.

5.4 The DC Pole-Current Differential Protection Based on the Bergeron Model 5.4.1 The Relationship Between the Differential Current and the Fault Point Current After an internal faut, the fault line is divided into two uniform transmission lines, as the line jf and line kf shown in Fig. 5.5. For this two line segments, the new time-domain response can be expressed as     u f t − τj u j (t) = −i j f t − τj + −i j (t) + ZC ZC

Fig. 5.5 The fault on the single line

j

ij

ijf

(5.23)

f

ik

ikf

ij_cal τj

τk τ

k

110

5 High-Speed Differential Protection for the VSC-HVDC Grid

i k f (t) +

u f (t) u k (t − τk ) = i k (t − τk ) + ZC ZC

(5.24)

where τ j is the propagation time of the traveling wave from the fault point to the terminal j, and τ k is the propagation time of the traveling wave from the terminal k to the fault point. ijf is the current flowing from the line segment jf to the fault point, and ikf is the current flowing from the line segment kf to the fault point. Substitute t − τ j for t in (5.24). Considering that τ j + τ k = τ, it can be obtained that     u f t − τj u k (t − τ ) = i k f t − τj + . (5.25) i k (t − τ ) + ZC ZC Eliminating uf by combining (5.23) and (5.25), it can be obtained that i j (t) −

    u j (t) u k (t − τ ) + i k (t − τ ) + = i j f (t − τk ) + i k f t − τj = i f t − τj ZC ZC (5.26)

Similarly, i k (t) −

u j (t − τ ) u k (t) + i j (t − τ ) + = i f (t − τk ). ZC ZC

(5.27)

Equations (5.26) and (5.27) are the basis of the Bergeron-model based current differential protection, which is also the theoretical basis of the traveling wave differential protection. In the Bergeron-model based current differential protection, a position on the transmission line will be selected as the reference point. And the differential current is defined as the differential current of the currents at two sides of the reference point, which are calculated according to the terminal currents and voltages of the line. As shown in Fig. 5.5, when the fault happens at the reference point, the calculated currents at the two sides of the reference point are ijf and ikf respectively. This means the differential current at the reference point is equal to the fault point current if . However, the reference point is selected previously, and the fault position is unpredictable. Therefore, it is impossible to guarantee that the reference point is the fault position all the time, while the relationship between the differential current at the reference point and the fault current at the fault point should be analyzed. In this section, the reference point is selected at the terminal j of the line. Under this condition, the differential current at the reference point (terminal j) can be calculated as i jdiff (t) = i j (t) − i j_ cal (t)

(5.28)

5.4 The DC Pole-Current Differential Protection Based on the Bergeron Model

111

where ijdiff is the differential current at the reference point (terminal j), and ij (t) is the measured current at the reference point. ij_cal (t) is the current at terminal j calculated according to the voltage and current at terminal k, which can be expressed as i j_ cal (t) =

u j (t) u j (t) u k (t − τ ) + Ijk (t − τ ) = − − i k (t − τ ). ZC ZC ZC

(5.29)

According to (5.26), (5.28) and (5.29), the differential current at the reference point, ijdiff can be expressed as i jdiff (t) = i j (t) − i j_ cal (t) = i j (t) −

  u j (t) u k (t − τ ) + + i k (t − τ ) = i f t − τj . ZC ZC (5.30)

The above conclusion is derivated for the single lossless uniform transmission line. When the transmission loss is considered, Fig. 5.3 and Eq. (5.11) can be introduced. In addition, when the reference point is not selected at the line terminal, the function relationship between the reference point differential current and the fault point current is a little different. But it is still a function of the fault point current.

5.4.2 The Proposed DC Pole-Current Differential Protection Based on the Bergeron Model According to the theoretical analysis above, the Bergeron line model can completely compensate the time-domain capacitor current, therefore the novel pole-current differential protection is designed as follows. For the dc transmission line jk, select the reference point r as shown in Fig. 5.6. According to the sampled terminal voltages and currents, uj , ij , uk and ik , calculate the currents at the two sides of the reference point, namely ijr_cal and ikr_cal . Under the external fault or system normal operation conditions, the line Bergeron model is not broken. So the calculated current ijr_cal is equal to ikr_cal , and the differential current is zero. On the contrary, when the fault happens on the protected line, the line Bergeron model is broken by the fault point. So the calculated current ijr_cal is not equal to ikr_cal anymore. The differential current is dependent on the fault point current according to the analysis in Sect. 5.4.1. Fig. 5.6 Reference point r on the line

ij

j

ijr_cal ikr_cal r

uj

ijf

f

idiff

ikf

ik k uk

τ'

112

5 High-Speed Differential Protection for the VSC-HVDC Grid

τ'

Fig. 5.7 The time selection of the calculation current

t-2τ'

τ' t-τ'

ikr_cal(t-τ')

t present moment

Therefore, the novel pole-current differential protection based on the Bergeron model is designed as 

i diff = i jr_cal − i kr_cal |i diff | ≥ i set

(5.31)

where idiff is the reference point differential current, and iset is the threshold value of the differential protection. iset is set as the largest unbalanced current, which may occur during external faults and pole-to-ground faults (on the healthy pole), i.e., i set = krel · max{i unbalance }

(5.32)

where k rel is the reliability coefficient (k rel = 1.3–1.5 generally). By using the Bergeron model, the influence of the capacitor current is avoided. Therefore, the proposed differential protection does not need a long-time delay anymore, and the operation speed is increased significantly. According to (5.11), when calculating the reference point current [ikr_cal (t) for instance], the terminal-k voltages and currents at t + τ  , t and t − τ  , i.e., uk (t + τ  ), uk (t), uk (t − τ  ), ik (t + τ  ), ik (t), ik (t − τ  ) are used. Obviously, it is impossible to obtain the voltage and current [uk (t + τ  ) and ik (t + τ  )], because they refer to the variables in the future time. Therefore, the voltages and currents at t, t − τ  and t − 2τ  are used to calculated the reference point current ikr_cal (t − τ  ) at t − τ  , as shown in Fig. 5.7. In addition, for eliminating the influence of the electromagnetic coupling, the sampled pole voltages and currents are transformed to the modulus values firstly. Then the reference point currents are calculated in the modulus domain. Finally, the modulus reference point calculated currents are inversely transformed to the pole currents. The detailed process is shown as Fig. 5.8, which takes the calculation of ikr_cal (t − τ  ) for instance. And the calculating steps are described as follows. (1) Calculate the k-terminal line-mode and zero-mode voltages and currents according to the sampled positive-pole and negative-pole voltages and currents, by the pole-mode transformation. (2) Calculate the line-mode current ikr_cal_1 (t − τ 1  ) according to the line-mode voltages uk_1 (t), uk_1 (t − τ 1  ) and uk_1 (t − 2τ 1  ), line-mode currents ik_1 (t), ik_1 (t − τ 1  ) and ik_1 (t − 2τ 1  ), line-mode wave impedance Z C1 , line-mode

5.4 The DC Pole-Current Differential Protection Based on the Bergeron Model

t-τ0' ikr_cal_0(t-τ0') inverse transform

ikr_cal_1(t-τ0')

t-τ1' ikr_cal_1(t-τ0')

113

t

present moment

interpolation

ikr_cal(t-τ0') Fig. 5.8 The calculation process of the reference point current

wave velocity v1 , and line-mode equivalent resistance r 1 . Calculate the zeromode current ikr_cal_0 (t − τ 0  ) according to the zero-mode voltages uk_0 (t), uk_0 (t − τ 0  ) and uk_0 (t − 2τ 0  ), zero-mode currents ik_0 (t), ik_0 (t − τ 0  ) and ik_0 (t − 2τ 0  ), zero-mode wave impedance Z C0 , zero-mode wave velocity v0 , and zero-mode equivalent resistance r 0 . (3) It should be noted that the line-mode and zero-mode wave velocities v1 and v0 are different, leading the propagation time delay τ 1  and τ 0  to be different. Therefore, the calculated ikr_cal_1 (t − τ 1  ) and ikr_cal_0 (t − τ 0  ) are at different time. In general, the line-mode wave velocity is larger than the zero-mode wave velocity, so τ 1  is smaller than τ 0  . To obtain the line-mode current and zeromode current at the same, the line-mode calculated at t − τ 0  , namely ikr_cal_1 (t − τ 0  ), can be calculated by interpolation. (4) The pole calculated current ikr_cal (t − τ 0  ) can be calculated according to ikr_cal_1 (t − τ 0  ) and ikr_cal_0 (t − τ 0  ), by the inverse pole-mode transformation. In the practical application, the reference point can be selected at the middle of the line. Under this condition, the required time window is the shortest for calculating the differential current. In addition, considering the error caused by the measurement error or communication delay, an appropriate short-time delay or the integral calculation can be introduced, to improve the operation reliability. For example, the integral criterion with braking variable can be introduced in the differential protection, i.e.,  T    T        K 1    ·  i diff_ p (t) + Iset_ fixed i diff_ p (t) > T  T    0

(5.33)

0

where T is the integral window length, K is the brake coefficient, and I set_fixed is the fixed threshold value.

5.4.3 Case Study The ±800 kV three-terminal HVDC system model as shown in Fig. 5.9 is built based on the PSCAD/EMTDC, where the station S1 is the LCC station, S2 and S3 are the

114

5 High-Speed Differential Protection for the VSC-HVDC Grid

f1 f 2

f3

f4

Line1 Bus_j Bus_k

f6 f5

S1

f7 Line2

f8

f9

Bus_m

S3

S2

Fig. 5.9 The three-terminal HVDC system

MMC stations. During the normal operation, the station S1 operates in the rectifier mode, while S2 and S3 operate in the inverter mode. The detailed parameters of S1 (LCC), S2 and S3 (MMC) are listed in Table 5.1 and Table 5.2 respectively. In addition, the frequency-dependent characteristics of the transmission line parameters are not considered in this section, so the Bergeron model is used in the simulation, and the corresponding parameters are listed in Table 5.3. In this case, the positive pole-to-ground fault f 3 is set to happen at t = 1 s. The fault point current and differential current are observed to verify the operation property of the protection. The corresponding simulation results are shown as Fig. 5.10. As shown in Fig. 5.10, there is a time delay between the fault point current and the calculated differential current, due to the propagation delay and calculation delay. However, it can be found that the differential current calculated based on the Bergeron model is almost accordance with the measured fault point current. However, the differential Table 5.1 The parameters of the LCC station (S1 )

Table 5.2 The parameters of the MMC stations (S2 and S3 )

Parameters

Value

Rated capacity/MW

5000

Rated dc voltage/kV

±800

Rated ac voltage/kV

525

Smoothing reactor/mH

100

Parameters

S2

S3

Rated capacity/MW

3000

2000

Rated dc voltage/kV

±800

±800

Rated ac voltage/kV

525

525

SM number per arm

206

206

SM capacitor/µF

12,000

18,000

Arm reactor/mH

61.2

41.2

Dc reactor/mH

75

75

5.4 The DC Pole-Current Differential Protection Based on the Bergeron Model Table 5.3 The parameters of Line1 and Line2

Parameters Length/km Unit resistance (/km) Unit inductance (mH/km) Unit capacitance (µF/km)

115

Line1

Line2

800

400

Line-mode

7.65 × 10−3

Zero-mode

7.86 × 10−3

Line-mode

0.833

Zero-mode

4.202

Line-mode

1.379 × 10−2

Zero-mode

9.93 × 10−3

15

Fig. 5.10 The differential currents and fault point current on the fault pole

fault point current idiff by the Bergeron model idiff by sampled currents

current/kA

10

5

0

1

1.005

1.010

1.015

1.020

t/s

current calculated directly according to the sampled current is different from the fault point current, due to the distributed capacitor current. It verifies that the differential current calculated based on the Bergeron model can eliminate the influence of the distributed capacitor current. Furthermore, the operation performances of the proposed strategy and the traditional strategy on Line1 and Line2 are observed, as shown in Fig. 5.11. Figure 5.11b shows the calculated differential currents on the healthy pole of the fault line (Line1). According to the simulation results, there is a large unbalanced current when the differential current is calculated directly according to the sampled terminal currents, which is caused by the line distributed capacitor current. But the differential current based on the Bergeron model is approximately equal to zero. Similarly, on the healthy line (Line2), the differential current calculated according to the sampled currents is very large, while it is almost zero when the differential current is calculated based on the Bergeron model.

116

5 High-Speed Differential Protection for the VSC-HVDC Grid

30

3 proposed method

proposed method

traditional method

traditional method

20

idiff/kA

idiff/kA

2

10

0

1.0

1.02

1.04

1.06

1.08

1

0

1.10

1.0

1.02

1.04

1.06

1.5

proposed method

traditional method

traditional method

1

idiff/kA

idiff/kA

1.10

1.5 proposed method

0.5

0

1.08

t/s b) negative pole of the fault line

t/s a) positive pole of the fault line

1

0.5

1.0

1.02

1.04

1.06

1.08

t/s c) positive pole of the healthy line

1.10

0

1.0

1.02

1.04

1.06

1.08

1.10

t/s d) negative pole of the healthy line

Fig. 5.11 The differential currents on the fault line (Line1) and healthy line (Line2) after the pole-to-ground fault f 3 (the transmission line model is the Bergeron model)

The above simulation results verify that the Bergeron model can eliminate the influence of the distributed capacitor current completely. In another word, the unbalanced current of the novel current differential protection is very small. So the operation reliability, speed and sensitivity are improved effectively.

5.5 The Influence of the Parameters Frequency-Dependent Characteristics on the Differential Protection and the Improved Strategy 5.5.1 The Influence of the Line Parameters Frequency-Dependent Characteristics on the Performance of the Current Differential Protection Based on the Bergeron Model As mentioned above, the parameters of the transmission line have the frequencydependent characteristics, due to the skin effect. However, the Bergeron model only considers the parameters distribution characteristic, which is a parameter-fixed model. In addition, during the normal operation of the dc system, the current is a constant dc current. To guarantee the calculation accuracy during this period, the

5.5 The Influence of the Parameters Frequency-Dependent …

117

low-frequency (such as 0.1 Hz or 0.01 Hz) parameters are selected for the protection design. However, after the dc fault, the fault current signal includes broadband components. And the parameters frequency-dependent characteristics obviously have negative influence on the calculation accuracy of the differential current based on Bergeron model (Fig. 5.12). Figure 5.13 shows the simulation results of f 3 , where the lines model in the three-terminal HVDC system described in Sect. 5.4.3 is replaced by the frequencydependent model. The geometric parameters of the line is shown as Fig. 5.12. According to Fig. 5.13, although the differential current (calculated based on the Bergeron model) on the fault pole is still close to the fault point current, the large unbalanced current occurs on the healthy pole (of the fault line) and healthy line due to the parameters frequency-dependent characteristics. It indicates that the line parameters frequency-dependent characteristics have serious influence on the calculation accuracy of the differential current based on the Bergeron model. Obviously, it will affect the reliable operation of the proposed Bergeron-model-based current differential protection. Figure 5.14 shows the calculated differential currents after the pole-to-ground f 3 with a 500  transition resistor. As shown in Fig. 5.14a, the maximum differential current is about 1.5 kA under the 500  pole-to-ground fault. However, as shown in Fig. 5.13b, the unbalanced current on the healthy pole of the fault line, after the metallic fault f 3 , is very large (larger than 1.5 kA) when the Bergeron model is used to calculate the differential current. To guarantee the operation reliability of the protection, the threshold value of the differential current criterion should be set at least above 2 kA. However, under this condition, the proposed current differential protection cannot operate under the high-resistance fault. Fig. 5.12 The geometric parameters of the line

118

5 High-Speed Differential Protection for the VSC-HVDC Grid

25

2 proposed method

idiff/kA

20

proposed method

traditional method

15 1 10 0.5

5 0

1.0

1.02

1.04

1.06

t/s a) positive pole of the fault line

1.08

0

1.10

proposed method

1.02

1.04

1.06

t/s b) negative pole of the fault line

1.08

1.10

proposed method

1

traditional method

1.5

traditional method

idiff/kA

0.8 0.6

1

0.4

0.5 0

1.0

1.2

2

idiff/kA

traditional method

1.5

0.2 1.0

1.02

1.04

1.06

1.08

1.10

0

1.0

t/s c) positive pole of the healthy line

1.02

1.04

1.06

1.08

1.10

t/s d) negative pole of the healthy line

Fig. 5.13 The differential currents on the fault line (Line1) and healthy line (Line2) after the pole-to-ground fault f 3 (the transmission line model is the frequency-dependent model) 0.5

2

0.4

idiff/kA

idiff/kA

1.5 1 0.5 0

0.3 0.2 0.1

6.3

6.32

6.34

6.36

6.38

t/s a) positive pole of the fault line

6.4

0

6.3

6.32

6.34

6.36

6.38

6.4

t/s b) negative pole of the fault line

Fig. 5.14 The differential currents on the fault line (fault pole and healthy pole) after the poleto-ground fault f 3 with 500  transition resistor (the transmission line model is the frequencydependent model)

5.5.2 The Improved Strategy 5.5.2.1

The Comparison of the Line-Mode and Zero-Mode Parameters

According to the above analysis, the differential current, in the Bergeron-modelbased current differential protection, is calculated based on (5.11). In (5.11), the line parameters equivalent resistance r, wave impedance Z C and the propagation delay (determined by the wave velocity v) are used. Therefore, the frequency-dependent characteristics of r, Z C and v are analyzed in this section. Figures 5.15, 5.16 and 5.17 calculate the line-mode and zero-mode r, Z C and v of the transmission line (the geometric parameters of the analyzed line is shown as Fig. 5.12). According to the calculated results, the change degree of the line-mode parameters is weaker than

5.5 The Influence of the Parameters Frequency-Dependent …

resistanceΩ/m

10-2

4.5

zero-mode

*10-6 zero-mode

4

line-mode

line-mode

3.5 inductance H/m

10-1

119

10-3 10-4 10-5

3 2.5 2 1.5 1

-6

10

10-1 100

101

102

103

0.5

104 105

f/Hz (a) frequency-dependent characteristic of the line resistance

10-1 100

101

102

103

104 105

f/Hz (b) frequency-dependent characteristic of the line inductance

Fig. 5.15 The line-mode and zero-mode equivalent resistance of the transmission with different frequency 700

0

zero-mode line-mode

650

-10

500

angle/°

magnitude/Ω

550 450 400

-15 -20

350 300

-25

250 200

zero-mode line-mode

-5

600

10-1 100

101

102

103

104 105

f/Hz (a) magnitude-frequency characteristic of the wave impedance

-30

10-1 100

101

102

103

104 105

f/Hz (b) phase-frequency characteristic of the wave impedance

Fig. 5.16 The line-mode and zero-mode wave impedance of the transmission with different frequency

the zero-mode parameters, especially the wave velocity. It means the calculation error of the line-mode differential current will be smaller than that of the zeromode differential current. In another word, when the current differential protection is designed under the line mode, the influence of the parameter frequency-dependent characteristic can be reduced significantly.

120

5 High-Speed Differential Protection for the VSC-HVDC Grid 3

Fig. 5.17 The line-mode and zero-mode wave velocity of the transmission with different frequency

wave velocity/m/s

zero-mode line-mode 2.5

2

1.5 -1 10

10

0

10

1

10

2

10

3

10

4

10

5

f/Hz

5.5.2.2

The Improved Line-Mode Bergeron-Model Based Current Differential Protection

According to the analysis in Sect. 5.5.2.1, the frequency-dependent characteristics of the line-mode parameters are not as great as the zero-mode parameters. Therefore, the line-mode Bergeron-model based current differential protection is proposed in this section, namely, 

i diff_ 1 = i jr_ cal_ 1 − i kr_ cal_ 1   i diff_ 1  ≥ i set_ 1

(5.34)

where idiff1 is the line-mode differential current, ijr_cal_1 and ikr_cal_1 are the line-mode calculated current at the two sides of the reference point r. And iset is the threshold value of the differential criterion, being set based on the largest unbalanced current, which may occur under different kinds of external faults, i.e.,   i set_ 1 = krel · max i unbalance_ 1

(5.35)

where the reliability coefficient kel is generally set as 1.3–1.5. For the differential protection, the largest unbalanced current occurs after the external nearby metallic pole-to-pole fault. And of all kinds of internal faults, the differential current is the smallest under high-resistance fault condition. Figure 5.18a, b shows the line-mode calculated differential current after the high-resistance (500 ) pole-to-ground fault at f 3 and metallic pole-to-pole fault at f 5 respectively. According to the simulation results, the largest unbalanced current under external fault conditions is only about 0.3 kA, while the differential current under internal high-resistance fault condition is about 1 kA. It indicates that, the line-mode Bergeron-model-based

5.5 The Influence of the Parameters Frequency-Dependent … 1.5

idiff/kA

Fig. 5.18 The line-mode differential current under different kinds of dc faults

121

1 0.5 0

6.3

6.32

6.34

6.36

6.38

6.4

t/s a) internal positive pole-to-ground fault with 500Ω

idiff/kA

0.4 0.3 0.2 0.1 0

6.3

6.32

6.34

6.36

6.38

6.4

t/s b) external pole-to-pole fault

current differential protection can distinguish the internal fault and external fault with high reliability and sensitivity, and has strong capability against the high transition resistance. However, it should be pointed that, the line-mode differential current cannot be used to select the fault pole, so the fault pole selection criterion must be configured additionally.

5.5.2.3

The Fault-Pole Selection Criterion

According to (5.30), the relationship between the differential currents and the fault point current satisfies 

 i diff_0 (t) i diff_1 (t)

 =



 1 i f p (t − τ0 ) + i f n (t − τ0 ) . =√ i f 1 (t − τ1 ) 2 i f p (t − τ1 ) − i f n (t − τ1 )

i f 0 (t − τ0 )

(5.36)

For different kinds of faults (positive pole-to-ground, negative pole-to-ground and pole-to-pole), the fault point currents can be expressed as Fig. 5.19a–c respectively. According to Fig. 5.19, it can be obtained that ⎧ ⎪ ⎨ positive pole-to-ground: i f p (t) = i f (t), i f n (t) = 0 negative pole-to-ground: i f p (t) = 0, i f n (t) = −i f (t) ⎪ ⎩ pole-to-pole: i f p (t) = i f (t), i f n (t) = −i f (t).

(5.37)

122

5 High-Speed Differential Protection for the VSC-HVDC Grid

ifp Rg

positive pole

positive pole

negative pole

negative pole

ifn

(a) positive pole-to-ground

ifp

positive pole negative pole

ifn

ifp

Rg

Rg

(b) negative pole-to-ground

ifn

(c) pole-to-pole

Fig. 5.19 Fault currents under different kinds of faults

Therefore, the differential currents under different kinds of faults can be expressed as ⎧ 1 1 ⎪ ⎪ ⎪ positive pole-to-ground: i diff0 (t) = √ i f (t − τ0 ), i diff1 (t) = √ i f (t − τ1 ) ⎪ ⎪ 2 2 ⎨ 1 1 negatives pole-to-ground: i diff0 (t) = − √ i f (t − τ0 ), i diff1 (t) = √ i f (t − τ1 ) ⎪ ⎪ ⎪ 2 2 ⎪ ⎪ √ ⎩ pole-to-pole: i diff0 (t)= 0, i diff1 (t) = 2i f (t − τ1 ) (5.38) Furthermore, ⎧ 1 1 ⎪ ⎪ positive pole-to-ground: i diff0 (t + τ0 ) = √ i f (t), i diff1 (t + τ1 ) = √ i f (t) ⎪ ⎪ ⎪ 2 2 ⎨ 1 1 negative pole-to-ground: i diff0 (t + τ0 ) = − √ i f (t), i diff1 (t + τ1 ) = √ i f (t) ⎪ ⎪ ⎪ 2 2 ⎪ ⎪ √ ⎩ pole-to-pole: i diff0 (t + τ0 ) = 0, i diff1 (t + τ1 ) = 2i f (t). (5.39) According to (5.39), it can be found that: Under the positive pole-to-ground fault, the value of idiff0 (t + τ 0 )/idiff1 (t + τ 1 ) = 1 in theory. Under the negative pole-toground fault, idiff0 (t + τ 0 )/idiff1 (t + τ 1 ) = −1. And under the pole-to-pole fault, idiff0 (t + τ 0 )/idiff1 (t + τ 1 ) = 0. According to the above characteristic, the fault pole selection criterion can be designed as

5.5 The Influence of the Parameters Frequency-Dependent …

123

⎧ ⎨ |i diff0 (t + τ0 )/i diff1 (t + τ1 )| < S pole-to-pole fault i (t + τ0 )/i diff1 (t + τ1 ) > S positive pole-to-ground ⎩ diff0 i diff0 (t + τ0 )/i diff1 (t + τ1 ) < −S negative pole-to-ground

(5.40)

where S is the threshold value, which is introduced to avoid the influence of the calculation error caused by the parameter frequency-dependent characteristics.

5.5.3 Case Study The proposed line-mode Bergeron-model-based current protection is applied in the three-terminal HVDC system described in Sect. 5.4.3, where the frequencydependent model is used for the transmission line. The sampling rate of the differential protection is 10 kHz, the threshold value of the current differential criterion (iset1 ) is set as 0.5 kA, and the threshold value of the fault pole selection criterion (S) is set as 0.1. Different kinds of faults are simulated to display the operation of the proposed method. The performance of the proposed method on Line1 are listed in Table 5.4. As shown in Table 5.4, the proposed line-mode current differential protection and fault pole selection criterion can operate correctly under different kinds of faults. The proposed method eliminates the influence of the distributed capacitor current and reduces the influence of the line parameters frequency-dependent characteristics. So the long-time delay is not needed anymore, and the protection operation speed can be increased significantly.

Table 5.4 Operation of the line-mode Bergeron-model-based current differential protection Position Type

f1

f2

f3

Pole-to-pole

Resistance/ Current idiff0 (t + τ 0 )/idiff1 (t + τ 1 ) Fault pole differential criterion 0

External

–

Positive 0 pole-to-ground 500

External

–

– –

External

–

–

Negative 0 pole-to-ground 500

External

–

–

External

–

–

Pole-to-pole

0

Internal

0.001

Pole-to-pole

Positive 0 pole-to-ground 500

Internal

0.989

Positive

Internal

0.957

Positive

Internal

−0.994

Negative

Negative 0 pole-to-ground 500

Internal

−0.980

Negative

Pole-to-pole

Internal

−2 × 10−5

Pole-to-pole

0

(continued)

124

5 High-Speed Differential Protection for the VSC-HVDC Grid

Table 5.4 (continued) Position Type

f4

f5

f6

f7

f8

f9

Resistance/ Current idiff0 (t + τ 0 )/idiff1 (t + τ 1 ) Fault pole differential criterion

Positive 0 pole-to-ground 500

Internal

0.992

Positive

Internal

0.974

Positive

Negative 0 pole-to-ground 500

Internal

−0.989

Negative

Internal

−0.977

Negative

Pole-to-pole

0

Internal

−0.001

Pole-to-pole

Positive 0 pole-to-ground 500

Internal

1.005

Positive

Internal

0.977

Positive

Negative 0 pole-to-ground 500

Internal

−0.995

Negative

Internal

−0.980

Negative

Pole-to-pole

0

External

–

–

Positive 0 pole-to-ground 500

External

–

–

External

–

–

External

–

– –

Negative 0 pole-to-ground 500

External

–

Pole-to-pole

0

Internal

1 × 10−4

Pole-to-pole

Positive 0 pole-to-ground 500

Internal

1.006

Positive

Internal

0.988

Positive

Negative 0 pole-to-ground 500

Internal

−1.004

Negative

Internal

−0.994

Negative

Pole-to-pole

0

Internal

1 × 10−4

Pole-to-pole

Positive 0 pole-to-ground 500

Internal

1.002

Positive

Internal

0.991

Positive

Negative 0 Pole-to-ground 500

Internal

−1.001

Negative

Internal

−1.001

Negative

Pole-to-pole

0

Internal

−1 × 10−4

Pole-to-pole

Positive 0 pole-to-ground 500

Internal

0.998

Positive

Internal

0.991

Positive

Internal

−0.998

Negative

Negative 0 pole-to-ground 500

Internal

−1.004

Negative

Pole-to-pole

0

External

–

–

Positive 0 pole-to-ground 500

External

–

–

External

–

–

External

–

–

External

–

–

Negative 0 pole-to-ground 500

References

125

References 1. Li, B., Chang, W., He, J., & Bo, Z. (2009). Special problems in current differential protection based on Bergeron model. In 2009 Asia-Pacific Power and Energy Engineering Conference, Wuhan (pp. 1–4). 2. Marti, J. R. (1982). Accurate modeling of frequency-dependent transmission lines in electromagnetic transient simulation. IEEE Transactions on Power Apparatus and Systems, 101(1), 147–157.

Chapter 6

Traveling-Wave Based Direction Protection for the Multi-terminal HVDC Grid

6.1 The Existing Direction Protections in DC Grid In the dc grid, the single-ended protection, which uses local signals to identify the fault line, is generally considered as the main protection for the dc transmission line, because the communication with the opposite end of the line is not required and the acting speed can be very fast [1–3]. In addition, the pilot protections (based on communication), such as the current differential protection and directional pilot protection, are generally used as the backup protection to improve the operating reliability of the dc protection strategy [4]. Obviously, in the directional pilot protection, fast and reliable fault direction criterion is the key technique. However, it should be pointed out that, even in the single-ended protection, the fault direction criterion is also necessary, to exclude the backward fault. Because the main criterion itself cannot identify the backward faults and the forward faults, especially the backward nearby metallic fault and the forward remote high-resistance fault. For example, in the non-unit protection scheme proposed in [3], which is based on the reflection of the traveling wave (TW) at inductive terminations, the voltage magnitude and derivative were used to identify the fault location, while the current change rate was used to identify the fault direction. In the Siemens TW based single-ended dc protection scheme, the dc current variation (i) based criterion is introduced to identify the fault direction [5]. In the ROCOV (ratio of change of voltage) based protection discussed in [6], the direction criterion by comparing the ROCOVs on both sides of the reactor is used. In the transient-voltage based protection proposed in [7], the direction criterion based on the transient-voltage amplitude ratio is proposed to exclude the backward fault. In summary, the direction criterion is very important for the protection in the multi-terminal HVDC grid, because it can be used not only for the direction pilot protection, but also for the single-ended protection to exclude the backward fault. In a dc grid, the dc current variation (i) based direction criterion and the dc current change rate (di/dt) based direction criterion are the two most typical direction criteria [8–11]. The i based direction criterion identifies the fault as forward when i is © Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_6

127

128

6 Traveling-Wave Based Direction Protection …

larger than a positive threshold value. However, under high-resistance fault condition, the value of i is very small, thus cannot be used to identify the fault direction reliably [8, 9]. Similarly, the di/dt based criterion identifies the fault as forward when it is larger than a positive threshold value, but the acting reliability is influenced by the line distributed capacitors [10, 11]. Recently, several novel direction criteria using the boundary effect of dc reactor are proposed. For example, Ref. [6] proposed to identify the fault direction by comparing the ROCOVs on both sides of the reactor. Similarly, Ref. [12] used the peak values of |du/dt| at both sides of dc reactor to identify the fault direction. Further, Ref. [7] proposed a novel direction criterion based on the amplitude ratio of the transient voltages at both sides of the reactor, to improve the capability against high transition resistance. However, the above dc direction criteria are all based on the boundary effect of dc reactor. In another word, for the dc line protection in dc grid, they are feasible only when the dc reactors are installed on both ends of each dc line. But in practical engineering, the dc reactors may not be installed on each dc line end in some dc grids. For example, in the Wudongde Three-terminal HVDC grid which is under construction in China [13], dc reactors are only installed at the converter export terminals. Therefore, the dc direction criterion suitable for multi-terminal HVDC grid, especially not based on the boundary components, still needs to be developed. The TW based direction protection uses the difference between forward TW and backward TW to identify the fault direction, which is not dependent on the boundary element. For example, Ref. [14] identified the fault direction by comparing the energy of the fault-generated forward and backward TWs. Reference [15] proposed a direction protection scheme based on the integral value relations of the forward and backward TWs within a short time after the fault. However, in the dc grid, the protection uses wide-frequency-band signals to configure the criterion. So the influence of transmission line parameters frequency-dependent characteristic, on the protection acting sensitivity and reliability, must be considered. In this chapter, the improved transient TW based direction criterion, which is not based on the boundary component and is immune to the frequency-dependent characteristic of dc line parameters (thus with high sensitivity and high reliability), is proposed.

6.2 The Development of the Single-Ended Selective Protection for DC Line in VSC-HVDC Grid 6.2.1 The TW Theory The parameters of power transmission lines have the distribution characteristics, as shown in Fig. 6.1. The time-domain response characteristics of the voltage u and current i can be expressed as [16]

6.2 The Development of the Single-Ended Selective … Fig. 6.1 The distribution parameters based transmission line model

i Rdx Ldx

…

u Gdx …

129

…

…

Cdx

b dx

…

⎧ ∂u ∂i ⎪ + L + Ri = 0 ⎨ ∂x ∂t ⎪ ⎩ ∂i + C ∂u + Gu = 0 ∂x ∂t

…

(6.1)

where L and R represent the series-connected inductance and resistance of the per-unit-length line respectively. While C and G represent the parallel-connected capacitance and conductance. For the dc transmission line, there is intercoupling characteristic between the positive and negative pole lines. Generally, in order to eliminate the above intercoupling influence, the decoupling transform is introduced as ⎧     U0 UP 1 1 1 ⎪ ⎪ ⎪ =√ ⎪ ⎨ U1 2 1 −1 UN      ⎪ IP ⎪ ⎪ I0 = √1 1 1 ⎪ ⎩ I1 IN 2 1 −1

(6.2)

where U 1 and I 1 represent the line-mode voltage and current respectively, while U 0 and I 0 represent the earth-mode voltage and current. U P and I P are the voltage and current of positive pole, while U N and I N are the voltage and current of negative pole [17, 18]. In addition, according to Ref. [7], the frequency-domain response characteristic of the voltage and current on transmission line is expressed as ⎧ −γ x γ x ⎨ Uk (x) = Fk e k + Bk e k =UF_k (x)+UB_k (x) B U (x) UB_k (x) F ⎩ Ik (x) = k e−γk x − k eγk x = F_k − Zk Zk Zk Zk

(6.3)

where k = 0 or 1, represents the earth-mode or line-mode respectively. γ k denotes the propagation √ constant of the line, and Z k is the wave √ impedance which can be obtained as Z 0 = (Z s + Z m )/(Y s + Y m ), and Z 1 = (Z s − Z m )/(Y s − Y m ). According to (6.3), the voltage and current are both composed of the forward TW and backward TW. In other words, the TW characteristics can reflect the parameter-distribution characteristics of the transmission line. Furthermore, according to (6.3), the forward and backward TWs can be calculated by the voltage and current. For example, the

130

6 Traveling-Wave Based Direction Protection …

line-mode forward and backward voltage TWs can be calculated as U 1 + I 1 Z 1 and U 1 − I 1Z 1.

6.2.2 Principle of the Traditional TW Based Direction Criterion The traditional TW based direction criterion is shown as

forward fault: K = |u F /u B | < K set backward fault: K = |u F /u B | ≥ K set

(6.4)

where uF and uB represent the change values of the forward and backward voltage TW (line-mode generally) in time domain, respectively. K set is the threshold value, which is generally set as between 1 and 2 [15]. Initially, this criterion was proposed for the ac system, while in [15], its use is extended to LCC-HVDC systems. For using in multi-terminal HVDC grid, the working principle of the TW based direction criterion is discussed here. Figure 6.2 shows the topology of a typical threeterminal HVDC grid. Taking the protection M in Fig. 6.2 for instance, under different fault conditions (forward fault and backward fault), the characteristics of the TW are different. (1) Forward Fault: The fault superposition circuit after the forward fault for protection M is shown in Fig. 6.3a, and the corresponding Bewley-lattice diagram is expressed as Fig. 6.3b. In Fig. 6.3b, t 0 is the time when the initial fault TW arrives at protection M, whereas v represents the transmission speed of the fault TW. In addition, the lengths of Line1 and Line2 are l 1 and l 2 respectively. As shown in Fig. 6.3b, during the period [t 0 , t 0 + 2l 2 /v), the fault TW at the protection M mainly includes: (1) the initial fault TW from the fault point (uM1_B ) and its reflection TW (uM1_F ); f8

f6

f7

908km

S1

N

M

f1

f2

S2

Mid-Span sag

Mid-Span sag 26m for Conductors 15m for Ground wires

G1

22m

G2 Ground wire

6m

0.5m

S3

f5

18m for Conductors 13m for Ground wires

Conductor

f4

f3

Line1

Line2

Ground wire

542km

C1

20m

Conductor

0.45m 0m

Fig. 6.2 The topology of a typical three-terminal HVDC grid

G2 28m

8m

C2

58m

G1

C1

23m

64m

0m

C2

6.2 The Development of the Single-Ended Selective …

131

Fig. 6.3 Propagation characteristics of the TW after the forward and backward faults (for protection M): a fault superposition circuit, b the Bewley-lattice diagram of the forward fault, c the Bewleylattice diagram of the backward fault

(2) the TW reflected from the opposite-terminal bus bar (Bus1 ) (uM2_B ) and its reflection TW (uM2_F ); and (3) the TW reflected from the fault point (uM3_B ) and its reflection TW (uM3_F ). It can be seen that uM1_F , uM2_F , uM3_F , …, uMi_F are the forward TWs for the protection M, while uM1_B , uM2_B , uM3_B , …, uMi_B are the backward TWs. Therefore, the amplitude ratio (K) of the forward TW and backward TW can be calculated as    u M1_F + u M2_F + u M3_F · · · + u Mi_F    K = u M1_B + u M2_B + u M3_B · · · + u Mi_B  

  k u M1_B + u M2_B + u M3_B · · · + u Mi_B   r = (6.5)  = |kr |  u M1_B + u M2_B + u M3_B · · · + u Mi_B  where k r denotes the reflection coefficient. Generally, |k r | < 1 [19], which will be analyzed in depth later. This means after forward fault, K = |k r | < 1 during the time period [t 0 , t 0 + 2l2 /v). (2) Backward Fault: After the backward fault, the fault superposition circuit and its Bewley-lattice diagram are shown as Fig. 6.3a and c respectively. As shown in Fig. 6.3c, during the period [t 0 , t 0 + 2l 1 /v), the fault TW at the protection M mainly

132

6 Traveling-Wave Based Direction Protection …

includes: (1) the transmission TW (uM1_F ) of the initial fault TW (uN1_B ); (2) the transmission TW (uM2_F ) of the TW reflected from the opposite-terminal bus bar Bus3 (i.e., uN2_B ); and (3) the transmission TW (uM3_F ) of the TW reflected from the fault point (i.e., uN3_B ). It can be found that, uM1_F , uM2_F , uM3_F , …, uMi_F are all the forward TWs for the protection M, and there is no backward TW during [t 0 , t 0 + 2l 1 /v). Therefore, the amplitude ratio (K) of the forward TW and backward TW can be calculated as 

 K =  u M1_F + u M2_F + u M3_F /0 = ∞

(6.6)

It indicates that, after backward fault, K → ∞ during the time period [t 0 , t 0 + 2l1 /v). In summary, during the time period [t 0 , t 0 + min (2l 1 /v, 2l 2 /v)), the value of K is smaller than 1 after the forward fault, but much larger than 1 after the backward fault. Therefore, this characteristic can be used to identify the fault direction reliably, and the detailed criterion is shown as (6.4). As analyzed above, for the protection M in Fig. 6.2, the fault direction criterion is valid only during the time period [t 0 , t 0 + min (2l 1 /v, 2l 2 /v)). In addition, if there are more than 2 lines connected with the bus bar, the direction criterion is still applicable, while the action time window should be adjusted to [t 0 , t 0 + min(2l1 /v, 2l2 /v, 2l 3 /v…)), where l1 , l 2 , l 3 … represent the lengths of the lines. Generally, the propagation speed of the TW on overhead line is approximately 300 km/ms [20], and the length of the dc lines in HVDC transmission grid is usually hundreds of kilometers. Therefore, the TW based direction criterion is valid in several milliseconds after the initial fault TW arrives. Thus, it can identify the fault direction reliably in several milliseconds, and such action speed is suitable for multi-terminal HVDC grid using MMC. Moreover, this direction criterion is not dependent on the boundary component (mainly referring to the dc reactor) at line terminal.

6.2.3 The Applicability Analysis of the Traditional TW Based Direction Criterion in Multi-terminal HVDC Grid The direction criterion with high speed, reliability and sensitivity is necessary for the multi-terminal HVDC grid. As analyzed in Sect. 6.2.2, the speed of the TW based direction criterion is fast enough for using in multi-terminal HVDC grid. However, the sensitivity and reliability of the traditional TW based direction criterion still need to be improved, which is discussed in detail here. In order to evaluate the sensitivity and reliability of the TW based direction criterion, the sensitivity coefficient ρ sen is defined as K set /K in this paper. For the forward fault, the measured TW amplitude ratio K should be smaller than the threshold value K set . Therefore, the sensitivity coefficient ρ sen is larger than 1. Moreover, a larger sensitivity coefficient ρ sen reflects that the criterion can identify the fault as forward

6.2 The Development of the Single-Ended Selective …

133

with high sensitivity, whereas a small ρ sen indicates that the criterion cannot identify the fault as forward with high sensitivity. On the contrary, for the backward fault, the measured TW amplitude ratio K should be larger than the threshold value K set , and thus, the sensitivity coefficient ρ sen is smaller than 1. A smaller sensitivity coefficient ρ sen reflects that the criterion can identify the fault as backward with high reliability, such that it can reliably avoid mistakenly identifying the fault as forward. After a dc fault, both the voltage and current include the full frequency band components. Therefore, the amplitude ratio of the forward TW and backward TW (K theo ) should be expressed as K theo

 f  max [U ( f ) + Z ( f )I ( f )]d f 1 c1 1  =  0fmax  [U1 ( f ) − Z c1 ( f )I1 ( f )]d f 0

    

(6.7)

where U 1 (f ) and I 1 (f ) represent the fault voltage and current (line-mode) at different frequencies, and Z c1 (f ) denotes the line-mode wave impedance at different frequencies. In practical systems, only the voltage and current in time domain are measured, and only a fixed value of the wave impedance can be used [15]. This means that, in practice, the measured amplitude ratio of the forward TW and backward TW (K prac ) is      u 1 + Z c1 i 1   0fmax [U1 ( f ) + Z c1 I1 ( f )]d f    (6.8) =  K prac =   u 1 − Z c1 i 1   fmax [U1 ( f ) − Z c1 I1 ( f )]d f  0 where u1 and i1 are the change values of the measured line-mode voltage and current, respectively. (1) Neglecting the frequency-dependent characteristics of the line parameters: If the frequency has no influence on the parameters of the transmission line, the wave impedance Z c1 (f ) is constant at different frequencies. Under this condition, the measured amplitude ratio of the forward TW and backward TW (K prac ) equals to the theoretical amplitude ratio (K theo ). It means that the protection-observed characteristic is in full accordance with the theoretical analysis in Sect. 6.2.2. Figure 6.4 shows the simulation results (based on PSCAD/EMTDC) of the forward TW and backward TW after different types of faults (forward and backward) in the multi-terminal HVDC grid shown in Fig. 6.2, where the non-loss Bergeron model is used for the overhead line. As the line parameters in the Bergeron model do not change with frequency, the wave impedance of the line is a fixed value. In this case, the inductive reactance and capacitive reactance (with the frequency 0.1 Hz) of the line per unit length are respectively selected as 0.0478 × 10−5 /m and 1.0457 × 105 M m. Therefore, the wave impedance of the line can be calculated as 224 . Figure 6.4a shows the forward and backward voltage TWs (line-mode) after the forward fault (pole-to-ground fault f 3 , for protection M), and Fig. 6.4b shows the corresponding amplitude ratio. As shown in Fig. 6.4b, during the time period [t 0 , t 0 + min (2l1 /v, 2l 2 /v)), i.e., [t 0 , t 0 + min (2 × 542/300 ms, 2 × 908/300 ms)) ≈ [t 0 , t 0

Fig. 6.4 Simulation results without frequency-dependent characteristics: a the forward and backward voltage TWs after the forward fault (f 3 ) (kV), b the amplitude ratio of the forward and backward voltage TWs after the forward fault (f 3 ), c the forward and backward voltage TWs after the backward fault (f 7 ) (kV), d the amplitude ratio of the forward and backward voltage TWs after the backward fault (f 7 )

6 Traveling-Wave Based Direction Protection … (d) Amplitude ratio (c) TWs [kV] (b) Amplitude ratio (a) TWs [kV]

134 1200

Protection start time (t0)

800

backward TW forward TW

400 0 0.4 0.3 0.2

Time window

0.1 0

-2

-1

0

1

2

3

4

5

3

4

5

800 Protection start time (t0)

600 400 200

forward TW backward TW

0 250 200 150 100 50 0

Time window

-2

-1

0

1

2

time (ms)

+ 3 ms], the maximum measured amplitude ratio K is 0.3485. Set the threshold value K set as 2, the sensitivity coefficient can be calculated as ρ sen = 2/0.3485 = 5.74. It indicates that the criterion can identify the fault as forward with high sensitivity. Figure 6.4c shows the forward and backward voltage TWs after the backward fault (pole-to-ground fault f 7 , for protection M), and Fig. 6.4d shows the corresponding amplitude ratio. It can be seen that, after the backward fault, the backward TW is extremely small during the time period [t 0 , t 0 + 3 ms], and thus the corresponding amplitude ratio is very large (K = 205.34). Under this condition, the sensitivity coefficient can be calculated as ρ rel = 2/205.34 = 0.00974. This means that the criterion can identify the fault as backward with high reliability. The simulation results verify that, if the parameters of the transmission line have no frequency-dependent characteristics, the traditional TW based direction criterion can correctly identify the fault direction with high sensitivity and reliability. (2) The influence of the frequency-dependent characteristics: However, in practical systems, the parameters of the transmission line are frequency-dependent, and the value of Z c changes at different frequencies. Taking the overhead line Line1 and Line2 shown in Table 6.1 for instance, the line-mode wave impedance Z c1 and earthmode wave impedance Z c0 can be obtained by the rational fitting method [21], as shown in Fig. 6.5a, b. As seen, the values of Z c1 and Z c0 change with the frequency. However, only a fixed value of the wave impedance can be used in the protection

6.2 The Development of the Single-Ended Selective … Table 6.1 Parameters of overhead line Conductor

Ground wire

800

magnitude/Ω

Parameter

Line1

Line2

Length (km)

542

908

Hight (m)

64

58

DC resistance (/km)

0.0391

0.02291

Horizontal spacing (m)

23

20

Outer radius (mm)

36.23

47.35

Sag (m)

26

18

Hight (m)

72

64

DC resistance (/km)

0.5807

0.5807

Horizontal spacing (m)

28

22

Outer radius (mm)

15.75

15.75

Sag (m)

15

13

700

700

magnitude/Ω

600

abs(Zc0)

600

135

abs(Zc0) 500

500 400

400

abs(Zc1)

300 200 10-1

1

102

10 f/Hz (a)

abs(Zc1)

300

103

104

200 10-1

1

102

10

103

104

f/Hz (b)

Fig. 6.5 The frequency-dependent characteristics of the wave impedance: a for Line1 , b for Line2

algorithm, and hence the measured amplitude ratio K prac will be different from the true amplitude ratio K theo . After the forward fault, according to (6.7) and (6.8), the difference between K prac and K theo can be calculated as δ = K prac − K theo f f 2 0 max U1 ( f )d f 0 max I1 ( f )[Z c1 ( f ) − Z c1 ]d f =  fmax f [U1 ( f ) − Z c1 ( f )I1 ( f )]d f 0 max [U1 ( f ) − Z c1 I1 ( f )]d f 0 (6.9)

136

6 Traveling-Wave Based Direction Protection …

where the condition, I 1 (f ) > 0, U 1 (f ) < 0 and U 1 (f ) + Zc1 (f )I 1 (f ) > 0, is taken for instance. As shown in Fig. 6.5, the magnitude of the wave impedance decreases with the frequency increasing. So, it can be obtained that [Z c1 (f ) − Z c1 ] ≤ 0. In addition, [U 1 (f ) − Z c1 (f ) · I 1 (f )] < 0 and [U 1 (f ) − Z c1 · I 1 (f )] < 0 under the condition of I 1 (f ) > 0 and U 1 (f ) < 0. Therefore, according to (6.9), δ = K prac − K theo > 0, i.e., K prac > K theo . This means that the parameter frequency-dependent characteristics of the transmission line may lead to the sensitivity coefficient ρ sen = K set /K prac being smaller than the theoretical value K set /K theo . Thus, for the forward fault, the sensitivity of the traditional TW based direction criterion is reduced due to the parameter frequency-dependent characteristics of the line. For the backward fault, in theory, there is only forward TW and no backward TW during the period [t 0 , t 0 + 2l1 /v), i.e., fmax [U1 ( f ) − Z c1 ( f )I1 ( f )]d f = 0

(6.10)

0

Therefore, the theoretical amplitude ratio of the forward and backward TWs (K theo ) is a very large value. However, in practice, the measured backward TW is fmax fmax u 1 − Z c1 i 1 = [U1 ( f ) − Z c1 I1 ( f )]d f = [Z c1 ( f ) − Z c1 ]I1 ( f )d f 0

0

(6.11) Because Zc1 (f ) = Zc1 for changing frequency, the measured backward TW u1 − Z c i1 is not zero. It means the measured amplitude ratio K prac is smaller than the theoretical value K theo , and the sensitivity coefficient ρ sen = K set /K prac is larger than the theoretical value K set /K theo . Consequently, for the backward fault, the reliability of the traditional TW based direction criterion becomes weaker due to the parameter frequency-dependent characteristics of the line. Figure 6.6 shows the simulation results of the forward and backward voltage TWs after different types of faults (forward and backward) in the multi-terminal HVDC grid shown in Fig. 6.2, where the frequency-dependent model is used for the overhead line. The line parameters are shown in Table 6.1, and a fixed wave impedance value (700  in this case) is used to calculate the measured voltage TWs. Figure 6.6a shows the forward and backward voltage TWs after the forward fault (pole-to-ground fault f 3 , for protection M), and Fig. 6.6b shows the corresponding amplitude ratio. As shown, during the time period [t 0 , t 0 + 3 ms], the maximum measured amplitude ratio is 0.7352, and the calculated sensitivity coefficient is ρ sen = 2/0.7352 = 2.72. Obviously, it is much smaller than that under the condition without parameter frequency-dependent characteristics.

Fig. 6.6 Simulation results with the frequency-dependent transmission line: a the forward and backward voltage TWs after the forward fault (f 3 ) (kV), b the amplitude ratio of the forward and backward voltage TWs after the forward fault (f 3 ), c the forward and backward voltage TWs after the backward fault (f 7 ) (kV), d the amplitude ratio of the forward and backward voltage TWs after the backward fault (f 7 )

(d) Amplitude ratio (c) TWs [kV] (b) Amplitude ratio (a) TWs [kV]

6.2 The Development of the Single-Ended Selective …

137

4000 Protection start time 3000 (t0) 2000 1000 0 1 0.8 0.6 0.4 0.2 0 -2 -1 0 2000 Protection start 1500

time (t0)

backward TW

forward TW

Time window 1

2

3

4

5

3

4

5

forward TW

1000 500 backward TW

0 2.5 2 1.5 1 0.5 0

-2

Time window

-1

0

1

2

time (ms)

Figure 6.6c shows the forward and backward voltage TWs after the backward fault (pole-to-ground fault f 7 , for protection M), and Fig. 6.6d shows the corresponding amplitude ratio. As shown, after the backward fault, the measured backward TW is not a small value during the time period [t 0 , t 0 + 3 ms], and the maximum amplitude ratio is only about 2.04. Under this condition, the sensitivity coefficient is calculated as ρ sen = 2/2.04 = 0.9804. Obviously, it is much larger than that under the condition without parameter frequency-dependent characteristics. This means that the acting reliability of the traditional criterion is very weak, and potentially it can lead to false action as the measured amplitude ratio is very close to the threshold value. The simulation results verify that, the frequency-dependent characteristics of the line parameters reduce the sensitivity and reliability of the traditional TW based direction criterion for using in the HVDC grid. In summary, for application in the multi-terminal HVDC grid, the traditional TW based direction criterion described in (6.4) has sufficient acting speed, and is not dependent on the boundary component. However, the sensitivity and reliability of the direction criterion are reduced due to the frequency-dependent characteristics of the transmission line parameters, and require further research.

138

6 Traveling-Wave Based Direction Protection …

6.3 The Proposed Improved TW Based Direction Criterion 6.3.1 The Basic Principle of the Improved Direction Criterion According to the above analysis, the wave impedance changes with frequency due to the frequency-dependent characteristics of the line parameters. However, as shown in Fig. 6.5, with further increase in frequency, the value of the wave impedance tends to be gradually stable. Specially, in the example, the line-mode wave impedance Z c1 (f ) almost becomes a fixed value (239  of Line1 and 219  of Line2 ) in the highfrequency band. Therefore, in order to improve the reliability and sensitivity, this paper proposes to extract the high-frequency components of the measured voltage and current to design the improved TW based direction criterion for using in the dc grid. In the high-frequency band, the theoretical amplitude ratio of the forward TW and backward TW (K theo ) can be expressed as   f2   f [U1 ( f ) + Z c1 ( f )I1 ( f )]d f K theo =  f12  [U1 ( f ) − Z c1 ( f )I1 ( f )]d f f1

    

(6.12)

and the measured amplitude ratio is K prac

  f   u 1,[ f1 , f2 ] + Z c1 i 1,[ f1 , f2 ]   f12 [U1 ( f ) + Z c1 I1 ( f )]d f =   = u 1,[ f1 , f2 ] − Z c1 i 1,[ f1 , f2 ]   f2 [U1 ( f ) − Z c1 I1 ( f )]d f f1

    

(6.13)

where [f 1 , f 2 ] is the selected high-frequency band. u1,[f 1, f 2] represents the components between [f 1 , f 2 ] of the line-mode voltage change value, and i1,[f 1, f 2] represents the components between[f 1 , f 2 ] of the line-mode current change value. According to Fig. 6.5, in high-frequency band, the line-mode wave impedance Z c1 (f ) is approximately a constant. Therefore, as long as the wave impedance Z c1 for the direction criterion is selected as the wave impedance at the high frequency, it is obvious that K prac = K theo according to (6.12) and (6.13). Thus, in high-frequency band, the measured amplitude ratio of the forward TW and backward TW is reliably smaller than 1 after forward fault, whereas it is much larger than 1 after backward fault. Under this condition, with a pre-set threshold value K set between 1 and 2, the sensitivity of the TW based direction criterion for the forward fault, and the reliability for the backward fault, can be much higher than that when the full-frequency-band signals are used.

6.3 The Proposed Improved TW Based Direction Criterion

139

6.3.2 The Designed Improved Direction Criterion Scheme (1) Wavelet Transform: As analyzed in Sect. 6.3.1, by using the high-frequency measured signals and highfrequency wave impedance, the TW based direction criterion has higher action sensitivity and reliability. To extract the high-frequency transient components of the voltage and current, an effective signal processing method becomes the key technology for the improved direction criterion. As the high-frequency components decay very quickly, the applied signal processing method should have the capability to correctly capture the fast-decay characteristic. The wavelet transform has excellent time-domain resolution in highfrequency band, therefore, it is very suitable to extract the fast-decay high frequency components of the measured signals. The continuous wavelet transform (CWT) can be described as ∞ WT(a, b) = −∞

  t −b 1 dt f (t) √ ψ ∗ a a

(6.14)

where f (t) is the original signal, ψ(t) represents the mother wavelet function which satisfies the admissible condition. a is the scale factor, and b is the shift factor. The family wavelets of the wavelet transform can be obtained by continuously changing the values of a and b. However, the CWT is a continuous calculation process, which will result in a large numbers of wavelet coefficients (namely a large storage requirement) and a long calculation process [22]. Obviously, a fast calculation process is essential for the dc protection. Therefore, it is not very suitable to apply the CWT for the proposed criterion. Differently, the discrete wavelet transform (DWT) makes the scale factor and shift factor discrete, which can reduce the calculation complexity significantly [7, 22, 23]. Therefore, the Mallat algorithm, which is a typical DWT algorithm in signal processing, is used to extract the high-frequency transient components of the dc voltage and current in the proposed criterion. The Mallat algorithm uses a series of filtering and binary sampling to process the sampled discrete signals. Supposing that the sampled discrete signal is a0 (k) with the sampling frequency f s , the operation process of the Mallat algorithm can be illustrated as Fig. 6.7. According to Fig. 6.7, the approximation coefficient aj (k) and the detail coefficient d j (k) at level j can be expressed as ⎧  ⎪ ⎪ a j (k) = a j−1 (n)h 0 (n − 2k) ⎪ ⎨ n

 ⎪ ⎪ ⎪ a j−1 (n)h 1 (n − 2k) ⎩ d j (k) = n

(6.15)

140

6 Traveling-Wave Based Direction Protection … a0(k)

h1(k)

fs

d1(k) 1/4fs~1/2fs

h0(k)

a1(k)

h1(k)

0~1/4fs binary sampling

d2(k) 1/8fs~1/4fs

h0(k)

a2(k)

…

0~1/8fs

Fig. 6.7 The operation process of the Mallat algorithm

where h0 (k) and h1 (k) are the low-pass and high-pass filter arrays. Actually, the approximation coefficient aj (k) and the detail coefficient d j (k) represent the low frequency components and high frequency components of the approximation coefficient aj−1 (k). As Fig. 6.5 shown, the higher the frequency is, the more stable the value of wave impedance will be, and thus the more accurate the calculation value of K prac will be. Therefore, it is the most ideal to use the first-level detail coefficient, namely d 1 (k), for the proposed criterion. However, the first level of DWT could be affected by the noise. Therefore, to exclude the influence of noise, the second-level detail coefficient, d 2 (k), is used in the improved direction criterion [24]. (2) Improved Direction Criterion Algorithm: Once the high-frequency components of u1 and i1 are extracted using the Mallat algorithm, the high-frequency forward TW and backward TW can be obtained, and the amplitude ratio is calculated as the ratio of the maximal moduli. In detail, the improved TW based direction criterion can be described as   ⎧ maxU1_d_ j (k)+Z c1 · I1_d_ j (k) ⎪ ⎪   < K set ⎪ ⎨ forward fault: K = maxU  1_d_ j (k) − Z c1 · I1_d_ j (k)   U1_d_ j (k)+Z c1 · I1_d_ j (k) ⎪ max ⎪ ⎪ backward fault: K =   ≥ K set ⎩ maxU1_d_ j (k) − Z c1 · I1_d_ j (k)

(6.16)

where U 1_d_j (k) and I 1_d_j (k) represent the detail coefficients of the measured u1 and i1 at level j. As analyzed, j is usually 2. In addition, in (6.16), the line-mode wave impedance Z c1 is selected as the value in the corresponding frequency band, which can be a fixed value as shown in Fig. 6.5. It should be noted that the frequency band corresponding to the used detail coefficients should guarantee that the wave impedance remains constant. At present, the sampling frequency of the protection in dc grid is around several kHz to dozens-ofkHz level. It means the frequency band corresponding to the used detail coefficients (j = 2) can be at kHz level according to the Shannon’s theorem and the working principle of the Mallat algorithm. As shown in Fig. 6.5, at kHz level, the line-mode wave impedance is approximately a constant. Therefore, the influence of the line

6.3 The Proposed Improved TW Based Direction Criterion

141

parameter frequency-dependent characteristics can be effectively eliminated, and the sensitivity and reliability of the TW based direction criterion can be improved significantly. The flowchart of the proposed novel TW based direction criterion is shown in Fig. 6.8. After a fault, the proposed direction criterion is quickly started by the typical starting criteria based on du/dt and di/dt [7, 23]. Then the change values of the line-mode voltage u1 and current i1 are calculated based on the measured dc voltage and current. After that, the Mallat algorithm is used to obtain the second-level detail coefficients of u1 and i1 , i.e., U 1_d_j (k) and I 1_d_j (k). Finally, the amplitude ratio K is calculated for identifying the fault direction. If K < 2, the fault is identified as forward, while the fault is identified as backward if K ≥ 2.

Fig. 6.8 The flowchart of the proposed novel TW based direction criterion

142

6 Traveling-Wave Based Direction Protection …

6.3.3 Complexity Evaluation of Wavelet Transform Algorithm In the proposed criterion, the wavelet transform is used to extract the transient components. It is necessary to evaluate the complexity of the wavelet transform, because the acting speed is very important for dc protection. In the improved transient TW based direction criterion, the typical DWT—Mallat algorithm, is used to extract the transient voltage and current. Actually, the essence of Mallat algorithm is the inner product between the analyzed data and the filter array, as shown in Fig. 6.9 (db3 wavelet function for instance). In another word, the Mallat algorithm is a series of multiplication and addition. Table 6.2 shows the evaluation results of the Mallat algorithm calculation times, where n represents the number of data in the selected time window of the protection. As shown in Table 6.2, the detailed result depends on the value of n. For example, if n is an odd number, the number of the first-level approximation coefficients is (n + 1)/2. Therefore, there are 3(n + 1) times of multiplication and 2.5(n + 1) times of addition to obtain the first-level approximation coefficients. Furthermore, if (n + 1)/2 is an even number, the number of the second-level detail coefficients is (n + 1)/4. Therefore, there are 1.5(n + 1) times of multiplication and 1.25(n + 1) times of addition to obtain the second-level Fig. 6.9 The calculation process of the Mallat algorithm

n aj-1(k) a j -1 , h1 or h0

Protection start

a j -1 , h1 or h0

6"×"and 6"+" h1(k) or h0(k)

dj(k) or aj(k) (n+1)/2(n is odd) or n/2(n is even)

Table 6.2 Evaluation of the Mallat algorithm calculation times n is odd First level Second level Total times

n is even

(n + 1)/2 is even

(n + 1)/2 is odd

n/2 is even

n/2 is odd

Times of “×”

3(n + 1)

3(n + 1)

3n

3n

Times of “+”

2.5(n + 1)

2.5(n + 1)

2.5n

2.5n

Times of “×”

1.5(n + 1)

3(n + 1)/2 + 3

1.5n

1.5n + 3

Times of “+”

1.25(n + 1)

1.25(n + 1) + 2.5

1.25n

1.25n + 2.5

Times of “×”

4.5(n + 1)

4.5(n + 1) + 3

4.5n

4.5n + 3

Times of “+”

3.75(n + 1)

3.75(n + 1) + 2.5

3.75n

3.75n + 2.5

6.3 The Proposed Improved TW Based Direction Criterion

143

detail coefficients. In conclusion, the total times of multiplication and addition are 4.5(n + 1) and 3.75(n + 1) respectively. In detail, supposing that the selected time window of the protection is 3 ms and the sampling frequency is 10 kHz, it means the number of the analyzed data is 31. Therefore, the total times of multiplication and addition in the Mallat algorithm are 144 and 120 respectively. Similarly, under the conditions with other values of n, the calculation times can be evaluated by the same methods, as shown in Table 6.2. At present, with the development of the hardware technology, the above calculations can be completed very quickly. For example, the DSP TMS320F2833x, which is a typical processor used in the dc protection and control [25], has the 150 MHz operation rate. In another word, the cycle time is 6.67 ns, during which one time of the multiplication or addition can be completed. Therefore, even if the processor is serial-processing, the time of 144 multiplication and 120 addition is only about 1.76 μs. Obviously, this time scale is very small for the dc protection (ms-level). So it can be concluded that, for the present dc protection hardware platform, the complexity of wavelet transform algorithm is very tiny.

6.3.4 The Influence of the DC Reactor on Reflection Coefficient Generally, the dc reactor will be installed at the converter dc export, which has influence on the reflection and transmission coefficients. Obviously, the value of reflection coefficient |k r | has influence on the acting sensitivity of the travelingwave based direction criterion. Therefore, in this section, the reflection coefficient is derived in detail, considering the existence of the dc reactor. The reflection and transmission process of TW, in the typical three-terminal HVDC gird shown as Fig. 6.2, can be described as Fig. 6.10. And the relationship between voltage TW and current TW at Bus2 is Bus3

ZCN1

Transmission TW (Ut, It) Bus2 Incident TW (Ue，Ie) N M Zc1_l2 Zc1_l1 Line2

ICN2 ZCN2

Line1 Reflection TW (Ur, Ir)

Ldc

Fig. 6.10 The reflection and transmission process of the TW

Bus1

ZCN3

144

6 Traveling-Wave Based Direction Protection …

⎧ Ut (ω) = Ue (ω) + Ur (ω) ⎪ ⎪ ⎪ ⎪ Ue (ω) + Ur (ω) ⎪ ⎪ ⎪ ⎪ Ie (ω) − Ir (ω) = It (ω) − Z ⎪ ⎪ CN2 (ω) + jωL dc ⎨ (6.17)

⎪ ⎪ ⎪ Ue (ω) = Ie (ω)Z c1_l1 (ω) ⎪ ⎪ ⎪ ⎪ ⎪ Ur (ω) = Ir (ω)Z c1_l1 (ω) ⎪ ⎪ ⎩ Ut (ω) = It (ω)Z c1_l2 (ω)

where U e (ω), U r (ω), and U t (ω) denote the incident voltage TW, reflection voltage TW and transmission voltage TW. I e (ω), I r (ω), and I t (ω) represent the incident current TW, reflection current TW and transmission current TW. Z c1_l1 , Z c1_l2 denote the line-mode wave impedance of Line1 and Line2 . In addition, L dc is the dc reactor. And Z CN2 represents the equivalent impedance of the converter, whose calculation method can be referred from [7] (MMC for instance). According to (6.17), the reflection coefficient k r can be derived as kr (ω) =

Z c1_ l2 (ω)//(Z CN2 (ω) + jωL dc ) − Z c1_l1 (ω) Ur (ω) = Ue (ω) Z c1_ l2 (ω)//(Z CN2 (ω) + jωL dc )+Z c1_l1 (ω)

(6.18)

According to (6.18), the influence of dc reactor and frequency on the amplitude of the reflection coefficient |k r | [namely the result of (6.5)] is analyzed as shown in Fig. 6.11. As the calculating results showing, in the low-frequency range, |k r | increases with the frequency increasing, which may even goes up to around 1. After that, the amplitude of |k r | begins to decrease. And in the high-frequency range, |k r | will be very small (much smaller than 1). According to the working principle of the TW based direction criterion, the smaller |k r | is, the higher the acting sensitivity will be. Therefore, it further indicates that, the proposed criterion has much higher Fig. 6.11 The frequency-dependent characteristic curve of |k r | with different L dc

1.2

|kr|

1

Ldc=50mH Ldc=150mH Ldc=500mH

0.1

0.8 0.075

0.6 0.05 1250 1500 1750 2000 2250 2500

0.4 0.2 0

0.1

1

10

102 f/Hz

103

104

105

6.3 The Proposed Improved TW Based Direction Criterion

145

acting sensitivity than the traditional criterion, because the proposed method uses the high-frequency transient components to configure the direction criterion. Also as Fig. 6.11 showing, a smaller dc reactor will make the frequency, where |k r | increases, move to the higher range. For example, the critical frequencies, which make the value of |k r | the largest (equal to 1), are 22 Hz, 32 Hz and 38 Hz respectively when L dc is 500 mH, 150 mH and 50 mH. However, even if the value of dc reactor is only 50 mH, |k r | has already become very small after 1 kHz. At present, the typical sampling rate in dc system is at dozens-of-kHz level, which means the frequency of the extracted transient components in the proposed criterion is much larger than 1 kHz. And so the value of dc reactor has tiny impact on the acting sensitivity of the proposed criterion (after the forward fault). In addition, according to the propagation mechanism of the TW, the value of dc reactor has no impact on the TW characteristic after backward fault, i.e., no backward TW can be observed at the protection during [t 0 , t 0 + 2l 1 /v). Therefore, it can be concluded that the value of dc reactor has no impact on the result of (6.6), thus having no influence on the performance of the proposed criterion after backward fault.

6.4 Real-Time Simulation Case Studies A RTDS real-time simulation model of the three-terminal HVDC transmission system shown in Fig. 6.2 is developed to verify the superiorities of the improved transient TW based direction criterion. In the built model, station S1 is the sending end using a LCC, whereas stations S2 and S3 are the receiving ends based on MMCs, whose detailed parameters are listed in Table 6.3. And the main parameters of the used frequency-dependent dc overhead lines were shown in Table 6.1. In order to verify the feasibility and superiorities of the proposed direction criterion, the performances of the protection M on Line1 , with different kinds of faults, are observed. In addition, the sampling frequency of the protection is set as 10 kHz. Table 6.3 Parameters of the three-terminal hybrid HVDC transmission system

Parameter

S1

S2

S3

Rated dc voltage/kV

±800

±770

±780

Rated ac voltage/kV

535

525

525

DC line reactor/mH

150

75

75

Rated power/MVA

9720

3132

5100

The arm reactor/mH

/

61.2

41.2

The SM capacitor/μF

/

12,000

18,000

SM number (per arm)

/

210

210

146

6 Traveling-Wave Based Direction Protection …

6.4.1 The Feasibility of the Traditional Direction Criteria At present, the direction criteria based on the dc current variation i or dc current change rate di/dt are widely used in HVDC transmission systems. In this case, the forward and backward remote pole-to-ground faults both with a 300  resistor are simulated respectively, to discuss the feasibility of the traditional direction criteria (the i based and the di/dt based). The corresponding results are shown in Fig. 6.12. The criterion based on i identifies the fault as forward when i is larger than a positive threshold value [8, 9]. Otherwise, the fault is identified as backward. Here, the positive threshold value is introduced to avoid the mal-operation of the direction criterion during disturbances such as system power flow changes. However, as shown in Fig. 6.12a, after the forward fault with high transition resistor, the value of i is very small, which may be smaller than the threshold value. And thus, the direction criterion cannot identify it as forward correctly. Similarly, for reliability consideration, the di/dt based direction criterion identifies the fault as forward when di/dt is larger than a positive threshold value (positive pole for instance). However, as shown in Fig. 6.12b, the value of di/dt oscillates

(a) Δi [kA]

2 1 0

(b) di/dt [kA/s]

-1

-2

-1

0

1

2

3

4

5

6

7

8

-2

-1

0

1

2

3

4

5

6

7

8

-2

-1

0

1

2

3

4

5

6

7

8

-2

-1

0

1

2

3

4

5

6

7

8

6000 4000 2000 0 -2000 -4000

(c) Δi [kA]

1 0.5 0 -0.5

(d) di/dt [kA/s]

-1 4000 2000 0 -2000 -4000

Time [ms]

Fig. 6.12 The feasibility of the traditional direction criteria based on i or di/dt: a i of the forward fault (kA), b di/dt of the forward fault (kA/s), c i of the backward fault (kA), d di/dt of the backward fault (kA/s)

6.4 Real-Time Simulation Case Studies

147

around zero after the forward fault. Similarly, as shown in Fig. 6.12d, di/dt also oscillates around zero after the backward fault. This phenomenon is caused by the line distributed capacitors. Obviously, this oscillation can result in the mal-operation of the di/dt based direction criterion. For example, after the backward fault, the value of di/dt will also become a positive value as shown in Fig. 6.12d, which may be larger than the pre-set threshold value, causing the criterion to mistakenly identify the fault as forward. Although the i based direction criterion and di/dt based direction criterion are very simple, their reliability is not enough for using in the multi-terminal HVDC transmission system.

6.4.2 The Superiorities of the Improved Transient TW Based Direction Criterion According to the basic principle of the TW based direction criterion, for the protection M in the three-terminal HVDC grid shown as Fig. 6.2, the time window should be within 3.6 ms after starting the criterion. For acting speed and reliability consideration, this paper selects the time window of the TW based direction criterion as [t 0 − 1 ms, t 0 + 2 ms], where t 0 is the protection starting time and is set as 0 in this paper. In the proposed transient TW based direction criterion, the transient voltage and current are extracted by the db3 wavelet. In addition, the high-frequency wave impedance (239  in this case) is selected as the wave impedance value in the proposed criterion. (1) Forward Fault: In this case, the forward metallic pole-to-ground fault (f 2 ) occurs at the midpoint of Line1 . As shown in Fig. 6.13a–c, the full-frequency-band line-mode forward and backward TWs can be calculated according to the measured line-mode dc voltage and current directly. However, as shown in Fig. 6.13c, during the selected time period, the forward TW is very close to the backward TW, and the largest amplitude ratio is 0.73 as shown in Fig. 6.13d. So the sensitivity coefficient ρ sen = 2/0.73 ≈ 2.74 (the threshold value K set is set as 2). In the improved criterion, the high-frequency transient components are extracted to calculate the high-frequency TWs. As shown in Fig. 6.13e, the maximum amplitude of the high-frequency transient forward TW is 20.38 kV while the maximum of the high-frequency transient backward TW is 241.65 kV. So the amplitude ratio K is 0.08, and the sensitivity coefficient ρ sen = 2/0.08 = 25. It indicates that the improved transient TW based direction criterion has higher acting sensitivity than the traditional TW based direction criterion. It should be noted that, the fault transient appears before t = 0, as shown in Fig. 6.13e. This is because, in the Mallat algorithm, the detail coefficient is calculated by the inner product between the analyzed signal data and filtering array, as shown in Fig. 6.9. And the filtering array is a series of data points (not one point). When

148

6 Traveling-Wave Based Direction Protection … (a) DC voltage [kV]

1200 1000 800 600

(b) DC current [kA]

400

-1

0

1

2

3

4

5

-1

0

1

2

3

4

5

4

5

4

5

4 2 0

(c) TWs [kV]

-2

6

-2

4000

Forward TW Backward TW

3000 2000 1000

(d) Amplitude ratio of the forward and backward TWs (e) Transient TWs [kV]

0 0.8

300

-2

-1

0

1

2

3

-2

-1

0

1

2

3

0.6 0.4 0.2 0

Forward TW Backward TW

200

Time window

100 0

-2

-1

0

1

2

3

4

5

Time [ms]

Fig. 6.13 Forward fault: a line-mode dc voltage (kV), b line-mode dc current (kA), c the fullfrequency-band line-mode forward and backward TWs (kV), d the amplitude ratio of the fullfrequency-band forward and backward TWs, e high-frequency transient components of the forward and backward TWs (kV)

calculating the detail coefficient corresponding to the time before (and near) t = 0, the influence of the analyzed data after t = 0 will be introduced, as the red frame in Fig. 6.9 showing. In another word, the detail coefficient, before (and near) t = 0, will also reflect the fault transient. (2) Backward Fault: In this case, the backward metallic pole-to-ground fault (f 6 ) occurs at the adjacent export line (Line2 ). According to the above analysis, in the selected time period, the backward TW is zero in theory. However, as shown in Fig. 6.14c, there is an obvious backward TW in the selected time window caused by the parameter frequencydependent characteristics of the transmission line. Therefore, the amplitude ratio of the forward and backward TWs is not a large value as the theoretical analysis. Here,

6.4 Real-Time Simulation Case Studies

149

(a) DC voltage [kV]

1200 1000 800 600 400

-2

-1

0

1

2

3

4

5

-1

0

1

2

3

4

5

(c) TWs [kV]

(b) DC current [kA]

2 1 0 -1 -2

-2

3000

Forward TW Backward TW

2000 1000

(e) Transient TWs [kV]

(d) Amplitude ratio of the forward and backward TWs

0 -2

-1

0

1

2

3

4

5

-1

0

1

2

3

4

5

4

5

2.5 2 1.5 1 0.5 0

-2 400

Forward TW Backward TW

300 Time window

200 100 0

-2

-1

0

1

2

3

Time [ms]

Fig. 6.14 Backward fault: a line-mode dc voltage (kV), b line-mode dc current (kA), c the fullfrequency-band line-mode forward and backward TWs (kV), d the amplitude ratio of the fullfrequency-band forward and backward TWs, e high-frequency transient components of the forward and backward TWs (kV)

the largest amplitude ratio is only 2.04 as shown in Fig. 6.14d, which is close to the threshold value K set (2). It means the traditional TW based direction criterion may lead to mal-operation. In comparison as shown in Fig. 6.14e, in the selected time window, the highfrequency transient backward TW is approximately equal to zero, and is much smaller than the high-frequency transient forward TW. Specifically, the maximum amplitudes of the transient forward and backward TWs are 349.58 kV and 2.81 kV, respectively, indicating an amplitude ratio K of 124.41 and sensitivity coefficient ρ sen = 2/124.41 = 0.0161. It verifies that the improved direction criterion can identify the backward fault correctly with high reliability.

(a) Transient TWs [kV]

6 Traveling-Wave Based Direction Protection … 80

(b) Transient TWs [kV]

150

120

60

Forward TW Backward TW

Time window

40 20 0

-2

-1

0

90

1

2

3

4

5

2

3

4

5

Time window

60 30 0

-2

-1

0

1

Time [ms]

Fig. 6.15 The capability of the improved direction criterion against high transition resistance: a high-frequency transient components of the forward and backward TWs after the forward fault (kV), b high-frequency transient components of the forward and backward TWs after the backward fault (kV)

(3) Capability Against High Transition Resistance: In this case, the forward and backward high-resistance faults are simulated respectively, to verify the capability of the improved transient TW based direction criterion against high transition resistance. As shown in Fig. 6.15a, after the pole-to-ground fault f 3 with a 300  transition resistor, the transient forward TW is much smaller than the backward TW in the selected time window, and the amplitude ratio K is 0.31. It means the improved criterion can identifies the fault as forward correctly with the sensitivity coefficient ρ sen = 2/0.31 ≈ 6.4516. As shown in Fig. 6.15b, after the pole-to-ground fault f 8 with a 300  transition resistor, the transient backward TW is approximately zero and is much smaller than the forward TW in the selected time window. The amplitude ratio K is 26.16, and the improved criterion can identifies the fault as backward correctly with the sensitivity coefficient ρ sen = 2/26.16 ≈ 0.0764. This case verifies that the improved direction criterion can also identifies the fault direction correctly with high sensitivity and reliability under high-resistance fault condition.

6.4.3 Operation Performance of the Improved Direction Criterion Table 6.4 shows the acting results of the improved direction criterion (with the pre-set threshold value K set = 2) for different kinds of faults in the three-terminal HVDC grid. As the simulation results showing, for the forward faults, the calculated amplitude ratio K of the protection M is far less than 2. Whereas for the backward faults, the amplitude ratio K is much larger than 2. It verifies that the improved direction

6.4 Real-Time Simulation Case Studies

151

Table 6.4 Protection action under different fault scenarios Fault type

Fault location

Dc pole-to-ground fault

f1 f2 f3

ρ sen

0.04

Forward

50.0000

300

0.06

Forward

33.3333

0

0.08

Forward

25.0000

300

0.15

Forward

13.3333

Kj

0

0.24

Forward

8.3333

300

0.31

Forward

6.4516

f4

0

0.19

Forward

10.5263

f5

0

19.12

Backward

0.1046

f6

0

124.41

Backward

0.0161

300

41.53

Backward

0.0482

f7 f8 Dc pole-to-pole fault

Direction

0

Fault resistance ()

f1 f2 f3 f6 f7 f8

0

70.94

Backward

0.0282

300

23.89

Backward

0.0837

0

55.38

Backward

0.0361

300

26.16

Backward

0

0.05

Forward

40.0000

300

0.05

Forward

40.0000

0.0764

0

0.08

Forward

25.0000

300

0.09

Forward

22.2222

0

0.20

Forward

10.0000

300

0.24

Forward

8.3333

0

357.97

Backward

0.0006

300

154.57

Backward

0.0129

0

217.19

Backward

0.0009

300

92.41

Backward

0.0216

0

139.98

Backward

0.0143

300

80.24

Backward

0.0249

criterion can identify the fault direction correctly with high speed, sensitivity and reliability under different kinds of faults.

References 1. Xue, Y. L., Xu, Z., & Tu, Q. R. (2012, October). Modulation and control for a new hybrid cascaded multilevel converter with DC blocking capability. IEEE Transactions on Power Delivery, 27(4), 2227–2237. 2. Ackermann, T., Andersson, G., & Soder, L. (2001, April). Distributed generation: A definition. Electric Power Systems Research, 57(3), 195–204.

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3. Meyer, C., Hoing, M., Peterson, A., et al. (2007, November). Control and design of DC grids for offshore wind farms. IEEE Transactions on Industry Applications, 43(6), 1475–1482. 4. Rahimi, E., Gole, A. M., Davies, J. B., et al. (2006, March). Commutation failure in single-and multi-infeed HVDC systems. Presented at the 8th IEE International Conference on AC and DC Power Transmission, London, UK (pp. 182–186). 5. Xue, Y., Zhang, X. P., & Yang, C. H. (2018, June). Commutation failure elimination of LCC HVDC systems using thyristor-based controllable capacitors. IEEE Transactions on Power Delivery, 33(3), 1448–1458. 6. Jovcic, D. (2007, January). Thyristor-based HVDC with forced commutation. IEEE Transactions on Power Delivery, 22(1), 557–564. 7. Xu, Z., Wang, S., & Xiao, H. (2016, October). Hybrid high-voltage direct current topology with line commutated converter and modular multilevel converter in series connection suitable for bulk power overhead line transmission. IET Power Electronics, 9(12), 2307–2317. 8. Li, B., He, J. W., Li, Y., et al. (2019, April). A novel solid-state circuit breaker with self-adapt fault current limiting capability for LVDC distribution network. IEEE Transactions on Power Electronics, 34(4), 3516–3529. 9. Tang, L. X., & Boon-Teck, O. ( 2007, July). Locating and isolating DC faults in multi-terminal DC system. IEEE Transactions on Power Delivery, 22(3), 1877–1884. 10. Tang, L. X., Dong, X. Z., Shi, S. X., & Qiu, Y. F. (2019, March). A high-speed protection scheme for the DC transmission line of a MMC-HVDC grid. Electric Power Systems Research, 168, 81–91. 11. Li, A., Cai, Z., Sun, Q., Li, X., Ren, D., & Yang, Z. (2009, July). Study on the dynamic performance characteristics of HVDC control and protections for the HVDC line fault. Presented at IEEE Power Energy Society General Meeting (pp. 1–5). 12. Leterme, W., Beerten, J., & Van Hertem, D. (2016, April). Nonunit protection of HVDC grids with inductive DC cable termination. IEEE Transactions on Power Delivery, 31(2), 820–828. 13. Liu, J., Tai, N. L., & Fan, C. J. ( 2017, June). Transient-voltage-based protection scheme for DC line faults in the multiterminal VSC-HVDC system. IEEE Transactions on Power Delivery, 32(3), 1483–1494. 14. Kontos, E., Pinto, R. T., & Bauer, P. (2013). Control and protection of VSC-based multi-terminal DC networks. LAP Lambert Academic Publishing. 15. Sneath, J., & Rajapakse, A. D. (2016, June). Fault detection and interruption in an earthed HVDC grid using ROCOV and hybrid DC breakers. IEEE Transactions on Power Delivery, 31(3), 973–981. 16. Li, B., Li, Y., He, J. W., et al. A novel single-ended transient-voltage-based protection strategy for flexible DC grid. IEEE Transactions on Power Delivery. https://doi.org/10.1109/tpwrd. 2019.2910390. 17. Yang, J., Fletcher, J., & O’Reilly, J. (2010, October). Multiterminal dc wind farm collection grid internal fault analysis and protection design. IEEE Transactions on Power Delivery, 25(4), 2308–2318. 18. Geddada, N., Yeap, Y. M., & Ukil, A. ( 2018, June). Experimental validation of fault identification in VSC-based DC grid system. IEEE Transactions on Industrial Electronics, 65(6), 4799–4800. 19. Farhadi, M., & Mohammed, O. A. (2015, July). Event-based protection scheme for a multiterminal hybrid dc power system. IEEE Transactions on Smart Grid, 6(4), 1658–1669. 20. Li, R., Xu, L., & Yao, L. Z. (2017, June). DC fault detection and location in meshed multiterminal HVDC systems based on DC reactor voltage change rate. IEEE Transactions on Power Delivery, 32(3), 1516–1524. 21. Haleem, N. M., & Rajapakse, A. D. (2018, June). Local measurement based ultra-fast directional ROCOV scheme for protecting Bi-pole HVDC grids with a metallic return conductor. International Journal of Electrical Power & Energy Systems, 98, 323–330. 22. Xiong, Y., Rao, H., Xu, S. K., et al. (2018, September). Research on start and fault ride-through strategy for ultra-high voltage multi-terminal hybrid DC transmission system. Journal of Global Energy Interconnection, 1(4), 478–486.

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Chapter 7

DC Fault Current Limiting Technique Based on the H-bridge Topology

7.1 Requirements on the Fault Current Limitation in DC Grid According to the analysis in Chap. 3, the fault current increases extremely fast after dc fault [1]. For the operation security and power supply reliability, dc faults in the dc grid should be detected and interrupted with a high level of selectivity in several milliseconds, e.g., 2–4 ms [2, 3], resulting in the challenges for both the selective protection and fault isolation. However, according to Chaps. 4–6, the dc protection needs at least several milliseconds to detect and identify the fault line. Meanwhile, the operating speed of the DCCB is also at several-milliseconds level. Obviously, this level of operating speed cannot match the propagation speed of the dc fault in VSC-based dc grid. To slow down the fault propagation, the dc fault current limitation becomes the key technique for fault ride-through of the dc grid, because it can lower the requirement on protection and DCCB operating speed. Recently, different kinds of fault current limiting methods for dc system were researched. Reference [4] proposed an LCL-VSC converter composed of a VSC converter and a passive inductor-capacitor-inductor (LCL) circuit, which can limit the ac-side current and converter current effectively during dc faults. In the multi-terminal dc system, it is very important to limit the dc line current and prevent the dc voltage dropping, however, the LCL-VSC does not have this ability. The superconducting fault current limiter (SFCL) has been proved to have a wide application prospect in the dc system [5]. And it is worth conducting further researches on the dc-systemused SFCL, especially the fast quench after dc faults, fast recovery after isolation and so on. In addition, the dc reactor generates no reactive power, while has strong and fast fault current limiting capability in the VSC-based dc grid [6]. However, for using in the VSC-based dc grid, the FCL must satisfy the following requirements: (1) Enough fault current limiting capability: the dc fault current increases very quickly after dc faults, so the FCL must be able to respond to the fault very quickly, and limit the © Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_7

155

156

7 DC Fault Current Limiting Technique Based …

fault current below the upper limit value until the DCCB is tripped. (2) Influence on the dc grid normal operation: the FCL should not have negative influence on the system normal operation. But the directly installed large dc reactor will deteriorate the dc grid transient response speed and operation stability, especially during the power flow shifting. (3) Cooperation with the DCCB: the DCCB should clear the fault current quickly after being tripped, but the directly installed large dc reactor will prolong the DCCB fault current clearing time drastically. In this chapter, the H-bridge FCL and H-bridge SSCB are researched in detail, which have strong fault current limiting capability, and can avoid the negative influences of the directly installed dc reactor mentioned above.

7.2 The H-bridge FCL Topology and Working Principle in DC Grid Based on the requirements discussed before, this section firstly proposes to apply the bridge-type FCL in the dc system for replacing the dc reactor directly installed on the dc line. As we know, the bridge-type FCL was initially invented for the ac system. When used in the dc system, it has a different working principle and the parameters should be redesigned.

7.2.1 Working Principle of the H-bridge FCL in the DC System As shown in Fig. 7.1, the bridge-type FCL used in the dc gird is composed of a diode bridge (formed by four series diode groups D1 –D4 ), as well as a dc reactor and a dc biased power supply connected in series, which are placed between the common cathode point of D1 , D3 and the common anode point of D2 , D4 . For reducing the power loss of the FCL during normal operation, one option is to replace copper coil by superconducting coil to enwind the dc reactor. The working principle of the bridge-type FCL in the dc system is illustrated in Fig. 7.1a–c. Unlike in the ac system, when the bride-type FCL is used in the dc grid, the dc biased power supply must be equipped. The dc biased power supply provides a dc biased current I b calculated as Ib = Vdc /(rL + rD )

(7.1)

where V dc is the voltage of the dc biased power supply, r L is the resistance of the dc reactor (r L is negligible in the case of the superconducting coil), and r D is the conducting resistance of each series diode group (D1 , D2 , D3 and D4 ).

7.2 The H-bridge FCL Topology and Working Principle in DC Grid

(a)

A

D1

iD1=(Ib+idc)/2 idc

LB

iL=Ib

-

iD2=(Ib-idc)/2

D1

iD1=idc

(b)

A

(c) A

D2 Vdc +

LB

idc iD2=0

D2 Vdc +

iD1=0

D1

idc iD2=-idc

LB

D2 Vdc +

D3

iL=-idc

iD3=(Ib-idc)/2 idc

D4

iL=idc

157

D3

B

iD4=(Ib+idc)/2

iD3=0 idc B

D4

iD4=idc

D3

iD3=-idc idc

D4

B

iD4=0

Fig. 7.1 Working principle of the bridge-type FCL in the MMC-based dc grid: a current flowing path during normal operation, b current flowing path during fault current limitation (idc > 0), current flowing path during fault current limitation (idc < 0)

According to the Kirchhoff’s current law, if all the series diode groups D1 –D4 are conducting as shown in Fig. 7.1a, the currents flowing through the diode groups can be expressed as 

i D1 = i D4 = (Ib +i dc )/2 i D2 = i D3 = (Ib − i dc )/2.

(7.2)

During normal operation, as long as the dc biased current I b is larger than the absolute value of the dc line current |idc |, (I b + idc )/2 and (I b − idc )/2 are both positive and thus all the diodes D1 –D4 can stay in the conducting state. Meanwhile, the current flowing through the dc reactor remains constant as I b . In this situation, the dc reactor is bypassed from the dc line, thus having no influence on the normal operation of dc grid.

158

7 DC Fault Current Limiting Technique Based …

After a dc fault, the dc fault current rises rapidly. As shown in Fig. 7.1b where idc > 0 (the forward direction of the current is shown in Fig. 7.1), when idc exceeds the dc biased current I b , (I b − idc )/2 will be negative. This means the series diode groups D2 and D3 will be turned off automatically. Thus the dc reactor is connected into the fault circuit instantaneously and automatically, working to limit the fault current. Similarly, if idc < 0, when the absolute value of idc exceeds I b , (I b + idc )/2 will be negative. Therefore, the series diode groups D1 and D4 will be turned off automatically, allowing the dc reactor to be in the fault circuit as well. This means the bridge-type FCL can realize the bidirectional fault current limitation in the dc gird. Moreover, when the dc biased current is properly set, the dc reactor in the FCL can be connected into the fault circuit very quickly after a dc fault, satisfying the fast fault-current-limiting response requirement on the dc-grid-adapted FCL.

7.2.2 Coordination with the DCCB The FCL is supposed to work closely with the DCCB. Next to be discussed is the coordination between the FCL and the DCCB, with focusing on the total fault clearing time (namely the isolation speed) of the DCCB. The hybrid DCCB is the most promising DCCB technique for using in the MMC-based dc grid, so it is taken for instance here. As shown in Fig. 7.2a, the total fault clearing time of the hybrid DCCB consists of the breaking time and fault clearance [7]. The breaking time refers to the duration from the onset moment of the fault to the moment the main breaker is turned off, which is only dependent on the action times of the load commutation switch, ultrafast disconnector and the selective protection. The fault clearance is defined as the period from the moment the main breaker is turned off till the fault current is eliminated to be small enough to be cut off by a residual dc current breaker [7], which mainly depends on the fault energy dissipation speed of the arresters. During the fault clearance period, the clamping voltage of the arrester should be larger than the dc voltage U dc , for eliminating the fault current, and it is assumed as U dc + U margin . Define that the duration of the fault clearance is T clear . As shown in Fig. 7.2b, in the case of installing the dc reactor on the dc line directly, U margin is applied to L F and L l (L l is the equivalent inductance of the fault line). Therefore, (L F + L l ) · didc /dt = −U margin [8]. Supposing the DCCB is tripped at t = 0 s, the dc fault current idc during this period thus can be expressed as i dc = Itrip − Umargin · t/(L F + L l )

(7.3)

where I trip is the dc fault current value at the DCCB tripping moment. So the duration of the fault clearance period T clear is Tclear = Itrip · (L F + L l )/Umargin .

(7.4)

7.2 The H-bridge FCL Topology and Working Principle in DC Grid

159

total fault clearing time fault clearance

breaking time main breaker open UFD open

Current

(a)

LCS open Current through the LCS Current through the main breaker Current through the arresters

Fault

Time

Ll

LF (b)

+

Udc+Umargin

Udc

+

-

-

+

VL

(c)

+

Ll

iL

-

Vdc

+

Udc

Udc+Umargin +

-

-

Fig. 7.2 Coordination between the FCL and DCCB: a fault isolation logic of the hybrid DCCB, b coordination between the dc reactor directly installed and DCCB, c coordination between the bridge-type FCL and DCCB

According to the analysis in [9], for preventing the converter from being blocked after dc faults, the required dc reactor value L F is very large. So T clear will be very large, namely, the total fault clearing time will be very long. This will make it difficult to achieve the fast fault isolation, as well as the fast recovery of the fault line in the case of nonpermanent faults. As analyzed above, for the bridge-type FCL, the dc reactor is connected into the fault circuit instantaneously and automatically after a dc fault, working to limit the fault current. However, once the main breaker in the DCCB is tripped by blocking all the IGBTs, the arresters will be connected into the fault circuit and the dc fault current will begin to decrease. So the voltage across the dc reactor surely satisfy the condition that V L = L B diL /dt ≤ 0. And all the four series diode groups D1 –D4 will

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7 DC Fault Current Limiting Technique Based …

become conducting synchronously due to the forward voltage contributed by the dc reactor and dc biased power supply. That is to say, the dc reactor in the bridge-type FCL is bypassed again from the fault circuit instantaneously, as shown in Fig. 7.2c. Therefore, the bridge-type FCL separates the fault energy of the fault circuit from that of the dc reactor during the fault clearance period. And the arresters in the DCCB only need to dissipate the fault energy in the fault circuit, so under this condition, T clear is Tclear = Itrip · L l /Umargin .

(7.5)

Obviously according to (7.3) and (7.5), the duration of the fault clearance period under this condition is much smaller compared with the dc reactor directly installed on the dc line. Thus the total fault clearing time of the DCCB is reduced significantly. That is to say the fault isolation speed becomes faster. In addition, it should be noted that the fault current being eliminated to zero and then a delay time for the recovery of the line insulation strength are the two necessary prerequisites for the DCCB reclosing. Therefore, with a faster fault isolation, the subsequent fault line recovery in the case of nonpermanent faults is also faster, because the insulation recovery process of the fault line can be advanced evidently. On the other hand, for the same isolation speed, the value of U margin when the bridge-type FCL is applied can be much smaller compared with the dc reactor directly installed. So the voltage-size of the DCCB can be smaller. According to the analysis above, the advantages of the bridge-type FCL to be used in the dc grid can be summarized as follows: (1) During normal operation, the dc reactor in the FCL is unconnected into the dc line, exerting no negative influence on the dc grid normal operation. (2) After a dc fault, the dc reactor will be connected into the fault circuit very quickly and automatically, working to limit the fault current. (3) After the main breaker of the hybrid DCCB is turned off, the dc reactor in the FCL will be bypassed again from the fault circuit instantaneously (also automatically), reducing the total fault clearing time of the hybrid DCCB compared with the dc reactor directly installed.

7.3 The H-bridge Solid-State Circuit Breaker with Self-adaptive Fault Current Limiting Capability The H-bridge FCL has outstanding prospect in dc system, due to the advantages on avoiding negative influence on system operation stability and accelerating the dc fault isolating speed. However, the H-bridge FCL is lack of fast recovery capability. Therefore, this section further proposes an H-bridge solid-state circuit breaker (SSCB) with self-adaptive fault current limiting capability and fast recovery capability [10].

7.3 The H-bridge Solid-State Circuit Breaker …

161

7.3.1 Topology and Working Principle of the H-bridge SSCB with Self-adaptive Fault Current Limiting Capability The topology of the proposed SSCB is shown in Fig. 7.3. It consists of an H-bridge, and a branch in which a dc reactor and a dc biased power supply are placed in series. In the H-bridge, the main breaker 1 composed of series IGBTs is connected with an arrester in parallel, and with the series diode group D1 in series, to constitute the Arm1 , while the structure of Arm2 is the same. For the other two arms (Arm3 and Arm4 ), they are both composed of series diodes (D3 and D4 ). The branch composed of the dc reactor and dc biased power supply is placed between the common cathode point of D1 , D2 and the common anode point of D3 , D4 . And the dc line is connected with the SSCB through the junctions between Arm1 and Arm3 , Arm2 and Arm4 respectively. There are four operation states of the proposed SSCB, namely, the normal operation state, fault current limiting state, fault current clearing state and recovery state. (1) Normal operation state: During the system normal operation, all the IGBTs in the SSCB are in on state. The dc biased power supply provides a dc biased current I b . With different dc line current idc , the proposed SSCB has two operation modes during this state. ➀ 0 < idc < I b (Ru + Rd )/2Ru : According to the KCL theorem, I b is averagely distributed to Arm1 and Arm2 , as well as Arm3 and Arm4 , because the conducting resistances of Arm1 is equal to that of Arm2 , and the resistances of Arm3 and Arm4 are also equal. In addition, idc is distributed to Arm1 and Arm3 at their junction. But considering that the devices in Arm1 and Arm3 are different, which means their conducting resistances are different, the distributed currents are also different. According to the current distribution theory of the parallel circuits, the current distributed to Arm1 from idc is idc · Rd /(Ru + Rd ), and the current distributed to Arm3 from idc is idc · Ru /(Ru + Rd ), where Ru , Rd are the conducting resistances of the upper arms (Arm1 and Arm2 ) and down arms (Arm3 and Arm4 ) respectively. Therefore, as shown in Fig. 7.4➀, the currents of Arm1 –Arm4 (i1 –i4 ) can be expressed as Fig. 7.3 The topology of the proposed SSCB

D2

D1 Arm1

Arm2

Lr

Ub + Arm3

D4

D3

main breaker 1

main breaker 2

arrester

Arm4

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7 DC Fault Current Limiting Technique Based …

i1

i1

i2

Lr

idc

idc

iL

idc

idc iL

Ub + i4

i3

i4

i3

i4

i2

Lr

idc

Ub +

i3

iL and idc

idc

iL

Ub +

i1

i2

Lr

iL idc

arm currents

0

i4 i1

0

i1 idc

i2 i3

t1 t2 t3

t4

i1

i2

Lr

idc

iL

idc

i3

t6

t7

iL

idc

idc

UA +

t8

i1

i2

Lr UA +

Ub +

t5

i3

+

i3

i4 USSCB

i2 idc

UA +

Ub +

Ub + i4

Lr UA +

-

+

i4 USSCB

-

Fig. 7.4 The working principle of the proposed SSCB

⎧ 1 Rd 1 Rd ⎪ ⎪ i dc , i 2 = Ib − i dc ⎨ i 1 = Ib + 2 Ru + Rd 2 Ru + Rd 1 Ru 1 Ru ⎪ ⎪ ⎩ i 3 = Ib − i dc , i 4 = Ib + i dc . 2 Ru + Rd 2 Ru + Rd

(7.6)

Obviously, i1 and i4 are larger than 0. In addition, because idc < I b (Ru + Rd )/2Ru and Rd < Ru , i3 and i2 are also larger than 0. As shown in Fig. 7.4, i1 –i4 are all larger than 0 (corresponding to the arm current schematic waveforms before t 1 ), meaning that Arm1 –Arm4 are all conducting. Therefore, it can be considered that the dc reactor is bypassed from the dc line by the conducting Arm1 –Arm4 . ➁ I b (Ru + Rd )/2Ru ≤ idc < I b : Obviously, according to (7.6), D3 cannot conduct under this condition because I b /2 − idc · Ru /(Ru + Rd ) ≤ 0. Therefore, the biased

7.3 The H-bridge Solid-State Circuit Breaker …

163

current I b can only flows through Arm4 and Arm2 , and the dc line current idc flows to Arm1 completely at the junction between Arm1 and Arm3 . As shown in Fig. 7.4➁, the arm currents can be expressed as 

i 1 = i dc , i 2 = Ib − i dc i 3 = 0, i 4 = Ib .

(7.7)

Obviously, i1 and i4 are all larger than 0. Considering that idc < I b , i2 is also larger than 0. Therefore, Arm1 , Arm2 and Arm4 are conducting under this condition, and it can also be concluded that the dc reactor is bypassed from the dc line by the conducting arms Arm1 and Arm2 . In conclusion, as long as the dc line current idc does not exceed the dc biased current I b , the dc reactor is always bypassed from the dc line, thus having no influence on the normal operation of the dc system. (2) Fault current limiting state: When a dc fault happens, the dc fault current rises [1]. Supposing that the dc line current satisfies 0 < idc < I b (Ru + Rd )/2Ru before the fault, the arm currents i2 and i3 will decrease with idc rising according to (7.6), as the current schematic waveforms shown in Fig. 7.4. And i3 reaches 0 firstly, because Ru > Rd . This means that Arm3 is turned off automatically, and the operation mode of the proposed SSCB gets into Fig. 7.4➁ from Fig. 7.4➀. According to (7.7), i2 continues to decrease. As long as idc increases to exceed I b , i2 reaches 0 and Arm2 is turned off automatically. As shown in Fig. 7.4➂, the dc line current idc can only flow through Arm1 , the dc reactor branch and Arm4 , which means the dc reactor is connected into the fault circuit instantaneously and automatically, working to limit the fault current. Similarly, when idc < 0, once |idc | > I b , only Arm2 and Arm3 will conduct, so the dc reactor is also connected into the fault circuit instantaneously and automatically to limit the fault current. In sum, the proposed SSCB has an automatic (without any change of the SSCB control) and bidirectional fault current limiting capability. Moreover, this fault current limiting response to dc faults can be very fast as long as I b is properly set. In addition, it should be noted that in Fig. 7.4, the current schematic waveforms before the fault correspond to the condition 0 < idc < I b (Ru + Rd )/2Ru . After the dc fault, the proposed SSCB will get into the fault current limiting state from the normal operation state shown as Fig. 7.4➀, passing the transition state shown as Fig. 7.4➁. Differently, if I b (Ru + Rd )/2Ru ≤ idc < I b before the dc fault, the proposed SSCB will get into the fault current limiting state directly from the normal operation state shown as Fig. 7.4➁. (3) Fault current clearing state: As shown in Fig. 7.3, the proposed SSCB has two main breakers. When the tripping signal from the protection is received, the corresponding main breaker should be turned off, with the other one in on state alone. For example, as shown in Fig. 7.4➃, if the fault is located at the Arm2 side, the main breaker 1 in Arm1 should be turned off, while the main breaker 2 in Arm2 is still in on state (taking the SSCB on the positive pole for instance). On the contrary,

164

7 DC Fault Current Limiting Technique Based …

if the fault is located at the Arm1 side, the main breaker 2 in Arm2 should be turned off, and the main breaker 1 in Arm1 is still in on state. As shown in Fig. 7.4➃, once one of the main breakers is turned off (main breaker 1 for instance), the corresponding arrester will be connected into the fault circuit, and thus the fault current begins to decrease. In this state, the freewheeling current of dc reactor will produce a reverse electromotive force to make the Arm2 and Arm4 conduct. And the Arm3 is turned off by the reverse clamping voltage from the arrester in Arm1 . So the freewheeling current of the dc reactor will only flow through Arm2 and Arm4 . It indicates that the dc reactor in the proposed SSCB is bypassed from the fault circuit again after turning off one of the main breakers. That is to say, the arrester needn’t dissipate the energy stored in the dc reactor, because the freewheeling current of the dc reactor can flow in the SSCB itself, and it can be considered that the energy in the reactor is separated from the dc line. So the arrester only needs to dissipate the fault energy of the line during the fault current clearing period, as the current schematic waveforms during t 4 –t 5 shown in Fig. 7.4. According to the calculation method proposed in [8], the fault current clearing time under this condition can be expressed as Tclear = Itrip · L l /(UA − Udc /2)

(7.8)

where I trip is the dc fault current at the moment when the main breaker is turned off, L l is the equivalent inductance of the fault line, U A is the clamping voltage of the arrester, and U dc is the dc voltage of the dc system. Obviously, T clear of the proposed SSCB is much smaller compared with the condition dc reactors are directly installed, because when the dc reactors are directly installed, T clear is Tclear = Itrip · (L l +L r )/(UA − Udc /2)

(7.9)

where L r is the value of the directly installed dc reactor. And generally, L r is much larger than L l . Therefore, the isolating speed of the proposed SSCB is much faster compared with that under the condition the dc reactors are directly installed in the dc system. This important feature is beneficial to guarantee the fast recovery of the healthy network and fast recovery of the fault line insulation characteristic. (4) Recovery state: After the fault point has disappeared or has been removed, the fault line should be re-connected into the system. Meanwhile, the freewheeling current of the dc reactor (namely iL ) in the proposed SSCB is also required to recover to the set value I b . It should be noted that the definitions of iL and I b are different in this chapter. I b is the dc biased current set value required to be provided by the biased power supply during system normal operation, which is a constant (neglecting the change of the power electronic switch conducting resistance). And iL refers to the current flowing through the dc reactor. During system normal operation, the dc line current does not flow through the dc reactor, and the dc reactor current iL is dependent on the dc biased power supply, which means iL = I b . But when the proposed SSCB gets into the fault current limiting state shown in Fig. 7.4➂, the dc reactor is connected

7.3 The H-bridge Solid-State Circuit Breaker …

165

into the fault circuit, therefore iL = idc . And iL is not equal to I b anymore in this state, because the current flowing through the dc reactor branch is not dependent on the dc biased power supply anymore. Then during the fault current clearing state, idc decreases very quickly due to the arrester. But iL only flows through Arm2 and Arm4 , being not exposed to the arrester, which means it decreases very slowly. Therefore, iL will keep in a large value before the recovery state, which is much larger than I b . For the recovery of iL , namely the recovery of the proposed SSCB, the other main breaker still in on state is turned off firstly as shown in Fig. 7.4➄. Therefore, the stored energy in the dc reactor can be dissipated by the arresters. And the freewheeling current iL of the reactor will decay rapidly. Then both the main breaker 1 and 2 are turned on synchronously when iL decays to near Ib , which means the proposed SSCB is recovered completely, to prepare for handling the next fault. In addition, the recovery state of the proposed SSCB also has two operation modes as shown in Fig. 7.4➄ and ➅. ➀ idc < iL /2: Before the recovery state, the dc line current idc = 0, because it has been cleared by the arrester in the fault current clearing state. Therefore, as long as the proposed SSCB gets into the recovery state, the dc reactor current iL is equally distributed to the branch composed of Arm1 and Arm3 , and the branch composed of Arm2 and Arm4 . And dc line current idc can flow through Arm3 and Arm4 directly as long as idc < iL /2 as shown in Fig. 7.4➄. So idc begins to recover quickly as the current schematic waveforms shown in Fig. 7.4. Moreover, the clamping voltages on the two arresters respectively in Arm1 and Arm2 are so polarity-opposite that they just cancel each other out from the dc line, namely, the voltage across the proposed SSCB U SSCB ≈ U A − U A = 0. Therefore, it can be considered that the arresters almost do not function to the dc system. In other words, the fault line is re-connected into the system at the moment when the other main breaker is turned off. And the fault part of the system can recover immediately. This means the recovery of the proposed SSCB almost has no influence on the recovery of the dc system. ➁ idc ≥ iL /2: During the recovery state, iL decreases quickly, and idc increases. If idc increases to exceed iL /2, Arm3 will not conduct anymore. And iL can only flow through Arm2 and Arm4 . As shown in Fig. 7.4➅, the voltage across the proposed SSCB still satisfies U SSCB ≈ U A − U A = 0. So under this condition, it can still be considered that the recovery of the SSCB almost has no influence on the recovery of the dc system.

7.3.2 Comparison with the Existing Methods Obviously, the method of installing the dc reactor directly is the simplest dc fault current limiting method, which, however, has negative influences on the system normal operation and DCCB isolating speed. The HCLC method proposed in [11] turns on the thyristors after opening the DCCB, to make the resistor in the EDC dissipate the fault energy together with the arrester in the DCCB, and thus the current

166

7 DC Fault Current Limiting Technique Based …

clearing speed can be accelerated significantly. However, during system normal operation, the reactor in the HCLC is always connected in the dc line, even when the power flow shifts. This means the HCLC method cannot avoid the negative influence of the reactor on the system normal operation. Differently, the proposed method can bypass or connect the large dc reactor from or into the dc line adaptively with different operation states of the SSCB, namely, the self-adapt fault current limiting. The detailed advantages of the proposed SSCB are listed as follows. • During normal operation, the dc reactor in the proposed SSCB is bypassed from the dc line, thus having no negative influence on the system, including transient response speed, stability and so on. • After dc faults, the dc rector is connected into the fault circuit very quickly and automatically. It can limit the fault current and slow the dc voltage dropping, guaranteeing the fault ride-through of the healthy network, and thus creating enough time for the protection and isolation. • During the fault current clearing state, the dc reactor is bypassed from the fault circuit again, also instantaneously and automatically. It can accelerate the fault isolation drastically, guaranteeing the fast recovery of the healthy network and fast recovery of the fault line insulation characteristic. • The fault part of the system can recover quickly after the fault point has disappeared or been removed. And the SSCB itself can also recover quickly, preparing for handling the next fault.

7.4 Parameter Design and Hybrid Configuration for the Multi-terminal DC Grid 7.4.1 Parameter Design of the Proposed SSCB The design of the proposed SSCB key parameters, mainly including the value of required dc reactor, withstand voltage and current of the power electronic devices, dc biased current and arrester capacity, is discussed in this section, for the purpose of healthy network fault ride-through and creating enough time for the protection. In the dc system, the proposed SSCB can be installed at the dc output positions of the converters. And the parameters should be determined according to the most serious condition, i.e., the metallic pole-to-pole fault at the converter output position, as shown in Fig. 7.5a. (1) Required dc reactor: After dc faults, the dc reactor in the proposed SSCB is connected into the fault circuit very quickly to slow the fault propagation, and create enough time for the protection. Two factors should be considered when determining the value of the required dc reactor. As shown in Fig. 7.5b, with the dc reactor being connected, the fault process will stay in the capacitor discharge stage chronically. In this stage, the overcurrent mainly occurs at the dc side [1]. Therefore, the main target of the fault current limitation is

7.4 Parameter Design and Hybrid Configuration for the Multi-terminal DC Grid

167

Fig. 7.5 DC pole-to-pole fault: a equivalent circuit of the dc pole-to-pole fault at the converter output position, b equivalent circuit of the capacitor discharge stage with proposed SSCB

to limit the dc current idc below the permitted level, namely, idc ≤ I set , before the protection acts to trip the corresponding DCCBs. In addition, during the capacitor discharge stage, the dc voltage decays. If the dc voltage decays to below 2U m (ac phase voltage amplitude), the converter will be blocked due to the over modulation. Hence the dc voltage udc should keep above a permitted value, namely, udc ≥ U set . The transient characteristic shown in Fig. 7.5b is a second-order process. In addition, the fault current limiting effect of conducting resistances (Ru , Rd , Rr ) of the power electronic devices and dc reactor is tiny, thus being neglected when calculating the required dc reactor. Therefore, the dc voltage and dc current during the capacitor discharge stage can be expressed as I0 sin ωt ωC

(7.10)

i dc = U0 ωC sin ωt + I0 cos ωt

(7.11)

u dc = U0 cos ωt −

where U 0 and I 0 are the √initial value of the dc voltage and dc current, L r is the value of the dc reactor, ω = 1/2L r C.

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7 DC Fault Current Limiting Technique Based …

Therefore, the required value L r of the dc reactor in the proposed SSCB can be calculated by solving the following equations I0 sin ωttrip = Uset ωC

(7.12)

U0 ωC sin ωttrip + I0 cos ωttrip = Iset

(7.13)

U0 cos ωttrip −

where t trip is the needed time from the fault moment to the moment when the DCCB is tripped. Because (7.12) and (7.13) are all the transcend equations, the iterative algorithm, such as the dichotomy algorithm, based on the computer is used to solve the equations. And the larger solution of these two equations is selected as the required value of the dc reactor. (2) Withstand voltages and currents of the power electronic devices: For the proposed SSCB, IGBTs and diodes are used, whose maximum voltages and currents should be estimated for type selection. According to the working principle of the proposed SSCB, the maximum currents which may flow through the IGBTs and diodes are both the same as its breaking current. Generally, in the dc system, the breaking current of the SSCB should be determined according to the overcurrent tolerance of the key equipments, such as the converter, the dc cable and so on. Therefore, the current parameter of the IGBTs and diodes can also be determined according to this experience. In addition, the IGBTs of the main breakers in the SSCB only need to withstand the clamping voltage of the arrester, namely U A , so the withstand voltage of the IGBTs can be determined correspondingly. Differently, as shown in Fig. 7.4➂ and ➃, the series diodes group should withstand the clamping voltage of the arrester or the voltage of the dc reactor. Therefore, the withstand voltage of the series diodes groups D1 –D4 is selected as the larger one between U A and U L_max , where U L_max is the largest voltage drop on the dc reactor. According to Fig. 7.5b, U L_max can be estimated as L r × didc /dt|t=0 = 0.5U 0 . Based on the analysis above, the type and number of the IGBTs and diodes in the proposed SSCB can be determined. (3) DC biased current: According to the working principle of the proposed SSCB, I b should not be smaller than the normal operation dc current idc , preventing the dc reactor from adversely affecting the system normal operation, especially the fast transient response and stability of the dc system during power flow shifting. In addition, I b should not be too large either, for the fast current-limiting response to the faults. Therefore, I b is designed as the largest dc load current or a little larger. In particular, it is also feasible to set I b as the largest dc load current. Under this condition, although the dc reactor is connected into the dc line similar to Fig. 7.4➂ when the converter operates at the largest dc load current, it will be bypassed from the dc line instantaneously and automatically during the power flow shifting, because idc will only decrease under this critical condition and the operation state of the proposed SSCB will come back to Fig. 7.4➁. For the required dc biased current, the voltage of the biased power supply should be estimated according to the conducting resistance of the biased current flowing path, mainly including the conducting resistance of the dc reactor and the conducting resistances of the power electronic switches in the

7.4 Parameter Design and Hybrid Configuration for the Multi-terminal DC Grid Fig. 7.6 Equivalent circuit of the fault current clearing state and recovery state: a equivalent circuit of the fault current clearing state, b equivalent circuit of the recovery of the proposed SSCB

+

UA

169

Ll

-

+ idc

(a)

Udc - U + A

Ll

-

(b)

UA

iL/2

Lr

UA

iL/2

+

+

SSCB arms. But it may be hard to calculate the conducting resistances of the power electronic switches accurately in the practical engineering, which may change with different flowing current and temperature. Therefore, the influence of the variety of the switch resistance on the feeding biased current and corresponding improved biased power supply design method will be researched in the future work of the authors. (4) Arrester capacity: The capacity of the arrester, referring to the energy the arrester needs to absorb, should be selected when designing the proposed SSCB. According to the working principle, the arrester needs to dissipate the fault energy of the line during the fault current clearing state and part of the reactor energy (from I trip to I b ) during the recovery state. During the fault current clearing state, the fault energy in the dc line is dissipated by the connected arrester as shown in Fig. 7.6a, which can be mathematically equivalent to 2UA + 2L l

di dc = Udc . dt

(7.14)

Therefore, the dc line current idc can be expressed as i dc = Itrip −

UA − Udc /2 t. Ll

(7.15)

Based on (7.15), the energy absorbed by the arrester in one SSCB thus can be calculated as  WA1 = 0

Itrip ·L l UA −Udc /2



UA − Udc /2 UA · Itrip − t dt Ll

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7 DC Fault Current Limiting Technique Based …



Itrip ·Ll UA − Udc /2 2

t= UA −Udc /2 =UA · Itrip t − t

2L l t=0 UA 1 2 = L l Itrip 2 UA − Udc /2

(7.16)

In addition, according to Fig. 7.6b, the energy stored in the reactor should be dissipated to make iL decay from I trip (neglecting the decay of iL due to the conducting resistors of the devices in the SSCB) to I b . In Fig. 7.6b, the biased power supply is also neglected because its output voltage is very small compared with U A . Obviously, this part of energy is completely absorbed by the two arresters on Arm1 and Arm2 averagely. Therefore, the energy absorbed in each arrester can be calculated by WA2 =

1  2 L r Itrip − Ib2 . 4

(7.17)

Finally, the largest energy may be absorbed by one arrester W A = W A1 + W A2 , namely WA =

UA 1 1  2 2 L l Itrip + L r Itrip − Ib2 . 2 UA − Udc /2 4

(7.18)

According to (7.18), the capacity of the arrester thus can be selected.

7.4.2 Hybrid Configuration of the DCCBs in the Multi-terminal DC Grid The dc fault propagation in dc system is extremely fast, so it requires that the action speed of the protection and DCCB should be quick enough, e.g., 2–4 ms (including the action time of the protection and DCCB) [2, 3]. Therefore, the high-speed SSCBs should be installed widely in the dc system [12], including the converter output positions and each terminal of the dc lines. Obviously, it is not economical because the conducting power loss and investment will be very high. Installing dc reactors in the dc system can slow the fault propagation effectively, and thus lower the requirement on the action speed of the protection and DCCB. However, as analyzed in Sect. 7.1, the large dc reactors directly installed in the dc system have negative influences on the normal operation of the system and isolating speed of the DCCB, thus being not feasible. Differently, the proposed SSCB with self-adapt fault current limiting capability has no negative influences described above, so it has outstanding application prospect in the dc system. Furthermore, considering that the negative influences of the dc reactor have been avoided, large enough reactor can be installed in the proposed SSCB to limit the fault current thoroughly. In addition, according to the dc fault transient characteristic,

7.4 Parameter Design and Hybrid Configuration for the Multi-terminal DC Grid

171

the fault current is mainly provided by the converter capacitors [1]. Therefore, as long as the proposed SSCB is installed at each converter output position, the fault current of the whole dc system is limited effectively, wherever the dc fault position is. Under this condition, the other positions of the dc system, mainly referring to the dc line terminals, can be configured with the mechanical DCCBs to replace the SSCBs, because the fault current has been limited by the proposed SSCBs installed at the converter output positions and it is not necessary to isolate the fault very fast (e.g., 2–4 ms) anymore. According to the analysis above, the hybrid configuration strategy of the proposed SSCB and mechanical DCCB for the multi-terminal dc grid is proposed, i.e., installing the proposed SSCB at each converter output position and installing the mechanical DCCBs at the dc line terminals. Taking the radial dc system shown in Fig. 7.7a for instance, without the proposed SSCB, 26 typical SSCBs (positive and negative poles) should be installed. When the proposed SSCBs are installed at the converter output positions, the remaining 16 SSCBs on the dc lines can be replaced by the mechanical DCCBs. Considering that the conducting power loss and investment of the mechanical DCCB is much smaller than of the

(a)

converter proposed SSCB mechanical DCCB

(b) Fig. 7.7 The hybrid configuration idea of the proposed SSCB and mechanical DCCB in the multiterminal dc grid: a the radial dc system, b the meshed dc system

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7 DC Fault Current Limiting Technique Based …

SSCB, it is obvious that this hybrid configuration strategy can reduce economic cost significantly. With the system scale increasing, this advantage will become more evident. Such as the meshed dc system shown in Fig. 7.7b, 32 SSCBs can be replaced by the mechanical DCCBs.

7.4.3 Power Loss Analysis The conducting power loss of DCCBs is one of the key factors for engineering application, because it is directly related to the cost. Therefore, the power loss of installing the typical SSCBs is analyzed to be compared with that of the hybrid configuration strategy from the scale of the whole system, taking the dc voltage 1.5 kV, dc current 0.1 kA for instance. For the typical SSCBs, the clamping voltage U A of the arrester in each SSCB (installed on the positive and negative poles respectively) should be larger than 0.75 kV, to realize reliable fault isolation. Here, the Infineon IGBT FF200R12kS4 (1.2 and 0.2 kA rated) is selected for instance, and 2 IGBTs (bidirectional isolation) are needed for one SSCB. As shown in Fig. 7.8a, during normal operation, the current flows through one IGBT and one antiparallel diode. According to the datasheet of the FF200R12kS4, V CE at I = 0.1 kA is about 2.7 V, and V F at I = 0.1 kA is about 1.3 V, so the conducting power loss of one typical SSCB can be calculated as Ploss_ typical_ SSCB = 100 × 2.7 + 100 × 1.3 = 0.4 kW.

Fig. 7.8 Equivalent circuit for calculating the conducting power loss: a typical SSCB, b proposed SSCB

+

I

(a)

+

(b)

I

VF VCE

-

VCE

VF

(7.19)

-

-

+

Rr Lr

+ Ub +

+

VF

7.4 Parameter Design and Hybrid Configuration for the Multi-terminal DC Grid

173

For the proposed SSCB, the needed number of the IGBTs is the same with the typical SSCB. And according to Sect. 7.4.1, the needed number of the diodes is 4. I b is set as 0.1 kA. Under this condition, the current flowing path in the proposed SSCB is shown as Fig. 7.8b at the largest load current 0.1 kA. According to Fig. 7.8b, the conducting power loss of the proposed SSCB is composed of three parts, namely, the conducting loss of the power electronic switches, the conducting loss of the reactor and the conducting loss of the biased power supply. The method to calculate the conducting loss of the power electronic switches is the same as the typical SSCB. For the dc reactor conducting loss, the equivalent resistor of a 50 mH dc reactor produced by a manufacturer in China is about 0.0072 . In the 1.5 kV, 0.1 kA dc system, a 75 mH reactor in the proposed SSCB is enough (seeing the detailed system parameters in simulation), namely, with an equivalent resistor about 0.011 . So the corresponding conducting loss can be calculated as 100 A · 100 A · 0.011  = 0.11 kW. In addition, the dc biased power supply is generally also based on the power electronic switches, but it is obvious that the voltage rating of the switches in the biased power supply is much smaller than that of the switches in the SSCB arms. This means the conducting loss of the biased power supply is much smaller than that of the switches in the arms, and thus can be neglected. In conclusion, the conducting power loss of the proposed SSCB can be calculated as Ploss_ pro_ SSCB = 100 × 2.7 + 2 × 100 × 1.3 + 0.11 kW = 0.64 kW.

(7.20)

Due to the additional diodes and dc reactor, the conducting power loss of one proposed SSCB is a little larger than one typical SSCB. However, for the multiterminal dc grid, when the proposed SSCBs are installed at converter output positions, only the mechanical DCCBs are required to be installed at other positions, as described in the hybrid configuration strategy in Sect. 7.4.2. Differently, if the typical SSCBs are applied, they should be installed at each position in the system. Under this condition, the advantage of hybrid configuration strategy is highlighted, because power loss of the mechanical DCCB is extremely small (can be neglected). Taking the radial dc system shown in Fig. 7.7a for instance, the power losses of using typical SSCB and the hybrid configuration strategy are Ploss_ typical = 0.4 × 26 = 10.4 kW

(7.21)

Ploss_ hybrid = 0.64 × 10 = 6.4 kW

(7.22)

respectively. According to (7.21) and (7.22), 4 kW power is saved by the hybrid configuration strategy. With the system scale increasing, this advantage is more evident. For example, for the meshed dc system shown in Fig. 7.7b, the corresponding power losses are

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7 DC Fault Current Limiting Technique Based …

Ploss_ typical = 0.4 × 48 = 19.2 kW

(7.23)

Ploss_ hybrid = 0.64 × 16 = 10.24 kW.

(7.24)

According to (7.23) and (7.24), 8.96 kW power is saved.

7.5 Experiment Test 7.5.1 Test Setup The proposed SSCB is built according to the topology described above, and a scaleddown test circuit is also constructed as shown in Fig. 7.9, to verify the working principle and superiority of the proposed SSCB.

Fig. 7.9 Experiment test circuit

7.5 Experiment Test Table 7.1 Parameters of the experiment test circuit

175 Parameter

Value

Rated dc voltage (V)

200

Rated dc current (A)

10

Capacitor C (mF)

4.7

IGBT of the SSCB

FF200R12kS4

Diode of the SSCB

MD200A1600V

Arrester

MYG 20D241K

DC reactor L r (mH)

40

DC biased current (A)

15

Equivalent dc line resistor Rl ()

0.3

Equivalent dc line inductor L l (mH)

3

Figure 7.9 illustrates the proposed SSCB experiment test circuit, whose parameters have been listed in Table 7.1. Two series capacitors are connected with a rectifier in parallel to build up the desired voltage. The dc line is imitated by a resistor and a reactor. Particularly, the dc biased power supply is simply designed as an uncontrolled rectifier, and the required dc biased current can be obtained by regulating the input ac voltage of the rectifier. Obviously, this kind of dc biased power supply is very simple to be realized in the practical engineering. It should be noted that the IGBT and arrester of the typical SSCB in the comparative experiments are the same as the proposed SSCB. And considering that the largest energy absorbed by the arrester may be larger than the tolerated energy of one MYG 20D241K, so two MYG 20D241Ks are connected in parallel for the SSCBs in the experiment tests.

7.5.2 Test Results (1) Performance of the designed dc biased power supply: As shown in Fig. 7.9, the dc biased power supply in the proposed SSCB is designed as an uncontrolled rectifier, and the required dc biased current is obtained by regulating the input ac voltage. As the experiment results shown in Fig. 7.10, with a little dc voltage ( idc_peak × L l /(U re − U dc ). As shown in Fig. 8.3c, although the thyristors cannot be turned off directly after the gate signals are removed, the IGBTs are all turned off to connect the corresponding arresters into the flowing path of the dc reactor current. So the freewheeling current of the dc reactor is also eliminated as shown in Fig. 8.4a, which means the FCL is recovered. It should be pointed out that this stage happens after the dc fault has been isolated, and the freewheeling current during this period only flows in the FCL itself, thus leading to no additional influences on the system. (2) Power flow shifting condition: If the change of the dc line current is caused by the power flow shifting, obviously, no DCCB will be tripped. So no local DCCB tripping signal is received. The thyristors and IGBTs are turned on after the set time t 1 arrives. In the flexible dc grid, the power flow shifting mainly reflects in the fast change of the dc current. As shown in Fig. 8.5a, b, with the designed control strategy, the dc line current idc is commutated to the CCB, and the dc reactor is bypassed from the dc line, similar to the fault current clearing state under the dc fault condition shown as Fig. 8.3b. Therefore, idc can response quickly and be stable at the new value as shown in Fig. 8.4c, because the limiting effect of the reactor on the fast change of dc line current has been avoided. This means the negative influence of the directly installed dc reactor on the system transient response speed, and even on the operation stability [as shown in Fig. 8.4d], is avoided. Then t 3 after all the thyristors and IGBTs being turned on, the IGBTs TG1 – TGN are turned off alternately to connect the corresponding arrester in, as shown in Fig. 8.5c (TG1 off and others on, for example). Here, the setting of t 3 should guarantee that the main process of the dc current shifting has completed. As shown in Fig. 8.4c, the current flowing through the CCB, ic , will decrease due to the connectedin arrester. And the dc reactor current iL will gradually approach the dc line current value under the effect of reverse voltage from the arrester. During this period, there is always only one arrester connected in, to guarantee the negative influence on the system operation characteristics is tiny. When ic decreases to below a small enough set value I set , it can be considered that iL ≈ idc . This means the dc line current idc has been commutated back to the dc reactor branch completely. At this time, all the thyristors and IGBTs can be turned off. Thus the FCL recovers to the working state corresponding to dc grid normal stable operation. It should be noted that the external fault will also lead to the same condition as the power flow shifting, namely, the local DCCB being not tripped after |idc | exceeding iset . But according to the set principle of t 1 , under the external fault condition, the dc reactor in the FCL is always connected-in before the corresponding DCCBs

8.1 The Proposed FCL Based on Current Commutation Fig. 8.5 Working principle of the proposed FCL during power flow shifting condition: a quick response of idc (iL > idc ), b quick response of idc (iL < idc ), c FCL recovery state (iL > idc for instance)

189

idc

iL LF

iL-idc

TJ1 TJM ic=iL-idc TG1 TGN

(a) idc

iL LF

idc-iL TJ1 TJM ic=idc-iL TG1 TGN

(b) iL

idc

LF

(iL-idc)

TJ1 TJM

ic=(iL-idc)

TG1 TGN

turned off alternately (always only one IGBT is in off state

(c)

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8 DC Fault Current Limiting Technique Based …

are tripped. This means the FCL can also guarantee the needed fault current limiting function for the external fault with the proposed control strategy. According to the analysis above, the power electronic switches parallel-connected with the arresters should have the quick turned-on-controllable capability, to bypass the dc reactor quickly after the DCCB being tripped or after power flow shifting. But only a part of the switches are required to have the turned-off-controllable capability for dissipating the reactor energy during the FCL recovery state. Therefore, only this part of power electronic switches should be full-controlled. And for the remaining switches parallel-connected with the arrester, just half-controlled switches are required, to reduce the total investment (generally the half-controlled switch is cheaper than the full-controlled one). In addition, in the CCB of the proposed FCL, the H bridge composed of diodes is used to realize the bi-directional currentflowing function, replacing the anti-parallel structure of the half-controlled and fullcontrolled switches. It is also for the economy consideration, because the diode is much cheaper than the half-controlled and full-controlled switches.

8.1.3 The Control Strategy of the Proposed FCL According to the working principle described above, the control strategy of the proposed FCL can be designed as Fig. 8.6, where the detailed steps can be described as follows. (1) All the thyristors and IGBTs are in off state during dc grid normal stable operation. (2) Measure the dc line current, and compare the dc line current change value |idc | with the threshold value iset . (3) If |idc | > iset is satisfied, start the timer t from the zero moment. (4) If the local DCCB tripping signal is received in the delay time period t 1 , it indicates that the change of the dc line current is caused by the internal fault, and the corresponding DCCB has been tripped. Turn on all the thyristors and IGBTs as soon as the local DCCB tripping signal is received. Then remove all the gate signals of the thyristors and IGBTs after t 2 . (5) If no local DCCB tripping signal is received during the time period t 1 , it indicates that the change of the dc line current is caused by the power flow shifting. Turn on the thyristors and IGBTs until the set time t 1 arrives. Then after delay time t 3 , turn off the IGBTs TG1 –TGN alternately (always only one IGBT is in off state). Finally, when ic decreases to a small enough set value I set , remove all the gate signals of the thyristors and IGBTs. It should be noted that the DCCB will be the main dc fault isolating scheme in the future flexible dc grid. For example, the under-construction Zhangbei Flexible DC Grid Project in China will install DCCBs on both ends of each dc line. So the proposed FCL is designed mainly based on the DCCB application situation in the paper. However, the proposed FCL is also applicable for the dc system without

8.1 The Proposed FCL Based on Current Commutation

191

Fig. 8.6 Control strategy of the proposed FCL

DCCB. According to the existing dc fault isolating techniques, when no DCCB is installed on the dc line, the converter itself should have the dc fault current clearing capability, such as the full-bridge sub-module based MMC. Under this condition, the dc fault current is eliminated by blocking the MMC, and negatively inserting the sub-module capacitors. Therefore, to bypass the dc reactor during the fault current clearing period, the local MMC blocking signal can be used for the proposed FCL to identify the working status, replacing the local DCCB tripping signal. In sum, the proposed FCL has following advantages: (1) After dc faults, the dc reactor in the FCL is always connected in the fault circuit until the DCCB is tripped, so it has the same fault current limiting capability as the directly installed dc reactor. (2) The dc reactor is bypassed from the fault circuit quickly after the DCCB trips. Therefore, the dc fault isolating speed is increased significantly compared with that under the condition with the directly installed dc reactor, and the requirement on

192

8 DC Fault Current Limiting Technique Based …

the arrester capacity is reduced. (3) Under the power flow shifting condition, the dc reactor in the FCL can be bypassed quickly, thus avoiding the negative influence of the directly installed dc reactor on the system transient response speed and operation stability. It should be pointed out that, the typical dc FCL, HCLC [1], does not consider this problem. In addition, as discussed in Sect. 8.1.2, the hybrid design (the hybrid of the half-controlled unit and full-controlled unit) and H-bridge design are introduced to reduce the investment of the proposed FCL. However, for engineering application, the investment of the proposed FCL still cannot be neglected, so the research on the improved topology with similar performances but lower investment can be carried on further. But as analyzed, the proposed FCL has outstanding advantages for the safe and reliable operation of the flexible dc grid. And it is believed that this kind of FCL technique can promote the spreading and application of the flexible dc grid.

8.1.4 Parameter Design of the Proposed FCL For engineering application, the principle to calculate the parameters of the proposed FCL is discussed. (1) DC reactor: In the MMC-based dc grid, the main function of the dc reactor is to limit the fault current and prevent the MMC being blocked after dc faults, and finally to guarantee the reliable ride-through of the healthy network. For this destination, the method to calculate the required dc reactor value L F has been proposed in [3], where L F is determined by solving the equation  U0 I0 ω0 −σ ttrip  e e−σ ttrip sin ωttrip sin ωttrip − β + ω ω(L s + 2L F )    1 2 1 1 2 + − IdcN =3 k1 k2 9 9 M 2 cos2 ϕ 3 Mcosϕ

−

(8.3)

 where 1/(L s + 2L F )Cs − σ2 , ω0 = √ σ = Rs /2(L s + 2L F ) , ω = 1/ (L s + 2L F )Cs , β = arctan(ω/σ ), Cs = 6CSM /N , L s =2L arm /3, and Rs = 2Rarm /3. C SM is the MMC sub-module capacitance, L arm is the inductance of each arm reactor in the MMC, and Rarm is the equivalent resistance of each arm [3]. In addition, cosϕ is the power factor, M the modulation ratio, I dcN the rated dc current of the corresponding converter, I 0 the initial dc current, and U 0 the initial dc voltage. t trip is the time from the fault moment to the moment when the DCCB is tripped. k 1 is the overload coefficient, while k 2 is the security coefficient, where k 1 > 1 and k 2 > 1.

8.1 The Proposed FCL Based on Current Commutation

LF(mH)

400

300

193

CSM=9000μF CSM=13000μF CSM=17000μF

200 5

6

7

8 ttrip(ms) (a) required LF with different CSM

9

10

8 9 ttrip(ms) (b) required LF with different Larm

10

LF(mH)

400

300

Larm=32mH Larm=64mH Larm=96mH

200 5

6

7

Fig. 8.7 Calculation results of the required L F with variation of the DCCB tripping time: a with different sub-module capacitances C SM , b with different MMC arm reactors L arm

In (8.3), as long as the system parameters and the DCCB tripping time are given, the required dc reactor L F becomes the only unknown variable. In other words, for any dc grid, the required dc reactor L F can be calculated by (8.3) when the other parameters are given. Considering that (8.3) is a transcendental equation, the iterative algorithm based on the computer, e.g., the dichotomy algorithm, should be introduced to calculate the required dc reactor value L F . Figure 8.7 shows the calculated results of L F for a ±200 kV MMC with different t trip , C SM and L arm . To be specific, the power rating of the analyzed MMC is 800 MW, the modulation ratio is 0.816, the power factor is 1 and the sub-modules number in each arm is 100. Figure 8.7a shows the calculating results of the required reactor L F , with different t trip and C SM , while L arm is fixed (32 mH). According to the calculated results, the required reactor L F will increase with the DCCB tripping time t trip increasing. In another word, the larger L F is, the longer t trip can be. In addition, the sub-module capacitance C SM also has influence on L F . The required L F can be reduced by applying smaller sub-module capacitance. However, the influence is not very great. Moreover, the value of C SM should be determined according to the system parameters, such as the converter capacity, capacitor voltage fluctuation amplitude and so on. So it is not very feasible to reduce the required reactor value L F by adjusting the sub-module capacitance. In addition, larger arm reactor can lead to smaller required L F as shown in Fig. 8.7b. But for adequate system transmission capacity, the arm reactor cannot be too large, because it is a part of the connecting

194

8 DC Fault Current Limiting Technique Based …

reactance between the converter station and the interconnected ac system. Therefore, in summary, large enough dc reactors on dc lines are necessary in the dc grid for fault current limitation, to create enough acting time for the protection and DCCB after dc faults. As shown in Fig. 8.7, the required reactor is quite large, so the power loss of the reactor during normal operation should be considered. The equivalent resistance of a 50 mH dc reactor produced by a Chinese manufacturer is about 0.007 . Based on the proportional calculation, the equivalent resistance of a 355 mH dc reactor can be estimated as 0.05 . So its power loss in the ±200 kV, 800 MW dc system can be calculated as 0.2 MW. According to [4], the efficiency of the MMC is about 99%. That is to say, the MMC power loss caused by the power electronic switches is about 1%. Compared with the MMC operation power loss, the loss on the dc reactor (0.2/800 = 0.025%) is slight. And the efficiency of the system with dc reactor can still keep near 99% (the power loss is still mainly caused by the power electronic switches in the converter). In addition, to produce large enough inductance, the iron core may be required. And the inductance value may reduce under large current condition due to the saturation of the iron core, which still needs further research. (2) Arresters: In the engineering field, the ZnO arrester is widely used. Its V-I characteristic curve can be approximated as Fig. 8.8, which is divided into three areas, namely, the small current area, the voltage-limiting area and the overload area. In the small current area, the equivalent resistance of the ZnO arrester is extremely large, and the leakage current on the arrester is very small. So it is expected that the arrester can stay in this area during system normal operation. With the voltage on the arrester increasing to exceed the action value U ac , the arrester enters the voltagelimiting area. In this area, the arrester shows a highly nonlinear characteristic, and the flowing-through current is very sensitive to the voltage, which means the current will increase significantly even if the increase of the voltage is tiny. This characteristic makes the ZnO arrester can be used to dissipate the additional energy of the reactor in the proposed FCL, with a limited voltage. With the voltage increasing further, the arrester will get into the overload area, where the voltage-limiting function is degraded, and thus this area should be avoided in the practical application. Fig. 8.8 V-I characteristic curve of the ZnO arrester

U small current area

voltage-limiting area

overload area

Uac

Iac

I

8.1 The Proposed FCL Based on Current Commutation

195

According to the V-I characteristic curve, two parameters of the arrester should be concerned when designing the FCL, namely the action voltage U ac and the capacity. Generally, the action voltage U ac of the arrester is defined as the critical point between the small current area and the voltage-limiting area. Obviously, if U ac is very small, the arrester will be very easy to get into the voltage-limiting area after dc faults. Considering that the equivalent resistance of the arrester in the voltage-limiting area is much smaller than that in the small current area, the fault-current-limiting impedance of the proposed FCL is reduced undesirably, and thus the fault current limiting capability is reduced under this condition. In another word, U ac of the arrester in the FCL should be large enough for required fault current limiting capability. In this paper, U ac is suggested to be larger than the maximum voltage which may occur on the dc reactor after dc faults. According to [3], U ac should satisfy Uac ≥ k3 L F /(L s + 2L F ) · [(I0 /Cs ω) · sin(−2β) + U0 ]

(8.4)

where k 3 is a reliability coefficient, and k 3 > 1. In fact, the right part of (8.4) calculates the largest voltage value occurring on the dc reactor [3]. As analyzed in [3], the largest voltage on the dc reactor occurs when the metallic fault happens at the location close to the FCL, because the dc fault current flowing through the reactor rises fastest. Under this condition, the largest voltage on the reactor can be calculated as L F · didc /dt|t=0 = L F /(L s + 2L F ) · [(I 0 /C s ω) · sin(−2β) + U 0 ], when the fault line only connects with the converter. However, in the flexible dc grid, the dc lines may connect with each other via dc bus, which means the FCL suffers not only from the fault current fed by the nearest converter. The remote converters also feed fault current to the fault point through interconnected lines. It means the rate of change of the fault current through the reactor may be larger, causing the actual voltage on the dc reactor to be larger. For this reason, the reliability coefficient k 3 , bigger than 1, is introduced in (8.4) to estimate the largest voltage on the reactor. Of course, it is obvious that the fault current is mainly fed by the nearest converter, so the reliability coefficient k 3 does not need to be very large (1.2 in [3]). After dc fault isolation, the FCL itself should recover, preparing for the next fault. As shown in Fig. 8.3c, the fault energy of the dc reactor is dissipated by the arresters paralleled with the IGBTs. It can be equivalent to L F · di L /dt + kRVR_ G · Uac_ G = 0

(8.5)

where U ac_G is the total action voltage of the arresters on all the IGBTs. During the FCL recovery state, the current flowing through the arresters is much larger than the current corresponding to the critical point between the small current area and the voltage-limiting area. So the arresters voltage will be larger than U ac_G according to Fig. 8.8. In engineering practice, the arrester voltage when inrush current flows through the arrester is defined as the residual voltage. So in (8.5), the residual voltage k RVR_G · U ac_G is used to reflect the arresters voltage during this state, where k RVR_G is the arrester residual voltage ratio defined as the ratio of the residual voltage to

196

8 DC Fault Current Limiting Technique Based …

the action voltage. Generally, k RVR_G depends on the material composition of the selected arrester, which can be provided by the manufacturer. Supposing that the initial time of the dissipation process is the zero moment. According to (8.5), the current iL can be expressed as   i L = i L_ trip − kRVR_ G · Uac_ G /L F · t.

(8.6)

Therefore, the freewheeling current clearing time t clear can be expressed as L F · iL_trip /k RVR_G · U ac_G , where iL_trip is the dc reactor current at the moment the corresponding DCCB is tripped, and obviously iL_trip can be calculated by the left part of (8.3). Generally, this process should finish before the DCCB reclosure (in the case of nonpermanent fault). In other words, t clear should be smaller than the set value t clear_min , so U ac_G should satisfy     Uac_ G ≥ L F · i L_ trip / kRVR_ G · tclear_ min .

(8.7)

In the engineering practice, hundred-milliseconds-level delay time after clearing the fault current is needed for the recovery of the fault line itself. Only after that, the DCCB is allowed to be reclosed. Therefore, t clear_min just needs to be smaller than this delay time. Based on (8.4) and (8.7), the action voltage of the arrester on the thyristors is also determined. In addition, for the capacity selection, the largest energy may be absorbed by the arresters on the IGBTs needs to be calculated. Two conditions should be considered, namely, the FCL recovery after fault isolation, and the FCL recovery after power flow shifting, respectively as shown in Figs. 8.3c and 8.5c. According to (8.6), the absorbed energy during the former condition can be calculated as  tclear kRVR_ G Uac_ G 2 kRVR_ G Uac_ G · i L_ trip − t dt = L F i L_ E1 = trip /2. LF

(8.8)

0

Similarly, the maximum absorbed energy during the FCL recovery after power flow shifting can be calculated as 2 . E 2 = 2L F IdcN

(8.9)

Finally, the total capacity of the arresters on the IGBTs can be selected as the larger one of E 1 and E 2 . Then for each arrester, the capacity is averagely allocated. Differently, the arrester on the thyristors does not need to absorb large energy, thus the required capacity is not large. (3) The power electronic switches: For the power electronic switches, namely, the thyristors, IGBTs and diodes, the rated current and voltage are the key parameters. According to the working principle, the

8.1 The Proposed FCL Based on Current Commutation

197

largest current which may flow through the switches can be estimated based on the dc fault current at the DCCB tripping moment. Therefore, the rated current of the thyristors, IGBTs, and the diodes, can all be determined as Ir = −

 I0 ω0 −σ ttrip  U0 e e−σ ttrip sin ωttrip sin ωttrip − β + ω ω(L s + 2L F )

(8.10)

Differently, the largest voltages on the thyristors and IGBTs are limited by the corresponding arresters, while each diode arm of the H bridge needs to bear the residual voltage sum of all the arresters, so the rated voltages should be respectively determined as   ⎧ ⎪ ⎨ Ur_ J = kRVR_ J Uac − Uac_ G /M Ur_ G = kRVR_ G · Uac_ G /N (8.11) ⎪     ⎩ Ur_ D = kRVR_ J Uac − Uac_ G + kRVR_ G · Uac_ G /K where k RVR_J is the residual voltage ratio of the arrester on the thyristors, and M, N, K are the series-connected numbers of the thyristors, IGBTs and each arm diodes.

8.2 Experiment Test In this section, a scaled-down experiment test platform, as shown in Fig. 8.9, is built to verify the working principle and advantage of the proposed FCL. The detailed parameters of the experiment test circuit are listed in Table 8.1. As shown in Fig. 8.9, the dc power supply is constructed by an uncontrolled rectifier connected in parallel with two series capacitors. And the required dc voltage 200 V can be built by adjusting the output voltage of the adjustable transformer. The dc line is imitated by a resistor and an inductor. For the FCL and DCCB in the test circuit, the IGBT FF200R12KS4 (200 A, 1200 V) and thyristor SKET 400/16E (400 A, 1600 V) are used, for the enough safety margin consideration. The dc fault and load change conditions with different FCLs are tested respectively, where the fault point is imitated by an IGBT, and the load change is realized by changing the load resistance Rload . In order to reduce the experiment complexity, the solid-state DCCB is used in the experiment test. The working principles of other kinds of DCCBs, including the hybrid DCCB and the mechanical DCCB, are different from the solid-state DCCB. For the hybrid DCCB, there is an additional bypass current path parallel-connected with the main breaker branch. And the current commutation from the bypass current path to the main breaker branch will be carried out before the fault current clearing. But this current commutation happens in the DCCB itself, thus having no influence on the performance of the proposed FCL. In addition, for the mechanical DCCB, the arc extinguishing process based on the LC oscillation is the main difference compared with the solid-state DCCB and hybrid DCCB (the open of the hybrid DCCB does

198

8 DC Fault Current Limiting Technique Based …

Fig. 8.9 Experiment test circuit

Table 8.1 Parameters of the experiment test circuit U dc (V) C (μF) L F (mH) L l (mH) Rl () Rload () IGBT 200

4700

40

3

0.3

20

Thyristor Arrester

FF200R12KS4 SKET 400/16E

MYG 20D241K (for the DCCB) MYG 20D390K (for the IGBTs in FCL) MYG 20D201K (for the thyristors in FCL)

also not produce the arc). However, the oscillation process happens between the LC oscillation branch and the mechanical switch in the mechanical DCCB. It means the oscillation current for arc extinguishing only flows in the DCCB, thus also having no influence on the performance of the proposed FCL. Therefore, the test results based on the solid-state DCCB are also valid to the cases with other DCCBs.

8.2 Experiment Test

199

(b) uA_DCCB(V)

(a) idc(A)

80 60

[10ms/div] 74A

40 20 0 400 300 200 100 0 -20

-10

0

10

20

30

40

50

60

70

80

Time (ms)

Fig. 8.10 Experiment result of the dc pole-to-pole fault without any FCL: a dc current idc (A), b DCCB arrester voltage uA_DCCB (V)

8.2.1 DC Fault Without Fault Current Limitation In this case, the dc pole-to-pole fault is set to happen at t = 0 s with no fault current limiting method applied. Meanwhile, the DCCB is set to be tripped 1 ms after the fault. The corresponding experiment result is shown in Fig. 8.10. Obviously, the dc current idc increases extremely fast (from the normal operation load current 10 A to about 74 A in 1 ms). This means that, in the practical engineering, it requires the dc protection and DCCB can identify and isolate the fault very fast. However, the existing dc protection and DCCB acting speed, especially the former, still cannot match the dc fault propagation speed, so it is necessary to use effective FCL in the flexible dc grid.

8.2.2 DC Fault with DC Reactor Directly Installed In this case, a 40 mH dc reactor is directly installed in the experiment test circuit. Similarly, the dc pole-to-pole fault is set to happen at t = 0 s. But the DCCB is set to be tripped 10 ms after the fault. The corresponding experiment result is shown in Fig. 8.11. As Fig. 8.11a showing, the dc fault current is limited significantly by the installed dc reactor. Although the DCCB tripping time is delayed to 10 ms after the fault, the dc current is much smaller compared with that under the condition without any FCL. It indicates that the dc reactor has a good fault current limiting capability. However, also as shown in Fig. 8.11, the DCCB needs about 20 ms to clear the fault current after being tripped. It is much longer than the fault current clearing time under the condition without any FCL (in 1 ms). This is because the DCCB arrester needs to dissipate the energy stored in the dc reactor additionally, which is much larger than that in the dc line. Moreover, according to the dc current and arrester voltage shown in Fig. 8.11a, b, supposing that the start moment of the fault current

200

8 DC Fault Current Limiting Technique Based …

(b) uA_DCCB(V)

(a) idc(A)

80 60

10ms

20ms

[10ms/div]

40 41A

20 0 400 300 200 100 0 -20

-10

0

10

20

30

40

50

60

70

80

Time (ms)

Fig. 8.11 Experiment result of the dc pole-to-pole fault with dc reactor: a dc current idc (A), b DCCB arrester voltage uA_DCCB (V)

clearing period is zero moment, the energy absorbed by the DCCB arrester during this period can be calculated as tclear 

E DCCB =

 u A_ DCCB − Udc u A_ DCCB · Iinitial − t dt LF

tclear 

u A_ DCCB · i dc dt = 0

0

 Iinitial u A_ DCCB · Iinitial − t dt tclear

tclear 

=



0

 41 t dt = 125 J 305 · 41 − 0.02

0.02 =

(8.12)

0

where uA_DCCB is the DCCB arrester voltage, idc the dc current, and I initial is the initial current of this period. Obviously, it is much larger than that under the condition without any FCL (only about 7 J), which means the required arrester capacity is drastically increased with the dc reactor being directly installed.

8.2.3 DC Fault with the Proposed FCL In this case, the proposed FCL is installed to replace the directly installed reactor, and the dc pole-to-pole fault is set to happen at t = 0 s. The results with different DCCB tripping times are observed to show the fault current limiting capability of the proposed FCL. As shown in Fig. 8.12, if the DCCB tripping time t trip = 1 ms (the same as the condition without FCL), the fault current peak value is limited to 15 A by the proposed FCL, which is much smaller than that under the condition without FCL. It verifies that the maximum current breaking capacity of the DCCB can be reduced

8.2 Experiment Test

201

(b) uA_DCCB(V)

(a) idc(A)

40 30

[5ms/div]

1ms 15A

20 10 0 400 200 0 -100 -10

0

10

20

30

40

Time (ms)

Fig. 8.12 Experiment result of the dc pole-to-pole fault with the proposed FCL (t trip = 1 ms): a dc current idc (A), b DCCB arrester voltage uA_DCCB (V)

(a) idc(A)

significantly when the proposed FCL is installed. Differently, Fig. 8.13 shows the function of the FCL on optimizing another DCCB index, namely the DCCB acting speed. As Fig. 8.13 showing, when t trip is delayed to 15 ms after the fault, although the DCCB needs to interrupt a 53 A dc fault current (still smaller than 74 A under the condition without FCL), more time is created for the dc protection and DCCB. This means the requirement on the DCCB acting speed, as well as the dc protection acting speed, can be decreased. In the engineering application, the maximum current breaking capacity and the tripping time (acting speed) of the DCCB should be considered comprehensively. For example, in the case shown as Fig. 8.14, the DCCB tripping time t trip is set as 10 ms. In this case, the fault current peak value is limited to a certain extent by the FCL, so the maximum current breaking capacity of the DCCB can be reduced. Meanwhile, the DCCB tripping time can also be longer than that under the condition without 80 60

15ms

40

[5ms/div] 53A

20

(b) uA_DCCB(V)

0 400 200 0 -100 -10

0

10

20

30

40

Time (ms)

Fig. 8.13 Experiment result of the dc pole-to-pole fault with the proposed FCL (t trip = 15 ms): a dc current idc (A), b DCCB arrester voltage uA_DCCB (V)

202

8 DC Fault Current Limiting Technique Based …

(a) idc(A)

80 60

1ms

10ms

[10ms/div]

40 45A

20 0

(b) ic(A)

80 60 40 20 0

(c) iL(A)

80 60 40 20

(d) iA_DCCB(A)

0 80 60 40 20 0

(e) uA_FCL(V)

100

0

(f) uA_DCCB(V)

-100 400 200

0 -100

-20

-10

0

10

20

30

40

50

60

70

80

Time (ms)

Fig. 8.14 Experiment result of the dc pole-to-pole fault with the proposed FCL (t trip = 10 ms): a dc current idc (A), b the current flowing through the CCB of the proposed FCL ic (A), c the current flowing through the reactor in the FCL iL (A), d the current flowing through the DCCB arrester iA_DCCB (A), e the voltage of the arrester on the IGBT of the FCL uA_FCL (V), f DCCB arrester voltage uA_DCCB (V)

FCL, which means the requirement on the dc protection and DCCB acting speed is decreased. The above experiment test results verify that the proposed FCL has a strong dc fault current limiting capability like the directly installed reactor. But as the experiment result in Sect. 8.2.2 showing, the directly installed reactor will result in a longer fault current clearing time (about 20 ms). Differently, with the proposed FCL being installed, the fault current can be cleared very quickly (about 1 ms) after the DCCB

8.2 Experiment Test

203

is tripped, which is very close to the condition without any FCL, and much faster than that under the condition with dc reactor directly installed. This is because the reactor current is commutated to the CCB during the fault current clearing period, as shown in Fig. 8.14b, c. What is more, the energy absorbed by the DCCB arrester is only about 8 J [the calculation method is similar to (12)] when the proposed FCL is installed. Even if the energy absorbed by the arrester in the FCL during its recovery state is also considered (40 J), the sum energy 48 J is much smaller than 125 J (under the condition with dc reactor directly installed). The above experiment results verify that the proposed FCL can limit the dc fault current effectively, decreasing the requirement on the DCCB maximum current breaking capacity, as well as the requirement on the dc protection and DCCB acting speed. In addition, with the proposed FCL being installed, the dc fault current clearing speed is much faster, and the DCCB arrester capacity can be much smaller, compared with the condition that the dc reactor is directly installed.

8.2.4 Power Flow Shifting with Different FCLs In this case, the load resistance is changed from 40 to 20  at t = 0 s, to create a load change condition where the load current changes from 5 to 10 A. The performances of the dc current without FCL, with dc reactor directly installed and with the proposed FCL, are observed respectively as shown in Fig. 8.15. As Fig. 8.15a showing, when no FCL is installed, the load current can change from 5 to 10 A very quickly (in 1 ms). But if the dc reactor is directly installed in the circuit, the dc current needs about 10 ms to change from 5 A to the new load current value 10 A as shown in Fig. 8.15b, because the reactor will limit the current changing speed. Differently, as Fig. 8.15c showing, the dc current can change from 5 to 10 A quickly (in 1 ms) under the condition with the proposed FCL being installed, similar to the condition without FCL. This is because the reactor in the FCL can be bypassed quickly to avoid the negative influence on the dc current changing speed. As we know, the fast response characteristic during power flow shifting is one of the main advantages of the flexible dc grid. The above experiment results indicate that the dc reactor will slow down the dc current changing speed during load change condition. And the proposed FCL can avoid this negative influence of the reactor. In the flexible dc grid, this advantage can improve the system transient response speed and operation stability after power flow shifting. Considering that the investment is too high to build a flexible dc grid platform for the experiment test, the further comparison and verification for the influence of different FCLs on the system operation stability are carried out based on the simulation platform (PSCAD/EMTDC).

204

8 DC Fault Current Limiting Technique Based …

idc(A)

20 15

[2ms/div]

1ms

10 5 0 -5

(a)

idc(A)

20 15 10 5 0 -5

(b)

20 15

idc(A)

[2ms/div]

10ms

[2ms/div]

1ms

10 5 0 -5

-6

-4

-2

0

2

4

6

8

10

12

14

Time (ms) (c)

Fig. 8.15 Experiment result of the load change condition with different FCLs: a without FCL, b with dc reactor directly installed, c with the proposed FCL

8.3 Simulation Case Study In Sect. 8.2, the effective dc fault current limiting capability of the proposed FCL has been verified by the experiment tests, and its advantage on cooperation with the DCCB (accelerating the dc fault current clearing, reducing the DCCB arrester capacity) is also proved. To further verify its superiorities for application in the flexible dc grid, an MMC-based three-terminal meshed dc grid shown as Fig. 8.16 is built on the PSCAD/EMTDC. The corresponding parameters are listed in Table 8.2. In the simulation model, the dc fault and power flow shifting are set to happen respectively, and the performance of the proposed FCL is observed.

8.3.1 DC Fault Overcurrent In this case, no FCL is installed in the system, and the dc pole-to-pole fault f 1 is set to happen at t = 2.2 s. Moreover, the DCCBs are not tripped, so the overcurrent condition can be displayed better. As the simulation result in Fig. 8.17 showing, the dc current and arm currents all increase extremely fast after the fault. In practical engineering, the MMC will be blocked undesirably and quickly due to the IGBT selfprotection, because the arm currents exceed the threshold value 4 kA very quickly

8.3 Simulation Case Study

205 B21 F21

F12 B12 idc of Line1 idc of S1 udc of S1 iarm of S1

S2

SMN

SMN

SM1

SM1

SM1

SM1

SM1

SM1

SMN

SMN

SMN

uJ

uG

Line3

idc

iarm

uD3

Line1

S1

SMN

uD1

f1

Line2

udc

S3

idc of S3 udc of S3 iarm of S3

DCCB

uD2

uD1

uD4

uD3

ideal condition

uJ

uG

FCL

uD2

uD4

with stray inductance

Fig. 8.16 Topology of the MMC-based three-terminal meshed dc grid Table 8.2 Parameters of the MMC-based three-terminal meshed dc grid

Parameter

Value

Rated dc voltage (kV)

±200

Rated ac voltage (kV)

200

Rated capacity of S1 –S3 (MW)

800, 400, 400

Number of SMs per arm

100

SM capacitors of S1 –S3 (μF)

13,000, 9750, 9750

Arm reactors of S1 –S3 (mH)

32, 64, 64

Resistance of the dc lines (ohm/km)

0.032

Inductance of the dc lines (mH/km)

1.29

Length of the dc lines (km)

100, 100, 150

206

8 DC Fault Current Limiting Technique Based …

(a) idc(kA)

60 40 20 0 2.2

Time (s)

2.3

2.4

10

(b) iarm(kA)

30

4 0 2.199

20

2.2

2.201

10 0 2.2

2.3

2.4

Time (s)

Fig. 8.17 Simulation result of the dc pole-to-pole fault without FCL: a dc current idc of Line1 (kA), b arm currents iarm of S1 (kA)

(in 1 ms) [3]. It means the ride-through of healthy network cannot be achieved. Therefore, the effective FCL is necessary for the flexible dc grid.

8.3.2 Healthy Network Ride-Through After DC Fault with the Proposed FCL (1) Performance of the dc grid with the proposed FCL: In this case, the proposed FCLs are installed on each terminal of the dc lines. The dc pole-to-pole fault f 1 is still set to happen at t = 2.2 s. And the DCCBs on Line1 (B12 and B21 ) are set to be tripped 10 ms after the fault, namely, t trip is 10 ms. In addition, k 1 , k 2 , k 3 and t clear_min are set as 2, 1.5, 1.2 and 80 ms respectively, so the parameters of the proposed FCL can be determined according to the method in Sect. 8.1.4. The corresponding simulation result is shown in Fig. 8.18. As Fig. 8.18a, b showing, although the system has to suffer the fault for 10 ms, the fault currents are limited effectively during this period. Especially, the arm currents iarm of S1 , which is the nearest to the fault point, are limited below the upper limit value (4 kA). This means the converter can continuously operate during the fault. As Fig. 8.18c showing, the dropping of the dc voltage udc after the fault is not very serious due to the fault current limiting function of the proposed FCL, and it can recover to the rated value quickly after the fault is isolated. Similarly as Fig. 8.18d showing, the active and reactive powers of each converter can recover to the reference value quickly from a disturbance caused by the fault. The above results indicate that the healthy network can ride through the fault successfully with the proposed FCL being installed. In

(b) iarm(kA)

(a) idc(kA)

8.3 Simulation Case Study 6 5 4 3 2 1 0 -1

207 6

0 2.2

2.21 2.212 2.22

2

2.2

2.4

2.6

2.8

2

2.2

2.4

2.6

2.8

2

2.2

2.4

2.6

2.8

(c) udc(kV)

3.4

3.6

3.8

4

3

3.2

3.4

3.6

3.8

4

3

3.2

3.4

3.6

3.8

4

3

3.2

3.4

3.6

3.8

4

3.2

3.4

3.6

3.8

4

1 0 -1

Time (s)

400 300 200 100 0

(d) P and Q (p.u.)

3.2

2

500

(e) iL(kA)

3

Time (s)

P of S3

1

Q of S2 0 -1 6 5 4 3 2 1 0 -1

Time (s)

Q of S3

P of S2 2

2.2

2.4

2.6

2.8

Time (s)

6

0

2

2.2

2.4

2.2 2.22

2.6

2.3

2.8

3

Time (s) Fig. 8.18 Simulation result after the dc fault with proposed FCL: a dc current idc of Line1 (kA), b arm currents iarm of S1 (kA), c dc voltage udc at S1 (kV), d active and reactive power (p.u.), e reactor current iL in the FCL (kA)

208

8 DC Fault Current Limiting Technique Based …

addition, as Fig. 8.18e showing, after the fault is isolated, the freewheeling current iL of the dc reactor can be eliminated within the set time period (80 ms), which means the proposed FCL can recover in time for handling the next fault. (2) Influence of the MMC parameters on fault current: The influence of the MMC parameters, mainly including the sub-module capacitance and arm reactor, on the fault current is discussed based on simulation cases. As shown in Fig. 8.19a, with the MMC sub-module capacitance C SM reducing, the dc fault current peak value decreases. On the contrary, the dc fault current peak value decreases with the MMC arm reactor L arm increasing. This means the fault current can be decreased by applying smaller sub-module capacitance or larger arm reactor, and then the requirement on the dc FCL can be reduced. But it should be noted that, although C SM and L arm have influence on the dc fault current, this influence is not very great. Moreover, as mentioned in Sect. 8.1.4, both C SM and L arm should be selected within a reasonable range, for the effective operation of the system. Therefore, it is not feasible to limit the fault current by adjusting the converter parameters, and the most ideal method is still installing dc FCL with enough fault current limiting capability. 6 5.3

(a) dc current with different CSM (kA)

5

CSM=17000μF CSM=13000μF

4 5

3 2

4.8 2.2094

CSM=9000μF 2.21

2.2104

1 0 -1

2.2

2.21

2.22 Time (s)

2.23

2.24

2.23

2.24

6 (b) dc current with different Larm (kA)

5

Larm=32mH Larm=64mH

4

Larm=96mH

3 2 1 0 -1

2.2

2.21

2.22 Time (s)

Fig. 8.19 Simulation result after the dc fault with different C SM and L arm : a with different C SM , b with different L arm

8.3 Simulation Case Study

209

8.3.3 Power Flow Shifting with Different Fault Current Limiting Methods In this case, the active power reference value of station S3 is set to change from 1 p.u. to −1 p.u. at t = 2.2 s. The performances of the dc grid with dc reactors directly installed, with HCLCs, and with proposed FCLs are simulated respectively, as shown in Figs. 8.20 and 8.21. As Fig. 8.20 showing, when the dc reactors are directly installed, the dc voltage udc , dc current idc and arm currents iarm all oscillate after the power flow shifting. It verifies that the directly installed dc reactors deteriorate the dc grid transient response capability, and then the system stability. Figure 8.20 also shows the simulation result under the condition with HCLC. It means the HCLC also cannot avoid the negative influence of the dc reactor on system transient response speed and operation stability. Because when the HCLC is designed in [1], this problem is not considered, and no measures will be taken after power flow shifting, to avoid the negative influence of the reactor.

(a) udc(kV)

450 400 350 300

2

2.2

2.4

2.6

2.8

3 3.2 Time (s)

3.4

3.6

3.8

4

2

2.2

2.4

2.6

2.8

3 3.2 Time (s)

3.4

3.6

3.8

4

2

2.2

2.4

2.6

2.8

3 3.2 Time (s)

3.4

3.6

3.8

4

(b) idc(kA)

2 1 0 -1 -2

(c) iarm(kA)

2 1 0 -1 -2

Fig. 8.20 Simulation result after power flow shifting with directly installed dc reactors or with HCLCs: dc voltage udc at S3 (kV), b dc current idc of S3 (kA), c arm currents iarm of S3 (kA)

210

8 DC Fault Current Limiting Technique Based …

(a) udc(kV)

400 300 200 100 0

2

2.2

2.4

2.6

2.8

3 3.2 Time (s)

3.4

3.6

3.8

4

2

2.2

2.4

2.6

2.8

3 3.2 Time (s)

3.4

3.6

3.8

4

2

2.2

2.4

2.6

2.8

3 3.2 Time (s) t4

3.4

3.6

3.8

4

3.4

3.6

3.8

4

(b) idc(kA)

2 1 0 -1 -2

(c) iarm(kA)

2 1 0 -1 -2

t1 t2

(d) currents in the FCL (kA)

2

Δt3

t3 ic

1

iL

0 -1 -2

idc 2

2.2

2.4

2.6

2.8

3

3.2

Time (s)

Fig. 8.21 Simulation result after power flow shifting with the proposed FCLs: a dc voltage udc at S3 (kV), b dc current idc of S3 (kA), c arm currents iarm of S3 (kA), d the currents in the FCL (kA)

Figure 8.21 shows the performance of the dc grid with proposed FCLs. As Fig. 8.21a–c showing, the dc voltage, dc current and arm currents can all transit to a new stable state. Compared with the conditions with dc reactors directly installed or with HCLCs, the dc grid transient response speed and operation stability are improved significantly. Figure 8.21d shows the working principle of the proposed FCL during power flow shifting. As long as the power flow shifting state is identified, the IGBTs and thyristors will all be turned on instantaneously (at t 2 ). Then the dc reactor current iL only circulates between the dc reactor and the CCB in the FCL. And the dc line current idc only flows through the CCB. Consequently, idc can trace the new reference

8.3 Simulation Case Study

211

value quickly, without the obstruction from the dc reactor. After the delay time t 3 (200 ms in the simulation), the drastic shifting process of the dc current has almost done, so the current ic on the CCB could begin to be commutated back to the dc reactor branch by turning off the IGBT to connect the arrester in. It should be noted that only a small part of the arresters is connected in during this period, so the influence on the system is very small. Finally, all the IGBTs and thyristors can be turned off when ic is commutated to the dc reactor branch completely. This means the proposed FCL is recovered.

8.3.4 Practical Application Discussion (1) Withstanding voltage: For practical engineering application, the withstanding voltage of the devices in the FCL is the key parameter, because it determines the series-connected devices number, namely, the investment. According to (8.4) and (8.7), the action voltages of the arresters on the half-controlled unit (thyristors branch) and full-controlled unit (IGBTs branch) in the FCL for S1 can be calculated as 211.8 kV (U ac_J ) and 20.4 kV (U ac_G ) respectively. Supposing that the rated voltages of the thyristors, IGBTs and diodes are all 3.3 kV, according to (8.11), the seriesconnected numbers of the thyristors branch, IGBTs branch and the diodes branch (per arm) can be calculated as 100, 10 and 109 respectively (the residual voltage ratios of the arresters used in the simulation model are all 1.545). Figure 8.22b, c show the voltages exerted on the thyristors branch, IGBTs branch and diodes branches (for the diodes branches, only uD1 and uD2 are displayed because uD4 is the same as uD1 and uD3 is the same as uD2 ) after the dc pole-to-pole fault f 1 . As the simulation results showing, the exerted voltages all do not exceed the voltage withstanding capability of the selected power electronic switches. It verifies the feasibility of the proposed parameter design principle. The simulation results also indicate that, in the FCL, the voltage on the IGBTs branch is much smaller than those on the thyristors branch and diodes branches. It means the needed number of the IGBTs is much smaller than that of the thyristors and diodes. The price of the thyristor and diode is much lower than that of the IGBT. Therefore, the hybrid design (the hybrid of the half-controlled unit and full-controlled unit) and H-bridge design for the proposed FCL can reduce the investment effectively, which improve the practical applicability of the proposed FCL in engineering. (2) Influence of the stray inductance: For high voltage application, a large number of devices need to be connected in series, thus leading to considerable stray inductances. Therefore, in this case, the influence of the stray inductance on the performance of the proposed FCL is discussed. In the above cases, the stray inductance is neglected, namely the ideal condition. In this case, the stray inductance is added for each branch in the FCL as shown in Fig. 8.16. According to [5], the stray inductance of a commercially available ABB 3.3 kV/1.5 kA IGBT module is about 170 nH. The stray inductances of the diode, thyristor and arrester are similar under the same

8 DC Fault Current Limiting Technique Based … with stray inductance no stray inductance

212 5 4 3 2 1 0

iL ic idc 2.2725

2.2114

5 4 3 2 1 0 2.19

iL ic idc

2.2

2.21

2.22

2.23

2.24

2.25

2.26

(b) voltages on the thyristors and IGBTs(kV)

(a) currents in the FCL(kA) 200 150

uJ uG

100

uJ uG

50 0 -50

2.2

2.22

2.24

2.26

2.28

2.2

no stray inductance

(c) voltages on the diodes(kV)

2.27 2.28 Time (s)

2.22 2.24 2.26 2.28 with stray inductance

200 150

uD2 uD1

100

uD2 uD1

50 0 -50

2.2

2.22

2.24

2.26

no stray inductance

2.28

2.2

2.22

2.24

2.26

2.28

with stray inductance

Fig. 8.22 Internal observation of the proposed FCL: a currents in the FCL (kA), b voltages on the thyristors branch (uJ ) and IGBTs branch (uG ) (kV), c voltages on the diodes branches (kV)

rating, because the stray inductances are mainly caused by the connecting bus bar, component lead and so on, which are similar under the same rating. Therefore, the stray inductance value of the IGBT module is also used to estimate the stray inductances of other components. According to (8.3), the maximum current that may flow through the FCL is about 7.1 kA. Taking the half-controlled unit for instance, 100 thyristors (also with the rating of 3.3 kV/1.5 kA) need to be connected in series for the required voltage withstanding capability as analyzed in Sect. 8.3.4. Then 5 such thyristors branches should be connected in parallel to form the half-controlled unit for the required current withstanding capability. Therefore, the total stray inductance of the half-controlled unit can be calculated as 170 nH · 100/5 = 3.4 μH. Similarly, the stray inductances of other branches can be calculated.

8.3 Simulation Case Study

213

Figure 8.22 shows the currents and voltages in the FCL after the dc pole-to-pole fault f 1 without stray inductance and with stray inductance respectively. In theory, the existence of the stray inductance will influence the current clearing speed. However, as the simulation result showing, under the condition with stray inductance, the dc fault current clearing speed and the reactor freewheeling current clearing speed are almost the same as those under the condition without stray inductance. This is because compared with the MMC arm reactor L arm and the dc reactor L F , the stray inductance is so small that the influence on the current clearing speed can be neglected. In addition, the simulation results shown as Fig. 8.22b, c also verify that the stray inductance almost has no influence on the withstanding voltages of the power electronic switches. Therefore, it can be concluded that the influence of the stray inductance on the performance of the proposed FCL is very slight.

References 1. Liu, J., Tai, N., Fan, C., & Chen, S. (2017, July). A hybrid current-limiting circuit for DC line fault in multiterminal VSC-HVDC system. IEEE Transactions on Industrial Electronics, 64(7), 5595–5607. 2. Sano, K., & Takasaki, M. (2014, July). A surgeless solid-state dc circuit breaker for voltagesource-converter-based HVDC systems. IEEE Transactions on Industrial Applications, 50(4), 2690–2699. 3. He, J., Li, B., & Li, Y. (2018, May). Analysis of the fault current limiting requirement and design of the bridge-type FCL in the multi-terminal DC grid. IET Power Electronics, 11(6), 968–976. 4. Rohner, S., Bernet, S., Hiller, M., & Sommer, R. (2010, August). Modulation, losses, and semiconductor requirements of modular multilevel converters. IEEE Transactions on Industrial Electronics, 57(8), 2633–2642. 5. Li, X. Luo, Y. F., Duan, Y. Q., Liu, B. L., Huang, Y. L., & Sun, F. X. (2018, November). Stray inductance extraction of high-power IGBT dynamic test platform and verification of physical model. In 2018 IEEE International Power Electronics and Application Conference and Exposition, Shenzhen, China (pp. 1–6).

Chapter 9

Restart Control Strategy for the MMC-Based HVDC System

9.1 Introduction The conventional MMC based on the half-bridge sub-module cannot handle the dc fault, due to the existence of the freewheeling diodes in the converter [1, 2]. Therefore, at present, most of the VSC-based dc transmission systems are based on the dc cables, to reduce the fault probability, such as the Zhoushan multi-terminal VSC-HVDC project in China [3]. In recent years, the improved sub-module topologies with dc fault current eliminating capability are proposed, such as the full-bridge sub-module (FBSM) [4], clamp double sub-module (CDSM) [5], series connected double sub-module (SDSM) [6], and three-level sub-module (TLSM) [7]. This self-eliminating technique (eliminating the dc fault current by the converter itself) provides an excellent approach to isolating the dc fault, allowing the use of the less costly overhead line for the MMC-based HVDC transmission system. For example, China Southern Power Grid Company is building a three-terminal overhead-line based HVDC transmission system, two terminals of which are based on the FBSM technique [8]. In addition, the dc circuit breaker technique also has developed significantly in recent years, which is also a promising dc fault isolating method in the VSC-HVDC grid, especially in the multi-terminal ones. Different from the dc cable, the fault probability, especially the nonpermanent fault probability of the overhead line, is much higher [9]. Therefore, the effective restart (or reclosing) control strategy which can identify the fault property (permanent or nonpermanent) must be applied to improve the power supply reliability of the system [10]. The design of the restart (or reclosing) control strategy is highly relevant to the applied isolation scheme. In this chapter, the restart control strategy, for the dc system based on the self-eliminating technique (such as the FBSM), is mainly discussed, while the restart (reclosing) strategy under the DCCB application condition will be discussed in Chap. 10.

© Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_9

215

216

9 Restart Control Strategy for the MMC-Based HVDC System

The conventional restart control strategy deblocks the converter directly and then identifies the fault property according to the dc voltage, which will result in serious second overcurrent or overvoltage damage to the system in the case of permanent faults. Therefore, this chapter proposed a novel restart control strategy for the MMCbased HVDC transmission system, which is very simple to be implemented in the engineering. During the restart period, the proposed strategy makes the converter come into the uncontrolled rectifier operation mode firstly, and then the fault property can be identified correctly according to the dc line current. By connecting the practically existing current limiting resistors into the circuit, the system current during the fault property identifying period is limited effectively, even if the fault is permanent. Thus compared with the conventional restart strategy, the proposed strategy causes much lower damage to the system, which is very important for the system security.

9.2 MMC Sub-module with DC Fault Current Eliminating Capability 9.2.1 The Problem of the Half-Bridge SM After dc faults, the capacitors in the on-state sub-modules (SMs) of the MMC will discharge to the fault point, as shown in Fig. 9.1a. Therefore, the fault current,

on-state

off-state

(a)

(b)

Fig. 9.1 Equivalent circuit of the dc pole-to-pole fault: a before the SM being blocked, b after the SM being blocked

9.2 MMC Sub-module with DC Fault Current Eliminating Capability

217

including the dc current, arm currents, increase extremely fast. According to the practical engineering, the overcurrent self-protection will be applied to protect the IGBTs in the MMC SMs, whose threshold value is generally about 1.5–2·I IGBTN (I IGBTN is the rated current of the selected IGBT) [11]. It means that the IGBTs in the MMC SMs will be blocked quickly after the dc faults. However, even if all the IGBTs are blocked, the MMC will operate as an uncontrolled rectifier, due to the existence of the anti-parallel diodes. It means the ac-side source will feed fault current to the dc fault point continuously, as shown in Fig. 9.1b. In another word, the dc fault current exists all the time and has no natural zero crossing point. Therefore, it can be concluded that, the MMC based on the half-bridge SM (HBSM) cannot handle the dc fault by itself.

9.2.2 The Topology and Working Principle of the MMC SM with DC Fault Current Eliminating Capability As analyzed above, the conventional MMC based on HBSM cannot handle the dc fault. Therefore, several improved SM topologies which can eliminate the dc fault current are proposed in recent years, including the FBSM, CDSM, SDSM and so on [5–7].

9.2.2.1

Working Principle of the FBSM

Based on the HBSM, the FBSM with dc fault current eliminating capability was proposed [5]. The topology of the FBSM is shown as Fig. 9.2. During normal operation, the modulation control of the FBSM is shown in Table 9.1, and the corresponding working principle is shown as Fig. 9.3. As shown in Fig. 9.3a, when T1 , T4 are turned on, and T2 , T3 are turned off, the output voltage of the FBSM U SM = U C , and the capacitor C is connected in the current flowing path. Fig. 9.2 FBSM topology

T1 iSM

D1

USM T2

D2

+

-

T3

D3

T4

D1

+ C1 Uc -

218

9 Restart Control Strategy for the MMC-Based HVDC System

Table 9.1 Working states of the FBSM SM working state

T1

T2

T3

T4

U SM

iSM

On state

1

0

0

1

UC

–

0

1

1

0

−U C

–

Off state

1

0

1

0

0

–

0

1

0

1

0

–

0

0

0

0

UC

>0

0

0

0

0

−U C

0，USM=Uc T1 iSM

D1

USM T2

D2

+

-

T3

D3

T4

D1

C1 Uc+ -

(b) iSM>0，USM=-Uc

As shown in Fig. 9.4, when the IGBTs in the FBSM are all turned off, the SM capacitor voltage U C is always connected into the current flowing path in reverse polarity, no matter what flowing direction the current is. During dc fault condition, this reversed voltage can be used to eliminate the fault current.

9.2.2.2

Working Principle of the CDSM

The MMC based on the FBSM has dc fault handling capability. However, the investment increases obviously compared with the HBSM-based MMC, because the needed power electronic switches increase drastically. Therefore, the CDSM as shown in Fig. 9.5 is proposed. During normal operation, the modulation control of the CDSM is shown in Table 9.2, and the corresponding working principle is shown as Fig. 9.6. As shown in Fig. 9.6a, when T1 , T4 , T5 are turned on, and T2 , T3 are turned off, the output voltage of the CDSM U SM = 2U C . And the capacitors C 1 , C 2 in the CDSM Fig. 9.5 CDSM topology T1 iSM USM T2

D1 Uc D2

D6 C1 T5

T3 C2 D5 D7

D3

Uc T4

D1

220

9 Restart Control Strategy for the MMC-Based HVDC System

Table 9.2 Working states of the CDSM SM working state

T1

T2

T3

T4

T5

U SM

iSM

On state

1

0

0

1

1

2U C

–

1

0

1

0

1

UC

–

0

1

0

1

1

UC

–

Off state

0

1

1

0

1

0

–

Blocking state

0

0

0

0

0

2U C

>0

0

0

0

0

0

−U C

0, USM=2Uc

T1 iSM + USM=-Uc -

T2

D6 D1 + C1 Uc T5 D2

T3 C2 + D5 - U c D7

T4

D3

D4

(b) iSM

√ 3Um

(9.1)

namely, UC >

√ 3 MUCN 2

(9.2)

9.2 MMC Sub-module with DC Fault Current Eliminating Capability

+

+

+ USM=-UcT2

D6 D1 Uc + T 5 D2

D5 D7

T3 + U -c

D3

+

T4

D4

+

-

upper arm A

T1

+ +

+

+

+

+

lower arm C

lower arm B

lower arm A

+

lower arm C

+

+

+

D4

+

T4

+

upper arm C

D7

+

upper arm C

D5

+

upper arm B

T5

D3

lower arm B

D2

T3 + U - c

upper arm B

T2 USM=2Uc

+

D6

lower arm A

D1 Uc + -

upper arm A

T1

223

Fig. 9.9 The dc fault isolating principle of the MMC with dc fault current self-eliminating capability: a the dc fault current eliminating, b the fault current fed from the ac-side source

224

9 Restart Control Strategy for the MMC-Based HVDC System

where U m is the amplitude of the ac line voltage and U CN is the SM capacitor rated voltage. In addition, M is the modulation ratio, namely, M = U m /(0.5U dc ) (0 < M ≤ 1).

9.3 Conventional Restart Control Strategy of the HVDC System Based on MMC with Self-eliminating Capability The conventional restart control strategy is shown as Fig. 9.10. After a dc fault, the fault current can be eliminated by blocking the converter. Then after a delay time for insulation recovery of the fault line, the converter is deblocked directly. And the fault property can be directly identified according to the dc voltage. If the dc voltage recovers quickly, it means the fault has disappeared (nonpermanent fault) and the system restarts successfully. If the dc voltage fails to recover, the fault is identified as permanent, and the converter should be blocked again quickly. This method can identify the fault property reliably. However, with this method being applied, severe secondary damage will occur, including the overcurrent in the Fig. 9.10 Flow chart of the conventional restart control strategy

the fault current has been eliminated delay Δt1 deblock the MMC

delay Δt2

Udc>Uset？

N

Y nonpermanent fault

permanent fault

the converter restart successfully

block the converter

end

9.3 Conventional Restart Control Strategy of the HVDC System …

225

case of permanent pole-to-pole fault, pole-to-ground fault in the bipolar dc system, or permanent pole-to-pole fault in the symmetric monopolar dc system [12], and the overvoltage in the case of permanent pole-to-ground fault in the symmetric monopolar dc system.

9.4 A Novel Restart Control Strategy for the MMC-Based HVDC Transmission System According to the analysis in Sect. 9.3, an appropriate restart control strategy which can not only identify the fault property (permanent or nonpermanent) correctly, but also ensure low damage to the system, deserves further research. By introducing the uncontrolled rectifier operation mode and the starting resistor, a simple and effective restart control strategy with low damage for the MMC-based HVDC system is proposed [13].

9.4.1 Uncontrolled Rectifier Operation Mode of the Converter The sub-modules with dc fault current eliminating capability like FBSM, CDSM and SDSM show an optimistic prospect for wide application in the overhead-line based HVDC transmission system. To reduce the damage to the system in the process of identifying the fault property, this section proposes an uncontrolled rectifier operation mode for the self-eliminating MMC. Here, the bipolar FBSM-MMC (F-MMC) based HVDC system is taken as an instance to illustrate the working principle.

9.4.1.1

Uncontrolled Rectifier Operation Mode

There are three operation states of the FBSM, namely the on state, off state and blocking state [14]. The on and off states are for the normal operation modulation of the converter, and the blocking state is for the system start charging and fault eliminating. According to the topology of the FBSM, a new operation state for the sub-module is proposed, which is named as the half-bridge-like blocking (HBB) state. The HBB state of the FBSM has two forms. As shown in Fig. 9.11a, with the IGBT T1 on and the rest T2 –T4 off, the current can only flow through the diode D3 and the IGBT T1 , rendering the state the same characteristic as the blocking state of the HBSM, and thus it is named as the half-bridge-like blocking state. Similarly, as shown in Fig. 9.11b, there is another form of the FBSM HBB state with T4 on and T1 –T3 off, where the fault current can only flow through the IGBT T4 and the diode D2 . Then the uncontrolled rectifier operation mode of the F-MMC (its operation characteristic

226

9 Restart Control Strategy for the MMC-Based HVDC System

T1

D1

T2

D2

+

+

T3

D3

T4

D4

T1

D1

T2

D2

+ -

-

+ -

T3

D3

T4

D4

-

(a)

(b)

+

+

+

-

-

-

+

+

+

-

-

-

+

+

+

-

-

-

+

+

+

-

-

-

(c) Fig. 9.11 Proposed operation mode of the F-MMC: a HBB state 1, b HBB state 2, c uncontrolled rectifier operation mode of the F-MMC

is the same as an uncontrolled rectifier) is proposed by turning all the FBSMs into the HBB state as shown in Fig. 9.11c.

9.4.1.2

DC Line Current Characteristic During the Uncontrolled Rectifier Operation Mode

When the dc fault happens, the fault current can be eliminated by blocking all the sub-modules in the converter. Then the converter comes to the proposed uncontrolled rectifier operation mode after the system insulation recovers. The dc line current characteristics will vary with different fault properties. Here, the influence of the line distributed capacitor charging current is not considered, and it will be discussed later.

9.4 A Novel Restart Control Strategy …

227

F-MMC

F-MMC

F-MMC

(a) upper arm B upper arm C

+ NUc -

+ -

+ -

lower arm A lower arm B

NUc + -

+ -

F-MMC

F-MMC

+ -

(b)

Fig. 9.12 DC line current characteristic during the uncontrolled rectifier operation mode: a the current flowing path when the fault still exists, b the potential current-feeding path when the fault has disappeared

Taking the pole-to-ground fault for instance, if the fault is permanent (the fault point still exists), the ac-side source will feed current to the fault point again through the converter when the F-MMC operates in the uncontrolled rectifier operation mode, as shown in Fig. 9.12a. On the contrary, if the fault is nonpermanent (the fault has disappeared), given the potential current-feeding path as shown in Fig. 9.12b (current possibly to be fed through the local converter and the opposite converter), the current on the dc fault line will not occur again in the uncontrolled rectifier operation mode as long as the following expression is satisfied. 2NUc > u L1 − u L2

(9.3)

where N is the number of the sub-modules of each arm in the converter, U c is the sub-module capacitor voltage, and uL1 , uL2 represent the ac phase-to-phase voltages of the local station and the opposite station respectively. Considering the most serious condition where uL1 and uL2 happen to be at opposite phases, the sub-module capacitor voltage should satisfy

228

9 Restart Control Strategy for the MMC-Based HVDC System

√

√ 3 3 2NUc > UdcN · M1 + UdcN · M2 2 2

(9.4)

namely √ Uc >

3 (M1 + M2 ) · UcN 4

(9.5)

where U dcN is the rated dc voltage, and U cN the rated sub-module capacitor voltage, while M 1 and M 2 are the modulation ratios of the local and opposite converters defined as U m /0.5U dcN (U m represents the rated ac phase voltage amplitude). After a dc fault, the sub-module capacitors in the F-MMC will undergo the discharging and charging processes respectively before and after the converter being blocked. In the charging process, most of the fault energy (stored in the arm reactors, released by the sub-module capacitors in the discharging process, and fed from the ac system) will be fed back to the sub-module capacitors, and only a small amount will be consumed by the fault resistor. That means when the converter is turned into the uncontrolled rectifier operation mode after the fault current being eliminated, the sub-module capacitor voltage U c must have recovered to the rated sub-module capacitor voltage U cN [7], or even a little higher. Considering that 0 < M 1 < 1, 0 < M 2 < 1, Eq. (9.5) is satisfied, and thus it is concluded that if the fault has disappeared, the current will not occur on the dc line again during the proposed uncontrolled rectifier operation mode. Therefore, as analyzed above, the dc fault can be identified as a permanent or nonpermanent one according to the differences of the dc line current characteristic during the proposed operation mode. Differently, under the dc pole-to-pole fault condition, the station should be equivalent to two series-connected uncontrolled rectifiers when turned into the proposed operation mode. Obviously, the dc line current characteristic difference between the permanent and nonpermanent faults still exists. Therefore, the dc line current characteristic during the proposed operation mode described above can also be used to identify the fault property of the pole-to-pole fault. In addition, for the bipolar dc system, the uncontrolled rectifier operation mode of the MMC is equivalent to a three-phase full-wave rectifier in the condition of pole-to-ground fault, and two series-connected three-phase full-wave rectifiers in the condition of pole-to-pole fault. As we know, for the three-phase full-wave rectifier, the ac-side source can feed current to the dc side no matter what connection mode of the transformer dc-side winding is. That is to say, the ac-side source can feed current to the dc side in the case of permanent faults, having nothing to do with the connection mode of the transformer dc-side winding. Therefore, in the bipolar dc system, the connection mode of the transformer dc-side winding has no impact on the dc line current characteristic difference between the permanent and nonpermanent faults during the uncontrolled rectifier operation mode. This means the connection mode of the transformer dc-side winding will have no influence when the dc line

9.4 A Novel Restart Control Strategy …

229

current characteristic during the proposed operation mode described above is used to identify the fault property.

9.4.2 Proposed Restart Control Strategy 9.4.2.1

Current Limitation During the Proposed Uncontrolled Rectifier Operation Mode

Compared with the conventional restart strategy which deblocks the converter directly to identify the fault property, the current during the proposed operation mode in the case of the permanent fault is smaller, since the secondary discharging of the sub-module capacitors is avoided. However, the steady-state current of the proposed operation mode is still larger than the rated current. This overcurrent may still threaten the system security. Therefore, in this section, the current-limiting method during the uncontrolled rectifier operation mode is proposed. In practical engineering, current limiting resistors Rlim will be installed at the ac side of the converter as shown in Fig. 9.13 [15]. During the system start charging period, the current limiting resistors are connected into the charging path in series,

+ -

upper arm C

-

upper arm B

+

Rlim

S +

lower arm B

lower arm A

-

+ -

Fig. 9.13 Current flowing path during the proposed uncontrolled rectifier operation mode with the current limiting resistors being connected into the circuit

230

9 Restart Control Strategy for the MMC-Based HVDC System

and thus the overcurrent damage to the devices can be avoided completely. After the charging period, the current limiting resistors will be bypassed by closing the parallel switches S. According to this practical engineering situation, it is easy to use the existing current limiting resistors Rlim and parallel switches S to limit the current level during the proposed uncontrolled rectifier operation mode. The current limiting resistors can be connected into the circuit in series by opening the parallel switches S after the fault current is eliminated. Since the fault current has been eliminated by the converter itself, the arc extinguishing capability of the parallel switches is almost not required. After that, the converter can be turned into the uncontrolled rectifier operation mode. In the case of a permanent pole-to-ground fault, with the arm inductance neglected, the maximum current which may occur in the converter arms and dc line in the proposed uncontrolled rectifier operation mode can be estimated as (without and with the current limiting resistors Rlim respectively) 

without Rlim : i max = Ulm /2Rarm with Rlim : i max = Ulm /2(Rarm + Rlim )

(9.6)

where U lm is the amplitude of the ac phase-to-phase voltage, and Rarm is the equivalent resistance of each arm. Obviously, Rarm is quite small, so imax will be very large without the current limiting resistor Rlim . Differently, with the current limiting resistor connected into the circuit, imax will be limited significantly according to (9.6).

9.4.2.2

Proposed Restart Control Strategy

Based on the dc line current characteristic of the proposed uncontrolled rectifier operation mode and the current limiting capability of the current limiting resistors, the restart control strategy with low damage is proposed as shown in Fig. 9.14. The detailed steps of implementing the proposed restart control strategy are as follows: Step (1): Ensure a delay of t 1 after the dc fault current is eliminated for recovering the insulation characteristic of the system. Meanwhile, open the parallel switches S during this delay period to connect the current limiting resistors Rlim into the circuit. Step (2): Turn all the sub-modules into the HBB state, enabling the converter to come into the uncontrolled rectifier operation mode. Step (3): After a delay of t 2 , detect the dc line current I dc . Step (4): Identify the fault property by comparing the detected dc line current I dc with the threshold value I set . If I dc is larger than I set , it is clear that the fault is permanent, so the converter should be blocked quickly again. Step (5): If I dc is no larger than I set , the fault can be identified as nonpermanent. Therefore, the system can recover to the normal operation mode, while the parallel switches should be closed to bypass the current limiting resistors.

9.4 A Novel Restart Control Strategy …

231

the fault current has been eliminated delay Δt1 and open the parallel switches S all the sub-modules operate into the HBB state the converter operates into the uncontrolled rectifier operation mode delay Δt2 detect the dc line current Idc

Idc>Iset？

Y

N nonpermanent fault

permanent fault

close the parallel switches S and recover the system to normal operation mode

block the converter

end Fig. 9.14 Flow chart of the proposed restart control strategy

The detailed criterion for the fault property identification can be described as 

permanent fault: Idc >Iset nonpermanent fault: Idc ≤ Iset

(9.7)

In step (3), the delay t 2 is introduced to eliminate the influence of the line distributed capacitor charging current on the reliability of the proposed fault property identification criterion. Therefore, the value of t 2 must be larger than the duration of the line distributed capacitor charging process that occurs at the initial stage of the proposed mode in the case of a nonpermanent fault, which will be discussed in detail later. In step (4) and step (5), I set is the threshold value of the criterion to identify the fault to be permanent or nonpermanent. According to the dc line current characteristic of the proposed uncontrolled rectifier operation mode, the fault property identification

232

9 Restart Control Strategy for the MMC-Based HVDC System

criterion only needs to identify whether the dc line current occurs again or not (the influence of line distributed capacitor charging current has been excluded by the delay of t 2 ). Therefore, the threshold value I set can be set very low, which only needs to consider the factors like the criterion reliability margin and measurement error. In the proposed strategy, the parallel switches only need to be opened and closed at most once respectively during the restart period. The opening operation can be implemented during the system insulation recovering period, so it has no influence on the restart speed. And the switches will not be closed until the fault is identified as nonpermanent. Even if the restart strategy is set to be tried several times, there is no need to operate the switches repeatedly, because they just need to keep in opening state before the fault is identified as nonpermanent. In addition, the arc extinguishing capability of the parallel switches S is almost not required, so the operation of the switches can be quite fast, e.g., several milliseconds, even if it is mechanical [16]. Therefore, the operation of the switches has little influence on the restart speed.

9.4.2.3

Duration Estimation of the Line Distributed Capacitor Charging Process

In Sect. 9.4.1, the line distributed capacitor charging current is neglected during the analysis of the dc line current characteristic in the proposed uncontrolled rectifier operation mode. In fact, the charging current to the line distributed capacitor will occur on the dc line when the converter turns into the proposed operation mode in the case of the nonpermanent fault. Especially in the initial stage, the line capacitor needs to be charged to match the output voltage of the uncontrolled rectifier, so the peak value of this charging current may even be close to the dc line current value during the uncontrolled rectifier operation mode after a permanent fault, thus leading to the maloperation of the proposed fault property (permanent or nonpermanent) identification criterion. Therefore, the delay time t 2 is introduced in the proposed restart control strategy to eliminate the influence of the line capacitor charging current. Obviously, it is necessary to estimate the duration of the line distributed capacitor charging process during the proposed operation mode in the case of a nonpermanent fault, to provide the theoretical reference for the setting of t 2 . Figure 9.15a shows the equivalent circuit of the line distributed capacitor charging process when the converter is turned to the proposed operation mode in the case of a nonpermanent pole-to-ground fault. In Fig. 9.15, the dc line is represented by the T model, where Rl , L l represent the equivalent resistance and self inductance of the line, and C gl represents the equivalent capacitance between the line and ground. Considering that the dc voltage U dc is the output voltage of a rectifier, it is reasonable to simplify the equivalent circuit to Fig. 9.15b. In fact, the dc current of the healthy pole i2 is constant since the healthy pole is still in normal operation during this period, therefore, d(L Ml · i2 /2)/dt = 0 (L Ml is the mutual inductance between the positive and negative poles).

9.4 A Novel Restart Control Strategy …

ich Rl/2

233

Ll/2

Rl/2

Ll/2

Cgl AC side

opposite station

Udc

(a)

ich

Rl/2

ich_tr Rl/2

Ll/2

T/2

Ll/2

+ Cgl

Cgl

Udc-d(LMl*i2/2)/dt -

(c)

(b)

Fig. 9.15 Equivalent circuit of line distributed capacitor charging process during the uncontrolled rectifier operation mode: a equivalent circuit, b simplified circuit, c equivalent circuit of the transient component

According to the dynamic circuit solving principle, the charging current ich can be expressed as ich (∞) + ich_tr . Obviously, the steady-state response ich (∞) of the circuit shown in Fig. 9.15b is zero (supposing U dc is a constant), so ich is equal to the transient response ich_tr . Considering that the dc line current was eliminated to zero by the converter in the previous blocking stage, namely ich (0+ )=0, and thus ich can be achieved as i ch = −

2U0 −σ t e sin ωt ωL l

(9.8)

 where σ = Rl /2L l , ω = 2/L l Cgl − σ2 , and U 0 is the initial value of the line capacitor voltage. Obviously, during the uncontrolled rectifier operation mode, ich cannot be negative due to the unidirectional conducting characteristic of the diode. Therefore, the charging period in the proposed operation mode after a nonpermanent fault will only last for half an oscillation cycle as shown in Fig. 9.15c, after which the dc line current will be clamped at zero by the diodes in the converter. So the duration time t ch of the charging process can be estimated by π /ω, namely

234

9 Restart Control Strategy for the MMC-Based HVDC System

 tch = π/ 2/L l C gl − (Rl /2L l )2 .

(9.9)

Similarly, the duration of the line distributed capacitor charging process during the proposed operation mode in the case of the nonpermanent pole-to-pole fault can be estimated by  tch = π/ 1/(L l − L Ml )C Ml − [Rl /2(L l − L Ml )]2

(9.10)

where C Ml is the equivalent capacitance between the positive pole and negative pole. In the proposed strategy, the set value of t 2 is supposed to be larger than t ch , for sufficient reliability. In fact, since the current during the proposed uncontrolled rectifier operation mode in the case of the permanent fault has been limited significantly by the current limiting resistors, no matter how large the delay time t 2 is, it causes no damage to the system security.

9.4.2.4

Feasibility Evaluation of the Proposed Strategy

(1) Feasibility for the other self -eliminating MMC-based HVDC system: Considering the power loss and cost, improved sub-modules with dc fault eliminating capability were proposed [5–7]. As shown in Fig. 9.16, the HBB state can also be achieved by the other sub-modules with dc fault eliminating capability. Therefore, the self-eliminating MMCs based on different sub-modules can all operate in the proposed uncontrolled rectifier operation mode. And the proposed restart control strategy is feasible for different kinds of self-eliminating MMC-based HVDC systems. Similarly, it is also suitable for the hybrid-MMC-based HVDC systems. (2) Application in the symmetric monopolar dc system: In the previous content, the bipolar dc system is mainly discussed. As we know, a pole-to-pole fault in the symmetric monopolar dc system is equivalent to a pole-to-ground fault in the bipolar dc system, so it is obvious that the proposed restart control strategy is also valid in identifying the fault property of the pole-to-pole fault in the symmetric monopolar dc system. For the pole-to-ground fault in symmetric monopolar dc system, the feasibility of the proposed restart strategy is dependent on the grounding mode of the system. Figure 9.17 shows two typical kinds of the grounding modes in the symmetric monopolar dc system. As shown in Fig. 9.17a, when the system grounds through the transformer neutral point with a large resistor, the dc line current characteristic during the proposed uncontrolled rectifier operation mode described above still exists, so the proposed restart control strategy is also feasible. Furthermore, in this case, only the sub-modules in the bridge arms corresponding to the fault pole should be turned into the HBB state, and the sub-modules in the bridge arms corresponding to the healthy pole still remain in blocking state. Under this condition, different from the conventional restart strategy, the normal operation control is not put in. So the overvoltage damage to the healthy pole and transformer during the fault property

9.4 A Novel Restart Control Strategy … Fig. 9.16 HBB states of the other sub-modules with dc fault eliminating capability: a HBB state of the CDSM, b HBB state of the SDSM, c HBB state of the TLSM

235

T1

(a)

D1

+ T2

D2

T1

D1

T2

D2

D6 + -

D5

T5

+ -

D7

T3

D3

T4

D4

T3

D3

T4

D4

T3

D3

T4

D4

-

(b)

+

D6 +

-

-

+

T5 D5

-

D6

(c)

T1

D1

T2

D2

D7 +

T6

+

+

-

-

T5

D8

D5

identifying period is reduced significantly. Differently as shown in Fig. 9.17b, when the dc system grounds at the dc side, the converter-side winding of the transformer will generally not be grounding anymore. Therefore, there is no flowing path for the current fed from the ac-side source to the fault point during the uncontrolled rectifier operation mode after a permanent pole-to-ground fault. That is to say, there shows no dc line current characteristic difference between the permanent and nonpermanent faults, and the proposed restart control strategy does not work. In summary, the proposed restart control strategy is feasible for the following cases: the pole-to-ground fault and pole-to-pole fault in the bipolar dc system, poleto-pole fault in the symmetric monopolar dc system, and pole-to-ground fault in the symmetric monopolar dc system grounding through the transformer neutral point with a large resistor. Compared with the conventional method, the proposed restart control strategy reduces the overcurrent and overvoltage damages to the system significantly during the fault property identifying period after permanent faults. Considering that the proposed strategy is not only very simple to implement, but also with a wide feasible range, especially in the bipolar dc transmission system which is the development trend of the MMC-based HVDC transmission, it is obvious to have an outstanding engineering application value.

236

9 Restart Control Strategy for the MMC-Based HVDC System

(a) lower arm A

lower arm B

lower arm C

lower arm A

lower arm B

lower arm C

(b)

Fig. 9.17 DC line current characteristic during the uncontrolled rectifier operation mode after permanent pole-to-ground fault in the symmetric monopolar dc system with different grounding modes: a grounding through the transformer neutral point with a large resistor, b grounding at the dc side

9.5 Case Study A model of the bipolar MMC-based HVDC transmission system with the parameters in Table 9.3 is built on the PSCAD/EMTDC, where the frequency-dependent model is used for the overhead line, and the converter stations are modeled using the high-speed electromagnetic transient simulation model [17]. Then the simulation cases with the conventional and proposed restart control strategies are carried out respectively, to verify the feasibility and superiority of the proposed strategy. In the simulation cases, t 1 is set as 150 ms, and I set as 0.1 kA. With the parameters of the used overhead line (Rl = 6.512 , L l = 534.2 mH, L Ml = 276.6 mH, C gl = 1.525 μF, C Ml = 0.9 μF), the maximum value of t ch calculated by (9.9)–(9.10) is 2 ms. In the simulation, the set value of t 2 is twice as large as t ch , namely, 4 ms.

9.5 Case Study

237

Table 9.3 Parameters of the MMC-based dc system

Parameter

Value

Rated dc voltage (kV)

±500

Rated ac voltage (kV)

260

Rated capacity (MW)

3000

Number of SMs per arm

220

SM capacitors (μF)

15,000

Arm inductance (mH)

80

Current limiting resistor ()

1000

Length of the dc line (km)

200

9.5.1 Pole-to-Ground Fault In this case, a permanent pole-to-ground fault occurs at t = 1 s 20 km from the converter. When the conventional restart control strategy is applied, the converter will be deblocked directly after the fault current is eliminated and the system insulation characteristic has recovered (at about t = 1.154 s) to identify the fault property. As shown in Fig. 9.18a, since the dc voltage cannot build, the fault will be identified as

(a)

400 0 -400 -800

(b)

12 8 4 0

6

iarma

iarmb

iarmc

(c)

4 2 0 -2

1

1.1

1.2

1.3

Time(s) Fig. 9.18 Simulation result of the permanent pole-to-ground fault with the conventional restart strategy: a dc pole-to-ground voltage (kV), b dc line current (kA), c arm currents (kA)

238

9 Restart Control Strategy for the MMC-Based HVDC System Δt1

(a)

400

Δt2

0 -400 -800

1.5

(b)

12 8

0.1 0 1.154

4

1.157

0 6

(c)

4

iarma iarmb

iarmc

2 0 -2

1

1.1

Time(s)

1.2

1.3

Fig. 9.19 Simulation result of the permanent pole-to-ground fault with the proposed restart strategy: a dc pole-to-ground voltage (kV), b dc line current (kA), c arm currents (kA)

permanent, leading the converter to be quickly blocked again. However, as shown in Fig. 9.18b, c, due to the secondary discharging of the SM capacitors, a severe overcurrent occurs again during the fault property identifying period, leading to a secondary damage to the system. As shown in Fig. 9.19, when the proposed strategy is applied, the fault can be identified as permanent correctly since the dc line current exceeds the threshold value I set quickly after the converter is turned into the uncontrolled rectifier operation mode. During the whole fault property identifying period, the SM capacitors are still bypassed, and the current limiting resistors are connected into the circuit, so no overcurrent occurs in the system. Figure 9.20 shows the simulation result of the nonpermanent pole-to-ground fault with the proposed restart strategy (the fault happens at t = 1 s and lasts for 0.1 s). As shown in Fig. 9.20b, the converter is turned into the uncontrolled rectifier operation mode at about t = 1.154 s. Although the current also occurs on the dc line at the initial stage of this operation mode, it decays completely in about 2.6 ms (this current

9.5 Case Study

239 800

(a)

400 0 -400 -800 1

(b)

12 8

0.1 0 1.154

4

1.157

0 6

iarma iarmb iarmc

(c)

4 2 0

(d)

-2 6 4 2 0 -2 -4 -6

isa isb isc

1

1.2

1.4

1.6

1.8

Time(s) Fig. 9.20 Simulation result of the nonpermanent pole-to-ground fault with the proposed restart strategy: a dc pole-to-ground voltage (kV), b dc line current (kA), c arm currents (kA), d ac-side currents (kA)

is the charging current to the line distributed capacitor). Thus after the delay t 2 , the proposed strategy can identify the fault as nonpermanent correctly. And the system can be recovered to the normal operation mode.

9.5.2 Pole-to-Pole Fault Figure 9.21 shows the simulation results of the permanent and nonpermanent poleto-pole faults with the proposed restart strategy. The simulation results verify that the proposed restart strategy can also identify the fault property of the pole-to-pole fault correctly. For the permanent fault, the converter can be blocked again quickly, with

240

9 Restart Control Strategy for the MMC-Based HVDC System 800

(a)

400

nonpermanent

0 permanent -400 1.5

16

permanent

(b)

12

nonpermanent 0.1 0 1.154

8 4

1.157

0 1

1.2

1.4

1.6

1.8

Time(s) Fig. 9.21 Simulation results of the pole-to-pole faults with the proposed restart strategy: a dc pole-to-ground voltage (kV), b dc line current (kA)

low damage to the system. While for the nonpermanent fault, the system is recovered to the normal operation mode quickly after the fault property identification.

9.5.3 Feasibility in the Symmetric Monopolar Dc System In this case, a model of a symmetric monopolar dc system is built. Figure 9.22 shows the simulation result of the permanent positive pole-to-ground fault with the conventional restart strategy in the symmetric monopolar dc system. As shown in Fig. 9.22, during the fault property identifying period, the overcurrent problem is not as severe as that in the bipolar system, and the permanent fault can be identified correctly due to the failed recovery of the fault pole voltage (U dcp ). However, serious overvoltage occurs on the healthy pole (U dcn ) and in the ac system (U s ), because the normal operation control is put in again during this period.

9.5 Case Study

241 800

Udc Udcp

(a)

400 0

Udcn

(b)

-400 -800 5 4 3 2 1 0 -1

(c)

400 200

usa usb usc

0 -200 -400 -600 1

1.2

1.1

1.3

Time(s) Fig. 9.22 Simulation result of the permanent pole-to-ground fault in the symmetric monopolar dc system with the conventional restart strategy: a dc voltage (kV), b dc line current (kA), c ac phase voltage (kV)

As shown in Fig. 9.23, when the proposed restart strategy is applied, the permanent fault can be identified correctly since the dc line current exceeds the threshold value I set quickly after the converter is turned into the proposed operation mode. And the overvoltage problem which occurs in the conventional strategy is reduced significantly. In addition, as shown in Fig. 9.24, the proposed restart strategy can identify the fault as nonpermanent correctly and then recover the system to normal operation mode immediately.

242

9 Restart Control Strategy for the MMC-Based HVDC System 800

Udc Udcp

(a)

400 0

Udcn

-400

(c)

(b)

-800 5 4 3 2 1 0 -1

0. 1

400 200 0 -200

usa usb usc

-400 -600 1

1.3

1.2

1.1

Time(s) Fig. 9.23 Simulation result of the permanent pole-to-ground fault in the symmetric monopolar dc system with the proposed restart strategy: a dc voltage (kV), b dc line current (kA), c ac phase voltage (kV) 800 Udc

(a)

400

Udcp

0 Udcn

(b)

-400 -800 5 4 3 2 1 0 -1

1

1.2

1.4

1.6

1.8

Time(s) Fig. 9.24 Simulation result of the nonpermanent pole-to-ground fault in the symmetric monopolar dc system with the proposed restart strategy: a dc voltage (kV), b dc line current (kA)

References

243

References 1. Yang, J., Fletcher, J. E., & O’Reilly, J. (2012, October). Short-circuit and ground fault analyses and location in VSC-based DC network cables. IEEE Transactions on Industrial Electronics, 59(10), 3827–3837. 2. Li, X. Q., Song, Q., Liu, W. H., Rao, H., Xu, S. K., & Li, L. C. (2013, January). Protection of nonpermanent faults on DC overhead lines in MMC-based HVDC systems. IEEE Transactions on Power Delivery, 28(1), 483–490. 3. Tang, G. F., He, Z. Y., Pang, H., Huang, X. M., & Zhang, X. P. (2015, June). Basic topology and key devices of the five-terminal DC grid. CSEE Journal of Power and Energy Systems, 1(2), 22–35. 4. Adam, G. P., & Davidson, I. E. (2015, December). Robust and generic control of full-bridge modular multilevel converter high-voltage dc transmission systems. IEEE Transactions on Power Delivery, 30(6), 2468–2476. 5. Marquardt, R. (2011, May). Modular multilevel converter topologies with DC-short circuit current limitation. In Proceedings of the 8th International Conference on Power Electronics, ECCE Asia (pp. 1425–1431). 6. Zhang, J., & Zhao, C. (2015, June). The research of SM topology with DC fault tolerance in MMC-HVDC. IEEE Transactions on Power Delivery, 30(3), 1561–1568. 7. Li, R., Fletcher, J. E., Lie, X., Holliday, D., & Williams, B. W. (2015, August). A hybrid modular multilevel converter with novel three-level cells for DC fault blocking capability. IEEE Transactions on Power Delivery, 30(4), 2017–2026. 8. Rao, H., Hong, C., Zhou, B., Huang, D., Shukai, X., Yao, W., et al. (2017, March). Study on improvement of VSC-HVDC at inverter side of Wudongde multi-terminal UHVDC for the problem of centralized multi-infeed HVDC. Southern Power System Technology, 11(3), 1–5. 9. Teeuwsen, S. P. (2011, June). Modeling the Trans Bay Cable Project as voltage-sourced converter with modular multilevel converter design. In Proceedings of the IEEE PES General Meeting (pp. 1–8). 10. Li, T., & Zhao, C. (2015, April). Recovering the modular multilevel converter from a cleared or isolated fault. IET Generation, Transmission and Distribution, 9(6), 550–559. 11. He, J., Li, B., & Li, Y. (2018). Analysis of the fault current limiting requirement and design of the bridge-type FCL in the multi-terminal DC grid. IET Power Electronics, 11(6), 968–976. 12. Gao, Y., Bazargan, M., Xu, L., & Liang, W. (2013, September). DC fault analysis of MMC based HVDC system for large offshore wind farm integration. In Proceedings of the 2nd IET Renewable Power Generation Conference (pp. 1–4). 13. Li, B., He, J., Li, Y., et al. (2018, July). A novel restart control strategy for the MMC-based HVDC transmission system. International Journal of Electrical Power & Energy Systems, 99, 465–473. 14. Petino, C., Heidemann, M., Eichhoff, D., Stumpe, M., Spahic, E., & Schettler, F. (2016, February). Application of multilevel full bridge converters in HVDC multiterminal systems. IET Power Electronics, 9(2), 297–304. 15. Xue, Y. L., Xu, Z., & Tang, G. (2014, February). Self-start control with grouping sequentially precharge for the C-MMC-based HVDC system. IEEE Transactions on Power Delivery, 29(1), 187–198. 16. Hafner, J., & Jacobson, B. (2011, September). Proactive hybrid HVDC breakers—A key innovation for reliable HVDC grid. In Proceedings of the Cigre Symposium, Bologna, Italy. 17. Xu, J., Ding, H., Fan, S., Gole, A. M., & Zhao, C. (2016, December). Enhanced high-speed electromagnetic transient simulation of MMC-MTdc grid. International Journal of Electrical Power & Energy Systems, 83, 7–14.

Chapter 10

The DCCB Reclosing Strategy in VSC-HVDC Grid

In the VSC-HVDC system, the design of reclosing (or restarting) strategy is highly dependent on the used dc fault isolation method. At present, there are mainly two kinds of dc fault isolation methods feasible for flexible HVDC system, i.e., the self-eliminating converter technique and the DCCB technique. The self-eliminating converter technique has been introduced in Chap. 9, and the corresponding restart strategy has also been discussed. However, the future VSC-HVDC grid will be multiterminal, where the dc lines interconnect with each other directly via the dc bus, such as the Zhangbei DC Grid Project which is under construction in China [1]. In the multi-terminal flexible dc grid, the self-eliminating converter technique is not suitable anymore, because this kind of dc fault isolation will lead to whole-system power outage. And the DCCB becomes the most ideal dc fault isolation method, as it can isolate the fault line with selectivity by cooperating with the dc protection [2]. At present, it is believed that the hybrid DCCB will be widely applied in the flexible HVDC grid [3], because it has both the advantages of high acting speed and low operation power loss. For example, the 200 kV hybrid DCCB has been used in the Zhoushan Multi-terminal VSC-HVDC Project in China [4]. And it has been determined that the 500 kV hybrid DCCB will be used in the Zhangbei DC Grid Project [1]. Therefore, the research about the DCCB reclosing strategy in this chapter is mainly based on the hybrid DCCB. For the hybrid DCCB, Ref. [5] proposed a sequential auto-reclosing strategy, which sequentially recloses the main breaker modules to limit the reclosing overcurrent under the permanent fault condition, and identifies if the fault has disappeared or not by the fault detection algorithm. This method effectively limits the second overcurrent during the reclosing process, thus obviously having a good application prospect. However, for engineering application of the sequential auto-reclosing strategy, several problems have to be considered: (1) With the sequential autoreclosing strategy, the turn-on and turn-off times of the power electronic switches in the DCCB will increase dramatically, which is not beneficial to the device life. (2) Although the current during the reclosing period is limited, the MOV capacity requirement will increase because it needs to eliminate the dc current repeatedly © Springer Nature Singapore Pte Ltd. 2020 B. Li and J. He, Protection Principle and Technology of the VSC-Based DC Grid, Power Systems, https://doi.org/10.1007/978-981-15-6644-8_10

245

246

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

within a small time period, meanwhile, the requirement on the cooling system may also increase. (3) The control strategy is complex for using in the practical engineering. Therefore, a novel reclosing strategy is proposed in this chapter, which uses the residual voltage characteristics to identify the fault property and is much more feasible for the engineering application.

10.1 Working Principle of DCCBs The dc fault current in VSC-HVDC grid increases extremely fast, with no natural zero crossing point. This is the core difficulty of the DCCB technique. At present, the types of DCCB mainly include solid-state DCCB, mechanical DCCB, and hybrid DCCB. The operation power loss of the solid-state DCCB is very high (about 30% of the converter power loss), thus being not suitable for HVDC application. Therefore, in this section, only the working principles of the mechanical DCCB and hybrid DCCB are discussed.

10.1.1 The Working Principle of Mechanical DCCB The mechanical DCCB uses the artificial-zero-crossing principle and the arc extinguishing characteristic of the mechanical switch, to cut off the dc fault. Firstly, the capacitor in the DCCB is connected into the fault circuit to build the transient recovery voltage (TRV). Then the arrester can be connected in, to clear the fault current. Figure 10.1 shows a typical topology of the mechanical DCCB, which is based on the active oscillation current commutation technique. As shown in Fig. 10.1, the mechanical DCCB consists of the load branch, current commutation branch and the energy absorbing branch MOV Imov K1 load branch If

Ims L Ic

K2

MS

TSG

Ihf

C Rc

current commutation branch Fig. 10.1 The mechanical DCCB based on the active oscillation current commutation technique

10.1 Working Principle of DCCBs

247

energy absorbing branch. The load branch mainly refers to the high-speed mechanical switch (MS). The current commutation branch is composed of the triggered sphere gap (TSG), the reactor L and the capacitor C. And the energy absorbing branch mainly consists of the arrester. The detailed working principle of the above mechanical DCCB can be described as following. During system normal operation, the load current flows through the load branch, where the conducting resistance is at micro-ohm level. So the operation power loss of the DCCB is very small. After the dc fault, and the DCCB receives the tripping signal, the opening signal is sent to the MS. When the dielectric strength of the MS recovers to ensure the TRV, the TSG is closed. Therefore, the capacitor in the current commutation branch discharges to generate a high-frequency oscillating current I hf between the load branch and the current commutation branch. So the oscillating current I hf is superimposed on the fault current I hf in the load branch, to make the total current I ms flowing through the MS extinguish the arc. After that, the fault current is commutated to the current commutation branch to build the TRV on the capacitor. The voltage U CB across the DCCB increases until the arrester gets into the voltage limiting area. Then the fault current can be cleared quickly by the arrester. Finally, the residual current is cut off by the switches (K1 and K2 ).

10.1.2 The Working Principle of the Hybrid DCCB The essential working principle of the hybrid DCCB is to build the TRV by turning off the fully-controlled power electronic devices (IGBT or IGCT), and then connect the arrester into the fault circuit. The typical topology of the hybrid DCCB is proposed by ABB, as shown in Fig. 10.2. As shown in Fig. 10.2, the hybrid DCCB consists of the load branch, current commutation branch and the energy absorbing branch. The load branch is composed of the high-speed mechanical switch (MS) and the load current switch (LCS). The K1 load branch If

MS

K2 LCS

Ims

current commutation branch Ic

SM_1

SM_n

LCS & SM IGBT_1

IGBT_2

Cs1 Ds1 Ds2 Cs2

Imov MOV energy absorbing branch

Rs1

Fig. 10.2 The hybrid DCCB based on the LCS current commutation technique

Rs2

248 Table 10.1 Advantages and drawbacks of the typical DCCBs

10 The DCCB Reclosing Strategy in VSC-HVDC Grid Solid-state Hybrid

Mechanical

Operating time

Very short

Short

Long

Arc ablation

No

Normal

Serious

Service life

Quite long Long

Short

Current commutation High reliability

High

Low

Operation power loss High

Low

Low

Cooling equipment

Require

No

No

Voltage and current balance

Require

Require

No

Control complexity

Easy

Quite easy Quite difficult

Control reliability

Quite high Quite high Normal

Investment

High

Normal

Low

current commutation branch consists of series-connected sub-modules (SMs). And the energy absorbing branch mainly refers to the arrester. The working principle of the hybrid DCCB is as following. During system normal operation, the SMs in the LCS are turned off firstly after the dc fault is detected. Meanwhile, the IGBTs in the current commutation branch are turned on. Therefore, the fault current is commutated to the current commutation branch from the load branch. After the current commutation process is completed, the open signal is sent to the MS. When the dielectric strength of the MS recovers to ensure the TRV, the IGBTs in the current commutation branch are then turned off. After that, the fault current charges the capacitors in the RCDs, and the arrester will come into the voltage limiting area when the voltage across the DCCB increases to exceed the acting voltage of the arrester. So the fault current is cleared quickly by the arrester. Finally, the residual current is cut off by the residual dc current breaker (RCB). In summary, the advantages and drawbacks of the above DCCBs can be concluded as Table 10.1.

10.2 Analysis of the Fault Line Residual Voltage Steady-State Characteristic 10.2.1 Equivalent Circuit of the Hybrid DCCB The hybrid DCCB is the key equipment and will be widely applied in the flexible HVDC grid. Therefore, the fault property identification based on hybrid DCCB is mainly discussed in this chapter. Figure 10.3a shows the topology of the typical hybrid DCCB. It mainly consists of the bypass current path, the main breaker path and the arrester path [3]. The bypass current path, composed of the series-connected

10.2 Analysis of the Fault Line Residual Voltage Steady-State Characteristic

UFD

249

LCS Main breaker

LF Residual dc current breaker (a)

+ -

+-

Udc/2

Arrester

+ -

Udc/2

+ + -

(b)

Udc/2 (c)

Fig. 10.3 The equivalent circuit of the hybrid DCCB: a the topology of the hybrid DCCB, b the equivalent circuit after the residual dc current breaker being opened, c the equivalent circuit after the residual dc current breaker being reclosed

load commutation switch (LCS) and the ultrafast disconnecter (UFD), is connected with the main breaker path in parallel, as well as the arrester path. The main breaker path is composed of the series-connected IGBT modules, and the snubber circuit (the RCD circuit is used in the chapter) is configured for each IGBT module [3]. In addition, the current limiting reactor and the residual dc current breaker are also installed. During normal operation, the load current flows through the bypass current path, thus only producing low power loss. After dc faults, the LCS will be switched off quickly to commutate the fault current to the main breaker path, then the UFD is subsequently opened. After that, the IGBT modules in the main breaker path can be turned off, and the fault current is eliminated by the arrester. Finally, the residual dc current breaker is opened to isolate the fault line physically. As shown in Fig. 10.3b, after the residual dc current breaker is opened, the residual energy in the snubber circuit is absorbed by the arrester. Then all the components

250

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

in the DCCB will keep in power-off state if the residual dc current breaker keeps open, because the DCCB is disconnected from the dc grid physically. Differently as shown in Fig. 10.3c, if the (and only the) residual dc current breaker is reclosed, the physical isolation between the DCCB and the healthy dc grid disappears. And for the dc grid, the DCCB can be simplified to a circuit composed of the parallelconnected capacitor and arrester, where the arrester can be equivalent to a resistor whose value is determined according to the V-I characteristic generally provided by the manufacturer [6].

10.2.2 Equivalent Circuit of the DC Overhead Line The dc overhead line can be equivalent to the distributed parameter model as shown in Fig. 10.4a [7]. The series resistance r represents the line power loss (per-unit distance). The self-inductance l and the mutual-inductance m represent the line magnetic field effect (per-unit distance). The self-partial-capacitance c and mutualpartial-capacitance cM represent the line electrostatic field effect (per-unit distance). And the conductance g represents the ion flow effect of the line (per-unit distance). It should be noted that there is only the pole-to-ground conductance (g) in the distributed

electrostatic field effect c

r

m

cM l

cM l

r g

c

g

l

r

m

power loss

c

g

l

r

g ion flow field effect

magnetic c field effect

(a) C

G

R=r*length

M=m*length

CM=cM*length/2

G

CM

L

R C

C

L=l*length

C=c*length/2

G=g*length/2

G

(b) Fig. 10.4 The equivalent circuit of the dc overhead line: a the distributed parameter model, b the  model

10.2 Analysis of the Fault Line Residual Voltage Steady-State Characteristic

251

parameter model, ignoring the pole-to-pole conductance, because the ions mainly move to the ground [7]. For theoretical analysis, the distributed parameter model can be simplified to the lumped parameter model. In this chapter, the typical lumped parameter model,  model as shown in Fig. 10.4b is used. In Fig. 10.4 (b), 

R = r × length, L = l × length, M = m × length C = c × length/2, C M = c M × length/2, G = g × length/2

(10.1)

where length represents the length of the dc overhead line.

10.2.3 The Residual Voltage Steady-State Characteristic of the Fault Line In this chapter, the residual voltage refers to the pole-to-ground voltage at the DCCB line side after the fault line being isolated. Obviously, if the residual dc current breaker keeps open after the fault line being isolated, the tripped DCCB and the fault line are always physically isolated from the dc grid. So the residual voltage during the steady state must be zero. However, if the residual dc current breaker is reclosed, the steady-state residual voltage will be much different. As shown in Fig. 10.5a, if the fault is a permanent pole-to-ground fault, the residual voltage U p_r during steady state can be expressed as Up_ r =

1 Rg // 2G Udc Udc · · = 1 2 2 RA1 //RA2 + Rg // 2G

RA1 ·RA2 RA1 +RA2

·



1 1 Rg

 + 2G + 1

(10.2)

where U dc is the dc grid voltage, Rg the transition impedance, RA1 and RA2 are the equivalent resistances of the arresters in the DCCBs. Similarly as shown in Fig. 10.5b, for the permanent pole-to-pole fault, the residual voltage U p_r during steady state can be expressed as Up_ r =

1 Udc   · 2 2 RA1 ·RA2 · 1 + G + 1. RA1 +RA2 Rg

(10.3)

Obviously, under this condition, the voltage exerted on the DCCB arrester will not be larger than the dc grid operation voltage. In addition, according to the working principle of the DCCB, the acting voltage of the DCCB arrester is generally set to be larger than the dc grid operation voltage, to ensure sufficient fault current clearing speed. Therefore, the arrester is in the small current area, during which the arrester equivalent resistances RA1 and RA2 are fixed values, which can be determined according to the V-I characteristic provided by the manufacturer.

252

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

RA1 +

Udc - 2

Up_r 2G

Udc + 2 -

Rg

RA2

RA1

RA2

Up_r

+

Udc

-

RA1

2G

Udc + 2 -

Up_r 2G

Up_r

+ -

Rg

(e)

Udc

2G

RA1

RA1

RA2

Up_r 2G

2G

Udc

RA2

+ -

(d)

RA1 Udc - 2

-

RA2

RA1

RA2

(c)

+

+

(b)

RA1 Udc - 2

Udc RA2

2G

(a)

+

Rg

Udc + 2 -

+

Udc - 2

RA2 Udc + 2 -

Up_r 2G

(f)

Fig. 10.5 The steady-state characteristic of the residual voltage: a the permanent pole-to-ground fault, b the permanent pole-to-pole fault, c the nonpermanent pole-to-ground fault, d the nonpermanent pole-to-pole fault, e the permanent pole-to-ground fault with only the local residual dc current breaker being reclosed, f the nonpermanent pole-to-ground fault with only the local residual dc current breaker being reclosed

Differently as shown in Fig. 10.5c, if the fault is a nonpermanent pole-to-ground fault, and has disappeared, the steady-state characteristics of the tripped DCCB and the fault line can be both equivalent to the resistor. Because during the dc steady state, the shunt capacitors in the DCCB and dc line can be both considered as the open circuits. In addition, the inductances (L F , L, M) can be omitted for steady-state characteristic analysis. And the series resistance R can also be omitted because it is much smaller than the DCCB arrester equivalent resistance. So under this condition, the residual voltage U p_r during steady state can be expressed as Up_ r =

1/2G Udc Udc · = ·RA2 2 1/2G + RA1 //RA2 2 + 4G · RRA1A1+R . A2

(10.4)

10.2 Analysis of the Fault Line Residual Voltage Steady-State Characteristic

253

Similarly, under this condition, the DCCB arrester is also in the small current area, which means RA1 and RA2 are fixed values. For the nonpermanent pole-to-pole fault condition, the residual voltage U p_r during steady state can be expressed as Up_ r = Udc ·

Udc 1/2G = ·RA2 1/G + 2(RA1 //RA2 ) 2 + 4G · RRA1A1+R A2

(10.5)

According to (10.4) and (10.5), the residual voltages (steady state) under the nonpermanent pole-to-ground and pole-to-pole fault conditions are the same. It should be pointed out that, the analysis above is based on the condition the residual dc current breakers at both ends of the fault line are reclosed. If only the local (for the reclosing strategy) residual dc current breaker is reclosed, the oppositeend DCCB is still physically opened, as shown in Fig. 10.5e, f. So RA1 //RA2 in (10.2)–(10.5) should be represented by RA1 , namely, Up_ r =

Udc 1   · 1 2 RA1 · Rg + 2G + 1

(10.6)

Up_ r =

1 Udc   · 2 2R · 1 + G + 1 A1 Rg

(10.7)

Udc 2 + 4G · RA1

(10.8)

Up_ r =

respectively. Obviously, it is different from the condition the residual dc current breakers at both ends of the fault line are reclosed. Based on (10.2)–(10.8), the residual voltage U p_r during steady state after the residual dc current breaker being reclosed under different conditions can be calculated. Figure 10.6a shows the residual voltage U p_r (steady state) in the ±400 kV flexible dc grid with different dc line lengths. Here, the V-I characteristic of the DCCB arrester is selected as listed in Table 10.2, which approximates the ASEA XAP-A metal oxide surge arrester. Correspondingly, it can be calculated that the values of RA1 and RA2 in the small current area are 440 k. In addition, the pole-to-ground conductance of the dc line is set as 1 × 10−8 S/km. According to (10.2), (10.3), (10.6) and (10.7), the steady-state residual voltage is obviously zero under metallic permanent fault condition, thus being not discussed in detail. In Fig. 10.6a, the transition impedance Rg is set as 300 . The calculation result shows that, even with high transition impedance, the residual voltage U p_r under the permanent fault condition is always approximately equal to zero (smaller than 1 kV). Differently, under the nonpermanent fault condition, U p_r is about hundredkilovolts level, which is much larger than that under the permanent fault condition. Therefore, this characteristic can be used for the DCCB reclosing strategy to identify the fault property (permanent or nonpermanent). In addition, with the line length

254

10 The DCCB Reclosing Strategy in VSC-HVDC Grid 400 both-side residual dc current breakers are reclosed

nonpermanent

Up_r(kV)

300

only the local residual dc current breaker is reclosed

200

100

permanent

0 100

200

300

400

500

600

700

800

900

1000

length (km)

(a) 400 nonpermanent

Up_r(kV)

300

200

100

permanent

0 100

200

300

400

500

600

(b)

700

800

900

1000

length (km)

Fig. 10.6 The residual voltage U p_r during steady state under different conditions: a RA1 and RA2 are the same, b RA1 and RA2 are different

Table 10.2 V-I characteristic of the DCCB arrester V (p.u.)

1.100, 1.600, 1.700, 1.739, 1.777, 1.815, 1.853, 1.881, 1.910, 1.948, 3.200

I (kA)

0.001, 0.01, 0.1, 0.2, 0.38, 0.65, 1.11, 1.50, 2.00, 2.80, 200.0

increasing, U p_r reduces gradually. And when only the local residual dc current breaker is reclosed, U p_r also reduces compared with the condition the residual dc current breakers at both ends of the fault line are reclosed. These characteristics should be considered when designing the DCCB reclosing strategy. It should be pointed out that, in Fig. 10.6a, the equivalent resistances of the DCCB arresters at two ends of the line are the same. In engineering practice, the capacities of DCCB arresters at different positions may be different, leading to different equivalent resistances, namely different RA1 and RA2 . For example, supposing that the capacity of DCCB arrester at the opposite end is twice as large as that of the local DCCB arrester, RA2 is 220 k under this condition, because two arresters shown as

10.2 Analysis of the Fault Line Residual Voltage Steady-State Characteristic

255

Table 10.2 should be parallel-connected to increase the capacity. Under this condition, RA2 is different from RA1 (440 k). The corresponding calculation results of U p_r are shown in Fig. 10.6b. Obviously, under permanent fault condition, U p_r during steady state is still approximately equal to zero, and it is hundred-kilovolts level under nonpermanent fault condition. This means when RA1 and RA2 are different, the residual voltage essential difference between permanent and nonpermanent faults still exists.

10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid 10.3.1 Working Principle of the Proposed DCCB Reclosing Strategy According to the residual voltage steady-state characteristics, this chapter proposes a novel DCCB reclosing strategy, which can identify the fault property and avoid the second damage to the system effectively. After dc faults, the fault line will be isolated quickly by the DCCB combining with the selective protection. The proposed DCCB reclosing strategy is then started. The detailed steps are as following. Step (1): Delay t 1 after opening the residual dc current breaker. Step (2): Reclose the residual dc current breaker. And then start the timer t. Step (3): Measure the residual voltage U p_r . And identify the fault property by comparing U p_r and the threshold value U set . Step (4): If U p_r > U set , for the reliability consideration, compare U p_r and U set for the second time after delay time t 2 . If U p_r > U set is still satisfied, it can be concluded that the fault is nonpermanent and the fault has disappeared. So the tripped DCCB can be reclosed. Step (5): If the condition described in step (4) is not satisfied during the delay time period t 3 from the start moment, the fault can be identified as permanent. So the residual dc current breaker should be opened again. In the proposed strategy, the delay time t 1 is introduced for the fault line to recover the insulation characteristic under the nonpermanent fault condition. And this delay time is typically in the range of 200–500 ms [5]. In addition, the delay time t 2 is suggested to be set as millisecond-level for the consideration of both the identification reliability and speed. While t 3 should be large enough (hundredmillisecond level is suggested), because there is a rising process for U p_r to exceed U set under the nonpermanent fault condition. The setting of the threshold value U set needs to distinguish the permanent fault and the nonpermanent fault. So U set should be larger than the steady-state residual voltage under high-impedance permanent fault. According to the analysis in Sect. 10.2, the steady-state residual voltage is approximately equal to zero under the permanent

256

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

fault condition (even with high transition impedance), while it is dozens-of-kilovolts to hundred-kilovolts level (in the ±400 kV dc grid) under the nonpermanent fault condition. So U set can be set as a very small value, in order to accelerate the DCCB reclosing under nonpermanent fault condition. In addition, the measurement error should also be considered in practical engineering. Therefore, the threshold value U set is set as k*U error , where k is the reliable coefficient and U error is the measurement error of the dc voltage sensor. At present, the measurement accuracy of the dc voltage sensor can be 2‰ level. For example, in the ±400 kV dc grid, U error is about 0.8 kV, which is even larger than the residual voltage under high-impedance permanent fault (only about 0.3 kV). Therefore, the residual voltage under the permanent fault condition can stay below k*U error reliably with the reliable coefficient k > 2, and that under the nonpermanent fault condition can rise above k*U error quickly.

10.3.2 Reclosing Cooperation Between the DCCBs on the Fault Line Firstly, it should be pointed out that, in the flexible dc grid, only the DCCBs on the fault line are tripped after the fault, due to the selective dc protection [8]. Therefore, only the DCCBs on the same line need to cooperate with each other during reclosing. According to Fig. 10.6, when only one-side residual dc current breaker is reclosed under nonpermanent fault condition, the residual voltage is smaller than that when the residual dc current breakers at both ends of the fault line are reclosed. However, this residual voltage value is still large enough to distinguish the nonpermanent fault from the permanent one. So it is tended to apply the reclosing strategy (proposed in Sect. 10.3.1) only for one of the two DCCBs on each dc line. For the DCCB on the other end of the line, it can determine to be reclosed or not, directly according to whether the voltage of the line recovers or not. In fact, in the ac system, the autoreclosing is also only configured for one of the two circuit breakers on each line, and the other one determines to be reclosed when the line voltage recovers to near the normal operation value. The detailed cooperation principle is shown in Fig. 10.7. In Fig. 10.7, the DCCB which applies the proposed reclosing strategy (proposed in Sect. 10.3.1) is named as DCCB1 , and the other one is named as DCCB2 . According to the proposed strategy, the residual dc current breaker in DCCB1 is reclosed for the fault property identification. If the fault is permanent, the residual voltage U p_r1 (the residual voltage at DCCB1 side) always keeps below U set , so the fault is identified as permanent by DCCB1 . And its residual dc current breaker is opened again. During the whole process, no reclosing control needs to be taken on the DCCB2 (including its residual dc current breaker). And because the line voltage (namely the residual voltage) at DCCB2 side (U p_r2 ) also keeps near zero, the DCCB2 will keep open all the time. Differently, if the fault is nonpermanent, the DCCB1 can identify it as nonpermanent quickly after the residual dc current breaker being reclosed, and then the DCCB1

10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid DCCB1

+ -

Up_r1

?

DCCB2

DCCB1

DCCB2 permanent

Up_r2 no control

reclosed

257

+

+

-

-

+

Up_r2

Up_r1

opened

not recover

not reclosed

nonpermanent

+

Up_r1

Up_r2

reclosed

DCCB2

DCCB1

DCCB2

DCCB1

+

+

-

-

Up_r1

recover

+

Up_r2

recover

reclosed

Fig. 10.7 The reclosing cooperation between the DCCBs on the fault line

is reclosed. After that, although the DCCB2 still keeps open, U p_r2 will recover to the dc grid normal operation voltage quickly, because the dc line has been re-connected to the dc grid by DCCB1 . Therefore, as long as U p_r2 recovers to exceed a threshold value, e.g. 0.8U dcpN , DCCB2 can be reclosed. By the above cooperation strategy, the DCCBs on the fault line can keep open under permanent fault condition, and be reclosed reliably under nonpermanent fault condition. Just like the ac-system auto-reclosing, no communication is needed for the designed cooperation strategy. Moreover, there is no additional requirement when selecting which is DCCB1 (configured with the reclosing strategy proposed in Sect. 10.3.1) and which is DCCB2 (not configured with the reclosing strategy proposed in Sect. 10.3.1), thus can be determined previously.

10.3.3 Influence of the Transient Process Under Permanent Fault Condition and the Improved Measure The analysis in Sect. 10.2 mainly focuses on the residual voltage steady-state characteristics after reclosing the residual dc current breaker. In fact, for the permanent fault, there is a transient oscillation process at the initial stage after the residual dc current breaker being reclosed. This may lead to negative influence on the proposed criterion in Sect. 10.3.1. Therefore, the transient characteristic of the permanent fault condition after the residual dc current breaker being reclosed is analyzed in this section, based on which the improved measure to eliminate the transient process influence is proposed.

258

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

(1) Pole-to-ground fault: Different from the steady-state characteristic analysis, the transient characteristic analysis cannot neglect the capacitors and the inductances. So the equivalent circuit of permanent pole-to-ground fault condition after the residual dc current breaker being reclosed should be expressed as Fig. 10.8a, b (the coupling influence is ignored). It should be noted that the equivalent circuit of the DCCB varies with different current directions. As shown in Fig. 10.8a, when the current on the main breaker flows from the dc bus to the dc line (positive pole for instance), the value of C D is the series capacitors value in the snubber circuits of IGBTs with the bus-to-line conduction direction in the main breaker. While the current does not flow through any resistors in the snubber circuits. Differently as shown in Fig. 10.8b, when the current direction is line-to-bus, the value of C D equals to the series capacitors value in the snubber circuits of all the IGBTs in the main breaker. And the value of RD is the series resistors value in the snubber circuits of IGBTs with the bus-to-line conduction direction. According to Fig. 10.8a, b, the transient process is fourth-order, so the complexfrequency-domain method is introduced. Figure 10.8c shows the equivalent circuit in the complex frequency domain, where the values of C D and RD are determined according to the current direction. Supposing the grounding point as the reference point, based on the node voltage method, the node-voltage equation at point A can be expressed as RA

RA R LF

LF

CD

+ Udc 2 -

C

G

Up_r C

+

G

-

RD CD

Udc 2

C

(a) sLF

LFi1(0-) -

+

Udc - 2s

+

I1(s)

L

R

L

G

Up_r C

G

(b) RD

1/sCD

ucD(0-)/s +

R

A

-

1/sC

Up_r(s)

+ -

sL I2(s)

Li2(0-) -

+

uc(0-)/s

(c) Fig. 10.8 The transient equivalent circuit of permanent pole-to-ground fault after the residual dc current breaker being reclosed: a equivalent circuit when the current direction is bus-to-line, b equivalent circuit when the current direction is line-to-bus, c equivalent circuit in the complex frequency domain

10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid

 1 s L F + RD + 1/sCD R + sL Li 2 (0−) u C (0−)/s Udc /2s + L F i 1 (0−) − u CD (0−)/s − + = s L F + RD + 1/sCD 1/sC R + sL 

1

Up_ r (s) ·

259

+ sC +

(10.9)

thus Up_ r (s) =

N (s) L F LCD C · s 4 + (L F RCD C + L RD CD C) · s 3 + (RD RCD C + LCD + LC + L F CD ) · s 2 + (RCD + RC + RD CD ) · s + 1

(10.10)

where   N (s) = u C (0−)L F LCD C · s 3 + i 1 (0−)L F LCD +u C (0−)L F RCD C + u C (0−)L RD CD C − i 2 (0−)L F LCD · s 2 

 + Udc /2 − u CD (0−) LC D +i 1 (0−)L F RCD + u C (0−)RD RCD C + u C (0−)LC − i 2 (0−)L RD CD   · s+ Udc /2 − u CD (0−) RC D + u C (0−)RC − i2(0−)L . (10.11)

Because the equivalent circuit will change between Fig. 10.8a, b repeatedly with the current direction changing, the initial values i1 (0− ), i2 (0− ), uCD (0− ) and uC (0− ) change continuously. So it is difficult to obtain the complete time-domain solution. However, it should be noted that there are only two fixed forms for the denominator of U p_r (s). Based on the partial fraction expansion method, the attenuation characteristic and frequency characteristic of U p_r (t) can be analyzed by analyzing the zero points of the denominator of U p_r (s), which is a quartic equation solving process. Supposing the zero points are 

s1 = −a1 + jb1 , s2 = −a2 + jb2 s3 = −a3 + jb3 , s4 = −a4 + jb4

(10.12)

where a1 –a4 and b1 –b4 are the indeterminate coefficients, the time-domain solution of U p_r (t) can be expressed as Up_ r (t) = A1 es1 t + A2 es2 t + A3 es3 t + A4 es4 t = A1 e−a1 t (cosb1 t + jsinb1 t)+A2 e−a2 t (cosb2 t + jsinb2 t) +A3 e−a3 t (cosb3 t + jsinb3 t)+A4 e−a4 t (cosb4 t + jsinb4 t)

(10.13)

According to (10.13), the attenuation coefficients (namely a1 –a4 ) and the oscillation frequencies (namely b1 –b4 ) of the residual voltage U p_r after the residual dc current breaker being reclosed under permanent fault condition can be calculated. It should be noted that, in the transient analysis above, the DCCB arrester, transition impedance (generally resistive in engineering practice) and the line conductance are neglected to reduce the analysis complexity. Obviously, the above-neglected components are all resistive. For the RLC transient oscillation process, the resistive

260

10 The DCCB Reclosing Strategy in VSC-HVDC Grid sLF

LFi1(0-)

1/sCD ucD(0-)/s

RD

+

-

+

I1(s)

+

Udc - 2s

- 2s +

-

Up_r(s)

+

1/sC +

I1(s)

LFi1(0-) sLF

uc(0-)/s

-

RD

-

+

ucD(0-)/s

1/sCD

+

-

uc(0-)/s

2Up_r(s)

-

Li2(0-)

sL I2(s)

1/sC -

+ Udc

R

A

B

I2(s) R

+

sL

-

Li2(0-)

Fig. 10.9 The complex-frequency-domain transient equivalent circuit of permanent pole-to-pole fault after the residual dc current breaker being reclosed

components mainly play the damping function, which accelerate the attenuation of the transient variables and shorten the duration of the oscillation. In another word, the duration of the transient oscillation without above components will be longer than that under the actual condition, and thus the influence on the proposed fault property identification criterion is more serious. Obviously, the designed measure according to this more serious condition can be more reliable for eliminating the transient oscillation influence. Therefore, it is feasible to neglect the above resistive components during transient analysis. (2) Pole-to-pole fault: Figure 10.8 shows the transient equivalent circuit of permanent pole-to-ground fault condition after the residual dc current breaker being reclosed. For permanent poleto-pole fault condition, the transient equivalent circuit is shown in Fig. 10.9. In Fig. 10.9, supposing point B as the reference point, the node-voltage equation at point A can be expressed as 

1 1 + sC/2 + 2Up_ r (s) · 2s L F + 2RD + 2/sCD 2R + 2s L Udc /s + 2L F i 1 (0−) − 2u CD (0−)/s = 2s L F + 2RD + 2/sCD 2Li 2 (0−) 2u C (0−)/s − + 2/sC 2R + 2s L



(10.14)

namely,  1 Up_ r (s) · + sC + s L F + RD + 1/sCD R + sL u C (0−)/s Udc /2s + L F i1(0−) − u CD (0−)/s Li 2 (0−) + = − s L F + RD + 1/sCD 1/sC R + sL 

1

(10.15)

10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid

261

Table 10.3 Parameters of the DCCB Max. breaking current (kA)

V GN (kV)

C D0 (µF)

RD0 (ohm)

Same-direction IGBTs number

20

2.5

40

5

320

which is the same as (10.9). Therefore, the transient oscillation characteristic of U p_r under permanent pole-to-pole fault condition is similar to that under the permanent pole-to-ground fault condition. For a ±400 kV dc grid, the typical parameters of the DCCB are selected as shown in Table 10.3 according to [3, 9, 10], where V GN is the rated voltage of the IGBT module, C D0 and RD0 are the capacitance and resistance of each snubber circuit. In addition, the dc line parameters are selected as r = 0.73 /km, l = 1.36 mH/km, and c = 8.6e−9 F/km. For permanent pole-to-ground fault, C D and RD in Fig. 10.8c are 0.125 µF and 0  when the current direction is bus-to-line, while they are 0.0625 µF and 1600  respectively when the current direction is line-to-bus. If the current limiting reactor L F is selected as 50 mH, and the fault distance is 200 km, the solutions of a1 –a4 and b1 –b4 can be obtained as (1, 1, 268, 268) and (−13,558, 13,558, 1910, −1910) when the current direction is bus-to-line. And when the current direction is line-to-bus, the solutions of a1 –a4 and b1 –b4 are (287, 287, 15981, 15981) and (2032, −2032, −8341, 8341). According to the solutions above, it can be found that all the components of U p_r (t) oscillate at some certain frequencies, and the smallest oscillation frequency is 1910 rad/s (304 Hz). Similar result can also be obtained under permanent pole-to-pole fault condition. Figure 10.10 shows the smallest oscillation frequency of U p_r (t) during transient process after the residual dc current breaker being reclosed under permanent fault condition with different fault distances and different current limiting reactor values. 2500

oscillation frequency (rad/s)

oscillation frequency (rad/s)

7000 6000 5000 4000 3000 2000 1000 0

50

200

400

600

(a)

800

1000

distance (km)

2000 1500 1000 500 0

100

200

300

(b)

400

500

LF (mH)

Fig. 10.10 The smallest oscillation frequency of U p_r (t) during transient process after the residual dc current breaker being reclosed under permanent fault condition: a with different fault distances, b with different current limiting reactor values L F

262

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

According to Fig. 10.10a, with the fault distance increasing, the smallest oscillation frequency of U p_r (t) decreases gradually. But it is still much larger than zero even if the fault distance is 1000 km. Figure 10.10b shows that the current limiting reactor value almost has no effect on the smallest oscillation frequency. (3) Improved measure: Due to the above transient process of U p_r , the fault property identification criterion may identify the permanent fault as nonpermanent by mistake. The effective measure should be taken for improving the reliability of the proposed criterion. Therefore, the low-pass filtering for the measured residual voltage is introduced before U p_r and the threshold value U set are compared in the proposed criterion, where the cutoff frequency equals the calculated smallest oscillation frequency divided by a reliable coefficient. Obviously, for the nonpermanent fault, there will be a dc steady-state component in U p_r during the whole process after the residual dc current breaker being reclosed. This means the low-pass filtering for the measured residual voltage will not affect the correct identification of the proposed criterion under nonpermanent fault condition. But for the permanent fault, the low-pass filtering can filter out the oscillation components of U p_r , to eliminate the influence of the transient oscillation, and guarantee that the proposed criterion will not identify it as nonpermanent by mistake. Finally, the proposed DCCB reclosing strategy is designed as Fig. 10.11. According to the analysis above, the change of the parameters, such as the arrester rating, the dc line length and the transition impedance, will lead to the change of the residual voltage value. However, they do not change the residual voltage essential characteristics used in the proposed reclosing strategy, including, the steady-state residual voltage under permanent fault is much smaller than that under the nonpermanent fault, and there is a transient oscillation under permanent fault whose influence can be eliminated by the low-pass filtering. Therefore, the proposed reclosing strategy has strong robustness against the change of the corresponding parameters.

10.3.4 Transient Current Analysis In the traditional reclosing strategy, the DCCB is completely reclosed directly for fault property identification. It means the residual dc current breaker and main breaker are all reclosed, so large secondary overcurrent will occur under the permanent fault condition. Differently, in the proposed reclosing strategy, only the residual dc current breaker is reclosed for fault property identification. As the DCCB arrester is still connected in the dc line during this period, it is obvious that the steady-state current is very small, even under the permanent fault condition. In addition, as analyzed above, at the initial stage after the residual dc current breaker being reclosed, there will be a transient current. Under the permanent fault condition, this transient current is obviously the largest when the fault is a metallic

10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid

263

Fig. 10.11 The flow chart of the proposed DCCB reclosing strategy

fault close to the DCCB (i.e., 0 km from the DCCB). Therefore, the maximum transient current can be estimated according to this condition, where the line parameters R, sL and 1/sC shown in Fig. 10.8c (also in Fig. 10.9) can be omitted. It means the maximum transient current estimation is simplified to second-order, namely, I1 (s) =

Udc /2s s L F + RD + 1/sCD

(10.16)

264

1.2

CD=0.3125μF (CD0=100μF)

1

Current (kA)

Fig. 10.12 Transient current estimation after the residual dc current breaker being reclosed

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

CD=0.25μF (CD0=80μF)

0.8

CD=0.1875μF (CD0=60μF)

0.6

CD=0.125μF (CD0=40μF)

0.4

CD=0.0625μF (CD0=20μF) CD=0.03125μF (CD0=10μF)

0.2 0

0

0.1

0.2

0.3

0.4

Time (ms)

where the values of RD and C D change with the transient current direction changing. For a second-order transient process, the maximum transient current occurs in the first half cycle, during which RD = 0 and C D equals to the series capacitors value in the snubber circuits of IGBTs with bus-to-line conduction direction. Therefore, the maximum transient current can be estimated as i 1 (t) =

Udc sinωt 2ωL F

(10.17)

√ where ω = 1/ L F C D . For the ±400 kV dc grid, the maximum transient current is calculated as shown in Fig. 10.12, with different values of C D (and L F = 50 mH). As the calculation result showing, with the value of C D increasing, the transient current increases gradually. For example, when C D = 0.0625 µF (C D0 = 20 µF), the maximum transient current is about 0.45 kA, and it increases to about 1 kA when C D = 0.3125 µF (C D0 = 100 µF). However, according to the design principle of DCCB [10], the value of capacitor for each snubber circuit (C D0 ) is at about dozensof-µF level, so the maximum transient current is at the level smaller than 1 kA in the ±400 kV dc grid. In addition, in the above analysis, the resistances, such as the conducting resistance of the diodes in snubber circuits, are neglected, which means the actual transient current is smaller. Obviously, for the ±400 kV dc grid, 1 kA current is in the normal operation current level, thus being not an overcurrent. Under the nonpermanent fault condition, the transient current can be approximately considered as the charging current to the capacitors of the DCCB snubber circuits and transmission line. Moreover, it should be noted that, the snubber circuits capacitor and the transmission line capacitor are series-connected for the transient current under this condition. So the equivalent total capacitance for the transient current analysis is smaller than the equivalent capacitance of the snubber circuits, i.e., smaller than C D . In complex frequency domain, the smaller the capacitance is, the larger the equivalent impedance will be, correspondingly, the smaller the transient current will be. In a word, the transient current, after the residual dc current breaker is reclosed under the nonpermanent fault condition, is smaller than the result as estimated in Fig. 10.12.

10.3 A Novel Reclosing Strategy of the DCCB in VSC-HVDC Grid

265

According to the analysis above, in the proposed reclosing strategy, the overcurrent will not occur when the residual dc current breaker is reclosed, and the power electronic devices will not suffer from the large secondary current. In summary, compared with the traditional strategy which recloses the DCCB directly, the proposed strategy can identify the fault property without completely reclosing the DCCB, thus thoroughly avoiding the second damage to the system. Moreover, compared with the sequential auto-reclosing strategy in [5], the proposed strategy significantly reduces the additional control and design requirements on the DCCB. So it is more suitable for the engineering application.

10.4 Case Study The CIGRE B4 dc grid test system described in [11] is built based on PSCAD/EMTDC, whose topology and parameters are shown as Fig. 10.13 and Table 10.4. The detailed parameters of this test system can be found in [11]. The frequency dependent model shown in Fig. 10.13 is used for the overhead line. And Cm-C1

Cm-A1

~

= AC/DC converter

=

=

= DC/DC converter

dc sym. monopole dc bipole ac onshore ac offshore cable overhead line

DCCB

G1 C1 0.450[m]

Bb-A1

f4

500km

f2 Bb-B4

f1 f3

LineB1-B4 200km

~

300km

LineA1-B1 400km

~

200km

~

=

=

=

Cd-B1

200km

Tower DC12 Conductors:chukar 30[m] Ground_Wires:3/8_High StrengthSteel 0[m]

Cb-B2

~ ~

=

=

~ 200km

200km

= ~

Cm-B2

=

Cm-B3

Bm-B3

f5

100km

f6

=

Cm-E1 Cm-F1

Bm-B5

LineB3-B5

=

= Cd-E1

200km

Bb-B2

=

Cb-D1

Bb-B1 Cb-B1

300km

Cb-C2

200km

G2

9[m] 7[m] 10[m] C2

=

= Cb-A1

Mid-Span Sag: 20[m] for conductors 14[m] for Ground Wires

~

200km

100km

~

=

Fig. 10.13 CIGRE B4 dc grid test system

Table 10.4 Parameters of the CIGRE B4 dc grid test system

Parameter

Value

Rated dc voltage/kV

±400 (dc bipole), ±200 (dc sym. monopole)

Rated ac voltage/kV

380 (onshore), 145 (offshore)

Power rating/MVA

CmA1: 800, Cm-C1: 800 Cm-B2: 800, Cm-B3: 1200 Cm-E1: 200, Cm-F1: 800 Cb-A1: 2 * 1200, Cb-B1: 2 * 1200 Cb-B2: 2 * 1200, Cb-C2: 2 * 400 Cb-D1: 2 * 800

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10 The DCCB Reclosing Strategy in VSC-HVDC Grid

the hybrid DCCB shown as Fig. 10.3a is also built, whose parameters are listed in Tables 10.2 and 10.3. In the simulation model, different kinds of dc faults (permanent and nonpermanent, pole-to-ground and pole-to-pole, metallic and high-impedance) at different locations are simulated to verify the correctness of the theoretical analysis, as well as the superiority and robustness of the proposed reclosing strategy. In addition, it should be pointed out that, the fault probability on the cable is much lower compared with the overhead line, and most of the faults on the cable are permanent [12]. Generally, the auto-reclosing is not applied on cables in the ac system. Similarly, in this chapter, the theoretical analysis and DCCB reclosing strategy are researched mainly for the overhead line. And the simulation case study mainly discusses the faults on the overhead lines.

10.4.1 Damage of Reclosing the DCCB Directly Generally in ac system, the tripped circuit breaker is reclosed directly, because the fault damage in ac system is acceptable. So in this case, the permanent pole-to-ground fault on LineB1–B4 (f 1 , 20 km from the dc bus Bb-B1) is set to happen at t = 2 s, and the DCCB is reclosed directly at t = 2.406 s. As shown in Fig. 10.14, the second overcurrent in the flexible dc grid is very large under the permanent fault condition. However, the widely-used power electronic devices in the flexible dc grid are very

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Fig. 10.14 Simulation results after the DCCB being reclosed directly under permanent fault condition: a dc current I dc on LineB1–B4 (kA), b arm currents iarm (kA), c ac currents is (kA)

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vulnerable to the overcurrent. Obviously, it is not appropriate to reclose the DCCB directly for re-connecting the fault line, due to the serious second damage under the permanent fault condition.

10.4.2 The Residual Voltage Characteristics

(b) permanent

(a) nonpermanent

In this case, the nonpermanent and permanent faults on dc line LineB1–B4 are simulated. The residual dc current breaker in the DCCB on LineB1–B4 (close to the bus Bb-B1) is reclosed 400 ms after being tripped. But the remaining part of the proposed reclosing strategy is not applied, to observe the steady-state and transient characteristics of the residual voltage. As shown in Fig. 10.15a, the nonpermanent pole-toground fault (f 2 , 200 km from the dc bus Bb-B1) is set to happen at t = 2 s. After the residual dc current breaker being reclosed, U p_r1 (the residual voltage at the side close to Bb-B1) will recover to the steady-state value 211 kV, which is very close to the calculated value 213 kV. In addition, according to the parameters of LineB1–B4 shown in Fig. 10.13, it can be calculated that the smallest oscillation frequency under permanent fault is 304 Hz, and thus the cutoff frequency of the low-pass filter is selected as 61 Hz (the reliable coefficient is 5). As Fig. 10.15a showing, the filtering value U p_r1_f also increases above the threshold value U set (set as 10 kV in this chapter) quickly after the residual dc current breaker being reclosed at t = 2.406 s, because the low-pass filtering will only filter out the oscillation components, and pass the dc component of the residual voltage. This means the proposed reclosing strategy with the low-pass filtering step can still identify the nonpermanent fault reliably. As shown in Fig. 10.15b, if the fault is permanent, the steady-state residual voltage after the residual dc current breaker being reclosed is approximately equal to zero. 600 400 200 0 -200 -400 -600 800 600 400 200 0 -200 -400 -600

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Fig. 10.15 Simulation results of the residual voltage after the residual dc current breaker being reclosed under pole-to-ground fault: a residual voltage under nonpermanent fault (kV), b residual voltage under permanent fault (kV)

10 The DCCB Reclosing Strategy in VSC-HVDC Grid (a) nonpermanent

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Fig. 10.16 Simulation results of the residual voltage after the residual dc current breaker being reclosed under pole-to-pole fault: a residual voltage under nonpermanent fault (kV), b residual voltage under permanent fault (kV)

But at the initial stage, the residual voltage U p_r1 has an oscillation process, with the oscillation frequency about 333 Hz (very close to the calculated result 304 Hz). This may cause the strategy to identify the permanent fault as nonpermanent by mistake. Differently, the filtering value U p_r1_f always keeps near zero. It means the influence of the transient oscillation process on the fault property identification can be eliminated effectively by adding the low-pass filtering step. As shown in Fig. 10.16, the residual voltage characteristics are similar under the pole-to-pole fault condition. It should be noted that, the arrester is considered when building the DCCB model. The simulation results show that the introduced low-pass filter with the selected cutoff frequency can eliminate the influence of transient oscillation reliably. It indicates that the DCCB arrester will not affect the correct action of the designed measure.

10.4.3 Performance of the Proposed Reclosing Strategy In this case, the complete proposed reclosing strategy and DCCBs cooperation strategy are applied. For the LineB1–B4 , the DCCB close to the bus Bb-B1 is selected as the DCCB1 (described in Sect. 10.3.2), and the DCCB close to the bus Bb-B4 is selected as DCCB2 . In the proposed reclosing strategy, t 1 , t 2 , and t 3 are set as 400 ms, 2 ms, and 100 ms respectively, and U set is set as 10 kV. In addition, as discussed in Sect. 10.4.2, the cutoff frequency of the low-pass filter is selected as 61 Hz. Figure 10.17 shows the performance of the proposed reclosing strategy under the permanent pole-to-ground fault at f 1 (happens at t = 2 s). As Fig. 10.17a showing, after the residual dc current breaker being reclosed at t = 2.406 s, U p_r1_f (at the side close to Bb-B1) always keeps below U set . So the proposed strategy can identify the fault as permanent correctly. In addition, as Fig. 10.17b showing, the residual

269 600 400 200 0 -200 -400 -600 600 400 200 0 -200 -400 -600 20

(e) is (kA)

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10.4 Case Study reclose the residual dc current breaker 50 10 0 2.406

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Fig. 10.17 Performance of the proposed reclosing strategy under the permanent pole-to-ground fault condition: a residual voltage at the side close to Bb-B1 (kV), b residual voltage at the side close to Bb-B4 (kV), c dc current Idc on LineB1–B4 (kA), d arm currents iarm (kA), e ac currents is (kA)

voltage U p_r2 (the residual voltage at the side close to Bb-B4) also keeps near zero, so the corresponding DCCB always keeps open. Moreover, as shown in Fig. 10.17c, the second dc current, after the residual dc current breaker being reclosed, is very small, because the main parts (main breaker and bypass current path) of the DCCB are not reclosed. Similarly, as shown in Fig. 10.17d, e, the second overcurrents also do not occur on the converter arms and at the ac side. It means that, with the proposed reclosing strategy, the power electronic devices will not suffer from the secondary overcurrent even under permanent fault condition. This is the core advantage of the proposed reclosing strategy compared with the traditional strategy which recloses the DCCB directly. Differently as shown in Fig. 10.18, under the nonpermanent fault condition, U p_r1_f increases above U set (10 kV) quickly after the residual dc current breaker

10 The DCCB Reclosing Strategy in VSC-HVDC Grid

(c) dc current (kA)

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Fig. 10.18 Performance of the proposed reclosing strategy under the nonpermanent pole-to-ground fault condition: a residual voltage at the side close to Bb-B1 (kV), b residual voltage at the side close to Bb-B4 (kV), c dc current (kA)

being reclosed, so the proposed strategy identifies the fault as nonpermanent at t = 2.417 s reliably. Then the DCCB close to Bb-B1 is reclosed, and the dc voltage recovers to the normal operation value quickly. It should be noted that, after the residual dc current breaker is reclosed, the residual voltage increases not very fast. However, according to the theoretical analysis, the steady-state residual voltage under permanent fault condition is approximately equal to zero even with high transition impedance (the influence of transient oscillation can be eliminated by the introduced low-pass filtering). Therefore, the threshold value U set can be a small value, to guarantee the proposed criterion can act quickly (about 11 ms in this case) under the nonpermanent fault condition. In addition, as shown in Fig. 10.18b, although the residual dc current breaker close to Bb-B4 is not reclosed for fault property identification, U p_r2 recovers above 320 kV (0.8U dcpN ) quickly after the DCCB close to Bb-B1 is reclosed, so the DCCB close to Bb-B4 can also be reclosed. Then the dc current of LineB1–B4 recovers as shown in Fig. 10.18c. Obviously, during the whole reclosing process, the DCCBs at both ends of LineB1–B4 are reclosed reliably without any communication. In addition, Fig. 10.18c also shows that, when the residual dc current breaker is reclosed under the nonpermanent fault condition, the transient current is very small (smaller than 0.2 kA), which obviously will not cause damage to the power electronic devices in the system. Figure 10.19a, b show the performances of the proposed reclosing strategy under pole-to-pole faults, which verify that the proposed strategy is also feasible for the pole-to-pole fault conditions.

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10.4 Case Study

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Fig. 10.19 Performances of the proposed reclosing strategy under the pole-to-pole faults: a permanent fault, b nonpermanent fault

10.4.4 Robustness of the Proposed Reclosing Strategy In this section, different kinds of dc faults at different locations are simulated to verify the robustness of the proposed reclosing strategy. (1) Remote fault: Figure 10.20a shows the simulation result of the permanent pole-to-ground fault at f 2 (200 km from Bb-B1). As the simulation result showing, the proposed reclosing strategy can identify the fault as permanent reliably because U p_r1_f always keeps below U set after the residual dc current breaker being reclosed. It verifies that the proposed reclosing strategy is effective for different fault distance. It should be noted that, under the nonpermanent fault condition, it is considered that the fault has disappeared during fault property identification. This means the fault distance obviously has no influence on the reclosing strategy under nonpermanent fault condition, thus being not discussed additionally. (2) High-impedance fault: Figure 10.20b shows the simulation result of the permanent pole-to-ground fault with 300  transition impedance. As the simulation result

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Fig. 10.20 Performances of the proposed reclosing strategy under weak fault conditions: a remote permanent fault, b permanent fault with 300  transition impedance

showing, after the residual dc current breaker being reclosed, the residual voltage during steady state also keeps near zero under this condition. And the introduced lowpass filter with the selected cutoff frequency can eliminate the influence of the initialstage transient oscillation effectively (U p_r1_f keeps below U set reliably). Therefore, the fault can be identified as permanent reliably. It verifies that, the proposed reclosing strategy is also feasible for the high-impedance fault condition. (3) Double-circuit line scene: In the built CIGRE B4 dc grid test system, the LineA1-B1 is a double-circuit line, which means there are two single-circuit lines coupling with each other. Figure 10.21a–c are the performances of the proposed reclosing strategy under permanent serious fault (metallic fault at f 3 ), permanent weak fault (300  fault at f 4 ), and nonpermanent fault respectively on LineA1–B1 , where the DCCB on LineA1–B1 close to Bb-B1 is selected as DCCB1 and the DCCB close to Bb-A1 is selected as DCCB2 . The simulation results show that the proposed reclosing strategy can identify the fault property and then determine to reclose the

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10.4 Case Study

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Fig. 10.21 Performances of the proposed reclosing strategy for the double-circuit line: a permanent serious fault (metallic fault at f 3 ), b permanent weak fault (300  fault at f 4 ), c nonpermanent fault

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DCCB or not correctly under different faults. It indicates that the coupling between lines has no influence on the correct action of the proposed reclosing strategy. (4) Monopole dc system: The above cases are all in the bipole dc system as shown in Fig. 10.13. Therefore, the feasibility of the proposed strategy in the monopole dc system is discussed in this case. The pole-to-pole fault in the monopole system is equivalent to the pole-to-ground fault in the bipole system, thus being not carried out anymore. Figure 10.22a–c are the performances of the proposed reclosing strategy under permanent pole-to-ground serious fault (metallic fault at f 5 ), permanent weak fault (300  fault at f 6 ), and nonpermanent fault respectively on LineB3–B5 (this line is in the monopole part of the test system as shown in Fig. 10.13), where the DCCB on LineB3–B5 close to Bm-B3 is selected as DCCB1 and the DCCB close to Bm-B5 is selected as DCCB2 . The simulation results verify that the proposed reclosing strategy is also feasible in the monopole dc system. In addition, in the monopole dc system, the DCCB parameters will change compared with that in the bipole system, such as the arrester equivalent resistance, the snubber circuits capacitors value C D and the snubber circuits resistors value RD , because the dc voltage rated value is different. This condition indicates that the proposed strategy is effective with the DCCB parameters changing. 300 200 100 0 -100 -200 -300 2

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Fig. 10.22 Performances of the proposed reclosing strategy in the monopole dc system: a permanent serious fault (metallic fault at f 5 ), b permanent weak fault (300  fault at f 6 ), c nonpermanent fault

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The above simulation cases verify that the proposed reclosing strategy has strong robustness against different system parameters, different fault kinds, as well as different fault locations.

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