PIC16F1847 Microcontroller-Based Programmable Logic Controller: Intermediate Concepts 9780367506438, 9780367506445

Table of contents :
Cover
Half Title
Title Page
Copyright Page
Table of Contents
Prologue
Preface
About the Author
Background and Use of the Book
References
Chapter 1 Arithmetical Macros
Introduction
1.1 Macro “R1addR2”
1.2 Macro “R1addR2_16”
1.3 Macro “RaddK”
1.4 Macro “RaddK_16”
1.5 Macro “R1subR2”
1.6 Macro “R1subR2_16”
1.7 Macro “RsubK”
1.8 Macro “RsubK_16”
1.9 Macro “R1mulR2”
1.10 Macro “DivU16by8”
1.11 Macro “incR”
1.12 Macro “incR_16”
1.13 Macro “decR”
1.14 Macro “decR_16”
1.15 Macro “Hbit_CNT” (High Bit Counter)
1.16 Macro “Lbit_CNT” (Low Bit Counter)
1.17 Examples for Arithmetical Macros
1.17.1 Example 1.1
1.17.2 Example 1.2
1.17.3 Example 1.3
1.17.4 Example 1.4
1.17.5 Example 1.5
1.17.6 Example 1.6
1.17.7 Example 1.7
1.17.8 Example 1.8
1.17.9 Example 1.9
References
Chapter 2 Logical Macros
Introduction
2.1 Macro “R1andR2”
2.2 Macro “RandK”
2.3 Macro “R1nandR2”
2.4 Macro “RnandK”
2.5 Macro “R1orR2”
2.6 Macro “RorK”
2.7 Macro “R1norR2”
2.8 Macro “RnorK”
2.9 Macro “R1xorR2”
2.10 Macro “RxorK”
2.11 The Macro “R1xnorR2”
2.12 Macro “RxnorK”
2.13 Macro “invR”
2.14 An Example for Logical Macros
Chapter 3 Shift and Rotate Macros
Introduction
3.1 Macro “Ashift_R” (Arithmetic Shift Right Rin)
3.2 Macro “Ashift_R_16” (Arithmetic Shift Right Rin)
3.3 Macro “Lshift_R” (Logical Shift Right Rin)
3.4 Macro “Lshift_R_16” (Logical Shift Right Rin)
3.5 Macro “Lshift_L” (Logical Shift Left Rin)
3.6 Macro “Lshift_L_16” (Logical Shift Left Rin)
3.7 Macro “shift_R” (Shift Right Rin)
3.8 Macro “shift_R_16” (Shift Right Rin)
3.9 Macro “shift_L” (Shift Left Rin)
3.10 Macro “shift_L_16” (Shift Left Rin)
3.11 Macro “rotate_R” (Rotate Right Rin)
3.12 Macro “rotate_R_16” (Rotate Right Rin)
3.13 Macro “rotate_L” (Rotate Left Rin)
3.14 Macro “rotate_L_16” (Rotate Left Rin)
3.15 Macro “Swap”
3.16 Examples for Shift and Rotate Macros
3.16.1 Example 3.1
3.16.2 Example 3.2
3.16.3 Example 3.3
3.16.4 Example 3.4
3.16.5 Example 3.5
3.16.6 Example 3.6
3.16.7 Example 3.7
Chapter 4 Selection Macros
Introduction
4.1 Macro “move_R” (Move)
4.2 Macro “load_R” (Load)
4.3 Macro “select” (Selection of One of Two 8-Bit Input Variables)
4.4 Macro “select_16” (Selection of One of Two 16-Bit Input Variables)
4.5 Macro “max _5” (Maximum in Five 8-Bit Variables)
4.6 Macro “max_10” (Maximum in Ten 8-Bit Variables)
4.7 Macro “max_N80” (Maximum in N 8-Bit Variables, N = 2, 3, …, 80)
4.8 Macro “max_N40_16” (Maximum in N 16-Bit Variables, N = 2, 3, …, 40)
4.9 Macro “max_N255” (Maximum in N 8-Bit Variables, N = 2, 3, …, 255)
4.10 Macro “max_N255_16” (Maximum in N 16-Bit Variables, N = 2, 3, …, 255)
4.11 Macro “min _5” (Minimum in Five 8-Bit Variables)
4.12 Macro min_10” (Minimum in Ten 8-Bit Variables)
4.13 Macro “min_N80” (Minimum in N 8-Bit Variables, N = 2, 3, …, 80)
4.14 Macro “min_N40_16” (Minimum in N 16-Bit Variables, N = 2, 3, …, 40)
4.15 Macro “min_N255” (Minimum in N 8-Bit Variables, N = 2, 3, …, 255)
4.16 Macro “min_N255_16” (Minimum in N 16-Bit Variables, N = 2, 3, …, 255)
4.17 Macro “limiter”
4.18 Macro “limiter_16”
4.19 Multiplexer Macros
4.20 Macro “mux_2_1”
4.21 Macro “mux_2_1_E”
4.22 Macro “mux_4_1”
4.23 Macro “mux_4_1_E”
4.24 Macro “mux_8_1”
4.25 Macro “mux_8_1_E”
4.26 Macro “mux_16_1”
4.27 Macro “mux_16_1_E”
4.28 Macro “B_mux_2_1_E”
4.29 Macro “B_mux_4_1_E”
4.30 Macro “B_mux_8_1_E”
4.31 Examples for Selection Macros
4.31.1 Example 4.1
4.31.2 Example 4.2
4.31.3 Example 4.3
4.31.4 Example 4.4
4.31.5 Example 4.5
4.31.6 Example 4.6
4.31.7 Example 4.7
4.31.8 Example 4.8
4.31.9 Example 4.9
4.31.10 Example 4.10
4.31.11 Example 4.11
4.31.12 Example 4.12
4.31.13 Example 4.13
4.31.14 Example 4.14
4.31.15 Example 4.15
4.31.16 Example 4.16
4.31.17 Example 4.17
4.31.18 Example 4.18
4.31.19 Example 4.19
4.31.20 Example 4.20
4.31.21 Example 4.21
4.31.22 Example 4.22
Chapter 5 Demultiplexer Macros
Introduction
5.1 Macro “Dmux_1_2” (1×2 DMUX)
5.2 Macro “Dmux_1_2_E” (1×2 DMUX with Enable Input)
5.3 Macro “Dmux_1_4” (1×4 DMUX)
5.4 Macro “Dmux_1_4_E” (1×4 DMUX with Enable Input)
5.5 Macro “Dmux_1_8” (1×8 DMUX)
5.6 Macro “Dmux_1_8_E” (1×8 DMUX with Enable Input)
5.7 Macro “Dmux_1_16” (1×16 DMUX)
5.8 Macro “Dmux_1_16_E” (1×16 DMUX with Enable Input)
5.9 Macro “B_Dmux_1_2_E” (1×2 Byte DeMultiplexer with Enable Input)
5.10 Macro “B_Dmux_1_4_E” (1×4 Byte DeMultiplexer with Enable Input)
5.11 Macro “B_Dmux_1_8_E” (1×8 Byte DeMultiplexer with Enable Input)
5.12 Macro “Dispatcher_1_8_E” (1×8 Dispatcher with Enable Input)
5.13 Macro “Patcher_8_1_E” (8×1 Patcher with Enable Input)
5.14 Examples for Demultiplexer Macros
5.14.1 Example 5.1
5.14.2 Example 5.2
5.14.3 Example 5.3
5.14.4 Example 5.4
5.14.5 Example 5.5
5.14.6 Example 5.6
5.14.7 Example 5.7
5.14.8 Example 5.8
5.14.9 Example 5.9
Chapter 6 Conversion Macros
Introduction
6.1 Macro “Conv_UsInt_2_BCD_U” (Unsigned Short Integer to Unpacked BCD Conversion)
6.2 Macro “Conv_UsInt_2_BCD_P” (Unsigned Short Integer to Packed BCD Conversion)
6.3 Macro “Conv_UInt_2_BCD_U” (Unsigned Integer to Unpacked BCD Conversion)
6.4 Macro “Conv_UInt_2_BCD_P” (Unsigned Integer to Packed BCD Conversion)
6.5 Macro “Conv_BCD_U_2_UInt” (5-Digit Unpacked BCD to Unsigned Integer Conversion)
6.6 Macro “Conv_BCD_P_2_UInt” (5-Digit Packed BCD to Unsigned Integer Conversion)
6.7 Seven-Segment LED Displays
6.8 Macro “Segment_CCD” (Segment_CCD Instruction)
6.9 Macro “Segment_CAD” (Segment_CAD Instruction)
6.10 Macro “Conv_Bin_2_Gray” (Binary to Gray Code Conversion)
6.11 Macro “Conv_Bin_2_Gray_16” (Binary to Gray Code Conversion)
6.12 Macro “Conv_Gray_2_Bin” (Gray Code to Binary Conversion)
6.13 Macro “Conv_Gray_2_Bin_16” (Gray Code to Binary Conversion)
6.14 Examples for Conversion Macros
6.14.1 Example 6.1
6.14.2 Example 6.2
6.14.3 Example 6.3
6.14.4 Example 6.4
6.14.5 Example 6.5
6.14.6 Example 6.6
6.14.7 Example 6.7
6.14.8 Example 6.8
6.14.9 Example 6.9
6.14.10 Example 6.10
6.14.11 Example 6.11
6.14.12 Example 6.12
References
Index

Citation preview

PIC16F1847 Microcontroller-Based Programmable Logic Controller

PIC16F1847 Microcontroller-Based Programmable Logic Controller Intermediate Concepts

Murat Uzam

First edition published 2021 by CRC Press 6000 Broken Sound Parkway NW, Suite 300, Boca Raton, FL 33487-2742 and by CRC Press 2 Park Square, Milton Park, Abingdon, Oxon, OX14 4RN © 2021 Taylor & Francis Group, LLC First edition published by CRC Press 2021 CRC Press is an imprint of Taylor & Francis Group, LLC Reasonable efforts have been made to publish reliable data and information, but the author and publisher cannot assume responsibility for the validity of all materials or the consequences of their use. The authors and publishers have attempted to trace the copyright holders of all material reproduced in this publication and apologize to copyright holders if permission to publish in this form has not been obtained. If any copyright material has not been acknowledged please write and let us know so we may rectify in any future reprint. Except as permitted under U.S. Copyright Law, no part of this book may be reprinted, reproduced, transmitted, or utilized in any form by any electronic, mechanical, or other means, now known or hereafter invented, including photocopying, microflming, and recording, or in any information storage or retrieval system, without written permission from the publishers. For permission to photocopy or use material electronically from this work, access www.copyright.com or contact the Copyright Clearance Center, Inc. (CCC), 222 Rosewood Drive, Danvers, MA 01923, 978-750-8400. For works that are not available on CCC please contact [email protected] Trademark notice: Product or corporate names may be trademarks or registered trademarks, and are used only for identifcation and explanation without intent to infringe. ISBN: 9780367506438 (hbk) ISBN: 9780367506445 (ebk) Typeset in Times by Deanta Global Publishing Services, Chennai, India Visit the Routledge website at: PIC16F1847 Microcontroller-Based Programmable Logic Controller: Intermediate Concepts, 1/E (9780367506438) https://www.routledge.com/9780367506438

To the memory of my beloved father, Mehmet Uzam (1937–2017) to my mother, Zeynep Uzam to my family who love and support me and to my teachers and students who enriched my knowledge

Contents Prologue ................................................................................................................. xiii Preface...................................................................................................................... xv About the Author ...................................................................................................xvii Background and Use of the Book ...........................................................................xix References .......................................................................................xxvi Chapter 1

Arithmetical Macros ............................................................................ 1 Introduction ..........................................................................................1 1.1 Macro “R1addR2” ....................................................................2 1.2 Macro “R1addR2_16” ..............................................................3 1.3 Macro “RaddK” ........................................................................5 1.4 Macro “RaddK_16” ..................................................................6 1.5 Macro “R1subR2” ....................................................................7 1.6 Macro “R1subR2_16” ...............................................................8 1.7 Macro “RsubK” ....................................................................... 10 1.8 Macro “RsubK_16” ................................................................ 10 1.9 Macro “R1mulR2” ................................................................. 12 1.10 Macro “DivU16by8” ............................................................... 14 1.11 Macro “incR” .......................................................................... 15 1.12 Macro “incR_16” .................................................................... 16 1.13 Macro “decR” ......................................................................... 17 1.14 Macro “decR_16” ................................................................... 19 1.15 Macro “Hbit_CNT” (High Bit Counter) ................................. 19 1.16 Macro “Lbit_CNT” (Low Bit Counter)................................... 30 1.17 Examples for Arithmetical Macros ......................................... 33 1.17.1 Example 1.1 ................................................................34 1.17.2 Example 1.2................................................................ 37 1.17.3 Example 1.3................................................................ 38 1.17.4 Example 1.4 ................................................................ 39 1.17.5 Example 1.5................................................................ 42 1.17.6 Example 1.6 ................................................................ 43 1.17.7 Example 1.7 ................................................................44 1.17.8 Example 1.8................................................................44 1.17.9 Example 1.9 ................................................................ 48 References .......................................................................................... 51

Chapter 2

Logical Macros................................................................................... 53 Introduction ........................................................................................ 53 2.1 Macro “R1andR2” .................................................................. 53 2.2 Macro “RandK” ...................................................................... 56 vii

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Contents

2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 Chapter 3

Macro “R1nandR2” ................................................................ 57 Macro “RnandK” ................................................................... 58 Macro “R1orR2” .....................................................................60 Macro “RorK” ........................................................................ 63 Macro “R1norR2” ...................................................................64 Macro “RnorK” ...................................................................... 65 Macro “R1xorR2” ...................................................................66 Macro “RxorK” ...................................................................... 69 The Macro “R1xnorR2” ......................................................... 71 Macro “RxnorK” .................................................................... 72 Macro “invR” ......................................................................... 73 An Example for Logical Macros ............................................. 76

Shift and Rotate Macros..................................................................... 85 Introduction ........................................................................................ 85 3.1 Macro “Ashift_R” (Arithmetic Shift Right Rin)..................... 86 3.2 Macro “Ashift_R_16” (Arithmetic Shift Right Rin)............... 87 3.3 Macro “Lshift_R” (Logical Shift Right Rin).......................... 89 3.4 Macro “Lshift_R_16” (Logical Shift Right Rin) ....................90 3.5 Macro “Lshift_L” (Logical Shift Left Rin)............................. 93 3.6 Macro “Lshift_L_16” (Logical Shift Left Rin) ......................94 3.7 Macro “shift_R” (Shift Right Rin) ..........................................97 3.8 Macro “shift_R_16” (Shift Right Rin) ....................................99 3.9 Macro “shift_L” (Shift Left Rin)........................................... 101 3.10 Macro “shift_L_16” (Shift Left Rin) .................................... 103 3.11 Macro “rotate_R” (Rotate Right Rin) ................................... 105 3.12 Macro “rotate_R_16” (Rotate Right Rin) ............................. 110 3.13 Macro “rotate_L” (Rotate Left Rin) ...................................... 113 3.14 Macro “rotate_L_16” (Rotate Left Rin)................................ 116 3.15 Macro “Swap” ...................................................................... 119 3.16 Examples for Shift and Rotate Macros ................................. 122 3.16.1 Example 3.1 .............................................................. 129 3.16.2 Example 3.2.............................................................. 139 3.16.3 Example 3.3.............................................................. 148 3.16.4 Example 3.4.............................................................. 157 3.16.5 Example 3.5.............................................................. 167 3.16.6 Example 3.6.............................................................. 177 3.16.7 Example 3.7 .............................................................. 186

Chapter 4

Selection Macros .............................................................................. 197 Introduction ...................................................................................... 197 4.1 Macro “move_R” (Move) ...................................................... 198 4.2 Macro “load_R” (Load) ........................................................ 198

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4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 4.15 4.16 4.17 4.18 4.19 4.20 4.21 4.22 4.23 4.24 4.25 4.26 4.27 4.28 4.29 4.30 4.31

Macro “select” (Selection of One of Two 8-Bit Input Variables) .............................................................................. 201 Macro “select_16” (Selection of One of Two 16-Bit Input Variables) .................................................................... 201 Macro “max _5” (Maximum in Five 8-Bit Variables) .........203 Macro “max_10” (Maximum in Ten 8-Bit Variables)...........208 Macro “max_N80” (Maximum in N 8-Bit Variables, N = 2, 3, …, 80) .....................................................................209 Macro “max_N40_16” (Maximum in N 16-Bit Variables, N = 2, 3, …, 40)..................................................................... 210 Macro “max_N255” (Maximum in N 8-Bit Variables, N = 2, 3, …, 255) ................................................................... 213 Macro “max_N255_16” (Maximum in N 16-Bit Variables, N = 2, 3, …, 255).................................................. 214 Macro “min _5” (Minimum in Five 8-Bit Variables)............ 216 Macro min_10” (Minimum in Ten 8-Bit Variables).............. 218 Macro “min_N80” (Minimum in N 8-Bit Variables, N = 2, 3, …, 80) ..................................................................... 218 Macro “min_N40_16” (Minimum in N 16-Bit Variables, N = 2, 3, …, 40)..................................................................... 221 Macro “min_N255” (Minimum in N 8-Bit Variables, N = 2, 3, …, 255) ................................................................... 223 Macro “min_N255_16” (Minimum in N 16-Bit Variables, N = 2, 3, …, 255).................................................. 225 Macro “limiter” ..................................................................... 227 Macro “limiter_16”................................................................ 228 Multiplexer Macros................................................................ 229 Macro “mux_2_1”................................................................. 230 Macro “mux_2_1_E” ............................................................ 230 Macro “mux_4_1” ................................................................. 231 Macro “mux_4_1_E” ........................................................... 231 Macro “mux_8_1” ................................................................. 233 Macro “mux_8_1_E” ............................................................ 233 Macro “mux_16_1” ............................................................... 234 Macro “mux_16_1_E”........................................................... 235 Macro “B_mux_2_1_E” ....................................................... 236 Macro “B_mux_4_1_E” ....................................................... 237 Macro “B_mux_8_1_E” ....................................................... 238 Examples for Selection Macros ............................................. 241 4.31.1 Example 4.1 .............................................................. 243 4.31.2 Example 4.2.............................................................. 247 4.31.3 Example 4.3..............................................................248 4.31.4 Example 4.4.............................................................. 249 4.31.5 Example 4.5.............................................................. 252 4.31.6 Example 4.6.............................................................. 261 4.31.7 Example 4.7 .............................................................. 263

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Contents

4.31.8 Example 4.8.............................................................. 268 4.31.9 Example 4.9.............................................................. 275 4.31.10 Example 4.10 ............................................................ 279 4.31.11 Example 4.11 ............................................................284 4.31.12 Example 4.12 ............................................................ 291 4.31.13 Example 4.13 ............................................................ 296 4.31.14 Example 4.14 ............................................................ 303 4.31.15 Example 4.15 ............................................................306 4.31.16 Example 4.16 ............................................................308 4.31.17 Example 4.17 ............................................................308 4.31.18 Example 4.18 ............................................................ 310 4.31.19 Example 4.19 ............................................................ 310 4.31.20 Example 4.20............................................................ 313 4.31.21 Example 4.21 ............................................................ 316 4.31.22 Example 4.22............................................................ 318 Chapter 5

Demultiplexer Macros ...................................................................... 321 Introduction ...................................................................................... 321 5.1 Macro “Dmux_1_2” (1×2 DMUX)....................................... 322 5.2 Macro “Dmux_1_2_E” (1×2 DMUX with Enable Input)..... 322 5.3 Macro “Dmux_1_4” (1×4 DMUX)....................................... 323 5.4 Macro “Dmux_1_4_E” (1×4 DMUX with Enable Input)..... 323 5.5 Macro “Dmux_1_8” (1×8 DMUX)....................................... 325 5.6 Macro “Dmux_1_8_E” (1×8 DMUX with Enable Input)..... 325 5.7 Macro “Dmux_1_16” (1×16 DMUX).................................... 330 5.8 Macro “Dmux_1_16_E” (1×16 DMUX with Enable Input).......................................................................... 330 5.9 Macro “B_Dmux_1_2_E” (1×2 Byte DeMultiplexer with Enable Input) ................................................................. 331 5.10 Macro “B_Dmux_1_4_E” (1×4 Byte DeMultiplexer with Enable Input) ................................................................. 334 5.11 Macro “B_Dmux_1_8_E” (1×8 Byte DeMultiplexer with Enable Input) ................................................................. 336 5.12 Macro “Dispatcher_1_8_E” (1×8 Dispatcher with Enable Input).......................................................................... 339 5.13 Macro “Patcher_8_1_E” (8×1 Patcher with Enable Input).......................................................................... 341 5.14 Examples for Demultiplexer Macros.....................................346 5.14.1 Example 5.1 .............................................................. 353 5.14.2 Example 5.2.............................................................. 357 5.14.3 Example 5.3.............................................................. 359 5.14.4 Example 5.4.............................................................. 361 5.14.5 Example 5.5.............................................................. 365 5.14.6 Example 5.6.............................................................. 367 5.14.7 Example 5.7 .............................................................. 369

Contents

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5.14.8 Example 5.8.............................................................. 372 5.14.9 Example 5.9 .............................................................. 376 Chapter 6

Conversion Macros........................................................................... 379 Introduction ...................................................................................... 379 6.1 Macro “Conv_UsInt_2_BCD_U” (Unsigned Short Integer to Unpacked BCD Conversion) ................................. 380 6.2 Macro “Conv_UsInt_2_BCD_P” (Unsigned Short Integer to Packed BCD Conversion)...................................... 383 6.3 Macro “Conv_UInt_2_BCD_U” (Unsigned Integer to Unpacked BCD Conversion).................................................. 385 6.4 Macro “Conv_UInt_2_BCD_P” (Unsigned Integer to Packed BCD Conversion) ...................................................... 386 6.5 Macro “Conv_BCD_U_2_UInt” (5-Digit Unpacked BCD to Unsigned Integer Conversion) ........................................... 389 6.6 Macro “Conv_BCD_P_2_UInt” (5-Digit Packed BCD to Unsigned Integer Conversion) ............................................... 392 6.7 Seven-Segment LED Displays............................................... 395 6.8 Macro “Segment_CCD” (Segment_CCD Instruction).......... 399 6.9 Macro “Segment_CAD” (Segment_CAD Instruction) .........406 6.10 Macro “Conv_Bin_2_Gray” (Binary to Gray Code Conversion)............................................................................ 410 6.11 Macro “Conv_Bin_2_Gray_16” (Binary to Gray Code Conversion)............................................................................ 412 6.12 Macro “Conv_Gray_2_Bin” (Gray Code to Binary Conversion)............................................................................ 414 6.13 Macro “Conv_Gray_2_Bin_16” (Gray Code to Binary Conversion)............................................................................ 418 6.14 Examples for Conversion Macros.......................................... 420 6.14.1 Example 6.1 .............................................................. 424 6.14.2 Example 6.2.............................................................. 427 6.14.3 Example 6.3.............................................................. 428 6.14.4 Example 6.4.............................................................. 430 6.14.5 Example 6.5.............................................................. 431 6.14.6 Example 6.6.............................................................. 433 6.14.7 Example 6.7 .............................................................. 434 6.14.8 Example 6.8.............................................................. 435 6.14.9 Example 6.9.............................................................. 436 6.14.10 Example 6.10 ............................................................ 437 6.14.11 Example 6.11 ............................................................ 439 6.14.12 Example 6.12 ............................................................ 441 References ........................................................................................448

About the Downloadable Files for Intermediate Concepts ..............................449 Index...................................................................................................................... 451

Prologue Think globally, act locally. Never give up. No pain, no gain. Practice makes perfect. If we hear, we forget If we see, we remember If we do, we understand. Success is not an accident, excellence is not a coincidence. Think out of the box.

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Preface Programmable Logic Controllers (PLCs) have been extensively used in industry for the past fve decades. PLC manufacturers offer different PLCs in terms of functions, program memories, and the number of inputs/outputs (I/Os), ranging from a few to thousands of I/Os. The design and implementation of PLCs have long been a secret of the PLC manufacturers. A serious project was reported by the author of this book in his previous book, entitled Building a Programmable Logic Controller with a PIC16F648A Microcontroller, published by CRC Press in 2014, to describe a microcontroller-based implementation of a PLC. The current project, called PIC16F1847 Microcontroller-Based Programmable Logic Controller, is based on the improved version of the project reported in the above-mentioned book. The improvements include both hardware and software elements. The current project is reported in three volumes and a downloadable document explaining application examples: 1. PIC16F1847 Microcontroller-Based Programmable Logic Controller: Hardware and Basic Concepts 2. PIC16F1847 Microcontroller-Based Programmable Logic Controller: Intermediate Concepts (this volume) 3. PIC16F1847 Microcontroller-Based Programmable Logic Controller: Advanced Concepts The current project is presented for students attending the related departments of engineering or technology faculties, for practicing engineers, and for hobbyists who want to learn how to design and use a microcontroller-based PLC. The book assumes the reader has taken courses on digital logic design, microcontrollers, and PLCs. In addition, the reader is expected to be familiar with the PIC16F series of microcontrollers and to have been exposed to writing programs using PIC assembly language within MPLAB integrated development environment. The contents of this book may be used to construct two different courses. The frst one may involve teaching the use of the PLC technology as described in this book. This course may well ft in the related departments of both engineering and technology faculties. The second one may involve teaching how to design the PLC technology. This second course may be taught in electrical and electronics engineering and computer engineering departments. Source and example fles defned for the intermediate concepts of the PIC16F1847Based PLC project are downloadable from this book’s webpage under the downloads section. Prof. Dr. Murat UZAM Yozgat Bozok Üniversitesi Mühendislik-Mimarlık Fakültesi Elektrik-Elektronik Mühendisliği Bölümü Yozgat Turkey xv

About the Author Murat Uzam was born in Söke, Turkey, in 1968. He received his B.Sc. and M.Sc. degrees from the Electrical Engineering Department, Yıldız Technical University, İstanbul, Turkey, in 1989 and 1991, respectively, and his Ph.D. degree from the University of Salford, Salford, U.K., in 1998. He was with Niğde University, Turkey, from 1993 to 2010 in the Department of Electrical and Electronics Engineering as a research assistant, assistant professor, associate professor, and professor. He was a professor in the Department of Electrical and Electronics Engineering, at Melikşah University in Kayseri, Turkey, from 2011 to 2016. Since 15 April 2020, he has been serving as a professor in the Department of Electrical and Electronics Engineering, at Yozgat Bozok University in Yozgat, Turkey. He was a visiting researcher at INRIA, the University of Metz, and the University of Rennes, France, in 1999, at the University of Toronto, Toronto, Canada, in 2003, and at Xidian University, Xi’an, China, in 2013, 2015, and 2019. He has published 47 conference papers and 106 journal and magazine papers, 70 of which are indexed by Science Citation Index Expanded (SCIE). He has had published two books in Turkish and fve books in English, by CRC Press (Taylor & Francis Group). According to Publons, his h-index is 16, and his papers have been cited more than 1370 times by the papers indexed in the SCIE. Dr. Uzam serves as a reviewer for prestigious journals and conferences. According to Publons, the number of verifed reviews by him is 70. His current research interests include design and implementation of discrete event control systems modelled by Petri nets and, in particular, deadlock prevention/liveness enforcing in fexible manufacturing systems, programmable logic controllers (PLCs), microcontrollers (especially PIC microcontrollers), and design of microcontroller-based PLCs. The details of his studies are accessible from his web page: https://pbs.bozok.edu.tr/goster.php?lookup=1074

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Background and Use of the Book This project has been completed during the search for an answer to the following question: “How could one design and implement a programmable logic controller (PLC)?”. An answer to this question was provided by the author in his previous book, entitled Building a Programmable Logic Controller with a PIC16F648A Microcontroller, published by CRC Press in 2014. This project is based on the improved version of the PLC project reported in the above-mentioned book. Many new features have been included within the PIC16F1847-Based PLC project to make it an almost perfect PLC. The reader should be aware of the fact that this project does not include graphical interface PC software as in commercial PLCs for developing PLC programs. Rather, PLC programs are developed using macros, as done in the Instruction List (IL) PLC programming language. An interested and skilled reader could well (and is encouraged to) develop graphical interface PC software for easy use of the PIC16F1847-Based PLC. In Volume I (Hardware and Basic Concepts), the hardware and basic software structures are explained in detail. This volume (Volume II – Intermediate Concepts) deals with the intermediate concepts built upon the basic hardware and software structures explained in Volume I. The improvements of the PLC project reported in this volume (Intermediate Concepts) compared with the previous version are summarized as follows. 1. The current version of the PLC provides 16 arithmetical instructions, whereas the previous version provided 6 arithmetical instructions. 2. The current version of the PLC provides 15 shift and rotate instructions, whereas the previous version provided 5 shift and rotate instructions. 3. The current version of the PLC provides 30 selection instructions, whereas the previous version provided 6 multiplexer instructions. 4. The current version of the PLC provides 13 demultiplexer instructions, whereas the previous version provided 6 demultiplexer instructions. 5. The current version of the PLC provides 16 decoder instructions, whereas the previous version provided 12 decoder instructions. 6. The current version of the PLC provides eight priority encoder instructions, whereas the previous version provided six priority encoder instructions. 7. The current version of the PLC provides 13 conversion instructions, whereas the previous version did not provide any conversion instructions. 8. Almost all macros are improved compared with the previous versions, in terms of fexibility. For example, there is no restriction on the SRAM Banks, i.e., Boolean variables, 8-bit variables, and 16-bit variables used as a parameter in an instruction can be in any Bank. This was not the case in the previous version. xix

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Background and Use of the Book

9. Flowcharts are provided to facilitate understanding of the macros (instructions). In order to follow the topics explained in this book properly, it is expected that the reader will construct his/her own PIC16F1847-Based PLC consisting of the CPU board and four I/O extension boards using the PCB fles provided on the frst volume’s (Hardware and Basic Concepts) webpage under the downloads section. It is also expected that the reader has previously studied the concepts treated in Volume I before reading this volume. In addition, the reader should also download and make use of the PLC project fles from the book’s webpage. In this project, as the PIC assembly is used as the programming language within the MPLAB integrated development environment (IDE), the reader is referred to the homepage of Microchip (www.microchip.com/) to obtain the latest version of MPLAB IDE. References [1, 2] may be useful to understand some aspects of the PIC16F1847 microcontroller and MPASMTM Assembler, respectively. The contents of this volume’s eight chapters are explained briefy, as follows. 1. Arithmetical Macros: The following arithmetical macros are described in this chapter: R1addR2 (R1 + R2; add the contents of two 8-bit registers), R1addR2_16 (R1 + R2_16; add the contents of two 16-bit registers), RaddK (R + K; add the content of an 8-bit register (R) and an 8-bit constant (K)), RaddK_16 (R + K_16; add the content of a 16-bit register (R) and a 16-bit constant (K)), R1subR2 (R1 - R2; subtract the content of the 8-bit register R2 from the content of the 8-bit register R1), R1subR2_16 (R1 - R2_16; subtract the content of the 16-bit register R2 from the content of the 16-bit register R1), RsubK (R - K; subtract the 8-bit constant value K from the content of the 8-bit register R), RsubK_16 (R - K_16; subtract the 16-bit constant value K from the content of the 16-bit register R), R1mulR2 (R1 × R2; multiply the contents of two 8-bit registers), DivU16by8 (R1_16 / R2_8; divide the content of the 16-bit register R1 by the content of the 8-bit register R2), incR (IN + 1; increment the content of the 8-bit register IN), incR_16 (IN + 1_16; increment the content of the 16-bit register IN), decR (IN – 1; decrement the content of the 8-bit register IN), decR_16 (IN – 1_16; decrement the content of the 16-bit register IN), Hbit_CNT (High Bit Counter), Lbit_CNT (Low Bit Counter). 2. Logical Macros: The following logical macros are described in this chapter: R1andR2 (R1 AND R2), RandK (R AND K), R1nandR2 (R1 NAND R2), RnandK (R NAND K), R1orR2 (R1 OR R2), RorK (R OR K), R1norR2 (R1 NOR R2), RnorK (R NOR K), R1xorR2 (R1 EXOR R2), RxorK (R EXOR K), R1xnorR2 (R1 EXNOR R2), RxnorK (R EXNOR K), inv_R (Complement of R). These macros are applied to two 8-bit registers (R1 and R2) or to an 8-bit register (R) and an 8-bit constant (K). 3. Shift and Rotate Macros: The following Shift and Rotate macros are described in this chapter: Ashift_R (Arithmetic Shift Right the 8-bit register Rin), Ashift_R_16 (Arithmetic Shift Right the 16-bit register

Background and Use of the Book

Rin), Lshift_R (Logical Shift Right the 8-bit register Rin), Lshift_R_16 (Logical Shift Right the 16-bit register Rin), Lshift_L (Logical Shift Left the 8-bit register Rin), Lshift_L_16 (Logical Shift Left the 16-bit register Rin), shift_R (Shift Right the 8-bit register Rin), shift_R_16 (Shift Right the 16-bit register Rin), shift_L (Shift Left the 8-bit register Rin), shift_L_16 (Shift Left the 16-bit register Rin), rotate_R (Rotate Right the 8-bit register Rin), rotate_R_16 (Rotate Right the 16-bit register Rin), rotate_L (Rotate Left the 8-bit register Rin), rotate_L_16 (Rotate Left the 16-bit register Rin), Swap (Swap the nibbles of the 8-bit register Rin). 4. Selection Macros: The following selection macros are described in this chapter: move_R (Move), load_R (Load), select (Selection of One of Two 8-bit Input Variables), select_16 (Selection of One of Two 16-bit Input Variables), max_5 (Maximum in Five 8-bit Variables), max_10 (Maximum in Ten 8-bit Variables), max_N80 (Maximum in N 8-bit Variables, N = 2, 3, …, 80), max_N40_16 (Maximum in N 16-bit Variables, N = 2, 3, …, 40), max_N255 (Maximum in N 8-bit Variables, N = 2, 3, …, 255), max_N255_16 (Maximum in N 16-bit Variables, N = 2, 3, …, 255), min_5 (Minimum in Five 8-bit Variables), min_10 (Minimum in Ten 8-bit Variables), min_N80 (Minimum in N 8-bit Variables, N = 2, 3, …, 80), min_N40_16 (Minimum in N 16-bit Variables, N = 2, 3, …, 40), min_N255 (Minimum in N 8-bit Variables, N = 2, 3, …, 255), min_N255_16 (Minimum in N 16-bit Variables, N = 2, 3, …, 255), limiter, limiter_16, mux_2_1 (2×1 MUX), mux_2_1_E (2×1 MUX with Enable Input), mux_4_1 (4×1 MUX), mux_4_1_E (4×1 MUX with Enable Input), mux_8_1 (8×1 MUX), mux_8_1_E (8×1 MUX with Enable Input), mux_16_1 (16×1 MUX), mux_16_1_E (16×1 MUX with Enable Input), B_mux_2_1_E (2×1 Byte Multiplexer with Enable Input), B_mux_4_1_E (4×1 Byte Multiplexer with Enable Input), B_mux_8_1_E (8×1 Byte Multiplexer with Enable Input). 5. DeMultiplexer Macros: The following demultiplexer macros are described in this chapter: Dmux_1_2 (1×2 DMUX), Dmux_1_2_E (1×2 DMUX with Enable Input), Dmux_1_4 (1×4 DMUX), Dmux_1_4_E (1×4 DMUX with Enable Input), Dmux_1_8 (1×8 DMUX), Dmux_1_8_E (1×8 DMUX with Enable Input), Dmux_1_16 (1×16 DMUX), Dmux_1_16_E (1×16 DMUX with Enable Input), B_Dmux_1_2_E (1×2 Byte DeMultiplexer with Enable Input), B_Dmux_1_4_E (1×4 Byte DeMultiplexer with Enable Input), B_Dmux_1_8_E (1×8 Byte DeMultiplexer with Enable Input), Dispatcher_1_8_E (1×8 Dispatcher with Enable Input), Patcher_8_1_E (8×1 Patcher with Enable Input). 6. Conversion Macros: The following conversion macros are described in this chapter: Conv_UsInt_2_BCD_U (Unsigned Short Integer to Unpacked BCD Conversion), Conv_UsInt_2_BCD_P (Unsigned Short Integer to Packed BCD Conversion), Conv_UInt_2_BCD_U (Unsigned Integer to Unpacked BCD Conversion), Conv_UInt_2_BCD_P (Unsigned Integer to Packed BCD Conversion), Conv_BCD_U_2_UInt (5 Digit Unpacked BCD to Unsigned Integer Conversion), Conv_BCD_P_2_UInt (5 Digit Packed

xxi

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Background and Use of the Book

BCD to Unsigned Integer Conversion), Segment_CCD (Segment_CCD Instruction), Segment_CAD (Segment_CAD Instruction), Conv_Bin_2_ Gray (Binary to Gray Code Conversion), Conv_Bin_2_Gray_16 (Binary to Gray Code Conversion), Conv_Gray_2_Bin (Gray Code to Binary Conversion), Conv_Gray_2_Bin_16 (Gray Code to Binary Conversion). 7. Priority Encoder Macros: The following priority encoder macros are described in this chapter: encod_4_2_p (4×2 Priority Encoder with Active High Outputs), encod_4_2_p_E (4×2 Priority Encoder with Active High Outputs and with Active High Enable Input), encod_8_3_p (8×3 Priority Encoder with Active High Outputs), encod_8_3_p_E (8×3 Priority Encoder with Active High Outputs and with Active High Enable Input), encod_ dec_bcd_p (Decimal to BCD Priority Encoder with Active High Outputs), encod_dec_bcd_p_E (Decimal to BCD Priority Encoder with Active High Outputs and with Active High Enable Input Input), encod_16_4_p (16×4 Priority Encoder with Active High Outputs), encod_16_4_p_E (16×4 Priority Encoder with Active High Outputs and with Active High Enable Input). (Note that this chapter is provided as downloadable ancillary material.) 8. Decoder Macros: The following decoder macros are described in this chapter: decod_1_2 (1×2 Decoder with Active High Outputs), decod_1_2_ AL (1×2 Decoder with Active Low Outputs), decod_1_2_E (1×2 Decoder with Active High Outputs and with Active High Enable Input), decod_1_2_E_AL (1×2 Decoder with Active Low Outputs and with Active High Enable Input), decod_2_4 (2×4 Decoder with Active High Outputs), decod_2_4_AL (2×4 Decoder with Active Low Outputs), decod_2_4_E (2×4 Decoder with Active High Outputs and with Active High Enable Input), decod_2_4_E_AL (2×4 Decoder with Active Low Outputs and with Active High Enable Input), decod_3_8 (3×8 Decoder with Active High Outputs), decod_3_8_AL (3×8 Decoder with Active Low Outputs), decod_3_8_E (3×8 Decoder with Active High Outputs and with Active High Enable Input), decod_3_8_E_AL (3×8 Decoder with Active Low Outputs and with Active High Enable Input), decod_4_16 (4×16 Decoder with Active High Outputs), decod_4_16_AL (4×16 Decoder with Active Low Outputs), decod_4_16_E (4×16 Decoder with Active High Outputs and with Active High Enable Input), decod_4_16_E_AL (4×16 Decoder with Active Low Outputs and with Active High Enable Input). (Note that this chapter is provided as downloadable ancillary material.) Application Examples: In total, there are 20 application examples considered. For some application examples, more than one solution is provided in order to point out how different methods can be used for controlling the same problem. When the three volumes are purchased separately, application examples from 1 to 9 (respectively, 10, 11, 13, 14, 15, 16, 17, 18, and 19; 7, 8, 9, 10, 11, 12, and 20) are provided as downloadable ancillary material for the book PIC16F1847 MicrocontrollerBased Programmable Logic Controller: Hardware and Basic Concepts (respectively, PIC16F1847 Microcontroller-Based Programmable Logic Controller:

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Background and Use of the Book

TABLE 0.1 General characteristics of the PIC16F1847-Based PLC

Inputs/Outputs/Functions

Byte Addresses/Related Bytes

Bit Addresses or Function Names/ Numbers

32 discrete inputs (external inputs: 5 or 24 V DC)

I0, I1, I2, I3

I0.0, I0.1, …, I0.7 I1.0, I1.1, …, I1.7 I2.0, I2.1, …, I2.7 I3.0, I3.1, …, I3.7

32 discrete outputs (relay-type outputs)

Q0, Q1, Q2, Q3 AI0H:AI0L, AI1H:AI1L, AI2H:AI2L, AI3H:AI3L Details are available in Chapter 4 of Volume III – Advanced Concepts M0, M1, . . M127

Q0.0, Q0.1, …, Q0.7 Q1.0, Q1.1, …, Q1.7 Q2.0, Q2.1, …, Q2.7 Q3.0, Q3.1, …, Q3.7 AI0H,1, AI0H,0, …, AI0L,0 AI1H,1, AI1H,0, …, AI1L,0 AI2H,1, AI2H,0, …, AI2L,0 AI3H,1, AI3H,0, …, AI3L,0 RA2 RB6 RA4 & RA7 Details are available in Chapter 4 of Volume III – Advanced Concepts) M0.0, M0.1, …, M0.7 M1.0, M1.1, …, M1.7 . . M127.0, M127.1, …, M127.7 TQ0, TQ1, …, TQ79

4 analog inputs

1 analog output 1 High Speed Counter input 2 PWM outputs Drum Sequencer Instruction with up to 16 steps and 16 outputs on each step 1024 internal relays (memory bits)

80 8-bit on delay timers (TON_8) 80 8-bit retentive on delay timers (RTO_8) 80 8-bit off delay timers (TOF_8) 80 8-bit pulse timers (TP_8) 80 8-bit extended pulse timers (TEP_8)

TV_L, TV_L+1, …, TV_L+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 T_Q0, T_Q1, …, T_Q9

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

(Continued )

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Background and Use of the Book

TABLE 0.1 (CONTINUED) General characteristics of the PIC16F1847-Based PLC

Inputs/Outputs/Functions 80 8-bit oscillator timers (TOS_8) 80 16-bit on delay timers (TON_16)

80 16-bit retentive on delay timers (RTO_16)

80 16-bit off delay timers (TOF_16)

80 16-bit pulse timers (TP_16)

80 16-bit extended pulse timers (TEP_16)

80 16-bit oscillator timers (TOS_16)

80 8-bit up counter (CTU_8) 80 8-bit down counter (CTD_8)

Byte Addresses/Related Bytes TV_L, TV_L+1, …, TV_L+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 TV_H, TV_H+1, …, TV_H+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 TV_H, TV_H+1, …, TV_H+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 TV_H, TV_H+1, …, TV_H+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 TV_H, TV_H+1, …, TV_H+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 TV_H, TV_H+1, …, TV_H+79 T_Q0, T_Q1, …, T_Q9 TV_L, TV_L+1, …, TV_L+79 TV_H, TV_H+1, …, TV_H+79 T_Q0, T_Q1, …, T_Q9 CV_L, CV_L+1, …, CV_L+79 C_Q0, C_Q1, …, C_Q9 CV_L, CV_L+1, …, CV_L+79 C_Q0, C_Q1, …, C_Q9

Bit Addresses or Function Names/ Numbers TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

TQ0, TQ1, …, TQ79

CQ0, CQ1, …, CQ79

CQ0, CQ1, …, CQ79

(Continued )

xxv

Background and Use of the Book

TABLE 0.1 (CONTINUED) General characteristics of the PIC16F1847-Based PLC

Inputs/Outputs/Functions 80 8-bit up/down counter (CTUD_8)

80 8-bit generalized up/down counter (GCTUD_8) 80 16-bit up counter (CTU_16)

80 16-bit down counter (CTD_16)

80 16-bit up/down counter (CTUD_16)

80 16-bit generalized up/down counter (GCTUD_16)

Byte Addresses/Related Bytes

Bit Addresses or Function Names/ Numbers

CV_L, CV_L+1, …, CV_L+79 C_Q0, C_Q1, …, C_Q9 CV_L, CV_L+1, …, CV_L+79 C_Q0, C_Q1, …, C_Q9 CV_L, CV_L+1, …, CV_L+79 CV_H, CV_H+1, …, CV_H+79 C_Q0, C_Q1, …, C_Q9 CV_L, CV_L+1, …, CV_L+79 CV_H, CV_H+1, …, CV_H+79 C_Q0, C_Q1, …, C_Q9 CV_L, CV_L+1, …, CV_L+79 CV_H, CV_H+1, …, CV_H+79 C_Q0, C_Q1, …, C_Q9

CQ0, CQ1, …, CQ79

CV_L, CV_L+1, …, CV_L+79 CV_H, CV_H+1, …, CV_H+79 C_Q0, C_Q1, …, C_Q9

CQ0, CQ1, …, CQ79

CQ0, CQ1, …, CQ79

CQ0, CQ1, …, CQ79

CQ0, CQ1, …, CQ79

CQ0, CQ1, …, CQ79

Intermediate Concepts; PIC16F1847 Microcontroller-Based Programmable Logic Controller: Advanced Concepts). On the other hand, when the three volumes are purchased as a set, all application examples are provided as a single ancillary material. Table 0.1 shows the general characteristics of the PIC16F1847-Based PLC. Important notices: 1. At any time, at most 80 different timers can be used. A unique timer number from 0 to 79 can only be assigned to one of the macros TP_8, TEP_8, TOS_8, TON_16, RTO_16, TOF_16, TP_16, TEP_16, TOS_16. 2. At any time, at most 80 different counters can be used. A unique counter number from 0 to 79 can only be assigned to one of the macros CTU_8, CTD_8, CTUD_8, GCTUD_8, CTU_16, CTD_16, CTUD_16, GCTUD_16.

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Background and Use of the Book

REFERENCES 1. PIC16(L)F1847 Data Sheet, DS40001453F, 2011-2017, Microchip Technology Inc. http://ww1.microchip.com/downloads/en/DeviceDoc/40001453F.pdf 2. MPASMTM Assembler, MPLINKTM Object Linker, MPLIBTM Object Librarian User’s Guide DS33014J, 2005, Microchip Technology Inc. http://ww1.microchip.com/downloads/en/devicedoc/33014j.pdf

1

Arithmetical Macros

INTRODUCTION Numerical data imply the ability to do arithmetical operations, and almost all PLCs provide some arithmetical operations such as add, subtract, multiply, and divide. Arithmetical functions will retrieve one or more values, perform an operation, and store the result in memory. As an example, Figure 1.1 shows an ADD function that will retrieve and “add” two values from sources labelled source A and source B and will store the result in destination C. Some arithmetical functions (macros) described for the PIC16F1847-Based PLC are as follows. The increment and decrement functions are unary, so there is only one source. ADD (source value 1, source value 2, destination) – add two source values and put the result in the destination. SUB (source value 1, source value 2, destination) – subtract the second source value from the frst one and put the result in the destination. MUL (source value 1, source value 2, destination) – multiply the source values and put the result in the destination. DIV (source value 1, source value 2, destination) – divide the frst source value by the second source value and put the result in the destination. INC (source value, destination) – increment the source and put the result in the destination. DEC (source value, destination) - decrement the source and put the result in the destination. In this chapter, the following integer arithmetical macros are described for the PIC16F1847-Based PLC: R1addR2 (R1 + R2), R1addR2_16 (R1 + R2_16), RaddK (R + K), RaddK_16 (R + K_16), R1subR2 (R1 - R2), R1subR2_16 (R1 - R2_16), RsubK (R - K), RsubK_16 (R - K_16), R1mulR2 (R1 × R2), DivU16by8 (R1_16 / R2_8), incR (IN + 1), incR_16 (IN + 1_16), decR (IN – 1), 1

2

Programmable Logic Controller

FIGURE 1.1 The ADD function.

decR_16 (IN – 1_16), Hbit_CNT (High Bit Counter), Lbit_CNT (Low Bit Counter). The fle “PICPLC_PIC16F1847_macros_Int.inc”, which is downloadable from this book’s webpage under the downloads section, contains macros defned for the PIC16F1847-Based PLC explained in this volume (Intermediate Concepts). Let us now consider the arithmetical macros in detail.

1.1

MACRO “R1ADDR2”

The algorithm and the symbol of the macro “R1addR2” are depicted in Table 1.1. Figure 1.2 shows the macro “R1addR2” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. This is especially useful if we want to carry out more than one operation based on a single input condition. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enableinput signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1addR2” adds the contents of

TABLE 1.1 Algorithm and the Symbol of the Macro “R1addR2” Algorithm

Symbol

if EN = 1 then OUT := R1 + R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

Arithmetical Macros

FIGURE 1.2

3

The macro “R1addR2” and its fowchart.

two 8-bit source variables R1 and R2 and stores the result into the 8-bit destination variable OUT (OUT := R1 + R2). This instruction affects the carry bit. If the sum is greater than 8-bit, then the carry bit (STATUS,C) is set; else it is reset. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

1.2

MACRO “R1ADDR2_16”

The algorithm and the symbol of the macro “R1addR2_16” are depicted in Table 1.2. Figure 1.3 shows the macro “R1addR2_16” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. This is especially useful if we want to carry out more than one operation based on a single input condition. R1 and R2 are both 16-bit source variables. R1 consists of two 8-bit variables, R1H and R1L. R1H holds the high byte of R1, and R1L holds the low byte of R1. Likewise, R2 consists of two 8-bit variables, R2H and R2L. R2H holds the high byte of R2, and R2L holds the low byte of R2. OUT refers to a 16-bit destination variable to which the result of the macro is stored. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1addR2_16” adds the contents of two 16-bit source variables, R1 and R2, and stores the result into the 16-bit destination variable OUT (OUT := R1 + R2). This instruction affects the carry bit. If the sum is greater than 16-bit, then the carry bit (STATUS,C) is set; else it is reset. Assumption: The operands “R1H”, “R1L”, “R2H”, “R2L”, “OUTH”, and “OUTL” can be in any Bank.

4

Programmable Logic Controller

TABLE 1.2 Algorithm and the Symbol of the Macro “R1addR2_16” Algorithm

Symbol

if EN = 1 then OUT := R1 + R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (16-bit source variable, consisting of two 8-bit variables, R1H & R1L) R2 (16-bit source variable, consisting of two 8-bit variables, R2H & R2L) OUT (16-bit destination variable, consisting of two 8-bit variables, OUTH & OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 1.3 The macro “R1addR2_16” and its fowchart.

5

Arithmetical Macros

1.3

MACRO “RADDK”

The algorithm and the symbol of the macro “RaddK” are depicted in Table 1.3. Figure 1.4 shows the macro “RaddK” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO TABLE 1.3 Algorithm and the Symbol of the Macro “RaddK” Algorithm

Symbol

if EN = 1 then OUT := R + K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 1.4

The macro “RaddK” and its fowchart.

6

Programmable Logic Controller

is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RaddK” adds the contents of the 8-bit variable R and the 8-bit constant value K and stores the result into the 8-bit destination variable OUT (OUT := R + K). This instruction affects the carry bit. If the sum is greater than 8-bit, then the carry bit (STATUS,C) is set; else it is reset. Assumption: The operands “R” and “OUT” can be in any Bank.

1.4

MACRO “RADDK_16”

The algorithm and the symbol of the macro “RaddK_16” are depicted in Table 1.4. Figure 1.5 shows the macro “RaddK_16” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R is a 16-bit source variable consisting of two 8-bit variables, RH and RL. RH holds the high byte of R, and RL holds the low byte of R. K is a 16-bit constant value. OUT refers to a 16-bit destination variable to which the result of the macro is stored. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Booleanenable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RaddK_16” adds the contents of the 16-bit variable R and the 16-bit constant value K and stores the result into the 16-bit destination variable OUT (OUT := R + K). This instruction affects the carry bit. If the sum is greater than 16-bit, then the carry bit (STATUS,C) is set;

TABLE 1.4 Algorithm and the Symbol of the Macro “RaddK_16” Algorithm

Symbol

if EN = 1 then OUT := R + K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (16-bit source variable, consisting of two 8-bit variables, RH & RL) K (16-bit constant value, K) OUT (16-bit destination variable, consisting of two 8-bit variables, OUTH & OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

7

Arithmetical Macros

FIGURE 1.5 The macro “RaddK_16” and its fowchart.

else it is reset. Assumption: The operands “RH”, “RL”, “OUTH”, and “OUTL” can be in any Bank.

1.5

MACRO “R1SUBR2”

The algorithm and the symbol of the macro “R1subR2” are depicted in Table 1.5. Figure 1.6 shows the macro “R1subR2” and its fowchart. In this macro, EN is a

TABLE 1.5 Algorithm and the Symbol of the Macro “R1subR2” Algorithm

Symbol

if EN = 1 then OUT := R1 – R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

8

Programmable Logic Controller

FIGURE 1.6

The macro “R1subR2” and its fowchart.

Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1subR2” subtracts the contents of the 8-bit variable R2 from the contents of the 8-bit variable R1 and stores the result into the 8-bit destination variable OUT (OUT := R1 – R2). Note: The subtraction is carried out by using the 2’s complement method. This instruction affects the borrow (carry) bit. If the result is negative, then the borrow (carry) bit (STATUS,C) is reset; else it is set. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

1.6

MACRO “R1SUBR2_16”

The algorithm and the symbol of the macro “R1subR2_16” are depicted in Table 1.6. Figure 1.7 shows the macro “R1subR2_16” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 and R2 are both 16-bit source variables. R1 consists of two 8-bit variables, R1H and R1L. R1H holds the high byte of R1, and R1L holds the low byte of R1. Likewise, R2 consists of two 8-bit variables, R2H and R2L. R2H holds the high byte of R2, and R2L holds the low byte of R2. OUT refers to a 16-bit

9

Arithmetical Macros

TABLE 1.6 Algorithm and the Symbol of the Macro “R1subR2_16” Algorithm

Symbol

if EN = 1 then OUT := R1 – R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (16-bit source variable, consisting of two 8-bit variables, R1H & R1L) R2 (16-bit source variable, consisting of two 8-bit variables, R2H & R2L) OUT (16-bit destination variable, consisting of two 8-bit variables, OUTH & OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 1.7 The macro “R1subR2_16” and its fowchart.

destination variable to which the result of the macro is stored. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1subR2_16” subtracts the contents of the 16-bit variable R2 from

10

Programmable Logic Controller

the contents of the 16-bit variable R1 and stores the result into the 16-bit destination variable OUT (OUT := R1 – R2). Note: The subtraction is carried out by using the 2’s complement method. This instruction affects the borrow (carry) bit. If the result is negative, then the borrow (carry) bit (STATUS,C) is reset; else it is set. Assumption: The operands “R1H”, “R1L”, “R2H”, “R2L”, “OUTH”, and “OUTL” can be in any Bank.

1.7 MACRO “RSUBK” The algorithm and the symbol of the macro “RsubK” are depicted in Table 1.7. Figure  1.8 shows the macro “RsubK” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RsubK” subtracts the 8-bit constant value K from the contents of the 8-bit variable R and stores the result into the 8-bit destination variable OUT (OUT := R – K). Note: The subtraction is carried out by using the 2’s complement method. This instruction affects the borrow (carry) bit. If the result is negative, then the borrow (carry) bit (STATUS,C) is reset; else it is set. Assumption: The operands “R” and “OUT” can be in any Bank.

1.8

MACRO “RSUBK_16”

The algorithm and the symbol of the macro “RsubK_16” are depicted in Table 1.8. Figure 1.9 shows the macro “RsubK_16” and its fowchart. In this macro, EN is a TABLE 1.7 Algorithm and the Symbol of the Macro “RsubK” Algorithm

Symbol

if EN = 1 then OUT := R – K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

11

Arithmetical Macros

FIGURE 1.8

The macro “RsubK” and its fowchart.

Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R is a 16-bit source variable consisting of two 8-bit variables, RH and RL. RH holds the high byte of R, and RL holds the low byte of R. K is a 16-bit

TABLE 1.8 Algorithm and the Symbol of the Macro “RsubK_16” Algorithm

Symbol

if EN = 1 then OUT := R – K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (16-bit source variable, consisting of two 8-bit variables, RH & RL) K (16-bit constant value, K) OUT (16-bit destination variable, consisting of two 8-bit variables, OUTH & OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

12

Programmable Logic Controller

FIGURE 1.9

The macro “RsubK_16” and its fowchart.

constant value. OUT refers to a 16-bit destination variable to which the result of the macro is stored. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Booleanenable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RsubK_16” subtracts the 16-bit constant value K from the contents of the 16-bit variable R and stores the result into the 16-bit destination variable OUT (OUT := R – K). Note: The subtraction is carried out by using the 2’s complement method. This instruction affects the borrow (carry) bit. If the result is negative, then the borrow (carry) bit (STATUS,C) is reset; else it is set. Assumption: The operands “RH”, “RL”, “OUTH”, and “OUTL” can be in any Bank.

1.9

MACRO “R1MULR2”

The algorithm and the symbol of the macro “R1mulR2” are depicted in Table 1.9. Figure 1.10 shows the macro “R1mulR2” and its fowchart. This macro is based on the unsigned 8 × 8 Software Multiplier defned in [R1.1]. The reader is referred to this reference for the detailed treatment of this multiplier. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 (mulcnd) is an 8-bit source variable and it represents the 8-bit multiplicand. R2 (mulplr) is another 8-bit source variable and it represents the 8-bit multiplier. OUT is a 16-bit destination variable to which the result of the macro is

13

Arithmetical Macros

TABLE 1.9 Algorithm and the Symbol of the Macro “R1mulR2” Algorithm

Symbol

if EN = 1 then OUT := R1 × R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, mulcnd) R2 (8-bit source variable, mulplr) OUT (16-bit destination variable, consisting of two 8-bit registers, prodH & prodL) ENO (Boolean-enable-output, through W) = 0 or 1

stored and it refers to the product of the multiplication. OUT consists of two 8-bit variables, prodH and prodL, where prodH holds the high byte of OUT, and prodL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1mulR2” multiples the contents of the 8-bit source variable R1

FIGURE 1.10 The macro “R1mulR2” and its fowchart.

14

Programmable Logic Controller

(mulcnd) by the contents of the 8-bit source variable R2 (mulplr) and stores the result (product) into the 16-bit destination variable OUT (OUT := R1 × R2; prodH&prodL = mulcnd × mulplr). Assumption: The operands “mulcnd”, “mulplr”, “prodH”, and “prodL” can be in any Bank.

1.10

MACRO “DIVU16BY8”

The algorithm and the symbol of the macro “DivU16by8” are depicted in Table 1.10. Figure 1.11 shows the macro “DivU16by8” and its fowchart. This macro is TABLE 1.10 Algorithm and the Symbol of the Macro “DivU16by8” Algorithm

Symbol

if EN = 1 then OUT := R1_16 / R2_8; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (16-bit source variable, consisting of two 8-bit variables, DvdH & DvdL) R2 (8-bit source variable, Divisor) OUT (8-bit destination variable, Quot) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 1.11

The macro “DivU16by8” and its fowchart.

15

Arithmetical Macros

based on the 16-bit by 8-bit unsigned integer division reported in [R1.2]. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 refers to the dividend and it is a 16-bit source variable. It consists of two 8-bit variables, R1H (DvdH) and R1L (DvdL). R1H (DvdH) holds the high byte of R1, and R1L (DvdL) holds the low byte of R1. R2 (Divisor) is an 8-bit source variable and it refers to the divisor. OUT (Quot) is an 8-bit destination variable to which the result of the integer division is stored. It refers to the quotient. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “DivU16by8” divides the contents of the 16-bit variable R1 by the contents of the 8-bit variable R2 and stores the result into the 8-bit destination variable OUT (OUT := R1 / R2 : Quot = DvdH&DvdL / Divisor). Assumption: The operands “DvdH”, “DvdL”, “Divisor”, and “Quot” can be in any Bank. Note 1: Quotient must be 8-bit long! This means that you cannot do such divisions as 65535/5, 990/3, 666/2, 256/1, …, with this macro as the quotient must be 8-bit long. Unfortunately, this is the drawback of the macro “DivU16by8”. Note 2: This macro does not deal with the case of divide by 0.

1.11

MACRO “INCR”

The algorithm and the symbol of the macro “incR” are depicted in Table 1.11. Figure 1.12 shows the macro “incR” and its fowchart. In this macro, EN is a Booleaninput-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. IN refers to an 8-bit source variable from where the source value is taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “incR” increments the contents of the 8-bit variable IN and stores the result into the 8-bit TABLE 1.11 Algorithm and the Symbol of the Macro “incR” Algorithm

Symbol

if EN = 1 then OUT := IN + 1; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit source variable, IN) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

16

Programmable Logic Controller

FIGURE 1.12

The macro “incR” and its fowchart.

destination variable OUT (OUT := IN + 1). Assumption: The operands “IN” and “OUT” can be in any Bank.

1.12

MACRO “INCR_16”

The algorithm and the symbol of the macro “incR_16” are depicted in Table 1.12. Figure 1.13 shows the macro “incR_16” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a TABLE 1.12 Algorithm and the Symbol of the Macro “incR_16” Algorithm

Symbol

if EN = 1 then OUT := IN + 1; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 IN (16-bit source variable, consisting of two 8-bit variables, INH & INL) OUT (16-bit destination variable, consisting of two 8-bit variables, OUTH & OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

Arithmetical Macros

FIGURE 1.13

17

The macro “incR_16” and its fowchart.

Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. IN refers to a 16-bit source variable consisting of two 8-bit variables, INH and INL. INH holds the high byte of IN, and INL holds the low byte of IN. OUT refers to a 16-bit destination variable to which the result of the macro is stored. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “incR_16” increments the contents of the 16-bit source variable IN and stores the result into the 16-bit destination variable OUT (OUT := IN + 1). Assumption: The operands “INH”, “INL”, “OUTH”, and “OUTL” can be in any Bank.

1.13 MACRO “DECR” The algorithm and the symbol of the macro “decR” are depicted in Table 1.13. Figure 1.14 shows the macro “decR” and its fowchart. In this macro, EN is a Boolean-inputvariable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that,

18

Programmable Logic Controller

TABLE 1.13 Algorithm and the Symbol of the Macro “decR” Algorithm

Symbol

if EN = 1 then OUT := IN – 1; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit source variable, IN) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 1.14 The macro “decR” and its fowchart.

when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. IN refers to an 8-bit source variable from where the source value is taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “decR” decrements the contents of the 8-bit variable IN and stores the result into the 8-bit destination variable OUT (OUT := IN – 1). Assumption: The operands “IN” and “OUT” can be in any Bank.

19

Arithmetical Macros

1.14

MACRO “DECR_16”

The algorithm and the symbol of the macro “decR_16” are depicted in Table 1.14. Figure 1.15 shows the macro “decR_16” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. IN refers to a 16-bit source variable consisting of two 8-bit variables, INH and INL. INH holds the high byte of IN, and INL holds the low byte of IN. OUT refers to a 16-bit destination variable to which the result of the macro is stored. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “decR_16” decrements the contents of the 16-bit variable IN and stores the result into the 16-bit destination variable OUT (OUT := IN – 1). Assumption: The operands “INH”, “INL”, “OUTH”, and “OUTL” can be in any Bank.

1.15

MACRO “HBIT_CNT” (HIGH BIT COUNTER)

The algorithm and the symbol of the macro “Hbit_CNT” are depicted in Table 1.15. Figures 1.16 and 1.17 show the macro “Hbit_CNT” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. The Boolean-input-variable “reg,bit” shows the frst input bit to be considered. The 8-bit constant value “N” indicates the number of successive bits to be considered, and the 8-bit output variable Counter shows the number of HIGH (set) bits in N bits starting from “reg,bit”. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no TABLE 1.14 Algorithm and the Symbol of the Macro “decR_16”. Algorithm

Symbol

if EN = 1 then OUT := IN - 1; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 IN (16-bit source variable, consisting of two 8-bit variables, INH & INL) OUT (16-bit destination variable, consisting of two 8-bit variables, OUTH & OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

20

Programmable Logic Controller

FIGURE 1.15 The macro “decR_16” and its fowchart.

action is taken. When EN = 1, the macro “Hbit_CNT” counts the number of HIGH (set) bits among N successive bits located in SRAM memory, starting from “reg,bit”, and then stores the result into the 8-bit output variable Counter. Assumption: The operands “reg,bit” and “Counter” can be in any Bank. The macro “Hbit_CNT” contains four “while” directives with three different conditions. The directive “while” is not an instruction, but is used to control how code is assembled, not how it behaves at run-time. This directive is used for conditional assembly. It is not executed at run-time, but produces assembly code based on a condition. “while” is used to perform a loop while a certain condition is true. This directive is used with the “endw” directive. The lines between the “while” and the “endw” are assembled as long as the condition evaluates to TRUE. An expression that evaluates to zero is considered logically FALSE. An expression that evaluates to any other value is considered logically TRUE. A relational TRUE expression is guaranteed to return a non-zero value; FALSE, a value of zero. A while loop can contain at most 100 lines and be repeated a maximum of 256 times. “while” loops can be nested up to 8 deep. In the macro “Hbit_CNT”, the frst “while” directive is based on the condition “if bit = 0”, the second “while” directive is based on the condition “if bit > 0 and (bit+N) ≤ 8”, and, fnally, the last two “while” directives are based on the condition “if bit > 0 and (bit+N) > 8”. At any time, only one of these conditions is hold

Arithmetical Macros

21

TABLE 1.15 The Symbol and the Algorithm of the Macro “Hbit_CNT” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 reg,bit (Boolean-input-variable, the frst input bit, reg,bit) N (The number of successive bits, N) = 1, 2, ..., 255 Counter (8-bit output variable, showing the number of HIGH (set) bits in N bits starting from reg,bit, Counter) ENO (Boolean-enable-output, through W) = 0 or 1 Algorithm if EN = 1 then Counter := 0; i := 0; while i < N if (reg,bit)i = 1, then Counter := Counter + 1; endif; endwhile; ENO := 1; else ENO := 0; endif;

according to “bit” and “N”. Therefore, code will be assembled based on the condition that evaluates to TRUE. Note that, for the last condition, two “while” directives are used. In order to explain the use of these “while” and “if” directives in the macro “Hbit_CNT”, let us consider three different scenarios. In the frst scenario, consider the following example program: ld Hbit_CNT

LOGIC1 ;reg,bit,N,Counter I0.0,9,Q0

Basically, according to this program, in an endless loop (EN = LOGIC1), the number of HIGH (set) bits within the consecutive 9-bits starting from I0.0 is counted, and the count value is stored in Q0. It is obvious that we have the following: reg = I0 = 70h bit = 0 N = 9 Counter = Q0

22

FIGURE 1.16

Programmable Logic Controller

The macro “Hbit_CNT”.

Arithmetical Macros

FIGURE 1.17

The fowchart of the macro “Hbit_CNT”.

23

24

Programmable Logic Controller

Now let us see how the code for this example is assembled by the macro “Hbit_ CNT”. If we look at the macro “Hbit_CNT”, we can see that the condition of the following part of the macro evaluates to TRUE, as bit = 0. ;----------------------------------bit==0 if i=0 while i < N btfsc reg+i/8,bit+i-(8*(i/8)) incf Temp_1,F i += 1 endw endif ;-----------------------------------

The following shows how the related part of the code is assembled for this example: i Note that the division is an integer division. Thus, we have the following 8 i i i results: = 0 éëi = 0,1,¼, 7 ùû , = 1 éëi = 8, 9,¼,15ùû , = 2 éëi = 16,17,¼, 23ùû ,¼ 8 8 8 if bit = 0 i = 0 while i < N [i = 0, N = 9] i 0 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 8 è ø ø è æ æ 0 öö 0 + 0 - ç8 * ç ÷ ÷ = è 8 øø è btfsc 70h,0 incf Temp_1,F i = i + 1 = 0 + 1 = 1 while i < N [i = 1, N = 9] i 1 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 è è 8 øø æ æ 1 öö 0+1 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 70h,1 incf Temp_1,F i = i + 1 = 1 + 1 = 2 while i < N [i = 2, N = 9] i 2 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 8 è ø ø è æ æ 2 öö 0+2 - ç 8* ç ÷ ÷ = è è 8 øø

25

Arithmetical Macros btfsc 70h,2 incf Temp_1,F i = i + 1 = 2 + 1 = 3 while i < N [i = 3, N = 9] i 3 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 8 è ø ø è æ æ 3 öö 0+3 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 70h,3 incf Temp_1,F i = i + 1 = 3 + 1 = 4 while i < N [i = 4, N = 9] i 4 æ i ö btfsc reg + , bit + i - ç 8* çæ ö÷ ÷ = btfsc 70h + , 8 8 è è 8 øø æ æ 4 öö 0+4 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 70h,4 incf Temp_1,F i = i + 1 = 4 + 1 = 5 while i < N [i = 5, N = 9] i 5 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 8 è ø ø è æ æ 5 öö 0+5 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 70h,5 incf Temp_1,F i = i + 1 = 5 + 1 = 6 while i < N [i = 6, N = 9] i 6 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 è è 8 øø æ æ 6 öö 0+6 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 70h,6 incf Temp_1,F i = i + 1 = 6 + 1 = 7 while i < N [i = 7, N = i btfsc reg + , bit + i 8 æ æ 7 öö 0 + 7 - ç8 * ç ÷ ÷ = è 8 øø è btfsc 70h,7 incf Temp_1,F

9] 7 æ æ i öö ç 8* ç ÷ ÷ = btfsc 70h + 8 , 8 è ø ø è

26

Programmable Logic Controller

i = i + 1 = 7 + 1 = 8 while i < N [i = 8, N = 9] i 8 æ i ö btfsc reg + , bit + i - ç 8* çæ ÷ö ÷ = btfsc 70h + , 8 8 è è 8 øø æ 8 ö 0 + 8 - ç 8 * æç ö÷ ÷ = è 8 øø è btfsc 71h,0 incf Temp_1,F endwhile endif

Assembled code has nine “bit test f skip if clear” (btfsc) assembly instructions for consecutive bits starting from 70h,0 to 71h,0, together with “incf Temp_1,F” assembly instructions. The shaded cells in the following table show the 9-bits starting from I0.0 to be tested owing to the instruction “Hbit_CNT I0.0,9,Q0”: Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

070h

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

071h

I1

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

In the second scenario, consider the following example program: ld Hbit_CNT

LOGIC1 reg,bit,N,Counter I0.1,7,Q0

Basically, according to this program, in an endless loop (EN = LOGIC1), the number of HIGH (set) bits within the consecutive 7-bits starting from I0.1 is counted, and the count value is stored in Q0. It is obvious that we have the following: reg = I0 = 70h bit = 1 N = 7 Counter = Q0

Now let us see how the code for this example is assembled by the macro “Hbit_ CNT”. If we look at the macro “Hbit_CNT”, we can see that the condition of the following part of the macro evaluates to TRUE, as bit > 0 and bit+N = 8: ;---------------------------------- if bit>0 && ((bit+N) 0 and (bit+N) ≤ 8 i = 0 while i < N [i = 0, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F i = i + 1 = 0 + 1 = 1 while i < N [i = 1, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F i = i + 1 = 1 + 1 = 2 while i < N [i = 2, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F i = i + 1 = 2 + 1 = 3 while i < N [i = 3, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F i = i + 1 = 3 + 1 = 4 while i < N [i = 4, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F i = i + 1 = 4 + 1 = 5 while i < N [i = 5, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F i = i + 1 = 5 + 1 = 6 while i < N [i = 6, N = 7] btfsc reg,bit+i = btfsc incf Temp_1,F endwhile endif

70h,1+0 = btfsc 70h,1

70h,1+1 = btfsc 70h,2

70h,1+2 = btfsc 70h,3

70h,1+3 = btfsc 70h,4

70h,1+4 = btfsc 70h,5

70h,1+5 = btfsc 70h,6

70h,1+6 = btfsc 70h,7

Assembled code has seven btfsc assembly instructions for consecutive bits starting from 70h,1 to 70h,7, together with “incf Temp_1,F” assembly instructions. The shaded cells in the following table show the seven bits starting from I0.1 to be tested owing to the instruction “Hbit_CNT I0.1,7,Q0”:

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

070h

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

Bit 1 I0.1

Bit 0 I0.0

28

Programmable Logic Controller

In the third scenario, consider the following example program: ld Hbit_CNT

LOGIC1 ;reg,bit,N,Counter I0.6,6,Q0

Basically, according to this program, in an endless loop (EN = LOGIC1), the number of HIGH (set) bits within the consecutive 6-bits starting from I0.6 is counted, and the count value is stored in Q0. It is obvious that we have the following: reg = I0 = 70h bit = 6 N = 6 Counter = Q0

Now let us see how the code for this example is assembled by the macro “Hbit_ CNT”. If we look at the macro “Hbit_CNT”, we can see that the condition of the following part of the macro evaluates to TRUE, as bit > 0 and bit+N > 8. ;---------------------------------- if bit>0 && ((bit+N)>8) i=0 while i < 8-bit btfsc reg,bit+i incf Temp_1,F i += 1 endw i=0 while i < N-(8-bit) btfsc reg+1+i/8,i-(8*(i/8)) incf Temp_1,F i += 1 endw endif ;-----------------------------------

The following shows how the related part of the code is assembled for this example. i Note that the division is an integer divison. Thus, we have the following results: 8 i i i = 0 [i = 0, 1, …, 7], = 1 [i = 8, 9, …, 15], = 2 [i = 16, 17, …, 23], … 8 8 8 if bit > 0 and (bit+N) > 8 i = 0 while i < 8 – bit [i = 0, 8 – bit = 8 – 6 = 2] btfsc reg,bit+i = btfsc 70h,6+0 = btfsc 70h,6 incf Temp_1,F

Arithmetical Macros

29

i = i + 1 = 0 + 1 = 1 while i < 8 – bit [i = 1, 8 – bit = 8 – 6 = 2] btfsc reg,bit+i = btfsc 70h,6+1 = btfsc 70h,7 incf Temp_1,F endwhile i = 0 while i < N – (8 – bit) [i = 0, N – (8 – bit) = 6 – (8 – 6) = 4] 0 i æ i ö btfsc reg + 1 + , i - ç 8* æç ö÷ ÷ = btfsc 70h + 1 + , 8 8 8 è ø è ø æ æ 0 öö 0 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 71h,0 incf Temp_1,F i = i + 1 = 0 + 1 = 1 while i < N – (8 – bit) [i = 1, N – (8 – bit) = 6 – (8 – 6) = 4] 0 i æ i ö btfsc reg + 1 + , i - ç 8* æç ö÷ ÷ = btfsc 70h + 1 + , 8 8 è è 8 øø æ æ 1 öö 1 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 71h,1 incf Temp_1,F i = i + 1 = 1 + 1 = 2 while i < N – (8 – bit) [i = 2, N – (8 – bit) = 6 – (8 – 6) = 4] 2 i æ i ö btfsc reg + 1 + , i - ç 8* æç ö÷ ÷ = btfsc 70h + 1 + , 8 8 è è 8 øø æ æ 2 öö 2 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 71h,2 incf Temp_1,F i = i + 1 = 2 + 1 = 3 while i < N – (8 – bit) [i = 3, N – (8 – bit) = 6 – (8 – 6) = 4] 3 i æ i ö btfsc reg + 1 + , i - ç 8* æç ö÷ ÷ = btfsc 70h + 1 + , 8 8 è è 8 øø æ æ 3 öö 3 - ç 8* ç ÷ ÷ = è è 8 øø btfsc 71h,3 incf Temp_1,F endwhile endif

30

Programmable Logic Controller

Assembled code has six btfsc assembly instructions for consecutive bits, starting from 70h,6 to 71h,3 together with “incf Temp_1,F” assembly instructions. The shaded cells in the following table show the 6-bits starting from I0.6 to be tested owing to the instruction “Hbit_CNT I0.6,6,Q0”:

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

070h

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

Bit 1

I0.0

Bit 0

071h

I1

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

1.16 MACRO “LBIT_CNT” (LOW BIT COUNTER) The algorithm and the symbol of the macro “Lbit_CNT” are depicted in Table 1.16. Figures 1.18 and 1.19 show the macro “Lbit_CNT” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO

TABLE 1.16 The Symbol and the Algorithm of the Macro “Lbit_CNT” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 reg,bit (Boolean-input-variable, the frst input bit, reg,bit) N (The number of successive bits, N) = 1, 2, ..., 255 Counter (8-bit output variable, showing the number of LOW (reset) bits in N bits starting from reg,bit, Counter) ENO (Boolean-enable-output, through W) = 0 or 1 Algorithm if EN = 1 then Counter := 0; i := 0; while i < N if (reg,bit)i = 0, then Counter := Counter + 1; endif; endwhile; ENO := 1; else ENO := 0; endif;

Arithmetical Macros

FIGURE 1.18 The macro “Lbit_CNT”.

31

32

Programmable Logic Controller

FIGURE 1.19 The fowchart of the macro “Lbit_CNT”.

Arithmetical Macros

33

follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. The Boolean-input-variable “reg,bit” shows the frst input bit to be considered. The 8-bit constant value “N” indicates the number of successive bits to be considered, and the 8-bit output variable Counter shows the number of LOW (reset) bits in N bits starting from “reg,bit”. The Boolean-enableinput signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “Lbit_CNT” counts the number of LOW (reset) bits among N successive bits located in SRAM memory starting from “reg,bit” and then stores the result into the 8-bit output variable Counter. Assumption: The operands “reg,bit” and “Counter” can be in any Bank.

1.17

EXAMPLES FOR ARITHMETICAL MACROS

Up to now in this chapter, we have seen arithmetical macros developed for the PIC16F1847-Based PLC. It is now time to consider some examples related to these macros. Before you can run the example programs considered here, you are expected to construct your own PIC16F1847-Based PLC hardware by using the necessary PCB fles and by producing your PCBs, with their components. For an effective use of examples, all example programs considered in this book are allocated within the fle “PICPLC_PIC16F1847_user_Int.inc”, which is downloadable from this book’s webpage under the downloads section. Initially, all example programs are commented out by putting a semicolon “;” in front of each line. When you would like to test one of the example programs, you must uncomment each line of the example program by following the steps shown below: 1. Highlight the block of source lines you want to uncomment by dragging the mouse with the left mouse button held down over these lines. With default coloring in MPLAB X IDE, you will now see green characters on a blue background. 2. Release the mouse button. 3. Press Ctrl/Shift/C or press “Alt”, “S” and “M” keys in succession or, from the toolbar “Source” menu, select “Toggle Comment”. Now a semicolon will be removed from all selected source lines. With default coloring, you will see red characters on a white background. Then, you can run the project by pressing the symbol from the toolbar. Next, the MPLAB X IDE will produce the “PICPLC_PIC16F1847.X.production.hex” fle for the project. Then, the MPLAB X IDE will be connected to the PICkit3 programmer and fnally it will program the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC. During these steps, make sure that, in the CPU board of the PIC16F1847-Based PLC, the 4PDT switch is in “PROG” position, and the power switch is in “OFF” position. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to “ON” position. Finally, you are ready to test the example program. Warning: When you fnish your study with an example and try to take a look at another example, do not forget to comment the current example program before uncommenting another

34

Programmable Logic Controller

one. In other words, make sure that only one example program is uncommented and tested at a time. Otherwise if you somehow leave more than one example uncommented, the example you are trying to test probably will not function as expected as it may try to access the same resources that are being used and changed by other examples. Please check the accuracy of each program by cross-referencing it with the related macros.

1.17.1 EXAMPLE 1.1 Example 1.1 shows the usage of the following arithmetical macros: “R1addR2”, “R1subR2”, “RaddK”, and “RsubK”. The user program of Example 1.1 is shown in Figure 1.20. The ladder diagram of Example 1.1 is depicted in Figure 1.21. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 1.1 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to “ON” position. Next, you can test the operation of this example. In rung 1, Q1 is cleared, i.e. 8-bit constant value “00h” is loaded into Q1, by using the macro “load_R”. This process is carried out once, at the frst program scan, by using the “FRSTSCN” NO contact. Another condition to carry out the same process is the NO contact of the input I0.0. This means that, when this program is run, during the normal PLC operation, if we force the input I0.0 to be true, then the above-mentioned process will take place. In rungs 2 and 3, we see how the arithmetical macro “R1addR2” could be used. In rung 2, the addition process Q1 = I1 + Q1 is carried out, when I0.1 goes true. With this rung, if I0.1 goes and stays true, the content of I1 will be added to the content of Q1 on every PLC scan. Rung 3 provides a slightly different usage of the arithmetical macro “R1addR2”. Here, we use a “rising edge detector” macro in order to detect the state change of input I0.2 from OFF to ON. So, this time, the addition process Q1 = I1 + Q1 is carried out only at the rising edges of I0.2. In rungs 4 and 5, we see how the arithmetical macro “R1subR2” could be used. In rung 4, the subtraction process Q1 = Q1 – I1 is carried out when I0.3 goes true. With this rung, if I0.3 goes and stays true, the content of I1 will be subtracted from the content of Q1 on every PLC scan. In rung 5, a “rising edge detector” macro is used in order to detect the state change of input I0.4 from OFF to ON. So, this time, the subtraction process Q1 = Q1 – I1 is carried out only at the rising edges of I0.4. In rungs 6 and 7, we see how the arithmetical macro “RaddK” could be used. In rung 6, the addition process Q1 = Q1 + 2 is carried out when I0.5 goes true. With this rung, if I0.5 goes and stays true, the constant value 2 will

Arithmetical Macros

FIGURE 1.20 The user program of “Example 1.1”.

be added to the content of Q1 on every PLC scan. In rung 7, a “rising edge detector” macro is used in order to detect the state change of input I0.6 from OFF to ON. So, this time, the addition process Q1 = Q1 + 2 is carried out only at the rising edges of I0.6. In rung 8, the subtraction process Q1 = Q1 – 3 is carried out with the rising edges of I0.7.

35

36

FIGURE 1.21

Programmable Logic Controller

The ladder diagram of the user program of “Example 1.1”.

Arithmetical Macros

FIGURE 1.22

The user program of “Example 1.2”.

FIGURE 1.23

The ladder diagram of the user program of “Example 1.2”.

37

1.17.2 EXAMPLE 1.2 Example 1.2 shows the usage of the arithmetical macro “R1addR2_16”. The user program of Example 1.2 is shown in Figure 1.22. The ladder diagram of Example 1.2 is depicted in Figure 1.23. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 1.2 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. Rung 1 shows how the arithmetical macro “R1addR2_16” could be used. In this rung, the 16-bit addition process OUT := R1 + R2 is carried out with the following: EN = LOGIC1. R1 is a 16-bit source variable consisting of two 8-bit source variables, I3 and I2. I3 is the high byte of R1, and I2 is the low byte of R1. R2 is a 16-bit source variable consisting of two 8-bit source variables, I1 and I0. I1 is the high byte of R2, and I0 is the low byte of R2. OUT is a 16-bit source variable consisting of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. In rung 2, the state of carry bit C is sent to the digital output Q2.0 : Q2.0 = STATUS,C. Recall that, in this 16-bit addition, if the sum is greater than 16-bit, then the carry bit is set; else it is reset.

38

Programmable Logic Controller

1.17.3

EXAMPLE 1.3

Example 1.3 shows the usage of the arithmetical macro “R1subR2_16”. The user program of Example 1.3 is shown in Figure 1.24. The ladder diagram of Example 1.3 is depicted in Figure 1.25. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 1.3 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. Rung 1 shows how the arithmetical macro “R1subR2_16” could be used. In this rung, the 16-bit subtraction process OUT := R1 - R2 is carried out with the following: EN = LOGIC1. R1 is a 16-bit source variable consisting of two 8-bit source variables, I3 and I2. I3 is the high byte of R1, and I2 is the low byte of R1. R2 is a 16-bit source variable consisting of two 8-bit source variables, I1 and I0. I1 is the high byte of R2, and I0 is the low byte of R2. OUT is a 16-bit source variable consisting of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. In rung 2, the state of carry bit C is sent to the digital output Q2.0 : Q2.0 = STATUS,C. Recall that, in this 16-bit subtraction, if the result is negative, then the carry bit is reset; else it is set.

FIGURE 1.24

The user program of “Example 1.3”.

FIGURE 1.25 The ladder diagram of the user program of “Example 1.3”.

Arithmetical Macros

1.17.4

39

EXAMPLE 1.4

Example 1.4 shows the usage of the following arithmetical macros: “RaddK_16” and “RsubK_16”. The user program of Example 1.4 is shown in Figure 1.26. The ladder diagram of Example 1.4 is depicted in Figure 1.27. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 1.4 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN”

FIGURE 1.26 The user program of “Example 1.4”.

40

Programmable Logic Controller

FIGURE 1.27 The ladder diagram of the user program of “Example 1.4”.

and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, Q0 and Q1 are cleared, i.e. 8-bit constant value “00h” is loaded into Q0 and into Q1, by using two “load_R” macros. This process is carried out once, at the frst program scan, by using the “FRSTSCN” NO contact.

Arithmetical Macros

Another condition to carry out the same process is the NO contact of the input I0.0. This means that, when this program is run, during the normal PLC operation, if we force the input I0.0 to be true, then the above mentioned process will take place. Rung 2 shows how the arithmetical macro “RaddK_16” could be used. In this rung, the 16-bit addition process OUT := R + K is carried out with the following: EN = I0.1. R is a 16-bit source variable consisting of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of R, and Q0 is the low byte of R. K is a 16-bit constant value defned as 100Fh. OUT is a 16-bit source variable consisting of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. When EN = I0.1 = 1, this instruction will add 100Fh to OUT on every PLC scan. Rung 3 provides a slightly different usage of the arithmetical macro “RaddK_16”. Here, we use a “rising edge detector” macro in order to detect the state change of input I0.2 from OFF to ON. So, this time, the addition process OUT := R + K is carried out only at the rising edges of I0.2 with the following: EN = ↑ I0.2. R is a 16-bit source variable consisting of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of R, and Q0 is the low byte of R. K is a 16-bit constant value defned as 100Fh. OUT is a 16-bit source variable consisting of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. In rung 4, we see how the arithmetical macro “RsubK_16” could be used. In this rung, the subtraction process OUT = R – K is carried out when I0.3 goes true. With this rung, if I0.3 goes and stays true, 16-bit constant value 100Fh will be subtracted from the contents of the 16-bit source variable R, and the result will be stored in a 16-bit destination variable OUT, on every PLC scan. R consists of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of R, and Q0 is the low byte of R. OUT consists of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. In rung 5, a “rising edge detector” macro is used in order to detect the state change of input I0.4 from OFF to ON. So, this time, the subtraction process OUT := R – K (the arithmetical macro “RsubK_16”) is carried out with each rising edge signal of I0.4. With this rung, the 16-bit constant value 100Fh will be subtracted from the contents of the 16-bit source variable R, and the result will be stored in a 16-bit destination variable OUT, on each rising edge signal of I0.4. R consists of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of R, and Q0 is the low byte of R. OUT consists of two 8-bit source variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. In rung 6, the 16-bit addition process OUT := R + K (the arithmetical macro “RaddK_16”) is carried out, when I0.5 goes true. With this rung, if I0.5 goes and stays true, the 16-bit constant value 100Fh will be added to the contents of 16-bit source variable R, and the result will be stored in the 16-bit destination register OUT on every PLC scan. R consists of two 8-bit source variables, I3 and I2. I3 is the high byte of R, and I2 is the low byte

41

42

Programmable Logic Controller

of R. OUT consists of two 8-bit source variables, Q3 and Q2. Q3 is the high byte of OUT, and Q2 is the low byte of OUT. In rung 7, the 16-bit subtraction process OUT := R - K (the arithmetical macro “RsubK_16”) is carried out, when I0.5 goes false. With this rung, if I0.5 goes and stays false, the 16-bit constant value 00FFh will be subtracted from the contents of 16-bit source variable R, and the result will be stored in the 16-bit destination register OUT on every PLC scan. R consists of two 8-bit source variables, I3 and I2. I3 is the high byte of R, and I2 is the low byte of R. OUT consists of two 8-bit source variables, Q3 and Q2. Q3 is the high byte of OUT, and Q2 is the low byte of OUT.

1.17.5 EXAMPLE 1.5 Example 1.5 shows the usage of the arithmetical macro “R1mulR2”. The user program of Example 1.5 is shown in Figure 1.28. The ladder diagram of Example 1.5 is depicted in Figure 1.29. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 1.5 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, two instances of the multiplication process OUT := R1 × R2 (the arithmetical macro “R1mulR2”) are carried out:

FIGURE 1.28 The user program of “Example 1.5”.

FIGURE 1.29 The ladder diagram of the user program of “Example 1.5”.

Arithmetical Macros

43

First multiplication: EN = LOGIC1. R1 is an 8-bit source variable, R1 = I0. R2 is an 8-bit source variable, R2 = I1. OUT is a 16-bit destination variable consisting of two 8-bit variables, Q1 and Q0. Q1 is the high byte of OUT, and Q0 is the low byte of OUT. Second multiplication: EN = LOGIC1. R1 is an 8-bit source variable, R1 = I2. R2 is an 8-bit source variable, R2 = I3. OUT is a 16-bit destination variable consisting of two 8-bit variables, Q3 and Q2. Q3 is the high byte of OUT, and Q2 is the low byte of OUT. Both multiplications will be carried out in an endless loop as both enable inputs are LOGIC1.

1.17.6 EXAMPLE 1.6 Example 1.6 shows the usage of the arithmetical macro “DivU16by8”. The user program of Example 1.6 is shown in Figure 1.30. The ladder diagram of Example 1.6 is depicted in Figure 1.31. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 1.6 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the division process OUT := R1 / R2 is carried out with each rising edge of I3.0. Here, a “rising edge detector” macro is used in order to detect

FIGURE 1.30 The user program of “Example 1.6”.

FIGURE 1.31

The ladder diagram of the user program of “Example 1.6”.

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Programmable Logic Controller

the state change of input I3.0 from OFF to ON. EN = ↑I3.0. R1 is a 16-bit source variable (dividend). It consists of two 8-bit variables, R1H (DvdH = I2) and R1L (DvdL = I1). R1H (DvdH) holds the high byte of R1, and R1L (DvdL) holds the low byte of R1. R2 (Divisor = I0) is an 8-bit source variable and it refers to the divisor. OUT (Quot = Q0) is an 8-bit destination variable to which the result of the integer division is stored. It refers to the quotient.

1.17.7

EXAMPLE 1.7

Example 1.7 shows the usage of the following arithmetical macros: “incR”, “decR”, “incR_16”, “decR_16”. The user program of Example 1.7 is shown in Figure 1.32. The ladder diagram of Example 1.7 is depicted in Figure 1.33. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 1.7 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, Q0, Q1, and Q2 are cleared, i.e. 8-bit constant value “00h” is loaded into Q0, Q1, and Q2, by using the three instances of macro “load_R”. This process is carried out once, at the frst program scan, by using the “FRSTSCN” NO contact. Another condition to carry out the same process is the NO contact of the input I0.0. This means that, when this program is run, during the normal PLC operation, if we force the input I0.0 to be true, then the above-mentioned process will take place. In rung 2, when I0.1 goes and stays true, Q0 is incremented on every PLC scan. In rung 3, Q0 is incremented with each rising edge of I0.2. In rung 4, when I0.3 goes and stays true, Q0 is decremented on every PLC scan. In rung 5, Q0 is decremented with each rising edge of I0.4. In rung 6, when I1.0 goes and stays true, the 16-bit output variable consisting of Q2 (high byte) and Q1 (low byte) is incremented on every PLC scan. In rung 7, with each rising edge of I1.1, the 16-bit output variable consisting of Q2 (high byte) and Q1 (low byte) is incremented. In rung 8, when I1.2 goes and stays true, the 16-bit output variable consisting of Q2 (high byte) and Q1 (low byte) is decremented on every PLC scan. In rung 9, with each rising edge of I1.3, the 16-bit output variable consisting of Q2 (high byte) and Q1 (low byte) is decremented.

1.17.8 EXAMPLE 1.8 Example 1.8 shows the usage of the following arithmetical macros: “Hbit_CNT” and “Lbit_CNT”. The user program of Example 1.8 is shown in Figure 1.34. The

Arithmetical Macros

FIGURE 1.32 The user program of “Example 1.7”.

45

46

FIGURE 1.33

Programmable Logic Controller

The ladder diagram of the user program of “Example 1.7”.

Arithmetical Macros

FIGURE 1.34

47

The user program of “Example 1.8”.

FIGURE 1.35 The ladder diagram of the user program of “Example 1.8”.

ladder diagram of Example 1.8 is depicted in Figure 1.35. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 1.8 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “Hbit_CNT” instruction is used with EN = LOGIC1, reg,bit = I0.1, N = 31, Counter = Q0. This instruction is always enabled (EN = LOGIC1). First, this instruction counts the number of HIGH (set) bits among 31 bits, starting from I0.0. Then, the count value is stored in Q0. In rung 2, the “Lbit_CNT” instruction is used with EN = LOGIC1, reg,bit = I0.1, N = 31, Counter = Q1. This instruction is always enabled (EN =

48

Programmable Logic Controller

LOGIC1). First, this instruction counts the number of LOW (reset) bits among 31 bits starting from I0.1. Then, the count value is stored in Q1.

1.17.9

EXAMPLE 1.9

Example 1.9 shows the usage of the following arithmetical macros: “Hbit_CNT” and “Lbit_CNT”, together with the macro “fll_sram_N80”. For a detailed explanation of the “fll_sram_N80” (Fill up to 80 variables with values in a Bank) macro, the reader is referred to Chapter 3 of the Advanced Concepts volume of this series. In brief, this macro flls the chosen N (a constant value from 1 to 80) consecutive SRAM registers in a Bank with a value from 00h to FFh. The user program of Example 1.9 is shown in Figure 1.36. The ladder diagram of Example 1.9 is depicted in Figure 1.37. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 1.9 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch

FIGURE 1.36

The user program of “Example 1.9”.

Arithmetical Macros

49

FIGURE 1.37 The ladder diagram of the user program of “Example 1.9”.

the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “fll_sram_N80” instruction is used with EN = I0.0&I0.1 & I0.2, IN1 = 020h, N = 32, Value = 0, Operator = ‘ ’, and K = 1. When this instruction is enabled (EN = I0.0&I0.1&I0.2 = 100), it flls 32 consecutive registers of Bank 0 from 020h to 03Fh with the value of 00h, as shown in Figure 1.38.(a). In rung 2, the “fll_sram_N80” instruction is used with EN = I0.1&10.0 & 10.2, IN1 = 020h, N = 32, Value = 0Fh, Operator = ‘ ’, K = 1. When this instruction is enabled (EN = I0.1&I0.0&I0.2 = 100), it flls 32 consecutive registers of Bank 0 from 020h to 03Fh with the value of 0Fh, as shown in Figure 1.38.(b).

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Programmable Logic Controller

FIGURE 1.38 Allocation of the user data in Bank 0 for Example 1.9. (a) After I0.0 is forced to be 1, while I0.1 = 0 & I0.2 = 0; (b) after I0.1 is forced to be 1, while I0.0 = 0 & I0.2 = 0; (c) after I0.2 is forced to be 1, while I0.0 = 0 & I0.1 = 0.

In rung 3, the “fll_sram_N80” instruction is used with EN = I0.2&10.0 & 10.1, IN1 = 020h, N = 32, Value = FFh, Operator = ‘ ’, and K = 1. When this instruction is enabled (EN = I0.2&I0.0&I0.1 = 100), it flls 32 consecutive registers of Bank 0 from 020h to 03Fh with the value of FFh, as shown in Figure 1.38.(c). In rung 4, the “Hbit_CNT” instruction is used with EN = LOGIC1, reg,bit = 020h,0, N = 255, Counter = Q0. This instruction is always enabled (EN = LOGIC1). First, this instruction counts the number of HIGH (set) bits among 255 bits, starting from 020h,0. Then, the count value is stored in Q0. In rung 5, the “Lbit_CNT” instruction is used with EN = LOGIC1, reg,bit = 020h,0, N = 255, Counter = Q1. This instruction is always enabled (EN = LOGIC1). First, this instruction counts the number of LOW (reset) bits among 255 bits, starting from 020h,0. Then, the count value is stored in Q1.

Arithmetical Macros

51

REFERENCES R1.1. Application Note AN526 of Microchip posted at www.microchip.com/wwwappnotes/ appnotes.aspx?appnote=en011000 (accessed in 2016) R1.2. Peter H. Anderson, Morgan State University, Baltimore, MD 21239 posted at www.p handerson.com/PIC/16C84/calc_disc_2.html (accessed in 2016)

2

Logical Macros

INTRODUCTION A logical function performs AND, NAND, OR, NOR, exclusive-OR (XOR), exclusiveNOR (XNOR), logical operations on two registers (or one register plus one constant value), and NOT (invert) logical operation on one register. As an example, Figure 2.1 shows an AND logical function that will retrieve and “AND” two values from sources labelled source A and source B and will store the result in destination C. AND, NAND, OR, NOR, XOR, and XNOR logical functions have the form of Figure 2.1, with two source values and one destination register. In these, the logical function is applied to the two source values, and the result is put in the destination register. However, the unary invert (INV) logical function has one source register and one destination register. It inverts all of the bits in the source register and puts the result in the destination register. In this chapter, the following logical macros are described for the PIC16F1847Based PLC: R1andR2 (R1 AND R2), RandK (R AND K), R1nandR2 (R1 NAND R2), RnandK (R NAND K), R1orR2 (R1 OR R2), RorK (R OR K), R1norR2 (R1 NOR R2), RnorK (R NOR K), R1xorR2 (R1 EXOR R2), RxorK (R EXOR K), R1xnorR2 (R1 EXNOR R2), RxnorK (R EXNOR K), inv_R (Complement of R). Table 2.1 shows the logic gates, symbols, and their truth tables. This table is provided to be used as a reference in the study of the macros explained in this chapter. The fle “PICPLC_PIC16F1847_macros_Int.inc”, which is downloadable from this book’s webpage under the downloads section, contains macros defned for the PIC16F1847Based PLC explained in this volume (Intermediate Concepts). Let us now consider the logical macros in detail.

2.1

MACRO “R1ANDR2”

The algorithm and the symbol of the macro “R1andR2” are depicted in Table 2.2. Figure 2.2 shows the macro “R1andR2” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a 53

54

Programmable Logic Controller

FIGURE 2.1

The AND function.

TABLE 2.1 Logic Gates, Symbols and Their Truth Tables Logic Gate 2-input AND gate

2-input NAND gate

2-input OR gate

2-input NOR gate

2-input EXOR gate

2-input EXNOR gate

Inverter

Symbol

Truth Table a

b

c

0 0 1 1 a 0 0 1 1 a 0 0 1 1 a 0 0 1 1 a 0 0 1 1 a 0 0 1 1

0 1 0 1 b 0 1 0 1 b 0 1 0 1 b 0 1 0 1 b 0 1 0 1 b 0 1 0 1

0 0 0 1 c 1 1 1 0 c 0 1 1 1 c 1 0 0 0 c 0 1 1 0 c 1 0 0 1

a 0

c 1

1

0

55

Logical Macros

TABLE 2.2 Algorithm and the Symbol of the Macro “R1andR2” Algorithm

Symbol

if EN = 1 then OUT := R1 AND R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. This is especially useful if we want to carry out more than one operation based on a single input condition. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Booleanenable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1andR2” applies the logical AND function to the corresponding bits of the two 8-bit input variables, R1

FIGURE 2.2

The macro “R1andR2” and its fowchart.

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Programmable Logic Controller

FIGURE 2.3

Schematic representation of the macro “R1andR2”, when EN = 1.

and R2, and stores the result into the 8-bit output variable OUT (OUT := R1 AND R2). Figure 2.3 shows the schematic representation of the macro “R1andR2”, when EN = 1. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

2.2

MACRO “RANDK”

The algorithm and the symbol of the macro “RandK” are depicted in Table 2.3. Figure 2.4 shows the macro “RandK” and its fowchart. In this macro, EN is a

TABLE 2.3 Algorithm and the Symbol of the Macro “RandK” Algorithm

Symbol

if EN = 1 then OUT := R AND K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

Logical Macros

57

FIGURE 2.4 The macro “RandK” and its fowchart.

Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RandK” applies the logical AND function to the corresponding bits of the 8-bit input variable R and the 8-bit constant value K and stores the result into the 8-bit output variable OUT (OUT := R AND K). Figure 2.5 shows the schematic representation of the macro “RandK”, when EN = 1. Assumption: The operands “R” and “OUT” can be in any Bank.

2.3

MACRO “R1NANDR2”

The algorithm and the symbol of the macro “R1nandR2” are depicted in Table 2.4. Figure 2.6 shows the macro “R1nandR2” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1nandR2” applies the logical NAND function to the corresponding bits of the two 8-bit input variables R1 and R2 and stores the result

58

Programmable Logic Controller

TABLE 2.4 Algorithm and the Symbol of the Macro “R1nandR2” Algorithm

Symbol

if EN = 1 then OUT := R1 NAND R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

into the 8-bit output variable OUT (OUT := R1 NAND R2). Figure 2.7 shows the schematic representation of the macro “R1nandR2”, when EN = 1. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

2.4

MACRO “RNANDK”

The algorithm and the symbol of the macro “RnandK” are depicted in Table 2.5. Figure 2.8 shows the macro “RnandK” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a

FIGURE 2.5

Schematic representation of the macro “RandK”, when EN = 1.

Logical Macros

FIGURE 2.6

59

The macro “R1nandR2” and its fowchart.

Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal

FIGURE 2.7

Schematic representation of the macro “R1nandR2”, when EN = 1.

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Programmable Logic Controller

TABLE 2.5 Algorithm and the Symbol of the Macro “RnandK” Algorithm

Symbol

if EN = 1 then OUT := R NAND K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RnandK” applies the logical NAND function to the corresponding bits of the 8-bit input variable R and the 8-bit constant value K and stores the result into the 8-bit output variable OUT (OUT := R NAND K). Figure 2.9 shows the schematic representation of the macro “RnandK”, when EN = 1. Assumption: The operands “R” and “OUT” can be in any Bank.

2.5

MACRO “R1ORR2”

The algorithm and the symbol of the macro “R1orR2” are depicted in Table 2.6. Figure 2.10 shows the macro “R1orR2” and its fowchart. In this macro, EN is a

FIGURE 2.8 The macro “RnandK” and its fowchart.

61

Logical Macros

FIGURE 2.9 Schematic representation of the macro “RnandK”, when EN = 1.

Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When

TABLE 2.6 Algorithm and the Symbol of the Macro “R1orR2” Algorithm

Symbol

if EN = 1 then OUT := R1 OR R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

62

Programmable Logic Controller

FIGURE 2.10 The macro “R1orR2” and its fowchart.

EN = 1, the macro “R1orR2” applies the logical OR function to the corresponding bits of the two 8-bit input variables R1 and R2 and stores the result into the 8-bit output variable OUT (OUT := R1 OR R2). Figure 2.11 shows the schematic representation of the macro “R1orR2”, when EN = 1. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

FIGURE 2.11

Schematic representation of the macro “R1orR2”, when EN = 1.

63

Logical Macros

2.6 MACRO “RORK” The algorithm and the symbol of the macro “RorK” are depicted in Table 2.7. Figure 2.12 shows the macro “RorK” and its fowchart. In this macro, EN is a Booleaninput-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this TABLE 2.7 Algorithm and the Symbol of the Macro “RorK” Algorithm

Symbol

if EN = 1 then OUT := R OR K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 2.12 The macro “RorK” and its fowchart.

64

Programmable Logic Controller

FIGURE 2.13 Schematic representation of the macro “RorK”, when EN = 1.

macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RorK” applies the logical OR function to the corresponding bits of the 8-bit input variable R and the 8-bit constant value K and stores the result into the 8-bit output variable OUT (OUT := R OR K). Figure 2.13 shows the schematic representation of the macro “RorK”, when EN = 1. Assumption: The operands “R” and “OUT” can be in any Bank.

2.7

MACRO “R1NORR2”

The algorithm and the symbol of the macro “R1norR2” are depicted in Table 2.8. Figure 2.14 shows the macro “R1norR2” and its fowchart. In this macro, EN is a TABLE 2.8 Algorithm and the Symbol of the Macro “R1norR2” Algorithm

Symbol

if EN = 1 then OUT := R1 NOR R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

Logical Macros

FIGURE 2.14

65

The macro “R1norR2” and its fowchart.

Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1norR2” applies the logical NOR function to the corresponding bits of the two 8-bit input variables R1 and R2 and stores the result into the 8-bit output variable OUT (OUT := R1 NOR R2). Figure 2.15 shows the schematic representation of the macro “R1norR2”, when EN = 1. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

2.8 MACRO “RNORK” The algorithm and the symbol of the macro “RnorK” are depicted in Table 2.9. Figure 2.16 shows the macro “RnorK” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that. when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RnorK” applies the logical NOR function to the corresponding bits of the 8-bit input variable R and the 8-bit constant value K and stores

66

Programmable Logic Controller

FIGURE 2.15

Schematic representation of the macro “R1norR2”, when EN = 1.

TABLE 2.9 Algorithm and the Symbol of the Macro “RnorK” Algorithm

Symbol

if EN = 1 then OUT := R NOR K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

the result into the 8-bit output variable (OUT := R NOR K). Figure 2.17 shows the schematic representation of the macro “RnorK”, when EN = 1. Assumption: The operands “R” and “OUT” can be in any Bank.

2.9

MACRO “R1XORR2”

The algorithm and the symbol of the macro “R1xorR2” are depicted in Table 2.10. Figure 2.18 shows the macro “R1xorR2” and its fowchart. In this macro, EN is a

Logical Macros

FIGURE 2.16

67

The macro “RnorK” and its fowchart.

Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the

FIGURE 2.17 Schematic representation of the macro “RnorK”, when EN = 1.

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Programmable Logic Controller

TABLE 2.10 Algorithm and the Symbol of the Macro “R1xorR2” Algorithm

Symbol

if EN = 1 then OUT := R1 EXOR R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1xorR2” applies the logical EXOR function to the corresponding bits of the two 8-bit input variables R1 and R2 and stores the result into the 8-bit output variable OUT (OUT := R1 EXOR R2). Figure 2.19 shows the schematic representation of the macro “R1xorR2”, when EN = 1. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

FIGURE 2.18

The macro “R1xorR2” and its fowchart.

69

Logical Macros

FIGURE 2.19

Schematic representation of the macro “R1xorR2”, when EN = 1.

2.10 MACRO “RXORK” The algorithm and the symbol of the macro “RxorK” are depicted in Table 2.11. Figure 2.20 shows the macro “RxorK” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to TABLE 2.11 Algorithm and the Symbol of the Macro “RxorK” Algorithm

Symbol

if EN = 1 then OUT := R EXOR K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

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Programmable Logic Controller

FIGURE 2.20 The macro “RxorK” and its fowchart.

which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “RxorK” applies the logical EXOR function to the corresponding bits of the 8-bit input variable R and the 8-bit constant value K and stores the result into the 8-bit output variable OUT (OUT := R EXOR K). Figure 2.21 shows

FIGURE 2.21 Schematic representation of the macro “RxorK”, when EN = 1.

71

Logical Macros

TABLE 2.12 Algorithm and the Symbol of the Macro “R1xnorR2 Algorithm

Symbol

if EN = 1 then OUT := R1 EXNOR R2; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R2 (8-bit source variable, R2) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

the schematic representation of the macro “RxorK”, when EN = 1. Assumption: The operands “R” and “OUT” can be in any Bank.

2.11 THE MACRO “R1XNORR2” The algorithm and the symbol of the macro “R1xnorR2” are depicted in Table 2.12. Figure 2.22 shows the macro “R1xnorR2” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO

FIGURE 2.22

The macro “R1xnorR2” and its fowchart.

72

FIGURE 2.23

Programmable Logic Controller

Schematic representation of the macro “R1xnorR2”, when EN = 1.

is forced to be 1. R1 and R2 refer to 8-bit source variables from where the source values are taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “R1xnorR2” applies the logical EXNOR function to the corresponding bits of the two 8-bit input variables R1 and R2 and stores the result into the 8-bit output variable OUT (OUT := R1 EXNOR R2). Figure 2.23 shows the schematic representation of the macro “R1xnorR2”, when EN = 1. Assumption: The operands “R1”, “R2”, and “OUT” can be in any Bank.

2.12 MACRO “RXNORK” The algorithm and the symbol of the macro “RxnorK” are depicted in Table 2.13. Figure 2.24 shows the macro “RxnorK” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that when EN = 0, ENO is forced to be 0 and when EN = 1, ENO is forced to be 1. R and K are source values. R refers to an 8-bit source variable, and K represents an 8-bit constant value. OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enableinput signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1 the macro “RxnorK” applies the logical EXNOR function to the corresponding bits of the 8-bit input variable R and the 8-bit constant value K and stores the result into the 8-bit output variable OUT (OUT := R EXNOR K). Figure 2.25 shows the schematic representation of

73

Logical Macros

TABLE 2.13 Algorithm and the Symbol of the Macro “RxnorK” Algorithm

Symbol

if EN = 1 then OUT := R EXNOR K; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 R (8-bit source variable, R) K (8-bit constant value, K) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 2.24

The macro “RxnorK” and its fowchart.

the macro “RxnorK”, when EN = 1. Assumption: The operands “R” and “OUT” can be in any Bank.

2.13 MACRO “INVR” The algorithm and the symbol of the macro “inv_R” are depicted in Table 2.14. Figure 2.26 shows the macro “inv_R” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input

74

Programmable Logic Controller

FIGURE 2.25

Schematic representation of the macro “RxnorK”, when EN = 1.

TABLE 2.14 Algorithm and the Symbol of the Macro “inv_R” Algorithm

Symbol

if EN = 1 then OUT := inverted IN; ENO := 1; else ENO := 0; endif; EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit source variable, IN) OUT (8-bit destination variable, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. IN refers to an 8-bit source variable from where the source value is taken into the macro, and OUT refers to an 8-bit destination variable to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “inv_R” forms the 1’s complement of the 8-bit source variable IN and stores the result into the 8-bit destination register OUT (OUT := inverted IN). Figure 2.27 shows the schematic representation of the macro “inv_R”, when EN = 1. Assumption: The operands “IN” and “OUT” can be in any Bank.

Logical Macros

FIGURE 2.26

The macro “inv_R” and its fowchart.

FIGURE 2.27

Schematic representation of the macro “inv_R”, when EN = 1.

75

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Programmable Logic Controller

2.14

AN EXAMPLE FOR LOGICAL MACROS

Up to now in this chapter, we have seen logical macros developed for the PIC16F1847Based PLC. It is now time to consider some examples related to these macros. Before you can run the example program considered here, you are expected to construct your own PIC16F1847-Based PLC hardware by using the necessary PCB fles and by producing your PCBs, with their components. For an effective use of examples, all example programs considered in this book are allocated within the fle “PICPLC _PIC16F1847_user_Int.inc”, which is downloadable from this book’s webpage under the downloads section. Initially, all example programs are commented out by putting a semicolon “;” in front of each line. When you would like to test one of the example programs, you must uncomment each line of the example program by following the steps shown below: 1. Highlight the block of source lines you want to uncomment by dragging the mouse with the left mouse button held down over these lines. With default coloring in MPLAB X IDE, you will now see green characters on a blue background. 2. Release the mouse button. 3. Press Ctrl/Shift/C or press “Alt”, “S”, and “M” keys in succession or, from the toolbar “Source” menu, select “Toggle Comment”. Now a semicolon will be removed from all selected source lines. With default coloring, you will see red characters on a white background. Then, you can run the project by pressing the symbol from the toolbar. Next, the MPLAB X IDE will produce the “PICPLC_PIC16F1847.X.production.hex” fle for the project. Then, the MPLAB X IDE will be connected to the PICkit3 programmer and, fnally, it will program the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC. During these steps, make sure that, in the CPU board of the PIC16F1847-Based PLC, the 4PDT switch is in “PROG” position and the power switch is in “OFF” position. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Finally, you are ready to test the example program. Warning: When you fnish your study with an example and try to take a look at another example, do not forget to comment the current example program before uncommenting another one. In other words, make sure that only one example program is uncommented and tested at a time. Otherwise, if you somehow leave more than one example uncommented, the example you are trying to test probably will not function as expected, as it may try to access the same resources that are being used and changed by other examples. Please check the accuracy of the example program by cross-referencing it with the related macros. Example 2.1 shows the usage of the all logical macros considered in this chapter. The user program of Example 2.1 is shown in Figure 2.28. The ladder diagram of Example 2.1 is depicted in Figure 2.29. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 2.1 and run the project by pressing the symbol

Logical Macros

FIGURE 2.28 The user program of “Example 2.1” .

77

78

FIGURE 2.28 Continued

Programmable Logic Controller

Logical Macros

FIGURE 2.29

The ladder diagram of the user program of “Example 2.1”.

79

80

FIGURE 2.29

Programmable Logic Controller

Continued

81

Logical Macros

from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, both Q1 and Q2 are cleared, i.e. 8-bit value “00h” is loaded into both Q1 and Q2, by using the NO contact of I0.3. This means that, when I0.3 = 0, Q1 and Q2 will be cleared. In rung 2, a “3 to 8 decoder” is implemented: Enable input = I0.3, select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the inputs I0.3, I0.2, I0.1, and I0.0. Table 2.15 shows the truth table based on the input data entered through I0.3, I0.2, I0.1, and I0.0, and the 8 memory bits chosen. TABLE 2.15 Selection of Memory Bits Based on the Inputs I0.3, I0.2, I0.1, and I0.0 I0.3

I0.2

I0.1

I0.0

Memory Bit

0

×

×

×

-

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

M0.0 M0.1 M0.2 M0.3 M0.4 M0.5 M0.6 M0.7

× : Don’t care.

TABLE 2.16 Selection of Logical Processes Based on Memory Bits Memory Bit

Logical Process Selected

M0.0

Q1 := INV I1, Q2 := INV I2

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := I1 AND I2 Q1 := I1 NAND I2 := INV M2 (M2 := I1 AND I2) Q1 := I1 NAND I2 Q1 := I1 OR I2 Q1 := I1 NOR I2 Q1 := I1 XOR I2

M0.7

Q1 := I1 XNOR I2

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Programmable Logic Controller

In 8 rungs from 3 and 10, we defne different logical operations according to the decoder outputs represented by the memory bits M0.0, M0.1, M0.2, M0.3, M0.4, M0.5, M0.6, and M0.7. In each of these eight rungs, a logical process is carried out, as shown in Table 2.16. For example, if M0.7 = 1, then the following operation is done: Q1 := I1 XNOR I2. This means that the macro “R1xnorR2” applies the logical XNOR function to the two 8-bit input variables I1 and I2 and stores the result into the 8-bit output variable Q1. It should be obvious that, as only one of the memory bits (M0.0, M0.1, M0.2, M0.3, M0.4, M0.5, M0.6, and M0.7) is active at any time, only one of the processes shown in Table 2.16 can be carried out at a time. In rung 11, Q3 is cleared, i.e. 8-bit value “00h” is loaded into Q3, by using the NC contact of I0.7. This means that, when I0.7 = 0, Q3 will be cleared. In rung 12, a “3 to 8 decoder” is implemented: Enable input = I0.7, select inputs s2,s1,s0 = I0.6, I0.5, and I0.4, and decoder outputs are d7 = M1.7, d6 = M1.6, d5 = M1.5, d4 = M1.4, d3 = M1.3, d2 = M1.2, d1 = M1.1, d0 = M1.0. This TABLE 2.17 Selection of Memory Bits Based on the Inputs I0.7, I0.6, I0.5, and I0.4 I0.7

I0.6

I0.5

I0.4

0

×

×

×

Memory Bit -

1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1

M1.0 M1.1 M1.2 M1.3 M1.4 M1.5 M1.6 M1.7

× : Don’t care.

TABLE 2.18 Selection of Logical Processes Based on Memory Bits Memory Bit

Logical Process Selected

M1.0

Q3 := I3 AND 50h

M1.1 M1.2 M1.3 M1.4 M1.5 M1.6

Q3 := I3 NAND 50h := INV M3 (M3 := I3 AND 50h) Q3 := I3 NAND 50h Q3 := I3 OR 50h Q3 := I3 NOR 50h := INV M4 (M4 := I3 OR 50h) Q3 := I3 NOR 50h Q3 := I3 XOR 50h

M1.7

Q3 := I3 XNOR 50h

Logical Macros

arrangement is made to choose 8 different memory bits based on the input data given through the inputs I0.7, I0.6, I0.5, and I0.4. Table 2.17 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, and the 8 memory bits chosen. In 8 rungs from 13 and 20, we defne different logical operations according to the decoder outputs represented by the memory bits M1.0, M1.1, M1.2, M1.3, M1.4, M1.5, M1.6, and M1.7. In each of these eight rungs, a logical process is carried out, as shown in Table 2.17. For example, if M1.7 = 1, then the following operation is done: Q3 := I3 XNOR 50h. This means that the macro “RxnorK” applies the logical XNOR function to the 8-bit input variable I3 and the 8-bit constant value 50h and stores the result into the 8-bit output variable Q3. It should be obvious that, as only one of the memory bits (M1.0, M1.1, M1.2, M1.3, M1.4, M1.5, M1.6, and M1.7) is active at any time, only one of the processes shown in Table 2.18 can be carried out at a time.

83

3

Shift and Rotate Macros

INTRODUCTION A shift (SHIFT) function moves the bits in a register to the right or to the left. As an example, Figure 3.1 shows a shift right function that retrieves the input data from the source register A and shifts the bits of the source register A towards the right as many numbers as specifed by the number of shift, and the serial data are taken from the left through the Boolean-input-variable “shift in bit”. The result of the shift operation is stored in a destination register B. In this case, the Least Signifcant Bit (LSB) is shifted out as many numbers as specifed by the number of shift. A shift left function is identical, except that the shift in bit, taken from the right, is moved in the opposite direction towards the left, shifting out the Most Signifcant Bit (MSB) as many numbers as specifed by the number of shift. A rotate (ROTATE) function, like a shift function, shifts data to the right or left, but, instead of losing the shift-out bit, this bit becomes the shift-in bit at the other end of the register (rotated bit). The number of rotation defnes how many bits will be rotated to the right or left. Similar to the shift function, the result of the rotate operation is stored in the destination register B. In this chapter, the following shift and rotate macros are described for the PIC16F1847-Based PLC: Ashift_R (Arithmetic Shift Right Rin), Ashift_R_16 (Arithmetic Shift Right Rin), Lshift_R (Logical Shift Right Rin), Lshift_R_16 (Logical Shift Right Rin), Lshift_L (Logical Shift Left Rin), Lshift_L_16 (Logical Shift Left Rin), shift_R (Shift Right Rin), shift_R_16 (Shift Right Rin), shift_L (Shift Left Rin), shift_L_16 (Shift Left Rin), rotate_R (Rotate Right Rin), rotate_R_16 (Rotate Right Rin), rotate_L (Rotate Left Rin), rotate_L_16 (Rotate Left Rin), Swap (Swap Rin). The fle “PICPLC_PIC16F1847_macros_Int.inc”, which is downloadable from this book’s webpage under the downloads section, contains macros defned for the PIC16F1847-Based PLC explained in this volume (Intermediate Concepts). Let us now consider the shift and rotate macros in detail. 85

86

Programmable Logic Controller

FIGURE 3.1 The SHIFT RIGHT function.

3.1 MACRO “ASHIFT_R” (ARITHMETIC SHIFT RIGHT RIN) The symbol and the algorithm of the macro “Ashift_R” are depicted in Table 3.1. Figures 3.2 and 3.3 show the macro “Ashift_R” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. This is especially useful if we want to carry out more than one operation based on a single input condition. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of arithmetic shift right, which can be any number in 1, 2, …, 7. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “Ashift_R” retrieves the 8-bit input data from Rin and moves them to the destination variable Rout. Then, the contents of Rout are shifted towards the right as TABLE 3.1 Symbol and the Algorithm of the Macro “Ashift_R” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) N (the number of arithmetic shift right, n) = 1, 2, …, 7 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN right-shifted by N bits, the MSB remains unchanged; ENO := 1; else ENO := 0; endif;

Shift and Rotate Macros

FIGURE 3.2

87

The macro “Ashift_R”.

many numbers as specifed by N, and the MSB, i.e., Rout, remains unchanged. The result of this arithmetic shift right operation remains in Rout. Figure 3.4 shows the schematic representation of the macro “Ashift_R”, when EN = 1. Assumption: The operands “Rin” and “Rout” can be in any Bank.

3.2 MACRO “ASHIFT_R_16” (ARITHMETIC SHIFT RIGHT RIN) The symbol and the algorithm of the macro “Ashift_R_16” are depicted in Table 3.2. Figures 3.5 and 3.6 show the macro “Ashift_R_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of Rin, and RinL holds the low byte of Rin. “ROUT” refers to a 16-bit destination variable to which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low byte of ROUT.

88

FIGURE 3.3

Programmable Logic Controller

The fowchart of the macro “Ashift_R”.

FIGURE 3.4 Schematic representation of the macro “Ashift_R”, when EN = 1.

Shift and Rotate Macros

89

TABLE 3.2 Symbol and the Algorithm of the Macro “Ashift_R_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) N (the number of arithmetic shift right, n) = 1, 2, …, 15 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN right-shifted by N bits, the MSB remains unchanged; ENO := 1; else ENO := 0; endif;

N represents the number of arithmetic shift right, which can be any number in 1, 2, …, 15. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “Ashift_R_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are shifted towards the right as many numbers as specifed by N, and the MSB, i.e., Rout, remains unchanged. The result of this arithmetic shift right operation remains in Rout. Figure 3.7 shows the schematic representation of the macro “Ashift_R_16”, when EN = 1. Assumption: The operands “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

3.3 MACRO “LSHIFT_R” (LOGICAL SHIFT RIGHT RIN) The symbol and the algorithm of the macro “Lshift_R” are depicted in Table 3.3. Figures 3.8 and 3.9 show the macro “Lshift_R” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of logical shift right, which can be any number in 1, 2, …, 7. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “Lshift_R” retrieves the 8-bit input data

90

Programmable Logic Controller

FIGURE 3.5

The macro “Ashift_R_16”.

from Rin and moves them to the destination variable Rout. Then, the contents of Rout are shifted towards the right as many numbers as specifed by N, and a ‘0’ is shifted into the MSB, i.e., Rout. The result of this logical shift right operation remains in Rout. Figure 3.10 shows the schematic representation of the macro “Lshift_R”, when EN = 1. Assumption: The operands “Rin” and “Rout” can be in any Bank.

3.4

MACRO “LSHIFT_R_16” (LOGICAL SHIFT RIGHT RIN)

The symbol and the algorithm of the macro “Lshift_R_16” are depicted in Table 3.4. Figures 3.11 and 3.12 show the macro “Lshift_R_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and

Shift and Rotate Macros

FIGURE 3.6

91

The fowchart of the macro “Ashift_R_16”.

ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of RIN, and RinL holds the low byte of RIN. “ROUT” refers to a 16-bit destination variable to which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low

92

FIGURE 3.7

Programmable Logic Controller

Schematic representation of the macro “Ashift_R_16”, when EN = 1.

TABLE 3.3 Symbol and the Algorithm of the Macro “Lshift_R” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) N (the number of logical shift right, n) = 1, 2, …, 7 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN right-shifted by N bits, zero-flled on left; ENO := 1; else ENO := 0; endif;

byte of ROUT. N represents the number of logical shift right, which can be any number in 1, 2, …, 15. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “Lshift_R_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are shifted towards the right as many numbers as specifed by N, and a ‘0’ is shifted into the MSB, i.e., Rout. The result of this logical shift right operation remains in Rout. Figure 3.13 shows the schematic representation of the macro “Lshift_R_16”, when

Shift and Rotate Macros

93

FIGURE 3.8 The macro “Lshift_R”.

EN = 1. Assumption: The operands “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

3.5 MACRO “LSHIFT_L” (LOGICAL SHIFT LEFT RIN) The symbol and the algorithm of the macro “Lshift_L” are depicted in Table 3.5. Figures 3.14 and 3.15 show the macro “Lshift_L” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of logical shift left, which can be any number in 1, 2, …, 7. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “Lshift_L” retrieves the 8-bit input data from

94

Programmable Logic Controller

FIGURE 3.9 The fowchart of the macro “Lshift_R”.

Rin and moves them to the destination variable Rout. Then, the contents of Rout are shifted towards the left as many numbers as specifed by N, and a ‘0’ is shifted into the LSB, i.e., Rout. The result of this logical shift left operation remains in Rout. Figure 3.16 shows the schematic representation of the macro “Lshift_L”, when EN = 1. Assumption: The operands “Rin” and “Rout” can be in any Bank.

3.6 MACRO “LSHIFT_L_16” (LOGICAL SHIFT LEFT RIN) The symbol and the algorithm of the macro “Lshift_L_16” are depicted in Table 3.6. Figures 3.17 and 3.18 show the macro “Lshift_L_16” and its fowchart, respectively.

Shift and Rotate Macros

95

FIGURE 3.10 Schematic representation of the macro “Lshift_R”, when EN = 1.

TABLE 3.4 Symbol and the Algorithm of the Macro “Lshift_R_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) N (the number of logical shift right, n) = 1, 2, …, 15 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN right-shifted by N bits, zero-flled on left; ENO := 1; else ENO := 0; endif;

In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of RIN, and RinL holds the low byte of RIN. “ROUT” refers to a 16-bit destination variable to which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low

96

FIGURE 3.11

Programmable Logic Controller

The macro “Lshift_R_16”.

byte of ROUT. N represents the number of logical shift left, which can be any number in 1, 2, …, 15. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “Lshift_L_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are shifted towards the left as many numbers as specifed by N, and a ‘0’ is shifted into the LSB, i.e., Rout. The result of this logical shift left operation remains in Rout. Figure 3.19 shows the schematic representation of the macro “Lshift_L_16”, when EN = 1. Assumption: The operands “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

Shift and Rotate Macros

97

FIGURE 3.12 The fowchart of the macro “Lshift_R_16”.

3.7 MACRO “SHIFT_R” (SHIFT RIGHT RIN) The symbol and the algorithm of the macro “shift_R” are depicted in Table 3.7. Figures 3.20 and 3.21 show the macro “shift_R” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and,

98

Programmable Logic Controller

FIGURE 3.13 Schematic representation of the macro “Lshift_R_16”, when EN = 1.

TABLE 3.5 Symbol and the Algorithm of the Macro “Lshift_L” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) N (the number of logical shift left, n) = 1, 2, …, 7 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN left-shifted by N bits, zero-flled on right; ENO := 1; else ENO := 0; endif;

when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of shift right, which can be any number in 1, 2, …, 8. SIN (reg,bit) is the Boolean-input-variable “shift in bit”. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “shift_R” retrieves the 8-bit input data from Rin and moves them to the destination variable Rout. Then, the contents of Rout are shifted

Shift and Rotate Macros

99

FIGURE 3.14 The macro “Lshift_L”.

towards the right as many numbers as specifed by N, and the serial data are taken from the left through SIN (reg,bit). The result of this shift right operation remains in Rout. Figure 3.22 shows the schematic representation of the macro “shift_R”, when EN = 1. Assumption: The operands “reg,bit”, “Rin”, and “Rout” can be in any Bank.

3.8 MACRO “SHIFT_R_16” (SHIFT RIGHT RIN) The symbol and the algorithm of the macro “shift_R_16” are depicted in Table 3.8. Figures 3.23 and 3.24 show the macro “shift_R_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of RIN, and RinL holds the low byte of RIN. “ROUT” refers to a 16-bit destination variable to

100

FIGURE 3.15

Programmable Logic Controller

The fowchart of the macro “Lshift_L”.

which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low byte of ROUT. N represents the number of shift right, which can be any number in 1, 2, …, 16. SIN (reg,bit) is the Boolean-input-variable “shift in bit”. The Boolean-enableinput signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “shift_R_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are shifted towards the right as many numbers as specifed by N, and the serial data is taken from the left through SIN (reg,bit). The result of this shift

Shift and Rotate Macros

FIGURE 3.16

101

Schematic representation of the macro “Lshift_L”, when EN = 1.

TABLE 3.6 Symbol and the Algorithm of the Macro “Lshift_L_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) N (the number of logical shift left, n) = 1, 2, …, 15 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN left-shifted by N bits, zero-flled on right; ENO := 1; else ENO := 0; endif;

right operation remains in Rout. Figure 3.25 shows the schematic representation of the macro “shift_R_16”, when EN = 1. Assumption: The operands “reg,bit”, “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

3.9 MACRO “SHIFT_L” (SHIFT LEFT RIN) The symbol and the algorithm of the macro “shift_L” are depicted in Table 3.9. Figures 3.26 and 3.27 show the macro “shift_L” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO

102

Programmable Logic Controller

FIGURE 3.17 The macro “Lshift_L_16”.

follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of shift left, which can be any number in 1, 2, …, 8. SIN (reg,bit) is the Boolean-input-variable “shift in bit”. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst the macro “shift_L” retrieves the 8-bit input data from Rin and moves them to the destination variable Rout. Then, the contents of Rout are shifted towards the left as many numbers as specifed by N, and the serial data are taken from the right through SIN (reg,bit). The result of this shift left operation remains in

Shift and Rotate Macros

103

FIGURE 3.18 The fowchart of the macro “Lshift_L_16”.

Rout. Figure 3.28 shows the schematic representation of the macro “shift_L”, when EN = 1. Assumption: The operands “reg,bit”, “Rin”, and “Rout” can be in any Bank.

3.10 MACRO “SHIFT_L_16” (SHIFT LEFT RIN) The symbol and the algorithm of the macro “shift_L_16” are depicted in Table 3.10. Figures 3.29 and 3.30 show the macro “shift_L_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the

104

FIGURE 3.19

Programmable Logic Controller

Schematic representation of the macro “Lshift_L_16”, when EN = 1.

TABLE 3.7 Symbol and the Algorithm of the Macro “shift_R” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) SIN (serial input bit from an input register, reg,bit) = 0 or 1 N (the number of shift right, n) = 1, 2, …, 8 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN right-shifted by N bits, flled on left by the serial data taken from SIN; ENO := 1; else ENO := 0; endif;

input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of RIN, and RinL holds the low byte of RIN. “ROUT” refers to a 16-bit destination variable to which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low byte of ROUT. N represents the number of shift left, which can be any number in 1, 2, …, 16. SIN (reg,bit) is the Boolean-input-variable

Shift and Rotate Macros

105

FIGURE 3.20 The macro “shift_R”.

“shift in bit”. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “shift_L_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are shifted towards the left as many numbers as specifed by N, and the serial data are taken from the right through SIN (reg,bit). The result of this shift left operation remains in Rout. Figure 3.31 shows the schematic representation of the macro “shift_L_16”, when EN = 1. Assumption: The operands “reg,bit”, “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

3.11

MACRO “ROTATE_R” (ROTATE RIGHT RIN)

The symbol and the algorithm of the macro “rotate_R” are depicted in Table 3.11. Figures 3.32 and 3.33 show the macro “rotate_R” and its fowchart, respectively. In

106

FIGURE 3.21 The fowchart of the macro “shift_R”.

Programmable Logic Controller

Shift and Rotate Macros

FIGURE 3.22

107

Schematic representation of the macro “shift_R”, when EN = 1.

TABLE 3.8 Symbol and the Algorithm of the Macro “shift_R_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) SIN (serial input bit from an input register, reg,bit) = 0 or 1 N (the number of shift right, n) = 1, 2, …, 16 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN right-shifted by N bits, flled on left by the serial data taken from SIN; ENO := 1; else ENO := 0; endif;

this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of rotation, which can be any number in 1, 2, …, 7. The Boolean-enable-input

108

FIGURE 3.23

Programmable Logic Controller

The macro “shift_R_16”.

signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “rotate_R” retrieves the 8-bit input data from Rin and moves them to the destination variable Rout. Then, the contents of Rout are rotated towards the right as many numbers as specifed by N. The result of this rotate right operation remains in Rout. Figure 3.34 shows the schematic representation of the macro “rotate_R”, when EN = 1. Assumption: The operands “Rin” and “Rout” can be in any Bank.

Shift and Rotate Macros

FIGURE 3.24

The fowchart of the macro “shift_R_16”.

109

110

Programmable Logic Controller

FIGURE 3.25

Schematic representation of the macro “shift_R_16”, when EN = 1.

TABLE 3.9 Symbol and the Algorithm of the Macro “shift_L” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) SIN (serial input bit from an input register, reg,bit) = 0 or 1 N (the number of shift left, n) = 1, 2, …, 8 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN left-shifted by N bits, flled on right by the serial data taken from SIN; ENO := 1; else ENO := 0; endif;

3.12

MACRO “ROTATE_R_16” (ROTATE RIGHT RIN)

The symbol and the algorithm of the macro “rotate_R_16” are depicted in Table 3.12. Figures 3.35 and 3.36 show the macro “rotate_R_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that when EN = 0, ENO is forced to be 0, and,

Shift and Rotate Macros

FIGURE 3.26

111

The macro “shift_L”.

when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of RIN, and RinL holds the low byte of RIN. “ROUT” refers to a 16-bit destination variable to which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low byte of ROUT. N represents the number of rotation, which can be any number in 1, 2, …, 15. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “rotate_R_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are rotated towards the right as many numbers as specifed by N. The result of this rotate right operation remains in Rout. Figure 3.37 shows the schematic representation of the macro “rotate_R_16”,

112

FIGURE 3.27

Programmable Logic Controller

The fowchart of the macro “shift_L”.

Shift and Rotate Macros

113

FIGURE 3.28 Schematic representation of the macro “shift_L”, when EN = 1.

TABLE 3.10 Symbol and the Algorithm of the Macro “shift_L_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) SIN (serial input bit from an input register, reg,bit) = 0 or 1 N (the number of shift left, n) = 1, 2, …, 16 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN left-shifted by N bits, flled on right by the serial data taken from SIN; ENO := 1; else ENO := 0; endif;

when EN = 1. Assumption: The operands “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

3.13

MACRO “ROTATE_L” (ROTATE LEFT RIN)

The symbol and the algorithm of the macro “rotate_L” are depicted in Table 3.13. Figures 3.38 and 3.39 show the macro “rotate_L” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and

114

Programmable Logic Controller

FIGURE 3.29 The macro “shift_L_16”.

ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. N represents the number of rotation, which can be any number in 1, 2, …, 7. The Boolean-enableinput signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst the macro “rotate_L” retrieves the 8-bit

Shift and Rotate Macros

FIGURE 3.30 The fowchart of the macro “shift_L_16”.

115

116

FIGURE 3.31

Programmable Logic Controller

Schematic representation of the macro “shift_L_16”, when EN = 1.

TABLE 3.11 Symbol and the Algorithm of the Macro “rotate_R” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) N (the number of rotation, n) = 1, 2, …, 7 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN right-rotated by N bits, circular; ENO := 1; else ENO := 0; endif;

input data from Rin and moves them to the destination variable Rout. Then, the contents of Rout are rotated towards the left as many numbers as specifed by N. The result of this rotate left operation remains in Rout. Figure 3.40 shows the schematic representation of the macro “rotate_L”, when EN = 1. Assumption: The operands “Rin” and “Rout” can be in any Bank.

3.14 MACRO “ROTATE_L_16” (ROTATE LEFT RIN) The symbol and the algorithm of the macro “rotate_L_16” are depicted in Table 3.14. Figures 3.41 and 3.42 show the macro “rotate_L_16” and its fowchart, respectively.

Shift and Rotate Macros

117

FIGURE 3.32 The macro “rotate_R”.

In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to a 16-bit source variable and consists of two 8-bit variables, RinH and RinL. RinH holds the high byte of RIN, and RinL holds the low byte of RIN. “ROUT” refers to a 16-bit destination variable to which the result of the macro is stored. ROUT consists of two 8-bit variables, RoutH and RoutL. RoutH holds the high byte of ROUT, and RoutL holds the low byte of ROUT. N represents the number of rotation, which can be any number in 1, 2, …, 15. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the macro “rotate_L_16” retrieves the 16-bit input data from Rin and moves them to the 16-bit destination variable Rout. Then, the contents of Rout are rotated towards the left as many numbers as specifed by N. The result of this rotate left operation remains in Rout. Figure 3.43 shows the schematic representation of the macro “rotate_L_16”,

118

FIGURE 3.33 The fowchart of the macro “rotate_R”.

Programmable Logic Controller

Shift and Rotate Macros

FIGURE 3.34

119

Schematic representation of the macro “rotate_R”, when EN = 1.

TABLE 3.12 Symbol and the Algorithm of the Macro “rotate_R_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) N (the number of rotation, n) = 1, 2, …, 15 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN right-rotated by N bits, circular; ENO := 1; else ENO := 0; endif;

when EN = 1. Assumption: The operands “RinH”, “RinL”, “RoutH”, and “RoutL” can be in any Bank.

3.15 MACRO “SWAP” The symbol and the algorithm of the macro “Swap” are depicted in Table 3.15. Figure 3.44 shows the macro “Swap” and its fowchart. In this macro, EN is a Boolean-inputvariable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that,

120

FIGURE 3.35

Programmable Logic Controller

The macro “rotate_R_16”.

when EN = 0, ENO is forced to be 0, and, when EN = 1, ENO is forced to be 1. “RIN” refers to an 8-bit source variable Rin from where the source value is taken into the macro, and “ROUT” refers to an 8-bit destination variable Rout to which the result of the macro is stored. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “Swap” retrieves the 8-bit input data from Rin and swaps (exchanges the upper and lower nibbles – 4-bits) the nibbles of Rin. The result of the swap operation is stored in the 8-bit destination variable Rout. Figure 3.45 shows the schematic

Shift and Rotate Macros

FIGURE 3.36 The fowchart of the macro “rotate_R_16”.

121

122

Programmable Logic Controller

FIGURE 3.37

Schematic representation of the macro “rotate_R_16”, when EN = 1.

TABLE 3.13 Symbol and the Algorithm of the Macro “rotate_L” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) N (the number of rotation, n) = 1, 2, …, 7 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := RIN left-rotated by N bits, circular; ENO := 1; else ENO := 0; endif;

representation of the macro “Swap”, when EN = 1. Assumption: The operands “Rin” and “Rout” can be in any Bank.

3.16

EXAMPLES FOR SHIFT AND ROTATE MACROS

Up to now in this chapter, we have seen shift and rotate macros developed for the PIC16F1847-Based PLC. It is now time to consider some examples related to these macros.

Shift and Rotate Macros

123

FIGURE 3.38 The macro “rotate_L”.

Before you can run the example programs considered here, you are expected to construct your own PIC16F1847-Based PLC hardware by using the necessary PCB fles and by producing your PCBs, with their components. For an effective use of examples, all example programs considered in this book are allocated within the fle “PICPLC_PIC16F1847 _user_Int.inc”, which is downloadable from this book’s webpage under the downloads section. Initially, all example programs are commented out by putting a semicolon, “;”, in front of each line. When you would like to test one of the example programs, you must uncomment each line of the example program by following the steps shown below: 1. Highlight the block of source lines you want to uncomment by dragging the mouse with the left mouse button held down over these lines. With default coloring in MPLAB X IDE, you will now see green characters on a blue background. 2. Release the mouse button.

124

FIGURE 3.39 The fowchart of the macro “rotate_L”.

Programmable Logic Controller

Shift and Rotate Macros

FIGURE 3.40

125

Schematic representation of the macro “rotate_L”, when EN = 1.

TABLE 3.14 Symbol and the Algorithm of the Macro “rotate_L_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (16-bit source variable, consisting of two 8-bit variables RinH&RinL) N (the number of rotation, n) = 1, 2, …, 15 ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (16-bit destination variable, consisting of two 8-bit variables RoutH&RoutL) Algorithm if EN = 1, then ROUT := RIN left-rotated by N bits, circular; ENO := 1; else ENO := 0; endif;

3. Press Ctrl/Shift/C or press “Alt”, “S”, and “M” keys in succession or, from the toolbar “Source” menu, select “Toggle Comment”. Now, a semicolon will be removed from all selected source lines. With default coloring, you will see red characters on a white background. Then, you can run the project by pressing the symbol from the toolbar. Next, the MPLAB X IDE will produce the “PICPLC_PIC16F1847.X.production.hex” fle for the project. Then, the MPLAB X IDE will be connected to the PICkit3 programmer and, fnally, it will program the PIC16F1847 microcontroller within the CPU

126

FIGURE 3.41

Programmable Logic Controller

The macro “rotate_L_16”.

board of the PIC16F1847-Based PLC. During these steps, make sure that, in the CPU board of the PIC16F1847-Based PLC, the 4PDT switch is in the “PROG” position, and the power switch is in the “OFF” position. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Finally, you are ready to test the example program. Warning: When you fnish your study with an example and try to take a look at another example, do not forget to comment the current example program before uncommenting another one. In other words, make sure that only one example program is uncommented and tested at a time. Otherwise, if you somehow leave more than one

Shift and Rotate Macros

FIGURE 3.42 The fowchart of the macro “rotate_L_16”.

127

128

Programmable Logic Controller

FIGURE 3.43 Schematic representation of the macro “rotate_L_16”, when EN = 1.

TABLE 3.15 Symbol and the Algorithm of the Macro “Swap” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 RIN (8-bit source variable, Rin) ENO (Boolean-enable-output, through W) = 0 or 1 ROUT (8-bit destination variable, Rout) Algorithm if EN = 1, then ROUT := swapped RIN; ENO := 1; else ENO := 0; endif;

example uncommented, the example you are trying to test probably will not function as expected, as it may try to access the same resources that are being used and changed by other examples. Please check the accuracy of each program by cross-referencing it with the related macros. When studying the shift and rotate examples, note that the register Q0 (respectively, Q1; Q2; Q3; I0; I1; I2; and I3) is made up of the 8-bits: Q0.7, Q0.6, …, Q0.0 (respectively, Q1.7, Q1.6, …, I1.0; Q2.7, Q2.6, …, I2.0; Q3.7, Q3.6, …, I3.0; I0.7, I0.6, …, I0.0; I1.7, I1.6, …, I1.0; I2.7, I2.6, …, I2.0; and I3.7, I3.6, …, I3.0), and that Q0.7 (respectively, Q1.7; Q2.7; Q3.7; I0.7; I1.7; I2.7; and I3.7) is the MSB, and Q0.0 (respectively, Q1.0; Q2.0; Q3.0; I0.0; I1.0; I2.0; and I3.0) is the LSB.

Shift and Rotate Macros

FIGURE 3.44

3.16.1

129

The macro “Swap” and its fowchart.

EXAMPLE 3.1

Example 3.1 shows the usage of the arithmetic shift right macros “Ashift_R” and “Ashift_R_16” and the macro “Swap”. The user program of Example 3.1 is shown in Figure 3.46. The ladder diagram of Example 3.1 is depicted in Figure 3.47. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 3.1 and run

FIGURE 3.45 Schematic representation of the macro “Swap”, when EN = 1.

130

FIGURE 3.46 The user program of “Example 3.1”.

Programmable Logic Controller

Shift and Rotate Macros

131

FIGURE 3.46 Continued

the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5,

132

Programmable Logic Controller

FIGURE 3.46 Continued

d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.16 shows the truth table based on the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected Swap or arithmetic shift right process. Note that, at any time, only one of the outputs of the “3 to 8 decoder”

Shift and Rotate Macros

FIGURE 3.47 The ladder diagram of the user program of “Example 3.1”.

133

134

Programmable Logic Controller

FIGURE 3.47 Continued

(i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active. In rung 2, when M0.0 = 1, the swap operation “Q1 := Swap (I1)” is carried out. In rung 3, when the rising edge of M0.1 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 once” is carried out. The rising

Shift and Rotate Macros

135

FIGURE 3.47 Continued

edge of M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 twice” is carried out. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2.

136

Programmable Logic Controller

TABLE 3.16 The Truth Table 1 of the User Program of “Example 3.1” I0.1

I0.0

Memory Bit

0

0

0

M0.0

Q1 := Swap I1

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Arithmetic shift right I1 once Q1 := Arithmetic shift right I1 twice Q1 := Arithmetic shift right I1 3 times Q1 := Arithmetic shift right I1 4 times Q1 := Arithmetic shift right I1 5 times Q1 := Arithmetic shift right I1 6 times

1

1

1

M0.7

Q1 := Arithmetic shift right I1 7 times

I0.2

Selected Process

In rung 5, when the rising edge of M0.3 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 3 times” is carried out. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3. In rung 6, when the rising edge of M0.4 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 4 times” is carried out. The rising edge of M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 5 times” is carried out. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5. In rung 8, when the rising edge of M0.6 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 6 times” is carried out. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the arithmetic shift right operation “Q1 := Arithmetic shift right I1 7 times” is carried out. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7. In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation, we obtain the following: Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6,

137

Shift and Rotate Macros

TABLE 3.17 The Truth Table 2 of the User Program of “Example 3.1” I0.6

I0.5

I0.4

Memory Bit

0

0

0

0

M2.0

No process is selected

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Arithmetic shift right I3,I2 once Q3,Q2 := Arithmetic shift right I3,I2 twice Q3,Q2 := Arithmetic shift right I3,I2 3 times Q3,Q2 := Arithmetic shift right I3,I2 4 times Q3,Q2 := Arithmetic shift right I3,I2 5 times Q3,Q2 := Arithmetic shift right I3,I2 6 times Q3,Q2 := Arithmetic shift right I3,I2 7 times Q3,Q2 := Arithmetic shift right I3,I2 8 times Q3,Q2 := Arithmetic shift right I3,I2 9 times Q3,Q2 := Arithmetic shift right I3,I2 10 times Q3,Q2 := Arithmetic shift right I3,I2 11 times Q3,Q2 := Arithmetic shift right I3,I2 12 times Q3,Q2 := Arithmetic shift right I3,I2 13 times Q3,Q2 := Arithmetic shift right I3,I2 14 times

1

1

1

1

M3.7

Q3,Q2 := Arithmetic shift right I3,I2 15 times

I0.7

Selected Process

d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.17 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected arithmetic shift right process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active. In rung 12, when the rising edge of M2.1 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 once” is carried out. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. In rung 13, when the rising edge of M2.2 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 twice” is carried out. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2. In rung 14, when the rising edge of M2.3 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 3 times” is carried out. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3.

138

Programmable Logic Controller

In rung 15, when the rising edge of M2.4 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 4 times” is carried out. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. In rung 16, when the rising edge of M2.5 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 5 times” is carried out. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. In rung 17, when the rising edge of M2.6 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 6 times” is carried out. The rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6. In rung 18, when the rising edge of M2.7 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 7 times” is carried out. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. In rung 19, when the rising edge of M3.0 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 8 times” is carried out. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0. In rung 20, when the rising edge of M3.1 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 9 times” is carried out. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. In rung 21, when the rising edge of M3.2 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 10 times” is carried out. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2. In rung 22, when the rising edge of M3.3 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 11 times” is carried out. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. In rung 23, when the rising edge of M3.4 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 12 times” is carried out. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4. In rung 24, when the rising edge of M3.5 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 13 times” is carried out. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. In rung 25, when the rising edge of M3.6 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 14 times” is carried out. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. In rung 26, when the rising edge of M3.7 is detected, the arithmetic shift right operation “Q3,Q2 := Arithmetic shift right I3,I2 15 times” is carried out.

Shift and Rotate Macros

139

The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

3.16.2

EXAMPLE 3.2

Example 3.2 shows the usage of the logical shift right macros “Lshift_R” and “Lshift_R_16” and the macro “Swap”. The user program of Example 3.2 is shown in Figure 3.48. The ladder diagram of Example 3.2 is depicted in Figure 3.49. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 3.2 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.18 shows the truth table based on the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected Swap or logical shift right process. Note that, at any time, only one of the outputs of the “3 to 8 decoder” (i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active. In rung 2, when M0.0 = 1, the swap operation “Q1 := Swap (I1)” is carried out. In rung 3, when the rising edge of M0.1 is detected, the logical shift right operation “Q1 := Logical shift right I1 once” is carried out. The rising edge of M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the logical shift right operation “Q1 := Logical shift right I1 twice” is carried out. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2. In rung 5, when the rising edge of M0.3 is detected, the logical shift right operation “Q1 := Logical shift right I1 3 times” is carried out. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3. In rung 6, when the rising edge of M0.4 is detected, the logical shift right operation “Q1 := Logical shift right I1 4 times” is carried out. The rising edge of M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the logical shift right operation “Q1 := Logical shift right I1 5 times” is carried out. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5.

140

FIGURE 3.48

Programmable Logic Controller

The user program of “Example 3.2”.

Shift and Rotate Macros

FIGURE 3.48

141

Continued

In rung 8, when the rising edge of M0.6 is detected, the logical shift right operation “Q1 := Logical shift right I1 6 times” is carried out. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the logical shift right operation “Q1 := Logical shift right I1 7 times” is carried out. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7.

142

Programmable Logic Controller

FIGURE 3.48

Continued

In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation we obtain the following: Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

Shift and Rotate Macros

FIGURE 3.49 The ladder diagram of the user program of “Example 3.2”.

143

144

FIGURE 3.49 Continued

Programmable Logic Controller

Shift and Rotate Macros

FIGURE 3.49 Continued

145

146

Programmable Logic Controller

TABLE 3.18 The Truth Table 1 of the User Program of “Example 3.2” I0.1

I0.0

Memory Bit

0

0

0

M0.0

Q1 := Q1 = Swap I1

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Logical shift right I1 once Q1 := Logical shift right I1 twice Q1 := Logical shift right I1 3 times Q1 := Logical shift right I1 4 times Q1 := Logical shift right I1 5 times Q1 := Logical shift right I1 6 times

1

1

1

M0.7

Q1 := Logical shift right I1 7 times

I0.2

Selected Process

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.19 shows the truth table based on the input data

TABLE 3.19 The Truth Table 2 of the User Program of “Example 3.2” I0.7

I0.6

I0.5

I0.4

Memory Bit

Selected Process

0

0

0

0

M2.0

No process is selected

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Logical shift right I3,I2 once Q3,Q2 := Logical shift right I3,I2 twice Q3,Q2 := Logical shift right I3,I2 3 times Q3,Q2 := Logical shift right I3,I2 4 times Q3,Q2 := Logical shift right I3,I2 5 times Q3,Q2 := Logical shift right I3,I2 6 times Q3,Q2 := Logical shift right I3,I2 7 times Q3,Q2 := Logical shift right I3,I2 8 times Q3,Q2 := Logical shift right I3,I2 9 times Q3,Q2 := Logical shift right I3,I2 10 times Q3,Q2 := Logical shift right I3,I2 11 times Q3,Q2 := Logical shift right I3,I2 12 times Q3,Q2 := Logical shift right I3,I2 13 times Q3,Q2 := Logical shift right I3,I2 14 times

1

1

1

1

M3.7

Q3,Q2 := Logical shift right I3,I2 15 times

Shift and Rotate Macros

In

In

In

In

In

In

In

In

In

In

147

entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected logical shift right process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active. rung 12, when the rising edge of M2.1 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 once” is carried out. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. rung 13, when the rising edge of M2.2 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 twice” is carried out. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2. rung 14, when the rising edge of M2.3 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 3 times” is carried out. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3. rung 15, when the rising edge of M2.4 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 4 times” is carried out. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. rung 16, when the rising edge of M2.5 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 5 times” is carried out. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. rung 17, when the rising edge of M2.6 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 6 times” is carried out. The rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6. rung 18, when the rising edge of M2.7 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 7 times” is carried out. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. rung 19, when the rising edge of M3.0 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 8 times” is carried out. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0. rung 20, when the rising edge of M3.1 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 9 times” is carried out. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. rung 21, when the rising edge of M3.2 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 10 times” is carried out. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2.

148

Programmable Logic Controller

In rung 22, when the rising edge of M3.3 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 11 times” is carried out. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. In rung 23, when the rising edge of M3.4 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 12 times” is carried out. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4. In rung 24, when the rising edge of M3.5 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 13 times” is carried out. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. In rung 25, when the rising edge of M3.6 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 14 times” is carried out. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. In rung 26, when the rising edge of M3.7 is detected, the logical shift right operation “Q3,Q2 := Logical shift right I3,I2 15 times” is carried out. The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

3.16.3

EXAMPLE 3.3

Example 3.3 shows the usage of the logical shift left macros “Lshift_L” and “Lshift_L_16” and the macro “Swap”. The user program of Example 3.3 is shown in Figure 3.50. The ladder diagram of Example 3.3 is depicted in Figure 3.51. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 3.3 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.20 shows the truth table based on the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected Swap or logical shift left process. Note that, at any time, only one of the outputs of the “3 to 8 decoder” (i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active. In rung 2, when M0.0 = 1, the swap operation “Q1 := Swap (I1)” is carried out. In rung 3, when the rising edge of M0.1 is detected, the logical shift left operation “Q1 := Logical shift left I1 once” is carried out. The rising edge of

Shift and Rotate Macros

FIGURE 3.50

The user program of “Example 3.3”.

149

150

FIGURE 3.50

Programmable Logic Controller

Continued

M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the logical shift left operation “Q1 := Logical shift left I1 twice” is carried out. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2.

Shift and Rotate Macros

FIGURE 3.50

151

Continued

In rung 5, when the rising edge of M0.3 is detected, the logical shift left operation “Q1 := Logical shift left I1 3 times” is carried out. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3. In rung 6, when the rising edge of M0.4 is detected, the logical shift left operation “Q1 := Logical shift left I1 4 times” is carried out. The rising edge of

152

Programmable Logic Controller

FIGURE 3.51 The ladder diagram of the user program of “Example 3.3”.

Shift and Rotate Macros

FIGURE 3.51 Continued

153

154

Programmable Logic Controller

FIGURE 3.51 Continued

M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the logical shift left operation “Q1 := Logical shift left I1 5 times” is carried out. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5.

155

Shift and Rotate Macros

TABLE 3.20 The Truth Table 1 of the User Program of “Example 3.3” I0.1

I0.0

Memory Bit

0

0

0

M0.0

Q1 := Swap I1

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Logical shift left I1 once Q1 := Logical shift left I1 twice Q1 := Logical shift left I1 3 times Q1 := Logical shift left I1 4 times Q1 := Logical shift left I1 5 times Q1 := Logical shift left I1 6 times

1

1

1

M0.7

Q1 := Logical shift left I1 7 times

I0.2

Selected Process

In rung 8, when the rising edge of M0.6 is detected, the logical shift left operation “Q1 := Logical shift left I1 6 times” is carried out. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the logical shift left operation “Q1 := Logical shift left I1 7 times” is carried out. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7. In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation we obtain the following:

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.21 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected logical shift left process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active.

156

Programmable Logic Controller

TABLE 3.21 The Truth Table 2 of the User Program of “Example 3.3” I0.6

I0.5

I0.4

Memory Bit

0

0

0

0

M2.0

No process is selected

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Logical shift left I3,I2 once Q3,Q2 := Logical shift left I3,I2 twice Q3,Q2 := Logical shift left I3,I2 3 times Q3,Q2 := Logical shift left I3,I2 4 times Q3,Q2 := Logical shift left I3,I2 5 times Q3,Q2 := Logical shift left I3,I2 6 times Q3,Q2 := Logical shift left I3,I2 7 times Q3,Q2 := Logical shift left I3,I2 8 times Q3,Q2 := Logical shift left I3,I2 9 times Q3,Q2 := Logical shift left I3,I2 10 times Q3,Q2 := Logical shift left I3,I2 11 times Q3,Q2 := Logical shift left I3,I2 12 times Q3,Q2 := Logical shift left I3,I2 13 times Q3,Q2 := Logical shift left I3,I2 14 times

1

1

1

1

M3.7

Q3,Q2 := Logical shift left I3,I2 15 times

I0.7

Selected Process

In rung 12, when the rising edge of M2.1 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 once” is carried out. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. In rung 13, when the rising edge of M2.2 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 twice” is carried out. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2. In rung 14, when the rising edge of M2.3 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 3 times” is carried out. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3. In rung 15, when the rising edge of M2.4 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 4 times” is carried out. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. In rung 16, when the rising edge of M2.5 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 5 times” is carried out. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. In rung 17, when the rising edge of M2.6 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 6 times” is carried out. The

Shift and Rotate Macros

In

In

In

In

In

In

In

In

In

157

rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6. rung 18, when the rising edge of M2.7 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 7 times” is carried out. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. rung 19, when the rising edge of M3.0 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 8 times” is carried out. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0. rung 20, when the rising edge of M3.1 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 9 times” is carried out. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. rung 21, when the rising edge of M3.2 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 10 times” is carried out. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2. rung 22, when the rising edge of M3.3 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 11 times” is carried out. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. rung 23, when the rising edge of M3.4 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 12 times” is carried out. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4. rung 24, when the rising edge of M3.5 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 13 times” is carried out. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. rung 25, when the rising edge of M3.6 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 14 times” is carried out. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. rung 26, when the rising edge of M3.7 is detected, the logical shift left operation “Q3,Q2 := Logical shift left I3,I2 15 times” is carried out. The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

3.16.4 EXAMPLE 3.4 Example 3.4 shows the usage of the shift right macros “shift_R” and “shift_R_16” and the macro “Swap”. The user program of Example 3.4 is shown in Figure 3.52. The ladder diagram of Example 3.4 is depicted in Figure 3.53. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 3.4 and run the project by

158

FIGURE 3.52

Programmable Logic Controller

The user program of “Example 3.4”.

Shift and Rotate Macros

FIGURE 3.52

Continued

159

160

FIGURE 3.52

Programmable Logic Controller

Continued

pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

Shift and Rotate Macros

FIGURE 3.53 The ladder diagram of the user program of “Example 3.4”.

161

162

FIGURE 3.53 Continued

Programmable Logic Controller

Shift and Rotate Macros

163

FIGURE 3.53 Continued

In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.22 shows the truth table based on

164

Programmable Logic Controller

TABLE 3.22 The Truth Table 1 of the User Program of “Example 3.4” I0.1

I0.0

Memory Bit

Selected Process

0

0

0

M0.0

Q1 := Shift right I1 8 times; shift in bit = I0.3

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Shift right I1 once; shift in bit = I0.3 Q1 := Shift right I1 twice; shift in bit = I0.3 Q1 := Shift right I1 3 times; shift in bit = I0.3 Q1 := Shift right I1 4 times; shift in bit = I0.3 Q1 := Shift right I1 5 times; shift in bit = I0.3 Q1 := Shift right I1 6 times; shift in bit = I0.3

1

1

1

M0.7

Q1 := Shift right I1 7 times; shift in bit = I0.3

I0.2

the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected shift right process. Note that, at any time, only one of the outputs of the “3 to 8 decoder” (i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active. In rung 2, when the rising edge of M0.0 is detected, the shift right operation “Q1 := Shift right I1 8 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.0 is detected by using an “r_edge” macro together with the memory bit M1.0. In rung 3, when the rising edge of M0.1 is detected, the shift right operation “Q1 := Shift right I1 once” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the shift right operation “Q1 := Shift right I1 twice” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2. In rung 5, when the rising edge of M0.3 is detected, the shift right operation “Q1 := Shift right I1 3 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3. In rung 6, when the rising edge of M0.4 is detected, the shift right operation “Q1 := Shift right I1 4 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the shift right operation “Q1 := Shift right I1 5 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5. In rung 8, when the rising edge of M0.6 is detected, the shift right operation “Q1 := Shift right I1 6 times” is carried out. The “shift in bit” for this shift

165

Shift and Rotate Macros

right operation is I0.3. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the shift right operation “Q1 := Shift right I1 7 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7. In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation we obtain the following: Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.23 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected

TABLE 3.23 The Truth Table 2 of the User Program of “Example 3.4” Memory Bit

I0.7

I0.6

I0.5

I0.4

Selected Process

0

0

0

0

M2.0

Q3,Q2 := Shift right I3,I2 16 times; shift in bit = I0.3

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Shift right I3,I2 once; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 twice; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 3 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 4 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 5 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 6 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 7 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 8 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 9 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 10 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 11 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 12 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 13 times; shift in bit = I0.3 Q3,Q2 := Shift right I3,I2 14 times; shift in bit = I0.3

1

1

1

1

M3.7

Q3,Q2 := Shift right I3,I2 15 times; shift in bit = I0.3

166

Programmable Logic Controller

shift right process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active. In rung 12, when the rising edge of M2.0 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 16 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.0 is detected by using an “r_edge” macro together with the memory bit M4.0. In rung 13, when the rising edge of M2.1 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 once” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. In rung 14, when the rising edge of M2.2 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 twice” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2. In rung 15, when the rising edge of M2.3 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 3 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3. In rung 16, when the rising edge of M2.4 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 4 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. In rung 17, when the rising edge of M2.5 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 5 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. In rung 18, when the rising edge of M2.6 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 6 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6. In rung 19, when the rising edge of M2.7 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 7 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. In rung 20, when the rising edge of M3.0 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 8 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0. In rung 21, when the rising edge of M3.1 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 9 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. In rung 22, when the rising edge of M3.2 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 10 times” is carried out. The “shift in bit” for

Shift and Rotate Macros

167

this shift right operation is I0.3. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2. In rung 23, when the rising edge of M3.3 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 11 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. In rung 24, when the rising edge of M3.4 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 12 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4. In rung 25, when the rising edge of M3.5 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 13 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. In rung 26, when the rising edge of M3.6 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 14 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. In rung 27, when the rising edge of M3.7 is detected, the shift right operation “Q3,Q2 := Shift right I3,I2 15 times” is carried out. The “shift in bit” for this shift right operation is I0.3. The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

3.16.5

EXAMPLE 3.5

Example 3.5 shows the usage of the shift left macros “shift_L” and “shift_L_16” and the macro “Swap”. The user program of Example 3.5 is shown in Figure 3.54. The ladder diagram of Example 3.5 is depicted in Figure 3.55. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 3.5 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.24 shows the truth table based on the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected shift left process. Note that, at any time, only one of the outputs of the “3 to 8 decoder” (i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active.

168

FIGURE 3.54 The user program of “Example 3.5”.

Programmable Logic Controller

Shift and Rotate Macros

FIGURE 3.54 Continued

169

170

Programmable Logic Controller

FIGURE 3.54 Continued

In rung 2, when the rising edge of M0.0 is detected, the shift left operation “Q1 := Shift left I1 8 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.0 is detected by using an “r_edge” macro together with the memory bit M1.0. In rung 3, when the rising edge of M0.1 is detected, the shift left operation “Q1 := Shift left I1 once” is carried out. The “shift in bit” for this shift left

Shift and Rotate Macros

FIGURE 3.55 The ladder diagram of the user program of “Example 3.5”.

171

172

FIGURE 3.55 Continued

Programmable Logic Controller

Shift and Rotate Macros

173

FIGURE 3.55 Continued

operation is I0.3. The rising edge of M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the shift left operation “Q1 := Shift left I1 twice” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2.

174

Programmable Logic Controller

TABLE 3.24 The Truth Table 1 of the User Program of “Example 3.5” I0.1

I0.0

Memory Bit

Selected Process

0

0

0

M0.0

Q1 := Shift left I1 8 times; shift in bit = I0.3

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Shift left I1 once; shift in bit = I0.3 Q1 := Shift left I1 twice; shift in bit = I0.3 Q1 := Shift left I1 3 times; shift in bit = I0.3 Q1 := Shift left I1 4 times; shift in bit = I0.3 Q1 := Shift left I1 5 times; shift in bit = I0.3 Q1 := Shift left I1 6 times; shift in bit = I0.3

1

1

1

M0.7

Q1 := Shift left I1 7 times; shift in bit = I0.3

I0.2

In rung 5, when the rising edge of M0.3 is detected, the shift left operation “Q1 := Shift left I1 3 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3. In rung 6, when the rising edge of M0.4 is detected, the shift left operation “Q1 := Shift left I1 4 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the shift left operation “Q1 := Shift left I1 5 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5. In rung 8, when the rising edge of M0.6 is detected, the shift left operation “Q1 := Shift left I1 6 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the shift left operation “Q1 := Shift left I1 7 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7. In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation we obtain the following: Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6, d13

175

Shift and Rotate Macros

TABLE 3.25 The Truth Table 2 of the User Program of “Example 3.5” I0.6

I0.5

I0.4

Memory Bit

Selected Process

0

0

0

0

M2.0

Q3,Q2 := Shift left I3,I2 16 times; shift in bit = I0.3

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Shift left I3,I2 once; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 twice; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 3 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 4 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 5 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 6 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 7 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 8 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 9 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 10 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 11 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 12 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 13 times; shift in bit = I0.3 Q3,Q2 := Shift left I3,I2 14 times; shift in bit = I0.3

1

1

1

1

M3.7

Q3,Q2 := Shift left I3,I2 15 times; shift in bit = I0.3

I0.7

= M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.25 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected shift left process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active. In rung 12, when the rising edge of M2.0 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 16 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.0 is detected by using an “r_edge” macro together with the memory bit M4.0. In rung 13, when the rising edge of M2.1 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 once” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. In rung 14, when the rising edge of M2.2 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 twice” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2.

176

Programmable Logic Controller

In rung 15, when the rising edge of M2.3 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 3 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3. In rung 16, when the rising edge of M2.4 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 4 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. In rung 17, when the rising edge of M2.5 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 5 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. In rung 18, when the rising edge of M2.6 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 6 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6. In rung 19, when the rising edge of M2.7 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 7 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. In rung 20, when the rising edge of M3.0 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 8 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0. In rung 21, when the rising edge of M3.1 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 9 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. In rung 22, when the rising edge of M3.2 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 10 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2. In rung 23, when the rising edge of M3.3 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 11 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. In rung 24, when the rising edge of M3.4 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 12 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4. In rung 25, when the rising edge of M3.5 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 13 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. In rung 26, when the rising edge of M3.6 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 14 times” is carried out. The “shift in bit” for this

Shift and Rotate Macros

177

shift left operation is I0.3. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. In rung 27, when the rising edge of M3.7 is detected, the shift left operation “Q3,Q2 := Shift left I3,I2 15 times” is carried out. The “shift in bit” for this shift left operation is I0.3. The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

3.16.6

EXAMPLE 3.6

Example 3.6 shows the usage of the rotate right macros “rotate_R”, “rotate_R_16” and the macro “Swap”. The user program of Example 3.6 is shown in Figure 3.56. The ladder diagram of Example 3.6 is depicted in Figure 3.57. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 3.6 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.26 shows the truth table based on the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected Swap or rotate right process. Note that, at any time, only one of the outputs of the “3 to 8 decoder” (i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active. In rung 2, when M0.0 = 1, the swap operation “Q1 := Swap (I1)” is carried out. In rung 3, when the rising edge of M0.1 is detected, the rotate right operation “Q1 := Rotate right I1 once” is carried out. The rising edge of M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the rotate right operation “Q1 := Rotate right I1 twice” is carried out. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2. In rung 5, when the rising edge of M0.3 is detected, the rotate right operation “Q1 := Rotate right I1 3 times” is carried out. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3. In rung 6, when the rising edge of M0.4 is detected, the rotate right operation “Q1 := Rotate right I1 4 times” is carried out. The rising edge of M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the rotate right operation “Q1 := Rotate right I1 5 times” is carried out. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5.

178

FIGURE 3.56

Programmable Logic Controller

The user program of “Example 3.6”.

Shift and Rotate Macros

FIGURE 3.56

179

Continued

In rung 8, when the rising edge of M0.6 is detected, the rotate right operation “Q1 := Rotate right I1 6 times” is carried out. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the rotate right operation “Q1 := Rotate right I1 7 times” is carried out. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7.

180

Programmable Logic Controller

FIGURE 3.56

Continued

In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation we obtain the following: Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

Shift and Rotate Macros

FIGURE 3.57

The ladder diagram of the user program of “Example 3.6”.

181

182

FIGURE 3.57

Programmable Logic Controller

Continued

Shift and Rotate Macros

FIGURE 3.57

183

Continued

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different

184

Programmable Logic Controller

TABLE 3.26 The Truth Table 1 of the User Program of “Example 3.6” I0.1

I0.0

Memory Bit

0

0

0

M0.0

Q1 := Swap I1

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Rotate right I1 once Q1 := Rotate right I1 twice Q1 := Rotate right I1 3 times Q1 := Rotate right I1 4 times Q1 := Rotate right I1 5 times Q1 := Rotate right I1 6 times

1

1

1

M0.7

Q1 := Rotate right I1 7 times

I0.2

Selected Process

memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.27 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected rotate right process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active. In rung 12, when the rising edge of M2.1 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 once” is carried out. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. In rung 13, when the rising edge of M2.2 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 twice” is carried out. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2. In rung 14, when the rising edge of M2.3 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 3 times” is carried out. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3. In rung 15, when the rising edge of M2.4 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 4 times” is carried out. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. In rung 16, when the rising edge of M2.5 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 5 times” is carried out. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. In rung 17, when the rising edge of M2.6 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 6 times” is carried out. The rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6.

185

Shift and Rotate Macros

TABLE 3.27 The Truth Table 2 of the User Program of “Example 3.6” I0.6

I0.5

I0.4

Memory Bit

0

0

0

0

M2.0

No process is selected

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Rotate right I3,I2 once Q3,Q2 := Rotate right I3,I2 twice Q3,Q2 := Rotate right I3,I2 3 times Q3,Q2 := Rotate right I3,I2 4 times Q3,Q2 := Rotate right I3,I2 5 times Q3,Q2 := Rotate right I3,I2 6 times Q3,Q2 := Rotate right I3,I2 7 times Q3,Q2 := Rotate right I3,I2 8 times Q3,Q2 := Rotate right I3,I2 9 times Q3,Q2 := Rotate right I3,I2 10 times Q3,Q2 := Rotate right I3,I2 11 times Q3,Q2 := Rotate right I3,I2 12 times Q3,Q2 := Rotate right I3,I2 13 times Q3,Q2 := Rotate right I3,I2 14 times

1

1

1

1

M3.7

Q3,Q2 := Rotate right I3,I2 15 times

I0.7

Selected Process

In rung 18, when the rising edge of M2.7 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 7 times” is carried out. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. In rung 19, when the rising edge of M3.0 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 8 times” is carried out. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0. In rung 20, when the rising edge of M3.1 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 9 times” is carried out. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. In rung 21, when the rising edge of M3.2 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 10 times” is carried out. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2. In rung 22, when the rising edge of M3.3 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 11 times” is carried out. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. In rung 23, when the rising edge of M3.4 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 12 times” is carried out. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4.

186

Programmable Logic Controller

In rung 24, when the rising edge of M3.5 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 13 times” is carried out. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. In rung 25, when the rising edge of M3.6 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 14 times” is carried out. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. In rung 26, when the rising edge of M3.7 is detected, the rotate right operation “Q3,Q2 := Rotate right I3,I2 15 times” is carried out. The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

3.16.7

EXAMPLE 3.7

Example 3.7 shows the usage of the rotate left macros “rotate_L” and “rotate_L_16” and the macro “Swap”. The user program of Example 3.7 is shown in Figure 3.58. The ladder diagram of Example 3.7 is depicted in Figure 3.59. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 3.7 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, a “3 to 8 decoder” is implemented: select inputs s2,s1,s0 = I0.2, I0.1, and I0.0, and decoder outputs are d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0. This arrangement is made to choose 8 different memory bits based on the input data given through the select inputs I0.2, I0.1, and I0.0. Table 3.28 shows the truth table based on the input data entered through I0.2, I0.1, and I0.0, the chosen 8 memory bits, and the selected Swap or rotate left process. Note that, at any time, only one of the outputs of the “3 to 8 decoder” (i.e., d7 = M0.7, d6 = M0.6, d5 = M0.5, d4 = M0.4, d3 = M0.3, d2 = M0.2, d1 = M0.1, d0 = M0.0) will be active. In rung 2, when M0.0 = 1, the swap operation “Q1 := Swap (I1)” is carried out. In rung 3, when the rising edge of M0.1 is detected, the rotate left operation “Q1 := Rotate left I1 once” is carried out. The rising edge of M0.1 is detected by using an “r_edge” macro together with the memory bit M1.1. In rung 4, when the rising edge of M0.2 is detected, the rotate left operation “Q1 := Rotate left I1 twice” is carried out. The rising edge of M0.2 is detected by using an “r_edge” macro together with the memory bit M1.2. In rung 5, when the rising edge of M0.3 is detected, the rotate left operation “Q1 := Rotate left I1 3 times” is carried out. The rising edge of M0.3 is detected by using an “r_edge” macro together with the memory bit M1.3.

Shift and Rotate Macros

FIGURE 3.58

The user program of “Example 3.7”.

187

188

FIGURE 3.58

Programmable Logic Controller

Continued

In rung 6, when the rising edge of M0.4 is detected, the rotate left operation “Q1 := Rotate left I1 4 times” is carried out. The rising edge of M0.4 is detected by using an “r_edge” macro together with the memory bit M1.4. In rung 7, when the rising edge of M0.5 is detected, the rotate left operation “Q1 := Rotate left I1 5 times” is carried out. The rising edge of M0.5 is detected by using an “r_edge” macro together with the memory bit M1.5.

Shift and Rotate Macros

FIGURE 3.58

189

Continued

In rung 8, when the rising edge of M0.6 is detected, the rotate left operation “Q1 := Rotate left I1 6 times” is carried out. The rising edge of M0.6 is detected by using an “r_edge” macro together with the memory bit M1.6. In rung 9, when the rising edge of M0.7 is detected, the rotate left operation “Q1 := Rotate left I1 7 times” is carried out. The rising edge of M0.7 is detected by using an “r_edge” macro together with the memory bit M1.7.

190

FIGURE 3.59

Programmable Logic Controller

The ladder diagram of the user program of “Example 3.7”.

Shift and Rotate Macros

FIGURE 3.59

Continued

191

192

FIGURE 3.59

Programmable Logic Controller

Continued

193

Shift and Rotate Macros

In rung 10, as EN = LOGIC1, the swap operation “M99 := Swap (I0)” is always carried out. After this operation we obtain the following: Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

I0

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Bit 0

M99

I0.3

I0.2

I0.1

I0.0

I0.7

I0.6

I0.5

I0.4

In rung 11, a “4 to 16 decoder” is implemented: select inputs s3,s2,s1,s0 = I0.7, I0.6, I0.5, and I0.4, and decoder outputs are d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0. This arrangement is made to choose 16 different memory bits based on the input data given through the select inputs I0.7, I0.6, I0.5, and I0.4. Table 3.29 shows the truth table based on the input data entered through I0.7, I0.6, I0.5, and I0.4, the chosen 16 memory bits, and the selected rotate left process. Note that, at any time, only one of the outputs of the “4 to 16 decoder” (i.e., d15 = M3.7, d14 = M3.6, d13 = M3.5, d12 = M3.4, d11 = M3.3, d10 = M3.2, d9 = M3.1, d8 = M3.0, d7 = M2.7, d6 = M2.6, d5 = M2.5, d4 = M2.4, d3 = M2.3, d2 = M2.2, d1 = M2.1, d0 = M2.0) will be active. In rung 12, when the rising edge of M2.1 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 once” is carried out. The rising edge of M2.1 is detected by using an “r_edge” macro together with the memory bit M4.1. In rung 13, when the rising edge of M2.2 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 twice” is carried out. The rising edge of M2.2 is detected by using an “r_edge” macro together with the memory bit M4.2. In rung 14, when the rising edge of M2.3 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 3 times” is carried out. The rising edge of M2.3 is detected by using an “r_edge” macro together with the memory bit M4.3. In rung 15, when the rising edge of M2.4 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 4 times” is carried out. The rising edge of M2.4 is detected by using an “r_edge” macro together with the memory bit M4.4. In rung 16, when the rising edge of M2.5 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 5 times” is carried out. The rising edge of M2.5 is detected by using an “r_edge” macro together with the memory bit M4.5. In rung 17, when the rising edge of M2.6 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 6 times” is carried out. The rising edge of M2.6 is detected by using an “r_edge” macro together with the memory bit M4.6. In rung 18, when the rising edge of M2.7 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 7 times” is carried out. The rising edge of M2.7 is detected by using an “r_edge” macro together with the memory bit M4.7. In rung 19, when the rising edge of M3.0 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 8 times” is carried out. The rising edge of M3.0 is detected by using an “r_edge” macro together with the memory bit M5.0.

194

Programmable Logic Controller

TABLE 3.28 The Truth Table 1 of the User Program of “Example 3.7” I0.1

I0.0

Memory Bit

0

0

0

M0.0

Q1 := Swap I1

0 0 0 1 1 1

0 1 1 0 0 1

1 0 1 0 1 0

M0.1 M0.2 M0.3 M0.4 M0.5 M0.6

Q1 := Rotate left I1 once Q1 := Rotate left I1 twice Q1 := Rotate left I1 3 times Q1 := Rotate left I1 4 times Q1 := Rotate left I1 5 times Q1 := Rotate left I1 6 times

1

1

1

M0.7

Q1 := Rotate left I1 7 times

I0.2

Selected Process

TABLE 3.29 The Truth Table 2 of the User Program of “Example 3.7” I0.6

I0.5

I0.4

Memory Bit

0

0

0

0

M2.0

No process is selected

0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 0 0 1 1 1 1 0 0 0 0 1 1 1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

M2.1 M2.2 M2.3 M2.4 M2.5 M2.6 M2.7 M3.0 M3.1 M3.2 M3.3 M3.4 M3.5 M3.6

Q3,Q2 := Rotate left I3,I2 once Q3,Q2 := Rotate left I3,I2 twice Q3,Q2 := Rotate left I3,I2 3 times Q3,Q2 := Rotate left I3,I2 4 times Q3,Q2 := Rotate left I3,I2 5 times Q3,Q2 := Rotate left I3,I2 6 times Q3,Q2 := Rotate left I3,I2 7 times Q3,Q2 := Rotate left I3,I2 8 times Q3,Q2 := Rotate left I3,I2 9 times Q3,Q2 := Rotate left I3,I2 10 times Q3,Q2 := Rotate left I3,I2 11 times Q3,Q2 := Rotate left I3,I2 12 times Q3,Q2 := Rotate left I3,I2 13 times Q3,Q2 := Rotate left I3,I2 14 times

1

1

1

1

M3.7

Q3,Q2 := Rotate left I3,I2 15 times

I0.7

Selected Process

In rung 20, when the rising edge of M3.1 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 9 times” is carried out. The rising edge of M3.1 is detected by using an “r_edge” macro together with the memory bit M5.1. In rung 21, when the rising edge of M3.2 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 10 times” is carried out. The rising edge of M3.2 is detected by using an “r_edge” macro together with the memory bit M5.2.

Shift and Rotate Macros

195

In rung 22, when the rising edge of M3.3 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 11 times” is carried out. The rising edge of M3.3 is detected by using an “r_edge” macro together with the memory bit M5.3. In rung 23, when the rising edge of M3.4 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 12 times” is carried out. The rising edge of M3.4 is detected by using an “r_edge” macro together with the memory bit M5.4. In rung 24, when the rising edge of M3.5 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 13 times” is carried out. The rising edge of M3.5 is detected by using an “r_edge” macro together with the memory bit M5.5. In rung 25, when the rising edge of M3.6 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 14 times” is carried out. The rising edge of M3.6 is detected by using an “r_edge” macro together with the memory bit M5.6. In rung 26, when the rising edge of M3.7 is detected, the rotate left operation “Q3,Q2 := Rotate left I3,I2 15 times” is carried out. The rising edge of M3.7 is detected by using an “r_edge” macro together with the memory bit M5.7.

4

Selection Macros

INTRODUCTION Selection macros (functions) are provided to enable one value to be selected from a number of given values according to certain criteria. In this chapter, the following selection macros are described for the PIC16F1847-Based PLC: move_R (Move), load_R (Load), select (Selection of One of Two 8-Bit Input Variables), select_16 (Selection of One of Two 16-Bit Input Variables), max_5 (Maximum in Five 8-Bit Variables), max_10 (Maximum in Ten 8-Bit Variables), max_N80 (Maximum in N 8-Bit Variables, N = 2, 3, …, 80), max_N40_16 (Maximum in N 16-Bit Variables, N = 2, 3, …, 40), max_N255 (Maximum in N 8-Bit Variables, N = 2, 3, …, 255), max_N255_16 (Maximum in N 16-Bit Variables, N = 2, 3, …, 255), min_5 (Minimum in Five 8-Bit Variables), min_10 (Minimum in Ten 8-Bit Variables), min_N80 (Minimum in N 8-Bit Variables, N = 2, 3, …, 80), min_N40_16 (Minimum in N 16-Bit Variables, N = 2, 3, …, 40), min_N255 (Minimum in N 8-Bit Variables, N = 2, 3, …, 255), min_N255_16 (Minimum in N 16-Bit Variables, N = 2, 3, …, 255), limiter, limiter_16, mux_2_1 (2×1 MUX), mux_2_1_E (2×1 MUX with Enable Input), mux_4_1 (4×1 MUX), mux_4_1_E (4×1 MUX with Enable Input), mux_8_1 (8×1 MUX), mux_8_1_E (8×1 MUX with Enable Input), mux_16_1 (16×1 MUX), mux_16_1_E (16×1 MUX with Enable Input), B_mux_2_1_E (2×1 Byte Multiplexer with Enable Input), B_mux_4_1_E (4×1 Byte Multiplexer with Enable Input), B_mux_8_1_E (8×1 Byte Multiplexer with Enable Input). The fle “PICPLC_PIC16F1847_macros_Int.inc”, which is downloadable from this book’s webpage under the downloads section, contains macros defned for the PIC16F1847-Based PLC explained in this volume (Intermediate Concepts). Let us now consider the selection macros in detail. 197

198

4.1

Programmable Logic Controller

MACRO “MOVE_R” (MOVE)

In a PLC, numbers are often required to be moved from one location to another; a timer preset value may be required to be changed according to plant conditions, or the result of some calculations may be used in another part of a program. To satisfy this need for 8-bit variables, in the PIC16F1847-Based PLC we defne the macro “move_R”. Similarly, the macro “load_R” is also described to load an 8-bit number into an 8-bit variable. The symbol and the algorithm of the macro “move_R” are depicted in Table 4.1. Figure 4.1 shows the macro “move_R” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-outputvariable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. This is especially useful if we want to carry out more than one operation based on a single input condition. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the macro “move_R” transfers the data from the 8-bit input variable IN to the 8-bit output variable OUT. Assumption: The operands “IN” and “OUT” can be in any Bank.

4.2 MACRO “LOAD_R” (LOAD) The symbol and the algorithm of the macro “load_R” are depicted in Table 4.2. Figure 4.2 shows the macro “load_R” and its fowchart. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Booleanoutput-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, the TABLE 4.1 Symbol and Algorithm of the Macro “move_R” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit input variable, IN) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, OUT) Algorithm if then

EN = 1; OUT := IN; ENO := 1;

else ENO := 0; endif;

199

Selection Macros

FIGURE 4.1 The macro “move_R” and its fowchart.

TABLE 4.2 Symbol and Algorithm of the Macro “load_R” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit constant value, IN) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, OUT) Algorithm If then

EN = 1; OUT := IN; ENO := 1;

else ENO := 0; endif;

200

Programmable Logic Controller

FIGURE 4.2

The macro “load_R” and its fowchart.

TABLE 4.3 Symbol and Algorithm of the Macro “select” Symbol EN (Boolean-enable-input, through W) = 0 or 1 G (Boolean-select-input, Greg,Gbit) = 0 or 1 IN0 (8-bit input variable, IN0) IN1 (8-bit input variable, IN1) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, OUT) Algorithm if then

EN = 1; OUT := IN0 if G = 0; OUT := IN1 if G = 1; ENO := 1;

else ENO := 0; endif;

Selection Macros

201

macro “load_R” transfers the 8-bit constant data IN into the 8-bit output variable OUT. Assumption: The operand “OUT” can be in any Bank.

4.3 MACRO “SELECT” (SELECTION OF ONE OF TWO 8-BIT INPUT VARIABLES) The symbol and the algorithm of the macro “select” are depicted in Table 4.3. Figures 4.3 and 4.4 show the macro “select” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a Boolean-select-input G (Greg,Gbit), two 8-bit input variables, IN0 and IN1, and an 8-bit output variable OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, if G = 0, then OUT is equal to IN0. If G = 1, then OUT is equal to IN1. Assumption: The operands “Greg,Gbit”, “IN0”, “IN1”, and “OUT” can be in any Bank.

4.4

MACRO “SELECT_16” (SELECTION OF ONE OF TWO 16-BIT INPUT VARIABLES)

The symbol and the algorithm of the macro “select_16” are depicted in Table 4.4. Figures 4.5 and 4.6 show the macro “select_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and

FIGURE 4.3

The macro “select”.

202

Programmable Logic Controller

FIGURE 4.4 The fowchart of the macro “select”.

ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a Boolean-selectinput G (Greg,Gbit), two 16-bit input variables, IN0 and IN1, and a 16-bit output variable OUT. IN0 consists of two 8-bit variables, IN0H and IN0L. IN0H holds the high byte of IN0, and IN0L holds the low byte of IN0. IN1 consists of two 8-bit variables, IN1H and IN1L. IN1H holds the high byte of IN1, and IN1L holds the low byte of IN1. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Boolean-enableinput signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, if G = 0, then OUT is equal to IN0. If G = 1, then OUT is equal to IN1. Assumption: The operands “Greg,Gbit”, “IN0H”, “IN0L”, “IN1H”, “IN1L”, “OUTH”, and “OUTL” can be in any Bank.

203

Selection Macros

TABLE 4.4 Symbol and Algorithm of the Macro “select_16” Symbol EN (Boolean-enable-input, through W) = 0 or 1 G (Boolean-select-input, Greg,Gbit) = 0 or 1 IN0H (High byte of a 16-bit input variable IN0, IN0H) IN0L (Low byte of a 16-bit input variable IN0, IN0L) IN1H (High byte of a 16-bit input variable IN1, IN1H) IN1L (Low byte of a 16-bit input variable IN1, IN1L) ENO (Boolean-enable-output, through W) = 0 or 1 OUTH (High byte of a 16-bit output variable OUT, OUTH) OUTL (Low byte of a 16-bit output variable OUT, OUTL) Algorithm if then

EN = 1; OUT := IN0 if G = 0; OUT := IN1 if G = 1; ENO := 1;

else ENO := 0; endif;

4.5 MACRO “MAX _5” (MAXIMUM IN FIVE 8-BIT VARIABLES) The symbol and the algorithm of the macro “max_5” are depicted in Table 4.5. Figures 4.7 and 4.8 show the macro “max_5” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has fve 8-bit input variables, IN1, IN2, IN3, IN4, and IN5, and an 8-bit output variable OUT. OUT represents the maximum value stored in fve input variables, IN1, IN2, …, IN5. The Booleanenable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the maximum value in fve 8-bit input variables, IN1, IN2, …, IN5, is identifed. Then, the contents of the input variable holding the maximum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1”, “IN2”, “IN3”, “IN4”, “IN5”, and “OUT” can be in any Bank. In the macro “max5” and in some forthcoming macros, the command “#v(expr)” is utilized. Now, let us consider the meaning of it. The command “#v(expr)” returns the integer value of expr. Typically, it is used to provide unique variable names with common prefxes or suffxes. It cannot be used in conditional assembly directives (e.g., ifdef, while). Let us imagine how the assembler interprets a macro with the command “#v(expr)”. When it encounters “#v(expr)”, this text is replaced with a

204

FIGURE 4.5

Programmable Logic Controller

The macro “select_16”.

number calculated by evaluating the expression. For example, the “label#v(2+1)” becomes “label3”. Now let us consider the related part of the “max5” macro as follows: ;--------------------;--------------i=2 ;i=2 (start from the second value) while i < 6 ;take the next value from the list banksel IN#v(i) ;banksel IN#v(i) movfw IN#v(i) ;W = IN#v(i) movwf Temp_2 ;Temp_2 = W. The next value in the list. subwf Temp_1,W ;if Temp_2 > Temp_1, btfsc STATUS,C ;then skip, goto L#v(6-i) ;else goto L#v(6-i).

Selection Macros

FIGURE 4.6 movfw movwf

205

The fowchart of the macro “select_16”. Temp_2 Temp_1

;W = Temp_2. ;Temp_1 = Temp_2. Update the current max value L#v(6-i) ;label L#v(6-i) i += 1 ;increment i endw ;repeat this process 4 times ;--------------------;---------------

When the “max5” macro is invoked, this part of the macro would generate the following code: ;--------------------;--------------i=2 ; ;--------------------;--------------; while (i < 6) while 2 < 6 banksel IN2 ; IN#v(i) = IN#v(2) = IN2 movfw IN2 ; IN#v(i) = IN#v(2) = IN2 movwf Temp_2 ; subwf Temp_1,W ;

206

Programmable Logic Controller

TABLE 4.5 Symbol and Algorithm of the Macro “max_5” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) IN2 (8-bit input variable, IN2) IN3 (8-bit input variable, IN3) IN4 (8-bit input variable, IN4) IN5 (8-bit input variable, IN5) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the maximum value stored in fve input variables IN1, IN2, …, IN5, OUT) Algorithm if then

EN = 1; OUT := MAX (IN1, IN2, IN3, IN4, IN5); ENO := 1;

else ENO := 0; endif;

btfsc goto movfw movwf

STATUS,C L4 Temp_2 Temp_1

; ; L#v(6-i) = L#v(6-2) ; ; L4 ; L#v(6-i) = L#v(6-2) i = i + 1 = 2 + 1 = 3; ;--------------------;--------------; while (i < 6) while 3 < 6 banksel IN3 ; IN#v(i) = IN#v(3) = movfw IN3 ; IN#v(i) = IN#v(3) = movwf Temp_2 ; subwf Temp_1,W ; btfsc STATUS,C ; goto L3 ; L#v(6-i) = L#v(6-3) movfw Temp_2 ; movwf Temp_1 ; L3 ; L#v(6-i) = L#v(6-3) i = i + 1 = 3 + 1 = 4; ;--------------------;--------------; while (i < 6) while 4 < 6 banksel IN4 ; IN#v(i) = IN#v(4) = movfw IN4 ; IN#v(i) = IN#v(4) = movwf Temp_2 ; subwf Temp_1,W ; btfsc STATUS,C ; goto L2 ; L#v(6-i) = L#v(6-4)

= L4 = L4

IN3 IN3

= L3 = L3

IN4 IN4

= L2

207

Selection Macros

FIGURE 4.7 movfw movwf

The macro “max_5”. Temp_2 Temp_1

; ; L2 ; L#v(6-i) = L#v(6-4) i = i + 1 = 4 + 1 = 5 ; ;--------------------;-------------- while 5 < 6 ; while (i < 6) banksel IN5 ; IN#v(i) = IN#v(5) = movfw IN5 ; IN#v(i) = IN#v(5) = movwf Temp_2 ; subwf Temp_1,W ; btfsc STATUS,C ; goto L1 ; L#v(6-i) = L#v(6-5) movfw Temp_2 ; movwf Temp_1 ; L1 ; L#v(6-i) = L#v(6-5) i = i + 1 = 5 + 1 = 6 ; ;--------------------;-------------- endw ;

= L2

IN5 IN5

= L1 = L1

208

Programmable Logic Controller

FIGURE 4.8 The fowchart of the macro “max_5”. ;--------------------;---------------

4.6

MACRO “MAX_10” (MAXIMUM IN TEN 8-BIT VARIABLES)

The symbol and the algorithm of the macro “max_10” are depicted in Table 4.6. Figures 4.9 and 4.10 show the macro “max_10” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has ten 8-bit input variables, IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, and IN10, and an 8-bit output variable OUT. OUT represents the maximum value stored in ten input variables, IN1, IN2, …, IN10. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the maximum value in ten 8-bit input variables, IN1, IN2, …, IN10, is identifed. Then, the contents of the input variable holding the maximum value are copied to the 8-bit

209

Selection Macros

TABLE 4.6 Symbol and Algorithm of the Macro “max_10” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) IN2 (8-bit input variable, IN2) IN3 (8-bit input variable, IN3) IN4 (8-bit input variable, IN4) IN5 (8-bit input variable, IN5) IN6 (8-bit input variable, IN6) IN7 (8-bit input variable, IN7) IN8 (8-bit input variable, IN8) IN9 (8-bit input variable, IN9) IN10 (8-bit input variable, IN10) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the maximum value stored in ten input variables IN1, IN2, …, IN10, OUT) Algorithm if then

EN = 1; OUT := MAX (IN1, IN2, IN3, …, IN10); ENO := 1;

else ENO := 0; endif;

output variable OUT. Assumption: The operands “IN1”, “IN2”, “IN3”, “IN4”, “IN5”, “IN6”, “IN7”, “IN8”, “IN9”, “IN10”, and “OUT” can be in any Bank.

4.7

MACRO “MAX_N80” (MAXIMUM IN N 8-BIT VARIABLES, N = 2, 3, …, 80)

The symbol and the algorithm of the macro “max_N80” are depicted in Table 4.7. Figures 4.11 and 4.12 show the macro “max_N80” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1, and an 8-bit output variable OUT. N represents the number of successive 8-bit variables located in the GPR area of the same Bank, which can be any number in 2, 3, …, 80. OUT represents the maximum value stored in N input variables, starting from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the maximum value in N 8-bit input variables, IN1, IN2, …,

210

Programmable Logic Controller

FIGURE 4.9 The macro “max_10”.

INN, is identifed. Then, the contents of the input variable holding the maximum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1” and “OUT” can be in any Bank. In this macro, the traditional data memory map is used.

4.8

MACRO “MAX_N40_16” (MAXIMUM IN N 16-BIT VARIABLES, N = 2, 3, …, 40)

The symbol and the algorithm of the macro “max_N40_16” are depicted in Table 4.8. Figures 4.13 and 4.14 show the macro “max_N40_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1L, and two 8-bit output variables, OUTH and OUTL. N represents the number of successive 16-bit variables located in the GPR area of the same Bank, which can be any number in 2, 3, …, 40. It is assumed that N successive

211

Selection Macros

FIGURE 4.10 The fowchart of the macro “max_10”.

TABLE 4.7 Symbol and Algorithm of the Macro “max_N80” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) N (The number of successive 8-bit variables located in the GPR area of the same Bank, N) = 2, 3, …, 80 ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the maximum value stored in N input variables starting from IN1, OUT) Algorithm if then

EN = 1; OUT := MAX (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif;

212

FIGURE 4.11

Programmable Logic Controller

The macro “max_N80”.

16-bit variables (words) are located in the GPR area of the same Bank in little endian format. IN1L represents the low byte of the frst 16-bit input variable, IN1. OUTH represents the high byte of the maximum value stored in N 16-bit input variables, starting from IN1. OUTL represents the low byte of the maximum value stored in N 16-bit input variables, starting from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the maximum value in N 16-bit input variables, IN1,

Selection Macros

213

FIGURE 4.12 The fowchart of the macro “max_N80”.

IN2, …, INN, is identifed. Then, the contents of the input variable holding the maximum value are copied to the 16-bit output variable OUT. Assumption: The operands “IN1L”, “OUTH”, and “OUTL” can be in any Bank. In this macro, the traditional data memory map is used.

4.9 MACRO “MAX_N255” (MAXIMUM IN N 8-BIT VARIABLES, N = 2, 3, …, 255) The symbol and the algorithm of the macro “max_N255” are depicted in Table 4.9. Figures 4.15 and 4.16 show the macro “max_N255” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1, and an 8-bit output variable OUT. N represents the number of successive 8-bit variables located in the GPR memories of the successive Banks, which can be any number in 2, 3, …, 255. IN1 represents the frst 8-bit input variable. OUT represents the maximum value stored in N input variables, starting

214

Programmable Logic Controller

TABLE 4.8 Symbol and Algorithm of the Macro “max_N40_16” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1L (8-bit input variable, showing the Low byte of the 16-bit input variable IN1) N (The number of successive 16-bit variables located in the GPR area of the same Bank, N) = 2, 3, …, 40 ENO (Boolean-enable-output, through W) = 0 or 1 OUTH (8-bit output variable, showing the High byte of the maximum value stored in N 16-bit input variables starting from IN1, OUTH) OUTL (8-bit output variable, showing the Low byte of the maximum value stored in N 16-bit input variables starting from IN1, OUTL) Algorithm if then

EN = 1; OUT := MAX (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif; IN1 = IN1H & IN1L, IN2 = IN2H & IN2L, …, INN = INNH & INNL

from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the maximum value in N 8-bit input variables, IN1, IN2, …, INN, is identifed. Then, the contents of the input variable holding the maximum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1” and “OUT” can be in any Bank. In this macro, the linear data memory map is used. The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the Banks. Use of the linear data memory region allows buffers to be larger than 80 bytes, because incrementing the FSR beyond one Bank will go directly to the GPR memory of the next Bank. The 16 bytes of common memory are not included in the linear data memory region.

4.10

MACRO “MAX_N255_16” (MAXIMUM IN N 16-BIT VARIABLES, N = 2, 3, …, 255)

The symbol and the algorithm of the macro “max_N255_16” are depicted in Table 4.10. Figures 4.17 and 4.18 show the macro “max_N255_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and,

Selection Macros

215

FIGURE 4.13 The macro “max_N40_16”.

when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1L, and two 8-bit output variables, OUTH and OUTL. N represents the number of successive 16-bit variables located in the GPR memories of the successive Banks, which can be any number in 2, 3, …, 255. It is assumed that N successive 16-bit variables (words) are located in the GPR memories of the successive Banks in little endian format. IN1L represents the low byte of the frst 16-bit input variable IN1. OUTH represents the high byte of the maximum value stored in N 16-bit

216

Programmable Logic Controller

FIGURE 4.13 Continued

input variables, starting from IN1. OUTL represents the low byte of the maximum value stored in N 16-bit input variables, starting from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the maximum value in N 16-bit input variables, IN1, IN2, …, INN, is identifed. Then, the contents of the input variable holding the maximum value are copied to the 16-bit output variable OUT. Assumption: The operands “IN1L”, “OUTH”, and “OUTL” can be in any Bank. In this macro, the linear data memory map is used. The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the Banks. Use of the linear data memory region allows buffers to be larger than 80 bytes, because incrementing the FSR beyond one Bank will go directly to the GPR memory of the next Bank. The 16 bytes of common memory are not included in the linear data memory region.

4.11

MACRO “MIN _5” (MINIMUM IN FIVE 8-BIT VARIABLES)

The symbol and the algorithm of the macro “min_5” are depicted in Table 4.11. Figures 4.19 and 4.20 show the macro “min_5” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a

Selection Macros

217

FIGURE 4.14 The fowchart of the macro “max_N40_16”.

Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has fve 8-bit input variables, IN1, IN2, IN3, IN4, and IN5, and an 8-bit output variable OUT. OUT represents the minimum value stored in fve input variables, IN1, IN2, …, IN5. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the minimum value in fve 8-bit input variables, IN1, IN2, …, IN5, is identifed. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1”, “IN2”, “IN3”, “IN4”, “IN5”, and “OUT” can be in any Bank.

218

Programmable Logic Controller

TABLE 4.9 Symbol and Algorithm of the Macro “max_N255” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) N (The number of successive 8-bit variables located in the GPR memories of the successive Banks, N) = 2, 3, …, 255 ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the maximum value stored in N input variables starting from IN1, OUT) Algorithm if then

EN = 1; OUT := MAX (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif;

4.12

MACRO MIN_10” (MINIMUM IN TEN 8-BIT VARIABLES)

The symbol and the algorithm of the macro “min_10” are depicted in Table 4.12. Figures 4.21 and 4.22 show the macro “min_10” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has ten 8-bit input variables, IN1, IN2, IN3, IN4, IN5, IN6, IN7, IN8, IN9, and IN10, and an 8-bit output variable OUT. OUT represents the minimum value stored in ten input variables, IN1, IN2, …, IN10. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the minimum value in ten 8-bit input variables, IN1, IN2, …, IN10, is identifed. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1”, “IN2”, “IN3”, “IN4”, “IN5”, “IN6”, “IN7”, “IN8”, “IN9”, “IN10”, and “OUT” can be in any Bank.

4.13

MACRO “MIN_N80” (MINIMUM IN N 8-BIT VARIABLES, N = 2, 3, …, 80)

The symbol and the algorithm of the macro “min_N80” are depicted in Table 4.13. Figures 4.23 and 4.24 show the macro “min_N80” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO

Selection Macros

FIGURE 4.15

219

The macro “max_N255”.

follows the input EN. This means that, when EN=0, ENO is forced to be 0, and. when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1, and an 8-bit output variable OUT. N represents the number of successive 8-bit variables located in the GPR area of the same Bank, which can be any number in 2, 3, …, 80. OUT represents the minimum value stored in N input variables, starting from IN1. The Boolean-enable-input signal EN should

220

FIGURE 4.16

Programmable Logic Controller

The fowchart of the macro “max_N255”.

221

Selection Macros

TABLE 4.10 Symbol and Algorithm of the Macro “max_N255_16” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1L (8-bit input variable, showing the Low byte of the 16-bit input variable IN1) N (The number of successive 16-bit variables located in the GPR memories of the successive Banks, N) = 2, 3, …, 255 ENO (Boolean-enable-output, through W) = 0 or 1 OUTH (8-bit output variable, showing the High byte of the maximum value stored in N 16-bit input variables starting from IN1, OUTH) OUTL (8-bit output variable, showing the Low byte of the maximum value stored in N 16-bit input variables starting from IN1, OUTL) Algorithm if then

EN = 1; OUT := MAX (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif; IN1 = IN1H & IN1L, IN2 = IN2H & IN2L, …, INN = INNH & INNL

be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the minimum value in N 8-bit input variables, IN1, IN2, …, INN, is identifed. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1” and “OUT” can be in any Bank. In this macro the traditional data memory map is used.

4.14 MACRO “MIN_N40_16” (MINIMUM IN N 16-BIT VARIABLES, N = 2, 3, …, 40) The symbol and the algorithm of the macro “min_N40_16” are depicted in Table 4.14. Figures 4.25 and 4.26 show the macro “min_N40_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1L, and two 8-bit output variables, OUTH and OUTL. N represents the number of successive 16-bit variables located in the GPR area of the same Bank, which can be any number in 2, 3, …, 40. It is assumed that N successive 16-bit variables (words) are located in the GPR area of the same Bank in little endian

222

Programmable Logic Controller

FIGURE 4.17 The macro “max_N255_16”.

format. IN1L represents the low byte of the frst 16-bit input variable IN1. OUTH represents the high byte of the minimum value stored in N 16-bit input variables starting from IN1. OUTL represents the low byte of the minimum value stored in N 16-bit input variables, starting from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the minimum value in N 16-bit input variables, IN1,

Selection Macros

223

FIGURE 4.17 Continued

IN2, …, INN, is identifed. Then, the contents of the input variable holding the minimum value are copied to the 16-bit output variable OUT. Assumption: The operands “IN1L”, “OUTH”, and “OUTL” can be in any Bank. In this macro the traditional data memory map is used.

4.15 MACRO “MIN_N255” (MINIMUM IN N 8-BIT VARIABLES, N = 2, 3, …, 255) The symbol and the algorithm of the macro “min_N255” are depicted in Table 4.15. Figures 4.27 and 4.28 show the macro “min_N255” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1, and an 8-bit output variable OUT. N represents the number of successive 8-bit variables located in the GPR memories of the successive Banks, which can be any number in 2, 3, …, 255. IN1 represents the frst 8-bit input variable. OUT represents the minimum value stored in N input variables, starting from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the minimum value in N 8-bit input variables, IN1, IN2, …, INN, is identifed. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT. Assumption: The operands “IN1” and “OUT” can be in any Bank.

224

Programmable Logic Controller

FIGURE 4.18 The fowchart of the macro “max_N255_16”.

225

Selection Macros

TABLE 4.11 Symbol and Algorithm of the Macro “min_5” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) IN2 (8-bit input variable, IN2) IN3 (8-bit input variable, IN3) IN4 (8-bit input variable, IN4) IN5 (8-bit input variable, IN5) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the minimum value stored in fve input variables IN1, IN2, …, IN5, OUT) Algorithm if then

EN = 1; OUT := MIN (IN1, IN2, IN3, IN4, IN5); ENO := 1;

else ENO := 0; endif;

In this macro, the linear data memory map is used. The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the Banks. Use of the linear data memory region allows buffers to be larger than 80 bytes, because incrementing the FSR beyond one Bank will go directly to the GPR memory of the next Bank. The 16 bytes of common memory are not included in the linear data memory region.

4.16

MACRO “MIN_N255_16” (MINIMUM IN N 16-BIT VARIABLES, N = 2, 3, …, 255)

The symbol and the algorithm of the macro “min_N255_16” are depicted in Table 4.16. Figures 4.29 and 4.30 show the macro “min_N255_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a constant value N, an 8-bit input variable IN1L, and two 8-bit output variables, OUTH and OUTL. N represents the number of successive 16-bit variables located in the GPR memories of the successive Banks, which can be any number in 2, 3, …, 255. It is assumed that N successive 16-bit variables (words) are located in the GPR memories of the successive Banks in little endian format. IN1L represents the low byte of the frst 16-bit input variable IN1. OUTH represents the high byte of the minimum value stored in N 16-bit input variables, starting from IN1. OUTL

226

FIGURE 4.19

Programmable Logic Controller

The macro “min_5”.

represents the low byte of the minimum value stored in N 16-bit input variables, starting from IN1. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1, frst, the minimum value in N 16-bit input variables, IN1, IN2, …, INN, is identifed. Then, the contents of the input variable holding the minimum value are copied to the 16-bit output variable OUT. Assumption: The operands “IN1L”, “OUTH”, and “OUTL” can be in any Bank. In this macro, the linear data memory map is used. The linear data memory is the region from FSR address 0x2000 to FSR address 0x29AF. This region is a virtual region that points back to the 80-byte blocks of GPR memory in all the Banks. Use of the linear data memory region allows buffers to be larger than 80 bytes, because incrementing the FSR beyond one Bank will go directly to the GPR memory of the next Bank. The 16 bytes of common memory are not included in the linear data memory region.

Selection Macros

227

FIGURE 4.20 The fowchart of the macro “min_5”.

4.17

MACRO “LIMITER”

The symbol and the algorithm of the macro “limiter” are depicted in Table 4.17. Figures 4.31 and 4.32 show the macro “limiter” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has two 8-bit constant values, MN and MX, an 8-bit input variable IN, and an 8-bit output variable OUT. MN represents the minimum value, and MX shows the maximum value. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1: if IN is less than MN, then OUT is equal to MN; if IN is greater than MX, then OUT is equal to MX; if MN ≤ IN ≤ MX, then OUT is equal to IN. Assumption 1: The operands “IN” and “OUT” can be in any Bank. Assumption 2: MN < MX. Assumption 3: 0 < MN < 256. Assumption 4: 0 < MX < 256.

228

Programmable Logic Controller

TABLE 4.12 Symbol and Algorithm of the Macro “min_10” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) IN2 (8-bit input variable, IN2) IN3 (8-bit input variable, IN3) IN4 (8-bit input variable, IN4) IN5 (8-bit input variable, IN5) IN6 (8-bit input variable, IN6) IN7 (8-bit input variable, IN7) IN8 (8-bit input variable, IN8) IN9 (8-bit input variable, IN9) IN10 (8-bit input variable, IN10) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the minimum value stored in ten input variables IN1, IN2, …, IN10, OUT) Algorithm if then

EN = 1; OUT := MIN (IN1, IN2, IN3, …, IN10); ENO := 1;

else ENO := 0; endif;

4.18

MACRO “LIMITER_16”

The symbol and the algorithm of the macro “limiter_16” are depicted in Table 4.18. Figures 4.33 and 4.34 show the macro “limiter_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has two 16-bit constant values, MN and MX, a 16-bit input variable IN, and a 16-bit output variable OUT. MN represents the minimum value, and MX shows the maximum value. IN consists of two 8-bit variables, INH and INL. INH holds the high byte of IN, and INL holds the low byte of IN. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Booleanenable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When EN = 1: if IN is less than MN, then OUT is equal to MN; if IN is greater than MX, then OUT is equal to MX; if MN ≤ IN ≤ MX, then OUT is equal to IN. Assumption 1: The operands “INH”, “INL”, “OUTH”, and “OUTL” can be in any Bank. Assumption 2: The operands “IN” and “OUT”

Selection Macros

229

FIGURE 4.21 The macro “min_10”.

can be in any Bank. Assumption 3: MN < MX. Assumption 4: 0 < MN < 65536. Assumption 5: 0 < MX < 65536.

4.19 MULTIPLEXER MACROS As a standard combinational component, the multiplexer, abbreviated MUX, allows the selection of one input signal among n signals, where n > 1 and is a power of two. Select lines connected to the multiplexer determine which input signal is selected and passed to the output of the multiplexer. As can be seen from Figure 4.35, in general, an n-to-1 multiplexer has n data input lines, m select lines, where m = log2 n, i.e. 2m = n, and one output line. However, not shown in Figure 4.35, in addition to the other inputs, the multiplexer may have an enable line, E, for enabling it. When the multiplexer is disabled, with E set to 0 (for active-high enable input E), no input signal is selected and passed to the output.

230

Programmable Logic Controller

FIGURE 4.22

4.20

The fowchart of the macro “min_10”.

MACRO “MUX_2_1”

The truth table and the symbol of the macro “mux_2_1” are depicted in Table 4.19. Figures 4.36 and 4.37 show the macro “mux_2_1” and its fowchart, respectively. In this macro, the select input, s0, input signals, “d0” and “d1”, and the output, y, are all Boolean variables. When s0 = 0, the input signal “d0” is selected and passed to the output “y”. When s0 = 1, the input signal “d1” is selected and passed to the output “y”. Assumption: The operands “regs0,bits0”, “regi1,biti1”, “regi0,biti0”, and “rego,bito” can be in any Bank.

4.21

MACRO “MUX_2_1_E”

The truth table and the symbol of the macro “mux_2_1_E” are depicted in Table 4.20. Figures 4.38 and 4.39 show the macro “mux_2_1_E” and its fowchart, respectively. In this macro, the active-high enable input, E, the select input, s0, input signals, “d0” and “d1”, and the output, y, are all Boolean variables. When this multiplexer is

231

Selection Macros

TABLE 4.13 Symbol and Algorithm of the Macro “min_N80” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) N (The number of successive 8-bit variables located in the GPR area of the same Bank, N) = 2, 3, …, 80 ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the minimum value stored in N input variables starting from IN1, OUT) Algorithm if then

EN = 1; OUT := MIN (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif;

disabled, with E set to 0, no input signal is selected and passed to the output. When this multiplexer is enabled, with E set to 1, it functions as described for “mux_2_1”. This means that, when E = 1: if s0 = 0, then the input signal “d0” is selected and passed to the output “y”. When E = 1: if s0 = 1, then the input signal “d1” is selected and passed to the output “y”. Assumption: The operands “regs0,bits0”, “regi1,biti1”, “regi0,biti0”, and “rego,bito” can be in any Bank.

4.22

MACRO “MUX_4_1”

The truth table and the symbol of the macro “mux_4_1” are depicted in Table 4.21. Figures 4.40 and 4.41 show the macro “mux_4_1” and its fowchart, respectively. In this macro, select inputs, s1, s0, input signals, “d0”, “d1”, “d2”, and “d3”, and the output, y, are all Boolean variables. When s1s0 = 00 (respectively, 01, 10, 11), the input signal “d0” (respectively, d1, d2, d3) is selected and passed to the output “y”. Assumption: The operands “regs1,bits1”, “regs0,bits0”, “regi3,biti3”, “regi2,biti2”, “regi1,biti1”, “regi0,biti0”, and “rego,bito” can be in any Bank.

4.23

MACRO “MUX_4_1_E”

The truth table and the symbol of the macro “mux_4_1_E” are depicted in Table  4.22. Figures 4.42 and 4.43 show the macro “mux_4_1_E” and its fowchart, respectively. In this macro, the active-high enable input, E, select inputs, s1, s0, input signals, “d0”, “d1”, “d2”, and “d3”, and the output, y, are all Boolean variables. When this multiplexer is disabled, with E set to 0, no input signal

232

FIGURE 4.23

Programmable Logic Controller

The macro “min_N80”.

is selected and passed to the output. When this multiplexer is enabled, with E set to 1, it functions as described for “mux_4_1”. This means that, when E = 1: if s1s0 = 00 (respectively, 01, 10, 11), then the input signal “d0” (respectively, d1, d2, d3) is selected and passed to the output “y”. Assumption: The operands “regs1,bits1”, “regs0,bits0”, “regi3,biti3”, “regi2,biti2”, “regi1,biti1”, “regi0,biti0”, and “rego,bito” can be in any Bank.

Selection Macros

FIGURE 4.24

4.24

233

The fowchart of the macro “min_N80”.

MACRO “MUX_8_1”

The truth table and the symbol of the macro “mux_8_1” are depicted in Table 4.23. Figures 4.44 and 4.45 show the macro “mux_8_1” and its fowchart, respectively. In this macro, select inputs, s2, s1, s0, input signals, “d0”, “d1”, “d2”, “d3”, “d4”, “d5”, “d6”, and “d7”, and the output, y, are all Boolean variables. When s2s1s0 = 000 (respectively, 001, 010, 011, 100, 101, 110, 111), the input signal “d0” (respectively, d1, d2, d3, d4, d5, d6, d7) is selected and passed to the output “y”. Assumption: The operands “regs2,bits2”, “regs1,bits1”, “regs0,bits0”, “regi7,biti7”, “regi6,biti6”, “regi5,biti5”, “regi4,biti4”, “regi3,biti3”, “regi2,biti2”, “regi1,biti1”, “regi0,biti0”, and “rego,bito” can be in any Bank.

4.25

MACRO “MUX_8_1_E”

The truth table and the symbol of the macro “mux_8_1_E” are depicted in Table 4.24. Figures 4.46 and 4.47 show the macro “mux_8_1_E” and its fowchart, respectively. In this macro, the active-high enable input, E, select inputs, s2, s1, s0, input signals, “d0”, “d1”, “d2”, “d3”, “d4”, “d5”, “d6”, and “d7”, and the output, y, are all Boolean variables. When this multiplexer is disabled, with E set to 0, no input signal

234

Programmable Logic Controller

TABLE 4.14 Symbol and Algorithm of the Macro “min_N40_16” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1L (8-bit input variable, showing the Low byte of the 16-bit input variable IN1) N (The number of successive 16-bit variables located in the GPR area of the same Bank, N) = 2, 3, …, 40 ENO (Boolean-enable-output, through W) = 0 or 1 OUTH (8-bit output variable, showing the High byte of the minimum value stored in N 16-bit input variables starting from IN1, OUTH) OUTL (8-bit output variable, showing the Low byte of the minimum value stored in N 16-bit input variables starting from IN1, OUTL) Algorithm if then

EN = 1; OUT := MIN (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif; IN1 = IN1H & IN1L, IN2 = IN2H & IN2L, …, INN = INNH & INNL

is selected and passed to the output. When this multiplexer is enabled, with E set to 1, it functions as described for “mux_8_1”. This means that, when E = 1: if s2s1s0 = 000 (respectively, 001, 010, 011, 100, 101, 110, 111), then the input signal “d0” (respectively, d1, d2, d3, d4, d5, d6, d7) is selected and passed to the output “y”. Assumption: The operands “regs2,bits2”, “regs1,bits1”, “regs0,bits0”, “regi7,biti7”, “regi6,biti6”, “regi5,biti5”, “regi4,biti4”, “regi3,biti3”, “regi2,biti2”, “regi1,biti1”, “regi0,biti0”, and “rego,bito” can be in any Bank.

4.26 MACRO “MUX_16_1” The truth table and the symbol of the macro “mux_16_1” are depicted in Table 4.25. Figures 4.48 and 4.49 show the macro “mux_16_1” and its fowchart, respectively. In this macro, select inputs s3, s2, s1, s0, input signals “d0”, “d1”, “d2”, “d3”, “d4”, “d5”, “d6”, “d7”, “d8”, “d9”, “d10”, “d11”, “d12”, “d13”, “d14” and “d15”, and the output y are all Boolean variables. When s3s2s1s0 = 0000, (respectively, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) the input signal “d0” (respectively, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15) is selected and passed to the output “y”. Assumption: The operands “Sin”, “DinH”, “DinL”, “rego,bito” can be in any Bank.

Selection Macros

FIGURE 4.25

235

The macro “min_N40_16”.

4.27 MACRO “MUX_16_1_E” The truth table and the symbol of the macro “mux_16_1_E” are depicted in Table 4.26. Figures 4.50 and 4.51 show the macro “mux_16_1_E” and its fowchart, respectively. In this macro, the active-high enable input E, select inputs s3, s2, s1, s0, input signals “d0”, “d1”, “d2”, “d3”, “d4”, “d5”, “d6”, “d7”, “d8”, “d9”, “d10”, “d11”, “d12”, “d13”, “d14” and “d15”, and the output y are all Boolean variables. When this multiplexer is

236

FIGURE 4.25

Programmable Logic Controller

Continued

disabled with E set to 0, no input signal is selected and passed to the output. When this multiplexer is enabled with E set to 1, it functions as described for “mux_16_1”. This means that when E = 1: if s3s2s1s0 = 0000, (respectively, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111) the input signal “d0” (respectively, d1, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10, d11, d12, d13, d14, d15) is selected and passed to the output “y”. Assumption: The operands “Sin”, “DinH”, “DinL”, “rego,bito” can be in any Bank.

4.28 MACRO “B_MUX_2_1_E” The truth table and the symbol of the macro “B_mux_2_1_E” are depicted in Table 4.27. Figures 4.52 and 4.53 show the macro “B_mux_2_1_E” and its fowchart, respectively. In this macro, the active-high enable input E and the select input s0 are Boolean variables. R1 and R0 are 8-bit source variables, and OUT is an 8-bit destination variable. When this byte multiplexer is disabled, with E set to 0, no input variable is selected and passed to the output Y. Therefore, the contents of the output Y (the destination variable OUT) remain unchanged. When this byte multiplexer is enabled, with E set to 1: if s0 = 0, then the 8-bit input variable R0 is selected and passed to the output Y (the destination variable OUT). When E = 1: if s0 = 1, then the 8-bit input variable R1 is selected and passed to the output Y (the destination

Selection Macros

FIGURE 4.26

237

The fowchart of the macro “min_N40_16”.

variable OUT). Assumption: The operands “regs0,bits0”, “R1”, “R0”, and “OUT” can be in any Bank.

4.29

MACRO “B_MUX_4_1_E”

The truth table and the symbol of the macro “B_mux_4_1_E” are depicted in Table 4.28. Figures 4.54 and 4.55 show the macro “B_mux_4_1_E” and its fowchart, respectively. In this macro, the active-high enable input, E, and select inputs, s1 and s0, are all Boolean variables. R3, R2, R1, and R0 are 8-bit source variables, and OUT

238

Programmable Logic Controller

TABLE 4.15 Symbol and Algorithm of the Macro “min_N255” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1 (8-bit input variable, IN1) N (The number of successive 8-bit variables located in the GPR memories of the successive Banks, N) = 2, 3, …, 255 ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, showing the minimum value stored in N input variables starting from IN1, OUT) Algorithm if then

EN = 1; OUT := MIN (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif;

is an 8-bit destination variable. When this byte multiplexer is disabled, with E set to 0, no input variable is selected and passed to the output Y. Therefore, the contents of the output Y (the destination variable OUT) remain unchanged. When this byte multiplexer is enabled, with E set to 1: if s1s0 = 00 (respectively, 01, 10, 11), then the 8-bit input variable R0 (respectively, R1, R2, R3) is selected and passed to the output Y (the destination variable OUT). Assumption: The operands “regs1,bits1”, “regs0,bits0”, “R3”, “R2”, “R1”, “R0”, and “OUT” can be in any Bank.

4.30

MACRO “B_MUX_8_1_E”

The truth table and the symbol of the macro “B_mux_8_1_E” are depicted in Table 4.29. Figures 4.56 and 4.57 show the macro “B_mux_8_1_E” and its fowchart, respectively. In this macro, the active-high enable input, E, and select inputs, s2, s1, and s0, are all Boolean variables. R7, R6, R5, R4, R3, R2, R1, and R0 are 8-bit source variables, and OUT is an 8-bit destination variable. When this byte multiplexer is disabled, with E set to 0, no input variable is selected and passed to the output Y. Therefore, the contents of the output Y (the destination variable OUT) remain unchanged. When this byte multiplexer is enabled, with E set to 1: if s2s1s0 = 000 (respectively, 001, 010, 011, 100, 101, 110, 111), then the 8-bit input variable R0 (respectively, R1, R2, R3, R4, R5, R6, R7) is selected and passed to the output Y (the destination variable OUT). Assumption: The operands “regs2,bits1”, “regs1,bits1”, “regs0,bits0”, “R7”, “R6”, “R5”, “R4”, “R3”, “R2”, “R1”, “R0”, and “OUT” can be in any Bank.

Selection Macros

FIGURE 4.27

The macro “min_N255”.

239

240

Programmable Logic Controller

FIGURE 4.28 The fowchart of the macro “min_N255”.

241

Selection Macros

TABLE 4.16 Symbol and Algorithm of the Macro “min_N255_16” Symbol EN (Boolean-enable-input, through W) = 0 or 1 IN1L (8-bit input variable, showing the Low byte of the 16-bit input variable IN1) N (The number of successive 16-bit variables located in the GPR memories of the successive Banks, N) = 2, 3, …, 255 ENO (Boolean-enable-output, through W) = 0 or 1 OUTH (8-bit output variable, showing the High byte of the minimum value stored in N 16-bit input variables starting from IN1, OUTH) OUTL (8-bit output variable, showing the Low byte of the minimum value stored in N 16-bit input variables starting from IN1, OUTL) Algorithm if then

EN = 1; OUT := MIN (IN1, IN2, …, INN); ENO := 1;

else ENO := 0; endif; IN1 = IN1H & IN1L, IN2 = IN2H & IN2L, …, INN = INNH & INNL

4.31 EXAMPLES FOR SELECTION MACROS Up to now in this chapter, we have seen selection macros developed for the PIC16F1847-Based PLC. It is now time to consider some examples related to these macros. Before you can run the example programs considered here, you are expected to construct your own PIC16F1847-Based PLC hardware by using the necessary PCB fles and by producing your PCBs, with their components. For an effective use of examples, all example programs considered in this book are allocated within the fle “PICPLC_PIC16F1847_user_Int.inc”, which is downloadable from this book’s webpage under the downloads section. Initially, all example programs are commented out by putting a semicolon, “;”, in front of each line. When you would like to test one of the example programs, you must uncomment each line of the example program by following the steps shown below: 1. Highlight the block of source lines you want to uncomment by dragging the mouse with the left mouse button held down over these lines. With default coloring in MPLAB X IDE, you will see now green characters on a blue background. 2. Release the mouse button.

242

Programmable Logic Controller

FIGURE 4.29 The macro “min_N255_16”.

3. Press Ctrl/Shift/C or Press “Alt”, “S”, and “M” keys in succession, or, from the toolbar “Source” menu, select “Toggle Comment”. Now, a semicolon will be removed from all selected source lines. With default coloring, you will see red characters on a white background. Then, you can run the project by pressing the symbol from the toolbar. Next, the MPLAB X IDE will produce the “PICPLC_PIC16F1847.X.production.hex” fle for

Selection Macros

243

FIGURE 4.29 Continued

the project. Then, the MPLAB X IDE will be connected to the PICkit3 programmer and, fnally, it will program the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC. During these steps, make sure that, in the CPU board of the PIC16F1847-Based PLC, the 4PDT switch is in the “PROG” position and the power switch is in the “OFF” position. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Finally, you are ready to test the example program. Warning: When you fnish your study with an example and try to take a look at another example, do not forget to comment the current example program before uncommenting another one. In other words, make sure that only one example program is uncommented and tested at a time. Otherwise if you somehow leave more than one example uncommented, the example you are trying to test probably will not function as expected as it may try to access the same resources that are being used and changed by other examples. Please check the accuracy of each program by cross-referencing it with the related macros.

4.31.1

EXAMPLE 4.1

Example 4.1 shows the usage of the selection macros: “move_R” and “load_R”. The user program of Example 4.1 is shown in Figure 4.58. The schematic diagram of Example 4.1 is depicted in Figure 4.59. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user

244

Programmable Logic Controller

FIGURE 4.30 The fowchart of the macro “min_N255_16”.

245

Selection Macros

TABLE 4.17 Symbol and Algorithm of the Macro “limiter” Symbol EN (Boolean-enable-input, through W) = 0 or 1 MN (8-bit constant value, MN) IN (8-bit input variable, IN) MX (8-bit constant value, MX) ENO (Boolean-enable-output, through W) = 0 or 1 OUT (8-bit output variable, OUT) Algorithm if then

EN = 1; if IN < MN, then OUT := MN; elseif IN > MX, then OUT := MX; else OUT := IN; endif; ENO := 1;

else ENO := 0; endif;

_Int.inc”, if you uncomment Example 4.1 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, as EN = LOGIC1, the contents of I0 are sent to the output register Q0 by using the “move_R” function, i.e., the move operation “Q0 := I0” is carried out. In rung 2, as EN = LOGIC1, the contents of I1 are sent to the output register Q1 by using the “move_R” function, i.e., the move operation “Q1 := I1” is carried out. In rung 3, as EN = I2.0 AND I2.1, when I2.0 = 1 and I2.1 = 0, the constant value 0Fh is loaded into the output register Q2 by using the “load_R” function, i.e., the load operation “Q2 := 0Fh” is carried out. In rung 4, as EN = I2.1 AND I2.0, when I2.1 = 1 and I2.0 = 0, the constant value F0h is loaded into the output register Q2 by using the “load_R” function, i.e., the load operation “Q2 := F0h” is carried out. In rung 5, as EN = I3.0 AND I3.1, when I3.0 = 1 and I3.1 = 0, the constant value 3Ch is loaded into the output register Q3 by using the “load_R” function, i.e., the load operation “Q3 := 3Ch” is carried out.

246

FIGURE 4.31

Programmable Logic Controller

The macro “limiter”.

In rung 6, sa EN = I3.1 AND I3.0, when I3.1 = 1 and I3.0 = 0, the constant value C3h is loaded into the output register Q3 by using the “load_R” function, i.e., the load operation “Q3 := C3h” is carried out.

Selection Macros

247

FIGURE 4.32 The fowchart of the macro “limiter”.

4.31.2 EXAMPLE 4.2 Example 4.2 shows the usage of the selection macro “select”. The user program of Example 4.2 is shown in Figure 4.60. The schematic diagram of Example 4.2 is depicted in Figure 4.61. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.2 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847

248

Programmable Logic Controller

TABLE 4.18 Symbol and Algorithm of the Macro “limiter_16” Symbol EN (Boolean-enable-input, through W) = 0 or 1 MN (16-bit constant value, MN) INH (HIGH byte of a 16-bit input variable IN, INH) INL (LOW byte of a 16-bit input variable IN, INL) MX (16-bit constant value, MX) ENO (Boolean-enable-output, through W) = 0 or 1 OUTH (HIGH byte of a 16-bit output variable OUT, OUTH) OUTL (LOW byte of a 16-bit output variable OUT, OUTL) Algorithm if then

EN = 1; if IN < MN, Then OUT := MN; elseif IN > MX, Then OUT := MX; else OUT := IN; endif; ENO := 1;

else ENO := 0; endif;

microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “select” macro is implemented with EN = I0.0, G = I0.1, IN0 = I1, IN1 = I2, and OUT = Q0. When this macro is enabled (I0.0 = 1), if G (I0.1) = 0, then Q0 := I1; if G (I0.1) = 1, then Q0 := I2.

4.31.3 EXAMPLE 4.3 Example 4.3 shows the usage of the selection macro “select_16”. The user program of Example 4.3 is shown in Figure 4.62. The schematic diagram of Example 4.3 is depicted in Figure 4.63. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.3 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

Selection Macros

249

FIGURE 4.33 The macro “limiter_16”.

In rung 1, the “select_16” macro is implemented with EN = LOGIC1, G = T_1s, IN0H = I1, IN0L = I0, IN1H = I3, IN1H = I2, OUTH = Q1, and OUTL = Q0. As EN = LOGIC1, this macro is always enabled. If G (T_1s) = 0, then Q1,Q0 := I1,I0; if G (T_1s) = 1, then Q1,Q0 := I3,I2.

4.31.4

EXAMPLE 4.4

Example 4.4 shows the usage of the selection macro “max_5”. The user program of Example 4.4 is shown in Figure 4.64. The schematic diagram of Example 4.4 is depicted in Figure 4.65. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.4 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

250

Programmable Logic Controller

FIGURE 4.33 Continued

In rung 1, as EN = FRSTSCN, with the frst PLC scan, the constant value 5 is loaded into the output register 0x020 (the frst register allocated in the GPR area of Bank 0) by using the “load_R” function, i.e., the load operation “0x020 := 5” is carried out. In rung 2, the “max_5” macro is implemented with EN = LOGIC1, IN1 = I0, IN2 = I1, IN3 = I2, IN4 = I3, IN5 = 0x020, and OUT = Q0. As EN = LOGIC1, this macro is always enabled. The macro “max_5” frst

Selection Macros

FIGURE 4.34

The fowchart of the macro “limiter_16”.

251

252

Programmable Logic Controller

FIGURE 4.35

The general form of an n-to-1 multiplexer, where n = 2m.

TABLE 4.19 Truth Table and Symbol of the Macro “mux_2_1” Truth Table

Symbol

input

output

s0 =

regs0,bits0

s0 0

y d0

d1 = d0 =

regi1,biti1 regi0,biti0

1

d1

y=

rego,bito

identifes the maximum value in fve 8-bit input variables, IN1, IN2, …, IN5. Then, the contents of the input variable holding the maximum value are copied to the 8-bit output variable OUT, i.e., OUT := MAX (IN1, IN2, IN3, IN4, IN5).

4.31.5

EXAMPLE 4.5

Example 4.5 shows the usage of the selection macros “max_5”, “max_10”, “max_ N80”, and “max_N255”, together with the macro “fll_sram_N255” (for the detailed explanation of this macro, the reader is referred to Chapter 3 of the Advanced Concepts volume). The user program of Example 4.5 is shown in Figure 4.66. The schematic diagram of Example 4.5 is depicted in Figure 4.67. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 4.5 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the

Selection Macros

FIGURE 4.36 The macro “mux_2_1”.

FIGURE 4.37

The fowchart of the macro “mux_2_1”.

253

254

Programmable Logic Controller

TABLE 4.20 Truth Table and Symbol of the Macro “mux_2_1_E” Truth Table Inputs E 0 1 1

s0 × 0 1

Symbol

Output

E

W

y 0 d0 d1

s0 = d1 = d0 =

regs0,bits0 regi1,biti1 regi0,biti0

y=

rego,bito

×: don’t care.

FIGURE 4.38 The macro “mux_2_1_E”.

program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “fll_sram_N255” instruction is used with EN = FRSTSCN, IN1 = 020h, N = 255, Value = 1, Operator = ‘+’, and K = 1. When this instruction is enabled during the frst PLC scan time, it flls 255 consecutive registers of Bank 0, Bank 1, Bank 2, and Bank 3 with the values as shown in Figure 4.68.

255

Selection Macros

FIGURE 4.39 The fowchart of the macro “mux_2_1_E”.

TABLE 4.21 Truth Table and Symbol of the Macro “mux_4_1” Truth Table Inputs

Symbol Output

s1 =

regs1,bits1

s1 0 0 1

s0 0 1 0

y d0 d1 d2

1

1

d3

s0 = d3 = d2 = d1 = d0 =

regs0,bits0 regi3,biti3 regi2,biti2 regi1,biti1 regi0,biti0

y=

rego,bito

256

FIGURE 4.40

Programmable Logic Controller

The macro “mux_4_1”.

In rung 2, the “max_5” macro is implemented with EN = I0.0, IN1 = 0x1A0, IN2 = 0x1A1, IN3 = 0x1A2, IN4 = 0x1A3, IN5 = 0x1A4, and OUT = Q0. When this macro is enabled, i.e., when I0.0 = 1, the macro “max_5” frst identifes the maximum value in fve 8-bit input variables, IN1, IN2, …, IN5. Then, the contents of the input variable holding the maximum value

257

Selection Macros

FIGURE 4.41

The fowchart of the macro “mux_4_1”.

are copied to the 8-bit output variable OUT, i.e., OUT := MAX (IN1, IN2, IN3, IN4, IN5). As the values are defned as shown in Figure 4.68, we can see that the output variable OUT will be found as follows: OUT = Q0 = (245) decimal = (F5) hexadecimal = (1111 0101) binary. In rung 3, the “max_10” macro is implemented with EN = I0.1, IN1 = 0x020, IN2 = 0x048, IN3 = 0x0A1, IN4 = 0x0C9, IN5 = 0x0EF, IN6 = 0x130, IN7 = 0x14F, IN8 = 0x168, IN9 = 0x1A0, IN10 = 0x1AF, and OUT = Q1. When this macro is enabled, i.e., when I0.1 = 1, the macro “max_10” frst identifes the maximum value in ten 8-bit input variables, IN1, IN2, …, IN10. Then, the contents of the input variable holding the maximum value are copied to the 8-bit output variable OUT, i.e., OUT := MAX (IN1, IN2, …, IN10). As the values are defned as shown in Figure 4.68, we can see

TABLE 4.22 Truth Table and Symbol of the Macro “mux_4_1_E” Truth Table Inputs E 0 1 1 1 1

Symbol Output

s1 × 0 0 1 1

s0 × 0 1 0 1

×: don’t care.

y 0 d0 d1 d2 d3

E

W

s1 = s0 = d3 = d2 = d1 = d0 =

regs1,bits1 regs0,bits0 regi3,biti3 regi2,biti2 regi1,biti1 regi0,biti0

y=

rego,bito

258

Programmable Logic Controller

FIGURE 4.42 The macro “mux_4_1_E”.

that the output variable OUT will be found as follows: OUT = Q1 = (241) decimal = (F1) hexadecimal = (1111 0001) binary. In rung 4, the “max_N80” macro is implemented with EN = I0.2, IN1 = 0x030, N = 40 (decimal), and OUT = Q2. When this macro is enabled, i.e., when I0.2 = 1, the macro “max_ N80” frst identifes the maximum value in forty 8-bit input variables, starting from IN1. Then, the contents of the input

259

Selection Macros

FIGURE 4.43 The fowchart of the macro “mux_4_1_E”.

TABLE 4.23 Truth Table and Symbol of the Macro “mux_8_1” Truth Table Inputs

Symbol Output

s2 =

regs2,bits2

s1 = s0 = d7 = d6 = d5 = d4 = d3 = d2 = d1 = d0 =

regs1,bits1 regs0,bits0 regi7,biti7 regi6,biti6 regi5,biti5 regi4,biti4 regi3,biti3 regi2,biti2 regi1,biti1 regi0,biti0

y=

rego,bito

s2 0 0 0 0 1 1 1

s1 0 0 1 1 0 0 1

s0 0 1 0 1 0 1 0

y d0 d1 d2 d3 d4 d5 d6

1

1

1

d7

260

FIGURE 4.44

Programmable Logic Controller

The macro “mux_8_1”.

Selection Macros

FIGURE 4.44

261

Continued

variable holding the maximum value are copied to the 8-bit output variable OUT, i.e., OUT := MAX (IN1, IN2, …, IN40). As the values are defned as shown in Figure 4.68, we can see that the output variable OUT will be found as follows: OUT = Q2 = (56) decimal = (38) hexadecimal = (0011 1000) binary. In rung 5, the “max_N255” macro is implemented with EN = I0.3, IN1 = 0x020, N = 255 (decimal), and OUT = Q3. When this macro is enabled, i.e., when I0.3 = 1, the macro “max_ N255” frst identifes the maximum value in two hundred and ffty-fve 8-bit input variables, starting from IN1. Then, the contents of the input variable holding the maximum value are copied to the 8-bit output variable OUT, i.e., OUT := MAX (IN1, IN2, …, IN255). As the values are defned as shown in Figure 4.68, we can see that the output variable OUT will be found as follows: OUT = Q3 = (255) decimal = (FF) hexadecimal = (1111 1111) binary.

4.31.6

EXAMPLE 4.6

Example 4.6 shows the usage of the selection macro “min_5”. The user program of Example 4.6 is shown in Figure 4.69. The schematic diagram of Example 4.6 is depicted in Figure 4.70. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.6 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

FIGURE 4.45 The fowchart of the macro “mux_8_1”.

262 Programmable Logic Controller

263

Selection Macros

TABLE 4.24 Truth Table and Symbol of the Macro “mux_8_1_E” Truth Table Inputs E 0 1 1 1 1 1 1 1 1

Symbol Output

s2 × 0 0 0 0 1 1 1 1

s1 × 0 0 1 1 0 0 1 1

×: don’t care.

s0 × 0 1 0 1 0 1 0 1

y 0 d0 d1 d2 d3 d4 d5 d6 d7

E

W

s2 = s1 = s0 = d7 = d6 = d5 = d4 = d3 = d2 = d1 = d0 =

regs2,bits2 regs1,bits1 regs0,bits0 regi7,biti7 regi6,biti6 regi5,biti5 regi4,biti4 regi3,biti3 regi2,biti2 regi1,biti1 regi0,biti0

y=

rego,bito

In rung 1, as EN = FRSTSCN, with the frst PLC scan, the constant value 5 is loaded into the output register 0x020 (the frst register allocated in the GPR area of Bank 0) by using the “load_R” function, i.e., the load operation “0x020 := 5” is carried out. In rung 2, the “min_5” macro is implemented with EN = LOGIC1, IN1 = I0, IN2 = I1, IN3 = I2, IN4 = I3, IN5 = 0x020, and OUT = Q0. As EN = LOGIC1, this macro is always enabled. The macro “min_5” frst identifes the minimum value in fve 8-bit input variables, IN1, IN2, …, IN5. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, IN3, IN4, IN5).

4.31.7 EXAMPLE 4.7 Example 4.7 shows the usage of the selection macros “min_5”, “min_10”, “min_ N80”, and “min_N255”, together with the macro “fll_sram_N255” (for the detailed explanation of this macro, the reader is referred to Chapter 3 of the Advanced Concepts volume). The user program of Example 4.7 is shown in Figure 4.71. The schematic diagram of Example 4.7 is depicted in Figure 4.72. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.7 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

264

FIGURE 4.46 The macro “mux_8_1_E”.

Programmable Logic Controller

Selection Macros

265

FIGURE 4.46 Continued

In rung 1, the “fll_sram_N255” instruction is used with EN = FRSTSCN, IN1 = 020h, N = 255, Value = 1, Operator = ‘+’, and K = 1. When this instruction is enabled during the frst PLC scan time, it flls 255 consecutive registers of Bank 0, Bank 1, Bank 2, and Bank 3 with the values as shown in Figure 4.73. In rung 2, the “min_5” macro is implemented with EN = I0.0, IN1 = 0x1A0, IN2 = 0x1A1, IN3 = 0x1A2, IN4 = 0x1A3, IN5 = 0x1A4, and OUT = Q0. When this macro is enabled, i.e., when I0.0 = 1, the macro “min_5” frst identifes the minimum value in fve 8-bit input variables, IN1, IN2, …, IN5. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, IN3, IN4, IN5). As the values are defned as shown in Figure 4.73, we can see that the output variable OUT will be found as follows: OUT = Q0 = (241) decimal = (F1) hexadecimal = (1111 0001) binary. In rung 3, the “min_10” macro is implemented with EN = I0.1, IN1 = 0x020, IN2 = 0x048, IN3 = 0x0A1, IN4 = 0x0C9, IN5 = 0x0EF, IN6 = 0x130, IN7 = 0x14F, IN8 = 0x168, IN9 = 0x1A0, IN10 = 0x1AF, and OUT = Q1. When this macro is enabled, i.e., when I0.1 = 1, the macro “min_10” frst identifes the minimum value in ten 8-bit input variables, IN1, IN2, …, IN10. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, …, IN10). As the values are defned as shown in Figure 4.73, we can see that the output

FIGURE 4.47 The fowchart of the macro “mux_8_1_E”.

266 Programmable Logic Controller

267

Selection Macros

TABLE 4.25 Truth Table and Symbol of the Macro “mux_16_1” Truth Table Inputs

Symbol Output

s3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

s2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1

s1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

s0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

y d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14

1

1

1

1

d15

s3 =

Sin,3

s2 = s1 = s0 = d15 = d14 = d13 = d12 = d11 = d10 = d9 = d8 = d7 = d6 = d5 = d4 = d3 = d2 = d1 = d0 =

Sin,2 Sin,1 Sin,0 DinH,7 DinH,6 DinH,5 DinH,4 DinH,3 DinH,2 DinH,1 DinH,0 DinL,7 DinL,6 DinL,5 DinL,4 DinL,3 DinL,2 DinL,1 DinL,0

y=

rego,bito

variable OUT will be found as follows: OUT = Q1 = (0) decimal = (00) hexadecimal = (0000 0000) binary. In rung 4, the “min_N80” macro is implemented with EN = I0.2, IN1 = 0x030, N = 40 (decimal), and OUT = Q2. When this macro is enabled, i.e., when I0.2 = 1, the macro “min_ N80” frst identifes the minimum value in forty 8-bit input variables, starting from IN1. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, …, IN40). As the values are defned as shown in Figure 4.73, we can see that the output variable OUT will be found as follows: OUT = Q2 = (17) decimal = (11) hexadecimal = (0001 0001) binary. In rung 5, the “min_N255” macro is implemented with EN = I0.3, IN1 = 0x020, N = 255 (decimal), and OUT = Q3. When this macro is enabled, i.e., when I0.3 = 1, the macro “min_ N255” frst identifes the minimum value in two hundred and ffty-fve 8-bit input variables, starting from IN1. Then, the contents of the input variable holding the minimum value are copied to the 8-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, …, IN255). As the values are defned as shown in Figure 4.73, we can see that the output

268

Programmable Logic Controller

FIGURE 4.48

The macro “mux_16_1”.

variable OUT will be found as follows: OUT = Q3 = (1) decimal = (01) hexadecimal = (0000 0001) binary.

4.31.8 EXAMPLE 4.8 Example 4.8 shows the usage of the selection macro “max_N40_16”, together with the macros “fll_sram_N80” (Chapter 3 of the Advanced Concepts volume) and

Selection Macros

FIGURE 4.48

Continued

269

270

FIGURE 4.48

Programmable Logic Controller

Continued

“sram_read” (Chapter 3 of the Advanced Concepts volume). The user program of Example 4.8 is shown in Figure 4.74. The schematic diagram of Example 4.8 is depicted in Figure 4.75. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.8 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “fll_sram_N80” instruction is used with EN = FRSTSCN, IN1 = 020h, N = 80, Value = AAh, Operator = ‘+’, and K = 1. When this instruction is enabled during the frst PLC scan time, it flls 80 consecutive registers of Bank 0 with the values as shown in Figure 4.76. In rung 2, the “max_N40_16” macro is implemented with EN = LOGIC1, IN1L = 0x020, N = 40 (decimal), OUTH = Q1, and OUTL = Q0. As EN = LOGIC1, this macro is always enabled. The macro “max_N40_16” frst identifes the maximum value in forty 16-bit input variables, IN1, IN2, …, IN40, allocated in Bank 0, in little endian format as shown in Figure 4.76. Then, the contents of the 16-bit input variable holding the maximum value are copied to the 16-bit output variable OUT, i.e., OUT := MAX (IN1, IN2,

FIGURE 4.49 The fowchart of the macro “mux_16_1”.

Selection Macros 271

272

Programmable Logic Controller

TABLE 4.26 Truth Table and Symbol of the Macro “mux_16_1_E” Truth Table

Symbol

Inputs

Output

E

W

s3 = s2 = s1 = s0 = d15 = d14 = d13 = d12 = d11 = d10 = d9 = d8 = d7 = d6 = d5 = d4 = d3 = d2 = d1 = d0 =

Sin,3 Sin,2 Sin,1 Sin,0 DinH,7 DinH,6 DinH,5 DinH,4 DinH,3 DinH,2 DinH,1 DinH,0 DinL,7 DinL,6 DinL,5 DinL,4 DinL,3 DinL,2 DinL,1 DinL,0

y=

rego,bito

E 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

s3 × 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

s2 × 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1

s1 × 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

s0 × 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

y 0 d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14

1

1

1

1

1

d15

…, IN40). As the values are defned as shown in Figure 4.76, we can see that the 16-bit output variable OUT will be found as follows: OUTL = Q0 = (248) decimal = (F8) hexadecimal = (1111 1000) binary; OUTH = Q1 = (249) decimal = (F9) hexadecimal = (1111 1001) binary. In rung 3, there are two instances of the “sram_read” macro. The frst “sram_ read” macro is implemented with EN = LOGIC1, in_regH = I1, in_regL = I0, and out_reg = Q2. Likewise, the second “sram_read” macro is implemented with EN = LOGIC1, in_regH = I3, in_regL = I2, and out_reg = Q3. With these two “sram_read” macros, it is possible to observe the contents of the values stored in Bank 0 as shown in Figure 4.76. For example, when I3,I2 = 021h, Q3 will show the contents of the second register of Bank 0 with the address 021h. Likewise, when I1,I0 = 020h, Q2 will show the contents of the frst register of Bank 0 with the address 020h. In this case, we must observe the following: Q3 = ABh, and Q2 = AAh. Note that the data observed are those of the frst 16-bit input variable stored in Bank 0.

Selection Macros

FIGURE 4.50

The macro “mux_16_1_E”.

273

274

FIGURE 4.50

Programmable Logic Controller

Continued

Selection Macros

FIGURE 4.50

4.31.9

275

Continued

EXAMPLE 4.9

Example 4.9 shows the usage of the selection macro “min_N40_16”, together with the macros “fll_sram_N80” (Chapter 3 of the Advanced Concepts volume) and “sram_read” (Chapter 3 of the Advanced Concepts volume). The user program of Example 4.9 is shown in Figure 4.77. The schematic diagram of Example 4.9 is depicted in Figure 4.78. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.9 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “fll_sram_N80” instruction is used with EN = FRSTSCN, IN1 = 020h, N = 80, Value = AAh, Operator = ‘-’, and K = 1. When this instruction is enabled during the frst PLC scan time, it flls 80 consecutive registers of Bank 0 with the values as shown in Figure 4.79. In rung 2, the “min_N40_16” macro is implemented with EN = LOGIC1, IN1L = 0x020, N = 40 (decimal), OUTH = Q1, and OUTL = Q0. As EN = LOGIC1, this macro is always enabled. The macro “min_N40_16” frst identifes the minimum value in forty 16-bit input variables, IN1, IN2, …,

FIGURE 4.51 The fowchart of the macro “mux_16_1_E”.

276 Programmable Logic Controller

277

Selection Macros

TABLE 4.27 Truth Table and Symbol of the Macro “B_mux_2_1_E” Truth Table Inputs E 0 1 1

Output s0 × 0 1

Y U R0 R1

Symbol E (Boolean-enable-input, through W) = 0 or 1 R1 (8-bit source variable, R1) R0 (8-bit source variable, R0) s0 (select input s0, regs0,bits0) = 0 or 1 Y (8-bit destination variable, OUT)

×: don’t care. U: The contents of the destination register Y remain unchanged.

IN40, allocated in Bank 0, in little endian format as shown in Figure 4.79. Then, the contents of the 16-bit input variable holding the minimum value are copied to the 16-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, …, IN40). As the values are defned as shown in Figure 4.79, we can see that the 16-bit output variable OUT will be found as follows: OUTL = Q0 = (92) decimal = (5C) hexadecimal = (0101 1100) binary; OUTH = Q1 = (91) decimal = (5B) hexadecimal = (0101 1011) binary.

FIGURE 4.52

The macro “B_mux_2_1_E”.

278

Programmable Logic Controller

FIGURE 4.53 The fowchart of the macro “B_mux_2_1_E”.

TABLE 4.28 Truth Table and Symbol of the Macro “B_mux_4_1_E” Truth Table Inputs E 0 1 1 1 1

Symbol Output

s1 × 0 0 1 1

s0 × 0 1 0 1

Y U R0 R1 R2 R3

×: don’t care. U: The contents of the destination register Y remain unchanged.

E (Boolean-enable-input, through W) = 0 or 1 R3 (8-bit source variable, R3) R2 (8-bit source variable, R2) R1 (8-bit source variable, R1) R0 (8-bit source variable, R0) s1 (select input s1, regs1,bits1) = 0 or 1 s0 (select input s0, regs0,bits0) = 0 or 1 Y (8-bit destination variable, OUT)

Selection Macros

279

FIGURE 4.54 The macro “B_mux_4_1_E”.

In rung 3, there are two instances of “sram_read” macro. The frst “sram_ read” macro is implemented with EN = LOGIC1, in_regH = I1, in_regL = I0, and out_reg = Q2. Likewise, the second “sram_read” macro is implemented with EN = LOGIC1, in_regH = I3, in_regL = I2, and out_reg = Q3. With these two “sram_read” macros, it is possible to observe the contents of the values stored in Bank 0 as shown in Figure 4.79. For example, when I3,I2 = 021h, Q3 will show the contents of the second register of Bank 0 with the address 021h. Likewise, when I1,I0 = 020h, Q2 will show the contents of the frst register of Bank 0 with the address 020h. In this case, we must observe the following: Q3 = A9h and Q2 = AAh. Note that the data observed are those of the frst 16-bit input variable stored in Bank 0.

4.31.10 EXAMPLE 4.10 Example 4.10 shows the usage of the selection macro “max_N255_16”, together with the macros “fll_sram_N80” (Chapter 3 of the Advanced Concepts volume)

280

Programmable Logic Controller

FIGURE 4.55 The fowchart of the macro “B_mux_4_1_E”.

TABLE 4.29 Truth Table and Symbol of the Macro “B_mux_8_1_E” Truth Table Inputs E 0 1 1 1 1 1 1 1 1

s2 × 0 0 0 0 1 1 1 1

Symbol Output

s1 × 0 0 1 1 0 0 1 1

s0 × 0 1 0 1 0 1 0 1

Y U R0 R1 R2 R3 R4 R5 R6 R7

×: don’t care. U: The contents of the destination register Y remain unchanged.

E (Boolean-enable-input, through W) = 0 or 1 R7 (8-bit source variable, R7) R6 (8-bit source variable, R6) R5 (8-bit source variable, R5) R4 (8-bit source variable, R4) R3 (8-bit source variable, R3) R2 (8-bit source variable, R2) R1 (8-bit source variable, R1) R0 (8-bit source variable, R0) s2 (select input s2, regs2,bits2) = 0 or 1 s1 (select input s1, regs1,bits1) = 0 or 1 s0 (select input s0, regs0,bits0) = 0 or 1 Y (8-bit destination variable, OUT)

Selection Macros

FIGURE 4.56

The macro “B_mux_8_1_E”.

281

282

FIGURE 4.56

Programmable Logic Controller

Continued

and “sram_read” (Chapter 3 of the Advanced Concepts volume). The user program of Example 4.10 is shown in Figure 4.80. The schematic diagram of Example 4.10 is depicted in Figure 4.81. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.10 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “fll_sram_N80” instruction is used with EN = FRSTSCN, IN1 = 020h, N = 255, Value = 1, Operator = ‘+’, and K = 1. When this instruction is enabled during the frst PLC scan time, it flls 255 consecutive registers of Bank 0, Bank 1, Bank 2, and Bank 3 with the values as shown in Figure 4.82. In rung 2, the “max_N255_16” macro is implemented with EN = LOGIC1, IN1L = 0x020, N = 128 (decimal), OUTH = Q1, and OUTL = Q0. As EN = LOGIC1, this macro is always enabled. The macro “max_N255_16” frst identifes the maximum value in one hundred and twenty-eight 16-bit input variables, IN1, IN2, …, IN128, allocated in Bank 0, Bank 1, Bank 2, and Bank 3 in little endian format as shown in Figure 4.82. Then, the contents of the 16-bit input variable holding the maximum value are copied to the 16-bit output variable OUT, i.e., OUT := MAX (IN1, IN2, …, IN128). As the values are defned as shown in Figure 4.82, we can see that the 16-bit output variable OUT will be found as follows: OUTL = Q0 = (253) decimal = (FD) hexadecimal = (1111 1101) binary; OUTH = Q1 = (254) decimal = (FE) hexadecimal = (1111 1110) binary. In rung 3, there are two instances of the “sram_read” macro. The frst “sram_ read” macro is implemented with EN = LOGIC1, in_regH = I1, in_regL = I0, and out_reg = Q2. Likewise, the second “sram_read” macro is

FIGURE 4.57

The fowchart of the macro “B_mux_8_1_E”.

Selection Macros 283

284

Programmable Logic Controller

FIGURE 4.58

The user program of “Example 4.1”.

implemented with EN = LOGIC1, in_regH = I3, in_regL = I2, and out_reg = Q3. With these two “sram_read” macros, it is possible to observe the contents of the values stored in Bank 0 as shown in Figure 4.82. For example, when I3,I2 = 021h, Q3 will show the contents of the second register of Bank 0 with the address 021h. Likewise, when I1,I0 = 020h, Q2 will show the contents of the frst register of Bank 0 with the address 020h. In this case, we must observe the following: Q3 = 2 and Q2 = 1. Note that the data observed are those of the frst 16-bit input variable stored in Bank 0.

4.31.11

EXAMPLE 4.11

Example 4.11 shows the usage of the selection macro “min_N255_16”, together with the macros “fll_sram_N80” (Chapter 3 of the Advanced Concepts volume) and

Selection Macros

FIGURE 4.59

285

The schematic diagram of the user program of “Example 4.1”.

“sram_read” (Chapter 3 of the Advanced Concepts volume). The user program of Example 4.11 is shown in Figure 4.83. The schematic diagram of Example 4.11 is depicted in Figure 4.84. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.11 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

FIGURE 4.60

The user program of “Example 4.2”.

286

Programmable Logic Controller

FIGURE 4.61

The schematic diagram of the user program of “Example 4.2”.

FIGURE 4.62

The user program of “Example 4.3”.

FIGURE 4.63

The schematic diagram of the user program of “Example 4.3”.

FIGURE 4.64 The user program of “Example 4.4”.

Selection Macros

FIGURE 4.65

287

The schematic diagram of the user program of “Example 4.4”.

FIGURE 4.66 The user program of “Example 4.5”.

In rung 1, the “fll_sram_N80” instruction is used with EN = FRSTSCN, IN1 = 020h, N = 255, Value = 255, Operator = ‘-’, and K = 1. When this instruction is enabled during the frst PLC scan time, it flls 255 consecutive registers of Bank 0, Bank 1, Bank 2, and Bank 3 with the values as shown in Figure 4.85. In rung 2, the “min_N255_16” macro is implemented with EN = LOGIC1, IN1L = 0x020, N = 128 (decimal), OUTH = Q1, and OUTL = Q0. As EN

288

Programmable Logic Controller

FIGURE 4.67 The schematic diagram of the user program of “Example 4.5”.

Selection Macros

FIGURE 4.68

Allocation of the SRAM data in Example 4.5.

289

290

Programmable Logic Controller

FIGURE 4.69 The user program of “Example 4.6”.

FIGURE 4.70 The schematic diagram of the user program of “Example 4.6”.

= LOGIC1, this macro is always enabled. The macro “min_N255_16” frst identifes the minimum value in one hundred and twenty-eight 16-bit input variables, IN1, IN2, …, IN128, allocated in Bank 0, Bank 1, Bank 2, and Bank 3 in little endian format as shown in Figure 4.85. Then, the contents of the 16-bit input variable holding the minimum value are copied to the 16-bit output variable OUT, i.e., OUT := MIN (IN1, IN2, …, IN128). As the values are defned as shown in Figure 4.85, we can see that the 16-bit output variable OUT will be found as follows: OUTL = Q0 = (1) decimal = (01) hexadecimal = (0000 0001) binary; OUTH = Q1 = (0) decimal = (00) hexadecimal = (0000 0000) binary.

Selection Macros

291

FIGURE 4.71 The user program of “Example 4.7”.

In rung 3, there are two instances of the “sram_read” macro. The frst “sram_ read” macro is implemented with EN = LOGIC1, in_regH = I1, in_regL = I0, and out_reg = Q2. Likewise, the second “sram_read” macro is implemented with EN = LOGIC1, in_regH = I3, in_regL = I2, and out_reg = Q3. With these two “sram_read” macros, it is possible to observe the contents of the values stored in Bank 0 as shown in Figure 4.85. For example, when I3,I2 = 021h, Q3 will show the contents of the second register of Bank 0 with the address 021h. Likewise, when I1,I0 = 020h, Q2 will show the contents of the frst register of Bank 0 with the address 020h. In this case, we must observe the following: Q3 = 254 (decimal) and Q2 = 255 (decimal). Note that the data observed are those of the frst 16-bit input variable stored in Bank 0.

4.31.12

EXAMPLE 4.12

Example 4.12 shows the usage of the selection macro “limiter”. The user program of Example 4.12 is shown in Figure 4.86. The schematic diagram of Example 4.12 is depicted in Figure 4.87. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.12 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the

292

Programmable Logic Controller

FIGURE 4.72 The schematic diagram of the user program of “Example 4.7”.

PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the “limiter” instruction is used with EN = LOGIC1, MN = 25 (decimal), IN = I0, MX = 125 (decimal), and OUT = Q0. As EN = LOGIC1, this instruction is always enabled. If IN (I0) is less than MN (25), then OUT

Selection Macros

FIGURE 4.73

293

Allocation of the SRAM data in Example 4.7.

(Q0) is equal to MN (25); if IN (I0) is greater than MX (125), then OUT (Q0) is equal to MX (125); if MN (25) ≤ IN (I0) ≤ MX (125), then OUT (Q0) is equal to IN (I0). In rung 2, the “limiter” instruction is used with EN = LOGIC1, MN = 100 (decimal), IN = I1, MX = 200 (decimal), and OUT = Q1. As EN = LOGIC1,

294

Programmable Logic Controller

FIGURE 4.74 The user program of “Example 4.8”.

this instruction is always enabled. If IN (I1) is less than MN (100), then OUT (Q1) is equal to MN (100); if IN (I1) is greater than MX (200), then OUT (Q1) is equal to MX (200); if MN (100) ≤ IN (I1) ≤ MX (200), then OUT (Q1) is equal to IN (I1).

FIGURE 4.75

The schematic diagram of the user program of “Example 4.8”.

Selection Macros

FIGURE 4.76 Allocation of the SRAM data in Example 4.8.

295

296

Programmable Logic Controller

FIGURE 4.77

The user program of “Example 4.9”.

FIGURE 4.78

The schematic diagram of the user program of “Example 4.9”.

4.31.13

EXAMPLE 4.13

Example 4.13 shows the usage of the selection macro “limiter_16”. The user program of Example 4.13 is shown in Figure 4.88. The schematic diagram of Example 4.13 is depicted in Figure 4.89. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you

Selection Macros

FIGURE 4.79

Allocation of the SRAM data in Example 4.9.

297

298

FIGURE 4.80

Programmable Logic Controller

The user program of “Example 4.10”.

FIGURE 4.81 The schematic diagram of the user program of “Example 4.10”.

uncomment Example 4.13 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

Selection Macros

FIGURE 4.82

Allocation of the SRAM data in Example 4.10.

299

300

FIGURE 4.83

Programmable Logic Controller

The user program of “Example 4.11”.

FIGURE 4.84 The schematic diagram of the user program of “Example 4.11”.

In rung 1, the “limiter_16” instruction is used with EN = LOGIC1, MN = 5000 (decimal), INH = I1, INL = I0, MX = 10000 (decimal), OUTH = Q1, and OUTL = Q0. As EN = LOGIC1, this instruction is always enabled. If IN (I1,I0) is less than MN (5000), then OUT (Q1,Q0) is equal to MN (5000); if IN (I1,I0) is greater than MX (10000), then OUT (Q1,Q0) is equal to MX (10000); if MN (5000) ≤ IN (I1,I0) ≤ MX (10000), then OUT (Q1,Q0) is equal to IN (I1,I0). In rung 2, the “limiter_16” instruction is used with EN = LOGIC1, MN = 25000 (decimal), INH = I3, INL = I2, MX = 50000 (decimal), OUTH =

Selection Macros

FIGURE 4.85 Allocation of the SRAM data in Example 4.11.

301

302

Programmable Logic Controller

FIGURE 4.86

The user program of “Example 4.12”.

FIGURE 4.87

The schematic diagram of the user program of “Example 4.12”.

FIGURE 4.88 The user program of “Example 4.13”.

Selection Macros

FIGURE 4.89

303

The schematic diagram of the user program of “Example 4.13”.

Q3, and OUTL = Q2. As EN = LOGIC1, this instruction is always enabled. If IN (I3,I2) is less than MN (25000), then OUT (Q3,Q2) is equal to MN (25000); if IN (I3,I2) is greater than MX (50000), then OUT (Q3,Q2) is equal to MX (50000); if MN (25000) ≤ IN (I3,I2) ≤ MX (50000), then OUT (Q3,Q2) is equal to IN (I3,I2).

4.31.14 EXAMPLE 4.14 Example 4.14 shows the usage of the selection macros “mux_2_1” and “mux_2_1_E”. The user program of Example 4.14 is shown in Figure 4.90. The schematic diagram of Example 4.14 is depicted in Figure 4.91. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 4.14 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the multiplexer macro “mux_2_1” (2×1 multiplexer) is used. In this multiplexer, input signals are d0 = I0.0 and d1 = I0.1, the output is y = Q0.0, and the select input is s0 = I0.2. In rung 2, the multiplexer macro “mux_2_1” (2×1 multiplexer) is used. In this multiplexer, input signals are d0 = I0.4 and d1 = I0.5, the output is y = Q0.3, and the select input is s0 = I0.6. In rung 3, the multiplexer macro “mux_2_1” (2×1 multiplexer) is used. In this multiplexer, input signals are d0 = I1.0 and d1 = I1.1, the output is y = Q1.0, and the select input is s0 = I1.2.

304

Programmable Logic Controller

FIGURE 4.90 The user program of “Example 4.14”.

In rung 4, the multiplexer macro “mux_2_1” (2×1 multiplexer) is used. In this multiplexer, input signals are d0 = T_100ms and d1 = T_1s, the output is y = Q1.3, and the select input is s0 = I1.6. In rung 5, the macro “mux_2_1_E” (2×1 multiplexer with active-high enable input) is used. In this multiplexer, input signals are d0 = I2.0 and d1 = I2.1, the output is y = Q2.0, and the select input is s0 = I2.2. In addition, the active-high enable input E is defned to be E = I2.3. In rung 6, the macro “mux_2_1_E” (2×1 multiplexer with active-high enable input) is used. In this multiplexer, input signals are d0 = I2.4 and d1 = I2.5, the output is y = Q2.3, and the select input is s0 = I2.6. In addition, the enable input E is defned to be E = I2.7. In rung 7, the macro “mux_2_1_E” (2×1 multiplexer with active-high enable input) is used. In this multiplexer, input signals are d0 = I3.0 and d1 = I3.1,

Selection Macros

FIGURE 4.91

The schematic diagram of the user program of “Example 4.14”.

305

306

Programmable Logic Controller

the output is y = Q3.0, and the select input is s0 = I3.2. In addition, the active-high enable input E is defned to be E = I3.3. In rung 8, the macro “mux_2_1_E” (2×1 multiplexer with active-high enable input) is used. In this multiplexer, input signals are d0 = T_100ms and d1 = T_1s, the output is y = Q3.3, and the select input is s0 = I3.6. In addition, the active-high enable input E is defned to be E = I3.7.

4.31.15 EXAMPLE 4.15 Example 4.15 shows the usage of the selection macros “mux_4_1” and “mux_4_1_E”. The user program of Example 4.15 is shown in Figure 4.92. The schematic diagram of Example 4.15 is depicted in Figure 4.93. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 4.15 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the multiplexer macro “mux_4_1” (4×1 multiplexer) is used. In this multiplexer, input signals are d3 = I0.3, d2 = I0.2, d1 = I0.1, and d0 = I0.0, the output is y = Q0.0, and the select inputs are s1 = I0.5 and s0 = I0.4. In rung 2, the multiplexer macro “mux_4_1” (4×1 multiplexer) is used. In this multiplexer, input signals are d3 = I1.3, d2 = I1.2, d1 = I1.1, and d0 = I1.0, the output is y = Q1.0, and the select inputs are s1 = I1.5 and s0 = I1.4.

FIGURE 4.92 The user program of “Example 4.15”.

Selection Macros

FIGURE 4.93

307

The schematic diagram of the user program of “Example 4.15”.

In rung 3, the macro “mux_4_1_E” (4×1 multiplexer with active-high enable input) is used. In this multiplexer, input signals are d3 = I2.3, d2 = I2.2, d1 = I2.1, and d0 = I2.0, the output is y = Q2.0, and the select inputs are s1 = I2.5 and s0 = I2.4. In addition, the active-high enable input E is defned to be E = I2.6.

308

Programmable Logic Controller

In rung 4, the macro “mux_4_1_E” (4×1 multiplexer with active-high enable input) is used. In this multiplexer, input signals are d3 = I3.3, d2 = I3.2, d1 = T_1s, and d0 = T_100ms, the output is y = Q3.0, and the select inputs are s1 = I3.5 and s0 = I3.4. In addition, the enable input E is defned to be E = I3.6.

4.31.16

EXAMPLE 4.16

Example 4.16 shows the usage of the selection macro “mux_8_1”. The user program of Example 4.16 is shown in Figure 4.94. The schematic diagram of Example 4.16 is depicted in Figure 4.95. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.16 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the multiplexer macro “mux_8_1” (8×1 multiplexer) is used. In this multiplexer, input signals are d7 = I0.7, d6 = I0.6, d5 = I0.5, d4 = I0.4, d3 = I0.3, d2 = I0.2, d1 = I0.1, and d0 = I0.0, the output is y = Q0.0, and the select inputs are s2 = I1.2, s1 = I1.1, and s0 = I1.0. In rung 2, the multiplexer macro “mux_8_1” (8×1 multiplexer) is used. In this multiplexer, input signals are d7 = I2.7, d6 = I2.6, d5 = I2.5, d4 = I2.4, d3 = I2.3, d2 = I2.2, d1 = T_1s, and d0 = T_100ms, the output is y = Q2.0, and the select inputs are s2 = I3.2, s1 = I3.1, and s0 = I3.0.

4.31.17

EXAMPLE 4.17

Example 4.17 shows the usage of the selection macro “mux_8_1_E”. The user program of Example 4.17 is shown in Figure 4.96. The schematic diagram of Example 4.17 is depicted in Figure 4.97. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”,

FIGURE 4.94 The user program of “Example 4.16”.

Selection Macros

309

FIGURE 4.95 The schematic diagram of the user program of “Example 4.16”.

if you uncomment Example 4.17 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the multiplexer macro “mux_8_1_E” (8×1 multiplexer with activehigh enable input) is used. In this multiplexer, input signals are d7 = I0.7, d6 = I0.6, d5 = I0.5, d4 = I0.4, d3 = I0.3, d2 = I0.2, d1 = I0.1, and d0 = I0.0, the

310

Programmable Logic Controller

FIGURE 4.96 The user program of “Example 4.17”.

output is y = Q0.0, and the select inputs are s2 = I1.2, s1 = I1.1, and s0 = I1.0. In addition, the active-high enable input E is defned to be E = I1.3. In rung 2, the multiplexer macro “mux_8_1_E” (8×1 multiplexer with activehigh enable input) is used. In this multiplexer, input signals are d7 = I2.7, d6 = I2.6, d5 = I2.5, d4 = I2.4, d3 = I2.3, d2 = I2.2, d1 = T_1s, and d0 = T_100ms, the output is y = Q2.0, and the select inputs are s2 = I3.2, s1 = I3.1, and s0 = I3.0. In addition, the enable input E is defned to be E = I3.3.

4.31.18

EXAMPLE 4.18

Example 4.18 shows the usage of the selection macro “mux_16_1”. The user program of Example 4.18 is shown in Figure 4.98. The schematic diagram of Example 4.18 is depicted in Figure 4.99. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 4.18 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the multiplexer macro “mux_16_1” (16×1 multiplexer) is used. In this multiplexer, input signals are d15 = I1.7, d14 = I1.6, d13 = I1.5, d12 = I1.4, d11 = I1.3, d10 = I1.2, d9 = I1.1, d8 = I1.0, d7 = I0.7, d6 = I0.6, d5 = I0.5, d4 = I0.4, d3 = I0.3, d2 = I0.2, d1 = I0.1, and d0 = I0.0, the output is y = Q0.0, and the select inputs are s3 = I2.3, s2 = I2.2, s1 = I2.1, and s0 = I2.0.

4.31.19 EXAMPLE 4.19 Example 4.19 shows the usage of the selection macro “mux_16_1_E”. The user program of Example 4.19 is shown in Figure 4.100. The schematic diagram of Example 4.19 is depicted in Figure 4.101. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847

Selection Macros

311

FIGURE 4.97 The schematic diagram of the user program of “Example 4.17”.

_user_Int.inc”, if you uncomment Example 4.19 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

312

Programmable Logic Controller

FIGURE 4.98 The user program of “Example 4.18”.

FIGURE 4.99

The schematic diagram of the user program of “Example 4.18”.

Selection Macros

313

FIGURE 4.100 The user program of “Example 4.19”.

In rung 1, the multiplexer macro “mux_16_1_E” (16×1 multiplexer with activehigh enable input) is used. In this multiplexer, input signals are d15 = I1.7, d14 = I1.6, d13 = I1.5, d12 = I1.4, d11 = I1.3, d10 = I1.2, d9 = I1.1, d8 = I1.0, d7 = I0.7, d6 = I0.6, d5 = I0.5, d4 = I0.4, d3 = I0.3, d2 = I0.2, d1 = I0.1, and d0 = I0.0, the output is y = Q0.0, and the select inputs are s3 = I2.3, s2 = I2.2, s1 = I2.1, and s0 = I2.0. In addition, the active-high enable input E is defned to be E = I2.4.

4.31.20 EXAMPLE 4.20 Example 4.20 shows the usage of the selection macro “B_mux_2_1_E”. The user program of Example 4.20 is shown in Figure 4.102. The schematic diagram of Example 4.20 is depicted in Figure 4.103. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847 _user_Int.inc”, if you uncomment Example 4.20 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, as EN = FRSTSCN, during the frst PLC scan time, by using four “load_R” functions, the following load operations are carried out: the constant value 0Fh is loaded into the output register M0, the constant value F0h is loaded into the output register M40, the constant value FFh is loaded into the output register M80, and the constant value 3Ch is loaded into the output register M120. In rung 2, the byte multiplexer macro “B_mux_2_1_E” (2×1 Byte Multiplexer with active-high enable input) is used. In this byte multiplexer, input variables are R1 = I1 and R0 = I2, the output variable is Y = Q1, and the select input is s0 = I0.0. In addition, the active-high enable input E is defned to be E = I0.1. In rung 3, the byte multiplexer macro “B_mux_2_1_E” (2×1 Byte Multiplexer with active-high enable input) is used. In this Byte multiplexer, input

314

Programmable Logic Controller

FIGURE 4.101 The schematic diagram of the user program of “Example 4.19”.

variables are R1 = M0 and R0 = M120, the output variable is Y = Q2, and the select input is s0 = I0.2. In addition, the active-high enable input E is defned to be E = I0.3. In rung 4, the byte multiplexer macro “B_mux_2_1_E” (2×1 Byte Multiplexer with active-high enable input) is used. In this byte multiplexer, input variables are R1 = M40 and R0 = M80, the output variable is Y = Q3, and the

Selection Macros

FIGURE 4.102

The user program of “Example 4.20”.

FIGURE 4.103

The schematic diagram of the user program of “Example 4.20”.

315

316

Programmable Logic Controller

select input is s0 = I0.4. In addition, the active-high enable input E is defned to be E = I0.5.

4.31.21

EXAMPLE 4.21

Example 4.21 shows the usage of the selection macro “B_mux_4_1_E”. The user program of Example 4.21 is shown in Figure 4.104. The schematic diagram of Example 4.21 is depicted in Figure 4.105. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int .inc”, if you uncomment Example 4.21 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, as EN = FRSTSCN, during the frst PLC scan time, by using fve “load_R” functions, the following load operations are carried out: the constant value 0Fh is loaded into the output register M0, the constant value F0h is loaded into the output register M1, the constant value FFh is loaded into the output register M2, the constant value 3Ch is loaded into the output register M3, and the constant value C3h is loaded into the output register M4. In rung 2, the byte multiplexer macro “B_mux_4_1_E” (4×1 Byte Multiplexer with active-high enable input) is used. In this byte multiplexer, input variables are R3 = M3, R2 = M2, R1 = M1, and R0 = M0, the output variable is Y = Q0, and the select inputs are s1 = I0.1 and s0 = I0.0. In addition, the active-high enable input E is defned to be E = I0.2.

FIGURE 4.104

The user program of “Example 4.21”.

Selection Macros

317

FIGURE 4.105 The schematic diagram of the user program of “Example 4.21”.

In rung 3, the byte multiplexer macro “B_mux_4_1_E” (4×1 Byte Multiplexer with active-high enable input) is used. In this byte multiplexer, input variables are R3 = M4, R2 = I3, R1 = I2, and R0 = I1, the output variable is Y = Q3, and the select inputs are s1 = I0.4 and s0 = I0.3. In addition, the activehigh enable input E is defned to be E = I0.5.

318

4.31.22

Programmable Logic Controller

EXAMPLE 4.22

Example 4.22 shows the usage of the selection macro “B_mux_8_1_E”. The user program of Example 4.22 is shown in Figure 4.106. The schematic diagram of Example 4.22 is depicted in Figure 4.107. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 4.22 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, as EN = FRSTSCN, during the frst PLC scan time, by using eight “load_R” functions, the following load operations are carried out: the constant value 03h is loaded into the output register M0, the constant value 06h is loaded into the output register M1, the constant value 30h is loaded into the output register M2, the constant value 60h is loaded into the output register M3, the constant value 0Fh is loaded into the output register M4, the constant value F0h is loaded into the output register M5, the constant value C3h is loaded into the output register M6, and the constant value FFh is loaded into the output register M7. In rung 2, the byte multiplexer macro “B_mux_8_1_E” (8×1 Byte Multiplexer with active-high enable input) is used. In this byte multiplexer, input variables are R7 = M7, R6 = M6, R5 = M5, R4 = M4, R3 = M3, R2 = M2, R1 = M1, and R0 = M0, the output variable is Y = Q0, and the select inputs are s2 = I0.2, s1 = I0.1, and s0 = I0.0. In addition, the active-high enable input E is defned to be E = I0.3.

FIGURE 4.106

The user program of “Example 4.22”.

Selection Macros

FIGURE 4.107 The schematic diagram of the user program of “Example 4.22”.

319

5

Demultiplexer Macros

INTRODUCTION A demultiplexer, abbreviated DMUX, is used when a circuit is to send a signal to one of many devices. This description sounds similar to the description given for a decoder, but a decoder is used to select among many devices, whereas a demultiplexer is used to send a signal among many devices. However, any decoder having an enable line can function as a demultiplexer. If the enable line of a decoder is used as a data input, then the data can be routed to any one of the outputs, and, thus, in that case, the decoder can be used as a demultiplexer. As the name implies, a demultiplexer performs the opposite function to that of a multiplexer. A single input signal can be connected to any one of the output lines provided by the choice of an appropriate select signal. The general form of a 1-to-n demultiplexer can be seen in Figure 5.1. If there are “m” select inputs, then the number of output lines to which the data can be routed is n = 2m. Although, not shown in Figure 5.1, in addition to the other inputs, the demultiplexer may have an enable line, E, for enabling it. When the demultiplexer is disabled with E set to 0 (for active-high enable input E), no output line is selected, and, therefore, the input signal is not passed to any output line. In this chapter, the following demultiplexer macros are described for the PIC16F1847-Based PLC: Dmux_1_2 (1×2 DMUX), Dmux_1_2_E (1×2 DMUX with Enable Input), Dmux_1_4 (1×4 DMUX), Dmux_1_4_E (1×4 DMUX with Enable Input), Dmux_1_8 (1×8 DMUX), Dmux_1_8_E (1×8 DMUX with Enable Input), Dmux_1_16 (1×16 DMUX), Dmux_1_16_E (1×16 DMUX with Enable Input), B_Dmux_1_2_E (1×2 Byte DeMultiplexer with Enable Input), B_Dmux_1_4_E (1×4 Byte DeMultiplexer with Enable Input), B_Dmux_1_8_E (1×8 Byte DeMultiplexer with Enable Input), Dispatcher_1_8_E (1×8 Dispatcher with Enable Input), Patcher_8_1_E (8×1 Patcher with Enable Input). The fle “PICPLC_PIC16F1847_macros_Int.inc”, which is downloadable from this book’s webpage under the downloads section, contains macros defned for the PIC16F1847-Based PLC explained in this volume (Intermediate Concepts). Let us now consider the demultiplexer macros in detail.

321

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Programmable Logic Controller

FIGURE 5.1 The general form of a 1-to-n demultiplexer, where n = 2m.

5.1 MACRO “DMUX_1_2” (1×2 DMUX) The truth table and the symbol of the macro “Dmux_1_2” are depicted in Table 5.1. Figures 5.2 and 5.3 show the macro “Dmux_1_2” and its fowchart, respectively. In this macro, the select input s0, output signals “y0” and “y1”, and the input signal i are all Boolean variables. When the select input s0 = 0, the input signal “i” is passed to the output line “y0”. When the select input s0 = 1, the input signal “i” is passed to the output line “y1”. Assumption: The operands “regi,biti”, “regs0,bits0”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

5.2 MACRO “DMUX_1_2_E” (1×2 DMUX WITH ENABLE INPUT) The truth table and the symbol of the macro “Dmux_1_2_E” are depicted in Table 5.2. Figures 5.4 and 5.5 show the macro “Dmux_1_2_E” and its fowchart, respectively. In this macro, the active-high enable input E, the select input s0, output signals TABLE 5.1 Truth Table and Symbol of the Macro “Dmux_1_2” Truth Table

Symbol

Input

Outputs

i=

regi,biti

s0 0

y0 i

y1 0

s0 = y1 =

regs0,bits0 rego1,bito1

1

0

i

y0 =

rego0,bito0

Demultiplexer Macros

323

FIGURE 5.2 The macro “Dmux_1_2”.

“y0” and “y1”, and the input signal i are all Boolean variables. When this demultiplexer is disabled, with E set to 0, no output line is selected, and the input signal is not passed to any output. When this demultiplexer is enabled, with E set to 1, it functions as described for “Dmux_1_2”. This means that, when E = 1: if the select input s0 = 0, then the input signal “i” is passed to the output line “y0”. When E = 1: if the select input s0 = 1, then the input signal “i” is passed to the output line “y1”. Assumption: The operands “regi,biti”, “regs0,bits0”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

5.3

MACRO “DMUX_1_4” (1×4 DMUX)

The truth table and the symbol of the macro “Dmux_1_4” are depicted in Table 5.3. Figures 5.6 and 5.7 show the macro “Dmux_1_4” and its fowchart, respectively. In this macro, select inputs s1, s0, output signals “y0”, “y1”, “y2”, and “y3”, and the input signal i are all Boolean variables. When the select inputs are s1s0 = 00 (respectively, 01, 10, 11), the input signal “i” is passed to the output line “y0” (respectively, y1, y2, y3). Assumption: The operands “regi,biti”, “regs1,bits1”, “regs0,bits0”, “rego3,bito3”, “rego2,bito2”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

5.4

MACRO “DMUX_1_4_E” (1×4 DMUX WITH ENABLE INPUT)

The truth table and the symbol of the macro “Dmux_1_4_E” are depicted in Table 5.4. Figures 5.8 and 5.9 show the macro “Dmux_1_4_E” and its fowchart,

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Programmable Logic Controller

FIGURE 5.3 The fowchart of the macro “Dmux_1_2”.

TABLE 5.2 Truth Table and Symbol of the Macro “Dmux_1_2_E” Truth Table Inputs E 0 1 1

Symbol

Outputs s0 × 0 1

y0 0 i 0

y1 0 0 i

E

W

i= s0 = y1 = y0 =

regi,biti regs0,bits0 rego1,bito1 rego0,bito0

×: don’t care.

respectively. In this macro, the active-high enable input E, select inputs s1, s0, output signals “y0”, “y1”, “y2”, and “y3”, and the input signal i are all Boolean variables. When this demultiplexer is disabled, with E set to 0, no output line is selected, and the input signal is not passed to any output. When this demultiplexer is enabled, with E set to 1, it functions as described for “Dmux_1_4”. This means that, when E = 1: if the select inputs are s1s0 = 00 (respectively, 01, 10, 11), the input signal “i” is passed to the output line “y0” (respectively, y1, y2, y3). Assumption: The operands “regi,biti”, “regs1,bits1”, “regs0,bits0”, “rego3,bito3”, “rego2,bito2”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

Demultiplexer Macros

325

FIGURE 5.4 The macro “Dmux_1_2_E”.

5.5 MACRO “DMUX_1_8” (1×8 DMUX) The truth table and the symbol of the macro “Dmux_1_8” are depicted in Table 5.5. Figures 5.10 and 5.11 show the macro “Dmux_1_8” and its fowchart, respectively. In this macro, select inputs s2, s1, s0, output signals “y0”, “y1”, “y2”, “y3”, “y4”, “y5”, “y6”, and “y7”, and the input signal i are all Boolean variables. When the select inputs are s2s1s0 = 000 (respectively, 001, 010, 011, 100, 101, 110, 111), the input signal “i” is passed to the output line “y0” (respectively, y1, y2, y3, y4, y5, y6, y7). Assumption: The operands “regi,biti”, “regs2,bits2”, “regs1,bits1”, “regs0,bits0”, “rego7,bito7”, “rego6,bito6”, “rego5,bito5”, “rego4,bito4”, “rego3,bito3”, “rego2,bito2”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

5.6 MACRO “DMUX_1_8_E” (1×8 DMUX WITH ENABLE INPUT) The truth table and the symbol of the macro “Dmux_1_8_E” are depicted in Table 5.6. Figures 5.12 and 5.13 show the macro “Dmux_1_8_E” and its fowchart, respectively. In this macro, the active-high enable input E, select inputs s2, s1, s0, output signals “y0”, “y1”, “y2”, “y3”, “y4”, “y5”, “y6”, and “y7”, and the input signal i are all Boolean variables. When this demultiplexer is disabled, with E set to 0, no output line is selected, and the input signal is not passed to any output. When this demultiplexer is enabled, with E set to 1, it functions as described for

326

Programmable Logic Controller

FIGURE 5.5 The fowchart of the macro “Dmux_1_2_E”.

TABLE 5.3 Truth Table and Symbol of the Macro “Dmux_1_4” Truth Table Inputs s1 0 0 1 1

Symbol

Outputs s0 0 1 0 1

y0 i 0 0 0

y1 0 i 0 0

y2 0 0 i 0

y3 0 0 0 i

i=

regi,biti

s1 = s0 = y3 = y2 = y1 =

regs1,bits1 regs0,bits0 rego3,bito3 rego2,bito2 rego1,bito1

y0 =

rego0,bito0

Demultiplexer Macros

FIGURE 5.6 The macro “Dmux_1_4”.

327

328

Programmable Logic Controller

FIGURE 5.7 The fowchart of the macro “Dmux_1_4”.

TABLE 5.4 Truth Table and Symbol of the Macro “Dmux_1_4_E” Truth Table Inputs E 0 1 1 1 1

s1 × 0 0 1 1

Symbol

Outputs s0 × 0 1 0 1

×: don’t care.

y0 0 I 0 0 0

y1 0 0 i 0 0

y2 0 0 0 i 0

y3 0 0 0 0 i

E

W

i= s1 = s0 = y3 = y2 = y1 =

regi,biti regs1,bits1 regs0,bits0 rego3,bito3 rego2,bito2 rego1,bito1

y0 =

rego0,bito0

“Dmux_1_8”. This means that, when E = 1: if the select inputs are s2s1s0 = 000 (respectively, 001, 010, 011, 100, 101, 110, 111), the input signal “i” is passed to the output line “y0” (respectively, y1, y2, y3, y4, y5, y6, y7). Assumption: The operands “regi,biti”, “regs2,bits2”, “regs1,bits1”, “regs0,bits0”, “rego7,bito7”, “rego6,bito6”, “rego5,bito5”, “rego4,bito4”, “rego3,bito3”, “rego2,bito2”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

Demultiplexer Macros

FIGURE 5.8 The macro “Dmux_1_4_E”.

329

330

Programmable Logic Controller

FIGURE 5.9 The fowchart of the macro “Dmux_1_4_E”.

5.7 MACRO “DMUX_1_16” (1×16 DMUX) The symbol and the truth table of the macro “Dmux_1_16” are depicted in Tables 5.7 and 5.8, respectively. Figures 5.14 and 5.15 show the macro “Dmux_1_16” and its fowchart, respectively. In this macro, select inputs s3, s2, s1, s0, output signals “y0”, “y1”, “y2”, “y3”, “y4”, “y5”, “y6”, “y7”, “y8”, “y9”, “y10”, “y11”, “y12”, “y13”, “y14”, and “y15”, and the input signal i are all Boolean variables. When the select inputs are s3s2s1s0 = 0000 (respectively, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111), the input signal “i” is passed to the output line “y0” (respectively, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15). Assumption: The operands “regi,biti”, “Sin”, “outH”, and “outL” can be in any Bank.

5.8 MACRO “DMUX_1_16_E” (1×16 DMUX WITH ENABLE INPUT) The symbol and the truth table of the macro “Dmux_1_16_E” are depicted in Tables 5.9 and 5.10, respectively. Figures 5.16 and 5.17 show the macro “Dmux_1_16_E” and its fowchart, respectively. In this macro, the active-high enable input E, select inputs s3, s2, s1, s0, output signals “y0”, “y1”, “y2”, “y3”, “y4”, “y5”, “y6”, “y7”, “y8”, “y9”,

331

Demultiplexer Macros

TABLE 5.5 Truth Table and Symbol of the Macro “Dmux_1_8” Truth Table Inputs s2 0 0 0 0 1 1 1 1 Symbol

s1 0 0 1 1 0 0 1 1

s0 0 1 0 1 0 1 0 1

Outputs y0 i 0 0 0 0 0 0 0

y1 0 i 0 0 0 0 0 0

y2 0 0 i 0 0 0 0 0

y3 0 0 0 i 0 0 0 0

y4 0 0 0 0 i 0 0 0

y5 0 0 0 0 0 i 0 0

y6 0 0 0 0 0 0 i 0

y7 0 0 0 0 0 0 0 i

i = regi,biti s2 = regs2,bits2 s1 = regs1,bits1 s0 = regs0,bits0 y7 = rego7,bito7 y6 = rego6,bito6 y5 = rego5,bito5 y4 = rego4,bito4 y3 = rego3,bito3 y2 = rego2,bito2 y1 = rego1,bito1 y0 = rego0,bito0

“y10”, “y11”, “y12”, “y13”, “y14”, and “y15”, and the input signal i are all Boolean variables. When this demultiplexer is disabled, with E set to 0, no output line is selected, and the input signal is not passed to any output. When this demultiplexer is enabled, with E set to 1, it functions as described for “Dmux_1_16”. This means that, when E = 1: if the select inputs are s3s2s1s0 = 0000 (respectively, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111), the input signal “i” is passed to the output line “y0” (respectively, y1, y2, y3, y4, y5, y6, y7, y8, y9, y10, y11, y12, y13, y14, y15). Assumption: The operands “regi,biti”, “Sin”, “outH”, and “outL” can be in any Bank.

5.9 MACRO “B_DMUX_1_2_E” (1×2 BYTE DEMULTIPLEXER WITH ENABLE INPUT) The truth table and the symbol of the macro “B_Dmux_1_2_E” are depicted in Table 5.11. Figures 5.18 and 5.19 show the macro “B_Dmux_1_2_E” and its fowchart, respectively. In this macro, the active-high enable input E and the select input s0 are Boolean variables. I (IN) is an 8-bit source variable, and Y1 (OUT1) and Y0 (OUT0) are 8-bit destination variables. When this byte demultiplexer is disabled,

332

FIGURE 5.10

Programmable Logic Controller

The macro “Dmux_1_8”.

Demultiplexer Macros

FIGURE 5.10

333

Continued

with E set to 0, no 8-bit destination variable is selected to receive the input data from the 8-bit source variable. Therefore, the contents of the outputs Y1 and Y0 (the destination variables OUT1 and OUT0) remain unchanged. When this byte demultiplexer is enabled, with E set to 1: if the select input is s0 = 0, then the input data from the 8-bit source variable I (IN) are passed to the 8-bit destination variable Y0 (OUT0).

334

FIGURE 5.10

Programmable Logic Controller

Continued

When E = 1: if the select input is s0 = 1, then the input data from the 8-bit source variable I (IN) are passed to the 8-bit destination variable Y1 (OUT1). Assumption: The operands “regs0,bits0”, “IN”, “OUT1”, and “OUT0” can be in any Bank.

5.10 MACRO “B_DMUX_1_4_E” (1×4 BYTE DEMULTIPLEXER WITH ENABLE INPUT) The truth table and the symbol of the macro “B_Dmux_1_4_E” are depicted in Table 5.12. Figures 5.20 and 5.21 show the macro “B_Dmux_1_4_E” and its fowchart, respectively. In this macro, the active-high enable input E and select inputs s1, s0 are Boolean variables. I (IN) is an 8-bit source variable, and Y3 (OUT3), Y2 (OUT2), Y1 (OUT1), and Y0 (OUT0) are 8-bit destination variables. When this byte demultiplexer is disabled, with E set to 0, no 8-bit destination variable is selected to receive the input data from the 8-bit source variable. Therefore, the contents of the outputs Y3, Y2, Y1, and Y0 (the destination variables OUT3, OUT2, OUT1, and OUT0) remain unchanged. When this byte demultiplexer is enabled, with E set to 1: if the select inputs are s1s0 = 00 (respectively, 01, 10, 11), then the input data from the 8-bit source variable I (IN) are passed to the 8-bit destination variable Y0 (OUT0; respectively, Y1 (OUT1), Y2 (OUT2), Y3 (OUT3)). Assumption: The operands “regs1,bits1”, “regs0,bits0”, “IN”, “OUT3”, “OUT2”, “OUT1”, and “OUT0” can be in any Bank.

FIGURE 5.11 The fowchart of the macro “Dmux_1_8”.

Demultiplexer Macros 335

336

Programmable Logic Controller

TABLE 5.6 Truth Table and Symbol of the Macro “Dmux_1_8_E” Truth Table Inputs E s2 s1 0 × × 1 0 0 1 0 0 1 0 1 1 0 1 1 1 0 1 1 0 1 1 1 1 1 1 ×: don’t care. Symbol

s0 × 0 1 0 1 0 1 0 1

Outputs y0 y1 0 0 i 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0

y2 0 0 0 i 0 0 0 0 0

y3 0 0 0 0 i 0 0 0 0

y4 0 0 0 0 0 i 0 0 0

E i= s2 = s1 = s0 = y7 = y6 = y5 = y4 = y3 = y2 = y1 =

y5 0 0 0 0 0 0 i 0 0

y6 0 0 0 0 0 0 0 i 0

y7 0 0 0 0 0 0 0 0 i

W regi,biti regs2,bits2 regs1,bits1 regs0,bits0 rego7,bito7 rego6,bito6 rego5,bito5 rego4,bito4 rego3,bito3 rego2,bito2 rego1,bito1

y0 = rego0,bito0

5.11

MACRO “B_DMUX_1_8_E” (1×8 BYTE DEMULTIPLEXER WITH ENABLE INPUT)

The truth table and the symbol of the macro “B_Dmux_1_8_E” are depicted in Table 5.13. Figures 5.22 and 5.23 show the macro “B_Dmux_1_8_E” and its fowchart, respectively. In this macro, the active-high enable input E and select inputs s2, s1, s0 are Boolean variables. I (IN) is an 8-bit source variable, and Y7 (OUT7), Y6 (OUT6), Y5 (OUT4), Y4 (OUT4), Y3 (OUT3), Y2 (OUT2), Y1 (OUT1), and Y0 (OUT0) are 8-bit destination variables. When this byte demultiplexer is disabled, with E set to 0, no 8-bit destination variable is selected to receive the input data from the 8-bit source variable. Therefore, the contents of the outputs Y7, Y6, Y5, Y4, Y3, Y2, Y1, and Y0 (the destination variables OUT7, OUT6, OUT5, OUT4, OUT3, OUT2, OUT1, and OUT0) remain unchanged. When this byte demultiplexer is enabled, with E set to 1: if the select inputs are s2s1s0 = 000 (respectively, 001, 010, 011, 100, 101, 110, 111), then the input data from the 8-bit source

Demultiplexer Macros

337

FIGURE 5.12 The macro “Dmux_1_8_E”.

variable I (IN) are passed to the 8-bit destination variable Y0 (OUT0; respectively, Y1 (OUT1), Y2 (OUT2), Y3 (OUT3), Y4 (OUT4), Y5 (OUT5), Y6 (OUT6), Y7 (OUT7)). Assumption: The operands “regs2,bits2”, “regs1,bits1”, “regs0,bits0”, “IN”, “OUT7”, “OUT6”, “OUT5”, “OUT4”, “OUT3”, “OUT2”, “OUT1”, and “OUT0” can be in any Bank.

338

FIGURE 5.12 Continued

Programmable Logic Controller

Demultiplexer Macros

339

FIGURE 5.12 Continued

5.12 MACRO “DISPATCHER_1_8_E” (1×8 DISPATCHER WITH ENABLE INPUT) The truth table and the symbol of the macro “Dispatcher_1_8_E” are depicted in Tables 5.14 and 5.15, respectively. Figures 5.24 and 5.25 show the macro “Dispatcher_1_8_E” and its fowchart, respectively. In this macro, the active-high enable input E and all eight outputs, O,7, O,6, O,5, O,4, O,3, O,2, O,1, O,0, are Boolean variables. R represents an 8-bit input variable. When this dispatcher is disabled, with E set to 0, all Boolean-output-variables (O,7, O,6, O,5, O,4, O,3, O,2, O,1, O,0) remain unchanged. When this dispatcher is enabled, with E set to 1, eight bits of the input variable R are dispatched into eight individual Boolean outputs as follows: O,7 := R,7, O,6 := R,6, O,5 := R,5, O,4 := R,4, O,3 := R,3, O,2 := R,2, O,1 := R,1, O,0 := R,0. Assumption: The operands “R”, “rego7,bito7”, “rego6,bito6”, “rego5,bito5”, “rego4,bito4”, “rego3,bito3”, “rego2,bito2”, “rego1,bito1”, and “rego0,bito0” can be in any Bank.

FIGURE 5.13 The fowchart of the macro “Dmux_1_8_E”.

340 Programmable Logic Controller

341

Demultiplexer Macros

TABLE 5.7 Symbol of the Macro “Dmux_1_16” Symbol i = regi,biti s3 = Sin,3 s2 = Sin,2 s1 = Sin,1 s0 = Sin,0 y15 = outH,7 y14 = outH,6 y13 = outH,5 y12 = outH,4 y11 = outH,3 y10 = outH,2 y9 = outH,1 y8 = outH,0 y7 = outL,7 y6 = outL,6 y5 = outL,5 y4 = outL,4 y3 = outL,3 y2 = outL,2 y1 = outL,1 y0 = outL,0

5.13 MACRO “PATCHER_8_1_E” (8×1 PATCHER WITH ENABLE INPUT) The truth table and the symbol of the macro “Patcher_8_1_E” are depicted in Tables 5.16 and 5.17, respectively. Figures 5.26 and 5.27 show the macro “Patcher_8_1_E” and its fowchart, respectively. In this macro, the active-high enable input E and all eight inputs, I,7, I,6, I,5, I,4, I,3, I,2, I,1, I,0, are Boolean variables. R represents an 8-bit output variable. When this patcher is disabled, with E set to 0, the 8-bit output variable R remains unchanged. When this patcher is enabled, with E set to 1, eight bits of the output variable R are patched from eight individual Boolean inputs as follows: R,7 := I,7, R,6 := I,6, R,5 := I,5, R,4 := I,4, R,3 := I,3, R,2 := I,2, R,1 := I,1, R,0 := I,0. Assumption: The operands “regi7,biti7”, “regi6,biti6”, “regi5,biti5”, “regi4,biti4”, “regi3,biti3”, “regi2,biti2”, “regi1,biti1”, “regi0,biti0”, and “OUT” can be in any Bank.

s2

0

0 0 0 1 1 1 1 0 0 0 0 1 1 1

1

s3

0

0 0 0 0 0 0 0 1 1 1 1 1 1 1

1

1

0 1 1 0 0 1 1 0 0 1 1 0 0 1

0

s1

Inputs

1

1 0 1 0 1 0 1 0 1 0 1 0 1 0

0

s0

0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

i

y0

0

i 0 0 0 0 0 0 0 0 0 0 0 0 0

0

y1

0

0 i 0 0 0 0 0 0 0 0 0 0 0 0

0

y2

TABLE 5.8 Truth Table of the Macro “Dmux_1_16”

0

0 0 i 0 0 0 0 0 0 0 0 0 0 0

0

y3

0

0 0 0 i 0 0 0 0 0 0 0 0 0 0

0

y4

0

0 0 0 0 i 0 0 0 0 0 0 0 0 0

0

y5

0

0 0 0 0 0 i 0 0 0 0 0 0 0 0

0

y6

0

0 0 0 0 0 0 i 0 0 0 0 0 0 0

0

y7

0

0 0 0 0 0 0 0 i 0 0 0 0 0 0

0

y8

Outputs

0

0 0 0 0 0 0 0 0 i 0 0 0 0 0

0

y9

0

0 0 0 0 0 0 0 0 0 i 0 0 0 0

0

y10

0

0 0 0 0 0 0 0 0 0 0 i 0 0 0

0

y11

0

0 0 0 0 0 0 0 0 0 0 0 i 0 0

0

y12

0

0 0 0 0 0 0 0 0 0 0 0 0 i 0

0

y13

0

0 0 0 0 0 0 0 0 0 0 0 0 0 i

0

y14

i

0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

y15

342 Programmable Logic Controller

Demultiplexer Macros

FIGURE 5.14 The macro “Dmux_1_16”.

343

344

FIGURE 5.14 Continued

Programmable Logic Controller

FIGURE 5.15 The fowchart of the macro “Dmux_1_16”.

Demultiplexer Macros 345

346

Programmable Logic Controller

TABLE 5.9 Symbol of the Macro “Dmux_1_16_E”. Symbol E i= s3 = s2 = s1 = s0 = y15 = y14 = y13 = y12 = y11 = y10 = y9 = y8 = y7 = y6 = y5 = y4 = y3 = y2 = y1 =

W regi,biti Sin,3 Sin,2 Sin,1 Sin,0 outH,7 outH,6 outH,5 outH,4 outH,3 outH,2 outH,1 outH,0 outL,7 outL,6 outL,5 outL,4 outL,3 outL,2 outL,1

y0 = outL,0

5.14

EXAMPLES FOR DEMULTIPLEXER MACROS

Up to now in this chapter, we have seen demultiplexer macros developed for the PIC16F1847-Based PLC. It is now time to consider some examples related to these macros. Before you can run the example programs considered here, you are expected to construct your own PIC16F1847-Based PLC hardware by using the necessary PCB fles and by producing your PCBs, with their components. For an effective use of examples, all example programs considered in this book are allocated within the fle “PICPLC_PIC16F1847_user_Int.inc”, which is downloadable from this book’s webpage under the downloads section. Initially, all example programs are commented out by putting a semicolon, “;”, in front of each line. When you would like to test one of the example programs, you must uncomment each line of the example program by following the steps shown below: 1. Highlight the block of source lines you want to uncomment by dragging the mouse with the left mouse button held down over these lines. With default coloring in MPLAB X IDE, you will now see green characters on a blue background.

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

×: don’t care.

×

×

0

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

s2

s3

E

Inputs

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

×

s1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

×

s0

i 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

y0

0 i 0 0 0 0 0 0 0 0 0 0 0 0 0 0

0

y1 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0 0

0

y2

TABLE 5.10 Truth Table of the Macro “Dmux_1_16_E”

0 0 0 i 0 0 0 0 0 0 0 0 0 0 0 0

0

y3 0 0 0 0 i 0 0 0 0 0 0 0 0 0 0 0

0

y4 0 0 0 0 0 i 0 0 0 0 0 0 0 0 0 0

0

y5 0 0 0 0 0 0 i 0 0 0 0 0 0 0 0 0

0

y6 0 0 0 0 0 0 0 i 0 0 0 0 0 0 0 0

0

y7 0 0 0 0 0 0 0 0 i 0 0 0 0 0 0 0

0

y8

Outputs

0 0 0 0 0 0 0 0 0 i 0 0 0 0 0 0

0

y9 0 0 0 0 0 0 0 0 0 0 i 0 0 0 0 0

0

y10 0 0 0 0 0 0 0 0 0 0 0 i 0 0 0 0

0

y11 0 0 0 0 0 0 0 0 0 0 0 0 i 0 0 0

0

y12 0 0 0 0 0 0 0 0 0 0 0 0 0 i 0 0

0

y13

0 0 0 0 0 0 0 0 0 0 0 0 0 0 i 0

0

y14

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 i

0

y15

Demultiplexer Macros 347

348

FIGURE 5.16

Programmable Logic Controller

The macro “Dmux_1_16_E”.

Demultiplexer Macros

FIGURE 5.16

Continued

349

FIGURE 5.17 The fowchart of the macro “Dmux_1_16_E”.

350 Programmable Logic Controller

351

Demultiplexer Macros

TABLE 5.11 Truth Table and Symbol of the Macro “B_Dmux_1_2_E” Truth Table Inputs E 0 1 1

Symbol

Outputs s0 × 0 1

Y0 U I U

Y1 U U I

E (Boolean-enable-input, through W) = 0 or 1 I (8-bit source variable, IN) s0 (select input s0, regs0,bits0) = 0 or 1 Y1 (8-bit destination variable, OUT1) Y0 (8-bit destination variable, OUT0)

×: don’t care. U: The contents of the destination register remain unchanged.

2. Release the mouse button. 3. Press Ctrl/Shift/C or press “Alt”, “S”, and “M” keys in succession or, from the toolbar “Source” menu, select “Toggle Comment”. Now, a semicolon will be removed from all selected source lines. With default coloring, you will see red characters on a white background. Then, you can run the project by pressing the symbol from the toolbar. Next, the MPLAB X IDE will produce the “PICPLC_PIC16F1847.X.production.hex” fle for the project. Then, the MPLAB X IDE will be connected to the PICkit3 programmer and, fnally, it will program the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC. During these steps, make sure that, in the CPU board of the PIC16F1847-Based PLC, the 4PDT switch is in the “PROG” position and the power switch is in the “OFF” position. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch

FIGURE 5.18 The macro “B_Dmux_1_2_E”.

352

Programmable Logic Controller

FIGURE 5.19 The fowchart of the macro “B_Dmux_1_2_E”.

TABLE 5.12 Truth Table and Symbol of the Macro “B_Dmux_1_4_E” Truth Table Inputs E 0 1 1 1 1

s1 × 0 0 1 1

Symbol

Outputs s0 × 0 1 0 1

Y0 U I U U U

Y1 U U I U U

Y2 U U U I U

×: don’t care. U: The contents of the destination register remain unchanged.

Y3 U U U U I

E (Boolean-enable-input, through W) = 0 or 1 I (8-bit source variable, IN) s1 (select input s1 regs1,bits1) = 0 or 1 s0 (select input s0, regs0,bits0) = 0 or 1 Y3 (8-bit destination variable, OUT3) Y2 (8-bit destination variable, OUT2) Y1 (8-bit destination variable, OUT1) Y0 (8-bit destination variable, OUT0)

Demultiplexer Macros

FIGURE 5.20

353

The macro “B_Dmux_1_4_E”.

to the “ON” position. Finally, you are ready to test the example program. Warning: When you fnish your study with an example and try to take a look at another example, do not forget to comment the current example program before uncommenting another one. In other words, make sure that only one example program is uncommented and tested at the same time. Otherwise, if you somehow leave more than one example uncommented, the example you are trying to test probably will not function as expected as it may try to access the same resources that are being used and changed by other examples. Please check the accuracy of each program by cross-referencing it with the related macros.

5.14.1 EXAMPLE 5.1 Example 5.1 shows the usage of the demultiplexer macros: “Dmux_1_2” and “Dmux_1_2_E”. The user program of Example 5.1 is shown in Figure 5.28. The schematic diagram of Example 5.1 is depicted in Figure 5.29. When the project

354

Programmable Logic Controller

FIGURE 5.21 The fowchart of the macro “B_Dmux_1_4_E”.

fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 5.1 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the demultiplexer macro “Dmux_1_2” (1×2 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.0, the select input is s0 = I0.1, and the output lines are y1 = Q0.1 and y0 = Q0.0. In rung 2, the demultiplexer macro “Dmux_1_2” (1×2 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.2, the select input is s0 = I0.3, and the output lines are y1 = Q0.3 and y0 = Q0.2. In rung 3, the demultiplexer macro “Dmux_1_2” (1×2 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.4, the select input is s0 = I0.5, and the output lines are y1 = Q0.5 and y0 = Q0.4. In rung 4, the demultiplexer macro “Dmux_1_2” (1×2 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.6, the select input is s0 = I0.7, and the output lines are y1 = Q0.7 and y0 = Q0.6.

355

Demultiplexer Macros

TABLE 5.13 Truth Table and Symbol of the Macro “B_Dmux_1_8_E” Truth Table Inputs Outputs E s2 s1 s0 Y0 Y1 Y2 Y3 Y4 Y5 0 U U U U U U × × × 1 0 0 0 I U U U U U 1 0 0 1 U I U U U U 1 0 1 0 U U I U U U 1 0 1 1 U U U I U U 1 1 0 0 U U U U I U 1 1 0 1 U U U U U I 1 1 1 0 U U U U U U 1 1 1 1 U U U U U U ×: don’t care. U: The contents of the destination register remain unchanged. Symbol

Y6 U U U U U U U I U

Y7 U U U U U U U U I

E (Boolean-enable-input, through W) = 0 or 1 I (8-bit source variable, IN) s2 (select input s2 regs2,bits2) = 0 or 1 s1 (select input s1 regs1,bits1) = 0 or 1 s0 (select input s0, regs0,bits0) = 0 or 1 Y7 (8-bit destination variable, OUT7) Y6 (8-bit destination variable, OUT6) Y5 (8-bit destination variable, OUT5) Y4 (8-bit destination variable, OUT4) Y3 (8-bit destination variable, OUT3) Y2 (8-bit destination variable, OUT2) Y1 (8-bit destination variable, OUT1) Y0 (8-bit destination variable, OUT0)

In rung 5, the macro “Dmux_1_2_E” (1×2 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = I1.0, the select input is s0 = I1.1, and the output lines are y1 = Q1.1 and y0 = Q1.0. In addition, the active-high enable input E is defned to be E = I1.2. In rung 6, the macro “Dmux_1_2_E” (1×2 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = I1.5, the select input is s0 = I1.6, and the output lines are y1 = Q1.7 and y0 = Q1.6. In addition, the enable input E is defned to be E = I1.7. In rung 7, the macro “Dmux_1_2_E” (1×2 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = T_100ms, the select input is s0 = I2.1, and the output lines are y1 = Q2.1 and y0 = Q2.0. In addition, the active-high enable input E is defned to be E = I2.2.

356

FIGURE 5.22 The macro “B_Dmux_1_8_E”.

Programmable Logic Controller

Demultiplexer Macros

357

FIGURE 5.22 Continued

In rung 8, the macro “Dmux_1_2_E” (1×2 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = I2.5, the select input is s0 = I2.6, and the output lines are y1 = Q2.7 and y0 = Q2.6. In addition, the active-high enable input E is defned to be E = I2.7.

5.14.2

EXAMPLE 5.2

Example 5.2 shows the usage of the demultiplexer macros: “Dmux_1_4” and “Dmux_1_4_E”. The user program of Example 5.2 is shown in Figure 5.30. The schematic diagram of Example 5.2 is depicted in Figure 5.31. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 5.2 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the demultiplexer macro “Dmux_1_4” (1×4 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.0, the select inputs are s1 = I0.2, s0 = I0.1, and the output lines are y3 = Q0.3, y2 = Q0.2, y1 = Q0.1, and y0 = Q0.0. In rung 2, the demultiplexer macro “Dmux_1_4” (1×4 demultiplexer) is used. In this demultiplexer, the input signal is i = I1.0, the select inputs are s1 = I1.2, s0 = I1.1, and the output lines are y3 = Q1.3, y2 = Q1.2, y1 = Q1.1, and y0 = Q1.0. In rung 3, the macro “Dmux_1_4_E” (1×4 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = I2.0, the select inputs are s1 = I2.2, s0 = I2.1, and the output lines are y3 = Q2.3, y2 =

FIGURE 5.23 The fowchart of the macro “B_Dmux_1_8_E”.

358 Programmable Logic Controller

359

Demultiplexer Macros

TABLE 5.14 Truth Table of the Macro “Dispatcher_1_8_E” Truth Table Input E 0 1

Outputs O,7 O,6 u u R,7 R,6

O,5 u R,5

O,4 u R,4

O,3 u R,3

O,2 u R,2

O,1 u R,1

O,0 u R,0

u: The related bit remains unchanged.

TABLE 5.15 Symbol of the Macro “Dispatcher_1_8_E” Symbol E (Boolean-enable-input, through W) = 0 or 1 R (8-bit input variable, R) O,7 (Boolean-output-variable, rego7,bito7) O,6 (Boolean-output-variable, rego6,bito6) O,5 (Boolean-output-variable, rego5,bito5) O,4 (Boolean-output-variable, rego4,bito4) O,3 (Boolean-output-variable, rego3,bito3) O,2 (Boolean-output-variable, rego2,bito2) O,1 (Boolean-output-variable, rego1,bito1) O,0 (Boolean-output-variable, rego0,bito0)

Q2.2, y1 = Q2.1, and y0 = Q2.0. In addition, the active-high enable input E is defned to be E = I2.3. In rung 4, the macro “Dmux_1_4_E” (1×4 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = T_100ms, the select inputs are s1 = I3.2, s0 = I3.1, and the output lines are y3 = Q3.3, y2 = Q3.2, y1 = Q3.1, and y0 = Q3.0. In addition, the enable input E is defned to be E = I3.3.

5.14.3

EXAMPLE 5.3

Example 5.3 shows the usage of the demultiplexer macros: “Dmux_1_8” and “Dmux_1_8_E”. The user program of Example 5.3 is shown in Figure 5.32. The schematic diagram of Example 5.3 is depicted in Figure 5.33. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 5.3 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN”

360

FIGURE 5.24 The macro “Dispatcher_1_8_E”.

Programmable Logic Controller

Demultiplexer Macros

361

FIGURE 5.24 Continued

and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the demultiplexer macro “Dmux_1_8” (1×8 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.0, the select inputs are s2 = I0.3, s1 = I0.2, s0 = I0.1, and the output lines are y7 = Q0.7, y6 = Q0.6, y5 = Q0.5, y4 = Q0.4, y3 = Q0.3, y2 = Q0.2, y1 = Q0.1, and y0 = Q0.0. In rung 2, the demultiplexer macro “Dmux_1_8” (1×8 demultiplexer) is used. In this demultiplexer, the input signal is i = I1.0, the select inputs are s2 = I1.3, s1 = I1.2, s0 = I1.1, and the output lines are y7 = Q1.7, y6 = Q1.6, y5 = Q1.5, y4 = Q1.4, y3 = Q1.3, y2 = Q1.2, y1 = Q1.1, and y0 = Q1.0. In rung 3, the macro “Dmux_1_8_E” (1×8 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = I2.0, the select inputs are s2 = I2.3, s1 = I2.2, s0 = I2.1, and the output lines are y7 = Q2.7, y6 = Q2.6, y5 = Q2.5, y4 = Q2.4, y3 = Q2.3, y2 = Q2.2, y1 = Q2.1, and y0 = Q2.0. In addition, the active-high enable input E is defned to be E = I2.4. In rung 4, the macro “Dmux_1_8_E” (1×8 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = T_100ms, the select inputs are s2 = I3.3, s1 = I3.2, s0 = I3.1, and the output lines are y7 = Q3.7, y6 = Q3.6, y5 = Q3.5, y4 = Q3.4, y3 = Q3.3, y2 = Q3.2, y1 = Q3.1, and y0 = Q3.0. In addition, the enable input E is defned to be E = I3.4.

5.14.4

EXAMPLE 5.4

Example 5.4 shows the usage of the demultiplexer macros: “Dmux_1_16” and “Dmux_1_16_E”. The user program of Example 5.4 is shown in Figure 5.34. The schematic diagram of Example 5.4 is depicted in Figure 5.35. When the project fle

362

Programmable Logic Controller

FIGURE 5.25 The fowchart of the macro “Dispatcher_1_8_E”.

363

Demultiplexer Macros

TABLE 5.16 Truth Table of the Macro “Patcher_8_1_E” Truth Table Input

Outputs

E 0 1

R,7 u I,7

R,6 u I,6

R,5 u I,5

R,4 u I,4

R,3 u I,3

R,2 u I,2

R,1 u I,1

R,0 u I,0

u: The related bit remains unchanged.

TABLE 5.17 Symbol of the Macro “Patcher_8_1_E” Symbol E (Boolean-enable-input, through W) = 0 or 1 I,7 (Boolean-input-variable, regi7,biti7) I,6 (Boolean-input-variable, regi6,biti6) I,5 (Boolean-input-variable, regi5,biti5) I,4 (Boolean-input-variable, regi4,biti4) I,3 (Boolean-input-variable, regi3,biti3) I,2 (Boolean-input-variable, regi2,biti2) I,1 (Boolean-input-variable, regi1,biti1) I,0 (Boolean-input-variable, regi0,biti0) R (8-bit output variable, OUT)

of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC _PIC16F1847_user_Int.inc”, if you uncomment Example 5.4 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the demultiplexer macro “Dmux_1_16” (1×16 demultiplexer) is used. In this demultiplexer, the input signal is i = I0.7, the select inputs are s3 = I0.3, s2 = I0.2, s1 = I0.1, s0 = I0.0, and the output lines are y15 = Q1.7, y14 = Q1.6, y13 = Q1.5, y12 = Q1.4, y11 = Q1.3, y10 = Q1.2, y9 = Q1.1, y8 = Q1.0, y7 = Q0.7, y6 = Q0.6, y5 = Q0.5, y4 = Q0.4, y3 = Q0.3, y2 = Q0.2, y1 = Q0.1, and y0 = Q0.0. In rung 2, the macro “Dmux_1_16_E” (1×16 demultiplexer with active-high enable input) is used. In this demultiplexer, the input signal is i = T_100ms,

364

FIGURE 5.26 The macro “Patcher_8_1_E”.

Programmable Logic Controller

Demultiplexer Macros

365

FIGURE 5.26 Continued

the select inputs are s3 = I2.3, s2 = I2.2, s1 = I2.1, s0 = I2.0, and the output lines are y15 = Q3.7, y14 = Q3.6, y13 = Q3.5, y12 = Q3.4, y11 = Q3.3, y10 = Q3.2, y9 = Q3.1, y8 = Q3.0, y7 = Q2.7, y6 = Q2.6, y5 = Q2.5, y4 = Q2.4, y3 = Q2.3, y2 = Q2.2, y1 = Q2.1, and y0 = Q2.0. In addition, the active-high enable input E is defned to be E = I2.4.

5.14.5 EXAMPLE 5.5 Example 5.5 shows the usage of the macro “B_Dmux_1_2_E”. The user program of Example 5.5 is shown in Figure 5.36. The schematic diagram of Example 5.5 is depicted in Figure 5.37. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 5.5 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the byte demultiplexer macro “B_Dmux_1_2_E” (1×2 byte demultiplexer with active-high enable input) is used. In this byte demultiplexer, output variables are Y1 = Q1 and Y0 = Q0, the input variable is I = I1, and the select input is s0 = I0.1. In addition, the active-high enable input E is defned to be E = I0.0. In rung 2, the byte demultiplexer macro “B_Dmux_1_2_E” (1×2 byte demultiplexer with active-high enable input) is used. In this byte demultiplexer, output variables are Y1 = Q3 and Y0 = Q2, the input variable is I = I2, the select input is s0 = I0.7. In addition, the active-high enable input E is defned to be E = I0.6.

366

Programmable Logic Controller

FIGURE 5.27 The fowchart of the macro “Patcher_8_1_E”.

Demultiplexer Macros

367

FIGURE 5.28 The user program of “Example 5.1”.

5.14.6 EXAMPLE 5.6 Example 5.6 shows the usage of the macro “B_Dmux_1_4_E”. The user program of Example 5.6 is shown in Figure 5.38. The schematic diagram of Example 5.6 is depicted in Figure 5.39. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 5.6 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the byte demultiplexer macro “B_Dmux_1_4_E” (1×4 byte demultiplexer with active-high enable input) is used. In this byte demultiplexer,

368

Programmable Logic Controller

FIGURE 5.29 The schematic diagram of the user program of “Example 5.1”.

Demultiplexer Macros

FIGURE 5.30

369

The user program of “Example 5.2”.

output variables are Y3 = Q3, Y2 = Q2, Y1 = Q1, and Y0 = Q0, the input variable is I = I1, and select inputs are s1 = I0.1, s0 = I0.0. In addition, the active-high enable input E is defned to be E = I0.2.

5.14.7

EXAMPLE 5.7

Example 5.7 shows the usage of the macro “B_Dmux_1_8_E”. The user program of Example 5.7 is shown in Figure 5.40. The schematic diagram of Example 5.7 is depicted in Figure 5.41. When the project file of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the file “PICPLC_PIC16F1847_user_Int .inc”, if you uncomment Example 5.7 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program file to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the byte demultiplexer macro “B_Dmux_1_8_E” (1×8 byte demultiplexer with active-high enable input) is used. In this byte demultiplexer, output variables are Y7 = Q3, Y6 = Q2, Y5 = Q1, Y4 = Q0, Y3 = M3, Y2 = M2, Y1 = M1, and Y0 = M0, the input variable is I = I1, and select inputs are s2 = I0.2, s1 = I0.1, s0 = I0.0. In addition, the active-high enable input E is defned to be E = I0.3.

370

Programmable Logic Controller

FIGURE 5.31 The schematic diagram of the user program of “Example 5.2”.

Demultiplexer Macros

FIGURE 5.32 The user program of “Example 5.3”.

FIGURE 5.33 The schematic diagram of the user program of “Example 5.3”.

371

372

FIGURE 5.34

Programmable Logic Controller

The user program of “Example 5.4”.

FIGURE 5.35 The schematic diagram of the user program of “Example 5.4”.

5.14.8 EXAMPLE 5.8 Example 5.8 shows the usage of the macro “Dispatcher_1_8_E”. The user program of Example 5.8 is shown in Figure 5.42. The schematic diagram of Example 5.8 is depicted in Figure 5.43. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 5.8 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the

Demultiplexer Macros

FIGURE 5.36 The user program of “Example 5.5”.

FIGURE 5.37 The schematic diagram of the user program of “Example 5.5”.

373

374

FIGURE 5.38

Programmable Logic Controller

The user program of “Example 5.6”.

FIGURE 5.39 The schematic diagram of the user program of “Example 5.6”.

FIGURE 5.40 The user program of “Example 5.7”.

Demultiplexer Macros

375

FIGURE 5.41 The schematic diagram of the user program of “Example 5.7”.

FIGURE 5.42 The user program of “Example 5.8”.

PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the dispatcher macro “Dispatcher_1_8_E” (1×8 dispatcher with active-high enable input) is used. In this dispatcher, Boolean output variables are O,7 = Q3.7, O,6 = Q3.3, O,5 = Q2.7, O,4 = Q2.3, O,3 = Q1.7, O,2 = Q1.3, O,1 = Q0.7, and O,0 = Q0.3, and the 8-bit input variable is R = I1. In addition, the active-high enable input E is defned to be E = I0.0.

376

Programmable Logic Controller

FIGURE 5.43 The schematic diagram of the user program of “Example 5.8”.

FIGURE 5.44 The user program of “Example 5.9”.

5.14.9

EXAMPLE 5.9

Example 5.9 shows the usage of the macro “Patcher_8_1_E”. The user program of Example 5.9 is shown in Figure 5.44. The schematic diagram of Example 5.9 is depicted in Figure 5.45. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 5.9 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847Based PLC will be programmed. After loading the program fle to the PIC16F1847

Demultiplexer Macros

377

FIGURE 5.45 The schematic diagram of the user program of “Example 5.9”.

microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the patcher macro “Patcher_8_1_E” (8×1 patcher with active-high enable input) is used. In this patcher, Boolean input variables are I,7 = I3.6, I,6 = I3.2, I,5 = I2.6, I,4 = I2.2, I,3 = I1.6, I,2 = I1.2, I,1 = I0.6, and I,0 = I0.2, and the 8-bit output variable is R = Q1. In addition, the active-high enable input E is defned to be E = I0.0.

6

Conversion Macros

INTRODUCTION Data conversion instructions convert the contents of a variable from one format to another. Typical data conversion instructions comprise integer to BCD (binary coded decimal), and BCD to integer conversions. The operation of a data conversion macro is essentially the same, regardless of whether it is performing an integer to BCD or a BCD to integer conversion. When the enable input is active, the macro converts the contents of the input variable (either BCD or integer) into integer or BCD, depending on the conversion instruction. It then places the result of the conversion in the output variable. In addition to integer to BCD or BCD to integer conversions, two macros are also considered to provide seven-segment LED display conversions, and “Binary to Gray Code” and “Gray Code to Binary” conversions are also provided. In this chapter, the following conversion macros are described for the PIC16F1847-Based PLC: Conv_UsInt_2_BCD_U (Unsigned Short Integer to Unpacked BCD Conversion), Conv_UsInt_2_BCD_P (Unsigned Short Integer to Packed BCD Conversion), Conv_UInt_2_BCD_U (Unsigned Integer to Unpacked BCD Conversion), Conv_UInt_2_BCD_P (Unsigned Integer to Packed BCD Conversion), Conv_BCD_U_2_UInt (5-Digit Unpacked BCD to Unsigned Integer Conversion), Conv_BCD_P_2_UInt (5-Digit Packed BCD to Unsigned Integer Conversion), Segment_CCD (Segment_CCD Instruction), Segment_CAD (Segment_CAD Instruction), Conv_Bin_2_Gray (Binary to Gray Code Conversion), Conv_Bin_2_Gray_16 (Binary to Gray Code Conversion), Conv_Gray_2_Bin (Gray Code to Binary Conversion), Conv_Gray_2_Bin_16 (Gray Code to Binary Conversion). There are fve 8-bit variables, namely TenK, Thou, Hund, Tens, and Ones, to be used for conversion macros “Conv_UsInt_2_BCD_P”, “Conv_BCD_P_2_UInt”, “Conv_ UInt_2_BCD_P”, and “Conv_BCD_U_2_UInt”. The defnition of these fve 8-bit variables and their allocation in BANK 12 of SRAM data memory are depicted in Figure 6.1 and Figure 6.2, respectively. The fle “PICPLC_PIC16F1847_macros_Int.inc”, which is downloadable from this book’s webpage under the downloads section, contains macros defned for the PIC16F1847-Based PLC explained in this volume (Intermediate Concepts). Let us now consider the conversion macros in detail.

379

380

FIGURE 6.1

Programmable Logic Controller

Defnition of fve 8-bit variables to be used for some conversion macros.

FIGURE 6.2 Allocation of fve 8-bit variables in SRAM data memory to be used for some conversion macros.

6.1 MACRO “CONV_USINT_2_BCD_U” (UNSIGNED SHORT INTEGER TO UNPACKED BCD CONVERSION) The symbol of the macro “Conv_UsInt_2_BCD_U” is shown in Table 6.1. Figures 6.3 and 6.4 show the macro “Conv_UsInt_2_BCD_U” and its fowchart, respectively. This macro has a Boolean-enable-input EN, an 8-bit input variable UsInt, and three 8-bit output variables, Hund, Tens, and Ones. The output variable Hund (respectively, Tens, Ones) holds the BCD value of hundreds (respectively, tens, ones). The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts an unsigned short integer (UsInt) value to its unpacked BCD form represented in three bytes (Hund, Tens, and Ones). Figure 6.5 shows the representation of data handling in the “Conv_UsInt_2_BCD_U” macro. This macro takes an 8-bit integer value from the input variable UsInt and places the BCD equivalent of the input variable in the least signifcant 4-bits (low nibbles) of the three 8-bit output variables Hund, Tens, and Ones. The “Conv_UsInt_2_BCD_U” instruction is enabled when the preceding logic is true, and disabled otherwise. The most signifcant 4-bits (high nibbles) of these three 8-bit output variables, Hund, Tens, and One, are always zero. The source data stored in the 8-bit variable UsInt remain unchanged. Similarly, when the “Conv_UsInt_2_BCD_U” instruction is not enabled, output variables Hund, Tens, and Ones remain unchanged. Some example input and output values for the

Conversion Macros

TABLE 6.1 Symbol of the Macro “Conv_UsInt_2_BCD_U” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 UsInt (8-bit input variable, UsInt) Hund (8-bit output variable, holding the BCD value of hundreds, Hund) Tens (8-bit output variable, holding the BCD value of tens, Tens) Ones (8-bit output variable, holding the BCD value of ones, Ones)

FIGURE 6.3

The macro “Conv_UsInt_2_BCD_U”.

381

382

Programmable Logic Controller

FIGURE 6.4 The fowchart of the macro “Conv_UsInt_2_BCD_U”.

“Conv_UsInt_2_BCD_U” macro are depicted in Table 6.2. Note that, in this table, higher nibbles of output variables Hund, Tens, and Ones are not shown as they are always zero. Assumption: The operands “UsInt”, “Hund”, “Tens”, and “Ones” can be in any Bank.

Conversion Macros

FIGURE 6.5

383

Representation of data handling in the “Conv_UsInt_2_BCD_U” macro.

6.2 MACRO “CONV_USINT_2_BCD_P” (UNSIGNED SHORT INTEGER TO PACKED BCD CONVERSION) The symbol of the macro “Conv_UsInt_2_BCD_P” is depicted in Table 6.3. Figures  6.6 and 6.7 show the macro “Conv_UsInt_2_BCD_P” and its fowchart, respectively. This macro has a Boolean-enable-input EN, an 8-bit input variable UsInt, and two 8-bit output variables, bcd1 and bcd0. The defnition of three 8-bit variables, namely Hund, Tens, and Ones, to be used for the “Conv_UsInt_2_ BCD_P” macro and their allocation in BANK 12 of SRAM data memory are both shown in Figures 6.1 and 6.2, respectively. These 8-bit variables are utilized to hold unpacked 3-digit BCD results before they are packed into two 8-bit output variables, bcd1 and bcd0. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts an unsigned short integer (UsInt) value to its packed BCD form represented in two bytes (8-bit output variables bcd1 and bcd0). Figure 6.8 shows how to obtain the “Conv_UsInt_2_BCD_P” macro from the “Conv_ UsInt_2_BCD_U” macro. Figure 6.9 shows the representation of data handling in the “Conv_UsInt_2_BCD_P” macro. When enabled (EN = 1), this macro takes an 8-bit integer value from the input variable UsInt and places the BCD equivalent of UsInt in the two 8-bit output variables bcd1 and bcd0. The least signifcant 4-bits (low nibble) of bcd1 hold Hund digit, and the other 4-bits are always zero. The most signifcant 4-bits (high nibble) of bcd0 hold Tens digit, and the least signifcant 4-bits (low nibble) of bcd0 hold Ones digit. The “Conv_UsInt_2_BCD_P” instruction is enabled when the preceding logic is true and disabled otherwise. The source data stored in the 8-bit input variable UsInt remain unchanged. Similarly, when the “Conv_UsInt_2_BCD_P” instruction is not enabled, output variables bcd1 and bcd0 remain unchanged. Some example input and output values for the “Conv_ UsInt_2_BCD_P” macro can be seen from Table 6.2. Assumption: The operands “UsInt”, “bcd1”, and “bcd0” can be in any Bank.

0 . 0 0 . 0 0 . 0 . 0 0 . 1 . 1 .

1

255

7

0 . 15 16 . 49 50 . 73 . 99 100 . 155 . 218 .

Decimal

1

0 . 0 0 . 0 0 . 1 . 1 1 . 0 . 1 .

6

1

0 . 0 0 . 1 1 . 0 . 1 1 . 0 . 0 .

5

1

0 . 0 1 . 1 1 . 0 . 0 0 . 1 . 1 .

4

UsInt

1

0 . 1 0 . 0 0 . 1 . 0 0 . 1 . 1 .

3

8-Bit Integer Input Variable

1

0 . 1 0 . 0 0 . 0 . 0 1 . 0 . 0 .

2

1

0 . 1 0 . 0 1 . 0 . 1 0 . 1 . 1 .

1

1

0 . 1 0 . 1 0 . 1 . 1 0 . 1 . 0 .

0

0

0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 .

3

0

0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 .

2

1

0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 1 .

1

Hund Digit

0

0 . 0 0 . 0 0 . 0 . 0 1 . 1 . 0 .

0

0

0 . 0 0 . 0 0 . 0 . 1 0 . 0 . 0 .

3

1

0 . 0 0 . 1 1 . 1 . 0 0 . 1 . 0 .

2

0

0 . 0 0 . 0 0 . 1 . 0 0 . 0 . 0 .

1

Tens Digit

1

0 . 1 1 . 0 1 . 1 . 1 0 . 1 . 1 .

0

3-Digit BCD Output Variables

TABLE 6.2 Some Example Input and Output Values for the “Conv_UsInt_2_BCD_U” Macro

0

0 . 0 0 . 1 0 . 0 . 1 0 . 0 . 1 .

3

1

0 . 1 1 . 0 0 . 0 . 0 0 . 1 . 0 .

2

0

0 . 0 1 . 0 0 . 1 . 0 0 . 0 . 0 .

1

Ones Digit

1

0 . 1 0 . 1 0 . 1 . 1 0 . 1 . 0 .

0

384 Programmable Logic Controller

Conversion Macros

385

TABLE 6.3 Symbol of the Macro “Conv_UsInt_2_BCD_P” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 UsInt (8-bit input variable, UsInt) bcd1 (8-bit output variable, holding the BCD value of hundreds, bcd1) bcd0 (8-bit output variable, holding the BCD values of tens, and ones, bcd0)

6.3

MACRO “CONV_UINT_2_BCD_U” (UNSIGNED INTEGER TO UNPACKED BCD CONVERSION)

The symbol of the macro “Conv_UInt_2_BCD_U” is depicted in Table 6.4. Figure 6.10 shows the macro “Conv_UInt_2_BCD_U”. This macro is based on the 16-bit to 5-digit conversion reported in [R6.1]. This macro has a Boolean-enableinput EN, a 16-bit input variable IN, consisting of two 8-bit variables, NumH (high byte of IN) and NumL (low byte of IN), and fve 8-bit output variables, TenK, Thou, Hund, Tens, and Ones. The 8-bit output variable TenK (respectively, Thou, Hund, Tens, and Ones) holds the BCD value of ten thousands (respectively, thousands, hundreds, tens, and ones). The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts an unsigned integer (16-bit input variable IN consisting of NumH and NumL) value to its unpacked BCD form represented in fve bytes. Figure 6.11 shows the representation of data handling in the “Conv_UInt_2_BCD_U” macro. When enabled (EN = 1), this macro takes a 16-bit integer value from the variable IN, consisting of two 8-bit variables, NumH and NumL, and places the binarycoded decimal equivalent of IN in the least signifcant 4-bits (low nibbles) of the fve 8-bit output variables TenK, Thou, Hund, Tens, and Ones. The “Conv_UInt_2_ BCD_U” instruction is enabled when the preceding logic is true and disabled otherwise. The most signifcant 4-bits (high nibbles) of these fve 8-bit output variables are always zero. The source data stored in two 8-bit variables, NumH and NumL, remain unchanged. Similarly, when the “Conv_UInt_2_BCD_U” instruction is not enabled, output variables TenK, Thou, Hund, Tens, and Ones remain unchanged. Some example input and output values for the “Conv_UInt_2_BCD_U” macro are shown in Table 6.5. Note that, in this table, higher nibbles of output variables TenK, Thou, Hund, Tens, and Ones are not shown as they are always zero. Assumption: The operands “NumH”, “NumL”, “TenK”, “Thou”, “Hund”, “Tens”, and “Ones” can be in any Bank.

386

Programmable Logic Controller

FIGURE 6.6

6.4

The macro “Conv_UsInt_2_BCD_P”.

MACRO “CONV_UINT_2_BCD_P” (UNSIGNED INTEGER TO PACKED BCD CONVERSION)

The symbol of the macro “Conv_UInt_2_BCD_P” is depicted in Table 6.6. Figure 6.12 shows the macro “Conv_UInt_2_BCD_P”. This macro is based on the 16-bit to 5-digit conversion reported in [R6.1]. This macro has a Boolean-enable-input EN, a 16-bit input variable IN, consisting of two 8-bit variables, NumH (high byte of IN) and NumL (low byte of IN), and three 8-bit output variables, bcd2, bcd1, and bcd0. The defnition of fve 8-bit variables, namely TenK, Thou, Hund, Tens, and Ones, to

Conversion Macros

FIGURE 6.7 The fowchart of the macro “Conv_UsInt_2_BCD_P”.

387

388

Programmable Logic Controller

FIGURE 6.8 Obtaining the “Conv_UsInt_2_BCD_P” macro from the “Conv_UsInt_2_ BCD_U” macro.

FIGURE 6.9

Representation of data handling in the “Conv_UsInt_2_BCD_P” macro.

be used for the “Conv_UInt_2_BCD_P” macro and their allocation in BANK 12 of SRAM data memory are both shown in Figures 6.1 and 6.2, respectively. These 8-bit variables are utilized to hold unpacked 5-digit BCD results before they are packed into three 8-bit output variables, bcd2, bcd1, and bcd0. The 8-bit output variable bcd2 (respectively, bcd1, and bcd0) holds the BCD value of ten thousands (respectively, thousands and hundreds; and tens and ones). The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no

Conversion Macros

389

TABLE 6.4 Symbol of the Macro “Conv_UInt_2_BCD_U” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 IN (16-bit input variable, consisting of two 8-bit variables NumH and NumL) TenK (8-bit output variable, holding the BCD value of ten thousands, TenK) Thou (8-bit output variable, holding the BCD value of thousands, Thou) Hund (8-bit output variable, holding the BCD value of hundreds, Hund) Tens (8-bit output variable, holding the BCD value of tens, Tens) Ones (8-bit output variable, holding the BCD value of ones, Ones)

action is taken. When enabled (EN = 1), this macro converts an unsigned integer (16bit input variable IN consisting of NumH and NumL) value to its packed BCD form represented in three bytes (8-bit output variables bcd2, bcd1, and bcd0). Figure 6.13 shows how to obtain the “Conv_UInt_2_BCD_P” macro from the “Conv_UInt_2_ BCD_U” macro. Figure 6.14 shows the representation of data handling in the “Conv_UInt_2_BCD_P” macro. The least signifcant 4-bits (low nibble) of bcd2 hold TenK digit, and the other 4-bits are always zero. The most signifcant 4-bits (high nibble) of bcd1 hold Thou digit, and the least signifcant 4-bits (low nibble) of bcd1 hold Hund digit. Likewise, the most signifcant 4-bits (high nibble) of bcd0 hold Tens digit, and the least signifcant 4-bits (low nibble) of bcd1 hold Ones digit. The “Conv_UInt_2_BCD_P” instruction is enabled when the preceding logic is true and disabled otherwise. The source data stored in two 8-bit variables, NumH and NumL, remain unchanged. Similarly, when the “Conv_UInt_2_BCD_P” instruction is not enabled, output variables bcd2, bcd1, and bcd0 remain unchanged. Some example input and output values for the “Conv_UInt_2_BCD_P” macro can be observed in Table 6.5. Assumption: The operands “NumH”, “NumL”, “bcd2”, “bcd1”, and “bcd0” can be in any Bank.

6.5 MACRO “CONV_BCD_U_2_UINT” (5-DIGIT UNPACKED BCD TO UNSIGNED INTEGER CONVERSION) The symbol of the macro “Conv_BCD_U_2_UInt” is depicted in Table 6.7. Figure 6.15 shows the macro “Conv_BCD_U_2_UInt”. This macro is based on the unpacked 5-digit BCD to 16-bit binary conversion reported in [R6.2]. This macro has a Booleanenable-input EN, fve 8-bit input variables, nTenK, nThou, nHund, nTens, and nOnes, and a 16-bit output variable OUT, consisting of two 8-bit variables, NumH (high byte

390

FIGURE 6.10

Programmable Logic Controller

The macro “Conv_UInt_2_BCD_U”.

of OUT) and NumL (low byte of OUT). Low nibble of the 8-bit input variable nTenK (respectively, nThou, nHund, nTens, and nOnes) holds the BCD value of ten thousands (respectively, thousands, hundreds, tens, and ones). The defnition of fve 8-bit variables, namely TenK, Thou, Hund, Tens, and Ones, to be used for the “Conv_ BCD_U_2_UInt” macro and their allocation in BANK 12 of SRAM data memory are both shown in Figures 6.1 and 6.2, respectively. These 8-bit variables are utilized to

Conversion Macros

FIGURE 6.10

391

Continued

hold the contents of unpacked 5-digit BCD inputs taken from input variables nTenK, nThou, nHund, nTens, and nOnes, respectively. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts an unpacked 5-digit BCD number, located in the least signifcant 4-bits (low nibbles) of the fve 8-bit input variables nTenK, nThou, nHund, nTens and nOnes, to its 16-bit unsigned integer value OUT, consisting of two 8-bit variables, NumH and NumL. If the input value is greater than

392

Programmable Logic Controller

FIGURE 6.10

Continued

65535, then the carry fag is set. Figure 6.16 shows the representation of data handling in the “Conv_BCD_U_2_UInt” macro. The “Conv_BCD_U_2_UInt” instruction is enabled when the preceding logic is true and disabled otherwise. The source data stored in fve 8-bit variables, nTenK, nThou, nHund, nTens, and nOnes, remain unchanged. Similarly, when the “Conv_BCD_U_2_UInt” instruction is not enabled, output variables NumH and NumL remain unchanged. Some example input and output values for the “Conv_BCD_U_2_UInt” macro can be observed in Table 6.8. If any one of input variables nTenK, nThou, nHund, nTens, and nOnes contains a value greater than 9, then the “Conv_BCD_U_2_UInt” macro will provide output registers as follows: NumH = 00 h, NumL = 00h, and Carry Flag = 0. Assumption: The operands “nTenK”, “nThou”, “nHund”, “nTens”, “nOnes”, “NumH”, and “NumL” can be in any Bank.

6.6

MACRO “CONV_BCD_P_2_UINT” (5-DIGIT PACKED BCD TO UNSIGNED INTEGER CONVERSION)

The symbol of the macro “Conv_BCD_P_2_UInt” is depicted in Table 6.9. Figure 6.17 shows the macro “Conv_BCD_P_2_UInt”. This macro is based on the unpacked 5-digit BCD to 16-bit binary conversion reported in [R6.2]. This macro has a Boolean-enable-input EN, three 8-bit input variables, bcd2, bcd1, and bcd0, and a 16-bit output variable OUT, consisting of two 8-bit variables, NumH (high byte of OUT) and NumL (low byte of OUT). The least signifcant 4-bits (low nibble) of bcd2 hold TenK digit, and the other 4-bits are always zero. The most signifcant 4-bits (high nibble) of bcd1 hold Thou digit, and the least signifcant 4-bits (low nibble) of bcd1 hold Hund digit. Likewise, the most signifcant 4-bits (high nibble) of bcd0 hold Tens digit, and the least signifcant 4-bits (low nibble) of bcd1 hold Ones digit. The defnition of fve 8-bit variables, namely TenK, Thou, Hund, Tens, and Ones, to be used for the “Conv_BCD_P_2_UInt” macro and their allocation in BANK 12 of SRAM data memory are both shown in Figures 6.1 and 6.2, respectively. These 8-bit variables are utilized to hold the contents of

FIGURE 6.11 Representation of data handling in the “Conv_UInt_2_BCD_U” macro.

Conversion Macros 393

0 . 255 256 . 999 1000 . 5000 . 9999 10000 . 20000 . 30000 . 40000 . 50000 . 60000 . 62525 . 65535

Decimal

7 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 . 1 . 1 . 1 . 1 . 1

6 0 . 0 0 . 0 0 . 0 . 0 0 . 1 . 1 . 0 . 1 . 1 . 1 . 1

5 0 . 0 0 . 0 0 . 0 . 1 1 . 0 . 1 . 0 . 0 . 1 . 1 . 1

4 0 . 0 0 . 0 0 . 1 . 0 0 . 0 . 1 . 1 . 0 . 0 . 1 . 1

3 0 . 0 0 . 0 0 . 0 . 0 0 . 1 . 0 . 1 . 0 . 1 . 0 . 1

NumH

2 0 . 0 0 . 0 0 . 0 . 1 1 . 1 . 1 . 1 . 0 . 0 . 1 . 1

1 0 . 0 0 . 1 1 . 1 . 1 1 . 1 . 0 . 0 . 1 . 1 . 0 . 1

0 0 . 0 1 . 1 1 . 1 . 1 1 . 0 . 1 . 0 . 1 . 0 . 0 . 1

7 0 . 1 0 . 1 1 . 1 . 0 0 . 0 . 0 . 0 . 0 . 0 . 0 . 1

6 0 . 1 0 . 1 1 . 0 . 0 0 . 0 . 0 . 1 . 1 . 1 . 0 . 1

16-Bit Integer Input Variable

5 0 . 1 0 . 1 1 . 0 . 0 0 . 1 . 1 . 0 . 0 . 1 . 1 . 1

4 0 . 1 0 . 0 0 . 0 . 0 1 . 0 . 1 . 0 . 1 . 0 . 1 . 1

3 0 . 1 0 . 0 1 . 1 . 1 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

NumL 2 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

1 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 1

0 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

3 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

2 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 . 1 . 1 . 1 . 1 . 1

1 0 . 0 0 . 0 0 . 0 . 0 0 . 1 . 1 . 0 . 0 . 1 . 1 . 1

TenK Digit 0 0 . 0 0 . 0 0 . 0 . 0 1 . 0 . 1 . 0 . 1 . 0 . 0 . 0

3 0 . 0 0 . 0 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

2 0 . 0 0 . 0 0 . 1 . 0 0 . 0 . 0 . 0 . 0 . 0 . 0 . 1

1 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 1 . 0

Thou Digit 0 0 . 0 0 . 0 1 . 1 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 1

3 0 . 0 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

2 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

1 0 . 1 1 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

0 0 . 0 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

Hund Digit 3 0 . 0 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

2 0 . 1 1 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

1 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

Tens Digit

5-Digit BCD Output Variables

TABLE 6.5 Some Example Input and Output Values for the “Conv_UInt_2_BCD_U” Macro

0 0 . 1 1 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 1

2 0 . 1 1 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

1 0 . 0 1 . 0 0 . 0 . 0 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

0 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 1 . 1

Ones Digit 3 0 . 0 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0

394 Programmable Logic Controller

Conversion Macros

395

TABLE 6.6 Symbol of the Macro “Conv_UInt_2_BCD_P” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 IN (16-bit input variable, consisting of two 8-bit variables NumH&NumL) bcd2 (8-bit output variable, holding the BCD value of ten thousands, bcd2) bcd1 (8-bit output variable, holding the BCD values of thousands and hundreds, bcd1) bcd0 (8-bit output variable, holding the BCD values of tens, and ones, bcd0)

unpacked 5-digit BCD inputs extracted from input variables bcd2, bcd1, and bcd0. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts a 5-digit BCD number, packed in three 8-bit input variables, namely, bcd2, bcd1, and bcd0, to its 16-bit unsigned integer value OUT, consisting of two 8-bit variables, NumH and NumL. If the input value is greater than 65535, then the carry fag is set. Figure 6.18 shows how to obtain the “Conv_BCD_P_2_UInt” macro from the “Conv_BCD_U_2_UInt” macro. Figure 6.19 shows the representation of data handling in the “Conv_BCD_P_2_UInt” macro. The “Conv_ BCD_P_2_UInt” instruction is enabled when the preceding logic is true and disabled otherwise. The source data stored in three 8-bit input variables, bcd2, bcd1, and bcd0, remain unchanged. Similarly, when the “Conv_BCD_P_2_UInt” instruction is not enabled, output variables NumH and NumL remain unchanged. Some example input and output values for the “Conv_BCD_P_2_UInt” macro can be observed in Table 6.8. If any one of fve BCD inputs, namely TenK digit, Thou digit, Hund digit, Tens digit, or Ones digit, contains a value greater than 9, then the “Conv_BCD_P_2_UInt” macro will provide output registers as follows: NumH = 00 h, NumL = 00h, and Carry Flag = 0. Assumption: The operands “bcd2”, “bcd1”, “bcd0”, “NumH”, and “NumL” can be in any Bank.

6.7 SEVEN-SEGMENT LED DISPLAYS Seven-segment LED (light emitting diode) or LCD (liquid crystal display) type displays provide a very convenient way of displaying information or digital data in the form of numbers, letters, or even alphanumerical characters. Typically, sevensegment displays consist of seven individual colored LEDs (called the segments), within one single display package. In order to produce the required numbers or HEX characters, from 0 to 9 and A to F, respectively, on the display, the correct combination of LED segments needs to be illuminated, and BCD to seven-segment display

396

FIGURE 6.12

Programmable Logic Controller

The macro “Conv_UInt_2_BCD_P”.

decoders such as the 74LS47 do just that. A standard seven-segment LED display generally has eight input connections, one for each LED segment and one that acts as a common terminal or connection for all the internal display segments. Some single displays also have an additional input pin to display a decimal point in their lower right- or left-hand corner.

Conversion Macros

FIGURE 6.12

397

Continued

In electronics, there are two important types of seven-segment LED digital display: 1. The common cathode display (CCD) – In the CCD, all the cathode connections of the LEDs are joined together to logic “0” or ground. The individual segments are illuminated by application of a “HIGH” (logic “1”) signal to the individual anode terminals. Figure 6.20 shows an example sevensegment CCD. Although not shown in this fgure, for each input terminal, there must be a current-limiting resistor.

FIGURE 6.13

Obtaining the “Conv_UInt_2_BCD_P” macro from the “Conv_UInt_2_BCD_U” macro.

398 Programmable Logic Controller

Conversion Macros

FIGURE 6.14

399

Representation of data handling in the “Conv_UInt_2_BCD_P” macro.

2. The common anode display (CAD) – In the CAD, all the anode connections of the LEDs are joined together to logic “1”, and the individual segments are illuminated by connecting the individual cathode terminals to a “LOW” (logic “0”) signal. Figure 6.21 shows an example seven-segment CAD. Although not shown in this fgure, for each input terminal, there must be a current-limiting resistor.

6.8 MACRO “SEGMENT_CCD” (SEGMENT_CCD INSTRUCTION) The symbol of the macro “Segment_CCD” is shown in Table 6.10. Table 6.11 depicts the seven-segment CCD coding used by the Segment_CCD instruction. Figures 6.22 and TABLE 6.7 Symbol of the Macro “Conv_BCD_U_2_UInt” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 nTenK (8-bit input variable, holding the BCD value of ten thousands, nTenK) nThou (8-bit input variable, holding the BCD value of thousands, nThou) nHund (8-bit input variable, holding the BCD value of hundreds, nHund) nTens (8-bit input variable, holding the BCD value of tens, nTens) nOnes (8-bit input variable, holding the BCD value of ones, nOnes) OUT (16-bit output variable, consisting of two 8-bit variables NumH and NumL)

400

FIGURE 6.15

Programmable Logic Controller

The macro “Conv_BCD_U_2_UInt”.

6.23 show the macro “Segment_CCD” and its fowchart, respectively. This macro has a Boolean-enable-input EN, an 8-bit input variable IN, and an 8-bit output variable OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro generates a bit pattern (OUT) that illuminates the segments of a seven-segment CCD. The illuminated segments represent the character in the least signifcant digit (LSD) of the input byte (IN). This instruction is enabled when the preceding logic is true and disabled otherwise. The input data stored in the 8-bit variable IN remain unchanged. Similarly, when the “Segment_CCD” instruction is not enabled, the output variable OUT remains unchanged. Assumption: The operands “IN” and “OUT” can be in any Bank.

Conversion Macros

FIGURE 6.15

Continued

401

402

FIGURE 6.15

Programmable Logic Controller

Continued

FIGURE 6.16

Representation of data handling in the “Conv_BCD_U_2_UInt” macro.

Conversion Macros 403

1 1

0

1

0

0 0 . 0 0 . 0 0 . 0 . 0 1 . 1 . 0 . 0 . 0 . 0 .

0

0

Thou Digit 3 2 1 0 0 0 . . . 0 0 0 0 0 0 . . . 0 0 0 0 0 0 . . . 0 1 0 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 0 0 0 . . . 0 0 1 . . . 0 1 0 . . . 0 0 0 . . .

TenK Digit 3 2 1 0 0 0 . . . 0 0 0 0 0 0 . . . 0 0 0 0 0 0 . . . 0 0 0 . . . 0 0 0 0 0 0 . . . 0 0 1 . . . 0 1 1 . . . 0 1 1 . . . 0 1 1 . . . 1 0 0 . . .

5-Digit BCD Input Variables

1 1

0 0 . 0 0 . 0 1 . 1 . 1 0 . 0 . 0 . 0 . 1 . 0 .

0

0

Hund Digit 3 2 1 0 0 0 . . . 0 0 1 0 0 1 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 0 0 0 . . . 0 1 0 . . . 0 1 0 . . . 0 0 0 . . .

1 1

0 0 . 0 0 . 1 0 . 0 . 1 0 . 0 . 0 . 1 . 1 . 0 . 0

0

Tens Digit 3 2 1 0 0 0 . . . 0 1 0 0 1 0 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 0 0 0 . . . 0 0 1 . . . 0 0 1 . . . 0 0 0 . . . 1 1

0 0 . 1 1 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 1 . 0 . 0

0

Ones Digit 3 2 1 0 0 0 . . . 0 1 0 0 1 1 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 1 0 0 0 0 0 . . . 0 0 0 . . . 0 0 0 . . . 0 1 0 . . . 0 1 0 . . . 0 0 0 . . . 1

1

1

0

NumH 0 Carry 7 6 0 0 0 0 . . . . 1 0 0 0 0 0 0 0 . . . . 1 0 0 0 0 0 0 0 . . . . 0 0 0 0 . . . . 1 0 0 0 0 0 0 0 . . . . 0 0 0 1 . . . . 0 0 1 1 . . . . 1 0 1 1 . . . . 1 0 1 1 . . . . 0 1 0 0 . . . . 0

5 0 . 0 0 . 0 0 . 0 . 1 1 . 1 . 1 . 1 . 1 . 1 . 0

4 0 . 0 0 . 0 0 . 1 . 0 0 . 1 . 0 . 1 . 1 . 1 . 0

3 0 . 0 0 . 0 0 . 0 . 0 0 . 0 . 1 . 0 . 1 . 1 . 1

2 0 . 0 0 . 0 0 . 0 . 1 1 . 1 . 0 . 1 . 1 . 0 . 1

1 0 . 0 0 . 1 1 . 1 . 1 1 . 0 . 1 . 0 . 1 . 0 . 0

NumL 7 6 0 0 . . 1 1 0 0 . . 1 1 1 1 . . 1 0 . . 0 0 0 0 . . 0 0 . . 0 1 . . 0 0 . . 1 1 . . 1 0 . . 0 1

0 0 . 0 1 . 1 1 . 1 . 1 1 . 1 . 0 . 0 . 1 . 0 .

16-Bit Integer Output Variable

TABLE 6.8 Some Example Input and Output Values for the “Conv_BCD_U_2_UInt” Macro

0

5 0 . 1 0 . 1 1 . 0 . 0 0 . 1 . 1 . 1 . 1 . 0 . 1

4 0 . 1 0 . 0 0 . 0 . 0 1 . 1 . 0 . 1 . 1 . 0 . 1

3 0 . 1 0 . 0 1 . 1 . 1 0 . 0 . 0 . 1 . 1 . 0 . 1

2 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 1 . 1 . 0 . 1

1 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 0 . 1 . 0 .

0 . 255 256 . 999 1000 . 5000 . 9999 10000 . 30000 . 60000 . 62525 . 65535 . 80000 .

Decimal

1 99999

0 0 . 1 0 . 1 0 . 0 . 1 0 . 0 . 0 . 1 . 1 . 0 .

404 Programmable Logic Controller

Conversion Macros

TABLE 6.9 Symbol of the Macro “Conv_BCD_P_2_UInt” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 bcd2 (8-bit input variable, holding the BCD value of ten thousands, bcd2) bcd1 (8-bit input variable, holding the BCD values of thousands and hundreds, bcd1) bcd0 (8-bit input variable, holding the BCD values of tens, and ones, bcd0) OUT (16-bit output variable, consisting of two 8-bit variables NumH and NumL)

FIGURE 6.17 The macro “Conv_BCD_P_2_UInt”.

405

406

Programmable Logic Controller

FIGURE 6.17 Continued

6.9 MACRO “SEGMENT_CAD” (SEGMENT_CAD INSTRUCTION) The symbol of the macro “Segment_CAD” is shown in Table 6.12. Table 6.13 depicts the seven-segment CAD coding used by the Segment_CAD instruction. Figures 6.24 and 6.25 show the macro “Segment_CAD” and its fowchart, respectively. This macro has a Boolean-enable-input EN, an 8-bit input variable IN, and an 8-bit output variable

Conversion Macros

407

FIGURE 6.17 Continued

OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro generates a bit pattern (OUT) that illuminates the segments of a seven-segment CAD. The illuminated segments represent the character in the LSD of the input byte (IN). This instruction is enabled when the preceding logic is true and disabled otherwise. The input data stored in the 8-bit variable IN remain unchanged. Similarly, when

FIGURE 6.18

Obtaining the “Conv_BCD_P_2_UInt” macro from the “Conv_BCD_U_2_UInt” macro.

408 Programmable Logic Controller

Conversion Macros

FIGURE 6.19

Representation of data handling in the “Conv_BCD_P_2_UInt” macro.

FIGURE 6.20

Seven-segment common cathode display (CCD).

FIGURE 6.21

Seven-segment common anode display (CAD).

409

410

Programmable Logic Controller

TABLE 6.10 Symbol of the Macro “Segment_CCD” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit input variable, IN) OUT (8-bit output variable, OUT)

the “Segment_CAD” instruction is not enabled, the output variable OUT remains unchanged. Assumption: The operands “IN” and “OUT” can be in any Bank.

6.10 MACRO “CONV_BIN_2_GRAY” (BINARY TO GRAY CODE CONVERSION) Gray code is an ordering of the binary numeral system such that two successive values differ in only one bit (binary digit). Gray code was originally designed to prevent spurious output from electromechanical switches. Gray codes are widely used to facilitate error correction in digital communications such as digital television and some cable TV systems. The binary to gray code conversion method strongly follows the EX-OR gate operation between binary bits. The following steps briefy show how to perform binary to gray code conversion: 1. To convert binary to gray code, bring down the most signifcant bit (MSB) of the given binary number, because the MSB of the gray coded number is the same as the binary number. 2. To obtain the successive gray coded bits from the given binary number, add the frst binary bit (the MSB) of binary to the second one and write down the result next to the frst bit of gray code, add the second binary bit to the third one and write down the result next to the second bit of gray code, follow this operation until the last binary bit, and write down the results to produce the equivalent gray coded number. Recall that the addition of two bits is carried out by means of a two-input EX-OR gate. The symbol of the macro “Conv_Bin_2_Gray” is shown in Table 6.14. Figures 6.26 and 6.27 show the macro “Conv_Bin_2_Gray” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has an 8-bit input variable, IN, holding the 8-bit Binary input, and an 8-bit output variable, OUT, holding the

411

Conversion Macros

TABLE 6.11 Seven-Segment Common Cathode Display Coding (IN) LSD Hex Value

(IN) LSD 3210

Seven-Segment Display

(OUT) 7 6 5 43 2 1 0 - g f ed c b a

(OUT) Hex Value

0

0000

0 0 1 11 1 1 1

3F

1

0001

0 0 0 00 1 1 0

06

2

0010

0 1 0 11 0 1 1

5B

3

0011

0 1 0 01 1 1 1

4F

4

0100

0 1 1 00 1 1 0

66

5

0101

0 1 1 01 1 0 1

6D

6

0110

0 1 1 11 1 0 1

7D

7

0111

0 0 0 00 1 1 1

07

8

1000

0 1 1 11 1 1 1

7F

9

1001

0 1 1 01 1 1 1

6F

A

1010

0 1 1 10 1 1 1

77

B

1011

0 1 1 11 1 0 0

7C (Continued )

412

Programmable Logic Controller

TABLE 6.11 (CONTINUED) Seven-Segment Common Cathode Display Coding (IN) LSD Hex Value

(IN) LSD 3210

Seven-Segment Display

(OUT) 7 6 5 43 2 1 0 - g f ed c b a

(OUT) Hex Value

C

1100

0 0 1 11 0 0 1

39

D

1101

0 1 0 11 1 1 0

5E

E

1110

0 1 1 11 0 0 1

79

F

1111

0 1 1 10 0 0 1

71

8-bit gray code obtained from the input IN. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts an 8-bit binary value IN to its 8-bit gray code OUT. Figure 6.28 shows the representation of 8-bit binary to 8-bit gray code conversion. The source data stored in the 8-bit variable IN remain unchanged. Similarly, when the “Conv_Bin_2_Gray” instruction is not enabled, the output variable OUT remains unchanged. Table 6.15 shows some example input and output values for the “Conv_Bin_2_Gray” macro. Assumption: The operands “IN” and “OUT” can be in any Bank.

6.11

MACRO “CONV_BIN_2_GRAY_16” (BINARY TO GRAY CODE CONVERSION)

The symbol of the macro “Conv_Bin_2_Gray_16” is shown in Table 6.16. Figures 6.29 and 6.30 show the macro “Conv_Bin_2_Gray_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a 16-bit input variable, IN, holding the 16-bit Binary input, and a 16-bit output variable, OUT, holding the 16-bit gray code of the input IN. IN consists of two 8-bit variables, INH and INL. INH holds the high byte of IN, and INL holds the low byte of IN. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT,

Conversion Macros

FIGURE 6.22 The macro “Segment_CCD”.

413

414

Programmable Logic Controller

FIGURE 6.22 Continued

and OUTL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts a 16-bit binary value IN to its 16-bit gray code OUT. Figure 6.31 shows the representation of the 16-bit binary to 16-bit gray code conversion, involving a 16-bit input variable IN and a 16-bit output variable OUT. Likewise, Figure 6.32 shows the representation of the 16-bit binary to 16-bit gray code conversion, involving a 16-bit input variable IN, consisting of two 8-bit variables, INH and INL, and a 16-bit output variable OUT, consisting of two 8-bit variables, OUTH and OUTL. The source data stored in the 16-bit variable IN remain unchanged. Similarly, when the “Conv_Bin_2_Gray_16” instruction is not enabled, the 16-bit output variable OUT remains unchanged. Table 6.17 shows some example input and output values for the “Conv_Bin_2_Gray_16” macro. Assumption: The operands “INH”, “INL”, “OUTH”, and “OUTL” can be in any Bank.

6.12

MACRO “CONV_GRAY_2_BIN” (GRAY CODE TO BINARY CONVERSION)

The following steps briefy show how to perform the gray code to binary conversion:

FIGURE 6.23 The fowchart of the macro “Segment_CCD”.

Conversion Macros 415

416

Programmable Logic Controller

TABLE 6.12 Symbol of the Macro “Segment_CAD” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit input variable, IN) OUT (8-bit output variable, OUT)

1. To convert gray code to binary, bring down the MSB of the given number in gray code, because the frst bit or the MSB of the number in gray code is the same as the binary number. 2. To obtain the successive second binary bit, perform the addition of the frst bit or the MSB of the binary number and the second bit from the left of the given gray code. 3. To obtain the successive third binary bit, perform the addition of the second bit from the left of the binary number and the third bit from the left of the gray code, and so on for the next successive binary bit’s conversion to fnd the equivalent. Recall that the addition of two bits is carried out by means of a two-input EX-OR gate. The symbol of the macro “Conv_Gray_2_Bin” is shown in Table 6.18. Figures 6.33 and 6.34 show the macro “Conv_Gray_2_Bin” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has an 8-bit input variable, IN, holding the gray coded 8-bit input, and an 8-bit output variable, OUT, holding the 8-bit binary value obtained from the IN. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts the gray coded 8-bit input IN to its 8-bit binary value OUT. Figure 6.35 shows the representation of 8-bit gray code to 8-bit binary conversion. The source data stored in the 8-bit variable IN remain unchanged. Similarly, when the “Conv_Gray_2_Bin” instruction is not enabled, the output variable OUT remains unchanged. Table 6.19 shows some example input and output values for the “Conv_Gray_2_Bin” macro. Assumption: The operands “IN” and “OUT” can be in any Bank. In this macro (Conv_Gray_2_Bin) and in the next macro (Conv_Gray_2_Bin_16), the command “#v(expr)” is utilized. The reader is referred to Chapter 4, Section 4.5, Macro “max _5”, of the Intermediate Concepts volume, for a brief explanation about the command “#v(expr)”.

417

Conversion Macros

TABLE 6.13 Seven-Segment Common Anode Display Coding (IN) LSD Hex Value

(IN) LSD 3210

Seven-Segment Display

(OUT) 7 6 5 43 2 1 0 - g f ed c b a

(OUT) Hex Value

0

0000

1 1 0 00 0 0 0

C0

1

0001

1 1 1 11 0 0 1

F9

2

0010

1 0 1 00 1 0 0

A4

3

0011

1 0 1 10 0 0 0

B0

4

0100

1 0 0 11 0 0 1

99

5

0101

1 0 0 10 0 1 0

92

6

0110

1 0 0 00 0 1 0

82

7

0111

1 1 1 11 0 0 0

F8

8

1000

1 0 0 00 0 0 0

80

9

1001

1 0 0 10 0 0 0

90

A

1010

1 0 0 01 0 0 0

88

B

1011

1 0 0 00 0 1 1

83 (Continued )

418

Programmable Logic Controller

TABLE 6.13 (CONTINUED) Seven-Segment Common Anode Display Coding (IN) LSD Hex Value

(IN) LSD 3210

Seven-Segment Display

(OUT) 7 6 5 43 2 1 0 - g f ed c b a

(OUT) Hex Value

C

1100

1 1 0 00 1 1 0

C6

D

1101

1 0 1 00 0 0 1

A1

E

1110

1 0 0 00 1 1 0

86

F

1111

1 0 0 01 1 1 0

8E

6.13

MACRO “CONV_GRAY_2_BIN_16” (GRAY CODE TO BINARY CONVERSION)

The symbol of the macro “Conv_Gray_2_Bin_16” is shown in Table 6.20. Figures 6.36 and 6.37 show the macro “Conv_Gray_2_Bin_16” and its fowchart, respectively. In this macro, EN is a Boolean-input-variable taken into the macro through W, and ENO is a Boolean-output-variable sent out from the macro through W. Output ENO follows the input EN. This means that, when EN=0, ENO is forced to be 0, and, when EN=1, ENO is forced to be 1. Additionally, this macro has a 16-bit input variable, IN, holding the gray coded 16-bit input, and a 16-bit output variable, OUT, holding the 16-bit binary value obtained from IN. IN consists of two 8-bit variables, INH and INL. INH holds the high byte of IN, and INL holds the low byte of IN. OUT consists of two 8-bit variables, OUTH and OUTL. OUTH holds the high byte of OUT, and OUTL holds the low byte of OUT. The Boolean-enable-input signal EN should be loaded into “W” before this macro is invoked. When EN = 0, no action is taken. When enabled (EN = 1), this macro converts the gray coded 16-bit input IN to its 16-bit binary value OUT. Figure 6.38 shows the representation of the 16-bit gray code to 16-bit binary conversion, involving a 16-bit input variable IN and a 16-bit output variable OUT. Likewise, Figure 6.39 shows the representation of the 16-bit gray code to 16-bit binary conversion, involving a 16-bit input variable, IN, consisting of two 8-bit variables, INH and INL, and a 16-bit output variable, OUT, consisting of two 8-bit variables, OUTH and OUTL. The source data stored in the 16-bit variable IN remain unchanged. Similarly, when the “Conv_Gray_2_Bin_16” instruction is not enabled, the 16-bit output variable OUT remains unchanged. Table 6.21 shows some example input and output values for the “Conv_Gray_2_Bin_16”

Conversion Macros

FIGURE 6.24 The macro “Segment_CAD”.

419

420

Programmable Logic Controller

FIGURE 6.24 Continued

macro. Assumption: The operands “INH”, “INL”, “OUTH”, and “OUTL” can be in any Bank.

6.14

EXAMPLES FOR CONVERSION MACROS

Up to now in this chapter, we have seen conversion macros developed for the PIC16F1847Based PLC. It is now time to consider some examples related to these macros. Before you can run the example programs considered here, you are expected to construct your own PIC16F1847-Based PLC hardware by using the necessary PCB fles and by producing your PCBs, with their components. For effective use of examples, all example programs considered in this book are allocated within the fle “PICPLC_PIC16F1847 _user_Int.inc”, which is downloadable from this book’s webpage under the downloads section. Initially, all example programs are commented out by putting a semicolon, “;”, in front of each line. When you would like to test one of the example programs, you must uncomment each line of the example program by following the steps shown below: 1. Highlight the block of source lines you want to uncomment by dragging the mouse with the left mouse button held down over these lines. With default coloring in MPLAB X IDE, you will now see green characters on a blue background. 2. Release the mouse button.

FIGURE 6.25

The fowchart of the macro “Segment_CAD”.

Conversion Macros 421

422

Programmable Logic Controller

TABLE 6.14 Symbol of the Macro “Conv_Bin_2_Gray” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit input variable, holding the 8-bit Binary input, IN) OUT (8-bit output variable, holding the 8-bit Gray Code obtained from the input IN, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 6.26 The macro “Conv_Bin_2_Gray”.

3. Press Ctrl/Shift/C or press “Alt”, “S”, and “M” keys in succession or, from the toolbar “Source” menu, select “Toggle Comment”. Now, a semicolon will be removed from all selected source lines. With default coloring, you will see red characters on a white background. Then, you can run the project by pressing the symbol from the toolbar. Next, the MPLAB X IDE will produce the “PICPLC_PIC16F1847.X.production.hex” fle for the project. Then, the MPLAB X IDE will be connected to the PICkit3 programmer and,

Conversion Macros

FIGURE 6.27

423

The fowchart of the macro “Conv_Bin_2_Gray”.

fnally, it will program the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC. During these steps, make sure that, in the CPU board of the PIC16F1847-Based PLC, the 4PDT switch is in the “PROG” position and the power switch is in the “OFF” position. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Finally, you are ready to test the example program. Warning: When you fnish your study with an example and try to take a look at another example, do not forget to comment the current example program before uncommenting another one. In other words, make sure that only one example program is uncommented and tested at the same time. Otherwise, if you somehow leave more than one example uncommented,

424

Programmable Logic Controller

FIGURE 6.28

Representation of 8-bit binary to 8-bit gray code conversion.

the example you are trying to test probably will not function as expected as it may try to access the same resources that are being used and changed by other examples. Please check the accuracy of each program by cross-referencing it with the related macros.

6.14.1 EXAMPLE 6.1 Example 6.1 shows the usage of the conversion macro “Conv_UsInt_2_BCD_U”. The user program of Example 6.1 is shown in Figure 6.40. The schematic diagram of Example 6.1 is depicted in Figure 6.41. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user TABLE 6.15 Some Example Input and Output Values for the “Conv_Bin_2_Gray” Macro IN (8-Bit Binary Input)

OUT (8-Bit Gray Coded Output)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

0

1

0

0

1

0

0

1

1

1

1

0

1

1

0

0 1 0 1 0 1

0 1 1 0 0 1

1 0 1 0 1 0

1 0 0 0 1 1

0 1 0 1 1 0

1 1 1 0 0 0

0 0 1 1 0 1

1 0 1 0 0 1

0 1 0 1 0 1

0 0 1 1 0 0

1 1 0 0 1 1

0 0 1 0 0 1

1 1 0 1 0 1

1 0 1 1 1 0

1 1 0 1 0 1

1 0 0 1 0 0

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

Conversion Macros

425

TABLE 6.16 Symbol of the Macro “Conv_Bin_2_Gray_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 INH (8-bit input variable, holding the High byte of the 16-bit Binary input IN, INH) INL (8-bit input variable, holding the Low byte of the 16-bit Binary input IN, INL) OUTH (8-bit output variable, holding the High byte of the 16-bit Gray code obtained from the input IN, OUTH) OUTL (8-bit output variable, holding the Low byte of the 16-bit Gray code obtained from the input IN, OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

FIGURE 6.29 The macro “Conv_Bin_2_Gray_16”.

426

FIGURE 6.30

Programmable Logic Controller

The fowchart of the macro “Conv_Bin_2_Gray_16”.

_Int.inc”, if you uncomment Example 6.1 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

Conversion Macros

427

FIGURE 6.31 Representation of 16-bit binary to 16-bit gray code conversion - 1.

In rung 1, the conversion macro “Conv_UsInt_2_BCD_U” (Unsigned Short Integer to Unpacked BCD Conversion) is used. In this conversion macro, the input variable is UsInt = I0, and the output variables are Hund = Q2, Tens = Q1, and Ones = Q0. In addition, the active-high enable input E is defned to be E = I1.0.

6.14.2

EXAMPLE 6.2

Example 6.2 shows the usage of the conversion macro “Conv_UsInt_2_BCD_P”. The user program of Example 6.2 is shown in Figure 6.42. The schematic diagram of Example 6.2 is depicted in Figure 6.43. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 6.2 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

428

Programmable Logic Controller

FIGURE 6.32

Representation of 16-bit binary to 16-bit gray code conversion - 2.

In rung 1, the conversion macro “Conv_UsInt_2_BCD_P” (Unsigned Short Integer to Packed BCD Conversion) is used. In this conversion macro, the input variable is UsInt = I0, and the output variables are bcd1 = Q1 and bcd0 = Q0. In addition, the active-high enable input E is defned to be E = I1.0.

6.14.3

EXAMPLE 6.3

Example 6.3 shows the usage of the conversion macro “Conv_UInt_2_BCD_U”. The user program of Example 6.3 is shown in Figure 6.44. The schematic diagram of Example 6.3 is depicted in Figure 6.45. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 6.3 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the conversion macro “Conv_UInt_2_BCD_U” (Unsigned Integer to Unpacked BCD Conversion) is used. In this conversion macro, the input variables are NumH = I1 and NumL = I0, and the output variables are TenK

6

1 1 1 0 0 1 1

0

7

1 0 1 0 1 0 1

1

0

1 0 0 1 0 0 1

5

1

1 1 1 1 0 0 0

4

1

0 0 0 1 1 0 1

3

0

0 1 0 0 1 0 0

2

1

0 0 1 1 0 0 1

1

INH (High Byte of 16-Bit Binary Input)

1

0 0 1 0 1 1 0

0

1

1 1 0 1 0 1 0

7

1

0 1 0 0 0 1 1

6

0

0 0 1 0 1 0 1

5

0

1 1 0 1 1 1 0

4

0

1 1 1 0 1 0 1

3

1

0 1 0 1 0 0 1

2

1

1 0 1 0 1 0 1

1

INL (Low Byte of 16-Bit Binary Input)

IN (16-Bit Binary Input)

0

1 0 0 1 1 0 0

0

1

1 0 1 0 1 0 1

7

1

0 1 0 0 1 1 0

6

0

0 1 1 1 0 1 0

5

1

0 1 1 0 0 0 1

4

0

1 1 1 0 1 0 1

3

1

0 1 0 1 0 0 1

2

1

0 1 1 1 1 0 1

1

0

0 0 0 1 1 1 1

0

0

1 1 1 1 1 0 0

7

0

1 0 0 1 0 0 1

6

1

0 1 1 0 1 1 0

5

0

1 1 1 1 0 1 1

4

0

0 0 1 1 0 1 1

3

1

1 0 1 1 1 0 0

2

0

1 1 1 1 1 0 0

1

OUTL (Low Byte of 16-Bit Gray Coded Output)

OUT (16-Bit Gray Coded Output) OUTH (High Byte of 16-Bit Gray Coded Output)

TABLE 6.17 Some Example Input and Output Values for the “Conv_Bin_2_Gray_16” Macro

1

0 0 1 1 0 0 1

0

Conversion Macros 429

430

Programmable Logic Controller

TABLE 6.18 Symbol of the Macro “Conv_Gray_2_Bin” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 IN (8-bit input variable, holding the Gray Coded 8-bit input, IN) OUT (8-bit output variable, holding the 8-bit Binary value obtained from the IN, OUT) ENO (Boolean-enable-output, through W) = 0 or 1

= M4, Thou = M3, Hund = Q2, Tens = Q1, and Ones = Q0. In addition, the active-high enable input E is defned to be E = I2.0. In rung 2, the byte multiplexer macro “B_mux_2_1_E” (2×1 Byte Multiplexer with Active-High Enable Input; Chapter 4 of the Intermediate Concepts volume) is used. In this byte multiplexer, input variables are R1 = M4 and R0 = M3, the output variable is Y = Q3, and the select input is s0 = I3.1. In addition, the active-high enable input E is defned to be E = I3.0. This byte multiplexer is used to observe the contents of M4 and M3 through the output byte Q3.

6.14.4

EXAMPLE 6.4

Example 6.4 shows the usage of the conversion macro “Conv_UInt_2_BCD_P”. The user program of Example 6.4 is shown in Figure 6.46. The schematic diagram of Example 6.4 is depicted in Figure 6.47. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847 _user_Int.inc”, if you uncomment Example 6.4 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the conversion macro “Conv_UInt_2_BCD_P” (Unsigned Integer to Packed BCD Conversion) is used. In this conversion macro, the input variables are NumH = I1 and NumL = I0, and the output variables are bcd2 = Q2, bcd1 = Q1, and bcd0 = Q0. In addition, the active-high enable input E is defned to be E = I2.0.

Conversion Macros

FIGURE 6.33

431

The macro “Conv_Gray_2_Bin”.

6.14.5 EXAMPLE 6.5 Example 6.5 shows the usage of the conversion macro “Conv_BCD_U_2_UInt”. The user program of Example 6.5 is shown in Figure 6.48. The schematic diagram of Example 6.5 is depicted in Figure 6.49. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 6.5 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, as EN = FRSTSCN, during the frst PLC scan time, by using the “load_R” function the following load operation is carried out: the constant value 9 (decimal) is loaded into the output register M4.

432

FIGURE 6.34

Programmable Logic Controller

The fowchart of the macro “Conv_Gray_2_Bin”.

In rung 2, the conversion macro “Conv_BCD_U_2_UInt” (5-Digit Unpacked BCD to Unsigned Integer Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variables are nTenK = M4, nThou = I3, nHund = I2, nTens = I1, and nOnes = I0, and the output variables are NumH = Q1 and NumL = Q0. In rung 3, the state of the carry fag is sent to the output bit Q2.0, i.e., Q2.0 := STATUS,C.

433

Conversion Macros

FIGURE 6.35 Representation of 8-bit gray code to 8-bit binary conversion.

6.14.6 EXAMPLE 6.6 Example 6.6 shows the usage of the conversion macro “Conv_BCD_P_2_UInt”. The user program of Example 6.6 is shown in Figure 6.50. The schematic diagram of Example 6.6 is depicted in Figure 6.51. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 6.6 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. TABLE 6.19 Some Example Input and Output Values for the “Conv_Gray_2_Bin” Macro IN (8-Bit Gray Coded Input)

OUT (8-Bit Binary Output)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

1

1

1

1

0

1

1

0

1

0

1

0

0

1

0

0

0 1 0 1 0 1

0 0 1 1 0 0

1 1 0 0 1 1

0 0 1 0 0 1

1 1 0 1 0 1

1 0 1 1 1 0

1 1 0 1 0 1

1 0 0 1 0 0

0 1 0 1 0 1

0 1 1 0 0 1

1 0 1 0 1 0

1 0 0 0 1 1

0 1 0 1 1 0

1 1 1 0 0 0

0 0 1 1 0 1

1 0 1 0 0 1

1

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

434

Programmable Logic Controller

TABLE 6.20 Symbol of the Macro “Conv_Gray_2_Bin_16” Symbol

EN (Boolean-enable-input, through W) = 0 or 1 INH (8-bit input variable, holding the High byte of Gray Coded 16-bit input IN, INH) INL (8-bit input variable, holding the Low byte of Gray Coded 16-bit input IN, INL) OUTH (8-bit output variable, holding the High byte of 16-bit Binary value obtained from the IN, OUTH) OUTL (8-bit output variable, holding the Low byte of 16-bit Binary value obtained from the IN, OUTL) ENO (Boolean-enable-output, through W) = 0 or 1

In rung 1, the conversion macro “Conv_BCD_P_2_UInt” (5-Digit Packed BCD to Unsigned Integer Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variables are bcd2 = I2, bcd1 = I1, and bcd0 = I0, and the output variables are NumH = Q1 and NumL = Q0. In rung 2, the state of the carry fag is sent to the output bit Q2.0, i.e., Q2.0 := STATUS,C.

6.14.7

EXAMPLE 6.7

Example 6.7 shows the usage of the conversion macro “Segment_CCD”. The user program of Example 6.7 is shown in Figure 6.52. The schematic diagram of Example 6.7 is depicted in Figure 6.53. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847 _user_Int.inc”, if you uncomment Example 6.7 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the conversion macro “Segment_CCD” (Segment_CCD Instruction) is used. In this conversion macro, the input variable IN = I0, and the output variable OUT = Q0. In addition, the active-high enable input E is defned to be E = I2.0.

Conversion Macros

FIGURE 6.36

435

The macro “Conv_Gray_2_Bin_16”.

6.14.8 EXAMPLE 6.8 Example 6.8 shows the usage of the conversion macro “Segment_CAD”. The user program of Example 6.8 is shown in Figure 6.54. The schematic diagram of Example 6.8 is depicted in Figure 6.55. When the project fle of the PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user_Int.inc”, if you uncomment Example 6.8 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

436

FIGURE 6.36

Programmable Logic Controller

Continued

In rung 1, the conversion macro “Segment_CAD” (Segment_CAD Instruction) is used. In this conversion macro, the input variable IN = I1, and the output variable OUT = Q1. In addition, the active-high enable input E is defned to be E = I3.0.

6.14.9 EXAMPLE 6.9 Example 6.9 shows the usage of the conversion macro “Conv_Bin_2_Gray”. The user program of Example 6.9 is shown in Figure 6.56. The schematic diagram of Example 6.9 is depicted in Figure 6.57. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 6.9 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the conversion macro “Conv_Bin_2_Gray” (Binary to Gray Code Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variable IN = I0, and the output variable OUT = Q0.

Conversion Macros

437

FIGURE 6.37 The fowchart of the macro “Conv_Gray_2_Bin_16”.

In rung 2, the conversion macro “Conv_Bin_2_Gray” (Binary to Gray Code Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variable IN = I1, and the output variable OUT = Q1.

6.14.10 EXAMPLE 6.10 Example 6.10 shows the usage of the conversion macro “Conv_Bin_2_Gray_16”. The user program of Example 6.10 is shown in Figure 6.58. The schematic diagram of Example 6.10 is depicted in Figure 6.59. When the project fle of the

438

FIGURE 6.38

Programmable Logic Controller

Representation of 16-bit gray code to 16-bit binary conversion - 1.

PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_ PIC16F1847_user_Int.inc”, if you uncomment Example 6.10 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the conversion macro “Conv_Bin_2_Gray_16” (Binary to Gray Code Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variables are INH = I1 and INL = I0, and the output variables are OUTH = Q1 and OUTH = Q0. In rung 2, the conversion macro “Conv_Bin_2_Gray_16” (Binary to Gray Code Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variables are INH = I3 and INL = I2, and the output variables are OUTH = Q3 and OUTH = Q2.

Conversion Macros

439

FIGURE 6.39 Representation of 16-bit gray code to 16-bit binary conversion - 2.

6.14.11 EXAMPLE 6.11 Example 6.11 shows the usage of the conversion macro “Conv_Gray_2_Bin”. The user program of Example 6.11 is shown in Figure 6.60. The schematic diagram of Example 6.11 is depicted in Figure 6.61. When the project fle of the PIC16F1847Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_PIC16F1847_user _Int.inc”, if you uncomment Example 6.11 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example. In rung 1, the conversion macro “Conv_Gray_2_Bin” (Gray Code to Binary Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variable IN = I0, and the output variable OUT = Q0. In rung 2, the conversion macro “Conv_Gray_2_Bin” (Gray Code to Binary Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variable IN = I1, and the output variable OUT = Q1.

6

0 1 0 0 1 1 0

1

7

1 0 1 0 1 0 1

1

0

0 1 1 1 0 1 0

5

1

0 1 1 0 0 0 1

4

0

1 1 1 0 1 0 1

3

1

0 1 0 1 0 0 1

2

1

0 1 1 1 1 0 1

1

INH (High Byte of 16-Bit Gray Coded Input)

0

0 0 0 1 1 1 1

0

0

1 1 1 1 1 0 0

7

0

1 0 0 1 0 0 1

6

1

0 1 1 0 1 1 0

5

0

1 1 1 1 0 1 1

4

0

0 0 1 1 0 1 1

3

1

1 0 1 1 1 0 0

2

0

1 1 1 1 1 0 0

1

1

0 0 1 1 0 0 1

0

INL (Low Byte of 16-Bit Gray Coded Input)

IN (16-Bit Gray Coded Input)

1

1 0 1 0 1 0 1

7

0

1 1 1 0 0 1 1

6

0

1 0 0 1 0 0 1

5

1

1 1 1 1 0 0 0

4

1

0 0 0 1 1 0 1

3

0

0 1 0 0 1 0 0

2

1

0 0 1 1 0 0 1

1

1

0 0 1 0 1 1 0

0

1

1 1 0 1 0 1 0

7

1

0 1 0 0 0 1 1

6

0

0 0 1 0 1 0 1

5

0

1 1 0 1 1 1 0

4

0

1 1 1 0 1 0 1

3

1

0 1 0 1 0 0 1

2

1

1 0 1 0 1 0 1

1

0

1 0 0 1 1 0 0

0

OUTL (Low Byte of 16-Bit Binary Output)

OUT (16-Bit Binary Output) OUTH (High Byte of 16-Bit Binary Output)

TABLE 6.21 Some Example Input and Output Values for the “Conv_Gray_2_Bin_16” Macro

440 Programmable Logic Controller

Conversion Macros

441

FIGURE 6.40 The user program of “Example 6.1”.

FIGURE 6.41 The schematic diagram of the user program of “Example 6.1”.

FIGURE 6.42

The user program of “Example 6.2”.

FIGURE 6.43

The schematic diagram of the user program of “Example 6.2”.

6.14.12 EXAMPLE 6.12 Example 6.12 shows the usage of the conversion macro “Conv_Gray_2_Bin_16”. The user program of Example 6.12 is shown in Figure 6.62. The schematic diagram of Example 6.12 is depicted in Figure 6.63. When the project fle of the

442

Programmable Logic Controller

FIGURE 6.44 The user program of “Example 6.3”.

FIGURE 6.45 The schematic diagram of the user program of “Example 6.3”.

FIGURE 6.46 The user program of “Example 6.4”.

Conversion Macros

FIGURE 6.47

The schematic diagram of the user program of “Example 6.4”.

FIGURE 6.48 The user program of “Example 6.5”.

FIGURE 6.49

The schematic diagram of the user program of “Example 6.5”.

443

444

Programmable Logic Controller

FIGURE 6.50 The user program of “Example 6.6”.

FIGURE 6.51

The schematic diagram of the user program of “Example 6.6”.

FIGURE 6.52 The user program of “Example 6.7”.

FIGURE 6.53

The schematic diagram of the user program of “Example 6.7”.

Conversion Macros

FIGURE 6.54

The user program of “Example 6.8”.

FIGURE 6.55

The schematic diagram of the user program of “Example 6.8”.

FIGURE 6.56

The user program of “Example 6.9”.

FIGURE 6.57

The schematic diagram of the user program of “Example 6.9”.

445

446

Programmable Logic Controller

FIGURE 6.58 The user program of “Example 6.10”.

FIGURE 6.59 The schematic diagram of the user program of “Example 6.10”.

FIGURE 6.60 The user program of “Example 6.11”.

Conversion Macros

447

FIGURE 6.61 The schematic diagram of the user program of “Example 6.11”.

PIC16F1847-Based PLC is open in the MPLAB X IDE, from the fle “PICPLC_ PIC16F1847_user_Int.inc”, if you uncomment Example 6.12 and run the project by pressing the symbol from the toolbar, then the PIC16F1847 microcontroller within the CPU board of the PIC16F1847-Based PLC will be programmed. After loading the program fle to the PIC16F1847 microcontroller, switch the 4PDT to “RUN” and the power switch to the “ON” position. Next, you can test the operation of this example.

FIGURE 6.62 The user program of “Example 6.12”.

FIGURE 6.63 The schematic diagram of the user program of “Example 6.12”.

448

Programmable Logic Controller

In rung 1, the conversion macro “Conv_Gray_2_Bin_16” (Gray Code to Binary Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variables are INH = I1 and INL = I0, and the output variables are OUTH = Q1 and OUTH = Q0. In rung 2, the conversion macro “Conv_Gray_2_Bin_16” (Gray Code to Binary Conversion) is used. As the active-high enable input is E = LOGIC1, this macro is always enabled. In this conversion macro, the input variables are INH = I3 and INL = I2, and the output variables are OUTH = Q3 and OUTH = Q2.

REFERENCES R6.1. 116-bit to 5-digit conversion written by John Payson & explained by Scott Dattalo www .piclist.com/techref/microchip/math/radix/b2bu-16b5d.htm (accessed on 11.06.2016). R6.2. Unpacked 5-digit BCD to 16-bit binary conversion written by Peter Hemsley www.p iclist.com/techref/microchip/math/radix/bu2b-5d16b-ph.htm (accessed on 11.06.2016).

About the Downloadable Files for Intermediate Concepts Downloadable fles of this book contain source and example fles defned for the intermediate concepts of PIC16F1847-Based PLC project. These fles are downloadable from this book’s webpage under the downloads section. The fles are organised in the following folders: The fles are organised in the following folders: 1. PICPLC_PIC16F1847.X (a folder containing MPLAB project fles) 2. PICPLC_PIC16F1847_macros_Int.inc (fles for PLC macros defned for the Intermediate Concepts) 3. PICPLC_PIC16F1847_main.asm (main program fle) 4. PICPLC_PIC16F1847_memory.inc (memory related defnitions) 5. PICPLC_PIC16F1847_subr.inc (subroutine defnitions) 6. PICPLC_PIC16F1847_user_Int.inc (user program fles and Application Example fles – for the Intermediate Concepts) Files “PICPLC_PIC16F1847_macros_Int.inc” and “PICPLC_PIC16F1847_user_Int. inc” refer to macros and user program fles of the intermediate concepts developed in the PIC16F1847-Based PLC project, respectively. They do not contain fles related to the basic and advanced concepts. These two fles are intended for the readers who purchased this book as a standalone book. On the other hand, when this book is purchased as a part of the set of three books, all project fles including basic, intermediate and advanced concepts are put in the same directory and the reader is entitled to download and use the whole project fles in one directory, the name of the which becomes “PICPLC_PIC16F1847” instead of “PICPLC_PIC16F1847_Int”. Therefore, in the second case the name of the fle “PICPLC_PIC16F1847_macros_Int.inc” (respectively, PICPLC_PIC16F1847_user_Int.inc) becomes “PICPLC_PIC16F1847_ macros.inc” (respectively, PICPLC_PIC16F1847_user.inc).

449

Index #v(expr), 203, 416 1 × 2 byte demultiplexer with enable input, 321, 331, 333, 365 1 × 2 DMUX, 321, 322, 353 1 × 2 DMUX with enable input, 321, 322, 353 1 × 4 byte demultiplexer with enable input, 321, 334, 367 1 × 4 DMUX, 321, 323, 357 1 × 4 DMUX with enable input, 321, 323, 357 1 × 8 byte demultiplexer with enable input, 321, 336, 369 1 × 8 dispatcher with enable input, 321, 339, 375 1 × 8 DMUX, 321, 325, 359 1 × 8 DMUX with enable input, 321, 325, 359 1 × 16 DMUX, 321, 330, 361 1 × 16 DMUX with enable input, 321, 330, 361 1-to-n demultiplexer, 321, 322 2 × 1 byte multiplexer with enable input, 197, 236, 313, 314, 430 2 × 1 MUX, 197, 230, 231, 252, 253, 303–306 2 × 1 MUX with enable input, 197, 230, 254, 255, 303–306 4 × 1 byte multiplexer with enable input, 197, 237, 316, 317 4 × 1 MUX, 197, 231, 232, 255–257, 306–308 4 × 1 MUX with enable input, 197, 231, 257–259, 306–308 5 digit packed BCD to unsigned integer conversion, 379, 392, 395, 405, 408, 409, 433, 434 5 digit unpacked BCD to unsigned integer conversion, 379, 389, 392, 395, 399, 400, 403, 404, 408, 431, 432 7-segment LED displays, 395 8 × 1 byte multiplexer with enable input, 197, 238, 318 8 × 1 Patcher with enable input, 321, 341, 377 8 × 1 MUX, 197, 233, 234, 259, 260, 262, 308, 309 8 × 1 MUX with enable input, 197, 233, 263, 264, 266, 308–310 16 × 1 MUX, 197, 234, 236, 267, 268, 271, 310–312 16 × 1 MUX with enable input, 197, 235, 272, 273, 276, 310, 312, 313

A ADD, 1, 2 Arithmetic Shift Right Rin (Ashift_R), 85–88, 129

Arithmetic Shift Right Rin (Ashift_R_16), 85, 87, 89–92, 129 Arithmetical functions, 1 Arithmetical macros decR, 1, 17, 18, 44 decR_16, 2, 19, 20, 44 DivU16by8, 1, 14, 15, 43 examples for, 33–50 Hbit_CNT, 2, 19–24, 26–28, 30, 44, 47, 48, 50 incR, 1, 15, 44 incR_16, 1, 16, 17, 44 Lbit_CNT, 2, 30–33, 44, 47, 48, 50 R1addR2, 1, 2, 34 R1addR2_16, 1, 3, 4, 37 R1mulR2, 1, 12, 13, 42 R1subR2, 1, 7, 8, 34 R1subR2_16, 1, 8, 9, 38 RaddK, 1, 5, 6, 34 RaddK_16, 1, 6, 7, 39, 41 RsubK, 1, 10, 11, 34 RsubK_16, 1, 12, 39, 41, 42 Ashift_R, 85–88, 129 Ashift_R_16, 85, 87, 89–92, 129

B B_Dmux_1_2_E, 321, 331, 333, 365 B_Dmux_1_4_E, 321, 334, 367 B_Dmux_1_8_E, 321, 336, 369 B_mux_2_1_E, 197, 236, 313, 314, 430 B_mux_4_1_E, 197, 237, 316, 317 B_mux_8_1_E, 197, 238, 318 Binary to Gray code conversion, 410–413

C Conv_BCD_P_2_UInt, 379, 392, 395, 405, 408, 409, 433, 434 Conv_BCD_U_2_UInt, 379, 389, 392, 395, 399, 400, 403, 404, 408, 431, 432 Conv_Bin_2_Gray, 379, 410, 412, 422–424, 436, 437 Conv_Bin_2_Gray_16, 379, 412, 414, 425, 426, 429, 438 Conv_Gray_2_Bin, 379, 414, 416, 430–433, 439 Conv_Gray_2_Bin_16, 379, 418, 434, 435, 437, 440, 441, 448 Conv_UInt_2_BCD_U, 379, 385, 389, 390, 393, 394, 398, 428 Conv_UInt_2_BCD_P, 379, 386, 388, 389, 395, 396, 398, 399, 430

451

452 Conv_UsInt_2_BCD_U, 379, 380, 381–384, 424, 427 Conv_UsInt_2_BCD_P, 379, 383, 385–388, 427, 428 Conversion macros, Conv_BCD_P_2_UInt, 379, 392, 395, 405, 408, 409, 433, 434 Conv_BCD_U_2_UInt, 379, 389, 392, 395, 399, 400, 403, 404, 408, 431, 432 Conv_Bin_2_Gray, 379, 410, 412, 422–424, 436, 437 Conv_Bin_2_Gray_16, 379, 412, 414, 425, 426, 429, 438 Conv_Gray_2_Bin, 379, 414, 416, 430–433, 439 Conv_Gray_2_Bin_16, 379, 418, 434, 435, 437, 440, 441, 448 Conv_UInt_2_BCD_U, 379, 385, 389, 390, 393, 394, 398, 428 Conv_UInt_2_BCD_P, 379, 386, 388, 389, 395, 396, 398, 399, 430 Conv_UsInt_2_BCD_U, 379, 380, 381–384, 424, 427 Conv_UsInt_2_BCD_P, 379, 383, 385–388, 427, 428 Segment_CAD, 379, 406, 410, 416, 419, 421, 435, 436 Segment_CCD, 379, 399, 400, 410, 413, 415, 434 examples for, 420–447

D DEC, 1 decR, 1, 17, 18, 44 decR_16, 2, 19, 20, 44 Decrement functions, 1 Demultiplexer macros B_Dmux_1_2_E, 321, 331, 333, 365 B_Dmux_1_4_E, 321, 334, 367 B_Dmux_1_8_E, 321, 336, 369 Dispatcher_1_8_E, 321, 339, 375 Dmux_1_2, 321, 322, 353 Dmux_1_2_E, 321, 322, 353 Dmux_1_4, 321, 323, 357 Dmux_1_4_E, 321, 323, 357 Dmux_1_8, 321, 325, 359 Dmux_1_8_E, 321, 325, 359 Dmux_1_16, 321, 330, 361 Dmux_1_16_E, 321, 330, 361 examples for, 346–377 Demultiplexers (DMUX), 321 Destination registers, shift functions in, 85 Dispatcher_1_8_E, 321, 339, 375 DivU16by8, 1, 14, 15, 43 Dmux_1_2, 321, 322, 353 Dmux_1_2_E, 321, 322, 353

Index Dmux_1_4, 321, 323, 357 Dmux_1_4_E, 321, 323, 357 Dmux_1_8, 321, 325, 359 Dmux_1_8_E, 321, 325, 359 Dmux_1_16, 321, 330, 361 Dmux_1_16_E, 321, 330, 361

E Example programs, arithmetical macros, 33–50 conversion macros, 420–447 demultiplexer macros, 346–377 logical macros, 76–83 selection macros, 241–319 shift and rotate macros, 122–195

F fowchart, 2–20, 23, 30, 32, 53, 55–60, 62–73, 75, 86–91, 93, 94, 97, 99–101, 103, 105, 106, 109, 110, 112, 113, 115, 116, 118, 119, 121, 124, 127, 129, 198–203, 205, 208–211, 213, 214, 216–218, 221–225, 227, 228, 230, 231, 233–238, 240, 244, 247, 251, 253, 255, 257, 259, 262, 266, 271, 276, 278, 280, 283, 322–326, 328, 330, 331, 334–336, 339–341, 345, 350, 352, 354, 358, 362, 366, 380, 382, 383, 387, 400, 406, 410, 412, 415, 416, 418, 421, 423, 426, 432, 437

G Gray code to binary conversion, 414–448

H Hbit_CNT, 2, 19–24, 26–28, 30, 44, 47, 48, 50 High bit counter (Hbit_CNT), 2, 19–24, 26–28, 30, 44, 47, 48, 50

I INC, 1 incR, 1, 15, 44 incR_16, 1, 16, 17, 44 Increment functions, 1 Input signals, 230, 231, 233–235, 303, 304, 306–310, 313, inv_R, 53, 73–75

L ladder diagram, 34, 36–40, 42–44, 46–49, 76, 79, 129, 133, 139, 143, 148, 152, 157, 161, 167, 171, 177, 181, 186, 190

Index Lbit_CNT, 2, 30–33, 44, 47, 48, 50 Least signifcant bit (LSB), 85, 94, 96, 128 limiter, 197, 227, 245–247, 291–293 limiter_16, 197, 228, 248, 249, 251, 296, 300 little endian format, 212, 215, 225, 270, 277, 282, 290, load_R, 34, 40, 44, 197, 198–201, 243, 245, 246, 250, 263, 313, 316, 318, 431 Logic gates, 54 Logical functions, 54 Logical macros, example for, 76–83 inv_R, 53, 73–75 R1andR2, 53, 55, 56 R1nandR2, 53, 57, 58, 59 R1norR2, 53, 64–66 R1orR2, 53, 60–62 R1xnorR2, 53, 71, 72, 82 R1xorR2, 53, 66, 68, 69 RandK, 53, 56–58 RnandK, 53, 58, 60, 61 RnorK, 53, 65–67 RorK, 53, 63, 64 RxnorK, 53, 72–74, 83 RxorK, 53, 69–71 Logical Shift Left Rin (Lshift_L), 85, 93, 94, 98–101, 148 Logical Shift Left Rin (Lshift_L_16), 85, 94, 96, 101–104, 148 Logical Shift Right Rin (Lshift_R), 85, 89, 90, 92–95, 139 Logical Shift Right Rin (Lshift_R_16), 85, 90, 92, 95–98, 139 Low bit counter (Lbit_CNT), 2, 30–33, 44, 47, 48, 50 LSB, See Least signifcant bit Lshift_L, 85, 93, 94, 98–101, 148 Lshift_L_16, 85, 94, 96, 101–104, 148 Lshift_R, 85, 89, 90, 92–95, 139 Lshift_R_16, 85, 90, 92, 95–98, 139

M Macros, arithmetical, 1–32 conversion, 379–419 demultiplexer, 321–345 logical, 53–75 selection, 197–240 shift and rotate, 85–121 Maximum in fve 8-bit variables (max_5), 197, 203, 206–208, 249, 250, 252, 256 Maximum in ten 8-bit variables (max_10), 197, 208–211, 252, 257 Maximum in N 8-bit variables, N = 2, 3, …, 80 (max_N80), 197, 209, 211–213, 258

453 Maximum in N 16-bit variables, N = 2, 3, …, 40 (max_N40_16), 197, 210, 214, 215, 217, 268, 270 Maximum in N 8-bit variables, N = 2, 3, …, 255 (max_N255), 197, 213, 218–220, 252, 261 Maximum in N 16-bit variables, N = 2, 3, …, 255 (max_N255_16), 197, 214, 221, 222, 224, 279, 282 max_5, 197, 203, 206–208, 249, 250, 252, 256 max_10, 197, 208–211, 252, 257 max_N80, 197, 209, 211–213, 258 max_N40_16, 197, 210, 214, 215, 217, 268, 270 max_N255, 197, 213, 218–220, 252, 261 max_N255_16, 197, 214, 221, 222, 224, 279, 282 min_5, 197, 216, 225–227, 261, 263, 265 min_10, 197, 218, 228–230, 263, 265 min_N80, 197, 218, 231–233, 267 min_N40_16, 197, 221, 234, 235, 237, 275 min_N255, 197, 223, 238–240, 263, 267 min_N255_16, 197, 225, 241, 242, 244, 284, 287, 290 Minimum in fve 8-bit variables (min_5), 197, 216, 225–227, 261, 263, 265 Minimum in ten 8-bit variables (min_10), 197, 218, 228–230, 263, 265 Minimum in N 8-bit variables, N = 2, 3, …, 80 (min_N80), 197, 218, 231–233, 267 Minimum in N 16-bit variables, N = 2, 3, …, 40 (min_N40_16), 197, 221, 234, 235, 237, 275 Minimum in N 8-bit variables, N = 2, 3, …, 255 (min_N255), 197, 223, 238–240, 263, 267 Minimum in N 16-bit variables, N = 2, 3, …, 255 (min_N255_16), 197, 225, 241, 242, 244, 284, 287, 290 Most signifcant bit (MSB), 85–87, 89, 90, 92, 128, 410, 416 Move macro, 197, 198, 199, 243, 245 move_R, 197, 198, 199, 243, 245 MSB, See Most signifcant bit Multiplexer, 229 Multiplexer (MUX) macros, mux_2_1, 197, 230, 231, 252, 253, 303–306 mux_2_1_E, 197, 230, 254, 255, 303–306 mux_4_1, 197, 231, 232, 255–257, 306–308 mux_4_1_E, 197, 231, 257–259, 306–308 mux_8_1, 197, 233, 234, 259, 260, 262, 308, 309 mux_8_1_E, 197, 233, 263, 264, 266, 308–310 mux_16_1, 197, 234, 236, 267, 268, 271, 310–312 mux_16_1_E, 197, 235, 272, 273, 276, 310, 312, 313

454 N n-to-1 multiplexers, 229 Number of rotation, 85, 107, 111, 114, 116, 117, 119, 122, 125 Number of shift, 85, 98, 100, 102, 104, 107, 110, 113

O Output lines, 321, 354, 355, 357, 359, 361, 363, 365

P Patcher_8_1_E, 321, 341, 377 Program examples, arithmetical macros, 33–50 conversion macros, 420–447 demultiplexer macros, 346–377 logical macros, 76–83 selection macros, 241–319 shift and rotate macros, 122–195

R R1addR2, 1, 2, 34 R1addR2_16, 1, 3, 4, 37 R1andR2, 53, 55, 56 R1mulR2, 1, 12, 13, 42 R1nandR2, 53, 57, 58, 59 R1norR2, 53, 64–66 R1orR2, 53, 60–62 R1subR2, 1, 7, 8, 34 R1subR2_16, 1, 8, 9, 38 R1xnorR2, 53, 71, 72, 82 R1xorR2, 53, 66, 68, 69 RaddK, 1, 5, 6, 34 RaddK_16, 1, 6, 7, 39, 41 RandK, 53, 56–58 RnandK, 53, 58, 60, 61 RnorK, 53, 65–67 RorK, 53, 63, 64 Rotate function, 85 Rotate macros. See Shift and rotate macros rotate_L, 85, 113, 114, 116, 122–125, 186 rotate_L_16, 85, 116, 117, 125–128, 186 Rotate Left Rin (rotate_L), 85, 113, 114, 116, 122–125, 186 Rotate Left Rin (rotate_L_16), 85, 116, 117, 125–128, 186 rotate_R, 85, 105, 108, 116–119, 177 rotate_R_16, 85, 110, 111, 119–122, 177 Rotate Right Rin (rotate_R), 85, 105, 108, 116–119, 177 Rotate Right Rin (rotate_R_16), 85, 110, 111, 119–122, 177 RsubK, 1, 10, 11, 34

Index RsubK_16, 1, 12, 39, 41, 42 RxnorK, 53, 72–74, 83 RxorK, 53, 69–71

S schematic diagram, 243, 247–249, 252, 261, 263, 270, 275, 282, 285–288, 290–292, 294, 296, 298, 300, 302, 303, 305–319, 353, 357, 359, 361, 365, 367–377, 424, 427, 428, 430, 431, 433–437, 439, 441–447 Segment_CAD, 379, 406, 410, 416, 419, 421, 435, 436 Segment_CCD, 379, 399, 400, 410, 413, 415, 434 select, 197, 200–202, 247, 248 select_16, 197, 201, 203–205, 248, 249 Selection macros B_mux_2_1_E, 197, 236, 313, 314, 430 B_mux_4_1_E, 197, 237, 316, 317 B_mux_8_1_E, 197, 238, 318 examples for, 241–319 limiter, 197, 227, 245–247, 291–293 limiter_16, 197, 228, 248, 249, 251, 296, 300 load_R, 34, 40, 44, 197, 198–201, 243, 245, 246, 250, 263, 313, 316, 318, 431 max_5, 197, 203, 206–208, 249, 250, 252, 256 max_10, 197, 208–211, 252, 257 max_N80, 197, 209, 211–213, 258 max_N40_16, 197, 210, 214, 215, 217, 268, 270 max_N255, 197, 213, 218–220, 252, 261 max_N255_16, 197, 214, 221, 222, 224, 279, 282 min_5, 197, 216, 225–227, 261, 263, 265 min_10, 197, 218, 228–230, 263, 265 min_N80, 197, 218, 231–233, 267 min_N40_16, 197, 221, 234, 235, 237, 275 min_N255, 197, 223, 238–240, 263, 267 min_N255_16, 197, 225, 241, 242, 244, 284, 287, 290 move_R, 197, 198, 199, 243, 245 mux_2_1, 197, 230, 231, 252, 253, 303–306 mux_2_1_E, 197, 230, 254, 255, 303–306 mux_4_1, 197, 231, 232, 255–257, 306–308 mux_4_1_E, 197, 231, 257–259, 306–308 mux_8_1, 197, 233, 234, 259, 260, 262, 308, 309 mux_8_1_E, 197, 233, 263, 264, 266, 308–310 mux_16_1, 197, 234, 236, 267, 268, 271, 310–312 mux_16_1_E, 197, 235, 272, 273, 276, 310, 312, 313 select, 197, 200–202, 247, 248 select_16, 197, 201, 203–205, 248, 249

455

Index Selection of one of two 8-bit input variables (select), 200–202, 247, 248 Selection of one of two 16-bit input variables (select_16), 197, 201, 203–205, 248, 249 shift_L, 85, 101, 102, 110–113, 167 shift_L_16, 85, 103, 105, 113–116, 167 shift_R, 85, 99, 104–107, 157 shift_R_16, 85, 99–101, 107–110, 157 Shift Left Rin (shift_L), 85, 101, 102, 110–113, 167 Shift Left Rin (shift_L_16), 85, 103, 105, 113–116, 167 Shift Right Rin (shift_R), 85, 99, 104–107, 157 Shift Right Rin (shift_R_16), 85, 99–101, 107–110, 157 Shift and rotate macros Ashift_R, 85–88, 129 Ashift_R_16, 85, 87, 89–92, 129 examples for, 195 Lshift_L, 85, 93, 94, 98–101, 148 Lshift_L_16, 85, 94, 96, 101–104, 148 Lshift_R, 85, 89, 90, 92–95, 139 Lshift_R_16, 85, 90, 92, 95–98, 139 rotate_L, 85, 113, 114, 116, 122–125, 186 rotate_L_16, 85, 116, 117, 125–128, 186 rotate_R, 85, 105, 108, 116–119, 177 rotate_R_16, 85, 110, 111, 119–122, 177 shift_L, 85, 101, 102, 110–113, 167 shift_L_16, 85, 103, 105, 113–116, 167 shift_R, 85, 99, 104–107, 157 shift_R_16, 85, 99–101, 107–110, 157 swap, 85, 119, 120, 122, 128, 129, 134, 136, 139, 142, 146, 148, 155, 165, 167, 174, 177, 180, 184, 186, 193, 194 Shift function, 85

shift in bit, 85, 98, 100, 102, 105, 164–167, 170, 173–177 Source variables, 2, 3, 8, 37, 38, 41, 42, 55, 57, 61, 65, 67, 72, 236–238 SRAM, 20, 33, 48 allocation of 8-bit variables for conversion macros in, 380 Static random-access memory. See SRAM SUB, 1 swap, 85, 119, 120, 122, 128, 129, 134, 136, 139, 142, 146, 148, 155, 165, 167, 174, 177, 180, 184, 186, 193, 194

U Unsigned integer to packed BCD conversion, 379, 386, 388, 389, 395, 396, 398, 399, 430 Unsigned integer to unpacked BCD conversion, 379, 385, 389, 390, 393, 394, 398, 428 Unsigned short integer to packed BCD conversion, 379, 383, 385–388, 427, 428 Unsigned short integer to unpacked BCD conversion, 379, 380, 381–384, 424, 427 user program, 34–40, 42–49, 76, 77, 79, 129, 130, 133, 136, 137, 139, 140, 143, 146, 148, 149, 152, 155–158, 161, 164, 165, 167, 168, 171, 174, 175, 177, 178, 181, 184–187, 190, 194, 243, 247–249, 252, 261, 263, 270, 275, 282, 284–288, 290–292, 294, 296, 298, 300, 302–319, 353, 357, 359, 361, 365, 367–377, 424, 427, 428, 430, 431, 433–437, 439, 441–447, 449