Operads of wiring diagrams 9783319950006, 9783319950013

Table of contents :
Preface......Page 7
Contents......Page 8
1.1 What Are Wiring Diagrams?......Page 11
1.2 Purposes of this Monograph......Page 13
1.4 Chapter Summaries......Page 15
1.5 References for the Main Results and Examples......Page 18
Part I Wiring Diagrams......Page 20
2.1 Colored Operads......Page 22
2.2 Defining Wiring Diagrams......Page 32
2.3 Operad Structure......Page 39
2.4 Summary of this Chapter......Page 46
3 Generators and Relations......Page 47
3.1 Generating Wiring Diagrams......Page 48
3.2 Internal Wasted Wires......Page 52
3.3 Elementary Relations......Page 54
3.4 Summary of this Chapter......Page 69
4 Decomposition of Wiring Diagrams......Page 70
4.1 Factoring Wiring Diagrams......Page 71
4.2 Unary Wiring Diagrams......Page 76
4.3 Unary Wiring Diagrams with No Loop Elements......Page 81
4.4 Summary of this Chapter......Page 94
5 Finite Presentation......Page 95
5.1 Stratified Presentation......Page 96
5.2 Finite Presentation for Wiring Diagrams......Page 100
5.3 Finite Presentation for Normal Wiring Diagrams......Page 107
5.4 Finite Presentation for Strict Wiring Diagrams......Page 108
5.5 Summary of this Chapter......Page 111
6 Finite Presentation for Algebras over Wiring Diagrams......Page 112
6.1 Operad Algebras......Page 113
6.2 Algebras over the Operad of Wiring Diagrams......Page 117
6.3 Finite Presentation for the Propagator Algebra......Page 126
6.4 Algebras over the Operad of Normal Wiring Diagrams......Page 145
6.5 Finite Presentation for the Algebra of Discrete Systems......Page 146
6.7 Finite Presentation for the Algebra of Open Dynamical Systems......Page 154
6.8 Summary of this Chapter......Page 160
Part II Undirected Wiring Diagrams......Page 161
7.1 Defining Undirected Wiring Diagrams......Page 162
7.2 Pushouts......Page 167
7.3 Operad Structure......Page 168
7.4 Summary of this Chapter......Page 177
8.1 Generating Undirected Wiring Diagrams......Page 178
8.2 Elementary Relations......Page 181
8.3 Wasted Cables......Page 189
8.4 Summary of this Chapter......Page 192
9.1 A Motivating Example......Page 193
9.2 Factoring Undirected Wiring Diagrams......Page 197
9.3 The Inner Undirected Wiring Diagram......Page 199
9.4 The Outer Undirected Wiring Diagram......Page 202
9.5 Iterated Splits......Page 206
9.6 Iterated Loops......Page 209
9.7 Summary of this Chapter......Page 211
10.1 Stratified Presentation......Page 212
10.2 Elementary Equivalences......Page 215
10.3 Summary of this Chapter......Page 220
11 Algebras of Undirected Wiring Diagrams......Page 221
11.1 Finite Presentation for Algebras......Page 222
11.2 Finite Presentation for the Relational Algebra......Page 229
11.3 Spivak's Conjecture: Rigidity of the Relational Algebra......Page 232
11.4 Finite Presentation for the Typed Relational Algebra......Page 236
11.5 Summary of this Chapter......Page 239
Part III Maps Between Operads of Wiring Diagrams......Page 240
12 A Map from Normal to Undirected Wiring Diagrams......Page 242
12.1 Operad Maps......Page 243
12.2 Normal to Undirected Wiring Diagrams......Page 246
12.3 Examples of the Operad Map......Page 252
12.4 Image of the Operad Map......Page 256
12.5 Map from Strict to Undirected Wiring Diagrams......Page 262
12.6 Summary of this Chapter......Page 266
13 A Map from Wiring Diagrams to Undirected Wiring Diagrams......Page 267
13.1 Wiring Diagrams to Undirected Wiring Diagrams......Page 268
13.2 Examples of the Operad Map......Page 274
13.3 Surjectivity of the Operad Map......Page 276
13.4 Summary of this Chapter......Page 283
14 Problems......Page 284
A.1 Category Theory......Page 287
A.3 Props......Page 288
A.4 Applications of Compositional Structures......Page 289
B List of Notation......Page 291
References......Page 294
Index......Page 297

Citation preview

Lecture Notes in Mathematics  2192

Donald Yau

Operads of Wiring Diagrams

Lecture Notes in Mathematics Editors-in-Chief: Jean-Michel Morel, Cachan Bernard Teissier, Paris Advisory Board: Michel Brion, Grenoble Camillo De Lellis, Princeton Alessio Figalli, Zurich Davar Khoshnevisan, Salt Lake City Ioannis Kontoyiannis, Athens Gábor Lugosi, Barcelona Mark Podolskij, Aarhus Sylvia Serfaty, New York Anna Wienhard, Heidelberg

2192

More information about this series at http://www.springer.com/series/304

Donald Yau

Operads of Wiring Diagrams

123

Donald Yau Department of Mathematics The Ohio State University at Newark Ohio, USA

ISSN 0075-8434 ISSN 1617-9692 (electronic) Lecture Notes in Mathematics ISBN 978-3-319-95000-6 ISBN 978-3-319-95001-3 (eBook) https://doi.org/10.1007/978-3-319-95001-3 Library of Congress Control Number: 2018943454 Mathematics Subject Classification (2010): 18D50, 37A60, 55P48, 81P45, 94C15 © Springer Nature Switzerland AG 2018 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To Eun Soo and Jacqueline

Preface

Wiring diagrams and undirected wiring diagrams are graphical languages for describing interconnected processes and their compositions. These objects have enormous potentials for applications in many different disciplines, including computer science, cognitive neuroscience, dynamical systems, network theory, and circuit diagrams. It is known that the collection of wiring diagrams is an operad and likewise for undirected wiring diagrams. This monograph is a comprehensive study of the combinatorial structure of various operads of wiring diagrams and undirected wiring diagrams. Our first main objective is to prove a finite presentation theorem for each operad of wiring diagrams, describing each one in terms of just a few operadic generators and a small number of generating relations. For example, the operad of wiring diagrams has 8 generators and 28 generating relations, while the operad of undirected wiring diagrams has 6 generators and 17 generating relations. Our second main objective is to prove a corresponding finite presentation theorem for algebras over each operad of wiring diagrams. As applications we provide finite presentations for the propagator algebra, the algebra of discrete systems, the algebra of open dynamical systems, and the (typed) relational algebra. We also provide a partial verification of Spivak’s conjecture regarding the quotientfreeness of the relational algebra. Our third main objective is to construct explicit operad maps among the several operads of wiring diagrams. In particular, there is a surjective operad map from the operad of all wiring diagrams, including delay nodes, to the operad of undirected wiring diagrams. This monograph is intended for graduate students, mathematicians, scientists, and engineers interested in operads and wiring diagrams. Assuming no prior knowledge of categories, operads, and wiring diagrams, this monograph is selfcontained and can be used as a supplement in a graduate course and for independent study. There are over 100 graphical illustrations and a chapter with a list of problems. Newark, OH, USA

Donald Yau vii

Contents

1

Introduction .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.1 What Are Wiring Diagrams? . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.2 Purposes of this Monograph . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.3 Audience and Features . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.4 Chapter Summaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 1.5 References for the Main Results and Examples . . . . . . . . . . . . . . . . . . . .

Part I

1 1 3 5 5 8

Wiring Diagrams

2

Wiring Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.1 Colored Operads.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.2 Defining Wiring Diagrams .. . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.3 Operad Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 2.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

13 13 23 30 37

3

Generators and Relations .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.1 Generating Wiring Diagrams . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.2 Internal Wasted Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.3 Elementary Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 3.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

39 40 44 46 61

4

Decomposition of Wiring Diagrams . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.1 Factoring Wiring Diagrams .. . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.2 Unary Wiring Diagrams.. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 4.3 Unary Wiring Diagrams with No Loop Elements . . . . . . . . . . . . . . . . . . 4.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

63 64 69 74 87

5

Finite Presentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 89 5.1 Stratified Presentation .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 90 5.2 Finite Presentation for Wiring Diagrams .. . . . . . .. . . . . . . . . . . . . . . . . . . . 94 5.3 Finite Presentation for Normal Wiring Diagrams.. . . . . . . . . . . . . . . . . . 101 5.4 Finite Presentation for Strict Wiring Diagrams .. . . . . . . . . . . . . . . . . . . . 102 5.5 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 105 ix

x

6

Contents

Finite Presentation for Algebras over Wiring Diagrams .. . . . . . . . . . . . . . 6.1 Operad Algebras.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.2 Algebras over the Operad of Wiring Diagrams .. . . . . . . . . . . . . . . . . . . . 6.3 Finite Presentation for the Propagator Algebra .. . . . . . . . . . . . . . . . . . . . 6.4 Algebras over the Operad of Normal Wiring Diagrams .. . . . . . . . . . . 6.5 Finite Presentation for the Algebra of Discrete Systems . . . . . . . . . . . 6.6 Algebras over the Operad of Strict Wiring Diagrams . . . . . . . . . . . . . . 6.7 Finite Presentation for the Algebra of Open Dynamical Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 6.8 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

Part II

107 108 112 121 140 141 149 149 155

Undirected Wiring Diagrams

7

Undirected Wiring Diagrams . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.1 Defining Undirected Wiring Diagrams .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.2 Pushouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.3 Operad Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 7.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

159 159 164 165 174

8

Generators and Relations .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 8.1 Generating Undirected Wiring Diagrams . . . . . . .. . . . . . . . . . . . . . . . . . . . 8.2 Elementary Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 8.3 Wasted Cables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 8.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

175 175 178 186 189

9

Decomposition of Undirected Wiring Diagrams . . . .. . . . . . . . . . . . . . . . . . . . 9.1 A Motivating Example .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 9.2 Factoring Undirected Wiring Diagrams .. . . . . . . .. . . . . . . . . . . . . . . . . . . . 9.3 The Inner Undirected Wiring Diagram .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . 9.4 The Outer Undirected Wiring Diagram . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 9.5 Iterated Splits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 9.6 Iterated Loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 9.7 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

191 191 195 197 200 204 207 209

10 Finite Presentation for Undirected Wiring Diagrams . . . . . . . . . . . . . . . . . . 10.1 Stratified Presentation .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 10.2 Elementary Equivalences . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 10.3 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

211 211 214 219

11 Algebras of Undirected Wiring Diagrams . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 11.1 Finite Presentation for Algebras .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 11.2 Finite Presentation for the Relational Algebra ... . . . . . . . . . . . . . . . . . . . 11.3 Spivak’s Conjecture: Rigidity of the Relational Algebra .. . . . . . . . . . 11.4 Finite Presentation for the Typed Relational Algebra . . . . . . . . . . . . . . 11.5 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

221 222 229 232 236 239

Contents

Part III

xi

Maps Between Operads of Wiring Diagrams

12 A Map from Normal to Undirected Wiring Diagrams . . . . . . . . . . . . . . . . . 12.1 Operad Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 12.2 Normal to Undirected Wiring Diagrams . . . . . . . .. . . . . . . . . . . . . . . . . . . . 12.3 Examples of the Operad Map .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 12.4 Image of the Operad Map .. . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 12.5 Map from Strict to Undirected Wiring Diagrams .. . . . . . . . . . . . . . . . . . 12.6 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

243 244 247 253 257 263 267

13 A Map from Wiring Diagrams to Undirected Wiring Diagrams .. . . . . 13.1 Wiring Diagrams to Undirected Wiring Diagrams . . . . . . . . . . . . . . . . . 13.2 Examples of the Operad Map .. . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 13.3 Surjectivity of the Operad Map .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 13.4 Summary of this Chapter . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .

269 270 276 278 285

14 Problems .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 287 A

Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 291

B

List of Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 295

References .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 299 Index . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . 303

Chapter 1

Introduction

1.1 What Are Wiring Diagrams? Wiring diagrams and undirected wiring diagrams allow one to consider a finite collection of related operations, wired together in some way, as an operation itself. Such an operation can then be considered as a single operation within a yet larger collection of operations, and so forth. For instance, a finite collection of related operations may be a group of neurons in a certain region of the brain, a collection of codes within a large computer program, or a few related agents within a large supply-chain. The main reason why wiring diagrams and undirected wiring diagrams are important is that they have enormous potential for applications in many different disciplines. In fact, the authors of [42] cited both computer science and cognitive neuroscience as potential applications of wiring diagrams. Furthermore, in [45, 48] wiring diagrams were used to study dynamical systems and to model certain kinds of differential equations. Many potential fields of applications are mentioned in the introduction of [48]. In [43] undirected wiring diagrams were used to study database relational queries, plug-and-play devices, recursion, and circuit diagrams. Wiring diagrams form a kind of graphical language that describes operations or processes with multiple inputs and multiple outputs and how such operations are wired together to form a larger and more complicated operation. Some visual examples of wiring diagrams are in (2.22), Chap. 3, and Example 4.13. The first type of wiring diagram that we are going to study in this monograph was originally introduced in [42], with variants studied in [45, 47, 48]. In [45, 47] wiring diagrams without delay nodes (Definition 5.23), which we call normal wiring diagrams, were used to study mode-dependent networks, discrete systems, and dynamical systems. In [48] wiring diagrams without delay nodes and whose supplier assignments are bijections (Definition 5.30), which we call strict wiring diagrams, were used to study open dynamical systems. Wiring diagrams are by nature directed, in the sense that every operation has a finite set of inputs and a finite set of outputs, each element of which is allowed to © Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_1

1

2

1 Introduction

carry a value of some kind. There is also an undirected version of wiring diagrams [43, 44]. Unlike a wiring diagram, in an undirected wiring diagram, each operation is a finite set, each element of which is again allowed to carry a value. Some visual examples of undirected wiring diagrams are in (7.4), Example 7.18, and Chaps. 8 and 9. For those familiar with operad theory, the distinction between wiring diagrams and undirected wiring diagrams is similar to that between operads and cyclic operads. Just as cyclic operads are not simpler than operads, undirected wiring diagrams are not really simpler than wiring diagrams and have their own subtlety. The substitution process involving wiring diagrams and undirected wiring diagrams described in the first paragraph can be captured precisely using the notion of colored operads. A colored operad, or just an operad, is a mathematical object that describes operations with multiple inputs and one output and their compositions. A colored operad in which there are only unary operations is precisely a category. If one restricts even further to just the 1-colored case in which the unary operations form a set, then one has a monoid, such as the set of integers under addition. Therefore, a colored operad is a multiple-input generalization of a category, and in fact colored operads are also called symmetric multicategories. Multicategories without symmetric group actions were introduced by Lambek [23]. One-colored operads, together with the name operad, were introduced by May [35] in the topological setting. See [36] for the definition of a one-colored operad in a symmetric monoidal category. The book [51] is an elementary introduction to colored operads in symmetric monoidal categories. The book [52] has a more indepth discussion of colored operads and related objects. In [42] Rupel and Spivak observed that the collection of wiring diagrams is a colored operad WD, in which the operadic composition corresponds precisely to the substitution process described above. Each colored operad has associated algebras, on which the colored operad acts. The operadic action is similar to the action of an associative algebra on a left module. The authors of [42] defined a WD-algebra, called the propagator algebra, that models a certain kind of input-output process. Closely related colored operads of sub-classes of wiring diagrams were introduced in [45, 47, 48]. We will denote by WD• (Definition 5.23) the operad of normal wiring diagrams, meaning those without delay nodes. In [45] Spivak introduced a WD• -algebra, called the algebra of discrete systems, that is closely related to a Moore machine, also known as a discrete state machine. We will also write WD0 (Definition 5.30) for the operad of strict wiring diagrams, meaning those without delay nodes and whose supplier assignments are bijections. In [48] a WD0 -algebra, called the algebra of open dynamical systems, was defined that models a certain kind of differential equation. Likewise, in [43] Spivak constructed the colored operad UWD of undirected wiring diagrams. Spivak also defined a UWD-algebra called the relational algebra, which was used to model relational queries in database.

1.2 Purposes of this Monograph

3

1.2 Purposes of this Monograph This monograph is a comprehensive study of the combinatorial structure of the operads WD, WD• , WD0 , and UWD of (normal/strict/undirected) wiring diagrams, their algebras, and the relationships between these operads. Specifically, our main results are of the following three types. Finite Presentation for Operads For each of the operads WD, WD• , WD0 , and UWD, we prove a finite presentation theorem that describes the operad in terms of just a few operadic generators and a small number of generating relations. For the operad of wiring diagrams WD, there are 8 generating wiring diagrams and 28 generating relations. For the smaller operads WD• and WD0 of normal and strict wiring diagrams, the numbers of operadic generators and of generating relations are (7, 28) and (4, 8), respectively. For the operad of undirected wiring diagrams UWD, there are 6 operadic generators and 17 generating relations. Finite Presentation for Algebras For each of the operads WD, WD• , WD0 , and UWD, we prove a corresponding finite presentation theorem for their algebras. To be more precise, we describe WD-algebras using 8 generating structure maps and 28 generating axioms. So finite presentation refers to the WD-algebra structure maps, not the elements in the underlying set. Similar finite presentations are also obtained for the algebras over the operads WD• of normal wiring diagrams, WD0 of strict wiring diagrams, and UWD of undirected wiring diagrams. As applications we provide finite presentations for the propagator algebra over WD, the algebra of discrete systems over WD• , the algebra of open dynamical systems over WD0 , and the (typed) relational algebra over UWD. Along the way, we provide a partial verification of Spivak’s conjecture [43] regarding the quotient-freeness of the relational algebra. Maps Between Operads We construct a commutative diagram

of operad maps, in which the horizontal maps are operad inclusions. For each of the operad maps χ 0 , χ, and ρ, we compute precisely the image in UWD. In / UWD is surjective. The existence of particular, the operad map ρ : WD the operad map ρ answers a question raised in [42]. The end of this chapter contains several tables that summarize the main results and contain some key references. The finite presentation theorems for the operads WD, WD• , WD0 , and UWD reduce the structure of these operads and their algebras to just a few generators and relations. For example, our finite presentation theorem for the operad WD reduces the understanding of this operad to just 8 simple wiring diagrams and 28 simple relations among them. Likewise, the structure map of a general WD-algebra can be

4

1 Introduction

quite involved, as can be seen in the propagator algebra [42]. Our finite presentation theorem for WD-algebras reduces the definition and understanding of WD-algebras to just 8 simple generating structure maps and 28 generating axioms, almost all of which are trivial to check in practice. We will further illuminate this point when we discuss the finite presentations for the propagator algebra over WD, the algebra of discrete systems over WD• , the algebra of open dynamical systems over WD0 , and the (typed) relational algebra over UWD. To give an even more familiar feel to our finite presentation theorems for the operads WD, WD• , WD0 , and UWD, and for their algebras, let us recall a few other places where various kinds of finite presentations occur. Each type of finite presentation is a way to reduce a large, usually infinite, collection of conditions to a finite, or at least smaller, collection of conditions, thereby making the relevant structure more manageable. 1. In basic group theory and commutative ring theory [3, 41], it is quite common to consider finite presentation of groups and modules. For example, over a commutative Noetherian ring, every finitely generated module is also finitely presented [41, Prop. 7.59]. 2. A cornerstone in category theory, Mac Lane’s Coherence Theorem [27, 29] can be regarded as a finite presentation theorem for monoidal categories. Roughly speaking, this theorem says that, in any monoidal category, the infinite collection of commutative formal diagrams has a finite presentation. The generators are the associativity isomorphism, the left and the right units, and their inverses. The generating relations are the Pentagon Axiom for fourfold iterated tensor products and two unity axioms. 3. In the linear setting, the operads for associative algebras, commutative algebras, Lie algebras, Leibniz algebras, Poisson algebras, and many others, are finitely presented [15]. For example, the associative operad has one generator, which / A of an in its algebras corresponds to the usual multiplication A ⊗ A associative algebra. The associative operad has one generating relation, which in its algebras corresponds to the usual associativity axiom, (ab)c = a(bc), of an associative algebra. 4. In [4, 10] a finite presentation is given for the symmetric monoidal category of signal-flow graphs. In applications signal-flow graphs form another kind of graphical language that describes processes with inputs and outputs and relations between them. One main difference between (undirected) wiring diagrams and signal-flow graphs is that the composition of signal-flow graphs is done by grafting. This means that the outputs of one signal-flow graph are connected to the inputs of another signal-flow graph. This is similar to the situation in string diagrams [21, 46] On the other hand, the operadic composition of (undirected) wiring diagrams is done by substitution, which is pictorially depicted in (2.25) for wiring diagrams and in (7.10) for undirected wiring diagrams. In more conceptual terms, the collection of signal-flow graphs is a prop, hence an algebra over the operad for props [52, Theorem 14.1]. On the other hand, the collection of (undirected) wiring diagrams is an operad.

1.4 Chapter Summaries

5

5. Closer to the topic of this monograph is [52, Ch.7], where finite presentations are given for various graph groupoids including those for colored operads, colored props, and colored wheeled props. In fact, the way we phrase and verify our finite presentation theorems for the operads of (undirected) wiring diagrams and for their algebras is conceptually similar to the presentation in [52, Ch.7]. One way to explain this conceptual similarity is that, for both (undirected) wiring diagrams and the graphs for, say, colored wheeled props, the composition is done by substitution. However, wiring diagrams are in several ways more complicated than the graphs in [52]. In fact, the graphs in [52] do not have delay nodes, internal and external wasted wires, and split wires, all of which can happen in a wiring diagram. See, for example, the wiring diagram in (2.22).

1.3 Audience and Features The main results in this monograph—namely, the finite presentation theorems for the various operads of (undirected) wiring diagrams and for their algebras as well as operad maps between them—are new. So this monograph should be useful to mathematicians with an interest in operads and (undirected) wiring diagrams. Furthermore, due to the wide variety of potential applications, we also intend to make this monograph and this subject accessible to scientists and engineers. With such a large audience in mind, the prerequisites for this monograph have been kept to an absolute minimum. In particular, we assume the reader is comfortable with the basic concepts of sets, functions, and mathematical induction. No prior knowledge of categories, operads, and (undirected) wiring diagrams is assumed. The presentation of the material proceeds at a fairly leisurely pace and is roughly at the advanced undergraduate to beginning graduate level. To motivate various constructions and concepts, we have many examples and a lot of discussion that explains the intuition behind the scene. Furthermore, there are over 100 pictures throughout this monograph that help the reader to visualize (undirected) wiring diagrams. Finally, to solidify their understanding of the subject, the reader may work through the problems in Chap. 14. There are enough problems there to keep one busy for a few days.

1.4 Chapter Summaries This monograph is divided into three parts. Part I Wiring Diagrams (Chaps. 2–6) This part contains the finite presentation theorems for the operad WD of wiring diagrams, the operad WD• of normal wiring diagrams, the operad WD0 of strict wiring diagrams, and their algebras.

6

1 Introduction

Part II Undirected Wiring Diagrams (Chaps. 7–11) This part contains the finite presentation theorems for the operad UWD of undirected wiring diagrams and for their algebras. Part III Maps Between Operads of Wiring Diagrams (Chaps. 12–14 and Appendix A) This part contains the construction and description of various operad maps between the operads WD, WD• , WD0 , and UWD. It also contains a chapter with a list of problems and a chapter with references for further reading. Each part begins with a brief introduction and a reading guide. Below is a brief description of each chapter. In Chap. 2, to keep this document self-contained, we first recall two equivalent definitions of a colored operad. The first definition is in terms of May’s operad structure map γ , and the other one is in terms of the ◦i -compositions. After recalling the definition of a wiring diagram, we provide a proof of the fact from [42] that the collection of wiring diagrams WD is a colored operad. The main difference here is that we use the definition of a colored operad based on the ◦i -compositions. In this monograph, we prefer to work with the ◦i -compositions rather than May’s operad structure map γ because the ◦i -compositions are more convenient in phrasing and verifying our finite presentation theorems. In Chap. 3 we introduce 8 generating wiring diagrams and 28 elementary relations among them. On the one hand, one may regard this chapter as a long list of concrete examples of wiring diagrams and their operadic compositions. On the other hand, in later chapters we will see that these finite collections of generating wiring diagrams and elementary relations are sufficient to describe the operad WD of wiring diagrams, its variants WD• and WD0 , and their algebras. For the finite presentation theorems for the operad WD of wiring diagrams and its variants WD• and WD0 , we will need to be able to decompose every wiring diagram in terms of the 8 generating wiring diagrams in a highly structured way. The purpose of Chap. 4 is to supply all the steps needed to establish such a decomposition. The finite presentation theorems for the operad WD of wiring diagrams as well as its two variants WD• and WD0 are given in Chap. 5; see Theorems 5.22, 5.29, and 5.37. Since we are not working in the linear setting (e.g., of modules) where we can take quotients, we need to be extra careful in phrasing our finite presentations for the operads WD, WD• , and WD0 . For this purpose, a crucial concept is that of a stratified presentation, which is the highly structured decomposition mentioned in the previous paragraph. The results in Chap. 4 guarantee the existence of a stratified presentation for each wiring diagram. This implies the finite generation parts of our finite presentation theorems for WD, WD• , and WD0 . The relation parts of the finite presentation theorems are phrased in terms of our concept of an elementary equivalence. Roughly speaking, an elementary equivalence means replacing one side of either (1) an elementary relation in Chap. 3 or (2) an operad associativity/unity axiom for the generating wiring diagrams, by the other side. In Chap. 6 we discuss finite presentations for algebras over the operads WD, WD• , and WD0 . In each case, the finite presentation for algebras is a consequence

1.4 Chapter Summaries

7

of the finite presentation theorem for the corresponding operad of wiring diagrams. To illustrate the finite presentation for WD-algebras, we will describe the propagator algebra in terms of 8 generating structure maps and 28 generating axioms. To illustrate our finite presentation for WD• -algebras, we will describe the algebra of discrete systems in terms of 7 generating structure maps and 28 generating axioms. To illustrate our finite presentation for WD0 -algebras, we will similarly describe the algebra of open dynamical systems in terms of 4 generating structure maps and 8 generating axioms. This finishes Part I on wiring diagrams. Part II begins with Chap. 7, where we first recall the notion of an undirected wiring diagram. Then we give a proof of the fact that the collection of undirected wiring diagrams forms an operad UWD. As in Chap. 2, the operad structure on UWD as well as its proof are both given in terms of the ◦i -compositions because the finite presentation theorems are easier to phrase this way. One subtlety about the operad UWD is that undirected wiring diagrams may have wasted cables (Definition 7.2), which are cables that are not soldered to any wires. As opposed to what was stated in [44, Example 7.4.2.10], wasted cables cannot be excluded from the definition of undirected wiring diagrams. In fact, wasted cables can actually be created from operadic composition of undirected wiring diagrams without wasted cables. We will make this point precise in Example 7.18. Chapter 8 is the undirected analogue of Chap. 3. In this chapter, we describe 6 generating undirected wiring diagrams and 17 elementary relations among them. On the one hand, one may regard this chapter as a long list of concrete examples of undirected wiring diagrams and their operadic compositions. On the other hand, in later chapters we will see that these finite collections of generating undirected wiring diagrams and elementary relations are sufficient to describe the operad UWD of undirected wiring diagrams. Chapter 9 is the undirected analogue of Chap. 4. In this chapter, we show that each undirected wiring diagram can be decomposed in terms of the generating undirected wiring diagrams in a highly structured way. Such a decomposition is needed to establish the finite presentation theorem for the operad UWD. Chapter 10 is the undirected analogue of Chap. 5. In this chapter, we establish the finite presentation theorem for the operad UWD of undirected wiring diagrams; see Theorem 10.19. This result is phrased in terms of the generating undirected wiring diagrams and an undirected version of an elementary equivalence. Chapter 11 contains the finite presentation theorem for UWD-algebras. This result is a consequence of the finite presentation theorem for the operad UWD. It describes each UWD-algebra in terms of 6 generating structure maps and 17 generating axioms, almost all of which are trivial to check in practice. We will illustrate this point with the relation algebra and the typed relational algebra from [43]. We will also provide a partial verification of Spivak’s conjecture regarding the quotient-freeness of the relational algebra. This finishes Part II on undirected wiring diagrams. Part III begins with Chap. 12, in which we first construct the operad inclusions / WD• / WD. Recall that WD• is the operad of normal wiring WD0 diagrams—i.e., those without delay nodes—and that WD0 is the operad of strict

8

1 Introduction

wiring diagrams—i.e., those without delay nodes and whose supplier assignments / UWD, essentially are bijections. Then we construct an operad map χ : WD• / UWD. For each of the by forgetting directions, and its restriction χ 0 : WD0 0 operad maps χ and χ , we compute precisely the image in UWD. In the terminology of Notation 9.1, the image of the operad map χ consists of precisely the undirected wiring diagrams without wasted cables and (0, ≥ 2)-cables. The image of the operad map χ 0 consists of precisely the undirected wiring diagrams with only (1, 1)-cables and (2, 0)-cables. / UWD to an operad In Chap. 13 we extend the operad map χ : WD• / map ρ : WD UWD that is defined for all wiring diagrams. We prove that the operad map ρ is surjective, so every undirected wiring diagram is the image of some wiring diagram. The operad map ρ is slightly subtle because wiring diagrams may have delay nodes, while undirected wiring diagrams do not seem to have an exact analogue of delay nodes. In fact, for this reason Rupel and Spivak [42] / UWD. (Sect. 4.1) expressed doubt about the existence of an operad map WD We will see that delay nodes, far from being an obstruction, play a critical role in the surjectivity of the operad map ρ. Chapter 14 contains some problems about operads and (undirected) wiring diagrams arising from the earlier chapters. Appendix A contains some relevant references on categories, operads, props, and their applications in the sciences. This finishes Part III.

1.5 References for the Main Results and Examples The following table summaries the key references for the various operads of (undirected) wiring diagrams and their finite presentation theorems.

WD

Operad of

Finite presentation

Generators

Relations

Wiring diagrams (Theorem 2.41)

Theorem 5.22

8 (Definition 3.9)

28 (Definition 3.43)

Normal wiring 7 28 WD• diagrams (Proposition 5.27) Theorem 5.29 (Definition 5.28(1)) (Definition 5.28(4)) Strict wiring 4 8 WD0 diagrams (Proposition 5.35) Theorem 5.37 (Definition 5.36(1)) (Definition 5.36(5)) UWD

Undirected wiring diagrams (Theorem 7.24)

Theorem 10.19

6 (Definition 8.7)

17 (Definition 8.26)

1.5 References for the Main Results and Examples

9

The following table summarizes the key references for the finite presentation theorems for algebras over the various operads of (undirected) wiring diagrams. Algebras over

Finite presentation

(Generators, relations)

Key example

WD

Theorem 6.10

(8, 28) (Definition 6.9)

Propagator algebra (Theorem 6.26)

WD•

Theorem 6.35

(7, 28) (Definition 6.34)

Discrete systems (Theorem 6.48)

WD0

Theorem 6.51

(4, 8) (Definition 6.50)

Open dynamical systems (Theorem 6.60)

UWD

Theorem 11.2

(6, 17) (Definition 11.1)

(Typed) relational algebra (Theorems 11.8 and 11.20)

The following table summarizes the key references for the operad maps between the various operads of (undirected) wiring diagrams. Operad map / WD•

WD0

χ

WD• χ0

WD0 ρ

WD

Reference Proposition 12.7

Note/image Inclusions

/ UWD

Theorem 12.14

No (0, 0)- and (0, ≥ 2)-cables (Theorem 12.28)

/ UWD

Theorem 12.39

Only (1, 1)- and (2, 0)-cables

/ UWD

Theorem 13.4

Surjective (Theorem 13.12)

/ WD

Part I

Wiring Diagrams

The main purpose of this part is to describe the combinatorial structure of 1. the operad WD of wiring diagrams, 2. the operad WD• of normal wiring diagrams, and 3. the operad WD0 of strict wiring diagrams. A normal wiring diagram is a wiring diagram without delay nodes. A strict wiring diagram is a normal wiring diagram whose supplier assignment is a bijection. For each of these three operads, we prove a finite presentation theorem that describes the operad in terms of a few operadic generators and a small number of generating relations. Operads and wiring diagrams are recalled in Chap. 2. Operadic generators and generating relations for the operad WD of wiring diagrams are presented in Chap. 3. Various decompositions of wiring diagrams are given in Chap. 4. Using the results in Chaps. 3 and 4, the finite presentation theorems for the operads WD, WD• , and WD0 are proved in Chap. 5. In Chap. 6 we prove the corresponding finite presentation theorems for WD-algebras, WD• -algebras, and WD0 -algebras and discuss the main examples of the propagator algebra, the algebra of discrete systems, and the algebra of open dynamical systems. Each finite presentation theorem for algebras describes the algebras in terms of finitely many generating structure maps and relations among these maps. Reading Guide In this reading guide we describe what can be safely skipped in this Part during the first reading. The purpose is to help the reader get to the main results and examples quicker without getting bogged down by all the technical details. In Chap. 2, the reader who already knows about colored operads and categories may skip Sect. 2.1 and start reading about wiring diagrams from Definition 2.18. In Sect. 2.3 about the operad structure on WD, the reader may wish to skip the proofs of the Lemmas and just study the pictures. Section 3.2 about internal wasted wires may be skipped during the first reading.

12

I Wiring Diagrams

In Chap. 4 the various decompositions of wiring diagrams are outlined in the introduction. The reader may read that introduction, followed by Motivations 4.4 and 4.9 and Examples 4.13 and 4.19, which provide pictures that illustrate the decompositions. In Sect. 5.2, after the initial definitions and examples, the reader may wish to skip the proofs of Lemmas 5.19–5.21 and go straight to Theorem 5.22, the finite presentation theorem for wiring diagrams. The reader who already knows about operad algebras may skip Sect. 6.1.

Chapter 2

Wiring Diagrams

The purpose of this chapter is to recall the definitions of colored operads and wiring diagrams. In Sect. 2.1 we recall two equivalent definitions of a colored operad, one in terms of the structure map γ (2.2) and the other in terms of the ◦i -compositions (2.9). Wiring diagrams are defined in Sect. 2.2. The main difference between our definition of a wiring diagram and the original one in [42] is that we allow the wires to carry values in an arbitrary class S instead of just the class of pointed sets. This added flexibility will be important in later chapters when we discuss operad algebras. Indeed, in Sect. 6.3 when we discuss the propagator algebra, we will take S to be the class of pointed sets. On the other hand, in Sect. 6.7 when we discuss the algebra of open dynamical systems, we will take S to be a set of representatives of isomorphism classes of second-countable smooth manifolds. In Sect. 2.3 we define the operad structure on wiring diagrams in terms of ◦i compositions. Although we could also have defined this operad structure in terms of γ as in [42], we chose to use ◦i -compositions because the finite presentation theorems in Chap. 5 can be phrased and proved more easily using the latter.

2.1 Colored Operads For brief discussion about classes in the set-theoretic sense, the reader is referred to [16, 39]. In this monograph, the reader can safely take the word class to just mean a collection of objects, such as sets, pointed sets, and real functions. First we introduce some notations for the colors in a colored operad. Definition 2.1. Suppose S is a class. 1. Denote by Prof(S) the class of finite ordered sequences of elements in S. An element in Prof(S) is called an S-profile or just a profile if S is clear from the context. © Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_2

13

14

2 Wiring Diagrams

2. A typical S-profile of length n is denoted by s = (s1 , . . . , sn ) with |s| denoting its length. 3. The empty S-profile is denoted by ∅. 4. For n ≥ 0 denote by Prof≥n (S) ⊆ Prof(S) the sub-class of S-profiles of length at least n. Motivation 2.2. Before we define an operad, let us first motivate its definition with a simple but important example. Suppose X is a set and Map(Xn , X) is the set of functions from Xn = X×· · ·×X, with n ≥ 0 factors of X, to X. If f ∈ Map(Xn , X) with n ≥ 1 and gi ∈ Map(Xmi , X) for each 1 ≤ i ≤ n, then one can form the new function   f ◦ (g1 , . . . , gn ) ∈ Map Xm1 +···+mn , X by first applying the gi s simultaneously and then applying f . Moreover, we may even allow the inputs and the output of each function to be from different sets, i.e., / Xd . In this case, the above composition is defined functions Xc1 × · · · × Xcn if and only if the outputs of the gi ’s match with the inputs of f . A function f ∈ Map(Xc1 × · · · × Xcn , Xd ) may be depicted as follows.

When n ≥ 1, the composition f ◦ (g1 , . . . , gn ) corresponds to the 2-level tree:

  Here each gi ∈ Map Xbi × · · · × Xbmi , Xci , n ≥ 1, and each mi ≥ 0. Together 1 i with permutations of the inputs, the above collection of functions satisfies some associativity, unity, and equivariance conditions. An operad is an abstraction of this example that allows one to encode operations with multiple, possibly zero, inputs and one output and their compositions. With the above motivation in mind, next we define colored operads. See, for example, [51] for a more in-depth discussion of colored operads. For each integer n ≥ 0, the symmetric group on n letters is denoted by Σn .

2.1 Colored Operads

15

Definition 2.3. Suppose S is a class. An S-colored operad (O, 1, γ ) consists of the following data. 1. For any d ∈ S and c ∈ Prof(S) with length n ≥ 0, O is equipped with a class O

d  c

=O



d  c1 ,...,cn

d 

called the entry of O with input profile c and output color d. An element in O c is called an n-ary element in O. d  2. For c ∈ Prof(S) × S as above and a permutation σ ∈ Σn , O is equipped with a bijection (2.1) called the right action or the symmetric group action, in which cσ = (cσ (1), . . . , cσ (n) ) is the right permutation of c by σ . c 3. For each c ∈ S, O is equipped with a specific element 1c ∈ O c , called the c-colored unit. d  4. For c ∈ Prof(S) × S as above with n ≥ 1, suppose b1 , . . . , bn ∈ Prof(S) and b = (b1 , . . . , b n ) ∈ Prof(S) is their concatenation. Then O is equipped with a map

(2.2) d 

called the operadic composition. For y ∈ O c and xi ∈ O image of the operadic composition is written as

 ci  bi

for 1 ≤ i ≤ n, the

  d  γ y; x1, . . . , xn ∈ O b . This data is required to satisfy the following associativity, unity, and equivariance axioms. Associativity Axiom

Suppose that:

• in (2.2)   j j bj = b1 , . . . , bkj ∈ Prof(S) has length kj ≥ 0 for each 1 ≤ j ≤ n such that at least one kj > 0; j • a i ∈ Prof(S) for each 1 ≤ j ≤ n and 1 ≤ i ≤ kj ;

16

2 Wiring Diagrams

• for each 1 ≤ j ≤ n, ⎧  ⎨ aj , . . . , aj if kj > 0, 1 kj aj = ⎩∅ if kj = 0;

(2.3)

• a = (a 1 , . . . , a n ) is their concatenation. Then the associativity diagram

(2.4) is commutative. Unity Axioms Suppose d ∈ S. 1. If c = (c1 , . . . , cn ) ∈ Prof(S) has length n ≥ 1, then the right unity diagram

(2.5) is commutative. Here {∗} is the one-point set, and {∗}n is its n-fold product. 2. If b ∈ Prof(S), then the left unity diagram

(2.6) is commutative. Equivariance Axioms

Suppose that in (2.2) |bj | = kj ≥ 0.

2.1 Colored Operads

17

1. For each permutation σ ∈ Σn , the top equivariance diagram

(2.7) is commutative. Here σ k1 , . . . , kn  ∈ Σk1 +···+kn is the block permutation induced by σ that permutes the n consecutive blocks of lengths k1 , . . . , kn , leaving the relative order within each block unchanged. 2. Given permutations τj ∈ Σkj for 1 ≤ j ≤ n, the bottom equivariance diagram

(2.8) is commutative. Here the block sum τ1 ⊕ · · · ⊕ τn ∈ Σk1 +···+kn is the image / Σk +···+kn . of (τ1 , . . . , τn ) under the inclusion Σk1 × · · · × Σkn 1 A colored operad is a C-colored operad for some class C. We will also call a colored operad simply an operad. Remark 2.4. A 1-colored operad [22, 34–36], with S = {∗}, is usually called an operad or a symmetric operad. The underline notation for c ∈ Prof(S) and the d  vertical notation for c ∈ Prof(S) × S originated in [20]. See [51, section 9.6] for more discussion of these notations. In a 1-colored operad O, the entry of O whose input profile has length n is denoted O(n). Example 2.5 (Endomorphism Operads). 1. Each set X yields a 1-colored operad End(X), called the endomorphism operad, whose nth entry is the set Map(Xn , X) of functions with the operad structure in Motivation 2.2. 2. More generally, for a non-empty class C, suppose X = {Xc }c∈C is a C-indexed d  class of sets. Then there is a C-colored endomorphism operad whose c -entry is the set of functions Map(Xc1 × · · · × Xcn , Xd ) with the operad structure in Motivation 2.2. Example 2.6 (Monoids as Operads). Recall that a monoid is a triple (A, μ, 1) / A, and an element consisting of a set A, a binary operation μ : A × A 1 ∈ A such that the following two conditions are satisfied.

18

2 Wiring Diagrams

    Associativity μ μ(a, b), c = μ a, μ(b, c) for all a, b, c ∈ A. Unity μ(1, a) = a = μ(a, 1). A monoid is uniquely determined by the operad O with O(1) = A, O(n) = ∅ for all n = 1, μ as the only non-trivial operadic composition, and 1 ∈ A as the unit. Example 2.7 (Associative and Commutative Operads). 1. There is a 1-colored operad As, called the associative operad, whose nth entry is the symmetric group Σn for each n ≥ 0 with group multiplication as the symmetric group action and the identity e ∈ Σ1 as the unit. Given permutations σ ∈ Σn with n ≥ 1 and τi ∈ Σki for each 1 ≤ i ≤ n, the operadic composition is given by   γ σ ; τ1 , . . . , τn = σ k1 , . . . , kn  ◦ (τ1 ⊕ · · · ⊕ τn ) ∈ Σk1 +···+kn . Here σ k1 , . . . , kn  ∈ Σk1 +···+kn is the block permutation in (2.7), and τ1 ⊕ · · · ⊕ τn ∈ Σk1 +···+kn is the block sum in (2.8). The algebras of the operad As, in the sense of Definition 6.2, are precisely monoids. 2. There is a 1-colored operad Com, called the commutative operad, whose nth entry is a single point ∗ for each n ≥ 0. Its operad structure maps are all trivial maps, and its algebras, in the sense of Definition 6.2, are precisely commutative monoids, i.e., monoids whose multiplication maps are commutative. Example 2.8 (Operad of Graph Operations). We now discuss an operad from noncommutative probability theory [30]. By a finite directed graph, or just a graph, we mean a pair of finite sets (V , E) with V non-empty such that an element in E is an ordered pair (u, v) ∈ V 2 , where each such ordered pair may appear in E more than once. Elements in V and E are called vertices and edges, respectively, and an edge e = (u, v) is said to have initial vertex u and terminal vertex v, denoted / v. An edge of the form (v, v) is called a loop at v. An edge of the form e:u (u, v) or (v, u) is said to connect u and v. We say that a graph (V , E) is connected if for each pair of distinct vertices u and v, there exist edges ei for 1 ≤ i ≤ n for some n ≥ 1 such that each ei connects vi−1 and vi with v0 = u and vn = v. A graph operation is a connected graph (V , E) equipped with 1. an ordering σ of the set E of edges and 2. two possibly equal vertices in and out, called the input and the output. / (V  , E  ) An isomorphism of graph operations is a pair of bijections (V , E) on vertices and edges that preserves the initial and the terminal vertices of each edge, the ordering on edges, and the input and the output. We only consider graph operations up to isomorphisms. That is, if there is an isomorphism (V , E, σ, in, out)

/ (V  , E  , σ  , in , out )

of graph operations, then we consider them to be the same. For each n ≥ 0, denote by GrOpn the set of graph operations with n edges. So GrOp0 contains only the

2.1 Colored Operads

19

graph with one vertex, which is both the input and the output, and no edges. Here is a graph operation with two vertices and four edges, two of which are loops:

There is an operad structure on graph operations given by edge substitution as follows. Suppose G ∈ GrOpn with n ≥ 1 and Gi ∈ GrOpmi for 1 ≤ i ≤ n. Then the operadic composition G(G1 , . . . , Gn ) ∈ GrOpm1 +···+mn is obtained from G by replacing the ith edge ei in G by Gi and by identifying the initial (resp., terminal) vertex of ei with the input (resp., output) of Gi . The edge ordering of the operadic composition is induced by those of G and of the Gi ’s. The input and the output are inherited from G. The symmetric group action on GrOpn is given by permutation of the edge ordering. The operadic unit is the graph operation / out with two vertices and one edge from the input to the output. in For example, suppose G, H , and K are the following graph operations in GrOp2 :

Then the operadic composition G(H, K) is the graph operation with four edges above. The algebras of the operad GrOp are closely related to traffic spaces and non-commutative probability, as we will discuss in Example 6.8 below. Due to the presence of the colored units, a colored operad can also be defined in terms of a binary product, called the ◦i -composition, which leads to axioms that are sometimes easier to check in practice and that we will use in most of the rest of this monograph. In the one-colored linear setting, this alternative formulation of an operad was first made explicit in [31]. Motivation 2.9. Using functions as in Motivation 2.2, the operadic ◦i -compositions can be visualized as follows. Suppose f ∈ Map(Xc1 × · · · × Xcn , Xd )

and

g ∈ Map(Xb1 × · · · × Xbk , Xci )

are functions for some 1 ≤ i ≤ n, pictorially depicted as follows.

20

2 Wiring Diagrams

Then their ◦i -composition   f ◦i g = f ◦ Idi−1 , g, Idn−i is the picture

in which the output of g is used as the ith input of f . The operadic ◦i -composition is an abstraction of this f ◦i g of functions. With the above motivation in mind, we now recall this alternative formulation of an operad. The elementary relations in Sect. 3.3 are almost all stated in terms of the ◦i -compositions in the following definition.   Definition 2.10. Suppose S is a class. An S-colored operad O, 1, ◦ consists of the following data. 1. It has the same data as in (1)–(3) in Definition 2.3. 2. For each d ∈ S, c = (c1 , . . . , cn ) ∈ Prof(S) with length n ≥ 1, b ∈ Prof(S), and 1 ≤ i ≤ n, it is equipped with a map (2.9) called the ◦i -composition, where   c ◦i b = c1 , . . . , ci−1 , b, ci+1 , . . . , cn .



 ∅ if i=1

(2.10)

∅ if i=n

This data is required to satisfy the following associativity, unity, and equivariance axioms. Suppose d ∈ S, c = (c1 , . . . , cn ) ∈ Prof(S), b ∈ Prof(S) with length |b| = m, and a ∈ Prof(S) with length |a| = l.

2.1 Colored Operads

Associativity Axioms

21

There are two associativity axioms.

1. Suppose n ≥ 2 and 1 ≤ i < j ≤ n. Then the horizontal associativity diagram

(2.11) is commutative. 2. Suppose n, m ≥ 1, 1 ≤ i ≤ n, and 1 ≤ j ≤ m. Then the vertical associativity diagram

(2.12) is commutative. Unity Axioms

There are two unity axioms.

1. The left unity diagram

(2.13) is commutative. 2. If n ≥ 1 and 1 ≤ i ≤ n, then the right unity diagram

(2.14) is commutative.

22

2 Wiring Diagrams

Equivariance Axiom Suppose |c| = n ≥ 1, 1 ≤ i ≤ n, σ ∈ Σn , and τ ∈ Σm . Then the equivariance diagram

(2.15) is commutative, where   σ ◦i τ = σ 1i−1 , m, 1n−i  idi−1 ⊕ τ ⊕ idn−i ∈ Σn+m−1 .



 block permutation

block sum

On the right-hand side, the block sum permutes the interval [i, i + m − 1] via τ . The block permutation induced by σ regards the interval [i, i + m − 1] as a single block, within which the relative order is unchanged. Each ◦i -composition is also called an operadic composition or just a composition. Remark 2.11. Without the symmetric group action (2.1) and the equivariance axiom (2.15), a non-symmetric colored operad as in Definition 2.10 is exactly a multicategory as defined by Lambek [23, pp. 103–105]. In [23]: 1. 2. 3. 4.

d 

The elements in an entry O c of a colored operad O are called multimaps. The ◦i -composition (2.9) is called a substitution or a cut. The horizontal associativity axiom (2.11) is called the commutative law. The vertical associativity axiom (2.12) is called the associative law.

The reader is cautioned that there are several typographical errors in [23, pp. 104– 105] in the definition of a multicategory. Due to the presence of the colored units, the two definitions of a colored operad are in fact equivalent. Proposition 2.12. Definitions 2.3 and 2.10 of an S-colored operad are equivalent. Proof. In the 1-colored case, a proof can be found in [32, Prop. 13]. For the general colored case, the proof is similar and can be found in, e.g., [51, section 16.4]. The d  correspondence goes as follows. Given the operadic composition γ (2.2), y ∈ O c ci  with |c| = n ≥ 1, and x ∈ O b with 1 ≤ i ≤ n, one defines the ◦i -composition as   y ◦i x = γ y; 1c1 , . . . , 1ci−1 , x, 1ci+1 , . . . , 1cn .



 ∅ if i=1

∅ if i=n

2.2 Defining Wiring Diagrams

23 d 

Conversely, given the ◦i -compositions (2.9), y ∈ O c with |c| = n ≥ 1, and c  xi ∈ O bii for 1 ≤ i ≤ n with ki = |bi |, one defines the operadic composition γ as      γ y; x1, . . . , xn = (y ◦1 x1 ) ◦k1 +1 x2 · · · ◦k1 +···+kn−1 +1 xn . On the right-hand side, every pair of parentheses starts on the left.

(2.16)  

2.2 Defining Wiring Diagrams The operad of wiring diagrams WD has BoxS as its class of colors. So before we define wiring diagrams, we first define BoxS . We begin by recalling the basic definition of a category. The reader may consult [2, 25, 29] for a more in-depth discussion of category theory. In this monograph, we do not need anything fancy from category theory. All that the reader needs to know is that a category consists of a collection of objects, such as sets or finite sets, and maps between them that can be composed and that satisfy some natural unity and associativity axioms with respect to compositions. Motivation 2.13. To motivate the definition of a category, consider the collection of groups and group homomorphisms. Given group homomorphisms f : / G2 and g : G2 / G3 , there is a composition g ◦ f : G1 / G3 . G1 The identity map of each group serves as the identity for composition. Furthermore, composition of group homomorphisms is associative, in the sense that given a group / G4 , there is an equality homomorphism h : G3 (h ◦ g) ◦ f = h ◦ (g ◦ f ) of group homomorphisms. One can think of a category as an abstraction of the collection of groups, group homomorphisms, their composition, and the unity and the associativity axioms governing composition. Definition 2.14. A category C consists of the following data. Objects It is equipped with a collection Ob(C) of objects. For an object a in C, we will write either a ∈ Ob(C) or simply a ∈ C. Morphisms For any objects a, b ∈ Ob(C), it is equipped with a collection C(a, b) of morphisms with domain a and codomain b. A morphism f in C(a, b) is usually / b and is also called a map from a to b. denoted by f : a / b and Composition For any objects a, b, c ∈ Ob(C) and morphisms f : a / c, it is equipped with a morphism g ◦ f : a / c, called the g : b composition of f and g. / a, Identities Each object a ∈ Ob(C) is equipped with a morphism 1a : a called the identity morphism of a.

24

2 Wiring Diagrams

The above data is required to satisfy the following axioms. Unity c

For any objects a, b, c ∈ Ob(C) and morphisms g : a / a, there are equalities of morphisms g ◦ 1a = g ∈ C(a, b)

and

/ b and h :

1a ◦ h = h ∈ C(c, a).

Associativity For any objects a, b, c, d ∈ Ob(C) and morphisms f : a / c, and h : c / d, there is an equality of morphisms g:b

/ b,

(h ◦ g) ◦ f = h ◦ (g ◦ f ) in C(a, d). Example 2.15. Here are some basic examples of categories. In each case, the identity morphisms and the composition are the obvious ones. 1. There is an empty category with no objects and no morphisms. 2. There is a category ∗ with only one object ∗ and only the identity morphism of ∗. 3. There is a category Set whose objects are sets and whose morphisms are functions between sets. 4. There is a category Fin whose objects are finite sets and whose morphisms are functions between finite sets. Given any disjoint finite sets X1 , . . . , Xn , their

coproduct ni=1 Xi is the finite set given by their disjoint union. If the Xi ’s are not disjoint, we can still define their coproduct, but we must first replace each Xi (or just the ones with i ≥ 2) by an Xi equipped with a bijection to Xi such that the

resulting X1 , . . . , Xn are disjoint. Then the coproduct ni=1 Xi is defined as the disjoint union of the Xi for 1 ≤ i ≤ n, and it is well-defined up to isomorphism. If n = 0 then the coproduct is defined as the empty set ∅. In what follows, if the identity morphisms and the composition are obvious, then we will omit mentioning them. Example 2.16. A monoid (A, μ, 1) (Example 2.6) is a category with one object, whose only morphism set is A. Composition and identity are those of A, i.e., the multiplication μ and the unit element 1. Therefore, one can think of a category as a monoid with multiple objects. Example 2.17. Suppose O is an S-colored operad (Definition 2.3). Then O determines a category C whose objects are the elements in S. For c, d ∈ S the morphism d object C(c, d) is O c , and the identity morphism of c is the c-colored unit of O. Composition in C is the restriction of the operadic composition in O. Therefore, one can think of a colored operad as a generalization of a category in which the domain of each morphism is a finite sequence of objects. For wiring diagrams, we will usually consider finite sets in which each element is allowed to carry a value of some kind. The precise notion is given in the following definition.

2.2 Defining Wiring Diagrams

25

Definition 2.18. Suppose S is a non-empty class, and Fin is the category of finite sets and functions between them. 1. Denote by FinS the category in which: • an object is a pair (X, v) with X ∈ Fin and v : X / (Y, vY ) is a function X • a map (X, vX )

/ S a function; / Y such that the diagram

(2.17) is commutative. 2. An object (X, v) ∈ FinS is called an S-finite set. 3. For (X, v) ∈ FinS , we call v the value assignment for X. For each x ∈ X, v(x) ∈ S is called the value of x.

4. If (Xi , vi ) ∈ FinS for 1 ≤ i ≤ n, then their coproduct X = ni=1 Xi ∈ FinS has value assignment ni=1 vi . 5. The empty S-finite set is denoted by ∅. Definition 2.19. Suppose S is a non-empty class. 1. An S-box is a pair X = (Xin , Xout ) ∈ FinS ×FinS . If S is clear from the context, then we will drop S and call X a box. • An element of Xin is called an input of X. • An element of Xout is called an output of X. / S for the value assignment for X. • We write v = vX : Xin  Xout 2. The class of S-boxes is denoted by BoxS . 3. The empty S-box, denoted by ∅, is the S-box with ∅in = ∅out the empty set. Convention 2.20. From now on, whenever FinS or BoxS is used, we always assume that the class S is non-empty. Remark 2.21. In [47, Def. 3.1] an S-box is called a signed finite set. It is a slight generalization of what appears in [42, 48]. In [42] S is the class of pointed sets, where an S-box is called a black box. In [48] S is a set of representatives of isomorphism classes of second-countable smooth manifolds and smooth maps, or more generally the class of objects in a category with finite products. Convention 2.22. For the purpose of visualization, an S-box X will be drawn as follows.

(2.18)

26

2 Wiring Diagrams

On the left, the inputs of X are depicted as arrows going into the box, and the outputs of X are depicted as arrows leaving the box. Alternatively, if we do not need to specify the sizes of Xin and Xout , then we depict them using a generic arrow ⇒, as in the picture on the right. The value of each x ∈ Xin  Xout is either not depicted in the picture for simplicity, or it is written near the corresponding arrow. Definition 2.23. Suppose X1 , . . . , Xn are S-boxes for some n ≥ 0. Define the Sbox X = ni=1 Xi , called the coproduct, as follows. 1. If n = 0, then X = ∅, the empty S-box. 2. If n ≥ 1, then: Xin =

n  i=1

Xiin ,

Xout =

n  i=1

Xiout ,

and

vX =

n 

vXi .

i=1

Motivation 2.24. Before we define wiring diagrams, let us first provide a motivating example. A typical wiring diagram looks like this:

There is an output box Y (the outermost box in the picture), a finite number of input boxes X (which the above picture only has one), and a finite number of delay nodes (which the above picture again only has one). To make sense of such a picture, first of all, for each output y i of Y we need to specify where the arrow is coming from. In the example above, y 1 comes from x 1 , and both y 2 and y 3 come from the delay node d. We will say that each y i is a demand wire, and y 1 (resp., y 2 and y 3 ) is supplied by the supply wire x 1 (resp., d). Similarly, for each input xi of X and the delay node d, we again need to specify where the arrow is coming from. So d is also a demand wire, and by tracing the arrow ending at d backward, we see that it is supplied by the supply wire y1 . Starting at the input x1 (resp., x2 and x3 ) and tracing the arrow backward, we see that it is supplied by x 1 (resp., y1 and d). We will come back to this example precisely in Example 2.22 below. The above exercise tells us that the outputs of Y , the inputs of X, and the delay nodes are demand wires, in the sense that each of their elements demands a supply wire. The supply wires consist of the inputs of Y , the outputs of X, and the delay

2.2 Defining Wiring Diagrams

27

nodes. Each supply wire may supply multiple demand wires or none at all. For instance, in the above example, the supply wire x 1 supplies both the demand wires x1 and y 1 . On the other hand, the supply wires y2 and x 2 do not supply to any demand wires at all. We will call them wasted wires. To avoid pathological situations, one requirement of a wiring diagram is that a demand wire in the outputs of Y should not be supplied by a supply wire in the inputs of Y . In other words, we exclude pictures like this

in which the demand wire y  is directly supplied by the supply wire y. So we insist that an output of Y be supplied by either an output of an input box X or a delay node d. We will call this the non-instantaneity requirement. Wiring diagrams will be defined as equivalence classes of prewiring diagrams, as defined below. Definition 2.25. Suppose S is a class. An S-prewiring diagram is a tuple   ϕ = X, Y, DN, v, s

(2.19)

consisting of the following data. 1. Y = (Y in , Y out ) ∈ BoxS , called the output box of ϕ. • An element in Y in is called a global input for ϕ. • An element in Y out is called a global output for ϕ. 2. X = (X1 , . . . , Xn ) is a BoxS -profile for some n ≥ 0; i.e., each Xi ∈ BoxS . • We call Xi the ith

input box of ϕ. • Denote by X = ni=1 Xi ∈ BoxS the coproduct. 3. (DN, v) ∈ FinS is an S-finite set. An element of DN is called a delay node. Define: • Dm = Y out  Xin  DN ∈ FinS . An element of Dm is called a demand wire in ϕ. • Sp = Y in  Xout  DN ∈ FinS . An element of Sp is called a supply wire in ϕ.

28

2 Wiring Diagrams

Furthermore: • When DN is regarded as a subset of Dm, an element in Xin  DN is called an internal input for ϕ. • When DN is regarded as a subset of Sp, an element in Xout  DN is called an internal output for ϕ. 4. With a slight abuse of notation, we write

for the coproduct of the value assignments for X, Y , and DN. / Sp ∈ FinS is a map, called the supplier assignment for ϕ, such 5. s : Dm that y ∈ Y out ⊆ Dm implies s(y) ∈ Sp \ Y in = Xout  DN.

(2.20)

• The condition (2.20) is called the non-instantaneity requirement. • For w ∈ Dm, we call s(w) ∈ Sp the supplier or the supply wire of w. So noninstantaneity says that the supply wire of a global output cannot be a global input. • A supply wire w ∈ Y in that does not belong to the image of the supplier assignment s is called an external wasted wire. The set of external wasted w. wires in ϕ is denoted by ϕ− out • A supply wire w ∈ X  DN that does not belong to the image of the supplier assignment s is called an internal wasted wire. The set of internal w. wasted wires in ϕ is denoted by ϕ+ If S is clear from the context, then we will drop S and call ϕ a prewiring diagram. If we need to emphasize ϕ, then we will use subscripts such as Dmϕ , Spϕ , and sϕ . Remark 2.26. In the constructions that follow, the compatibility of the value assignments with the various supplier assignments are usually immediate because, / Sp is a map in in each prewiring diagram, the supplier assignment s : Dm FinS . Therefore, we will omit checking such compatibility. Definition 2.27. Suppose S is a class, ϕ = (X, Y, DN, v, s) is an S-prewiring diagram as in (2.19), and ϕ  = (X, Y, DN , v  , s  ) is another S-prewiring diagram with the same input boxes X and output box Y . / ϕ  is an isomorphism f0 : (DN, v) 1. An equivalence f : ϕ   (DN , v ) ∈ FinS such that the diagram /

2.2 Defining Wiring Diagrams

29

in FinS is commutative. / ϕ. 2. We say that ϕ and ϕ  are equivalent if there exists an equivalence ϕ 3. An S-wiring diagram is an equivalence class of S-prewiring diagrams. If S is clear from the context, we will drop S and just say wiring diagram. 4. The class of S-wiring diagrams with input boxes X = (X1 , . . . , Xn ) and output box Y is denoted by WD

Y  X

or

WD



 Y X1 ,...,Xn

.

(2.21)

The class of all S-wiring diagrams is denoted by WD. If we want to emphasize S, then we will write WDS . Convention 2.28. To simplify the presentation, we usually suppress the difference between a prewiring diagram and a wiring diagram. In any given wiring diagram, DN is a finite set in which each element d is equipped with a value v(d) ∈ S. We will suppress the difference between each delay node d and its value v(d). In other words, each wiring diagram has a unique representative in which: • each delay node is an element in S; / S sends each delay node to itself. • v : DN Unless otherwise specified, in the rest of this book, we will always use this Y  representative of a wiring diagram. For a wiring diagram ϕ ∈ WD X , we will sometimes draw it as

without drawing the input boxes X, the delay nodes, and the supplier assignment. Remark 2.29. Definition 2.27 of an S-wiring diagram is a slight generalization of the one given in [42], where S was taken to be the class of pointed sets. Note that Y when S is a proper class (e.g., the class of pointed sets), the collection WD X (2.21) is also a proper class, not a set. This is the reason why in Definition 2.3 we allow d O c to be a class, in contrast to what was stated in [42, Def. 2.1.2B]. Example 2.30. Suppose S is a non-empty class and: • Xin = {x1, x1 , x3 }, Xout = {x 1 , x 2 }, Y in = {y1 , y2 }, Y out = {y 1 , y 2 , y 3 }, and DN = {d}; • v(x2 ) = v(x3 ) = v(y1 ) = v(y 2 ) = v(y 3 ) = v(d) ∈ S;

30

2 Wiring Diagrams

• v(x1 ) = v(x 1 ) = v(y 1 ) ∈ S, and v(x 2 ) and v(y2 ) in S are arbitrary; • s(x1 ) = s(y 1 ) = x 1 , s(x2 ) = s(d) = y1 , and s(x3 ) = s(y 2 ) = s(y 3 ) = d. Then the above data defines a wiring diagram ϕ ∈ WD and output box Y , which can be depicted as follows:

Y  X

with one input box X

(2.22) The output box Y is drawn as the outermost box. The single input box X is the smaller box. The delay node d is drawn as a circle, which will be our convention from now on. The supply wires y2 ∈ Y in and x 2 ∈ Xout are not in the image of / Sp, so y2 (resp., x 2 ) is an external (resp., the supplier assignment s : Dm internal) wasted wire.

2.3 Operad Structure Throughout this section, S denotes a class. In this section, using Definition 2.10 of a colored operad, we define the colored operad structure on the collection WD of S-wiring diagrams (Definition 2.27). The equivariant structure is given by permuting the labels of the input boxes. Definition 2.31 (Equivariance in WD). Suppose Y ∈ BoxS , X is a BoxS -profile of length n, and σ ∈ Σn is a permutation. Define the function (2.23) Y 

by sending ϕ = (DN, v, s) ∈ WD X to ϕ = (DN, v, s) ∈ WD

that ni=1 Xi = ni=1 Xσ (i) ∈ BoxS .

Y  Xσ

, using the fact

Next we define the colored units. For a box Y , the Y -colored unit can be depicted as follows.

2.3 Operad Structure

31

Definition 2.32 (Units in WD). For each Y ∈ BoxS , the Y-colored unit is defined as the wiring diagram   Y  1Y = DN = ∅, s = Id ∈ WD Y

(2.24)

with: • no delay nodes and trivial v : DN • supplier assignment

/ S;

the identity function. Motivation 2.33. Before we define the ◦i composition (2.9) in WD, let us first describe the intuition behind the definition. Pictorially, the ◦i composition ϕ ◦i ψ in WD replaces the ith input box Xi in ϕ with the wiring diagram ψ, using Xiin and Xiout for the necessary wire connections. Here is a picture to keep in mind for ϕ ◦i ψ.

(2.25)

32

2 Wiring Diagrams

For simplicity we did not draw any delay nodes. In the actual definition below, we will take the coproduct of the sets of delay nodes in ϕ and ψ. Definition 2.34 (◦i -Composition in WD). Suppose: Y 

• ϕ = (DNϕ , vϕ , sϕ ) ∈ WD X with X = (X1 , . . . , Xn ), n ≥ 1, and 1 ≤ i ≤ n; X  • ψ = (DNψ , vψ , sψ ) ∈ WD Wi with |W | = r ≥ 0. Define the wiring diagram ϕ ◦i ψ ∈ WD



Y  X◦i W

as follows, where the BoxS -profile   X ◦i W = X1 , . . . , Xi−1 , W , Xi+1 , . . . , Xn is as in (2.10). 1. DNϕ◦i ψ = DNϕ  DNψ ∈ FinS , so vϕ◦i ψ = vϕ  vψ . 2. The supplier assignment for ϕ ◦i ψ,

(2.26)

in which the coproduct j =i is indexed by all j ∈ {1, . . . , i − 1, i + 1, . . . , n}, is defined as follows. Suppose z ∈ Dmϕ◦i ψ .

a. If z ∈ Y out  j =i Xjin  DNϕ ⊆ Dmϕ , then  sϕ◦i ψ (z) = b. If z ∈

r

in k=1 Wk

sϕ (z)

if sϕ (z) ∈ Xiout ;

sψ sϕ (z)

if sϕ (z) ∈ Xiout .

(2.27)

 DNψ ⊆ Dmψ , then

⎧ ⎪ ⎪ ⎨sψ (z) sϕ◦i ψ (z) = sϕ sψ (z) ⎪ ⎪ ⎩s s s (z) ψ ϕ ψ

if sψ (z) ∈ Xiin ; if sψ (z) ∈ Xiin and sϕ sψ (z) ∈ Xiout ; if sψ (z) ∈

This finishes the definition of ϕ ◦i ψ.

Xiin

and sϕ sψ (z) ∈

Xiout .

(2.28)

2.3 Operad Structure

33

Lemma 2.35. Definition 2.34 indeed defines a wiring diagram ϕ ◦i ψ in WD



Y  X◦i W

.

Proof. We need to check that the supplier assignment for ϕ ◦i ψ satisfies the non-instantaneity requirement (2.20). So suppose y ∈ Y out . We must show that sϕ◦i ψ (y) ∈ Y in . By (2.27) we have

sϕ◦i ψ (y) =

⎧

out ⎪ Xj  DNϕ ⎪ ⎨sϕ (y) ∈

if sϕ (y) ∈ Xiout ;

r

⎪ ⎪ Wkout  DNψ ⎩sψ sϕ (y) ∈

if sϕ (y) ∈ Xiout .

j =i

k=1

Here we have used the non-instantaneity requirement for both ϕ and ψ. So in either case we have that sϕ◦i ψ (y) ∈ Y in .   Many examples of the ◦i -composition in WD will be given in Chap. 3. We now prove that, equipped with the structure above, WD is a colored operad. Lemma 2.36. The ◦i -composition in Definition 2.34 satisfies the left unity axiom (2.13), the right unity axiom (2.14), and the equivariance axiom (2.15). Proof. This follows from a direct inspection of the definitions of the equivariant structure (2.23) and the colored units in WD (2.24).   Next we show that WD satisfies the associativity axioms (2.11) and (2.12). The reader may wish to skip the proofs of the following two Lemmas and simply look at the pictures during the first reading. Motivation 2.37. For the horizontal associativity axiom (2.11), one should keep in mind the following picture for the iterated operadic composition (ϕ ◦j ζ ) ◦i ψ.

(2.29) Note that on the right, ψ and ζ are depicted as gray boxes because their output boxes—namely Yi and Yj —are no longer input boxes in (ϕ ◦j ζ ) ◦i ψ. Furthermore, for simplicity the delay nodes are not drawn.

34

2 Wiring Diagrams

Lemma 2.38. The ◦i -composition in Definition 2.34 satisfies the horizontal associativity axiom (2.11). Proof. Suppose: Z 

• ϕ ∈ WD Y  with |Y | = n ≥ 2 and 1 ≤ i < j ≤ n; Y • ψ ∈ WD Wi with |W | = l; Yj  • ζ ∈ WD X with |X| = m. We must show that     Z ϕ ◦j ζ ◦i ψ = (ϕ ◦i ψ) ◦j −1+l ζ ∈ WD (Y ◦j X)◦i W .

(2.30)

By Lemma 2.35 we already know that both sides are well-defined wiring diagrams in the indicated entry of WD. Moreover, both sides have DNϕ DNψ DNζ ∈ FinS as the set of delay nodes. So it remains to show that their supplier assignments are equal. Note that both sides in (2.30) have demand wires Dm = Z out 



Ypin 

p =i,j

l 

Wqin 

q=1

m 

Xrin  DNϕ  DNψ  DNζ

r=1

in which the coproduct p =i,j is indexed by all 1 ≤ p ≤ n such that p = i, j . Similarly, both sides in (2.30) have supply wires Sp = Z in 



Ypout 

p =i,j

l 

Wqout 

q=1

m 

Xrout  DNϕ  DNψ  DNζ .

r=1

Using the definitions (2.27) and (2.28), it follows from direct inspection that both / Sp. sides in (2.30) have the following supplier assignment s : Dm

1. If v ∈ Z out  p =i,j Ypin  DNϕ ⊆ Dmϕ , then

s(v) =

2. If v ∈

l

in q=1 Wq

⎧ ⎪ ⎪ ⎨sϕ (v)

if sϕ (v) ∈ Yiout  Yjout ;

s s (v) ⎪ψ ϕ ⎪ ⎩s s (v) ζ ϕ

if sϕ (v) ∈ Yjout .

if sϕ (v) ∈ Yiout ;

 DNψ ⊆ Dmψ , then

⎧ ⎪ sψ (v) ⎪ ⎪ ⎪ ⎨s s (v) ϕ ψ s(v) = ⎪sψ sϕ sψ (v) ⎪ ⎪ ⎪ ⎩ sζ sϕ sψ (v)

if sψ (v) ∈ Yiin ; if sψ (v) ∈ Yiin and sϕ sψ (v) ∈ Yiout  Yjout ; if sψ (v) ∈ Yiin and sϕ sψ (v) ∈ Yiout ; if sψ (v) ∈ Yiin and sϕ sψ (v) ∈ Yjout .

2.3 Operad Structure

3. Finally, if v ∈

35

m

in r=1 Xr

 DNζ ⊆ Dmζ , then

⎧ ⎪ s (v) ⎪ ⎪ζ ⎪ ⎨s s (v) ϕ ζ s(v) = ⎪sψ sϕ sζ (v) ⎪ ⎪ ⎪ ⎩ sζ sϕ sζ (v)

if sζ (v) ∈ Yjin ; if sζ (v) ∈ Yjin and sϕ sζ (v) ∈ Yiout  Yjout ; if sζ (v) ∈ Yjin and sϕ sζ (v) ∈ Yiout ; if sζ (v) ∈ Yjin and sϕ sζ (v) ∈ Yjout .

This finishes the proof of the desired equality (2.30).

 

Motivation 2.39. For the vertical associativity axiom, one should keep the following picture of ϕ ◦i (ψ ◦j ζ ) in mind.

(2.31) Once again on the right, ζ is depicted as a gray box because its output box Xj is no longer an input box in ϕ ◦i (ψ ◦j ζ ). Furthermore, for simplicity the delay nodes are not drawn. Lemma 2.40. The ◦i -composition in Definition 2.34 satisfies the vertical associativity axiom (2.12). Proof. Suppose: Z 

• ϕ ∈ WD Y  with |Y | = n ≥ 1 and 1 ≤ i ≤ n; Y • ψ ∈ WD Xi with |X| = m ≥ 1 and 1 ≤ j ≤ m; Xj  • ζ ∈ WD W with |W | = l. We must show that     Z (ϕ ◦i ψ) ◦i−1+j ζ = ϕ ◦i ψ ◦j ζ ∈ WD (Y ◦i X)◦i−1+j W .

(2.32)

36

2 Wiring Diagrams

By Lemma 2.35 we already know that both sides are well-defined wiring diagrams in the indicated entry of WD. Moreover, both sides have DNϕ DNψ DNζ ∈ FinS as the set of delay nodes. So it remains to show that their supplier assignments are equal. Note that both sides in (2.32) have demand wires Dm = Z out 





Ypin 

p =i

Xqin 

q =j

l 

Wrin  DNϕ  DNψ  DNζ

r=1

in which p =i is indexed by all 1 ≤ p ≤ n such that p = i, and q =j is indexed by all 1 ≤ q ≤ m such that q = j . Similarly, both sides in (2.32) have supply wires Sp = Z in 



Ypout 

p =i



Xqout 

q =j

l 

Wrout  DNϕ  DNψ  DNζ .

r=1

Using the definitions (2.27) and (2.28), it follows from direct inspection that both / Sp. sides in (2.32) have the following supplier assignment s : Dm

1. If v ∈ Z out  p =i Ypin  DNϕ ⊆ Dmϕ , then

s(v) =

⎧ ⎪ ⎪ ⎨sϕ (v) sψ sϕ (v) ⎪ ⎪ ⎩s s s (v) ζ ψ ϕ

2. If v ∈

q =j

if sϕ (v) ∈ Yiout ; if sϕ (v) ∈ Yiout and sψ sϕ (v) ∈ Xjout ; if sϕ (v) ∈ Yiout and sψ sϕ (v) ∈ Xjout .

Xqin  DNψ ⊆ Dmψ , then

⎧ ⎪ sψ (v) ⎪ ⎪ ⎪ ⎪ ⎪ sζ sψ (v) ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨sϕ sψ (v) s(v) = sψ sϕ sψ (v) ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ sζ sψ sϕ sψ (v) ⎪ ⎪ ⎪ ⎩

if sψ (v) ∈ Xjout  Yiin ; if sψ (v) ∈ Xjout ; if sψ (v) ∈ Yiin and sϕ sψ (v) ∈ Yiout ; if sψ (v) ∈ Yiin , sϕ sψ (v) ∈ Yiout , and sψ sϕ sψ (v) ∈ Xjout ; if sψ (v) ∈ Yiin , sϕ sψ (v) ∈ Yiout , and sψ sϕ sψ (v) ∈ Xjout .

2.4 Summary of this Chapter

3. If v ∈

l

in r=1 Wr

37

 DNζ ⊆ Dmζ , then

⎧ ⎪ sζ (v) ⎪ ⎪ ⎪ ⎪ ⎪ sψ sζ (v) ⎪ ⎪ ⎪ ⎪ ⎪ ⎪sζ sψ sζ (v) ⎪ ⎪ ⎪ ⎨s s s (v) ϕ ψ ζ s(v) = ⎪ ⎪sψ sϕ sψ sζ (v) ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ sζ sψ sϕ sψ sζ (v) ⎪ ⎪ ⎪ ⎩

if sζ (v) ∈ Xjin ; if sζ (v) ∈ Xjin and sψ sζ (v) ∈ Xjout  Yiin ; if sζ (v) ∈ Xjin and sψ sζ (v) ∈ Xjout ; if sζ (v) ∈ Xjin , sψ sζ (v) ∈ Yiin , and sϕ sψ sζ (v) ∈ Yiout ; if sζ (v) ∈ Xjin , sψ sζ (v) ∈ Yiin , sϕ sψ sζ (v) ∈ Yiout , and sψ sϕ sψ sζ (v) ∈ Xjout ; if sζ (v) ∈ Xjin , sψ sζ (v) ∈ Yiin , sϕ sψ sζ (v) ∈ Yiout , and sψ sϕ sψ sζ (v) ∈ Xjout .

 

This finishes the proof of the desired equality (2.32).

Theorem 2.41. For any class S, when equipped with the structure in Definitions 2.31–2.34, WD in Definition 2.27 is a BoxS -colored operad, called the operad of wiring diagrams. Proof. In view of Definition 2.10, this follows from Lemmas 2.36, 2.38, and 2.40.   Remark 2.42. When S is the class of pointed sets, Theorem 2.41 is proved in [42, section 2]. The proof in [42] is somewhat different than ours because it uses Definition 2.3 of a colored operad instead of Definition 2.10.

2.4 Summary of this Chapter 



1. An S-colored operad consists of a class O c1 ,...,cn for each d, c1 , . . . , cn ∈ S and n ≥ 0 together with symmetric group actions, an operadic composition, and colored units that satisfy the associativity, unity, and equivariance axioms. 2. Every operad is determined by the ◦i -compositions. 3. An S-wiring diagram has a finite number of input boxes, an output box, an S-finite set of delay nodes, and a supplier assignment that satisfies the noninstantaneity requirement. 4. For each class S, the collection of S-wiring diagrams WD is a BoxS -colored operad. d

Chapter 3

Generators and Relations

Fix a class S. The purpose of this chapter is to describe a finite number of wiring diagrams that we will later show to be sufficient to describe the entire operad WD of wiring diagrams (Theorems 5.22) as well as its variants WD• (Theorem 5.29) and WD0 (Theorem 5.37). One may also regard this chapter as consisting of a long list of examples of wiring diagrams. In Sect. 3.1 we describe eight wiring diagrams, called the generating wiring diagrams. In Theorem 5.11 we will show that they generate the operad WD of wiring diagrams. This means that every wiring diagram can be obtained from finitely many generating wiring diagrams via iterated operadic compositions. For now one may think of the generating wiring diagrams as examples of wiring diagrams. In Sect. 3.2 we explain why a wiring diagram with an internal wasted wire is not among the generating wiring diagrams. More concretely, we will observe in Proposition 3.13 that an internal wasted wire can be generated using two generating wiring diagrams. In Sect. 3.3 we describe 28 elementary relations among the generating wiring diagrams. In Theorem 5.22 we will show that these elementary relations together with the operad associativity and unity axioms—(2.11)–(2.14)—for the generating wiring diagrams generate all the relations in the operad WD of wiring diagrams. In other words, suppose an arbitrary wiring diagram can be built in two ways using the generating wiring diagrams. Then there exists a finite sequence of steps connecting them in which each step is given by one of the 28 elementary relations or an operad associativity/unity axiom for the generating wiring diagrams. For now one may think of the elementary relations as examples of the operadic composition in the operad WD.

© Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_3

39

40

3 Generators and Relations

3.1 Generating Wiring Diagrams Recall the definition of a wiring diagram (Definition 2.27). In this section, we introduce 8 wiring diagrams, called the generating wiring diagrams. They will be used in later chapters to give a finite presentation for the operad WD of wiring diagrams. Definition 3.1. Define the empty wiring diagram  ∈ WD 1. 2. 3. 4.

∅

with:

no input boxes; the empty box ∅ (Definition 2.19) as the output box; no delay nodes (i.e., DN = ∅); / ∅ = Sp the trivial function. supplier assignment s : Dm = ∅

The next wiring diagram has a delay node as depicted in the following picture, where we use the convention that delay nodes are drawn as circles as in (2.22).

Definition 3.2. Suppose d ∈ S. Denote also by d ∈ BoxS the box with one input and one output,both also denoted by d and having values d ∈ S. Define the 1-delay d node δd ∈ WD as the wiring diagram with: 1. 2. 3. 4.

no input boxes; the output box d = ({d}, {d}), in which both d’s have values d ∈ S; DN = {d}, in which d has value d ∈ S; supplier assignment

the identity function that takes d ∈ Y out to d ∈ DN and d ∈ DN to d ∈ Y in . Next we define the wiring diagram:

Definition 3.3. Suppose X, Y ∈ BoxS together with isomorphisms f in : Xin ∼ = Y in Y out out out ∼ and f :Y = X in FinS . Define the wiring diagram τf ∈ WD X with: 1. one input box X and output box Y ; 2. no delay nodes;

3.1 Generating Wiring Diagrams

41

3. supplier assignment

the coproduct of the given isomorphisms. We will often suppress the given isomorphisms and simply write τX,Y or even τ , which will be called a name change. Next we define the wiring diagram:

Definition 3.4. Suppose X, Y ∈ BoxS . Define the wiring diagram XY  WD X,Y with:

θX,Y ∈

1. two input boxes (X, Y ) and output box X  Y ; 2. no delay nodes; 3. supplier assignment

the identity map. We will call θX,Y a 2-cell. Next we define the wiring diagram:

Definition 3.5. Suppose: • X ∈ BoxS , and (x+ , x− ) ∈ Xout × Xin such that v(x+ ) = v(x− ) ∈ S. • X \ x ∈ BoxS is obtained from X by removing x± , so (X \ x)in = Xin \ {x− } and (X \ x)out = Xout \ {x+ }.

42

3 Generators and Relations

Define the wiring diagram λX,x ∈ WD

X\x  X

with:

1. one input box X and output box X \ x; 2. no delay nodes; 3. supplier assignment

given by s(x− ) = x+ and the identity function everywhere else. We will call the wiring diagram λX,x a 1-loop. Next we define the wiring diagram:

Definition 3.6. Suppose: • X ∈ BoxS , and x1 , x2 ∈ Xin are distinct elements such that v(x1 ) = v(x2 ) ∈ S. • Y = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 , so Y in = Xin /(x1 = x2 ) and Y out = Xout . The identified element of x1 and x2 in Y in will be denoted by x12. Define the wiring diagram σX,x1 ,x2 ∈ WD

Y  X

with:

1. one input box X and output box Y ; 2. no delay nodes; 3. supplier assignment

that sends both x1 , x2 ∈ Xin to x12 ∈ Y in and is the identity function everywhere else.

3.1 Generating Wiring Diagrams

43

We will call the wiring diagram σX,x1 ,x2 an in-split. Next we define the wiring diagram:

Definition 3.7. Suppose: • Y ∈ BoxS , and y1 , y2 ∈ Y out are distinct elements such that v(y1 ) = v(y2 ) ∈ S. • X = Y/(y1 = y2 ) ∈ BoxS is obtained from Y by identifying y1 and y2 , so Xin = Y in and Xout = Y out /(y1 = y2 ). The identified element of y1 and y2 in Xout will be denoted by y12 . Define the wiring diagram σ Y,y1 ,y2 ∈ WD

Y  X

with:

1. one input box X and output box Y ; 2. no delay nodes; 3. supplier assignment

that sends both y1 , y2 ∈ Y out to y12 ∈ Xout and is the identity function everywhere else. We will call the wiring diagram σ Y,y1 ,y2 an out-split. Next we define the following wiring diagram with an external wasted wire:

Definition 3.8. Suppose: • Y ∈ BoxS , and y ∈ Y in . • X ∈ BoxS is obtained from Y by removing y, so Xin = Y in \ {y} and Xout = Y out .

44

3 Generators and Relations

Define the wiring diagram ωY,y ∈ WD

Y  X

with:

1. one input box X and output box Y ; 2. no delay nodes; 3. supplier assignment

the inclusion. We will call the wiring diagram ωY,y a 1-wasted wire. Definition 3.9. The eight wiring diagrams in Definitions 3.1–3.8 will be referred to as generating wiring diagrams. Remark 3.10. Among the generating wiring diagrams: 1. A 1-delay node δd (Definition 3.2) is the only wiring diagram that has a delay node. 2. A 1-wasted wire ωY,y (Definition 3.8) is the only wiring diagram that has an external wasted wire, namely y ∈ Y in . 3. None has an internal wasted wire (Definition 2.25). As we will see in Proposition 3.13 below, an internal wasted wire can be generated using a 1-loop and a 1-wasted wire, hence is not needed as a generator. 4. The empty wiring diagram  (Definition 3.1) and a 1-delay node δd are 0-ary elements in WD. 5. A name change τ (Definition 3.3), a 1-loop λX,x (Definition 3.5), an in-split σX,x1 ,x2 (Definition 3.6), an out-split σ Y,y1 ,y2 (Definition 3.7), and a 1-wasted wire ωY,y are unary elements in WD. 6. A 2-cell θX,Y (Definition 3.4) is a binary element in WD.

3.2 Internal Wasted Wires Recall from Definition 2.25 that an internal wasted wire is an internal output, hence a supply wire, that does not belong to the image of the supplier assignment. The purpose of this section is to explain why the wiring diagram

3.2 Internal Wasted Wires

45

that has an internal wasted wire x is not needed as a generating wiring diagram. First we define this wiring diagram. Definition 3.11. Suppose: • X ∈ BoxS , and x ∈ Xout . • Y = X \ {x} ∈ BoxS is obtained from X by removing x. Define the wiring diagram ωX,x ∈ WD

Y  X

with:

1. one input box X and output box Y ; 2. no delay nodes; 3. supplier assignment

the inclusion. We will call the wiring diagram ωX,x a 1-internal wasted wire. Motivation 3.12. The following observation says that a 1-internal wasted wire can be obtained as the substitution of a 1-wasted wire into a 1-loop, both of which are generating wiring diagrams. This is expressed in the following picture

in which the intermediate gray box will be called W below. Proposition 3.13. Suppose: Y 

• ωX,x ∈ WD X is a 1-internal wasted wire (Definition 3.11). in • W = X  {w} ∈ Box S such that w ∈ W satisfies v(w) = v(x) ∈ S. Y • λW,{w,x} ∈ WD W is the 1-loop (Definition 3.5) in which x ∈ Xout = W out is the supply wire of w ∈ W in . W  • ωW,w ∈ WD X is a 1-wasted wire (Definition 3.8). Then 

   Y  λW,{w,x} ◦1 ωW,w = ωX,x ∈ WD X .

(3.1)

46

3 Generators and Relations Y 

Proof. By definition both sides of (3.1) belong to WD X and have no delay nodes. It remains to check that their supplier assignments are equal. By the definitions of ◦1 (Definition and   1-wasted wire, the supplier assignment of the left 2.34), 1-loop, hand side λW,{w,x} ◦1 ωX,x , namely

is the inclusion. By Definition 3.11 this is also the supplier assignment of the 1internal wasted wire ωX,x .   As a consequence of (3.1), the 1-internal wasted wire ωX,x is not needed as a generating wiring diagram.

3.3 Elementary Relations The purpose of this section is to introduce 28 elementary relations among the generating wiring diagrams (Definition 3.9). Each elementary relation is proved by a simple inspection of the relevant definitions of the generating wiring diagrams and operadic compositions, similar to the proofs of Lemmas 2.38, 2.40, and Proposition 3.13 above. Therefore, we will prove only the first one and omit the proofs for the rest, providing a picture instead in most cases. We will frequently use the ◦i -composition (2.9) in describing these elementary relations. Notation 3.14. Suppose O is an S-colored operad (Definition 2.10), and T is a set. 1. If ϕ ∈ O write

d  c

c 

where the input profile (c) has length 1 and if φ ∈ O b , then we

ϕ ◦ φ = ϕ ◦1 φ.

(3.2)

2. Suppose ϕ1 , . . . , ϕk ∈ O such that each of ϕ1 , . . . , ϕk−1 belongs to an entry of O whose input profile has length 1. Then we write   ϕ1 ◦ · · · ◦ ϕk = · · · (ϕ1 ◦1 ϕ2 ) ◦1 · · · ◦1 ϕk

(3.3)

3.3 Elementary Relations

47

whenever the right-hand side is defined, in which each pair of parentheses starts on the left. For example, we have ϕ1 ◦ ϕ2 ◦ ϕ3 = (ϕ1 ◦1 ϕ2 ) ◦1 ϕ3 ,   ϕ1 ◦ ϕ2 ◦ ϕ3 ◦ ϕ4 = (ϕ1 ◦1 ϕ2 ) ◦1 ϕ3 ◦1 ϕ4 . 3. Write |T | for the cardinality of T . The first six relations concern the name change wiring diagrams (Definition 3.3). The first relation says that two consecutive name changes can be composed into one name change. Proposition 3.15. Suppose: Z 

Y 

• τY,Z ∈ WD Y  and τX,Y ∈ WD X are name changes. Z • τX,Z ∈ WD X is the name change given by composing the isomorphisms that define τY,Z and τX,Y . Then     Z  τY,Z ◦ τX,Y = τX,Z ∈ WD X .

(3.4)

Proof. We are given isomorphisms f in : Xin ∼ = Y in and f out : Y out ∼ = Xout in in in out out out ∼ ∼ for τX,Y and isomorphisms g : Y = Z and g : Z for τY,Z . = Y The name change τX,Z given by composing these isomorphisms is defined by the isomorphisms g in ◦ f in : Xin ∼ = Z in

and

f out ◦ g out : Z out ∼ = Xout .

On the other hand, by Definition 2.34 the composition τY,Z ◦ τX,Y has no delay nodes, since neither τX,Y nor τY,Z has a delay node. Its supplier assignment is the function

given by s(z) = sτX,Y sτY,Z (z) = f out g out (z) for z ∈ Z out ; s(x) = sτY,Z sτX,Y (x) = g in f in (x) for x ∈ Xin . This is the same supplier assignment as that of the name change τX,Z above.

 

The next relation says that name changes inside a 2-cell (Definition 3.4) can be rewritten as a name change outside of a 2-cell.

48

3 Generators and Relations

Proposition 3.16. Suppose: X  

Y  

• τX,X ∈ WD X and τY,Y  ∈ WD Y are name changes. X Y   • τXY,X Y  ∈ WD XY is the name change induced by τX,X and τY,Y  . X Y   XY  • θX ,Y  ∈ WD X ,Y  and θX,Y ∈ WD X,Y are 2-cells. Then       X Y   θX ,Y  ◦1 τX,X ◦2 τY,Y  = τXY,X Y  ◦ θX,Y ∈ WD X,Y .

(3.5)

The next relation says that a name change inside a 1-loop (Definition 3.5) can be rewritten as a name change of a 1-loop. Proposition 3.17. Suppose: X ∈ BoxS , (x+ , x− ) ∈ Xout × Xin such that v(x+ ) = v(x− ) ∈ S. X \ x ∈ Box S is obtained from X by removing x± . X\x λX,x ∈ WD  X is the corresponding 1-loop. Y τX,Y ∈ WD X is a name change such that (y+ , y− ) ∈ Y out × Y in corresponds to (x+ , x− ).  Y \y • λY,y ∈ WD Y is the corresponding 1-loop.  Y \y  • τX\x,Y \y ∈ WD X\x is the name change induced by τX,Y .

• • • •

Then         Y \y  λY,y ◦ τX,Y = τX\x,Y \y ◦ λX,x ∈ WD X .

(3.6)

The next relation says that a name change inside an in-split (Definition 3.6) can be rewritten as a name change of an in-split. Proposition 3.18. Suppose: X ∈ BoxS , and x1 , x2 ∈ Xin are distinct elements such that v(x1 ) = v(x2 ) ∈ S. X = X/(x1 =x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 . X σX,x1 ,x2 ∈ WD is the corresponding in-split. Y  X τX,Y ∈ WD X is a name change with y1 , y2 ∈ Y in corresponding to x1 , x2 ∈ Xin . • Y  = Y/(y1 = y2 ) ∈ BoxS is obtained from Y by identifying y1 and y2 . Y • σY,y1 ,y2 ∈ WD Y is the corresponding in-split. Y   • τX ,Y  ∈ WD X is the name change induced by τX,Y .

• • • •

Then         Y   σY,y1 ,y2 ◦ τX,Y = τX ,Y  ◦ σX,x1 ,x2 ∈ WD X . The next relation is the out-split (Definition 3.7) analogue of (3.7).

(3.7)

3.3 Elementary Relations

49

Proposition 3.19. Suppose: Y ∈ BoxS , and y1 , y2 ∈ Y out are distinct elements such that v(y1 ) = v(y2 ) ∈ S. Y  = Y/(y1 = y2) ∈ BoxS is obtained from Y by identifying y1 and y2 . Y  σ Y,y1 ,y2 ∈ WD is an out-split. Y  Y τX,Y ∈ WD X is a name change with x1 , x2 ∈ Xout corresponding to y1 , y2 ∈ Y out . • X = X/(x1 = x2) ∈ BoxS is obtained from X by identifying x1 and x2 . X  • σ X,x1 ,x2 ∈ WD is the corresponding out-split.  Y  X • τX ,Y  ∈ WD X is the name change induced by τX,Y .

• • • •

Then         Y  σ Y,y1 ,y2 ◦ τX ,Y  = τX,Y ◦ σ X,x1 ,x2 ∈ WD X .

(3.8)

The next relation says that a name change inside a 1-wasted wire (Definition 3.8) can be rewritten as a name change of a 1-wasted wire. Proposition 3.20. Suppose: • • • • • •

Y ∈ BoxS , y ∈ Y in , and Y  = Y \ {y} ∈ BoxS is obtained from Y by removing y. Y ωY,y ∈ WD Y  is the corresponding 1-wasted wire. Y  τX,Y ∈ WD X is a name change with x ∈ Xin corresponding to y ∈ Y in . X ∈ BoxS is obtained from X by removing x. X ωX,x ∈ WD X is the corresponding 1-wasted wire. Y   τX ,Y  ∈ WD X is the name change induced by τX,Y .

Then 

       Y  ωY,y ◦ τX ,Y  = τX,Y ◦ ωX,x ∈ WD X .

(3.9)

The next seven relations concern 2-cells (Definition 3.4). The following relation says that substituting the empty wiring diagram (Definition 3.1) into a 2-cell yields a colored unit (2.24). Proposition 3.21. Suppose: X 

• X ∈ BoxS with X-colored unit 1X ∈ WD X . ∅ •  ∈ WD is the empty wiring diagram.  X  • θX,∅ ∈ WD X,∅ is the 2-cell with input boxes (X, ∅) and output box X. Then θX,∅ ◦2  = 1X ∈ WD

X X

.

(3.10)

The next relation is the associativity property of 2-cells. It says that, in the picture below, the wiring diagram in the middle can be constructed using two 2-cells, either as the operadic composition on the left or the one on the right.

50

3 Generators and Relations

Proposition 3.22. Suppose: XY Z

XY 

• θXY,Z ∈ WD  XY,Z  and θX,Y ∈ WD X,Y  are 2-cells. XY Z Y Z • θX,Y Z ∈ WD X,Y Z and θY,Z ∈ WD Y,Z are 2-cells. Then         XY Z θXY,Z ◦1 θX,Y = θX,Y Z ◦2 θY,Z ∈ WD X,Y,Z .

(3.11)

The next relation is the commutativity property of 2-cells and uses the equivariant structure in WD (2.23). Proposition 3.23. Suppose: XY 

• θX,Y ∈ WD X,Y is a 2-cell. • (1 2) ∈ Σ2 is the non-trivial permutation. Then θX,Y (1 2) = θY,X ∈ WD

Y X Y,X

.

(3.12)

The next relation says that substituting a 1-loop inside a 2-cell can be rewritten as substituting a 2-cell inside a 1-loop. It gives two different ways to construct the wiring diagram in the middle in the picture below using a 1-loop and a 2-cell, either as the operadic composition on the left or the one on the right.

Proposition 3.24. Suppose: • X ∈ BoxS , and (x+ , x− ) ∈ Xout × Xin such that v(x+ ) = v(x− ) ∈ S. • X \ x ∈ BoxS is obtained from X by removing x± .

3.3 Elementary Relations (XY )\{x}

51 XY 

• θX\x,Y ∈ WD X\x,Y and θX,Y ∈ WD X,Y are 2-cells. X\x  (XY )\{x} • λX,x ∈ WD X and λXY,x ∈ WD XY are the corresponding 1-loops. Then 

       (XY )\{x} θX\x,Y ◦1 λX,x = λXY,x ◦ θX,Y ∈ WD X,Y .

(3.13)

All the relations in the rest of this section can be illustrated with pictures similar to the two previous pictures, each one showing how a wiring diagram can be built in two different ways using operadic compositions. So we will mostly just draw the picture of the wiring diagram being built without the accompanying pictures of the operadic compositions. The next relation says that substituting an in-split inside a 2-cell can be rewritten as substituting a 2-cell inside an in-split. It gives two different ways to construct the following wiring diagram using an in-split and a 2-cell:

Proposition 3.25. Suppose: • • • •

X ∈ BoxS , and x1 , x2 ∈ Xin are distinct elements such that v(x1 ) = v(x2 ) ∈ S. X = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 . XY  X Y θX ,Y ∈ WD X ,Y and θX,Y ∈ WD X,Y are 2-cells. X   X Y  σX,x1 ,x2 ∈ WD X and σXY,x1 ,x2 ∈ WD XY are in-splits.

Then         X Y  θX ,Y ◦1 σX,x1 ,x2 = σXY,x1 ,x2 ◦ θX,Y ∈ WD X,Y .

(3.14)

The next relation says that substituting an out-split inside a 2-cell can be rewritten as substituting a 2-cell inside an out-split. It gives two different ways to construct the following wiring diagram using an out-split and a 2-cell:

52

3 Generators and Relations

Proposition 3.26. Suppose: • • • •

X ∈ BoxS , and x1 , x2 ∈ Xout are distinct elements such that v(x1 ) = v(x2 ) ∈ S. X = X/(x1 = x 2 ) ∈ BoxS is obtained from X by identifying x1 and x2 . X Y  XY θX,Y ∈ WD X,Y and θX ,Y ∈ WD X ,Y are 2-cells.  XY  X σ X,x1 ,x2 ∈ WD X and σ XY,x1 ,x2 ∈ WD X Y are out-splits.

Then 

       XY  θX,Y ◦1 σ X,x1 ,x2 = σ XY,x1 ,x2 ◦ θX ,Y ∈ WD X ,Y .

(3.15)

The next relation says that substituting a 1-wasted wire inside a 2-cell can be rewritten as substituting a 2-cell inside a 1-wasted wire. It gives two different ways to construct the following wiring diagram using a 1-wasted wire and a 2-cell:

Proposition 3.27. Suppose: • X ∈ BoxS , x0 ∈ Xin , and X = X \ {x0 } ∈ BoxS is obtained from X by removing x0 . XY  X Y  • θX,Y ∈ WD X,Y and θX ,Y ∈ WD X ,Y are 2-cells. X XY  • ωX,x0 ∈ WD X and ωXY,x0 ∈ WD X Y are 1-wasted wires. Then         XY  θX,Y ◦1 ωX,x0 = ωXY,x0 ◦ θX ,Y ∈ WD X ,Y .

(3.16)

The following six relations concern 1-loops. The next relation is the commutativity property of 1-loops. It gives two different ways to construct the following wiring diagram, which we will call a double-loop, using two 1-loops:

3.3 Elementary Relations

53

Proposition 3.28. Suppose: 1 = x 2 ∈ X in , and x 1 = x 2 ∈ X out such that v(x 1 ) = v(x 1 ) ∈ S • X ∈ BoxS , x− − + + + − 2 ) = v(x 2 ) ∈ S. and v(x+ − 1 , x 2 , and • X \ x 1 , X \ x 2 , and X \ x ∈ BoxS are obtained from X by removing x± ± 1 2 {x± , x± }, respectively.  X\x  X\x 1 • λX\x 1 ,x 2 ∈ WD X\x 1 and λX,x 1 ∈ WD X are 1-loops.

• λX\x 2 ,x 1 ∈ WD

 X\x  X\x 2

and λX,x 2 ∈ WD

X\x 2 X

are 1-loops.

Then 

       X\x  λX\x 1 ,x 2 ◦ λX,x 1 = λX\x 2 ,x 1 ◦ λX,x 2 ∈ WD X .

(3.17)

The next relation is the commutativity property between 1-loops and in-splits. It gives two different ways to construct the following wiring diagram using one 1-loop and one in-split:

Proposition 3.29. Suppose: • X ∈ BoxS , x− , x1 , x2 ∈ Xin are distinct, and x+ ∈ Xout such that v(x+ ) = v(x− ) ∈ S and v(x1 ) = v(x2 ) ∈ S. • X \ x ∈ BoxS is obtained from X by removing x± . • X = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 . • X \ x ∈ BoxS is obtained from X by removing x± . X \x  X\x  • λX ,x ∈ WD X and λX,x ∈ WD X are 1-loops. X   X \x  • σX,x1 ,x2 ∈ WD X and σX\x,x1 ,x2 ∈ WD X\x are in-splits. Then         X \x  λX ,x ◦ σX,x1 ,x2 = σX\x,x1,x2 ◦ λX,x ∈ WD X .

(3.18)

The next relation is the commutativity property between 1-loops and out-splits. It gives two different ways to construct the following wiring diagram using one 1-loop and one out-split:

54

3 Generators and Relations

Proposition 3.30. Suppose: • • • • • • •

X ∈ BoxS , and (x+ , x− ) ∈ Xout × Xin such that v(x+ ) = v(x− ) ∈ S. x1 = x2 ∈ Xout \ {x+ } such that v(x1 ) = v(x2 ) ∈ S. X = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 . X \ x ∈ BoxS is obtained from X by removing x± . X \ x ∈ BoxS is obtained from X by removing x± . X \x  X\x  λX ,x ∈ WD X  and λX,x ∈ WD X are 1-loops. X\x X σ X\x,x1 ,x2 ∈ WD X \x and σ X,x1 ,x2 ∈ WD X are out-splits.

Then 

       X\x σ X\x,x1,x2 ◦ λX ,x = λX,x ◦ σ X,x1 ,x2 ∈ WD X .

(3.19)

The next relation is the commutativity property between 1-loops and 1-wasted wires. It gives two different ways to construct the following wiring diagram using one 1-loop and one 1-wasted wire:

Proposition 3.31. Suppose: • X ∈ BoxS , (x+ , x− ) ∈ Xout × Xin such that v(x+ ) = v(x− ) ∈ S, and x0 ∈ Xin \ {x− }. • X = X \ {x0 } ∈ BoxS is obtained from X by removing x0 . • X \ x ∈ BoxS is obtained from X by removing x± . • X \ x ∈ BoxS is obtained from X by removing x± . X \x  X\x  λX,x ∈ WD X  are 1-loops. • λX ,x ∈ WD X and X\x  X • ωX\x,x0 ∈ WD X \x and ωX,x0 ∈ WD X are 1-wasted wires. Then 

       X\x  ωX\x,x0 ◦ λX ,x = λX,x ◦ ωX,x0 ∈ WD X .

(3.20)

The next relation involves 1-loops, in-splits, and out-splits. It says that the following two wiring diagrams are equal:

3.3 Elementary Relations

55

The wiring diagram on the left, in which the gray box is called X below, is created by substituting an in-split into a 1-loop. The wiring diagram on the right is created by substituting an out-split into a 1-loop, which is then substituted into another 1loop. The inner gray box is called Y , and the outer gray box is called Y \ x(1) below. In both wiring diagrams, the outermost box is called X∗ . Proposition 3.32. Suppose: • Y ∈ BoxS , and x 1 = x 2 ∈ Y out such that v(x 1 ) = v(x 2 ) ∈ S. • X = Y/(x 1 = x 2 ) ∈ BoxS is obtained from Y by identifying x 1 and x 2 , called x 12 ∈ Xout . • x1 = x2 ∈ Xin = Y in such that v(x 12 ) = v(x1 ) = v(x2 ) ∈ S. • X = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 , called x12 in X . X   • σX,x1 ,x2 ∈ WD X is an in-split. • X∗ = X \ {x12∗ , x1 , x2 } ∈ BoxS is obtained from X by removing x 12 , x1 , and x2 . X • λX ,x ∈ WD X is the 1-loop in which x 12 is the supply wire of x12 . Y  1 2 an out-split. • σ Y,x ,x ∈ WD X is Y \x(1) • λY,x(1) ∈ WD Y is a 1-loop, where Y \ x(1) ∈ BoxS is obtained from Y by removing {x1 , x 1 }. ∗  X • λY \x(1),x(2) ∈ WD Y \x(1) is a 1-loop, in which x 2 is the supply wire of x2 . Then 

         X∗  1 2 λX ,x ◦ σX,x1 ,x2 = λY \x(1),x(2) ◦ λY,x(1) ◦ σ Y,x ,x ∈ WD X .

(3.21)

The next relation says that the colored unit of a box can be rewritten as the substitution of an out-split into a 1-wasted wire and then into a 1-loop. This is depicted in the picture

in which the outer gray box is called Z and the inner gray box is called Y below. Proposition 3.33. Suppose: • • • •

Z ∈ BoxS , and (x1 , x 1 ) ∈ Z in × Z out such that v(x1 ) = v(x 1 ) ∈ S. Y = Z \ {x1 } ∈ BoxS is obtained from Z by removing x1 ∈ Z in . x 1 = x 2 ∈ Y out = Z out such that v(x 1 ) = v(x 2 ) ∈ S. X = Z \ {x1 , x 1 } ∈ BoxS is obtained from Z by removing {x1 , x 1 }.

56

3 Generators and Relations 1

2

Y 

• σ Y,x ,x ∈ WD X is an out-split in which both x 1 , x 2 ∈ Y out have supply wire x 2 ∈ Xout .   Z • ωZ,x1 ∈ WD Y is a 1-wasted wire. X • λZ,x ∈ WD Z is a 1-loop in which x 1 ∈ Z out is the supply wire of x1 ∈ Z in . Then 

     X 1 2 λZ,x ◦ ωZ,x1 ◦ σ Y,x ,x = 1X ∈ WD X .

(3.22)

The following five relations concern in-splits. The next one is the associativity property of in-splits. It gives two different ways to construct the following wiring diagram using two in-splits:

Proposition 3.34. Suppose: • X ∈ BoxS , and x1 , x2 , x3 ∈ Xin are distinct elements such that v(x1 ) = v(x2 ) = v(x3 ) ∈ S. • X12 = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 , called in . x12 ∈ X12 • X23 = X/(x2 = x3 ) ∈ BoxS is obtained from X by identifying x2 and x3 , called in . x23 ∈ X23 • Y = X/(x1 = x2 = x3 ) ∈ BoxS is obtained from X by identifying x1 , x2 , and x3 . Y  X  • σX12 ,x12 ,x3 ∈ WDX12  and σX,x1 ,x2 ∈ WD X12  are in-splits. Y X • σX23 ,x1 ,x23 ∈ WD X23 and σX,x2 ,x3 ∈ WD X23 are in-splits. Then 

       Y  σX12 ,x12 ,x3 ◦ σX,x1 ,x2 = σX23 ,x1 ,x23 ◦ σX,x2 ,x3 ∈ WD X .

(3.23)

The next relation is the commutativity property of in-splits. It gives two different ways to construct the following wiring diagram using two in-splits:

3.3 Elementary Relations

57

Proposition 3.35. Suppose: • X ∈ BoxS , and x1 , x2 , x3 , x4 ∈ Xin are distinct elements such that v(x1 ) = v(x2 ) and v(x3 ) = v(x4 ) ∈ S. • X12 = X/(x1 = x2 ) ∈ BoxS is obtained from X by identifying x1 and x2 , called in . x12 ∈ X12 • X34 = X/(x3 = x4 ) ∈ BoxS is obtained from X by identifying x3 and x4 , called in . x34 ∈ X34 • Y = X/(x1 = x2 ; x3 = x4 ) ∈ BoxS is obtained from X by (i) identifying x1 and x2 and (ii) identifying x and x4 . Y  3 X  • σX12 ,x3 ,x4 ∈ WDX12  and σX,x1 ,x2 ∈ WD X12  are in-splits. Y X • σX34 ,x1 ,x2 ∈ WD X34 and σX,x3 ,x4 ∈ WD X34 are in-splits. Then 

       Y  σX12 ,x3 ,x4 ◦ σX,x1 ,x2 = σX34 ,x1 ,x2 ◦ σX,x3 ,x4 ∈ WD X .

(3.24)

The next relation is the commutativity property between an in-split and an outsplit. It gives two different ways to construct the following wiring diagram using one in-split and one out-split:

Proposition 3.36. Suppose: Z ∈ BoxS , and z1 = z2 ∈ Z out such that v(z1 ) = v(z2 ) ∈ S. X = Z/(z1 = z2 ) ∈ BoxS is obtained from Z by identifying z1 and z2 . z1 = z2 ∈ Z in such that v(z1 ) = v(z2 ) ∈ S. Y = Z/(z1 = z2 ) ∈ BoxS is obtained from Z by identifying z1 and z2 . W = Z/(z1 = z2 ; z1 = z2 ) ∈ BoxS is obtained from Z by (i) identifying z1 and z2 and (ii) identifying z1 and z2 . Y  W  1 2 • σ Y,z ,z ∈ WD W is an out-split, and σX,z1 ,z2 ∈ WD X is an in-split. Y  Z  1 2 • σZ,z1 ,z2 ∈ WD Z is an in-split, and σ Z,z ,z ∈ WD X is an out-split.

• • • • •

Then         Y  1 2 1 2 σ Y,z ,z ◦ σX,z1 ,z2 = σZ,z1 ,z2 ◦ σ Z,z ,z ∈ WD X .

(3.25)

The next relation is the commutativity property between an in-split and a 1wasted wire. It gives two different ways to construct the following wiring diagram

58

3 Generators and Relations

using one in-split and one 1-wasted wire:

Proposition 3.37. Suppose: • • • • • •

Z ∈ BoxS , and z, z1 , z2 ∈ Z in are distinct elements such that v(z1 ) = v(z2 ) ∈ S. Y = Z/(z1 = z2 ) ∈ BoxS is obtained from Z by identifying z1 and z2 . X = Z \ {z} ∈ BoxS is obtained from Z by removing z ∈ Z in . W = X/(z1 =z2) ∈ BoxS is obtained from X by identifying z1 and z2 . W Y σX,z1 ,z2 ∈ WD and σ ∈ WD are in-splits. Z,z ,z X Z 1 2 Y  Z  ωY,z ∈ WD W and ωZ,z ∈ WD X are 1-wasted wires.

Then 

       Y  ωY,z ◦ σX,z1 ,z2 = σZ,z1 ,z2 ◦ ωZ,z ∈ WD X .

(3.26)

The next relation says that the colored unit of a box X can be rewritten as the substitution of a 1-wasted wire into an in-split. This is depicted in the picture

in which the intermediate gray box is called Y below. Proposition 3.38. Suppose: • • • •

Y ∈ BoxS , and x, y ∈ Y in are distinct elements such that v(x) = v(y) ∈ S. X = Y/(x = y) ∈ BoxS is obtained from Y by identifying x and y. Y  ωY,y ∈ WD X is a 1-wasted wire. X σY,x,y ∈ WD Y is an in-split.

Then     X  σY,x,y ◦ ωY,y = 1X ∈ WD X .

(3.27)

The following three relations concern out-splits. The next one is the associativity property of out-splits. It gives two different ways to construct the following wiring

3.3 Elementary Relations

59

diagram using two out-splits:

Proposition 3.39. Suppose: • Y ∈ BoxS , and y 1 , y 2 , y 3 ∈ Y out are distinct elements such that v(y 1 ) = v(y 2 ) = v(y 3 ) ∈ S. • Y 12 = Y/(y 1 = y 2 ) ∈ BoxS is obtained from Y by identifying y 1 and y 2 , called y 12 in Y 12 . • Y 23 = Y/(y 2 = y 3 ) ∈ BoxS is obtained from Y by identifying y 2 and y 3 , called y 23 in Y 23 . • X = Y/(y 1 = y 2 = y 3 ) ∈ BoxS is obtained from Y by identifying y 1 , y 2 , and y3. Y  Y 12  1 2 12 12 3 • σ Y,y ,y ∈ WD Y 12 and σ Y ,y ,y ∈ WD X are out-splits. Y  Y 23  2 3 23 1 23 • σ Y,y ,y ∈ WD Y 23 and σ Y ,y ,y ∈ WD X are out-splits. Then    12 12 3     23 1 23  Y  1 2 2 3 σ Y,y ,y ◦ σ Y ,y ,y = σ Y,y ,y ◦ σ Y ,y ,y ∈ WD X .

(3.28)

The next relation is the commutativity property of out-splits. It gives two different ways to construct the following wiring diagram using two out-splits:

Proposition 3.40. Suppose: • Y ∈ BoxS , and y 1 , y 2 , y 3 , y 4 ∈ Y out are distinct elements such that v(y 1 ) = v(y 2 ) and v(y 3 ) = v(y 4 ) ∈ S. • Y 12 = Y/(y 1 = y 2 ) ∈ BoxS is obtained from Y by identifying y 1 and y 2 . • Y 34 = Y/(y 3 = y 4 ) ∈ BoxS is obtained from Y by identifying y 3 and y 4 . • X = Y/(y 1 = y 2 ; y 3 = y 4 ) ∈ BoxS is obtained from Y by (i) identifying y 1 and y 2 and (ii) identifying y 3 and y 4 . Y  Y 12  1 2 12 3 4 • σ Y,y ,y ∈ WD Y 12 and σ Y ,y ,y ∈ WD X are out-splits.   Y 34  3 4 34 1 2 Y • σ Y,y ,y ∈ WD Y 34 and σ Y ,y ,y ∈ WD X are out-splits.

60

3 Generators and Relations

Then   12 3 4     34 1 2   Y  1 2 3 4 σ Y,y ,y ◦ σ Y ,y ,y = σ Y,y ,y ◦ σ Y ,y ,y ∈ WD X .

(3.29)

The next relation is the commutativity property between an out-split and a 1wasted wire. It gives two different ways to construct the following wiring diagram using one out-split and one 1-wasted wire:

Proposition 3.41. Suppose: • • • • • •

Y ∈ BoxS , y ∈ Y in , and y 1 , y 2 ∈ Y out such that v(y 1 ) = v(y 2 ) ∈ S. W = Y/(y 1 = y 2 ) ∈ BoxS is obtained from Y by identifying y 1 and y 2 . Z = Y \ {y} ∈ BoxS is obtained from Y by removing y ∈ Y in . X = Z/(y 1 = y 2 ) ∈ BoxS is obtained from Z by identifying y 1 and y 2 . Z  Y  1 2 1 2 σ Z,y ,y ∈ WD and σ Y,y ,y ∈ WD W are out-splits. Y  X W ωY,y ∈ WD Z and ωW,y ∈ WD X are 1-wasted wires.

Then         Y  1 2 1 2 ωY,y ◦ σ Z,y ,y = σ Y,y ,y ◦ ωW,y ∈ WD X .

(3.30)

The final relation is the commutativity property of 1-wasted wires. It gives two different ways to construct the following wiring diagram using two 1-wasted wires:

Proposition 3.42. Suppose: • • • • • •

Y ∈ BoxS , and y1 , y2 ∈ Y in are distinct elements. Y1 = Y \ {y1 } ∈ BoxS is obtained from Y by removing y1 . Y2 = Y \ {y2 } ∈ BoxS is obtained from Y by removing y2 . X = Y \ {y1, y2 } ∈ BoxS is obtained from Y by removing y1 and y2 . Y  Y ωY,y1 ∈ WD Y1 and ωY1 ,y2 ∈ WD X1 are 1-wasted wires. Y  Y  ωY,y2 ∈ WD Y2 and ωY2 ,y1 ∈ WD X2 are 1-wasted wires.

Then 

       Y  ωY,y1 ◦ ωY1 ,y2 = ωY,y2 ◦ ωY2 ,y1 ∈ WD X .

(3.31)

3.4 Summary of this Chapter

61

Definition 3.43. The 28 relations (3.4)–(3.31) are called elementary relations.

3.4 Summary of this Chapter 1. There are eight generating wiring diagrams in WD. 2. Each internal wasted wire can be generated using a 1-wasted wire and a 1-loop. 3. There are 28 elementary relations in WD.

Chapter 4

Decomposition of Wiring Diagrams

As part of the finite presentation theorem for the operad WD of wiring diagrams (Theorem 5.22), in Theorem 5.11 we will observe that each wiring diagram has a highly structured decomposition into generating wiring diagrams (Definition 3.9), called a stratified presentation. Stratified presentations are also needed to establish the second part of the finite presentation theorem for WD regarding relations. The purpose of this chapter is to provide all the steps needed to establish the existence of a stratified presentation for each wiring diagram. We remind the reader of Notation 3.14 for (iterated) operadic compositions. In Sect. 4.1 we show that each wiring diagram ψ has a specific operadic decomposition (4.6) ψ = α ◦ ϕ. An explanation of this decomposition is given just before Definition 4.5. The idea of this decomposition is that we are breaking the complexity of a general wiring diagram into two simpler parts. On the one hand, the inner wiring diagram ϕ contains all the input boxes and the delay nodes of ψ, but its supplier assignment is as simple as possible, namely the identity map. See Lemmas 4.8 and 4.10. On the other hand, the outer wiring diagram α has only one input box and no delay nodes, but its supplier assignment is equal to that of ψ. In Sect. 4.2 we observe that the outer wiring diagram α in the previous decomposition of ψ can be decomposed as (4.12) α = π1 ◦ π2 . Example 4.13 has a concrete wiring diagram that illustrates this decomposition. The idea of this decomposition is that in a wiring diagram there are usually wires that go backward (i.e., “point to the left”), as in (2.22), in a 1-loop (Definition 3.5), and in the pictures just before Propositions 3.24 and 3.28. This decomposition breaks © Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_4

63

64

4 Decomposition of Wiring Diagrams

the complexity of the wiring diagram α into two simpler parts. On the one hand, the outer wiring diagram π1 contains all the backward-going wires in α but no wasted wires or split wires (Lemma 4.17). On the other hand, the inner wiring diagram π2 contains no backward-going wires, but it has all the wasted wires and split wires in α. In Sect. 4.3 we observe that the wiring diagram π2 in the previous decomposition of α can be decomposed further as (4.17) π2 = β1 ◦ β2 ◦ β3 . Example 4.19 has a concrete wiring diagram that illustrates this decomposition. In this decomposition: • The outermost wiring diagram β1 is an iterated operadic composition of 1-wasted wires (Lemma 4.23). • The middle wiring diagram β2 is an iterated operadic composition of in-splits (Lemma 4.26). • The innermost wiring diagram β3 is an iterated operadic composition of out-splits (Lemma 4.29). By convention an empty operadic composition means a colored unit. In summary, for a wiring diagram ψ, we will decompose it as ψ = π1 ◦ β1 ◦ β2 ◦ β3 ◦ ϕ.

4.1 Factoring Wiring Diagrams Assumption 4.1. Throughout this chapter, fix a class S. Suppose   Y  ψ = DNψ , vψ , sψ ∈ WD X

(4.1)

is a wiring diagram with: • output box Y ∈ BoxS and input boxes X = (X1 , . . . , XN ) for some N ≥ 0; • r delay nodes DNψ = {d1 , . . . , dr } for some r ≥ 0; / S, where Xin = • value assignment vψ : Y in  Y out  Xin  Xout  DNψ

N

N in out out = i=1 X i ; i=1 Xi and X / Spψ . • supplier assignment sψ : Dmψ Since N = 0 and r = 0 are both allowed, ψ is a general wiring diagram. Furthermore: 1. To simplify the notation, we will write vψ (di ) ∈ S simply as di , so each δdi ∈ di  WD is a 1-delay node (Definition 3.2). 2. X = N i=1 Xi ∈ BoxS is the coproduct of the Xi ’s.

4.1 Factoring Wiring Diagrams

65

3. Define X ∈ BoxS as Xin = Xin  DNψ

and

Xout = Xout  DNψ .

(4.2)

Motivation 4.2. The first observation concerns the marginal case where ψ has no input boxes and no delay nodes. So it looks like this

with finitely many, possibly zero, external wasted wires. In any case, it can be written in terms of the empty wiring diagram and finitely many 1-wasted wires. Y 

has no input boxes and Lemma 4.3. Suppose N = r = 0 in ψ; i.e., ψ ∈ WD no delay nodes. Then one of the following two statements is true. ∅

1. ψ =  ∈ WD , the empty wiring diagram (Definition 3.1). 2. There exist 1-wasted wires (Definition 3.8) ω1 , . . . , ωm , where m = |Y in | > 0, such that ψ = ω1 ◦ · · · ◦ ωm ◦ .

(4.3)

Proof. Since Xin = Xout = DNψ = ∅, the supplier assignment of ψ is a function

The non-instantaneity requirement (2.20) then implies Y out = ∅. If m = |Y in | = 0, then Y is the empty box and ψ = , the empty wiring diagram, by definition. If m > 0, then every global input y ∈ Y in = {y1 , . . . , ym } is an external wasted / Y in is the trivial map. For wire, and the supplier assignment s : Y out = ∅ each 1 ≤ j ≤ m, define the box ⎧ ⎪ ⎪ ⎨Y Yj = Y \ {y1 , . . . , yj −1 } ⎪ ⎪ ⎩∅ Each ωYj ,yj ∈ WD composition



Yj  Yj+1

if j = 1; if 2 ≤ j ≤ m; if j = m + 1.

is a 1-wasted wire. Using the notation (3.3), the iterated

ωY1 ,y1 ◦ · · · ◦ ωYm ,ym ◦  ∈ WD

Y 

66

4 Decomposition of Wiring Diagrams

is then a wiring diagram with output box Y1 = Y , no input boxes and no delay / Y in the trivial map. This is the nodes, and supplier assignment ∅ = Y out same as ψ.   Next, for wiring diagrams ψ not necessarily covered by Lemma 4.3, we define two relatively simple wiring diagrams that will be shown to provide a decomposition for ψ. Each of these two simpler wiring diagrams will then be analyzed further. Motivation 4.4. This decomposition for ψ is depicted in the following picture:

Here the intermediate gray box is X (4.2). In this decomposition, the inside wiring diagram ϕ has all the input boxes and the delay nodes of ψ, but its supplier assignment is the identity function. The outside wiring diagram α has a single input box X and no delay nodes, but it has the same supplier assignment as ψ. Definition 4.5. Suppose ψ is as in Assumption 4.1. Define the wiring diagram   X   ϕ = DNϕ , vϕ , sϕ ∈ WD X

(4.4)

with: • output box X (4.2) and input boxes X = (X1 , . . . , XN ); • delay nodes DNϕ = DNψ = {d1 , . . . , dr }; • supplier assignment

the identity function that sends Xout to (Xout  DNψ ) and (Xin  DNψ ) to Xin .

4.1 Factoring Wiring Diagrams

67

Definition 4.6. Suppose ψ is as in Assumption 4.1. Define the wiring diagram   Y  α = DNα , vα , sα ∈ WD X

(4.5)

with: • one input box X (4.2) and output box Y ; • no delay nodes; • supplier assignment

equal to sψ . Lemma 4.7. Given a wiring diagram ψ (4.1), there is a decomposition ψ = α ◦ ϕ ∈ WD in which α ∈ WD

Y  X

is as in (4.5) and ϕ ∈ WD

Y 

(4.6)

X

X  X

is as in (4.4). Y 

Proof. By the definition of ◦1 (Definition 2.34), α ◦ ϕ = α ◦1 ϕ belongs to WD X and has DNϕ = DNψ as its set of delay nodes. It remains to check that its supplier assignment is equal to that of ψ. This follows from a direct inspection because sϕ is the identity function, while sα = sψ .   To obtain the desired stratified presentation of ψ, we now begin to analyze the wiring diagram ϕ. Lemma 4.8. Consider the wiring diagram ϕ (4.4). 1. If N = r = 0, then ϕ = , the empty wiring diagram (Definition 3.1). 2. If (N, r) = (1, 0), then ϕ = 1X1 , the colored unit of X1 (Definition 2.32). 3. If (N, r) = (0, 1), then ϕ = δd1 , a 1-delay node (Definition 3.2). Proof. All three cases are checked by direct inspection.

 

Motivation 4.9. Next we observe that, for higher values of N + r, the wiring diagram ϕ is generated by 2-cells (Definition 3.4) and 1-delay nodes via iterated operadic compositions, as depicted in the following picture.

68

4 Decomposition of Wiring Diagrams

The operadic composition γ (2.2) is used in the following observation. Lemma 4.10. Suppose N + r ≥ 2 in the wiring diagram ϕ ∈ WD admits a decomposition

X   X

(4.4). Then it

    r  N ϕ = γ θ ; 1Xi i=1 , δdj j =1 .

(4.7)

Here θ=

⎧ ⎨θ 1 ⎩θ 1 ◦ 2



  · · · ◦2 θN+r−2 ◦2 θN+r−1

with each θk a 2-cell, and each δdj ∈ WD

dj 

if N + r = 2, if N + r > 2

(4.8)

is a 1-delay node as in Assumption 4.1.

Proof. Recall that X = (X1 , . . . , XN ) and DNϕ = DNψ = {d1 , . . . , dr }. For N + 1 ≤ j ≤ N + r define the box Xj = dj ∈ BoxS as Xjin = {dj } = Xjout . For 1 ≤ i ≤ N + r define the box X≥i =

N+r 

Xp ∈ BoxS .

p=i

Note that X≥1 = X (4.2). Next, for 1 ≤ k ≤ N + r − 1, define the 2-cell θk = θXk ,X≥k+1 ∈ WD



X ≥k  Xk , X ≥k+1

.

4.2 Unary Wiring Diagrams

69

Then we have a wiring diagram θ ∈ WD



 X X1 ,...,XN+r X 

d 

in which θ ∗ is defined as in (4.8). Since 1Xi ∈ WD Xii and δdj ∈ WD j , the operadic composition on the right-hand side of (4.7) is defined and belongs to X   WD X . Since the two sides of (4.7) both have delay nodes {d1 , . . . , dr }, it remains to check that the supplier assignment of the right-hand side is equal to sϕ = Id. This follows from a direct inspection because (i) colored units (Definition 2.32), 1-delay nodes (Definition 3.2), and 2-cells (Definition 3.4) all have identity supplier assignments and because (ii) γ (2.16) is an iteration of various ◦i (Definition 2.34).  

4.2 Unary Wiring Diagrams In this section, we analyze wiring diagrams with exactly one input box and no delay nodes, such as α (4.5). We will show that such a wiring diagram can be generated by the generating wiring diagrams (Definition 3.9) of name changes (Definition 3.3), 1-loops (Definition 3.5), 1-wasted wires (Definition 3.8), in-splits (Definition 3.6), and out-splits (Definition 3.7), in this order. We remind the reader of Notation 3.14 for (iterated) ◦1 . We will need a few definitions and notations. Definition 4.11. Suppose π ∈ WD and no delay nodes.

Y  X

is a wiring diagram with one input box X

1. A loop element in π is an element x ∈ Xout such that there exists an x  ∈ Xin with x as its supply wire. The set of loop elements in π is denoted by π lp . 2. An element x  ∈ Xin is said to be internally supplied if sπ (x  ) ∈ Xout . The set sp of such elements in π is denoted by π+ . 3. An element x  ∈ Xin is said to be externally supplied if sπ (x  ) ∈ Y in . The set of sp such elements in π is denoted by π− . Recall from Definition 2.25 the concepts of external wasted wires π−w and of internal wasted wires π+w of a wiring diagram π. Lemma 4.12. Suppose π ∈ WD no delay nodes. Then: sp

sp

1. π+  π− = Xin . out 2. π+w π lp ⊆X . sp 3. sπ π+ = π lp .

Y  X

is a wiring diagram with one input box X and

70

4 Decomposition of Wiring Diagrams

  sp 4. sπ π−  π−w = Y in .   5. sπ Y out ⊆ Xout \ π+w . Proof. All the statements are immediate from the definitions. Example 4.13. Consider the wiring diagram π ∈ WD

Y  X

 

as depicted in the picture

with • Xin = {x1 , x2 , x3 , x4 }, Xout = {x 1 , x 2 , x 3 }, Y in = {y1 , y2 }, and Y out = {y 1 , y 2 }; sp sp • π lp = {x 1 }, π+ = {x1, x2 }, π− = {x3 , x4 }, π+w = {x 3 }, and π−w = {y1 }. Note that we may operadically decompose π as follows.

(4.9) The point of this decomposition is that the inner wiring diagram π2 is generated by: • two 1-wasted wires, one for the external wasted wire y1 and the other for the internal wasted wire x 3 ; • two in-splits, one for {x1 , x2 } and the other for {x3 , x4 }; • one out-split for x 1 , which is the supply wire of y 1 , x1 , and x2 . At the same time, the outer wiring diagram π1 is generated by two 1-loops, one for the loop element x 1 and the other for the internal wasted wire x 3 . With this example as a guide, next we will factor a general wiring diagram with one input box and no delay nodes into two wiring diagrams. The outer wiring diagram will be generated by name changes and 1-loops. The inner wiring diagram will be generated by 1-wasted wires, in-splits, and out-splits. The intermediate gray box in (4.9) will be called Z below.

4.2 Unary Wiring Diagrams

71

Convention 4.14. Using the five elementary relations (3.5)–(3.9), name changes can always be rewritten on the outside (i.e., left side) of an iterated operadic composition in WD. Moreover, using the elementary relation (3.4), an iteration of name changes can be composed down into just one name change. To simplify the presentation, in what follows these elementary relations regarding name changes are automatically applied wherever necessary. With this in mind, we will usually not mention name changes. For a wiring diagram with one input box and no delay nodes, we will decompose it using the wiring diagrams in the next definition. Definition 4.15. Suppose π ∈ WD and no delay nodes.

Y  X

is a wiring diagram with one input box X

1. Define the box Z ∈ BoxS as Z in = Y in  π+w  π lp ; Z out = Y out  π+w  π lp . 2. Define the wiring diagram π1 ∈ WD

Y  Z

with:

• one input box Z, output box Y , and no delay nodes; • supplier assignment

(4.10) the identity function. 3. Define the wiring diagram π2 ∈ WD

Z  X

with:

• one input box X, output Z, and no delay nodes; • supplier assignment

(4.11) whose restriction to: / Xout ; – Y out is sπ : Y out – π+w  π lp is the subset inclusion into Xout ;

72

4 Decomposition of Wiring Diagrams sp

sp

/ π lp ;

sp

sp

/ Y in .

– π+ is sπ : π+ – π− is sπ : π−

This is well-defined by the non-instantaneity requirement (2.20) for π and Lemma 4.12. An example of the following decomposition is the picture (4.9) above. Y 

Lemma 4.16. Suppose π ∈ WD X is a wiring diagram with one input box X and no delay nodes. Then it admits a decomposition π = π1 ◦ π2 in which π1 ∈ WD

Y  Z

and π2 ∈ WD

Z  X

(4.12)

are as in Definition 4.15. Y 

Proof. Both sides of (4.12) belong to WD X and have no delay nodes. So it remains to check that the supplier assignment s of π1 ◦ π2 is equal to sπ . Note that   sp sp Dmπ1 ◦π2 = Y out  Xin = Y out  π+  π− . By the definitions of ◦ = ◦1 (Definition 2.34), sπ1 (4.10), and sπ2 (4.11): • on Y out the supplier assignment s is sπ2 sπ1 = sπ Id = sπ . sp sp • on π+  π− the supplier assignment s is sπ2 sπ1 = Idsπ = sπ . So the supplier assignment of π1 ◦ π2 is equal to sπ .

 

To obtain the desired stratified presentation of π, next we observe that π1 in Definition 4.15 is either a colored unit (2.24) or an iterated operadic composition of 1-loops (Definition 3.5). An example of π1 is the outer wiring diagram in the example (4.9). Lemma 4.17. Suppose: • Y, Z ∈ Box S such that Z in = Y in  T and Z out = Y out  T for some T ∈ FinS . Y • ζ ∈ WD Z is a wiring diagram with no delay nodes and with supplier assignment

the identity function. Then the following statements hold. 1. ζ = 1Y if T = ∅.

4.2 Unary Wiring Diagrams

73

2. If p = |T | > 0, then there exist 1-loops λ1 , . . . , λp such that ζ = λ1 ◦ · · · ◦ λp .

(4.13)

Y 

Proof. If T = ∅, then ζ ∈ WD Y has no delay nodes and has supplier assignment sζ = Id. So ζ is the Y -colored unit. Next suppose T = {t1 , . . . , tp } with p > 0. For the definitions below, it is convenient to keep in mind the following picture of ζ :

For 0 ≤ j ≤ p define the box Yj ∈ BoxS as  Yj =

Y if j = 0; Y  {t1 , . . . , tj } if 1 ≤ j ≤ p.

Here Y  {t1 , . . . , tj } means a copy of ti for 1 ≤ i ≤ j is added to each of Y in and Y out . In particular, we have Yp = Z. For 1 ≤ j ≤ p define the 1-loop λj = λYj ,tj ∈ WD

Yj−1  Yj

in which tj ∈ Yjin has supply wire tj ∈ Yjout . The iterated operadic composition λ1 ◦ · · · ◦ λp ∈ WD

 Y0  Yp

= WD

Y  Z

has no delay nodes. To see that it is equal to ζ , it remains to check that its supplier assignment is equal to sζ = Id. This holds because each 1-loop λj has identity supplier assignment.   Y 

Observe that Lemma 4.17 applies to π1 ∈ WD Z in Definition 4.15 with T = π+w  π lp . So π1 is either the Y -colored unit or an iterated operadic composition of 1-loops.

74

4 Decomposition of Wiring Diagrams

4.3 Unary Wiring Diagrams with No Loop Elements Z 

In order to show that the wiring diagram π2 ∈ WD X in Definition 4.15 is generated by 1-wasted wires, in-splits, and out-splits, first we identify its external wasted wires, internal wasted wires, and loop elements. Lemma 4.18. Consider the wiring diagram π2 ∈ WD 1. 2. 3. 4. 5.

w = πw The set of external wasted wires in π2 is π2− + w The set of internal wasted wires in π2 is π2+ = ∅. lp The set of loop elements in π2 is π2 = ∅. out out sπ2 (Z ) = X . Z in = π+w  π−w  sπ2 (Xin ).

Z  X

in Definition 4.15.

 π−w .

Proof. 1. By definition an external wasted wire in π2 is an element in Z in that is not in the image of sπ2 (4.11). By the definition of sπ2 , this is the subset sp

π+w  [Y in \ sπ (π− )] ⊆ Z in . It follows from the non-instantaneity requirement (2.20) for π that sp

Y in \ sπ (π− ) = π−w . 2. By definition an internal wasted wire in π2 is an element in Xout that is not in the image of sπ2 . An element of Xout is either an internal wasted wire in π, or else it sp is the sπ -image of an element in π+  Y out . Since   sp Xout = π+w  sπ π+  Y out   = π+w  π lp ∪ sπ (Y out ) , an inspection of the definition of sπ2 (4.11) reveals that all of Xout is in the image of sπ2 . So π2 has no internal wasted wires. 3. By definition a loop element in π2 is an element in Xout that is the supply wire, sp sp under sπ2 , of some element in Xin . Since Xin = π+  π− , the definition of sπ2 (4.11) yields sp

sp

sp

sp

sπ2 (π+  π− ) = sπ (π+ )  sπ (π− ) ⊆ π lp  Y in ⊆ Z in = Spπ2 \ Xout . So π2 has no loop elements. sp 4. By (2) π2 has no internal wasted wires, so Xout = sπ2 (Z out  π2+ ). But by (3) sp π2 has no loop elements, so π2+ = ∅ and Xout = sπ2 (Z out ).

4.3 Unary Wiring Diagrams with No Loop Elements

75

5. Since π2 has no loop elements by (3), sπ2 (Xin ) ⊆ Z in . An element in Z in that is not in sπ2 (Xin ) is precisely an external wasted wire in π2 . By (1) the set of external wasted wires in π2 is π+w  π−w .   Continuing our analysis of wiring diagrams with one input box and no delay nodes, our next goal is to construct a decomposition for π2 (Definition 4.15) involving 1-wasted wires, in-splits, and out-splits. Example 4.19. Consider the inner wiring diagram π2 ∈ WD ple (4.9), which is depicted in the following picture.

Z  X

in the exam-

For this wiring diagram, the desired decomposition is depicted in the picture:

The inner gray box will be called V , and the outer gray box will be called W below. Note that: Z 

is generated by two 1-wasted wires. • The outermost wiring diagram β1 ∈ WD W  W • The middle wiring diagram β2 ∈ WD V  is generated by two in-splits. V • The innermost wiring diagram β3 ∈ WD X is an out-split. For a general wiring diagram with one input box, no delay nodes, no loop elements, and no internal wasted wires, such a decomposition uses the following definitions. Definition 4.20. Suppose X, Z ∈ BoxS and β ∈ WD no delay nodes and no loop elements.

Z  X

is a wiring diagram with

w ∈ Box is obtained from Z ∈ Box by removing 1. Suppose the box W = Z \ β− S S w and W out = Z out . the external wasted wires of β, so W in = Z in \ β− Z 2. Define the wiring diagram β1 ∈ WD W as having:

• no delay nodes; • supplier assignment

76

4 Decomposition of Wiring Diagrams

(4.14) w ⊆ Z in . the identity function on Z out and the subset inclusion on Z in \ β− in and V out = Z out = W out . 3. Define the box V ∈ BoxS as V in = X W  4. Define the wiring diagram β2 ∈ WD V as having:

• no delay nodes; • supplier assignment

(4.15) the coproduct of the identity function on W out and the restriction of the / Z in \ β w . supplier assignment sβ : Xin − This is well-defined because β has no delay nodes and no loop elements. V 5. Define the wiring diagram β3 ∈ WD X as having: • no delay nodes; • supplier assignment

(4.16) the coproduct of the identity function on Xin and sβ : Z out

/ Xout .

This is well-defined because β has no delay nodes and because of the noninstantaneity requirement (2.20) for β. Lemma 4.21. In the context of Definition 4.20: / Z in \ β w , which is part of sβ , is surjective. 1. The map sβ : Xin − 2 2. If β has no internal wasted wires (such as π2 in Definition 4.15), then the map / Xout , which is part of sβ , is surjective. sβ : Z out 3 Proof. The first assertion is true because β has no delay nodes and because of the non-instantaneity requirement (2.20). The second assertion is true because β has no delay nodes and no loop elements.  

4.3 Unary Wiring Diagrams with No Loop Elements

77

Lemma 4.22. In the context of Definition 4.20, there is a decomposition β = β1 ◦ β2 ◦ β3 ∈ WD

Z  X

(4.17)

.

Proof. By construction the iterated operadic composition β1 ◦β2 ◦β3 also belongs to Z  WD X and has no delay nodes. So it remains to check that its supplier assignment s is equal to sβ . A direct inspection of (4.14)–(4.16) reveals that: • on Xin ⊆ Dmβ3 the supplier assignment s is given by Idsβ2 IdXin = sβ ; • on Z out ⊆ Dmβ1 the supplier assignment s is given by sβ3 IdZ out IdZ out = sβ . So the supplier assignment of β1 ◦ β2 ◦ β3 is equal to sβ .

 

Note that the decomposition in Lemma 4.22 applies to π2 because π2 has one input box, no delay nodes, and no loop elements (by Lemma 4.18). Next we show that in the decomposition (4.17): 1. β1 is either a colored unit (Definition 2.32) or an iterated operadic composition of 1-wasted wires (Definition 3.8). See Lemma 4.23. 2. β2 is either a colored unit or an iterated operadic composition of in-splits (Definition 3.6). See Lemma 4.26. 3. If β has no internal wasted wires, such as π2 by Lemma 4.18, then β3 is either a colored unit or an iterated operadic composition of out-splits (Definition 3.7). See Lemma 4.29. During the first reading, the reader may wish to skip the proofs of the following Lemmas and simply look at the pictures. The following observation deals with the first statement. Lemma 4.23. Consider the wiring diagram β1 ∈ WD

Z  W

in Definition 4.20.

w = ∅ (i.e., β has no external wasted wires), then β = 1 , the Z-colored 1. If β− 1 Z unit. w | > 0, then there exist 1-wasted wires ω , . . . , ω such that 2. If q = |β− 1 q

β1 = ω1 ◦ · · · ◦ ωq .

(4.18)

Proof. Recall that β1 has no delay nodes and has supplier assignment (4.14)

w . If β w = ∅, that is the identity function on Z out and the subset inclusion on Z in \β− − then sβ1 = Id and, therefore, β1 is the colored unit.

78

4 Decomposition of Wiring Diagrams

w = {w , . . . , w } ⊆ Z in with q > 0. Recall that W = Z \ β w . Next suppose β− 1 q − For 0 ≤ j ≤ q define the box

Zj =

 Z

if j = 0;

Z \ {w1 , . . . , wj }

if 1 ≤ j ≤ q.

So in particular Zq = W . The iterated operadic composition on the right-hand side of (4.18) is represented in the following picture.

Here the outermost box is Z, the outermost gray box is Z1 , and the innermost gray box is Zq−1 . For 1 ≤ j ≤ q define the 1-wasted wires (Definition 3.8) ωj = ωZj−1 ,wj ∈ WD

Zj−1  Zj

.

The iterated operadic composition ω1 ◦ · · · ◦ ωq ∈ WD

 Z0  Zq

= WD

Z W

has no delay nodes. So to prove (4.18), it remains to check that its supplier assignment s is equal to sβ1 . • On Z out ⊆ Dmω1 the supplier assignment s is the composition of q copies of the identity function, hence is the identity function. • On W in ⊆ Dmωq the supplier assignment s is the composition of the inclusions / Z in for 1 ≤ j ≤ q, which is the inclusion W in / Z in .   Zjin j −1 Motivation 4.24. To show that β2 is either a colored unit or an iterated composition of in-splits, we first need a lemma that says that the following wiring diagram is generated by in-splits.

4.3 Unary Wiring Diagrams with No Loop Elements

79

Lemma 4.25. Suppose: • X, Y ∈ BoxS such that Xout = Y out . • There exist y ∈ Y in and distinct elements x1 , . . . , xk ∈ Xin with k ≥ 1 such that   Xin = Y in \ {y}  {x1, . . . , xk } and v(y) = v(x i ) ∈ S for all i. Y • σ ∈ WD X is a wiring diagram with no delay nodes and with supplier assignment

given by sσ (z) =

 y z

if z = x1 , . . . , xk ;   if z ∈ Y out  Y in \ {y} .

Then: 1. σ is the Y -colored unit if k = 1; 2. σ is an iterated operadic composition of (k − 1) in-splits if k ≥ 2. Proof. Since σ has no delay nodes, if k = 1, then sσ = Id. So σ is a colored unit. Suppose k ≥ 2. We will prove that σ is an iterated operadic composition of (k − 1) in-splits by induction on k. If k = 2, then by definition σ is the in-split σX,x1 ,x2 (Definition 3.6). Suppose k ≥ 3. We will factor σ into two wiring diagrams as depicted in the picture

in which the intermediate gray box will be called W below. The outer wiring diagram σ1 will be an in-split, and the inner wiring diagram σ2 will be an iterated operadic composition of (k − 2) in-splits. To define such a decomposition, we will need the following definitions.

80

4 Decomposition of Wiring Diagrams

1. Suppose W ∈ BoxS such that W out = Y out = Xout and   W in = Y in \ {y}  {x  , xk } for some xk = x  such that v(x  ) = v(xk ) ∈ S. In particular, we have   Xin = W in \ {x  }  {x1 , . . . , xk−1 }. 2. Define the wiring diagram σ1 ∈ WD assignment

Y  W

(4.19)

with no delay nodes and with supplier

given by sσ1 (z) =

 y

if z = x  , xk ; otherwise.

z

3. Define the wiring diagram σ2 ∈ WD assignment

W  X

with no delay nodes and with supplier

given by sσ2 (z) = Y 

 x z

if z = x1 , . . . , xk−1 ; otherwise.

Then σ1 ◦ σ2 ∈ WD X is a wiring diagram with no delay nodes. To see that it is equal to σ , it suffices to check that the supplier assignment of σ1 ◦ σ2 is equal to sσ . This is true by a direct inspection of sσ1 and sσ2 . By definition σ1 is the in-split σW,x  ,xk . By (4.19) the induction hypothesis applies to σ2 , which says that it is an iterated operadic composition of (k − 2) in-splits.

4.3 Unary Wiring Diagrams with No Loop Elements

81

Combined with the previous paragraph, it follows that σ = σ1 ◦ σ2 is the iterated operadic composition of (k − 1) in-splits, finishing the induction.   Next we consider β2 .

W 

Lemma 4.26. The wiring diagram β2 ∈ WD V in Definition 4.20 is either a colored unit or an iterated operadic composition of in-splits. w , V in = X in , and V out = Z out = W out . The Proof. Recall that W in = Z in \ β− W  wiring diagram β2 ∈ WD V has no delay nodes and has supplier assignment (4.15)

the coproduct of the identity function on Z out and sβ : Xin

/ Z in \ β w . Write −

w = {z , . . . , z }, so each s −1 (z ) is non-empty by Lemma 4.21. W in = Z in \ β− 1 p i β in w in If p = 0, then Z \ β− = ∅ = X , and β2 is the W -colored unit. Suppose p > 0. We will write β2 as an iterated composition as in the following picture.

There are p − 1 gray boxes. The outermost gray box will be called W1 , and the innermost gray box will be called Wp−1 below. To define such a decomposition, we will need the following definitions. 1. For 0 ≤ j ≤ p define the box Wj ∈ BoxS with Wjout = W out and Wjin

⎡ ⎤ j  = ⎣ sβ−1 (zi )⎦  {zj +1 , . . . , zp } .

 i=1 ∅ if j =p

 ∅ if j =0

82

4 Decomposition of Wiring Diagrams

Note that W0in = W in by definition, while Wpin = Xin = V in by Lemma 4.21. So W0 = W and Wp = V . W  with no delay nodes 2. For 1 ≤ j ≤ p define the wiring diagram σj ∈ WD Wj−1 j and with supplier assignment

given by sσj (x) =

 zj x

if x ∈ sβ−1 (zj ); otherwise.

Since   Wjin = Wjin−1 \ {zj }  sβ−1 (zj ), by Lemma 4.25 σj is: • a colored unit if |sβ−1 (zj )| = 1;

  • an iterated operadic composition of |sβ−1 (zj )| − 1 in-splits if |sβ−1 (zj )| ≥ 2. Therefore, to show that β2 is either a colored unit or an iterated operadic composition of in-splits, it is enough to check that there is a decomposition β2 = σ1 ◦ · · · ◦ σp ∈ WD

W  V

.

Since the iterated operadic composition on the right has no delay nodes, it remains to check that its supplier assignment s is equal to sβ2 (4.15). On W out = Z out ⊆ Dmσ1 the supplier assignment s is the composition of p identity functions, hence the identity function. On V in = Xin =

p 

sβ−1 (zi ) ⊆ Dmσp

i=1

the supplier assignment s sends elements in each sβ−1 (zj ) to zj ∈ W in , so it is equal to sβ2 .  

4.3 Unary Wiring Diagrams with No Loop Elements

83

Motivation 4.27. Next, to show that β3 is either a colored unit or an iterated operadic composition of out-splits, we first need a lemma that says that the following wiring diagram is generated by out-splits.

The following observation is the out-split analogue of Lemma 4.25. Lemma 4.28. Suppose: • X, Y ∈ BoxS such that Xin = Y in . • There exist x ∈ Xout and distinct elements y1 , . . . , yk ∈ Y out with k ≥ 1 such that   Y out = Xout \ {x}  {y1 , . . . , yk } and v(x) = v(y i ) ∈ S for 1 ≤ i ≤ k. Y • σ ∈ WD X is a wiring diagram with no delay nodes and with supplier assignment

given by  sσ (z) =

x z

if z = y1 , . . . , yk ;   if z ∈ Xout \ {x}  Xin .

Then: 1. σ is the Y -colored unit if k = 1; 2. σ is an iterated operadic composition of (k − 1) out-splits if k ≥ 2. Proof. If k = 1, then sσ is the identity function, so σ is a colored unit. The assertion for k ≥ 2 is proved by induction. If k = 2, then σ is by definition the out-split σ Y,y1 ,y2 (Definition 3.7). Suppose k ≥ 3. We will factor σ into two wiring diagrams as depicted in the picture

84

4 Decomposition of Wiring Diagrams

in which the intermediate gray box will be called W below. The inner wiring diagram σ 2 will be an out-split, and the outer wiring diagram σ 1 will be an iterated operadic composition of (k − 2) out-splits. To define such a decomposition, we will need the following definitions. 1. Define the box W ∈ BoxS with W in = Xin = Y in and   W out = Xout \ {x}  {w, yk } for some w = yk such that v(w) = v(yk ) ∈ S. In particular, we have   Y out = W out \ {w}  {y1 , . . . , yk−1 }. 2. Define the wiring diagram σ 1 ∈ WD assignment

Y  W

(4.20)

with no delay nodes and with supplier

given by  sσ 1 (z) =

w

if z = y1 , . . . , yk−1 ;

z

otherwise.

3. Define the wiring diagram σ 2 ∈ WD assignment

W  X

with no delay nodes and with supplier

4.3 Unary Wiring Diagrams with No Loop Elements

85

given by sσ 2 (z) =

 x z

if z = w, yk ; otherwise.

Y 

Then σ 1 ◦ σ 2 ∈ WD X is a wiring diagram with no delay nodes. To see that it is equal to σ , it suffices to check that the supplier assignment of σ 1 ◦ σ 2 is equal to sσ . This is true by a direct inspection of sσ 1 and sσ 2 . By (4.20) the induction hypothesis applies to σ 1 , which says that it is an iterated operadic composition of (k − 2) out-splits. By definition σ 2 is the out-split σ W,w,yk . Combined with the previous paragraph, it follows that σ = σ 1 ◦ σ 2 is the iterated operadic composition of (k − 1) out-splits, finishing the induction.   Finally, we consider β3 . Lemma 4.29. In the context of Definition 4.20, suppose β has no internal wasted V wires (such as π2 (4.11) by Lemma 4.18). Then β3 ∈ WD X is either a colored unit or an iterated operadic composition of out-splits. Proof. Recall that the wiring diagram β3 ∈ WD supplier assignment (4.16)

V  X

has no delay nodes and has

/ Xout . Since β the coproduct of the identity function on Xin and sβ : Z out / Xout is has no internal wasted wires, by Lemma 4.21 the map sβ : Z out surjective.

Write Xout = {x1 , . . . , xr }, so Z out = ri=1 sβ−1 (xi ) with each sβ−1 (xi ) nonempty. If r = 0, then Xout = ∅ = Z out , and β3 is a colored unit. Suppose r > 0. We will decompose β3 as in the picture:

86

4 Decomposition of Wiring Diagrams

The outermost gray box will be called V1 , and the innermost gray box will be called Vr−1 below. To define such a decomposition, we first need some definitions. 1. For 0 ≤ j ≤ r define the box Vj ∈ BoxS with Vjin = V in = Xin and Vjout = {x1 , . . . , xj } 

 ∅ if j =0

r  i=j +1



sβ−1 (xi ) .



∅ if j =r



Note that V0out = Z out = V out , so V0 = V . Also, Vrout = Xout , so Vr = X. V  with no delay nodes 2. For 1 ≤ j ≤ r define the wiring diagram σ j ∈ WD Vj−1 j and with supplier assignment

given by  sσj (z) =

xj

if z ∈ sβ−1 (xj );

z

otherwise.

The iterated operadic composition σ 1 ◦ · · · ◦ σ r ∈ WD

V0  Vr

= WD

V  X

has no delay nodes. To see that it is equal to β3 , it remains to check that the former’s supplier assignment s is equal to sβ3 . • On Xin ⊆ Dmσ r the supplier assignment s is the composition of r identity functions, hence the identity function. • On V out = Z out ⊆ Dmσ 1 the supplier assignment s sends elements in each sβ−1 (xi ) to xi . So s is equal to sβ3 . By Lemma 4.28 each σ j for 1 ≤ j ≤ r is either a colored unit or an iterated operadic composition of out-splits. Therefore, β3 = σ 1 ◦ · · · ◦ σ r is either a colored unit or an iterated operadic composition of out-splits.  

4.4 Summary of this Chapter

87

4.4 Summary of this Chapter 1. A wiring diagram with no input boxes and no delay nodes is generated by the empty wiring diagram and a finite number of 1-wasted wires. 2. Every wiring diagram ψ has a decomposition ψ = π1 ◦ β1 ◦ β2 ◦ β3 ◦ ϕ in which: • • • • •

π1 is generated by 1-loops; β1 is generated by 1-wasted wires; β2 is generated by in-splits; β3 is generated by out-splits; ϕ is either the empty wiring diagram or is generated by 2-cells and 1-delay nodes.

Chapter 5

Finite Presentation

Fix a class S, with respect to which the BoxS -colored operad WD of wiring diagrams is defined (Theorem 2.41). The main purpose of this chapter is to establish finite presentations for the operad WD of wiring diagrams and its variants WD• and WD0 . For the operad WD, our finite presentation means the following two statements. 1. The 8 generating wiring diagrams (Definition 3.9) generate the operad WD. This means that every wiring diagram can be expressed as a finite iterated operadic composition involving only generating wiring diagrams. 2. If a wiring diagram can be operadically generated by the generating wiring diagrams in two different ways, then there exists a finite sequence of elementary equivalences from the first iterated operadic composition to the other one. An elementary equivalence is induced by either an elementary relation (Definition 3.43) or an operad associativity/unity axiom for the generating wiring diagrams. In Chap. 6 we will use these finite presentations to describe algebras over the operads WD, WD• , and WD0 in terms of finitely many generating structure maps and generating axioms corresponding to the generating wiring diagrams and elementary relations. In Sect. 6.3 we will use the finite presentation for WD-algebras to study the propagator algebra. In Sect. 6.7 we will use the finite presentation for WD0 -algebras to study the algebra of open dynamical systems. In Sect. 5.1 we establish the first part of the finite presentation theorem for WD by showing that every wiring diagram has a stratified presentation (Theorem 5.11). A stratified presentation (Definition 5.9) is a highly structured iterated operadic composition of the generating wiring diagrams. The proof of the second part of the finite presentation theorem also requires the use of stratified presentations. In Sect. 5.2 we establish the second part of the finite presentation theorem for WD. We show that any two presentations of the same wiring diagram in terms of generating wiring diagrams are connected by a finite sequence of elementary equivalences (Theorem 5.22). © Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_5

89

90

5 Finite Presentation

In Sect. 5.3 we establish a finite presentation for the operad WD• of wiring diagrams without delay nodes, which we call normal wiring diagrams. Normal wiring diagrams appeared in Spivak’s study of mode-dependent networks and dynamical systems [45, 47]. In Sect. 5.4 we restrict further and establish a finite presentation for the operad WD0 of wiring diagrams without delay nodes and whose supplier assignments are bijections. We call them strict wiring diagrams. They appeared in [48]. We will use strict wiring diagrams in Sect. 6.7 to study the algebra of open dynamical systems.

5.1 Stratified Presentation In this section, we define a stratified presentation and show that every wiring diagram has a stratified presentation (Theorem 5.11). We also need the concept of a simplex to discuss generators and relations in the operad WD of wiring diagrams. Motivation 5.1. In plain language, a simplex is a finite parenthesized word whose alphabets are generating wiring diagrams, in which each pair of parentheses has a well defined associated ◦i -composition. In particular, a simplex has a well defined operadic composition. As we have seen in Chap. 3, it is often possible to express a wiring diagram as an operadic composition of generating wiring diagrams in multiple ways. In other words, a wiring diagram can have many different simplex presentations. We now start to develop the necessary language to say precisely that any two such simplex presentations of the same wiring diagram are equivalent in some way. Definition 5.2. Suppose n ≥ 1. An n-simplex Ψ and its composition |Ψ | ∈ WD are defined inductively as follows. 1. A 1-simplex is a generating wiring diagram (Definition 3.9) ψ. Its composition |ψ| is defined as ψ itself. 2. Suppose n ≥ 2 and that k-simplices for 1 ≤ k ≤ n − 1and their  compositions in WD are already defined. An n-simplex is a tuple Ψ = ψ, i, φ consisting of • an integer i ≥ 1, • a p-simplex ψ for some p ≥ 1, and • a q-simplex φ for some q ≥ 1 such that: (i) p + q = n; (ii) the operadic composition     def     |Ψ | == ψ  ◦i φ  is defined in WD (Definition 2.34).

(5.1)

5.1 Stratified Presentation

91

The wiring diagram |Ψ | in (5.1) is the composition of Ψ . A simplex in WD is an m-simplex in WD for some m ≥ 1. We say that a simplex Ψ is a presentation of the wiring diagram |Ψ |. Notation 5.3. To simplify the notation, we will sometimes use the right-hand side of (5.1) to denote a simplex. To simplify the notation even further, we may even just list the generating wiring diagrams (ψ1 , . . . , ψn ) in a simplex in the order in which they appear in the composition (5.1), omitting all the pairs of parentheses and the operadic compositions from the notations. Remark 5.4. In Definition 5.2 we could have made the definition for a general operad O other than WD, using a specified collection of elements in O in place of the generating wiring diagrams. Such a definition would be useful in discussing generators and relations in a general operad O. In the next three Examples, every ψi denotes a generating wiring diagram, and we will use Notation 5.3.   Example 5.5. A 2-simplex has the form ψ1 , i, ψ2 , which we abbreviate to ψ1 ◦i ψ2 , for some integer i ≥ 1. For instance, suppose d ∈ S, and X is the box with Xin = {d} = Xout . Suppose Y is an arbitrary box. Then there is a 2-simplex   θX,Y , 1, δd in which θX,Y is a 2-cell (Definition 3.4) and δd is a 1-delay node (Definition 3.2). Its composition θX,Y ◦1 δd is the wiring diagram

in WD

XY  Y

with one delay node.

Example 5.6. A 3-simplex is an iterated operadic composition in WD of the form (ψ1 ◦i ψ2 ) ◦j ψ3

or

ψ1 ◦i (ψ2 ◦j ψ3 )

for some integers i, j ≥ 1. Once again these are really abbreviations for the 3simplices   (ψ1 , i, ψ2 ) , j, ψ3

or

  ψ1 , i, (ψ2 , j, ψ3 ) .

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5 Finite Presentation

For instance, continuing the example above, suppose λXY,d ∈ WD (Definition 3.5). Then there is a 3-simplex



Y  XY

is a 1-loop

   λXY,d , 1, θX,Y , 1, δd whose composition λXY,d ◦1 (θX,Y ◦1 δd ) is the wiring diagram

in WD

Y  Y

with one delay node.

Example 5.7. A 4-simplex is an iterated operadic composition in WD of the form 

 (ψ1 ◦i ψ2 ) ◦j ψ3 ◦k ψ4 ,   ψ1 ◦i (ψ2 ◦j ψ3 ) ◦k ψ4 ,



 ψ1 ◦i (ψ2 ◦j ψ3 ) ◦k ψ4 , (ψ1 ◦i ψ2 ) ◦j (ψ3 ◦k ψ4 ),   or ψ1 ◦i ψ2 ◦j (ψ3 ◦k ψ4 )

for some integers i, j, k ≥ 1. For instance, continuing the previous example, suppose Y out = {y} and Z is a box such that Z out = {z,z} with v(z) =  Z v(z ) = v(y) and that Z/(z = z ) = Y . Suppose σ Z,z,z ∈ WD Y is an out-split (Definition 3.7). Then there is a 4-simplex     σ Z,z,z , 1, λXY,d , 1, (θX,Y , 1, δd ) whose composition    σ Z,z,z ◦1 λXY,d ◦1 (θX,Y ◦1 δd ) is the wiring diagram

in WD

Z  Y

with one delay node.

5.1 Stratified Presentation

93

In Sect. 5.2 we will show that any two presentations of the same wiring diagram are equivalent in a certain way. For this purpose, we will need a more structured kind of presentation. Motivation 5.8. If we think of a simplex as a parenthesized word whose alphabets are generating wiring diagrams, then the stratified simplex in the next definition is a word where the same alphabets must occur in a consecutive string. For example, all the 1-loops must occur together as a string (λ1 , . . . , λn ). Furthermore, we can even insist that these strings for different types of generating wiring diagrams occur in a specific order, with name changes and 1-loops at the top and with 1-delay nodes and 2-cells at the bottom. Definition 5.9. A stratified simplex in WD is a simplex in WD (Definition 5.2) of one of the following two forms, where Notation 5.3 is used:   1. ω,  , where: • ω is a possibly empty string of 1-wasted wires (Definition 3.8); •  is the empty wiring diagram (Definition 3.1).   2. τ, λ, ω, σ ∗ , σ ∗ , θ , δ , where: • • • • • • •

τ is a name change (Definition 3.3); λ is a possibly empty string of 1-loops (Definition 3.5); ω is a possibly empty string of 1-wasted wires; σ ∗ is a possibly empty string of in-splits (Definition 3.6); σ ∗ is a possibly empty string of out-splits (Definition 3.7); θ is a possibly empty string of 2-cells (Definition 3.4); δ is a possibly empty string of 1-delay nodes (Definition 3.2).

We call these stratified simplices of type (1) and of type (2), respectively. If Ψ is a stratified simplex, then we call it a stratified presentation of the wiring diagram |Ψ |. Remark 5.10. Stratified simplices of type (1) and of type (2) are mutually exclusive. Indeed, the composition of a stratified simplex of type (1) has no input boxes and no delay nodes. On the other hand, the composition of a stratified simplex of type (2) either has at least one input box or at least one delay node or both. Using the decompositions in the previous chapter, we now observe that the generating wiring diagrams generate the operad WD of wiring diagrams in a highly structured way. Theorem 5.11. Every wiring diagram has a stratified presentation (Definition 5.9). Y 

Proof. Suppose ψ ∈ WD X is a general wiring diagram as in Assumption 4.1 with input boxes X = (X1 , . . . , XN ) and delay nodes DNψ = {d1 , . . . , dr }. Recall Notation 3.14 for (iterated) ◦1 . If N = r = 0, then ψ has a stratified presentation of type (1) by Lemma 4.3. Next suppose N + r ≥ 1. We use the decomposition ψ = α ◦ ϕ (4.6) and show that ψ has a stratified presentation of type (2) using the following observations.

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5 Finite Presentation

1. If N + r = 1, then ϕ is either a colored unit, which can be ignored in a simplex by Lemma 2.36, or a 1-delay node by Lemma 4.8.   2. If N + r ≥ 2, then ϕ has a stratified presentation θ , δ consisting of 2-cells and 1-delay nodes by Lemma 4.10 and by the equivalence between γ and the ◦i -compositions (2.16). 3. By definition α (4.5) has one input box and no delay nodes. There is a decomposition α = π1 ◦ π2 by Lemma 4.16. The outer  wiring diagram π1 is either a colored unit or has a stratified presentation λ consisting of 1-loops by Lemma 4.17. 4. Furthermore, by Lemma 4.22 there is a decomposition π2 = β1 ◦ β2 ◦ β3 in which:   • β1 is a colored unit or has a stratified presentation ω consisting of 1-wasted wires by Lemma 4.23.   • β2 is a colored unit or has a stratified presentation σ ∗ consisting of in-splits by Lemma 4.26.   • β3 is a colored unit or has a stratified presentation σ ∗ consisting of out-splits by Lemma 4.29. Using the decomposition ψ = π1 ◦ β1 ◦ β2 ◦ β3 ◦ ϕ together with Convention 4.14, we obtain the desired stratified presentation of type (2) for ψ when N + r ≥ 1.  

5.2 Finite Presentation for Wiring Diagrams The purpose of this section is to establish the second part of the finite presentation theorem for the operad WD. First we define precisely what it means for two presentations of the same wiring diagram to be related to each other. Recall the 28 elementary relations (Definition 3.43) and the definition of a colored operad (Definition 2.10). In what follows, we will regard each operad associativity or unity axiom as an equality. We remind the reader of Notation 5.3 regarding simplices in WD. Motivation 5.12. Recall that a simplex is essentially a parenthesized word whose alphabets are generating wiring diagrams. In the next definition, we develop the precise concept through which one simplex presentation of a wiring diagram may be replaced by another. We only allow replacement of strings within a simplex corresponding to either one of the 28 elementary relations or an operad associativity/unity axiom. When such a replacement within a simplex is possible, we say that the two simplices are elementarily equivalent.

5.2 Finite Presentation for Wiring Diagrams

95

Definition 5.13. Suppose Ψ is an n-simplex in WD as in Definition 5.2. 1. A subsimplex of Ψ is a simplex in WD defined inductively as follows. • If Ψ is a 1-simplex, then a subsimplex  of Ψ is Ψ itself.  • Suppose n ≥ 2 and Ψ = ψ, i, φ for some i ≥ 1, p-simplex ψ, and qsimplex φ with p + q = n. Then a subsimplex of Ψ is – a subsimplex of ψ, – a subsimplex of φ, or – Ψ itself. If Ψ  is a subsimplex of Ψ , then we write Ψ  ⊆ Ψ . 2. An elementary subsimplex Ψ  of Ψ is a subsimplex of one of two forms: (i) Ψ  is one side (either left or right) of a specified elementary relation (Definition 3.43). (ii) Ψ  is one side (either left or right) of a specified operad associativity or unity axiom—(2.11), (2.12), (2.13), or (2.14)—involving only the generating wiring diagrams (Definition 3.9). 3. Suppose Φ is another simplex in WD. Then Ψ and Φ are said to be equivalent if their compositions are equal; i.e., |Ψ | = |Φ| ∈ WD. 4. Suppose: • Ψ  ⊆ Ψ is an elementary subsimplex corresponding to one side of R, which is either an elementary relation or an operad associativity/unity axiom for the generating wiring diagrams. • Ψ  is the simplex given by the other side of R. • Ψ 1 is the simplex obtained from Ψ by replacing the subsimplex Ψ  by Ψ  . We say that Ψ and Ψ 1 are elementarily equivalent. Note that elementarily equivalent simplices are also equivalent. 5. If Ψ and Φ are elementarily equivalent, we write Ψ ∼ Φ and call this an elementary equivalence. 6. Suppose Ψ0 , . . . , Ψr are simplices for some r ≥ 1 and that there exist elementary equivalences Ψ0 ∼ Ψ1 ∼ · · · ∼ Ψr . Then we say that Ψ0 and Ψr are connected by a finite sequence of elementary equivalences. Note that in this case Ψ0 and Ψr are equivalent. Remark 5.14. In the definition of an elementary subsimplex and an elementary equivalence, we did not use the operad equivariance axiom (2.15). The reason is that the associativity and commutativity properties of 2-cells—namely, the elementary relations (3.11) and (3.12)—are enough to guarantee the operad equivariance axiom involving only the generating wiring diagrams.

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5 Finite Presentation

Example 5.15. In a 3-simplex (ψ1 ◦i ψ2 ) ◦j ψ3 , both (ψ1 , ψ2 ) = ψ1 ◦i ψ2

and

(ψ1 , ψ2 , ψ3 ) = (ψ1 ◦i ψ2 ) ◦j ψ3

are subsimplices. However, (ψ2 , ψ3 ) is not a subsimplex. Example 5.16. A given wiring diagram may have many different equivalent presentations. For example, suppose X ∈ BoxS . Then the 1-simplex consisting of the X-colored unit 1X (2.24) is elementarily equivalent to: 1. the 2-simplex θX,∅ ◦2  by (3.10);      1 2 2. the 3-simplex λZ,x ◦ ωZ,x1 ◦ σ Y,x ,x by (3.22);     3. the 2-simplex σY,x,y ◦ ωY,y by (3.27). Any two of these three simplices are connected by a finite sequence of elementary equivalences. Note that elementarily equivalent simplices may have different lengths. Example 5.17. Suppose: XY 

• θX,Y ∈ WD X,Y  is a 2-cell (Definition 3.4). X • θV ,W ∈ WD V,W is a 2-cell with X = V  W ∈ BoxS . Y • σT ,t1 ,t2 ∈ WD T is an in-split (Definition 3.6). Then the 3-simplices 

 θX,Y ◦1 θV ,W ◦3 σT ,t1 ,t2

and

  θX,Y ◦2 σT ,t1 ,t2 ◦1 θV ,W

are elementarily equivalent by the horizontal associativity axiom (2.11). This elementary equivalence expresses the fact that the wiring diagram

can be created from θX,Y by substituting in the two gray boxes in either order. Convention 5.18. In what follows, to simplify the presentation, elementary equivalences corresponding to an operad associativity/unity axiom—(2.11), (2.12), (2.13), or (2.14)—for the generating wiring diagrams will often be applied tacitly wherever necessary. For instance, an elementary equivalence given by replacing one of the 3simplices in Example 5.17 by the other one will often not be mentioned explicitly.

5.2 Finite Presentation for Wiring Diagrams

97

Our next goal is to show that any two equivalent simplices are connected by a finite sequence of elementary equivalences. In other words, with respect to the generating wiring diagrams, the 28 elementary relations and the operad associativity/unity axioms—(2.11)–(2.14)—for the generating wiring diagrams generate all the relations in WD. During the first reading, the reader may wish to skip the proofs of the following three Lemmas. The first step is to show that every simplex is connected to a stratified simplex in the following sense. Lemma 5.19. Every simplex is either a stratified simplex or is connected to an equivalent stratified simplex by a finite sequence of elementary equivalences (Definition 5.13). Proof. Using Notation 5.3 suppose Ψ = (ψ1 , . . . , ψn ) is a simplex with comY  position |Ψ | = ψ ∈ WD X as in Assumption 4.1. So ψ has input boxes X = (X1 , . . . , XN ) and delay nodes DNψ = {d1 , . . . , dr }. Suppose Ψ is not a stratified simplex. We will show that Ψ is connected to an equivalent stratified simplex by a finite sequence of elementary equivalences. Using the five elementary relations (3.5)–(3.9), first we move all the name changes (Definition 3.3) in Ψ , if there are any, to the left. Then we use the elementary relation (3.4) repeatedly to compose them down into one name change. Therefore, after a finite sequence of elementary equivalences, we may assume that there is at most one name change in Ψ , which is the leftmost entry. If there are further elementary equivalences later that create name changes, we will perform the same procedure without explicitly mentioning it. ∅ The empty wiring diagram  ∈ WD (Definition 3.1) and the 1-delay nodes d  δd ∈ WD (Definition 3.2) have no input boxes, so no operadic composition of the forms ◦i —or δd ◦i —can be defined. Therefore, after a finite sequence of elementary equivalences corresponding to the horizontal associativity axiom (2.11), we may assume that Ψ has the form 

τ, Ψ 1 , , δ



in which: • • • •

τ is a name change; all the 1-delay nodes δ are at the rightmost entries; all the empty wiring diagrams  are just to their left; Ψ 1 is either empty or is a subsimplex involving 2-cells (Definition 3.4), 1loops (Definition 3.5), in-splits (Definition 3.6), out-splits (Definition 3.7), and 1-wasted wires (Definition 3.8).

Next we use the elementary relations (3.13)–(3.16) to move all the 2-cells in Ψ just to the left of . Then we use the elementary relations (3.18)–(3.20) to move all the remaining 1-loops just to the right of the name change τ . After that, we use the elementary relations (3.26) and (3.30) to move all the 1-wasted wires just to the

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5 Finite Presentation

right of the 1-loops. Then we use the elementary relation (3.25) to move all the insplits just to the right of the 1-wasted wires. So after a finite sequence of elementary equivalences, we may assume that the simplex Ψ has the form   τ, λ, ω, σ ∗ , σ ∗ , θ , , δ .

(5.2)

If the string  of empty wiring diagrams is empty, then we are done because this is now a stratified simplex of type (2). So suppose the string  in (5.2) is non-empty. Using finitely many elementary equivalences corresponding to the elementary relations (3.10)–(3.12), we may cancel all the unnecessary empty wiring diagrams in (5.2). If there are no empty wiring diagrams left after the cancellation, then we have a stratified simplex of type (2). Suppose that, after the cancellation in the previous paragraph, the resulting string  is still non-empty. Then it must contain a single empty wiring diagram , and there are no 2-cells θ and no 1-delay nodes δ in the resulting simplex Ψ . Since the output box of  is the empty box, the current simplex Ψ cannot have any 1-loops λ, in-splits σ ∗ , or out-splits σ ∗ . Therefore, in this case the simplex (5.2) has the form   τ, ω,  .

(5.3)

There are now two cases. First suppose the string ω in (5.3) is empty. Since the output box of  is the empty box, in the simplex (τ, ) the name change τ must be unit of the empty box. So by the left unity axiom (2.13), the simplex the colored  1∅ ,  is elementarily equivalent to the simplex (), which is a stratified simplex of type (1). Next suppose the string ω in (5.3) is non-empty. Using finitely many elementary equivalences corresponding to the elementary relation (3.9), the simplex (5.3) is connected to a simplex of the form   ω, τ, 

(5.4)

with τ ◦  as one of the operadic compositions. As in the previous case, the composition   τ ◦  forces τ to be the colored unit of the empty box.  So  the simplex ω, 1∅ ,  in (5.4) is elementarily equivalent to the simplex ω,  , which is a stratified simplex of type (1).   The next step is to show that equivalent stratified simplices are connected. We begin with stratified simplices of type (1). Lemma 5.20. Any two equivalent stratified simplices of type (1) are either equal or are connected by a finite sequence of elementary equivalences (Definition 5.13).     Proof. Suppose Ψ 1 = ω1 ,  and Ψ 2 = ω2 ,  are equivalent stratified simplices of type (1) with common composition ψ. Then ψ has no input boxes and no delay

5.2 Finite Presentation for Wiring Diagrams

99

nodes, and its output box contains only external wasted wires as in Lemma 4.3. Each 1-wasted wire in each Ψ i creates one external wasted wire in ψ. So the 1-wasted wire strings ω1 and ω2 have the same length. It follows that the simplices Ψ 1 and Ψ 2 are connected by a finite sequence of elementary equivalences corresponding to the elementary relation (3.31) and the vertical associativity axiom (2.12).   Lemma 5.21. Any two equivalent stratified simplices of type (2) are either equal or are connected by a finite sequence of elementary equivalences (Definition 5.13). Proof. The proof consists of a series of reductions. Suppose Ψ 1 and Ψ 2 are distinct but equivalent stratified simplices of type (2) with common composition Y  ψ ∈ WD X . Using elementary equivalences corresponding to • the operad unity axioms (2.13) and (2.14), • the elementary relations (3.10), (3.22), and (3.27) regarding colored units, and • other elementary relations that move the generating wiring diagrams around the simplices, we may assume that there are no unnecessary generating wiring diagrams in these stratified simplices. Here unnecessary refers to either a colored unit or generating wiring diagrams whose (iterated) operadic composition is a colored unit. The name change τ 1 in Ψ 1 has output box Y and input box uniquely determined by ψ, and the same is true for the name change τ 2 in Ψ 2 . It follows that τ 1 is equal to τ 2 . So we may assume that there are no name changes in the two stratified simplices Ψ i . The string of delay nodes δ i in each simplex Ψ i represents the set of delay nodes in ψ. Therefore, the two Ψ i without their strings of delay nodes are also equivalent. Moreover, if these simplices without delay nodes are connected by a finite sequence of elementary equivalences, then so are the two Ψ i themselves by the horizontal associativity axiom (2.11). So we may assume that the wiring diagram ψ and the two simplices Ψ i have no delay nodes. At this stage, each stratified simplex Ψ i has the form   λi , ωi , σ i∗ , σ ∗i , θ i . The composition of the string of 2-cells |θ i | in each simplex Ψ i has the same input boxes as ψ. So using finitely many elementary equivalences corresponding to the elementary relations (3.11) and (3.12), we may assume that the wiring diagram ψ has only one input box and that the simplices Ψ i have no 2-cells. At this stage, each stratified simplex Ψ i has the form 

 λi , ω i , σ i∗ , σ ∗i .

Observe that for each i ∈ {1, 2}, the string of 1-wasted wires ωi in the simplex w  ψ w of external and internal wasted wires Ψ i corresponds to precisely the set ψ− + in the wiring diagram ψ (Definition 2.25). Here an internal wasted wire in ψ is

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5 Finite Presentation

created by applying a 1-loop to a 1-wasted wire as in (3.1). Therefore, using finitely many elementary equivalences corresponding to the elementary relations (3.17) and (3.20), we may assume that the wiring diagram ψ and the two simplices Ψ i have no 1-wasted wires. At this stage, each stratified simplex Ψ i has the form   λi , σ i∗ , σ ∗i . Using finitely many elementary equivalences corresponding to the elementary relation (3.21), we may assume that each loop element in the wiring diagram ψ (Definition 4.11) corresponds to precisely one 1-loop λ in each simplex Ψ i . At this stage, the 1-loops in each simplex Ψ i are in bijection in ψ.  with the loop elements  Moreover, the two stratified subsimplices σ 1∗ , σ ∗1 ⊆ Ψ 1 and σ 2∗ , σ ∗2 ⊆ Ψ 2 are equivalent. Therefore, using finitely many elementary equivalences corresponding to the elementary relation (3.17), we may assume that the wiring diagram ψ has no loop elements and that the simplices Ψ i have no 1-loops. So each stratified simplex Ψ i now has the form   σ i∗ , σ ∗i .   The two stratified subsimplices σ i∗ ⊆ Ψ i of in-splits for i ∈ {1, 2} are also equivalent. They are connected by a finite sequence of elementary equivalences corresponding to the elementary relations (3.23) and (3.24). Likewise, the stratified subsimplices σ ∗i ⊆ Ψ i of out-splits for i ∈ {1, 2} are connected by a finite sequence of elementary equivalences corresponding to the elementary relations (3.28) and (3.29). So the two simplices Ψ i are also connected by a finite sequence of elementary equivalences.   We are now ready for the finite presentation theorem for wiring diagrams. It describes the wiring diagram operad WD (Theorem 2.41) in terms of finitely many generators and finitely many relations. Theorem 5.22. Consider the operad WD of wiring diagrams. 1. Every wiring diagram can be obtained from finitely many generating wiring diagrams (Definition 3.9) via iterated operadic compositions (Definition 2.10). 2. Any two equivalent simplices are either equal or are connected by a finite sequence of elementary equivalences (Definition 5.13). Proof. The first statement is a special case of Theorem 5.11. The second statement is a combination of Remark 5.10, Lemma 5.19 twice, Lemmas 5.20, and 5.21.  

5.3 Finite Presentation for Normal Wiring Diagrams

101

5.3 Finite Presentation for Normal Wiring Diagrams In this section, we establish a finite presentation theorem for the operad of wiring diagrams without delay nodes. Such wiring diagrams are used in [45, 47] to study mode-dependent networks and dynamical systems. Recall Definitions 2.25, 2.27, and Convention 2.28 regarding wiring diagrams. Definition 5.23. Fix a class S. 1. A wiring diagram is said to be normal if its set of delay nodes is empty. 2. The collection of normal wiring diagrams is denoted by WD• . If we want to emphasize S, then we will write WDS• . Example 5.24. Among the 8 generating wiring diagrams (Sect. 3.1): 1. A 1-delay node δd (Definition 3.2) is not normal. 2. The empty wiring diagram  (Definition 3.1), a name change τX,Y (Definition 3.3), a 2-cell θX,Y (Definition 3.4), a 1-loop λX,x (Definition 3.5), an in-split σX,x1 ,x2 (Definition 3.6), an out-split σ Y,y1 ,y2 (Definition 3.7), and a 1-wasted wire ωY,y (Definition 3.8) are normal. In particular, there is a proper inclusion WD•  WD. Furthermore, the 1-internal wasted wire ωX,x (Definition 3.11) is normal. Example 5.25. All the wiring diagrams that appear in the 28 elementary relations (Sect. 3.3) are normal. Example 5.26. Among the wiring diagrams in Chap. 4: 1. ϕ (4.4) is not normal, unless r = 0. 2. ψ in (4.3), α (4.5), π1 (4.10), π2 (4.11), β1 (4.14), β2 (4.15), and β3 (4.16) are normal. Proposition 5.27. With respect to • the equivariant structure in Definition 2.31, • the colored units in Definition 2.32, and • the ◦i -compositions in Definition 2.34, WD• is a BoxS -colored operad, called the operad of normal wiring diagrams. Proof. We can reuse the proof of Theorem 2.41—that WD is a BoxS -colored operad—as long as we know that the relevant structure is well-defined in WD• . The collection WD• is closed under the equivariant structure map (2.23). Furthermore, each colored unit 1Y (2.24) is in WD• . Suppose both ϕ and ψ are normal wiring diagrams such that ϕ ◦i ψ ∈ WD is defined. Then ϕ ◦i ψ is also normal because DNϕ◦i ψ = DNϕ  DNψ = ∅.

102

5 Finite Presentation

Therefore, Lemmas 2.36, 2.38, and 2.40 all apply to WD• to show that it is an operad.   Our next objective is to obtain a version of the finite presentation theorem for WD• . For this purpose, we will use the following definitions. Definition 5.28. Consider the operad WD• of normal wiring diagrams. 1. A normal generating wiring diagram is a generating wiring diagram (Definition 3.9) except for 1-delay nodes δd (Definition 3.2). 2. A normal simplex is defined as in Definition 5.2 using normal generating wiring diagrams and WD• in place of WD. 3. A normal stratified simplex and a normal stratified presentation are defined as in Definition 5.9 with WD• in place of WD, except that a normal stratified simplex  of type (2) has the form τ, λ, ω, σ ∗ , σ ∗ , θ . 4. All of Definition 5.13 is repeated with normal generating wiring diagrams and WD• in place of WD. The following result is the finite presentation theorem for normal wiring diagrams. Theorem 5.29. Consider the operad WD• of normal wiring diagrams. 1. Every normal wiring diagram has a normal stratified presentation. 2. Every normal wiring diagram can be obtained from finitely many normal generating wiring diagrams via iterated operadic compositions (Definition 2.10). 3. Any two equivalent normal simplices are connected by a finite sequence of elementary equivalences (Definition 5.13). Proof. For statement (1), we reuse the proof of Theorem 5.11 while assuming r = 0. Statement (2) is a special case of statement (1). For statement (3) we reuse the proof of Theorem 5.22(2). In other words, we simply reuse the proofs of Lemmas 5.19–5.21 while assuming r = 0 throughout. The key observation is that, for normal simplices, elementary equivalences as in Definition 5.13 involve either: • elementary relations (Definition 3.43), none of which involves delay nodes, or • an operad associativity or unity axiom—(2.11), (2.12), (2.13), or (2.14)—for the normal generating wiring diagrams. So in the WD• versions of these Lemmas, we simply ignore all the delay nodes in the original proofs.  

5.4 Finite Presentation for Strict Wiring Diagrams In this section, we establish a finite presentation theorem for the operad of strict wiring diagrams. Such wiring diagrams are used in [48] to study open dynamical systems.

5.4 Finite Presentation for Strict Wiring Diagrams

103

Definition 5.30. Fix a class S. 1. A wiring diagram (Definition 2.27) is said to be strict if (i) it is normal (Definition 5.23) and (ii) its supplier assignment is a bijection. 2. The collection of strict wiring diagrams is denoted by WD0 . If we want to emphasize S, then we will write WDS0 . Remark 5.31. What we call a strict wiring diagram is simply called a wiring diagram in [48, Def. 3.5]. In [48, Remark 2.7] S is a set of representatives of isomorphism classes of second-countable smooth manifolds. The non-instantaneity requirement (2.20) in this case is called the no passing wires requirement in [48]. As noted in [48, Remark 3.6], strictness implies the non-existence of external wasted wires, internal wasted wires (Definition 2.25), and split wires, i.e., multiple (at least two) demand wires having the same supply wire. So strict wiring diagrams are much simpler than a general wiring diagram. Example 5.32. Among the 8 generating wiring diagrams (Sect. 3.1): 1. A 1-delay node δd (Definition 3.2) is not normal (Definition 5.23), hence also not strict. 2. The empty wiring diagram  (Definition 3.1), a name change τX,Y (Definition 3.3), a 2-cell θX,Y (Definition 3.4), and a 1-loop λX,x (Definition 3.5) are strict. 3. An in-split σX,x1 ,x2 (Definition 3.6), an out-split σ Y,y1 ,y2 (Definition 3.7), and a 1-wasted wire ωY,y (Definition 3.8) are normal but not strict. In particular, there are proper inclusions WD0  WD•  WD. Furthermore, the 1-internal wasted wire ωX,x (Definition 3.11) is normal but not strict. Example 5.33. Among the wiring diagrams that appear in the 28 elementary relations (Sect. 3.3): 1. (3.4)–(3.6), (3.10)–(3.13), (3.17), (3.22), and (3.27) are strict wiring diagrams. 2. The other 18 are normal but not strict. 3. Only (3.4)–(3.6), (3.10)–(3.13), and (3.17) involve only strict wiring diagrams on both sides. Indeed, both (3.22) and (3.27) involve a 1-wasted wire, which is not strict. Example 5.34. Among the wiring diagrams in Chap. 4: 1. ψ in (4.3) is normal but not strict. 2. α (4.5), π2 (4.11), β1 (4.14), β2 (4.15), and β3 (4.16) are normal but not strict in general. 3. π1 (4.10) is a strict wiring diagram by Lemma 4.17.

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5 Finite Presentation

Proposition 5.35. With respect to • the equivariant structure in Definition 2.31, • the colored units in Definition 2.32, and • the ◦i -compositions in Definition 2.34, WD0 is a BoxS -colored operad, called the operad of strict wiring diagrams. Proof. The argument is essentially identical to the proof of Proposition 5.27 with a minor modification. Suppose both ϕ and ψ are strict wiring diagrams such that ϕ ◦i ψ ∈ WD is defined. Then ϕ ◦i ψ is also strict. Indeed, we already know that it is normal. Next, one can check directly from the definition of the supplier assignment sϕ◦i ψ (2.26) that it is a bijection because, in all cases, it is defined as a composition of the bijections sϕ and sψ . Therefore, Lemmas 2.36, 2.38, and 2.40 all apply to WD0 to show that it is an operad.   Our next objective is to obtain a version of the finite presentation theorem for WD0 . For this purpose, we will use the following definitions. Definition 5.36. Consider the operad WD0 of strict wiring diagrams. 1. A strict generating wiring diagram means the empty wiring diagram  (Definition 3.1), a name change τX,Y (Definition 3.3), a 2-cell θX,Y (Definition 3.4), or a 1-loop λX,x (Definition 3.5). 2. A strict simplex is defined as in Definition 5.2 using strict generating wiring diagrams and WD0 in place of WD. 3. A strict stratified simplex is a stratified simplex (Definition 5.9) of the form ()   or τ, λ, θ . 4. If Ψ is a strict stratified simplex, then we call it a strict stratified presentation of the strict wiring diagram |Ψ |. 5. A strict elementary relation means one of the 8 elementary relations that involve only strict wiring diagrams on both sides, namely, (3.4)–(3.6), (3.10)–(3.13), and (3.17). See Example 5.33. 6. All of Definition 5.13 is repeated with WD0 in place of WD using strict generating wiring diagrams, strict simplices, and strict elementary relations. The resulting notions are called strict elementary equivalences, and so forth. The following result is the finite presentation theorem for strict wiring diagrams. Theorem 5.37. Consider the operad WD0 of strict wiring diagrams. 1. Every strict wiring diagram has a strict stratified presentation. 2. Every strict wiring diagram can be obtained from finitely many strict generating wiring diagrams via iterated operadic compositions (Definition 2.10). 3. Any two equivalent strict simplices are connected by a finite sequence of strict elementary equivalences.

5.5 Summary of this Chapter

105

Proof. As in the proof of Theorem 5.29, for statement (1), we reuse the proof of Theorem 5.11 while assuming the wiring diagram ψ is strict. In this case, ψ is either the empty wiring diagram  or has a decomposition (using (4.6) and (4.12)) ψ = π1 ◦ π2 ◦ ϕ in which π2 (4.11) is a name change. The desired strict stratified presentation follows from Convention 4.14 and the facts that: • π1 is either a colored unit or has a stratified presentation (λ) by Lemma 4.17; • ϕ is either a colored unit or has a stratified presentation (θ ) by Lemma 4.10. Statement (2) is a special case of statement (1). For statement (3) we use the strict versions of the proofs of Lemmas 5.19–5.21. The key observation is that, in this case, only strict generating wiring diagrams and strict elementary equivalences are used in these proofs.  

5.5 Summary of this Chapter 1. A simplex in WD is a finite non-empty parenthesized word of generating wiring diagrams in which each pair of parentheses is equipped with an operadic ◦i composition. 2. A stratified simplex in WD is a simplex of one of the following two forms.   • ω,   • τ, λ, ω, σ ∗ , σ ∗ , θ , δ 3. Every wiring diagram has a stratified presentation. 4. Two simplices are elementarily equivalent if one can be obtained from the other by replacing a subsimplex Ψ  by an equivalent simplex Ψ  such that |Ψ  | = |Ψ  | is either one of the twenty-eight elementary relations in WD or an operad associativity/unity axiom involving only the eight generating wiring diagrams. 5. Any two simplex presentations of a given wiring diagram are connected by a finite sequence of elementary equivalences. 6. A normal wiring diagram is a wiring diagram with no delay nodes. 7. The operad WD• of normal wiring diagrams satisfies a finite presentation theorem involving the seven normal generating wiring diagrams and the 28 elementary relations. 8. A strict wiring diagram is a wiring diagram with no delay nodes and whose supplier assignment is a bijection. 9. The operad WD0 of strict wiring diagrams satisfies a finite presentation theorem involving the four strict generating wiring diagrams and the eight strict elementary relations.

Chapter 6

Finite Presentation for Algebras over Wiring Diagrams

The main purpose of this chapter is to provide finite presentations for algebras over the operads WD (Theorem 2.41), WD• (Proposition 5.27), and WD0 (Proposition 5.35). The advantage of such a finite presentation is that sometimes the general structure map of an operad algebra can be a bit difficult to write down and understand. On the other hand, our generating structure maps and generating axioms are all fairly easy to write down and understand, as we will illustrate with examples in Sects. 6.3, 6.5, and 6.7. In Sect. 6.1 we recall the basics of algebras over an operad. In Sect. 6.2 we first define a WD-algebra in terms of 8 generating structure maps and 28 generating axioms corresponding to the generating wiring diagrams (Definition 3.9) and the elementary relations (Definition 3.43), respectively. Then we observe that this finite presentation for a WD-algebra is in fact equivalent to the general definition of a WD-algebra (Theorem 6.10). This is an application of the finite presentation theorem for the operad WD (Theorem 5.22). In Sect. 6.3 we provide a finite presentation for the WD-algebra called the propagator algebra. In its original form, the propagator algebra was the main example in [42]. In Sect. 6.4 we observe that algebras over the operad WD• of normal wiring diagrams have a similar finite presentation with 7 generating structure maps and 28 generating axioms. In Sect. 6.5 we provide a finite presentation for the WD• -algebra called the algebra of discrete systems. In its original form, this algebra was one of the main examples in [45]. In Sect. 6.6 we observe that algebras over the operad WD0 of strict wiring diagrams admit a finite presentation with 4 generating structure maps and 8 generating axioms. In Sect. 6.7 we provide a finite presentation for the WD0 -algebra called the algebra of open dynamical systems. In its original form, this algebra was one of the main examples in [48].

© Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_6

107

108

6 Finite Presentation for Algebras over Wiring Diagrams

6.1 Operad Algebras Let us first recall the definition of an algebra over an operad. The following definition can be found in [51, Def. 13.2.3]. In its original 1-colored topological form, it was first given in [35]. Fix a class S as before. Motivation 6.1. One can think of an algebra over an operad as a generalization of a module over a ring. Given a ring R, a left R-module M is equipped with / M for each element r ∈ R that satisfy some axioms. structure maps r : M In particular, these structure maps are associative in the sense that (r1 r2 )(m) = r1 (r2 m) for r1 , r2 ∈ R and m ∈ M. Furthermore, the multiplicative unit 1R of R acts as the identity map, so 1R (m) = m. For algebras over an operad, there is also an equivariance axiom because operads can model operations with multiple inputs. Definition 6.2. Suppose (O, 1, γ ) is an S-colored operad as in Definition 2.3. An O-algebra is a pair (A, μ) consisting of the following data. 1. For each c ∈ S, A is equipped with a class Ac called the c-colored entry of A. d 2. For each d ∈ S, c = (c1 , . . . , cn ) ∈ Prof(S), and ζ ∈ O c , A is equipped with a structure map

(6.1) in which an empty product, for the case n = 0, means the one-point set {∗}. This data is required to satisfy the following associativity, unity, and equivariance axioms. d 

d 

Associativity Suppose c ∈ Prof(S) × S is as above with n ≥ 1, ζ0 ∈ O c , c  ζi ∈ O bii for each 1 ≤ i ≤ n with bi ∈ Prof(S), and b = b1 , . . . , bn as   d  in (2.2). Write ζ = γ ζ0 ; ζ1 , . . . , ζn ∈ O b . Then the diagram

(6.2) is commutative.

6.1 Operad Algebras

Unity

109

For each c ∈ S, the structure map (6.3) c

is the identity map, where 1c ∈ O c is the c-colored unit of O.   d d Equivariance Suppose ζ ∈ O c as in (6.1), σ ∈ Σn , and ζ σ ∈ O cσ is the image of ζ under the right action (2.1). Then the diagram

(6.4) −1 is commutative. Here the  top σ permutes the factors of Ac from the left, and  cσ = cσ (1) , . . . , cσ (n) .

To simplify the notation, we will sometimes denote an O-algebra by just A and denote the structure map μζ by ζ . Just as operads can be expressed in terms of the ◦i -compositions (Proposition 2.12), so can operad algebras. Definition 6.3. Suppose (O, 1, ◦) is an S-colored operad as in Definition 2.10. An O-algebra (A, μ) is defined exactly as in Definition 6.2 except that the associativity axiom (6.2) is replaced by the following axiom. Associativity

Suppose:

• d ∈ S, c = (c1 , . . . , cn ) ∈ Prof(S) with n ≥ 1, and 1 ≤ i ≤ n; • b ∈ Prof(S) andc ◦i b as in (2.10);   d  c d • ζ ∈ O c , ξ ∈ O bi , and ζ ◦i ξ ∈ O c◦i b . Then the diagram

(6.5) is commutative. Notation 6.4. To simplify the notation, we will sometimes denote the structure map μζ by ζ . We will also write the composition in the diagram (6.5) as μζ ◦i μξ , called the ◦i -composition of μζ and μξ . So this associativity axiom states that μζ ◦ i ξ = μζ ◦ i μξ .

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6 Finite Presentation for Algebras over Wiring Diagrams

In other words, the structure map of the ◦i -composition ζ ◦i ξ is the ◦i -composition of the structure maps corresponding to ζ and ξ . Using the associativity and the unity axioms in Definitions 2.3 and 2.10, it is not hard to check that Definitions 6.2 and 6.3 are in fact equivalent. A proof of this equivalence can be found in [51, Prop. 16.7.8 and Exercises 10 and 11 in Chapter 16]. Remark 6.5. In Definitions 6.2 and 6.3, each entry of an operad algebra has no structure beyond being a class. We could have just as easily defined operad algebras in a symmetric monoidal category, which is in fact the setting in [51, Definition 13.2.3]. One simply replaces the product with the symmetric monoidal product and the one-point set with the monoidal unit. However, to keep the presentation simple, we chose to define operad algebras whose entries are just classes. This is sufficient for the main examples in Sects. 6.3, 6.5, and 6.7. Example 6.6 (Monoid Modules). Suppose (A, μ, 1) is a monoid (Example 2.6). Recall that a left A-module is a set M equipped with a structure map a : / M for each a ∈ A that is associative and unital. Associativity means M (ab)m = a(bm) for a, b ∈ A and m ∈ M. Unity means 1m = m for m ∈ M. If we regard A as a 1-colored operad O concentrated in arity 1 as in Example 2.6, then left A-modules yield O-algebras in the sense of Definition 6.2. The only slight difference between a left A-module and an O-algebra is that the former has an underlying set, while the latter is allowed to have an underlying class. Example 6.7 (Associative and Commutative Monoids). This is a continuation of Example 2.7. 1. For the associative operad As, an As-algebra with an underlying set is exactly a monoid. 2. For the commutative operad Com, a Com-algebra with an underlying set is exactly a monoid whose multiplication is commutative. Example 6.8 (Traffic Spaces and Probability Spaces). This is a continuation of Example 2.8, where we discussed the graph operation operad GrOp. Here we consider GrOp-algebras in the category of complex vector spaces; see Remark 6.5. In particular, a GrOp-algebra A has an underlying complex vector space, and all the structure maps are linear maps, with tensor products playing the roles of products. The graph operation • ∈ GrOp0 , consisting of a single vertex and no edges, yields an element in A, also denoted by •. For a general graph operation G ∈ GrOpn , / A is also denoted by G. We will write the corresponding structure map A⊗n δ ∈ GrOp1 for the graph operation consisting of a single vertex and a loop. A traffic space [30] is a pair (A, ϕ) in which A is a GrOp-algebra and / C is a linear functional such that the following two conditions are ϕ : A satisfied.

6.1 Operad Algebras

111

Unity and Diagonality ϕ(•) = 1 and ϕ = ϕ ◦ δ. Input-Independence For each graph operation G ∈ GrOpn , the graph operation δ(G) ∈ GrOpn is obtained from G by identifying its input and output. Suppose G is a graph operation obtained from δ(G) by choosing a different vertex as the input/output. Then ϕ ◦ δ(G) = ϕ ◦ G . For example, suppose G ∈ GrOp4 is the graph operation on the left:

Then δ(G) is the graph operation in the middle, and the graph operation on the right is an example of a G . Traffic spaces play an important role in (non-commutative) probability theory. Indeed, a non-commutative probability space, also known as a quantum probability space, is a pair (A, ϕ) in which: 1. A is a unital C-algebra. / C is a unital linear functional. 2. ϕ : A A ∗-probability space is a non-commutative probability space (A, ϕ) in which: 1. A is equipped with an anti-linear involution ∗ such that (ab)∗ = b ∗ a ∗ for all a, b ∈ A. 2. ϕ satisfies the positivity condition that ϕ(a ∗ a) ≥ 0 for all a ∈ A. Then a commutative ∗-probability space is an example of a traffic space, since the product of n elements in A is well-defined and is independent of the order of those elements. It is, furthermore, a ∗-algebra in the following sense. For each graph operation G ∈ GrOpn , its transpose Gt is the graph operation obtained from G by reversing the direction of each edge and swapping the input and the output. Then 

G(a1 ⊗ · · · ⊗ an )

for all a1 , . . . , an ∈ A.

∗

= Gt (a1∗ ⊗ · · · ⊗ an∗ )

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6 Finite Presentation for Algebras over Wiring Diagrams

6.2 Algebras over the Operad of Wiring Diagrams The purpose of this section is to provide a finite presentation for WD-algebras. We begin by defining a WD-algebra in terms of the generating wiring diagrams and the elementary relations. Immediately afterwards we will establish its equivalence with Definition 6.3 when O = WD. Recall that WD is a BoxS -colored operad (Theorem 2.41). Definition 6.9. A WD-algebra A consists of the following data. For each X ∈ BoxS , A is equipped with a class AX called the X-colored entry of A. It is equipped with the following 8 generating structure maps corresponding to the generating wiring diagrams (Definition 3.9). 1. Corresponding to the empty wiring diagram  ∈ WD a structure map

∅

(Definition 3.1), it has

(6.6) i.e., a chosen element in A∅ . d  2. Corresponding to each 1-delay node δd ∈ WD (Definition 3.2), it has a structure map (6.7) i.e., a chosen element in Ad . Y  3. Corresponding to each name change τX,Y ∈ WD X (Definition 3.3), it has a structure map (6.8) is the colored unit 1X (2.24). that is, furthermore, the identity map if τX,X XY  4. Corresponding to each 2-cell θX,Y ∈ WD X,Y (Definition 3.4), it has a structure map (6.9) 5. Corresponding to each 1-loop λX,x ∈ WD map

X\x  X

(Definition 3.5), it has a structure

(6.10)

6.2 Algebras over the Operad of Wiring Diagrams

6. Corresponding to each in-split σX,x1 ,x2 ∈ WD structure map

113 Y  X

(Definition 3.6), it has a

(6.11) 7. Corresponding to each out-split σ Y,y1 ,y2 ∈ WD structure map

Y  X

(Definition 3.7), it has a

(6.12) 8. Corresponding to each 1-wasted wire ωY,y ∈ WD structure map

Y  X

(Definition 3.8), it has a

(6.13) The following 28 diagrams, called the generating axioms, which correspond to the elementary relations (Definition 3.43), are required to be commutative. 1. In the setting of (3.4), the diagram

(6.14) is commutative. 2. In the setting of (3.5), the diagram

(6.15) is commutative. 3. In the setting of (3.6), the diagram

(6.16) is commutative.

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6 Finite Presentation for Algebras over Wiring Diagrams

4. In the setting of (3.7), the diagram

is commutative. 5. In the setting of (3.8), the diagram

is commutative. 6. In the setting of (3.9), the diagram

is commutative. 7. In the setting of (3.10), the diagram

(6.17) is commutative. 8. In the setting of (3.11), the diagram

(6.18) is commutative.

6.2 Algebras over the Operad of Wiring Diagrams

115

9. In the setting of (3.12), the diagram

(6.19) is commutative. 10. In the setting of (3.13), the diagram

(6.20) is commutative. 11. In the setting of (3.14), the diagram

is commutative. 12. In the setting of (3.15), the diagram

is commutative. 13. In the setting of (3.16), the diagram

is commutative.

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6 Finite Presentation for Algebras over Wiring Diagrams

14. In the setting of (3.17), the diagram

(6.21) is commutative. 15. In the setting of (3.18), the diagram

is commutative. 16. In the setting of (3.19), the diagram

is commutative. 17. In the setting of (3.20), the diagram

is commutative. 18. In the setting of (3.21), the diagram

(6.22) is commutative.

6.2 Algebras over the Operad of Wiring Diagrams

19. In the setting of (3.22), the diagram

is commutative. 20. In the setting of (3.23), the diagram

is commutative. 21. In the setting of (3.24), the diagram

is commutative. 22. In the setting of (3.25), the diagram

is commutative. 23. In the setting of (3.26), the diagram

is commutative.

117

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6 Finite Presentation for Algebras over Wiring Diagrams

24. In the setting of (3.27), the diagram

is commutative. 25. In the setting of (3.28), the diagram

is commutative. 26. In the setting of (3.29), the diagram

is commutative. 27. In the setting of (3.30), the diagram

is commutative. 28. In the setting of (3.31), the diagram

is commutative. This finishes the definition of a WD-algebra.

6.2 Algebras over the Operad of Wiring Diagrams

119

At this moment we have two definitions of a WD-algebra. 1. On the one hand, in Definition 6.3 with O = WD, a WD-algebra has a structure map μζ (6.1) for each wiring diagram ζ . This structure map satisfies the associativity axiom (6.5) for a general operadic composition in WD, together with the unity and the equivariance axioms in Definition 6.2. 2. On the other hand, in Definition 6.9 a WD-algebra has 8 generating structure maps and satisfies 28 generating axioms. We now observe that these two definitions are equivalent, so WD-algebras indeed have a finite presentation as in Definition 6.9. Theorem 6.10. For the operad of wiring diagrams WD (Theorem 2.41), Definition 6.3 with O = WD and Definition 6.9 of a WD-algebra are equivalent. Proof. First suppose (A, μ) is a WD-algebra in the sense of Definition 6.3. To see that it is also a WD-algebra in the sense of Definition 6.9, first note that the structure map μ? (6.1) gives the eight generating structure maps (6.6)–(6.13). Moreover, the generating structure map μ1X (6.8) is the identity map by the unity axiom (6.3). The generating axiom (6.19) is a special case of the equivariance diagram (6.4), so it is commutative. Each of the other 27 generating axioms corresponds to an elementary relation that describes two different ways to construct the same wiring diagram as an iterated operadic composition of generating wiring diagrams. Each such generating axiom asserts that the two corresponding compositions of generating structure maps—defined using the composition in the diagram (6.5)— are equal. The associativity axiom (6.5) of (A, μ) applied twice guarantees that two such compositions are indeed equal. Conversely, suppose A is a WD-algebra in the sense of Definition 6.9, so it has eight generating structure maps that satisfy 28 generating axioms. We must show that it is a WD-algebra in the sense of Definition 6.3. For a wiring diagram ψ ∈ WD with a presentation Ψ (Definition 5.2), we define its structure map μψ (6.1) inductively as follows. 1. If Ψ is a 1-simplex, then Ψ = (ψ), and ψ is a generating wiring diagram by the definition of a simplex. In this case, we define μψ as the corresponding generating structure map (6.6)–(6.13) of A. 2. Inductively, suppose Ψ is an n-simplex for some n ≥ 2, so Ψ = (Φ, i, Θ) for some i ≥ 1, p-simplex Φ, and q-simplex Θ with p+q = n. Since 1 ≤ p, q < n, by the induction hypothesis, the structure maps μ|Φ| and μ|Θ| are already defined. Then we define the structure map μψ = μ|Φ| ◦i μ|Θ|

(6.23)

as in Notation 6.4. By Theorem 5.11 every wiring diagram has a stratified presentation, hence a presentation. To see that the structure map μψ as above is well-defined, we need

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6 Finite Presentation for Algebras over Wiring Diagrams

to show that the map μψ is independent of the choice of a presentation Ψ . Any two presentations of a wiring diagram are by definition equivalent simplices. By Theorem 5.22(2) (= the relations part of the finite presentation theorem for WD), any two equivalent simplices are either equal or are connected by a finite sequence of elementary equivalences. Therefore, it suffices to show that every elementary equivalence in WD yields a commutative diagram involving the generating structure maps of A, where ◦i is interpreted as in Notation 6.4. Recall from Definition 5.13 that an elementary equivalence comes from either an elementary relation or an operad associativity/unity axiom for the generating wiring diagrams. It follows from a direct inspection that the operad associativity and unity axioms—(2.11)–(2.14)—for the generating wiring diagrams yield commutative diagrams involving the generating structure maps of A. In fact, the diagrams involving the horizontal and the vertical associativity axioms (2.11) and (2.12) are commutative because composition of functions is associative. The diagrams for the two unity axioms (2.13) and (2.14) are commutative because the generating structure map for a colored unit (6.8) is required to be the identity map. By definition each of the 28 generating axioms of A corresponds to an elementary relation (Definition 3.43) and is a commutative diagram. Therefore, the structure map μψ for each wiring diagram ψ is well-defined. It remains to check that the structure map μ satisfies the required unity, equivariance, and associativity axioms. The unity axiom (6.3) holds because it is part of the assumption on the generating structure map corresponding to a name change (6.8). The associativity axiom (6.5) holds because the structure map μψ is defined above (6.23) by requiring that the diagram (6.5) be commutative. For the equivariance axiom (6.4), first note that it is enough to check it when the wiring diagram in question is an iterated operadic composition of 2-cells. This is because 2-cells are the only binary generating wiring diagrams (Remark 3.10). All other generating wiring diagrams are either 0-ary or unary, for which equivariance is trivial. So now suppose ζ in the equivariance axiom (6.4) is an iterated operadic composition of 2-cells. If ζ is a 2-cell and the permutation σ is the transposition (1 2) ∈ Σ2 , then the equivariance axiom (6.4) is true by the generating axiom (6.19). The general case now follows from this special case using: • the generating axiom (6.18) corresponding to the associativity property of 2cells (3.11); • the operad associativity axioms (2.11) and (2.12) when applied to 2-cells; • the fact that the transpositions (i, i + 1) for 1 ≤ i ≤ n − 1 generate the symmetric group Σn . So (A, μ) is a WD-algebra in the sense of Definition 6.3.

 

6.3 Finite Presentation for the Propagator Algebra

121

6.3 Finite Presentation for the Propagator Algebra As an illustration of Theorem 6.10, in this section we provide a finite presentation for the WD-algebra called the propagator algebra that was first introduced in [42, Section 3]. This finite presentation involves the structure maps, not the underlying sets. As explained in [42, Section 3.4], the propagator algebra can be used, for example, to provide an iterative description of the Fibonacci sequence. In contrast to the original definition in [42], we will define the propagator algebra using finitely many generating structure maps and axioms—8 generating structure maps and 28 generating axioms to be exact. Since our generating structure maps are rather simple, our description of the propagator algebra is less involved than the original definition and verification in [42]. The equivalence between the two definitions of the propagator algebra is explained in Remark 6.33. Assumption 6.11. Throughout this section, S denotes the class of pointed sets, with respect to which S-boxes (Definition 2.19) and the operad WD are defined (Theorem 2.41). In a pointed set, the base point is denoted by ∗. Recall the concept and notations regarding profiles from Definition 2.1. Let us first recall a few definitions from [42, section 3]. Definition 6.12. Suppose T and U are pointed sets and k ≥ 0. 1. Define the truncation ∂T : Prof≥1 (T )

/ Prof(T ) as the function

∂T (t1 , . . . , tn ) = (t1 , . . . , tn−1 ).

(6.24)

We will often omit the subscript and just write ∂. 2. A k-historical propagator from T to U is a function f : Prof(T )

/ Prof(U )

such that: (i) |f (t)| = |t| + k for all t ∈ Prof(T ); (ii) if t ∈ Prof(T ) has length |t| ≥ 1, then ∂U f (t) = f (∂T t).

(6.25)

The condition (6.25) is called historicity. 3. The set of k-historical propagators from T to U is denoted by Histk (T , U ). 4. A historical propagator from T to U is an m-historical propagator from T to U for some m ≥ 0.

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6 Finite Presentation for Algebras over Wiring Diagrams

Example 6.13. Given a pointed set T and an integer k ≥ 0, the function Dk : / Prof(T ) defined as Prof(T ) Dk (t1 , . . . , tn ) = (∗, . . . , ∗, t1 , . . . , tn ), in which the right-hand side starts with k entries of the base point ∗, is a k-historical propagator, called the k-moment delay function in [42]. Before we can define the propagator algebra, we first need to define its entries. Definition 6.14. Suppose X = (Xin , Xout ) ∈ BoxS (Definition 2.19). 1. Define the pointed sets Xvin =



v(x)

and

Xvout =



v(x)

(6.26)

x∈X out

x∈X in

in which each v(x), a pointed set, is the value of x (Definition 2.18) and an empty product means the one-point set. 2. Define the set   PX = Hist1 Xvin , Xvout

(6.27)

of 1-historical propagators of type X. So a 1-historical propagator of type X is a function that takes each Xvin profile to an Xvout -profile whose length is one higher than before and that satisfies historicity (6.25). Example 6.15. Suppose (N, 1) is the pointed set of non-negative integers with base point 1. Consider the box X with Xin and Xout both equal to the one-point set ∗ with value v(∗) = (N, 1).

A 1-historical propagator of type X is a function that takes each finite sequence of non-negative integers to a sequence of non-negative integers whose length is one higher than before and that satisfies historicity. For example: 1. The 1-moment delay function in Example 6.13, given by D1 (m1 , . . . , mn ) = (1, m1 , . . . , mn ) for mi ∈ N, is a 1-historical propagator of type X. For instance, we have D1 (1, 5, 6) = (1, 1, 5, 6).

6.3 Finite Presentation for the Propagator Algebra

2. The function f : Prof(N)

123

/ Prof(N) defined as 

f (m1 , . . . , mn ) = 0, m1 , m1 + m2 , . . . ,

n 

mi

i=1

is a 1-historical propagator of type X, denoted “Σ” in [42]. This 1-historical propagator takes a sequence of non-negative integers to the sequence whose ith entry is the sum of the first i − 1 entries of the given sequence. For instance, we have f (1, 5, 6) = (0, 1, 6, 12). / Prof(N) defined as 3. The function g : Prof(N)  g(m1 , . . . , mn ) = 1, m1 , m1 m2 , . . . ,

n 

mi

i=1

is a 1-historical propagator of type X. This 1-historical propagator takes a sequence of non-negative integers to the sequence whose ith entry is the product of the first i − 1 entries of the given sequence. For instance, we have g(1, 5, 6) = (1, 1, 5, 30). Example 6.16. Consider the box Y with Y in = {y1 , y2 }, Y out = {y}, and values v(y1 ) = v(y2 ) = v(y) = (N, 1).

A 1-historical propagator of type Y is a function that takes each finite sequence of ordered pairs of non-negative integers to a sequence of non-negative integers whose length is one higher than before and that satisfies historicity. For example: 1. The function h : Prof(N × N)

/ Prof(N) given by

    h (m1 , m1 ), . . . , (mn , mn ) = 1, m1 + m1 , . . . , mn + mn isa 1-historical propagator of type Y , denoted “+” in [42]. For instance, we have  h (1, 4), (5, 2), (6, 8) = (1, 5, 7, 14). / Prof(N) given by 2. The function j : Prof(N × N)     j (m1 , m1 ), . . . , (mn , mn ) = 1, m1 m1 , . . . , mn mn is a 1-historical propagator of type Y . For instance, we have   j (1, 4), (5, 2), (6, 8) = (1, 4, 10, 48).

124

6 Finite Presentation for Algebras over Wiring Diagrams

Example 6.17. Consider the box Z with Z in = {z1 , z2 , z3 }, Z out = {z1 , z2 }, and all v(−) = (N, 1).

A 1-historical propagator of type Z is a function that takes each finite sequence of ordered triples of non-negative integers to a sequence of ordered pairs of nonnegative integers whose length is one higher than before and that satisfies historicity. For example, the function

given by    (m1 , m1 , m1 ), . . . , (mn , mn , mn )   = (1, 1), (m1 , m1 + m1 ), . . . , (mn , mn + mn ) is a 1-historical propagator of type Z. For instance, we have      (3, 1, 4), (7, 2, 9), (8, 5, 10) = (1, 1), (3, 5), (7, 11), (8, 15) . We will come back to this example several times below. The generating structure map of the propagator algebra associated to a 1-loop requires a few notations in its definition. So here we define this map first. The reader should keep in mind that the following definition as well as all the proofs in this section involve simple inductions on the length of some profiles. Definition 6.18. Suppose X ∈ BoxS , x− ∈ Xin , and x+ ∈ Xout such that v(x− ) = v(x+ ) as pointed sets. The box  X \ x ∈ BoxS is obtained from X by removing x = {x± }. For t ∈ Prof Xvout , we will write:   (i) t x+ ∈ Prof v(x+ ) for the profile obtained from t by taking only the v(x+ )entry;   (ii) t \x+ ∈ Prof (X \ x)out for the profile obtained from t by removing the v(x+ )v entry. Suppose g ∈ PX (6.27). Define two functions (6.28)

6.3 Finite Presentation for the Propagator Algebra

125

and (6.29) with the properties |(λg)(?)| = |?| + 1 = |Gg (?)|

(6.30)

inductively as follows. (i) For the empty profile, define   (λg)(∅) = g(∅)\x+ ∈ Prof (X \ x)out v   Gg (∅) = g(∅)x+ ∈ Prof v(x+ ) .

(6.31)

In each definition in (6.31), the first ∅ is the empty (X \ x)in v -profile, and the in -profile. The profile g(∅) has second ∅, to which g applies, is the empty X v  length 1 because g ∈ Hist1 Xvin , Xvout . So both (λg)(∅) and Gg (∅) have length 1.   (ii) Inductively, suppose w ∈ Prof (X \ x)in v has length n ≥ 1. Define     (λg)(w) = g w, Gg (∂w) \x+ ∈ Prof (X \ x)out v     Gg (w) = g w, Gg (∂w) x+ ∈ Prof v(x+ ) .

(6.32)

Here ∂ is the truncation (6.24), so the profile     Gg (∂w) ∈ Prof v(x+ ) = Prof v(x− ) is already defined and has length n by the induction hypothesis. In each definition in (6.32), 

   w, Gg (∂w) ∈ Prof Xvin

has length n, so its image under g has length n + 1. Therefore, both (λg)(w) and Gg (w) have length n + 1. We say that λg and Gg are defined with respect to x = {x± }. Example 6.19. This is a continuation of Example 6.17, where the box Z has Z in = {z1 , z2 , z3 }, Z out = {z1 , z2 }, and all v(−) = (N, 1). For z1 ∈ Z in and z1 ∈ Z out ,

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6 Finite Presentation for Algebras over Wiring Diagrams

suppose Z \ z is the box obtained from Z by removing z = {z1 , z1 }. So we have (Z \ z)in v = v(z2 ) × v(z3 ) = N × N; 2 (Z \ z)out v = v(z ) = N.

For the 1-historical propagator  of type Z defined as    (m1 , m1 , m1 ), . . . , (mn , mn , mn )   = (1, 1), (m1 , m1 + m1 ), . . . , (mn , mn + mn ) , the functions

in (6.28) and (6.29) are given as follows. Suppose   m = (m1 , m1 ), . . . , (mn , mn ) ∈ Prof(N × N) is an (N × N)-profile of length n ≥ 0. Then a simple induction shows that   (λ)(m) = 1, m1 + m1 , . . . , mn + mn , G (m) = (1, 1, . . . , 1), in which on the right of G (m) there are n + 1 copies of 1. In particular, λ = h, the 1-historical propagator of type Y in Example 6.16. In this example, both λ and G are 1-historical propagators. This is not an accident, as we show in the next result. The following observation will use Definition 6.12 of historical propagators. Lemma 6.20. In the context of Definition 6.18 with g ∈ PX , the following statements hold.   1. Gg ∈ Hist1 (X \ x)in , v(x+ ) . v   out = P 2. λg ∈ Hist1 (X \ x)in X\x . v , (X \ x)v

6.3 Finite Presentation for the Propagator Algebra

127

Proof. In this proof, we will abbreviate Gg to G. For statement (1), we are trying to show that G is a 1-historical propagator from (X \ x)in v to v(x+ ). In view of the property (6.30), it remains to check historicity (6.25) for G, which we will do by  has length ≥ 1. induction. Suppose w ∈ Prof (X \ x)in v If |w| = 1, then ∂w = ∅. Using the definitions (6.31) and (6.32) we have:   ∂G(w) = ∂g w, G(∅) x+    = g ∂ w, g(∅)x+ x+

by historicity of g

= g(∅)x+ = G(∅). Inductively, suppose |w| ≥ 2. Using the definition (6.32), we have:   ∂G(w) = ∂g w, G(∂w) x+   = g ∂w, ∂G(∂w) x+   = g ∂w, G(∂∂w) x+

by historicity of g by the induction hypothesis on G

= G(∂w). This finishes the proof of statement (1). Statement (2) is proved by essentially the same argument as above, except that, in view of the definitions (6.31) and (6.32), the various rightmost subscripts x+ are replaced by \x+ .   We are now ready to define the propagator algebra in terms of finitely many generating structure maps and generating axioms as in Definition 6.9. Most of the generating structure maps below are easily seen to be well-defined. The only exception is the generating structure map associated to a 1-loop, which we dealt with in Lemma 6.20 above. Definition 6.21. Define the propagator algebra P as the WD-algebra, in the sense of Definition 6.9, with X-colored entry   PX = Hist1 Xvin , Xvout as in (6.27) for each X ∈ BoxS . Its 8 generating structure maps are defined as follows. 1. Corresponding to the empty wiring diagram  ∈ WD structure map

∅

(Definition 3.1), the

(6.33)

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6 Finite Presentation for Algebras over Wiring Diagrams

sends ∗ to the unique function     (∗) ∗, . . . , ∗ = ∗, . . . , ∗ .   m

m+1

2. Corresponding to each 1-delay node δd ∈ WD pointed set, the structure map

d 

(Definition 3.2) with d a

(6.34) sends ∗ to the function   (δd ∗)(t) = ∗, t for each t ∈ Prof(d). Here the ∗ on the right is the base point in d. In other words, δd ∗ is the 1-moment delay function in Example 6.13. Y 3. Corresponding to each name change τX,Y ∈ WD X (Definition 3.3), the structure map (6.35) is the identity map. Here we are using the fact that, if x ∈ Xin  Xout and y ∈ Y in  Y out corresponds to x under τX,Y, then v(x) = v(y) as pointed sets. XY  4. Corresponding to each 2-cell θX,Y ∈ WD X,Y (Definition 3.4), the structure map

(6.36) is given by θX,Y (fX , fY ) = fX × fY     for fX ∈ Hist1 Xvin , Xvout and fY ∈ Hist1 Yvin , Yvout . X\x  5. Corresponding to each 1-loop λX,x ∈ WD X (Definition 3.5), the structure map (6.37) sends each g ∈ PX to λg ∈ PX\x (6.28), which is well-defined by Lemma 6.20.

6.3 Finite Presentation for the Propagator Algebra

6. Corresponding to each in-split σX,x1 ,x2 ∈ WD map

129 Y  X

(Definition 3.6), the structure

(6.38) is given by 

 σX,x1 ,x2 g (y) = g(πy)

for g ∈ PX and y ∈ Prof(Yvin ). Here πy ∈ Prof(Xvin ) is the same as y except that its v(x1 )-entry and v(x2 )-entry are both given by the v(x12 )-entry of y. Y  7. Corresponding to each out-split σ Y,y1 ,y2 ∈ WD X (Definition 3.7), the structure map (6.39) is given by   σ Y,y1 ,y2 g (y) = πg(y) for g ∈ PX and y ∈ Prof(Yvin ) = Prof(Xvin ). Here πg(y) ∈ Prof(Yvout ) is the same as g(y) ∈ Prof(Xvout ) except that its v(y1 )-entry and v(y2 )-entry are both given by the v(y12 )-entry of g(y). Y  8. Corresponding to each 1-wasted wire ωY,y ∈ WD X (Definition 3.8), the structure map (6.40) is given by 

   ωY,y g (t) = g t \y

for g ∈ PX and t ∈ Prof(Yvin ). Here t \y ∈ Prof(Xvin ) is obtained from t by removing the v(y)-entry. This finishes the definition of the propagator algebra P. The following four examples continue Examples 6.17 and 6.19, where Z is the box with Z in = {z1 , z2 , z3 }, Z out = {z1 , z2 }, and all v(−) = (N, 1). The 1-historical

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6 Finite Presentation for Algebras over Wiring Diagrams

propagator  ∈ PZ = Hist1 (N3 , N2 ) is defined as    (m1 , m1 , m1 ), . . . , (mn , mn , mn )   = (1, 1), (m1 , m1 + m1 ), . . . , (mn , mn + mn ) . Let us consider the image of  under some of the structure maps of P. Example 6.22. Suppose Y is the box obtained from Z by removing z = {z1 , z1 }. Consider the 1-loop (Definition 3.5)

in WD

Y  Z

, the structure map

  in (6.37), and m = (m1 , m1 ), . . . , (mn , mn ) ∈ Prof(Yvin ) = Prof(N2 ). As observed in Example 6.19 we have   (λZ,z )(m) = h(m) = 1, m1 + m1 , . . . , mn + mn in Prof(Yvout ) = Prof(N), where h ∈ PY is the 1-historical propagator in Example 6.16. For instance, we have   (λZ,z ) (2, 5), (4, 9), (3, 7) = (1, 7, 13, 10). Example 6.23. Suppose W is the box with W in = Z in /(z1 = z2 ) = {w, z3 }, and W out = Z out . For the in-split (Definition 3.6)

in WD

W  Z

, the structure map

6.3 Finite Presentation for the Propagator Algebra

131

in (6.38) propagator  ∈ PZ is given as follows. For  applied to the 1-historical  m = (m1 , m1 ), . . . , (mn , mn ) ∈ Prof(Wvin ) = Prof(N2 ), we have   σZ,z1 ,z2  (m) = (πm)   =  (m1 , m1 , m1 ), . . . , (mn , mn , mn )   = (1, 1), (m1 , m1 + m1 ), . . . , (mn , mn + mn ) in Prof(Wvout ) = Prof(N2 ). For instance, we have      σZ,z1 ,z2  (2, 5), (4, 9), (3, 7) = (1, 1), (2, 7), (4, 13), (3, 10) . Example 6.24. Suppose V is a box with V out = {v, v  , z2 } such that V out /(v = v  ) = Z out , and V in = Z in . For the out-split (Definition 3.7)

in WD

V  Z

, the structure map

in (6.39)  ∈ PZ is given as follows. For  applied to the 1-historical propagator  m = (m1 , m1 , m1 ), . . . , (mn , mn , mn ) ∈ Prof(Vvin ) = Prof(N3 ), we have  V ,v,v   σ  (m) = π(m)   = π (1, 1), (m1 , m1 + m1 ), . . . , (mn , mn + mn )   = (1, 1, 1), (m1 , m1 , m1 + m1 ), . . . , (mn , mn , mn + mn ) in Prof(Vvout ) = Prof(N3 ). For instance, we have 

   σ V ,v,v  (2, 5, 1), (4, 9, 10), (3, 7, 6)   = (1, 1, 1), (2, 2, 6), (4, 4, 19), (3, 3, 13) .

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6 Finite Presentation for Algebras over Wiring Diagrams

Example 6.25. Suppose U is a box such that U \ u = Z for some u ∈ U in with v(u) = (N, 1). For the 1-wasted wire (Definition 3.8)

in WD

U  Z

, the structure map

in (6.40) applied to  ∈ PZ is given as follows. For ! "n m = (m1i , m2i , m3i , m4i )

i=1

∈

Prof(Uvin )

  = Prof v(u) × v(z1 ) × v(z2 ) × v(z3 ) = Prof(N4 ),

we have 

 !  "n  ωU,u  (m) =  m\u =  (m2i , m3i , m4i ) =



i=1

(1, 1), (m21 , m31

+ m41 ), . . . , (m2n , m3n

+ m4n )



in Prof(Uvout ) = Prof(N2 ). For instance, we have      ωU,u  (2, 5, 1, 7), (4, 9, 10, 2), (3, 7, 6, 5) = (1, 1), (5, 8), (9, 12), (7, 11) . The following observation is the finite presentation theorem for the propagator algebra. Theorem 6.26. The propagator algebra in Definition 6.21 is actually a WDalgebra in the sense of Definition 6.9, hence also in the sense of Definition 6.3 by Theorem 6.10. Proof. We need to check the 28 generating axioms in Definition 6.9. The 8 generating structure maps are all rather simple functions except for λX,x (6.37). The only generating axioms that are not obvious are the ones that involve a composition of two such generating structure maps, namely (6.21) and (6.22). These two generating axioms are verified in Lemmas 6.30 and 6.32 below.   In preparation for Lemma 6.30, we will need a few definitions and notations. Recall that the generating axiom (6.21) is really the WD-algebra manifestation of Proposition 3.28. The next definition is essentially the double-loop version of Definition 6.18.

6.3 Finite Presentation for the Propagator Algebra

133

Definition 6.27. Suppose: 1 = x 2 ∈ X in , and x 1 = x 2 ∈ X out such that v(x i ) = v(x i ) as • X ∈ BoxS , x− + − − + + pointed sets for each i ∈ {1, 2}. 1 }, • X \ x 1 , X \ x 2 , and X \ x ∈ BoxS are obtained from X by removing x 1 = {x± 2 }, and x = {x 1 , x 2 }, respectively. x 2 = {x± ± ±  out  Suppose t ∈ Prof Xv . 1 ) × v(x 2 ) and v(x ) = v(x 1 ) × v(x 2 ). (i) Write v(x+ ) = v(x+ − − −  + (ii) Write t x+ ∈ Prof v(x+ ) for the profile obtained from t by taking only the v(x+ )-entries.  i  (iii) For i ∈ {1, 2}, write t x i ∈ Prof v(x+ ) for the profile obtained from t by +

i )-entry. taking only the v(x+ (iv) The profile zx i is also defined as long as +

 z ∈ Prof



v(u)

u∈T 1 , x 2 } ⊆ T ⊆ X out . for some subset {x+  + out  (v) Write t \x+ ∈ Prof (X \ x)v for the profile obtained from t by removing the v(x+ )-entries.   for the profile obtained from t (vi) For i ∈ {1, 2}, write t \x i ∈ Prof (X \ x i )out v +

i )-entry. by removing the v(x+

Suppose g ∈ PX . Define two functions (6.41) and (6.42) with the properties |(λ2 g)(?)| = |?| + 1 = |G2g (?)|

(6.43)

inductively as follows. (i) For the empty profile, define   (λ2 g)(∅) = g(∅)\x+ ∈ Prof (X \ x)out v   G2g (∅) = g(∅)x+ ∈ Prof v(x+ ) .

(6.44)

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6 Finite Presentation for Algebras over Wiring Diagrams

In each definition in (6.44), the first ∅ is the empty (X \ x)in v -profile, and the in -profile. The profile g(∅) has second ∅, to which g applies, is the empty X v   length 1 because g ∈ Hist1 Xvin , Xvout . So both (λ2 g)(∅) and G2g (∅) have length 1.   (ii) Inductively, suppose w ∈ Prof (X \ x)in v has length n ≥ 1. Define     (λ2 g)(w) = g w, G2g (∂w) \x+ ∈ Prof (X \ x)out v     G2g (w) = g w, G2g (∂w) x+ ∈ Prof v(x+ ) .

(6.45)

Here ∂ is the truncation (6.24), so the profile     G2g (∂w) ∈ Prof v(x+ ) = Prof v(x− ) is already defined and has length n by the induction hypothesis. In each definition in (6.45), 

   w, G2g (∂w) ∈ Prof Xvin

has length n, so its image under g has length n + 1. Therefore, both (λ2 g)(w) and G2g (w) have length n + 1. Example 6.28. This is a continuation of Examples 6.17 and 6.19, where Z is the box with Z in = {z1 , z2 , z3 }, Z out = {z1 , z2 }, and all v(−) = (N, 1). The 1-historical propagator  ∈ PZ = Hist1 (N3 , N2 ) is defined as    (m1 , m1 , m1 ), . . . , (mn , mn , mn )   = (1, 1), (m1 , m1 + m1 ), . . . , (mn , mn + mn ) . With w1 = {z1 , z1 } and w2 = {z2 , z2 }, suppose Z \ w is the box obtained from Z by removing {z1 , z2 , z1 , z2 }. Then (Z \ w)in v = v(z3 ) = N

and

(Z \ w)out v = ∗,

where ∗ here is the one-point set (= empty product).

6.3 Finite Presentation for the Propagator Algebra

135

The functions

in (6.41) and (6.42) are given as follows. For m = (m1 , . . . , mn ) ∈ Prof(N), a simple induction shows that (λ2 )(m) = (∗, . . . , ∗),   (G2 )(m) = (1, 1), (1, 1 + m1 ), (1, 1 + m1 + m2 ), . . . , (1, 1 + m1 + · · · + mn ) , where on the right of (λ2 )(m) there are n + 1 copies of ∗. For instance, we have   (G2 )(6, 3, 2, 9) = (1, 1), (1, 7), (1, 10), (1, 12), (1, 21) . The generating axiom (6.21) for the propagator algebra P claims that the diagram

(6.46) is commutative. We will consider the top-right composition, so let us use the abbreviations λ2 = λX,x 2

and

λ1 = λX\x 2 ,x 1 .

(6.47)

For the proof of Lemma 6.30, we will need the following observation. It provides an explicit formula for the function G2g (6.42) in terms of Gg (defined with respect to x 2 ) and Gλ2 g (6.29) (defined with respect to x 1 ) for each g ∈ PX . Lemma 6.29. In the context of Definition 6.27, suppose g ∈ PX and w ∈ Prof   (X \ x)in with length at least 1. Then the following equalities hold. v  1  G2g (∂w)x 1 = Gλ2 g (∂w) ∈ Prof v(x+ ) , +    2  G2g (∂w)x 2 = Gg ∂w, ∂Gλ2 g (∂w) ∈ Prof v(x+ ). +

In the above equalities: 1. ∂ is the truncation (6.24). 2. λ2 g ∈ PX\x 2 by Lemma 6.20(2).

(6.48)

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6 Finite Presentation for Algebras over Wiring Diagrams

3. The function

1 , x 1 } (6.29). is defined with respect to x 1 = {x+ − 4. The function

2 , x 2 }. is defined with respect to x 2 = {x+ −

Proof. The proof of (6.48) is by induction on |w| ≥ 1. If |w| = 1, then ∂w = ∅. So by (6.31) and (6.44) we have   Gλ2 g (∅) = (λ2 g)(∅)x 1 = g(∅)\x 2 x 1 = g(∅)x 1 = G2g (∅)x 1 . +

+

+

+

+

Likewise, we have Gg (∅) = g(∅)x 2 = G2g (∅)x 2 . +

+

This proves the initial case |w| = 1. For the induction step, suppose |w| ≥ 2. For the first equality in (6.48) we have:   Gλ2 g (∂w) = (λ2 g) ∂w, Gλ2 g (∂ 2 w)

1 x+

by (6.32)

   = g ∂w, Gλ2 g (∂ 2 w), Gg ∂ 2 w, ∂Gλ2 g (∂ 2 w)   = g ∂w, G2g (∂ 2 w)x 1 , G2g (∂ 2 w)x 2 +

= G2g (∂w)x 1

+

+

1 x+

by (6.32)

by induction hypothesis

1 x+

by (6.45).

In the second equality above, we used the fact that ! " g(· · · )\x 2 +

1 x+

= g(· · · )x 1 . +

For the second equality in (6.48) we have:   Gg ∂w, ∂Gλ2 g (∂w)   = Gg ∂w, Gλ2 g (∂ 2 w) by Lemma 6.20(1)    = g ∂w, Gλ2 g (∂ 2 w), Gg ∂ 2 w, ∂Gλ2 g (∂ 2 w)

2 x+

by (6.32)

6.3 Finite Presentation for the Propagator Algebra

137

  = g ∂w, G2g (∂ 2 w)x 1 , G2g (∂ 2 w)x 2 +

= G2g (∂w)x 2

+

+

2 x+

by induction hypothesis

by (6.45).  

This finishes the induction.

Lemma 6.30. The propagator algebra P in Definition 6.21 satisfies the generating axiom (6.21); i.e., the diagram (6.46) is commutative. 1} Proof. We will use the abbreviations (6.47). By the symmetry between x 1 = {x± 2 2 and x = {x± }, it suffices to show that



 λ1 λ2 g (w) = (λ2 g)(w)

(6.49)

  2 for g ∈ PX and w ∈ Prof (X\x)in v , where λ g is defined in (6.41). We prove (6.49) by induction on the length |w|. If |w| = 0, then by (6.31) and (6.44) the left-hand side of (6.49) is: 

  λ2 g)(∅)\x 1 = g(∅)\x 2 +

+

1 \x+

= g(∅)\x+ = (λ2 g)(∅).

For the induction step, suppose |w| ≥ 1. Then the left-hand side of (6.49) is:   (λ2 g) w, Gλ2 g (∂w) \x 1 by (6.32) +    = g w, Gλ2 g (∂w), Gg ∂w, ∂Gλ2 g (∂w)

\x+

  = g w, G2g (∂w)x 1 , G2g (∂w)x 2 +

= (λ2 g)(w)

+

\x+

by (6.32)

by (6.48)

by (6.45).  

This finishes the induction.

The proof of the generating axiom (6.22) in Lemma 6.32 below will use the following observation. Recall that the generating axiom (6.22) is really a WDalgebra manifestation of the generating relation (3.21). Lemma 6.31. In the context of Proposition 3.32, recall that X=

Y , (x 1 = x 2 )

X =

X , (x1 = x2 )

and

X∗ = X \ {x 12, x1 , x2 }.

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6 Finite Presentation for Algebras over Wiring Diagrams

Consider the maps:

  Then for g ∈ PX and w ∈ Prof Xv∗in with length ≥ 1, the equality   G2σ • g (∂w) = Gσ• g (∂w), Gσ• g (∂w)

(6.50)

holds. Here: 1. σ • g ∈ PY and σ• g ∈ PX . 2. The function

is defined as in (6.42), starting with the box Y and the wires x 1 = x 2 ∈ Y out and x1 = x2 ∈ Y in . 3. The function

is defined as in (6.29), starting with the box X and the wires x12 ∈ Xin and x 12 ∈ Xout . Proof. The proof is by induction on the length of w. If |w| = 1, then ∂w = ∅. So we have: G2σ • g (∅) = (σ • g)(∅){x 1 ,x 2 } by (6.44)   by (6.39) = g(∅)x 12 , g(∅)x 12   = (σ• g)(∅)x 12 , (σ• g)(∅)x 12 by (6.38)   by (6.31). = Gσ• g (∅), Gσ• g (∅) For the induction step, suppose |w| ≥ 2. Then we have:   G2σ • g (∂w) = (σ • g) ∂w, G2σ • g (∂ 2 w)

{x 1 ,x 2 }

by (6.45)

  = (σ • g) ∂w, Gσ• g (∂ 2 w), Gσ• g (∂ 2 w)

{x 1 ,x 2 }

by ind.hypothesis

6.3 Finite Presentation for the Propagator Algebra

139

    = g ∂w, Gσ• g (∂ 2 w), Gσ• g (∂ 2 w) x 12 , same by (6.39)     by (6.38) = (σ• g) ∂w, Gσ• g (∂ 2 w) x 12 , same   = Gσ• g (∂w), Gσ• g (∂w) by (6.32).  

This finishes the induction.

Lemma 6.32. The propagator algebra P in Definition 6.21 satisfies the generating axiom (6.22); i.e., the diagram

is commutative.

  Proof. For g ∈ PX and w ∈ Prof Xv∗in , we will prove the desired equality     (λσ• g)(w) = λ(2) λ(1) σ • g (w) ∈ Prof Xv∗out

(6.51)

by induction on the length of w. If |w| = 0, then both sides of (6.51) are equal to g(∅)\x 12 . For the induction step, suppose |w| ≥ 1. Then we have:   (λσ• g)(w) = (σ• g) w, Gσ• g (∂w)

\x 12

by (6.32)

  = g w, Gσ• g (∂w), Gσ• g (∂w)

\x 12

  = g w, G2σ • g (∂w)

\x 12

by (6.50)

  = (σ • g) w, G2σ • g (∂w)   = λ(2) λ(1) σ • g (w) This finishes the induction.

by (6.38)

\{x 1 ,x 2 }

by (6.39)

by (6.45) and (6.49).  

Remark 6.33. To see that our definition of the propagator algebra P in Definition 6.21 agrees with the one in [42, Section 3], recall that our version of the propagator algebra is based on Definition 6.9. On the other hand, the propagator algebra in [42] is based on Definition 6.2, which is equivalent to Definition 6.3. A direct inspection of [42, Announcement 3.3.3 and Eq. (17)] reveals that the structure

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6 Finite Presentation for Algebras over Wiring Diagrams

map of P, when applied to the generating wiring diagrams (Sect. 3.1), reduces to our 8 generating structure maps in Definition 6.21. Theorem 6.10 then guarantees that the two definitions are equivalent.

6.4 Algebras over the Operad of Normal Wiring Diagrams The purpose of this section is to provide a finite presentation for algebras over the BoxS -colored operad WD• of normal wiring diagrams (Proposition 5.27). We begin by defining these algebras in terms of finitely many generators and relations. Recall from Definition 5.28 that a normal generating wiring diagram is a generating wiring diagram that is not a 1-delay node δd . Definition 6.34. A WD• -algebra A consists of the following data. 1. For each X ∈ BoxS , A is equipped with a class AX called the X-colored entry of A. 2. It is equipped with the seven generating structure maps in Definition 6.9 corresponding to the normal generating wiring diagrams. This data is required to satisfy the same 28 generating axioms in Definition 6.9. The next observation is the WD• version of Theorem 6.10. It guarantees that the two existing definitions of a WD• -algebra are equivalent. The first one (Definition 6.3) is in terms of a general structure map satisfying an associativity axiom for a general operadic composition. The other one (Definition 6.34) is in terms of 7 generating structure maps and 28 generating axioms regarding the normal generating wiring diagram. Therefore, algebras over WD• have a finite presentation. Theorem 6.35. For the operad WD• of normal wiring diagrams (Proposition 5.27), Definition 6.3 with O = WD• and Definition 6.34 of a WD• -algebra are equivalent. Proof. Simply restrict the proof of Theorem 6.10 to normal (generating) wiring diagrams. Instead of Theorem 5.11, here we use Theorem 5.29 for the existence of a presentation involving only normal generating wiring diagrams.   Remark 6.36. In [45, Definitions 4.1–4.4] several closely related WD• -algebras were defined, although they appeared in the language of symmetric monoidal categories. By Theorem 6.35 each of these WD• -algebras has a finite presentation with 7 generating structure maps and 28 generating axioms as in Definition 6.34. In Sect. 6.5 we will discuss one of these WD• -algebras and its finite presentation. In Sect. 6.7 we will discuss a similar algebra of open dynamical systems over the operad WD0 of strict wiring diagrams. Essentially the same formalism applies to the other WD• -algebras in [45].

6.5 Finite Presentation for the Algebra of Discrete Systems

141

6.5 Finite Presentation for the Algebra of Discrete Systems The purpose of this section is to provide a finite presentation for the algebra of discrete systems introduced in [45, Definition 4.9]. Let us first recall some definitions from [45, Sections 2.1 and 4.1]. Assumption 6.37. Throughout this section, S denotes the class of sets. So BoxS = BoxSet , and WD• is the BoxSet -colored operad of normal wiring diagrams (Proposition 5.27). Definition 6.38. Suppose A and B are sets. An (A, B)-discrete system is a triple (T , f rd , f up ) consisting of: 1. a set T , called the state set; / B, called the readout function; 2. a function f rd : T up / T , called the update function. 3. a function f : A × T Definition 6.39. Suppose X = (Xin , Xout ) ∈ BoxS is a box. An X-discrete system is an (Xvin , Xvout )-discrete system, where Xvin =



v(x)

and

x∈X in

Xvout =



v(x) ∈ Set

x∈X out

as in (6.26) (but with sets instead of pointed sets). In other words, an X-discrete system is a triple (T , f rd , f up ) such that T is a set and that

are functions. The collection of all X-discrete systems is denoted by DS(X). Example 6.40. If X = ∅ ∈ BoxS is the empty box, then Xvin = Xvout = ∗ by / ∗ gives no information, and ∗×T ∼ convention. A readout function f rd : T = T . So (6.52) In particular, the collection DS(∅) is not a set but a proper class. This example explains why in Definition 6.2 we defined an entry of an operad algebra to be a class and not a set. Example 6.41. Suppose X is the box

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6 Finite Presentation for Algebras over Wiring Diagrams

with Xin = {x1 , x2 }, Xout = {x 1 , x 2 }, and values v(x1 ) = {a1 , b1 }, v(x 1 ) = {a 1 , b 1 },

v(x2 ) = {a2 , b2 }, and

v(x 2 ) = {a 2, b2 }.

An X-discrete system is an (Xvin , Xvout )-discrete system, where Xvin = v(x1 ) × v(x2 ) = {a1 , b1 } × {a2 , b2 }; Xvout = v(x 1 ) × v(x 2 ) = {a 1 , b 1 } × {a 2, b2 }. Suppose T = {1, 2} is the state set. There is an X-discrete system (T , f rd , f up ) / Xout and update function f up : Xin × with the readout function f rd : T v v / T T defined as follows. f rd (1) = (a 1 , a 2 ) f rd (2) = (b1 , a 2 )

  f up (a1 , a2 ), 1 = 1   f up (a1 , b2 ), 1 = 2   f up (b1 , a2 ), 1 = 2   f up (b1 , b2 ), 1 = 1

  f up (a1 , a2 ), 2 = 1   f up (a1 , b2 ), 2 = 1   f up (b1 , a2 ), 2 = 2   f up (b1 , b2 ), 2 = 2

Visually it can also be represented by the transition diagram:

For example, the arrow labeled (b1 , a2) from the box for state 1 to the box for state  2 represents the value f up (b1 , a2 ), 1 = 2, and likewise for the other arrows. We now define the algebra of discrete systems in terms of seven very simple generating structure maps. Definition 6.42. The algebra of discrete systems is the WD• -algebra DS in the sense of Definition 6.34 defined as follows. For each X ∈ BoxS , the X-colored entry is the class DS(X) of X-discrete systems in Definition 6.39. The seven generating structure maps—as in Definition 6.9 but without δd —are defined as follows.

6.5 Finite Presentation for the Algebra of Discrete Systems

143

1. Corresponding to the empty wiring diagram  ∈ WD• chosen element in DS(∅) (6.52) is the pair (∗, Id) with:

∅

(Definition 3.1), the

• the one-point set ∗ as its state set; • the identity map as its update function. 2. Corresponding to each name change τX,Y ∈ WD• structure map

Y  X

(Definition 3.3), the

in is the identity map, using the fact that X Y in and Xvout = Yvout . v = XY  v 3. Corresponding to a 2-cell θX,Y ∈ WD• X,Y (Definition 3.4), it has the structure map

using the fact that in in (X  Y )in v = Xv × Yv

and

out out (X  Y )out v = Xv × Yv .

X\x 

4. Corresponding to a 1-loop λX,x ∈ WD• X (Definition 3.5) with x =   x− , x+ ∈ Xin × Xout (so v(x+ ) = v(x− )), it has the structure map

in which, for (y, t) ∈ (X \ x)in v ×T:   f rd (t) = f rd (t)\x+ , f rd (t)x+ ∈ Xvout = (X \ x)out v × v(x+ ); rd f\x (t) = f rd (t)\x+ ∈ (X \ x)out v ;      up  f\x y, t = f up y, f rd (t)x+ , t .

Y 

5. Corresponding to an in-split σX,x1 ,x2 ∈ WD• X (Definition 3.6) with v(x1 ) = v(x2 ) and Y = X/(x1 = x2 ), it has the structure map

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6 Finite Presentation for Algebras over Wiring Diagrams

in which the update function is      σ• f up y, t = f up σ• y, t for (y, t) ∈ Yvin ×T . Here σ• y ∈ Xvin is obtained from y by using the v(x12 )-entry of y in both the v(x1 )-entry and the v(x2 )-entry, where x12 ∈ Y in is the identified element of x1 and x2 . Y  6. Corresponding to an out-split σ Y,y1 ,y2 ∈ WD• X (Definition 3.7) with v(y1 ) = v(y2 ) and X = Y/(y1 = y2 ), it has the structure map

in which the readout function is    • rd  σ f (t) = σ • f rd (t) ∈ Yvout   for t ∈ T . Here σ • f rd (t) is obtained from f rd (t) ∈ Xvout by using its v(y12 )entry in both the v(y1 )-entry and the v(y2 )-entry, where y12 ∈ Xout is the identified element of y1 and y2 . Y  7. Corresponding to a 1-wasted wire ωY,y ∈ WD• X (Definition 3.8) with y ∈ Y in and X = Y \ y, it has the structure map

in which the update function is   up   ωf (z, t) = f up z\y , t for (z, t) ∈ Yvin × T . Here z\y ∈ Xvin is obtained from z by removing the v(y)entry. This finishes the definition of the WD• -algebra of discrete systems. Remark 6.43. In [45, Example 2.7] the image of θX,Y is called the parallel composition. The structure map λX,x corresponding to a 1-loop was discussed in [45, Example 2.9]. The structure maps σX,x1 ,x2 and σ Y,y1 ,y2 corresponding to an in-split and an out-split were discussed in [45, Example 2.8]. The following four examples refer to the X-discrete system (T , f rd , f up ) in Example 6.41, where Xin = {x1 , x2 }, Xout = {x 1 , x 2 }, v(xi ) = {ai , bi }, and v(x i ) = {a i , b i } for i = 1, 2. Let us consider the effects of some of the structure maps in Definition 6.42 on (T , f rd , f up ) ∈ DS(X).

6.5 Finite Presentation for the Algebra of Discrete Systems

145

Example 6.44. Suppose a1 = a 1 and b1 = b1 , so v(x1 ) = {a1 , b1 } = v(x 1 ). Suppose X \ x is the box obtained from X by removing x = {x1 , x 1 }, so (X \ x)in v = 2 ). Consider the 1-loop (Definition 3.5) v(x2 ) and (X \ x)out = v(x v

in WD•

X\x X

. Then up

rd λX,x (T , f rd , f up ) = (T , f\x , f\x ) ∈ DS(X \ x)

is the (X \ x)-discrete system with update and readout functions

Its transition diagram is:

For instance, we have     up f\x (a2 , 1) = f up (a2 , f rd (1)x 1 ), 1 = f up (a1 , a2 ), 1 = 1, which explains the loop at state 1 labeled a2 . Similar calculation yields the rest of the update function and the readout function. Example 6.45. Suppose a1 = a2 and b1 = b2 , so v(x1 ) = {a1 , b1 } = v(x2 ). Suppose Y is the box X/(x1 = x2 ), so Yvin = v(x1 ) and Yvout = Xvout . Consider the in-split (Definition 3.6)

146

in WD•

6 Finite Presentation for Algebras over Wiring Diagrams Y  X

. Then σX,x1 ,x2 (T , f rd , f up ) = (T , f rd , σ• f up ) ∈ DS(Y )

is the Y -discrete system with update and readout functions

Its transition diagram is:

For instance, we have   (σ• f up )(a1 , 2) = f up (a1 , a2 ), 2 = 1, which explains the arrow from state 2 to state 1 labeled a1 . Similar calculation yields the rest of the update function. Example 6.46. Suppose Z is a box with z = z in Z out such that v(z) = v(z ) = v(x 1 ) and that Z/(z = z ) = X. So Zvin = Xvin and Zvout = v(x 1 ) × v(x 1 ) × v(x 2 ). Consider the out-split (Definition 3.7)

in WD•

Z  X

. Then 

σ Z,z,z (T , f rd , f up ) = (T , σ • f rd , f up ) ∈ DS(Z) is the Z-discrete system with update and readout functions

6.5 Finite Presentation for the Algebra of Discrete Systems

147

Its transition diagram is:

This transition diagram is the same as that of (T , f rd , f up ), except for the values of the readout function at states 1 and 2. Example 6.47. Suppose W is a box such that W \ w = X for some w ∈ W in . So Wvin = v(w) × Xvin and Wvout = Xvout . Consider the 1-wasted wire (Definition 3.8)

in WD•

W  X

. Then ωW,w (T , f rd , f up ) = (T , f rd , ωf up ) ∈ DS(W )

is the W -discrete system with update and readout functions

Its transition diagram is:

Here each double arrow ⇒ represents the set of arrows as s runs through v(w). For instance, for each s ∈ v(w) we have     (ωf up ) (s, a1 , b2 ), 1 = f up (a1 , b2 ), 1 = 2,

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6 Finite Presentation for Algebras over Wiring Diagrams

which explains the double arrow from state 1 to state 2 labeled (s, a1 , b2 ). Similar calculation yields the rest of the update function. The following observation ensures that DS is a well-defined WD• -algebra, i.e., that it satisfies the generating axioms. Theorem 6.48. The algebra of discrete systems DS in Definition 6.42 is actually a WD• -algebra in the sense of Definition 6.34, hence also in the sense of Definition 6.3 by Theorem 6.35. Proof. We must check that DS satisfies the 28 generating axioms in Definition 6.9, which are all trivial to check. For example, the generating axiom (6.22) says that, in the setting of (3.21) with X∗ = X \ {x 12, x1 , x2 } and v(x 12 ) = v(x1 ) = v(x2 ), the diagram

is commutative. When applied to a typical element (T , f rd , f up ) ∈ DS(X), a simple direct inspection reveals that both compositions in the above diagram yield (T , g rd , g up ) ∈ DS(X∗ ), in which g rd (t) = f rd (t)\x 12 ;      g up y, t = f up y, f rd (t)x 12 , f rd (t)x 12 , t . Here for (y, t) ∈ Xv∗in × T , we have   f rd (t) = f rd (t)\x 12 , f rd (t)x 12 ∈ Xvout = Xv∗out × v(x 12 ); 

 y, f rd (t)x 12 , f rd (t)x 12 ∈ Xv∗in × v(x1 ) × v(x2 ) = Xvin .

The other generating axioms are checked similarly.

 

Remark 6.49. Our definition of the algebra of discrete systems DS actually agrees with the one in [45, Example 2.7 and Def. 4.9]. To see this, note that Spivak’s definition is essentially based on Definition 6.2, except that it is stated in terms of symmetric monoidal categories. Spivak’s structure map of DS, when applied to the seven normal generating wiring diagrams (Definition 5.28(1)), agrees with ours in Definition 6.42. So Theorems 6.35 and 6.48 imply that the two definitions of DS—namely, the one in [45] and our Definition 6.42—are equivalent.

6.7 Finite Presentation for the Algebra of Open Dynamical Systems

149

6.6 Algebras over the Operad of Strict Wiring Diagrams The purpose of this section is to provide a finite presentation for algebras over the BoxS -colored operad WD0 of strict wiring diagrams (Proposition 5.35). We begin by defining these algebras in terms of finitely many generators and relations. Recall from Definition 5.36) that: 1. The strict generating wiring diagrams are the empty wiring diagram , a name change τX,Y , a 2-cell θX,Y , and a 1-loop λX,x . 2. The strict elementary relations are the eight elementary relations that involve only strict generating wiring diagrams on both sides. Definition 6.50. A WD0 -algebra A consists of the following data. 1. For each X ∈ BoxS , A is equipped with a class AX called the X-colored entry of A. 2. It is equipped with the f our generating structure maps in Definition 6.9 corresponding to the strict generating wiring diagrams. This data is required to satisfy the eight generating axioms in Definition 6.9 corresponding to the strict elementary relations, namely, (6.14)–(6.21). The next observation is the WD0 version of Theorems 6.10 and 6.35. It gives a finite presentation for WD0 -algebras. Theorem 6.51. For the operad WD0 of strict wiring diagrams (Proposition 5.35), Definition 6.3 with O = WD0 and Definition 6.50 of a WD0 -algebra are equivalent. Proof. Simply restrict the proof of Theorem 6.10 to strict (generating) wiring diagrams. Instead of Theorem 5.11, here we use Theorem 5.37 for the existence of a presentation involving only strict generating wiring diagrams.  

6.7 Finite Presentation for the Algebra of Open Dynamical Systems The purpose of this section is to provide a finite presentation for the algebra of open dynamical systems introduced in [48]. In [48] the algebra of open dynamical systems G was defined and verified using essentially Definition 6.2 but in the form of symmetric monoidal categories and monoidal functors. Our definition of G in Definition 6.58 is based on Definition 6.50, which involves four relatively simple generating structure maps. Our verification that G is actually a WD0 -algebra in Theorem 6.60 boils down to verifying the generating axiom (6.21) for a doubleloop. This is a simple exercise involving the definition of the generating structure map corresponding to a 1-loop (6.60). The equivalence between the two definitions of the algebra of open dynamical systems is explained in Remark 6.61.

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6 Finite Presentation for Algebras over Wiring Diagrams

Let us first recall the setting of [48]. For the definitions of the basic objects in differential geometry that appear below, the reader may consult, for example, [17, Ch.1]. Assumption 6.52. Throughout this section: 1. S is a chosen set of representatives of isomorphism classes of second-countable smooth manifolds, henceforth called manifolds. 2. The operad of strict wiring diagrams WD0 (Proposition 5.35) is defined using this choice of S. 3. All the maps between manifolds are smooth maps. / M the projection map of the 4. For a manifold M, denote by π : T M tangent bundle. Definition 6.53. Suppose (M, v) ∈ FinS is an S-finite set (Definition 2.18). 1. Define Mv =



v(m) ∈ S.

(6.53)

m∈M

2. For a subset I ⊆ M and x = (xm )m∈M ∈ Mv , define  v(m) x I = (xm )m∈I ∈ Iv = m∈I

x \I = (xm )m∈M\I ∈ (M \ I )v =



(6.54) v(m).

m∈M\I

6.54. An open dynamical system, or ods for short, is a tuple Definition M, U in , U out , f consisting of: 1. manifolds M, U in , and U out ; 2. a pair of maps f = (f in , f out ),

such that the left diagram is commutative. Next is [48, Definition 4.2]. Definition 6.55. For each X = (Xin , Xout ) ∈ BoxS , define the class ! " GX = (M, f ) : M ∈ FinS , (Mv , Xvin , Xvout , f ) is an ods in which Mv , Xvin , and Xvout are as in (6.53).

(6.55)

6.7 Finite Presentation for the Algebra of Open Dynamical Systems

151

Example 6.56. For the empty box ∅ = (∅, ∅) ∈ BoxS and an S-finite set M, to say that (Mv , ∅v = {∗}, ∅v = {∗}, f ) is an open dynamical system means that f is a pair of maps f = (f in , f out ),

such that the left diagram is commutative. Since f out gives no information, f = f in is equivalent to a vector field on Mv . So ! " G∅ = (M, f ) : M ∈ FinS , f is a vector field on Mv .

(6.56)

Example 6.57. Suppose W is the box with W in = {w1 , w2 }, W out = {w1 , w2 }, and all v(−) = R, so Wvin = Wvout = R2 . Suppose M is the one-point set with value R. There is an element (M, f ) ∈ GW whose structure maps

are given by f in (x, y, z) = (x, ax + by + cz)

and

f out (x) = (dx, ex )

for any choice of fixed parameters a, b, c, d ∈ R. We now define the algebra of open dynamical systems in terms of 4 generating structure maps. Definition 6.58. The algebra of open dynamical systems is the WD0 -algebra G in the sense of Definition 6.50 defined as follows. For each box X ∈ BoxS , the Xcolored entry is GX in (6.55). The four generating structure maps (Definition 6.9) are defined as follows. 1. Corresponding to the empty wiring diagram  ∈ WD0 structure map

∅

(Definition 3.1), the

(6.57) sends ∗ to (∅, ∗) ∈ G∅ (6.56). Here ∅ ∈ FinS is the empty set, in which ∅v = {∗}, and in the second entry ∗ is the trivial vector field.

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6 Finite Presentation for Algebras over Wiring Diagrams

2. Corresponding to a name change τX,Y ∈ WD0 map

Y  X

(Definition 3.3), the structure

(6.58) in is the identity map, using the fact that X Y in and Xvout = Yvout . v = XY  v 3. Corresponding to a 2-cell θX,Y ∈ WD0 X,Y (Definition 3.4), it has the structure map

(6.59) 2.18). in which MX  MY is the coproduct in FinS (Definition X\x  4. Corresponding to a 1-loop λ ∈ WD (Definition 3.5) with x = X,x 0 X   x− , x+ ∈ Xin × Xout , it has the structure map (6.60)   in , f out are defined as The maps f\x = f\x \x      in f\x m, y = f in m, f out (m)x+ , y ∈ T Mv out f\x (m) = f out (m)\x+ ∈ (X \ x)out v out (m) ∈ X out , the elements for m ∈ Mv and y ∈ (X \ x)in v . Recalling that f v

f out (m)x+ ∈ v(x+ ) = v(x− )

and

f out (m)\x+ ∈ (X \ x)out v

are as in (6.54). This finishes the definition of the WD0 -algebra of open dynamical systems. Example 6.59. This is a continuation of Example 6.57, where W is the box with W in = {w1 , w2 } and W out = {w1 , w2 } and M is the one-point set, all with v(−) = R. Suppose W \ w is the box obtained from W by removing w = {w1 , w1 }, so out (W \ w)in v = (W \ w)v = R.

6.7 Finite Presentation for the Algebra of Open Dynamical Systems

153

Consider the 1-loop (Definition 3.5)

in WD0

W \w W

. Then λW,w (M, f ) = (M, f\w ) ∈ GW \w has structure maps

given by out f\w (x) = f out (x)\w1 = (dx, ex )\w1 = ex ;     in f\w (x, y) = f in x, (f out (x)w1 , y) = f in (x, dx, y) = x, (a + bd)x + cy .

The following observation ensures that G is a well-defined WD0 -algebra, i.e., that it satisfies the generating axioms. Theorem 6.60. The algebra of open dynamical systems G in Definition 6.58 is actually a WD0 -algebra in the sense of Definition 6.50, hence also in the sense of Definition 6.3 by Theorem 6.51. Proof. We must check the eight generating axioms corresponding to the strict elementary relations listed in Definition 6.50. All of them follow from a quick inspection of the definitions except for (6.21). This generating axiom says that, in the setting of the elementary relation (3.17) corresponding to a double-loop, the diagram

(6.61) is commutative.

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6 Finite Presentation for Algebras over Wiring Diagrams

To prove (6.61), suppose (M, f ) ∈ GX . First define the element (M, f\x ) ∈ in , f out ), GX\x with the maps f\x = (f\x \x

defined as follows. Given m ∈ Mv and 

y ∈ (X \ x)in v =

v(y)

1 ,x 2 } y∈X in \{x− −

we define

     in f\x m, y = f in m; f out (m){x 1 ,x 2 } , y ∈ T Mv +

+

out f\x (m) = f out (m)\{x 1 ,x 2 } ∈ (X \ x)out v . +

+

Recalling that f out (m) ∈ Xvout , the elements 1 2 1 2 f out (m){x 1 ,x 2 } ∈ v(x+ ) × v(x+ ) = v(x− ) × v(x− ) +

+

and f out (m)\{x 1 ,x 2 } are as in (6.54). + + Now it follows from a direct inspection using the definition (6.60) that both composites in (6.61), when applied to (M, f ), yields (M, f\x ) ∈ GX\x . This proves the generating axiom (6.61) for G.   Remark 6.61. Our definition of the algebra of open dynamical systems G actually agrees with the one in [48, Definitions 4.4 and 4.5]. To see this, note that among the four generating structure maps in Definition 6.58: •  (6.57), τX,Y (6.58), and λX,x (6.60) agree with [48, Definition 4.4]; • θX,Y (6.59) agrees with [48, Definition 4.5]. Theorem 6.51 then implies that the two definitions of G—namely, the one in [48] and our Definition 6.58—are equivalent.

6.8 Summary of this Chapter

155

6.8 Summary of this Chapter 1. For an S-colored operad O, an O-algebra A consists of a class Ac for each c ∈ S and a structure map



2. 3. 4. 5. 6. 7.



for each ζ ∈ O c1 ,...,cn that satisfies the associativity, unity, and equivariance axioms. Each WD-algebra can be described using eight generating structure maps that satisfy twenty-eight generating axioms. The propagator algebra is a WD-algebra. Each WD• -algebra can be described using seven generating structure maps that satisfy twenty-eight generating axioms. The algebra of discrete systems is a WD• -algebra. Each WD0 -algebra can be described using four generating structure maps that satisfy eight generating axioms. The algebra of open dynamical systems is a WD0 -algebra. d

Part II

Undirected Wiring Diagrams

The main purpose of this part is to describe the combinatorial structure of the operad UWD of undirected wiring diagrams. The main result is a finite presentation theorem that describes the operad UWD in terms of six operadic generators and 17 generating relations. The operad UWD of undirected wiring diagrams is recalled in Chap. 7. Operadic generators and generating relations for the operad UWD are presented in Chap. 8. Various decompositions of undirected wiring diagrams are given in Chap. 9. Using the results in Chaps. 8 and 9, the finite presentation theorem for the operad UWD is proved in Chap. 10. In Chap. 11 we prove the corresponding finite presentation theorem for UWD-algebras and discuss the main example of the relational algebra. This finite presentation theorem for algebras describes each UWD-algebra in terms of finitely many generating structure maps and relations among these maps. Also given in this chapter is a partial verification of a conjecture of Spivak about the rigidity of the relational algebra. Reading Guide The reader who already knows about pushouts of finite sets may skip Sect. 7.2. In Sect. 7.3, where we define the operad structure on undirected wiring diagrams, the reader may wish to skip the proofs of Lemmas 7.21 and 7.23 and just study the accompanying pictures. Section 8.3 is not technically needed in later sections. However, it contains several illuminating examples showing how wasted cables can be created from undirected wiring diagrams without wasted cables. So we urge the reader not to skip these examples. The decompositions in Chap. 9 are illustrated with a detailed example in Sect. 9.1. The reader may read that section and skip the rest of the chapter during the first reading. In Sect. 10.2, after the initial definitions and examples, the reader may skip the proofs of Lemmas 10.17 and 10.18 and go straight to Theorem 10.19, the finite presentation theorem for undirected wiring diagrams.

Chapter 7

Undirected Wiring Diagrams

The purposes of this chapter are 1. to recall the definition of an undirected wiring diagram (Definition 7.4) from [43]; 2. to give a proof that the collection of undirected wiring diagrams forms an operad (Theorem 7.24). There is a subtlety regarding the definition and the operadic composition of undirected wiring diagrams; see Remark 7.5(4) and Example 7.18. Many more examples of undirected wiring diagrams and their operadic composition will be given in the next chapter. Fix a class S for this chapter.

7.1 Defining Undirected Wiring Diagrams In this section, we recall the definition of an undirected wiring diagram. Recall from Definition 2.18 that an S-finite set is a pair (X, v) with X a finite set and / S a function, called the value assignment. Maps between S-finite sets v:X are functions compatible with the value assignments. The category of S-finite sets is denoted by FinS . As in earlier chapters, if there is no danger of confusion, then we write an S-finite set (X, v) simply as X. The number of elements in a finite set T is denoted by |T |. As in Sect. 2.2 we first define undirected prewiring diagrams. Undirected wiring diagrams are then defined as the appropriate equivalence classes.

© Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_7

159

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7 Undirected Wiring Diagrams

Motivation 7.1. Before we define an undirected wiring diagram precisely, let us first provide some motivation for it. An undirected wiring diagram is a picture similar to this:

There are two input boxes X1 = {x1 , . . . , x6 } and X2 = {x 1 , x 2 }, an output box Y = {y1 , . . . , y6 }, and seven cables {c1 , . . . , c7 }. In general, there can be any finite number of input boxes and cables, and each input/output box is a finite set. For each element z in the input boxes and the output box, we need to specify a cable c to which z is connected. For instance, x4 , x5 , and x 2 are connected to the cable c6 . Depending on the given undirected wiring diagrams, there are four possible kinds of cables. First, a cable may only be connected to elements in the inside boxes, such as c6 and c7 in the picture above. Second, a cable may only be connected to elements in the outside box, such as c1 and c5 above. Third, a cable may be connected to elements in both the inside boxes and the outside box, such as c2 and c3 above. Finally, there may be standalone cables that are not connected to anything in the inside and the outside boxes, such as c4 above. Such distinction among the set of cables will be important later when we discuss the finite presentation for the operad of undirected wiring diagrams. We will come back to this picture in Example 7.7 below. The following definition is a slight generalization of [43, Examples 2.1.7 and 4.1.1]; see Remark 7.5. Definition 7.2. Suppose S is a class. An undirected S-prewiring diagram is a tuple   ϕ = X, Y, C, f, g

(7.1)

consisting of the following data. 1. Y ∈ FinS , called the output box of ϕ. An element in Y is called an output wire for ϕ. 2. X = (X1 , . . . , Xn ) is a FinS -profile for some n ≥ 0 (Definition 2.1); i.e., each Xi ∈ FinS . • We call Xi the i-th input box of ϕ. • An element in each Xi is called an input wire for ϕ

7.1 Defining Undirected Wiring Diagrams

161

• Denote by X = ni=1 Xi ∈ FinS the coproduct. • Each element in X  Y is called a wire. 3. C ∈ FinS , called the set of cables of ϕ. Each element in C is called a cable. 4. f and g are maps in the diagram, called a cospan (7.2) in FinS . • f is called the input soldering function and g the output soldering function. • If f (x) = c, then we say that x is soldered to c and that c is soldered to x via f . If g(y) = c, then we say that y is soldered to c and that c is soldered to y via g. • If c ∈ C is a cable and if m = |f −1 (c)| and n = |g −1 (c)|, then c is called an (m,n)-cable. • A (0, 0)-cable is also called a wasted cable. In other words, a wasted cable is a cable that is in neither the image of f nor the image of g. Given Y and X, we will denote ϕ as either the tuple (C, f, g) or the cospan (7.2). Remark 7.3. In Definition 2.19 an S-box is an element in FinS ×FinS . In the context of undirected (pre)wiring diagrams, the name box refers to an element in FinS , such as the output box or one of the input boxes. The context itself should make it clear what box means. The cables tell us how to wire the input wires and the output wires together. So the names of the cables should not matter. This is made precise in the following definition.     Definition 7.4. Suppose ϕ = X, Y, C, f, g and ϕ  = X, Y, C  , f  , g  are two undirected S-prewiring diagrams with the same output box Y and input boxes X. 1. An equivalence h : ϕ that the diagram

/ ϕ  is an isomorphism h : C

/ C  ∈ FinS such

in FinS is commutative. / ϕ. 2. We say that ϕ and ϕ  are equivalent if there exists an equivalence ϕ 3. An undirected S-wiring diagram is an equivalence class of undirected Sprewiring diagrams. If S is clear from the context, we will drop S and just say undirected wiring diagram.

162

7 Undirected Wiring Diagrams

4. The class of undirected S-wiring diagrams with output box Y and input boxes X = (X1 , . . . , Xn ) is denoted by UWD

Y  X

or

UWD



 Y X1 ,...,Xn

.

(7.3)

The class of all undirected S-wiring diagrams is denoted by UWD. If we want to emphasize the class S, we will write UWDS . Remark 7.5. Consider Definitions 7.2 and 7.4. 1. If S = {∗}, a one-point set, then what we call an undirected {∗}-wiring diagram is called a singly-typed wiring diagram in [43, Example 2.1.7]. 2. If S = Set, the collection of sets, then what we call an undirected Set-wiring diagram is called a typed wiring diagram in [43, Example 4.1.1]. 3. Cospans (7.2) are also used in other work about processes and networks. For example, cospans in a category, rather than just FinS , are used in [14]. That setting is then used in [5, 6] to study passive linear networks and Markov processes. 4. In the book [44, p. 464] (but not in [43, Example 2.1.7]), Spivak’s definition of an undirected {∗}-wiring diagram is slightly different from ours. More precisely, Spivak insisted that the maps (f, g) in the cospan (7.2) be jointly surjective, meaning that there are no wasted cables. However, undirected wiring diagrams whose structure maps (f, g) are jointly surjectivity are not closed under the operad structure in UWD, to be defined in Sect. 7.3. In Example 7.18 and Sect. 8.3 we will illustrate that the operadic composition of undirected wiring diagrams without wasted cables can have wasted cables. In other words, while individual undirected wiring diagrams may have no wasted cables, the operadic composition can actually create wasted cables. So there is no such thing as the operad of undirected wiring diagrams without wasted cables. In [14, Def. 3.1] Fong also used cospans, but did not insist that they be jointly surjective in any way. Convention 7.6. To simplify the presentation, we usually suppress the difference between an undirected prewiring diagram and anundirected wiring diagram. Each  undirected wiring diagram ϕ = X, Y, C, f, g has a unique representative in which: • each cable is an element in S; • the value assignment v : C

/ S sends each cable to itself.

Unless otherwise specified, we will always use this representative of an undirected wiring diagram. Example 7.7. Suppose S is any class. Consider the undirected wiring diagram ϕ ∈  Y  UWD X1 ,X2 defined as follows. • The input boxes are X1 = {x1 , x2 , x3 , x4 , x5 , x6 } and X2 = {x 1 , x 2 } ∈ FinS . • The output box is Y = {y1 , y2 , y3 , y4 , y5 , y6 } ∈ FinS . • The set of cables is C = {c1 , c2 , c3 , c4 , c5 , c6 , c7 } ∈ FinS .

7.1 Defining Undirected Wiring Diagrams

163

Their value assignments satisfy the following conditions: • • • • • • •

v(c1 ) = v(y1 ) = v(y2 ) ∈ S. v(c2 ) = v(x1 ) = v(y3 ) ∈ S. v(c3 ) = v(x2 ) = v(x3 ) = v(x 1 ) = v(y4 ) = v(y5 ) ∈ S. v(c4 ) ∈ S is arbitrary. v(c5 ) = v(y6 ) ∈ S. v(c6 ) = v(x4 ) = v(x5 ) = v(x 2 ) ∈ S. v(c7 ) = v(x6 ) ∈ S.

The input and the output soldering functions

are defined as follows: • • • • • • •

c1 c2 c3 c4 c5 c6 c7

= g(y1 ) = g(y2 ) is a (0, 2)-cable. = f (x1 ) = g(y3 ) is a (1, 1)-cable. = f (x2 ) = f (x3 ) = f (x 1 ) = g(y4 ) = g(y5 ) is a (3, 2)-cable. is a (0, 0)-cable, i.e., a wasted cable. = g(y6 ) is a (0, 1)-cable. = f (x4 ) = f (x5 ) = f (x 2 ) is a (3, 0)-cable. = f (x6 ) is a (1, 0)-cable.

Graphically we represent this undirected wiring diagram ϕ ∈ UWD follows.



Y  X1 ,X2

as

(7.4) The input boxes X1 = {x1 , . . . , x6 } and X2 = {x 1 , x 2 } are drawn as the smaller boxes inside. The output box Y = {y1 , . . . , y6 } is drawn as the outer rectangle. Each element within each box is drawn along the boundary, either just inside (as in X1 and X2 ) or just outside (as in Y ). Note that no orientation is attached to the sides of these squares and rectangles. For example, we could have drawn y6 ∈ Y on the bottom side of the outer rectangle. Each cable ci ∈ C is drawn as a small gray disk, which is not to be confused with a delay node in a wiring diagram (such as d in (2.22)). The soldering functions f and g tell us how to connect the wires in X = X1  X2 and Y to the cables. We will revisit this example in Example 9.2 below.

164

7 Undirected Wiring Diagrams

7.2 Pushouts The operadic composition on the collection of undirected wiring diagrams UWD (Definition 7.4) involves the basic categorical concept of a pushout, which we recall in this section. The reader may consult [2, 5.6] and [29, pp. 65–66] for more discussion of pushouts. Roughly speaking, a pushout is a way of summing two objects with some identification. We will only use the following definition when the category is FinS (Definition 2.18), so the reader may simply take the category C below to be FinS and objects and maps to be those in FinS . Definition 7.8. Suppose C is a category (Definition 2.14), and

(7.5) is a diagram in C. Then a pushout of this diagram is a tuple (W, α, β) consisting of / W and β : Z / W in C such that the an object W ∈ C and maps α : Y following two conditions hold. 1. The square

in C is commutative, i.e., αf = βg. 2. Suppose (W  , α  , β  ) is another such tuple, i.e., α  f = β  g. Then there exists a / W  in C such that the diagram unique map h : W

(7.6) in C is commutative, i.e., α  = hα and β  = hβ. If a pushout exists, then by definition it is unique up to unique isomorphisms. In a general category, a pushout may not exist for a diagram of the form (7.5). Even if

7.3 Operad Structure

165

it exists, it may be difficult to describe. Luckily, for S-finite sets (Definition 2.18), pushouts always exist and are easy to describe, as the following observation shows. Proposition 7.9. In the category FinS of S-finite sets, each diagram of the form (7.5) has a pushout given by the quotient Y Z " W = ! f (x) = g(x) : x ∈ X

(7.7)

taken in FinS . / W and β : Z / W are the obvious maps, each Proof. The maps α : Y being the inclusion into Y  Z followed by the quotient map to W . Then the tuple (W, α, β) has the required universal property of a pushout in FinS .   Example 7.10. A commutative square with opposite identity maps is a pushout square. In other words, a pushout of the diagram

in any category is given by the commutative square

as can be checked by a direct inspection.

7.3 Operad Structure Fix a class S. In this section we define the FinS -colored operad structure (Definition 2.10) on the collection of undirected wiring diagrams UWD (Definition 7.4). When S is either {∗} or the collection of sets, this operad structure on UWD was first introduced in [43] using the structure map γ (2.2). Definition 7.11 (Equivariance in UWD). Suppose Y ∈ FinS , X = (X1 , . . . , Xn ) is a FinS -profile of length n, and σ ∈ Σn is a permutation. Define the function (7.8)

166

by sending ϕ = (C, f, g) ∈ UWD

that ni=1 Xi = ni=1 Xσ (i) .

7 Undirected Wiring Diagrams Y  X

to ϕ = (C, f, g) ∈ UWD

Y  Xσ

, using the fact

In other words, the equivariant structure in UWD simply relabels the input boxes. Next we define the colored units in UWD. The Y -colored unit in UWD, for Y ∈ FinS , may be depicted as follows.

Definition 7.12 (Units in UWD). For each Y ∈ FinS , the Y-colored unit is defined as the undirected wiring diagram (7.9) Motivation 7.13. Next we define the ◦i -composition in UWD. The operadic composition ϕ ◦i ψ can be visualized as in the following picture.

(7.10) Intuitively, to form the operadic composition ϕ ◦i ψ in UWD, we replace the ith input box Xi in ϕ by the input boxes in ψ. The set of cables in ψ is added to the set of cables in ϕ, with appropriate identification from the input and the output soldering functions in ϕ and ψ. The following notation will be useful in the definition of the ◦i -composition.

7.3 Operad Structure

167

Notation 7.14. Suppose X = (X1 , . . . , Xn ) is a FinS -profile. 1. Write X = X1  · · ·  Xn ∈ FinS . 2. For integers i and j , define X[i,j ] =

 Xi  · · ·  Xj

if 1 ≤ i ≤ j ≤ n;

∅

otherwise.

(7.11)

Definition 7.15 (◦i -Composition in UWD). Suppose: ⎧ ⎨ fϕ gϕ  Y  / Cϕ o • ϕ = X ∈ UWD X with X = (X1 , . . . , Xn ), Y ⎩ n ≥ 1,⎧and 1 ≤ i ≤ n; ⎨ fψ / Cψ o • ψ= W ⎩

gψ

Xi



∈ UWD

 Xi  W

with |W | = m ≥ 0.

Define the undirected wiring diagram ϕ ◦i ψ = (C, f, g) ∈ UWD



Y  X◦i W

as the cospan

(7.12) in FinS . Here: • The square is a pushout in FinS , which always exists by Proposition 7.9. • The S-finite sets W , X[1,i−1] , and X[i+1,n] are as in Notation 7.14. • The FinS -profile   X ◦i W = X1 , . . . , Xi−1 , W , Xi+1 , . . . , Xn is as in (2.10).

168

7 Undirected Wiring Diagrams

• The map f is the bottom horizontal composition, and the map g is the right vertical composition. In the following observation, we describe the undirected wiring diagram ϕ ◦i ψ more explicitly. Proposition 7.16. Consider the diagram (7.12). 1. A choice of a pushout C is the quotient C=

Cϕ  Cψ  fϕ (x) = gψ (x) : x ∈ Xi

(7.13)

in FinS . The following statements use this choice of C. / C and Cψ / C are the obvious maps, each being the 2. The maps Cϕ inclusion into Cϕ  Cψ followed by the quotient map to C. 3. In the map f and in the horizontal unnamed map, for j = i, the map / C is the composition Xj

4. On W the map f is the composition

Proof. A direct inspection shows that the first three statements indeed describe a pushout of the square in the diagram (7.12). The last assertion follows from the definition of f as the bottom horizontal composition.   Remark 7.17. Consider Definition 7.15. 1. Pushouts are unique up to unique isomorphisms. Since undirected wiring diagrams are defined as equivalence classes of undirected prewiring diagrams (Definition 7.4), the undirected wiring diagram ϕ ◦i ψ is well-defined. 2. In [43] S was taken to be either the one-point set or the collection of sets. The operadic composition in UWD was defined in terms of the operadic composition γ (2.2). By Proposition 2.12 the two descriptions—i.e., the one in [43] and Definition 7.15—are equivalent. Recall from Definition 7.2 that a wasted cable in an undirected wiring diagram is a cable that is not in the image of the input and the output soldering functions.

7.3 Operad Structure

169

Example 7.18. In this example, we observe that wasted cables can be created by the ◦i -composition, even if the original undirected wiring diagrams have no wasted cables. Suppose: two-element set. • S = {∗}  and X = {x1 , x2 } ∈ Fin is a # ∅ / {∗} o ∅ ∈ UWD X . • ϕ= X $  = X  / X o X ∈ UWD ∅ . • ψ= ∅ Note that neither ϕ nor ψ has a wasted cable. On the other hand, the undirected ∅ wiring diagram ϕ ◦1 ψ ∈ UWD ∅ is the cospan

in Fin, in which the square is a pushout by Example 7.10. The following picture gives a visualization of this ◦1 -composition.

In particular, the unique cable in ϕ ◦1 ψ is a wasted cable. This example illustrates that the ◦i -composition of two undirected wiring diagrams without wasted cables may have wasted cables, which we mentioned in Remark 7.5. We will revisit this example in Sect. 8.3 and Example 10.5 below. We now prove that the collection UWD of undirected wiring diagrams is a FinS colored operad in the sense of Definition 2.10. Lemma 7.19. The ◦i -composition in Definition 7.15 satisfies the left unity axiom (2.13), the right unity axiom (2.14), and the equivariance axiom (2.15).

170

7 Undirected Wiring Diagrams

Proof. The equivariance axiom holds because the equivariant structure (7.11) simply relabels the input boxes. The unity axioms follow from the definitions of the colored units in UWD (7.9) and Example 7.10.   Motivation 7.20. The horizontal associativity axiom in UWD may be visualized as follows.

To keep the picture simple, we omitted drawing the wires and the cables. Note that this is basically the undirected version of the picture (2.29). Lemma 7.21. The ◦i -composition in Definition 7.15 satisfies the horizontal associativity axiom (2.11). Proof. Suppose:   Z  • ϕ = Cϕ , fϕ , gϕ ∈ UWD Y with |Y | = n ≥ 2 and 1 ≤ i < j ≤ n;   Y  • ψ = Cψ , fψ , gψ ∈ UWD Wi with |W | = l;   Yj  • ζ = Cζ , fζ , gζ ∈ UWD X with |X| = m. We must show that     Z ϕ ◦j ζ ◦i ψ = (ϕ ◦i ψ) ◦j −1+l ζ ∈ UWD (Y ◦j X)◦i W . Consider the undirected wiring diagram (C, f, g) ∈ UWD given by the cospan



 Z (Y ◦j X)◦i W

(7.14)

7.3 Operad Structure

171

in FinS , where Notation 7.14 was used. In this cospan: • The set of cables is the quotient C=!

Cϕ  Cψ  Cζ fϕ (yi ) = gψ (yi ), fϕ (yj ) = gζ (yj ) : yi ∈ Yi , yj ∈ Yj gϕ

• The output soldering function g is the composition Z

".

/ Cϕ

/ C .

• For the input soldering function f : fϕ

– The restriction to Yk is the composition Yk

/ Cϕ

/ C

for

k = i, j . fψ

– The restriction to W is the composition W fζ

– The restriction to X is the composition X

/ Cψ / Cζ

/ C . / C .

Using the description of ◦i in Proposition 7.16, a direct inspection reveals that both sides of (7.14) are equal to (C, f, g).   Motivation 7.22. The vertical associativity axiom in UWD may be visualized as follows.

As before, to keep the picture simple, we did not draw the wires and the cables. Note that this is basically the undirected version of the picture (2.31). Lemma 7.23. The ◦i -composition in Definition 7.15 satisfies the vertical associativity axiom (2.12).

172

7 Undirected Wiring Diagrams

Proof. Suppose:   Z  • ϕ = Cϕ , fϕ , gϕ ∈ UWD Y with |Y | = n ≥ 1 and 1 ≤ i ≤ n;   Y  • ψ = Cψ , fψ , gψ ∈ UWD Xi with |X| = m ≥ 1 and 1 ≤ j ≤ m;    Xj  • ζ = Cζ , fζ , gζ ∈ UWD W with |W | = l. We must show that     Z (ϕ ◦i ψ) ◦i−1+j ζ = ϕ ◦i ψ ◦j ζ ∈ UWD (Y ◦i X)◦i−1+j W .

(7.15)

Consider the undirected wiring diagram (C, f, g) ∈ UWD



 Z (Y ◦i X)◦i−1+j W

given by the cospan

in FinS , where Notation 7.14 was used. In this cospan: • The set of cables is the quotient Cϕ  Cψ  Cζ ". C= ! fϕ (y) = gψ (y), fψ (x) = gζ (x) : y ∈ Yi , x ∈ Xj gϕ

• The output soldering function g is the composition Z

/ Cϕ

/ C .

• For the input soldering function f : fϕ

– The restriction to Yl is the composition

Yl

/ Cϕ

/ C

/ Cψ

/ C for

for

l = i. fψ

– The restriction to Xk is the composition Xk k = j . fζ

– The restriction to W is the composition W

/ Cζ

/ C .

Using the description of ◦i in Proposition 7.16, a direct inspection reveals that both sides of (7.15) are equal to (C, f, g).   Theorem 7.24. For any class S, when equipped with the structure in Definitions 7.11–7.15, UWD in Definition 7.4 is a FinS -colored operad, called the operad of undirected wiring diagrams.

7.3 Operad Structure

173

Proof. In view of Definition 2.10, this follows from Lemmas 7.19, 7.21, and 7.23.   Example 7.25. Consider Theorem 7.24. 1. If S = {∗}, a one-point set, then our Fin-colored operad UWD is called the operad of singly-typed wiring diagrams in [43, Example 2.1.7] . 2. If S = Set, the collection of sets, then our FinSet -colored operad UWD is called the operad of typed wiring diagrams in [43, Example 4.1.1]. We defined the operad UWD in terms of the ◦i -compositions (Definition 7.15). The following observation expresses the operad UWD in terms of the operadic composition γ (2.2). In [43] the operad structure on undirected wiring diagrams was actually defined in terms of γ . Proposition 7.26. Suppose: Y 

• ϕ = (Cϕ , fϕ , gϕ ) ∈ UWD X with X = (X1 , . . . , Xn ) for some n ≥ 1 and X = X1  · · ·  Xn .   X  • For each 1 ≤ i ≤ n, ψi = (Ci , fi , gi ) ∈ UWD Wii with W i = Wi,1 , . . . , Wi,ki for some ki ≥ 0.

• W = (W 1 , . . . , W n ), Wi = Wi,1  · · ·  Wi,ki , and W = 1≤i≤n Wi . Then   Y  γ ϕ; ψ1 , . . . , ψn = (C, f, g) ∈ UWD W is given by the cospan

(7.16) in FinS , in which the square is a pushout. In this diagram: 1. C is the quotient Cϕ  C1  · · ·  Cn " C= ! fϕ (x) = gi (x) : x ∈ Xi , 1 ≤ i ≤ n in FinS .

174

7 Undirected Wiring Diagrams

/ C and Ci / C are the obvious maps, each being an 2. The maps Cϕ inclusion followed by a quotient map to C. / Ci and 3. The restriction of f to Wi is the composition of fi : Wi / Ci C. Proof. This follows from (i) the correspondence (2.16) between γ and the ◦i compositions and (ii) the description of ◦i given in Proposition 7.16.  

7.4 Summary of this Chapter 1. An undirected S-wiring diagram has a finite number of input boxes, an output box, an S-finite set of cables, an input soldering function, and an output soldering function. 2. For each class S, the collection of S-wiring diagrams UWD is a FinS -colored operad.

Chapter 8

Generators and Relations

Fix a class S, and consider the FinS -colored operad UWD of undirected wiring diagrams (Theorem 7.24). The purpose of this chapter is to describe a finite number of undirected wiring diagrams that we will later show to be sufficient to describe the entire operad UWD. One may also regard this chapter as consisting of a long list of examples of undirected wiring diagrams. In Sect. 8.1 we describe six undirected wiring diagrams, called the generating undirected wiring diagrams. Later we will show that they generate the operad UWD of undirected wiring diagrams. This means that every undirected wiring diagram can be obtained from finitely many generating undirected wiring diagrams via iterated operadic compositions. For now one may think of the generating undirected wiring diagrams as examples of undirected wiring diagrams. In Sect. 8.2 we describe 17 elementary relations among the generating undirected wiring diagrams. Later we will show that these elementary relations together with the operad associativity and unity axioms—(2.11)–(2.14)—for the generating undirected wiring diagrams generate all the relations in the operad UWD of undirected wiring diagrams. In other words, suppose an arbitrary undirected wiring diagram can be built in two ways using the generating undirected wiring diagrams. Then there exists a finite sequence of steps connecting them in which each step is given by one of the 17 elementary relations or an operad associativity/unity axiom for the generating undirected wiring diagrams. For now one may think of the elementary relations as examples of the operadic composition in the operad UWD.

8.1 Generating Undirected Wiring Diagrams Recall the definition of an undirected wiring diagram (Definition 7.4). In this section, we introduce six undirected wiring diagrams, called the generating undirected wiring diagrams. They will be used in later chapters to give a finite presentation for © Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_8

175

176

8 Generators and Relations

the operad UWD of undirected wiring diagrams. The undirected wiring diagrams in this section all have directed analogues in Sect. 3.1. The following undirected wiring diagram is an undirected analogue of the empty wiring diagram (Definition 3.1). Definition 8.1. Define the empty cell

where ∅ is the empty S-finite set. Note that the empty cell is a 0-ary element in UWD. Next we define the undirected wiring diagram

with no input boxes and whose unique cable is a (0, 1)-cable. This is an undirected analogue of a 1-wasted wire (Definition 3.8). To simplify the typography, we will often write x for the one-point set {x}. Definition 8.2. Suppose ∗ ∈ FinS is a one-element S-finite set. Define the 1-output wire

Note that a 1-output wire is a 0-ary element in UWD. Next we define the undirected wiring diagram

with 1 input box and whose cables are all (1, 1)-cables. This is an undirected analogue of a name change (Definition 3.3). Definition 8.3. Suppose f : X undirected name change

/ Y ∈ FinS is a bijection. Define the

8.1 Generating Undirected Wiring Diagrams

177

If the bijection f is clear from the context, then we write τf as τX,Y or just τ . If there is no danger of confusion, then we will call τf a name change. Next we define the undirected wiring diagram

with two input boxes and whose cables are all (1, 1)-cables. This is an undirected analogue of a 2-cell (Definition 3.4). Definition 8.4. Suppose X, Y ∈ FinS and X  Y is their coproduct. Define the undirected 2-cell

If there is no danger of confusion, then we will call it a 2-cell. Next we define the undirected wiring diagram

with a (2, 0)-cable, all other cables being (1, 1)-cables. This is an undirected analogue of a 1-loop (Definition 3.5). Definition 8.5. Suppose: • X ∈ FinS , and x+ , x− ∈ X are two distinct elements with v(x+ ) = v(x− ) ∈ S. • X \ x± ∈ FinS is obtained from X by removing x+ and x− . • X/(x+ = x− ) ∈ FinS is the quotient of X with x+ and x− identified. Define the loop

Next we define the undirected wiring diagram

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8 Generators and Relations

with a (1, 2)-cable, all other cables being (1, 1)-cables. This is an undirected analogue of an out-split (Definition 3.7). Definition 8.6. Suppose: • X ∈ FinS , and x1 , x2 are two distinct elements in X with v(x1 ) = v(x2 ) ∈ S. • X ∈ FinS , and x ∈ X such that v(x) = v(x1 ) and that X \ {x} = X \ {x1 , x2 }. Define the aligned

in which the output soldering function X is the identity function on X \ {x1 , x2 }.

/ X sends x1 , x2 ∈ X to x ∈ X and

Definition 8.7. The 6 undirected wiring diagrams in Definitions 8.1–8.6 will be referred to as generating undirected wiring diagrams. If the context is clear, we will simply call them generators. Remark 8.8. Among the generating undirected wiring diagrams: 1. None has a wasted cable (Definition 7.2). As we will see in Sect. 8.3, wasted cables can be created by the generators. 2. The empty cell  (Definition 8.1) and a 1-output wire ω∗ (Definition 8.2) are 0-ary elements in UWD. 3. A name change τ (Definition 8.3), a loop λ(X,x± ) (Definition 8.5), and a split 1 2 σ (X,x ,x ) (Definition 8.6) are unary elements in UWD. 4. A 2-cell θ(X,Y ) (Definition 8.4) is a binary element in UWD.

8.2 Elementary Relations The purpose of this section is to introduce 17 elementary relations among the generating undirected wiring diagrams (Definition 8.7). Each elementary relation is proved using Proposition 7.16 and Example 7.10 and by a simple inspection of the relevant definitions of the generating undirected wiring diagrams and operadic compositions. Each proof is similar to Example 7.18 and the proofs of Lemmas 7.21 and 7.23. Therefore, we will omit the proofs, providing a picture instead in most cases. Some, but not all, of the following relations have directed analogues in Sect. 3.3. Recall the operadic composition in the FinS -colored operad UWD (Definition 7.15) and Notation 3.14 for (iterated) ◦1 . The first five relations concern name changes (Definition 8.3). The first one says that two consecutive name changes can be composed down into one name change.

8.2 Elementary Relations

179

Proposition 8.9. Suppose: / Z ∈ FinS are bijections. / Y and g : Y • f :X Y  Z  Z  • τf ∈ UWD X , τg ∈ UWD Y , and τgf ∈ UWD X are the corresponding name changes. Then τg ◦ τf = τgf ∈ UWD

Z  X

(8.1)

.

The next relation says that a name change of a 1-output wire (Definition 8.2) is again a 1-output wire. Proposition 8.10. Suppose: • X = {x} and Y = {y} are two 1-element S-finite sets with v(x) = v(y) ∈ S. Y  X and ωy ∈ UWD are the corresponding 1-output wires. • ωx ∈ UWD Y  • τX,Y ∈ UWD X is the name change corresponding to the bijection / Y ∈ FinS . X Then τX,Y ◦ ωx = ωy ∈ UWD

Y 

.

(8.2)

The next relation says that name changes inside a 2-cell (Definition 8.4) can be rewritten as a name change of a 2-cell. Proposition 8.11. Suppose: / Y1 and f2 : X2 / Y2 ∈ FinS are bijections. • f1 : X1 / Y1  Y2 ∈ FinS is their coproduct. • f1  f2 : X1  X2 Y  Y   Y Y  • τf1 ∈ UWD X11 , τf2 ∈ UWD X22 , and τf1 f2 ∈ UWD X11 X22 corresponding name changes. X X  Y Y  • θ(X1 ,X2 ) ∈ UWD X11 ,X22 and θ(Y1 ,Y2 ) ∈ UWD Y11 ,Y22 are 2-cells.

are the

Then   Y Y  θ(Y1 ,Y2 ) ◦1 τf1 ◦2 τf2 = τf1 f2 ◦ θ(X1 ,X2 ) ∈ UWD X11 ,X22 .

(8.3)

The next relation says that a name change inside a loop (Definition 8.5) can be rewritten as a name change of a loop. Proposition 8.12. Suppose: • X ∈ FinS , and x+ , x− ∈ X are two distinct elements with v(x+ ) = v(x− ) ∈ S. / Y ∈ FinS is a bijection with y+ = f (x+ ) and y− = f (x− ). • f :X • X \ x± ∈ FinS and Y \ y± ∈ FinS are obtained from X and Y by removing the indicated elements. / Y \ y± is the corresponding bijection. • f  : X \ x±

180

8 Generators and Relations Y 

 Y \y 

• τf ∈ UWD X and τf  ∈ UWD X\x±± are name changes. X\x  Y \y  • λ(X,x± ) ∈ UWD X ± and λ(Y,y± ) ∈ UWD Y ± are loops. Then λ(Y,y± ) ◦ τf = τf  ◦ λ(X,x± ) ∈ UWD

Y \y±  X

(8.4)

.

The next relation says that a name change inside a split (Definition 8.6) can be rewritten as a name change of a split. Proposition 8.13. Suppose: X ∈ FinS , and x1 , x2 are two distinct elements in X with v(x1 ) = v(x2 ) ∈ S. X ∈ FinS , and x ∈ X such that v(x) = v(x1 ) and that X \ {x} = X \ {x1 , x2 }. / Y ∈ FinS is a bijection with y1 = f (x1 ) and y2 = f (x2 ). f :X Y  ∈ FinS , and y ∈ Y  such that v(y) = v(y1 ) ∈ S and that Y  \ {y} = Y \ {y1 , y2 }. / Y  ∈ FinS is a bijection such that f  (x) = y and that its • f  : X restriction to X \ {x} = X \ {x1, x 2 } is equal to that of f . Y  Y • τf ∈ UWD X and τf  ∈ UWD X are name changes. X   (X,x ,x ) (Y,y 1 2 ∈ UWD  and σ 1 ,y2 ) ∈ UWD Y are splits. • σ X Y • • • •

Then σ (Y,y1 ,y2 ) ◦ τf  = τf ◦ σ (X,x1 ,x2 ) ∈ UWD

Y  X

.

(8.5)

The following two relations involve 1-output wires in somewhat subtle ways. The next relation says that the undirected wiring diagram

with a (1, 0)-cable, all other cables being (1, 1)-cables, can be obtained from the generators as either one of the following two (iterated) operadic compositions.

8.2 Elementary Relations

181

As in Sect. 7.3, the gray boxes here indicate an operadic composition. • On the left, a 1-output wire ωy is substituted into a 2-cell θ(X,y), which is then substituted into a loop λ(Y,x,y). • On the right, a split σ (Y,x,y) is substituted into a loop λ(Y,x,y). Proposition 8.14. Suppose: • • • • • •

Y ∈ FinS , and x, y ∈ Y are distinct elements with v(x) = v(y) ∈ S. X =Y \y ∈ Fin is obtained from Y by removing y. y  S ωy ∈ UWD is the 1-output wire for y. Y  θ(X,y) ∈ UWD X,y is a 2-cell. W  λ(Y,x,y) ∈ UWD Y is a loop, where W = Y \ {x, y} = X \ x. Y  σ (Y,x,y) ∈ UWD X is a split.

Then

  W  λ(Y,x,y) ◦ θ(X,y) ◦2 ωy = λ(Y,x,y) ◦ σ (Y,x,y) ∈ UWD X .

(8.6)

The next relation says that the X-colored unit (Definition 7.12) can be obtained from the generators as the following iterated operadic composition.

More precisely, it says that the X-colored unit 1X can be obtained by substituting a 1-output wire ωy into a 2-cell θ(X,y), then into a split σ (W,x,w) , and then into a loop λ(W,w,y) . Proposition 8.15. Suppose: • • • • • • •

W ∈ FinS , and w, x, y are distinct elements in W with v(w) = v(x) = v(y) ∈ S. Y = W \ w ∈ FinS is obtained from W by removing w. X =Y \y ∈ Fin is obtained from Y by removing y. y  S ωy ∈ UWD is the 1-output wire for y. Y  θ(X,y) ∈ UWD X,y is a 2-cell. W  σ (W,x,w) ∈ UWD Y  is a split. X λ(W,w,y) ∈ UWD W is a loop.

Then

  X  λ(W,w,y) ◦ σ (W,x,w) ◦ θ(X,y) ◦2 ωy = 1X ∈ UWD X ,

in which 1X is the X-colored unit (Definition 7.12).

(8.7)

182

8 Generators and Relations

The next five relations concern 2-cells (Definition 8.4). The following relation is the unity property of 2-cells. Proposition 8.16. Suppose: 



• θ(X,∅) ∈ UWD X,∅ is a 2-cell. ∅ •  ∈ UWD is the empty cell (Definition 8.1). X

Then θ(X,∅) ◦2  = 1X ∈ UWD

X  X

(8.8)

.

The next relation is the associativity property of 2-cells. It gives two different ways to construct the following undirected wiring diagram using two 2-cells.

Proposition 8.17. Suppose: XY Z

XY 

• θ(XY,Z) ∈ UWD  XY,Z  and θ(X,Y ) ∈ UWD X,Y  are 2-cells. XY Z Y Z • θ(X,Y Z) ∈ UWD X,Y Z and θ(Y,Z) ∈ UWD Y,Z are 2-cells. Then θ(XY,Z) ◦1 θ(X,Y ) = θ(X,Y Z) ◦2 θ(Y,Z) ∈ UWD

XY Z X,Y,Z

.

(8.9)

The next relation is the commutativity property of 2-cells. It uses the equivariant structure (7.11) in UWD. Proposition 8.18. Suppose: XY 

• θX,Y ∈ UWD X,Y is a 2-cell. • (1 2) ∈ Σ2 is the non-trivial permutation. Then θ(X,Y )(1 2) = θ(Y,X) ∈ UWD

Y X Y,X

.

(8.10)

The next relation is the commutativity property between a 2-cell and a loop. It gives two different ways to construct the following undirected wiring diagram.

8.2 Elementary Relations

183

Proposition 8.19. Suppose: • • • • •

Y ∈ FinS , and y+ , y− are distinct elements in Y with v(y+ ) = v(y− ) ∈ S. Y  = Y \ y± ∈ Fin is obtained from Y by removing y+ and y− . Y   S λ(Y,y± ) ∈ UWD Y is a loop. XY  XY   θ(X,Y ) ∈ UWD X,Y and θ(X,Y  ) ∈ UWD X,Y  are 2-cells for some X ∈ FinS . XY   λ(XY,y± ) ∈ UWD XY is a loop.

Then θ(X,Y  ) ◦2 λ(Y,y± ) = λ(XY,y± ) ◦ θ(X,Y ) ∈ UWD

XY   X,Y

(8.11)

.

The next relation is the commutativity between a 2-cell and a split. It gives two different ways to construct the following undirected wiring diagram.

Proposition 8.20. Suppose: • • • • •

Y ∈ FinS , and y1 , y2 are distinct elements in Y with v(y1 ) = v(y2 ) ∈ S. Y  ∈ FinS , and y ∈ Y  such that v(y) = v(y1 ) and that Y  \ {y} = Y \ {y1 , y2 }. Y  is a split. σ (Y,y1 ,y2 ) ∈ UWD XYY XY   θ(X,Y ) ∈ UWD X,Y and θ(X,Y  ) ∈ UWD X,Y  are 2-cells for some X ∈ FinS .  XY  σ (XY,y1 ,y2 ) ∈ UWD XY  is a split.

Then θ(X,Y ) ◦2 σ (Y,y1 ,y2 ) = σ (XY,y1,y2 ) ◦ θ(X,Y  ) ∈ UWD

XY  X,Y 

.

(8.12)

The following four relations concern splits. The next relation is the commutativity property of splits. It gives two different ways to construct the following undirected wiring diagram using two splits.

184

8 Generators and Relations

Proposition 8.21. Suppose: • X ∈ FinS , and y1 , y2 , z1 , z2 are distinct elements such that v(y1 ) = v(y2 ) and v(z1 ) = v(z2 ) ∈ S. • X ∈ FinS , and y and z are distinct elements in X such that – v(y) = v(y1 ) and v(z) = v(z1 ); – X \ {y, z} = X \ {y1, y2 , z1 , z2 }.     • Y = X \ {y}  {y1 , y2 } and Z = X \ {z}  {z1 , z2 } ∈ FinS X Z • σ (X,y1 ,y2 ) ∈ UWD Z and σ (Z,z1 ,z2 ) ∈ UWD X are splits. X Y • σ (X,z1 ,z2 ) ∈ UWD Y and σ (Y,y1 ,y2 ) ∈ UWD X are splits. Then σ (X,y1 ,y2 ) ◦ σ (Z,z1 ,z2 ) = σ (X,z1 ,z2 ) ◦ σ (Y,y1 ,y2 ) ∈ UWD

X X

.

(8.13)

The next relation is the associativity property of splits. It gives two different ways to construct the following undirected wiring diagram using two splits.

Proposition 8.22. Suppose: • Y ∈ FinS , and y1 , y2 , y3 are distinct elements in Y with v(y1 ) = v(y2 ) = v(y3 ) ∈ S. • X ∈ FinS , and x ∈ X such that – v(x) = v(y1 ); – X \ {x} = Y \ {y1, y2 , y3 }. • Y1 = Y/(y1 = y2 ) ∈ FinS is the quotient of Y with y1 and y2 identified, called y12 ∈ Y1 . • Y2 = Y/(y2 = y3 ) ∈ FinS is the quotient of Y with y2 and y3 identified, called y23 ∈ Y2 . Y  Y  • σ (Y,y1 ,y2 ) ∈ UWDY1  and σ (Y1 ,y12 ,y3 ) ∈ UWD X1  are splits. Y Y • σ (Y,y2 ,y3 ) ∈ UWD Y2 and σ (Y2 ,y1 ,y23 ) ∈ UWD X2 are splits.

8.2 Elementary Relations

185

Then σ (Y,y1 ,y2 ) ◦ σ (Y1 ,y12 ,y3 ) = σ (Y,y2 ,y3 ) ◦ σ (Y2 ,y1 ,y23 ) ∈ UWD

Y  X

.

(8.14)

The next relation is the commutativity property between a split and a loop. It gives two different ways to construct the following undirected wiring diagram using a split and a loop.

Proposition 8.23. Suppose: • Y ∈ FinS , and y1 and y2 are distinct elements in Y with v(y1 ) = v(y2 ) ∈ S. • X ∈ FinS , and x, x+ , x− are distinct elements in X such that – v(x) = v(y1 ); – v(x+ ) = v(x− ); – X \ {x, x+ , x− } = Y \ {y1 , y2 }.   • Y  = X \ {x}  {y1 , y2 } and X = X \ {x+ , x− }. Y   Y    are splits. and σ (Y,y1 ,y2 ) ∈ UWD • σ (Y ,y1 ,y2 ) ∈ UWD Y X X  X • λ(Y  ,x± ) ∈ UWD Y  and λ(X,x± ) ∈ UWD X are loops. Then λ(Y  ,x± ) ◦ σ (Y

 ,y

1 ,y2 )

= σ (Y,y1 ,y2 ) ◦ λ(X,x± ) ∈ UWD

Y  X

.

The next relation says that the undirected wiring diagram

can be obtained by substituting a split inside a loop as in the picture

(8.15)

186

8 Generators and Relations

or in the counterpart in which x+ and x− are switched. In (8.16) below, this picture corresponds to the left-hand side, and its counterpart corresponds to the right-hand side. Proposition 8.24. Suppose: • • • • •

X ∈ FinS , and x+ and x− are distinct elements in X with v(x+ ) = v(x− ) ∈ S. Y ∈ FinS , and y ∈ Y such that v(y) = v(x+ ) and that X \ x± = Y \ y. W =Xy =Y  x ∈ FinS . W ± W  σ (W,y,x+ ) ∈ UWD and σ (W,y,x− ) ∈ UWD X are splits. X Y  λ(W,x± ) ∈ UWD W is a loop.

Then λ(W,x± ) ◦ σ (W,y,x+ ) = λ(W,x± ) ◦ σ (W,y,x− ) ∈ UWD

Y  X

(8.16)

.

The final relation is the commutativity property of loops. It gives two different ways to construct the following undirected wiring diagram using two loops.

Proposition 8.25. Suppose: • X ∈ FinS , and x1 , x2 , x3 , x4 are distinct elements in X with v(x1 ) = v(x2 ) and v(x3 ) = v(x4 ) ∈ S. • W = X \ {x1 , x2 },Z= X \ {x3 , x4 }, and Y = X \ {x1 , x2 , x3 , x4 } ∈ FinS . W  Y • λ(W,x3 ,x4 ) ∈ UWD W and λ(X,x1 ,x2 ) ∈ UWD X are loops. Y Z • λ(Z,x1 ,x2 ) ∈ UWD Z and λ(X,x3 ,x4 ) ∈ UWD X are loops. Then λ(W,x3 ,x4 ) ◦ λ(X,x1 ,x2 ) = λ(Z,x1 ,x2 ) ◦ λ(X,x3 ,x4 ) ∈ UWD

Y  X

.

(8.17)

Definition 8.26. The 17 relations (8.1)–(8.17) are called elementary relations in UWD. If there is no danger of confusion, we will call them elementary relations.

8.3 Wasted Cables The purpose of this section is to consider several examples of how the generators in the operad UWD can create wasted cables (Definition 7.2). Example 8.30 provides

8.3 Wasted Cables

187

an illustration of some of the elementary relations in UWD. The examples in this section provide a good warm-up exercise for the discussion in Chap. 10 about stratified presentations and elementary equivalences. Recall from Remark 8.7 that none of the generators has a wasted cable. Example 8.27. In the context of Example 7.18 with X = {x1 , x2 }:  # ∅ / ∗ o 1. ϕ = X ∅ ∈ UWD X is the loop λ(X,x1 ,x2 ) . $  = X  / X o X ∈ UWD ∅ is the iterated operadic 2. ψ = ∅ composition ψ=

   θ(∅,X) ◦2 θ(x1 ,x2 ) ◦2 ωx1 ◦2 ωx2

involving two 2-cells and two 1-output wires. So the composition

which is depicted as

and has one wasted cable, is the iterated operadic composition λ(X,x1 ,x2 ) ◦

     θ(∅,X) ◦2 θ(x1 ,x2 ) ◦2 ωx1 ◦2 ωx2

(8.18)

involving five generators. Example 8.28. As a variation of the previous example, consider any box Y ∈ FinS and the undirected wiring diagram with one wasted cable

188

8 Generators and Relations

It is depicted as follows.

This undirected wiring diagram can be created by replacing the empty box ∅ in the 2-cell θ(∅,X) by Y and the loop λ(X,x1 ,x2 ) by the loop λ(Y X,x1 ,x2 ) in (8.18) above. The resulting operadic composition ζY = λ(Y X,x1 ,x2 ) ◦

 

   Y  θ(Y,X) ◦2 θ(x1 ,x2 ) ◦2 ωx1 ◦2 ωx2 ∈ UWD Y

(8.19)

involves five generators: one loop, two 2-cells, and two 1-output wires. It corresponds to the following picture.

The intermediate gray box is Y  X = Y  {x1 , x2 }. Roughly speaking, the operadic composition (8.19) says that a wasted cable can be created by applying a loop to two 1-output wires. Additional wasted cables can similarly be created using more 2-cells, 1-output wires, and loops. Example 8.29. The undirected wiring diagram ζY in Example 8.28 can also be created as in the following picture.

The inner gray box is Y  x1 , and the outer gray box is Y  X. In terms of the generators, the above picture is realized as the operadic composition     Y  ζY = λ(Y X,x1 ,x2 ) ◦ σ (Y X,x1 ,x2 ) ◦ θ(Y,x1) ◦2 ωx1 ∈ UWD Y .

(8.20)

8.4 Summary of this Chapter

189

It involves one loop, one split, one 2-cell, and one 1-output wire. Roughly speaking, the operadic composition (8.20) says that a wasted cable can be created by applying a loop to a split that is attached to a 1-output wire. Example 8.30. As an illustration of using the elementary relations in UWD, recall Y  the undirected wiring diagram ζY ∈ UWD Y in Examples 8.28 and 8.29. It can be generated by the generators as either one of the two iterated operadic compositions (8.19) and (8.20). These two decompositions of ζY are actually connected as follows      by (8.19) θ(Y,X) ◦2 θ(x1,x2 ) ◦2 ωx1 ◦2 ωx2 λ(Y X,x1 ,x2 ) ◦      by elem. rel. (8.9) = λ(Y X,x1 ,x2 ) ◦ θ(Y x1,x2 ) ◦1 θ(Y,x1) ◦2 ωx1 ◦2 ωx2      = λ(Y X,x1 ,x2 ) ◦ θ(Y x1,x2 ) ◦1 θ(Y,x1 ) ◦2 ωx1 ◦2 ωx2 by v.ass. (2.12)     by h.ass. (2.11) = λ(Y X,x1 ,x2 ) ◦ θ(Y x1,x2 ) ◦2 ωx2 ◦1 θ(Y,x1 ) ◦2 ωx1      = λ(Y X,x1 ,x2 ) ◦ θ(Y x1,x2 ) ◦2 ωx2 ◦ θ(Y,x1 ) ◦2 ωx1 by v.ass. (2.12)     by elem. rel. (8.6). = λ(Y X,x1 ,x2 ) ◦ σ (Y X,x1 ,x2 ) ◦ θ(Y,x1) ◦2 ωx1 The last iterated operadic composition above is (8.20). In other words, one can go from the decomposition (8.19) of ζY to (8.20) using two elementary relations, the operad vertical associativity axiom twice, and the operad horizontal associativity axiom once. In the terminology of Chap. 10, we say that (8.19) and (8.20) are stratified presentations (Definition 10.8) of ζY , and they are connected by a finite sequence of elementary equivalences (Definition 10.13).

8.4 Summary of this Chapter 1. There are six generating undirected wiring diagrams. 2. There are 17 elementary relations in UWD. 3. Wasted cables can arise from operadic composition of undirected wiring diagrams with no wasted cables.

Chapter 9

Decomposition of Undirected Wiring Diagrams

This chapter is the undirected analogue of Chap. 4. As part of the finite presentation theorem for the operad UWD of undirected wiring diagrams (Theorem 7.24), in Theorem 10.12 we will observe that each undirected wiring diagram has a highly structured decomposition in terms of generators (Definition 8.7), called a stratified presentation (Definition 10.8). Stratified presentations are also needed to establish the second part of the finite presentation theorem for the operad UWD regarding relations (Theorem 10.19). The purpose of this chapter is to provide all the steps needed to establish the existence of a stratified presentation for each undirected wiring diagram. We remind the reader of Notation 3.14 for (iterated) operadic compositions. Fix a class S, with respect to which the operad UWD of undirected wiring diagrams (Definition 7.24) is defined.

9.1 A Motivating Example Before we establish the desired decomposition of a general undirected wiring diagram, in this section we consider an elaborate example that will serve as a guide and motivation for the construction later in this chapter for the general case. The point of this decomposition is to break the complexity of a general undirected wiring diagram into several stratified pieces, each of which is easy to understand and visualize. The following notations regarding subsets of cables will be used frequently in this chapter. Recall that an (m, n)-cable is a cable to which exactly m input wires and exactly n output wires are soldered (Definition 7.2).

© Springer Nature Switzerland AG 2018 D. Yau, Operads of Wiring Diagrams, Lecture Notes in Mathematics 2192, https://doi.org/10.1007/978-3-319-95001-3_9

191

192

9 Decomposition of Undirected Wiring Diagrams

Notation 9.1. Suppose ψ = (Cψ , fψ , gψ ) is an undirected wiring diagram and m, n ≥ 0. Define: (m,n)

(0,0)

• Cψ ⊆ Cψ as the subset of (m, n)-cables. In particular, Cψ wasted cables. (≥m,n) • Cψ ⊆ Cψ as the subset of (l, n)-cables with l ≥ m.

is the set of

(m,≥n)

⊆ Cψ as the subset of (m, k)-cables with k ≥ n. (≥m,≥n) Cψ ⊆ Cψ as the subset of (j, k)-cables with j ≥ m and k ≥ n. ≥3 Cψ ⊆ Cψ as the subset of (k, l)-cables with k, l ≥ 1 and k + l ≥ 3.

• Cψ • •

(≥m,n)

is called an (≥ m, n)-cable, and similarly for cables in the other A cable in Cψ subsets defined above. As in the case of wiring diagrams (see Convention 4.14), name changes (Definition 8.3) are easy to deal with. Therefore, in the following example, to keep the presentation simple, we will ignore name changes.    Y  Example 9.2. Consider ϕ = Cϕ , fϕ , gϕ ∈ UWD X1 ,X2 in (7.4), which is visualized as

with X1 = {x1 , . . . , x6 } and X2 = {x 1 , x 2 }. We can decompose it as ϕ = ϕ1 ◦ ϕ2 as indicated in the following picture.

(9.1)

9.1 A Motivating Example

193

As before, the intermediate gray box Z indicates that an operadic composition occurs along it. The box Z is defined as Z = X  {c4+ , c4− }  {c1 , c5 }  {c7 } ∈ FinS in which: • X = X1  X2 . • c4+ and c4− are two copies of the wasted cable c4 in ϕ, so {c4+ , c4− } = Cϕ(0,0)  (0,0) Cϕ . • {c1 , c5 } = Cϕ(0,≥1). (1,0) • {c7 } = Cϕ . So we may also write Z as (0,0) Z = X  Cϕ,±  Cϕ(0,≥1)  Cϕ(1,0) (0,0)

(0,0)

in which Cϕ,± = Cϕ

(0,0)

 Cϕ

(9.2)

is the coproduct of two copies of the set of wasted

cables Cϕ(0,0) in ϕ. In the decomposition (9.1) of ϕ, the inside undirected wiring diagram is the cospan

Note that in ϕ2 : • All the input wires—i.e., those in X—are soldered to (1, 1)-cables. (0,0) • All other cables—i.e., those in Cϕ,±  Cϕ(0,≥1)  Cϕ(1,0) —are (0, 1)-cables. • There are no wasted cables. As we will see later in (9.13), such an undirected wiring diagram can be decomposed into 2-cells (Definition 8.4) and 1-output wires (Definition 8.2). For example, this ϕ2 needs: • five 1-output wires, exactly as many as the number of (0, 1)-cables; • six 2-cells, where 6 is the number of input boxes plus the number of (0, 1)-cables minus 1. The outside undirected wiring diagram in the decomposition ϕ = ϕ1 ◦ ϕ2 is the cospan

194

9 Decomposition of Undirected Wiring Diagrams

Here: / Cϕ is the input soldering function of ϕ. / Cϕ is the inclusion map on each coproduct ι:  Cϕ(0,≥1)  Cϕ(1,0) summand. / Cϕ is the output soldering function of ϕ. gϕ : Y Every cable is an (m, n)-cable with m ≥ 1 and n ≥ 0. In other words, every cable in ϕ1 is soldered to some input wires, so in particular there are no wasted cables in ϕ1 . There are also no (1, 0)-cables, but there are (≥ 2, 0)-cables.

• fϕ : X • • •

•

(0,0) Cϕ,±

As we will see later, such an undirected wiring diagram can be decomposed into loops (Definition 8.5) and splits (Definition 8.6). In the case of ϕ1 , which is the undirected wiring diagram

this further decomposition ϕ 1 = φ1 ◦ φ2

(9.3)

can be visualized as follows.

(9.4)

9.2 Factoring Undirected Wiring Diagrams

195

In this decomposition ϕ1 = φ1 ◦ φ2 , the inner undirected wiring diagram is the cospan

with gφ2 surjective. So every cable in φ2 is a (1, n)-cable for some n ≥ 1 . As we will see later, such an undirected wiring diagram is generated by splits (Definition 8.6). For example, this φ2 is the iterated operadic composition of 5 splits—one for the cable soldered to c1 , one for the cable soldered to x5 , and three for the cable soldered to x2 . The outer undirected wiring diagram in the decomposition (9.3) is the cospan

in which every cable is either a (1, 1)-cable or a (2, 0)-cable. We will show later that such an undirected wiring diagram is generated by loops (Definition 8.5). For example, this φ1 is the iterated operadic composition of 6 loops, where 6 is the number of (2, 0)-cables in φ1 .  Y  In summary, we decompose ϕ ∈ UWD X1 ,X2 as the iterated operadic composition ϕ = ϕ 1 ◦ ϕ 2 = φ1 ◦ φ2 ◦ ϕ 2   = λ, . . . , λ, σ, . . . , σ , θ, . . . , θ , ω, . . . , ω .     6

5

6

(9.5)

5

Here λ, σ , θ , and ω denote a loop, a split, a 2-cell, and a 1-output wire, respectively. This decomposition in terms of the generators is called a stratified presentation (Definition 10.8). In the next few sections, we will establish all the steps needed to obtain a stratified presentation for a general undirected wiring diagram.

9.2 Factoring Undirected Wiring Diagrams In this section, using Example 9.2 as a guide and motivation, we establish a decomposition of a general undirected wiring diagram into two simpler undirected wiring diagrams (Theorem 9.5). This is the general version of the decomposition (9.1) above. Each undirected wiring diagram in this decomposition will be decomposed further, eventually leading to the desired stratified presentation.

196

9 Decomposition of Undirected Wiring Diagrams

Assumption 9.3. Suppose

(9.6) is a general undirected wiring diagram with: • output box Y ∈ FinS and input boxes X = (X1 , . . . , XN ) for some N ≥ 0; • X = X1  · · ·  XN ∈ FinS . Recall Notation 9.1 for certain subsets of cables. The undirected wiring diagrams ψ1 and ψ2 in the next definition are the general versions of ϕ1 and ϕ2 in the decomposition (9.1) above.   Y  Definition 9.4. Suppose ψ = Cψ , fψ , gψ ∈ UWD X is a general undirected wiring diagram as in (9.6) with X = (X1 , . . . , XN ). 1. Define (0,0)

(0,≥1)

Z = X  Cψ,±  Cψ

(1,0)

 Cψ

∈ FinS

(9.7)

in which (0,0)

(0,0)

Cψ,± = Cψ

(0,0)

 Cψ

(0,0)

is the coproduct of two copies of the set of wasted cables Cψ 2. Define the undirected wiring diagram

in ψ.

(9.8) in which

is the inclusion map on each coproduct summand. 3. Define the undirected wiring diagram (9.9) Theorem 9.5. In the context of Definition 9.4, there is a decomposition ψ = ψ1 ◦ ψ2 ∈ UWD

Y  X

.

(9.10)

9.3 The Inner Undirected Wiring Diagram

197

Proof. By the definition of ◦ = ◦1 (Definition 7.15), the operadic composition ψ1 ◦ ψ2 is given by the cospan

in FinS . The square is a pushout by Example 7.10. This cospan is equal to ψ. Example 9.6. If ψ =  ∈ UWD

∅

 

is the empty cell (Definition 8.1), then:

• ψ1 = 1∅ , the ∅-colored unit (Definition 7.12) with ∅ ∈ FinS the empty box; • ψ2 = . So in this case the decomposition (9.10) simply says  = 1∅ ◦ . Remark 9.7. In the decomposition (9.10), both ψ1 and ψ2 are simpler than ψ for the following reasons. 1. ψ1 has the same set of cables Cψ and the same output soldering function gψ as ψ. Furthermore, its input soldering function (fψ , ι) includes the input soldering function fψ of ψ. However, every cable in ψ1 is soldered to at least one input wire (i.e., Cψ(0,≥0) = ∅), whereas Cψ(0,≥0) may be non-empty. In particular, ψ1 1 has no wasted cables, even though ψ may have some. Furthermore, ψ1 has only one input box Z, while ψ has N ≥ 0 input boxes. 2. ψ2 has the same input boxes X as ψ. However, it is, in general, much simpler than ψ and ψ1 because its cables are either (1, 1)-cables or (0, 1)-cables. In particular, ψ2 also has no wasted cables. 3. Neither ψ1 nor ψ2 has any (1, 0)-cables, even though ψ may have some.

9.3 The Inner Undirected Wiring Diagram The purpose of this section is to analyze the undirected wiring diagram ψ2 in the decomposition (9.10). The undirected wiring diagram ψ1 will be studied in the next few sections. We begin with the following observation regarding iterated operadic compositions of 2-cells (Definition 8.4).

198

9 Decomposition of Undirected Wiring Diagrams

Motivation 9.8. The following result says that an undirected wiring diagram of the form

can be generated by 2-cells. Proposition 9.9. Suppose n ≥ 2, Xi ∈ FinS for 1 ≤ i ≤ n, and X = Then the undirected wiring diagram

n

i=1 Xi .

(9.11) is: • a 2-cell if n = 2; • an iterated operadic composition    Θ = θ1 ◦2 θ2 ◦3 · · · ◦n−1 θn−1 with each θj a 2-cell if n ≥ 3. Proof. This is proved by induction on n ≥ 2. The initial case simply says that Θ is the 2-cell θ(X1 ,X2 ) by Definition 8.4. Suppose n ≥ 3. By the definition of ◦n−1 (Definition 7.15) and Example 7.10, we may decompose Θ as Θ = Θ1 ◦n−1 θ(Xn−1 ,Xn ) in which

and θ(Xn−1 ,Xn ) ∈ UWD

Xn−1 Xn  Xn−1 ,Xn

is a 2-cell. Since the induction hypothesis applies to Θ1 , the proof is finished. Example 9.10. In the previous Proposition: 1. If n = 3, then Θ decomposes as Θ = θ(X1 ,X2 X3 ) ◦2 θ(X2 ,X3 ) into two 2-cells.

 

9.3 The Inner Undirected Wiring Diagram

199

2. If n = 4, then Θ decomposes as   Θ = θ(X1 ,X2 X3 X4 ) ◦2 θ(X2 ,X3 X4 ) ◦3 θ(X3 ,X4 ) into three 2-cells. Notation 9.11. In the context of (9.7), write: • Cψ = Cψ,±  Cψ   • p = Cψ . (0,0)

(0,≥1)

(1,0)

 Cψ

∈ FinS , so Z = X  Cψ .

The following observation covers the marginal cases for ψ2 . Lemma 9.12. For ψ2 in (9.9):

=



inclusion

X

/ Z o



=

∈

Z

UWD

Z  X

1. If N = p = 0, then ψ2 is the empty cell  (Definition 8.1). 2. If N = 0 and p = 1, then ψ2 is a 1-output wire (Definition 8.2). 3. If N = 1 and p = 0, then ψ2 is the X1 -colored unit (Definition 7.12). Proof. Since X = (X1 , . . . , XN ) and X = X1  · · ·  XN , all three statements follow immediately from the definition of ψ2 .   The next observation covers the other cases for ψ2 . Recall Cψ  in Notation 9.11. Motivation 9.13. The following result says that an undirected wiring diagram of the form

can be generated by 2-cells and 1-output wires. Proposition 9.14. For ψ2 = in (9.9), suppose:



inclusion

X

/ Z o

=

 Z

∈ UWD

Z  X

• N, p ≥ 1, and Cψ  = {c1 , . . . , cp };   = c  / cj o ∈ UWD j is the 1-output wire for cj ∅ cj • ωj = (Definition 8.2) for 1 ≤ j ≤ p. Then there is a decomposition ψ2 =

   Z  Θ ◦N+1 ω1 · · · ◦N+1 ωp ∈ UWD X

(9.12)

200

9 Decomposition of Undirected Wiring Diagrams

in which every pair of parentheses starts on the left and

Z 

Proof. The right-hand side of (9.12) is a well-defined element in X . By the correspondence between the ◦i -compositions and γ (2.16) in the operad UWD, the right-hand side of (9.12) can be rewritten as   ψ2 = γ Θ; 1X1 , . . . , 1XN , ω1 , . . . , ωp . Since Z = X  {c1 , . . . , cp }, by Proposition 7.26 the cospan for ψ2 is

in FinS . This is equal to the cospan that defines ψ2 .

 

The following observation says that, if N, p ≥ 1, then ψ2 is generated by 2-cells and 1-output wires.   Z  Corollary 9.15. Suppose ψ2 ∈ UWD X in (9.9) has N = |X|, p = Cψ  ≥ 1. Then there is a decomposition ψ2 =



     θ1 ◦2 θ2 ◦3 · · · ◦N+p−1 θN+p−1 ◦N+1 ω1 · · · ◦N+1 ωp

(9.13)

with: • each θi a 2-cell; • each ωj a 1-output wire; • each pair of parentheses starting on the left. Proof. This is true by the decomposition (9.12) above and Proposition 9.9 with n = N + p ≥ 2, applied to Θ.  

9.4 The Outer Undirected Wiring Diagram The purpose of this section is to establish a decomposition for the undirected wiring diagram ψ1 (9.8) that appeared in (9.10). This is the general version of

9.4 The Outer Undirected Wiring Diagram

201

the decomposition (9.3), so the reader may wish to refer back there for specific examples of the constructions below. Each of the constituent undirected wiring diagrams in this decomposition will be studied further in later sections. The goal is to decompose ψ1 into two undirected wiring diagrams in which the outer one, called φ1 below, is generated by loops (Definition 8.5), while the inner one, called φ2 below, is generated by splits (Definition 8.6). Recall Notation 9.1 for certain subsets of cables. Also recall from Remark 9.7 Y  that ψ1 ∈ UWD Z has neither (0, ≥ 0)-cables nor (1, 0)-cables. So ψ1 satisfies the hypotheses of the next definition.   B  Definition 9.16. Suppose ϕ = Cϕ , fϕ , gϕ ∈ UWD A is an undirected wiring diagram with • one input box A and (0,≥0) (1,0) = ∅ = Cϕ . • Cϕ We will write fϕ and gϕ as f and g, respectively. 1. For each cable c ∈ Cϕ  Cϕ≥3 , choose a wire ac ∈ f −1 c ⊆ A, where −1 −1 f c = f ({c}) is the set of f -preimages of c. 2. Define    f −1 c \ ac ∈ FinS W = B  f −1 Cϕ(2,0)  (9.14) (≥3,0)

±

c∈Cϕ(≥3,0) Cϕ≥3

in which 

f −1 c \ ac

 ±

    = f −1 c \ ac  f −1 c \ ac +

−

  is the coproduct of two copies of f −1 c \ ac . This W is the general version of the W in example (9.4). 3. Define    V = B  Cϕ(2,0)  f −1 c \ ac ∈ FinS . (9.15) (≥3,0)

c∈Cϕ

Cϕ≥3

This V is the general version of the set of cables between W and Y in example (9.4). 4. Define (9.16)

202

9 Decomposition of Undirected Wiring Diagrams

in which the restrictions of f1 to the coproduct summands of W are defined as follows. / B is the identity map. / Cϕ(2,0) is the map f . • f1 :     / f −1 c \ ac is the fold map for each c ∈ Cϕ(≥3,0)  • f1 : f −1 c \ ac ±     ≥3 Cϕ . That is, the restriction of f1 to each of f −1 c \ ac and f −1 c \ ac • f1 : B

f −1 Cϕ(2,0)

+

is the identity map.

−

This φ1 is the general version of the φ1 in example (9.4). 5. Define (9.17) as follows. We will use the equality B = g −1 Cϕ(1,≥1)  g −1 Cϕ(≥2,≥1) (0,≥0)

which is true because Cϕ

(1,0)

= ∅ = Cϕ

. For   f −1 c \ ac ∈ FinS



w ∈ W = g −1 Cϕ(1,≥1)  g −1 Cϕ(≥2,≥1)  f −1 Cϕ(2,0) 

(≥3,0)

c∈Cϕ

Cϕ≥3

±

(9.18) define

g2 (w) =

⎧ ⎪ f −1 g(w) ∈ A if w ∈ g −1 Cϕ(1,≥1); ⎪ ⎪ ⎪ ⎪ ⎨ag(w) ∈ f −1 g(w) ⊆ A if w ∈ g −1 Cϕ(≥2,≥1); w ⎪ ⎪ ⎪ ⎪ ⎪ ⎩ac ∈ f −1 c ⊆ A

  (2,0) if w ∈ f −1 Cϕ or w ∈ f −1 c \ ac ; +   ifw ∈ f −1 c \ ac . −

(1,≥1)

has a In the first line of this definition, we used the fact that each cable in Cϕ unique f -preimage in A. In the second line, a? was defined earlier in the current definition, using the fact that Cϕ(≥2,≥1) ⊆ Cϕ≥3 . This φ2 is the general version of the φ2 in example (9.4). Remark 9.17. Consider the previous definition. 1. The input soldering function f1 of φ1 is surjective. Furthermore, all the cables in φ1 are either (1, 1)-cables (namely, those cables in B ⊆ V ) or (2, 0)-cables (namely, those in V \ B). 2. The output soldering function g2 of φ2 is surjective because of the assumption (0,≥0) (1,0) Cϕ = ∅ = Cϕ .

9.4 The Outer Undirected Wiring Diagram

203

Theorem 9.18. In the context of Definition 9.16, there is a decomposition ϕ = φ1 ◦ φ2 .

(9.19)

Proof. It suffices to check that the operadic composition φ1 ◦φ2 ∈ UWD by the cospan

B  A

is given

(≥3,0) in FinS . Here the two coproducts are both indexed by all c ∈ Cϕ  Cϕ≥3 . By the definition of ◦ = ◦1 (7.12), we just need to check that the rectangle is a pushout (Definition 7.8) in FinS . It follows from direct inspection of each coproduct summand of W in (9.18) that the rectangle is commutative. Next, suppose given a solid-arrow commutative diagram

in FinS . We must show that there exists a unique map h that makes the diagram commutative. Recall that Cϕ = Cϕ(1,1)  Cϕ(2,0)  Cϕ(≥3,0)  Cϕ≥3 (0,≥0)

because Cϕ

(1,0)

= ∅ = Cϕ

. Define h : Cϕ

⎧ −1 ⎪ ⎪ ⎨αf (c) h(c) = β(c) ⎪ ⎪ ⎩α(a ) c

/ U as

if c ∈ Cϕ(1,1) ; if c ∈ Cϕ(2,0) ⊆ V ; if c ∈ Cϕ(≥3,0)  Cϕ≥3 .

204

9 Decomposition of Undirected Wiring Diagrams

One checks by direct inspection that (i) hf = α and hg3 = β and that (ii) h is the only such map.   As we mentioned just before Definition 9.16, the decomposition (9.19) applies Y  to ψ1 ∈ UWD Z defined in (9.8). In the next two sections, we will show that, up to name changes, φ1 is generated by loops (Proposition 9.27), and φ2 is generated by splits (Proposition 9.21).

9.5 Iterated Splits The purpose of this section is to show that φ2 (9.17) is either a name change or is generated by splits. First let us adopt the following convention, which is the undirected version of Convention 4.14. Convention 9.19. Using the three elementary relations (8.3)–(8.5), name changes (Definition 8.3) can always be rewritten on the outside (i.e., left side) of an iterated operadic composition in UWD. Moreover, using the elementary relation (8.1), an iteration of name changes can be composed down into just one name change. To simplify the presentation, in what follows these elementary relations regarding name changes are automatically applied wherever necessary. With this in mind, in the sequel we will mostly not mention name changes. Recall from Remark 9.17 that in φ2 (9.17), the input soldering function is the identity function and the output soldering function is surjective. So the following Proposition applies to φ2 . Motivation 9.20. The following result says that an undirected wiring diagram of the form

can be generated by splits. Proposition 9.21. Suppose A, B ∈ FinS , and (9.20) with fρ = IdA and gρ surjective. 1. If A = ∅, then ρ = 1∅ ∈ UWD 2. Suppose A = ∅.

∅ ∅

(Definition 7.12).

9.5 Iterated Splits

205

(i) If gρ is a bijection, then ρ is a name change τA,B . (ii) Otherwise, ρ is an iterated operadic composition of splits (Definition 8.6). Proof. We will write fρ and gρ as f and g, respectively. If A = ∅, then ρ is / ∅ o the cospan ( ∅ ∅ ), which is the ∅-colored unit in UWD. Suppose A = ∅. If g is a bijection, then by definition g is the name change τg −1 . So suppose g is surjective but is not a bijection. We must show that ρ is an iterated operadic composition of splits. The first step is to decompose ρ in such a way that each constituent undirected wiring diagram creates one group of output wires g −1 ai . Decompose A as A = A1  A2 ∈ FinS in which " !   • A1 = a ∈ A : g −1 a  = 1 ; " !   • A2 = a ∈ A : g −1 a  ≥ 2 = {a1 , . . . , an }. By assumption A2 = ∅. To decompose ρ we will use the following intermediate boxes. For each 1 ≤ i ≤ n + 1, define  g −1 ak  {ai , . . . , an } ∈ FinS . Di = A1 

 1≤k