Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems (Green Energy and Technology) [1st ed. 2023] 3031368428, 9783031368424

Table of contents :
Foreword
Preface
Acknowledgements
Contents
About the Author
Acronyms
Symbols
List of Figures
List of Tables
1 Introduction to Modular Energy Storage Systems
1.1 Intro
1.2 Cascaded Power Electronics Structures
1.3 Modular Reconfigurable Storages
1.4 Main Challenges
1.4.1 Level of Modularity
1.4.2 Modulation Strategy and Control
1.4.3 Topologies and Circuit Analysis
1.4.4 Better Monitoring and Protection
1.5 Main Objectives/Incentives
1.6 Book Outline
References
2 Selected Types of Energy Storage
2.1 Intro
2.2 Possible Types of Energy Storage
2.2.1 Capacitors
2.2.2 Batteries
2.2.3 Double-Layer Capacitors, Also Known as Super-Capacitors
References
3 Topology, Circuit Analysis, and Modeling
3.1 Intro
3.2 Generic Macro Circuits and Output Types
3.2.1 DC Structures
3.2.2 AC Structures
3.2.3 Hybrid or Unconventional Structures
3.3 Generic Micro Topologies and Interconnections
3.3.1 Dual Quadrant
3.3.2 Four Quadrant
References
4 Modulation and Scheduling Techniques
4.1 Intro
4.2 Modulation
4.2.1 Low-Frequency Modulation
4.2.2 Pulse-Width-Modulation Strategies
4.3 Scheduling
4.3.1 Scheduling/Balancing Strategies Based on Low-Switching-Rate Modulations
4.3.2 Scheduling/Balancing for PWM-Based Modulation Strategies
4.3.3 Sensorless Balancing for Diode-Clamped Topologies
4.3.4 Optimum Switching Loss for Topologies with Parallel Mode
4.3.5 Optimum Conduction Loss Scheduling
References
5 Novel Topologies and/or Techniques for Emerging Applications
5.1 Modular Reconfigurable Systems in Electromobility
5.1.1 Dynamically Reconfigurable DC Storages
5.1.2 Dynamically Reconfigurable AC Storages
References
6 Monitoring Methods
6.1 Intro
6.2 Terminal Voltage Estimation Techniques
6.2.1 Modules Without Parallel Connectivity
6.2.2 Modules with Parallel Connectivity
6.2.3 Simulation and Experimental Verification
6.3 Internal Resistance Estimation Techniques
6.3.1 Mathematical Model of the MMS Considering the Internal Resistances
6.3.2 Dual KF Estimator
6.3.3 Sequential Estimation Procedure and Relevant Discussions
6.3.4 Results
6.4 Discussion
References
7 Remaining Challenges and Future Potentials
7.1 Summary
7.2 Future Works
Appendix A Detailed Derivation of Non-ideal Gain for the Auxiliary Output

Citation preview

Green Energy and Technology

Nima Tashakor

Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems

Green Energy and Technology

Climate change, environmental impact and the limited natural resources urge scientific research and novel technical solutions. The monograph series Green Energy and Technology serves as a publishing platform for scientific and technological approaches to “green”—i.e. environmentally friendly and sustainable—technologies. While a focus lies on energy and power supply, it also covers “green” solutions in industrial engineering and engineering design. Green Energy and Technology addresses researchers, advanced students, technical consultants as well as decision makers in industries and politics. Hence, the level of presentation spans from instructional to highly technical. **Indexed in Scopus**. **Indexed in Ei Compendex**.

Nima Tashakor

Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems

Foreword by Stefan Götz

Nima Tashakor Department of Electrical and Computer Engineering Rheinland-Pfälzische Technische Universität (RPTU) Kaiserslautern Kaiserslautern, Germany Duke University Durham, USA

ISSN 1865-3529 ISSN 1865-3537 (electronic) Green Energy and Technology ISBN 978-3-031-36842-4 ISBN 978-3-031-36843-1 (eBook) https://doi.org/10.1007/978-3-031-36843-1 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

I dedicate this work to my family, which has supported me all these years, and to my wonderful wife, who is always in my corner, even in a circle. I have no doubt I could not have achieved this without her help and never-ending support. ‘Mamnoon Elham jan!’ My family has always believed in me, motivated me, and supported me. ‘Mom’ is another word for selflessness and kindness for me. ‘Dad’ is the solution to every problem. Everybody needs a baby ‘Brother’ as funny and loyal as mine. ‘Mamnoon Maman, Baba, va Pouya!’ I am also grateful to my in-laws for their understanding and support, which have become my second family. ‘Mamnoon Madar, Pedar, Elahe, Alireza, va Pouriya!’

Foreword

Modular power electronic circuits form a scientifically and industrially promising field. Such modular circuits control significant amounts of electrical power using a larger number of small and inexpensive transistors, instead of relying on only a few large transistors. Modular electronic concepts have received enormous attention in power electronics in recent years and have been implemented in numerous applications. The use of a larger number of identical circuit modules for the conversion and regulation of larger power allows for the exploitation of scale effects and simplified manufacturing. The challenge is twofold, specifically finding regular circuit structures, which are flexible but cost-efficient, and managing the many degrees of freedom provided by the many combinatorial switch states, which complicates the full exploitation of optimality and requires good enough heuristics. Such circuits and methods have various applications from grid converter and grid support systems for managing the challenges of the general electrification and the electronification of the grids to large drives. In some of these applications, there is no alternative to modular circuits. Most interestingly, however, the current enormous technological development of low-voltage transistors enables dynamically reconfigurable energy storage systems, such as batteries, double-layer capacitors, and fuel cells. Such dynamically reconfigurable storage systems break the hard-wired series-parallel configuration of conventional systems for grid storage and electric vehicle applications apart. As analysed in this book, the possible dynamic reconfiguration of the series-parallel structure allows for overcoming several major limitations of conventional storage systems. However, this rather deep change of conventional battery structures requires solutions and novel concepts from control to integration and for the entire periphery of batteries for the exploitation of all of its advantages. The book provides an examination of various circuit concepts and designs that underpin the development of both modular power electronic converters and reconfigurable energy storage systems. It covers a wide range of topics, including hardwaresafe and self-balancing module types, sensorless operation methods, and advanced modulation techniques for more conventional power conversion with modular circuits and capacitors as storage elements in the modules, such as cascaded H bridges and modular multilevel converters. Previous modular multilevel converters mostly served vii

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Foreword

in shielded-off high-voltage grid applications that could not be solved otherwise, e.g., due to extreme space or quality requirements as in high-voltage dc converter stations downtown and converters on small offshore wind-farm platforms without space for large filters so that the effort of monitoring of every module was acceptable. In many emerging applications, however, a reduction of the number of sensors and data as well as of the strong software-dependency of operation turns appealing, while safety and self-balancing as presented here can be the important missing piece. The book explores the use of modular electronics to estimate a number of important properties of individual modules, offering an innovative approach that relies on a limited number of standard sensors rather than the numerous high-bandwidth, high-quality sensors often proposed in this field. On the battery side, the book studies the many gaps and necessary changes that the fundamental concept of reconfigurable direct or alternating current energy storage systems entails. One of the key strengths of the book is its focus on integrating peripherals, which are often overlooked in other works but are crucial for understanding the full complexity of these systems. For example, the book offers detailed analyses and solutions for low-voltage auxiliaries in electric vehicles, demonstrating how reconfigurable battery systems can be integrated with vehicle electronics and architectures. Previous work on reconfigurable batteries in cars typically ignored the aspect that the drive train is not an isolated element in a car but the main energy source for numerous units and elements in the car. Thus, the drive train strongly determines the entire architecture. Both reconfigurable dc batteries that can change or stabilize the supply voltage as well as ac approaches that directly generate multiphase ac output for motors have to also supply the other units with various power and voltage levels. A solution that cannot provide these supplies in a compact and cost-efficient way will likely not have any future. Kaiserslautern, Germany April 2023

Stefan Goetz

Preface

The latest developments in high-performance low-voltage semiconductors, driven by the increasing number of consumer electronics, higher penetration of renewable energies into the modern grids, and electrification of the automotive industry, enable the formation of highly flexible modular power electronics with high power density and low cost. Instead of using one central high-power component, which requires relatively expensive power semiconductors manufactured in small quantities, a high number of identical modules can exploit the economy-of-scales effect. Additionally, such modular electronics can increase controllability by offering naturally redundant states that, if correctly exploited, leads to exponentially higher degrees of freedom (DoF). The high number of DoF allows the integration of various functions that conventionally require separate electronic components or are not integrable in the same hardware. A few of these functions or capabilities are better power distribution control, improved thermal control, better energy balancing, improved efficiency, better fault tolerance, and even higher reliability or resilience. However, the high number of DoFs also requires novel flexible control and monitoring approaches that can exploit these capabilities and trade-off various novel objectives while maintaining the costs at acceptable levels. Similar to the benefits of modular power electronics, state-of-the-art energy storage systems can also benefit from this approach. The current storage systems, batteries in particular, are large and bulky modules that are hard-wired in a fixed arrangement. Despite advancements in storage technology, many traditional challenges such as strict protection and safety requirements, complex monitoring, suboptimal balancing routines, lower efficiency, weakest-cell effect, low power density, and slow charging speed still persist. Although the continuous increase of capacity, voltage, and power levels in many applications has increased the power and energy densities, as well as the charging speed, it has introduced newer challenges such as thermal balancing, and high-voltage variation between full-charge and depletion, or made some of the previous issues more severe. Nevertheless, further optimizing the chemistry might not be the answer to all problems.

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Preface

Recent advancements in modular power electronics, on the other hand, have led to the development of storage-integrated modular electronics. These systems divide the bulky storage system into multiple modules and integrate them with power electronics, allowing for dynamic and rapid reconfiguration of the complete structure. While this concept is very interesting, there are still many challenges and unanswered questions regarding, modeling, topology, modulation, control, and monitoring. This book studies these aspects and discusses some of the open questions in this field. The book first provides a general overview of the main issues, incentives, and objectives. Then it studies state-of-the-art modular converters and storage systems. Additionally, it improves the electronics topology of current modular reconfigurable storages and converters by integrating parallel connectivity, reducing the semiconductor count by eliminating irrelevant states, and improving performance through higher function integration. Three of the main module topologies extensively covered in this book are diode-clamped half-bridge, switch-clamped halfbride, and the unidirectional full-bridge module which can offer significant advantages, e.g., self-balancing, improved efficiency, and higher reliability, with minimum added costs. Additionally, the main macrostructures including single-star, doublestar, polygon, and open-polygon macrostructures are introduced, and their advantage and disadvantages are discussed for each application in combination with each module topology. Integrating different storage types with electronics can affect the behavior of the module and consequently impact the overall model of the system. Additionally, the discrete reconfiguration of modules changes the load pattern of the modules and affects their equivalent circuit model. Therefore, this book studies the inherent characteristics of storage modules and the impact of modulations on the modeling process. Additionally, it develops models of modular reconfigurable storage systems with different degrees of accuracy for different storage types that help in better understanding the dynamics of the system under balanced and imbalanced conditions. The book further establishes novel optimum or near-optimum methods for exploiting the DoF to achieve higher efficiency, more function integration, better equilibrium, or output quality, while considering the feasibility and applicability of these approaches in a real-world application. After a detailed analysis of different modulation and scheduling techniques, this book describes new methods, enhances the state-of-the-art, or simplifies the implementation complexities of the modulators and schedulers. One of the modulation strategies presented in this book is level adjusted phase-shifted carrier modulation which allows for stable sensorless operation with minimum balancing loss. Furthermore, the concepts of optimalconduction and optimal-switching schedulers based on the nearest-level modulation are comprehensively studied and compared with the state-of-the-art. The book also presents the concept of interconnected multi-port systems through integrating novel modulation techniques and the acquired understanding of the behaviour of dynamically reconfigurable storages. The presented concepts can significantly reduce the number of energy conversion stages as well as the final footprint

Preface

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of the system, reduce the number of required controlled semiconductors, and ultimately save costs. Within this context, the concept of open-end polygon for multiphase machines is developed and novel control strategies for supplying multiple phases and loads are presented. Furthermore, novel control strategies to control multiple interconnected ports from the same reconfigurable structure are introduced and verified. The book correspondingly develops more accurate models through analysis of the inherent differences of the topologies with parallel connectivity compared to the state-of-the-art. It also presents novel monitoring techniques based on estimators that can significantly reduce the number of required sensors and the required data communication bandwidth. Namely, a novel dual-Kalman-filter (dual KF) estimator is presented that can estimate the equivalent resistance and open-circuit voltage of every storage with only two sensors at the output of the system. Moreover, the book describes a more accurate state-space model for the diode-clamped topology that takes into account the clamping dynamics as well as possible balancing efforts. The presented compensated model in combination with a state estimator offers significant potential for simplifying the monitoring subsystem. Comprehensive simulations allow for studying the behavior of the system in controlled conditions with minimum noise and nonidealities present, which in all cases support the provided analysis and discussions. Additionally, each new concept and novel feature is verified via experiments and measurements from developed lab prototypes that further confirm the analysis and simulations. Lastly, the book provides general research directions to extend the concept of modular reconfigurable converters and storage systems. Selected possible research directions are the inclusion of other types of energy storage such as fuel cells and super-capacitors, expanding the developed models for more complex storage types, and investigation of the further increase of module utilization by integrating additional functionalities, expanding the monitoring functionalities to include fault detection and prognosis, investigating the possibility of distributed controllers in combination with novel control strategies. Kaiserslautern, Germany

Nima Tashakor

Acknowledgements

I want to thank my colleagues and friends Davood, Axel, Masoud, Max, Akshata, Alex, Steffen, Pouyan, Mahdi, Jiawei, and many others for creating a friendly and fun working environment and for their help during my Ph.D. I extend special thanks to Udo Oppermann, our laboratory technician, for his help at work and patience with my German language skills. Over the years, I got to appreciate his calm, supportive attitude toward work. I cannot think of colleagues and do not mention Stephanie Jung (Steffi for us). I am grateful for all her support in wading through the German bureaucracy, which without her I would have been certainly lost, and for her always upbeat presence. Except for Mondays, who likes Mondays anyways?! I also want to acknowledge the support of my fellow scholars Jan and Tomas Kacetl, Jingyang Fang, Farshid Naseri, and Bita Arabsalmanabadi. They have collaborated with me on parts of this work and helped improve its quality. As an advisor for multiple bachelor’s and master theses, I got to know and appreciate many students of high caliber. They have certainly contributed to developing my work to the current level. Above all, I am genuinely grateful for my advisor and friend Stefan Götz, who has always supported me throughout my studies and pushed me to achieve higher. It was indeed a privilege to know him, and I have learned a lot from him; above all, I learned hard work, dedication, and integrity.

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Contents

1 Introduction to Modular Energy Storage Systems . . . . . . . . . . . . . . . . . 1.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Cascaded Power Electronics Structures . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Modular Reconfigurable Storages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Main Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Level of Modularity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Modulation Strategy and Control . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 Topologies and Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Better Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . 1.5 Main Objectives/Incentives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Book Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 1 2 5 8 8 8 9 9 9 10 11

2 Selected Types of Energy Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Possible Types of Energy Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Batteries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.3 Double-Layer Capacitors, Also Known as Super-Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17 18 18 18 19 31 34

3 Topology, Circuit Analysis, and Modeling . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Generic Macro Circuits and Output Types . . . . . . . . . . . . . . . . . . . . . . 3.2.1 DC Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 AC Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.3 Hybrid or Unconventional Structures . . . . . . . . . . . . . . . . . . . 3.3 Generic Micro Topologies and Interconnections . . . . . . . . . . . . . . . . . 3.3.1 Dual Quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.2 Four Quadrant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

37 38 38 38 42 55 55 56 74 77 xv

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Contents

4 Modulation and Scheduling Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . 81 4.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.2 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 4.2.1 Low-Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.2.2 Pulse-Width-Modulation Strategies . . . . . . . . . . . . . . . . . . . . . 87 4.3 Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 4.3.1 Scheduling/Balancing Strategies Based on Low-Switching-Rate Modulations . . . . . . . . . . . . . . . . . . . 92 4.3.2 Scheduling/Balancing for PWM-Based Modulation Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 4.3.3 Sensorless Balancing for Diode-Clamped Topologies . . . . . . 95 4.3.4 Optimum Switching Loss for Topologies with Parallel Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 4.3.5 Optimum Conduction Loss Scheduling . . . . . . . . . . . . . . . . . . 128 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5 Novel Topologies and/or Techniques for Emerging Applications . . . . . 5.1 Modular Reconfigurable Systems in Electromobility . . . . . . . . . . . . . 5.1.1 Dynamically Reconfigurable DC Storages . . . . . . . . . . . . . . . 5.1.2 Dynamically Reconfigurable AC Storages . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

145 146 149 194 204

6 Monitoring Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Intro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Terminal Voltage Estimation Techniques . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Modules Without Parallel Connectivity . . . . . . . . . . . . . . . . . . 6.2.2 Modules with Parallel Connectivity . . . . . . . . . . . . . . . . . . . . . 6.2.3 Simulation and Experimental Verification . . . . . . . . . . . . . . . . 6.3 Internal Resistance Estimation Techniques . . . . . . . . . . . . . . . . . . . . . 6.3.1 Mathematical Model of the MMS Considering the Internal Resistances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Dual KF Estimator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.3 Sequential Estimation Procedure and Relevant Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.3.4 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

209 210 211 211 213 217 223 226 228 233 235 243 243

7 Remaining Challenges and Future Potentials . . . . . . . . . . . . . . . . . . . . . . 249 7.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 7.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Appendix A: Detailed Derivation of Non-ideal Gain for the Auxiliary Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

About the Author

Nima Tashakor was born in 1990 in Shahrekord, Iran. He obtained his B.Sc. degree in Electrical Power Engineering from Isfahan University in Isfahan, Iran, in 2013. His undergraduate research focused on harmonic sources in electrical grids and methods for filtering them. In 2015, Tashakor earned his M.Sc. degree in Electrical Power Engineering from Shiraz University in Shiraz, Iran. Graduating Summa Cum Laude, he ranked at the top of his class in the Institute of Electrical Power and Control Engineering, boasting a cumulative GPA of 18.73 out of 20. Throughout his master’s program, Tashakor developed innovative designs for electric vehicle chargers and protective devices based on power electronics for modern electrical grids. Following his master’s degree, he served as a research assistant at Shiraz University for three years, collaborating on multiple industrial research projects. Concurrently, he worked as a development engineer, focusing on the design and analysis of high-reliability battery packs and corresponding power electronic devices. Tashakor pursued his Ph.D. at the Technical University of Kaiserslautern, Germany, from 2019 to 2022. During this time, he also collaborated with Duke University, USA, and Aalborg University, Denmark, as a guest researcher. In 2021, he was awarded the DAAD grant for his collaboration with Aalborg University, followed by the DAAD prize for outstanding achievements of international students in 2022. Throughout his doctoral studies, Tashakor published and co-authored more than 15 peer-reviewed journal articles, contributed over 15 papers to six conferences, and received the IES-SYPA grant. Additionally, he filed seven patent applications during his Ph.D. and graduated Summa Cum Laude in 2022. Tashakor’s research interests encompass power electronics and energy storage systems. His work primarily involves the development, control, and monitoring of modular converters and storage systems. Additionally, he explores the application of machine learning and smart controllers in power electronics applications.

xvii

Acronyms

ADC CHB CNLM DoD DoF ECM EIS EMF ESPM ESR EV FACTS FB FET FPGA FSEM GaN HB HFT HVDC IGBT KF KMC KVL LAPSC LSC MESS MLC MMC MMS MMSPC

Analog-to-Digital Converter Cascaded H-Bridge Conventional Nearest Level Modulation Depth of disCharge Degree of Freedom Equivalent Circuit Model Electrochemical Impedance Spectroscopy Electromotive Force Enhanced-Single-Particle Model Equivalent Series Resistance Electric Vehicle Flexible AC Transmission System Full-Bridge Field-Effect Transistor Field Programmable Gate Array Fractional Single-Electrode Model Gallium Nitride Half-Bridge High-Frequency Transformer High-Voltage Direct-Current Insulated-Gate Bipolar Transistor Kalman Filter Kinetic Monte Carlo Kirchhoff’s Voltage Law Level-Adjusted Phase-Shifted Carrier Level-Shifted Carrier Modular Energy Storage System Multilevel Converter Modular Multilevel Converter Modular Multilevel Energy Storage Modular Multilevel Series/Parallel Converter xix

xx

MOSFET NLM OCV P2D P3D PDE PF PI PID PSANLM PSAPSC PSC PSO PU PWM RMS SC SELV SHE SHM SiC SIL SoC SOH SPM THD

Acronyms

Metal–Oxide–Semiconductor Field-Effect Transistor Nearest Level Modulation Open-Circuit Voltage Pseudo-Two-Dimension Pseudo-Three-Dimension Partial Differential Equations Power Factor Proportional–Integral Proportional–Integral–Derivative Phase-Shifted Arms Nearest Level Modulation Phase-Shifted Arms Phase-Shifted Carrier Phase-Shifted Carrier Particle Swarm Optimization Per Unit Pulse Width Modulation Root Mean Square Super-Capacitor Safety Extra Low Voltage Selective Harmonic Elimination Selective Harmonic Mitigation Silicon Carbide Safety Integrity Level State of Charge State of Health Single-Particle Model Total Harmonic Distortion

Symbols Q Q res Vm and i m vt and i t v p and i p VC Vm NC N ph N L τ ...

Electrical charge Remaining electrical charge Rated voltage of a module and its current Terminal voltage and current of a module Voltage and current of a reconfigurable storage system Voltage of a capacitor module Vector of modules’ voltages in the string/arm Number of carriers Number of phases, legs, or ports Number of modules in the whole string Number of modules in one specific port (L  Nc or N ) Time constant Ceiling function

Acronyms

... Cj rj Lj U/L ϕ θ AB A.B mx m (k) j , m j (t)

xxi

Floor function Capacitance of the jth module or its corresponding carrier Internal resistance of the jth module Inductance corresponding to the jth interconnection Upper or Lower arms/strings Phase-shift of a carrier or reference signal in rad Phase difference of corresponding carriers from multiple phases in rad Matrix product of A and B matrices Element-wise product of A and B matrices Amplitude of the xth modulation index or reference signal in an ac system Instantaneous modulation reference of the jth module at sample k or time t

List of Figures

Fig. 1.1 Fig. 1.2 Fig. 1.3 Fig. 1.4 Fig. 2.1 Fig. 2.2 Fig. 2.3 Fig. 2.4 Fig. 2.5 Fig. 2.6 Fig. 2.7 Fig. 2.8 Fig. 2.9 Fig. 2.10 Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Fig. 3.5 Fig. 3.6 Fig. 3.7

Generic topology of a dual-arm MMC topology . . . . . . . . . . . . . Generic topology of conventional HB and FB modules . . . . . . . . Overview of different control levels in an MMC . . . . . . . . . . . . . Intuitive representation of an MMS as well as hard-wired energy storage system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit model of a capacitor . . . . . . . . . . . . . . . . . . . . . Comparison of energy density versus the specific energy of different types of battery (with permission from [6, 7]) . . . . . . RC ECMs: a zero-Order ECM b first-Order ECM c second-Order ECM d N th-Order ECM . . . . . . . . . . . . . . . . . . . Randles’ battery model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bidirectional second-order ECM with self-discharge . . . . . . . . . . Battery model capable of runtime prediction, presented by [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nonlinear battery model presented by [32] for SoC estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of various battery models . . . . . . . . . . . . . . . . . . . . . Three RC branch proposed by [43] . . . . . . . . . . . . . . . . . . . . . . . . The extension of the three-branch model proposed by [41] . . . . . The single-string dc structure of modular reconfigurable storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The single-string dc structure of modular reconfigurable storage with parallel functionality . . . . . . . . . . . . . . . . . . . . . . . . . Profile of modulation indices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Profiles of the dc-link voltage and the inductor current. i.e., the main state variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage profile of the first RC network of Module 2 . . . . . . . . . . Voltage profile of the second RC network of Module 3 . . . . . . . . Macro structure of single-arm topology, also known as single-star in three-phase systems . . . . . . . . . . . . . . . . . . . . . . .

3 3 5 6 19 20 26 27 27 28 28 29 32 33 39 40 42 43 43 43 44

xxiii

xxiv

Fig. 3.8 Fig. 3.9 Fig. 3.10 Fig. 3.11 Fig. 3.12 Fig. 3.13 Fig. 3.14

Fig. 3.15 Fig. 3.16 Fig. 3.17 Fig. 3.18 Fig. 3.19 Fig. 3.20 Fig. 3.21 Fig. 3.22 Fig. 3.23 Fig. 3.24 Fig. 3.25 Fig. 3.26 Fig. 3.27 Fig. 3.28 Fig. 3.29

List of Figures

Macro structure of dual-arm topology, also known as double-star in three-phase systems . . . . . . . . . . . . . . . . . . . . . . Macro structure of polygon topology, also known as the delta in three-phase systems . . . . . . . . . . . . . . . . . . . . . . . . Macro structure of cascaded-arms or open-end polygon topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-phase topology of an MMC without parallel connection between modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual-arm single-phase structure with the possibility of parallel connection among modules . . . . . . . . . . . . . . . . . . . . . Conventional single-phase single-arm structure of a modular reconfigurable storage . . . . . . . . . . . . . . . . . . . . . . . . Single-phase single-arm structure of modular reconfigurable storage with parallel connectivity among modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conventional three-phase delta-structure of modular reconfigurable storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-phase delta-structure of modular reconfigurable storage with parallel connectivity among modules . . . . . . . . . . . . Generic ac structure based on open-end polygon topology with a single connection among modules . . . . . . . . . . . . . . . . . . . Generic ac structure based on open-end polygon topology with multiple connections among modules . . . . . . . . . . . . . . . . . . Dual-quadrant modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Different operating modes of a half-bridge module . . . . . . . . . . . Possible operation modes of a unidirectional full-bridge module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Semi-controlled bypass mode in a unidirectional FB with parallel connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A unit of N p paralleled modules. © 2021 IEEE. Reprinted, with permission, from [19, 30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit of a unit with N p paralleled modules. © 2021 IEEE. Reprinted, with permission, from [19, 30] . . . . . . Operation modes of a switch-clamped module . . . . . . . . . . . . . . . Generic circuit of a switch-clamped module with low-current clamping branch . . . . . . . . . . . . . . . . . . . . . . . . . Operation modes of a switch-clamped module if S( j+1)2 is on. © 2021 IEEE. Reprinted, with permission, from [15] . . . . . . Equivalent electrical circuit of the modules when S( j+1)2 is on. © 2021 IEEE. Reprinted, with permission, from [15] . . . . . . Representative voltage and current waveforms of a balancing operation in a switch-clamped half-bridge module. © 2021 IEEE. Reprinted, with permission, from [15] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

44 45 45 47 49 51

51 52 53 54 54 56 57 58 59 59 60 62 63 64 65

65

List of Figures

Fig. 3.30 Fig. 3.31 Fig. 3.32

Fig. 3.33 Fig. 3.34

Fig. 3.35 Fig. 3.36 Fig. 3.37 Fig. 4.1 Fig. 4.2 Fig. 4.3 Fig. 4.4 Fig. 4.5 Fig. 4.6 Fig. 4.7 Fig. 4.8

Fig. 4.9 Fig. 4.10

Fig. 4.11

Fig. 4.12

Fig. 4.13

Operation modes of a switch-clamped module if S( j+1)2 is off. © 2021 IEEE. Reprinted, with permission, from [15] . . . . . . Simplest topology for a diode-clamped module . . . . . . . . . . . . . . Possible modes of operation for the diode-clamped modules. © 2021 IEEE. Reprinted, with permission, from [12, 37] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent electrical circuits during the balancing operation . . . . Intuitive balancing process for balancing of two modules through the clamping branch. © 2021 IEEE. Reprinted, with permission, from [12, 37] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Different operating modes of full-bridge module . . . . . . . . . . . . . Different operating modes of the dual full-bridge module . . . . . . Different operating modes of each interconnection with dual full-bridge modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resulted phase voltage waveforms for CNLM and PSANLM techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intuitive representation of carriers in conventional PSC modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intuitive representation of carriers in conventional PSC modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic shape of output in case of a symmetric PSC modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of the resulted voltages using NLM methods and PSC modulation with similar switching rate . . . . . . . . . . . . . Integrated balancing loop for PWM-based modulation strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integrated weighted balancing strategy for PWM-based modulation strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intuitive representation of the level-adjusted carriers in a dual-arm structure. © 2021 IEEE. Reprinted, with permission, from [24, 25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of level-adjustment on the module pulses. © 2021 IEEE. Reprinted, with permission, from [24, 25] . . . . . . . . . . . . . Output voltages for different scenarios using LAPSC modulation. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module voltages with balanced parameters and zero level-adjustment (x = 0). © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module voltages with balanced parameters and minimum level-adjustment (x = 0.002). © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Module voltages with mismatches between the modules’ capacitors and level-adjustment x = 0 → 0.02 at t = 5s. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . .

xxv

66 69

70 71

71 75 76 77 87 88 89 89 91 94 94

95 96

104

105

106

106

xxvi

Fig. 4.14

Fig. 4.15

Fig. 4.16

Fig. 4.17

Fig. 4.18

Fig. 4.19

Fig. 4.20

Fig. 4.21 Fig. 4.22

Fig. 4.23

Fig. 4.24

Fig. 4.25

Fig. 4.26

List of Figures

Module voltages with different capacitance and self-discharge rates, and level-adjustment x = 0 → 0.02 at t = 7s. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The profile of power loss for the LAPSC modulation versus x . © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured waveforms of the phase current and phase voltage with the clamping circuit during standard operation, x = 2% and m x = 0.95. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . Measured waveforms of the phase current and phase voltage with the clamping circuit during standard operation, x = 2% and m x = 0.75. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . Measured phase voltage and current with LAPSC modulation and mismatched modules a m = 0.95, unity PF; b m = 0.75, unity PF; c m = 0.95, PF = 0.93; d m = 0.95, with PF and load variation. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . . . . . . . . . . . . . . Measured voltage profiles of the modules in both arms a initially imbalanced modules; b m = 0.75, unity PF. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . The voltage and current waveforms of the clamping branch as well as the modules during the charge equalization. © 2021 IEEE. Reprinted, with permission, from [24] . . . . . . . . . The intuitive representation of the scheduler for four modules with parallel connectivity [16] . . . . . . . . . . . . . . . . . . . . The flowchart of the halving-doubling scheduler with optimal switching in combination with NLM and other modulation methods [16] . . . . . . . . . . . . . . . . . . . . . . . . Structure of a dual-arm single-phase dual-arm structure with unidirectional half-bridge modules. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . Output voltages based on the optimum switching scheduler in combination with NLM techniques. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . Dynamics of capacitor voltages and balancing currents using PSC modulation with an initial voltage imbalance of 0.8 pu. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamics of capacitor voltages and balancing currents using CNLM modulation with an initial voltage imbalance of 0.8 pu. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

107

107

108

108

109

110

111 113

114

115

120

121

121

List of Figures

Fig. 4.27

Fig. 4.28

Fig. 4.29

Fig. 4.30

Fig. 4.31 Fig. 4.32

Fig. 4.33 Fig. 4.34

Fig. 4.35

Fig. 4.36

Fig. 4.37

Fig. 4.38

Dynamics of capacitor voltages and balancing currents using PSANLM modulation with an initial voltage imbalance of 0.8 pu. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage envelope and peak current amplitude for a system with 20% spread in the modules’ parameters. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . Laboratory testbench for evaluating the halving-doubling scheduler. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured phase and module voltages with PSC, CNLM, and PSANLM methods. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THDV for different loads and switching rates. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . Power losses for various switching schemes at varying operating points. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . THDv verses losses for various loads. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . . Output voltages as well as their corresponding THD values: a Waveforms of the output voltage for various modulation schemes, b THD waveforms using a moving window. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modules’ voltages and currents: a Maximum voltage imbalance among modules for each scheme; b Mean absolute value if the capacitor currents averaged over a moving window. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of power loss for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . Comparison of conduction losses for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . Comparison of switching losses for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . .

xxvii

122

123

123

124 124

125 125

134

135

135

136

136

xxviii

Fig. 4.39

Fig. 4.40

Fig. 4.41

Fig. 4.42

Fig. 4.43

Fig. 4.44

Fig. 4.45

Fig. 5.1

Fig. 5.2 Fig. 5.3 Fig. 5.4

Fig. 5.5

List of Figures

Comparison of power loss for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are imbalanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . Comparison of power loss for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and inductive PF ≈ 0.87. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental measurements according to the presented scheduler with unity PF, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . Experimental measurements using PSC modulation with unity PF, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . Experimental measurements using the presented scheduler for inductive loads with PF ≈ 0.87, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental measurements using PSC modulation for inductive loads with PF ≈ 0.87, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spectrum of the harmonics in the resulted voltage according to the PSC modulation and presented scheduler with NLM modulation, a ForPSC modulation, b For the presented scheduler. © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conventional electrical circuit of an EV where the hardwired batteries directly supply the inverter (modified based on [12]) . . . . . . . . . . . . . . . . . . . . . . . Conventional electrical circuit of an EV with a hardwired storage and regulated dc-link (modified based on [12]) . . . . . . . . Electrical circuit of an EV with modular reconfigurable batteries and separate auxiliary (modified based on [12]) . . . . . . Electrical circuit of an EV with modular reconfigurable batteries and separate unidirectional auxiliary (modified based on [12]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical circuit of the envisioned EV with modular reconfigurable batteries and integrated auxiliary output (modified based on [12]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

137

137

138

139

140

140

141

147 148 150

152

153

List of Figures

Fig. 5.6 Fig. 5.7

Fig. 5.8

Fig. 5.9

Fig. 5.10

Fig. 5.11 Fig. 5.12 Fig. 5.13 Fig. 5.14

Fig. 5.15

Fig. 5.16 Fig. 5.17 Fig. 5.18 Fig. 5.19 Fig. 5.20

Fig. 5.21

Fig. 5.22

Fig. 5.23

The electrical circuit of the EV with integrated auxiliary output [56] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical circuit of the envisioned EV with modular reconfigurable batteries with the integrated auxiliary output in series to the dc-link capacitor (modified based on [12]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The electrical circuit of the EV with integrated auxiliary output and reduced number of switch-sets. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . Intuitive representation of carriers in conventional PSC modulation. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graphic illustration of the carriers in conventional PSC modulation and the effective equivalent carrier waveform. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . Graphical representation of the increased effective switching frequency due to the PSC modulation . . . . . . . . . . . . . Circuit diagram of the integrated auxiliary unit. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . Intuitive representation of Vin with different D . . . . . . . . . . . . . . . Equivalent circuit diagram of the integrated auxiliary unit from the primary side. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Developed controller with symmetric PSC modulation and reduced number of switch-sets in discharge mode. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . Developed controller with symmetric PSC modulation and reduced number of switch-sets in charge mode . . . . . . . . . . . Developed controller with symmetric PSC modulation and reduced number of switch-sets in idle mode [69, 70] . . . . . . Generic curve of the terminal voltage of the battery versus its SoC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain variations of the auxiliary power unit with respect to D . . . Voltage and current waveforms of both ports for the simulated system. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . The pulsating voltage of the modular reconfigurable battery. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The control signals as well as the outputs’ deviations from reference values. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Balancing performance of the integrated auxiliary when both ports are actively discharging the modules (P1 = 25 kW, P2 = 3 kW) [69, 70] . . . . . . . . . . . . . . . . . . . . . . . .

xxix

154

155

156

157

157 158 158 159

160

163 164 164 165 166

168

168

169

169

xxx

Fig. 5.24

Fig. 5.25

Fig. 5.26

Fig. 5.27 Fig. 5.28 Fig. 5.29

Fig. 5.30 Fig. 5.31 Fig. 5.32 Fig. 5.33

Fig. 5.34

Fig. 5.35

Fig. 5.36

Fig. 5.37 Fig. 5.38

Fig. 5.39 Fig. 5.40

List of Figures

Voltage and current profiles of the reconfigurable-battery ports during charge. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Laboratory testbench for the dual-port setup with symmetric PSC. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured voltage and currents at the semi-controlled main port during discharge. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured voltage and currents at the auxiliaries. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . Voltage deviations from the reference values. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . The measured voltages at the primary and secondary terminals of the HFT. © 2023 IEEE. Reprinted, with permission, from [69, 70] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic structure of a string with interconnected ports. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . ECM of a generic string of modular reconfigurable storage elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The electrical circuit of a non-isolated port. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . The ECM of a non-isolated port from the secondary side of the transformer. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ac and dc components of the resulted voltage using symmetric PSC modulation. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intuitive representation of carriers in case of an asymmetric PSC modulation. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic voltage shape of a string with an asymmetric PSC modulation. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Normalized output voltages with respect to m. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . Proposed control strategy for the dual-port system with symmetric PSC. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic controller for multiple non-isolated and isolated ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Possible gain profiles with asymmetric PSC with nine-module string. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . .

170

171

172 172 173

173 174 175 176

176

177

179

180 183

184 185

186

List of Figures

Fig. 5.41

Fig. 5.42

Fig. 5.43

Fig. 5.44

Fig. 5.45

Fig. 5.46

Fig. 5.47

Fig. 5.48 Fig. 5.49

Fig. 5.50

Fig. 5.51

Fig. 5.52

Fig. 5.53 Fig. 5.54 Fig. 5.55 Fig. 5.56

The developed control strategy for a dual-port system with asymmetric PSC modulation. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . Voltage and current profiles of the high-power non-isolated port supplying the inverters. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and current profiles of the low-power isolated port with symmetric PSC. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and current profiles of the high-power non-isolated port with asymmetric PSC. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage and current profiles of the low-power isolated port with asymmetric PSC. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation index for modules only supplying the main load (i.e., Load1 ). © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation index for the shared modules between the two ports. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Picture of the testbench. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured voltage and current profiles of the high-power non-isolated port with asymmetric PSC. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . Measured voltage and current profiles of the low-power isolated port with asymmetric PSC. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . Measured voltage and current profiles of the two outputs with load variations in auxiliaries. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . Measured voltage and current profiles of the two outputs with load variations in auxiliaries based on asymmetric PSC modulation. © 2023 IEEE. Reprinted, with permission, from [71, 72] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Intuitive representation of a multi-port system with a main load and multiple secondary loads . . . . . . . . . . . . . . . . . . . . . . . . . Intuitive representation of a string with multiple decoupled ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase-shift distribution with zero phase difference between corresponding carriers of different ports . . . . . . . . . . . . . Optimal phase-shift distribution in a three-port system with three modules in each port . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxxi

188

189

189

190

190

191

191 192

193

193

193

194 196 197 198 198

xxxii

Fig. 5.57 Fig. 5.58 Fig. 5.59

Fig. 5.60 Fig. 5.61

Fig. 6.1

Fig. 6.2

Fig. 6.3

Fig. 6.4

Fig. 6.5

Fig. 6.6

Fig. 6.7

Fig. 6.8 Fig. 6.9 Fig. 6.10

Fig. 6.11 Fig. 6.12

List of Figures

Illustration of aligning the pulse edges with zero equivalent voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The shape of the triangular carrier and its modulation index . . . . Example of controlling the phase difference between the first carriers of every port to generate additional outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macro structure of the additional dc output in the single-string multi-phase system . . . . . . . . . . . . . . . . . . . . . Extended macro structure of multi-phase ac smart battery with multiple integrated auxiliary outputs for electromobility applications (modified from [12]) . . . . . . . . . Estimation results of the capacitor voltages in the simulated balanced system © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maximum error in the simulated balanced system using conventional and developed estimators © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . . . . . . . Estimation results of the capacitor voltages in the simulated balanced system without any balancing effort © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . Maximum error in the simulated imbalanced system using conventional and developed estimators without any balancing effort © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimation results of the capacitor voltages in the simulated balanced system wit with x = 0.02 © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . . . . . . . Maximum error in the simulated imbalanced system using conventional and developed estimators with x = 0.02 © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Profile of maximum error with x = 0 for low-frequency © 2023 IEEE. Reprinted, with permission, from modulation [56] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Profile of the average error with respect to the sampling frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Picture of the diode-clamped MMC prototype © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . Measured and estimated arm voltage, as well as the error of the arm voltage estimation for a = 0 © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . . . . . . . . . . . . . . Measured capacitor voltages and estimation results as well as the maximum estimation error for a = 0 [56] . . . . . . . . . . . . Measured capacitor voltages and estimation results as well as the maximum estimation error for a = 0.02 [56] . . . . . . . . .

199 200

201 202

203

218

219

219

220

221

221

222 222 222

223 224 224

List of Figures

Fig. 6.13

Fig. 6.14

Fig. 6.15

Fig. 6.16 Fig. 6.17

Fig. 6.18 Fig. 6.19

Fig. 6.20

Fig. 6.21 Fig. 6.22

Fig. 6.23 Fig. A.1

The estimation profiles of the OCV and internal resistance of batteries for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The difference between estimations and true values for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The diagram of the estimated parameters compared to true values for Simulation 2 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errors between the estimation and true values in Scenario 2 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . The estimated OCVs, estimated resistances, and profile of the modulation index for Simulation 3 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . Picture of the developed testbench © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . Estimated and measured voltages and resistances of all seven modules for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimated and measured output voltage of the pack for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimation errors for Scenario 1 of the experiments © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . The estimated and measured voltages and resistances of all seven modules for Scenario 2 © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Estimation errors for the second experimental scenario © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . The equivalent non-ideal circuit of the auxiliary port based on D values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xxxiii

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237

237 238

238 239

240

240 241

242 242 254

List of Tables

Table 2.1 Table 2.2 Table 3.1 Table 4.1

Table 4.2

Table 4.3 Table 4.4 Table 4.5 Table 4.6

Table 4.7

Table 4.8

Table 5.1 Table 5.2 Table 5.3 Table 6.1 Table 6.2

Comparison of battery chemistries . . . . . . . . . . . . . . . . . . . . . . . . Comparison of Li-ion battery chemistries . . . . . . . . . . . . . . . . . . . Operation modes of the clamping branch . . . . . . . . . . . . . . . . . . . Cost comparison of developed sensorless balancing method with the conventional sensor-based method. © 2021 IEEE. Reprinted, with permission, from [24, 25] . . . . . . Simulation and experiment parameters used to study the sensorless balancing performance using LAPSC modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mismatches in the modules’ parameters . . . . . . . . . . . . . . . . . . . . THD values of the output voltage for different scenarios . . . . . . Parameters of the simulated systems and the laboratory prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of various modulation schemes with various scheduling strategies for 250 load. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . Comparison of various modulation schemes with various scheduling strategies for 25  load. © 2021 IEEE. Reprinted, with permission, from [16] . . . . . . . . . . . . . . . . . . . . . Parameters of the simulation system as well as the lab prototype © 2022 IEEE. Reprinted, with permission, from [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation parameters of the dual-port setup [69, 70] . . . . . . . . . Parameters of the dual-port prototype with five modules . . . . . . Parameters of the simulation and experimental setups with nine modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KF for estimating the module voltages of the MMC © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . . Parameters for simulation and experimental systems © 2023 IEEE. Reprinted, with permission, from [56] . . . . . . . . .

20 21 70

103

103 104 105 119

127

127

133 166 171 187 216 217

xxxv

xxxvi

Table 6.3 Table 6.4 Table 6.5 Table 6.6 Table 6.7

List of Tables

Dual KF for estimating the modules’ voltages and resistances of MMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . KF estimator for internal resistance of the modules . . . . . . . . . . . KF estimator for open-circuit voltages of the modules . . . . . . . . Estimator for open-circuit voltages when modules are at equilibrium . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameters of the simulation (Scenarios 1 and 3) and experimental (Scenario 2) setups © 2022 IEEE. Reprinted, with permission, from [17] . . . . . . . . . . . . . . . . . . . . .

229 229 230 233

235

Chapter 1

Introduction to Modular Energy Storage Systems

This chapter introduces the concept of modular power electronic systems and provides a short history of their development and their main advantages over conventional systems from the hardware and software standpoint. The chapter also highlights the unique capabilities and potentials for modular power electronics, and in particular, modular reconfigurable storage systems. Additionally, it clarifies the main challenges in developing, controlling, and monitoring modular energy storage and conversion systems that currently hinder their expansion. Lastly, the outline of the book is presented. General concepts, potentials, and discussions of the advantages and disadvantages of the presented reconfigurable storage systems are developed in collaboration with Mr. Tomas Kacetl, Dr. Jingyang Fang, and Mr. Jan Kacetl. Furthermore, multiple bachelor and master theses are developed from this chapter in collaboration with students as their (co)advisor [1–10].

1.1 Intro Environmental and economic incentives create considerable pressure to improve energy storage systems. Energy storage systems, particularly batteries, have considerably improved over the last decade. However, colossal shortcomings still need to be addressed, particularly for broad acceptance in electromobility and grid-storage applications. In such applications, large high-capacity and -power storages are necessary that are also cost-efficient, performant, and reliable. Nevertheless, the available technology fails to address all the critical challenges, and optimizing the storage chemistry might prove insufficient, as many issues originate from all the additional requirements of such applications, multiple peripheral subsystems, and lack of flexibility in conventional rigid energy storage systems.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1_1

1

2

1 Introduction to Modular Energy Storage Systems

Modular energy storage systems (MMSs) are not a new concept [11]. This work defines MMS as a structure with an arbitrary number of relatively similar modules stacked together. Such structures often have none or minimal reconfigurability through controlled mechanical switches or limited electrical circuitries [12]. However, modular reconfigurable storage systems, as we know them, became popular through the emergence of cascaded electronic structures. The goal of cascaded electronics is to offer flexible and extendable circuits. The clear advantages of cascaded electronics alongside the falling price of power electronics components and ever-increasing demand for larger, more flexible, and more performant energy storages have increased the interest in modular multilevel or reconfigurable energy storages [13].

1.2 Cascaded Power Electronics Structures Modular or cascaded yet fully reconfigurable electronic structures are fascinating concepts that are yet to be fully realized. Multilevel converters (MLC) were the first step toward modular electronics, initially developed to improve the output quality and reduce the filter size. However, they needed more flexibility for broader adoption [14]. Among various alternatives and solutions, modular multilevel converters (MMC) are considered the next step toward modularity, especially in high-voltage applications [15]. Nevertheless, they are still relatively limited in topology and performance, as they only scale vertically (i.e., can be only series or bypassed) in a modular structure and require complicated control and monitoring. Lesnicar and Marquardt initially proposed MMC topology for the first time as a more flexible and extendable MLC solution in 2003 [16]. The first commercial use of MMCs was seven years later in San Francisco’s Trans Bay project [17]. Since introduction, MMCs have evolved, but the core limitations have persisted [18, 19]. The conventional topology of the MMC is a dual-arm structure with half-bridge (HB) modules with the output phase connected in the middle. Figure 1.1 shows the generic structure of an MMC and Fig. 1.2 depicts the two well-known module topologies for such a structure. Conventional MMC topologies consisting of half-bridge modules have mnumber of deficiencies, including the need for constant voltage balancing [20, 21], complex control [22], costly monitoring system [23], and eventually challenging modulation strategies [24], which counterbalance their advantages. Additionally, it is challenging to attain higher safety integrity levels (SIL) in the software due to the high level of complexity [25, 26]. Therefore, a wide area of research focuses in addressing each of these obstacles through hardware [27–30] and/or software [22, 31, 32]. Cascaded H-Bridges (CHBs) with full-bridge (FB) modules are another alternative for a general modular electronics solution. However, similar to the conventional MMCs, CHBs are limited to only vertical scalability, limited performance versus cost, poor treatment of the modules, low efficiency, and complicated balancing controllers [33, 34]. Therefore, both MMC and CHB are a limited subset of a generic

1.2 Cascaded Power Electronics Structures

3

Other phases can be added

Module

Arm

ac or dc

Module

Module ac or dc

Module Module

Arm

ac or dc

ac or dc

Module

Fig. 1.1 Generic topology of a dual-arm MMC topology Fig. 1.2 Generic topology of conventional HB and FB modules

modular reconfigurable structure, not a mature solution. Nevertheless, concentrated research attempts to improve or rectify the shortcomings of existing modular electronics through novel hardware or software. Chapter 3 investigates the possible arm and module topologies and the shortcomings of these structures in detail. There are topologies with additional features on the hardware side, which can potentially solve some abovementioned shortcomings [35–38]. Compared to conventional circuits, these topologies provide benefits and capabilities such as

4

1 Introduction to Modular Energy Storage Systems

• Capable of autonomous charge balancing and capability of stable sensorless operation [21, 36, 38]; • Obtaining higher efficiency during operation due to reduced equivalent impedance [39–42]; • Reducing the stress on the batteries [33, 43] • Offering bidirectional operation of the modules [39]; • Reducing communication requirements [44–46]; • Achieving higher granulation of the output voltage with nonidentical module voltages [47–50]; • Optimize the necessary capacitance or voltage levels [51, 52]; • Offer better fault tolerance [53]. Although effective, the available solutions do not consider the complete system with interactions among different subsystems and neglect many practical restrictions, including cost and weight, which prevent the realization of the full potential of modular, reconfigurable structures. Furthermore, the efforts should focus on higher functional integration and avoid additional complex structures. The endeavors on software-based solutions mainly focus on analyzing the system more accurately, optimizing the higher-level controllers to improve such structures’ performance or stability, and developing more efficient balancing or modulation techniques. Some of the available advancements in these fields include • • • • •

Improving harmonic content through novel modulation methods [54–57]; Increasing the generated voltage levels [58]; Reducing the common-mode or differential-mode noises [59, 60]; Enhancing the monitoring estimation routines using available information [61] Minimizing the constraints on the capacitance of the modules or reducing the voltage ripple on the modules [51, 62]. • Improving the reliability and reducing the susceptibility of these systems to cyber attacks [63, 64].

However, due to the inherent limitations of conventional topologies, the improvement obtained through purely software-based solutions is suboptimal. Additionally, many such solutions come at the cost of higher complexity, higher computations, and additional or higher bandwidth measurements. In effect, not considering the complete system replaces one issue with another outside the optimization criteria, such as reducing the hardware stress, increasing integration or creating additional functions, and minimizing the monitoring system complexity or cost. The envisioned control diagram of a generic modular, reconfigurable electronics consists of four main stages. However, they are combinable in specific topologies or applications, and further control objectives can increase these stages [65]. The highest level of control usually determines the necessary voltage or current levels for each phase depending on the objectives, such as controlling the rate and direction of energy transfer. The next level determines the arm voltages or current references to control and balance the energy transfer between phases and arms. At the module level, to

Module Controller/ Modulator

Scheduler/ Balancer

The mapping of the connections through the arm

5

Numbers of serial, bypass,... connections

Arm Controller

The arms‘ reference voltage and current

Phase Controller

The phases‘ reference voltage and current

1.3 Modular Reconfigurable Storages

Switching Signals

Fig. 1.3 Overview of different control levels in an MMC

determine the control (gate) signals for the respective modules, the modulator determines the module states depending on the modulation strategy, and concurrently the scheduler or balancer selects the priority by which the modules should be connected or removed from the arm. This work will also present that further optimization of efficiency or output quality is possible in this stage. The modulation and scheduler routines can be combined in some topologies or controllers [21]. Figure 1.3 depicts the hierarchy of different control levels.

1.3 Modular Reconfigurable Storages Despite renewable energy generation expansion, growth of the electromobility sector, environmental incentives, and intensified research on the battery or super-capacitor (SC) technologies, many of the traditional challenges persist [66]. Today, the rigid series and parallel connection of literally hundreds of cells power an electric vehicle (EV) [67, 68]. In addition to the improved capacity, a trend in increasing the voltage levels of the storage systems has grown the share of series connections with the same energy capacity [69]. The advantages behind higher-voltage storage (i.e., 800 V), among which batteries are the most common one, include lower weight, better efficiency, and increased power rating with similar current levels [70]. However, storage systems with higher rated voltage and more series connections can also challenge protection or safety requirements, increase the complexity of monitoring and balancing subsystems, reduce efficiency, increase system impedance, and reduce usable capacity. An energy storage module is not a new concept, and the available technology in most modern large storages uses some form of a fixed module to form large packs [12, 71]. However, with the ever-decreasing cost of power electronics, interest in reconfigurable storage systems in high-power, medium- or low-voltage applications has significantly grown [72, 73].

6

1 Introduction to Modular Energy Storage Systems Fixed Energy Storage

Modular Reconfigurable Energy Storage

+

+

Protection/ balancer/ Sensors/...

+ Energy Converter Output 1 or Adaptor

Protection/ balancer/ Sensors/...

+ Output 1

Individual

+ Protection/ balancer/ Sensors/...

Output 2 Energy Converter Output 2 or Adaptor

+

Fig. 1.4 Intuitive representation of an MMS as well as hard-wired energy storage system

One major trend is merging the energy storage system with modular electronics, resulting in fully controlled modular, reconfigurable storage, also known as modular multilevel energy storage. These systems break the conventionally hard-wired and rigid storage systems into multiple smaller modules and integrate them with electronic circuits to obtain a modular system capable of fast and dynamic reconfiguration [68, 74]. Figure 1.4 provides an intuitive representation of a hard-wired energy storage system and a modular, reconfigurable one. The integration allows flexible and yet dynamic connectivity of multiple strings into various dc, single-phase, and multi-phase structures [68, 75]. The possibility of dynamic reconfiguration allows for modulating each module individually to act as an independent yet coherent energy conversion unit. The bulky and rigid storage system is distributed among different modules, enabling lower voltage/power electronics to improve the response speed and the effective switching frequency [76]. The energy storage of each module can range from relatively small capacities, such as typical capacitors that act as an intermediary device for energy conversion, or high energy/power density components, such as double-layer (super) capacitors (SCs) and batteries, which offer a significant amount of energy [74, 77–79].

1.3 Modular Reconfigurable Storages

7

The modular reconfigurable energy storages generally should benefit from similar advantages to other modular electronics (e.g., MMCs) [76, 80, 81], such as • better balancing with more control over the charge/discharge of the modules as well as the possibility of energy exchange among modules [68, 73]; • better tolerance to faults in a single storage, as the system can continue to operate after bypassing the faulty modules; • better controllability over individual storage modules [41, 82]; • faster output regulation due to better output voltage quality and increased effective frequency of the system [49]; • better efficiency due to the possibility of load sharing among different modules resulting in reduced effective impedance of the system [43]; • improved usable energy capacity resulting from the possibility of high-efficiency energy exchange among modules and the possibility of loading each module separately [76]. Similar to advantages, such systems share some shortcomings, too, including complex control and monitoring systems, challenging protection requirements, and more complex structures resulting in increased cost and volume. On the other hand, despite the similarities, an MMS is not only an energy converter with minimum storage capability. The difference in the application and the inherent behavior of larger storage elements (i.e., simple capacitors as opposed to large batteries or SC) brings new challenges and opportunities. For example, while the voltage of the capacitor is an accurate measure of its energy, this is not the case in other types of energy storage [83, 84]. Hence, more complex models and monitoring and estimation routines will be necessary to represent the nonlinear behavior of the larger energy storages in a modular, reconfigurable storage. Another significant difference between various types of energy storage in modular, reconfigurable storage is dynamics. Although all systems benefit from relatively fast output dynamics, they differ quite significantly in the dynamics of their modules. The capacitors (dis)charge pretty rapidly. Therefore, the bandwidth of the balancing and monitoring routines is highly critical in their performance [68]. However, larger storages, such as batteries, have significantly slower dynamics where they can bear imbalanced loads/charges for a limited duration. Therefore, the speed of the monitoring routine is of lower priority [85]. On the other hand, the monitoring routines are computationally more demanding and considerably more demanding due to the more complex modeling. Lastly, considering the available degrees of freedom in such systems, they have yet to fully achieve their potential in many applications, such as EVs and grid-storages. Moreover, many aspects are still not thoroughly investigated.

8

1 Introduction to Modular Energy Storage Systems

1.4 Main Challenges Despite many advantages or potentials of modular reconfigurable storages, significant aspects must be addressed or studied rigorously for broader acceptance. These aspects include the cost-versus-gain of different topologies or structures, the level of control complexity, monitoring or protection, and interactions of different subsystems.

1.4.1 Level of Modularity The advantages of a dynamically reconfigurable energy storage system include better quantization of the output voltage, improved effective switching frequency, and usable capacity. However, these benefits are at the cost of the increasing number of components, particularly switches, higher peripheral electronics such as gate drivers, possibly higher weight and volume due to packaging, and limitations on the controller side. Therefore, some trade-offs in the modules’ rating and quantity are necessary. However, there are no universal solutions, as the cost and gains are highly affected by outside factors such as the application requirement (e.g., power, weight, volume, capacity gain, output quality), the component costs and availability, and lastly, manufacturing processes.

1.4.2 Modulation Strategy and Control The modulation scheme(s) of the semiconductors can immensely impact(s) the overall performance of the system, including efficiency, current ripple, and output quality [21, 44, 57, 86]. Chapter 5 will show that it is possible to gain additional capabilities or enhance the previous ones by using novel modulation methods and topologies. Other aspects of the modulation strategy that must be considered are computation efficiency, feasibility for the lower-end controllers, and interaction with other control routines such as balancing/scheduler and protection routines. Few modulation methods can inherently combine multiple control routines to reduce the computation demand or complexity, which are studied and enhanced in Chap. 4 [87]. Some modulation techniques can be easily extended to higher number of modules, whereas some methods are more limited in this aspect [88]. Although most modulation techniques are easily understood, developing a mathematical model for them can be challenging, depending on the technique. Such models are exciting in designing controllers or estimators. Therefore, an accurate mathematical model of the system that considers the impact of modulation strategies is essential.

1.5 Main Objectives/Incentives

9

1.4.3 Topologies and Circuit Analysis Various macro and micro structures are available in the literature [66, 89]. Different macro structures are available for providing DC, single-phase, and multi-phase outputs with specific features [73]. It is possible to place only one connection between every two adjacent modules (e.g., in case of half-bridge or bidirectional full-bridge) allowing for merely bypass and series connections in the string or there can be more than one point of connection (e.g., diode-clamped [27, 90, 91], FET-clamped [92], or topologies with higher number of switches [36]). Moreover, the topology of the modules and string will impact the system’s performance and control. This work will introduce modules and control methods capable of additional states that scale not only vertically but also horizontally by creating parallel paths, which can have huge impact on the performance of the modules and the overall system. The added states can also simplify the control by allowing for sensorless or open-loop operation and concurrently increasing the available DoFs. However, the parallel connectivity among modules can make developing a model of the system challenging and necessitate novel monitoring techniques.

1.4.4 Better Monitoring and Protection The higher number of modules and controllable components in MMSs necessitates additional monitoring routines. Sensors and high-bandwidth isolated communication interfaces would replace the simple passive or active balancing circuits with minimum communication to the central controller. In conventional topologies, there are only current sensors at the output terminal of the storage and not at every module. However, as the performance of a modular, reconfigurable storage depends highly on accurate information about the states of the modules (e.g., temperature, load, charge, age), a higher number of sensors, additional data communication, and more performant controllers are essential. An alternative is to simplify the monitoring system by developing fast and dynamic estimators or observers based on the developed model of such systems. Additionally, it is possible to detect and compensate for the measurement noise and bias of critical sensors using estimators [76, 93].

1.5 Main Objectives/Incentives This book exploits and develops modular power electronics integrated energy storages that offer dynamic reconfiguration with various advantages and added capabilities. However, the improvements should not be at the cost of increasingly higher complexity or cost.

10

1 Introduction to Modular Energy Storage Systems

A comprehensive review of the literature on possible modular topologies and storage types helps to select more relevant topologies and develop suitable models that account for the particular traits of MMSs. As the suitability of a topology depends on the application and requirement, the book presents multiple new topologies on a case-by-case basis with significant advantages over conventional technologies. Developing and improving the available control strategies is another goal of this work that focuses on simplifying the modulation strategy, improving the output quality, increasing the efficiency, simplifying the hardware, and reducing costs. However, proposing higher-level controls for such systems during their interactions with the grid/load is not the focus of this work. The last goal is to develop feasible state estimation and parameter identification methods based on the specific behavior and applications to simplify the monitoring system, improve accuracy, and minimize costs. The focus of this goal is simplifying the footprint using the available information to the fullest and reducing the sensors while avoiding needlessly computationally demanding algorithms

1.6 Book Outline The outline of this book is as follows. Chapter 2 provides a general overview of different energy storage types, the study of specific requirements, critical features, and modeling approaches with a specific focus on batteries and capacitors. Chapter 3 studies novel topologies and structures of modular power electronics and develops accurate models of each system for both control and estimation purposes. Additionally, this chapter investigates various advantages and disadvantages of each topology and thoroughly investigates the potential for further improvements and optimization. Chapter 4 studies conventional modulation techniques, develops novel modulations, or optimizes the available ones for better performance, including more straightforward implementation, higher efficiency/balancing, and enhanced capabilities. Leveraging the gained knowledge and understanding of the behavior of various MMS and other modular power electronics in general, Chap. 5 proposes new topologies for emerging applications with a specific focus on electromobility. Chapter 6 develops new estimation methods and optimizes the already available ones using the developed models in Chap. 3. The critical goals of the developed techniques are sensor reduction, accuracy improvement, and computation efficiency. Finally, Chap. 7 concludes this work with some remarks about the main conclusions and results, a summary of the scientific and technical achievements, and possible future research directions.

References

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60. Edpuganti, A., & Rathore, A. K. (2017). Optimal pulsewidth modulation for common-mode voltage elimination scheme of medium-voltage modular multilevel converter-fed open-end stator winding induction motor drives. IEEE Transactions on Industrial Electronics, 64, 848– 856. 61. Tashakor, N., Dusengimana, J., Bayati, M., Kersten, A., Schotten, H., & Götz, S. (2023). General decoupling and sampling technique for reduced-sensor battery management systems in modular reconfigurable batteries. Batteries, 9. 62. Picas, R., Ceballos, S., Pou, J., Zaragoza, J., Konstantinou, G., & Agelidis, V. G. (2015). Closed-loop discontinuous modulation technique for capacitor voltage ripples and switching losses reduction in modular multilevel converters. IEEE Transactions on Power Electronics, 30, 4714–4725. 63. Burgos-Mellado, C., Donoso, F., Dragiˇcevi´c, T., Cárdenas-Dobson, R., Wheeler, P., Clare, J., & Watson, A. (2022). Cyber-attacks in modular multilevel converters. IEEE Transactions on Power Electronics, 37, 8488–8501. 64. Burgos-Mellado, C., Donoso, F., & Dragiˇcevi´c, T. (2022). AC battery: Modular layout and cyber-secure cell-level control for cost-effective transportation electrification. In 2022 IEEE Transportation Electrification Conference & Expo (ITEC) (pp. 1163–1167). 65. Dekka, A., Wu, B., Fuentes, R. L., Perez, M., & Zargari, N. R. (2017). Evolution of topologies, modeling, control schemes, and applications of modular multilevel converters. IEEE Journal of Emerging and Selected Topics in Power Electronics, 5, 1631–1656. 66. Ronanki, D., & Williamson, S. S. (2018). Modular multilevel converters for transportation electrification: Challenges and opportunities. IEEE Transactions on Transportation Electrification, 4, 399–407. 67. Aghabali, I., Bauman, J., Kollmeyer, P. J., Wang, Y., Bilgin, B., & Emadi, A. (2021). 800-V electric vehicle powertrains: Review and analysis of benefits, challenges, and future trends. IEEE Transactions on Transportation Electrification, 7, 927–948. 68. Tashakor, N., Farjah, E., & Ghanbari, T. (2017). A bidirectional battery charger with modular integrated charge equalization circuit. IEEE Transactions on Power Electronics, 32, 2133– 2145. 69. Absar, S., Taha, W., & Emadi, A. (2021). Efficiency evaluation of six-phase VSI and NSI for 400V and 800V electric vehicle powertrains. In IECON 2021 – 47th Annual Conference of the IEEE Industrial Electronics Society (pp. 1–6). 70. Jung, C. (2017). Power up with 800-V systems: The benefits of upgrading voltage power for battery-electric passenger vehicles. IEEE Electrification Magazine, 5, 53–58. 71. Peek, S. C. (1978). Modular and programmable energy storage control. In 1978 IEEE Conference on Decision and Control including the 17th Symposium on Adaptive Processes (pp. 217–219). 72. Priya, M., Ponnambalam, P., & Muralikumar, K. (2019). Modular-multilevel and converter topologies application’s a review. IET Power Electronics, 12, 170–183. 73. Fang, J., Blaabjerg, F., Liu, S., & Goetz, S. M. (2021). A review of multilevel converters with parallel connectivity. IEEE Transactions on Power Electronics, 36, 12468–12489. 74. Goetz, S. M., Li, Z., Liang, X., Zhang, C., Lukic, S. M., & Peterchev, A. V. (2017). Control of modular multilevel converter with parallel connectivity - application to battery systems. IEEE Transactions on Power Electronics, 32, 8381–8392. 75. Li, Y., & Han, Y. (2016). A module-integrated distributed battery energy storage and management system. IEEE Transactions on Power Electronics, 31, 8260–8270. 76. Tashakor, N., Kacetl, J., Kacetl, T., & Goetz, S. (2022). Modular battery-integrated power electronics-modelling, advantages, and challenges. In 2022 24th European Conference on Power Electronics and Applications (EPE’22 ECCE Europe) (pp. 1–10). 77. Rahman, M. A., de Craemer, K., Büscher, J., Driesen, J., Coenen, P., & Mol, C. (2019). Comparative analysis of reconfiguration assisted management of battery storage systems. In IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, vol. 1 (pp. 5921– 5926).

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Chapter 2

Selected Types of Energy Storage

This book chapter offers an accessible look into practical energy storage solutions for modular reconfigurable systems, focusing on three main technologies: capacitors, batteries, and double-layer capacitors (also known as supercapacitors). It explores the roles of capacitors as intermediary devices in energy conversion stages, batteries as high-power and high-voltage storage options, and supercapacitors as flexible storage solutions with considerable energy capacity. Special emphasis is placed on Li-ion batteries, discussing their components, chemistries, terminology, and unique pros and cons. The chapter equips readers with a thorough understanding of these energy storage technologies and their use in modular reconfigurable energy storage systems, making it a must-read for anyone interested in the future of integrated energy storage and power electronics. Additionally, the chapter compares different modeling approaches and provides an understanding of parameter identification procedures to determine equivalent models for these storage types. This knowledge is crucial for comprehending the dynamics of a modular system that includes each of these storage technologies. Collaboration with Mr. Tomas Kacetl and Mr. Jan Kacetl has contributed to the discussion about unique behavior and possible applications. Moreover, Dr. Bita Arabsalmanabadi collaborated in developing and reviewing the modeling techniques of the batteries. Multiple bachelor and master students have also collaborated in developing this chapter while serving as their book supervisor [1–4]. Publications from these collaborations are cited to acknowledge their support and help throughout the chapter.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1_2

17

18

2 Selected Types of Energy Storage

2.1 Intro Although many types of energy storage are possible, here we only consider the ones usable and practical in modular reconfigurable storage elements. Hence, energy storage types, such as flywheels, and super-conductors with an inductive behavior, are neglected. Also, storages that cannot be easily integrated into a modular structure, such as a fuel cell, are also not considered.

2.2 Possible Types of Energy Storage Generally, the existing energy storages in the most available modular reconfigurable energy storages fall within three main groups of i capacitors, ii batteries, and iii SCs. While, in principle, SCs (SCs) are a subset of capacitors, this book distinguishes them based on their dynamics, models, and energy capacity. A capacitor-based module in an MMS can only provide energy for very short intervals (e.g., sub-milliseconds), which can be ideal as an intermediary device during energy conversion. The small energy capacity of the capacitor can also simplify the control since only a voltage control loop would be sufficient. On the other hand, the SC can have a significant energy capacity and can supply a load for an extended amount of time. Therefore, the voltage of the SC is relatively constant in short intervals; therefore, like batteries, current control loops in addition to the voltage loop will be necessary.

2.2.1 Capacitors From the perspective of this work, a capacitor’s main functionality is to work as an intermediary device or buffer between two energy conversion stages. Consequently, they have minimal energy capacity and can only supply loads within a brief duration, e.g., less than a few milliseconds in a power electronics application. In most power electronics applications, a capacitor is usually modeled as an ideal component with negligible resistance. An ideal capacitor is mathematically defined per ic = C

dvc . dt

(2.1)

However, in a few cases, an electrolyte capacitor is modeled with an ideal RC network in series with another resistance as Fig. 2.1 shows and is mathematically represented per

2.2 Possible Types of Energy Storage

19

Fig. 2.1 Equivalent circuit model of a capacitor

vc RS C

ic

RP ic −

vc d(vc − Rs i c ) , =C Rp dt

(2.2)

where vc and i c are the ideal capacitor’s voltage and current, Rs is the internal series resistance, and R p emulates the self-discharge or leakage current. For short intervals, usually, R p is assumed to be infinite, turning the model into an ideal capacitor with internal resistance.

2.2.2 Batteries Today, a significant part of research in many sectors, particularly energy and electromobility, is focused on batteries. A battery is a device that can convert the chemical energy produced by a reaction in its active materials into electrical energy and vice versa. The reaction which takes place between the active materials is called electrochemical oxidation-reduction (redox) reaction1 . This chemical reaction in the battery cell enables the electrons to transfer from one material to another through an electrical circuit [5]. Cells are the units where the actual chemical reaction takes place [3]. However, in most applications, a battery pack consisting of many individual cells connected in parallel or series, typically through fixed (hard-wire) connections, is required. Depending on their active material, many different types of batteries exist, including lead acid, nickel-cadmium, nickel-metal-hydride, and lithium-ion. Figure 2.2 shows the comparison of energy densities and specific energies of different rechargeable batteries [6]. Table 2.1 will provide a brief overview of some common battery chemistries, such as lead-acid, lithium-ion, nickel-cadmium, nickel-metal hydride, and sodium-sulfur, highlighting their key characteristics. Because of the inherent features of Li-ion batteries, they are typically favored in high-power high-voltage applications. This preference is mainly due to higher

1

‘An oxidation-reduction (redox) reaction is a type of chemical reaction that involves a transfer of electrons between two species in which the oxidation number of a molecule, atom, or ion changes by gaining or losing an electron.’For more detail, see link.

20

2 Selected Types of Energy Storage

Table 2.1 Comparison of battery chemistries Battery type Energy Power density Cycle life density Lead-acid Lithium-ion Ni-Cd Ni-MH Na-S

Low High Low Med High

Low High Med Med Med

Low High Med High Med

Cost

Safety

Low Med Med Med High

High Med Low High Low

Li-ion Smaller Size

Energy Density (Wh/L)

Li-Metal (Unsafe)

PLiON Ni-MH

Ni-Cd Lead Acid Lighter Weight

Specific Energy (Wh/kg)

Fig. 2.2 Comparison of energy density versus the specific energy of different types of battery (with permission from [6, 7])

energy density, higher power density, environmental friendliness, lower weight, low self-discharge rate, low maintenance, and negligible memory effect [6].

2.2.2.1

Li-ion Overview

Li-ion batteries are in commercial use since the early 1990s, and experts anticipate that they will still be the leading technology in the future of energy storage devices [8]. A Li-ion cell has four main components, a cathode (positively charged electrode) of lithium metal oxide material (e.g., Li Fe P O4 ), an anode (negatively charged electrode) of carbon transfused with Lithium (e.g., Li x C), an electrolyte, and a separator responsible for preventing a short circuit among the Cathode and Anode. The four components are arranged so that the anode and the cathode are submerged in the

2.2 Possible Types of Energy Storage

21

Table 2.2 Comparison of Li-ion battery chemistries Li-ion type Energy Power density Cycle life density LCO LMO LFP NMC NCA

High Med Low High High

Med High High High High

Med High High High Med

Cost

Safety

High Med Med Med High

Low Med High Med Med

electrolyte, separated by a permeable separator. The separator allows the lithium ions to be exchanged freely between the two electrodes but blocks the exchange of electrons. The detailed study of the chemical reactions in a Li-ion battery is not the focus of this book, but the following provides a broad overview. When the two electrodes are connected to an external power source for charging, the electrons are released at the cathode and move externally toward the anode. Concurrently Lithium ions also move internally through the electrolyte toward the anode. Hence, the energy is stored electrochemically, increasing the chemical potential differences between the anode and cathode. The process reverses during the discharging operation into a load, where the electrons externally leave the anode and move towards the cathode through the load, providing energy to it. Concurrently, the lithium ions return from the anode to the cathode through the electrolyte. The state-of-the-art of Li-ion cell design is still widely similar to the past two decades but vary significantly in electrode materials, electrolyte, and separators [6]. Several variations of Li-ion batteries have been developed to cater to the diverse needs of different applications. The most common types include Lithium Cobalt Oxide (LiCoO2 or LCO), Lithium Manganese Oxide (Li Mn 2 O4 or LMO), Lithium Iron Phosphate (Li Fe P O4 or LFP), Lithium Nickel Manganese Cobalt Oxide (NMC or Li N i MnCoO2 ), and Lithium Nickel Cobalt Aluminum Oxide (Li N iCo Al O2 or NCA). Each type has its unique advantages and disadvantages, which can affect factors such as energy density, power density, safety, and cost. Table 2.2 will provide a brief comparison between different Li-ion chemistries.

2.2.2.2

Battery Terminology

Some critical parameters by which Li-ion batteries are evaluated include volumetric energy, specific energy, specific capacity, cyclability, abuse tolerance, safety, charging rate, and discharging rate [3, 6]. Specific energy, usually measured in Wh/kg, specifies the amount of energy per unit mass that the battery can store and release. Similarly, the volumetric energy, also known as energy density, usually measured in Wh/L, specifies the storable/releasable energy per volume [6].

22

2 Selected Types of Energy Storage

Specific capacity, usually measured in Ah/kg, represents the amount of charge the cell can store per unit mass. Multiplying the specific energy with the battery’s operating voltage (V) determines the specific energy. Cyclability measures the possible number of charge and discharge cycles before the battery loses its capacity significantly (in most cases 20%–30% of its rated capacity) or it can no longer provide sufficient energy/power to the connected device [6]. Some of the significant factors affecting the cycle life of Li-ion batteries are depth of discharge (DoD) and state of charge (SoC), operating temperature, load profile, storage profile, battery chemistry [9–11]. Cycle life is enhanced by reducing the cycle’s DoD, minimizing the SoC swings, avoiding charging at high or low temperatures, and storing the battery at mid-SoC ranges [1, 11]. Abuse tolerance is a vital prerequisite for most applications of Li-ion batteries, particularly EVs. Typically, mechanical (e.g., mechanical shocking and dropping, rolling-over, pin penetration, and immersion in water), thermal (e.g., radiant heat, thermal stability, overheating resilience, and extreme cold exposure), and electrical (overcharging, over-discharging, short circuit, and ac currents loading) abuse tests are performed on prototypes to determine abuse tolerance [6]. Rate of charge or discharge, typically specified by C-rate, measures the sustainable speed of charge or discharge that the battery can tolerate without significant degradation. A discharge rate of one C means the battery fully depletes its energy in one hour. Compared to the charging speeds, the batteries can conventionally tolerate a significantly higher discharging speed, even neglecting the constant voltage stage of charging. Additionally, the batteries cannot sustain charge at full current to a 100% SoC, as their terminal voltage will increase exponentially at higher SoCs to beyond safe limits of operation [12–14]. Charging speed is even more critical for EVs, as the battery size is significantly larger. A popular research direction regarding Li-ion batteries is methods to increase the charge/discharge rates [14]. There are metrics by which the current state of a battery is determined, which include state of health, open circuit voltage, end of charge and cut-off voltage, and state of charge [1, 3]. As the battery ages, its capacity reduces. State of health (SOH), usually in %, describes the age of the battery through the ratio of the existing capacity to the rated capacity of the battery. Therefore, the SOH of the battery is ideally 100% in the beginning and gradually decays to zero as the battery ages [12]. In most applications, a battery with a SOH of V2 , the diode will be forwardbiased and form a parallel mode between modules, where the upper storage will discharge into the lower one, hence the so-called semi-controlled bypass mode. It is also possible to create a unit or union of more than two parallel modules. Figure 3.23 depicts a unit of such modules intuitively. Each unit starts with a series connection to the previous module/union and ends with a series connection to the lower module/union. The resulting voltage of each union with multiple parallel modules depends on the module states, as well as the switch states of the adjacent unions. Small inductors, as discussed in other topologies, can reduce the stress on the components and improve the balancing efficiency [17, 19, 28].

At similar potential with the negative terminal of the storage

S2

S1

S2

S1

S4

S3

S4

S3

Mode 1 Series to upper module Series to lower module

Mode 2 Parallel to upper module Series to lower module

S2

S1

S2

S1

S4

S3

S4

S3

Mode 3 Series to upper module Parallel to lower module

Mode 4 Parallel to upper module Parallel to lower module

Fig. 3.21 Possible operation modes of a unidirectional full-bridge module

At similar potential with the positive terminal of the storage

3.3 Generic Micro Topologies and Interconnections Fig. 3.22 Semi-controlled bypass mode in a unidirectional FB with parallel connectivity

59

v1

S14

S13

S22

S21

Mode 5 To bypass upper storage: • all switches except S13 must be off • v1 < v2

S 11

S14

S13

S22

S21

S24

S23

SNp2

SNp1

SNp4

SNp3

Interconnection 1

S12

Lower End Connection

Fig. 3.23 A unit of N p paralleled modules. © 2021 IEEE. Reprinted, with permission, from [19, 30]

Upper End Connection

v2

60

3 Topology, Circuit Analysis, and Modeling

Fig. 3.24 Equivalent circuit of a unit with N p paralleled modules. © 2021 IEEE. Reprinted, with permission, from [19, 30]

The equivalent circuit of a union includes three terms • (1) the equivalent circuit of a series connection to the previous union; • (2) the equivalent circuit of the paralleled modules; • (3) the equivalent circuit of a series connection to the next union. With identical and limited parallel modules, we can assume that the load current is divided equally among the parallel modules [35]. Therefore, in the simplest form, we can replace the storage with a zero-order ECM with a controlled current source

3.3 Generic Micro Topologies and Interconnections

61

(i p /N p ) and a resistive element (rc ), where N p is the number of parallel modules in the union. Figure 3.24 shows the equivalent circuit of a group of paralleled modules that includes N p parallel modules. Each union is connected in series to the previous and next union. For the top and bottom unions, unions are connected at one side in series to the load path. Depending on the application, it is possible to derive suitable equations with any level of accuracy by replacing the zero-order ECM with higher-order ECMs. The equivalent resistance of the union shown in Fig. 3.24 follows [19] Req,union =

rc rint + (N p + 1) , Np 2

(3.28)

where rint = rl + rsw is equal to the summation of the interconnection inductors and switch resistances. With a known number of required parallel and series connections enables calculating the equivalent resistance of a string with Ns unions connected in series. The total equivalent resistance of one arm is 

Resistance of all unions





Resistance ofNp,j parallel modules

Req,arm



 Ns   (N p, j − 1) rc rint Rint + (Ns − 1) + rsw . = + N p, j 2 2 j=1

(3.29)

The last term in (3.29) represents the internal resistance first half-bridge in the first module of the string, in which at each instance, only one switch is conducting the full arm current. Equation 3.29 can be further simplified through straightforward mathematical manipulations to Req,arm = rc

 Ns   1 rint + (N − 1) + rsw . N p, j 2 j=1

(3.30)

Although the unidirectional full-bridge has almost twice (4N − 2) the number of individual semiconductors compared to the typical half-bridge modules, the effective current of each FB switch is half of the HB one, as the current is distributed among the parallel paths [19]. Therefore, it is possible to use switches with smaller die-area (i.e., lower current ratings and higher internal resistances) for the unidirectional FB [36]. Another noteworthy point is that (3.30) states that the equivalent resistance of the string depends on the distribution (mapping) of the formed series and parallel configurations in the string. The lowest effective resistance for a given Ns is attained when all the unions have the same size, i.e., the number of parallel modules for every union is identical. Although identical parallel numbers for all unions cannot

62

3 Topology, Circuit Analysis, and Modeling

S3

S2

S1

Mode 1: Series S2

S3

S1

S3

S2

S1

S4 Removing the redundant switch results in

Mode 2: parallel S3

S2

S1

Mode 3: Bypass upper module (semi-controlled) Fig. 3.25 Operation modes of a switch-clamped module

be guaranteed at times, nevertheless, an evener allocation of parallel modules among unions throughout the arm can provide a lower effective impedance [19, 36]. Switch-Clamped Half-Bridge Module is a simpler form of the unidirectional FB modules. As Fig. 3.25 intuitively shows, removing one of the two switches in parallel in the unidirectional FB module can simplify the four-switch topology to a threeswitch one. The main functionality, as well as the available modes of operation, are widely similar to the unidirectional FB topology, with the exception that here the middle switch (S2 ) would bear the full current, and hence has to be larger than the other two switches (S3 and S1 ). Additionally, to ensure better energy sharing during the parallel modes, no inductors can be used between the module connections to limit the balancing surge currents. In such cases, a low-pass filter can be paralleled to each storage module [33]. During Mode 1, the two storages are in series, and they are in parallel during Mode 2. This topology does not have a complete bypass, but by turning on S1 , we can bypass the upper storage if its voltage is not higher than the lower storage. If the voltage of the upper storage is higher, then the anti-parallel diode of S3 will be forward biased, and the two modules will be in parallel. In some applications, usually in high-voltage high-power applications, to reduce cost, the clamping circuit bears only a small share of the current, mainly for balancing purposes. In such cases, an inductor in series with S3 ensures the energy transfer rate

3.3 Generic Micro Topologies and Interconnections

63

Sj1

Sj2

S(j+1)1

S(j+1)2

Sj3

Cj

Lj

S(j+1)3

C(j+1)

L(j+1)

Fig. 3.26 Generic circuit of a switch-clamped module with low-current clamping branch

is limited. Hence the current rating of S3 and its parallel diode can be only a fraction of the main switches. Figure 3.26 shows the generic shape of the structure in this case [15]. Such structures are primarily used in HVDC applications with capacitors in the modules. Therefore, capacitor-based modules serve as an example in explaining and analyzing the circuit. The analysis can also extend to other storages. If the storage C( j+1) is bypassed (by turning S( j+1)2 on), switch-diode pair S j3 connects C j and C( j+1) in parallel, resulting in balancing the voltage of the two modules. Depending on the storages’ voltages, the balancing current can flow in either direction as highlighted in Figs. 3.27. As shown, voltages can be equalized or balanced in both directions. In low-voltage applications, a single MOSFET and its inherent body diode can replace the IGBT-diode set in the clamping circuit. It should be mentioned that the existence of the inductance, ensures that the clamping path does not contribute to the load sharing, and only a fraction of the load current necessary for balancing purposes flows through the clamping circuit. Therefore, the size of the semiconductors in the clamping path can be significantly smaller. This topology is capable of sensorless balancing, as the following describes. The process for capacitor-based modules with IGBT-diode sets is explained. However, the principle of operation is similar for other storage types, as well as other MOSFETs [15, 30]. For a sensorless balancing operation, it would suffice to trigger the switch S j3 of the clamping circuit and S( j+1)2 simultaneously, as depicted in Fig. 3.26. The inductor L j plays a critical role in preventing excessive current spikes and protecting the

64

3 Topology, Circuit Analysis, and Modeling

iclamping

Mode 1 Sj1

Sj2

S(j+1)1

S(j+1)2

Sj1

Sj3

Cj

Lj

Sj2

S(j+1)1

S(j+1)3

C(j+1)

iclamping

Mode 2

L(j+1)

S(j+1)2

Sj3

Cj

Lj

S(j+1)3

C(j+1)

L2

Fig. 3.27 Operation modes of a switch-clamped module if S( j+1)2 is on. © 2021 IEEE. Reprinted, with permission, from [15]

lower-current clamping branch from being overloaded. Depending on the direction of the current, there are two potential scenarios: Mode 1: if the voltage of storage C j is larger than that of module C( j+1) , i.e., V j > V( j+1) , switches S( j+1)2 and S j3 conduct and the balancing current flows from C j to C( j+1) . This current flow results in the increase of V( j+1) and the decrease of V j , finally, charge equilibrium. In this scenario, the system’s equivalent circuit is depicted in Fig. 3.28, which includes the IGBT forward voltage drop denoted as Vsw and the voltage drop of the free-wheeling diode, indicated as Vfd . After turning S j3 off, the inductor current falls to zero [15]. Mode 2: if the voltage of C( j+1) is higher, meaning that V j < V( j+1) , then the current will flow from C( j+1) through the clamping diode and inductor to C j in order to balance the voltage difference. This process can be visualized using the equivalent circuit shown in Fig. 3.28. When switch S( j+1)2 is turned off and S( j+1)1 on, the VC j reverse biasses the diode in the clamping  path, and the inductor current gradually  di

− VC j +Vfd

. falls to zero with a rate of dtj = Lj The energy transfer through the clamping branch persists until the voltages are balanced. As the voltage difference between the capacitors vanishes, the current flowing through the inductor decays to zero. In Fig. 3.29, which disregards the forward voltage drop of diodes and switches for simplicity, you can observe the typical waveforms of the clamping current and the voltage across the modules [15]. With identical balancing paths between every two modules (L j = L), the equivalent circuit can be approximated with a series R LC circuit described by

3.3 Generic Micro Topologies and Interconnections

Vsw,Sj3

rSj

Vfd,Sj3

rLj rCj+1

rCj

65

iclamping

rLj rCj+1

iclamping Cj+1

Cj rD(j+1)2

rdj

rCj

Cj+1

Cj rD(j+1)2

Vfd,S(j+1)2 Mode 1

Vsw,S(j+1)2 Mode 2

Fig. 3.28 Equivalent electrical circuit of the modules when S( j+1)2 is on. © 2021 IEEE. Reprinted, with permission, from [15] Fig. 3.29 Representative voltage and current waveforms of a balancing operation in a switch-clamped half-bridge module. © 2021 IEEE. Reprinted, with permission, from [15]

S(j+1)2 time

iclamping

time

V(j+1) Vavg Vj

time

1 d 2 Vdiff R d Vdiff + + Vdiff = 0, 2 dt L dt LCe

(3.31)

and solving the resulting second-order differential equation leads to two roots per

P1,2

−R ± = 2L



R 2L

2 −

1 , LCe

(3.32)

where Ce = 21 C j = 21 C( j+1) , Vdiff, j = V( j+1) − V j − Vfd − Vsw , and R = 2rc + 2r S + r L are the parameters of the equivalent circuit. Based on (3.32), two scenario are possible:  Scenario 1: if R ≥ 2 CLe , the balancing behavior of the circuit is overdamped and nonoscillatory;   R 2 freScenario 2: R < 2 CLe describes a damped oscillation with a LC1 e − 2L quency.

66

3 Topology, Circuit Analysis, and Modeling Mode 3

iclamping

Sj1

Si1

Sj3 Snubber

Cj

Sj2

S(j+1)1

C(j+1)

Sj3

S(j+1)1

Lj

S(j+1)3

C(j+1)

S(j+1)2

L(j+1)

Snubber

Cj

Sj2

Lj

S(j+1)3

S(j+1)2

iclamping

Mode 4

L(j+1)

Fig. 3.30 Operation modes of a switch-clamped module if S( j+1)2 is off. © 2021 IEEE. Reprinted, with permission, from [15]

The system typically operates underdamped because of its low equivalent resistances. However,  it is recommended to maintain the system near the underdamped

threshold (R < 2 CLe ) to minimize power loss caused by oscillation. according to (3.31), the balancing current is i(t) = Ae−αt sin (ωd t), where α =

R , ω0 2L

=

√ 1 , ωd LCe

=



(3.33)

ω0 2 − α2 , i(0) = 0, Vdiff denotes the initial volt-

age disparity between the two neighboring modules, amplitude is A = L(ωVddiff−α) =  L VdiffR2 R . Ce

−

4

di(0) dt

=

Vdiff , L

and the current

−2

At the end of the switching period, when S( j+1)2 and S j3 are switched off, there are two possible scenarios. If V( j+1) > V j , then the current will rapidly decrease to zero by discharging into C j through the anti-parallel diodes with the switches. Alternatively, if V j > V( j+1) , switching off S j3 will discharge the inductor into the Insulated-Gate Bipolar Transistor (IGBT) snubber, parasitic capacitances, and C j , pushing the inductor current to zero. Figure 3.30 depicts the current paths of the inductor when S j3 is off for both scenarios [15]. As the formed R LC circuit is typically underdamped, the peak balancing current (i max ) is smaller than A.

i max,1 < 

Vdiff L Ce

−

R2 4

−

R 2

,

(3.34)

3.3 Generic Micro Topologies and Interconnections

67

Furthermore, in the case of high switching rates (e.g., f sw ωd /(2π)), the inductor current would not reach the peak value. Considering the voltage imbalance between the two storages is constant within a switching period (due to a sufficiently high switching rate), the peak current flowing through the inductor can be computed per i max,2 ≤

Vdiff Dmax Tsw , L

(3.35)

where it is possible to consider Dmax = 1 as the worst-case scenario. To avoid overdesign, a more practical approach is to consider Dmax equal to the maximum modulation index of the module. Equations (3.34) and (3.35) can be combined to select a suitable inductance range that can limit the peak balancing current to a desired value as follows  L ≥ min

Vdiff,max R + i rated 2

2

R2 + 4



Vdiff,max Tsw Ce , i rated

 .

(3.36)

Besides restricting current surges, increasing the inductor value also decreases the oscillation frequency, which is determined by the equation f osc = 2π√1LC , and e reduces the power loss caused by the oscillations. However, larger inductor values also slow down the balancing process and increase the inductor cost and the steadystate voltage difference among the modules [16]. Therefore, a trade-off exists in the inductor value. The minimum value for the inductor is determined by Eq. (3.36), while the switching frequency ( f sw ) and fundamental frequency ( f 0 ) of the system define the upper limit. As every two modules only balance when the lower one is bypassed, the average time span that the lower module is bypassed should be longer than the oscillation time constant to ensure sufficient time for the modules to stay balanced. The average ratio of the bypass state duration compared to one switching cycle, here denoted by Tb , in a dc application is (1 − m) with m denoting the modulation index of the module [15]. Similarly, the average time-share of the bypass states of a module can be calculated for any ac application. As an example, Tb for the dual-arm topology follows Tb =

km f0

(3.37)

where k is the coefficient that relates to modulation strategy and is between zero and one, m is the average modulation index of the arm, and f 0 is the fundamental frequency of the output voltage. For example, in case of the dual-arm MMC topology, for conventional nearest-level and conventional phase-shifted carrier (PSC) modulations,2 k = 1, and m = 0.5 for both arms. 2

(See Chap. 4).

68

3 Topology, Circuit Analysis, and Modeling

The following inequality system time constant

5

  2L R

≤ Tb ,

(3.38)

should hold to ensure a balanced operation. A limit of five times the system time constant guarantees complete balancing during one cycle of the output voltage. Reference [15]. Through straightforward manipulation, the upper boundary for the inductance follows L≤

Tb R . 10

(3.39)

With a known inductance value, the rated current of the clamping circuit can be calculated (i rated ≥ i max ), which follows i rated ≥ min {Eq.(3.34), Eq.(3.35)} .

(3.40)

Switch S j3 can have a significantly lower current rating compared to the power switches, as low as less than 1/20th of the rated current of the string. However, Switch S j3 and its diode must be rated for the complete voltage of one module. Additionally, the anti-parallel diodes ensure that there is no negative voltage on the IGBTs. Diode-Clamped Half-Bridge Module is the simplest topology in this category. The added expenses resulting from the increased quantity of individual semiconductors, drivers, and a more complex design can hinder the expansion of the aforementioned topologies in high-voltage applications. [12, 16]. Compared to their fully controlled counterparts, diodes are inherently less expensive and less complex. Therefore, diode-clamped topologies can be considered the most straightforward and cheapest solution to a parallel-capable module topology. By replacing the S1 unidirectional switch with a diode, an even simpler and lower cost form of a parallel-capable module is formed, which is also known as a diode-clamped HB module. While there are more complex methods, Fig. 3.31 illustrates the most basic form of a diode-clamped topology [13, 14, 28]. In Fig. 3.31, the added diode links the positive terminals of two successive modules and, with the help of the primary switches, forms a unidirectional balancing path. However, since module surplus energy can only move from the bottom module to the upper one, the imbalance remains and accumulates if the top module has a higher state of charge. Similar to other topologies capable of a parallel connection, a tiny inductor can restrict the amplitude of the current surges if two modules with different voltages connect in parallel [12]. A minimal inductance, as low as few microhenries, hence with negligible core size, can be sufficient [12, 16].

3.3 Generic Micro Topologies and Interconnections

69

Fig. 3.31 Simplest topology for a diode-clamped module

S2

S1

D

Sj1 Dj Sj2

Cj Lj

jth Module and clamping circuit

S(j+1)1 D(j+1) S(j+1)2

C(j+1)

L(j+1)

Each string with such topology contains N HB modules, but only (N − 1) clamping circuits are sufficient. In most applications, the diode is only responsible for balancing purposes and should bear only a fraction of the string current, reducing the diode’s cost. However, diodes with higher current rantings can provide some current sharing among the modules, even though typically, a diode has a higher voltage drop compared to MOSFET, and the current will not be distributed evenly among the main and the clamping paths. The voltage across the clamping branch (vb j ) includes the diode forward voltage-drop (Vfd ), the voltage across the inductor (v L j ), and the voltage across the sum of parasitic resistances (v Rsum ) per vb j = Vfd + v L j + v Rsum .

(3.41)

Depending on the switching signals of the ( j + 1)th module and the module voltages, three possibilities exist, which are depicted in Table 3.1 and Fig. 3.32. When S( j+1)1 : off and S( j+1)2 : on, the voltage across the clamping branch depends on the

70

3 Topology, Circuit Analysis, and Modeling

Table 3.1 Operation modes of the clamping branch Mode Switch states Voltage condition 1

S( j+1)1 S( j+1)2 S( j+1)1 S( j+1)2

2

: : : :

of f on of f on

Vcj+1 ≤ Vc j + Vfd Vcj+1 > V j + Vfd

S( j+1)1 : on S( j+1)2 : o f f

3

Sj1

iD

Cj

S(j+1)1

Lj

Sj1

Sj2

Cj

Lj

Mode 1 Clamping branch is open

Dj

S(j+1)2

Sj2

Cj

Lj

S(j+1)1

S(j+1)1

C(j+1)

iD

Dj

iD = 0

S(j+1)2

Open-circuit Cj + 1 discharges into C j (balancing) Current decays to zero or stays zero

—

Sj1

Sj2

Circuit behavior

C(j+1)

Mode 2 Two storages are paralleled

S(j+1)2

C(j+1)

Mode 3 Inductor’s current decays

Fig. 3.32 Possible modes of operation for the diode-clamped modules. © 2021 IEEE. Reprinted, with permission, from [12, 37]

storage voltages following vb j = v j+1 − v j . If v j+1 ≤ v j + Vfd , the branch is open (Mode 1), but if v j+1 > v j + v f d , a balancing current flows from Module ( j + 1) to Module (i) (Mode 2). When S( j+1)1 : on and S( j+1)2 : off, the diode is reverse-biased (Mode 3), and the balancing current decays to zero. Figure 3.33 shows the equivalent electrical circuits during Mode 1 and Mode 2. Neglecting the parasitic resistances, the clamping inductor confines the decay rate following

− VC j + Vfd di D ≈ dt Lj where i D is the clamping current.

(3.42)

3.3 Generic Micro Topologies and Interconnections

71

Mode 2 Dj ECM of the ( j) storage

Lj

iDj

RLj

Mode 3 Lj

In case of capacitors

Lj

Dj

Lj

Dj

Ce Vdiff

Dj

iDj decays to zero

RDj

Rsum1

RS( j+1)2

RDj

ECM of the ( j) storage

ECM of the ( j+1) storage

RLj

Rsum2 In case of capacitors

Cj Vj

RD( j+1)1

Fig. 3.33 Equivalent electrical circuits during the balancing operation Fig. 3.34 Intuitive balancing process for balancing of two modules through the clamping branch. © 2021 IEEE. Reprinted, with permission, from [12, 37]

Vbj

vj

vj+1 vj

time

vj+1

time

vj time

Larger charge imbalances among modules can necessitate multiple cyclesof switching (i.e., toggling between Mode 2 and Mode 3), until the voltage imbalance of the modules follows V( j+1) − V j ≤ Vfd . Figure 3.34 represents this procedure intuitively. The analysis is extendable to all of the modules in an arm following V1 + Vfd ≥ · · · ≥ V(N −1) + Vfd ≥ VN ,

(3.43)

where N is the number of modules. Equation (3.43) neglects the voltage drop across the main half-bridge switches or diodes.

72

3 Topology, Circuit Analysis, and Modeling

In case of modules with capacitors as the storage element, the equivalent electrical circuit when S( j+1)2 : on and V( j+1) > V j + Vfd is a second-order R LC circuit [14, 28]. The right side of Fig. 3.33 shows the equivalent circuits with capacitors as the main storages in the modules. The equivalent voltage is Vdiff = V( j+1) − V j , and the equivalent capacitance Ce = 0.5C j = 0.5C( j+1) , Rsum1 = RC( j+1) + R L j + RC j + R D j + R S( j+1)2 is the sum of all the resistive elements for Mode 2. Similarly, Rsum2 = R L j + RC j + R D j + R D( j+1)1 is the equivalent resistance in Mode 3. Assuming similar diode and switch resistances, we can simplify the analysis. Kirchhoff’s voltage law and after mathematical manipulations results in a secondorder differential equation that describes the diode current per 1 Rsum di D (t) d 2 i D (t) + + i D (t) = 0, dt 2 Lj dt L j Ce

(3.44)

where Rsum = RC( j+1) /2 + R L j + RC j + R D j + R S( j+1)2 , assuming identical parameters for the modules. Applying Laplace transformation and solving it results in system roots per P1,2

Rsum =− ± 2L j



2 Rsum 1 − L j Ce 4L 2j

(3.45)

The equivalent resistance Rsum is comparably small; hence the current will be a damped oscillation for capacitor-based modules, which is given by i D (t) =

⎧ ⎨ ⎩

Vdiff Lj Ce

−

2 Rsum 4

−

Rsum 2

e−αt sin(ωdt ), 0 ≤ ωd t ≤ π (3.46) ωd t > π

0

where the damping factor is α = R2Lsumj , and the frequency of the oscillation is ωd =  R2 1 − 4Lsum2 . As the diode cannot conduct in reverse, the clamping current can only L j Ce j

follow (3.46) during the first positive half-cycle, and then it stays at zero. Therefore, the highest inductor current follows I D,max1 < 

Vdiff Lj Ce

−

2 Rsum 4

−

Rsum 2

,

(3.47)

where Vdiff is the maximum permitted voltage difference. If ω1d tan−1 ωαd < DTsw , the current never converges to its maximum value (i.e., S( j+1)2 is turned off beforehand), and the peak inductor current is calculated per

3.3 Generic Micro Topologies and Interconnections

I Dmax2 < 

Vdiff Lj Ce

−

2 Rsum 4

−

Rsum 2

73

e−αDmax Tsw sin (ωd Dmax Tsw )

(3.48)

where 0 ≤ Dmax ≤ 1 is the maximum duty cycle of S( j+1)2 , and Tsw is the switching cycle. For a worst-case scenario, Dmax = 1 can be considered. The peak value of the inductor current also defines the current rating of clamping diode D j [28]. Therefore, either the inductor should be selected based on the current rating of the diode, or the maximum current rating of D j should be selected based on the clamping inductor. Solving for L j for the highest permitted voltage imbalance (Vdiff,max ) gives the lower boundary of the inductance per  L j ≥ min

Vdiff,max Rsum + I D,max1 2

2

R2 + sum 4



Vdiff,max Tsw Ce , I D,max2

 ,

(3.49)

and as long as the inequality described by (3.49) holds, the current of diode D j is within its rated boundary [28]. Additionally, it is possible to reduce the diode’s current rating by increasing the inductor’s size. However, a larger inductor value reduces the speed of the balancing [16]. On the other hand, the maximum permissible voltage difference depends on the balancing technique, tolerance of the capacitors, and the load current [20]. The next chapter presents a more detailed design procedure for the inductor as it develops the sensorless balancing technique [12, 38]. Although the principle operation of the diode-clamped topology is now clear, the limitation of unidirectional energy transfer still persists. Reference [39] solve the unidirectional balancing path using a high-voltage dc-dc converter that provides an isolated energy transfer path from the first module in each string (top module) to the last (bottom module). However, a high-voltage switching transformer tolerates the entire voltage of the string defeats the objective of diode-clamped structures to simplify the balancing procedure and reduce cost. Additionally, in most high-voltage applications, the switching frequency of the modules is relatively low (typically subkHz), which increases the size of the transformer or necessitates additional switches. Moreover, added stages of power conversion diminish the balancing efficiency, which is a strong focus in high-power applications. An alternative approach presented in [14] utilizes two parallel strings per arm with opposite balancing directions, with each string carrying half of the load current. While this load-sharing technique reduces the expense of high-current semiconductors, the overall cost and complexity of this solution are still considerably greater than that of a standard half-bridge topology, as noted in [12]. Reference [28] introduces a potential solution that involves a feedback control mechanism to regulate only the voltage of the upper module (V1 ) in a diode-clamped topology and adjust its modulation index to ensure the balance is maintained at all times. Reference [40] propose a relatively similar approach. These approaches use the simplest diode-clamped topology (e.g., half-bridge with an extra diode) and a

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3 Topology, Circuit Analysis, and Modeling

PID controller. However, they necessitate constant monitoring of the top module’s voltage in each arm and adjusting its target voltage to be lower than that of all the other modules. Hence, the top module is the sole element that is actively manipulated to balance the other modules by discharging them through the diode backbone rather than actively charging negative outliers. Consequently, this method is constrained by the weakest link and is susceptible to increased losses. In high-voltage and ultrahigh-voltage applications, voltage sensors need high-voltage isolation since the first module in the arm is at the highest electrical potential, as indicated in [12, 38]. Chapter 4 presents a sensorless balancing method integrated into the modulation scheme. Additionally, Chap. 6 presents a voltage monitoring technique that does not require any sensors at the modules.

3.3.2 Four Quadrant 3.3.2.1

Single-connection (Without Parallel)

Like the half-bridge module, the full-bridge topology can be analyzed according to the switch states, and the terminal voltages can be calculated. Figure 3.35 shows different modes of operation. Assuming, that the switches in each half-bridge are switched complementary (i.e., S1 = 1 − S2 and S3 = 1 − S4 ), the terminal voltage of the module for positive currents (during charge) is vt = (S1 − S3 )Vc + (S1rd1 + S2 rsw2 + S3rsw3 + S4 rd4 )i p ,

(3.50)

and for negative currents (during discharge) follows vt = (S1 − S3 )Vc + (S1rsw1 + S2 rd2 + S3rd3 + S4 rsw4 )i p ,

(3.51)

where i p is the string current which is positive during charge and negative during discharge. Equations (3.50) and (3.51) can be further simplified, by defining S = S1 − S3 , and assuming all the switches and diodes have similar resistances, i.e., rsw = rsw1 = rd1 = rsw2 = · · · = rd4 .

S1

S2

S1

2rsw1 or 2rd1

ECM of the storage

S2

75

2rsw1 or 2rd1

ECM of the storage

3.3 Generic Micro Topologies and Interconnections

+ vt _ S4

S3

S4

Mode 1

S2

S4

S1

S3

Mode 3

S3

Mode 2

S2

S4

S1

+ vt _

S3

+ vt _

rd2 or rsw2

Mode 4

Fig. 3.35 Different operating modes of full-bridge module

3.3.2.2

Multi-connection (With Parallel)

One interesting topology capable of generating both positive and negative voltages is the double FB topology. This topology consists of eight unidirectional switches (switches and an anti-parallel diode), which, compared to the four-quadrant FB topology, has two times the semiconductor. The discussions and comparisons between the two-quadrant FB and the HB topologies in the previous section (including, current sharing, similar die-area, lower effective impedance) are also true between the fourquadrant FB and the double FB topologies. With eight controlled switches, there are 24 possible modes, but only some of them are feasible. Figure 3.36 shows the main operation modes of the double FB topology. It is easier to study the possible operation modes considering the switch network (interconnection) between two modules rather than looking at each module independently. Figure 3.37 depicts the six feasible modes.

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3 Topology, Circuit Analysis, and Modeling

S2

S1

S2

S1

S2

S1

S4

S3

S4

S3

S4

S3

S6

S5

S6

S5

S6

S5

S8

S7

S8

S7

S8

S7

Mode 1 + Series to upper module + Series to lower module

Mode 2 − Series to upper module − Series to lower module

Mode 3 + Bypass

S2

S1

S2

S1

S2

S1

S4

S3

S4

S3

S4

S3

S6

S5

S6

S5

S6

S5

S8

S7

S8

S7

S8

S7

Mode 4 − Bypass

Modes 5 & 6 Modes 7 & 8 Parallel to upper module (1) Parallel to upper module (2) Both series or parallel to lower module is possible

Fig. 3.36 Different operating modes of the dual full-bridge module

Similar to the previous modules, equivalent circuits can be derived for this topology depending on the switch states [36]. Similarly, it is possible to include very small inductors between the two connection points to prevent current surges among modules. It is also possible to decouple the main load and the balancing currents’ paths using a single inductor in one of the connections.

References

77

S6

S5

S6

S5

S6

S5

S8

S7

S8

S7

S8

S7

S2

S1

S2

S1

S2

S1

S4

S3

S4

S3

S4

S3

Mode 2: −V1−V2

Mode 1: V1+V2

Mode 3: V1 or V2 is bypassed

S6

S5

S6

S5

S6

S5

S8

S7

S8

S7

S8

S7

S2

S1

S2

S1

S2

S1

S4

S3

S4

S3

S4

S3

Mode 4: V2 or V1 is bypassed

Mode 5: V1 || V2

Mode 6: V1 || V2

Fig. 3.37 Different operating modes of each interconnection with dual full-bridge modules

References 1. Berg, P. (2020). Novel controller to reduce high frequent components of battery currents in a MMC with parallel connection, Master’s thesis, Technische Universität Kaiserslautern. 2. Awan, M. H. U. (2022). Development of test bench for AC/DC based on modular multilevel converters (MMC’s), Master’s thesis, Technische Universität Kaiserslautern. 3. Banana, S. (2021). Sensorless voltage balancing of diode-clamped MMC modules with optimal phase-shifted level-adjusted carrier modulation, Master’s thesis, Technische Universität Kaiserslautern.

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4. Mani, S. (2022). Simulation and analysis of multiport cascaded full bridge converters, Master’s thesis, Technische Universität Kaiserslautern. 5. Cervera, L. O. (2020). A sensorless voltage estimation method for modular multilevel converter with half-bridge modules, Master’s thesis, Technische Universität Kaiserslautern. 6. Kurdekar, P. R. (2021). Voltage and resistance estimation of battery integrated cascaded converter, Master’s thesis, Technische Universität Kaiserslautern. 7. Iradukunda, A. (2020). Analysis of power loss in modular multilevel converters with parallel connectivity, Master’s thesis, Technische Universität Kaiserslautern. 8. Meyer, T. D. (2021). Development of a modular battery-integrated charger for E.V. applications, Master’s thesis, Technische Universität Kaiserslautern. 9. Tashakor, N., Kacetl, J., Fang, J., Li, Z., & Goetz, S. (2022). Dual-Port Dynamically Reconfigurable Battery with Semi-Controlled and Fully-Controlled Outputs. 10. Tashakor, N., Farjah, E., & Ghanbari, T. (2017). A bidirectional battery charger with modular integrated charge equalization circuit. IEEE Transactions on Power Electronics, 32, 2133– 2145. 11. Zheng, T., Gao, C., Liu, X., Liao, X., Li, Z., Sun, B., & Lv, J. (2020). A novel high-voltage DC transformer based on diode-clamped modular multilevel converters with voltage self-balancing capability. IEEE Transactions on Industrial Electronics, 67, 10304–10314. 12. Tashakor, N., Kilictas, M., Bagheri, E., & Goetz, S. (2021). Modular multilevel converter with sensorless diode-clamped balancing through level-adjusted phase-shifted modulation. IEEE Transactions on Power Electronics, 36, 7725–7735. 13. Xu, J., Feng, M., Liu, H., Li, S., Xiong, X., & Zhao, C. (2018). The diode-clamped half-bridge MMC structure with internal spontaneous capacitor voltage parallel-balancing behaviors. International Journal of Electrical Power & Energy Systems, 100, 139–151. 14. Gao, C., & Lv, J. (2017). A new parallel-connected diode-clamped modular multilevel converter with voltage self-balancing. IEEE Transactions on Power Delivery, 32, 1616–1625. 15. Tashakor, N., Kılıçta¸s, M., Fang, J., & Goetz, S. M. (2021). Switch-clamped modular multilevel converters with sensorless voltage balancing control. IEEE Transactions on Industrial Electronics, 68, 9586–9597. 16. Jin, Y., Xiao, Q., Dong, C., Jia, H., Mu, Y., Xie, B., Ji, Y., Chaudhary, S. K., & Teodorescu, R. (2019). A novel submodule voltage balancing scheme for modular multilevel cascade converter’ double-star chopper-cells (MMCC-DSCC) based STATCOM. IEEE Access, 7, 83058–83073. 17. Xu, J., Li, J., Zhang, J., Shi, L., Jia, X., & Zhao, C. (2019). Open-loop voltage balancing algorithm for two-port full-bridge MMC-HVDC system. International Journal of Electrical Power & Energy Systems, 109, 259–268. 18. Xu, J., Zhang, J., Li, J., Shi, L., Jia, X., & Zhao, C. (2018). Series-parallel HBSM and two-port FBSM based hybrid MMC with local capacitor voltage self-balancing capability. International Journal of Electrical Power & Energy Systems, 103, 203–211. 19. Tashakor, N., Li, Z., & Goetz, S. M. (2021). A generic scheduling algorithm for low-frequency switching in modular multilevel converters with parallel functionality. IEEE Transactions on Power Electronics, 36, 2852–2863. 20. Fang, J., Yang, S., Wang, H., Tashakor, N., & Goetz, S. M. (2021). Reduction of MMC capacitances through parallelization of symmetrical half-bridge submodules. IEEE Transactions on Power Electronics, 36, 8907–8918. 21. Fang, J., Blaabjerg, F., Liu, S., & Goetz, S. M. (2021). A review of multilevel converters with parallel connectivity. IEEE Transactions on Power Electronics, 36, 12468–12489. 22. Korte, C., Specht, E., Hiller, M., & Goetz, S. (2017). Efficiency evaluation of MMSPC/CHB topologies for automotive applications. In 2017 IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS) (pp. 324–330). 23. Goetz, S. M., Peterchev, A. V., & Weyh, T. (2015). Modular multilevel converter with series and parallel module connectivity: Topology and control. IEEE Transactions on Power Electronics, 30, 203–215. 24. Zhao, C., Wang, Z., Li, Z., Wang, P., & Li, Y. (2019). Characteristics analysis of capacitor voltage ripples and dimensioning of full-bridge MMC with zero sequence voltage injection. IEEE Journal of Emerging and Selected Topics in Power Electronics, 7, 2106–2115.

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25. Yang, W., Song, Q., Xu, S., Rao, H., & Liu, W. (2018). An MMC topology based on unidirectional current H-bridge submodule with active circulating current injection. IEEE Transactions on Power Electronics, 33, 3870–3883. 26. Liu, W., Li, G., Liang, J., Ugalde-Loo, C. E., Li, C., & Guillaud, X. (2020). Protection of single-phase fault at the transformer valve side of FB-MMC-based bipolar HVdc systems. IEEE Transactions on Industrial Electronics, 67, 8416–8427. 27. Hu, P., & Jiang, D. (2015). A level-increased nearest level modulation method for modular multilevel converters. IEEE Transactions on Power Electronics, 30, 1836–1842. 28. Liu, X., Lv, J., Gao, C., Chen, Z., Guo, Y., Gao, Z., & Tai, B. (2017). A novel diode-clamped modular multilevel converter with simplified capacitor voltage-balancing control. IEEE Transactions on Industrial Electronics, 64, 8843–8854. 29. Tashakor, N., Arabsalmanabadi, B., Zhang, Y., Al-Haddad, K., & Goetz, S. (2021). Efficiency analysis of conduction losses in modular multilevel converters with parallel functionality. In IECON 2021 – 47th Annual Conference of the IEEE Industrial Electronics Society (pp. 1–6). 30. Tashakor, N., Iraji, F., & Goetz, S. M. (2022). Low-frequency scheduler for optimal conduction loss in series/parallel modular multilevel converters. IEEE Transactions on Power Electronics, 37, 2551–2561. 31. Goetz, S. M., Li, Z., Liang, X., Zhang, C., Lukic, S. M., & Peterchev, A. V. (2017). Control of modular multilevel converter with parallel connectivity-application to battery systems. IEEE Transactions on Power Electronics, 32, 8381–8392. 32. Li, Z., Yang, A., Chen, G., Tashakor, N., Zeng, Z., Peterchev, A. V., & Goetz, S. M. (2023). A rapidly reconfigurable DC battery for increasing flexibility and efficiency of electric vehicle drive trains. IEEE Transactions on Transportation Electrification, 1. 33. Novakovic, B., & Nasiri, A. (2017). Modular multilevel converter for wind energy storage applications. IEEE Transactions on Industrial Electronics, 64, 8867–8876. 34. Tashakor, N., Arabsalmanabadi, B., Naseri, F., & Goetz, S. (2022). Low-cost parameter estimation approach for modular converters and reconfigurable battery systems using dual Kalman filter. IEEE Transactions on Power Electronics, 37, 6323–6334. 35. Tashakor, N., Kacetl, J., Kacetl, T., & Goetz, S. (2022). Modular battery-integrated power electronics-modelling, advantages, and challenges. In 2022 24th European Conference on Power Electronics and Applications (EPE’22 ECCE Europe) (pp. 1–10). 36. Goetz, S. M., Li, Z., Peterchev, A. V., Liang, X., Zhang, C., & Lukic, S. M. (2016). Sensorless scheduling of the modular multilevel series-parallel converter: enabling a flexible, efficient, modular battery. In 2016 IEEE Applied Power Electronics Conference and Exposition (APEC) (pp. 2349–2354). 37. Tashakor, N., Zhang, Y., Banana, S., Blaabjerg, F., & Goetz, S. (2023). Voltage Estimation for Diode-Clamped MMC Using Compensated State-Space Model. 38. Tashakor, N., Keshavarzi, D., Banana, S., & Goetz, S. (2022). Voltage estimation for diodeclamped MMCs based on a simplified neural network. In 2022 24th European Conference on Power Electronics and Applications (EPE’22 ECCE Europe) (pp. 1–10). 39. Gao, C., Jiang, X., Li, Y., Chen, Z., & Liu, J. (2013). A DC-link voltage self-balance method for a diode-clamped modular multilevel converter with minimum number of voltage sensors. IEEE Transactions on Power Electronics, 28, 2125–2139. 40. Yin, T., Wang, Y., Wang, X., Yin, S., Sun, S., & Li, G. (2018). Modular multilevel converter with capacitor voltage self-balancing using reduced number of voltage sensors. In 2018 International Power Electronics Conference (IPEC-Niigata 2018 -ECCE Asia) (pp. 1455–1459).

Chapter 4

Modulation and Scheduling Techniques

This book chapter offers an in-depth investigation of various modulation strategies and their potential when combined with parallel-connected modules. The chapter studies low-frequency modulation strategies such as nearest level modulation, and pulse-width-modulations such as phase-shifted carrier and level-shifted carrier. Each strategy is thoroughly analyzed, and its applicability is discussed in detail. Furthermore, the chapter develops novel balancing and scheduling schemes, including for both low-switching-rate modulation strategies as well as scheduling/balancing for pulse-width modulations. Furthermore, novel concepts such as sensorless balancing for diode-clamped topologies, optimum switching loss, and optimum conduction loss scheduling algorithms for topologies with parallel mode are presented. The chapter also examines the combination of different modulation and scheduling algorithms, comparing their performance across various applications and scenarios. This comprehensive analysis makes it an essential read for those seeking a deeper understanding of modulation strategies, their implementation, and their application with a specific focus on topologies capable of parallel connectivity. Collaboration with Mr. Jan Kacetl and Dr. Jingyang Fang has contributed to developing implementation techniques for different modulation schemes and multiple patents. Dr. Farzad Iraji collaborated in developing the modulation strategy to optimize the conduction loss. Multiple bachelor and master students have also collaborated in developing this chapter while I was serving as their thesis supervisor [1–6]. Publications from these collaborations are cited to acknowledge their support and help throughout the chapter.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1_4

81

82

4 Modulation and Scheduling Techniques

4.1 Intro The modulation technique, also known as the switching strategy or switching scheme, is the rule or method that determines the semiconductors’ states. In MMS or even in modular reconfigurable power electronics, the achievable performance depends highly on an appropriate modulation and switching scheme [7]. Considering the DoFs in such a system, the modulation strategy can significantly impact the control’s performance and complexity. In general, the modulation strategies can be categorized into (i) pulse-width modulation (PWM) strategies, (ii) shape-forming modulation strategies, and (iii) optimization-based techniques. As one of the main goals of this work is to reduce the system’s complexity and make the controllers feasible, the techniques based on online (numeric) optimization are not covered. Instead, this chapter develops algorithms that can perform optimally without numerically solving an optimization function. In the PWM-based schemes, the reference/control signal, also known as the modulation index, is compared with a much higher-frequency waveform, typically with a saw-tooth or triangular shape, to determine the module states. Phase-shifted carrier (PSC) and level-shifted carrier (LSC) modulations are well-known solutions in this group. These methods are more prevalent in lower voltage applications where the primary semiconductors are MOSFETs. Space-vector modulation is another popular technique in this category. However, space-vector modulation often involves undesirable complexity with a high number of modules, making them unfeasible in high-voltage systems. The shape-forming modulator utilizes the higher voltage quantization due to numerous modules to generate a waveform that tracks the reference signal or modulation index as closely as possible. This modulation strategy aims to track the reference signal as closely as possible without excessive switching. Such a strategy is favored in ultra-high-voltage applications with hundreds of modules, allowing for much higher output voltage granularity. This category includes nearest level modulation (NLM) and harmonic mitigation/elimination modulations with low switching rates. In methods based on optimization, an optimization function determines the switching states to minimize the defined cost functions. Methods based on machine learning and model-predictive controllers are some examples of this group of modulation strategies. There is a significant difference between determining the modulation reference or index using machine learning or optimization and actual switch states. The former can be easily integrated with any of the three modulation groups, requires a considerably lower update rate, and can be feasible for real-time applications but requires accurate modeling. However, the latter determines the actual switch states of each module or their connection mode, which requires a significantly higher update rate and is computationally more demanding. Nevertheless, the use of methods that directly calculate the switching state of the modules is increasing.

4.2 Modulation

83

Some techniques can also be combined, and in many applications, they are not easily distinguished from one another. For example, combining the shape forming and PWM methods can achieve a better trade-off between switching frequency and the output voltage quality. Many modulation strategies, such as NLM, can calculate the required number of series, bypass, and parallel connections in a string but fail to provide the priority by which the modules should be connected. As Chap. 3 presented, mapping the connections throughout the string (i.e., the order of series, parallel, and bypass states) significantly impacts the string’s impedance. The algorithm which determines the optimal configuration of these connections throughout the arm is known as the scheduler. As one of the main functions of such an algorithm is to ensure a balanced and stable operation, in scientific references, a scheduler is also known as the balancing subroutine.

4.2 Modulation The majority of modulation techniques involve converting the continuous reference voltage into a limited number of voltage levels. Hence, a modulation strategy determines the required number of series connections, denoted here as Ns , from the reference voltage. A considerable number of modulation schemes have been proposed for conventional MMCs and other multilevel converters, but only a few take into account the possibility of parallel connectivity and its effect on the performance of the switching and modulation methods [7–11]. Hence the main focus of this section is to adopt the available state-of-the-art techniques for more advanced topologies and improve the performance considering the inherent differences of such structures with conventional technology. A potential solution to address this issue is to adjust established switching algorithms to take advantage of the capabilities of parallel-capable topologies and their unique features. As we studied in the introduction of the chapter, available modulation schemes for MMCs or MMSs can be categorized into low-frequency (shape forming), PWMbased (often with high switching rate), and optimization-based strategies. In many ways, the first two categories have the same principle of operation and the main differences are in the switching frequency and the distribution of the switching instances within a cycle. Nevertheless, each category has its own advantages and disadvantages warranting further study. In larger systems with numerous modules, fundamental- or low-frequency switching modulation techniques are often utilized because they provide a better trade-off between voltage quality and power losses. Nearest-level modulation (NLM) is a general low-frequency switching scheme that is one of the better-known techniques in this category, even though there are other approaches as well. Although there has been extensive research into NLM and its variations, the focus so far has been exclusively on conventional modular structures that utilize half-bridge module topologies [12].

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4 Modulation and Scheduling Techniques

However, the exact adaptation of the conventional methods does not perform well when parallel connections are added or fail to take advantage of the extra capabilities [13]. PWM or PSC based methods in ultra-high-voltage applications where the high switching loss due to high switching rates reduces the efficiency are also not appealing or limit flexibility, e.g., to operate under asymmetric grid conditions [14]. In comparison, these methods are favored in low- to medium-voltage applications where fewer modules are employed, and lower-voltage semiconductors have a better switching performance. However, the advancements in the field of SiC and GaN technologies with significantly better switching performance can increase the applicability of PWM strategies in high-voltage applications. When considering optimizing a modulation technique for parallel-capable topologies, the inherent differences between the behavior during parallel mode and bypass should be considered, which can impact the overall system’s performance. As Chap. 3 shows, in contrast to strings with conventional HB and FB modules, where the number of series and bypass connections determines the equivalent arm impedance, the arrangement of the series and parallel connections in multi-connection topologies can also significantly impact the equivalent circuit and impedance.

4.2.1 Low-Frequency Modulation The low-frequency modulation strategies particularly suit high-voltage and ultrahigh-voltage systems with dual-arm structures. Therefore, the following presents a generic NLM for a dual-arm structure that can be applied to conventional and advanced topologies with parallel connectivity.

4.2.1.1

Nearest Level Modulation

As shown in Figs. 3.11 and 3.12, various topologies have been reported in the literature for MMSs. Through (3.12), the output phase voltage is   d vph = 0.5 (v L − vU ) − 0.5 L arm + Rarm i ph . dt

(4.1)

The reference value for the phase voltage, neglecting the voltage across the resistance and inductance, follows from vph,ref (t) =

1 m x Vdc sin (ωt) 2

(4.2)

4.2 Modulation

85

where 0 ≤ m x ≤ 1 is the modulation index amplitude. Similarly, the upper and lower reference voltages are 1 Vdc (1 − m x sin (ωt)) , 2 1 v L,ref (t) = Vdc (1 + m x sin (ωt)) . 2

vU ,ref (t) =

(4.3a) (4.3b)

Normalizing the voltage references with the maximum achievable voltage in each case results in m ph (t) = m x sin (ωt), 1 m U (t) = (1 − m x sin (ωt)) , 2 1 m L (t) = (1 + m x sin (ωt)) . 2

(4.4a) (4.4b) (4.4c)

The arms reference voltages determine the required number of series connections through quantization of the output voltage. The modulation references m U , m L , m ph are then used to determine the modules’ connections throughout the arms, and in combination with the scheduling functions (e.g., balancing, loss optimization), the complete mapping of the modules’ states (vector S). As presented in [15], in a conventional NLM (CNLM), the modules in the upper and lower arms are switched complementary, e.g., if a module in the upper arm is switched in series, another module in the lower arm is bypassed). The complementary switching results in (N + 1) voltage levels for N modules per arm. One alternative π phase-shift between switching of the upper and lower arms, approach is to create a 2N known as PSANLM, which boosts the number of available voltage levels in the dualarm configuration to (2N + 1). Better granularity in the phase voltage decreases the output total harmonic distortion (THD) as well as the module operating voltage from Vdc dc to N V+0.5 . In the case of the second modulation scheme, when (N + 1) series N modules are connected in parallel to the dc side, the voltage discrepancy between dc . The surge current caused the dc side and (N + 1) modules in series equals N0.5V +0.5 by this voltage difference is limited by the inductor. Consequently, the stress and voltage drops on the arm inductors are slightly elevated [13, 16]. However, the voltage difference and consequently the stress across the arms’ inductors reduces as the number of modules per arm increases. The number of series connections in the upper (NsU ) and lower (Ns L ) arms for CNLM and PSANLM, respectively, is determined per [13, 16]  NsU = round

N vU,ref Vdc



 , Ns L = round

N vL,ref Vdc

 (4.5)

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4 Modulation and Scheduling Techniques



N vU,ref Vdc

NsU = round



 , Ns L = round

 N vL,ref + 0.25 . Vdc

(4.6)

After calculating Ns L and NsU by the modulator, the results are fed to scheduling, balancing, or optimization algorithms to devise which modules should switch to realize the most suitable arrangement. It is possible to analyze the THD of the voltage based on the fundamentalfrequency voltage for an arbitrary number of voltage levels and switching rates [17]. The fundamental amplitudes based on CNLM and PSANLM are N   4Vm  cos α j → CNLM, π j=1

(4.7)

2N   2Vm  cos α j → PSANLM, π j=1

(4.8)

A1 = A1 =

where 0 < α1 < · · · < α N < π2 and 0 < α1 < · · · < α2N < π2 are respectively the angles of switchings for CNLM and PSANLM in the first quarter-cycle. Consequently, the order of switchings can be derived for the other three quarter-cycles assuming a fully sinusoidal output. The THD of the output voltage for each modulation scheme can be calculated by comparing the acquired amplitudes with the resulting voltage waveform following  THDV =

2 π

 Nϕ ϕ j+1 j=0

ϕj

2

(V j,d − A1 cos(ϕ))dϕ A1

,

(4.9)

N for CNLM , ϕ0 = 0, and ϕ j is the jth switching instance. 2N for PSANLM The PSANLM generates considerably lower harmonics content. However, this comes at the cost of higher voltage drop and stress on the arm inductors and slightly lower module voltage, resulting in a slightly lower amplitude for the fundamental harmonic [16]. The comparison is presented in more detail for different systems after the development of the optimized scheduling methods (see Sect. 4.3.4.3), but Fig. 4.1 presents an example of the resulted output voltages for each of these two outputs from CNLM and PSANLM. Table 4.5 presents the parameters of the system. In Fig. 4.1, N = 8 and the modulation index amplitude (m x = 0.95). The quality of the output voltage according to PSANLM is better for PSANLM, although the amplitude of the voltage has slightly reduced. where Nϕ =

4.2 Modulation

87 5

Vph [kV]

Fig. 4.1 Resulted phase voltage waveforms for CNLM and PSANLM techniques

CNLM PSANLM

0

-5 1.96

1.965

1.97

1.975

1.98

1.985

1.99

1.995

2

time [sec]

4.2.2 Pulse-Width-Modulation Strategies Modulation methods based on PWM compare the reference signal or modulation index with a repetitive pattern (called the carrier) to generate the necessary switching commands. The underlying implementation of these methods for a single module is relatively similar to any other switching converter. However, the shape of the carriers and their relation to each other in a multi-module structure can strongly affect the system’s overall performance. Two of the most well-known modulation techniques in modular reconfigurable storages are PSC and LSC modulations, which we will study in detail. Additionally, a novel modulation technique from the combination of these two methods will be presented.

4.2.2.1

Phase-Shifted Carrier Modulation

The PSC modulation involves comparing a reference waveform to several PSCs in order to produce control signals for the modules. PSC has the advantage of inherent module scheduling, i.e., translating voltage levels into specific states for each module, increased effective switching frequency, and excellent voltage quantization, making it the preferred choice in low-voltage high-power applications. In traditional PSC modulation, the entire switching cycle is distributed among various carriers, with each carrier representing a set of switches. The modulation index is contrasted with the appropriate carrier for each module to produce the switching signals. The actual switching logic depends on the specifications of the applications. Nonetheless, typically, if the modulation index is greater than the carrier, the module will be connected in series. Conversely, when the modulation index is smaller, the module will either be bypassed or linked in parallel with a different module [13, 16]. With NC denoting the count of all distinct carriers in the system, in the context of conventional PSC modulation, the phase-difference (ϕ) between a pair of adjacent carriers is

88

4 Modulation and Scheduling Techniques

ϕ = k2π/NC .

(4.10)

In typical applications with a single output per string, k = 1, and all the modules form the output. However, it is also possible to form subsets in the string, where each subset has L carriers with a symmetric PSC. For example, for NC = 9, subsets of {1, 3, 9} can be formed. Therefore, k can be also a factor of NC ( {k∈ N| ∃L∈ N with k × L = NC }). Figure 4.2 shows an intuitive representation of one group including L = NkC carriers from the total NC carriers in the string, and k is the number of formed groups. As long as the carriers in the same group are divided evenly within one cycle of switching, the carrier’s order is inconsequential. Meaning that the order by which the carriers are assigned to modules in the string/group will not matter in a conventional topology. For example, for L = 3, the  of three cascaded modules with  output

4πvoltage

effective 4π 2π are identical. As even distribution and the phase-shift vectors of 2π 0 0 3 3 3 3 of phase-shifts in the conventional PSC creates a symmetry both in the output and in the switching, conventional PSC is also referred to as symmetrical PSC. Distributing the phase-shift of carriers has the benefit of increased output frequency [11]. Figure 4.3 illustrates the effective signal observed from the output that contains carriers that are evenly distributed. By employing symmetric PSC, the resulting carrier exhibits an amplitude of L1 and a frequency of L f sw . Chapter 5 presents a more detailed explanation of carrier distribution, and here for simplicity, we assume K = 1 and L = NC = N . With symmetric PSC modulation, only two voltage levels are produced, namely Vbase and Vbase + Vm . Figure 4.4 depicts that the resulting output voltage contains a pulsing voltage (Vpulse ) added on top of a base level (Vbase ) with a non-zero average term in one complete switching cycle [18, 19]. In dc applications, the Vavg is the dc output voltage. In ac applications, provided the switching frequency is significantly higher than the fundamental frequency, Vavg can approximate the instantaneous value

Carriers 1

CL

C

C Modulation Reference (m)

4

0 time L Fig. 4.2 Intuitive representation of carriers in conventional PSC modulation

4.2 Modulation

89

Modulation

Modulation Reference (m)

L

Fig. 4.3 Intuitive representation of carriers in conventional PSC modulation Fig. 4.4 Generic shape of output in case of a symmetric PSC modulation

Modulation

Output Voltage

vM

of the fundamental frequency of the output. Regardless, in both cases, the average voltage can be calculated per Vavg = m NC Vm ,

(4.11)

where m is the modulation index, NC is the number of carriers (also corresponding modules) in the formed group/string, and Vm is the voltage of one module. Equation (4.11) is valid, assuming the modules are balanced and there are no parasitic elements. Otherwise, the average of modules’ voltages should be considered as described in (3.2). In an ac application, the modulation references for the phase voltage follows m ph = m x sin (ωt)

(4.12)

where 0 ≤ m x ≤ 1 is the modulation index amplitude. In a dual-arm topology, the upper and lower reference voltages are 1 (1 − m x sin (ωt)), 2 1 m L = (1 + m x sin (ωt)). 2

mU =

(4.13a) (4.13b)

90

4 Modulation and Scheduling Techniques

The modulation references m U and m L are combined with the balancing/scheduling outputs, which results in a slightly different modulation index for each module (m j ). Next, the individual modulation index of each module is compared to its respective carrier to determine the module’s state in the arm. The connection of the jth module is determined per SU/L , j =

series m U/L , j ≥ C j , bypass/parallel m U/L , j < C j

(4.14)

for the dual-arm topology. Similarly, for the single-arm structures, the reference voltage is m = m x sin (ωt),

(4.15)

and the complete map of the connections (S) throughout the arm is determined using (4.16). ⎧ mj ≥ Cj ⎨ Positive series bypass/parallel −C (4.16) Sj = j ≤ mj < Cj . ⎩ Negative series m j < −C j With NC modules and carriers per arm, there are (N + 1) voltage levels for dualarm and single-arm structures using conventional PSC modulation. The fundamental amplitude of the voltage can be calculated per

A1 =

f sw NC 2 f1



  4Vm  (−1)k cos α j → PSC, π j=1

(4.17)



1 positive step . 0 negative step The low switching rate PSC modulation has a poor performance compared to NLM-based modulations. By comparing (4.7), (4.8), and (4.17), it is clear that the switching frequency of PSC must be higher than the fundamental frequency to achieve comparable THD. This is clear in Fig. 4.5, where waveforms of the resulted voltages from CNLM, PSANLM, and PSC are compared. Similar to the NLM, in the case of the dual-arm topology, it is possible to create an additional phase shift between the carriers of the upper and lower arms, which can result in a significant improvement in the output-voltage quality. Conventionally, the phase-shifts of the carriers for the upper and lower arms are identical and defined per where 0 < α1 < α2 < · · ·


(N − 1)ε2 . 2

(4.36)

Considering the imbalances due to the discretization delay can slightly increase the required level adjustments [22].

4.3.3.1

Principle Operation of the System and Design Procedure

In Sect. 3.3.1.2, the operation of the diode-clamped circuit is described. The minimum value of inductance is determined by (3.49), whereas the upper limit is determined by the level adjustment, switching, and fundamental frequencies of the system. The inductance should be chosen such that it is low enough to balance the added circulating current within one cycle of the arm current as discussed in [24, 26]. The average amplitude of the balancing current due to the level adjustment is approximately I x ,min = Idc,min

I p,min x = . N −1 2k(N − 1)

(4.37)

The modules are balanced when S( j+1)2 is on, and the average duration that S( j+1)2 is on follows T S( j+1)2 =

1 . 2Tsw

(4.38)

The average attainable current of the inductor should be larger than the average circulating current per Vdiff,max T S( j+1)2 I P,min x > , Lj 2 2k(N − 1)

(4.39)

which describes the upper boundary of the clamping inductance and can be rewritten per Lj ≤

x I P,min T S( j+1)2 Vdiff,max (N − 1)

.

(4.40)

Therefore, the required value of the inductor can be determined by using Eqs. (3.49) and (4.40), after finding the permissible diode current [24, 27]. An alternative to the LAPSC modulation is directly integrating δ j s into the control of the modulation index as a small offset. Both cases cause almost no computational effort as one of the main appeals of the diode-clamped MMCs. Zero offsets in the individual modulation indices lead to all modules having the same average series

100

4 Modulation and Scheduling Techniques

connection duration. If δ j represents the introduced negative offset in the modulation reference, δ1 ≥ δ2 ≥ · · · ≥ δ N ensures an upward balancing direction (bottom of the arm to the top of the arm) at all times. Without lack of generalization, the effective modulation index m j for the jth module of the upper arm with δU, j follows m U, j =

1 − m x sin (ωt) − δU, j , 2

(4.41)

Which is identical to the effect of a positive level adjustment. Similarly, the effective modulation index for the entire arm can be written, similar to (4.27). Based on the symmetry and assuming identical clamping branches with sufficiently large switching frequencies, the average clamping current of the jth clamping branch in the upper arm follows  (N − j) j 1 + m x sin(ωt) iU (t)x ,0 , i b j ,U (t) = max 2 N −1 

(4.42)

where j = 1, . . . , (N − 1) and iU is the upper arm current. The max(. . .) function shows that the clamping branch conducts only in the positive direction. Similarly, the clamping current equation for the lower arm is  i b j ,L (t) = max

 (N − j) j 1 − m x sin(ωt) i L (t)x ,0 . 2 N −1

(4.43)

Although a symmetrical definition of the adjustments using (4.30) can help to reduce the effects of balancing in the voltage shape, many of the balancing strategies do not follow such conventions. Nevertheless, the operating principles of the balancing algorithms remain unchanged. The average value of the arm current is always positive. However, higher harmonic content, such as first-order and second-order components, can result in instances where the arm current is negative. A negative arm current combined with the openloop balancing techniques can reduce the balancing efficiency, even though it is still stable. Therefore, an improved level-adjustment control follows  δu, j = sgn(iU )x

 1 j −1 − , 2 N −1

(4.44)

where sgn(...) is the sign function. Controlling the level adjustment according to (4.44) maintains all the previous advantages in addition to improved efficiency. Although (4.44) is not a fully open-loop balancing method, it still does not require direct measurements at the modules level. Additionally, the arm currents are usually available for higher-level controllers, and extra sensors are unnecessary. The cellsorting algorithms are not necessary here, but the sign of the arm current must be closely monitored to control the level adjustment. The read-out of the arm current’s

4.3 Scheduling

101

sign needs at least two updates per fundamental cycle or a phase-locked-loop unit, even though it can be easily estimated [24].

4.3.3.2

Power Loss Analysis of LAPSC Modulation

The focus of this section is analyzing the power losses and understanding the impact of level adjustment on balancing losses. It has been demonstrated that the level adjustment does not alter the system’s behavior at the arm and phase levels as per Eq. (4.28). Additionally, the total number of switches and diodes conducting throughout the arm remains unchanged because the displacements and phase shifts are complementary. Hence, it is possible to calculate the power loss resulting from the arm current by numerical techniques, as done for conventional MMC systems, without depending on the value of the level adjustment [28]. A simpler approximation of power loss due to the arm current can be derived based on the average and RMS values of the current, considering equal conduction losses for both diodes and switches. This approximation assumes that power switches and diodes have identical conduction loss, with voltage drops and internal resistances being the same for both (i.e., Vsw = Vfd = V0 and rsw = rd = r ) [24]. The RMS current of the switches and diodes, the capacitor’s RMS current, and the average current of the switches and diodes are respectively given by Irms,cap

IP = 4



m 2x + 2 − 4km x cos(ϕ) 4m 2x + 4 − m 2x cos(ϕ) , + 2k 2 8

Irms,arm

IP = 2



Iavg,arm =

(4.45)

1 1 + , 2 k 2

(4.46)

IP . 2k

(4.47)

Therefore, the power loss in one arm follows      1 Vm Iavg,sw (ton + toff ) + Nrc Irms,cap + 2N f sw 2 (4.48) Nsw

Ploss = N Iavg V0 +

2 Nr Irms,arm

where toff and ton are rated durations of the turn-on and turn-off intervals in the switches, and Vm is the average operating voltage of the modules. The power loss calculation in (4.48) does not take into account the balancing loss. The balancing loss needs to be calculated separately, and determining its exact value requires detailed numerical simulations. Nevertheless, it is possible to estimate the maximum additional power loss due to the introduced balancing current [24].

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4 Modulation and Scheduling Techniques

By exploiting the symmetry between the carriers level shifts, the additional power loss due to the generated circulating current between the jth and (N − j)th modules can be expressed as j,N − j

E loss

 =

   Irms,arm x 2 Irms,arm x (N − 2 j + 1)V0 . (N − 2 j + 1)2 (r L + 2r ) + (N − 1) (N − 1)

(4.49) The total balancing loss of one arm is the sum of the energy lost between all the modules, which can be expressed as  Pbalancing =

Irms,arm x (N − 1)  +

2

N

2  (N − 2 j + 1)2 (r L + 2r )

Irms,arm x (N − 1)

j=1



(4.50)

N

V0

2 

(N − 2 j + 1).

j=1

Based on (4.48), the balancing loss increases as x or load increases.

4.3.3.3

General Discussion and Comparison

The main advantages of the developed solution compared to state-of-the-art include • With just a single additional diode and sensorless balancing, the suggested topology requires the least number of extra components. • The topology can operate stably without the need for any control mechanism to balance the module voltages. • The method presented can attain high efficiency. • The balancing mechanism does not negatively impact the system’s output quality. While cost may not be the primary concern in ultra-high-voltage grid applications such as HVDC, the situation is different in lower-voltage and lower-power applications, where modular power electronics are increasingly being used. Highpower yet low- to medium-voltage applications have different cost structures, packaging or robustness constraints, and safety prerequisites. Table 4.1 presents the estimation of cost1 between sensor-based methods and the developed sensorless balancing technique for the experimental testbench in the following section (see Sect. 4.3.3.4). According to the given data, the cost of using a traditional approach is significantly higher (3–5 times) than the presented technique for low-voltage applications. As the voltage and power levels increase, the difference in cost between the two methods 1

All prices are per piece for at least 10,000 pieces, accessed in 2021.

4.3 Scheduling

103

Table 4.1 Cost comparison of developed sensorless balancing method with the conventional sensorbased method. © 2021 IEEE. Reprinted, with permission, from [24, 25] Sensorless method Direct measurement Diode (SS110-HF) Small magnetic core (MP1710MDGC) _

e0.04 e0.87

_

_

_

Voltage Divider Isolated power supply Circuit (PCN2-S5-D15-S) Isolated ADC (AMC1303M2510DWVR) Digital multiplexer (SY54017ARMG)

e0.04 e3.6 e2.8 e1.88

becomes smaller, and in ultra-high-voltage applications, the costs can be similar for both approaches [24].

4.3.3.4

Simulation and Experimental Validation

The LAPSC modulation technique was implemented and studied in a single-phase model using MATLAB/Simulink, which allowed for a detailed analysis of the system behavior. To further validate the technique, a prototype with eight modules was constructed, providing proof of concept. Table 4.2 provides a list of the simulation and experimental system parameters. The simulation utilized SEMiX854GB176HDs power modules from Semikron for modeling the semiconductors, while other system parameters were determined based on design instructions. In the simulations, the study examined four different scenarios, namely (i) matching modules with x = 0, (ii) matching modules with x = 0.2%, (iii) modules with mismatched capacitors, and (iv) modules with different leakage current. The capacitances and internal resistances of the imbalanced modules in the third system

Table 4.2 Simulation and experiment parameters used to study the sensorless balancing performance using LAPSC modulation Circuit parameters Simulation Experiment Number of modules DC-link voltage Module’s capacitance Fundamental frequency Modulation amplitude (m) Switching rate Arm inductor Clamping inductance

40 24 kV 15 mF 50 Hz 0.95 5 kHz 10 mH 10 µH

8 180 V 5.5 mF 50 Hz 0.95–0.75 5 kHz 2 mH 7.5 µH

104

4 Modulation and Scheduling Techniques

Table 4.3 Mismatches in the modules’ parameters In simulation Changes reduced to 32 k reduced to 28 k reduced to 24 k reduced to 20 k reduced to 16 k reduced to 12 k reduced to 8 k reduced to 4 k Changes reduced to 3.5 mF reduced to 68 k reduced to 4.5 k

Vout [kV]

Leakage resistance of S M4,U Leakage resistance of S M9,U Leakage resistance of S M14,U Leakage resistance of S M19,U Leakage resistance of S M4,L Leakage resistance of S M9,L Leakage resistance of S M14,L Leakage resistance of S M19,L In Laboratory Prototype Capacitance of S M1,U and S M3,L Leakage resistance of S M1,U Leakage resistance of S M3,L

time [sec] Fig. 4.10 Output voltages for different scenarios using LAPSC modulation. © 2021 IEEE. Reprinted, with permission, from [24]

 j C and rC j = (1 − ε + 2ε) r , where ε = 30% are defined per C j = 1 + ε − 2ε NN − −1 Also, Table 4.3 depicts the altered parameters. Figure 4.10 illustrates the output phase voltage for all scenarios. In general, the phase voltages are almost perfectly sinusoidal with very small differences. However, upon closer inspection, minor high-frequency ripples can be observed due to the balancing process. Table 4.4 provides the THD values for various scenarios. It demonstrates that even level adjustments as high as 2% (x = 0.02) have a negligible negative effect (below 0.04%) on the quality of the phase voltage.

4.3 Scheduling

105

Table 4.4 THD values of the output voltage for different scenarios Condition THDV (%) Matching modules, x = 0 Matching modules, x = 0.001 Matching modules, x = 0.02 Modules with different capacitances, x = 0.02 Modules with different self-discharge, x = 0.02

0.74 0.74 0.77 0.77 0.78

SMvoltage [kV]

1.3

1.25

1.2

1.15

1.1 1

2

VSM,max Lower Arm

VSM,max Upper Arm

VSM,min Lower Arm

VSM,min Upper Arm

3

4

5

6

time [sec]

7

8

9

10

Fig. 4.11 Module voltages with balanced parameters and zero level-adjustment (x = 0). © 2021 IEEE. Reprinted, with permission, from [24]

Figure 4.11 examines the balancing performance of the proposed technique. As discussed earlier, the simulation results presented in Fig. 4.11 indicate that even with identical modules, the voltages gradually deviate from their rated value. Figure 4.12 demonstrates that the same system will be stable with a deviation of x = 0.2%. Based on the loss analysis, the maximum increase in power loss with x = 0.2% is approximately 0.01% in all situations. Furthermore, according to Fig. 4.15, the added power loss is even lower [24]. Figure 4.13 illustrates the response of a system where modules have distinct capacitances and internal resistances. When the level shift is raised from 0% to 2% at t=5 s, the voltages of the modules begin to converge promptly toward the rated value. The simulation was repeated while gradually reducing the level adjustment. The results show that the system can bring the modules’ voltages back to their nominal value with adjustment values greater than 0.9%. This confirms the analysis presented previously. As the displacement reduces, the speed of convergence is also reduced. However, in practical applications, the system operates with a constant adjustment, so the speed of convergence is not a concern as the imbalances are not accumulated to require long balancing intervals [24].

106

4 Modulation and Scheduling Techniques

SMvoltage [kV]

1.3

1.25

1.2

1.15

1.1 1

2

VSM,max Lower Arm

VSM,max Upper Arm

VSM,min Lower Arm

VSM,min Upper Arm

3

4

5

6

7

8

9

10

time [sec] Fig. 4.12 Module voltages with balanced parameters and minimum level-adjustment (x = 0.002). © 2021 IEEE. Reprinted, with permission, from [24]

SMvoltage [kV]

1.6 1.4 1.2 1 0.8 1

2

VSM,max Lower Arm

VSM,max Upper Arm

VSM,min Lower Arm

VSM,min Upper Arm

3

4

5

6

7

8

9

10

time [sec] Fig. 4.13 Module voltages with mismatches between the modules’ capacitors and level-adjustment x = 0 → 0.02 at t = 5s. © 2021 IEEE. Reprinted, with permission, from [24]

The final scenario involved modifying the self-discharge rate of certain modules to emulate various levels of leakage and aging across the modules. Figure 4.14 depicts the voltage behavior of the modules in this scenario. Despite a significant mismatch between the modules, all voltages eventually reach the rated value by t = 7 s after increasing the x from 0% to 2%. The power-loss profile of a balanced system versus level adjustment is presented in Fig. 4.15. Based on the previous analysis, the required  value in an actual application is about 0.3%. The curve in Fig. 4.15 indicates that the additional power loss is approximately 0.01% [24]. To further confirm the developed analysis, a prototype system with scaled-down parameters is constructed. Table 4.2 provides the parameters of the testbench used. Design constraints (3.49)and(4.40) restrict the clamping inductor range between 3 µH and 10 µH. A single wire through a toroidal core leads to 7 µH inductance with insignificant resistance, which is within the limit defined by inequalities (3.49)

4.3 Scheduling

107 1.4

SMvoltage [kV]

1.3 1.2 1.1 1 0.9 1

2

VSM,max Lower Arm

VSM,max Upper Arm

VSM,min Lower Arm

VSM,min Upper Arm

3

4

5

6

7

8

9

time [sec] Fig. 4.14 Module voltages with different capacitance and self-discharge rates, and level-adjustment x = 0 → 0.02 at t = 7s. © 2021 IEEE. Reprinted, with permission, from [24]

Ploss [%]

The nominal displacements in normal conditions

Level Adjustment [-] Fig. 4.15 The profile of power loss for the LAPSC modulation versus x . © 2021 IEEE. Reprinted, with permission, from [24]

and (4.40) [24, 29]. The modules are composed of low ESR ceramics and electrolytes with a capacity of approximately 4.5 mF. The system is controlled by Labview and switching pulses are generated using an FPGA development board from National Instruments. By using PSC modulation, it is possible to generate a five-level output voltage with four modules in each arm. Figures 4.16 and 4.17 demonstrate the shape of the phase voltages and currents for a regular system, with a capacitance spread of ±15%). Furthermore, the measurements obtained from the testbench with severely imbalanced modules are illustrated in Fig. 4.18. Both figures are plotted with a vertical level-shift of x = 2%. The altered parameters of the modules are listed in Table 4.3.

108

4 Modulation and Scheduling Techniques

m = mx = ref 0.95 0.95 PF = 1 PF = 1

Normal Operation

Fig. 4.16 Measured waveforms of the phase current and phase voltage with the clamping circuit during standard operation, x = 2% and m x = 0.95. © 2021 IEEE. Reprinted, with permission, from [24]

mx = 0.75 PF = 1

Normal Operation

Fig. 4.17 Measured waveforms of the phase current and phase voltage with the clamping circuit during standard operation, x = 2% and m x = 0.75. © 2021 IEEE. Reprinted, with permission, from [24]

4.3 Scheduling

109

mx = 0.95 PF = 1

mx = 0.75 PF = 1

(a)

(b) Load change

mx = 0.95 PF = 0.93

Phase differenc e

(c)

mref = 0.95 PF = 1

mref = 0.95 PF = 0.93

(d)

Fig. 4.18 Measured phase voltage and current with LAPSC modulation and mismatched modules a m = 0.95, unity PF; b m = 0.75, unity PF; c m = 0.95, PF = 0.93; d m = 0.95, with PF and load variation. © 2021 IEEE. Reprinted, with permission, from [24]

There are no noticeable differences in the output and behavior of a system with identical modules and one with significantly mismatched ones, which confirms the capability of the proposed balancing technique in maintaining a balanced operation, and minimum output distortion. Throughout all the experiments, the difference between the capacitor voltages did not exceed 3% of the rated voltage. The THD of the output voltage is dependent on the number of modules and can be calculated easily [30]. In addition, Fig. 4.19a illustrates the balancing efficiency when using identical modules with varying initial voltages. After initiating the system with a voltage difference of x = 1.5%, the voltages reach their specified values. Balancing is accomplished in under 800 ms when the voltage distribution is 50%. Raising the adjustment led to a quicker convergence rate, with a minimum adjustment of 0.4% being necessary for stability. The diode current, on average, is generally lower than 5% of the load current [24]. Consequently, the efficiency alteration with x < 1%

110

4 Modulation and Scheduling Techniques

Fig. 4.19 Measured voltage profiles of the modules in both arms a initially imbalanced modules; b m = 0.75, unity PF. © 2021 IEEE. Reprinted, with permission, from [24]

mref = 1 PF = 0.99

(a)

mx = 0.95 PF = 0.99

(b)

was indistinguishable. Nevertheless, when the displacement was set to x = 5%, we observed a decrease in efficiency of 0.3%. The convergence is for severely imbalanced modules understandably slower, but it can be improved with higher levels-adjustment values. Figure 4.19 displays the arm module voltages of a system with mismatched modules, which shows that the system can reach a balanced operation with a level adjustment of 2%, and the maximum voltage difference is confined to < 1.5%. The system exhibits quicker convergence when higher x values are used, but this does not impact the maximum voltage difference. The maximum voltage difference solely depends on the switching frequency and the degree of imbalance among the modules. Furthermore, Fig. 4.20 illustrates the current and voltage of the clamping diode when the modules exhibit a substan-

V diode [V]

V modules [V]

4.3 Scheduling

111 50

VSM,L1 30 0 50

5

10

15

20

5

10

15

20

10

15

20

40 30 20 0 20

I diode [A]

VSM,L2

40

10 0 0

5

time [ms] Fig. 4.20 The voltage and current waveforms of the clamping branch as well as the modules during the charge equalization. © 2021 IEEE. Reprinted, with permission, from [24]

tial voltage difference. The figure shows that the diode current decays to nearly zero when the voltage difference is compensated. In standard operation, the voltage difference among the modules is consistently kept below 1.5%, and the average balancing current is below 1% [24].

4.3.4 Optimum Switching Loss for Topologies with Parallel Mode This section develops a simple yet effective scheduling algorithm for MMSs with parallel connectivity. The presented algorithm is most effective for topologies with parallel connectivity, which offers a simple and general way to select a suitable arrangement of modules in the arm for each voltage step. Thus, this algorithm is suitable not only for NLM techniques but also for any other switching schemes that directly control Ns , including selective harmonic elimination [31]. Nevertheless, the scheduling approach is evaluated using NLM since low-frequency switching techniques are the preferred choice for high-voltage applications. The proposed scheduling algorithm determines the appropriate connections to modify after receiving Ns . When designing the algorithm, the main priorities are to minimize switching and conduction losses, enhance voltage balance, and reduce balancing current. Additionally, it should be extendable to a greater number of modules to allow the algorithm to be used in larger systems. In order to make the developed algorithm useful for topologies with and without parallel connection, here, the inter-

112

4 Modulation and Scheduling Techniques

connection between two modules is controlled rather than the state of individual modules.

4.3.4.1

Integration with Low-Rate Switching Modulators: Halving-Doubling Scheduler

The scheduling algorithm aims to limit changes in the modules’ states (series, parallel, bypass) to only one per step in the reference voltage, making it simple and effective. This would additionally, minimize the switching instances. To increase the output voltage by one step, the algorithm splits the largest union in two by changing the most central parallel connection to a series connection. This would result in the two new unions having either an identical number of parallel modules (when initial N p = 2k) or one union having one extra module (when N p = 2k + 1). On the other hand, to reduce the output voltage by a step, it reverses the series connection between the two of the smallest adjacent unions to parallel. Thus, forming a larger union from the two smaller ones. The algorithm follows a specific procedure for each arm to arrive at these conclusions, as described in [13, 16]. For the starting point, Ns = 1 is taken into consideration. When multiple modules are connected in parallel, it forms a union that behaves as a larger module from both the load side and the grid point of view. For Ns = 1, there is only one large union that consists of N parallel modules in the arm. When the arm reference voltage increases to Ns = 2, the optimal module distribution for the next instance where two series connections are required is to divide the initial union in half, resulting in ( N2 , N ) modules in each union (referred to as even distribution here). Similarly, for an 2 equal distribution of parallel modules among the unions in the subsequent voltage step, the modules should be divided among three unions with N3 parallel modules in each arrangement. However, rearranging the arm in this manner necessitates toggling three connections, which would contradict the goal of minimizing switching loss by limiting the number of changes per step. This situation underscores the trade-off between conduction and switching loss. The number of switching actions needed for an even module distribution grows exponentially with the number of modules in the arm. [13, 16]. Consequently, for the distribution of N modules among Ns unions for the Ns th voltage step, unions with NNs paralleled modules should be formed. To achieve the lowest equivalent resistance and a more balanced distribution of modules, about (2Ns − 1) interconnections should change their states when transitioning from Ns to (Ns + 1) series connections. However, this approach results in significantly higher switching losses. A more balanced trade-off can be achieved by breaking the largest union in half, resulting in only one connection change per step from parallel to series. In addition, if two unions with the highest number of parallel modules have similar sizes, the order of changes is chronological, i.e., the union that was first formed should be given higher priority for balancing purposes [13, 16].

4.3 Scheduling Fig. 4.21 The intuitive representation of the scheduler for four modules with parallel connectivity [16]

113 NS = 0

NS = 1

Serial Connection

NS = 2

NS = 3

NS = 4

Parallel Connection

The scheduling algorithm can be adapted considering a similar logic for when the reference voltage is declining. To achieve the lowest equivalent resistance and an even distribution of modules, the series connection between two neighboring unions with the lowest number of modules should be changed to parallel. If there are similar numbers of parallel modules, the unions that were broken apart during the previous voltage step should be connected first to improve balancing. A graphical presentation of the scheduling operation for four modules according to this method is depicted in Fig. 4.21. The halving-doubling scheme offers a satisfactory balance between power losses, THD, and maintaining charge equilibrium among modules. By toggling only one interconnection at each step, the implementation is greatly simplified and the switching loss is minimized. It is worth noting that the algorithm is not restricted to lowfrequency modulation, although its operation has been presented in this context. The approach introduced by [32] combines Nearest Level Modulation (NLM) and Pulse Width Modulation (PWM) techniques by using series-connected modules to generate the desired voltage level and controlling the connection of the last unit through PWM. This method can be conveniently integrated with the presented algorithm by changing the last switching site between series and parallel based on the PWM carrier signal. The algorithm described here is usually implemented in capacitor-based modules for ultra-high-voltage applications, but the underlying principles can be applied to any energy storage topology and topology that is capable of parallel connectivity. In topologies without parallel connectivity, balancing requires additional consideration, and a bypass connection can be used instead of a parallel connection. One significant advantage of the presented approach is its compatibility with various modular reconfigurable structures and modulation techniques as demonstrated in previous studies [33]. Figure 4.22 illustrates the general process for NLM and how it can be adapted to other topologies and control methods [14, 16].

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4 Modulation and Scheduling Techniques

with NLM.pdf with NLM.pdf Higher level controllers

Step 1 can be replaced with any other controller method as long as NS,K+1 is given as input to step 2

1

NLM controller

Get modulation index m and Vdc

Calculate the arm reference voltages (4) Calculate number of serial Yes connections at instant k+1 using (5) or (6)

2

System Configuration Controller

New (NS,K+1) and old (NS,K) number of serial configurations

No

Smallest neighbor configurations

Connect in serial

Largest configuration

NS,K+1 NS,K

Is NS,K+1=NS,K No

Is NS,K+1>NS,K

Initiate interrupt Yes

Break into half

Store NS,K+1 as NS,K for next iteration

Update the available Modules in the arm

Module config updater

Determine Largest configuration Determine smallest neighbor configurations

End of interrupt

3

Fig. 4.22 The flowchart of the halving-doubling scheduler with optimal switching in combination with NLM and other modulation methods [16]

4.3 Scheduling

4.3.4.2

115

THD and Loss Discussion of the Optimal Switching Scheduler

The scheduling algorithm proposed in the study is beneficial for module topologies that have parallel connectivity. However, for a more detailed analysis, the singlephase topology illustrated in Fig. 4.23 is selected. It should be noted that a comparable analysis can be carried out for other topologies as well. Additionally, for comparison, we analyze a conventional HB module without any parallel capability alongside the parallel capable topology [13, 16]. The topology that has been selected for analysis consists of two arms with N modules each, where all but the last module in each arm possess four switches. Additionally, each module with parallel connectivity is linked through two small uncoupled inductors, in addition to the primary arm inductors described earlier. The figure in Fig. 4.23 shows that the four semiconductor switches of each module can enable four different states. These states allow each module to connect temporarily in parallel or series with each of its neighboring modules independently. However,

Fig. 4.23 Structure of a dual-arm single-phase dual-arm structure with unidirectional half-bridge modules. © 2021 IEEE. Reprinted, with permission, from [16]

serial to previous serial to next

CU,1 iU

CU,2

parallel to previous serial to next

Larm

Vdc/2

Cdc CU,N Load

iph CL,1 Vdc/2

serial to previous parallel to next

Cdc

Larm

CL,2

iL

CL,N

parallel to previous parallel to next

116

4 Modulation and Scheduling Techniques

modules without parallel connectivity can only make use of the typical HB topology, which is limited to series and bypass connections. Assuming steady-state conditions and ignoring the circulating or balancing currents, the conduction loss can be approximated using the equivalent resistance. In Chap. 3, the equivalent resistance of a union containing N p, j parallel modules connected and in series to the rest of the arm was derived. By determining the necessary number of parallel and series connections, the equivalent resistance of a configuration with Ns series connections can be computed [13, 16]. The arm equivalent resistance is 

Resistance of all unions





Resistance ofNp,j parallel modules

Req,arm

   Ns   (N p, j − 1) rc rint rint + (Ns − 1) + rsw , = r L,arm + + N 2 2 p, j j=1

(4.51)

where rint = rsw + r L is the resistance of the switches and interconnection inductors, r L,ar m is the arm inductor resistance, and rc is the capacitor resistances. Additionally, the final term in the equation represents the first module in each arm, which is connected to the dc-link through a half-bridge. During operation, only one switch in this HB bears the full arm current at a time. The switch resistances of each interconnection are represented by rint . Through mathematical manipulations, (3.29) results in Req,arm

 Ns   1 rint + (N − 1) + rsw . = r L,arm + rc N 2 p, j j=1

(4.52)

Although the modules with parallel connections generally have twice the number of semiconductors in comparison with the ones without a parallel mode, as the average operating current of each switch is reduced, lower-rating semiconductors can be employed. For example, in the unidirectional FB modules, each semiconductor operates at approximately half the arm current as opposed to HB modules which operate at the full arm current. To ensure a fair comparison, it is necessary to increase the current rating of HBswitches by a factor of two and reduce their resistance to half of that of the FB switches (rsw,HB = rFB /2), i.e., semiconductors with twice the current rating can be assumed to have smaller internal resistances. Using a comparable method, the arm equivalent resistance of a standard dual-arm circuit is Req,arm = Ns rc + Nrsw,HB + r L,arm = Ns rc + N

rsw + r L,arm , 2

(4.53)

4.3 Scheduling

117

where r L,arm is the resistance of the inductor. No additional inductors are required between the normal HB modules because they do not have a parallel state. Therefore, in (4.53), rint is replaced with rsw . By taking into account the balance between input and output power, it is possible to determine the instantaneous and RMS magnitudes of the arm current using i arm =

 Iph m cos(ϕ) ± sin (ωt − ϕ) , 2 2

rms Iarm

Iph = 2



m2 1 cos(ϕ)2 + , 4 2

(4.54)

(4.55)

where Iph is the amplitude of the phase current, and ϕ is the phase angle of the load. According to [28], the conduction loss per the average model can be obtained as follows rms rms 2 + Req,arm (Iarm ) , Pcond,arm = N Vsw Iarm

(4.56)

For simplicity, the voltage drops across the diodes and IGBTs are considered equal. Additionally, the voltage across the switches is modeled using rms , Vsw = Vconstant + ksw Iarm

(4.57)

in which Vconstant and ksw are obtained from the manufacturer datasheet. The switch’s internal resistance (rsw ) is assumed to be relatively unaffected by changes in current. The switch equivalent resistance remains the same; however, according to Eq. (4.56), the conduction loss related to the capacitor resistance is notably decreased, up to 45% of its original value. This has been demonstrated in [13, 16]. Additionally, as the capacitors work in parallel, the overall capacitance is enhanced while each capacitor’s effective current is lowered. As a result, smaller capacitors can be used. The presented scheduling method minimizes the number of switchings per voltage level, but it may not always lead to the lowest equivalent resistance. The optimization of switching loss is more appropriate for systems with a high switching-toconduction-loss ratio, such as those with high-voltage or -current IGBTs. On the other hand, optimizing conduction loss is more important in systems with a low switching-to-conduction-loss ratio, such as high-power but low-voltage applications with fast discrete MOSFETs, SiC- or GaN-based devices. In such cases, other methods like space vector, PSC, or the optimal conduction loss approach described in the following subsection are more advantageous [13, 34, 35]. Assuming a switching ratio of two, each module undergoes four state changes within a single cycle of the output, e.g., in 50 Hz system, there will be 200 toggling actions per second for each module. If we neglect the balancing currents and assume a unity power factor with identical voltages across all modules, we can use (4.58) to estimate the system’s switching loss. The process for calculating the switching loss is

118

4 Modulation and Scheduling Techniques

derived from [36] approach and provides an approximation of the total switching loss. Basically, during each switching action, as one switch turns off, another turns on. In addition, optimum snubber can increase the switching loss [13, 16]. The switching power loss in one arm can be approximated with

Psw

⎛ ⎞ Energy loss for turning the previous ⎜switch off, and the next switch on ⎟ Energy loss of snubber⎟ ⎜       ⎜ ⎟ 1 ⎜ ⎟ Vm i m (ton + toff ) = karm Nph Nsw ⎜ + αCsnub Vm2 ⎟ , ⎜ ⎟ 2 ⎜ ⎟ ⎝ ⎠

(4.58) where Nsw is the total switching actions per second, Csnub is the equivalent capacitance of the snubber and parasitic capacitance, and 0.1 < α < 0.9 is the snubber coefficient. Vm and i m are the module voltage and current, respectively. karm is the number of arms per phase, and Nph is the number of phases. The number of IGBTs or MOSFETs that change their states between parallel and series mode in each arm depends on the selected topology and the selected modulation, which can be calculated using

Nsw

⎧ N f sw , half-bridge [37], ⎪ ⎪ ⎪ ⎪ , semi-full-bridge [9], 1.5N f ⎨ sw full-bridge [40], = 2N f sw , ⎪ ⎪ Reduced-dual-full-bridge [29], ⎪ 3N f sw , ⎪ ⎩ dual-full-bridge [39], 4N f sw ,

(4.59)

where f sw is the switching frequency, and N is the number of arm’s modules. Equation (4.59) computes the accumulated number of switching actions in one fundamental period, e.g., 20 ms for 50 Hz system. For modulation schemes based on fundamental frequency such as NLM, SHM, and SHE, f sw = 2 f 1 . For each switching instance, i m value must be computed individually. Although using the rectified average arm current for loss calculation is more accurate, the arm current’s RMS can be considered a reasonable approximation [40]. The switching loss for the PSC method can be obtained by using a similar analogy. To calculate the number of switching actions for the PSC method, we can use the equation Nsw = 8 N f C where f C denotes the carrier frequency. The total switching loss associated with PSC modulation can be determined using the Eq. (4.58). By comparing the derived equations, we can calculate the switching loss ratio between PSC and NLM methods, which is given by ffC1 . The objective of balancing performance is to minimize the difference between the voltage of each module and its average value. To obtain the exact voltage variations resulting from parallel mode, numerical calculations or detailed simulations are necessary. However, when the switching rate is close to the output frequency, the dominant voltage ripple has a frequency of 2 f 1 and is similar for all modulation

4.3 Scheduling Table 4.5 Parameters of the simulated systems and the laboratory prototype Simulation I Simulation II Module number (per arm) 8 20 Rated power (per arm) 580 kVA 3.6 MVA DC link voltage 9.6 kV 24 kV Switch Model SEMiX854GB176HDs parameters Vce 1–2.5 V 1.9–2.5 V Rce 2.1–2.5 m 2.1–2.5 m ton + toff 1.7 µs 1.7 s Csnub 0 F 0 μF α 0 0 Module capacitor 6 mF 10 mF Capacitor resistance 2 m 2 m Decoupling inductors 50 µH 20 µH Decoupling inductor resistance 0.5 m 0.5 m Arm inductor 5 mH 12.5 mH Inductor resistance 20 m 50 m Implementation MATLAB

119

Experiments 4 – 1 kVA 100 V IPT015N10N5 – 1.5 m – – – 4 mF 20 m 20 mH 0.5 m 1.5 mH 40 m sbRIO9627

techniques [13, 16]. At higher frequencies, the PSC method offers better switchingallocation and charge equalization [10].

4.3.4.3

Simulation and Experimental Validation

To confirm the accuracy of the analysis, MATLAB/Simulink simulations are conducted on two high-voltage systems consisting of 16 and 40 modules. Additionally, a smaller prototype with four modules per arm verifies the concept experimentally. The relevant system parameters are listed in Table 4.5. The modulator operates without a feedback loop in both the simulated and lab prototype systems to illustrate the variation in output for identical input references. However, it is feasible to implement a closed-loop system. The objective of this section is to analyze the system’s behavior, which includes evaluating the charge equalization performance as well as investigating the modules and output current and voltage waveforms. The proposed algorithm is integrated with NLM, which can act as a benchmark for most low-frequency modulation techniques, and compared with PSC, which is another option that can deliver sensorless operation in parallel-connected modules. The effectiveness of PSC modulation is greatly influenced by the phase difference between the carriers. In an arm comprising N modules, there exist N carriers with a . However, the outcome is significantly impacted by the initial phase difference of 2π N

120

4 Modulation and Scheduling Techniques

phase of the carriers when the switching rate is close to the frequency of the phase voltage. To ensure an unbiased comparison, the optimal carrier distribution for PSC modulation, introduced in [12], is employed. This optimal distribution maximizes the efficiency and balancing performances of the system. Moreover, the system is simulated for each condition with three different phase shifts between the first carrier and the phase voltage, and the outcome with the minimum THD is provided. The most efficient carrier distribution for a system with eight modules per arm is

 2π + θinit , θopt = 0 3 6 1 4 7 2 5 × 8

(4.60)

π where θinit ∈ {0, 1, 2} × 12 are the considered phase differences to find the optimum initial carrier-phase. Figure 4.24 illustrates the output voltages obtained for CNLM, PSANLM, and PSC methods, highlighting the significant difference among them. As anticipated from the analysis in the preceding section, the PSANLM method generates a more sinusoidal output voltage. However, as depicted in Fig. 4.24, the output voltage has a marginally lower amplitude due to the higher voltage drop across the inductors and slightly diminished module voltages. The voltage drop effect reduces as more modules are integrated into the arm [15]. As anticipated from (4.17), the PSC method has the poorest voltage quality. The simulation outcomes for terminal voltages of the modules and high-frequency current components are presented in Figs. 4.25, 4.26, and 4.27. These results are

0

1.965

1.97

0

-5 1.96

1.975 5

1.98

2

1.98

1.985

PSC

CNLM

-5 1.96 5

CNLM PSANLM PSC

PSANLM

V out [kV]

5

0

-5 1.96

1.98

2

1.99 5

1.995

2

1.98

2

0

-5 1.96

time [sec] Fig. 4.24 Output voltages based on the optimum switching scheduler in combination with NLM techniques. © 2021 IEEE. Reprinted, with permission, from [16]

4.3 Scheduling

121

IHF [pu]

1 0 -1

1.5

0.36

1 VSM[pu]

Module Voltages [kV]

2

0.37

0.4

1 0.95 0.36

0.05

0.39

1.05

0.5 0

0.38

0.1

0.37

0.15

0.2

0.38

0.25

0.39

0.3

0.4

0.35

0.4

time [sec] Fig. 4.25 Dynamics of capacitor voltages and balancing currents using PSC modulation with an initial voltage imbalance of 0.8 pu. © 2021 IEEE. Reprinted, with permission, from [16]

IHF [pu]

0.5 0

-0.5 0.36

1.5

1

VSM[pu]

Module Voltages [kV]

2

0.5 0.05

0.38

0.39

0.4

0.37

0.38

0.39

0.4

1.05 1 0.95 0.36

0

0.37

0.1

0.15

0.2

time [sec]

0.25

0.3

0.35

0.4

Fig. 4.26 Dynamics of capacitor voltages and balancing currents using CNLM modulation with an initial voltage imbalance of 0.8 pu. © 2021 IEEE. Reprinted, with permission, from [16]

obtained for a system that starts with a 0.8 PU voltage imbalance (varying from 0.6 to 1.4 pu) that falls to zero as time passes. It is important to mention that the significant voltage swings observed at the beginning are due to the considerable voltage imbalance among the modules at startup. During normal operation, the imbalance is maintained within a tight boundary, and there are typically start-up plans in place to reduce inrush and voltage transients. However, these procedures are beyond the scope of this chapter [41].

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4 Modulation and Scheduling Techniques

IHF [pu]

1.5

0.5 0 -0.5 0.36

0.37

0.38

0.39

0.4

1 VSM[pu]

Module Voltages [kV]

2

0.5 0

0.05

1 0.95 0.9 0.36

0.1

0.37

0.15

0.2

time [sec]

0.38

0.25

0.39

0.3

0.4

0.35

0.4

Fig. 4.27 Dynamics of capacitor voltages and balancing currents using PSANLM modulation with an initial voltage imbalance of 0.8 pu. © 2021 IEEE. Reprinted, with permission, from [16]

Figure 4.28 shows the envelope of the capacitors’ voltages and the peak current under more realistic conditions with a 20% spread in capacitance, internal resistance, and initial voltage imbalance in the modules. Despite the 20% deviation in the system parameters, the voltage differences reach stability, and the systems operate normally. During steady-state operation, PSANLM has the least peak currents, which results in higher efficiency. The maximum current in PSC modulation is higher because the modules are not optimally scheduled at lower frequencies, leading to higher balancing surges. Figure 4.28 indicates that the maximum amplitudes of the transient voltage and current waveforms in an imbalanced system are within the satisfactory range. Furthermore, the parallel connectivity of the modules reduces the peak amplitude of the capacitor currents. It is worth noting that during regular operation, the transients of voltage or current are further mitigated. The laboratory setup used in the experiment is shown in Fig. 4.29. The switching and scheduling algorithms were implemented in LabView using an FPGA development board. The system consists of four modules in each arm, and each pair of modules is separated by a choke filter. Figure 4.30 displays the output phase voltage and the voltages of the four modules in the upper arm. The experimental results confirm the simulation findings, showing that the PSANLM achieves the most sinusoidal output waveform. Also, the parallel connectivity among modules balances the voltages during operation. However, the experimental setup had a lower number of modules per arm, which caused a higher voltage ripple compared to simulations. The PSANLM mode resulted in a significant increase in module voltage ripple compared to simulations due to the doubled stress on the arm inductor and increased voltage ripple of the modules with only four modules per arm. The algorithm primarily focuses on high-voltage applications with a high number of modules where the voltage ripple caused by the phase shift in the arms is insignificant. growing the number of modules per arm to 400 can decrease the high-frequency

4.3 Scheduling

123

ISM [pu]

1 0.8

VSM [pu]

0.1

0.3

1 0.8 0.2

0.3

0.8 0.1

0.2

0.3

0.1

0.4

0.2

0.3

0.4

PSANLM

2 1 0.1

3

ISM [pu]

1

1

0

0.4

1.2

CNLM

2

0 3

0.4

Vmax Vmin

1.2

0.1

VSM [pu]

0.2

ISM [pu]

VSM [pu]

3 1.2

0.2

0.3

0.4

PSC 2 1 0

0.1

time [sec]

0.2

0.3

0.4

time [sec]

Fig. 4.28 Voltage envelope and peak current amplitude for a system with 20% spread in the modules’ parameters. © 2021 IEEE. Reprinted, with permission, from [16] Fig. 4.29 Laboratory testbench for evaluating the halving-doubling scheduler. © 2021 IEEE. Reprinted, with permission, from [16]

Vout with PSC modulation Sub-modules

Lower Arm FPGA Controller

Upper Arm Arm Inductors

voltage ripple of inductors due to phase-shifted arms to below 0.25% of the dc-link voltage. Furthermore, during PSANLM, the decrease of module voltage compared to conventional NLM is below than 0.125% of one module’s rated voltage. For other N values, the voltage reduction follows V Vconventional

=

0.5 . N + 0.5

(4.61)

It is anticipated that the performance of PSC will be inadequate for switching frequencies below 4 f 1 , based on the analysis of voltage distortion [13, 16].

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4 Modulation and Scheduling Techniques

Fig. 4.30 Measured phase and module voltages with PSC, CNLM, and PSANLM methods. © 2021 IEEE. Reprinted, with permission, from [16]

5 V/Div

20 V/Div

100 ms/Div

4 ms/Div

(a)

20 V/Div

5 V/Div 100 ms/Div

4 ms/Div (b)

5 V/Div

20 V/Div 4 ms/Div

(c)

13

PSC,load=50 CNLM,load=50 PSANLM,load=50 PSC,load=10 CNLM,load=10 PSANLM,load=10 PSC,load=5 CNLM,load=5 PSANLM,load=5

11

THDN [%]

100 ms/Div

9 7 5 3 1 1 2

6

11

16

21

25

Switching Ratio Fig. 4.31 THDV for different loads and switching rates. © 2021 IEEE. Reprinted, with permission, from [16]

The resulting voltage THD in the simulations with various loads and switching frequencies are illustrated in Fig. 4.31. As anticipated, the PSC approach is not optimal for low-rate switching. Based on the results shown in Fig. 4.31, the PSC method requires a switching rate greater than four times and eleven times the fundamental frequency of the system to be equivalent to CNLM and PSANLM, respectively.

4.3 Scheduling

125 4

PSC,load=50 CNLM,load=50 PSANLM,load=50 PSC,load=10 CNLM,load=10 PSANLM,load=10 PSC,load=5 CNLM,load=5 PSANLM,load=5

3.5

Ploss [%]

3 2.5 2 1.5 1 1 2

6

11

16

21

25

Switching Ratio Fig. 4.32 Power losses for various switching schemes at varying operating points. © 2021 IEEE. Reprinted, with permission, from [16] 1

3.5 PSC CNLM PSANLM

2.5

20 30 40

2

50 60

1.5

70 80

1

Load Resistance [ ]

10 3

Ploss [%]

Fig. 4.33 THDv verses losses for various loads. © 2021 IEEE. Reprinted, with permission, from [16]

90 0.5

2

3

4

5

6

7

8

9

THDN [%]

Figure 4.32 illustrates a comparison of power losses for different switching frequencies. The efficiency of the NLM-based techniques is higher than the PSC method due to increased conduction and balancing losses in the latter at low switching frequencies, which is a result of suboptimal scheduling of the modules. In Fig. 4.32, it can be seen that CNLM and PSANLM exhibit similar losses for light loads, but the difference between them increases as the load increases. The primary reason for this difference is the lower balancing loss in PSANLM. To analyze the system performance during load variations, simulation results are presented in Fig. 4.33 for all three methods, ranging from light loads to overload conditions. The frequency at which the PSANLM and PSC methods exhibit comparable THDs is 11 f 1 . Thus, the selected switching frequency for PSC modulation in Fig. 4.33 is f sw = 11 f 1 . The results indicate that with increasing load, the distortion decreases. Nonetheless, during overload conditions, there is a significant rise in THD due to the high ripples in the module voltages. Moreover, in nearly all operating conditions, the proposed scheduler-based PSANLM method outperforms PSC.

126

4 Modulation and Scheduling Techniques

In the next step, we investigate the impact of the optimal scheduler when used with other modulation techniques. Moreover, as low switching-frequency modulation techniques are primarily utilized in high-voltage systems, a larger system consisting of 40 modules is used, and various modulation-scheduling combinations are applied. Table 4.5 displays the parameters of the simulated systems, while the implemented modulation techniques include: (a) CNLM; (b) PSANLM; (c) selective harmonic elimination (SHE) with N + 1 pulses; and (d) SHE with 2N + 1 pulses. The proposed scheduler, fixed-switching pattern, and even distribution schedulers were combined with every modulation technique. Also, optimized and conventional PSC modulations were added as alternative techniques for sensorless operation and balancing that also perform scheduling [13, 16]. The fixed-switching pattern scheduler arranges the modules in series based on a rotating vector A, where each index (ai ) corresponds to the priority in which its corresponding module is connected in series or bypassed (e.g., for A = [1, 2, . . . , N ], Module one is first, Module two is second, and Module N is last to be connected in series). The elements of vector A rotate clockwise after each cycle, i.e. new old new a1old → a2new ; a2old → a3new ; . . . ; a old N −1 → a N ; a N → a1 . For example, if A1 = [1, 2, . . . , N ] in the first cycle, for the second cycle A2 = [2, 3, . . . , N , 1]. Hence, Module 2 would be the first to connect in series to the arm. The even distribution technique is provided with more detail in Subsect. 4.3.5, which ensures optimum conduction losses [7]. Simulation results for low- and heavy-load conditions are presented in Tables 4.6 and 4.7. To compute the losses in the switches, the instantaneous values of modules’ voltage and current are considered in (4.58) during the simulations. Additionally, other switching behaviors were considered based on the SEMiX854GB176HDs datasheet, which is presented in Table 4.5. Comparing the THDs of the output voltages with and without the presented algorithm reveals almost no difference. Among the modulation techniques, PSANLM provides the best THD while PSC provides the worst, although the THD content for PSC modulation significantly improves as the switching frequency increases. The power losses in the CNLM and PSANLM with the presented scheduler are fairly comparable, and the slight disparity results from different balancing losses. According to the Eqs. (3.30) and (4.53), and the parameters given in Table 4.5, comparing the effective equivalent resistances of arms for conventional and parallel capable structures are found to be 45% better in case of the parallel connectivity. Additionally, the optimal-switching scheduler enhances the equivalent resistance by 40% compared to the fixed switching pattern, resulting in lower power losses. Moreover, optimum balancing throughout the arms in the presented scheduler also contributes to lower power loss by reducing the balancing loss. The presented algorithm is versatile and can be employed with various control methods that use the number of series-connected modules as the control variable. Both simulation and experimental results support the effectiveness of the algorithm in enhancing charge distribution among modules, increasing the efficiency, and reducing the THD. The findings demonstrate that PSC modulation requires at least ten times higher switching rates to achieve comparable voltage quality, and its power

4.3 Scheduling

127

Table 4.6 Comparison of various modulation schemes with various scheduling strategies for 250 load. © 2021 IEEE. Reprinted, with permission, from [16] Modulation THD Conduction Switching loss Total loss loss CNLM

PSANLM

SHE with N+1 levels

SHE with 2N+1 levels

Fixed pattern Even distribution Proposed Fixed pattern Even distribution Proposed Fixed pattern Even distribution Proposed Fixed pattern Even distribution Proposed

3.93 3.92

1.41 0.4

0.13 0.6

1.53 1

3.92 1.54 1.52

0.62 1.31 0.4

0.07 0.13 0.59

0.69 1.44 0.99

1.53 4.85 4.85

0.6 1.31 0.4

0.07 0.1 0.59

0.67 1.35 0.99

4.85 2.21 2.2

0.6 1.32 0.41

0.06 0.12 0.61

0.66 1.44 1.02

2.20

0.71

0.07

0.78

Table 4.7 Comparison of various modulation schemes with various scheduling strategies for 25  load. © 2021 IEEE. Reprinted, with permission, from [16] Modulation THD Conduction Switching loss Total loss loss CNLM

PSANLM

SHE with N+1 levels

SHE with 2N+1 levels

Fixed pattern Even distribution Proposed Fixed pattern Even distribution Proposed Fixed pattern Even distribution Proposed Fixed pattern Even distribution Proposed

2.82 2.26

4.89 1.06

0.13 0.7

5.02 1.76

2.27 2.03 1.43

1.50 4.51 1.01

0.08 0.13 0.69

1.57 4.63 1.7

1.43 2.77 2.32

1.45 4.33 1.07

0.07 0.11 0.69

1.52 4.44 1.76

2.32 2.20 1.55

1.48 4.38 1.08

0.06 0.11 0.69

1.54 4.49 1.77

1.56

1.60

0.07

1.67

128

4 Modulation and Scheduling Techniques

loss is twice that of the proposed algorithm with NLM. In summary, the algorithm is a simple yet effective approach to improve the performance of modular multilevel converters [13, 16]. • It is advisable to use PSC in systems with MOSFET modules and NLM with IGBT-based systems since MOSFETs have a lower switching-to-conduction-loss ratio, while large IGBTs have a relatively high switching-to-conduction-loss ratio. • When the dc-link voltage is constant and the number of modules is low, the use of PSC results in high THD content and a much higher switching frequency is needed to achieve comparable THDs. In contrast, in systems with a high number of modules, the THD is not a limiting factor, and methods that reduce switching loss are more critical. Thus, NLM is more appropriate for systems with both high and low numbers of modules. • In situations where the number of modules or inductor values are low, the performance of CNLM is superior to that of PSANLM.

4.3.5 Optimum Conduction Loss Scheduling The previous scheduling technique focused on reducing the switching loss first, and the conduction loss was the second priority. However, in low- to medium-voltage applications where faster semiconductors are used, and the number of modules per arm is manageable, the conduction loss can have a more significant share in the total power loss of the system. In such cases, it might be more beneficial to minimize the conduction losses as the first priority. Additionally, the importance of such methods is increasing as SiC- and GaN-based devices become popular in higher power applications, where the switching loss compared to the conduction loss is negligible. This subsection studies the general procedure of such a scheduling technique. This technique is more helpful for modules capable of parallel connectivity, as the modules without a parallel connection do not benefit from the reduced equivalent impedance by paralleling two modules. However, it is still applicable to a broad spectrum of topologies [13]. The conduction loss depends on the number of series, parallel, and bypassed modules and their arrangement within the arm. When assuming balanced storages and identical modules, the conduction loss depends on the arm equivalent impedance with a quadratic function. Therefore, minimizing the equivalent impedance of the system can lead to a reduction in conduction loss. To achieve this for a given number of series modules, all unions within the system should have a similar number of parallel modules and be distributed as uniformly as possible. This means that a more even distribution of parallel connections in each arm results in a lower equivalent resistance. [12, 13, 42]. The subsequent scheduler is designed to optimize conduction losses in the system, making it a good fit for systems with high conduction to switching loss ratios, where modules with higher internal resistance operate at high currents. The algorithm also

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129

restricts switching loss through low-frequency switching methods, such as NLM modulation. In addition, switching loss can be reduced by minimizing the number of modules that switch states. While the scheduler is effective for all system sizes, its benefits are more pronounced in smaller systems. Additionally, it enhances module balancing, providing advantages for both small and large systems [13]. The scheduler prioritizes minimizing switching loss, but if switching is unavoidable, it aims to reduce module imbalance by reversing their mapping order. For instance, if the scheduler previously formed unions with N p1 and N p2 parallel modules starting from the top of the arm, it will start from the bottom of the arm in the next cycle [13]. Increasing the number of states in a system leads to a higher DoFs. However, achieving global optimization in real-time requires solving complex and timeconsuming optimization problems at each time step. In order to address this challenge, the proposed method takes advantage of the intricate interactions that govern MMSs with parallel connectivity to optimize the system’s most critical aspect, i.e., minimizing power loss, while also considering other relevant parameters. Given that conduction loss typically constitutes a larger proportion of power loss in high-power applications, prioritizing the minimization of conduction loss over switching loss is a logical approach. To minimize conduction loss in each arm, it is essential to distribute the formed unions, achieved by paralleling the modules, as uniformly as possible [13]. For a given value of Ns , the number of paralleled modules (N p j , j = 1, ..., Ns ) in all unions of each arm should be approximately equal. The calculation of N p j requires considering the value of h = N /Ns , where N is the total number of modules in the arm. Depending on the value of h, two different scenarios are possible: • h ∈ N. It is possible to equally divide N into Ns unions each having h modules in parallel, i.e., all N p j are equal to N p1 = N p2 = ... = N p(Ns ) = N /Ns .

(4.62)

• h∈ / N. The remainder of N /Ns equals R = 0. In this case, R unions contain h + 1 modules, and (Ns − R) unions will contain h modules, to distribute the paralleled modules as evenly as possible. To achieve better balancing, similar unions should not be connected in series with each other. As a result, the numbers of parallel modules in the two types of unions are: N p1 = ... = Np R = h + 1, Np(R+1) = ... = Np(Ns ) = h ,

(4.63)

where f (x) = x yields the largest integer less than or equal to x as output. A similar routine can be followed for both positive and negative arm currents as well as the increase and decrease of Ns .

130

4.3.5.1

4 Modulation and Scheduling Techniques

Equivalent Resistance and Conduction Loss

Assuming no voltage imbalance and transients, the conduction loss of a system depends on the equivalent resistance (Req,arm ) and the arms currents. The equivalent resistance of a union comprising N p, j parallel modules is determined using (4.64). Req,union (N p, j ) =

Np j − 1 rC (rL + rsw ), + N p, j 2

(4.64)

The equivalent resistance of the arm (Req,arm ) can be determined using Eq. (3.29), given the values of Ns and N p j . The average equivalent resistance of the arm changes constantly with each voltage step as the value of Ns varies. To simplify the analysis, the average equivalent resistance of the arm in one cycle can be used. The number of required series connections is determined at each instant based on the modulation strategy, which can be arbitrary [13]. However, for most modulation strategies and regardless of the type of output (ac or dc), the number of series connected modules (Ns, j ) in each arm fluctuates between a boundary defined by 0 ≤ Ns,min ≤ Ns, j ≤ Ns,max ≤ N .

(4.65)

For example, based on the NLM and PSC techniques, the min and max numbers of series connections, corresponding to the modulation index m, inserted in the arm will be ⎧ N −  (1−m2 x )N , ac, dual-arm, PSC ⎪ ⎪ ⎪ ⎪ 0, ac, single-arm, PSC ⎪ ⎪ ⎪ ⎨ m x N ,  dc, single-arm, PSC Ns,min = (4.66) (1−m x )N N − round , ac, dual-arm, NLM ⎪ ⎪ 2 ⎪ ⎪ ⎪ 0, ac, single-arm, NLM ⎪ ⎪ ⎩ dc, single-arm, NLM round (m x N ) ,

Ns,max =

⎧ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ ⎨

 (1−m2 x )N , m x N , m x N + 1, 

ac, dual-arm, PSC ac, single-arm, PSC dc, single-arm, PSC

round (1−m2 x )N , ac, dual-arm, NLM ⎪ ⎪ ⎪ ⎪ ⎪ round (m x N ) , ac, single-arm, NLM ⎪ ⎪ ⎩ round (m x N ) , dc, single-arm, NLM

(4.67)

where m x is the amplitude of the modulation index. For the cases, where the value of Ns,min = Ns,max , the average arm resistance in one cycle is equal to the value of Req,arm (Ns ), but for other cases, the average arm resistance can be approximated with

4.3 Scheduling

131



Nmax−1

Ravg,arm =

 Req-arm (Ns ) + 0.5 Req-arm (Nmin ) + Req-arm (Nmax )

Ns =Nmin+1

(Nend − Nstart )

.

(4.68)

The reason for multiplying the Req-arm (Nmax ) and Req-arm (Nmin ) with a 0.5 coefficient is that the duration of these two voltage steps is roughly half the other steps. Additionally, as the duration of voltage steps for the ac systems is not entirely linear, the derived equation for the average arm resistance is an approximation. In the case of PSC modulation, it has been assumed that the series connections are distributed optimally. Having the average equivalent resistance of the arm, the average conduction loss follows (4.56), which shows that the conduction loss caused by the switch resistances is almost unaffected, but the loss because of the resistive elements of the storages is reduced significantly.

4.3.5.2

Switching Loss

If the modules are balanced, the switching loss can be estimated using the method suggested in [36]. To calculate the switching loss of the system, the compounded number of switching actions within one period of the phase voltage in each arm needs to be approximated. The number of switching actions depends on the modulation strategy and the application. For example, according to the NLM, approximately 2k − 1 interconnections change states when the number of series modules changes from Ns = k − 1 to Ns = k [5, 13]. Hence, in ac applications, the compounded number of switching actions in each arm with the fundamental frequency f 1 , modulation index amplitude m x , and modulation method NLM can be approximated as

Nsw

⎧ 2N f 1 , half-bridge [37], ⎪ ⎪ ⎪ ⎪ Nmax semi-full-bridge [9], ⎨ 3N f 1 ,  4N f 1 , full-bridge [12, 40], ≈ (2k − 1) × ⎪ ⎪ , Reduced-dual-full-bridge [29], 6N f k=Nmin +1 ⎪ 1 ⎪ ⎩ dual-full-bridge [39], 8N f 1 ,

(4.69)

Furthermore, the scheduling algorithm does not benefit significantly with a conventional HB topology, except for improved balancing. Hence we have not considered, and we have just included the number of switchings of a HB modules for comparison purposes. The system switching loss for a multi-phase system follows  Psw, total = karm Nph Nsw

 1 Vm i m (ton + toff ) , 2

(4.70)

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4 Modulation and Scheduling Techniques

where Nph is the total number of phases in the system, Vm is module voltage, and i m is module current. karm depends on the structure of the modular storage and equals the number of arms. Vm and i m should be computed numerically at each switching step. An average model can significantly simplify the loss computations. The average of the absolute arm current for half of the fundamental cycle follows Iph im = 2N

 N  k=1

abs

m 2

cos(ϕ) ± sin

π 2

kω − ϕ

 

.

(4.71)

The average of the absolute amplitude of the current is also a good first approximation for the average switching current. In (4.70), the snubber operation is not considered. In case of a snubber for each module, (4.58) should be used.

4.3.5.3

Simulation and Experimental Validation

In this section, the performance of the proposed system is assessed and compared to other commonly used techniques. MATLAB/Simulink simulates a model of the system comprising 40 modules, and a scaled-down system with only eight modules is used to validate the concept experimentally. The optimal-conduction scheduler combined with PSANLM is evaluated against PSC modulation, which automatically schedules the modules according to the carrier arrangements, in both the simulations and experiments. In addition, this section compares the proposed scheduler’s performance to that of a traditional cell-sorting scheduler that heavily depends on module voltage measurements [43], as well as a fixed-switching-pattern scheduler [44, 45]. While the results are provided for a capacitor-based modular multilevel system, the general concept is similar for all modular reconfigurable storages or converters [13]. The employed balancing strategy based on sorting the modules’ voltages is according to the literature [32]. For MMS with parallel connectivity, parallel connections replace the bypass ones. The fixed-switching-pattern scheduler arranges the modules in the arm according to their index without any specific scheduling. The efficiency and voltage THD output of the PSC heavily depend on the frequency of the carriers. Higher carrier frequencies result in greater switching loss and lower voltage THD. To make a fair comparison, the minimum carrier frequency should be chosen to achieve an acceptable THD. In the following section, the THD output of the PSC is briefly analyzed [13]. Comparing Eq. (4.17) with the total harmonic distortion (THD) of the Phase-Shifted Arms Nearest Level Modulation reveals that to achieve a comparable THD, the switching rate in PSC modulation needs to be at least four times higher than the fundamental frequency. In systems with many modules, obtaining similar THD values with PSC modulation requires a much higher switching rate, leading to elevated switching losses. However, in systems with a lower number of modules where higher switching frequencies are possible, such as those with lower power ratings, PSC modulation can achieve THD values that are not possible for NLM. For the experiments, a carrier frequency of 11 f 1 is chosen, while a frequency of 4 f 1

4.3 Scheduling

133

is used for the simulations. The precise parameters of the system are provided in Table 4.8. For N modules in the arm, PSC modulation utilizes N carriers which are phaseshifted with respect to each other with 2π/N phase difference. The effectiveness of this technique largely relies on the starting phase difference between the voltage reference and the carriers. To ensure fairness, the study utilizes the optimal carrier distribution proposed in [12], which enhances the system’s balancing performance and efficiency. The carrier distribution that maximizes performance for a system with twenty modules per arm is ϕopt = [10 19 8 17 6 15 4 13 2 11 0 9 + 2π/3. 18 7 16 5 14 3 12 1] × 2π 20

(4.72)

The results for the output voltages of the five modulation methods are presented in Fig. 4.34a. The PSANLM method generates a more sinusoidal output voltage. Figure 4.34b displays the THD of the output voltages, which confirms the effectiveness of the method in combination with the optimal-switching scheduler. The THD of the NLM-based techniques is relatively similar, and the PSANLM with the presented scheduler has the best THD, while the fixed-pattern scheduling has the worst. This is mainly because the scheduler impacts the balancing and improves the quality of the voltage steps [13]. The balancing performance of different methods is analyzed in Fig. 4.35 by comparing the voltage difference between maximum and minimum values of the modules’ voltages. The results in Fig. 4.35 show that the optimal-conduction method has

Table 4.8 Parameters of the simulation system as well as the lab prototype © 2022 IEEE. Reprinted, with permission, from [13] Parameters Simulations Experiments Rated Power (per arm) DC-link voltage Number of modules per arm Modules capacitance Capacitor resistance Decoupling inductor Decoupling inductor’s resistance Arm inductor Arm inductor’s resistance Switch model RCE VCE Implementation/Controller

36 kVA 1200 V V 20 20 mF 20 m 5 µH 100 µ

1.25 kVA 200 V 4 5 mF 20 m 7 µH 150 µ

0.9 mH 2 m IGBT 1.5 m 1.5 V MATLAB

1.5 mH 20 m IPT015N10N5 1.5 m 1.5 V sbRIO9627

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4 Modulation and Scheduling Techniques 1

(a)

V [pu]

0.5 0 -0.5

THD V [%]

(b)

-1 1.96 6

1.965

5

1.97

1.975

1.98

1.985

MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC

4

1.99

1.995

2

MMSPC-Sorting MMSPC-Proposed

3 2 1.96

1.965

1.97

1.975

1.98

1.985

1.99

1.995

2

time [sec] Fig. 4.34 Output voltages as well as their corresponding THD values: a Waveforms of the output voltage for various modulation schemes, b THD waveforms using a moving window. © 2022 IEEE. Reprinted, with permission, from [13]

the best performance in balancing the voltages of the capacitors, while the fixedswitching-pattern scheduler performs the worst. This is mainly because the optimal conduction scheduler leads to a lower accumulation of voltage imbalance over time. Additionally, the developed scheduler outperforms the conventional cell sorting scheduler in balancing the capacitors’ voltages. Figure 4.35 illustrates that the proposed method has a lower average capacitor current compared to the other methods. Consequently, the optimum conduction scheduler has higher efficiency and can use smaller capacitors. The modules’ currents are impacted by the phase current (i ph ↑ ⇒ i sm ↑), modulation index (m ↑ ⇒ i sm ↑), power factor (P F ↑ ⇒ i sm ↑), and balancing operation (i balancing ↓ ⇒ i sm ↓). The four factors that affect the balancing requirement and average capacitor current cannot be controlled entirely by scheduling, but using an appropriate scheduler can assist in decreasing the required charge-equalization efforts and thus reduce the average current capacitors. As capacitors are one of the most expensive and largest components in the system, any reduction in their size can lead to significant benefits and should be further explored. References [13, 46] investigate the possibility of capacitor reduction through parallel connectivity in more detail.

4.3 Scheduling

135

(a)

V diff, caps [pu]

0.6

0.4

0.2

I avg, caps [pu]

0 1.96 0.35 (b)

1.965

1.97

1.975

1.98

1.985

MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC

0.3

1.99

1.995

2

MMSPC-Sorting MMSPC-Proposed

0.25

0.2 1.96

1.965

1.97

1.975

1.98

1.985

1.99

1.995

2

time [sec] Fig. 4.35 Modules’ voltages and currents: a Maximum voltage imbalance among modules for each scheme; b Mean absolute value if the capacitor currents averaged over a moving window. © 2022 IEEE. Reprinted, with permission, from [13] 14

MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC MMSPC-Sorting MMSPC-Proposed

12

Loss [%]

10 8 6 4 2 0 0.5

0.6

0.7

0.8

Modulation Index

0.9

1

Fig. 4.36 Comparison of power loss for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13]

Figure 4.36 depicts a comparison of power losses for different modulation indices assuming that the capacitors have the same voltage and the modulation index ranges from 0.5 to 1. Higher modulation index amplitudes decrease power loss in all methods except for the fixed-switching-pattern scheduler. For modulation indices below 0.8, the power losses for the fixed-switching-pattern scheduler are high, indicating the

136

4 Modulation and Scheduling Techniques

Pconduction [%]

20 MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC MMSPC-Sorting MMSPC-Proposed

15

10

5

0 0.5

0.6

0.7

0.8

0.9

1

Modulation Index Fig. 4.37 Comparison of conduction losses for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13]

significance of minimizing conduction loss. Conduction and switching losses are respectively compared in Figs. 4.37 and 4.38. The power loss of the presented scheduler is lower than other methods, including PSC. Although it leads to slightly higher switching losses, the switching losses of PSANLM are negligible compared to conduction losses, as shown in Figs. 4.37 and 4.38. An inductive load with PF  0.87 serves to evaluate all the scheduling methods, and Fig. 4.40 illustrates the power losses as a function of the modulation index. The developed scheduler outperforms the conventional methods by reducing the average 0.06 MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC MMSPC-Sorting MMSPC-Proposed

Pswitching [%]

0.05 0.04 0.03 0.02 0.01 0 0.5

0.6

0.7

0.8

0.9

1

Modulation Index Fig. 4.38 Comparison of switching losses for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13]

4.3 Scheduling

137 14 12

Loss [%]

10

MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC

MMSPC-Sorting MMSPC-Proposed

8 6 4 2 0 0.5

0.6

0.7

0.8

0.9

1

Modulation Index Fig. 4.39 Comparison of power loss for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are imbalanced, and unity PF. © 2022 IEEE. Reprinted, with permission, from [13] 14

MMC-Sorting MMSPC-Fixed Pattern MMSPC-PSC MMSPC-Sorting MMSPC-Proposed

12

Loss [%]

10 8 6 4 2 0 0.5

0.6

0.7

0.8

0.9

1

Modulation Index Fig. 4.40 Comparison of power loss for various schemes with modulation index amplitude ranging from 0.5 and 1 when modules are balanced, and inductive PF ≈ 0.87. © 2022 IEEE. Reprinted, with permission, from [13]

losses by over 20%. The power losses for mismatched capacitors in the modules are also studied. As Fig. 4.39 shows, the results are similar. The modulation and scheduling algorithms are executed on an FPGA development board. Each arm consists of four modules, with a small inductor placed between every two modules. The main parameters are provided in Table 4.8. The output voltage frequency is set 50 Hz, and the load of the system is a 5  resistor. The dc-link voltage is 200 V, and the modulation index is set to 95%. Figure 4.41 shows the experimental results obtained with PSANLM using the proposed scheduler under a resistive load. Specifically, Fig. 4.41a provides evidence of the balancing capability of the parallel-capable MMS system, while Fig. 4.41b

138

4 Modulation and Scheduling Techniques

Fig. 4.41 Experimental measurements according to the presented scheduler with unity PF, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13]

presents the performance of PSANLM. The impact of the scheduler on the output voltage waveform is typically minor, and the use of any of the scheduler methods with PSANLM would yield similar output shapes. However, there are notable differences in efficiency among the various scheduling methods. The experimental setup has a lower number of modules compared to the simulation, which results in higher THD of the output voltage and a larger ripple in module voltages. This is expected because a lower number of modules increases the stress on the inductor and leads to a higher voltage ripple.

4.3 Scheduling

139

Fig. 4.42 Experimental measurements using PSC modulation with unity PF, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13]

Figure 4.43 shows the behavior of the scheduling method under a highly inductive load. As PF decreases, the drawn active energy from the capacitors reduces and the capacitors have a more stable voltage. Thus, the voltage steps in the output voltage of the system become more distinct and more identical. In contrast, the experimental results of the PSC method for PF = 1 and PF  0.87 are shown in Figs. 4.42 and 4.44, respectively. As expected, the output voltages from PSANLM in combination with the optimal-conduction scheduler are more sinusoidal in both cases.

140

4 Modulation and Scheduling Techniques

Fig. 4.43 Experimental measurements using the presented scheduler for inductive loads with PF ≈ 0.87, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13]

Fig. 4.44 Experimental measurements using PSC modulation for inductive loads with PF ≈ 0.87, a waveforms of the modules’ voltages, b waveforms of the phase voltage and current. © 2022 IEEE. Reprinted, with permission, from [13]

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141

Fig. 4.45 Spectrum of the harmonics in the resulted voltage according to the PSC modulation and presented scheduler with NLM modulation, a ForPSC modulation, b For the presented scheduler. © 2022 IEEE. Reprinted, with permission, from [13]

Figure 4.45 presents the THDs of the output voltages obtained from the measurements. As anticipated, the THD of the PSANLM method is significantly better than that of the PSC method. The major harmonic contents of the PSC modulation are at higher frequencies, which reduces the size of filters. However, it should be noted that the NLM is more suited to applications with a many modules. Similar to the simulation results, the THD value of the PSANLM method can be significantly lower [13].

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26. Tashakor, N., Keshavarzi, D., Banana, S., & Goetz, S. (2022). Voltage estimation for diodeclamped MMCs based on a simplified neural network. In 2022 24th European Conference on Power Electronics and Applications (EPE’22 ECCE Europe) (pp. 1–10). 27. Tashakor, N., Keshavarzi, D., Iraji, F., Banana, S., & Goetz, S. (2022). Voltage estimation in combination with level-adjusted phase-shifted-carrier modulation (LA-PSC) for sensorless balancing of diode-clamped modular multilevel converters (MMCs). IEEE Transactions on Power Electronics, 1–11. 28. Zygmanowski, M., Grzesik, B., Fulczyk, M., & Nalepa, R. (2013). Analytical and numerical power loss analysis in modular multilevel converter. In IECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society (pp. 465–470). 29. Li, Z., Motwani, J. K., Zeng, Z., Lukic, S. M., Peterchev, A. V., & Goetz, S. M. (2021). A reduced series/parallel module for cascade multilevel static compensators supporting sensorless balancing. IEEE Transactions on Industrial Electronics, 68, 15–24. 30. Rohner, S., Bernet, S., Hiller, M., & Sommer, R. (2010). Modulation, losses, and semiconductor requirements of modular multilevel converters. IEEE Transactions on Industrial Electronics, 57, 2633–2642. 31. Kavousi, A., Vahidi, B., Salehi, R., Bakhshizadeh, M. K., Farokhnia, N., & Fathi, S. H. (2012). Application of the bee algorithm for selective harmonic elimination strategy in multilevel inverters. IEEE Transactions on Power Electronics, 27, 1689–1696. 32. Wang, Y., Hu, C., Ding, R., Xu, L., Fu, C., & Yang, E. (2018). A nearest level PWM method for the MMC in DC distribution grids. IEEE Transactions on Power Electronics, 33, 9209–9218. 33. Dekka, A., Wu, B., & Zargari, N. R. (2016). A novel modulation scheme and voltage balancing algorithm for modular multilevel converter. IEEE Transactions on Industry Applications, 52, 432–443. 34. Deng, Y., Wang, Y., Teo, K. H., & Harley, R. G. (2016). A simplified space vector modulation scheme for multilevel converters. IEEE Transactions on Power Electronics, 31, 1873–1886. 35. Zhou, D., Yang, S., & Tang, Y. (2019). Model-predictive current control of modular multilevel converters with phase-shifted pulsewidth modulation. IEEE Transactions on Industrial Electronics, 66, 4368–4378. 36. Quraan, M., Tricoli, P., D’Arco, S., & Piegari, L. (2017). Efficiency assessment of modular multilevel converters for battery electric Vehicles. IEEE Transactions on Power Electronics, 32, 2041–2051. 37. Yao, W., Hu, H., & Lu, Z. (2008). Comparisons of space-vector modulation and carrier-based modulation of multilevel inverter. IEEE Transactions on Power Electronics, 23, 45–51. 38. Ilves, K., Bessegato, L., Harnefors, L., Norrga, S., & Nee, H.-P. (2015). Semi-full-bridge submodule for modular multilevel converters. In 2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia) (pp. 1067–1074). 39. Goetz, S. M., Li, Z., Liang, X., Zhang, C., Lukic, S. M., & Peterchev, A. V. (2017). Control of modular multilevel converter with parallel connectivity application to battery systems. IEEE Transactions on Power Electronics, 32, 8381–8392. 40. Hu, J., Xiang, M., Lin, L., Lu, M., Zhu, J., & He, Z. (2018). Improved design and control of FBSM MMC with boosted AC voltage and reduced DC capacitance. IEEE Transactions on Industrial Electronics, 65, 1919–1930. 41. Wang, Z., Zhang, Y., Wang, H., & Blaabjerg, F. (2020). Capacitor condition monitoring based on the DC-side start-up of modular multilevel converters. IEEE Transactions on Power Electronics, 35, 5589–5593. 42. Tashakor, N., Arabsalmanabadi, B., Cervera, L. O., Hosseini, E., Al-Haddad, K., & Goetz, S. (2020). A simplified analysis of equivalent resistance in modular multilevel converters with parallel functionality. In IECON 2020 The 46th Annual Conference of the IEEE Industrial Electronics Society (pp. 4158–4163). 43. Lesnicar, A., & Marquardt, R. (2003). An innovative modular multilevel converter topology suitable for a wide power range. In 2003 IEEE Bologna Power Tech Conference Proceedings,, vol. 3 (pp. 6 pp. Vol.3–).

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44. Goetz, S. M., Wang, C., Li, Z., Murphy, D. L., & Peterchev, A. V. (2019). Concept of a distributed photovoltaic multilevel inverter with cascaded double H-bridge topology. International Journal of Electrical Power & Energy Systems, 110, 667–678. 45. Wang, C., Peterchev, A. V., & Goetz, S. M. (2019). Online switch open-circuit fault diagnosis using reconfigurable scheduler for modular multilevel converter with parallel connectivity. In 2019 21st European Conference on Power Electronics and Applications (EPE ’19 ECCE Europe) (pp. P.1–P.10). 46. Fang, J., Yang, S., Wang, H., Tashakor, N., & Goetz, S. M. (2021). Reduction of MMC capacitances through parallelization of symmetrical half-bridge submodules. IEEE Transactions on Power Electronics, 36, 8907–8918.

Chapter 5

Novel Topologies and/or Techniques for Emerging Applications

This book chapter discusses the potential of modular reconfigurable power electronics in the field of electromobility. While these systems have already gained dominance in ultra-high-voltage applications, they are now expanding into other areas such as stationary storage systems and electromobility. The main focus of the chapter is on simplifying the circuit design in complex systems where multiple outputs are required with minimal added costs or control complexity. The chapter introduces the concepts of symmetric and asymmetric modulation strategies and expands on the modulation strategy ideas. Additionally, a generic control strategy is developed for systems with high degrees of freedom. This control strategy enables the generation of multiple fully or semi-controlled outputs and can be readily integrated into higher-level control strategies. The chapter covers both ac and dc applications of modular reconfigurable systems in electromobility, with a specific focus on increasing module utilization, developing novel control strategies, and simplifying circuits. It provides a valuable resource for researchers, engineers, and professionals who are interested in the innovative applications of modular reconfigurable power electronics in electromobility. The chapter concludes by highlighting the potential for modular reconfigurable power electronics to revolutionize the way power electronics are used in the electromobility industry, making it more efficient and cost-effective. Collaboration with Mr. Jan Kacetl, Mr. Tomas Kacetl, Dr. Zhongxi Li, and Dr. Jingyang Fang has contributed to developing implementation techniques for the new topologies and multiple patents. Multiple bachelor and master students have also collaborated in developing this chapter while serving as their advisor [1–5]. Publications from these collaborations are cited to acknowledge their support and help throughout the chapter.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1_5

145

146

5 Novel Topologies and/or Techniques for Emerging Applications

5.1 Modular Reconfigurable Systems in Electromobility Despite the acceleration of EV market penetration due to recent technological advancements and environmental motivations, numerous conventional obstacles persist. In the last few years, the convergence of technological innovation and the demand for increased driving ranges have led to nearly a threefold increase in the capacity of battery packs employed in contemporary EVs [6]. Today, an EV is powered by an arrangement of series–parallel connections consisting of literally hundreds of cells. There is a growing trend towards higher voltage levels in batteries, which is resulting in increased use of series connections to achieve the same energy capacity. Reference [7] debates the advantages of a higher voltage battery pack (i.e., 800 V), including lower weight, better efficiency, and faster charge [7]. However, there are also several challenges associated with using a high-voltage battery pack with numerous series connections. These challenges include more complicated monitoring, increased balancing loss, the requirement for multiple voltage levels to support legacy systems, and safety concerns. A notable concern in these systems is the reduced efficiency of inverters when functioning at partial load. Additionally, extended strings heighten the likelihood of incorporating cells exhibiting subpar performance within the pack, resulting from manufacturing variances, which ultimately constrains the overall pack [8–10]. Figure 5.1 depicts the circuit diagram of a traditional EV with hardwired batteries. The high-power drive system comprises high-voltage batteries that supply both the traction inverter(s) and a second low-power isolated output for supplying the critical loads (e.g., dashboard components, lights and control units, and other auxiliary units). It is even conceivable that the heating, ventilation, and air conditioning units are also supplied from the auxiliary output, although they usually have separate converters. Often, galvanic isolation is usually realized through an isolated single-active bridge, dual-active bridge, or fly-back converters. As the inverter is directly connected to the batteries, the dc-link voltage or the pack’s output voltage can vary within a wide range depending on its state of charge, and all the control is achieved through the modulation of the inverter [11]. Several studies have demonstrated the feasibility of actively regulating the dc-link voltage to shift the operating point of inverters toward optima [13–16]. Hence, in most recent applications, often a dc/dc converter stabilizes the dc-link of the drive inverter(s) to reduce dependence on SoC [11, 17]. Figure 5.2 illustrates the overall electrical circuit of such a system. Although actively regulating the dc-link voltage can enhance the efficiency of the system, issues related to balancing battery cells and fault tolerance still remain [18, 19]. Recent progress in modular systems and the enhanced performance of low-voltage transistors have facilitated the growth of MMS and, more broadly, adaptable power electronics in electromobility applications [20–24]. These systems divide the formerly fixed battery pack into smaller units, typically under 100 V or 60 V (safety

5.1 Modular Reconfigurable Systems in Electromobility Fig. 5.1 Conventional electrical circuit of an EV where the hardwired batteries directly supply the inverter (modified based on [12])

147

Hard-wired Battery

Active FB HFT

Active FB

=/~

3-ph Inverter

Auxiliaries 12 V/48 V

extra-low voltage, SELV1 ). Simplified variations of such concepts are being developed in the automotive industry [26–32]. 1

Safety Extra-Low Voltage (SELV) is a term used to describe electrical systems where the voltage is deliberately kept at a low level to minimize the risk of electric shock in the event of a fault. SELV systems are designed to ensure that under normal and single-fault conditions, the voltage between any two accessible parts or between any accessible part and the earth does not exceed a safe level. This safe voltage level is typically below 50 V AC or 120 V DC when measured under normal operating conditions [25]. SELV systems are commonly employed in applications where the possibility of electrical shock could pose significant safety hazards, such as in bathrooms, swimming pool areas, and outdoor lighting installations. The use of SELV systems in electromobility applications, as

148 Fig. 5.2 Conventional electrical circuit of an EV with a hardwired storage and regulated dc-link (modified based on [12])

5 Novel Topologies and/or Techniques for Emerging Applications

Hard-wired Battery

=/=

Active Buck/Boost FB Converter HFT

Active FB

=/~

3-ph Inverter

Auxiliaries 12 V/48 V

In such applications, a reconfigurable storage system can offer balancing functionality [18, 19, 33], enhanced fault tolerance [34–36], quicker output regulation [37–39], and increased effective switching frequency, leading to volume reduction [20]. Moreover, innovative topologies such as unidirectional FB or dual-FB configurations can boost overall efficiency [40, 41], self-balance [42, 43], and operate at all four quadrants [44]. For a more detailed study of each feature, please see Chaps. 3 and 4. mentioned in the previous text, ensures that the voltage of the battery subunits remains at a safe level to reduce the risks associated with electric shocks.

5.1 Modular Reconfigurable Systems in Electromobility

149

5.1.1 Dynamically Reconfigurable DC Storages Reconfigurable storages, particularly battery-based ones, have been suggested for EV applications. For instance, [45, 46], and [47] explore a double-arm MMC topology incorporating batteries in a storage system with three phases. However, the doublestar configuration is better suited for capacitor-based modular power electronics. In another example, [20] put forward an MMC with integrated batteries in each module, offering fault tolerance, high modularity, and complete control over the dclink voltage when driving a switched reluctance motor. However, the topology is only limited to switched reluctance motors. Although a vast range of topologies exists that drive the electric motors, most modular topologies ignore the auxiliary loads of an EV. Therefore, as Fig. 5.3 depicts, they need a separate battery and at least one more energy conversion stage. Moreover, due to current safety measures, auxiliary supplies below the safety extra-low voltage level must be isolated from the high-voltage side.2 Isolating the auxiliary unit from the high-voltage battery pack raises the system’s cost, complexity, and volume/weight [48, 49]. To address the issue of galvanic isolation, [50] suggest an inductively coupled battery-integrated full-bridge inverter. However, multiple high-frequency transformers and numerous active components decrease efficiency and increase the system’s cost and size. References [51, 52] introduce an intriguing method in which each battery module exchanges energy with the auxiliaries through an isolated dualactive bridge converter [51, 52]. While this approach can provide greater flexibility, the cost and complexity of the proposed solution are significant. Another option is cascaded full-bridge converters, as [53] recommend, but a separate isolated converter is still required. Reference [48] incorporate part of the auxiliary circuit with the onboard charger to lower the cost, but a non-modular battery pack is assumed. Considering the extremely high DoF in a modular storage system, it is conceivable to try and generate more than one output level, leading to what is known as a 2

Safety standards for electric vehicles (EVs) are put in place to protect both the users and the equipment from electrical hazards associated with high-voltage batteries. One of the key safety requirements is the isolation of low-voltage auxiliary systems from the high-voltage battery pack. This isolation ensures that the low-voltage systems do not come into direct contact with the highvoltage battery pack, thereby preventing possible electrical shock, short circuits, or other hazards. Several international standards and regulations govern the design and operation of EVs and their components, including high-voltage battery systems: (i) IEC 61851: This standard specifies the general requirements for the electric vehicle supply equipment (EVSE) and the charging systems of EVs. It also covers the safety and performance requirements for the EV charging process, including isolation between high-voltage and low-voltage systems; (ii) ISO 6469: This standard focuses on the safety aspects of electric road vehicles, including their battery systems. It defines the requirements for electrical protection, functional safety, and the prevention of potential hazards during the operation, maintenance, and disposal of electric vehicles; (i) SAE J1766: This standard, developed by the Society of Automotive Engineers (SAE), provides guidelines for minimizing hazards associated with high-voltage electric propulsion systems in electric vehicles. It addresses the isolation of highvoltage systems, requirements for insulation and shielding, and the use of safety barriers; (i) UL 2202: This standard, developed by Underwriters Laboratories (UL), covers the safety requirements for electric vehicle charging system equipment. It includes specifications for isolation, grounding, and protection against electrical hazards.

150

5 Novel Topologies and/or Techniques for Emerging Applications

Fig. 5.3 Electrical circuit of an EV with modular reconfigurable batteries and separate auxiliary (modified based on [12])

Active FB

=/~

3-ph Inverter HFT

Active FB

Auxiliaries 12 V/48 V

multi-port system. Multi-port power electronic circuits are systems that can handle multiple inputs and outputs simultaneously, enabling efficient energy management and conversion in a variety of applications. These circuits have the potential to generate multiple outputs for electromobility applications by managing and converting power from different sources such as batteries, solar panels, or other renewable energy sources. Interestingly, every modular reconfigurable storage system is a multiport system. While multi-port systems have been around for some time in other applications such as grid-storage systems, the majority of existing topologies are not suitable for reconfigurable battery systems in EVs [54, 55].

5.1 Modular Reconfigurable Systems in Electromobility

151

This chapter fills this gap by presenting new strategies for modular reconfigurable power electronics to create multiple separate outputs by exploiting the additional DoFs and developing methods to decouple the control of each output. Such techniques are particularly of interest in EV applications. They can significantly simplify the generation of an isolated auxiliary output without negatively impacting the operation of the MMS controlling the dc-link voltage of the inverters. For better clarity, the concept is presented in two parts. The first part introduces a more detailed yet more restricted concept of a dual-port setup, and the second part studies a more general case by expanding the concept into multiple ports and outputs. Furthermore, the general concepts can be used with all the studied structures, This chapter uses the terms batteries and storage elements interchangeably unless specifically mentioned.

5.1.1.1

Dual-Port DC MMS

The primary objective is to leverage the pulsating DC voltage of the MMS or modular power electronics to generate an additional (isolated) output for low-voltage auxiliaries. A generic procedure for decoupling the control of the main output (e.g., the inverter’s dc-link) and the isolated auxiliaries should be established. The main DC output can closely track the inverters’ optimal operating point, while the auxiliary output can maintain a constant voltage or controlled current under varying loads. The system’s appeal is further enhanced by fewer semiconductors than traditional topologies and significantly reduced filter and transformer size. Figure 5.3 displays the state-of-the-art macro structure of a system with a dc MMS. The modular topology, combined with the inductor (L) and the dc capacitor (Cdc1 ), forms a dc-dc buck converter (i.e., the circuit in black in Fig. 5.6) that can control the dc-link voltage of the traction inverters. Additionally, an isolated dual-activebridge converter offers a secondary output for auxiliaries. However, incorporating a completely separate converter with numerous active switches is not cost-effective. As the power transfer is conventionally unidirectional, the dual-active-bridge converter can be replaced with a single-active one with slightly lower efficiency as Fig. 5.4 shows. Furthermore, the battery-side switches must handle the pack’s total voltage, for example, 800–1000 V in an 800 V storage system which with sufficient derating can lead to the 1200 kV semiconductor class range. Higher voltage semiconductors make high switching frequencies difficult and potentially increase the size of the transformer (HFT). A more intelligent alternative can utilize the available DoFs to incorporate additional functionalities with minimal added components. Therefore, a closer examination of the system’s behavior is required. Figure 5.5 shows the conceived system where the only controlled semiconductors are in the storage modules. In Fig. 5.6, the dc capacitors (Cdc2 and Cdc3 ), the highfrequency transformer, and the diode-bridge create a second isolated output port for the EV’s auxiliary loads (see the circuit in blue in Fig. 5.6). Comparing Figs. 5.3 and 5.5 reveals that the proposed system only requires a diode-bridge with the auxiliaries’ rated voltage and a small high-voltage decoupling capacitor. Additionally, the

152

5 Novel Topologies and/or Techniques for Emerging Applications

Fig. 5.4 Electrical circuit of an EV with modular reconfigurable batteries and separate unidirectional auxiliary (modified based on [12])

Active FB

=/~

3-ph Inverter HFT

Diode Bridge

Auxiliaries 12 V/48 V

effective switching frequency is considerably higher, reducing the transformer and filters’ volume and size. Figure 5.6 illustrates the electrical circuit of the proposed system. As energy flow typically goes from high-voltage batteries to auxiliaries, using a diode bridge simplifies the controller and lowers system costs. Alternatively, the HFT can act as the inductor in the LC filter in Fig. 5.6. Hence, the topology can be further simplified as Fig. 5.7 depicts. However, the dc-link capacitor is now subjected to the complete current ripple generated by the auxiliary circuit and the HFT will operate at the current ratings of the main output port.

5.1 Modular Reconfigurable Systems in Electromobility

153

Fig. 5.5 Electrical circuit of the envisioned EV with modular reconfigurable batteries and integrated auxiliary output (modified based on [12])

HFT

=

Diode Bridge

~

Although the analysis applies to any sufficiently large storage type, batteries are more dominant in EV applications. Hence the following considers a batterybased MMS. Additionally, in Fig. 5.6, the capacitors in parallel with the batteries are optional for both reducing stress from the batteries and providing a low-impedance path for current commutation during switching.

154

Normal HalfBridge

5 Novel Topologies and/or Techniques for Emerging Applications

(N)th Switch-Set

N th

Main LOAD

(N-1)th Switch-Set

Normal HalfBridge or Parallel Capable Switch-Sets

2nd Switch-Set Optional

2nd

1st Switch-Set Auxiliary LOAD

1st HFT Fig. 5.6 The electrical circuit of the EV with integrated auxiliary output [56]

Various topologies can serve as the electronic foundation for battery modules, as explored in Chap. 3. Half-bridges offer the simplest form capable of generating a multilevel output voltage using low-voltage switches [57–59]. However, other topologies like the three-switch and unidirectional FB topologies provide additional parallel connectivity across modules [60–63]. Any other module topology that can produce a two-level output for the modules is also suitable. Therefore, depending on the application requirements, different topologies can be selected. As the battery modules are the only actively controllable components in the system, traditional control techniques cannot independently manage both outputs. To devise a method for decoupling the control of these two outputs, it is essential to investigate the behavior of each converter and determine the equations that dictate their interactions. High-Power Modular dc-dc Converter As illustrated in Figs. 5.1 and 5.3, the state-of-the-art dynamically reconfigurable battery system supplants the formerly hard-wired battery and the distinct non-isolated

5.1 Modular Reconfigurable Systems in Electromobility

155

Fig. 5.7 Electrical circuit of the envisioned EV with modular reconfigurable batteries with the integrated auxiliary output in series to the dc-link capacitor (modified based on [12])

HFT

=

Diode Bridge

~

dc-dc converter. Nevertheless, the auxiliary topology remains unchanged. During discharge, the MMS functions as a multilevel buck converter, responsible for maintaining the traction inverters’ dc-link voltage within the optimal range [64, 65]. Determining the inverter’s optimal operating region or its control is a well-established process and beyond the scope of this book [64, 66, 67]. Hence, without any loss of generality, we regard the desired dc-link voltage for the inverters as an arbitrary reference value and represent the inverter(s) and the motor(s) connected to the dc-link as a variable load connected to it.

156

5 Novel Topologies and/or Techniques for Emerging Applications

N th

Main LOAD

(N-1)th Switch-Set

Parallel Capable Switch-Sets

2nd Switch-Set Optional 2nd

1st Switch-Set Auxiliary LOAD

1st HFT

Fig. 5.8 The electrical circuit of the EV with integrated auxiliary output and reduced number of switch-sets. © 2023 IEEE. Reprinted, with permission, from [69, 70]

The established PSC modulation determines the switching pulses for the modules in the string [44, 68]. Each switch-set in Fig. 5.6 corresponds to one carrier. Typically the number of carriers matches the number of modules in the string, as Fig. 5.6 illustrates. However, in the case of modules with parallel connectivity, it is possible to reduce the number of switch-sets as Fig. 5.8 shows. The general behavior of the system in both cases is similar, but as the previous chapter has already investigated the strings with a similar number of storages, switch-sets, and corresponding carriers, here is a string with a reduced number of switch-sets for better clarity. As Fig. 5.8 shows, N battery modules require (N − 1) carriers and (N − 1) switching circuits. The carrier waveforms are compared with one global modulation index (here, the effect of balancing or scheduling is neglected) to determine the switching pulses for the corresponding switching circuits. Figures 5.9 and 5.10 show a graphical representation of carriers in a system with a system with (N − 1) carriers as well as the effective carrier of such a system due to PSC modulation. Additionally, the higher effective switching frequency is intuitively depicted for three modules in Fig. 5.11. With (N − 1) individual switching circuits

5.1 Modular Reconfigurable Systems in Electromobility #1

#(N-2)

Carriers 1

157 #3 Modulation Reference (m)

( j+1)/(N-1) j/(N-1)

3/(N-1) 2/(N-1) 0

time

Fig. 5.9 Intuitive representation of carriers in conventional PSC modulation. © 2023 IEEE. Reprinted, with permission, from [69, 70]

Tsw one carrier

Modulation Reference (m) ( j+1)/(N-1)

j/(N-1)

Modulation

Vbase

Vpulse

Output Voltage

Fig. 5.10 Graphic illustration of the carriers in conventional PSC modulation and the effective equivalent carrier waveform. © 2023 IEEE. Reprinted, with permission, from [69, 70]

or switch sets, the first harmonic of the output voltage in the system is (N − 1) times the frequency of one carrier. The voltage of the dc-link at the main load according to the terminal voltage of the modules is Vdc1 = (1 + m (Narm − 1)) Vm where Vm is the voltage of one module.

(5.1)

158

5 Novel Topologies and/or Techniques for Emerging Applications

Tsw

Module is in series

Module 1

time Module 2 time Module 3 time Effective time

Tsw 3

Fig. 5.11 Graphical representation of the increased effective switching frequency due to the PSC modulation

Vdc1 HFT

Cdc2 VBase + Vpulse

Cdc3 Vdc2

Vin N1 : N2

load

Fig. 5.12 Circuit diagram of the integrated auxiliary unit. © 2023 IEEE. Reprinted, with permission, from [69, 70]

Low-Power Isolated Port for the Auxiliaries This section derives the essential equations for computing the isolated auxiliary port’s output based on the modulation index m. Figure 5.12 displays the circuit of this port, with the input voltage being the pulsating output of the reconfigurable pack. Based on the values of m and N , the output of the system using PSC modulation resembles the sum of a constant voltage (Vbase ) and a PWM-regulated voltage (Vpulse ∈ [Vm , 0]). Figure 5.10 illustrates that the pulsating voltage’s effective switching rate is (N − 1) f sw , with f sw representing the frequency of a single carrier. The base voltage value is then determined per Vbase = m (Narm − 1) + 1 Vm .

(5.2)

5.1 Modular Reconfigurable Systems in Electromobility

Vin

Vp+

159

D=0.75 D=0.50 D=0.25 time

Vp_

D

1-D

Tsw,eff = Tsw /(N-1) Fig. 5.13 Intuitive representation of Vin with different D

Figure 5.10 displays the effective carrier waveform for the PWM voltage in a clear way. By contrasting the modulation reference and the effective carrier waveform, the duty cycle of the pulses can be determined D = m(N − 1) − m(N − 1);

(5.3)

which demonstrates a cyclic function of m. For each operational state, the capacitor Cdc2 charges to Vdc1 according to (5.1), and the input voltage (Vin ) applied across HFT fluctuates between a positive step (V p+ ) and a negative step (V p− ). These pulses are determined based on 

V p+ = (1 − D) (Vm − Vr ) , V p− = −D (Vm − Vr ) ,

(5.4)

where Vr is the voltage ripple of the decoupling capacitor. Altering m modifies the value of D, which influences the applied voltage waveform across the primary of the transformer. Consequently, unlike the dual-active-bridge topology, both the amplitude and width of the resulting pulses vary concerning m and subsequently D, which complicates developing a suitable controller. On the other hand, with knowledge of (5.3), it is possible to control the width and amplitude of both positive and negative pulses using m. Figure 5.13 illustrates this variation in an intuitive manner. Based on (5.4), increasing D not only widens V p+ but also effectively diminishes its amplitude and vice versa. There are two possible scenarios, depending on the value of D as per 

D  0.5 V  V p− . ⇒ p+ V p+ < V p− D > 0.5

(5.5)

160

5 Novel Topologies and/or Techniques for Emerging Applications

HFT equivalent circuit Diode Bridge

Fig. 5.14 Equivalent circuit diagram of the integrated auxiliary unit from the primary side. © 2023 IEEE. Reprinted, with permission, from [69, 70]

For D < 0.5, the amplitude of the positive pulse is greater than the negative pulse. During the interval 0  t  DTsw,eff , the diode-bridge is forward-biased, and the capacitor (Cdc3 ) is charged while supplying the load. Throughout the DTsw,eff  t  Tsw,eff interval, when V p− < Vdc2 , the diode-bridge is reverse-biased, and Cdc3 discharges into the load. The output of the system for D < 0.5 can be described as  N2  Vdc2 = V p+ N1

(5.6)

where NN21 is the primary to secondary ratio of the HFT. Finally, the approximate gain of an ideal system (i.e., without any parasitic elements) for D  0.5 is Vdc2 = Vm



1− D 1+



Vr Vm

N2 . N1

(5.7)

Taking into account the voltage drop across the parasitic or stray resistive elements of the auxiliary path depicted in Fig. 5.14, a more accurate gain for D  0.5 can be derived (refer to Appendix A). Hence, the nonideal gain of the system follows r (1 − D) NN21 (1 − V )− Vdc2 Vm = Vm Req + 1

2Vfd Vm

.

(5.8)

Equation (5.8) can be further simplified by neglecting Vfd and Vr into Vdc2 = Vm



1− D Req + 1



N2 , N1

(5.9)

Value of Req in (5.8) and (5.9) represents the effective resistance across the auxiliary path following

5.1 Modular Reconfigurable Systems in Electromobility

 Req =

N2 N1

2

161

  rCdc2 + r L1 + r L2 + 2rfd



1 . D Rload

(5.10)

For D values greater than 0.5, the negative pulse is greater, resulting in the reversebiasing of the diode-bridge during positive pulses (0  t  DTsw,eff ). During negative pulses (DTsw,eff  t  Tsw,eff ), the capacitor charges. The system output for D > 0.5 is given by  N2  . Vdc2 = V p− N1

(5.11)

Ultimately, the gain of an ideal system without any parasitic elements for D > 0.5 can be expressed as Vdc2 = Vm





D 1+

Vr Vm

N2 . N1

(5.12)

A more accurate gain for D > 0.5 can be obtained by taking into account the parasitic components represented in Fig. 5.14 per r D NN21 (1 − V )− Vdc2 Vm = Vm Req + 1

2Vfd Vm

.

(5.13)

For the exact derivation process, see Appendix A. By neglecting Vfd and Vr , (5.13) is simplified to Vdc2 = Vm



D Req + 1



N2 , N1

(5.14)

where Req in (5.13) and (5.14) is the total resistance of the auxiliary path that can be expressed by  Req =

N2 N1



2 req1 + req2

1 . (1 − D)Rload

(5.15)

Both equations, (5.7) and (5.12), exhibit symmetry with respect to D = 0.5. For example, the output of the ideal system for D = 0.25 and D = 0.75 are comparable. Therefore, the two equations can be combined into one following Vdc2 max(D, 1 − D) = . Vm Req + 1

(5.16)

162

5 Novel Topologies and/or Techniques for Emerging Applications

With a resistive load across the main port, the higher modulation indices will increase the output voltage and consequently output current. Hence, the output gains due to the higher modulation indices are slightly lower, as higher currents increase the voltage drop across the batteries. The symmetry observed in Fig. 5.19 implies that for each operating point of Vdc2 , there exist two possible values of D. Additionally, each D value yields (N − 1) possible values of m, according to (5.3). Hence, there are 2(N − 1) m values for every operating point of the auxiliary load, resulting in the same output voltage (Vdc2 ) but different dc-link voltages (Vdc1 ). Stated differently, each operating point of the auxiliary load corresponds to 2(N − 1) potential Vdc1 values for a specific D. In a system with N switching circuits, such as the one in Fig. 5.6, each operating point of the auxiliary load would have (2N ) possible Vdc1 values. The possible values of m that result in similar D can be determined as follows.     i−D i −1+ D , ∀ i = 1, . . . , N − 1, (5.17) m i (D) = N −1 N −1 and consequently, possible Vdc1 values are Vdc1,i = (N − 1)Vm m i (D) + 1.

(5.18)

The primary aim of the system is to maintain a constant voltage for the auxiliary while closely tracking the reference voltage of the main load. The analysis reveals the existence of 2(N − 1) operating points for the dc-link voltage corresponding to each operating point of the auxiliary output. This additional degree of freedom can be utilized to design a controller that can independently control the output of each load. The controller first identifies the optimal operating point for the auxiliary load (D ∗ ) and then selects the best m among the 2(N − 1) options. Due to the presence of non-ideal components, a closed-loop controller is employed to regulate the operating point of the auxiliary by means of D. General Control Strategy ref The optimal operating dc-link voltage for the inverter (Vdc1 ) is arbitrary and can be set to any value within the voltage range of the batteries. This value is provided as input from higher-level control loops. The output voltage of the auxiliary power unit (Vdc2 ) is constant and in most EVs set to around 12 V (per LV 124 standard) or 48 V (per LV 148 and VDA 320 standards). Figure 5.15 illustrates the developed control strategy when both ports in the system are active, e.g., during driving. The efficiency maps of the system can be used at each ref is the rated voltage instance to obtain a reference value for Vdc1 . The value of Vdc2 of the auxiliary power unit. The measured voltage at the output of the auxiliary power unit is represented by Vdc2 , and the average operating voltage of the modules is denoted by Vm . Initially, a PI controller is employed to calculate the required D ∗ to maintain the voltage of the auxiliary output at a constant level. Subsequently, the algorithm uses (5.17) to determine possible modulation indices (m i ) for D ∗ and

5.1 Modular Reconfigurable Systems in Electromobility

163

- Vbase = floor(V* ) - If V* = Vbase m = (Vbase+0.5− D* )/(N-1)

_

- ElseIf (V*− Vbase)≥0.5 m = (Vbase+0.5+D* )/(N-1)

_ ∑

∀∈

- Else m = (Vbase+0.5− D* )/(N-1)

÷

…

Fig. 5.15 Developed controller with symmetric PSC modulation and reduced number of switch-sets in discharge mode. © 2023 IEEE. Reprinted, with permission, from [69, 70]

(1 − D ∗ ). It then selects the m value that minimizes the discrepancy between Vdc1 ref and Vdc1 , as specified in (5.18). This fully regulates the output voltage of the auxiliary unit to a constant value and maintains the dc-link voltage of the inverters within a small boundary of the optimal point. The largest possible difference between the dcref depends on the transformer ratio and the number of modules link voltage and Vdc1 in the system following Vmax 

0.5 Vm . 1− N

(5.19)

The principal operation of the system during charge and discharge modes are similar, and the provided analysis holds for both modes. The only difference is that the current sign of i dc1 is positive during discharging and negative during charging. Regardless of the current direction, the system can also provide power to the auxiliaries. Typically, dc chargers have two limiting factors: maximum current and maximum power. It is preferable to increase the voltage of the string to the highest value that the charger can support (Vdcref = V max, charge ) to maximize the charge power. However, the dc-link voltage (Vdc1 ) reference can be arbitrary within the operation range of the charger. Figure 5.16 illustrates the control algorithm during this mode. Lastly, when the EV is at a standstill but the auxiliaries are still operating (e.g., ref behind the traffic light or while parking), the dc-link voltage reference (Vdc1 ) can be selected arbitrarily. However, the minimum operating voltage should be selected to minimize the stress on the caps. Figure 5.17 illustrates the control diagram during the idle operation. It is also possible to supply the main load without generating any voltage at the output of the auxiliary port. To that end, the value of D should be zero, which means i . Alternatively, it is possible to select the modulation index of each module m i = N −1 in a way that the summation of the generated pulses is a completely level dc voltage.

164

5 Novel Topologies and/or Techniques for Emerging Applications

If

_

− ElseIf

−

≥

_

÷

∑

∀∈

Else

−

…

Fig. 5.16 Developed controller with symmetric PSC modulation and reduced number of switch-sets in charge mode - Vbase = floor(V* ) - If V* = Vbase m = (Vbase+0.5− D* )/(N-1)

_

- ElseIf (V*− Vbase)≥0.5 m = (Vbase+0.5+D* )/(N-1)

Vmin

- Else m = (Vbase+0.5− D* )/(N-1)

Fig. 5.17 Developed controller with symmetric PSC modulation and reduced number of switch-sets in idle mode [69, 70]

Self-Balancing Capability When D is less than or equal to 0.5, the diode-bridge conducts solely during the positive pulses, and the ratio of energy transfer is a linear function of the pulse duration. If all modules have similar voltages, then equivalent quantities of charge are extracted from each module. However, if a module has a higher voltage, its corresponding positive pulses’ amplitude increases, leading to higher charge transfers during these intervals. Thus, the auxiliary circuit takes more energy from modules with higher voltages at higher SoCs and less energy from modules with lower voltages at lower SoCs. This characteristic produces a built-in balancing ability irrespective of the module topology without the need for an additional controller. The effectiveness of the inherent charge balancing depends on the voltage profile versus SoC of the storages. For example, Fig. 5.18 shows the general curve of a Li-ion battery that is discharging with 1 C. In general, at the beginning and end of the profile, the terminal voltage of the battery varies noticeably with SoC variations. However, in the middle of the curve, the battery’s terminal voltage has a much smaller slope. Therefore, the inherent charge balancing will have a better effect if the battery operates at the two ends of the curve (at low or high SoCs). The balancing capability of the integrated auxiliary unit is advantageous during idle states where the main port does not draw any current but the auxiliary unit is still

Large ΔV/Δ(SOC)

Flat Region

165

Large ΔV/Δ(SOC)

5.1 Modular Reconfigurable Systems in Electromobility

Fig. 5.18 Generic curve of the terminal voltage of the battery versus its SoC

functional. This enables the unit to provide power while balancing the modules. To reduce stress on the dc-link and the decoupling capacitors, it is advisable to minimize the modulation index of the modules. Thus, setting the reference value of Vdc1 to its minimum is sufficient to obtain the control algorithm in this mode, as shown in Fig. 5.15. Despite considering a simple global modulation index for all modules, as long as the modulation indices are so diverse that they change the operating point of D, other balancing or scheduling techniques can also be combined with the global m. Design Considerations L dc and Cdc1 can be chosen conventionally for the main port as it behaves like a buck converter with a much higher effective switching frequency. The values of the module voltage and the expected voltage of the auxiliary power unit determine the transformer ratio N2 : N1 . The appropriate range for N2 : N1 can be determined based on (5.7) and (5.12). 

   Req + 1 (V dc2 − Vfd ) Req + 1 (V dc2 − Vfd ) N2  .  0.95(V m − Vr ) N1 0.5(V m − Vr )

(5.20)

While (5.20) provides a large range for calculating the transformer ratio, in practice, the voltage of battery modules can vary depending on their state of health. For example, for many Li-Ion cell chemistries, such as Li-NMC, the voltage ranges between 0.8 and 1.2 V rated. Therefore, a more realistic relation for calculating the transformer ratio is     Req + 1 (V dc2 − Vfd ) Req + 1 (V dc2 − Vfd ) N2   , (5.21) 0.95(Vm,min − Vr ) N1 0.5(Vm,max − Vr )

166

5 Novel Topologies and/or Techniques for Emerging Applications 0.7

Fig. 5.19 Gain variations of the auxiliary power unit with respect to D

Stable Control Range

0.65

Vdc2/Vm

0.6 0.55 0.5 0.45

GainSim GainIdeal

0.4

GainNonideal

0.35 0.2

0.4

0.6

0.8

Deff Table 5.1 Simulation parameters of the dual-port setup [69, 70]

Parameter

Value

Vdc1 Cdc1 L dc Cdc2 Cdc3 Rldc Pload,1 Pload,2 f carrier f sw,effective Rds ,Rd Vm rbt,1 8˜

400–800 V 20 µF 23 µH 348 µF 5.4 mF 10 m 300 kW 5 kW 5 kHz 25 kHz 1 m 82–103 V 5 m

where Vm,min and Vm,max are the minimum and maximum operating voltage of one module. In addition to the parasitic impedance, the gain of the system is affected by Req in (5.9) and (5.14), resulting in nonlinearity. When D approaches the upper and lower limits (i.e., close to one and zero), the impact of parasitic impedance on the system increases significantly. To illustrate, Fig. 5.19 compares the gains obtained from simulations using both ideal and non-ideal equations. Table 5.1 presents the parameters employed in the simulated setup. The system’s controllable range can be improved by designing its normal operating point closer to D = 0.5, as shown in Fig. 5.19. In contrast, the performance of the system deteriorates when D < 0.2 or D > 0.8. Therefore, the preferred value

5.1 Modular Reconfigurable Systems in Electromobility

167

for N2 : N1 is the upper boundary in (5.21). By replacing Req with (5.10) or (5.15) and solving for N2 : N1 , the suitable value for the transformer ratio can be obtained. Capacitor Cdc2 is utilized for separating the dc and switching components of the voltage. The system behavior is considerably influenced by the voltage ripple of capacitor Cdc2 , as demonstrated in (5.13) and (5.13). By applying an analysis comparable to that of the transformer ratio design, the minimum capacitor required for the system can be obtained as follows Cdc2 =

N2 Pmax2 , Vdc2 (Vr ) f sw,effective N1 

(5.22)

(N −1) f sw

where Pmax2 denotes the rated power of the auxiliary unit, and f sw,effective represents the equivalent frequency of the pulses at the primary of HFT. The minimum capacitance required for capacitor Cdc3 can be determined in a similar way, and it is given by Cdc3 =

Pmax2 . V2 ((Vr ) f sw,effective

(5.23)

Since MMS results in higher effective frequency and smaller voltage steps compared to a conventional battery pack, a significant reduction of required capacitances (Cdc1 , Cdc2 , and Cdc3 ) and inductance (L dc ) by a factor of 1/ N −1 is expected. Comparison with State-of-the-Art Table II provides a qualitative comparison of the proposed system with state-of-theart topologies, which demonstrates that The developed system has all the general advantages attributed to MMS. Additionally, the proposed system has fewer semiconductors than other MMSs with an independent auxiliary circuit [20–22]. Moreover, the transformer operates at a lower voltage and with (N − 1) times the switching frequency of one module, leading to a significant reduction in weight and volume. Finally, the inherent balancing capability ensures that the battery modules remain balanced even in the absence of a closed-loop balancing controller.

5.1.1.2

Simulation and Experimental Validation

In order to simulate the proposed system, MATLAB/Simulink is utilized with the main parameters provided in Table 5.1, considering ten modules. The batteries are modeled using a simplified electrical equivalent circuit, comprising an internal resistance and a constant dc voltage source. A variable load with a variable reference voltage is connected to the modular battery. The rated voltage of each battery module is 91 V, which can fluctuate between 80 and 105 V. The reference voltage for Vdc2 is set to 48 V, as it is becoming increasingly common in executive and sports cars and may soon expand to economy vehicles. Based on the module voltage range and ref , the transformer ratio is approximately 1.13, as determined by (5.21). Vdc2

168

5 Novel Topologies and/or Techniques for Emerging Applications

250 Vdc1

400

Vdc1,opt

200 0

200

I dc1 [A]

V dc1 [V]

600

150

Idc1

0

1

2

3

4

5

100

Vdc2

20

50

Vdc2,ref

I dc2 [A]

V dc2 [V]

100 40

Idc2

0

0

1

2

3

4

5

0

time [sec] Fig. 5.20 Voltage and current waveforms of both ports for the simulated system. © 2023 IEEE. Reprinted, with permission, from [69, 70] Fig. 5.21 The pulsating voltage of the modular reconfigurable battery. © 2023 IEEE. Reprinted, with permission, from [69, 70]

D=0.37 D=0.63

During simulation, the rated battery voltages are considered. The voltage and current waveforms of the first and second outputs are shown in Fig. 5.20. Additionally, Fig. 5.21 illustrates the instantaneous voltage of the battery pack in addition to its dc value, which clearly shows the resulting pulses. The simulation includes variations in the optimal reference voltage and demand power for the first output, as well as intermittent changes in the demand power for the second output. Despite these variations, the controller is able to maintain a fixed Vdc2 . Moreover, the voltage of the first output closely tracks the optimal reference provided to the controller. The steady-state ripple of Vdc1 and Vdc2 is less than 3% and 1%, respectively.

5.1 Modular Reconfigurable Systems in Electromobility

169 PI Controller D m

1

0.1

0.05

0 0

2

4

V 2 [V] [pu]

0.1 steady state

V2 < 0.2 %

0.05

Modulation Signals [pu]

V 1 [pu]

V1=|V dc1,opt-Vdc1 |/V dc1,opt

0.8

0.6

0.4

0.2

0

0 0

2

4

time [sec]

0

2

4

time [sec]

Fig. 5.22 The control signals as well as the outputs’ deviations from reference values. © 2023 IEEE. Reprinted, with permission, from [69, 70] Fig. 5.23 Balancing performance of the integrated auxiliary when both ports are actively discharging the modules (P1 = 25 kW, P2 = 3 kW) [69, 70]

Δ

Δ

Figure 5.22 displays the modulation signals for both outputs as well as the voltage deviation from their respective reference values. Although some transients are present at the start of each step, the steady-state error for the second output is less than 0.2%. Similarly, the maximum deviation of Vdc1 from its reference value during transients is limited to 6%. Furthermore, Fig. 5.23 illustrates the inherent self-balancing capability of the system when both ports are providing power to their respective loads. In the simulated system, the modules have different initial SoC values and a maximum capacity tol-

170

5 Novel Topologies and/or Techniques for Emerging Applications

Fig. 5.24 Voltage and current profiles of the reconfigurable-battery ports during charge. © 2023 IEEE. Reprinted, with permission, from [69, 70]

erance of 6% from the rated values. Figure 5.23 shows that the balancing speed is initially high, but it decreases as the SoC values get closer to the average SoC and the voltage differences between the modules reduce. The balancing speed gradually approaches zero as the voltage differences between the modules get closer to the voltage drop across the parasitic elements. The figure also demonstrates that the balancing limit for the simulated modules is less than 1%, which depends on the parasitic voltage drop and the capacity tolerances. The presented system has the capability to supply power to the auxiliary unit while charging the battery pack. Figure 5.24 illustrates the terminal voltage and current of the auxiliary unit during charging with a constant current of 100 A. An experimental setup using a reconfigurable battery pack with five modules validates the analysis and simulations. To implement the proposed control algorithms and the PSC modulation, an FPGA-based rapid prototyping controller (sbRIO 9726) is used, and measurements are recorded using an eight-channel oscilloscope from LeCroy. To provide isolated feedback of the second dc output, an isolated transducer (LV25P) with an analog amplifier is utilized due to its low settling time. Each battery module consists of six series cells that offer a 24 V open-circuit voltage. A load with a resistance of 5.5  is connected to the first dc output, and a controllable electronic load is connected to the second isolated output. The laboratory setup’s parameters are summarized in Table 5.2, and Fig. 5.25 shows the laboratory testbench. The FPGA controller takes the desired voltage of the first dc output (Vdc1,ref ) as an arbitrary input signal, and the reference output of the auxiliary port only changes between 0 V when it is turned off and 12 V when it is operating. Using the proposed algorithm, the controller determines the most suitable modulation index and generates the switch signals for all modules. The measurements for the output voltage and current of the main output port are shown in Fig. 5.26.

5.1 Modular Reconfigurable Systems in Electromobility Table 5.2 Parameters of the dual-port prototype with five modules

171

Parameter

Value

Vdc1 Cdc1 L dc Cdc2 Cdc3 Rldc Pload,1 Pload,2 f carrier f sw,effective Rds ,Rd Vm rbt,1 8˜

20–100 V 100 µF 200 µH 940 µF 2.7 mF 50 m 2 kW 36 W 5 kHz 25 kHz 1 m 22–25.2 V 20 m

Fig. 5.25 Laboratory testbench for the dual-port setup with symmetric PSC. © 2023 IEEE. Reprinted, with permission, from [69, 70]

The terminal voltage of Vdc1 is closely following the reference value Vdc1,ref for each step, as shown in Fig. 5.26. Similarly, Fig. 5.27 displays the voltage and current at the auxiliary port’s terminal with a zero steady-state error. Although the output voltage of the main port does not fully converge to its desired value due to the limited number of possible points with only five modules, it remains close to the reference

172

5 Novel Topologies and/or Techniques for Emerging Applications 25 80

60

15 10

Vdc1

40

Vdc1,ref

5

Idc1

20 0

2

4

6

I dc1 [A]

V dc1 [V]

20

0 10

8

time [s] Fig. 5.26 Measured voltage and currents at the semi-controlled main port during discharge. © 2023 IEEE. Reprinted, with permission, from [69, 70]

Turn on instant

Vdc,ref2 = 12 V

Turn off instant

12

Vdc,ref2 goes to 0 V

Fig. 5.27 Measured voltage and currents at the auxiliaries. © 2023 IEEE. Reprinted, with permission, from [69, 70]

value. However, since the number of battery modules can be increased, the output voltage of the main port can follow the reference even more closely. On the other hand, the output voltage of the auxiliaries closely follows its reference value at all times, regardless of the number of modules, and with no transients. The errors of the output voltages from their target values are shown in Fig. 5.28. The error of output voltage for the auxiliary port Vdc2 = Vdc2,ref − Vdc2 remains below 2%. Despite relatively large deviations in the reference voltage of Vdc1 , the provided output voltage is within a 6% limit, which is a notable enhancement compared to a fixed dc-link voltage in conventional systems. Additionally, Fig. 5.29 depicts the primary and secondary voltages of the switching transformer, indicating that the voltage at the transformer’s primary is close to Vm /2 despite the main port’s dc-link voltage. The transformer primary has a narrow operating voltage range, which sim-

5.1 Modular Reconfigurable Systems in Electromobility

173

Fig. 5.28 Voltage deviations from the reference values. © 2023 IEEE. Reprinted, with permission, from [69, 70]

Fig. 5.29 The measured voltages at the primary and secondary terminals of the HFT. © 2023 IEEE. Reprinted, with permission, from [69, 70]

plifies its isolation requirements. Small spikes are present on the primary side due to sudden changes in the reconfigurable battery’s operating point, but the HFT acts as a filter, eliminating them on the secondary side. An additional advantage of the presented system over the conventional reconfigurable battery system is the higher equivalent switching frequency, which reduces the size of the HFT. Moreover, the new auxiliary circuit does not need any high-voltage full-bridge circuit on the battery side, leading to significant cost reduction. Moreover,

174

5 Novel Topologies and/or Techniques for Emerging Applications

the developed controller does not require any modifications for the extension of the system to more modules. The analysis, simulations, and experimental measurements confirm the suitability and effectiveness of the developed topology and method. Compared to conventional hard-wired battery packs, which exhibit output fluctuations of over 40%, the nonisolated traction output is controlled to within 6% of the rated voltage with five modules, which can be further reduced with a higher number of modules. Adding more modules can also enhance the resolution of the primary non-isolated output.

5.1.1.3

Extended Multi-port Concept Through Symmetric and Asmmetric PSC Modulation

The previous part presented a novel control technique for decoupling the control of two different ports connected to the same string. This part further expands the concept and investigates the possibility of more ports in a larger string using the string interconnections as Fig. 5.30. Here a generic topology and control for isolated and non-isolated ports based on an MMS with minimum added passive components are developed. Initially, a general case of PSC modulation is presented to develop the control strategy for the ports, which can happen when the ports are connected to only some of the available modules, resulting in an uneven distribution of corresponding carriers. Afterward, the gain of each port, considering the interaction of modules and the modulation technique, is calculated. Lastly, a closed-loop strategy is proposed to decouple the control of multiple interconnected ports in the system for each scenario. The controller fully exploits the available DoFs offered by MMSs without adding extra switches. Such features are in addition to the typical benefits of MMS and modular power electronics, including improved output granularity, higher effective switching frequency, and

Fig. 5.30 Generic structure of a string with interconnected ports. © 2023 IEEE. Reprinted, with permission, from [71, 72]

Lth

2nd

1st

Port

5.1 Modular Reconfigurable Systems in Electromobility

175

improved fault tolerance [71, 72]. Like Sect. 5.1.1.1, battery and storage terms are used interchangeably. In all cases, all the systems and control methods are generic and work for all types of voltage-based storages such as capacitors, SCs, and batteries. When some modules are not included in one or more strings, it may not be possible to achieve sensorless operation and balancing without parallel connectivity, as different modules will have different loads. Therefore, parallel connectivity might be necessary to ensure the modules remain in a balanced state. In this case, the missing modules and their corresponding carriers create a gap in the evenly distributed carriers of that string, resulting in asymmetric PSC. Both symmetric and asymmetric PSC modulations can affect the behavior of ports and must be considered during component analysis and design. While symmetric PSC can lead to better pulse distribution and lower filter requirements for a single port, asymmetric PSC can offer more DoF to control the output of multiple interconnected ports. Distributing the carriers as evenly as possible is generally preferred to increase voltage symmetry, improve voltage quantization, and reduce the required output filter size [41, 57]. Two main types of dc ports can be used, namely non-isolated and isolated. Various topologies for each of these ports can include different numbers of active and passive components. However, in most applications, especially in the field of electromobility, the complexity and cost of the system are important factors to consider. Hence, to develop the extended concept, the only fully controllable components for each port are the modular batteries, and no additional switches are considered [71, 72]. The terminal of a non-isolated port is generally connected through a low-pass LCfilter that forms a buck converter to discharge the batteries and a boost converter when charging them. The generic string of modular storages can be illustrated equivalently as shown in Fig. 5.31. Here, Vbase represents the minimum voltage of the string at each operating point, while Vpulse denotes a voltage that pulses. A non-isolated port’s possible representation is shown in Fig. 5.32, which can be connected to the modular storage system shown in Fig. 5.31. L 1 and Cdc1 are the components of the formed low-pass filter. Figure 5.32 displays the envisioned circuit diagram of an isolated port without any additional controlled switches. To decouple the high-voltage string from the sensitive load through galvanic isolation, capacitor Cdc2 and the high-frequency transformer (HFT) are used. The diode-bridge rectifies the high-frequency voltage, and capacitor Cdc3 provides energy to the load when the diode-bridge is not conducting, making this circuit a cost-efficient solution [21, 48].

Fig. 5.31 ECM of a generic string of modular reconfigurable storage elements

Vpulse

+ _

+ _

Vbase + _

Port

5 Novel Topologies and/or Techniques for Emerging Applications

Fig. 5.32 The electrical circuit of a non-isolated port. © 2023 IEEE. Reprinted, with permission, from [71, 72]

L1 Port terminals

Buck Vdc1

load

176

Cdc1 Boost

Figure 5.33 shows the equivalent electrical circuit of the string with the isolated load, considering the secondary side of the transformer. Here, 



Cdc2 =

N1 N2

2 Cdc2 ,

(5.24)

L es ,

(5.25)

and 



L es =

N2 N1

2

are the capacitance and series equivalent inductance of the transformer referred to the secondary side of the transformer. The upcoming section will show that the amplitude and duration of the positive and negative pulses applied to the HFT can vary significantly depending on the modulation index and the number of modules. A full-wave diode bridge can provide more control over the operation point of the ports without adding a fully controlled switch. Although adding two low-power diodes increases the cost slightly, it is insignificant since the isolated loads are usually for control and monitoring services, which require lower voltage and power than the non-isolated loads in most applications. Nevertheless, it is also possible to use only one diode or a halfwave diode bridge for the rectification.

Vac (N2/N1) Vdc1(N2/N1) Vdc1(N2/N1)

‚ Les Galvanic Isolation

‚ Cdc2

Diode Bridge

Cdc3

Vdc2

Fig. 5.33 The ECM of a non-isolated port from the secondary side of the transformer. © 2023 IEEE. Reprinted, with permission, from [71, 72]

5.1 Modular Reconfigurable Systems in Electromobility

5.1.1.4

177

Extended Symmetric PSC Modulation

Assuming NC to be the number of all the individual carriers in the system (assuming a similar number of switch sets and number of storages), the phase-difference (ϕ) between two successive carriers in symmetric PSC modulation is ϕ = k2π/NC ,

(5.26)

where k can be also a factor of NC ( {k∈ N| ∃L∈ N with k × L = NC }). For example, for NC = 9, L can be {1, 3, 9} to achieve conventional PSC. The carrier’s order is inconsequential as long as the maximum phase difference is k2π/L. A symmetric PSC modulation results in only two voltage levels (i.e., Vbase and Vbase + Vm ). Figure 5.34 depicts that the resulting output voltage contains a pulsing voltage (Vpulse ) added on top of a base level (Vbase ), i.e., a dc term and a squared ac one (as we also discussed in the previous section). The average dc term of the voltage across the string is Vdc1 = m L Vm

(5.27)

where m is the modulation index, L denotes the number of modules (as well as their corresponding carriers) included between the port’s terminals, and Vm is the nominal voltage of a module. The value of the base voltage is a function of the carriers’ number (L) as well as the modulation index (m) per Vbase = m LVm ,

(5.28)

where  denotes the floor function that returns the next smaller integer number [71, 72]. According to Fig. 4.3, it is possible for the pulse width of the square waveform (D) to differ from the modulation index value (m) according to D = m L − m L.

Fig. 5.34 The ac and dc components of the resulted voltage using symmetric PSC modulation. © 2023 IEEE. Reprinted, with permission, from [71, 72]

(5.29)

Modulation

Output Voltage

Vm

178

5 Novel Topologies and/or Techniques for Emerging Applications

Consequently, the amplitudes of the positive pulse (V p+ ) and negative pulse (V P− ) are  V P+ = (1 − D)Vm (5.30) V P− = −DVm In Fig. 5.33, the HFT provides galvanic isolation, allowing the alternating term of the string voltage, to be fed to an isolated load. The full-bridge rectifier only conducts the pulses with the larger amplitude, charging capacitor Cdc2 , and blocking the other pulses. When the diode bridge is not conducting, the capacitor Cdc2 discharges into the load. According to (5.30), if D  0.5, the positive pulse is larger, and if D > 0.5, the negative pulse is larger. Hence, ignoring parasitics, the average voltage at the load terminal is given by

Vdc2

⎧   ⎨(1 − D)Vm N2 0 < D  0.5 ∼  N1 , = 0.5 < D < 1 ⎩ DVm N2 N1

(5.31)

  where NN21 is the transformer ratio [71, 72]. (Vdc2 /Vm ) in According to (5.31), the ratio of Vdc2 to thevoltage  of one  module  an isolated port is a linear function for 0.5 × NN21 to 1 × NN21 , and the curve is symmetric with respect to the line of D = 0.5. This means that Vdc2 at D = 0.35 equals Vdc2 at D = 0.65. However, due to resistive elements and leakage inductances, non-linearities increase as D deviates from 0.5, so a more practical operating range for D is between 0.25 and 0.75. Additionally, The average amplitude of current for the conducting switches in the diode-bridge can be determined using Id ∼ =

Pload2 . Vdc2 min (D, 1 − D)

(5.32)

According to (5.32), when D → 0 or D → 1, the peak current becomes infinitely large, as shown in (5.32). This can potentially cause damage to the diode-bridge due to overload and result in transformer saturation. Therefore, it is important to avoid duty cycles that are too close to zero or one. All the previous equations assume that the equivalent series inductance of the highfrequency transformer is negligible. Considering the system parasitic inductance, the analysis holds for D  0.5 as long as L eq,p
0.5, the analysis is accurate as long as L eq,p
(L − 1)/NC or m < (NC − L + 1) /NC , then there are instances where all carriers are respectively below or above m (as indicated in Fig. 5.35), which results in either all modules being in series with a maximum voltage of L Vm or all modules being bypassed with a minimum voltage of 0. The highest and lowest voltage levels can be determined using Fig. 5.35 during other conditions. Hence, the general relation between Vmax and Vmin can be expressed as ⎞

⎛

Vmax = min ⎝  L , NC − (1 − m)NC ⎠ Vm ,

 Condition I

(5.35)

Conditions II and III

⎛

⎞

Vmin = max ⎝ L−N C + m NC ,

 Conditions I and II

⎠ Vm . 0 

(5.36)

Condition III

Knowing Vmax , Vmin , and Vdc , the amplitude of positive and negative pulses after Cdc2 removes the dc term of the string voltage can be calulcated per

5.1 Modular Reconfigurable Systems in Electromobility

V p+ =

181

 (NC − (1 − m)NC  − m L) Vm , m < L/NC (1 − m)L Vm , m  L/NC

(5.37)

and  V p− =

, m  (NC − L) /NC m L Vm (NC − m NC  − (1 − m)L) Vm , m > (NC − L) /NC

(5.38)

With V p+ and V p− , it is possible to estimate the output gain per   Vdc2 ∼ = max V p+ , V p−



N2 N1

 .

(5.39)

The diode-bridge only conducts when the amplitude of the voltage step is at its peak, charging Cdc3 in the process. At other times, the capacitor (Cdc3 ) supplies energy to the load. To determine the current and transformer requirements, one must also consider the effective duty cycle (Deff ), which differs from the value in (5.29) and follows Deff =

t . Tsw,eff

(5.40)

The value of t represents the total time during which the diode-bridge conducts, and the value of Tsw corresponds to the switching cycle of a single module. However, if the PSC modulation is symmetric, then the effective duty cycle is equal to the duty cycle, i.e., Deff = D. The total time during which the diode-bridge conducts in an asymmetric PSC modulation is calculated as t =

⎧ ⎨

n p DTsw,eff +  p , V p+ > V p− n p DTsw,eff +  p + n n (1 − D)Tsw,eff + n , V p+ = V p− . ⎩ n n (1 − D)Tsw,eff + n , V p+ < V p−

(5.41)

To calculate the total duration of conduction of the diode-bridge, we first calculate the number of positive pulses n p , the duty cycle D of each positive pulse, and the interval  p during which m is above all carriers. This is done using Figs. 5.35 and 5.36. Similarly, we calculate the number of negative pulses n n , the duty cycle of each negative pulse, and the interval n during which m is below all carriers. Finally, we calculate the effective switching cycle Tsw,eff = Tsw /NC . Based on the general pattern of the carriers illustrated in Fig. 5.35, the count of positive and negative pulses are  np = and

, m < L/NC  L − m  NC  , 1 m + NC (L − 1) , m  L/NC

(5.42)

182

5 Novel Topologies and/or Techniques for Emerging Applications

   − m − N1C (L − 1) , m  (NC − L) /NC nn = . L − (1 − m)NC  , m > (NC − L) /NC

(5.43)

Using basic geometric principles, it is possible to determine  p and n as functions of m, which follows  0 , m < (L)/NC p = , (5.44) (m NC − L + 1) Tsw,eff , m  (L)/NC

n =

 (m NC − L + 1) Tsw,eff , m < (NC − L) /NC . 0 , m  (NC − L) /NC

(5.45)

After determining the effective duty cycle, the average current of the diode-bridge switches depending on the rated power of the port is Id >

Pload2 . Vdc2 Deff

(5.46)

The analysis presented for the asymmetric PSC holds true under similar conditions as for the symmetric PSC, that is when the equivalent series inductance (L es ) at the port terminals is much smaller than the load resistance. While it is not possible to calculate a precise set of generic boundary conditions, the inequality L es
V p− . In case of V p+ < V p− a similar relation can be checked following L es
f n−1,min > (10. . .20) f n−2,max > · · · · · · > (10. . .20) f 2,max > f 2,min > (10. . .20) f 1,max ,

(5.54)

where n is the number of coupled outputs. Nevertheless, as the outputs are connected to the same string, the controller loops must also be decoupled from one another or have different response speeds, i.e., the higher frequency outputs require faster responses (inner loops), and the lower

196

5 Novel Topologies and/or Techniques for Emerging Applications

Fig. 5.53 Intuitive representation of a multi-port system with a main load and multiple secondary loads

Port k Port 1

Port j

frequency outputs must be considerably slower (outer loops) to avoid fluctuations. Such a scheme can complicate developing an effective controller and even restrict the operation bandwidth due to interference from many control loops. Previous sections demonstrated the advantages of evenly distributed carriers for a string, which is still the case for a single arm/string connected to one ac output. For multi-port strings, as Fig. 5.53 shows, the highest-voltage load/port gets the complete string with evenly distributed carriers (symmetric PSC), and the other ports use the sections of this string, which can have evenly distributed carriers (symmetric PSC) or not. To this point, the main assumption was that at least one port is connected to the complete length of the string. However, in multi-port applications, particularly in ac applications, multiple decoupled ports can also exist, and Fig. 5.54 depicts such a structure graphically. This is particularly the case in multi-phase systems with balanced isolated loads/sources, such as electrical machines in EV applications. All the previously discussed analysis holds for individual ports and their corresponding carriers/modules. In the simplest case, all the modules can be considered as one string, and the phase shifts be determined per ϕ j = ( j)

2π , NC

(5.55)

5.1 Modular Reconfigurable Systems in Electromobility

197

Port k

Port j

Port 1

Fig. 5.54 Intuitive representation of a string with multiple decoupled ports

where NC is the total number of modules or carriers, and j represents the order of modules in the string from bottom to top. the phase shifts of the   Consequently, 2π 4π carriers corresponding to the first port are NC , NC . . . which does not result in a symmetric PSC. To achieve an even distribution of phase shifts among carriers of each port, the , where L k is the number phase shifts among each consecutive module should be 2π Lk of modules in Port k. As long as the ports do not share any modules, the phase shifts of carriers in each port can be assigned independently. There is no specific limitation on the phase difference of the carriers corresponding to different ports, and such a phase difference does not affect the quality of the output in each port. For example, Figs. 5.55 and 5.56 show two cases of carrier order for a system with three phases and three modules in each phase. However, to achieve the best balancing and efficiency performance in modules with parallel connectivity, the carrier’s phase shifts in the whole string can be defined per  ϕ0k, j where k is the port number [57].

=

NC j +k L



2π . NC

(5.56)

198

5 Novel Topologies and/or Techniques for Emerging Applications

Phase 1

Phase 3

Phase 2

Carriers 1

0

time

Fig. 5.55 Phase-shift distribution with zero phase difference between corresponding carriers of different ports

Phase 1

Phase 3

Phase 2

Carriers 1

0

time

Fig. 5.56 Optimal phase-shift distribution in a three-port system with three modules in each port

In both cases, the output quality of each phase is relatively similar. However, another degree of control is still available: controlling the phase shifts among cascaded strings of modules. The average total string voltage for any balance multi-phase system is zero during one fundamental cycle. However, depending on the modulation indices, the carrier phase shifts, and the number of modules, the instantaneous value of string voltage can fluctuate between −Nph Vm  Vtotal (t) =

Nph 

Vph,k (t)  Nph Vm ,

(5.57)

k=1

where Nph is the number of phases/ports, and Vph,k (t) is the instantaneous voltage of kth port. It is possible to control the phase shift of the carriers in a way that the instantaneous voltage is also constantly zero. Thus, the top and bottom points of the string would constantly be at the same potential, i.e., the two points can be assumed virtually

5.1 Modular Reconfigurable Systems in Electromobility

199

connected. This is achieved by complementary aligning voltage steps’ positive and negative edges throughout the string. For simplicity, a three-phase three-module system help to clarify the edge-aligning concept, and then the concept is extended for multiple phases with multiple modules. Consider three distinctive carriers C1 , C2 , and C3 with arbitrary modulation references m 1 , m 2 , and m 3 . Each modulation index is compared with its corresponding carrier. The output voltage of each corresponding module is positive when m j > C j , zero when −C j < m j < C j , and negative when m j < −C j . As long as the positive and negative edges of two pulses match, no variation is observed in the total voltage of the string. Figure 5.57 graphically shows how the phase shifts of three carriers, each corresponding to separate phases, can be controlled to achieve a zero equivalent voltage. If AC is the maximum amplitude of the jth carrier with the initial phase-shift of φ j0 , the rising and falling edges of the resulted pulse from a modulation index of m j is ⎧ ⎨ϕrise = φ j0 + π(1 − ⎩

ϕfall = φ j0 + π(1 +

mj AC

),

mj AC

),

(5.58)

where the shape of the carrier is shown in Fig. 5.58.

Fig. 5.57 Illustration of aligning the pulse edges with zero equivalent voltage

Carriers AC

C1

C2 m1 m2 time m3

−AC

−C3

Vout1

time

Vout2

time

Vout3

time

Vtotal

time

200

5 Novel Topologies and/or Techniques for Emerging Applications

Fig. 5.58 The shape of the triangular carrier and its modulation index

Rising Edge

Carriers

Falling Edge

AC mj φj0

φj0+2π

Vpulse

With an equal number of modules in each port, the phase shifts of the carriers corresponding to the same modules in each phase are regulated sequentially. The required variation in the initial phase-shift of the jth module in the kth port so that its resulted voltage pulse cancels the resulted voltage of the jth module in the (k − 1)th port is (ϕ)k, j and is calculated recursively following   m k, j − m (k−1), j (ϕ)k, j = 2 − π + ϕ0(k−1), j − ϕ0k, j + δϕ(k−1), j , AC

(5.59)

where ϕ0(k−1), j is the initial phase-shift of the jth carrier in the (k)th per (5.56) and (ϕ)1, j = 0. Therefore, the final phase-shift of the jth module in the kth port is ϕk, j = ϕ0k, j + (ϕ)k, j

(5.60)

Using (5.60), in effect the falling(/rising) edge of the jth module of one port matches the rising(/falling) edge of the jth module in the previous port and cancel each other. Normally, the initial phase shifts of carriers within each phase/port are fixed (2π/L for L modules per port). Therefore, calculating (ϕ)k, j for only the first carriers of each port is sufficient, and (5.60) simplifies to ϕk, j = ϕ0k, j + (ϕ)k,1 .

(5.61)

Therefore, total string voltage can also be kept zero at all instances by actively regulating the corresponding pulses of all the first carriers to have a zero voltage summation. Figure 5.57 shows this concept for a three-phase system. The above analysis also holds for the polygon structure and can help to reduce the size of the required inductors to limit surge currents. However, further considerations would be necessary, which are not the focus of this work.

5.1 Modular Reconfigurable Systems in Electromobility

201

Alternatively, the phase shift between the first carriers of each port can be used to generate another output voltage. In the example of the three-phase system with single modules per phase/port, summing the calculated phase shift from (5.61) with an additional phase-shift function (θ) per (ϕ)k, j

  m k, j − m (k−1), j π + ϕ0(k−1), j − ϕ0k, j + δϕ(k−1), j + f (θk ), = 2− AC (5.62)

can create an ac pulse as depicted in Fig. 5.59. For example, the function to control the added phase difference can follow f (θ) ≈ sgn (m k (t)) θ,

(5.63)

that results in generating 2(Nph L) in each switching cycle as long as the value of θ is not extremely large that the created pulses cancel each other. Additionally, the width of each pulse is Wp = θ

Tsw . 2π

(5.64)

The resulting ac voltage of the string can also be rectified to generate an additional dc output in the multi-phase system.

Fig. 5.59 Example of controlling the phase difference between the first carriers of every port to generate additional outputs

Carriers AC

C1

C2 m1 m2 time m3

−AC Vout1

θ×Tsw /2π

−C3 time

Vout2

time

Vout3

time

Vtotal

time

202

5 Novel Topologies and/or Techniques for Emerging Applications

Figure 5.60 illustrates the macro topology of a single-string multi-port system with the integrated additional output. As the width of the generated pulses depends on the f (θ), regulating θ can easily control the average (in case of a dc output) or RMS (in case of an ac output). The concept can be further expanded into generating multiple phases with multiple additional integrated outputs as Fig. 5.61 depicts.

Fig. 5.60 Macro structure of the additional dc output in the single-string multi-phase system

Port k

Vdc2

Cdc3

Port j

load Auxiliary Port

Port 1

#(2N)

#(N)

Phase2

#(2+N)

#(2)

Phase1

#(1+N)

#(1)

Phase M

#(MN)

(2+(M-1)N)

(1+(M-1)N)

Phase M+1

#(N)

#(2)

#(1)

Phase M+2

#(2N)

#(2+N)

#(1+N)

Phase 2M 2M

AC outputs

Relay 3

Relay 1

#(MN)

(2+(M-1)N)

(1+(M-1)N)

Relay 2

Charging Connector

Integrated output 1

Integrated output 2

5.1 Modular Reconfigurable Systems in Electromobility 203

Fig. 5.61 Extended macro structure of multi-phase ac smart battery with multiple integrated auxiliary outputs for electromobility applications (modified from [12])

204

5 Novel Topologies and/or Techniques for Emerging Applications

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Chapter 6

Monitoring Methods

This book chapter focuses on reducing the complexity of the monitoring circuit for modular reconfigurable power electronics by utilizing the available degrees of freedom and information. Newer topologies are often limited by the need for an expensive and complex monitoring subsystem, which makes them impractical for cost-sensitive applications or those that require additional sensor information for safety, such as electric mobility systems. To address this issue, the chapter presents a compensated model that considers the effects of balancing and parallel connectivity for half-bridge and diode-clamped half-bridge systems. The chapter also introduces a sampling compensation technique to improve accuracy in low sampling rates and small balancing efforts scenarios. Furthermore, the chapter extends the models to an MMS, where the internal resistances and open-circuit voltages of each module are estimated using a consecutive sampling concept and a general estimator. What sets this approach apart is that only measurements at the output terminal of the system and module connections are required, which are typically available in systemlevel controllers. This chapter is a valuable resource for researchers, engineers, and professionals in the field who are interested in reducing the complexity of monitoring circuits for modular reconfigurable power electronics, particularly in electric mobility systems. The techniques presented in this chapter have the potential to make these systems more cost-effective and safer. Collaboration with Mr. Tomas Kacetl, Dr. Bita Arabsalmanabadi, and Dr. Jingyang Fang has contributed to the practical implementation of the monitoring technique and comparison with the state-of-the-art. Multiple bachelor and master students have also collaborated in developing this chapter while serving as their advisor [1–8]. Publications from these collaborations are cited to acknowledge their support and help throughout the chapter.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1_6

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6.1 Intro The practical advantages of MMS and modular power electronics make them predominantly valuable in medium to high-voltage applications such as HVDC, grid storage, and distributed generation [9–14]. Although there are many benefits to using modular power electronics, there are still issues that need to be addressed, including voltage balancing, safety, and module monitoring [15–18]. An imbalance in modules can occur due to parameter variation, parasitic effects, discretization delay, or uneven utilization leading to aging of the modules, which can ultimately result in the failure of the entire system [15]. We have already studied the balancing of modules which revolves around two approaches. One method for addressing voltage imbalances in MMC and MMS systems involves implementing sorting algorithms and continuously monitoring the system’s modules, either through direct measurement or estimators [19–22]. Direct measurement for monitoring the modules requires multiple sensors per module and high-bandwidth data communications, increasing the cost and complexity of the system [23, 24]. Another approach involves changing the macro and micro topologies to introduce charge equalization paths among the modules autonomously [23, 25–27]. These topology adaptations are capable of solving some of the main obstacles for the expansion of the MMCs and MMSs in general1 [28]. However, such modification will not make monitoring irrelevant but rather reduce its priority [29, 30]. In conventional topologies, to ensure the safety of storage modules, nonstop tracking of the system states is an indisputable necessity [31–34]. Moreover, the cells’ inherent parameter spread, different environmental conditions, and different aging speeds can lead to charge imbalance across the modules and deteriorated system performance [35–37]. Hence, it is crucial to have continuous monitoring of the modules to ensure that the system operates in a balanced, stable, and safe manner [21, 38]. Additionally, although topologies with self-balancing can achieve open-loop operation, good knowledge of the modules’ voltages for system monitoring and protection functions still improves operation in some applications or is mandatory in more critical others. However, higher safety or improved performance should not be at the cost of additional sensors, the higher bandwidth requirement for the communication channels, or larger capacitances. On the other hand, an estimator can perform such a task while keeping the costs and system complexity to a minimum, provided sufficiently accurate system models are available [39]. An estimator in a conventional energy storage system is typically used for states or parameters that are generally unavailable, or unmeasurable [40–43]. The goal of sensor reduction is usually not discussed. However, the concept of the estimators in modular power electronics, particularly in MMCs, focuses more on reducing the number of required sensors on the module level or providing an extra level of verification in case of sensor fault or bias [44–47]. The concept of reduced sensor estimation for MMCs can be also further expanded for other energy storages [17, 48, 49]. This chapter focuses on developing estimation techniques for modular 1

See Chap. 3 for more detail about the macro and micro structures of such self-balancing systems.

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multilevel or reconfigurable storages without any direct measurement at the terminal of the modules for conventional HB topology as well as more advanced structures. The presented methods can be divided into two general groups: • methods that estimate the terminal voltage of the modules (more suitable for capacitor- or SC-based modules), • methods that estimate the internal parameters of the ECMs (more suitable for batteries).

6.2 Terminal Voltage Estimation Techniques The methods that estimate the terminal voltage of the modules can be divided into two categories, • methods based on equivalent arm voltage update the vector of the module voltages gradually based on the measured arm voltage and knowledge of the connected modules at each instance • methods based on decoupling of parameters update the modules’ parameters by monitoring the voltage of the arm before and after a change in operation The method based on incremental updating of the vector of modules’ voltages requires a lower sampling frequency. However, it is more sensitive to the behavior of each storage and the modeling error. Hence, this method suits storage types with relatively simpler models and a more linear behavior, such as capacitors. On the other hand, the method based on decoupling modules’ parameters requires exact sampling instances before and after each variation in the operation and is more sensitive to switching noises. This section studies the general principles of the method based on the arm voltage, and the next section will cover methods based on the decoupling technique. Recent research studies focus on reducing direct measurement at the module level for capacitive modules by employing state observers to estimate their voltage [44, 47]. Different methods have been implemented to estimate the voltage of modules with capacitors, which include recursive techniques such as least-squares and model-based estimators like Kalman filters (KFs) and machine learning methods [46, 50–52].

6.2.1 Modules Without Parallel Connectivity Initially, modules without parallel connectivity are considered. The output voltage of the arm based on the module voltages and their states is

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Varm =

N 

Vm j S j = Vm T S,

(6.1)

j=1

where V m is the vector of module voltages neglecting the voltage drop across the resistive elements in the arm and S is the vector of the module states in the arm with S j representing its jth element following ⎧ ⎨ 1 , positive-series connection , bypass connection Sj = 0 ⎩ −1 , negative-series connection

(6.2)

Considering capacitors as the energy storage type, the dynamics of the capacitor voltage of an inserted module follow i arm V˙m j = S j , Cj

(6.3)

where C j is the capacitance of the jth module in the arm. Applying the forward Euler discretization leads to + V˙m(k−1) Ts , Vm(k)j = Vm(k−1) j j

(6.4)

where Ts is the sampling period. Substituting the dynamic equation of the caps in (6.4) results in + S (k−1) Vm(k)j = Vm(k−1) j j

Ts (k−1) i , C j arm

(6.5)

and the arm voltage can be written as Vm (k) = Vm (k−1) + ST (k−1) I

Ts (k−1) i C arm

(6.6)

T  (k) (k) (k) where the vector V (k) is the vector of the modules’ voltm = Vm 1 , Vm 2 , . . . , Vm N C

ages, S(k−1) is a vector containing the switching signals of the modules (S (k−1) ), I j is the identity matrix, and the vector TCs is a fixed vector which can be written as  Ts Ts Ts Ts T = , ,..., , C C1 C2 CN

(6.7)

and can be precalculated. Additionally, the CTsj vector turns into a constant coefficient, if all the capacitances are identical.

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Hence the average state-space model of the module voltages follows (k−1) + w(k) , Vm (k) = Ass Vm (k−1) + Bss i arm

(6.8)

(k) Varm = C ss Vm (k) + v (k)

(6.9)

where the state matrices are Ass = I, B ss = S T (k−1) I CTsu , C ss = S(k) , and Dss = 0. Additionally, w(k) and v (k) are the modeling and measurement noises, respectively. Having the state-space model of the battery we can use any iterative algorithm (such as ADALINE [53], KF [17, 54], or sliding-mode [55]) to solve it. The general form of the iterative method is

 W (k) = W (k−1) + αS(k) y − yˆ ,

(6.10)

where α is the learning rate, and (k − 1) and k respectively denote the previous and present samples. Also, yˆ is the calculated output arm voltage based on the previous estimations at (k − 1) and the current module connections. Similarly, y is the measured arm voltage at sample time k.

6.2.2 Modules with Parallel Connectivity In the next step, we develop a compensated model for the diode-clamped HB module as the simplest topology with parallel connectivity. The concept can be extended to more complex modules. The general procedure for modules capable of a parallel connection remains similar. The general behavior of the diode-clamped MMC is similar to their conventional counterparts as we studied in Chaps. 3 and 4. However, the clamping branches and non-uniform parameter distributions, such as capacitances and leakage currents, make it challenging to derive a complete model for the diode-clamped MMC that is accurate for the inter-dynamics of the system. As a result, numerical solutions become the only viable option. Furthermore, available analytical simplifications for conventional MMCs are not accurate due to the impact of balancing modulation and the clamping branch. To overcome this, we expand the conventional MMC model by considering both clamping as well as balancing efforts and then use an optimal estimator such as KF to verify the applicability of the model by estimating the voltage of each module [56]. With adequate sampling frequencies, (6.9) and (6.8) partially take into account the impact of balancing on individual modules (e.g., level adjustment as in [57], the effect of conduction time as in [58], and influence of switching delays as in [29]). This leads to an increase in the voltage of the bottom modules in the arm and a decrease in the voltage of the top modules. This effect mainly occurs because any balancing

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routine directly influences the S(k) vector. However, the model is only adequate when considering the clamping branch’s impact on energy exchange among modules, as discussed in [56]. Each module is connected to the previous and the next modules via two clamping branches, with the exception of the first and last modules. The clamping branch connected to the previous module can only discharge it, while the one connected to the next module can only charge it. The clamping branch behaves as a simple series LC circuit when the lower module is bypassed, hence the effect of energy exchange between the modules can be included by studying the average voltage across the inductor according tot he module states. By rewriting (6.4) and taking into account the influence of these two clamping branches, we obtain: Vm(k)j = 1 − b T





b j 1 − S (k−1) + b( j+1) 1 − S((k−1) Vm(k−1) j j+1) j



b( j+1) Ts (k−1) (k−1) (k−1) 1 − S (k−1) V 1 − S V + c( j−1) c( j+1) j ( j+1) 2L j C j

Ts 2L jCj

+ 2Ljj Cs j

+ CTsj

(6.11)

(k−1) S (k−1) i arm , j

where S j = S j1 is the upper switch state which is one when it is conducting and zero when it is blocking, and b j is a function based on the switching frequency and modulation reference  (1 − m x + δx, j )Tsw , V( j+1) > V j (6.12) bj = 0, V( j+1)  V j , that computes the average duration during which the clamping path remains forwardbiased. Here, m x is the modulation amplitude of the arm/string, and δx, j is the balancing effort in Module j [56]. As a result, the extended state-space model can be reformulated as 





(k−1) + w(k) , Vm (k) = Ass Vm (k−1) + Bss i arm

(6.13)

(k) varm = C ss Vm (k) + v (k) ,

(6.14) 

where a pq ∈ Ass is the element in the pth row and the qth column of Ass . Except the  first and last module, the value of a pq for all q and p values (i.e., ∀ p, q| p = 1, NC ) is ⎧  b p Ts

(k−1) ⎪ 1 − S , q = p−1 ⎪ p 2L C ⎪ p p

⎪ (k−1) (k−1) ⎪ Ts b p 1−S p Ts b( p+1) 1−S( p+1) ⎨  − , q=p 2L p C p 2L p C p a pq = 1 − (6.15) ⎪ b( p+1) Ts (k−1) ⎪ 1 − S , q = p + 1 ⎪ ( p+1) ⎪ 2L p C p ⎪ ⎩ 0, else

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For p = 1 and ∀q ∈ (1, . . . , N ), the value of a pq is



a1q =

⎧ ⎪ ⎪ ⎨1 − ⎪ ⎪ ⎩



Ts b( p+1) 2L q C q Ts b( p+1) 1 2L p C p

1 − S((k−1) p+1) ,

− S((k−1) p+1) , 0.

q=1 q=2 else

(6.16)





Also, the value of a pq for p = N and ∀q ∈ (1, . . . , N ), a N q follows



a NC q =

⎧ ⎪ ⎨ ⎪ ⎩

1

 Ts b p

1 − S (k−1) , p 2L p C p  Ts b p

(k−1) − 2L p C p 1 − S p , 0.

q = N −1 q=N else

(6.17)

In the case of fast dynamics or severely imbalanced systems, the hardware constraints can prevent sufficiently large sampling rates. Hence, if the sampling frequency is low or sampling is not synchronized, the small balancing efforts can go unnoticed, which leads to an increased error [56]. The average of the modulation index for each module in one cycle of the phase voltage follows m x, j =

1 − δx, j . 2

(6.18)

Ideally, this should represent the average value of S j (t) in one cycle for the xth arm. However, factors such as low sampling frequencies, significant measurement delays, or asynchronous sampling (i.e., one state of a module is observed more frequently than the other) may cause the average of the discrete values of S (k) j to have a difference from m x, j . the average of the discrete values of S (k) is j Sj =

k− f s 1  S j1 (z), f s z=k

(6.19)

The existence of a disparity between S j and m x, j means the balancing effort is not accurately considered in the model [56]. To counteract the negative impact of sampling, an additional term can be intro duced to the model by defining a compensated state vector (S ) as follows S

(k)

= S(k) − (S − m x ).

(6.20)

In (6.20), S represents the vector of averaged switch states over one fundamental cycle. This vector is continually updated using a sliding window approach for each iteration. m x is the vector of the expected modulation index, which can be easily

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Table 6.1 KF for estimating the module voltages of the MMC © 2023 IEEE. Reprinted, with permission, from [56] STEPS (k−1) , P (0) +, Q, R Vˆm

STEP 0

Initialization

STEP 1

Projection

V m = Ass Vm (k−1)+ + B ss i arm P (k)− = P (k−1)+ + Q

STEP 2

Calculate KF gain

K (k) g =

STEP 3

Correction

 P (k)+ = I − K g (k) C ss P (k)−

STEP 4

Return to STEP 1

Vm



(k)−

(k)+

(k−1)

P (k)− C ss T C ss P (k)− C ss T +R

, P (k)+ =⇒ Vm (k)+ , P (k)+

calculated for each module by calculating the average of the modulation index in one fundamental cycle. Substituting S (k) in (6.9) and (6.8) or in (6.13) and (6.14) results in a model that can consider the balancing efforts more accurately or achieve a similar accuracy at lower sampling rates [56]. Having an accurate model of the arm for the diode-clamped MMCs, the process for updating the vector of the modules’ voltages is using (6.10). As an example, the procedure to estimate the module voltages using KF is provided in the following [56]. In the final step, an estimation algorithm is incorporated with the extended statespace model to estimate the voltages of the modules, as discussed in [50]. An optimal estimator such as KF can be used to evaluate the performance of the developed model. The pseudo-code for the KF algorithm to estimate module voltages in the arm is provided in Table 6.1. Nevertheless, other state-of-the-art estimators can also be employed with the models as needed. The main purpose of the KF is to offer a quantitative comparison between the conventional and compensated models, as discussed in [56]. In many power electronics systems, measurement noise and parameter imbalances often lack uniform distributions. As a result, it is crucial to heuristically define the initial covariance matrix ( P) for the KF [59]. Typically, the measurement noise (R) and modeling error ( Q) are assumed to be independent for each module and from one another [60]. Consequently, Q is defined as a diagonal matrix and R as a scalar value, with initial values set heuristically. Understanding the impact of each parameter on the estimator’s behavior is advantageous at the beginning of our analysis. Increasing the value of Q results in faster convergence and divergence prevention, though it may also lead to increased fluctuations. Conversely, reducing the value of Q diminishes estimation ripples but slows convergence and increases error. Noise sensitivity can be mitigated by augmenting R, albeit at the expense of slower dynamics [56]. A comparison between the developed model and the conventional one reveals  that the matrix Ass is no longer diagonal. However, it is unnecessary to form the  complete Ass for STEP 1 in order to perform matrix multiplications. Instead, the projected voltage of each module in STEP 1 can be calculated using basic scalar mathematics, starting with the first module.

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217

The developed approach formulates the estimator so that each state equation contains a maximum of three state variables, and the entire state-space model comprises only one output variable. Moreover, calculations related to the output equation involve straightforward scalar computations, making them computationally less demanding for online implementation in large systems [56]. The presented approach considers the balancing routine, and the influence of the clamping branch on the voltages, and provides a technique to compensate for the low sampling rates, which other methods neglect. Furthermore, the performance is superior, particularly in cases of imbalance. The developed method requires only one voltage sensor per arm instead of one per module, which is on par with other state-of-the-art methods. Additionally, the compensation method for lower sampling frequency can noticeably reduce the estimation error [56].

6.2.3 Simulation and Experimental Verification A single-phase model featuring 16 modules and 14 clamping branches is employed to demonstrate the feasibility of the extended model and estimator, as well as to study the system’s general behavior. Additionally, a scaled prototype serves as a proof of concept in an experimental setup. The parameters of both the simulation and experimental systems can be found in Table 6.2.

Table 6.2 Parameters for simulation and experimental systems © 2023 IEEE. Reprinted, with permission, from [56] Circuit parameters Simulation Experiment Rated power Load inductance Module rated voltage DC-link voltage Number of SMs Arm inductance Arm resistance Carrier frequency Sampling frequency Output frequency Modules Modulation index (m) Modules

Capacitance Capacitor’s resistance Inductance Resistance

1.14 MW 0.1 mH 1.2 kV 9.6 kV 16 5 mH 50 m 2 kHz 10 kHz 50 Hz 6 mF 2 m 0.95 10 µF 0.5 m

2 kW 0.1 mH 45 V 230 V 10 2 mH 20 m 2 kHz 10 kHz 50 Hz 2.5 mF 2 m 0.95–0.75 1 µF 0.5 m

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6 Monitoring Methods

Fig. 6.1 Estimation results of the capacitor voltages in the simulated balanced system © 2023 IEEE. Reprinted, with permission, from [56]

The specifications of the SEMiX854GB176HDs power modules2 from Semikron are utilized for modeling the semiconductors in the simulations. Each module operates at a switching frequency of 2 kHz, while the amplitude of the modulation reference varies within a range of 0.50–0.95. Furthermore, the sampling frequency of the KF and the sampling rate for both the simulations and the experimental setup are set at 10 kHz. Simulation Studies Simulations help to study the behavior of the developed estimators under balanced conditions with identical modules and imbalanced conditions with mismatches in the module capacitances and self-discharging rates. In the second case, the selfdischarges of Modules 2, 4, and 8 are increased, where the bottom module in the arm has the highest discharge to simulate a worst-case scenario [56]. Figures 6.1 and 6.2 show the results of the KFs based on the developed state-space model as well as the conventional model of MMCs per [50]. In Fig. 6.1, the exact value of the module voltages are marked in yellow, the results obtained using the conventional model are shown in blue, and the results derived from the extended method are displayed in red. The KF parameters for both estimators are largely identical. Estimation results confirm the stability of both models. Furthermore, even 2

For more information, please see Link, accessed on 22.10.2022.

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219

Fig. 6.2 Maximum error in the simulated balanced system using conventional and developed estimators © 2023 IEEE. Reprinted, with permission, from [56] Fig. 6.3 Estimation results of the capacitor voltages in the simulated balanced system without any balancing effort © 2023 IEEE. Reprinted, with permission, from [56]

in a completely balanced system, the modified state-space model converges with slightly lower absolute errors than the conventional model. As illustrated in Fig. 6.2, the maximum error for the proposed estimator in an ideal system is below 0.5%. Figures 6.3 and 6.4 depict the behavior of the estimator in a heavily imbalanced system with x = 0. Due to the imbalance and absence of balancing efforts, the voltages begin to diverge. Figure 6.3 shows both the measured and estimated voltages. Similar to the previous case, both estimators converge; however, the extended model follows the measured voltages more closely. Figure 6.4 demonstrates a greater than

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Fig. 6.4 Maximum error in the simulated imbalanced system using conventional and developed estimators without any balancing effort © 2023 IEEE. Reprinted, with permission, from [56]

50% reduction in the estimation error in comparison to the conventional dual-arm MMS model, in addition to a decrease in the amplitude of the error fluctuations [56]. The third scenario explores the behavior of the models in an imbalanced system where a non-zero level adjustment is applied, i.e., the modules are actively forced to a balanced state (in this case, x = 0.02). Figure 6.5 displays the profile of the measured and estimated module voltages in one arm. Despite the capacitance mismatches and varying discharge rates, the balancing technique can balance the modules with minimal balancing effort. As the modules start with completely imbalanced voltages, it takes about eight seconds for the voltages to fully converge to balanced states. However, it is also possible to increase the balancing speed using x values. One of the advantages of using an estimator is the active control of x to achieve faster or more efficient convergences [56]. Similar to previous scenarios, the estimator using the proposed model can track module voltages with significantly better accuracy. As shown in Fig. 6.6, the maximum instantaneous error is less than 10 V, which is an 80% reduction compared to the conventional model. This considerable increase in estimation error during a relatively small value of x highlights the conventional model’s sensitivity to the balancing effect. In contrast, the extended model’s accuracy is relatively stable and achieves similar results to the previous scenarios [56]. In larger systems, where the switching frequency is typically close to the fundamental voltage frequency. Hence, Fig. 6.7 compares the accuracy of the estimators when a low-frequency modulation ( f sw = 200 Hz) is employed and there is a step variation in the modulation index. The results show that the extended model can accurately monitor the voltages even at low switching frequencies, with errors remaining below 1%. Furthermore, if the modulation indices are reduced, the clamping branch will on average conduct for longer durations, which can affect the accuracy and cause larger fluctuations. To mitigate this effect, the extended model clearly offers better accuracy [56]. The extended and conventional models’ accuracies are plotted against the sampling frequency in Fig. 6.8. The modulation index has a significant impact on the estimator’s accuracy, so each point on the graph represents the average error for ten modulation indices, with x set to 0. As the sampling frequency decreases, the estimation error tends to increase. However, the extended model compensates for the decrease in sampling frequency and provides better results compared to the

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Fig. 6.5 Estimation results of the capacitor voltages in the simulated balanced system wit with x = 0.02 © 2023 IEEE. Reprinted, with permission, from [56]

3.9%

The modules are fully balanced

3.2%

0.55% 0.1%

Fig. 6.6 Maximum error in the simulated imbalanced system using conventional and developed estimators with x = 0.02 © 2023 IEEE. Reprinted, with permission, from [56]

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Switching frequency = 200 Hz

Modulation index is changed to 0.5

Fig. 6.7 Profile of maximum error with x = 0 for low-frequency © 2023 IEEE. Reprinted, with permission, from modulation [56]

Fig. 6.8 Profile of the average error with respect to the sampling frequency

Capacitors

Inductor 7th

Inductor 7th

7th

7thGeneric 6th

5th 4th switch-sets

3rd

2nd

1st

Fig. 6.9 Picture of the diode-clamped MMC prototype © 2023 IEEE. Reprinted, with permission, from [56]

conventional model. The difference between the two models becomes more significant as the value of x increases. Experimental validation A test setup consisting of a scaled-down diode-clamped MMC with ten modules is used to verify the estimator’s performance, as shown in Fig. 6.9. Each module in the setup is equipped with about 0.5 mF of low-Equivalent Series Resistance (ESR) ceramic capacitors in parallel with 2.2 mF electrolytic capacitors. The control and modulation functions are implemented using Labview in combination with an FPGA development board (National Instruments sbRIO 9627). Additionally, the voltages of the modules in the upper arm are independently monitored using an oscilloscope to evaluate the estimation accuracy. The measured and estimated voltages are then analyzed in MATLAB [56].

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Fig. 6.10 Measured and estimated arm voltage, as well as the error of the arm voltage estimation for a = 0 © 2023 IEEE. Reprinted, with permission, from [56]

Without the switching noises, the estimation error is T H3 , the term w11 |vest p | is added to both PR and PV to increase the agility of the estimator in tracking new

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233

(k) disturbances. Adding w11 |vest − v (k) p | term to P R and P V when the estimation has diverged from the measurement effectively increases the Q R and Q V . This approach has been shown to improve both the convergence speed and likelihood of the estimation. However, as the difference between the estimation and the measurement falls, the added bias decreases, reducing the sensitivity of the KFs to noise and minimizing oscillations after the estimator has converged. The adaptive learning rate, as described by [60], can further enhance the convergence speed of the estimator.

6.3.3 Sequential Estimation Procedure and Relevant Discussions In order to prevent the difficulties caused by high variability conditions when trying to estimate all DoFs simultaneously, the system divides the estimation process is performed sequentially suitable conditions. There are four different operating modes related to the output current. These four operating modes are • • • •

zero current, fast current variations, gradual current variations, constant current.

If there is no output current in the battery system for a considerable period of time, the battery’s internal chemical reactions will eventually balance out [75]. Measuring the battery’s terminal voltage directly can estimate the system’s open-circuit voltage [61]. Depending on the application, such a condition usually can occur a few times a day or not at all. For example, in an electromobility application, when the EV is parked for more than an hour, which can happen at night [76]. Under these circumstances, the controller can connect the modules in a sequence and measure the steady-state value of the terminal voltage once the storage has been idle. The pseudo-code for this operation is shown in Table 6.6. Although the presented estimation technique does not require this mode for convergence, it can still detect and correct any bias or additional offset resulting from the switching operation.

Table 6.6 Estimator for open-circuit voltages when modules are at equilibrium Estimation of Voc under idling conditions   →Voc = 0 · · · 0   →SU = 0 · · · 0 → for j = 1 to N 1. SU, j = 1 2. Voc = Voc .SU 3. SU, j = 0

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6 Monitoring Methods

The estimation of internal resistances is possible during the second and third modes, using changes in current as shown in (6.29). When the current fluctuates rapidly (e.g., at a rate of (0.1–1) C/s), the changes in the batteries’ SoCs are insignificant. For instance, for a current of 1 C, the rate of change in SoC is only 0.025%. On average, 0.025% variation in SoC leads to approximately 0.3 mV change in the opencircuit voltage. As a result, the open-circuit voltage remains stable (with a variation of less than 1 mV) within the sliding window, and any d V /di observed is simply due to the internal resistance of the batteries and switches. It is possible that there are some d V /didue to switching and measurement noises, but the effect of these noises can be mitigated through proper R R and RV selection. On the other hand, when there is a gradual current variation (i.e., variations that occur over several seconds) with a large dc component, it can alter the SoC and temperature of the storage modules, which can then impact the system’s output voltage and consequently affect the estimation results. Therefore, this scenario is not ideal for estimating the vector of resistances. Instead, the estimation of the open-circuit voltages can be revised in case of gradual current variations or if the current is constant. The threshold for distinguishing between gradual and rapid variations depends on the current and voltage sensors’ accuracy and noise rejection capabilities. The duration of the variation should be significantly longer than the primary time constant (usually in the range of a few milliseconds) of the battery while also being low enough to prevent changes in the SoC or open-circuit voltage [62, 77]. Thus, in this case, a threshold of one second has been chosen. If the current is stable before and after one second, the internal resistances are updated, otherwise, only the open-circuit voltages get updated. For other energy storage systems, similar hyperparameters should be determined based on their behavior, but the same reasoning can be applied to deduce suitable limits. The requirements for updating the internal resistance vector do not limit performing monitoring or prognosis functions and do not diminish the method’s applicability. Although the mode with slow or small current dynamics is not suitable for accurately estimating internal resistances, it can still identify anomalies and provide early warnings. Battery aging causes very gradual variations in the internal resistance (approximately 2% per month according to [78]), so a large fluctuation in the estimated resistance of a module over a short period or even sudden changes in the estimated open-circuit voltage when there is no noticeable change in the operating conditions of the system are indications of faulty operation or fault occurrence [79]. Fault detection is outside the focus of this work. However, it is considered interesting future work further to integrate the monitoring system into the reconfigurable storage control and exploit the available potential for higher performance. The internal resistance of a battery can change depending on the battery’s temperature and SoC. Nevertheless, the SoC variations are much slower than the estimator’s convergence rate [61]. In contrast, the impact of temperature on internal resistance is significant and can affect the convergence speed of the estimator. However, the internal resistance at a specific temperature, such as 20 ◦ C, can be obtained from a

6.3 Internal Resistance Estimation Techniques

235

look-up table or a nonlinear function available in the literature [80, 81]. The generation of these tables or functions is specific to each case and is not discussed in this book. The battery temperature in this study is maintained at room temperature.

6.3.4 Results The developed estimator’s robustness and precision are verified through three distinct scenarios, which are tested in both a simulation model and an experimental setup. Two simulation models are used, one for a low-power system that resembles the laboratory experimental setup, and the other for a high-power system that examines the estimator’s performance for higher ratings.

6.3.4.1

Simulation Results

The estimator’s performance and accuracy are assessed in two scenarios—during a balanced operation with similar parameters and during an imbalanced operation or with mismatched modules. The impact of the modulation index on the system’s accuracy is also studied. In Table 6.7, the primary parameters of the low- and highpower systems with seven half-bridge modules are presented. The parameters of the low-power system are designed to replicate the experimental setup. For the simulation, a simplified electrical equivalent circuit is utilized to model the batteries, which comprises an internal resistance, a constant DC voltage source, and a second-order RC circuit [62]. The second-order RC circuit is responsible for representing the battery modules’ dynamic response when the load changes. Throughout all simulations,

Table 6.7 Parameters of the simulation (Scenarios 1 and 3) and experimental (Scenario 2) setups © 2022 IEEE. Reprinted, with permission, from [17] Parameter Low-power setup High-power setup (Experimental and simulation) (Simulation) Vdc Cdc L dc Rldc Rload Rds Rd Voc,1−8 rbt,1−8 Scenario

30–40 V 5 mF 1 mH 0.05  5–40  1 m 1 m 7.6 V 0.18  1, 3

500–600 V 5 mF 1 mH 0.05  5–40  1 m 1 m 85–115 V 18 m 2

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Fig. 6.13 The estimation profiles of the OCV and internal resistance of batteries for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17]

random noises with a uniform distribution are incorporated into the output voltage and current, with an amplitude of ±0.2%. The first scenario’s estimation outcomes for the batteries’ OCV and internal resistance are illustrated in Fig. 6.13. Scenario 1 involves all modules possessing the same parameters. The initial estimates for the OCVs are 2 V, and for the internal resistances, they are 0.05 . After approximately 40 s, the estimation results for all seven modules converge to the correct values. The absolute errors, depicted in Fig. 6.14, demonstrate less than 0.5% error for the voltages and a maximum of 4.5% error for the resistances, which are well within the acceptable range. The oscillations around the convergence point are within a 0.2% range. Scenario 2 aims to examine how the estimator functions for high-power applications where the internal resistance of the batteries is substantially smaller, such as in EVs or large grid storages. Figure 6.15 displays the comparison between the estimations and true values for the resistances and voltages of all modules. Consequently, Fig. 6.16 illustrates the profile of the estimation error in this scenario. The estimator is able to determine the battery parameters in Scenario 2 with relatively similar errors. The estimation error for the resistances remains below 4%, and the highest error for the open-circuit voltages is shy of 0.5%, similar to the previous scenario. These results indicate that the estimator converges within 20 s. The convergence speed of the estimator can be significantly higher if the initial estimations are selected according to the rated values of a parameter. The third scenario aims to study how the Modulation index changes affect the behavior of the estimator. The graphs of the OCVs, internal resistances, and modulation index are presented in Fig. 6.17. The modulation index changes from 0.4 to 0.7 at t = 10 s and then increases to 0.9 at t = 20 s. The results indicate that the

6.3 Internal Resistance Estimation Techniques

237

Error less than 0.5 % at t = 100 sec

Error reduces to 3 % at t = 100 sec

Fig. 6.14 The difference between estimations and true values for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17]

Fig. 6.15 The diagram of the estimated parameters compared to true values for Simulation 2 © 2022 IEEE. Reprinted, with permission, from [17]

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Fig. 6.16 Errors between the estimation and true values in Scenario 2 © 2022 IEEE. Reprinted, with permission, from [17] Error goes below 0.5 % after 20 sec

Errormax = 4 %

Fig. 6.17 The estimated OCVs, estimated resistances, and profile of the modulation index for Simulation 3 © 2022 IEEE. Reprinted, with permission, from [17]

M

Errormax = 5 %

Modulation index is increased to 0.7

Modulation index is increased to 0.9

estimator gradually converges to the correct values despite the varying duty cycle. Furthermore, the speed of convergence slightly improves with each step, primarily due to the additional disturbances applied to the system by the modulation index changes that are crucial for decoupling the OCV and internal resistances from one another.

6.3 Internal Resistance Estimation Techniques

6.3.4.2

239

Experimental Results

The experimental setup consists of a proof-of-concept modular system with seven modules, which is illustrated in Fig. 6.18. The parameters of the experimental setup consisting of seven modules are the same as those listed in Table 6.7 for the low-power system. Each module has a Li-ion battery with a voltage ranging from 6.6 to 8.3 V. Each battery module contains two sets of series units with two parallel cells in each (2s2p). Moreover, each module includes a parallel capacitor consisting of a 2.2 mF electrolyte and roughly 500 µF ceramic types. The parallel capacitor acts as a low-pass filter and reduces the current ripples due to the switching action. The current measurement is conducted by a current clamp with a 5 mA resolution. Additionally, two series inductors act as the string inductance and form a low-pass filter with the dc-link capacitor. The true internal resistance profile of each battery module was obtained using the pulsed current method with multiple current amplitudes. This method involves applying a current pulse to the battery and measuring the resulting voltage drop across the battery. By varying the current amplitude and measuring the voltage drop, the internal resistance can be calculated for each current amplitude [49, 62, 82]. The control of the PSC is executed by sbRIO 9726 controller, which is an FPGA based rapid-prototyping controller. The system is subjected to various switching frequencies from 1 to 5 kHz, and the sampling rate of 100 kHz is selected to ensure about 20 samples per cycle. Each experiment lasts for 50 s, and at the beginning of each test, the estimator is initialized with inaccurate values to demonstrate its ability to converge to the correct ones. Similar to the simulation procedures, we assess the system’s performance under diverse circumstances, such as changing the switching frequencies, utilizing various modulation indices, and having modules with both closely and widely different parameters. The following tests are a sample of the acquired results. The current deviations higher than 0.1 A/s with durations shorter than one second are regarded as rapid changes and are used to update the resistances. Figure 6.19 illustrates the open-circuit voltages and internal resistances of all modules during standard operation, where there are no significant imbalances or mismatches among the modules. The modulation index of the modules is 0.5 and is maintained within the measurement process. Although there were no intended

Fig. 6.18 Picture of the developed testbench © 2022 IEEE. Reprinted, with permission, from [17]

L/2

Current Clamp

Battery Module

Vp,avg 7th L/2

6th

5th 4th 3rd 2nd Generic switch-sets

1st

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Fig. 6.19 Estimated and measured voltages and resistances of all seven modules for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17] Fig. 6.20 Estimated and measured output voltage of the pack for Scenario 1 © 2022 IEEE. Reprinted, with permission, from [17]

imbalances in the batteries and comparable modules were used, there were still minor innate differences among them. Despite this, the estimator manages to converge to the correct values for all seven modules. Furthermore, the open-circuit voltages converge quicker than the internal resistances, which take longer to converge. This is primarily because the resistance vector is more susceptible to noise and is updated less frequently. Figure 6.20 shows how the measured output voltage of the system changes over time and depicts the output voltage calculated using (6.44), which is updated as the estimator continues to correct its estimation of the modules’ true parameters. The small discrepancies observed between the measured and calculated voltage of the

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241

Fig. 6.21 Estimation errors for Scenario 1 of the experiments © 2022 IEEE. Reprinted, with permission, from [17]

Error < 1.5%

Errormax = 2.5%

system can be attributed to several factors, including measurement bias, switching noise, and dynamic differences that cause measurement distortion. Figure 6.21 illustrates the profile of the errors for the estimation of the voltage and resistance of the modules. The maximum difference between the true values and the estimated values of the open-circuit voltages is below 1.5%. Likewise, the estimation of the internal resistances has less than 5% error. It is difficult to determine the precise open-circuit voltage of a battery during operation. However, before and after the measurement with the modules at rest (no current), the terminal voltages of the batteries were measured after a resting period. In the second scenario, the performance of the estimator is evaluated when one module’s resistance is increased to simulate an aged battery. This is achieved by adding a series resistance to the 6th module. The system’s switching frequency is lowered to 1 kHz, and the modulation index is adjusted to 70% of the switching cycle. Figures 6.22 and 6.23 show the estimation profiles and errors. The results obtained in this scenario are similar to the first one, with an error of approximately 1.5% in estimated voltages and a 5% error in the estimation of the resistances. Moreover, the accuracies are compatible with the simulation results. In conclusion, the proposed estimation technique shows promising results in accurately estimating the open-circuit voltage and internal resistance of battery modules while reducing the size and cost of the monitoring circuit. Future research can focus on applying this technique for the acute detection of failures and simplifying the method to make it faster without losing significant accuracy. Additionally, the proposed algorithm can be extended to larger systems with multiple strings or modules.

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Fig. 6.22 The estimated and measured voltages and resistances of all seven modules for Scenario 2 © 2022 IEEE. Reprinted, with permission, from [17]

Estimator has converged

Fig. 6.23 Estimation errors for the second experimental scenario © 2022 IEEE. Reprinted, with permission, from [17]

References

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Further investigations can also explore the potential of incorporating other parameters, such as temperature, into the estimation process to improve the accuracy and robustness of the technique.

6.4 Discussion The analysis of newer topologies is limited by the requirement for an expensive and complex monitoring subsystem, which restricts their use in cost-sensitive applications or those that demand an additional source of sensor information for safety, such as electric mobility and its related systems. Additionally, the present estimation approaches neglect crucial parameters, including the internal resistance of the storage elements as well as the voltage drop across the other components, the balancing effect of the parallel connection, the more novel modulation schemes, and the low-frequency or asynchronized sampling. This chapter filled the gap by presenting a compensated model that considers the effect of balancing, and parallel connectivity for half-bridge as well as diode-clamped half-bridge systems. Additionally, we present a sampling compensation that improves the accuracy in case of a low sampling rate as well as small balancing efforts. The models are further extended in an MMS, where the internal resistances, as well as the open-circuit voltages of every module, is estimated by introducing a consecutive sampling concept and then through a dual KF. In all cases, only the voltage and current measurements at the output terminal of the system and the module connections are used which greatly simplifies the monitoring circuit. These parameters are typically present for system-level controllers, which further adds to the appeal of this approach. In future work, the proposed method and framework could potentially be utilized for detecting failures that cause rapid fluctuations in estimated impedance and opencircuit voltage. However, to achieve this, the method needs to be made significantly faster by sacrificing some degree of accuracy, which requires further research. Fault detection and/or location is outside the focus of this work but is considered an interesting future work to further integrate the monitoring system into the reconfigurable storage control and exploit the available potential for higher performance.

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79. Zheng, Y., Lu, Y., Gao, W., Han, X., Feng, X., & Ouyang, M. (2021). Micro-short-circuit cell fault identification method for lithium-ion battery packs based on mutual information. IEEE Transactions on Industrial Electronics, 68, 4373–4381. 80. Canals Casals, L., Schiffer González, A. M., Amante García, B., & Llorca, J. (2016). PHEV battery aging study using voltage recovery and internal resistance from onboard data. IEEE Transactions on Vehicular Technology, 65, 4209–4216. 81. Lievre, A., Sari, A., Venet, P., Hijazi, A., Ouattara-Brigaudet, M., & Pelissier, S. (2016). Practical online estimation of lithium-ion battery apparent series resistance for mild hybrid vehicles. IEEE Transactions on Vehicular Technology, 65, 4505–4511. 82. Wei, X., Zhu, B., & Xu, W. (2009). Internal resistance identification in vehicle power lithiumion battery and application in lifetime evaluation. In International Conference on Measuring Technology and Mechatronics Automation, (vol. 3, pp. 388–392).

Chapter 7

Remaining Challenges and Future Potentials

Whereas modular or reconfigurable energy storage systems offer many advantages over conventional systems, there are still unclear aspects in need of study, unfulfilled potentials yet to be realized, and critical challenges to be solved. This book tries to fill this gap and pave the way for further expansion of these systems, particularly in electromobility applications.

7.1 Summary In a holistic view of modular power electronics and particularly reconfigurable storages, this work systematically covers the main aspects in a bottom-to-top approach, starting from modules, continuing to various ac or dc macro-structures, and then covering the main challenges in the system, such as modulation, balancing, scheduling, and monitoring. The main contributions of this work to each aspect include the following: • At the micro level, Chap. 3 – analyzes the conventional and novel module topologies and discusses their various operation modes; – investigates various advantages and disadvantages of each topology; – introduces neglected aspects of parallel connectivity and modular storage elements. • At the macro level, Chaps. 3 and 5 – study suitable macro structures for ac, dc, and hybrid applications; – develop mathematical models for different string topologies with different degrees of accuracy; © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1_7

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– propose novel highly-integrated structures with clear advantages with a particular focus on electromobility. • From the Control and monitoring aspects, Chaps. 4, 5, and 6 – analyze state-of-the-art modulation schemes and develop novel modulation strategies for parallel-capable modules; – explore the effect of modulation on different performance metrics such as balancing, scheduling, efficiency, and output quality and improve them through novel yet feasible techniques; – propose novel controllers to regulate multiple outputs at the same time in combination with new modulation techniques; – present compensated models for some topologies with parallel connectivity; – reduce monitoring circuitry through estimation techniques capable of tracking the voltage or resistance of every module.

7.2 Future Works The first two chapters of the book aim to provide an introduction to the motivations and goals of the book, as well as some fundamental knowledge about storage types and their modeling approaches. However, in conventional applications, the modeling of storage elements typically overlooks the impact of switching and modulation on the effective model of the storage and its degradation. This is a point that requires further investigation in the field of modular or reconfigurable energy storage systems to fully understand and optimize their performance. By considering the effect of constant modulation, researchers and engineers can gain a better understanding of the behavior of the storage elements and improve their overall performance. Chapter 3 studies the available topologies and their analysis. This chapter’s main potential for future research would be developing other topologies or concepts that can simplify the control or offer additional capabilities. Chapter 4 studies the state-of-the-art modulation techniques and also presents novel modulation concepts for more advanced module topologies. Some remaining research-worthy aspects include • investigating the effect of asymmetric phase-shifted carriers or modulation indices from the perspective of output quality; • developing a fully decentralized modulation technique; • integrating the modulation technique with online parameter/state estimation, e.g., active online impedance spectroscopy; • using more intelligent or model-free controllers to control the carriers for improved performance (e.g., efficiency, harmonic, or reduce degradation). Chapter 5 focuses on developing highly integrated ac/dc systems and their control. The chapter selects electromobility applications to emphasize the true potential of

7.2 Future Works

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modular reconfigurable storage. However, what is covered in this chapter is but a glance at the true potential of such a system. Possible future works are • investigating the different operation modes (e.g., vehicle-to-grid, grid-to-vehicle, and vehicle-to-home) in the developed controllers; • study of the possibility of further integration of different functions or subsystems into the modular structure; • controlling the integrated auxiliary circuit as a resonant converter and using the switching frequency as an additional degree of freedom for even more performance or efficiency; • employing more intelligent control methods, such as reinforcement learning, as the number of interconnected ports increases and estimating the gain profiles gets challenging; • Investigating the possibility of hybrid modular energy storage systems, where the combination of different types of storage can optimize the behavior and performance of the system. In Chap. 6, the focus is to estimate the open-circuit and internal resistance of all modules online and with minimum sensors. For simplicity, only capacitors and batteries are considered due to their higher popularity. Still, the analysis and the concept can be readily extended for other storages and models. Some potential aspects in the monitoring of modular reconfigurable storages for future study are • extending the developed procedures for parameter estimations of the other energy storages (such as SCs) as well as more complex models (e.g., first- and secondorder ECM); • utilizing the developed algorithms in combination with conventional monitoring systems with the direct measurement at the modules to detect sensor fault or correct biases of the individual sensors; • combination of the parameter estimation technique with state estimation to achieve a higher level of monitoring; • as the model parameters have relatively large time constants, the concept of cloud or edge-computation can help in reducing the computational load from the local controller.

Appendix A

Detailed Derivation of Non-ideal Gain for the Auxiliary Output

For D < 0.5, the positive pulse is larger. Hence, during 0 ≤ t ≤ DTsw,eff , the diodebridge is forward biased, and the capacitor (Cdc3 ) is charged. During DTsw,eff ≤ t ≤ Tsw,eff interval with V p− < Vdc2 , the diode-bridge is reverse biased, and Cdc3 discharges into the load. Figure 5.14 shows the equivalent circuit diagram of the auxiliary port in this condition. Referring all the components to the secondary side of the high-frequency transformer (HFT), as Fig. A.1 depicts, the relation between i 1 , i 2 , and load current Iload follows i 1 =

N2 Iload , i2 , i2 = N1 D

(A.1)

where N1 and N2 are respectively winding coefficients of the primary and secondary sides. Applying Kirchhoff voltage law (KVL) when D ≤ 0.5 results in  V p+ −

N2 Iload req1 N1 D



N2 Iload − req2 − 2Vfd = Vo , N1 D

(A.2)

where req1 = rCdc2 + r L1 and req2 = r L2 + 2rfd . When DTsw,e f f ≤ t ≤ Tsw,eff , the diode-bridge is an open circuit and the Cdc3 discharges to supply the load following V p− − req1 i 1 − RC i 1 = 0,

(A.3)

From these two states, the steady-state output voltage can be calculated based on the value of V p+ . Substituting (5.4) in the paper in (A.3) results in

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 N. Tashakor, Novel Highly Flexible Modular Power Electronics for Energy Storage and Conversion Systems, Green Energy and Technology, https://doi.org/10.1007/978-3-031-36843-1

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Appendix A: Detailed Derivation of Non-ideal Gain for the Auxiliary Output

≤ ≤ ≤

≤ ≤ ≤

≠

≠

≠

diode circuit is open

≤ ≤

≠

diode circuit is open

≤ ≤

≠

≠

Fig. A.1 The equivalent non-ideal circuit of the auxiliary port based on D values



N2 Iload (1 − D) (Vm − Vr ) − req1 N1 D



N2 Iload − Vfd = Vdc2 , − req2 N1 D

(A.4)

where Iload = VRload and Vm is the voltage of an individual battery module. load Through some simplification and manipulation, (A.4) is rewritten as N2 (1 − D) (Vm − Vr ) − 2Vfd = Vdc2 (Req + 1), N1 where Req is the total equivalent resistance of the system and is calculated per

(A.5)

Appendix A: Detailed Derivation of Non-ideal Gain for the Auxiliary Output

 Req =

N2 N1



2 req1 + req2

1 . D Rload

255

(A.6)

Finally, the output gain of the system for D ≤ 0.5 is r (1 − D) NN21 (1 − V )− Vdc2 Vm = Vm Req + 1

2Vfd Vm

,

(A.7)

which can be further simplified by neglecting Vfd and Vr into Vdc2 = Vm



1− D Req + 1



N2 . N1

(A.8)

For D > 0.5, the negative pulse is larger. Therefore, as Fig. A.1 presents, the diode bridge is an open circuit during positive pulses (0 ≤ t ≤ DTsw,eff ), and the capacitor charges during the negative pulses (DTsw,eff ≤ t ≤ Tsw,eff ). The relation between the secondary current and the load current follows i2 =

Iload , 1− D

(A.9)

Similarly, KVL results in 

N2 V p− − N1



   Iload N2 Iload − req2 req1 − 2Vfd = Vdc2 , 1− D N1 1− D

(A.10)

which can be simplified to r D NN21 (1 − V )− Vdc2 Vm = Vm Req + 1

2Vfd Vm

,

(A.11)

1 . (1 − D)Rload

(A.12)

with  Req =

N2 N1



2 req1 + req2

Not considering Vfd and Vr simplifies (A.11) further into Vdc2 = Vm



D Req + 1



N2 . N1

(A.13)