Non-volatile Memories 9781848216235, 1848216238

Table of contents :
ACKNOWLEDGEMENTS xi PREFACE xiii PART 1. INFORMATION STORAGE AND THE STATE OF THE ART OF ELECTRONIC MEMORIES 1 CHAPTER 1. GENERAL ISSUES RELATED TO DATA STORAGE AND ANALYSIS CLASSIFICATION OF MEMORIES AND RELATED PERSPECTIVES 3 1.1. Issues arising from the flow of digital information 3 1.2. Current electronic memories and their classification 5 1.3. Memories of the future 8 CHAPTER 2. STATE OF THE ART OF DRAM, SRAM, FLASH, HDD AND MRAM ELECTRONIC MEMORIES 13 2.1. DRAM volatile memories 13 2.1.1. The operating principle of a MOSFET (metal oxide semiconductor field effect transistor) 14 2.1.2. Operating characteristics of DRAM memories 17 2.2. SRAM memories 19 2.3. Non-volatile memories related to CMOS technology 22 2.3.1. Operational characteristics of a floating gate MOSFET 22 2.3.2. Flash memories 38 2.4. Non-volatile magnetic memories (hard disk drives HDDs and MRAMs) 45 2.4.1. The discovery of giant magneto resistance at the origin of the spread of hard disk drives 46 2.4.2. Spin valves 49 2.4.3. Magnetic tunnel junctions 51 2.4.4. Operational characteristics of a hard disk drive (HDD) 51 2.4.5. Characteristics of a magnetic random access memory (MRAM) 54 2.5. Conclusion 56 CHAPTER 3. EVOLUTION OF SSD TOWARD FERAM, FEFET, CTM AND STT-RAM MEMORIES 59 3.1. Evolution of DRAMs toward ferroelectric FeRAMs 60 3.1.1. Characteristics of a ferroelectric material 60 3.1.2. Principle of an FeRAM memory 63 3.1.3. Characteristics of an FeFET memory 67 3.2. The evolution of Flash memories towards charge trap memories (CTM) 77 3.3. The evolution of magnetic memories (MRAM) toward spin torque transfer memories (STT-RAM) 82 3.3.1. Nanomagnetism and experimental implications 83 3.3.2. Characteristics of spin torque transfer 84 3.3.3. Recent evolution with use of perpendicular magnetic anisotropic materials 88 3.4. Conclusions 90 PART 2. THE EMERGENCE OF NEW CONCEPTS: THE INORGANIC NEMS, PCRAM, RERAM AND ORGANIC MEMORIES 93 CHAPTER 4. VOLATILE AND NON-VOLATILE MEMORIES BASED ON NEMS 95 4.1. Nanoelectromechanical switches with two electrodes 96 4.1.1. NEMS with cantilevers 97 4.1.2. NEMS with suspended bridge 102 4.1.3. Crossed carbon nanotube networks 103 4.2. NEMS switches with three electrodes 106 4.2.1. Cantilever switch elaborated by lithographic techniques 107 4.2.2. Nanoswitches with carbon nanotubes 110 4.2.3. NEMS-FET hybrid memories with a mobile floating gate or mobile cantilever 116 4.4. Conclusion 121 CHAPTER 5. NON-VOLATILE PHASE-CHANGE ELECTRONIC MEMORIES (PCRAM) 123 5.1. Operation of an electronic phase-change memory 125 5.1.1. Composition and functioning of a GST PCRAM 125 5.1.2. The antinomy between the high resistance of the amorphous state and rapid heating 129 5.2. Comparison of physicochemical characteristics of a few phase-change materials 134 5.3. Key factors for optimized performances of PCM memories 137 5.3.1. Influence of cell geometry on the current Im needed for crystal melting 138 5.3.2. Optimization of phase-change alloy composition to improve performance 143 5.3.3. Influence of nanostructuration of the phase-change material 148 5.3.4. Recent techniques for improvement of amorphization and crystallization rates of phase-change materials 156 5.3.5. Problems related to interconnection of PCRAM cells in a 3D crossbar-type architecture 160 5.4. Conclusion 162 CHAPTER 6. RESISTIVE MEMORY SYSTEMS (RRAM) 165 6.1. Main characteristics of resistive memories 168 6.1.1. Unipolar system 169 6.1.2. Bipolar system 170 6.2. Electrochemical metallization memories 171 6.2.1. Atomic switches 174 6.2.2. Metallization memories with an insulator or a semiconductor 177 6.2.3. Conclusions on metallization memories 182 6.3. Resistive valence change memories (VCM) 183 6.3.1. The first work on resistive memories 183 6.3.2. Resistive valence change memories after the 2000s 185 6.3.3. A perovskite resistive memory (SrZrO3) with better performance than Flash memories 186 6.3.4. Electroforming and resistive switching 189 6.3.5. Hafnium oxide for universal resistive memories? 195 6.4. Conclusion 198 CHAPTER 7. ORGANIC AND NON-VOLATILE ELECTRONIC MEMORIES 201 7.1. Flash-type organic memories 204 7.1.1. Flexible FG-OFET device with metal floating gate 205 7.1.2. Flexible organic FG-OFET entirely elaborated by spin coating and inkjet printing 212 7.1.3. Flexible OFETs with charge-trap gate dielectrics 216 7.1.4. OFETs with conductive nanoparticles encapsulated in the gate dielectric 221 7.1.5. Redox dielectric OFETs 226 7.2. Resistive organic memories with two contacts 230 7.2.1. Organic memories based on electrochemical metallization 232 7.2.2. Resistive charge-trap organic memories 238 7.3. Molecular memories 244 7.4. Conclusion 248 CONCLUSION 251 BIBLIOGRAPHY 255 INDEX 285

Citation preview

Non-volatile Memories

Series Editor Robert Baptist

Non-volatile Memories

Pierre Camille Lacaze Jean-Christophe Lacroix

First published 2014 in Great Britain and the United States by ISTE Ltd and John Wiley & Sons, Inc.

Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Ltd 27-37 St George’s Road London SW19 4EU UK

John Wiley & Sons, Inc. 111 River Street Hoboken, NJ 07030 USA

www.iste.co.uk

www.wiley.com

© ISTE Ltd 2014 The rights of Pierre Camille Lacaze and Jean-Christophe Lacroix to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988. Library of Congress Control Number: 2014953190 British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library ISBN 978-1-84821-623-5

Contents

ACKNOWLEDGEMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xi

PREFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xiii

PART 1. INFORMATION STORAGE AND THE STATE OF THE ART OF ELECTRONIC MEMORIES . . . . . .

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1

CHAPTER 1. GENERAL ISSUES RELATED TO DATA STORAGE AND ANALYSIS CLASSIFICATION OF MEMORIES AND RELATED PERSPECTIVES . . . . . . . . . . . . . . . . .

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1.1. Issues arising from the flow of digital information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2. Current electronic memories and their classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3. Memories of the future . . . . . . . . . . . . . . . . . . . . . . . . . CHAPTER 2. STATE OF THE ART OF DRAM, SRAM, FLASH, HDD AND MRAM ELECTRONIC MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1. DRAM volatile memories . . . . . . . 2.1.1. The operating principle of a MOSFET (metal oxide semiconductor field effect transistor) . . . . . . . . . . . 2.1.2. Operating characteristics of DRAM memories . . . . . . . . . . . . . 2.2. SRAM memories . . . . . . . . . . . . 2.3. Non-volatile memories related to CMOS technology . . . . . . . . . . . .

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2.3.1. Operational characteristics of a floating gate MOSFET . . . . . . . . . 2.3.2. Flash memories . . . . . . . . . . . 2.4. Non-volatile magnetic memories (hard disk drives – HDDs and MRAMs) . 2.4.1. The discovery of giant magneto resistance at the origin of the spread of hard disk drives . . . . . . . . . . . . . . 2.4.2. Spin valves . . . . . . . . . . . . . 2.4.3. Magnetic tunnel junctions . . . . 2.4.4. Operational characteristics of a hard disk drive (HDD) . . . . . . . . . 2.4.5. Characteristics of a magnetic random access memory (MRAM) . . . . 2.5. Conclusion . . . . . . . . . . . . . . . .

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CHAPTER 3. EVOLUTION OF SSD TOWARD FERAM, FEFET, CTM AND STT-RAM MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

59

3.1. Evolution of DRAMs toward ferroelectric FeRAMs 3.1.1. Characteristics of a ferroelectric material . . . . 3.1.2. Principle of an FeRAM memory . . . . . . . . . 3.1.3. Characteristics of an FeFET memory . . . . . . . 3.2. The evolution of Flash memories towards charge trap memories (CTM) . . . . . . . . . . . . . . . . . . . . . 3.3. The evolution of magnetic memories (MRAM) toward spin torque transfer memories (STT-RAM) . . . 3.3.1. Nanomagnetism and experimental implications 3.3.2. Characteristics of spin torque transfer . . . . . . 3.3.3. Recent evolution with use of perpendicular magnetic anisotropic materials . . . . . . . . . . . . . . 3.4. Conclusions . . . . . . . . . . . . . . . . . . . . . . . .

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88 90

PART 2. THE EMERGENCE OF NEW CONCEPTS: THE INORGANIC NEMS, PCRAM, RERAM AND ORGANIC MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . .

93

CHAPTER 4. VOLATILE AND NON-VOLATILE MEMORIES BASED ON NEMS . . . . . . . . . . . . . . . . . . . . . . . . .

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4.1. Nanoelectromechanical switches with two electrodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

96

Contents

4.1.1. NEMS with cantilevers . . . . . . . . . . . . . 4.1.2. NEMS with suspended bridge . . . . . . . . . 4.1.3. Crossed carbon nanotube networks . . . . . . 4.2. NEMS switches with three electrodes . . . . . . . 4.2.1. Cantilever switch elaborated by lithographic techniques . . . . . . . . . . . . . . . . . 4.2.2. Nanoswitches with carbon nanotubes . . . . 4.2.3. NEMS-FET hybrid memories with a mobile floating gate or mobile cantilever . . . . . . . . . . . 4.4. Conclusion . . . . . . . . . . . . . . . . . . . . . . .

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97 102 103 106

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116 121

CHAPTER 5. NON-VOLATILE PHASE-CHANGE ELECTRONIC MEMORIES (PCRAM) . . . . . . . . . . . . . . . . . . . . .

123

5.1. Operation of an electronic phase-change memory . . . . . . . . . . . . . . . . . . 5.1.1. Composition and functioning of a GST PCRAM . . . . . . . . . . . . . . . . . . . . 5.1.2. The antinomy between the high resistance of the amorphous state and rapid heating . . . . . 5.2. Comparison of physicochemical characteristics of a few phase-change materials . . . 5.3. Key factors for optimized performances of PCM memories . . . . . . . . . . . . . . . . . . . . 5.3.1. Influence of cell geometry on the current Im needed for crystal melting . . . . . . . . 5.3.2. Optimization of phase-change alloy composition to improve performance . . . . . . . 5.3.3. Influence of nanostructuration of the phase-change material . . . . . . . . . . . . . . 5.3.4. Recent techniques for improvement of amorphization and crystallization rates of phase-change materials . . . . . . . . . . . . . . 5.3.5. Problems related to interconnection of PCRAM cells in a 3D crossbar-type architecture . . . . . . . . . . . . . . . . . . . . . . . 5.4. Conclusion . . . . . . . . . . . . . . . . . . . . . .

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160 162

CHAPTER 6. RESISTIVE MEMORY SYSTEMS (RRAM) . . . . . . . . . .

165

6.1. Main characteristics of resistive memories . . . . . . . . . . . . . 6.1.1. Unipolar system . . . . . . . . . . . . . . . . . . . . . . . . . .

168 169

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6.1.2. Bipolar system . . . . . . . . . . . . . . . . 6.2. Electrochemical metallization memories . . . 6.2.1. Atomic switches . . . . . . . . . . . . . . . 6.2.2. Metallization memories with an insulator or a semiconductor . . . . . . . . . . . . 6.2.3. Conclusions on metallization memories . 6.3. Resistive valence change memories (VCM) . 6.3.1. The first work on resistive memories . . . 6.3.2. Resistive valence change memories after the 2000s . . . . . . . . . . . . . . . . . . . . 6.3.3. A perovskite resistive memory (SrZrO3) with better performance than Flash memories . 6.3.4. Electroforming and resistive switching. . 6.3.5. Hafnium oxide for universal resistive memories? . . . . . . . . . . . . . . . . . 6.4. Conclusion . . . . . . . . . . . . . . . . . . . . .

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170 171 174

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195 198

CHAPTER 7. ORGANIC AND NON-VOLATILE ELECTRONIC MEMORIES . . . . . . . . . . . . . . . . . . . . . . . . . . . .

201

7.1. Flash-type organic memories . . . . . . . . . 7.1.1. Flexible FG-OFET device with metal floating gate . . . . . . . . . . . . . . . . . 7.1.2. Flexible organic FG-OFET entirely elaborated by spin coating and inkjet printing 7.1.3. Flexible OFETs with charge-trap gate dielectrics . . . . . . . . . . . . . . . . . . . 7.1.4. OFETs with conductive nanoparticles encapsulated in the gate dielectric . . . . . . . 7.1.5. Redox dielectric OFETs . . . . . . . . . 7.2. Resistive organic memories with two contacts . . . . . . . . . . . . . . . . . . . . . . 7.2.1. Organic memories based on electrochemical metallization . . . . . . . . . . 7.2.2. Resistive charge-trap organic memories . . . . . . . . . . . . . . . . . . . . . . 7.3. Molecular memories . . . . . . . . . . . . . . 7.4. Conclusion . . . . . . . . . . . . . . . . . . . .

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Contents

ix

CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

251

BIBLIOGRAPHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

255

INDEX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

285

Acknowledgments

Upon completion of this work, we wish to thank all the people who have contributed to it with their valuable advice and suggestions. We greatly thank Robert Baptist, Research Director at the Laboratoire d’Electronique des Technologies de l’Information (CEA-LETI, Grenoble) for having peer-reviewed the French version of the manuscript and providing sound advice. We also thank Damien Deleruyelle, researcher at the Institut Matériaux Microélectronique Nanosciences of Provence (Im2np) with whom we had fruitful discussions. We are grateful to W. Bruch for his translation of this scientific text, and to John S. Lomas, Research Director at the CNRS, for polishing the English translation. We are indebted to Céline Benoit, in charge of scientific documentation in the Physics department at the University Paris Diderot, who helped us greatly in the search for documentation. We also thank our respective wives for their great patience during this long period of research and writing.

Preface

Information storage is a research topic of great importance in the electronic component industry. The constant increase in the quantity of information in circulation on the planet has created an ever more urgent need for more efficient memory systems characterized by shorter execution times (at the nanosecond level), low energy consumption and data retention times that go beyond a decade. Current electronic memories by no means satisfy all these criteria, which explain the enormous amount of research carried out worldwide by companies specialized in the manufacture of electronic components, as well as by academic laboratories. In addition to improvements to existing systems, great efforts are being made on the development of new concepts likely to lead to the emergence of more efficient memory devices. Three emerging systems are currently the focus of intensive research that could lead to the commercialization of new products: spin-torque transfer magnetic memories (STT-MRAMs), phase-change memories (PCRAMs) and resistive memories (RRAMs). The electronics industry is also very interested in the elaboration of electronic memories by printing onto many different kinds of flexible supports, such as paper and plastic. It is clear that the objective here is not to replace silicon technology, which remains at the heart of the elaboration of existing transistors and memories. As with photovoltaic

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technology, the aim is to develop new low-cost devices for domestic applications that do not require high execution speeds or storage capacities. This research, still the focus of several teams, depends on experimentation and the discovery of new molecular components, generally based on organic compounds and soft chemical techniques. Taking into account the diversity and complexity of physical, chemical and electrochemical phenomena applied in these new emerging memories, this book attempts in the simplest possible way to describe the origin of memory effects. The performances of various existing systems are compared with those of systems currently undergoing development and evaluation; the reasons behind their limitations are discussed. This book is mainly addressed to researchers in nanosciences, and chemists and physicians involved in the physical chemistry of solids and materials in the form of thin mineral or organic layers. Indeed, their work could lead to promising applications in the domain of information storage.

Pierre-Camille LACAZE Jean-Claude LACROIX October 2014

PART 1

Information Storage and the State of the Art of Electronic Memories

1 General Issues Related to Data Storage and Analysis Classification of Memories and Related Perspectives

Over the past few years, the massive increase in the volume of information has encouraged the search for ways to resolve issues related to data storage and processing. The technical means for resolving these problems go hand in hand with the improvement of read–write–erase speeds, a reduction in energy consumption of electronic memory devices as well as an increase in their storage capacity. A short description of the characteristics of the different types of memories, volatile or non-volatile, reveals the existence of a technological gap between the performance of extremely rapid volatile memories and nonvolatile memories, the latter being used for storage, but too slow for handling large volumes of data. The search for universal memories capable of combining storage and processing capabilities for data-use is a new field of research in the industry. In the years to come, this is expected to lead to the progressive replacement of current systems by new generations of memories with qualification characteristics equivalent to those of “Storage Class Memories” (SCMs). 1.1. Issues arising from the flow of digital information Information storage and the continuous increase in the volume of information circulating in the world are topics that preoccupy large

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bodies responsible for political anticipation and decision-making. A recent report by the International Data Corporation (IDC), “The Digital Universe in 2020” [GAN 12], indicates that the volume of digital information in the world decupled between 2006 and 2011, increasing from 180 to 1,800 Exabytes (EBs)1, and should reach an astounding 40,000 EBs by 2020, the equivalent of 5,200 Gigabytes (GBs) per human being. This trend is not expected to slow down – the authors of the report estimate that the volume of digital information will double every two years from 2012 to 2020 – thus leading de facto to the consideration of issues in energy consumption inherent in the running of large servers that, for obvious reasons, are now preferably located close to centers of electrical energy production and distribution, a tendency emphasized by the recent boom in “Cloud Computing” [MEL 11]. Since the 1990s, digital technologies have taken over from analog technologies. In 2007, 99.9% of telecommunications were carried-out digitally. As of the early 2000s, the majority of information was also stored in digital mode, representing 94% of all stored information in 2007 [HIL 11]. This irreversible and ultra-fast increase in the global flux of information with, in addition to this, a strong demand for increasingly powerful computers, requires an extreme miniaturization of electronic components and memories. The end of the applicability of Moore’s Law2 is considered as imminent, and new solutions must be found to resolve issues related to information storage. This question has already been considered by many bodies, and a very general prospective has been developed over the years with a view to the possible replacement of current components (transistors and memories), essentially founded on silicon-based technology, by 1 An EB represents 1018 bytes or 1 billion Gigabytes 2 Moore’s Law, laid down during the boom in computing (1965), stipulates that the number of transistors implanted on a “chip” approximately doubles every two years, which means that the width of the printed circuit lines decrease by a factor of 0.7 for each generation of transistors.

General Issues Related to Data Storage and Analysis

5

new systems based on materials capable of increasing the integration density of components in the electronic circuits so as to improve energy efficiency while promoting high operational reliability. 1.2. Current electronic memories and their classification Computers and information storage currently depend on the use of two kinds of memories: volatile and non-volatile (Figure 1.1). Volatile memories (essentially Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM)), which are used to run computers, have very short execution times but, unfortunately, the conservation of data with time (retention) requires either periodical refreshing (DRAMs) or a constant power supply (SRAMs), both of which are costly in terms of energy. Non-volatile memories, consisting mainly of hard drives (Hard Disk Drives (HDDs)) and more recently Flash memories (NOR and NAND) have retention times that are convenient for the requirements of information storage. At rest, they do not require a power supply but have read–write and erase times that are too long for logic operations. They are used for storage and are classified as Read Only Memory (ROM) memories. Magnetic memories (MRAM) are also non-volatile and very fast, and can be addressed in random access. Among volatile memories, DRAMs and SRAMs are the main memories used to run logic operations. DRAMs have very short retention times (at the ms level or less) and therefore require periodical refreshing. SRAMs conserve information when they are connected to a power supply, and lose this information when the power is off. This last type of memory, for which write, read and erase tasks are very rapid (a few nanoseconds), is mostly used in computers as cache memory3.

3 Cache memory is temporarily saved data that is extracted from the main memory. It is a data and instruction “reserve” used to run repetitive operations, and has the advantage of being very rapidly accessible, the effect of which is to shorten execution times of certain computing operations.

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Non-volatile memories, which have very high retention times, must be considered as peripheral components of the computer that do not take part in logic functions. They are used for reading information that is archived, and hence are referred to as ROM. Within this first and very general definition, a distinction is made between memories used to store information that is considered as programmed just once, and can be read without any possible modification – One Time Programmable Read Only Memory (OTPROM) or Write One Time Read Many (WORM) – and those where the information can also be indefinitely conserved, but this time, with the possibility of modifying it when required – EPROM memories, i.e. ROM memories that can be erased and reprogrammed.

Semiconductor memories RAM

ROM

Magnetic memories ROM

RAM

HDD

MRAM

EPROM DRAM

SRAM

UVEPROM

EEPROM FLASH

Non Volatile

Volatile Figure 1.1. Classification of the main current types of volatile and non-volatile memories. Adapted from Jeong et al. [JEO 12]

The first memories of the latter type, known as UV-EPROM, which appeared on the market in the 1970s, could be erased by exposing the entire device to prolonged UV irradiation. In the 1980s the first memories appeared that could be written and erased

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electronically (Electrically Erasing PROM (EEPROM)) but that could also conserve the information indefinitely, therefore providing an advantageous replacement for UV-EPROM. Flash memories, first produced in the 1980s by Toshiba, and a few years later by INTEL (1988), were derived from EEPROM memories. These memories are in fact an assembly of EEPROMs that, depending on their connection mode (parallel or series), lead to NOR Flash and NAND Flash memories. In the past few years, these memories have been the object of considerable industrial development and are considered as future storage memories, capable of competing with magnetic hard drives. Their common feature is the local appearance or disappearance of an electrical charge trapped in a “floating” electrode, designated as a storage “node”, and corresponding to processes involving “charge storage nodes” [ZHI 12]. The magnetic storage of information is without doubt the oldest procedure4. Magnetic hard drives (HDD) rely on a process in which the memory effect is due to the recognition of magnetic microdomains that can be reversibly created and erased. They constitute exceptional non-volatile memories that have the advantage of allowing periodical and almost indefinite writing and erasure of data, and are able to conserve it for as long as the rotating disk is functional. The most significant event that can lead to the loss of data is a mechanical incident that crashes the read–write head onto the rotating disk, which unfortunately, like any catastrophe, occurs without warning and not infrequently. Contrary to HDDs, for which access to data is sequential, MRAM magnetic memories operate by random access and no longer have any mechanical parts, but require greater space, due to the number of leads necessary for the magnetic field, and have a higher energy consumption, for which reasons they are restricted to specific applications (see Chapter 2, section 2.4.5). 4 The first device at the origin of current hard drives was produced by IBM in 1954 (350-Random Access Method of Accounting and Control (RAMAC)). It weighed over a ton, consisted of 50–60 cm-diameter disks, had a storage capacity of just 5 megabytes. In 1956 it cost more than 50,000 dollars [IBM 57].

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Non-volatile Memories

1.3. Memories of the future For a long time the electronic memory industry was dominated by the production of DRAMs and HDDs, and it is only recently, with the beginning and the intrusion into everyday life of portable devices of all kinds, that the share in the market of Flash memories (Solid State Drives (SSD)) has considerably increased compared to that of HDDs. It is admitted, however, that the scale reduction of floating gate Flash memories beyond the 16 nm scale will be difficult to achieve without a significant increase in their manufacturing costs [BUR 13]. The ambition to develop ever more powerful yet less powerhungry calculators, while remaining within reasonable costs, implies that either great progress has to be made in the conception of storage hard drives or that new approaches for data storage must be considered. It is this research effort toward new technologies that has led the industry to select a limited group of systems capable of combining the dynamic characteristics of DRAMs with storage characteristics close to those of HDDs. The International Technology Roadmap for Semiconductors5 (ITRS) in its 2010 editions (Emerging Research Materials, [HUT 10, ITR 11]) suggests new paths in research for the elaboration of

5 The ITRS is an international body created by the Semiconductor Industry Association (SIA) that ever since its formation in 1977 has guided the majority of the major American electrical component manufacturers by proposing important R&D directions, the latter discussed and established by a committee of researchers and engineers, which has led to the birth of the National Technology Roadmap for Semiconductors (NTRS). This committee rapidly grew on the international scale and, in 1998, several countries associated themselves with the SIA to found ITRS, a body that is now sponsored by Europe, Japan, South Korea, Taiwan and the USA. Since 1999 this new international body has published an important report every year, the fruit of a widespread consensus between manufacturers, whose goal is to guide the semiconductor industry in its choice of R&D programs with a realistic vision of “emerging” systems for the 15 years to come. It is also at the origin of “More than Moore” (MtM), a concept for the development of new technologies, implying the creation of devices that combine different functionalities on the same electronic chip.

General Issues Related to Data Storage and Analysis

9

electronic memories so as to reduce energy consumption but also increase the density of chip memories. The evolution toward twocontact memories, which remains compatible with current Complementary Metal Oxide Semiconductor (CMOS) technology, is considered as being the best solution [ITR 11]. In order to better understand the challenges involved in the development of information, with the related problems, the necessity for shorter and shorter access times and for increasingly large storage capacities (in terms of time and quantity), we show in Table 1.1 a few essential properties of the most widely used types of memories that make up the major part of the market. SRAM

DRAM

Flash (NAND)

HDD

Reciprocal density (F2)

140

6-12

1-4

2/3

Energy per bit (pJ)

0.0005

0.005

0.00002

Read time (ns)

0.1-0.3

10

100 000

5-8x106

Write time (ns)

0.1-0.3

10

100 000

5-8x106

Retention Endurance (cycles)

as long as V applied > 10 16

VGS. The current is then equal to: I DS,sat =

µsat Ci (VGS – VTh)2

where µsat represents the charge carrier mobility in the saturation region.

Figure 2.2. Electrical characteristics of an n-type MOSFET (current and voltage in arbitrary units); a) output curves for different VGS gate potentials (VGS increasing). For each curve corresponding to a single VGS value we observe a region where the current increases linearly with VSD (linear regime) and a region where it remains constant (saturation regime); b) transfer curves, log(IDS) vs. VGS and (IDS)1/2 vs. VGS, at constant VDS. Adapted from [ZAU 07]

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A double representation of the transfer curves IDS = f(VGS) is shown in Figure 2.2(b) and corresponds to: – the logarithmic variation of the current IDS with VGS; – the variation of the square root of IDS with VGS, which gives two line segments the intersection of which indicates the threshold voltage VTh of the gate where the current IDS in the channel becomes significant.2 As we will see later, this quantity is particularly important in the definition of the operation of electronic memories based on floating gate MOSFETs. 2.1.2. Operating characteristics of DRAM memories They consist of a MOSFET and a capacitor, linked to two conducting command lines, orthogonal to each other (word line and bit line). The device includes three contacts; it is generally referred to as a 1T/1C memory (Figure 2.3).

Figure 2.3. Scheme of a DRAM memory made of an n-type MOSFET and a capacitor, linked to the word and bit lines, respectively, driving the gate and drain voltages. Adapted from [SCO 07]

2 The region located below the threshold VTh varies exponentially and is characterized by a slope S = dVGS/d(logIDS) (subthreshold swing). S is a function of the gate oxide and of the depletion layer capacities; it is equal to or greater than 60 mV per decade [KIN 03].

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Non-volatile Memories

Each DRAM memory can store a ‘1’ or ‘0’ bit corresponding to the capacitor charge or lack of charge, respectively. Programming and erasing the capacitor charge are carried out by the transistor, the latter acting as a switch for the capacitor (considered as a storage node). The closing and opening of the channel, controlled by the gate voltage, is therefore dictated by the word line that defines the access or non-access to the capacitor. The bit line, directly linked to the transistor channel, is then able to charge (bit ‘1’) or discharge (bit ‘0’) the capacitor. The charge is read with the bit line after the opening of the channel through the word line. The drawback of this process is that reading implies the destruction of the capacitor charge, this requiring immediate restoration. The simplicity of the manufacturing process which de facto implies a low cost and, moreover, a high integration density at the 6F2 scale, allowing several billion transistors on the same chip, is obviously an advantage. Other advantages include their high endurance to cycling (greater than 1016), which make them almost indestructible, as well as their very high programming and erasing speeds, with switching times less than 10 ns, that fully justify their use to carry out logic operations of computers at very high speed [JEO 12]. The main drawback of this type of memory is its very high volatility due to the fact that the electrical charge stored by the capacitor is rapidly dissipated, therefore requiring refreshing approximately every millisecond. Another drawback is that the charge stored in the capacitor is destroyed during reading, this also requires a new charge operation immediately after reading, as well as a greater complexity of the connectics.

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2.2. SRAM memories SRAMs are also volatile memories but, in contrast to DRAMs, the information is stored as long as the device is connected to a power supply, and loses it as soon as its connection to the latter is removed. The device, which is more complex than a DRAM, is made of several transistors, six generally, and is therefore referred to as 6T memory (Figure 2.4). The memory comprises a 4-transistor storage cell or latch (shown in dark gray in Figure 2.4), formed by two crossed voltage inverters M1-M2 and M3-M4 (see Box 2.1). This set-up, typical of CMOS technology, and equivalent to a “flip-flop” circuit, has the ability to store information ‘0’ or ‘1’ (the logic equivalent of low or high voltage) in a stable state as long as the system is powered.

Figure 2.4. Functional diagram of a 6-transistor SRAM memory, consisting of a latch (crossed inverters M1-M2 and M3-M4) and of two access transistors M5 and M6. The input signal Q of the M1-M2 inverter is linked to the output of the M3-M4 inverter, and inversely the input signal ͞Q of the M3-M4 inverter is linked to the output of the M1-M2 inverter. M5 and M6 transistors are comparable to two switches driven by the word line WL that simultaneously polarizes the gates of these transistors and allows the two bit lines BL to read the stored information

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Non-volatile Memories

A CMOS inverter is an electronic device that gives an output signal (Out) inversed compared to the input signal (In). For logic data, this occurs by the conversion of the input and output voltages into a couple of logic data (‘0’, ‘1’). As a result, with a low ‘In’ voltage signal (coded ‘0’) we obtain a strong ‘Out’ voltage signal (coded ‘1’) and, reciprocally, if ‘In’ is strong (‘1’) then ‘Out’ is low (‘0’).

a)

This inversion is performed in CMOS technology by the series combination of an n-type and a p-type MOSFET in a way that connects the source of the pMOSFET to the drain of the n-MOSFET. The drain of the p-MOSFET is brought to a voltage VDD (logic signal ‘1’) whereas the source of the n-MOSFET is earthed (logic signal ‘0’). The two gates are linked to each other and the input signal ‘In’ is applied to them. The output signal ‘Out’ is measured at a point, common to the source and the drain of the p- and nMOSFETs, respectively (a).

+ VDD p n a)

b)

A

o

A

Symbolically, the inverter is represented by (b), where A is the input signal and A is the output signal.

When the gate voltage is low (In = ‘0’) the channels of the n and p transistors are closed and open, respectively, implying that the output signal is at voltage VDD, so that ‘Out’ = ‘1’ (c). Conversely, when the gate voltage is high (In = ‘1’), the p and n transistors are nonconductive (open) and conductive (closed), respectively, this resulting in the direct grounding of the output, so that Out = ‘0’ (d).

Box 2.1. CMOS inverter characteristics

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The two binary signals Q and Q (‘0’ and ‘1’ or ‘1’ and ‘0’) stored in the latch are transmitted to the two bit lines (BL and BL) by two access transistors, M5 and M6 (light gray regions), which are opened or closed by a word line connected to each of the gates of the M5 and M6 transistors. The operation of the memory can be summarized by three functions: stand-by, read, and write or erase. The stand-by function, corresponding to the conservation of information ‘0’ or ‘1’ in the latch, is imposed by the word line by applying a negative or low voltage at the gates of the two n-type MOSFETs M5 and M6, making them non-conductive, and is equivalent to isolating the latch from the two BLs. Read, on the other hand, is latch in communication with the two represented here), connected to the two the stronger signal, and thus reads the the BL3.

obtained by putting the BLs. A sense amplifier (not BLs, identifies which line has initial information carried by

Writing and erasing are carried out by opening the channels of the transistors M5 and M6 and by imposing the values ‘0’ and ‘1’ on the two BLs. From a practical point of view, SRAM memories are extremely rapid and have commutation times of a few tenths of a nanosecond, which makes them 10 times faster than DRAMs. The number of cycles (write – erase) is, as for DRAMs, almost unlimited (>1016). Though they are volatile when the power supply is cut, they do not require periodical refreshing, making them more advantageous than DRAMs in terms of energy consumption.

3 A sense amplifier is an electronic device connected to the extremities of two complementary BLs (‘0’ and ‘1’) whose function, after amplification of the voltage difference between the two BLs, is to identify which of them has the logic state ‘0’ or ‘1’.

22

Non-volatile Memories

Unfortunately, their complexity makes them expensive to manufacture, and their large size (area > 140F2) does not allow high integration densities. As a result, their use in computers is limited to low-capacity cache memory, which is used to carry out repetitive operations at high speed, thus considerably shortening the execution times of complex operations. 2.3. Non-volatile memories related to CMOS technology This refers mainly to devices derived from the MOSFET technology that initially led to electrically erasable programmable read only memory (EEPROM) memories, and later to Flash memories. The introduction into a MOSFET of a metallic floating gate, separated from the control gate and from the SC by two very thin insulating layers, gives rise to a memory effect, discovered in the 1960s by Kahng and Sze, at the Bell Labs [KAH 67]. Charging the floating gate at different levels induces a shift in the operating threshold VTh of the MOSFET, thus opening a read window between the ‘1’ and ‘0’ states, corresponding to the charge or lack of charge in the floating gate. A considerable advantage compared to DRAMs is that the charge stored in the floating gate can be preserved over very long times (10 years approximately), and also, in contrast to DRAMs, the read process does not destroy the charge stored in the gate. 2.3.1. Operational characteristics of a floating gate MOSFET The structure constitutes a charge storage node and differs from a MOSFET in the additional introduction of a metallic floating gate FG, surrounded by an insulating material (Figure 2.5).

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Figure 2.5. MOSFET with a floating gate (FG). Metallic deposits are in dark gray and insulating layers (metal oxide) that surround FG are in white

The charge stored in the floating gate acts as an electrostatic screen for the control gate CG and, consequently, shifts the operating threshold VTh of the transistor. The transfer curves of the transistor are shifted parallel to the VGS axis (Figure 2.6). This shift, which increases with the charge, occurs toward positive or negative voltages depending on whether SC is n- or p-type. In the absence of charge in the floating gate, the transfer curve indicating the drain current IDS variation with the control gate voltage VGS is characterized by a threshold operating voltage equal to VTh(1). This threshold voltage is shifted toward positive voltages and is equal to VTh(0) when the floating gate acquires a negative charge. When a VGS between VTh(1) and VTh(0) is applied to the control gate, the two memory states are read by measuring IDS: a high current IDS corresponding to the absence of a charge in the floating gate, defines the ‘1’ state whereas a low current intensity, resulting from a negative charge, defines the ‘0’ state. It is easier to read both ‘0’ and ‘1’ states for greater Δ(VTh(1) - VTh(0)) values. Programming is therefore equivalent to injecting an electrical charge into FG. In contrast to this, erase corresponds to the discharge of FG and the return to the initial value VTh(1) of the gate potential.

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Non-volatile Memories

Figure 2.6. Operational characteristics of an n-type floating gate MOSFET

COMMENTS ON FIGURE 2.6.– When there is no charge in the FG, the transfer curve corresponds to ‘1’ state, with a control gate CG threshold voltage VTh(1). When the FG is charged, the transfer curve is shifted toward more positive voltages of CG, the shift increasing with the charge in FG. The new transfer curve corresponds to ‘0’ state with a new operating threshold VTh(0). The two states, ‘0’ and ‘1’, are read by choosing VGS between VTh(0) and VTh(1) (Read = dotted line potential). 2.3.1.1. How to charge and discharge the floating gate? In the case of an n-type MOSFET, the injection of electrons into the floating gate is carried out by applying a positive and significant potential to the control gate CG (10–15 V) and by maintaining a small current between the source and the drain (requiring the application of a difference VDS of a few volts) (Figure 2.7(a)). This charge carrier injection occurs through the oxide layer next to the channel and can only take place if the electrons in the channel have sufficient kinetic energy to jump over the insulating barrier, a mechanism known as “hot electron injection” [CON 67].

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Figure 2.7. Diagrams of charge a) and discharge b) of an n-type floating gate MOSFET

COMMENTS ON FIGURE 2.7.– For both charge and discharge, the electrons are made to move from the channel to the floating gate through the oxide layer 1. The floating gate FG is charged by briefly polarizing the control gate at a potential VGC >> VTh; it is discharged by applying a potential VGC 10 years); the speeds of injection and ejection of this charge determine the write and erase time performances; the minimum charge stored which allows reliable reading by the field effect transistor. 2.3.1.2.1. Charge retention Charge retention is a function of the energy barriers that appear every time an insulator is in contact with an SC or a metal, and for which different conduction mechanisms can be considered (see Box 2.2). As a result, in the case of a symmetrical Metal/Insulator, (I1)/Metal/Insulator, or (I2)/Metal structure, an electrical charge located in the “potential well” created by the I1/Metal/I2 junction is isolated by two energy barriers of height Wb and of width a (Figure 2.8). This electrical charge has two possibilities to exit from the potential well (equivalent to the floating gate): either by a tunnel effect (IT current) through the two barriers, or by jumping over the barrier (thermionic emission), after gaining a quantity of energy greater than Wb (current Io-b). Actually, the presence of electrical charges in the wells increases its potential to Vs, equal to eNs/Cm, where e represents the charge of an

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electron, Ns the number of electrons trapped in the well and Cm the equivalent capacity of the I1/M/I2 structure. This results in a modification of the profiles of the energy barriers.

Figure 2.8. Diagram of an electrical charge trapped in the potential well resulting from the I1/M/I2 structure (Insulator/Metal/Insulator). Io-b and IT represent leakage currents occurring, by thermionic emission or tunnel effect, respectively. Adapted from [ZHI 12]

Initially rectangular, the energy profiles become trapezoidal, with an increasingly narrow triangular part as the charge becomes greater, which makes electron transfer by tunnel effect easier (Figure 2.9).

Figure 2.9. Energy profile of a symmetrical I1/MFG/I2 structure in the presence of a charge on the floating gate MFG. Adapted from [ZHI 12]

As a consequence, the greater the charge, the more leakage is significant, and the less time the charge is retained. This is the reason why, in practice, the charge is limited to a number of electrons so that eVs does not exceed a value significantly greater than Wb/2. Under these conditions, the maximum number Nmax of electrons that can be stored in the floating gate is of the order of: Nmax ≈ CmWb/2e2, or Nmax = ε0 εrWb A/a e2 [ZHI 12]

28

Non-volatile Memories

Adapted from [YAN 13] and [WON 12]

(1) Schottky injection: thermionic injection of electrons into the conduction band (CB) of the insulator (thermal activation of the electrons). (2) Fowler–Nordheim injection: tunnel injection through a thin triangular energetic barrier from the cathode toward the CB of the insulator. (3) Injection of electrons by tunnel effect: transition of the electrons of the cathode toward the anode through the insulator. (4) Injection of electrons through traps: tunnel injection of thermally activated electrons from the cathode toward electron traps located in the forbidden band of the insulator. The traps are located at an energy level Et below the CB and are due to the presence of impurities, stoichiometric defects, etc. (5) Poole–Frenkel injection from traps: thermally activated electron injection toward the CB of the insulator. (6) Tunnel injection of electrons from the traps: transfer by tunnel effect of electrons trapped in the forbidden band of the insulator toward the CB. (7) Hopping of electrons between traps: electron transition by tunnel effect between neighboring traps located inside the forbidden band. (8) Tunnel injection of trapped electrons toward the anode.

Box 2.2. Conduction mechanisms of electrons for a polarized Metal/Insulator/Metal junction

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where, a: thickness of I1 and I2; ε0: vacuum permittivity = 8.85 × 10-12 F/m; εr: relative permittivity of the insulator (dielectric constant); A: area of the floating gate; e: electron charge. As an example, by taking an insulator thickness a = 5 or 10 nm, a floating gate area of 400 nm2 (20 × 20 nm) and an energy barrier Wb of 3.1 eV (SiO2 on silicon), we obtain 53 and 27 stored electrons, respectively, which is very few. From these numerical values, the theoretical retention times of the charges in a MOSFET floating gate structure can be predicted, by estimating that losing half the charge is a limit that must not be exceeded to ensure the memory works well. As a result, considering that the charges can disappear by thermionic emission and the tunnel effect, the time tr necessary for the initial charge to decrease by half is: tr = 0.5 Ns e/2(I o-b + IT) where factor 2 comes from the fact that, statistically, the electrons can escape in two opposite directions. By calculating the average of thermionic current IT and tunnel current Io-b depending on Wb and a the minimum theoretical value, a retention time greater than 10 years (3 × 108 s) is obtained. A numerical simulation for T = 400 K, with an insulator with dielectric constant = 10, indicates that the energy barrier must be at least 1.73 eV and the oxide layers at least 7 nm thick to get a retention time greater than 10 years (minimum norm for a non-volatile memory). The energy barriers relative to Si and obtained with the oxides SiO2 (3.1 eV), Si3N4 (2.4 eV) and Al2O3 (2.8 eV) appear to give retention times of more than 10 years, whereas hafnium oxide HfO2 (1.5 eV), sometimes used in association with other oxides, cannot reach this norm alone [ZHI 12].

30

Non-volatile Memories

2.3.1.2.2. Problems related to writing and electron injection Electrons can be injected into the floating gate from the substrate or from the S and D electrodes in two ways: either through the Fowler–Nordheim (F–N) effect or by thermionic hot electron injection. The F–N emission is a tunnel injection process through an energetic barrier made “triangular and thinner” by an applied high voltage between the electrodes. In the case of a MOS structure with a floating gate, this is equivalent to applying a very high positive voltage VCG (in general eVCG > 2 Wb) to the control gate CG that is in contact with the insulator I2. Initially “rectangular” in the absence of polarization (Figure 2.9), the energy barrier (SC–Insulator) is transformed into a “triangular” barrier, increasing the electron transfer by the tunnel effect in the region where the barrier is the thinnest (Figure 2.10).

Figure 2.10. Energy profile of the Channel (Ch)/I1/FG/I2/CG structure in the case of Fowler–Nordheim-type injection. It is necessary to polarize the control gate to a high potential VCG (between 10 and 12 V) so that tunnel transfer takes place in the narrowest part of the energy band of the insulator I1. Adapted from [ZHI 12]

Experiment shows that to obtain a very short write time (corresponding to a significant tunnel current), a very high voltage must be applied between the control gate CG and the source electrode. As a result, in the case of a silica insulating layer I1 with dimensions comparable to those previously described (~7 nm), a

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voltage of 10 V applied at the CG leads to a write time that is barely less than the ms. The voltage of the CG must be increased to 12 V to reduce this to a few tens of µs [ZHI 12]. Electron injection by a thermionic procedure refers to a very different mechanism and implies a significant activation of the electrons in the MOSFET channel. A small positive voltage greater than Wb must be applied between the source and the drain (generally around 4 to 5 V) so as to create a channel current of about 100 µA. The energy gained by the electrons (hot electrons) allows them to jump over the energy barrier of the M/I1 junction, while at the same time, the positive voltage applied at the CG attracts them into the floating gate. This injection mechanism is known as “channel hot electron injection” (CHE) (Figure 2.11). This electron injection mechanism, which is much faster than that of the Fowler–Nordheim method, allows write times on the µs scale but especially enables write operations with much lower CG voltages (7–8 V instead of 12 V for the F–N mechanism).

Figure 2.11. Energy profile of the Channel (Ch)/I1/FG/I2/CG structure in the case of CHE injection. The voltage VCG (around 4–5 V) is much lower than that applied in the case of F–N-type injection. Adapted from [ZHI 12]

It has, however, a major drawback from the perspective of energy consumption. The yield of this injection procedure is extremely small, around 10-5–10-6, which means that 105 to 1 million electrons are needed in the channel to store just one in the floating gate [ZHI 12].

32

Non-volatile Memories

As a result, the write procedure has a high energy consumption. As an example, the storage of 100 electrons in FG (equivalent to writing one bit), achieved with a voltage of 5 V between the source and the drain, requires 10-11–10-10 joules (i.e. 10–100 pJ). It must be recalled that the energy consumption for writing a bit in the case of SRAMs and DRAMs is only 5 × 10-4 and 5 × 10-3 pJ, respectively [YAN 13]. 2.3.1.3. Multilevel cells The previously described floating gate MOSFETs run according to the absence or presence of a charge in FG corresponding to the two values ‘0’ and ‘1’ of a bit. Such a memory is described as a “single level cell” (SLC) memory. Recently, in an attempt to increase integration density, several manufacturers have developed floating gate memories in which, instead of considering only two levels of charge storage (‘0’ and ‘1’) corresponding to two separate values, VTh,0 and VTh,1, several storage levels are defined, which lead to several operating thresholds, and, consequently, memories with several bits, described as “multilevel cells” (MLC) memories. Depending on the number of stored cells corresponding to intermediate levels of charge, several operating thresholds VTh of the MOSFET can be defined and, therefore, several read voltages, each located between the two consecutive operating thresholds, VTh, n and VTh, n+1. As a result, for a memory capable of storing four levels of charge 0, N, 2N and 3N electrons (2-Bit memory), four combinations of the two bits, ‘00’, ‘01’, ‘10’ and ‘11’ are associated. To each charge value corresponds a voltage of the operating threshold of the transistor designated by VTh,00, VTh,01,VTh,10 and VTh,11. Two consecutive thresholds are separated by the same interval. So, by applying a gate potential (VRead) equal to one of the values (VTh,00 + VTh,01)/2, (VTh,01 + VTh,10)/2, (VTh,10 + VTh,11)/2 or greater than VTh,11 the drain currents corresponding to the ‘00’, ‘01’, ‘10’ and ‘11’ states can be read as one of the four combinations of two bits.

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Following the same principle, a three-bit memory can be made if 8 levels of charge in FG, corresponding to the three bit combinations (‘000’, ‘001’, ‘010’, ‘011’, ‘100’, ‘101’, ‘110’ and ‘111’), can be achieved. By a simple error calculation (application of the Poisson statistical law and of the definition of the standard deviation equal to √ ), it can also be shown that the construction of MLC memories implies that a minimal number of electrons be injected into each level. As a result, in the case of a two-bit memory, to avoid overlap errors between two levels, the difference N in the number of electrons stored in two neighboring levels must be at least 6, which implies a limit to the area of the FG of around 400–600 nm2, when the insulator I1 (SiO2) is 7 nm thick [ZHI 12]4. This technology already dates back a few years and is applied in the manufacture of Flash memories, in principle structurally identical to EEPROMs. They make it possible to increase the integration density of memories (that can be lower than 4F2) but, on the other hand, new constraints are appearing with more complex programming, which makes MLCs slower than SLCs. This induces longer write times as well as a drop in the endurance that considerably reduces the number of write–erase cycles, which falls to about 104 instead of 105– 106 in the case of SCL cells. 2.3.1.4. The quality of dielectrics: one of the reasons behind the limitation of floating gate memory performances All the values indicated previously correspond to supposedly perfect dielectrics, particularly with oxides free of stoichiometric defects and perfectly insulating. In fact, this is not the case and, furthermore, these dielectrics are “chemically worn” during the write and erase cycles, resulting in the input of small quantities of electrons. The latter react with the oxide and create local defects, which allow the stored electrons to move out of FG toward the channel or CG [LU 09]. 4 To avoid overlap between the two levels with, for example, N and 2N electrons, N + √ must be less than ~ 2N - √2 , meaning that √ (1 + √2 ); hence the minimum value of N should be ~6 and, therefore, a memory with 4 levels of charge (0, N, 2N and 3N) requires not fewer than approximately 36 stored electrons.

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Non-volatile Memories

On the practical side, this requires that the dielectrics be made thicker, while also taking into account the fact that the manufactured oxide I1 (between SC and the floating gate) is of better quality than I2 between FG and CG5. In view of these experimental facts, manufacturers have created floating gate memories with lower and upper dielectric layers at least 8 and 15 nm thick, respectively. The lower insulating layer is generally considered as the “tunnel oxide” layer, the upper insulating layer being the “blocking oxide” layer. Another way of limiting the loss of efficiency of a floating gate memory is to replace it by a series of isolated conductors or semiconductors. It must be noted that when a conducting path has been formed between the gate and the channel, it is the whole charge of the floating gate that disappears, thus annihilating the memory. By replacing the gate by conductive nanocrystals isolated from one another and surrounded by the dielectric, we avoid the general malfunction of the memory. The simultaneous discharge of all the isolated conductors is unlikely, and so the endurance of the memory to cycling is considerably improved. This concept of “immersion” of conductive nanocrystals in a dielectric was considered for the first time at IBM by Tiwari et al. at the end of the 1990s [TIW 96]. Work on this has since been resumed by many researchers and several microelectronics companies continue to carry out research in this direction and estimate that “nano-crystal Flash memories” could be the future generation of Flash memories with a considerably increased endurance to cycling [CHA 11].

5 The dielectric I1 (generally SiO2) is obtained by thermal oxidation of the underlying silicon, which leads to a high-quality oxide, almost exempt of stoichiometric defects. The dielectric I2, located above FG (polysilicon, generally strongly doped and very conductive) is obtained through CVD (chemical vapor deposition). This procedure consists in reacting components in the gas phase to obtain the oxide and to deposit it onto FG, a method that does not give as good a dielectric as in the previous case.

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This technology has been developed essentially at Freescale Semiconductors since 2003, and much research is being carried out on the same topic by Toshiba, Hitachi, Atmel, IBM, Philips, Renesas, Samsung, STMicroelectronics, etc. 2.3.1.5. The “Achille’s heel” of floating gate memories The presence of the floating gate FG in the transistor attenuates the electric field applied by CG to the electrons of the channel. This is equivalent to saying that this electric field is screened by FG. In addition to this, to obtain the same effect over the channel as with an ordinary MOSFET, we must apply a much greater potential to CG. This last point is in contradiction with the reduction of write and erase voltage values which is being sought. This attenuating effect is characterized by a coupling coefficient αG (GCR, gate coupling ratio) that relates the potential VFG to VCG. This potential VFG can be considered as the effective voltage Ve seen by the electrons of the channel. It is given by the relation: Ve = αG VCG = VCG/(1 + CFG/CCG) 6 VCG is the CG voltage, CCG the capacity resulting from the presence of the dielectric between CG and FG, CFG the capacity due to the lower dielectric located between FG and the semiconductor. CFG is equal to the sum of the capacities, FG-Source (CS), FG-Channel (CCh), FGDrain (CD), so that CFG = CS + CCh + CD (Figure 2.12). The memory operates acceptably with a coefficient αG greater than 0.6 [LU 09], which implies that CCG > 1.5 CFG. Such a value cannot be reached with a planar symmetrical system in which the insulating layers are of silica (SiO2) and where the upper insulating layer has to be around 15 nm thick in order to exercise its charge blocking effect.

6 This relation is obtained by considering that FG, in which a charge is stored, is the common electrode for both capacitors CCG and CFG. This charge is therefore equal to CCG (VCG – VFG) and CFG VFG, whence the coupling coefficient between CG and FG is obtained.

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Non-volatile Memories

Figure 2.12. Diagram of the different coupling capacitors of a floating gate FG MOSFET. CCG represents the capacitor between the two control gate CG and floating gate FG electrodes; CS, CCh and CD are the coupling capacitors between FG and the source, FG and the channel, FG and the drain (CFG = CS + CCh + CD), respectively

Overcoming this problem implies the adoption of new materials and new structures. This is the major difficulty that prevents extreme miniaturization of geometrically planar floating gate MOSFET memories which, for some, is their “Achille’s heel” [LU 09]. Several solutions have been considered to resolve the problem of reaching a coupling coefficient αG greater than 0.6. The first solution consists of replacing the planar CG with a geometry that surrounds the FG and increases the active area of the condenser CG–FG and thus its capacity CCG (Figure 2.13). As an example, with a square base (WxL) floating gate of height H, the active area of the capacitor CCG is approximately 3F2 (F being the minimum dimension permitted by the technology), equivalent to 3 times that corresponding to a planar structure (WxL = F2), which leads to an αG greater than 0.6.7 This type of structure, sometimes referred to as the “wrap-around floating gate”, presents, however, a number of limitations that prevent it reaching high integration densities. 7 This 3F2 value corresponds to the effective area A of the capacitor CG-upper dielectric-FG. We have: A = W.L + 4 (L.H/2), resulting in 3F2, by writing W = L = H = F (H/2 corresponds to the fact that encapsulation is only effective for half the height of FG).

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The fact that the upper oxide layer cannot be less than 10 nm thick means that the lateral distance of approach between the two FGs cannot be less than 20 nm, which excludes any attempt to integrate these memories beyond this size limit, and makes any prospect for evolution in terms of miniaturization difficult 8. The planar structure does not possess this limitation and we can in this case consider much greater integration densities, compatible with the need to reduce the size of memories, as long as a solution is found to the problem of bringing the coefficient αG up to a value greater than 0.6.

Figure 2.13. Floating gate MOSFET memory in which FG (considered to have a square base WxL and height H) is partially covered by CG: a) cross-section view; b) view from above (horizontal cross-section). Adapted from [ZHI 12]

The replacement of SiO2 in the upper layer of the dielectric by an insulating oxide of high dielectric constant (between 9 and 30), but also with an elevated interface energy barrier Wb, is one of the solutions to obtain a value of αG compatible with the operation of a planar memory. Among the different oxides with a high dielectric constant and a high energy interface barrier, alumina Al2O3 (εr = 9, Wb = 2.8 eV)

8 Recently, the possibility of fabricating NAND Flash memories according to the “wrap-around floating gate” principle has been shown for 25 nm technology [PRA 10].

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satisfies both requirements and has been considered as a blocking layer to replace inter-poly-Si ONO (SiO2–SiN–SiO2) -type dielectric layers9. Good retention performances, however, are only obtained after thermal treatment at 850°C, that transforms the amorphous alumina into a crystalline form. This crystal increases, on the one hand, the width of the forbidden band and the value of Wb and, on the other hand, allows to locate the defects (electrons traps) at a greater depth in the forbidden band (between 1.9 and 2 eV from the bottom of the CB), all these features contributing to the improvement of the retention properties of the memory [KIT 09]. Much research, with the increase in the integration density of these memories still in sight, is turning to oxides of even higher dielectric constant than alumina. For certain hafnium and rare earth oxides, in particular, those of scandium, lanthanum and dysprosium alloyed to Al, have dielectric constants ranging between 10 and 30, which offer new paths for research in this field [KIT 09]. 2.3.2. Flash memories In contrast to EEPROM memories from which they are derived, Flash memories, due to a different connection method, can simultaneously be erased in packets. This erasing method is at the origin of the name “Flash”; the fact that they are generally faster than EEPROMs allows a greater number of applications. Invented in the 1980s by Masuoka [MAS 85] at Toshiba, they became a considerable commercial success and currently represent a large part of the market in the electronic components industry10.

9 In general, FG and CG are made of thin n+ poly-silicon crystal layers that are highly conductive (poly-Si). The insulator between FG and CG is defined as the inter-poly dielectric (IPD). 10 In 10 years, between 1995 and 2005, the annual global Flash memory market went from 1.86 to 18.57 billion dollars [YIN 07] to reach around 20 billion dollars in 2009.

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It is from two universal NOR and NAND logical functions that other logical functions can be carried out such as OR, AND and NOT, corresponding to the three Boolean algebra operations that are disjunction (OR), conjunction (AND) and negation (NOT). For example, the OR and AND functions are obtained by putting the NOT function in series with the NOR and the NAND, so that NOR + NOT →OR and NAND + NOT →AND. These different functions are represented by the symbols:

where A and B are the two inputs ‘0’ and ‘1’ corresponding to greater or smaller analogical potential values, respectively. The correspondence between A and A means that if A = ‘1’ or ‘0’, A = ‘0’ or ‘1’. These logic functions can be carried out with integrated electronic circuits based on p and n MOSFETs (p-MOS and n-MOS). The electronic circuits equivalent to logic gates NAND and NOR, with their corresponding truth tables, are made by coupling n and p MOSFETs in series or in parallel to the source voltage S.

Box 2.3. NOR and NAND logical gates

This success is due to the fact that their connection mode leads to high integration densities, which considerably reduces the manufacturing cost per memory cell. Their tolerance to shock, that

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makes them suitably mobile, has encouraged their incorporation into numerous devices of everyday life (cameras, smartphones, computers, computer tablets, robotic instruments, medical devices, video games, etc.) making them more advantageous than HDDs. 2.3.2.1. NOR and NAND Flash memories Beyond the term for Flash memories, we distinguish two types of memories: NOR Flash and NAND Flash that differ in the nature of their cell connections, in parallel for NOR, and in series for NAND. This terminology, inspired by the NOR and NAND logic gates (Box 2.3), may be explained by noticing that in the NAND and NOR Flash arrays, the n-type transistors connected to the source line SL, which is equivalent to the low voltage of the NAND and NOR gates, are in series or in parallel, respectively, in the same way as for the NAND and NOR gates (Figure 2.14). The NOR memory array is addressed by random access, this meaning that each cell can be addressed individually, whereas for the NAND this is done sequentially, and achieved according to a block addressing procedure, combining a large number of memories. This leads to high erase speeds for NAND Flash and low ones for NOR. For reading, in contrast, the process is very fast for NOR but slower for NAND. The growth of NAND Flash on the market is more recent than that of NOR Flash but NAND Flash have now become much more important than NOR Flash. This is essentially due to the fact that the evolution of its characteristics in terms of integration density make it a data storage system that competes favorably with HDDs for portable devices. Due to this difference in properties, NOR Flash is especially used in the storage of coded computer data destined to be executed directly (XiP-type operation, “execute in place”) and has found applications in TV decoders, smartphones, computer tablets, motherboards and peripheral computer devices.

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Figure 2.14. Connection modes of NOR and NAND memory arrays: a) NOR Flash memory array, b) NAND Flash. BL: bit line; SL: source line; MC: memory; BLS: bit line select; ● contacts. In a) all the MCs are connected in parallel between a BL and a SL whereas in b) they are connected in series between the BL and the SL. Adapted from [TAL 02]

From the commercial point of view, the NOR Flash market is limited and much less significant than that of NAND Flash, primarily directed toward data storage. As opposed to NOR memory arrays, that have much lower erase speeds than NAND Flash and are not appropriate for the storage of large quantities of data, NAND Flash are now considered as solid state drive (SSD) memories which can replace HDDs in many areas. This is especially due to recent progress in the manufacture of MLC FG memories and charge trap memories (CTMs) that significantly increase the data storage capacity11. Also, their manufacturing cost has not ceased to decrease since their launch

11 The market for NOR memories, 10.3 billion dollars in 2000, has dropped to 5.5 billion, whereas the market for NAND Flash, that was negligible in 2000 (370 million dollars), has considerably and almost constantly increased, 14 billion dollars in 2009 [WON 13], an evolution corresponding to the explosion in the use of smartphones and other portable devices, which are important NAND Flash consumers.

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in the 2000s and, despite the fact that it is still high, it is getting closer to that of HDDs with a global turnover of over 20 billion dollars in 201212. 2.3.2.2. General organization of NAND Flash memories A NAND Flash chip (Box 2.4) is a unit made up of blocks gathered into planes (2,048 blocks per plane), into dies (2 planes), and then into a Flash chip (4 dies or 8 planes). The blocks can feature 16 kilobytes (kB), 512 kB, and up to several MB [WES 09]. The reason for this type of organization is to limit the number of connections. The four dies share a certain number of connection dots specific to the chip and each group of two dies has an operating autonomy similar to that of the chip [THA 09]. The block is the smallest unit capable of being erased and reprogrammed; a Flash chip has 16,384 of them. It combines a large number of memory cells connected to each other by word lines WL and bit lines BL. The memories connected to a same WL by their control gates CG constitute a “page”. A block generally contains 64 pages, numbered from 0 to 63, and each page has a very large number of memories (16,000 in the example of Box 2.4). The cells are also linked in series through their channels following horizontal lines, thus forming “strings” or bit lines. Each bit line is driven at its two extremities by two access transistors (themselves connected through their CGs to a “bit line selected” and a “ground line selected”). In the example presented in Box 2.4, each page contains 16,000 cells, i.e. a total of 1,024,000 memory cells for the block.

12 A recent report indicates that the price of an SSD-256 GB dropped by more than 70% in 3 years (September 2010–June 2013), going from 500 to 100–150 dollars, whereas during the same period, the price of a HDD-250 GB remained constant in the 30–40 dollar range [STO 14].

State of the Art of DRAM, SRAM, Flash, HDD and MRAM Electronic Memories

The selected example represents a 2 GB chip consisting of SLC memories gathered into blocks, planes, dies and chips. The block itself has a complex structure. It has 64 pages (numbered from 0 to 63) corresponding to the WLs (word lines) and a variable number of strings (bit lines, BLs), a function of the block size (in the example of the figure, the number of strings per block is 16,000). Adapted from [THA 09].

Note the presence of two selection transistor columns (“bit line selected” and “ground line selected”) allowing to address bit lines (signal In and Out – I/O) at the earth of the array, making all the memories of the same string communicate. The total capacity of the Flash chip is: 2 kB × 64 × 2048 × 8 = 2,097152 kB, equivalent to ~2 Gigabytes (2 GB). Adapted from [FAL 11]

Box 2.4. Organization of a 2GB NAND Flash array

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Due to the connection in series of the memories, the erase and program functions are operated according to a Fowler–Nordheim injection mechanism. The erase function is a global procedure that consists of the removal of all the charges stored in the FG of all the cells of the same block that then display bit ‘1’. This requires an instantaneous erase voltage of zero, applied to all the WLs at the same time as the bit lines are brought to a high voltage range of 15–20 V. It is this fast erasing for all the cells that is at the origin of the term “Flash”. The programming function on the contrary is done by “charging” the FG of a certain number of cells leading to the writing of ‘0’ bits. This is achieved by applying, on the one hand, a high voltage (15–20 V) to the WLs connected to the different cells and, on the other hand, by maintaining the voltage of the corresponding BL at 0 V. A cell bit can be read anywhere in the 16,384 blocks of a Flash chip. For this, the voltage of the corresponding BL is maintained at 1 V, and 4.5 V is applied to the WLs, except to the one to be read, to which 0 V is applied. The latter behaves like a switch for the current in the BL. If the FG of the cell is “charged” or “discharged” the current in the BL is null (bit ‘0’) or, on the contrary, non-zero (bit ‘1’), respectively. 2.3.2.3. Perspectives for Flash memories Fundamentally, their operation is identical to that of EEPROMs. Compared to the older EEPROMs, however, the storage capacity of Flash memory arrays has been slightly improved by the adoption of new architectures for the control gate and the floating gate, and more recently with the transition to the technology of “charge trap memories” (see Chapter 3). The non-volatile nature of the information after reading and the small energy consumption (see Chapter 1, Table 1.1) are without a doubt additional assets that have contributed to the development of NAND Flash.

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Technology based on the use of cells with FGs currently occupies a large part of the market, with the development of MLC memories that have allowed to considerably increase their capacity. Progress in terms of miniaturization is remarkable, as shown by the significant reduction in cell dimensions over a few years. The “halfpitch” (half distance between identical strokes of two adjacent cells) has evolved from 45 nm in 2008 to 22 nm in 2012. This progression is expected to continue until 2025 with a halfpitch that should reach 8 nm [ITR 11a]. This should increase the storage capacity of a NAND chip, currently of 64 gigabits (Toshiba, 2010) to 2 terabits (Tb) in 2025 in the case of SLC memories and to 4 Tb in the case of two-bit MLC memories [LIU 12]. According to the same author, this evolution should continue with the progressive replacement of floating gate memories by CTMs, the FG → CT transition being expected to occur around 2016, in addition to the expected adoption of 3D geometry, corresponding to the superposition of cells in successive layers. There could, however, be a limit to this progression in the coming years, due to the fact that the electronics industry favors a new standard for silicon-based logic circuits with a progressive decrease in the operating voltages from 5 V to 3.3 V, then to 1.1 V and eventually down to 0.5 V. Such small voltages are incompatible with Fowler– Nordheim mechanisms, and would require new structural arrangements, which obviously complicate the design of NAND Flash memories [JEO 12]. 2.4. Non-volatile magnetic memories (hard disk drives – HDDs and MRAMs) The ancestor of HDDs invented at IBM in the 1950s and commercialized as early as 1956 (IBM RAMAC 350), weighed more than a ton, cost more than 50,000 dollars and had a capacity of just 5 Mb. Currently, commercial HDDs have capacities that go beyond the Tb (equivalent to two hundred thousand times the capacity of the

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RAMAC), for standard dimensions of 3.5 inches (~9 cm) at a price of about 100 dollars. These numbers illustrate the distance travelled in the space of half a century. The principle is still described by the writing and the reading of magnetic domains recorded on a hard disk. It is the discovery of new phenomena, however, that has led to improvements in sensitivity and to extreme miniaturization of data storage. The 1988 discovery by Fert and Grünberg (2007 Nobel Prize for Physics) of “giant magneto resistance” (GMR), followed by progress on spin valves, led in the 2000s to considerably increase the storage capacity of HDDs, with a bit density close to the Tb/inch2 [NOZ 12]13. 2.4.1. The discovery of giant magneto resistance at the origin of the spread of hard disk drives It has been known for over a century that the resistance of a ferromagnetic material (iron, cobalt or nickel) varies by some % when the measurements are carried out in the presence or in the absence of a magnetic field (Lord Rayleigh). This variation in resistivity can be greatly amplified when the same experiment is carried out on a composite material consisting of successive layers that are alternately ferromagnetic (Fe) and nonmagnetic (Cr). This is giant magneto resistance (GMR). 2.4.1.1. GMR characteristics The experiment makes use of a very large number of ultra-thin Fe/Cr/Fe layers, each a few nm thick. The variation in resistance increases with the overall number of layers and decreases with the thickness of the non-magnetic layer: the thinner the better (Figure 2.15).

13 This density is equivalent to the presence of a bit approximately every 600 nm2, leading to a magnetic dot of dimensions 20x30 nm.

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Figure 2.15. Relative decrease in the magnetic resistance vs. the applied field for ternary layers Fe/Cr/Fe

COMMENTS ON FIGURE 2.15.– The indices 30, 35 and 60 represent the number of ternary Fe/Cr/Fe layers. The observed plateau for an applied field greater than Hs corresponds to saturation of the magnetization of the ferromagnetic layers. The experiment is carried out at low temperature and with strong magnetic fields. Note that the relative variation of the resistance becomes greater for a thinner Cr layer. Adapted from [BAI 88]. This variation in resistance can be explained by considering that the electric current through the magnetic layers consists of two channels of electrons with opposite spins. These two channels differ from one another in the electrical resistance that they encounter when going through a polarized ferromagnetic environment. The resistance is low when the electronic spins have the same orientation as the ferromagnetic spins (parallel spins); it is stronger when the spins are antiparallel. By considering that the coupling between magnetic layers is antiferromagnetic in the absence of a magnetic field (antiparallel

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orientation of the spins) and becomes ferromagnetic (parallel orientation of the spins) in the presence of the magnetic field, we can then qualitatively understand how the resistance depends on the applied field. In the case of parallel polarization of the ferromagnetic layers (parallel alignment of the spin orientations due to the applied magnetic field, Figure 2.16(a)), the current through the metallic layers follows a channel of low resistance r (oblique linear arrow), whereas in the case of antiparallel polarization (opposite orientations of the spins in the iron layers, observed in the absence of an applied field) each channel has a high resistance R (oblique broken arrow, Figure 2.16(b))14. This last diagram makes it possible to understand the relative variation of the resistance as a function of the applied magnetic field described in Figure 2.15. In the absence of a magnetic field, the ferromagnetic layers have opposite magnetizations (antiparallel spin orientation), which corresponds to the highest resistance of the multilayer. When the intensity of the external magnetic field increases, the spins of the magnetic layers are orientated parallel to one another, which leads to a decrease in the resistance of the multilayer, as shown in Figure 2.16(b). In fact, the GMR as it has just been described is still not well adapted to reading magnetic micro-domains. Indeed, the latter exert very weak magnetic fields of a few tens of oersteds only, when the magnetic fields necessary to cause a variation in the resistance of ferromagnetic layers, as described in Figure 2.15, are greater than 10,000 oersteds. The solution was found a few years later at IBM with “spin valves” that allow a GMR to be observed with very weak magnetic fields at ambient temperature [DIE 91]. 14 The resistance rp between two parallel magnetic layers is equal to rR/(r + R), that between two anti-parallel layers to rap = (r + R)/4. The GMR is defined by (rap - rp)/ rp, so that GMR = (R – r)2/4rR.

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Figure 2.16. Simplified diagram of a system of ternary ultra-thin layers iron/chromium/iron crossed by a current made up of two channels of + and – spins (oblique arrows): a) parallel magnetization of the iron layers noted+,+; b) antiparallel magnetization of the iron layers (noted – ,+). Adapted from [FER 12]

2.4.2. Spin valves The idea consists of replacing one of the magnetic layers, with strong coercive field strength (HC), with a layer of a soft magnetic material with a very low HC15. This implies that its magnetization (specific orientation of the electronic spins) can be inverted with a very weak magnetic field (20 to 40 oersteds) whereas the layer with a high HC maintains its original orientation (Figure 2.17). This therefore leads to the possibility of a GMR with very weak magnetic fields, on the same scale as those produced by the magnetic nano-dots on a HDD. The diagram in Figure 2.17(a) is an example of a spin valve, in which we notice: – a “trapped ferromagnetic” (FM) layer in strong interaction with another magnetic layer (FM trapping layer), both with high HC values which retain their magnetization in weak magnetic fields; 15 A magnetic material is characterized by two fundamental properties: the remanent field (HR) and the coercive field (HC), defined from a hysteresis loop that describes how the magnetization of the material varies with the applied field.

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– a “free” magnetic layer made up of a low HC material, the magnetization of which can change orientation in a weak magnetic field. This device has been found in the read heads of HDDs since 1998, after having been developed at IBM in the early 1990s. A new upgrade for spin valves was found a few years later with the replacement of non-magnetic metallic layers by a very thin insulating layer, through which the current can travel by the tunnel effect. The device, known as the “magnetic tunnel junction” (MTJ), has led to a considerable increase in the detection sensitivity of the magnetic dots in HDDs.

Figure 2.17. GMR of a spin valve. Adapted from [DIE 12]

FIGURE 2.17. – (a) The “free” ferromagnetic layer (free FM, NiFe) is able to couple with the trapped ferromagnetic layer (trapped FM layer) in a “parallel” or “antiparallel” way, the spin orientation of the latter being blocked by the upper trapping layer. The magnetization in the trapped ferromagnetic layer cannot be inversed with a weak magnetic field, as opposed to the magnetization of the free FM layer. (b) When the magnetic field applied to the spin valve changes its orientation and varies from -20 to 20 oersteds, the

COMMENTS ON

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spin valve switches from a configuration where the two ferromagnetic layers have the same spin orientation toward one where the spin orientation is antiparallel, this leading to a variation of about 16% in the valve resistance. 2.4.3. Magnetic tunnel junctions By replacing the non-magnetic metallic layer by an insulating layer consisting of a metal oxide (MgO and Al2O3), and by keeping the same arrangement between magnetic layers as with spin valves, the passage of the electric current from one magnetic layer to another occurs by tunneling through the insulating layer. Thus, in the case of the Co/MgO/Co MTJ, where MgO is an insulating crystal, ΔR/R can reach more than 400% at room temperature [YUA 06]. On account of this increase in GMR, MTJ devices progressively began to replace spin valves in the read heads of HDDs. 2.4.4. Operational characteristics of a hard disk drive (HDD) The HDD and the read–write–erase head are conceived using a very high mechanical precision mechanism. Indeed, the read–write– erase device consists of one single component combining two elements, each of which has a specific function: read–write–erase of the magnetic information recorded (or to record) on the HDD (Figures 2.18 and 2.19). This read–write–erase head is designed so that it can move in a radial manner and very rapidly above the disk whilst remaining at a constant distance, close to 10 nm, from the surface of the disk. The disk rotates at speeds ranging from 7,000 to 10,000 revolutions per minute (rpm) (Figure 2.19). This sophisticated mechanical device

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allows reading and saving of the information found on the disk in the form of magnetic dots of sub-micrometric dimensions16.

Figure 2.18. Diagram of the characteristics of a read–write–erase head placed on a recording medium of a hard disk drive. According to [MOS 02]

FIGURE 2.18. – The write head has a GMR element that receives the magnetic flux emitted by a magnetic dot, the magnetization (longitudinal) of which corresponds to a bit ‘0’ or ‘1’. The write head is a tiny electromagnet that can print a specific magnetization ‘0’ or ‘1’ onto each dot. W represents the width of a track on the disk, B is the width of a magnetic dot recorded on the track, t is the thickness of the magnetic material and d is the distance that separates the read–write head from the track. COMMENTS ON

The ‘0’ or ‘1’ bits written on the hard disk, corresponding to two different states of magnetization, have dimensions of around 2,500 nm2 and can be read and written by the head at frequencies

16 For more technical details concerning the operating of HDDs the articles by Moser et al. [MOS 02] and McFadyen et al. [MCF 06] can be consulted.

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close to the GHz when the disk is rotating at 10,000 rpm17. In fact, the read and write speeds are limited by the sequential access of the data, making the effective read and write times correspond to half a disk rotation, thus 8 ms at 3,600 rpm and 3 ms at 10,000 rpm.

Figure 2.19. Diagram of a hard disk drive (HDD) equipped with two plates and two read-write heads. A plate is divided into tracks on which information is recorded into sectors and blocks. Adapted from [NOZ 12]

The surface densities of the data are 200 Gbit/inch2 with a theoretical maximum value of 1Tbit/inch2. This is an enormous progress, corresponding to an increase by 3 orders of magnitude compared to the first GMR HDDs produced in the 1990s [NOZ 12]18. This technological advance is the result of successive improvements, amongst which we find the use of coupled ferromagnetic layers in an antiferromagnetic way (AFC, antiferromagnetically coupled media) simultaneously developed by IBM [FULL 00] and Fujitsu [ABA 00] at the beginning of the 2000s. This reduces the transition width between two successive bits, thus

17 Considering that each magnetic dot is approximately 100 nm long and that it is recorded on a 6 cm diameter magnetic track, the passage from one dot to another at 10,000 rpm takes about 3 ns. 18 These integration densities correspond to magnetic cell areas of 0.5F2.

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improving the signal received by the read head and the thermal stability of the recording [MOS 02]. Replacing the longitudinal magnetization by a recording perpendicular to the plane (perpendicular magnetic recording (PMR)) is also an important improvement, developed by Hitachi in 2000 [TAK 00] and commercialized by Toshiba in 2005. It has allowed a significant increase of the recording density on HDDs, but has required an adaptation of the read heads [MER 05]. We must point out that reading the data in the case of HDDs is achieved in a sequential manner along the tracks on the plate. RAMtype random access is possible, however, if the write or erase operations of each MTJ cell occurs using a magnetic field created by two crossing-over current lines. This corresponds to “solid state” magnetic memories, without a moving part and with random access (MRAM). 2.4.5. Characteristics of a magnetic random access memory (MRAM) The magnetic cell is still an MTJ junction, but it is now incorporated into a network that has no moving part. The magnetic field necessary to reverse the spin in the low coercive field ferromagnetic layer is created with two orthogonal current lines. The MTJ magnetic cell is located between the two lines at their intersection (Figure 2.20). With their qualities of endurance to cycling and extremely high read and write speeds (switching times of a few ns), their characteristics are very close to those of DRAMs and SRAMs. Also, like Flash memories, they are non-volatile and can be driven using small voltages. Another property of interest is that they are insensitive to ionizing radiations, thus enabling very specific applications in fields such as spatial, military, medical, etc. This technique, however, presents a certain number of drawbacks. On the one hand, a high write–erase current is required to reverse the spin, which conflicts with the aim of optimizing energy. On the other

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hand, due to thermally induced magnetization instability, data retention properties are poorer when the size of the cells decreases and, moreover, write or read errors result from addressing mistakes [NOZ 12]. Though the technique is still being developed by certain industrial firms (Everspin, Freescale) for precise applications, and certain improvements have been made, such as writing with thermally assisted switching systems (TAS)19, its development as a universal memory cannot currently be envisaged, due to the previously cited handicaps.

Figure 2.20. Diagram of a magnetic RAM memory consisting of a MTJ-type magnetic cell. Adapted from [NOZ 12]

COMMENTS ON FIGURE 2.20. –

The device comprises two current lines perpendicular to each other that create the magnetic fields Hx and Hy and reverse the spin in the weak coercive field magnetic layer. The read function consists of measuring the difference in conductivity resulting from parallel spin/antiparallel spin commutation. It is 19 The TAS procedure consists of the local heating of the free storage layer so as to make magnetization switching easier, after which the latter is “quenched” through rapid cooling in its new state of magnetization. Heating is achieved by the Joule effect in a conductor located next to the storage layer. This technique has also been applied to HDDs by Seagate but by using the local heating produced by a laser beam [MEL 08].

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obtained by reading an electric current in the magnetic cell, itself driven by the opening (Off) or the closing (On) of a transistor. Another magnetic process, in which spin reversal is achieved by an electric current, is currently being studied and does not have the previously mentioned handicaps. This makes use of the spin torque transfer (STT) technique that, according to the ITRS [ITR 10, ITR 11a], can meet the criteria specific to a SCM class memory (see Chapter 3). 2.5. Conclusion The various properties corresponding to the different types of memories can be applied to precise functions. On the one hand, DRAMs and SRAMs have very short write and read times, within the range of a few nanoseconds, but are volatile and can only be exploited for logic operations. On the other hand, memories derived from CMOS technology, namely floating gate MOSFETs in NAND and NOR Flash memories, are non-volatile but much slower for the write and read tasks, and therefore are better adapted to data storage and archiving operations. In this last field, HDDs are still the most advantageous due to their far better storage capacities compared to Flash memories, and especially, looking at the current state of the technology, due to their much lower manufacturing costs compared to NAND Flash. In 2012, the ratio was 1 to 4 in favor of HDDs. In contrast, the read and write times, as well as the energy consumption per bit, are greater. This point is the most critical for the use of high-capacity servers that are very power-hungry, which must be installed near energy distribution centers. Table 1.1 (Chapter 1) presents these differences in the properties of the volatile (DRAMs and SRAMs) and non-volatile (HDD and NAND Flash) memories. It also indicates the directions future memory specifications will have to take in terms of execution speeds and storage density, these two parameters forming one of the most important aspects. This implies the exploitation of new physical means and phenomena, leading to binary variations of properties,

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operating on the basis of simpler architectures, especially with the use of dual contact memory cells located at the intersection between two orthogonal addressing lines (crossbar architecture). As will be shown in the following chapters, new systems, likely to lead to binary resistive phenomena, capable of being integrated into crossbar-type architectures and compatible with CMOS technology, are the object of active research and have already gone beyond the prototype stage. The most advanced, from the commercial point of view, include phase-change systems (PCRAM), ferroelectric DRAMs and resistive systems (RRAMs). Magnetic memories MRAM, with commutation speeds comparable to those of DRAMs, have a significant handicap from the dimensional point of view, thus limiting their commercialization; a more compact STT-MRAM technology should replace them in the near future. Systems with organic components are still a long way from finding suitable applications, but the possibility of using plastic and flexible devices at very low cost could orient them toward specific “niche” markets, such as that of sensors, for which execution speeds and mass data storage are not a priority.

3 Evolution of SSD Toward FeRAM, FeFET, CTM and STT-RAM Memories

The main SSD-type electronic memories (solid state drives) described in the previous chapter concerning dynamic random-access and magnetoresistive random-access memories (MRAMs) reveal some limitations concerning volatility (DRAM and SRAM), a poor endurance to cycling (Flash) or low integration density (MRAM). The use of new materials and different ways of applying physical phenomena have led to improvements in the performances of these memories. The replacement of the conventional dielectrics of DRAMs and FETs by ferroelectric (Fe) materials has led to FeRAM and FeFET memories, respectively. FeRAMs are already commercialized, and have performances close to DRAMs with the advantage that information is saved without the need for any refreshing process; FeFETs transform FETs into non-volatile memories and allow nondestructive reading of the information, but have retention times which are still too short. The replacement of the floating gate in Flash memories by an electron trap dielectric (charge trap memory (CTM)) is a significant simplification that noticeably improves the endurance to cycling. The spin torque transfer phenomenon induced by an electric current is a new means of reversing the magnetization in a ferromagnetic material. It constitutes a real progress and leads to

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much more compact, extremely fast and less power-hungry devices compared to MRAMs. 3.1. Evolution of DRAMs toward ferroelectric FeRAMs Beyond the generic FeRAM designation, two types of memories are identified, those derived from DRAMs in which the dielectric is replaced by a ferroelectric (FeRAM), and those derived from a MOSFET where a ferroelectric also replaces the dielectric associated with the gate of the transistor (gate dielectric) (FeFET). The former have already been produced industrially, whereas the latter are still at the prototype stage. 3.1.1. Characteristics of a ferroelectric material The discovery of barium titanate (BaTiO3) in 1945 by Megaw [MEG 45], the first dielectric material with easily exploitable ferroelectric properties, is at the origin of a new ceramic industry, based on metallic oxides, and identified as ceramic electronics. A whole series of new applications has been developed, in particular with the emergence of high capacity ceramic capacitors, mainly using BaTiO3 as the dielectric [SCO 07]. The use of ferroelectrics for the elaboration of memories is more recent, however, this being due mainly to the difficulty of depositing a crystallized ferroelectric thin layer on a silicon-based integrated circuit [SCO 89]. A ferroelectric material is a unique dielectric that, when inserted between the two electrodes of a capacitor and subjected to voltage cycles between +V and –V, has a characteristic symmetrical hysteresis polarization curve (Figure 3.1). This hysteresis polarization curve1 is characterized by the remanent polarizations PR, and –PR obtained at 0 V (when the applied voltage was previously brought to a very positive or a very negative value, respectively), and by the coercive field related to EC = VC/d 1 Polarization is measured by the density of electric charge appearing on each side of the capacitor.

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(d, thickness of the ferroelectric material), VC and –VC being the two potential values that define the changes in orientation of the polarization.

Figure 3.1. Hysteresis polarization curve of a capacitor with a PZT [Pb(ZrxTi1-x)O3] dielectric (approximate thickness 100 nm). The polarization in the presence of an electric field of 5 × 105 V/cm is 30 µC/cm2; it drops spontaneously to 15 µC/cm2 when the electric field is brought to zero. A coercive threshold of ±1 V is needed to reverse the direction of polarization (coercive field EC ~ 105 V/cm). Adapted from [MOA 95]

Commutation between the two polarization states is extremely rapid, requiring 100–200 ps for a PZT film a few hundred nm thick [LI 04, JIA 11]. This switching property and that of polarization retention in the absence of an electrical field are at the origin of a memory effect used in the conception of ferroelectric DRAM memories2.

2 Before entering into FeRAMs, ferroelectrics were especially used for their piezoelectric and pyroelectric properties. Ferroelectric piezoelectric ceramics are particularly useful in the conception of ultra-sound transducers, actuators for motion (AFM-STM microscopy), and capacitors with high capacities due to very high dielectric constants. For more details about the properties of ferroelectrical materials and their applications, see reviews by Damjanovic [DAM 05], Setter et al. [SET 06], Scott [SCO 07] and Schröder et al. [SCH 12].

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The PZT ceramic, one of the ferroelectric materials most studied for memory applications, is an ABO3-type perovskite that can be considered as a solid solution of lead zirconate and lead titanate. It has a strong remanent polarization (of the order of ±15 µC/cm2) as well as a high dielectric constant (between 300 and several thousand, depending on the preparation and doping process). This ferroelectric property is due to the fact that the crystal structure of PZT is modified when it is subjected to an electric field. This leads to the formation of dipoles aligned with the electric field and resulting from an asymmetrical distribution of the charges between the O2- ions and the Zr4+ or Ti4 cations. They change orientation when the polarity of the field changes, and this occurs at a threshold ± VC corresponding to the coercive field ± EC. The crystal structure of PZT is made up of a cubic subnetwork of lead ions (2+) and an octahedral subnetwork of oxygen anions (2-). The zirconium (4+) or titanium (4+) ions are located inside the octahedron formed by the O2- ions and can move to occupy two stable, off-center positions relative to the center of the octahedron, thus leading to the appearance of an electric dipole (Figure 3.2).

A2+: Pb2+ , Ca2+

O2–

B4+: TI4+ or Zr4+

Figure 3.2. Representation of the PZT crystal lattice. In an electric field the octahedral lattice formed by the oxygen atoms (gray spheres) undergoes a deformation that leads to vertical motion of the Ti4+ or Zr4+ cations (black sphere), either up or down, which induces an asymmetrical distribution of the charges. This new distribution of the electric charges is responsible for the appearance of an electric dipole. Adapted from [MOA 95]

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The remanent polarization (which disappears when the ferroelectric is heated above a critical temperature corresponding to the Curie point TC)3 results from the fact that the Ti4+ and Zr4+ cations occupy two stable positions inside the crystal lattice, and that an electric field greater than the coercive field must be applied to make them move in the opposite direction and produce a reversed polarization of the ferroelectric, properties that are exploited in FeRAM and FeFET memories. 3.1.2. Principle of an FeRAM memory A FeRAM memory is similar to a DRAM (1T,1C) memory and consists of a MOSFET-type transistor (1T) coupled with a capacitor (1CFe) the dielectric of which is a ferroelectric material (Figure 3.3).

Figure 3.3. Diagram of a FeRAM (1T,1C) memory. The transistor gate (MOSFET) is connected to a word line WL that commands access of the bit line BL to the ferroelectric capacitor (CFe), connected itself to a plate line PL. CBL represents the capacity of the BL when its voltage floats. Adapted from [KOH 05]

In contrast to the conventional DRAM where the voltage applied to one of the capacitor plates (PL, plate line) is held constant, in the present case the PL is polarized positively or negatively in order to

3 TC is a function of the chemical composition of the perovskite. For PZT, TC is lower than 350°C, and lower than 400°C for SBT (SrBi2Ta2O9).

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switch the polarization of the ferroelectric between values PR and –PR. As a result, to write the bit ‘1’ corresponding to the polarization PR, several brief voltage pulses are addressed simultaneously to BL, PL and WL. WL and PL are brought to VDD and 0 V, respectively, and the transistor gate is driven through WL, the effect of which is to close the circuit between BL and PL, leading to charging (PR) of the capacitor. The writing of ‘0’, corresponding to the other polarization –PR, is produced in a similar way by permuting the previous potentials of BL and PL. The reading of ‘1’ and ‘0’ is achieved from the remanent polarization states PR or –PR corresponding to the representative points A and B, respectively, of Figure 3.4. When the memory is in the ‘0’ state, corresponding to point A of the ferroelectric polarization curve, the capacitor is submitted to a voltage pulse ΔV that saturates the polarization (point C), giving an average current I1 equal to ΔQ1/Δt in the BL. If the memory is at the ‘1’ state (point B), the same pulse of potential ΔV produces in the BL an average current Io equal to (ΔQ1 + ΔQ2)/Δt, greater than the previous one, thus allowing to differentiate bits ‘1’ and ‘0’.

Figure 3.4. Reading the two bits ‘1’ and ‘0’. When the memorized bit is ‘0’ (point A), by applying a pulse ΔV to the capacitor, the polarization of the ferroelectric follows the path A→C →A and generates the current I1 = ΔQ1/Δt. On the contrary, when the bit is ‘1’ (point B), the same potential pulse ΔV gives the current I0 = (ΔQ1 + ΔQ2)/Δt corresponding to the path B→C→ A. Adapted from [FUJ 10]

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We note, as for classic DRAMs, that this method of reading unfortunately destroys the information initially stored. Whatever the recorded bit ‘0’ or ‘1’, the polarization after the ΔV pulse always returns to A, corresponding to bit ‘0’. This implies that the information which has been read must also be refreshed after reading. Moreover, the endurance to cycling is poor. The reason for this is that the electric field pulses of 105 V/cm (1 V for 100 nm of dielectric thickness), necessary to change the orientation of the remanent polarization, have a detrimental effect on the oxide-based ferroelectric. Indeed, the electric field causes chemical reactions that induce a loss of oxygen atoms at the ferroelectric/metal interface, leading to its progressive degradation (see Chapter 5). This phenomenon does not exist in the case of a classic dielectric capacitor where the electric charges are localized on the metallic electrodes. This explains why the number of read and write operations is limited (around 1012) whereas it is almost unlimited in the case of DRAMs [FUJ 10]. In 2012 Texas Instruments reported a much greater number of cycles, of the order of 1015 for a PZT-based commercialized product of the MSP430FR57xxFRAM series [THA 12]. Compared to a DRAM, this type of memory presents an undeniable advantage regarding energy consumption. Most of the refreshing operations are now suppressed due to the very high retention times, around 10 years at an ambient temperature of 85°C (norm required by the industry). In contrast to NAND Flash (see Chapter 2), which occupies a significant share of the market of electronic memories, the advantages of FeRAMs are considerable: 1) write and read are carried out with 1–4 V (for PZT), i.e. 10 times smaller than for Flash memories; 2) write speeds (switching times about 50 ns) are 100 times greater than those of Flash memories;

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3) the endurance, evaluated at 1015 read–write cycles (for an MSP 430 FR573x microcontroller, Texas Instruments) is incomparably better than that of NAND Flash memories that does not exceed 106 cycles [THA 12]. This last property relative to endurance, in addition to read and write speeds close to those of DRAMs, indicates that these nonvolatile memories are quick enough to execute logic operations usually performed by DRAMs and SRAMs. They are also capable of storing information over very long periods of time in the absence of power. In view of the quality of these memories, FeRAMs might appear to be universal memories. In fact, like DRAM memories, their integration density remains poor, and this results from the fact that the signal related to PR decreases as the cell becomes smaller [MIL 09]. Moreover, the technology for the deposition of perovskite in thin layers (PZT and SBT) remains delicate and costly. It requires high annealing temperatures in an oxygen atmosphere, a fact which tends to degrade the underlying metal electrode in contact with the ferroelectric. To avoid this drawback, the bottom electrode is covered with a conductive layer that prevents oxygen diffusion. Usually, this is achieved by depositing a Ru/RuO2 bilayer on the bottom electrode [JIA 07]. This complicates the general production of the memory and increases its manufacturing cost, which is far greater than that of NAND Flash, and lowers its chances for commercial application in the mass storage of data. However, they are commonly used for the elaboration of “robust” microcontrollers dedicated to specific applications, with storage capacities of several tens or hundreds of kilobits. Resistant to radiation, capable of withstanding high ambient temperatures, they are now incorporated into various pieces of equipment found in the medical field, are widely used in the automotive industry where they are associated with various sensors, and are also present in various communication and radiofrequency identification devices (RFID, transport cards, etc.).

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Despite its many advantages, a FeRAM memory still presents the same drawback as that of a classic DRAM memory, i.e. the destruction of the information after its reading and the need to re-write the data. This handicap disappears if the dielectric is replaced by a ferroelectric in a field effect transistor (FET). This kind of device is known as a FeFET transistor. 3.1.3. Characteristics of an FeFET memory A FeFET transistor works differently from a standard MOSFET. A brief potential pulse applied to the gate of the FeFET is enough to induce a permanent and constant current IDS over a very long period of time. This pulse, which is greater or less than the coercive voltage ±VC, provokes a constant polarization ± PR of the ferroelectric that induces the source-drain current, the magnitude of which, a function of the state of polarization of the ferroelectric, constitutes a memory state that can be read without destruction of the information. The structure of an FeFET is fundamentally the same as that of a conventional MOSFET. The only difference is the replacement of the insulating dielectric by a ferroelectric film. In addition, to avoid interdiffusion of elements between the Si and the ferroelectric during annealing operations, which is detrimental to the good running of the transistor, a thin insulating buffer layer 4 nm-thick, generally a hafnium-based oxide (HfAlO or HfO2)4, is introduced between the ferroelectric and the semiconductor. This gives MFeIS-type (Figure 3.5) or MFeIMIS-type structures (M: metal; Fe: ferroelectric; I: insulator; S: semiconductor) [ISH 09]. As for FeRAMs, the most commonly used ferroelectric materials are PZT and SBT (SrBi2Ta2O9). PZT is used for its strong remanent polarization (PR) and SBT for the low values of its coercive field EC, which in the latter case make it possible to reduce the voltage required for writing. 4 The thin layers of HfAlO and HfO2 are deposited by evaporation, then annealed at 800°C in an oxygen atmosphere, which slightly improves the retention time of the device [ISH 09].

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The advantage of the system compared to a conventional MOSFET is that, after application of a gate potential VGS > VC (corresponding to the coercive field of the ferroelectric), the channel at the Si/insulator interface becomes conductive, and the information (bit ‘1’) is maintained when the gate potential is removed. It can be erased and changed into bit ‘0’ by applying VGS < –VC. Figure 3.6 shows the IDS = f(VGS) curves for two FeFETs elaborated with BLT [(Bi,La)4Ti3O12] and SBT ferroelectrics (each 400 nm thick), deposited onto an insulating film of HfO2 (8 nmthick).

Figure 3.5. Diagram of an FeFET (MFeIS) including an n-type MOSFET. The figure shows the polarization of the ferroelectric corresponding to a positive gate potential (G). The electric field resulting from this potential makes the channel of the semiconductor conductive. The reverse polarization makes the channel nonconductive. Adapted from [TAK 10]

For each ferroelectric we observe a very high ratio between the currents IDS from the ON and OFF states. In the case of SBT, this ratio is around 105, for a gate potential of 0.8 V. It remains very high and equal to 200 when a write pulse is applied for just 20 ns, thus confirming the ferroelectric origin of the hysteretic curves in Figure 3.6 [ISH 09].

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Figure 3.6. IDS = f(VGS) characteristics of a FeFET transistor of MFeIS structure. The channel (p-type) is 5 µm long, 50 µm wide. The SBT and BLT ferroelectrics are 400 nm thick, the insulating HfO2 layers are 8 nm thick, VDS = –0.1 V. Adapted from [ISH 09]

3.1.3.1. Retention characteristics The retention of the polarization of the ferroelectric is not as good, however, as we might imagine. The insulating buffer layer necessary to avoid inter-diffusion between the Si and the ferroelectric unfortunately has a doubly detrimental effect. On the one hand, the gate voltages have to be greater due to the presence of an additional insulator and, on the other hand, the retention times fall considerably due to the presence of a depolarizing electric field [WUR 73]. This is equivalent to introducing an additional capacitor C in series with that of the ferroelectric CFe. As a result, when the power supply is off and the gate is put back to 0 V, the capacitor C discharges itself through the ferroelectric, producing an electric field opposite to that of the initial polarization. As a consequence, loss of polarization and information occurs progressively. To remedy this effect, the depolarizing field must be reduced as much as possible, i.e. the voltage difference at the terminals of the condenser must be as small as possible.

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Therefore, for a given charge Q (Q = CV), a high capacity is needed, this requiring a very thin insulating layer and a material with a high dielectric constant (εr). It is the reason why hafnium-based dielectrics have been chosen, since they have a good compatibility with Si and high permittivity, HfO2 and HfAlO oxides having dielectric constants of 16 and 19, respectively. Figure 3.7 gives an idea of the retention times observed with SBTtype or BLT-type ferroelectrics. For the SBT/HfO2 transistor, after 30 days the ON/OFF ratio is far greater than 103. Extrapolating from the curves up to 3 × 108 s (10 years) indicates that this ratio is still approximatively 100. It must be noted that these retention curves are obtained with a transistor of micrometric dimensions and, in principle, nothing currently prevents further miniaturization beyond the 20 nm scale. In fact, other constraints on the extreme miniaturization of FeFETs are to be taken into consideration and have been perfectly described in the ITRS 2010 evaluation report [TAK 10].

. Figure 3.7. Retention curves of two FeFET (SBT/HfO2 and BLT/HfO2) submitted to a write pulse of ± 10 V for 1 µs. IDS is then measured against time by maintaining the gate potential at 0.6 and 0.3 V for SBT and BLT, respectively, and with VDS = –0.1 V. Same transistor dimensions as those in Figure 3.6. Adapted from [ISH 09]

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Considering that for the memory to run well the gate voltage is distributed with 2/3 in the ferroelectric (SBT, εr > 300) and with 1/3 in the insulating layer (HfAlO, εr =19), this implies that the ferroelectric capacity is twice that of the insulating layer; hence the SBT layer is approximately 30 times thicker than that of HfAlO. As a result, for a HfO2 insulating layer of around 2 nm, the SBT ferroelectric layer must be about 60 nm, which is not enough to give good retention properties. Properties corresponding to retention averages (estimated in 2010 to be around 30 days) are obtained for SBT layers in the 300–400 nm range. Moreover, as a ratio of 6–8 is observed between the thickness and the lateral dimensions, this indicates that minaturization cannot go beyond 50 nm which, from an integration density perspective, is far less than that of NAND Flash. Despite the fact that perovskite FeFETs present undeniable advantages compared to NAND Flash (relatively low write voltages of 5 V instead of 15 V for NAND Flash, dissipation of energy 9 to 16 times smaller than that of Flash, high endurance to cycling [TAK 10]), they have not, as opposed to FeRAMs, led to commercial products. FeFETs are still at the prototype stage and research continues into improving their reliability and their retention properties. 3.1.3.2. Ferroelectric materials other than oxides? The search for materials other than the perovskites for making FeFETs is relatively old and the first demonstrations of feasibility of organic ferroelectric memories using fluoropolymers date back to the 1980s [LOV 83, YAM 86]. In particular, the recent interest in “all organic” electronics has led to the appearance of new research focusing for the most part on fluoropolymers. The copolymer, poly(vinylidene fluoride-trifluoroethylene), P(VDF-TrFE), is about 70% VDF and 30% TrFE (Figure 3.8). It is partially crystallized and ferroelectric in its natural state, and is the most commonly used organic material, due to its good

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ferroelectric characteristics that allow it to be considered for use in FeFET-type memories, referred to as ferroelectric organic FET (FeOFET).

Figure 3.8. Chemical structure of the copolymer P(VDF-TrFE). x and 1-x represent the molar fractions in monomer units VDF and TrFE. The most used commercial product is that for which x = 0.7

P(VDF-TrFE) has a strong remanent polarization between 5 and 10 µC/cm2, is very stable with time, has a high resistivity of 1012 Ω cm, and switching times close to 10 µs, much longer however than those obtained with perovskites (0.01 µs) [HER 11]. The Curie point for a copolymer of molar composition 70/30 is 118°C for a melting point of 144°C [MAO 10]. The ferroelectric nature of P(VDF-TrFE) copolymer is due to the fact that, in its crystal form, the carbon chain of the copolymer adopts a trans conformation, which aligns the dipole moments µ1 and µ2 of the corresponding monomer units CH2CF2 and CHFCF2 in the same direction, giving the dipole µ (Figure 3.9). When a sufficiently strong electric field is applied in the direction opposed to µ, the carbon chain makes a 180° rotation that orientates the dipole moment in the opposite direction (–µ). The advantage of organic ferroelectrics compared to perovskites is that the processes of elaboration of FeFET are simpler. They do not require high annealing temperatures, thus limiting the risk of interdiffusion of elements at the Si/Ferroelectric interface, which in the case of perovskites requires the insertion of an insulating buffer layer between perovskite and silica.

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Figure 3.9. Perspective view of fluorocarbon chain of P(VDF-TrFE) in its “transˮ conformation. The CH2CF2 and CHFCF2 monomers have dipole moments µ1 and µ2, respectively, which result in the overall dipole moment µ. In an electrical field opposite to µ, the carbon chain makes a 180° rotation that reverses the polarization of the polymer. Adapted from [HER 11]

This copolymer can also be deposited from solution, this being a favorable argument in terms of cost, and besides, makes it compatible with the conception of flexible components of the FeRAM and FeFET type [NAB 05, LIN 08, NAB 10]. Recent work reports promising performances and is deliberately oriented toward the constitution of “flexible” memories on plastic supports [HWA 12, BRE 13]. The possibility of making multilevel memory cells (MLC) has recently been demonstrated in an “all-organic” system where the semiconductor (p-type) is a poly(3-hexylthiophene) (P3HT) film (100 nm thick) and ferroelectric P(VDF-TrFE) film (700 nm-thick), all deposited onto a flexible polyimide substrate [HWA 12] (Figure 3.10). Tests have been made on a device of millimetric size and the gate voltages, very high, are between 80 and –80 V. The procedure consists of reading for VGS = 0 V the different resistive states of the polythiophene channel (VDS = –5 V) programmed by the gate voltage. As a result, after having applied four VGS values (–80, –50, –30, and +80 V) to the gate of the transistor (Figure 3.11) and after putting the gate back to 0 V, four different remanent polarization values are obtained. Each of them induces a different current IDS equal to IPGM, IIRS-2, IIRS-1 and IERS, respectively.

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These four values of IDS can be identified at the corresponding combinations of two bits ‘1,1’, ‘1,0’, ‘0,1’ and ‘0,0’.

Figure 3.10. Cross-section of the P(VDF-TrFE) ferroelectric FeFET with a P3HT channel. Adapted from [HWA 12]

Figure 3.11. Electrical characteristics of a FeFET memory with a P(VDF-TrFE) organic ferroelectric with a P3HT semiconductor. Adapted from [HWA 12]

COMMENTS ON FIGURE 3.11.– a) Hysteresis curves IDS = f(VGS) showing polarization retention of the ferroelectric when the gate potential is put back to 0 V. IPGM is the maximum remanent value of IDS after polarizing the gate at –80 V and its return to 0 V. IRS-2 and IRS1 are the currents IDS corresponding to two intermediary remanent states of the ferroelectric polarization when the gate polarization has been put to –50 and –30 V, respectively; ERS is the IDS value corresponding to the remanent value of the polarization of the ferroelectric after gate polarization at +80 V (erase operation). b) Display of the retention of four levels of memory corresponding to

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four different values of IDS read at VGS = 0 V after various potential pulses have been applied to the gate (–80 V, PGM; –50 V, IRS-2; –30 V, IRS-1; +80 V, ERS erasing). A similar device with thinner P(VDF-TrFE) films (about 100 nm), has also been made by using pentacene as the organic semiconductor. This leads to a considerable reduction in the switching voltages, which instead of the previous ±80 V are now around ±15 V [DAS 12]. Finally, the recent discovery of new organic ferroelectric materials such as diisopropylammonium bromide (DIPAB) must be mentioned. This is an ammonium salt that can be obtained through simple crystallization of the compound from water. Its ferroelectric properties are close to those of BaTiO3, especially in that it has a spontaneous remanent polarization of 23 µC/cm2 and a Curie point at 153°C (the salt decomposes at 247°C when its melting point is reached) [FU 13]. Its ferroelectric properties are far better than those of other organic polymers with, in particular, a coercive field value 100 times smaller than that of the classical ferroelectric fluoro-polymers and half that of BaTiO3, and has a high dielectric constant at frequencies of 1 MHz [BON 13]. Ferroelectricity based on hydrogen bonds, observed at low temperature, has been known for a long time. A new interest has arisen since the discovery of supramolecular networks resulting from combined intermolecular associations of hydrogen bonds and charge transfer complexes (CTCs). Hence, for the first time, it was demonstrated that it is possible to obtain supramolecular compounds with ferroelectric properties at room temperature [TAY 12]. Supramolecularity is obtained by using an electron donor and an electron acceptor, capable of associating in the form of a CTC. They also have lateral chains that are able to form hydrogen bonds between them, this reinforcing the stacking of the compound (Figure 3.12). The technique, referred to by the authors as “lock arm supramolecular ordering”, leads to perfectly organized supramolecular networks.

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The remanent polarizations remain modest, however, and do not go beyond 5–6 µC/cm2 at room temperature. Outstanding behavior was observed at low temperature with a supramolecular complex obtained between a diimide acceptor and a tetrathiafulvalene (TTF) derivative as donor. A remanent polarization of about 50 µC/cm2 is observed at 4 K but it unfortunately decreases at room temperature to reach 4–5 µC/cm2.

Figure 3.12. Example of a ferroelectric supramolecular charge transfer complex resulting from the association of an electron acceptor (diimide a) and an electron donor (tetrathiafulvalene b). Each compound has lateral chains terminated by OH groups capable of binding to each other by hydrogen bonds, which improve the crystalline organization of the network. Adapted from [TAY 12]

In conclusion, electronic memories based on ferroelectrics constitute a field that still remains very prospective, but that has already led to commercial applications in the case of FeRAM perovskite memories. Their performances approach those of conventional DRAMs concerning read and write speeds; their very high retention times and, especially, a remarkable endurance to cycling, make them far better than NAND Flash. In contrast, they remain poorer than the latter as regards integration density and, consequently, they appear to be especially well-adapted to the elaboration of integrated microcontrollers that do not require very large memory capacities, and for which there exists a significant and diverse market. The second type of memory, based on the concept of an FET, where the dielectric is replaced by a ferroelectric, is still subject to research focused essentially on improving the retention times, that barely go beyond a month at present. Research is orientated toward the all-organic, and is based on fluoro-polymers, which have a number of advantages with, especially, manufacturing costs that should be less than those with perovskites. The strength of the

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coercive field, which requires high operating voltages, is still a handicap to their development. Recent results on supramolecular compounds show that the search for new ferroelectric materials remains totally open and could reveal in the future other surprises capable of transforming the field of FeFET memories. 3.2. The evolution of Flash memories towards charge trap memories (CTM) The underlying idea is to remedy the fact that, when the dielectric that isolates the floating gate of a channel of a MOSFET deteriorates and induces a local leakage current, it is the whole gate charge that disappears. Replacing the floating gate by semiconductive or conductive nanodots, isolated from one another, overcomes this drawback. The merits of this concept were established for the first time in the 1990s by a team at IBM [TIW 96]. They showed that by replacing the continuous metal floating gate by Si nanocrystals 5 nm in diameter, immersed in the dielectric, a memory comparable to that of a floating gate MOSFET was obtained, but with much improved endurance to cycling, capable of withstanding about 109 read–write cycles, equivalent to one thousand times that of a traditional floating gate memory (Figure 3.13). Similar results have been obtained using germanium nanocrystals [KIN 01].

Figure 3.13. Diagram of a silicon nanocrystal (NC) MOSFET. The floating gate is replaced by a network of nanocrystals in which the electric charges can be stored and ejected by changing the control gate potential. Adapted from [TIW 96]

The technology used to achieve such a network of nanocrystals inside a dielectric is, however, quite complex and requires multiple

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evaporation and annealing operations [KIN 01]. For this reason this model has been practically abandoned. In contrast, the use of a dielectric containing atomic defects that act as electron traps is a much simpler concept, the behavior of which is similar to that of a nanocrystal MOSFET. Silicon nitride (Si3N4) is used to trap the electrons, giving it the properties of a virtual floating gate FG. Such a charge trap memory cell is obtained by intercalating a layer of Si3N4 between two insulating layers of SiO2, with a conductive layer of poly-Si as the control gate CG. The many electron traps contained in the nitride layer therefore play a role equivalent to that of an FG. The first SiO2 layer (“tunnel oxide”) is 2–5 nm thick, which allows the electrons coming from the channel to move by tunneling into the thicker insulating SiN layer and to occupy the traps located inside the forbidden SiN band. Electrons are transferred by applying a positive voltage to CG (Figure 3.14).

. Figure 3.14. Diagram of a charge trap memory cell. The SiN layer, equivalent to a floating gate, is a far more efficient charge store, and much greater retention times are achieved than with traditional FG memories. Adapted from [ZHI 10]

The advantage of this device compared to a conventional FG is that CG interacts directly with the electrons circulating in the channel. The shielding effect of the conductive FG is no longer observed and, as a

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result, the issue of coupling between CG and FG, a limiting factor in the problems concerning miniaturization, disappears. Replacing the poly-Si-based conductive FG by an Si3N4 layer, which is insulating and rich in electron traps (CTL, charge trap layer), also presents the advantage of storing the electrons in distinct areas of the insulator and, consequently, affords the possibility of creating cells with multiple bits. Such a device has been commercialized by AMD, followed by Spansion under the name “mirror bit flash memory”. Initially intended to improve the storage capacity and reduce the cost of NOR Flash, the system owes its name to the fact that the trapped electrons are located at the two extremities of the CTL (Figure 3.15). As for a usual FG memory, the injection of electrons in the CTL (equivalent to FG) corresponds to the write phase and is equivalent to hot electron emission. With the polarizations indicated in Figure 3.15(a) the charge is locally injected into the right-hand extremity of the CTL. The charge is located on the left extremity of the CTL by reversing the polarities of source S and drain D.

Figure 3.15. Diagram of a charge trap cell memory (CTM) of type “mirror bit” with two bits. Adapted from [LU 09]

COMMENTS ON FIGURE 3.15.– (a) Injection of hot electrons into the charge trap layer (CTL) corresponds to write (in the present case, the injected electronic charge is trapped in the right part of the CTL; the injection into the left part of the CTL is achieved by inversing the S and D voltages). (b) The charge located on the right-hand side of the

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CTL is erased by hole injection (+) by putting the source S Off and applying 11 V (VD – VG) between the drain D and CG. Erase, however, takes place differently and does not require the Fowler–Nordheim mechanism, as in a classical FG memory but, on the contrary, involves the localized injection of holes under the influence of an electric field. In the example of Figure 3.15(b), where the trapped electric charge is located on the right-hand side of the CTL, the source is disconnected (floating voltage), the drain is brought to about 5 V and the gate CG to approximately –6 V. When an electric field is applied, there is an injection of holes by tunnel transfer from band to band in the right-hand side of the CTL, which neutralizes the negative charges stored in this part of the CTL. When the polarities applied to S and D are reversed, the charges located in the left part of the CTL are erased. Bits located on the right and the left of the CTL are read by taking into account the fact that the left L and right R charges act differently on the channel current IDS and can therefore be distinguished from one another by applying different gate voltages and by choosing the direction of the current in the channel5. Figure 3.16 shows how the different combinations of two bits ‘11’, ‘01’, ‘10’ and ‘00’ can be read from the corresponding values of the operating thresholds of the transistor.

Figure 3.16. Reading the charges stored on the left L or right R extremities of the CTL. Adapted from [LU 09]

5 Experiment shows that the charge located on the left extremity of the CTL greatly increases VTh if the drain current is directed from D toward S, and is practically without any effect on VTh if the drain current is reversed (permutation of the polarities of D and S).

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COMMENTS ON FIGURE 3.16. – (a) State (11): no charge in the CTL, the operating threshold VTh of the transistor is about 1 V whatever the direction of the current in the channel. (b) State ‘01’: charges on the left extremity of the CTL. When IDS is directed from D toward S, VTh is about 4 V; if IDS is in the opposite direction (permutation of the D and S polarities) then VTh is about 2 V, the charges stored on the left have little influence on VTh. (c) State ‘10’: same reasoning for the charges stored on the right-hand extremity of the CTL. (d) State ‘00’): charges located at both extremities of the CTL. Whatever the direction of the current IDS, the operating threshold is around 5 V. This technology has several advantages over multiple layer FG-MLC memories. First of all, they are easier to manufacture than FG memories, hence lower production costs. There is also an improvement resulting from the replacement of FG by an insulating CTL, which eliminates problems arising out of the capacitive coupling between CG and FG (gate coupling ratio – GCR). The simplest system, known under the name of SONOS (Si, Oxide, Nitride, Oxide, Si), consists of alternating layers of Si, SiO2, Si3N4, SiO2, polySi (CG). The very small thickness (2–3 nm) of the insulating tunnel oxide layer (lower SiO2 layer) conflicts with the objective of good charge retention. Many improvements have been made, focusing mainly on the composition of the silicon nitride-based insulating layer (much thicker than the tunnel layer and the upper blocking SiO2 layer) as well as on the nature and the thickness of the tunnel layer. This has led to similar devices, commercialized under distinct names by several companies, the aim being to miniaturize beyond 30 nm, which is a challenging dimension for devices with a planar structure6. The transition from a planar structure to a 3D structure is one of the objectives that have been set by manufacturers to reach even

6 Spansion Inc. have already been producing mirror bit memory cells for about 10 years (NOR Flash memories) and are currently developing a 32 nm cell [THE 13].

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greater integration densities, particularly for NAND Flash memories (see Chapter 2, section 2.3), devoted to high density data storage. An entirely new technology needs to be put in place by progressively giving up planar technology, which is condemned to stagnate at 20 nm. Memory manufacturers engaged in this perspective (Micron, Samsung, SanDisk-Toshiba, SK Hynix, etc.) program the first productions to appear around 2016, with NAND Flash memory integration densities far greater than those currently produced [LAP 13]. 3.3. The evolution of magnetic memories (MRAM) toward spin torque transfer memories (STT-RAM) Previously, we showed that the current magnetic memories, operation of which is based on that of HDDs and MRAMs, with a magnetic tunnel junction (MTJ), consist of two ferromagnetic layers separated by an insulating layer through which the electrons move by the tunnel effect. One of the ferromagnetic layers is pinned with a fixed spin polarization whereas the other layer is a ferroelectric material with a weak coercive field (free layer), the spin polarization of which can easily be reversed by applying a small magnetic field. This spin inversion in one of the layers of the junction leads to a variation in the resistivity that is at the origin of the memory effect in HDDs and MRAMs (see Chapter 2, section 2.4). MRAM magnetic memories present considerable advantages over HDDs. Other than the fact that there is no mobile part, they have read and write speeds, as well as a resistance to cycling, that make them very comparable to DRAMs and SRAMs, with in addition a nonvolatility greater than 10 years, equivalent to that of Flash memories. In virtue of all these qualities, we might think that MRAMs satisfy the criteria required for a SCM class universal memory (storage class memory, see Chapter 1).

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Unfortunately, they have a serious handicap in terms of miniaturization. On the one hand, their area is between 20 and 30F2 [FON 06] and is far greater than for a DRAM (8F2). On the other hand, the reduction in the size of cells cannot be pushed very far, due to the fact that, very quickly, a degradation of the write, read and retention properties is observed, due to the thermal instability of the magnetization in the layer with a weak coercive field [NOZ 12]. It is especially this size criterion that makes high density storage impossible. From this perspective they are much poorer than Flash (4F2) and HDDs (0.5F2) memories, which are much more compact. This limitation can be overcome by exploiting the spin torque transfer phenomenon, an electromagnetic effect that makes it possible to reverse the magnetization by the simple action of a spin-polarized electric current, an elegant way of avoiding the leads necessary for the creation of a magnetic field. This is a double advantage: on the one hand, the electric circuit is considerably simplified and, on the other hand, the memory device can be made by crossing two current lines corresponding to a crossbar system with a small cell area. 3.3.1. Nanomagnetism and experimental implications A great many discoveries and observations regarding magnetic properties over the last decade concern nanostructures and owe a lot to the technological skills gained in the last few years in the making of ultra-thin magnetic or non-magnetic multilayers (a few nm), for which interface phenomena are key factors. The magnetic storage of binary information into a nano-volume V of matter requires that an energy barrier established between two states should be much greater than the ambient thermal energy, so as to obtain high retention times. Thus, to obtain a retention time greater than 10 years, the energy barrier, equal to KV (K: anisotropy constant

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expressed in energy/unit of volume) must be greater than 50–60 kBT (kB: Boltzmann constant) [CHA 07])7. From this relation, it can be deduced that every reduction in the volume V must be accompanied by an increase in K, which requires the application of higher fields for the write operation. The problem is particularly relevant in the case of MRAMs where the current lines that induce the magnetic fields cannot withstand current densities greater than 107 A/cm2, beyond which electromigration of the conductor occurs, leading to its destruction [CHA 07]. This implies that for a conductor 20 nm-wide and 10 nm-thick, capable of withstanding a maximum current of 0.02 mA, the magnetic induction created at a distance of 10 nm (minimal distance separating the MTJ cell from the conductive lead) is at the most 0.4 millitesla (mT)8. This is a value that is already too low to reverse the magnetization, which shows the obvious limits of the miniaturization for this type of memory [DIE 12]. The exploitation of spin transfer makes it possible to overcome these constraints. 3.3.2. Characteristics of spin torque transfer Spin torque transfer is a new concept that was theoretically developed at the end of the 1990s by Berger and Slonczewski [BER 96, SLO 96]. The authors show that the magnetization of a

7 There are two varieties of magnetic materials: isotropic and anisotropic. An isotropic magnetic material does not tend toward a preferred magnetization direction, whereas an anisotropic magnetic material presents a spontaneous magnetization according to a particular axis (easy axis) and two opposed directions. This presence of an easy axis is at the origin of the remanence and of the coercive field in the material. The orientation of all the magnetic domains along this axis leads to a stable state that can be reversed by applying an external field (coercive field) and energy consumption. 8 The magnetic induction B at a distance from a linear conducting wire with a current I is obtained by application of the Biot–Savart law (B = µoI/2πa).

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ferromagnetic environment can be modified by subjecting it to a spin-polarized electric current. Soon after, the phenomenon was observed and verified for the first time by Myers et al. for a sandwich structure Co/Cu/Co of nanometric dimensions corresponding to a spin valve [MYE 99]. The spin valve used to demonstrate the spin transfer mechanism consists of two cobalt ferromagnetic layers S1 and S2, separated by a thin non-ferromagnetic layer (Cu). The S2 layer has a fixed magnetization (pinned layer) and the S1 layer is an “adjustable” layer (free layer) (Figure 3.17).

Figure 3.17. Diagram of a spin valve consisting of ferromagnetic layers S1 and S2 separated from each other by a very thin non-ferromagnetic metal layer. S2 has a fixed magnetization (pinned layer) and S1 a free magnetization (free layer). Adapted from [MYE 99]

COMMENTS ON FIGURE 3.17.– The small arrows indicate the direction of the force applied on the magnetization vector in S1, a function of the direction of the current and of the orientation of the magnetization of S1 relative to that of S2: (a) and (b) correspond to the parallel

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magnetization of the S1 and S2 layers; (c) and (d) to antiparallel magnetizations. The theory predicts that the spin-polarized conduction electrons exercise a stress on the magnetic torque of the ferromagnetic layer S1 and that for a current above a critical threshold, the magnetization switches. Depending on the direction of the current, this switch leads to a parallel or antiparallel orientation of the magnetization of S1 relative to S29. When the magnetizations of S1 and S2 are parallel (Figures 3.17(a) and (b)), and when electrons flow from S2 to S1 (negative current from S1 toward S2), the configuration is stable. It is unstable in the opposite case where the electrons propagate from S1 toward S2 (positive current from S2 toward S1), this involving spin inversion in the S1 layer, leading to antiparallel magnetizations of S1 and S2. Similarly, when the magnetizations are initially antiparallel (Figures 3.17(c) and (d)), a negative current (electron flux from S2 toward S1) provokes an inversion of magnetization in S1 and leads to the parallel configuration of the magnetizations of S1 and S2. A positive current, however, maintains the magnetization in its initial state [MYE 99]. Exploitation of the spin torque transfer phenomenon considerably simplifies the conception of magnetic memories, since it becomes possible to command spin inversion in a ferromagnetic layer by the simple application of a spin-polarized electric current, thus allowing us to switch the magnetization in the absence of an external magnetic field. Another advantage, and not the least one, is the fact that the couple that provokes the switch is proportional to the current density, which means that the read current itself is proportional to the area of the magnetic structure. It can therefore be reduced by miniaturization without affecting the spin transfer effect [CHA 07].

9 A detailed description of spin torque transfer is given by Ralph and Stiles [RAL 08].

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Figure 3.18 shows two examples of magnetic switching in a spin valve, either by the application of a magnetic field (a), or by spin torque transfer (b). As expected, the variation in resistance (about 3%) is practically identical in the two cases, confirming the magnetic commutation by spin transfer in (b). We also note that in case (a) the variation of the magnetic field necessary for magnetization switching is about 40 mT, which implies a current of 20 mA for a geometry identical to that defined in the previous section, whereas for spin torque transfer, 0.4 mA is enough to cause magnetization inversion.

Figure 3.18. Comparison of magnetic commutation of a spin valve: a) by application of a magnetic field; b) by spin torque transfer

COMMENTS ON FIGURE 3.18.– The spin valve has a pillar-type structure with two ferromagnetic alloy layers of Ni81Fe19, separated by a Cu layer (12 nm-thick). The first ferromagnetic layer is a pinned layer (20 nm), the second (4.5 nm) is a free layer. The shift of the hysteresis curve R = f(H) relative to the origin of the magnetic field is due to the fact that the pinned layer is a magnetic bilayer with antiferromagnetic coupling. From Braganca et al. [BRA 05].

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3.3.3. Recent evolution with use of perpendicular magnetic anisotropic materials Significant progress has been observed in the operation of MTJ memories by replacing magnetic materials with in-plane magnetic anisotropy by materials with perpendicular anisotropy10. The main advantage of these materials is an anisotropy energy greater than for materials with in-plane magnetic anisotropy, which gives them a thermal stability of over 10 years, and also predisposes them for better miniaturization [MAN 08, MIR 11]. Ikeda et al. [IKE 10] have obtained particularly encouraging results for devices with MTJ memories of the CoFeB-MgO type. These materials, mostly used in the case of in-plane magnetic anisotropy, leading to an extremely high tunnel magnetoresistance ratio (TMR) (see Chapter 2, section 2.4.3), are also exceptional in that the orientation of their magnetic polarization depends on the thickness of the magnetic layers. For example, in the case of the CoFeB-MgO structure, when the CoFeB layer is 2 nm-thick, the in-plane magnetic anisotropy component is far greater than the perpendicular component, the opposite occurring when the CoFeB layer is 1.3 nm-thick. Ikeda et al. have produced relatively complex magnetic layers, incorporated within multilayer structures, composed of tantalum, ruthenium and of an iron, cobalt, boron (CoFeB) alloy of atomic composition Co20Fe60B20 (Figure 3.19). With the example of the cell represented in Figure 3.19, 40 nm in diameter, where the 1.3 nm-thick ferromagnetic CoFeB layer is inserted between two buffer layers Ta/Ru/Ta (bottom electrode) and Ta/Ru/Cr/Au (upper electrode), switching between the states of low and high impedance is obtained with a 1 ns current pulse of about 50 µA, i.e. a current density of 4 × 106 A/cm2, which is relatively 10 The magnetic anisotropy axis of thin magnetic layers can be perpendicular to the plane or in-plane, which corresponds to magnetization of the material perpendicular or parallel to the layer plane, respectively.

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small for this type of experiment. The resistance ratio between the states of low and high impedance is greater than two (15 kΩ and 34 kΩ). Moreover, the thermal stability of the system, defined by the magnetic anisotropy energy, is greater than 40 kBT, which ensures retention times of about 10 years at room temperature, with a high resistance to cycling typical of MTJ.

Figure 3.19. Example of a spin torque transfer MTJ (magnetic tunnel junction) cell with perpendicular magnetic anisotropy. The MTJ cell consists of an MgO insulating layer 0.85–0.9 nm-thick, sandwiched between two ferromagnetic layers CoFeB between 1 and 2 nm-thick. Perpendicular magnetic anisotropy is observed for CoFeB layers about 1.3 nm-thick. Adapted from [IKE 10]

In conclusion, with switching times in the ns range, small commutation currents (several MA/cm2), a magnetic anisotropy energy high anough to ensure retention times greater than 10 years with, also, a high TMR ratio (greater than 100%) and the capacity for high integration densities, CoFeB/MgO magnetic tunnel junctions

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seem to satisfy all the criteria required to enter the category of storage class memories in the near future. 3.4. Conclusions The different types of memories described previously (ferroelectric memories, charge trapping memories, spin torque transfer magnetic memories) each present advantages and disadvantages that restrict their use to particular applications. Ferroelectric memories (FeRAM and FeFET) fall into two distinct categories. FeRAM memories operate in a similar way to DRAMs (1T, 1C). They differ from them in the replacement of the dielectric by a perovskite-type ferroelectric, which removes the need for periodic refreshing that is a characteristic of common DRAMs, but does not prevent the read operation destroying the information. They have very high read and write speeds and high retention times. Their endurance to cycling is far better than that of NAND Flash and they have a good tolerance for aggressive environments. In contrast, the integration densities are far smaller than those of NAND Flash, which essentially limits their use to various microcontrollers. Field effect transistors FeFET, where the dielectric is also replaced by a ferroelectric material (perovskite), are built like a FET and are still at the research stage, especially for the use of organic ferroelectrics. They have electric characteristics comparable to those of MOSFET with, in addition, a memory effect induced by the remanent polarization of the ferroelectric, which allows a read procedure that is non-destructive of the information. Unfortunately, as for FeRAMs, the integration densities are low and the retention times are very short; currently they do not go beyond one month. They have many advantages, however, compared to NAND Flash memories: the write voltages are small (5 V instead of 15 V), the dissipation of energy is 9–16 times lower than for Flash and the endurance to cycling is 100–1,000 times greater. NAND Flash memories have a large share of the market and research continues with a view to increasing integration densities,

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implying the transition from planar technology (limited to 20 nm) to 3D technology, corresponding to a “vertical” architecture. The replacement of the floating gate by a dielectric acting as an electron trap (charge trap memory) is also likely to increase the performances of Flash memories. On the one hand, the endurance to cycling is improved; on the other hand, by removing the capacitive constraints of the FG-MOSFETs between the control gate and the floating gate, the 20 nm technological barrier is also removed, which should allow progress in the miniaturization of cells, the latter also having been adapted for the conception of multilevel cells. STT-RAM-type magnetic memories, based on spin torque transfer, seem to be able to reach the standards of a universal SCM memory. The technique allows to eliminate the magnetic fields and as a result greatly simplifies the connections while much increasing integration densities. According to the ITRS report [ITR 10], it is a memory that can be very easily integrated onto a chip of CMOS technology with the possibility of vertical integration that considerably reduces the cell area down to 4F2. Its use does not require high voltages, the switching times are short and comparable to those of DRAMs, and retention and cycling are typical of a MTJ device. Recent results on MTJ with perpendicular field anisotropy show that the densities are now within the 2–10 MA/cm2 range, resulting in commutation currents less than 50 µA for cell sizes of about 40 nm. From a practical point of view, the technology is complex, and requires the deposition of a great number of layers, which can be a handicap compared to other less costly technologies (HDD, Flash). Despite this, they represent a potentially enormous progress compared to MRAMs, where switching between states is achieved by an external magnetic field, and are close to meeting the requirements to qualify as SCM memories.

PART 2

The Emergence of New Concepts: The Inorganic NEMS, PCRAM, ReRAM and Organic Memories

4 Volatile and Non-volatile Memories Based on NEMS

In the late 1990s and early 2000s, progress in nanolithography led to the fabrication of sub-micronic electromechanical switches (nanoelectromechanical systems – NEMS). Well adapted for the detection of extremely small masses and capable of reaching sensitivity thresholds down to the attogram [ABA 01], they function as RF oscillators. Very high sensitivity electrometers [CLE 98], as well as field effect transistors (FET), were made by exploiting the electromechanical deformation of carbon nanotubes [MAR 98]. The additional possibility of creating electromechanical nanoswitches able to memorize two ON/OFF states corresponding to the opening/closing of an electric circuit provides an original perspective for the conception of new types of memories. Such memories have many advantages, such as the absence of leakage currents, excellent ON/OFF ratios and the ability to operate in harsh environments without damage (high temperatures, radiations). On account of the great progress made in the development of techniques in photolithography and electron beam lithography (EBL) these past few years, this research area presents an unquestionable

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interest for the conception of volatile or non-volatile memories1. This is especially confirmed by the demonstration of the ability to make mechanical devices with extremely complex architectures, and having oscillation frequencies ranging from 100 MHz to the GHz, which should provide switching times of a few nanoseconds. To make NEMS memories, many systems with different architectures comprising two or three electrodes have therefore been imagined. Loh and Espinosa [LOH 12] list about a dozen, each of which has a mobile part (cantilever, suspended bridge, carbon nanotubes) driven by electrostatic forces which can open and close an electric circuit or even modulate the current in a semi-conductor. 4.1. Nanoelectromechanical switches with two electrodes Two-electrode systems have been mainly described in two forms: 1) NEMS with a cantilever or a suspended bridge and a static electrode, between which a voltage is applied that triggers the closing or opening of the circuit, corresponding to ON and OFF states, respectively. 2) NEMS made of two crossed conductive nanotubes, one motionless and the other floating. The nanotubes are separated from one another at their intersection by a very small distance (from a fraction of a nanometer to a few nanometers), and can occupy two positions corresponding to two thermodynamicallystable ON and OFF states. These two states are identified by the tunnel current induced by a voltage applied between the two conductors.

1 For more information on lithographic techniques applied to the conception of MEMs and NEMs, one can consult the review article by Berman and Krim that gives a very detailed view of the various physicochemical deposition and etching methods for thin layers of materials, used in the 3D assembly of different components [BER 13].

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4.1.1. NEMS with cantilevers These are nanoswitches of submicronic dimensions, the ON and OFF states of which are induced mechanically by a cantilever (suspended beam) and correspond to the closing and the opening of an electric circuit. 4.1.1.1. Operation and memory effect of an NEMS with a cantilever Typically, a cantilever-equipped nanoswitch consists of a suspended titanium nitride (TiN) conducting beam about 300–400 nm long, lying above a static electrode (TiN/W) at a distance of about 15– 20 nm (Figure 4.1).

Figure 4.1. Scheme of a nanoswitch with a cantilever (suspended beam): a) perspective image. Titanium nitride TiN is chosen for its low resistivity (20 µΩ cm), its high Young’s modulus (600 GPa) and its chemical inertness. b) SEM image from above. Adapted from [JAN 08a]

The bottom electrode (BE), brought to a voltage V, and the cantilever (maintained at 0 V) make up the two plates of a capacitor and are submitted to an electrostatic force F, equal to: F = ½ ε0εr AV2/x2 where: – εr is the dielectric constant (relative permittivity) of the air that separates the cantilever from the BE, ε0 the permittivity in vacuum; – A is the effective area of the capacitor plate; – V is the voltage applied between the cantilever and BE;

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– x is the distance that separates the cantilever from BE2. When a voltage Vo is applied between the cantilever and BE, the attractive force F becomes greater than the elastic force of the cantilever. The effect is to close the circuit between the two electrodes. With the previously described NEMS, 14 V must be applied to close the circuit between the cantilever and BE. An abrupt increase in the current of 10–14 A (open circuit) to 10–8 A (closed circuit) is then observed, for a ∆V of only 20 mV, which corresponds to a variation of about 3 mV per decade3 (Figure 4.2).

Figure 4.2. Obtaining the two ON and OFF states by closing (pull-in) and opening (pull-out) for the cantilever-electrode circuit. The NEMS used is that of Figure 4.1. Adapted from [JAN 08a] 2 The force F is calculated from the electric energy W = ½ CV2 (C: capacitance = εr ε0 A/x), from which we determine F = – dW/dx = ½ εr ε0AV2/x2. This formula implies that as soon as the electrostatic force is slightly greater than the restoring force of the cantilever, the latter immediately comes into contact with the BE, due to the fact that a very small decrease in the distance x considerably increases the electrostatic force. 3 The value of the current at closure is limited to around ten nano-amperes (compliance current) so as to avoid the deterioration of the contact surfaces between the cantilever and BE. Local current densities can be very high due to the existence of point contacts at the irregular surface which lead to significant localized Joule effects. This could be at the origin of intermetallic fusion leading to an erratic behavior of the cantilever.

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Return to the initial state, however, is very different in voltage and occurs at 8 V. This apparent anomaly can be explained by the presence of adhesive forces between the cantilever and the electrode that add to the electrostatic attraction forces. The endurance of the system has been tested with hundreds of closing–opening cycles by applying an alternating voltage of 15 V at a frequency of 5 Hz. After 300 cycles, the random variation of the voltage corresponding to the closing of the circuit remains below 1 V and there is no degradation in terms of the operation of the NEMS [JAN 08a]. We must note, however, that the ON state (closing of the circuit) is volatile and can only be conserved if the voltage between the cantilever and BE is held constant. The OFF state (opening of the circuit) corresponds to the stable state of the NEMS; it does not require the application of a voltage, and can therefore be considered, as opposed to the ON state, as being nonvolatile. 4.1.1.2. Description of the elaboration technique The conception and realization of a cantilever (suspended beam) requires several depositing and etching operations of various materials, based on conventional CMOS technology used for the elaboration of integrated circuits. Figure 4.3 shows how a specific NEMS can be made according to this technology. Various etching operations are also used to structure the component. The STI (shallow trench isolation) technique, currently used in the fabrication of integrated circuits to isolate the transistors from one another, makes use of this kind of combined procedure. It consists of digging networks of trenches into the silicon that will then be filled in by one or more insulating dielectrics (generally SiO2), with the possibility of removing the excess with a technique of chemical etching (CMP) that keeps the surface planar.

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Figure 4.3. Simplified description of the different steps in the making of a suspended cantilever NEMS. Adapted from [JAN 08a]

COMMENTS ON FIGURE 4.3.– (a) Deposition of four successive layers on a silicon substrate: SiO2 (insulating layers, obtained by thermal oxidation of Si, thickness 30 nm); tungsten (W, bottom electrode, 30 nm); poly-Si (sacrificial layer, planned to be etched away to create the space between the cantilever and the bottom electrode, 20 nm); Si3N4 (a temporary protective layer, 150 nm thick). (b) Elaboration of the word line WL with the shallow trench etching (STE) technique: the lateral dimensions of the tungsten electrode are reduced by etching the different layers. (c) Lateral insulation made by depositing SiO2 followed by chemical and mechanical polishing (CMP) that ensures the planarity of the surface. (d) After etching of the residual Si3N4 layer, the cantilever is elaborated by depositing TiN by evaporation (black) and is protected by a new layer of poly-Si.(e) The layers of poly-Si are removed, thus producing a space of 15 nm between the cantilever and the bottom electrode.

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To make a very small space between the cantilever and the bottom electrode, the prior deposit of a sacrificial layer of controlled thickness is required (generally of poly-Si), which is then removed by chemical etching [JAN 08a]4. Several manufacturing details are particularly important to get a cantilever which runs correctly (Figure 4.4).

Figure 4.4. SEM cross-section of the suspended cantilever NEMS obtained after oxidation and annealing of the bottom electrode. Adapted from [JAN 08a]

COMMENTS ON FIGURE 4.4.– The titanium nitride cantilever (TiN, approximately 300 nm long, 30 nm thick) is conductive and is at a distance of 20 nm from the bottom electrode. This electrode is protected by a superficial oxidation layer (8 nm thick, not visible on the photo) that prevents sticking between the cantilever and the electrode. A tilted cantilever (not desirable for the running of NEMS) is produced in the absence of annealing (bottom-left part of the figure). Jang et al. [JAN 08a] mention in particular the need to coat the bottom electrode with a thin annealed oxide layer (8 nm thick), which prevents the cantilever sticking onto the bottom electrode and

4 Chemical etching is a technique commonly used in microelectronics. It allows us to create spaces in objects of diverse shapes. In the present case, the superficial layer of poly-Si can be dissolved using a specific wet etching product such as HNO3/H2O/HF or NH4F [WIL 96].

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reducing the current between the cantilever and this electrode when the contact is on. 4.1.2. NEMS with suspended bridge New architectures that require switching voltages below 1 V have very recently been suggested. Lee et al. [LEE 13] have built an NEMS that they compare to a pipe clip structure (Figure 4.5).

Figure 4.5. a) Perspective view showing contact points between suspended electrode and bottom electrode BE. The suspended electrode SE facing BE is 1.4 µm long and 300 nm thick. b) SEM image. c) Cross-section. The thickness gf of the air layer that separates SE from BE is around 50 nm; when the U-shape of the SE is taken into account, the distance gs from one extremity of BE to one of SE is only 4–10 nm. Adapted from [LEE 13]

As for the cantilever system, the suspended bridge NEMS operates with two electrodes, separated by a thin air layer, less than 10 nm thick. The top electrode, in the shape of a pipe clip, is mobile. It is anchored on an insulating support at its two extremities and is suspended like a bridge over the bottom electrode that, on the contrary, is motionless. The authors show that when the gap gs between the two electrodes is about 4 nm, commutation between the ON and OFF states occurs

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for an applied voltage of only 0.4 V instead of a dozen volts for a 10-nm gap. The ON/OFF ratio is then greater than 105, the currents between the ON and OFF states are 10-7 and 10-12 A, respectively, and the switching time is about 60 ns. As for the previous cantilever system, the ON state is volatile: it disappears as soon as the voltage between the bridge and the bottom electrode is removed. In terms of endurance, the authors do not mention tests going beyond about twenty cycles, and the current measured for the ON state is very unstable. This lack of stability is attributed to the fact that the voltage drops when contact is made. This voltage drop weakens the electrostatic attraction, and should lead to a rupture of the contact, which, however, is maintained by the additional attractive forces resulting from the “adhesive” contact between the bottom electrode and the suspended electrode. This can explain the unstability of the ON state and a series of random oscillations. 4.1.3. Crossed carbon nanotube networks The system, which is very different from the previous NEMS, consists of a double network of carbon nanotubes aligned in two rows that are perpendicular to each other, one of them floating and without electric contact with the nanotubes of the other row (Figure 4.6(a)). They run like a bistable switch which oscillates between two thermodynamically stable positions through electrostatic attraction. Each of these positions corresponds to a tunnel current, thus allowing two ON and OFF states to be differentiated. Such a system was made and tested for the first time by Rueckes et al. [RUE 00]. The first network consists of CNTs, parallel to each other, placed over a Si/SiO2 subtrate and each connected to a metal electrode (nanodots 1 and 2).

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The second network is also made up of parallel CNTs connected to electrodes 1’ and 2’. They are placed perpendicular to the CNTs of the first network and rest on supports (insulating dot array). The spacing between CNTs at their intersection is very small (about one nanometer or less, see Figure 4.6(b)). The total interaction energy ET at the intersection between the carbon nanotubes is given by the relation: ET = EVdW + EElas + E Elec, where EVdW is the van der Waals energy, EElas is the elastic energy, EElec the electrostatic energy.

Figure 4.6. a) Perspective view of double network CNTs each linked to separate electrodes 1, 2 and 1’, 2’. The second network, placed perpendicular to the first, is suspended above the nanotubes of the first network and lies on insulating supporting dots. b) Disposition of two CNTs relative to each other at their intersection in the OFF and ON states resulting from a voltage applied between nanotubes 2 and 1’). Adapted from [RUE 00]

The energy curves corresponding to the region of intersection between the two CNTs have been calculated [RUE 00]. The authors show that in the absence of electrostatic coupling (V1 = V2 = 0 V), there are two stable energetic minima at room temperature, separated from each other by an energy difference greater than 10 kBT (curves V1 = V2 = 0 V, see Figures 4.7(a) and 4.7(b)) and corresponding to two states, ON and OFF.

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The gaps at the intersection between the CNTs are 0.3 nm and 1.5 nm in the ON and OFF states, respectively. When the voltage applied between two CNTs is modified, the energy curves clearly show that in the case of electrostatic attraction (V1 and V2 of opposite sign) the system evolves toward the ON state, corresponding to a gap of about 0.3 nm (Figure 4.7(a)). In contrast, in the case of an electrostatic repulsion (V1 and V2 of the same sign) the system evolves toward the OFF state, corresponding to a gap of about 1.5 nm (Figure 4.7(b)). The ON and the OFF states can be easily identified by measuring the corresponding tunnel current I given by: I ~ exp(-βd), where β is the attenuation constant (2Å-1) and d is the distance in Å between the two carbon tubes at their intersection.

Figure 4.7. Energy curves at the intersection between the two CNTs, 1 and 2. The curve for which V1 = V2 = 0 V corresponds to the sum of the elastic (EElas) and the van der Waals (EVdW) energies. a) Application of positive and negative potentials between two CNTs lowers the energy corresponding to the ON state, and as a result improves the stability of this state compared to the OFF state. b) The application of positive voltages between two CNTs increases the energy of the system and favors the OFF state of lower energy. Adapted from [RUE 00]

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For small voltages ranging within ±0.3 V, the tunnel current measured for the ON state varies quasi-linearly with the voltage. The resistance, calculated from the slope of the linear part of the I = f(V) curve, is 112 kΩ (Figure 4.8(a)).

Figure 4.8. a) Current versus voltage in the ON and OFF states, measured at room atmosphere. b) variation of the resistance between two crossed CNTs and for several switches carried out at ± 5 V (ON) and at 40 V (OFF). Adapted from [RUE 00]

In the OFF state, the current is negligible (about 10 pA between 0 and 0.4 V) with a corresponding resistance of 1 GΩ, i.e. 10,000 times that of the ON state (Figure 4.8(b)). Switching between ON and OFF states is reversible but requires high voltages: ± 5 V for the ON state, 40 V for the OFF state [RUE 00]. However, it must be noted that this system is “semi-volatile”. 4.2. NEMS switches with three electrodes A third static electrode, similar to a transistor gate, is introduced into the previous two-electrode NEMS and confers on these systems a certain analogy with an FET. This electrode controls the movement of the mobile part of the NEMS that can be either a cantilever or a suspended bridge. It also determines, in fine, the strength of the current flowing between two electrodes that are similar to the source S and drain D electrodes of an MOSFET.

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4.2.1. Cantilever switch elaborated by lithographic techniques The cantilever is conductive, flexible and connected at its extremity to an electrode S. The gate electrode G lies just below the cantilever. When a voltage is applied between G and the cantilever an electrostatic attractive force is produced that leads to contact between the cantilever and D, and the closing of the circuit between S and D (Figure 4.9(a)). Compared to the system using two electrodes, the difference lies in the fact that G, located below the cantilever, is not in contact with the latter. The electric circuit is established between D and S, and the current IDS varies from “all” to “nothing” depending on whether the S-D circuit (source-drain) is closed or open. Figure 4.9(b) shows the brusque increase in IDS when a voltage VGS = VON is applied between G and the cantilever, involving contact of the latter with D. The transition between the OFF (open circuit) and ON (closed circuit) states corresponds to a variation in VGS by a few mV for a decade in IDS, which is by far smaller than the subthreshold swing of an MOSFET transistor5.

Figure 4.9. Characteristics of a “capacitive” three-electrode nanoswitch. Adapted from [ITR 10]

5 The slope S = dVG/d(logIDS) defined as the subthreshold swing of an MOSFET transistor below the operating threshold VT is a function of the gate/oxide capacitance and that of the depletion layer. It is equal or greater than 60 mV per decade (see Chapter 2 [KIN 03]).

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COMMENTS ON FIGURE 4.9.– (a) Scheme of a capacitive threeelectrode NEMS. The plates of the capacitor consist of a cantilever and a static electrode G separated by an insulating air layer (dielectric). The electrostatic force applied to the cantilever connected to the source S closes or opens the circuit between S and D. (b) Curve IDS = f(VGS). For a voltage VON applied between G and S, the cantilever comes into contact with D which provokes a rapid variation in IDS. When the voltage of G is lowered to VOFF, the switch is opened which results in a drop in IDS. The VGS/IDS slope (subthreshold swing) when the circuit is closed is almost nil. When the gate voltage is lowered to VOFF, the restoring force of the cantilever becomes greater than the electrostatic and adhesive attractive forces, entailing the return of the cantilever to its initial position. This leads to the opening of the circuit between S and D, which is marked by an immediate drop in IDS (Figure 4.9(b)). A similar system suggested by Lee et al. is capable of operating at very high temperatures (such as 500 °C) thanks to the use of a refractory material such as silicon carbide [LEE 10]6. The device, used to make a voltage inverter, combines two cantilevers connected to a high voltage VDD and a low voltage VSS (Figure 4.10), and is comparable to a CMOS inverter (see box 2.1, Chapter 2). When a positive voltage (equivalent to logic state “1”) is applied to the input of the invertors, the switch (2) closes and links the output to the negative voltage VSS (equivalent to logic state “0”). On the other hand, when a negative voltage is applied to the input (logic state “0”), it is switch (1) which closes and links the output to the high voltage VDD (logic state 1) (Figure 4.10(a)).

6 Silicon carbide (SiC) has already been used as semi-conductor in the conception of field effect transistors designed to operate at high temperature. Its sublimation temperature of 1,800°C is a guarantee against any risk of melting by the Joule effect [PAT 09].

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Figure 4.10. Electromechanical voltage inverter: a) electrical diagram of NEMS device composed of two nanoswitches (1) and (2) connected to the high VDD and the low VSS voltages, respectively. b) SEM image of the NEMS and the two cantilevers. c) Enlarged SEM image of the contact zone of the nanoswitch (2) showing the gap (~150 nm) between the cantilever and the output contact. Adapted from [LEE 10]

The system has been tested at frequencies of 500 kHz and it withstands about 2.109 cycles without rupture of the cantilever (Figure 4.11). The driving voltage (±6 V) is much greater, however, than that used in classic CMOS inverters (about 3 V), but is comparable to that of CMOS devices operating at high temperatures [LEE 10]. The NEMS inverter is large (area around 8 µm2), but remains smaller than field-FET devices used at high temperatures whose dimensions vary between tens and hundreds of microns [PAT 09]. Though a memory application has never been considered, it is predicted from the characteristics of the inverter that a single SiCbased cantilever, similar to the previous system, could also operate as a “semi-volatile” memory at very high temperatures.

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Figure 4.11. Inverter response to an input of ± 6 V at 500 kHz. The switching time of the NEMS is estimated to be about 10 ns. Adapted from [LEE 10]

4.2.2. Nanoswitches with carbon nanotubes The purpose behind the use of carbon nanotubes (CNTs) for the making of nanoswitches is simple to understand. On the one hand, they are very light, and, on the other hand, they are characterized by extremely high Young’s modulus values. This leads to much shorter switching times than those obtained with nanoswitches made of silicon-based or other inorganic materials [KAU 06, JON 04]7. The main difficulty lies in their handling, particularly with the need to position them onto a substrate with precision and to connect them individually to an electric circuit. Many devices have been imagined and fabricated. Some are obtained by directly manipulating nanotubes on an inorganic substrate on which connection dots are arranged in regular and ordered arrays. Others, which are better adapted for automatization and integration processes, rely on the direct synthesis of carbon nanotubes in predefined locations of the surface. 7 Carbon nanotubes are known for their impressive mechanical properties that are far greater than those of materials such as steel or kevlar. Their Young’s modulus is around 1 TPa [PEN 08] which is five times greater than that of steel.

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4.2.2.1. NEMS memory with a carbon nanotube cantilever The operating characteristics are the same as those described for a cantilever made by lithography (see section 4.2.1). The device consists of a multiple wall carbon nanotube (MWCNT) connected to a source electrode S above a planar Si/SiO2 substrate at a distance of about 150 nm. Two gold electrodes, gate G and drain D, at 1 and 1.5 µm from the source, respectively, are deposited on SiO2 and aligned with the nanotube (Figure 4.12)8.

Figure 4.12. Diagram of a NEMS made of a carbon cantilever (MWCNT). S, G and D are the Au contacts of the source, gate and drain. After the carbon nanotube is placed on S, new Ti (5 nm) and Au (75 nm) deposits are made on S to ensure that a good electric contact is achieved between S and the nanotube. Adapted from [LEE 04a]

The nanotubes are synthesized by plasma-enhanced chemical vapor deposition (PECVD) [MOR 04]. They are dispersed into a solvent and are deposited onto S by the ac-electrophoresis technique. 8 Elaboration of the device comprises many steps. After deposition of the gold electrodes S, G and D onto the silica surface, a poly-methyl methacrylate (PMMA) layer is deposited by spin coating and its thickness adjusted on top of S. Carbon nanotubes are deposited on S and PMMA by ac-electrophoresis ([JON 03, CHH 01, ZHA 05]. Two titanium and gold layers are then deposited on the carbon nanotubes so as to improve their contact with S. The PMMA layer is then removed by plasma etching (O2-plasma), which, finally, fixes the carbon nanotube onto S [LEE 04b].

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When the polarization of the gate electrode G is changed, an attractive electrostatic force is exerted onto the carbon nanotube, which induces its displacement toward electrode D. For a sufficiently high gate potential, contact is made between the nanotube and D and, therefore, a significant variation in the current between D and S occurs, a fact which can be exploited for a memory effect. The main constraint, however, lies in the difficulty of reproducing the positions of the carbon nanotubes relative to G and D. This leads to differences in the ISD = f(VSG) curves from one component to another (Figure 4.13).

Figure 4.13. ISD = f(VSG) curves obtained for two different devices with VSD = 0.5 V. Adapted from [LEE 04a]

COMMENTS ON FIGURE 4.13.– (a) ISD = f(VSG) curves, obtained with two voltage cycles on a first NEMS device. The variation in current as a function of VSG is nonlinear as long as the voltage is lower than 20 V (which corresponds to a tunnel current); it is approximately linear and very unstable beyond 20 V. This may be due to the formation of poor contacts between the nanotube and D. (b) ISD = f(VSG) curves between 0 and 6 V, obtained with another NEMS device. Between 0 and 5 V, the nonlinear variation of the current is very small and is typical of a tunnel current (between 0 and 0.3 µA, region A). A sudden increase occurs at 5 V due to a first contact with electrode D (region B) followed by a second increase (region C) corresponding to a contact with electrode G. Despite favorable electromechanical features (high conductivity, small weight, high Young’s modulus), the poor reproducibility

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observed from one component to another underlines the difficulty of using carbon nanotubes as cantilevers to make electromechanical memories. On the one hand, the techniques used for preparation do not currently guarantee a perfect dimensional reproducibility of the nanotubes, and on the other hand, their positioning on a surface by spin-coating remains random and will inevitably lead to uncontrolled behavior. 4.2.2.2. NEMS memories with “vertical” carbon nanotubes (CNTs) The concept is to use well-organized compact CNT networks to elaborate NEMS. This is achieved by the in situ synthesis of CNTs perpendicular to the surface and from nanodots as catalyzers, previously deposited in regular arrays on an insulating planar support. This technique used by Jang et al. gives good dimensional reproducibility of the nanotubes, positions them in a precise and regular manner, and, in the case of vertical growth, leads to extremely high implantation densities [JAN 08b]. Each NEMS has three electrodes, identified as the source S, the drain D and the gate G. On the first two electrodes (nickel nanodots) MWCNTs are synthesized, then modified by different chemical treatments9. The CNT connected to S is static and is transformed into a [CNT/insulator/metal] capacitor (CIM) by successive deposition of an insulating layer (SiNx) and a metal layer (chromium). The CNT connected to the drain D is free of any coating and constitutes the mobile mechanical element; the electrode G is a Ni dot without CNT. The different steps in the making of the NEMS are depicted in Figure 4.14.

9 Carbon nanotubes are synthesized by “plasma enhanced chemical vapor deposition” of a gaseous mixture of acetylene and ammonia (C2H2 + NH3) on catalytic Ni nanodots at 600–650°C. Plasma enhanced chemical vapor deposition (PECVD) has been described in detail by Chowalla et al. [CHH 01], and Teo et al. [TEO 03].

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The NEMS works in a way similar to that of a network of volatile DRAM memories, corresponding to the charge and discharge of the nanocapacitor by contact with the CNT connected to D. The latter works as a cantilever, activated by the gate G that exerts a repulsive electrostatic force on D.

Figure 4.14. Description of the different steps in the fabrication of a NEMS with three electrodes S, D and G (source, drain, gate). Adapted from [JAN 08b]

COMMENTS ON FIGURE 4.14.– (a) Elaboration and vertical alignment of multi-wall carbon nanotubes (MWCNT) by the PECVD technique and using Ni nanodots (outer diameter of the MWCNTs: 60 nm). (b) Deposition of a 40-nm-thick SiNx insulating layer by PECVD from a gaseous SiH4+NH3 mixture. (c) Metallization of electrode S with a 40 nm thick chromium layer so as to obtain a Cr/SiNx/MWCNT capacitor. (d) Coating of the insulator on the nanotube D is removed by etching. Application of a far greater voltage VG than that of the drain VD onto gate G electrically charges the carbon nanotube associated with D and leads to its deflection toward the nanotubes at

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S (potential 0). After contact with the latter, the charges on D are transferred to the capacitor S. (e) SEM image of the device. Figure 4.15 describes the write and read operations corresponding to the two ON and OFF states and their addressing. We note that, as for DRAM memories (1T/1C, see Chapter 2), the read operation destroys the data stored in the capacitor.

Figure 4.15. Addressing modes of cells 1 and 2 during write a, b) and read c, d) operations. Adapted from [JAN 08b]

COMMENTS ON FIGURE 4.15.– (a) Data in cell 1 are written by using the bit line BL1 connected to electrode D and the word line WL connected to the G electrodes of cells 1 and 2. When VG > VD, the nanotube of cell 1 connected to D comes into contact with the

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[Cr/SiNx insulator/CNT] capacitor connected to S to which it transfers its electric charge. The cell 1 is then in the ON state (bit ‘1’); cell 2 remains in the OFF state or bit ‘0’ (no voltage in the bit line BL2). (b) The capacitor of cell 1 remains charged in state ‘1’ after the return to 0 V of BL1, BL2 and WL. (c) Data in cells 1 and 2 are read by applying a voltage VG (WL) greater than VD (BL1 and BL2) which results in the charging of the capacitor S of cell 2 without modifying the charge of cell 1 (nanotube D is repelled by the already charged nanotube S). The ‘0’ state in cell 2 is identified by a current pulse in BL2 while the current in BL1 remains nil. d) After the return of BL1, BL2 and of WL to 0 V, the two cells are in state ‘1’. This indicates that the initial state of cell 2 has been destroyed. 4.2.3. NEMS-FET hybrid memories with a mobile floating gate or mobile cantilever This refers to a device that combines the function of an MOSFET with that of an NEMS. It is made either of an electrically-charged mobile floating gate or of a static gate and a mobile cantilever. 4.2.3.1. Mobile floating gate memory The peculiarity of the system lies in the conception of an NEMS consisting of a floating gate that can mechanically oscillate between two stable states corresponding to ON and OFF without any contact with the bottom part of the device (Figure 4.16). When the control gate G is polarized, the floating gate is moved to one of its two equilibrium positions. This induces a variation in current in the channel of an FET transistor, an effect which is used as a memory state. The device, conceived by Nagami et al., is comparable to a floating gate MOSFET; it consists of a suspended silica bridge into which silicon nanocrystals, about 8 nm in diameter, have been inserted [NAG 10]. These nanocrystals have a surface density of 1011– 1012 cm-2 and are charged through trapping of electrons.

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Figure 4.16. Diagram of a mobile floating gate NEMS-FET. The SiO2 floating gate contains Si nanocrystals (Si-QDots) in which electronic charges have been trapped: a) perspective view of the NEMS-FET. b) Stable ON and OFF states corresponding to two distinct deformations of the floating gate. Adapted from [NAG 10]

The advantage of the system compared to a traditional floating gate MOSFET memory lies in the fact that the electrical charges located in the silicon nanocrystals do not move and are not submitted to charge and discharge dynamics that can damage the dielectric. Changing the control gate potential G moves the floating gate closer to or further from the surface of the semiconductor. The consequence of this is to reduce or increase the field applied in the MOSFET channel and, as a result, to control the magnitude of the drain current at the origin of the memory effect. Nagami et al. showed by simulation that the NEMS characteristics could be improved by miniaturization of the device. Thus, when the length of the suspended “bridge” is reduced from 1 µm to 100 nm, the gate potential necessary for commutation falls from 6.7 to 2.8 V, and the time necessary for switching is then very short (4.6 ns). The ON/OFF ratio of the current in the canal is high at about 105–106 [NAG 10]. 4.2.3.2. MEMS memory with a mobile cantilever and a fixed carbon nanotube An ingenious non-volatile memory device combining a micro electromechanical switch (MEMS) and a FET has been achieved and tested by a Korean and British team [LEE 11].

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The device consists of a transistor and a metal micro-cantilever, used to charge and discharge a floating gate FG by electric contact. The channel of the transistor is immobile and is made of semiconductive carbon nanotubes (Figure 4.17).

Figure 4.17. Hybrid MEMS MOSFET memory with a CNT channel. Adapted from [LEE 11]

COMMENTS ON FIGURE 4.17.– (a) Scheme of the device. The metal floating gate FG is located beside the semi-conducting channel CNT and deposited onto a SiO2 layer, which guarantees its electric insulation. The cantilever and the underlying electrode (actuating electrode) are the two plates of a capacitor-actuator that transfers an electric charge to FG by direct contact with the cantilever. (b) SEM image of the device (the carbon nanotube is not visible on the image and is hidden by FG). The FG is electrically charged by direct contact with the metal cantilever that transfers a positive or negative charge in a controlled manner. The contact between the cantilever and FG is made by an electrode (actuating electrode) located below the cantilever that, depending on its potential, exerts an attractive or repulsive electrostatic force on the cantilever.

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As soon as FG is charged the cantilever returns to its initial position by reversing the potential of the electrode below it. The charge inside FG is perfectly isolated and can, therefore, be stored over a very long time in the absence of contact with the cantilever. The properties of the device are comparable to those of a Flash memory. Tests carried out for over 10 h (~ 4 × 104 s) show no significant variation in the ISD currents in the ON or OFF states (Figure 4.18).

Figure 4.18. Retention tests for ON and OFF states. Adapted from [LEE 11]

COMMENTS ON FIGURE 4.18.– The ON state is programmed by negative polarization of the cantilever that transfers a negative charge to FG and induces p-type conduction in the CNT. Erase (OFF state) is obtained by a positive polarization of the cantilever that makes IDS negligible in the CNT. The ON/OFF ratio is high and around 105. The voltage applied between the drain D and the source S is 100 mV. Moreover, the system is well adapted for multi-level programming. The transfer of increasing electric charges to FG by the simple application of increasing negative potentials to the cantilever allows us to modulate IDS at well differentiated values. This is the procedure for obtaining a multilevel memory (MLC) (Figure 4.19).

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As the charge and discharge of FG are directly related to the oscillation frequency of the MEMS, read and write are extremely rapid. For the MEMS-transistor described in Figure 4.18, the oscillation frequency is 8.5 GHz. This gives a theoretical commutation time of 60 ns [LEE 11], far shorter than that of an NAND Flash for which programming and erase times are about 100 µs (see Chapter 1, Table 1.1).

Figure 4.19. Multiprogramming the MEMS-transistor. The current IDS in the channel is determined by the electric charge transferred to FG by the cantilever. For various cantilever potential values (2, –4, –6, and –9 V), IDS settles at levels (between 10-12 and 10-6 A) which are sufficiently different to be read as separate memory states. Points A, B, C and D can be considered as the ‘00’, ‘01’, ‘10’ and ‘11’ states. Adapted from [LEE 11]

These switching times can be further improved by reducing the dimensions of the cantilever. In particular, with a cantilever of nanometric dimensions (100 nm), the oscillation frequency is increased by an order of magnitude and should give switching times of about 10 ns, comparable to that of DRAMs. The endurance, which is another major quality criterion, is obviously a function of the mechanical properties of the cantilever. Cantilever systems are renowned for their ability to endure more than

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108 open–close cycles, and hence guarantee an operational reliability 100–1,000 times better than that of Flash memories. 4.3. Conclusion Using the mechanical properties of NEMS to make memories is an attractive concept. This is especially true when it comes to operating in harsh environments (radiation and high temperatures). This idea, however, encounters opposition due to technical difficulties. In the case of NEMS based on inorganic materials, fabrication according to the traditional methods of the microelectronics industry, commutation through contact between the two nanometric elements (cantilever and electrodes) is very fast and is determined by the oscillation frequency of the system. They are comparable to the commutation times of DRAMs when the oscillating arm is about 100 nm long. This appears to be a technological limit for their construction, and greater integration densities than those of Flash memories cannot be considered, especially when it is hoped to use 16-nm technology for the latter. Adhesive phenomena during switching, leading to poor reproducibility of the commutation potential, have not been overcome and hinder the exploitation of such devices. The case of NEMS using carbon nanotubes as cantilevers is also complicated by the difficulty of reproducing the position of nanotubes on a surface. The technique that consists of the direct synthesis of the nanotube at catalytic locations is undoubtedly a better solution to the problem of positioning, and thus improves reproducibility. The vertical synthesis of carbon nanotubes inserted into a three-electrode system is ingenious and provides read and write speeds that are comparable to those of DRAMs. This also makes it possible to obtain extremely high integration due to the very small diameters of nanotubes. All these systems are currently at the experimental stage and have not benefited from sufficient research to allow the elaboration of a prototype DRAM-type memory.

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The hybrid solution, however, that integrates an NEMS into the operation of a FET allows us to obtain non-volatile memories. The performances of NEMS combined with those of an FET in which a stationary carbon nanotube acts as a transistor channel, are impressive in terms of endurance, retention and read and write speeds that are far greater than those of Flash memories. Great efforts are needed to reduce the size of the devices that are currently on the micrometric scale. Though NEMS and MEMS are at the origin of significant industrial production in terms of resonators, extremely sensitive mass detectors, motion detectors and various sensors, application on a larger scale with the production of volatile and non-volatile memories remains a very difficult challenge. NEMS memories no longer have the support of the ITRS which, in its 2012 report [ITR 12], does not consider them as future SCMs (storage class memories) capable of competing with STTRAMs, PCRAMs or some RRAMs (see Chapters 3, 5 and 6).

5 Non-volatile Phase-Change Electronic Memories (PCRAM)

Phase-change materials (PCMs) were initially used for optical storage of data. The peculiarity of these materials is that they have different reflectances in the crystalline or amorphous state. This phase change can be induced by a very brief local thermal impulsion. It is this property that is used to generate a memory effect. This discovery allowed the large-scale production of widely adopted and common objects in the 1990s, such as compact disk read only memory (CD-ROMs) and digital versatile disks (DVDs), offering greater storage capacities than the cassettes or floppy disks of the 1980s1. The problem of rewritable data is more complex, as it requires the choice of materials that are capable of conserving crystalline or amorphous forms over long periods of time, and capable of returning to their initial state when subjected to a short thermal pulse. Such properties are unusual and very few materials are capable of meeting these requirements. 1 The first non-rewritable CD-ROMs were available on the market in 1990 and had storage capacities of about 500 megabytes (MB). They have been progressively improved with the use of shorter wavelengths (from infrared to red, and then from red to blue-violet). This has led to rewritable DVDs and blue-ray disks (BDs), the latter providing a storage capacity of several dozen gigabytes (GB). In 2004, the capacity of a single BD layer was 23.3 GB [WUT 07].

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The discovvery of semii-conductive ternary alloyys by Yamadda et al. [Y YAM 87] inn 1987, which when heeated are caapable of revversibly sw witching from m an amorpphous state to a crystalline state, iss at the orrigin of the developmennt of rewritable compacct disks (RW WCDs). Thhese alloys were w based on germanium m (Ge), antim mony (Sb), teellurium (T Te) and particcularly Ge2Sb S 2Te5 (GST)). The use of these phasse-change alloys for deeveloping eleectronic memories is not m n new. It goes g back to the discoveery by Ovshiinsky in 19968 of a variation v in conductivity y between the t crystalliine and am morphous staates of a maaterial [OVS S 68], as weell as to the idea of ussing this propperty to desiign a non-vo olatile memoory device tw wo years latter [NEA 700]. It is only after a the disccovery of GS ST-type alloyys and their various appplications inn optical stoorage in the 1990s that the t interest iin these m materials for the t elaboratioon of electro onic memoriees became clear. To thhis we must add the fact that switchiing between two resistivve states caan be obtaineed by a two-terminal deevice, thus alllowing eachh cell to bee addressed according a to a crossbar-ty ype geometrry. The two-tterminal deevice offers the best soluution in scalle reduction with a valuee of 4F2 (F Figure 5.1).

Figure 5.1. 5 Network off phase-change resistive memoories distributedd accordingg to a crossbar--type architectuure

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COMMENTS ON FIGURE 5.1.– The phase-change material is placed between two electrodes that can be addressed by the bit lines BL and world lines WL. The limiting area of a cell, calculated from the linewidth (1F) of a BL and a WL, is then of 4F2. The International Technology Roadmap for Semiconductors (ITRS) currently considers them as being one of the emerging systems that have the best chance of going beyond the scale limitations of flash memories, classifying them de facto as storage class memory. Many companies such as BAE Systems, Hitachi, Samsung, Intel, IBM, Macronix, STMicroelectronics, Quimonda, NXP, Hitachi and Renesas are implicated in the development of these memories [RAO 09]. Samsung was the first company in 2011 to make a 512 Mbit PCRAM memory. 5.1. Operation of an electronic phase-change memory The operation of the memory relies on the variations in resistivity of a PCM, triggered over a very short period of time by a local intense variation in temperature, that leads to the transition between the two stable states: amorphous ↔ crystalline. The device comprises two electrodes between which two different materials are placed: a heating filament (heater) and the semi-conductive (PCM). 5.1.1. Composition and functioning of a GST PCRAM The heater is a conductive nanofilament made of titanium nitride (TiN) and connected to the bottom electrode (BE). The PCM (generally GST) in contact with the heater and the top electrode TE is introduced in its crystalline form (the more conductive). The (crystalline ↔ amorphous) phase changes occur in a small part of the material (near the heating filament), which is considered as the active and programmable region of the GST (Figure 5.2(a)). The phase change is achieved by imposing an electric current between the two electrodes. This current produces heat in the filament (Joule effect) that is diffused toward the GST; the volume in which the

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phase change occurs has the shape of a spherical cap slightly bigger than the filament2. It is in this reduced volume that the transformations (amorphous (OFF or Reset state) ↔ crystalline (ON or Set state)) occur and with which are associated variations in the conductivity of the cell. The conditions for these two transformations are of great importance and each requires a very precise optimization of the electric pulse, which is calculated according to the thermochemical properties of the PCM3.

Figure 5.2. Operation of a phase-change memory. Adapted from a) [LAC 08] and b) [ITR 10]

COMMENTS ON FIGURE 5.2.– a) Simplified diagram of the device used to achieve the phase changes occurring in the nanodomain (active GST) at the [heater/GST] interface. b) Temperature peaks produced 2 The global resistance of the cell is, in fact, the sum of the resistances of the filament (RF) and the GST (RC). RC is adjusted so that the heat produced by the Joule effect is initially located in the filament and is later diffused in the GST. 3 It must be noted that the use of the terms “Set” and “Reset” can lead to confusion. Indeed, it is a common practice with PCRAM memories to use Reset and Set to refer to the amorphous and crystalline states, respectively, and also to the (amorphous state → crystalline state) and (crystalline state → amorphous state) transformations. These Set and Reset states correspond to the ON (low-resistance state) and OFF (high-resistance state) states which are used to describe the switching of resistive memories (RRAM).

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in the programmable region of the GST to achieve the different phase changes (Set and Reset) as well as the reading of the different states. The Reset transition produces a very high variation in temperature over a very short period of time, whereas the Set transition corresponds to a smaller variation in temperature over a longer period of time. To achieve the transformation from the crystalline state to the amorphous state (Reset), the material is heated so as to reach the molten state which requires a strong current pulse in order to exceed the melting point Tmelt (between 500 and 800°C for different PCM). Cooling must also be very fast (cooling rate greater than 1011 K/s) so that the material is quenched in the amorphous state with a high resistance4. Cooling too slowly would lead to the previous more conductive crystalline state. When the material is in the amorphous state (high resistance), the electric pulse is adjusted so as to produce a heat flux that locally increases the temperature slightly above the crystallization temperature Tcryst but much lower than the melting point Tmelt. This changes the nanovolume of amorphous matter into crystal (stable state), which corresponds to the Set transformation and an increase in the conductivity (Figure 5.3(b)). These phase-change transformations are obtained using very short electric pulses (of a few nanoseconds); the smaller the cells, the shorter they are. As a result, for 50 nm thick GST cells and for a contact diameter between the GST and the heater ranging from 20 to 500 nm, the pulses necessary to achieve a Reset transformation (amorphization) range from 0.2 to 1.4 ns for an applied voltage of 4.5 V (Figure 5.3(a)).

4 This cooling rate is calculated for a GST thickness of 45 nm, a programmable region of the GST equivalent to half a sphere with a radius 45 nm. The calorific capacity and the thermal conductivity of the GST are Cp = 1.25 106 J/m3K and kth = 0.5 W/mK, respectively. This cooling rate allows the temperature to be reduced by 50 K in 0.5 ns, which is enough to get back from the liquid state to the amorphous state [LAC 13].

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The Set transition (crystallization) requires far less energy and is a slower process. This is achieved with an electric pulse of 0.8 V, which is much smaller than the previous one, but requires dozens of nanoseconds (Figure 5.3(b)). The two different values of the resistance (20–30 kΩ in the Set state and 300–500 kΩ in the Reset state for cells of 20 nm diameter and 50 nm thickness [WAN 08]) are read under a current intensity, generated by a low-amplitude voltage pulse, chosen so that the heat released by the Joule effect does not disturb the amorphous or crystalline states of the active zone of the GST. As a result, current pulses related to the two Set and Reset transformations range from 2.6 to 4 µA and 110–220 µA, respectively. This last value, corresponding to the amorphization transition, is relatively high and represents one of today’s technological obstacles which could prevent significant miniaturization of this type of memory5.

Figure 5.3. Amorphization and crystallization rates of GST cells. The thickness and the diameter (variable) of the contact between the GST and the heater are 50 nm and 20–500 nm, respectively. The amplitude of the potential pulse is: a) 4.5 V for the amorphization transformation and b) 0.8 V for the crystallization transformation. Adapted from [WAN 08] 5 The high current necessary to achieve the Reset transition (crystalline→ liquid → amorphous) is a factor that goes against the conception of low energy consumption devices. It is also a handicap in terms of miniaturization, due to the fact that the selection transistor associated with the PCM memory must have a minimum size to provide enough current and to allow phase changes. For pnp or npn-type bipolar transistors, the currents are a function of their sizes and it is accepted that a maximum of 0.5 mA is obtained for a transistor about 1 µm in size [RYU 11].

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5.1.2. The antinomy between the high resistance of the amorphous state and rapid heating We indicated previously that each transformation requires a rapid increase in temperature. This implies a high current so as to release enough heat in the filament to provide the temperature increase necessary for each transformation. In the case of the Reset transformation (crystalline → amorphous), the entire GST is in the crystalline state; therefore, its high conductivity makes the passage of high currents easier. This is no longer the case for the Set (amorphous → crystalline) transformation for which the initial resistance is high. This limits the current to a value that is too small for the crystallization temperature of the PCM to be reached rapidly. This transformation therefore requires longer switching times. Fortunately, there is a threshold switching potential below 1 V at which the material commutes in a few nanoseconds from a state of high impedance to a state of low impedance while remaining in the amorphous state (Figure 5.4). This property is specific to GST-type alloys.

Figure 5.4. I/V curves characteristic of a GST alloy initially in its amorphous state. Adapted from a) [WUT 07] and b) [LAC 06, LAC 08]

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COMMENTS ON FIGURE 5.4.– a) I/V curve obtained by controlling the voltage. A sudden increase in the conductivity occurs at 0.7 V (threshold switching) allowing the current to increase sufficiently to release the heat necessary for the transformation to the crystalline state (memory switching) which is stable and more conductive. b) I/V curve obtained by imposing the current. Beyond the current threshold (electronic switching), conductivity increases, causing a drop in voltage. This phenomenon, frequently observed with (metal/insulator/ metal) junctions, has been defined in the case of metal oxides as an electroforming process (see Chapter 6), in which the insulator goes from a state of high impedance to a state of low impedance, and is accompanied by I/V curves with a negative differential resistance (NDR)6. In the case of GST, the fact that this transition is extremely rapid and occurs in a few nanoseconds instead of a few seconds, in the case of a metal oxide, is remarkable7. Moreover, this transition is reversible. Indeed, the conductivity of the material returns to its initial value if the voltage is rapidly lowered so as to avoid heating the material and transforming it into a stable crystalline phase. The conductivity continues to increase when the voltage increases, and this leads to a greater current and so a release of heat that causes the transformation from amorphous to crystalline (Figure 5.4(a)). This phenomenon, recognized as electronic, has been subjected to many interpretations. One of them, based on the theory of ionization by electron impact, was developed at the start of the 1980s by Adler et al. [ADL 80]. More recently, Ielmini and Zhang [IEL 07] have given a coherent and detailed interpretation of the phenomenon by 6 An I/V curve with a negative differential resistance (NDR) indicates that for a region of the curve, the current decreases while V continues to increase. 7 The low rate of the change in conductivity, observed with insulating oxides (“electroforming”), is due to the formation of conductive filaments resulting from ion migration processes.

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considering that GST in its amorphous state has a pseudo-forbidden band (mobility band) in which there are many localized states, occupied by or free of electrons. The occupied and available levels are below and above the Fermi level, respectively (Figure 5.5(a)). For a voltage V below the switching threshold VT (subthreshold switching) (Figures 5.5(a) and (b)), Ielmini and Zhang showed that the conductivity is of Poole–Frenkel type (see Box 5.1). The authors found an activation energy of about 0.3 eV, approximately equal to the width of the pseudo-forbidden band, i.e. EC-EF. In agreement with the theory, they verified that this activation energy decreases proportionally to the applied voltage V, and that the current varies exponentially with the voltage, according to the law: I = I’PF exp(βPFV), (I’PF and βPF are two constants)8 This confirms a Poole–Frenkel-type conduction mechanism where the current is controlled by charge carriers at high concentration, located in deep traps and with small distances between them. The sudden transition toward a state of high conductivity observed at a critical voltage VT accompanied by an NDR implies a nonequilibrium redistribution of the charge carriers toward high energy levels close to the conduction band (Figure 5.5(c)). Electrons are injected toward the higher energy traps when an electrical field F is applied; this corresponds to a tunnel effect of ballistic nature that leads to a non-equilibrium distribution of the charge carriers (q). These electron transfers occur between the electrode (Fermi level EF) and the high-energy traps located at the same level EF and for a separation length ua,OFF equal to ΔE/qF, where

8 For isolated traps separated from each other by large enough distances, the current variation with V is expressed by I = I’PF exp(βPFV1/2) and the activation energy varies with V1/2.

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ΔE E is the eneergy differennce between the initial and a final traap states 9 [IE EL 07] . c meechanism is foound in This conduction amorph hous semi-condductor materials (ASC) where there is a largge number of localized states (trapped). ( The cu urrent is due to a thermal emiission of an elecctron in a trap (occupied) ( tow wards the conducction band E’C. This electronn is then captureed by another trap (free), at distance Δz. The heeight of the enerrgy barrier ΔΦ depends on the applied voltagee Va. ( is equal to E’C- EF For Va = 0 V, ΔΦ (0) (EFis the t Fermi levvel considered as the highestt energy of thee occupied traps, E’C is the bottom of the psseudo-conductioon band A of the ASC). For Va>0, the heigght of the baarrier is reduced to become eqqual to ΔΦ = ΔΦ (0) – (qVa Δz)/2u Δ h thickness of the a . ( ua is the ASC; ½ comes from the fact that thhe height of the barrier b measureed for Δz/2).

For Va> 0, the t current is prroportional to e

ΔΦ (0) – (qVa Δz ) / 2ua kT

q: electron charge, k: Boltzzmann constantt, T: absolute teemperature o I is of the form m I = exp (αV) instead of I = As a result, the variation of 1 ⎛ ⎞ exp ⎜ βV 2 ⎟ in the case off isolated traps, very distant froom each other. ⎝ ⎠ Adapted froom [IEL 07b]. Box 5.1. Poole–FrenkelP -type conductioon 9 The T energy ΔE acquired by thhe electrons durring their tunnell transfer is equual to qFx (x being the lengtth of the displaccement). ua,OFF corresponds to the minimum ddistance x at which tunnel trransfer can occuur.

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Figure 5.5. Energy distribution of the electrons in an amorphous semiconductor of thickness Ua with a high trap density. Adapted from [IEL 07a]

COMMENTS ON FIGURE 5.5.– a) When the electrical field is very weak (V~ 0 V), the electrons occupy the traps located below the Fermi level EF. b) Profile of the energy bands of the semiconductor for a polarization V slightly smaller than VT, but too small for tunnel transfer of electrons from EF toward the energy levels of the traps located below the conduction band (EC). c) The polarization is slightly greater than VT, and the curvature of the bands is greater than in b); consequently, ua,OFF is sufficiently small to allow ballistic tunnel transfer of the electrons from EF toward the high-energy states. The transition between low conductivity (OFF state) and high conductivity (ON state) can then be explained by the modification of the band structure and the appearance of an electric field discontinuity. A first region of low thickness (ua,OFF) in contact with the negative electrode is formed in which the charge distribution is in thermodynamic equilibrium (no electrons in the high-energy traps). Conduction in the GST region takes place by the tunnel effect. This is

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favored by the marked curvature of the energy bands resulting from a strong electric field. In addition to this first region, a thicker (ua,ON) second region is found, whose higher conductivity can be explained by the high concentration of high-energy and non-equilibrium charges located close to the bottom of the conduction band. This switching effect between low and high conductivity is purely electronic, and hence its high rate, which allows a current strong enough to produce the minimal heat for the transition from the amorphous to the crystalline states. This is achieved by the Joule effect in just a few nanoseconds. This rapid switching is essential to run the component and to induce a sufficient heat flux. Without this peculiarity, the rapid transformation from the amorphous state to the stable crystalline state would be impossible. 5.2. Comparison of physicochemical characteristics of a few phase-change materials The criteria for a non-volatile PCM memory, which performs better than a Flash memory or is even as good as a DRAM in terms of read and write speeds, imply that the phase transition must be extremely rapid and induced by low-amplitude potential pulses of a few nanoseconds at the most. The amorphous and crystalline states must be stable over very long periods (>10 years) and the resistivity ratio between the amorphous and crystalline states must be much greater than 10. Finally, the material must be able to endure a very large number of cycles without damage (>105) while offering very high chemical stability [WUT 07]. Very few materials meet all of these conditions. Many studies have focused on the composition of GST and of similar materials with the aim of improving their performances. Emphasis is placed on four physicochemical criteria of primordial importance: melting (Tm) and crystallization (TC) temperatures, activation energy (Eac) corresponding to an amorphous → crystalline transition and the resistivity ratio between the amorphous and crystalline states.

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A very high stability for the crystalline state (ON) is obtained using materials with high crystallization and melting temperatures. This is the case of GeTe (cubic structure) for which TC and Tm are 189 and 700°C, respectively, while they have a high forbidden energy bandwidth of 0.73–0.94 eV, which leads to low crystallization rates [CHO 06]. In contrast to this, an alloy such as Sb2Te3 (rhombohedric structure) is characterized by relatively low crystallization and melting temperatures (Tc = 90–100°C; Tm = 621°C) and a forbidden bandwidth of 0.21 eV, leading to high crystallization rates but low stability at the ON state. GST, whose composition is intermediate between these two binary alloys Sb2Te3 and GeTe, seems to be better adapted. Much work has focused on the improvement of its properties, either by the introduction of new elements (doping) or by the modification of the structure of the PCM layers (Figure 5.6). All these materials display variations in resistivity between the amorphous and crystalline states which depend on the different alloy compositions.

Figure 5.6. Ternary alloy phase diagram of germanium, tellurium and antimonybased alloys. GST (Ge2Sb2Te5) located between the two binary alloys Sb2Te3 and GeTe has properties intermediate between those of Sb2Te3 and GeTe. The arrow inside the triangle indicates that Tcrist, Tm and Eac increase when the composition of the alloy changes from Sb2Te3 to GeTe. Adapted from [CHO 06]

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Figure 5.7 represents the temperature dependence of the resistivity for several materials: GST, N-GST (nitrogen-doped GST), GeSb (Ge15Sb85), and Sb2Te and AIST (silver and indium-doped Sb2Te). For these different alloys, the resistivity in the amorphous state ranges from 1 to 104 Ω cm. A drop by two orders of magnitude occurs when the temperature increases from 0 to 150–200°C. The transition toward the crystalline state occurs within a relatively narrow range of temperatures for Sb2Te (120°C), AIST (175°C) and GeSb (250°C). The transition is more progressive with GST and N-GST. GST (Ge2Sb2Te5) is a special case. Indeed, there is a first transition around 160°C, where the resistivity drops from 10 to 0.1 Ω cm, followed by a slow decrease and finally a faster decrease at around 360°C. The first transition corresponds to the change of the amorphous state toward a first metastable crystalline state (rocksalt), corresponding to an fcc-type crystalline network; the second transition is due to the rocksalt → hexagonal crystalline state transformation. This last state is stable and is maintained throughout cooling [RAO 07].

Figure 5.7. Resistivity curves ρ = f(T) of different PCM materials deposited in thin layers (50 nm) on an inert support: GST (Ge2Sb2Te5), N-GST (N-doped GST), AIST (Ag and In-doped Sb2Te), GeSb (Ge15Sb85). AIST and GeSb were used in the 2000s for the development of DVD-RW [WUT 07]. Adapted from [RAO 07]

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The fact that these transitions occur (apart from Sb2Te) at temperatures greater than 150°C is an advantage. This means that they have possible applications in various fields for which resistance to temperatures of up to 85°C is required in the case of computers, and up to 150°C for automotive applications. It is important to note, however, that these phase-change properties are a function of the thickness of the films, a criterion which turns out to be of crucial importance for the production of nanometric-scale memories. Fortunately, by using ultrathin films, it has been experimentally confirmed that the R = f(T) curves remain unchanged up to thicknesses of a few nanometers, which in theory is compatible with very high integration densities [RAO 08]. 5.3. Key factors for optimized performances of PCM memories Currently, the most commonly used material for PCRAM memories is GST (Ge2Sb2Te5). This is partly explained by the considerable knowledge of the material that was acquired with the production of optical storage disks. Now one of the main research objectives is to reduce the current necessary for the Reset transformation (crystalline state → amorphous state) as much as possible while keeping very short switching times. This implies the use of a melting point Tm that is not too high, so as to have the smallest possible Reset current, as well as the highest possible crystallization temperature Tc (while remaining far below Tm ) to guarantee a good stability in the Set state. The activation energy corresponding to the Reset transition must be sufficiently high to guarantee the stability of the crystalline state. This leads to high retention times for the Set state but, unfortunately, this is incompatible with very short crystallization switching times which imply, on the contrary, small activation energies. This means that a compromise must be found between the need for fast crystallization and high retention times.

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Modifications of cell geometry and GST composition, nanostructuration of the GST layer and new polarization modes are also paths that are being explored in order to improve these memories. 5.3.1. Influence of cell geometry on the current Im needed for crystal melting Cell geometry has a significant influence on performance, especially with regard to the current Im that is necessary for the localized melting of a crystal (Reset transition). A model of thermal exchanges between the heating filament and the PCM allows to predict this current Im that itself is related to IReset corresponding to the Reset transition (IReset ~ 1.5 Im). For a mushroomtype cell (see Figure 5.1(a)) with specific size and geometry, Russo et al. [RUS 08] have determined IReset by taking into account the thermodynamic and electric GST data as well as those of the heating filament. As said previously, the heat Qh is generated by the Joule effect and is due to the current in the heater. This heat is diffused into a small volume of the GST and increases its temperature (ΔT), leading to the localized melting of the alloy. Diffusion being spherical, the “programmed” molten volume (VProg) has the shape of a spherical cap. The current IReset and the programming time ∆tp are determined by two relationships: one depends on heat production achieved by the Joule effect Qh and the other depends on the dissipation of the heat by diffusion. The heat released by the Joule effect is: Qh = I2Reset Rdyn ∆tp (Rdyn is the dynamic resistance, the average value of R during the Reset transformation).

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The law of heat conservation expressed by the equality of the heat absorbed by the material to reach melting Qt (Qt = ρ cp ΔT Vprog + ΔHf Vprog) and the quantities of heat released by the Joule effect (Qh) and by thermal diffusion leads to the following expression: t

( pc p ΔT + ΔH f )V prog = ∫ ∇. (k ∇T ) dt + Qh 0

where: – ρ is the mass density; – cp is the specific heat; – ΔT is the variation of temperature between the initial state and the melting temperature (Tm) equal to Tm – 298K; – ΔHf is the enthalpy of melting; – k is the thermal conductivity; – VProg is the programmed volume in which the phase transition occurs [RYU 11, LAC 13]. From these relations, the current intensities necessary to achieve the phase changes, which depend on the material and the cell geometry, can be calculated. Taking this into account, Russo et al. modeled the region corresponding to the melting temperature calculated for different geometries of the mushroom-type GST PCM cell. They obtained a temperature map that locates the melted zone of GST, which strongly depends on the dimensions of GST and the heating filament (Figure 5.8). The current Im corresponding to the melting of GST is calculated and experimentally measured for different thicknesses Lc of the PCM layer for a TiN heater of length Lh and diameter Ф. Im is defined at the point in the R = f(I) curve where RSet begins to increase (Figure 5.9(a)). The temperature maps are modeled for an Im value that leads, at the surface of the filament-GST interface, to the melting point of GST.

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The temperature map shown in Figure 5.8(b) is considered to be the most favorable and corresponds to a minimum value of Im.

Figure 5.8. Model of the temperature map of a GST cell; dependence on LC (thickness of the GST layer), Lh and Ф (length and diameter of the heater, respectively). (a–c) Temperature maps calculated for the same value of RSet, the latter being adjusted with a selection of LC, Lh and Ф. The half sphere in black at the PCM/heater interface corresponds to the zone where the temperature has reached the melting point of GST. Adapted from [RUS 08]

By adjusting Lc and Lh in order to keep the overall resistance of the cell in its crystalline state (RSet) the same, Russo et al. showed that for the same TiN heating filament (diameter 30 nm) and for current pulses of a given width, Im corresponding to the melting of the PCM is minimal for an optimal value of Lh10. For every value of RSet, the variation of LC is calculated as a function of Lh, thus leading to the “iso RSet” curves of Figure 5.10. Knowing the minimum value of the current Im determined in Figure 5.9(b), an optimal pair of lengths Lc and Lh is calculated. The darker shaded area of Figure 5.10 indicates the optimal values of Im (to within ± 10 µA), thus defining the dimensions of Lc and Lh corresponding to an optimized construction of the PCM cell. 10 The model was achieved by using 17 and 2.5 mΩ cm as the resistivities of GST and TiN (doped), respectively, that of the insulator being considered as infinite. The thermal conductivities of GST, TiN (doped) and of the insulator were estimated to be 1.12 and 0.7 W/(Km), respectively.

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Figure 5.9. Geometrical optimization of a PCM cell with a heater diameter of 30 nm: a) experimental and calculated curve of R vs I (heating current), for an initial RSet of 3 kΩ. b) Melting current curve of Im versus Lh. For each value of the resistance RSet of the cell, the thickness LC is adjusted according to Lh. Adapted from [RUS 08]

As an example, to the “iso-RSet” curve of 4 kΩ for which the minimum Im is approximately 300 µA (Figure 5.9(b)) corresponds a heater length Lh ranging from 60 to 90 nm (Figure 5.10). Then, by taking Lh as 70 nm (point A, Figure 5.10), it is found that the thickness of the GST (Lc) must remain in the 30–15 nm range. This is equivalent to stating that for a resistance RSet of 4 kΩ, the minimum value of the current IReset is obtained with a heater length of ~70 nm and a GST thickness of ~20 nm. In parallel with these results, the diameter of the contact between the GST and the two electrodes, which determines the heater current, is also a key factor. As shown previously, the pulse durations can be much reduced when the diameter of the cell is very small, about 20 nm (0.4 ns and 10 ns for the Reset and Set switchings, Figure 5.3). These last particularly important results show that it is possible to observe the phenomena of phase change on extremely small structures. To this, we add the possibility of reading switching times of a few hundred picoseconds. This, from the perspective of write and erase execution speeds, makes phase-change memories comparable to DRAMs with, in addition, very good properties of non-volatility.

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Figure 5.10. Curves of Lh versus Lc for different values of RSet. Adapted from [RUS 08]

COMMENTS ON FIGURE 5.10.– The darker shaded area corresponds to the optimal dimensions for LC and Lh for which Im (to ± 10 µA) reaches a minimum. The rectangle within dashed lines is a region where the LC and Lh dimensions vary between 10 and 200 nm, and correspond, according to the authors, to a region where manufacturing is possible with 45 nm technologies. Point A on the isoRSet curve of 4 kΩ corresponds to the optimal dimensions of the PCM cell allowing the Reset transition with a minimal current Im. From a practical point of view, and with a view to minimizing the PCM cells, this makes possible manufacturing techniques to be very different from those found in classical lithography. Zhang et al. have shown that it is possible to observe phase changes of GST-type materials in networks of 15 nm nanodots obtained by deposition through porous polymer membranes [ZHA 08]11.

11 The manufacturing technique for porous polymer membranes is well known and consists of the synthesis of block copolymers from two different monomers. In the present case, the PS-PMMA copolymer is obtained from styrene (S) and methyl methacrylate (MMA), thus leading to two immiscible PMMA and PS polymer chains. These block copolymers are organized in the form of separate domains. For specific ratios of the two monomers, cylindrical PMMA structures are regularly distributed inside a PS matrix. Dissolution of the PMMA gives a network of regularly spaced nano-pores, each about 15 nm in diameter, into which the phase-change material can be deposited.

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5.3.2. Optimization of phase-change alloy composition to improve performance All the experience and know-how acquired in the production of GST-based CDs and DVDs made this material a reference for many years. However, recent work showed that variations in GST composition or its doping (by elements such as nitrogen, oxygen, silicon and carbon) [BEN 11] lead to significant improvements in Set and Reset switching times and the corresponding current intensities. 5.3.2.1. Effect of variations in GST composition (Ge, Sb and Te) Very recently, Gu et al. [GU 13] have shown that, when the proportions of Ge and Te are reduced compared to Sb, the Ge0.61Sb2Te alloy has far better characteristics than GST (Ge2Sb2Te5), in particular with higher crystallization temperatures and activation energies for the Reset → Set transition (Tcryst = 200.5°C instead of 160°C for GST and Ec = 3.28 eV instead of 2.87 eV). This makes the crystalline and amorphous states more stable. The PCRAM cell is T-shaped (or mushroom-type) and is made by CMOS 0.18 µm technology. The active layer of the cell is 150 nm thick and the heating filament is 280 nm in diameter. The Reset and Set transitions, which depend on the amplitude of the potential pulses, take between 10 and 80 ns for corresponding voltages of 6 and 2 V in the case of the amorphization transformation, and 80 and 10 ns for corresponding voltages of 0.7 and 1 V for crystallization (Figure 5.11). The cell withstands 106 cycles without noticeable degradation and the resistance ratio between the Reset and Set states is about 500. Retention in the Reset state that is thought to exceed 10 years

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in an environment at 120°C is also slightly better than that of alloys of different compositions12 (Figure 5.12).

Figure 5.11. Electric characteristics of the Set → Reset (OFF state) and Reset → Set (ON state) transitions for different potential pulses for 150 nm thick Ge0.61Sb2Te alloy. The cell is T-shaped, and the tungsten bottom electrode has a diameter of 260 nm. Adapted from [GU 13]

The current relative to the Set transformation (estimated from the data of Figure 5.12) varies between 1 and 1.5 µA, which is very low. In contrast, the Reset current is much higher, with values between 1 and 2 mA. These very recent results are based on large cells, and significant improvements can be expected, especially a noticeable reduction in IReset with smaller cells. 5.3.2.2. Doping of GST with elements other than Ge, Sb and Te Modification of the composition of the GST-type alloys by elements such as nitrogen and silicon (the most studied elements), 12 The retention times are calculated by extrapolation from the log t = f(Ea/kBT) curves obtained by the Arrhenius formula t = τ exp (-Ea/kBT), where t corresponds to the cell failure time that is defined when the resistance of the alloy decreases by half at temperature T. Ea is the activation energy of the Reset → Set transition, kB is the Boltzmann constant and τ is a constant [LAN 03].

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carbon, oxygen, silver, indium, bismuth, tin, titanium and aluminum (oxides) has led to much work. Some of this was initially carried out with the aim of increasing the performances of CDs or DVDs before they were exploited for PCRAM memories13.

Figure 5.12. a) Endurance to cycling of Ge0.61Sb2Te. b) Arrhenius plots giving the failure times of three alloys (GST or Ge2Sb2Te5, Ge0.15Sb2Te and Ge0.61Sb2Te). Adapted from [GU 13]

These dopants are generally injected into the GST or GeTe alloys at atomic concentrations rarely above 15%. Horii et al. [HOR 03] were the first to consider GST doping with nitrogen. This made possible to reduce the current required for the Set → Reset transformation. More recently, Raoux et al. (IBM, Macronix) [RAO 11] described the resistivity/temperature of GST and GeTe, both modified by various dopants (nitrogen, silicon, titanium, aluminum oxide, etc.). They recalled the following criteria to be satisfied for a PCM cell in order to work well: – the crystallization temperature must be high. This increases the stability of the amorphous state as well as the retention times of the data; 13 Much of the work and the research directions concerning phase-change materials and their application in electronic memories can be found in the yearly accounts of the European Library, Phase Change Ovonics Symposiums, published since 2001 and freely accessible on the Internet at www.epcos.org/ library/library200.htm.

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– the resistivity of the crystalline state must not be too low so as to avoid an excessively high current for the Set → Reset transition; – the electric field corresponding to the threshold potential VT associated with the variation in conductivity in the amorphous state (see Figure 5.4(a)) must be as high as possible. The last property becomes relevant when we consider the operation of a network of PCRAM cells that, when they are very small, may interfere with each other. This is especially true when the read potential VR is close to VT. Indeed, it is possible for the Set state of an adjacent PCRAM cell to be disturbed. This explains why VT must be greater than and sufficiently different from VR. A fourth property must be added to the above list here: the drift with time of the resistance of the amorphous state must be as small as possible; this is of primordial importance in multilevel cells (MLC). The same authors showed that two important improvements are associated with nitrogen doping of the GST alloy. First, the crystallization temperature is higher and, second, the resistivity of the crystalline state is greater than that of the non-doped GST. The electric field corresponding to the threshold switch in the amorphous state, however, is little changed compared to GST. For a nitrogen atomic concentration of 9.9% (Ge 21.0, Sb 24.6, Te 44.5 and N 9.9), Raoux et al. observed that the crystallization temperature for the “rocksalt → hexagonal system” transition is 540°C instead of 380°C with non-doped GST. The resistivity versus temperature curve is located slightly above that of non-doped GST, but with a more progressive variation in the “amorphous → crystalline” transition zone (Figure 5.7). According to Jung et al. [JUN 07], this increase in resistivity is related to the formation of Ge nitrides, which was demonstrated by X-ray photoelectron spectroscopy (XPS). However, in the case of nitrogen-doped GeTe alloy (Ge 45.5, Te 44.2 and N 10.3 atomic %), it is the electric field corresponding to the conductivity transition threshold that is very high at 248 V/µm instead of 143 V/µm for GeTe. The crystallization temperatures are higher for

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doped GeTe (GeTeN) than for non-doped GeTe (Tc = 280°C for the N-doped GeTe instead of 180°C for the non-doped GeTe) but remain much lower than that of non-doped GST. Significant improvements have also been made to GeTe alloy by doping with carbon. Beneventi et al. [BEN 11] from CEA-LETI Minatec in Grenoble have shown that the crystallization temperature increases from 180°C (GeTe) to 340°C for a doping level of 10%. This is accompanied by a significant increase in the activation energy of the crystalline state Ea: 4.16 eV instead of 2.03 eV for GeTe. This guarantees an excellent retention time of over 10 years for the Reset state at an ambient temperature of about 120°C. The current and the power necessary for the Reset transformation decrease by 30 and 50%, respectively, when the doping level goes from 0 to 10%. Unfortunately, these improvements are counterbalanced by lower switching rates of the Set state, which, however, remain comparable to those of GST (Figure 5.13) For carbon-doped GST, coated with a thin layer of titanium, Souiki et al. [SOU 13] showed that the stability of the amorphous state is also increased and perfectly preserved when the cell is subjected to high temperatures that are met during the different manufacturing steps of a cell network14. The crystallization rates, however, are lower, and the difference in resistivity between the Set and Reset states is smaller than that for standard GST alloy. These examples show that the doping of GST or GeTe by different elements leads to noticeable improvements, with, in some cases, a reduction in Reset current intensities of 30–50%. Alloys other than those based on Ge, Sb and Te are also a focus of active research. British teams suggest the use of other alloys that, on a few key points, perform better than GST. Indeed, alloys based on 14 This refers to the different manufacturing steps and inter-cell connections that require high temperatures and are used toward the end of the process (400°C for 2 min for a typical “back end of line”) or during lead-free reflow soldering operations at 260°C.

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gallium, lanthanum and sulfur (Ga13La7S30) have very high resistance in the amorphous and crystalline states, as well as a resistivity ratio of approximately 104 between the two states. Very small currents are observed for the Reset transformation, but no details are given regarding switching speeds [HEW 11].

Figure 5.13. Resistance of the Set state versus the width of the pulse applied in the Reset state. The GeTeC alloys have carbon concentrations of 4 and 10%. The switching speeds and the resistivity ratios, between the Reset and Set states, are both lower than for GeTe. Adapted from [BEN 11]

Alloys of composition intermediate between GeTe and Sb2Te3 and close to the composition of GeTe were also studied [WUT 12]. Generally speaking, it is rare to achieve a global improvement across all the criteria required to obtain an electronic memory that is fast and non-volatile as well as resilient to cycling and has data retention times more than 10 years at temperatures above 100°C. 5.3.3. Influence of nanostructuration of the phase-change material The Ge2Sb2Te5 alloy, considered as the reference in the manufacture of phase-change cells, can be considered as a binary pseudo-alloy of GeTe and Sb2Te3. These two components have different thermal properties due to different crystal systems: – GeTe is very stable but has a low crystallization rate;

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– Sb2Te3, on the other hand, has a high crystallization rate but poor stability in the amorphous state15. The idea is to make use of the different thermal properties of GeTe and Sb2Te3 by replacing Ge2Sb2Te5 with alternating nanometric layers (superlattice-like (SLL) structure). 5.3.3.1. Alternating GeTe and Sb2Te3 layers The first work related to the use of SLL layers in PCM cells was by Chong et al. [CHO 06]. More recently, the concept was further completed by Loke et al. who investigated the effect of cell size [LOK 11]. When successive GeTe and Sb2Te3 layers, 3 and 4 nm thick, are deposited for a total thickness of 35 nm, there is a noticeable reduction in the Set and Reset switching times compared to a cell with a homogeneous GST layer. The switching times are also much reduced when the size of the cell decreases (Figure 5.14). The improvement is important in the amorphization transition corresponding to “crystalline state → amorphous state” switching (Reset). There is a decrease by about 200 ps between two PCM cells, one made with a homogeneous GST layer and the other with a structured GeTe/Sb2Te3 layer. This difference remains when the cell diameter is reduced from 400 to 40 nm (Figure 5.14(a)). In the case of Set switching, corresponding to the “amorphous state → crystalline state” transition, the effect of structuring on the reduction of the switching times is also important, being 20 ns for cells in the 200–400 nm range. It is much lower, however, when the cell is in the 200–40 nm range (Figure 5.14(b)).

15 GeTe has a high crystallization temperature of 189°C and a melting point of 700°C that make it very stable. In contrast, Sb2Te3 has a low crystallization temperature between 90 and 100°C and a melting point of 621°C, much lower than that of GeTe. As a result, its rate of crystallization is high, but its stability is less good than that of GeTe [CHO 06].

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Figure 5.14. Switching rates of GST and SLL cells (superlattice-like structure, GeTe/Sb2Te3) versus size: a) amorphization transitions (crystalline state, 10 kΩ → amorphous state, 300 kΩ) achieved with potential pulses of 5 V; b) crystallization transitions (amorphous state, 300 kΩ → crystalline state, 10 kΩ) achieved with potential pulses of 1 V. Adapted from [LOK 11]

The structuring of the PCM also contributes to the reduction of the amplitude of the potential pulses for both the Reset and Set transitions for a given Reset or Set switching time (Figure 5.15). Whatever the cell type (regular GST or SLL), the voltage necessary for the amorphization transition (Reset) is the smallest for pulse widths in the range 5–10 ns. It is smaller for an SLL cell, being about 2 and 0.5 V for corresponding diameters of 150 and 40 nm. In both cases, the applied voltage increases rapidly to 5 V as soon as the pulse width is smaller than 5 ns. A very small voltage value of 0.5 V is reached in the case of an SLL cell with a diameter of 40 nm for a pulse width of 10 ns (Figure 5.15(a)). The characteristics of the crystallization transition (Set) are similar to those of an amorphization transition. The voltages, however, are not as high, and the difference in amplitude between 40 or 150 nm GST and SLL cells is about 0.2 V. This is very much less than that observed with the Reset transition. Switching can be achieved with pulses of very low amplitude (0.5 V for a 40 nm diameter SLL cell), but for a minimum pulse of 40 ns (Figure 5.15(b)).

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Figure 5.15. Amplitudes and widths of potential pulses for the Reset (amorphization) and Set (crystallization) transformations for GST and SLL cells of different sizes (diameters: 40 and 150 nm, thickness: 35 nm ): a) amorphization transitions (crystalline state → amorphous state); b) crystallization transitions (amorphous state → crystalline state). Adapted from [LOK 11]

The endurance to cycling is also very good. In the case of an SLL cell (diameter 40 nm and thickness 35 nm) that is submitted to potential pulses of 2.5 V (amorphization) and 0.9 V (crystallization), 6 and 90 ns wide, respectively, an endurance of more than 107 cycles is reached without apparent degradation (Figure 5.16).

Figure 5.16. Endurance to cycling of an SLL cell (diameter 40 nm, thickness 35 nm) submitted to 6 ns pulses of 2.5 V (amorphization, Reset) and 90 ns pulse of 0.9 V (crystallization, Set). Adapted from [LOK 11]

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The resistances of the Reset (300 kΩ) and Set (10 kΩ) states remain fairly constant with cycling, with a constant ratio of 30. The maximum values of the current pulses for the Reset and Set transitions are 400 and 90 µA, respectively. The current for the Reset transition (400 µA) is relatively high and could be an obstacle to miniaturization, due to the fact that the size of the bipolar transistor that is essential for cell addressing is in the order of 1 µm for a current of 0.5 mA [RYU 11]. Comparable results were obtained by Simpson et al. [SIM 11], this also with alternating GeTe and Sb2Te3 layer cells, but with very small thicknesses of 0.5 and 4 nm. This increases the interfacial properties of the PCM layer, which is now referred to as interfacial phase-change material (IPCM). The current Ires is about 40% less than in a classical GST cell and the electric characteristics of IPCM are maintained over a long cycling period. This is evidence for the good stability of the material (Figures 5.17(a) and (b)).

Figure 5.17. Electric characteristics of nanostructured phase-change IPCM materials [(GeTe)4(Sb2Te3)2] and GST (Ge2Sb2Te5) for Set and Reset switching cycles carried out by a TiN heater of 75 nm diameter: a) first switching cycle; b) after 106 switching cycles (Set, Reset). Adapted from [SIM 11]

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The energies of the Set and Reset transitions are also much less than that of a standard GST cell for GST and IPCM cells of comparable dimensions (heating filament with a diameter of 75 nm), the energy consumption for the Reset transformation is three times smaller with an IPCM cell than for a GST cell (127 pJ, 3.5 V, 0.73 mA and 50 ns against 375 pJ, 6 V, 1.25 mA and 50 ns). It is just 11 pJ (1.5 V, 0.15 mA and 50 ns) for the Set transformation as opposed to 90 pJ for the GST cell (3 V, 0.3 mA and 100 ns). The endurance of the IPCM material to Set → Reset → Set cycling is far better than for GST, with, in particular, good conservation of the electric characteristics of the cell up to 109 cycles when the PCM is very thin (15 nm). This behavior differs from that of a GST-based cell. The latter runs correctly for a thickness of 40 nm and for as long as the number of cycles does not go beyond 106. This value drops significantly to 2 × 104 cycles when the thickness of the GST layer decreases to 15 nm (Figure 5.18) [SIM 11].

Figure 5.18. Characteristics of IPCM and GST cell cycling versus the thickness of the phase-change material layer. The diameter of the TiN heating filament is 75 nm. Adapted from [SIM 11]

5.3.3.2. Interpretation of structuring effect of GST layer on switching speeds The previous experimental results show that for a given active layer thickness, the amorphization (Reset) and crystallization (Set) transitions of the PCM gain in speed when the size of the cell

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decreases. This phenomenon is more noticeable in the case of an SLL cell than in the case of a conventional “homogeneous” GST (Figure 5.14). The increase in the crystallization rate when the size of the cell decreases is mainly due to the increase in the surface/volume ratio, as well as due to the fact that the heterogeneous surface crystallization rates are greater than those in the bulk material. In the case of a cell where the active region is cylindrical, Lee et al. [LEE 08] have shown that the ratio NS/NL of the crystallization rates, NL and NS, of two cells of diameters dL (large) and dS (small) is given by16: NS/NL = (dL/dS) exp[(Ea,L – Ea,S)/kBT The activation energies Ea,L and Ea,S are fairly similar. This leads to crystallization rates that are to a first approximation inversely proportional to the size of the cell. This is equivalent to: NS/NL ≈ dL/dS Not only does the size have an effect, but the structure of the PCM also contributes to the reduction in Set and Reset switching times. This can be seen as a cumulative effect with, on the one hand, the increase in crystallization rates due to a greater heterogeneity of the active material and, on the other hand, to the fact that the thermal conductivity of heterogeneous layers is anisotropic and globally smaller than that of a homogeneous layer. As a result, in the case of SLL layers, the thermal conductivity amounts to a third of that of a homogeneous layer of comparable overall composition [LOK 11, CHO 06]. This results in better heat confinement and thus a decrease in the current Im for the melting of the PCM as well as that of the IReset transition. The greater electric resistivity of the SLL layers has also the advantage of increasing the efficiency of the Joule effect. This improvement is not only due to a reduction in thermal conductivity. The very small thickness of the different layers that 16 The experiments are carried out using GST nanotubes of different diameters.

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make up the IPCM material induces a change in the direction of the crystallographic transformation. From tridirectional in the case of homogeneous GST, it becomes unidirectional with IPCM material, and thus decreases the entropy of the crystallization process17. According to Simpson et al., this could explain the increase in the cyclability [SIM 11] Another electronic effect has been considered by Wang et al. [WAN 08]. This concerns the potential threshold for which the conductivity of the amorphous state increases almost instantaneously, and helps an electric current strong enough to melt the material locally (Figure 5.3(a)). According to the authors, this sudden increase in conductivity could be related to the production of charge carriers resulting from electron impact ionization occurring over approximately 10 ps, followed by their recombination, which occurs over 1–10 ns. This time phenomenon is much shorter than what is usually obtained experimentally for phase-change systems and thus cannot be considered as the principal cause [SAV 05]18,19. However, this electron impact ionization would be of much greater significance with SLL-type cells. With the increase in the surface/volume ratio, the number of pendant bonds increases along with the number of located electrons and non-bonded atoms. This increases the concentration of free charge carriers. The presence of free charges and the decoupling of atoms and electrons cause electrostatic interaction forces that lead to a distortion of the network and, consequently, assist the structural transition, i.e. the phase change [WAN 08]. 17 Activation energy Ea, strictly equal to the free activation enthalpy: ∆G = ∆H - T∆S, decreases when entropy increases. 18 The theory of impact ionization was experimentally demonstrated in 1980 with amorphous selenium. It can be applied to other amorphous semiconductors such as Ge2Sb2Te5. A detailed description is given by Jandieri et al. [JAN 09] and Rubel et al. [RUB 11]. 19 The same conclusions in terms of switching speed can be drawn from the more classical mechanism by Ielmini et al. [IEL 07], which has the advantage of being based on more familiar experimental facts (see section 5.1.2).

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The better endurance to cycling for an SLL or IPCM cell is also related to the higher surface/volume ratio. Kim [KIM 09] and Yang [YAN 09] showed that the main reason behind the failure of a GST cell is the diffusion of atoms toward the electrodes, which is more pronounced when the thickness of the GST becomes very small. In the case of a material composed of alternating and ultra-thin GeTe and Sb2Te3 layers, the diffusion of the atoms toward the electrodes is attenuated. The effect of this is to conserve the structure of the alternating layers in the region subject to heating. This could explain why much longer cycling periods are obtained with an IPCM cell than for a homogeneous GST cell [SIM 11]. 5.3.4. Recent techniques for improvement of amorphization and crystallization rates of phase-change materials The previously described results show that the Reset → Set and Set → Reset transformations are of thermal origin. In the case of the transition leading from the amorphous state to the crystalline state, the current must not be too high so as to avoid melting the material. This requires relatively long switching times and low currents. The opposite Set → Reset transformation, which implies melting followed by a rapid cooling, requires on the contrary that a high current should be delivered in a short pulse. In best conditions, the write speeds (Set) have switching times greater than the nanoseconds whereas erase (Reset) can be achieved in a few tenths of a nanosecond. Reducing crystallization time beyond the nanosecond is equivalent to reducing the activation energy of the crystallization process. Unfortunately, this results in a degradation of the stability of the crystalline state and leads to reduced data retention times. Very recently, new procedures applicable to amorphization and crystallization of the PCM have been suggested in order to reduce switching times. This could bring PCRAM memory performances up to a standard high enough to be close to storage class memories.

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5.3.4.1. New procedures for improving crystallization rates without modifying retention properties The process of crystallization begins with a first stage of nucleation that leads to the formation of crystallites. The following step corresponds to the growth of these crystallites. The first step is faster at low temperature, whereas the rate of crystallite growth increases with the temperature [LOK 12]. The idea suggested by Loke et al. [LOK 12] in Cambridge is to start by applying a weak electric field to the PCM (0.3 V for a GST thickness of 30 nm, equivalent to 105 V/cm). The effect of this is to cause a low-amplitude variation in temperature that induces a preorganization of the material by generating clusters containing crystallization seeds. The final crystalline state is obtained by applying a second, stronger electric field pulse to the material (about 1 V, equivalent to 3.3 × 105 V/cm). The pulse width of the Set transition is even less when the potential pulse is higher. Thus, with a cell of 30 nm thickness and 50 nm diameter, the Set switching, carried out by applying a continuous polarization of 0.3 V, followed by a potential pulse ranging from 0.5 to 0.95 V, requires pulse widths that vary between 14.5 and 0.5 ns, respectively (Figures 5.19(a) and (b)).

Figure 5.19. Effect of a continuous weak electric field on the Reset → Set transition rate of a PCM cell (diameter 50 nm, thickness 30 nm): a) potential pulse (0.9 V) superimposed on a constant polarization of 0.3 V; b) relationship between the minimum pulse potential and its width to induce the Set transition in the presence of a constant polarization of 0 V or 0.3 V. Adapted from [LOK 12]

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More importantly, for the same pulse potential, the Set transition is faster when the PCM is subject to a constant polarization. In the example of a potential pulse of 0.95 V, the Set switching is 15 times faster when the material is continuously polarized at 0.3 V (0.5 ns for a continuous polarization of 0.3 V and 7.5 ns for 0 V)20. The authors also show that the use of this double polarization of the PCM does not deteriorate its data retention properties. Indeed, prolonged cycling of 104 cycles between the Set and Reset states does not lead to any visible signs of degradation (Figure 5.20(a)).

Figure 5.20. Endurance to cycling of a PCM cell (50 nm diameter) between the Set and Reset states. a) The cell is submitted to a continuous voltage of 0.3 V and to potential pulses (0.5 ns width) of 1 V and 6.5 V for Set and Reset transitions, respectively. b) Pulse width variation versus cell size and in the presence or absence of continuous polarization at 0.3 V in the case of the Set transition. Adapted from [LOK 12]

In the presence of double polarization, reduction in the cell size also accentuates the relative reduction of the pulse width corresponding to the Set transition. For a 300 nm PCM, the relative decrease in the pulse width is about 28% in the presence of a continuous polarization of 0.3 V, and 95% when the cell size is 50 nm (Figure 5.20(b)). This effect of size reduction adds to that of continuous polarization and contributes to increasing the nucleation speed and crystallite growth. 20 The continuous polarization of 0.3 V is a maximum value. A value greater than 0.3 V leads to a Set transition.

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5.3.4.2. Amorphization without melting induced by electric pulses of a few hundred picoseconds The reverse transformation of the crystalline state (Set) toward the amorphous state (Reset) is generally achieved by melting the material and then cooling rapidly. This requires high currents and pulse widths that vary with the size of the cell and that generally are a few nanoseconds. Miao et al. [HUA 11, WAN 13] recently showed for GST that the pulse widths can be considerably reduced to a few tenths of a nanosecond without the need of melting the PCM (Figure 5.21). Their demonstration is based, first, on observation of the changes in resistivity caused by pulses of a few hundred picoseconds and, second, on the fact that the heat released by the Joule effect with such short-lived impulsions does not allow us to go beyond a temperature of 60°C, which is not enough to melt the GST, thus implying a mechanism different from the thermal process induced by pulses of a few nanoseconds21. Their interpretation also relies on the principle of electronic impact ionization (see section 5.3.1.3), a process that would induce the failure of the bonds without melting, as shown in Figure 5.22. In favor of this mechanism, the authors consider that for a voltage threshold VT, the charge carriers acquire enough energy to cause the ionization of bonds such as Ge–Te, Ge–Sb and Sb–Te in GST. Thus, in the case of a 50 nm thick GST layer, if the mean free path of the electrons is 7.2 nm for a non-elastic diffusion process, the kinetic energy acquired by the electrons for a voltage of 4.2 V can be estimated as 604.8 meV. The energy that is released following one or 21 The authors simulated the heat released by a potential pulse of 3.5 V (50 and 0.8 ns wide) in a GST cell at the crystalline state (Set). The GST is 150 nm thick and the contact electrode has a diameter of 1 µm. By taking the electric and thermal characteristics of GST into account, they showed that with the 50 ns pulse the temperature reached by the cell is 700°C. With a 0.8 ns pulse, however, the maximum temperature does not go beyond 65°C, which is not enough to cause melting.

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more collisions is then far greater than that of the GeTe3 (420.45 meV) or GeTe (757.59 meV) bonds, and can then lead to the amorphization of the material [WAN 13].

Figure 5.21. Amorphization of GST without melting. The Set state is previously established by applying a long (0.5 ms) pulse of amplitude 0.1 mA. a) Potential pulse width required for the Set → Reset transition with 2.4, 3 and 4.2 V pulses for a 50 nm thick GST cell; b) Reset pulse width versus voltage pulse amplitude for different GST layer thicknesses. The contact electrode is about 1 µm in diameter. Adapted from [WAN 13]

Figure 5.22. Interactions between electrons and matter: a) non-elastic interaction process with creation of phonons and b) ionization by impact followed by bond rupture. Adapted from [WAN 13]

5.3.5. Problems related to interconnection of PCRAM cells in a 3D crossbar-type architecture The possibility of connecting cells in a crossbar-type architecture is a great advantage with respect to integration density. This is

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determined by the width F of the write line, leading to a contact area of 4F². This is the smallest area possible, given the current limits of lithographic technology. 3D Integration, including n-stacked layers of cells, is equivalent to artificially dividing the contact area by n. Crossbar geometry has advantages, but has also a drawback regarding the addressing of one cell. Indeed, a cell interacts with its neighbors so that the current corresponding to an ON (Set) or OFF (Reset) state may be disturbed by adjacent cells that induce parasite conduction paths. Figure 5.23, as an example, representing an array of nine resistive cells, shows clearly the presence of leakage currents. The vertically arranged resistive cells (Cxiyj) are connected to two horizontal conductive lines which are perpendicular to each other and are numbered x1, x2, x3 and y1, y2, y3 (equivalent to the bit lines and word lines in Flash cell arrays).

Figure 5.23. Crossbar array of nine resistive cells. Adapted from [LIN 10]

COMMENTS ON FIGURE 5.23.– The cell Cx2y2 (in gray) whose resistive state has to be measured is presumed to be in the OFF state. The neighboring cells x3y2, x3y3 and x2y3, however, are in the ON state. The read voltage applied between x2 and y2 lines produces the current Ielement and the leakage current Isneak in the cells Cx3y2, Cx3y3 and Cx2y3 so that the read current Iread is the sum of Isneak and Ielement, thus leading to a wrong reading of the resistive state of Cx2y2.

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The cell referred to as Cx2y2 is, therefore, connected to the conductive lines x2 and y2 and it must be possible to read its resistive state directly by applying a voltage between lines x2 and y2. In fact, because of the passive nature of the PCM cell, the current resulting from the application of the reading voltage is distributed between Ielement, which is the current through Cx2y2, and Isneak, the leakage current through the neighboring cells. As a result, in the case where cell Cx2y2 is in the OFF state and the neighboring cells Cx3y2, Cx3y3 and Cx2y3 are in the ON state, it is obvious that the measured current supposed to represent Cx2y2 is practically equal to the leakage current. This leads to a misinterpretation of the resistive state of Cx2y2. One of the solutions for solving this problem is to implement an access device (AD) in series with each cell. This can be achieved with a diode D or a transistor T. This will switch off the leakage circuit and the current Ielement is fully recovered. The resistive cell is then of type 1R1D or 1R1T. The high value of the IReset current that is necessary for restoring the PCM cell from its crystallized state to its amorphous state is another intrinsic problem of PCRAM cells. Current densities may exceed 107 A/cm2. Such values require transistor or diode sizes that are incompatible with a miniaturization of PCM cells beyond 20 nm [BUR 10]. Recently, IBM found a solution which consists of using a resistive-type cell using mixed ionic electronic conductivity (MIEC) materials as an access component to the PCM cell [GOP 10]. 5.4. Conclusion Since the early 2000s, phase-change memories have been considered as one of the most plausible candidates to replace Flash memories. This is especially due to their operating speeds that are 1,000 times higher, and their manufacturing costs that are far lower than those of Flash memories. The simplicity of the crossbar architecture greatly contributes to this. The high value of the amorphization current, which corresponds to the Reset state and implies the implantation of an access transistor of

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significant size, has been a limiting factor for high integration densities [CHO 06, HOR 03]. This difficulty should be overcome soon, and new solutions have been suggested. Changes in PCM composition, as well as its ultrafine layer structuring (GeTe and Sb2Te3), increase the performances of PCM while significantly reducing switching times and guaranteeing endurance to more than 109 cycles, performances which are far better than those of Flash memories. The recent discovery of new crystallization and amorphization mechanisms with switching times of a few hundred picoseconds, comparable to those of SRAM memories, leads to new prospects for non-volatile PCM memories which may attain the category of storage class memories in the future.

6 Resistive Memory Systems (RRAM)

In the 1960s, thin layers of insulating and amorphous metal oxides (I) inserted between two metal electrodes (M) to form M/I/M tunnel junctions were the focus of many studies. After an electroforming (EF) process, performed by polarizing the device for variable lengths of time, the system was found to switch between two different resistive states corresponding to ON and OFF memory states. Variations in conductivity associated with these states are qualitatively comparable to those observed with phase-change materials, but differ in the electrochemical nature of the transformations, which correspond to the formation and failure of conductive filaments. Hickmott was one of the first researchers to observe memory effects of a resistive nature with M/I/M devices such as Al/SiO/Au, Al/Al2O3/Au, Ta/Ta2O5/Au, Zr/ZrO2/Au, and Ti/TiO2/Au [HIC 62, HIC 64, HIC 65]. Resumed by Simmons and Verderber [SIM 67] as well as Daernaley et al. [DAE 70], these works were neglected for a long time, in part because of the invention of the floating-gate MOSFET by Khang and Sze [KHA 07], which was a great success at that time. This same invention led, a decade later, to electrically erasing programming read only memory (EEPROM) memories (Intel 1980 and Toshiba 1980) followed by the Flash memories (Toshiba, 1980) a decade later. As seen previously (see Chapter 1), the need for increasingly efficient and miniaturized memories has led to the scale limit being

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reached (16–20 nm) for Flash memories, beyond which it is very difficult to make any progress. These memories had previously been thought to be a good substitute for hard drives (see Chapter 2). The new trend is to have ever-smaller “universal” memories, capable of fulfilling storage and read-write tasks, close to the storage class memory (SCM) concept. Phase-change random access memories (PCRAM) and spin-torque transfer magnetic memories (STT-MRAM) have characteristics that correspond in part to these new requirements; consequently, the International Technology Roadmap for Semiconductors (ITRS) considers them as possible substitutes for Flash memories [ITR 10]. In concordance with this tendency, there has been a regain in interest for resistive memories (RRAM) after the very promising results obtained for the first time by Beck et al. at IBM (Zürich, 2000) [BEC 00]. The authors showed that a chromium-doped perovskite (SrZrO3-Cr) sandwiched between two electrodes (SrO3 and Au) leads to switching times between two ON (low resistance) and OFF (high resistance) states that are far shorter to those of Flash memories (100 ns at ±5 V). With this device, retention times and endurance to cycling are constant over a period of 10 months, and it is possible to make multi-level memories. These new and encouraging results probably account for the increase in the amount of research in this field. Since 2004, there has been a considerable increase in the number of publications on RRAM memories. Bibliographic browsing using the key words “resistive switching memory” clearly shows that the interest of the scientific community, which was almost non-existent around 2000, has grown considerably since 2004–2005 to reach more than 500 publications in 2013, and more than 8,000 citations (Figure 6.1). In the search for resistive properties that are compatible with the development of efficient memories, only a few metal oxides have been targeted and studied. Most concerned NiO [SEO 04] (Samsung), TiO2 [CHO 05] and, more recently, HfO2, the last metal oxide giving the best performances (Figure 6.2).

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The simplicity of the manufacturing process for resistive cells (a single material that can be placed in crossbar-type architecture between two conductive lines) is a considerable advantage in terms of miniaturization as well as manufacturing costs.

Figure 6.1. Evolution in the number of publications between 1990 and 2013, including January 2014. The diagram is a result of the search for “resistive switching memory” from the Thomson Reuters databases. Adapted from Web of Science

Figure 6.2. Comparison between the number of publications on HfO2, TiO2 and NiO resistive memories. Recent interest in HfO2 since 2010 continues to increase, in contrast to NiO and TiO2 that has regressed. The diagrams are made using the Thomson Reuters databases and by searching for “HfO2, TiO2 and NiO resistive switching”. Adapted from Web of Science

When the current qualities of Flash memories are taken into account, it is obvious that resistive memories (RRAM) are only of interest if they are capable of outdoing the performances of the former. As indicated by the ITRS in its 2010 edition [ITR 10], switching speeds, endurance, retention, integration density (scalability) as well as energy consumption have to be far better than those of Flash memories (Table 6.1).

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Endurance : > 107 cycles (Flash 103 -107) Resistance ratio : ROFF/RON > 10 Read current : ION ~ 1 µA for a contact area 100x100 nm2 ( 104 A/cm2) Scalability : F < 22 nm, and/or 3-D stacking Write voltage : 1 – 5 Volts (Flash > 5 Volts) Read voltage : 0.1 – 0.5 Volts Write speed : < 100 ns (Flash > 10 µs) Retention : > 10 years

Table 6.1. Operational norms that must be met by resistive memories (RRAM) to compete with and outdo NAND Flash memories. Adapted from the ITRS 2010 report [HUT 10]

6.1. Main characteristics of resistive memories Generally, a resistive memory is an M/I/M(M’)-type or M/SC/M(M’)-type device where I or SC is a low-conductivity dielectric (electronic and sometimes ionic) or a semiconductor sandwiched between two identical (M) or different (M, M’) metals. The system can be considered as a programmable electronic device where the resistivity is a function of earlier treatment. They were referred to as memristors by Chua in 1971 [CHU 71], a concept that was later experimentally confirmed by Strukov et al. [STR 08]1. With regard to terminology, resistive memories are usually classified according to their switching characteristics relative to two different resistive states, corresponding to symmetrical and asymmetrical I/V curves. The transition from a high resistance state (HRS) to a low resistance state (LRS) corresponds to the Set transition, and the reverse transformation LRS → HRS corresponds to the Reset transition. These are obtained using different polarizations. If the polarizations of the Set and Reset transitions are of the same sign (Figure 6.3(a)), the systems are unipolar. If these polarities are of the opposite sign (Figure 6.3(b)), the systems are bipolar. 1 For further details on memristors, the review article by Pershin et al. [PER 11] is of interest.

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Figure 6.3. Diagram of I/V curves corresponding to a) unipolar and b) bipolar M/I/M memristors. The current I1 or - I1 is a compliance imposed on the system so as to prevent deterioration. Adapted from [WAS 07]

6.1.1. Unipolar system The Set and Reset transitions occur for polarizations ±V1 and ±V2, respectively (Figure 6.3(a)). In the OFF state, the current between the two electrodes is very small as long as the voltage is below V1. It increases very rapidly to reach a limiting value I1 imposed by the apparatus (current compliance) when the voltage is equal to V1. As a result, the system evolves from a high-impedance (OFF) state toward a low-impedance (ON) state. This is the Set (V1 → I1) transition that can be achieved in an identical manner by operating with opposite voltages and negative currents (–V1 → -I1). In the ON state, the system generally has ohmic behavior, where the current I varies linearly with the voltage. When I2 (I2 > I1) is reached corresponding to V2, the conductivity rapidly drops and the OFF state is restored. This is the Reset (I2 → V2) switch that is also observed for negative I and V values (-I2 → -V2). This type of behavior is found in thermochemical switching processes that occur whatever the polarities. The typical case is that of phase-change memories PCM (see Chapter 5) and of some metal oxides.

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6.1.2. Bipolar system As opposed to unipolar systems, Set and Reset transitions occur for polarizations of opposite sign. As a result, if the Reset transition of the ON state toward the OFF state takes place with a positive voltage V2 (I2 →V2), then the return to the ON state (Set transition) occurs with a negative potential –V1 (–V1→ –I1), with V1 generally different from V2 (Figure 6.3(b)). An electrochemical metallization memory (ECMM) made up of an ionic conduction solid and an oxidizable metal electrode (Ag, Cu) is the typical example of a bipolar system. Switching between two resistive states is due to the formation and rupture of metal filaments, formed between the two electrodes, due to the migration and reduction of Ag+ or Cu+ cations resulting from oxidation of the Ag or Cu electrode. Valence-change memory (VCM) systems consisting of an insulating oxide and inert metal electrodes also have resistive behavior that is often bipolar. They also correspond to an electrochemical process, with, however, a significant difference from that of ECMM systems. The metal of an electrode is no longer responsible for the formation of conductive metal filaments. Instead, it is the insulator that is subject to local chemical modifications that, in turn, lead to the formation of conductive filaments, the latter being non-metallic and responsible for variations in conductivity. The changes in state are locally due to the migration of anionic species (O2−) combined with a thermal effect and the reduction of metal cations of the network2. Given these mechanisms, ECMM and VCM systems are also considered Redox memories, and the difference between ECMM

2 It must be noted that the reduction of metal cations, often mentioned in studies on valence-change memory systems, could lead to the formation of conductive metal filaments, but this possibility has not been further developed.

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and VCM is sometimes defined by referring to ECMM and VCM systems as “cation memory devices” and “anion memory devices”, respectively [YAN 13]. 6.2. Electrochemical metallization memories The operation of the device relies entirely on an electrochemical process involving the formation and failure of a metal nanofilament that closes or opens a contact between two electrodes, thus inducing the ON and OFF conduction states, respectively. This phenomenon was observed for the first time by Hirose et al. toward the end of the 1970s [HIR 76]. The principle is therefore similar to that of electromechanical switches (Chapter 3), but without mechanical movement. As mentioned previously, one of the electrodes of the MIM device is an electro-active metal (generally Ag or Cu), the other electrode being an inert metal (Pt, Au, W, Ru, etc.). The material sandwiched between the two electrodes is an ionic conduction material (Ag2S, Cu2S) or an insulating or semi-conductive material such as Ta2O5, SiO2, HfO2, WO3 and ZnO3. The different steps corresponding to the Set and Reset transformations of the ECMM device, switching from the OFF to the ON state, and from the ON to the OFF state, respectively, are illustrated in the case of the Ag/Ag2S/Pt device (Figure 6.4). The first step, “electroforming”, consists of the formation of the first conductive filament in the electrolyte. This is achieved by applying a voltage corresponding to the oxidation of silver (Figure 6.4(a)): Ag – e- → Ag+

3 An exhaustive list of the different insulators, solid electrolytes and electrodes used for making ECMM memories can be found in reviews by Yang et al. [YAN 13] and Valov et al. [VAL 11].

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The Ag+ ioons producedd migrate un nder the influuence of the electric fieeld and are reduced r at thhe platinum cathode c to form fo a silver deposit coorrespondingg to the reverrse reaction: Ag+ + ee → Ag (metal) This depossit grows andd spreads to form f a silverr metal filam ment that makes contactt with the sillver electrodee (ON state) (Figures 6.44(b) and m (cc)); the reverrse polarizatiion causes th he failure off the filamennt (OFF staate).

Figure 6.4. Electrochemical formation off a silver filameent in the case of an dapted from [VA AL 11] [Ag/Ag2S/Pt] component. Ad

COMMENTS O ON N FIGURE 6.4 4.– a) System m is in the innitial OFF sttate; the cuurrent is neggligible whenn the Ag eleectrode is negatively poolarized. b)) When the Ag A electrodee potential is i increased,, oxidation rreleases Agg+ cations thhat are reduced at the ca athode (Pt) to metallic A Ag. c) A neew increase in i the Ag eleectrode poten ntial makes the t filament grow in the opposite direction d to the Ag+ ion drift, until a contact is formed N state. d) P Polarity wiith the silveer electrodee and leads to the ON innversion folloowed by heatting of the fillament leadss to its failuree and to

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the recovery of an OFF state. The current corresponding to the Set transition is a few dozen µA and is fairly independent of the contact area as well as the thickness of Ag2S. It must be noted that this new OFF state is different from the initial OFF state because the distance between the silver electrode and the platinum electrode has been shortened. This implies a much faster new Set transition compared to the first EF transition (Figure 6.4(d)). Concerning the switching rates, it must be noted that this formation of filaments implies a cation migration whose rate depends on the electric field. In the case of solids, this rate is very low compared to an electron transfer. Switching times are expected to depend on the sandwiched material (insulator or electrolyte), on the strength of the electric field (determined by the voltage applied between the two electrodes, as well as the thickness of the insulator or electrolyte) and on the method used for the preparation of the oxide, which can induce defects and variations in conductivity4. Another important point is that this metallization process is based on an electrochemical redox reaction of a metal (Cu and Ag). Thus, it occurs at very low switching voltages (generally less than a volt). As a result, in the example of a silver electrode and the Ge0.3Se0.7 electrolyte, the Set and Reset transitions occur with voltages of 0.3 V and −0.1 V, respectively, and with currents ISet of a few dozen µA. Although switching between ON and OFF states results from an ionic migration process, which is much slower than electron transfer, extremely short switching times are nevertheless obtained with devices of nanometric dimensions. One promising and particular case is found 4 The motion of an ion in an electrolyte is conditioned by the presence of defects mainly in the solid, Frenkel or Schottky defects. In a Schottky defect, a cation and an anion have left the sites they occupied in the crystal, creating two holes. On the contrary, in a Frenkel defect, an ion has left the site it occupied to move to an interstice in the crystal. The mobility µ of an ion (speed per unit of electric field) and its ionic conductivity σ in the crystal (σ = Nqµ, where N is the number of charges per unit of volume and, q is the electric charge of the ion) are determined by the speed of the ion moving toward the vacant sites corresponding to the holes and interstices of the network [KUM 06].

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when the contact between the two electrodes is obtained by metal filaments whose diameters are up to a few atoms. These filaments have a quantized conductance that varies in integer multiples of the conductance quantum GO. The formation and the rupture of these filaments therefore constitute an atomic switch [TER 05]. 6.2.1. Atomic switches Terabe et al. in Japan were the first to demonstrate a “metallization resistive memory” capable of functioning as an atomic switch by using an Ag/Ag2S/Pt-type metallization cell [TER 05]. One of the significances of the system lies in the possibility of controlling the formation and the failure of the conducting filament over a length of 1 nm. This is equivalent to maintaining a space of 1 nm between the platinum electrode and the Ag2S electrolyte. This particular device is obtained by successively depositing through evaporation a 1 nm-thick layer of silver onto Ag/Ag2S followed by a deposit of platinum on top of the silver layer, thus leading to the Ag/Ag2S/Ag(1 nm)/Pt structure. In the initial setup, the Ag/Ag2S and Ag(1nm)/Pt electrodes are disposed in a crossbar architecture consisting of two lines and one column (Figures 6.5(a) and (b)). When a positive polarization is applied to the platinum electrode, the silver layer under the platinum electrode is oxidized and dissolved, thus creating a space of about 1 nm between the Pt and the Ag/Ag2S electrolyte. This is equivalent to an EF step corresponding to the initial OFF state (Figure 6.5(c)). As a large amount of silver is initially present, this OFF state is only formed after a relatively long polarization lasting a few seconds. After this OFF state (R ~ 100 kΩ) is produced, the formation and failure of metal filaments, where the smallest diameter is on the atomic scale, is possible (Figure 6.6(a)). This is achieved by the successive application of positive and negative voltages of a few hundred mV between the two electrodes. The transport of electrons through this filament is ballistic, without the Joule effect, and the conductance of the whole device is controlled by the finite number of

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atoms making up the contact at the smallest diameter of the nanowire connecting the electrodes. Breaking the conduction path requires the displacement of a few atoms; this corresponds to a “quantized conductance atomic switch” (QCAS). One interesting feature is that multiple conductance “plateaus” at 1, 2 and 3 GO are obtained by successive pulses of potential of 200, 100 and 80 mV (each 50 ms wide), corresponding to filament diameters of atomic dimensions (1, 2 or 3 atoms) (GO is the conductance quantum unit equal to 2e2/h, e: electron charge; h: Planck’s constant, 1/GO= 12.9 kΩ). The OFF state is restored by applying a potential pulse of opposite polarity and leads to a resistance of 100 kΩ. The time required to make the Set transition corresponding to the formation of a 12.9 kΩ filament (1/GO) is also a function of the applied potential. It varies from approximately 0.1 s to 100 ns when the voltage increases from 100 to 300 mV (Figure 6.6(b)) [TER 05].

Figure 6.5. Quantized atomic conductance switch device. Adapted from [TER 05]

COMMENTS ON FIGURE 6.5.– a) Representation of the electric circuit comprising two platinum leads parallel to each other, and

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perpendicular to the Ag/Ag2S line. The platinum and Ag2S leads are 100 and 150 nm wide, respectively (TEM image of the inset). b) Diagram of the device showing the 1 nm thick silver deposit between the platinum and Ag2S, thus corresponding to the ON state of the memory. c) The first OFF state is reached with the dissolution of the silver layer. d) Restored ON state with the formation of a small highly conductive atomic silver bridge. The device runs at room temperature in vacuum as well as in ambient atmosphere. Switching between the two ON and OFF states with voltages of ±600 mV was obtained at a frequency of 1 MHz. According to the authors, this frequency is, in fact, limited by the capacitance of the device and could be made to reach the GHz, equivalent to switching times close to the nanosecond. Endurance to cycling has been tested over periods of more than 105 cycles without any apparent deterioration of the characteristics of the device. By associating two switches in parallel, the authors also showed the possibility of making AND, OR and NOT logic gates. These low voltages, which are of interest from an energy viewpoint, are deemed too low, however, to be compatible with a logic circuit for which the required voltage is greater than 1 V [BAN 06].

Figure 6.6. Switching characteristics of the nanometric Ag/Ag2S/Pt component. Adapted from [TER 05]

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COMMENTS ON FIGURE 6.6.– a) Set transitions are achieved for successive potential pulses 50 ms wide and with an amplitude of (1) 200 mV, (2) 100 mV and (3) 80 mV. These transitions lead to conductance plateaus whose heights are multiples of GO = 2e2/h. Reset transition (4) is obtained by applying 260 mV with a polarity opposite to the previous Set transition. b) Switching times of the Set transition (OFF → ON) versus the applied voltage. Adapted from [TER 05]. Change in the solid electrolyte by Cu2S, Ta2O5 and Nb2O, or its replacement by an insulator (SiO2) or a semiconductor (ZnO) has led to new research and brought the switching voltages to around a volt. Cu/Ta2O5/Pt, Cu/SiO2/Pt and especially Ag/ZnO/Pt are three examples of metallization memories (not envisaged as atomic switch memories) which have also been developed. 6.2.2. Metallization memories with an insulator or a semiconductor 6.2.2.1. Cu/SiO2/Pt metallization memory An increase in the Set voltage is indeed observed when a solid electrolyte is replaced by an insulator such as SiO2. The “electroforming” (EF) voltage necessary for the production of metal filaments is also higher; it is assumed to induce, in a strong electric field, the formation of pores or channels which favor ion transport. Schindler et al. [SCH 09] have shown that an initially insulating [Cu/SiO2/Pt] device, consisting of a 15 nm thick SiO2 layer, becomes conductive when the copper electrode is polarized at 4 V. This EF voltage is much higher than for an electrolyte due to the very low ionic conductivity of SiO2 (Figure 6.7(a)). Once this first EF step is achieved, the voltages corresponding to new Set transformations are then close to 1.5 V. It is worth noting that this EF voltage, which corresponds to the formation of metal filaments, increases linearly with the thickness of the insulator, whereas those corresponding to the successive Set transformations (observed for much lower voltages of 1.5 V) are independent of thickness (Figure 6.7(b)).

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Figure 6.7. Electric characteristics of a metallization [Cu/SiO2/Pt] memory cell (diameter 75 µm). Adapted from [SCH 09]

COMMENTS ON FIGURE 6.7.– a) I/V electroforming curves with successive Set and Reset cycles. Electroforming is achieved by polarizing the copper electrode at 4 V (VForm) and limiting the current to 10 nA (compliance current (CC)). The following Set and Reset transitions occur at 1.5 and −0.3 V, respectively. b) Electroforming and successive Set transition voltages (obtained after the first electroforming step) versus SiO2 thickness. This relationship between the electric field and EF confirms the mechanism whereby Cu+ ions migrate in the insulator. The fact that the following Set voltages are independent of the thickness of the insulator indicates that the failure of the filaments only occurs over a very small portion of the conductive region. Thus, as with a solid electrolyte, the filament is restored more rapidly and more easily. The Reset transition is obtained by reversing the polarity and applying a few hundred millivolts. 6.2.2.2. Ag/ZnO/Pt memory device At the same time as Schindler et al. [SCH 09], Yang et al. [YAN 09b] developed a resistive metallization memory with a zincoxide “pseudo-electrolyte” doped with 3% of manganese.

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The performances of this metallization memory are impressive: ultra-fast ON/OFF programming speeds with switching times of 5 ns, for voltages of ±3 volts with a ROFF/RON ratio of 107, retention times greater than 107 s as well as good endurance to cycling at high temperature. The fact that the device can be elaborated at room temperature using cathodic sputtering is another advantage. The memory cells are sandwiched structures of 300 µm in diameter, comprising an Ag electrode, a manganese-doped ZnO film (ZnO:Mn) and a platinum electrode with thicknesses of 90, 30 and 120 nm, respectively. The I/V curves are typical of a bipolar memory with Set and Reset voltages of 2 and –2 V, respectively (Figure 6.8(a)). Conduction in the Set state is ohmic and confirms the formation of Ag metal filaments, the diameters of which have been estimated by scanning transmission electron microscopy (STEM), combined with energy dispersive X-ray spectroscopy (EDX) analysis, to be between 30 and 50 nm.

Figure 6.8. I/V characteristics of a [Ag/ZnO:Mn/Pt] metallization memory. a) Linear I/V curves. b) Logarithmic I/V curves. The numbers 1.06, 2.03, 10 and 1.00 represent the slopes of different linear segments corresponding to the different conduction mechanisms of the OFF and ON states. Adapted from [YAN 09]

Conduction in the Reset state is more complex and corresponds to a mechanism controlled by the trapping/detrapping of charges (spacecharge limited conduction (SCLC). Ohmic for very small values of V, the current becomes proportional to V2 for intermediate voltages

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below 1.2 V (Child’s law), and then to Vn (n = 10) before reaching the ON state (Figure 6.8(b)). Manganese is a strongly electron-donating element that increases the resistivity of the component at the OFF state. According to the authors, this increase in resistivity could be due to the neutralization of structural defects in the ZnO (interstitial zinc, positive oxygen vacancies (VO2+)) and the transformation of Mn into Mn2+, equivalent to the production of a high concentration of traps in the semiconductor, responsible for an SCLC-type mechanism. One of the critical aspects of this kind of memory, however, is the relatively high dispersion of the VSet and VReset voltages, corresponding to the ON and OFF states which, from the practical point of view, is a problem for logic circuits. This variability of voltages, especially important with VSet, is due to the stochastic nature of nucleation and the growth of filaments, which depends very much on the structure of the insulator into which they are inserted. This is a general problem that is found both in VCM and ECM memories. Among the different solutions considered, Liu et al. [LIU 10] suggest that the reproducibility of filament formation could be improved by favoring their directional growth. This requires us to focus and increase the electric field at certain points of the surface of one of the electrodes. An [Ag/ZrO2/Pt] device was made in which copper nanocrystals (Cu NCs) were inserted at the Pt-ZrO2 interface (Figure 6.9)5. The presence of Cu NCs increases the nucleation rate of the silver atoms at the top of the NCs. This favors directional growth of the silver filament from the cathode toward the Ag electrode. An undeniable improvement in the reproducibility of the VReset and VSet voltages is observed with this device (Figure 6.10). 5 Copper NCs are obtained by successive deposition of a film of Cu and ZrO2 by e-Beam, with thicknesses of 3 and 20 nm, respectively. Annealing at 600°C in a nitrogen-rich environment for several seconds produces the copper NCs shown in Figure 6.9.

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In cells with Cu NCs, the variation of VSet is less than 1 V (VSet is held between 0.30 and 1.2 V, Figure 6.10(b)), whereas it is much larger (about 3 V) with the Ag/ZrO2/Pt reference cells, and ranges from 0.5 to 3.5 V (Figure 6.10(b)).

Figure 6.9. TEM images of the [Au/Ag/ZrO2/Pt] device with copper NCs at the Pt-ZrO2 interface. a) Electric circuit. b) TEM cross-section of the device. c) TEM image of a silver filament grown from a copper NC. Adapted from [LIU 10]

For the Reset voltages, the effect of the NCs is less significant. This is understandable, as this situation involves the failure of filaments in which the NCs do not play any role. The variation of VReset, of 0.5 V for the cells with Cu NCs (VReset varying between −0.75 and −0.25 volt), is only slightly less important than with the reference cells without Cu NCs for which VReset varies between −1.5 and −0.5 volt, i.e. a variation of 1 V, approximately (Figure 6.10(b)).

Figure 6.10. Dispersion of voltages VReset and VSet observed for 50 Set–Reset cycles made with 5 cells, each 3 × 3 µm2. a) Cell with copper NCs. b) Reference cell without NCs. Adapted from [LIU 10]

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6.2.3. Conclusions on metallization memories These examples show that a very large variety of metallization memories can be elaborated, with the choice of an oxidizable metal (silver or copper), and so does an insulator with ionic-type conduction (solid electrolyte). The resulting performances are very promising: Set and Reset switching times of a few nanoseconds have been obtained with read and erase voltages of just a few volts. Endurance to cycling (greater than 105) and retention times of 10 years for certain systems greatly exceed the performances of Flash memories. The switching mechanisms, typical of bipolar memory cells, clearly demonstrate the electrochemical formation of metal filaments. However, the spread in switching voltage values remains a major problem. This can be reduced with a better focalization of the electric field, achieved by inserting Cu NCs into the cathode. The fact that these memories are relatively easy to produce is a considerable advantage, facilitating the use of crossbar architecture and the possibility of three-dimensional (3D) integration. This could provide very small equivalent cell areas of 4F2/n for systems with n layers. Memories with atomic switches present a particularly attractive and extreme case of metallization memories. The best performances announced so far include a device smaller than 10 nm width, switching times close to the nanosecond, retention times of 10 years, cyclability of 105 cycles and control voltage below 1 V [AON 13]. These performances compete with that of the PCRAM (phase-change memories) already at the prototype stage in many companies. The use of a solid polymer electrolyte (see Chapter 7), the development of photosensitive atomic contacts and the extension of these systems to three-electrode configurations are some of the current research directions. Another direction that seems equally promising consists of the use of the synaptic characteristics of atomic contacts to make neural circuits with learning capabilities. One of the major advantages of this last type of memory lies in the fact that the reduction in size is not accompanied by a reduction in the

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ON/OFF ratios of the resistances of the Set and Reset states. The resistance of a contact with a single atom is constant and equal to 12.9 kΩ (ON state) independently of the area and the thickness of the component, whereas the resistance of the same device at the OFF state (broken atomic contact) tends to increase when the size of the component decreases. 6.3. Resistive valence change memories (VCM) 6.3.1. The first work on resistive memories In the early 1960s, Hickmott, Dearnaley, Simmons and Verderber discovered binary memory effects of thin metal oxide films “sandwiched” between two inert electrodes. Hickmott was therefore among the first to discover the electric properties of M/I/M(M’)-type resistive devices made up of an insulating film (I) between 15 and 100 nm thick, sandwiched between two inert metal electrodes M and M’ [HIC 62, HIC 64, HIC 65]6. As a result, in the case of an Al/Al2O3(30 nm)/Au diode and for a positive polarization of the gold electrode, Hickmott found that the resistance of the junction drops from 1010 Ω to approximately 100 Ω, equivalent to a variation in conductivity of more than 8 orders of magnitude. Having established this change in conductivity due to the “electroforming” of the insulator, he showed that the I/V curves present regions of negative differential resistance (NDR) that can lead to binary memory states. These NDR current–voltage curves have led to two different interpretations: one by Simmons and Verderber based on the existence of an impurity band in the insulator [SIM 67] and the other advanced by Dearnaley et al. who consider that it is due to the formation and the failure of conductive filaments inside the insulator [DEA 70].

6 A large variety of materials, such as Au, Al, Ta, Ti, Zr, Ag, Cu, Co, Sn, In, Bi, Pb, Al and Mg, have been used to produce M/I/M’ resistive devices with SiO2, Al2O3, Ta2O5, ZrO2, TiO2, etc., as insulators.

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The idea proposed by Simmons and Verderber, but contested by Dearnaley7, is that an insulator should be considered as a crystal with a large forbidden band into which Au+ ions (from a gold electrode) are injected by a strong electric field. A large impurity band (corresponding to a band of electron traps) is therefore formed inside the forbidden band, which makes it possible for electrons to tunnel along these traps. The authors modeled the experimental I/V curves from this energy diagram with good precision and gave a good interpretation of EF as well as the memory states8. Dearnaley suggests a different model in which conduction after EF of the component is due to the formation of conducting filaments that do not imply the presence of Au+ ions inside the insulator. These filaments result from the migration of O2− ions in the electric field as well as from a local chemical modification of the structure of the insulator. These filaments have variable diameters (of a few nanometers to a few dozen nanometers); they can be locally heated by the Joule effect and are broken when the melting point is reached. This failure leads to a drop in conductivity, which is at the origin of the NDR I/V curves [DEA 70]. Currently, this model is the most widely used model to account for the memory properties of M/I/M devices made up of chemically inert metal electrodes. Compared to the advancement in the 1960s, significant progress has now been made in the understanding of resistive switching (RS). Due to the important contribution of nearfield microscopy techniques (e.g. scanning tunnel microscopy (STM), atomic force microscopy (AFM) and conductive atomic force microscopy (CAFM)), the physicochemical mechanisms at the origin of these variations in conductivity have been analyzed at the atomic scale. To this, we must add the impressive improvements made in the

7 Dearnaley opposes the use of an energy band model and asserts that he has never observed traces of gold in the insulator after electroforming. 8 A similar model was used by Ielmini et al. to interpret variations in conductivity in the case of phase-change memories (PCM) (see Chapter 5).

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material deposition techniques into thin layers that have also contributed to obtaining high-quality deposits with a much better controlled degree of purity. 6.3.2. Resistive valence change memories after the 2000s As previously mentioned, this research topic sparked new interest in the 2000s, and a significant number of metal oxides were studied and revisited so as to produce RRAM-type resistive memories. This field has been considerably broadened and prospection for oxides has included a large variety of elements of the periodic table [HA 11]. Yang et al. [YAN 13] classified them into three main categories: 1) oxides are essentially mainly transition metals: TiOx, ZrOx, HfOx (column IV B); VOx, NbOx, TaOx (column V B); MnOx, FeOx, CoOx, NiOx, CuOx, ZnOx (columns VI B to 11 B); along with metals from columns II A (AlOx, GaOx), column IV A (SiOx, SiOxNy, GeOx, SnO2) and column V A (SbOx, BiOx); 2) rare earth metal oxides: Ce, Pr, Nd, Sm, Eu, Gd, Dy, Er; 3) perovskites: SrTiO3, Ba0.7Sr0.3TiO3, SrZrO3, BiFeO3, Pr0.7 Ca0.3 MnO3, La0.33 Sr0.67 FeO3, PryLa0.625−y Ca 0,375 MnO3. Three oxides in particular were studied between 2000 and 2005. Chromium-doped perovskite SrZrO3-Cr [BEC 00] (IBM, Zürich), nickel oxide [SEO 04] (Samsung) and titanium oxide [CHO 05] have all contributed to rekindling the interest of the field and giving it a new start. Since 2010, hafnium-based oxides9 have emerged as the ideal materials for resistive memories. Their characteristics in terms of

9 Hafnium oxide is an oxide with a high dielectric constant that was proposed as the insulator of choice for the gate insulators of MOSFET transistors at the beginning of the 2000s. It is perfectly compatible with CMOS technology, and this explains why recent developments in its use as a resistive memory material are largely due to this first application, that is perfectly integrated within the electronic component industry.

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switching speed and endurance to cycling far outdo those of Flash memories, and explain the significant investments in this particular domain, shown by the exponential increase in the number of publications over the last few years (see Figure 6.2). 6.3.3. A perovskite resistive memory (SrZrO3) with better performance than Flash memories At the end of the 1990s, Beck et al. [BEC 00] demonstrated that a resistive device with a chromium-doped perovskite ran as a binary resistive memory with very promising electrical properties, especially with far greater switching speed than Flash memories. The resistive memory designed by Beck et al. was made up of a SrZrO3 polycrystalline 300 nm thick film, 0.2% chromium-doped and sandwiched between a SrRuO3 or platinum bottom electrode and a gold top electrode, deposited on a thin layer of titanium10. The I/V curves are typical of a bipolar system for which the Set and Reset transitions occur at –0.5 and 0.5 V, respectively (Figure 6.11).

Figure 6.11. a) Linear I/V curves and b) semi-logarithmic I/V curves of a [SrRuO3/SrZrO3 (0.2% Cr)/Au] device. Area of the gold electrode: 4 × 104 µm2; SrZrO3 thickness: 300 nm; sweep rate: 0.2 V/min. Adapted from [BEC 00]

10 Titanium layer is used as an adhesion promoter.

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In its initial state, the device has a high impedance (OFF state) that remains constant as long as the potential is maintained above –0.5 V. When the polarization is made more negative, the current abruptly increases and reaches a value of –40 µA, corresponding to a state of high conductivity11. This state of low impedance (ON) is maintained during the backward sweep to 0.5 V. At this point, the device recovers its state of high impedance (OFF) and the current drops to a few µA. In the case of a partially crystallized perovskite, the resistances of the ON and OFF states are 100 kΩ and 100 MΩ, respectively. An impressive fact is that the two OFF and ON states are very stable in the ±0.5 V potential interval; they are also maintained in the absence of polarization and may be considered as non-volatile memory states. Moreover, these phenomena seem to occur without the need for prior EF of the insulator12. For small potentials, the variation of I is linear (I = aV), but is quadratic (I = aV + bV2) for high values. Such a variation indicates the presence of energy traps in the insulator near the bottom of the conduction band (shallow traps) and a conduction mechanism corresponding to space-charge limited current (SCLC) injection [BEC 00]. The authors noted that charge transport is thermally activated in the Set state, thus excluding the formation of metal filaments. This switching between the ON and OFF states was also demonstrated in a potential pulse regime with devices made up of 100 nm thick perovskite films (Figure 6.12(a)). Repetitive ON and OFF state cycles, carried out over very long periods of time (more than 10 months), do not show any noticeable degradation (decrease in read signal lower than 1%). 11 –40 µA is the current compliance corresponding to an imposed limiting value. 12 This behavior is very rare and is only encountered when the insulator is strongly doped or contains a very high concentration of electron traps. This is the case for amorphous semi-conductors of phase-change materials for which switching between the semi-conductive and conductive states is very rapid. This is characteristic of an electronic process and can be interpreted by an energy band model (see Chapter 5, Ielmini et al.).

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Figure 6.12. Switching characteristics between the ON and OFF states. a) Potential pulses of 2 ms width at 1.1 V (OFF), –1.1 V (ON) and –0.2 V (read). b) Currents in the ON (~60 µA) and OFF (a few µA) states. The current is read every second for 1 min. The contact area is 4 × 104 µm2. Adapted from [BEC 00]

If a switching potential of ±1.1 volt is chosen, the width of the pulse necessary for the ON and OFF transitions is 2 ms. It is smaller than 100 ns for switching potentials of ±5 V. The current pulse used to write the ON state is –200 µA and that used for the OFF state is about 130 µA, this being equivalent to current densities of 0.5 and 0.3 A/cm2, respectively, which are very small compared to PCRAM and STTRAM memories, for which values vary between 106 and 107 A/cm2. The reading of the ON and OFF states is achieved by applying small potential pulses (–0.2 volt) for 2 ms, a pulse width it should be possible to reduce without difficulty (Figure 6.12(b)). These particularly promising results (short switching times, small energy consumption, retention times of 10 months or more without noticeable degradation of the signals, and good resistance to prolonged cycling between ON and OFF states) have been an incentive for the renewal of research dedicated to metal oxides and their application to resistive memories. Among the important points to resolve, EF and switching phenomena are still debated, and the great diversity in the results obtained with different oxides is probably one of the reasons that is

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further delaying the industrial exploitation of these systems. Better knowledge of these systems is necessary, which explains the large number of papers dedicated to their study. 6.3.4. Electroforming and resistive switching Electroforming and switching processes are more complex than those in metallization memories. Electrochemical modifications are made to the insulator considered as an ionic metal oxide, with O2− ions and metal cations as the ionic species in the network. The analysis of I/V curves in the LRS (ON state) and HRS (OFF state) shows a great diversity of conduction mechanisms. The nature of the dielectric (width of the forbidden band, trap level), the height of the energy barrier at the metal/insulator interface and the method of preparing the oxide (with or without annealing) are all parameters that determine switching and conduction properties [WON 12]. Before being able to switch reversibly between the two ON and OFF states, the device must generally be submitted to a first transformation corresponding to an EF step. 6.3.4.1. Electroforming process Generally, the freshly prepared oxide is in a high state of impedance, and the forming (or EF) process, often interpreted as the beginning of a soft breakdown, transforms the dielectric and makes it conductive13. This EF is achieved by applying a strong electric field (about 107 V/cm)14. This electric field induces electrochemical reactions corresponding, on the one hand, to a migration of the O2− ions of the oxide toward the anode with possible oxidation to gaseous oxygen

13 A detailed description of resistive switching phenomena can be found in several recent reviews by Yang et al. [YAN 13], Wong et al. [WON 12], Kim et al. [KIM 11], Szot et al. [SZO 11], Waser et al. [WAS 09] and Sawa [SAW 08]. 14 An electric field of 107 V/cm is very high and corresponds, for example, to a voltage of 5 V applied to a 5 nm thick insulating layer sandwiched between two metal electrodes.

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and, on the other hand, to the reduction of the cations of the network. The effect of these transformations is to introduce, in the form of filaments, either positive oxygen vacancies VO2+ corresponding to the departure of oxygen atoms from their sites in the network, or metal atoms coming from the reduction of metal cations. These filaments are far more conductive than the initial material; their formation is stochastic and, depending on the oxide, their diameters vary between a few and dozens of nanometers15. This interpretation of the EF process, resulting in the formation of conductive filaments, which was initially proposed by Dearnaley, has been confirmed in the case of the TiO2 and NiO oxides and is now a widely accepted mechanism. By high-resolution transmission electron microscopy (HRTEM) on titanium oxide (TiO2), several Korean teams associated with Samsung have recently shown the existence of filaments that are far more conductive than the background oxide TiO2 [KWO 10]. These filaments, identified as Magnéli phases (TinO2n-1)16, are conical with a half-length diameter of 5–10 nm and are separated from each other by 0.5 to 5 µm. The authors showed that in the conductive state (ON state) the filaments are connected to the two electrodes and in the OFF state they are disconnected [KWO 10]. As indicated by the authors, the large spacing of filaments could a priori constitute a difficulty with a view to miniaturization, with contact areas much smaller than 100 × 100 nm2. In fact, the 15 It is a challenge to determine clearly what differentiates various resistive memories from each other. In the case of valence-change resistive memories, the conductive filaments are not metallic, even if metal atoms are produced by metal cation reduction during electroforming. 16 The Magnéli phases are titanium oxides, of formula TinO2n -1, with n most often equal to 4 or 5. At room temperature, most Magnéli phases have a metal-type conduction [ING 83]. Titanium oxides can also exist as non-stoichiometric TiO2-x structures. At 1,000 K, the x value is less than 1%; this implies that after annealing at around 700°C, the non-stoichiometric form of titanium oxide is preserved. It is transformed into the Magnéli phase as soon as x goes beyond the stability range of the non-stoichiometric oxide [KIM 11].

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simultaneous presence of several filaments in the same cell is improbable due to the fact that, as soon as a filament comes into contact with two electrodes, all the current goes through this filament and thus prevents the transformation of any other part of the insulator. Under these conditions, whatever the size of the cell, a conductive filament will always be formed. This can be an advantage in terms of reproducibility. The transformation of TiO2 into TinO2n-1 results from an electrochemical oxidation–reduction process in which O2− is oxidized, while Ti4+ is reduced to maintain electroneutrality inside the filament, according to the following two reactions (Figure 6.13): O2- → VO2+ + O (or ½ O2) + 2eTi4+ + me- → Ti (4-m)+

Figure 6.13. Formation mechanism for conducting filament. a) Electroforming step: the O2– ions leave their sites of occupation by creating VO2+ holes and migrate toward the anode in the electric field. b) Device in the Set state. The conductive filament is formed by the multiple VO2+ vacancies, the O2– ions are oxidized at the anode TE and are transformed into oxygen atoms that are inserted into the metal of the anode. Adapted from [WON 12]

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The choice of electrodes is also important for the observation of EF and resistive switching (RS). The anode must not completely block the O2– ions, as their accumulation and the oxidation at the M/I interface would lead to the deformation and destruction of the electrode. Moreover, the electrode metal must not react with oxygen because the formation of a thin oxide layer at the metal/TiO2 interface could prevent the formation of filaments, and the RS process would not occur. The energy barrier of the metal/oxide Schottky junction must also be optimized. An energy barrier which is too high will strongly reduce the current and prevent the EF; in contrast, too low a barrier makes the contact ohmic and prevents the electric field becoming strong enough for EF. This is the reason why, in the case of TiO2 (n-type oxide), titanium and aluminum electrodes, which have small work functions Ф for electrons (4.3 and 4.1 eV, respectively) are not well adapted to EF and RS, as opposed to platinum, for which Ф is 5.12 eV [KIM 11]. In the case of NiO and Cu2O (p-type oxides), the choice of electrodes raises the same problems. This time, metals with small work functions (Ti, Al) form Schottky junctions with high energy barriers. Again, these metals are not well adapted for the production of filaments, as opposed to materials with metallic characteristics such as SrRuO3, TaN, TiN and Pt [KIM 11]. 6.3.4.2. Resistive switching mechanisms Once the transformation of the oxide is established, the RS phenomenon remains the key point of these systems. Yang et al. [YAN 08] attribute switching in TiO2 to the presence or absence of a rectifying junction between the metal electrode and the oxide. Switching between the states of high and low impedance is interpreted as being due to the formation at the M/TiO2 interface, of a Schottky barrier (Pt/TiO2, for example), or an ohmic contact (Pt/TiO2-X). According to the authors, these transformations occur over the entire surface of the electrode [YAN 09].

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However, the currently prevailing interpretation for most oxides is that of a filament, whose failure and reformation correspond to Reset and Set transitions, in agreement with Figure 6.14. Many experimental facts, particularly the direct observation of variations in conductivity by near-field microscopy, have confirmed the filament theory, and have invalidated the theory of homogenous transformation over the entire electrode surface. Nevertheless, debate continues concerning the nature of the chemical phenomena at the origin of these transformation and conduction mechanisms, which depend on the nature of the oxide and the way it is prepared. Generally, it is agreed that the forming and restoration of the failed filaments corresponding to the Set operation, result from the migration toward the anode of the O2− ions, dislodged from their sites of occupation in the network, themselves transformed into charged oxygen vacancies (VO2+). The oxidation of O2− into O (atomic) + 2 e- at the anode is followed by the insertion of oxygen atoms into the metal of the electrode that, according to Wong et al., behaves as an oxygen reservoir [WON 12]. When the electrode is an oxidizable metal, a thin oxide layer can be formed at the interface, a situation which can oppose switching operations. In fine, the filaments are made up of an assembly of vacancies that provide paths for electric conduction inside the insulator (Figure 6.14). The return from the Set state toward the high impedance (HRS) Reset state is carried out with a change in polarity that causes the migration of the O2− ions toward the bottom electrode (positive), and in a direction opposed to that observed for the transformation leading to the Set state. During this transformation, the O2− ions neutralize the vacancies VO2+; oxygen atoms are formed and can reoxidize the metal atoms originating from a previous reduction. These redox phenomena lead to the restoration of a part of the filament in a non-conductive state (Figure 6.14).

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Figure 6.14. Mechanism of switching between Set and Reset states. a) The device is in its initial Set state, corresponding to low resistance (LRS); when V < 0, the O2– ions migrate toward the inside of the oxide and progressively neutralize the VO2+ vacancies by releasing oxygen atoms and destroying the conductivity paths. b) Obtaining the high resistance state (HRS or Reset) of the component. The conduction paths are broken by the recombination of the O2– ions with the VO2+ vacancies. Adapted from [WON 12]

The Set and Reset operations in the case of oxides generally correspond to bipolar switching. They can present, however, the characteristics of a unipolar system. This implies either thermal dissolution of the metal filaments or diffusion of the O2− ions in the absence of an interfacial barrier. Unipolar RS has been observed with crystalline NiOx films sandwiched between two platinum electrodes, and has been attributed to the formation of nickel metal filaments [PAR 07]. Many oxide systems have been tested in the hope of obtaining resistive memory effects. Among these, hafnium oxide-based resistive components show great promise. Revealed for the first time by Lee et al. in 2008 [LEE 08], their remarkable switching and endurance properties made them stand out from the other known systems. This has led to the recent implication of numerous teams and to the rapid

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increase in the number of publications over the last few years (Figure 6.3). Another reason behind this interest is that hafnium oxide is a well-mastered material at the industrial level, and is perfectly compatible with CMOS technology. Over the last decade or so, it has already been used as a gate insulator in the production of highperformance Flash-type charge storage memories. Its application to resistive memories is currently considered as the most realistic solution to reaching the performances of a universal memory and replacing Flash memories. 6.3.5. Hafnium oxide for universal resistive memories? For the past few years, many teams across the world have been developing important research on the use of HfO2 in resistive memories. Lee et al. [LEE 08] were the first to use titanium-based electrodes and to demonstrate that is was possible to produce HfO2 memories with very high switching speeds and low energy consumption. Their bipolar-type component consists of alternating HfO2/Ti layers placed between two TiN electrodes to form a [TiN/HfO2 (20 nm)/Ti (10 nm)/TiN] device. The high switching speeds correspond to write times smaller than 10 ns. The ratio of OFF/ON resistances is greater than 100, the endurance to ON ↔ OFF cycling is very good (>106 cycles) and the retention times at 200 °C are about 10 h. Energy consumption is also very small: the current and voltage peaks necessary for carrying out ON ↔ OFF transitions are only 25 µA and 1.5 volt for a 0.1 µm2 component, which represents an energy per bit of approximately 0.4 pJ. The use of titanium nitride electrodes marks a real progress compared to platinum electrodes. Cabout et al. of LETI-CEA (Laboratoire d’électronique et de technologie de l’informationCommissariat à l’énergie atomique et aux technologies alternatives) have recently shown that the replacement of Pt electrodes by TiN electrodes significantly improves the switching properties of the memory [CAB 13].

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They showed in particular that the original unipolar mechanism becomes bipolar. A clear improvement in performances is observed, especially with a significant decrease in the forming and Set/Reset switching voltages, the last two of which depend very little on switching speeds, as opposed to platinum electrode components (Figure 6.15).

Figure 6.15. Variations in switching voltages of “Pt-Pt”(Pt (25 nm)/HfO2 (10 nm)/Pt (25 nm)] and “TiN-Ti”[Ti (10 nm)/HfO2 (10 nm)/TiN (25 nm)) devices versus a triangular ramp voltage speed. The devices are 1 µm in diameter. A very small variation of switching voltages is observed in the case of the “TiN-Ti” device. Adapted from [CAB 13]

The reproducibility of different functions (forming, Set and Reset) is improved, as well as the data retention time. The latter is estimated at 10 years at 65°C in contrast to only 50°C with platinum electrodes. The lower switching voltages are related to the spontaneous formation of a TiOx/HfOx interface in the Ti/HfO2 bilayer that most probably behaves as an oxygen vacancy reservoir. Several years after the publication of the works by Lee et al., Govoreanu et al. [GOV 11] from the Interuniversity Microelectronics

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Centre (IMEC) in Belgium showed that it was possible to obtain exceptional RS performances with a TiN/Hf/HfO2/TiN component of extremely small dimensions, below 100 nm2 and where a thin layer of hafnium metal is deposited onto the HfO2 (Figure 6.16(a)). As in the previous example (titanium layer deposited on HfO2), the thin hafnium layer in contact with HfO2 is partially transformed into a non-stoichiometric oxide HfOx at the interface. This facilitates the formation of filaments with the migration of O2– ions and VO2+ vacancies. Diffusion of oxygen in the hafnium layer is shown by ionic etching and XPS analysis of the HfO2/Hf bilayer (Figure 6.16(b)). A very comprehensive study of the device operation was conducted by the IMEC teams. This study revealed that the forming voltage VF decreases when the thickness of the oxide layer is reduced. From 5 V in the case of a 10 nm thick amorphous oxide layer, it drops close to 0 V for a thickness of 2 nm. This confirms that the electric field is important for the forming process, and it validates the previously described migration mechanisms.

Figure 6.16. [TiN/HfOx/Hf/TiN] resistive component. a) TEM image of the device showing the Hf deposit (