New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters [1st ed. 2020] 978-981-32-9933-7, 978-981-32-9934-4

Table of contents :
Front Matter ....Pages i-xxv
Introduction (Zhiqiang Guo, Deshang Sha)....Pages 1-21
Hybrid Phase-Shift-Controlled Three-Level and LLC DC–DC Converter with Active Connection at the Secondary Side (Zhiqiang Guo, Deshang Sha)....Pages 23-45
Hybrid Three-Level and Half-Bridge DC–DC Converter with Reduced Circulating Loss and Output Filter Inductance (Zhiqiang Guo, Deshang Sha)....Pages 47-70
Improved ZVS Three-Level DC–DC Converter with Reduced Circulating Loss (Zhiqiang Guo, Deshang Sha)....Pages 71-90
Analysis and Evaluation of Dual Half-Bridge Cascaded Three-Level DC–DC Converter for Reducing Circulating Current Loss (Zhiqiang Guo, Deshang Sha)....Pages 91-113
Output-Series-Connected Dual Active Bridge Converters for Zero-Voltage Switching Throughout Full Load Range by Employing Auxiliary LC Networks (Zhiqiang Guo, Deshang Sha)....Pages 115-145
Dual Active Bridge Converter with Parallel-Connected Full Bridges in Low-Voltage Side for ZVS by Using Auxiliary Coupling Inductor (Zhiqiang Guo, Deshang Sha)....Pages 147-168
An Isolated Micro-converter Utilizing Fixed-Frequency BCM Control Method for PV Applications (Zhiqiang Guo, Deshang Sha)....Pages 169-191
Modulation Scheme of Dual Active Bridge Converter for Seamless Transitions in Multi-working Modes Compromising ZVS and Conduction Loss (Zhiqiang Guo, Deshang Sha)....Pages 193-213
An Improved Modulation Scheme of Current-fed Bidirectional DC–DC Converters for Loss Reduction (Zhiqiang Guo, Deshang Sha)....Pages 215-243

Citation preview

CPSS Power Electronics Series

Zhiqiang Guo Deshang Sha

New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters

CPSS Power Electronics Series Series Editors Wei Chen, Fuzhou University, Fuzhou, Fujian, China Yongzheng Chen, Liaoning University of Technology, Jinzhou, Liaoning, China Xiangning He, Zhejiang University, Hangzhou, Zhejiang, China Yongdong Li, Tsinghua University, Beijing, China Jingjun Liu, Xi’an Jiaotong University, Xi’an, Shaanxi, China An Luo, Hunan University, Changsha, Hunan, China Xikui Ma, Xi’an Jiaotong University, Xi’an, Shaanxi, China Xinbo Ruan, Nanjing University of Aeronautics and Astronautics, Nanjing Shi, Jiangsu, China Kuang Shen, Zhejiang University, Hangzhou, Zhejiang, China Dianguo Xu, Harbin Institute of Technology, Haerbin Shi, Heilongjiang, China Jianping Xu, Xinan Jiaotong University, Chengdu, Sichuan, China Mark Dehong Xu, Zhejiang University, Hangzhou, Zhejiang, China Xiaoming Zha, Wuhan University, Wuhan, Hubei, China Bo Zhang, South China University of Technology, Guangzhou Shi, Guangdong, China Lei Zhang, China Power Supply Society, Tianjin, China Xin Zhang, Hefei University of Technology, Heifei Shi, Anhui, China Zhengming Zhao, Tsinghua University, Haidian Qu, Beijing, China Qionglin Zheng, Beijing Jiaotong University, Haidian, Beijing, China Luowei Zhou, Chongqing University, Chongqing, Sichuan, China

This series comprises advanced textbooks, research monographs, professional books, and reference works covering different aspects of power electronics, such as Variable Frequency Power Supply, DC Power Supply, Magnetic Technology, New Energy Power Conversion, Electromagnetic Compatibility as well as Wireless Power Transfer Technology and Equipment. The series features leading Chinese scholars and researchers and publishes authored books as well as edited compilations. It aims to provide critical reviews of important subjects in the field, publish new discoveries and significant progress that has been made in development of applications and the advancement of principles, theories and designs, and report cutting-edge research and relevant technologies. The CPSS Power Electronics series has an editorial board with members from the China Power Supply Society and a consulting editor from Springer. Readership: Research scientists in universities, research institutions and the industry, graduate students, and senior undergraduates.

More information about this series at http://www.springer.com/series/15422

Zhiqiang Guo Deshang Sha •

New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters

123

Zhiqiang Guo Beijing Institute of Technology Beijing, China

Deshang Sha Advanced Power Conversion Center, School of Automation Beijing Institute of Technology Beijing, China

ISSN 2520-8853 ISSN 2520-8861 (electronic) CPSS Power Electronics Series ISBN 978-981-32-9933-7 ISBN 978-981-32-9934-4 (eBook) https://doi.org/10.1007/978-981-32-9934-4 © Springer Nature Singapore Pte Ltd. 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Preface

Isolated DC–DC converters are widely used as power supplies for many applications, such as telecommunications, data centers, battery chargers, industrials, and aerospace applications. Using galvanic isolation is not only for voltage conversion, but also for the safety consideration. The modern power supplies require high efficiency and high power density in wide input or output voltage range. High switching frequency can reduce the volume of the magnetic components, but it leads to high switching loss. Soft switching, especially for zero-voltage switching for MOSFETs, becomes the universal requirement of loss reduction and good EMC. This book aims to present the techniques of topologies and modulation schemes for soft-switching isolated DC–DC converters to improve the efficiency. Detailed theoretical analyses with design examples and experimental verifications are included for different fields of applications. This book contains ten chapters. Chapter 1 gives a brief review of the topologies and modulation schemes for the isolated DC–DC converters, including ZVS performance and conduction loss for the wide voltage and the load range. Then the optimization objectives for isolated DC–DC converters are introduced. Chapter 2 introduces a hybrid phase-shift-controlled three-level and LLC DC–DC converter to achieve full-load ZVS performance. Chapter 3 presents a three-level DC–DC converter with a blocking capacitor to reset the primary winding circulating current. By using four-diode rectifier stage, the circulating current at the primary side stays zero during the freewheeling period. The reduction of the circulating current can improve the efficiency. Chapter 4 presents an improved three-level DC–DC converter with two transformers connected in series on the primary side of the transformer to achieve wide ZVS and low conduction loss. The current ripple of the filter inductor current is also reduced.

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Chapter 5 is focused on a dual half-bridge cascaded three-level DC–DC converter, in which the circulating current is reduced without loss of ZVS performance. The current ripple of the filter inductor is also reduced. The converter can achieve good efficiency and power density performance. Chapters 6 and 7 show the modular isolated DC–DC converters for bidirectional applications. Chapter 6 is focused on output series-connected dual active bridge (DAB) converters for high output voltage applications, and Chap. 7 is focused on parallel-connected DAB converters for low battery voltage applications. In these two chapters, ZVS in full-operation range is achieved by using auxiliary networks. In order to guarantee the currents in auxiliary networks just enough for ZVS, modulation trajectories are studied based on the boundary of the ZVS condition. The conduction loss in the auxiliary components and ZVS performance are compromised. Chapter 8 introduces a micro-converter utilizing fixed-frequency boundarycurrent-mode control method for PV applications. The leakage inductance current can work in boundary current mode with fixed switching frequency, which improves the reliability and power density. Chapter 9 presents a modulation scheme for the voltage-fed DAB converter. The potential working modes for ZVS are analyzed. Based on the ZVS working modes, the root-mean-square current is set as the optimized objective. The modulation scheme builds the relationship of the optimized working modes for the seamless transition, which leads to efficiency improvement and stable operation during the whole load range. Chapter 10 introduces a modulation scheme of current-fed bidirectional DC–DC converters for loss reduction. The potential working modes of the current-fed DC–DC converters are analyzed. The optimized modulation scheme for different battery voltages and different loads are developed to achieve full-operation ZVS and low conduction loss. This book is essential and valuable reference for the graduate students, academics majoring in power electronics, and engineers been engaged in developing DC–DC converters. The authors wish to express their sincere thanks to Prof. Kai Sun, Tsinghua University, for his comments and guides on research and other contributions to this book. Finally, the authors are extremely grateful to Springer and the editorial staff for the opportunity to publish this book and help in all possible manners. Beijing, China

Zhiqiang Guo Deshang Sha

Contents

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Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Application of Isolated DC–DC Converters . . . . . . 1.1.1 Server Power Supply . . . . . . . . . . . . . . . . 1.1.2 Electrical Vehicle . . . . . . . . . . . . . . . . . . . 1.1.3 Solid-State Transformer . . . . . . . . . . . . . . 1.2 Typical Topologies of Isolated DC–DC Converter . 1.2.1 Phase-Shift Controlled DC–DC Converter . 1.2.2 Isolated Resonant DC–DC Converter . . . . . 1.2.3 Voltage-Fed Bidirectional Isolated DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.4 Current-Fed Bidirectional Isolated DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Trend of the DC–DC Converter . . . . . . . . . . . . . . . 1.4 Organization of the Book . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Hybrid Phase-Shift-Controlled Three-Level and LLC DC–DC Converter with Active Connection at the Secondary Side . . . . . 2.1 Hybrid Three-Level and LLC DC–DC Converter . . . . . . . . 2.2 Analysis of the HTL–LLC Converter . . . . . . . . . . . . . . . . . 2.2.1 DC Conversion Ratio . . . . . . . . . . . . . . . . . . . . . . 2.2.2 Power Losses of the Active Switch . . . . . . . . . . . . 2.2.3 ZVS Condition of Switches . . . . . . . . . . . . . . . . . 2.2.4 Filter Inductor and Current Ripple . . . . . . . . . . . . . 2.2.5 Current Stress of the Primary Semiconductors . . . . 2.2.6 Voltage Stress of the Secondary Diodes . . . . . . . . . 2.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.1 Turns Ratio of the Two Transformers . . . . . . . . . . 2.3.2 Magnetizing Inductance of the LLC Transformer . . 2.3.3 Current Stress Comparison of the Primary Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . .

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2.3.4 Resonant Capacitance Cr . . . . . . . . . . . . . . . . . . . . . . . 2.3.5 Resonant Inductance Lr . . . . . . . . . . . . . . . . . . . . . . . . 2.3.6 Selection of the Secondary Semiconductors . . . . . . . 2.4 Experimental Verifications . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

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Hybrid Three-Level and Half-Bridge DC–DC Converter with Reduced Circulating Loss and Output Filter Inductance . . 3.1 Hybrid Three-Level Plus Half-Bridge DC–DC Converter . . . 3.2 Analysis of the HTL-HB Converter . . . . . . . . . . . . . . . . . . . 3.2.1 DC Conversion Ratio . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Voltage of the Blocking Capacitor . . . . . . . . . . . . . . 3.2.3 ZVS Condition of Switches . . . . . . . . . . . . . . . . . . 3.2.4 Current Stress of the Primary Semiconductors . . . . . 3.2.5 Voltage Stress of the Secondary Diodes and Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Turns Ratio of the Two Transformers . . . . . . . . . . . 3.3.2 Filter Inductor and Current Ripple . . . . . . . . . . . . . . 3.3.3 Magnetizing Inductance of the HB Transformer . . . . 3.3.4 Current Stress Comparison of the Primary Semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.5 Blocking Capacitor Cb . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.6 Selection of the Secondary Semiconductors . . . . . . . 3.4 Experimental Verifications . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Improved ZVS Three-Level DC–DC Converter with Reduced Circulating Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Improved Two-Transformer Three-Level DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Analysis of the Converter . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 DC Conversion Ratio . . . . . . . . . . . . . . . . . . . . . 4.2.2 ZVS Condition of Switches . . . . . . . . . . . . . . . . 4.2.3 Current Stress of the Primary Semiconductors . . . 4.2.4 Voltage Stress of the Rectifier Diodes . . . . . . . . . 4.3 Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Turns Ratio of the Two Transformers . . . . . . . . . 4.3.2 Filter Inductor and Current Ripple . . . . . . . . . . . . 4.3.3 Magnetizing Inductance of Tr2 . . . . . . . . . . . . . . 4.3.4 Current Stress Comparison of the Primary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4.3.5 Selection of the Rectifier Diodes . 4.3.6 Output Filter Capacitance . . . . . . 4.4 Experimental Verifications . . . . . . . . . . . . 4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

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Analysis and Evaluation of Dual Half-Bridge Cascaded Three-Level DC–DC Converter for Reducing Circulating Current Loss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Improved Dual Half-Bridge Cascaded Three-Level DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Analysis and Design Consideration of the Converter . . . . . . 5.2.1 ZVS Condition of Switches . . . . . . . . . . . . . . . . . 5.2.2 Comparison of the Gain of the Converter . . . . . . . 5.2.3 Comparison of the Filter Inductance . . . . . . . . . . . 5.2.4 Comparisons of Rms Current in the Primary Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.5 Ringing of the Rectifier Diodes . . . . . . . . . . . . . . . 5.3 Experimental Verifications . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Output-Series-Connected Dual Active Bridge Converters for Zero-Voltage Switching Throughout Full Load Range by Employing Auxiliary LC Networks . . . . . . . . . . . . . . . 6.1 Working Modes of the Presented DAB Converter . . . . 6.2 Key Feature and Modulation Scheme of the Converter 6.2.1 ZVS Analyses for Q1–Q4 . . . . . . . . . . . . . . . 6.2.2 ZVS Analyses for Q5–Q12 . . . . . . . . . . . . . . 6.2.3 Modulation Trajectory . . . . . . . . . . . . . . . . . 6.2.4 Design of the Auxiliary Inductor Ls . . . . . . . . 6.2.5 Switch Conduction Loss Comparison . . . . . . 6.3 Experimental Verifications . . . . . . . . . . . . . . . . . . . . . 6.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Dual Active Bridge Converter with Parallel-Connected Full Bridges in Low-Voltage Side for ZVS by Using Auxiliary Coupling Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Parallel-Connected DAB in Low-Voltage Side . . . . . . . . . . 7.2 Key Features and Modulation of the Converter . . . . . . . . . . 7.2.1 ZVS Analyses for Q9–Q12 . . . . . . . . . . . . . . . . . . 7.2.2 ZVS Analyses for Q1–Q8 . . . . . . . . . . . . . . . . . . . 7.2.3 Design of the Auxiliary Inductance Ls . . . . . . . . . .

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7.2.4 Control Loop of the Modulation Trajectory 7.2.5 Conduction Loss Analyses . . . . . . . . . . . . 7.3 Experimental Validation . . . . . . . . . . . . . . . . . . . . 7.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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An Isolated Micro-converter Utilizing Fixed-Frequency BCM Control Method for PV Applications . . . . . . . . . . 8.1 BCM Operation Analysis . . . . . . . . . . . . . . . . . . . 8.1.1 Topology Description . . . . . . . . . . . . . . . . 8.1.2 BCM Modes Analysis . . . . . . . . . . . . . . . 8.1.3 BCM Operation Condition . . . . . . . . . . . . 8.1.4 ZVS Condition Analysis . . . . . . . . . . . . . . 8.1.5 Light Load Optimization . . . . . . . . . . . . . . 8.2 Loss Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3 Control and MPPT Implementation . . . . . . . . . . . . 8.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . 8.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Modulation Scheme of Dual Active Bridge Converter for Seamless Transitions in Multi-working Modes Compromising ZVS and Conduction Loss . . . . . . . . . . . 9.1 Analyses of the Working Modes for DAB Converter 9.2 Modulation Scheme for Seamless Transition and Performance Analyses . . . . . . . . . . . . . . . . . . . . 9.2.1 Modulation Scheme When M < 1 . . . . . . . . 9.2.2 Modulation Scheme When M > 1 . . . . . . . . 9.2.3 Unified Modulation Scheme . . . . . . . . . . . . 9.2.4 Switch Conduction Loss Comparison . . . . . 9.2.5 Peak Current Comparison . . . . . . . . . . . . . . 9.3 Experimental Validation . . . . . . . . . . . . . . . . . . . . . 9.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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10 An Improved Modulation Scheme of Current-fed Bidirectional DC–DC Converters for Loss Reduction . . . . . . . . . . . . . . . . . . 10.1 Operation Modes of the Current-fed Bidirectional DC–DC Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1.1 Review of the Modulations for the Current-fed Bidirectional DC–DC Converter . . . . . . . . . . . . . . 10.1.2 Analyses of the Key Operation Modes . . . . . . . . . 10.1.3 ZVS Conditions for the Modified Operation Mode .

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10.2 Modulation and Control Scheme for the Modified Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 Modified PWM Plus Phase-Shift (MPPS) Modulation Scheme and Control Diagram . . . . . . . . . . . . . . . . . 10.2.2 Switch Conduction Loss Comparison . . . . . . . . . . . 10.2.3 Comparison of the Core Loss in the Series Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 Experimental Verifications . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Fig. Fig. Fig. Fig. Fig.

1.1 1.2 1.3 1.4 1.5

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Fig. 1.11 Fig. 1.12 Fig. 1.13 Fig. 1.14 Fig. Fig. Fig. Fig. Fig. Fig.

1.15 1.16 1.17 2.1 2.2 2.3

Fig. 2.4 Fig. 2.5 Fig. 2.6

Typical structure of the server power supply . . . . . . . . . . . . On/off board charging system and power level for EVs [5] . Circuit diagram of DC solid-state transformer . . . . . . . . . . . Phase-shift full-bridge DC–DC converter . . . . . . . . . . . . . . . Phase-shift full-bridge DC–DC converter with the series inductor in the primary side of the transformer . . . . . . . . . . . Typical isolated PSTL DC–DC converter . . . . . . . . . . . . . . . Key waveforms of the PSTL DC–DC converter . . . . . . . . . . ZVZCS isolated TL DC–DC converter . . . . . . . . . . . . . . . . . Key waveforms of the ZVZCS TL DC–DC converter . . . . . Circuit of the resonant DC–DC converter and several common resonant tanks . . . . . . . . . . . . . . . . . . . . . . . . . . . . DAB converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms of the typical modulation schemes: a SPS, b EPS, and c DPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Series resonant DAB converter . . . . . . . . . . . . . . . . . . . . . . . Hybrid three-level and two-level series resonant DAB converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Buck/boost converter cascaded with a DAB converter . . . . . Current-fed bidirectional DC–DC converter . . . . . . . . . . . . . Half-bridge current-fed bidirectional DC–DC converter . . . . Hybrid TL and LLC converter . . . . . . . . . . . . . . . . . . . . . . . Key waveforms of the HTL–LLC converter . . . . . . . . . . . . . Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC conversion ratio versus duty cycle . . . . . . . . . . . . . . . . . DC conversion ratio versus the load resistance . . . . . . . . . . . Load distribution between the two transformers and the duty cycle with different input voltages . . . . . . . . . . . . . . . . . . . .

. . . .

. . . .

2 3 4 5

. . . . .

. . . . .

5 6 6 7 7

.. ..

8 9

.. ..

10 12

. . . . . .

. . . . . .

13 13 13 14 24 25

.. .. ..

26 30 30

..

31

xiii

xiv

Fig. 2.7 Fig. 2.8 Fig. 2.9

Fig. 2.10 Fig. 2.11 Fig. 2.12 Fig. 2.13 Fig. 2.14

Fig. 2.15

Fig. 2.16

Fig. 2.17 Fig. 2.18

Fig. 3.1 Fig. 3.2 Fig. 3.3

Fig. 3.4 Fig. 3.5 Fig. 3.6

Fig. 3.7 Fig. 3.8

List of Figures

Idealized rectifier voltage vrec a conventional TL converter b HTL–LLC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter inductance as the function of input voltage for the desired current ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary winding current of the transformers and the currents of the primary semiconductors a conventional TL converter, b HTL–LLC converter, c currents of the primary semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit of the secondary side in Stage 4. . . . . . . . . . Magnetizing inductance of Tr2 versus the leakage inductance of Tr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the switches in per unit as the function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the switches in per unit as the function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured key waveform of the HTL–LLC converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 200 W . . . . . Current of Q4, primary current of the clamping diode D1, and gate signal and drain-source voltage of switch Q4, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current of Q4, current of Tr2, and gate signal and drain-source voltage of switch Q3 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of QR at Vin = 550 V and P = 1000 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency for the HTL–LLC converter, the conventional TL converter, and the HTL–LLC converter replacing the active switch to a diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HTL-HB DC–DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms of the HTL-HB converter . . . . . . . . . . . . . . . . Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC conversion ratio versus duty cycle . . . . . . . . . . . . . . . . . . . Equivalent circuit in Stage 2 at light loads . . . . . . . . . . . . . . . . Primary winding current of the transformers and the currents of the primary semiconductors a conventional TL converter, b HTL-HB converter, c currents of the primary semiconductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Equivalent circuit of the secondary side in Stage 5. . . . . . . . . . Idealized rectifier voltage vrec a conventional TL converter b HTL-HB converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32 33

34 36 38 39 40

42

43

43 44

44 48 49

50 54 55

57 59 61

List of Figures

Fig. 3.9 Fig. 3.10 Fig. 3.11 Fig. 3.12 Fig. 3.13

Fig. 3.14

Fig. 3.15

Fig. 3.16 Fig. 3.17 Fig. 4.1 Fig. 4.2 Fig. 4.3 Fig. 4.4

Fig. 4.5 Fig. 4.6

Fig. 4.7 Fig. 4.8 Fig. 4.9 Fig. 4.10 Fig. 4.11

xv

Filter inductance as the function of input voltage for the desired current ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Magnetizing inductance of Tr2 versus the leakage inductance of Tr1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the switches in per unit as the function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the primary clamping diodes in per unit as the function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . Measured key waveform of the HTL-HB converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 200 W . . . Current of Q4, primary current of the clamping diode D1, and gate signal and drain-source voltage of switch Q4, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current of Q4, current of Tr2, and gate signal and drain-source voltage of switch Q3 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . . Efficiency for the HTL-HB converter, the conventional TL converter, and the converter in [2] . . . . . . . . . . . . . . . . . . . . Calculated power loss distribution at rated load when Vin = 550 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conventional two-transformer TL DC–DC converter . . . . . . Improved two-transformer three-level (ITT–TL) DC–DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms of the ITT–TL converter . . . . . . . . . . . . . . . Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hybrid PWM and phase-shift modulation scheme . . . . . . . . Primary winding current of the transformers and the currents of the primary semiconductors a conventional TL converter, b ITT–TL converter, c currents of the primary semiconductors in ITT–TL converter . . . . . . . . . . . . . . . . . . Equivalent circuit of the secondary side in Stage 4. . . . . . . . Idealized rectifier voltage vrec a conventional TL converter b ITT–TL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter inductance as the function of input voltage for the desired current ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the switches in per unit as the function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the primary clamping diodes in per unit as the function of the input voltage . . . . . . . . . . . . . . . . . . . . . . . . .

..

62

..

62

..

63

..

64

..

65

..

66

..

67

..

69

.. ..

69 72

.. ..

73 73

.. ..

74 78

.. ..

79 81

..

82

..

83

..

84

..

84

xvi

Fig. 4.12 Fig. 4.13

Fig. 4.14

Fig. 4.15

Fig. 4.16 Fig. 4.17 Fig. 5.1 Fig. 5.2 Fig. 5.3 Fig. 5.4

Fig. 5.5 Fig. 5.6 Fig. 5.7 Fig. 5.8 Fig. 5.9

Fig. 5.10 Fig. 5.11 Fig. 5.12

Fig. 5.13 Fig. 5.14 Fig. 5.15

Fig. 5.16

List of Figures

a RCD snubber circuit; b Prototype of a 1 kW ITT-TL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measured key waveform of the ITT–TL converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . Current of Q4, current in Tr1, and gate signal and drain-source voltage of switch Q4, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . . . . Current of Q2, current in Tr2, and gate signal and drain-source voltage of switch Q2 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W . . . . . . . . . . . . . . . . . . . . . . . Efficiency for the ITT–TL converter and the conventional TL converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calculated power loss distribution at rated load when Vin = 550 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dual half-bridge cascaded TL (DHBC-TL) DC–DC converter: a main circuit, b key waveforms . . . . . . . . . . . . . . . Derivation of IDHBC-TL DC–DC converter . . . . . . . . . . . . . . Key waveforms of the IDHBC-TL converter . . . . . . . . . . . . . . Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Leakage inductor for ZVS versus load percentage . . . . . . . . . . Voltage across the output filter inductor: a IDHBC-TL converter, b DHBC-TL converter, c ITT-TL converter . . . . . . . DC conversion ratio versus duty cycle . . . . . . . . . . . . . . . . . . . Filter inductance as the function of input voltage for the desired current ripple . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Currents in the primary winding of the transformers and the switches: a primary winding currents, b currents in the switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms current of the switches versus the input voltage . . . . . . . . Total conduction loss of the primary switches . . . . . . . . . . . . . a Equivalent circuit of the secondary side in the IDHBC-TL converter for Stage 4, b equivalent circuit of the corresponding stage in ITT-TL converter, c equivalent circuit of the corresponding stage in DHBC-TL converter . . . . . . . . . . Voltage stress of rectifier diodes versus input voltage. . . . . . . . Prototype of a 1 kW IDHBC-TL converter . . . . . . . . . . . . . . . . Measured key waveform of the IDHBC-TL converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 250 W . . . . . . . . . . . . . . . . . . . . Output voltage of the rectifier stage . . . . . . . . . . . . . . . . . . . . .

85

86

87

87 89 89 92 93 94

95 98 99 100 101

102 103 104

105 106 107

108 109

List of Figures

Fig. 5.17

Fig. 5.18

Fig. 5.19 Fig. 5.20 Fig. 5.21 Fig. 6.1 Fig. 6.2 Fig. 6.3 Fig. 6.4 Fig. 6.5 Fig. 6.6 Fig. 6.7 Fig. 6.8 Fig. 6.9

Fig. Fig. Fig. Fig.

6.10 6.11 6.12 6.13

Fig. 6.14

Fig. 6.15 Fig. 6.16 Fig. 6.17

xvii

Current of Q2, and gate signal and drain-source voltage of switch Q2, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 250 W. . . . . . . . . . . . . . . . . . . . . . . . . Current of Q1, and gate signal and drain-source voltage of switch Q1 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 250 W. . . . . . . . . . . . . . . . . . . . . . . . . Transient response to a step load change for 50% load to 100% load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency curves for different TL converters . . . . . . . . . . . . Calculated power loss distribution at rated load when Vin = 550 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input-parallel output-series dual active bridge converter . . . . Output-series dual active bridge (OSDAB) converter . . . . . . Output-series dual active bridge converter with dual auxiliary LC network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Working modes in forward power flow: a Mode 1a, b Mode 2a, c Mode 3, and d Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . Topological stages with half-switching period in Mode 1a: a [t0, t1], b [t1, t2], c [t2, t3], and d [t3, t4] . . . . . . . . . . . . . . Key waveforms of Mode 2a with specific duty cycle: a D1 = M(1 − Du/p)/2 and b D1 = M(1 − Du/p)/2 + Dm . . Commutations during the dead time for Q5 and Q10 and Q8 and Q11: a Q5 and Q10, b Q8 and Q11 . . . . . . . . . . . . . . . . . Three-dimensional (3D) surface of the ZVS boundary versus Vbat and u. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZVS range and modulation trajectory for different battery voltages: a Vbat = 200 V, b Vbat = 250 V, and c Vbat = 300 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flowchart of the modulation trajectory . . . . . . . . . . . . . . . . . Closed-loop control diagram . . . . . . . . . . . . . . . . . . . . . . . . . D1 versus phase-shift angle u and battery voltage Vbat . . . . . Output power versus phase-shift angle u and battery voltage Vbat: a three-dimensional surface, b right lateral view of Fig. 6.13a, and c two-dimensional curves of the output power versus u . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms currents in p.u. in the converter versus the output power (dashed lines: conventional OSDAB converter without LC networks; solid lines: OSDAB converter with LC networks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 kW experimental prototype for test . . . . . . . . . . . . . . . . . Measured key waveforms of vAB, vCD, and vEF when Vbat = 250 V, Po = 650 W . . . . . . . . . . . . . . . . . . . . . Currents in the auxiliary LC networks: a Vbat = 200 V and Po = 650 W, b Vbat = 250 V and Po = 650 W . . . . . . .

. . 109

. . 110 . . 110 . . 111 . . 112 . . 116 . . 116 . . 117 . . 118 . . 122 . . 126 . . 128 . . 130

. . . .

. . . .

130 132 132 133

. . 134

. . 135 . . 136 . . 137 . . 137

xviii

Fig. 6.18

Fig. 6.19

Fig. 6.20

Fig. 6.21

Fig. 6.22

Fig. 6.23

Fig. 6.24

Fig. 6.25

Fig. 6.26 Fig. 6.27 Fig. 6.28 Fig. 6.29 Fig. 7.1 Fig. 7.2

Fig. 7.3 Fig. 7.4 Fig. 7.5

List of Figures

Measured key waveforms for the forward power flow in light loads: a Vbat = 200 V, Po = 300 W, b Vbat = 250 V, Po = 300 W, and c Vbat = 300 V, Po = 300 W . . . . . . . . . . . . . . . . . . . . . . . . . Measured key waveforms for the forward power flow in heavy loads: a Vbat = 200 V, Po = 1300 W, b Vbat = 250 V, Po = 1300 W, and c Vbat = 300 V, Po = 1300 W . . . . . . . . . . . Measured key waveforms for the reverse power flow in light loads: a Vbat = 200 V, Po = −328 W, b Vbat = 240 V, Po = −313 W, and c Vbat = 280 V, Po = −300 W . . . . . . . . . . Measured key waveforms for the reverse power flow in heavy loads: a Vbat = 200 V, Po = −1200 W, b Vbat = 240 V, Po = −1250 W, and c Vbat = 280 V, Po = −1268 W . . . . . . . . Gate signal and drain-source voltage of switch Q1: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W . . . . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q4: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W . . . . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q5: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W . . . . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q8: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W . . . . . . . . . . . . . . . . . . . . . . . . . Efficiency curves for the OSDAB converters with and without dual LC networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss breakdown in 1.3 kW output power . . . . . . . . . . . . . . . . . Rms current in the series inductor versus the battery voltage in 1.3 kW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loss breakdown in 200 W output power . . . . . . . . . . . . . . . . . Low-voltage-side parallel-connected DAB converter with auxiliary coupling inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms for working modes in forward power flow: a Mode 1a: 0.5 − D1/2  ua/p  ub/p  0.5, b Mode 2a: −(0.5 − D1/2)  ua/p  0.5 − D1/2  ub/p  0.5, c Mode 3: −(0.5 − D1/2)  ua/p  ub/p  0.5 − D1/2, d Mode 4: ua/ p  −(0.5 − D1/2)  0  0.5 − D1/2  ub/p . . . . . . . . . . Topological stages with half-switching period for Mode 1a: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4] . . . . . . . . . . . . . . . . . . . . Three-dimensional surface of the ZVS boundary conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZVS range in two-dimensional plane for different battery voltages: a Vbat = 20 V, b Vbat = 26.5 V, c Vbat = 27 V, d Vbat = 29 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

138

138

139

140

140

141

141

142 143 143 144 144 148

149 151 155

156

List of Figures

Fig. Fig. Fig. Fig.

7.6 7.7 7.8 7.9

Fig. 7.10 Fig. 7.11 Fig. 7.12 Fig. 7.13

Fig. 7.14

Fig. 7.15

Fig. 7.16

Fig. 7.17

Fig. 7.18

Fig. 7.19

Fig. 7.20

Fig. 7.21 Fig. 7.22

Fig. 8.1

xix

Control loop of the modulation scheme . . . . . . . . . . . . . . . . . . Flowchart of the modulation trajectory . . . . . . . . . . . . . . . . . . . Output power (p.u.) versus the phase-shift angle u . . . . . . . . . Rms current in the converter versus the output power in per unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Experimental prototype for test . . . . . . . . . . . . . . . . . . . . . . . . . Waveforms of currents in the auxiliary coupling inductor: a Vbat = 20 V, Po = 560 W, b Vbat = 30 V, Po = 560 W . . . . . Key waveforms in the forward power flow under light load: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W . . . . . Key waveforms in the forward power flow under heavy load: a Vbat = 20 V, Po = 1125 W, b Vbat = 30 V, Po = 1125 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms in the reverse power flow under light load: a Vbat = 20 V, Po = −190 W, b Vbat = 30 V, Po = −230 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms in the reverse power flow under heavy load: a Vbat = 20 V, Po = −1050 W, b Vbat = 30 V, Po = −1050 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q2: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W . . . . . . . . Gate signal and drain-source voltage of switch Q3: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q9: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q11: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W . . . . . . . . . . . . . . Hard switching waveforms of switch Q2 for the conventional parallel-connected DAB (PCDAB) converter in battery side: a Vbat = 20 V, Po = 450 W, b Vbat = 25 V, Po = 450 W . . . . . Efficiency curves of the PCDAB converter with and without CI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transient experimental results for load step change from 160 to 620 W when Vbat = 25 V: a output voltage (vo) and load current (io), b voltages and currents of the transformer, c extended figure of Fig. 7.22b before the load step change, d extended figure of Fig. 7.22b after the load step change . . . . Topology of the micro-converter . . . . . . . . . . . . . . . . . . . . . . .

157 158 158 159 160 161 161

162

162

163

163

164

164

165

165 166

166 170

xx

List of Figures

Fig. 8.2

Fig. 8.3 Fig. 8.4 Fig. 8.5 Fig. 8.6 Fig. 8.7 Fig. 8.8 Fig. 8.9 Fig. 8.10 Fig. 8.11 Fig. 8.12 Fig. 8.13

Fig. 8.14 Fig. 8.15 Fig. Fig. Fig. Fig. Fig. Fig.

8.16 8.17 8.18 8.19 8.20 8.21

Fig. 8.22 Fig. 8.23

Fig. 8.24 Fig. 9.1 Fig. 9.2

Detailed operating waveforms of BCM with different input voltages: a matched point, b higher than matched point, c lower than matched point . . . . . . . . . . . . . . . . . . . . . . . . . . Detailed modes during boundary conduction . . . . . . . . . . . . Output power ability with different leakage inductance values under different input voltages: a Vin = 24 V, b Vin = 36 V . Power versus phase angle under different input voltages with leakage inductance of 78 lH . . . . . . . . . . . . . . . . . . . . . . . . BCM power condition with leakage inductance of 78 lH . . BCM actual power condition when connected to an inventor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching legs definition of the primary-side full-bridge MOSFET network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Primary phase angle versus different input voltages at 300 W output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Border of two conduction conditions . . . . . . . . . . . . . . . . . . Ideal waveforms of the converter operating in high input voltage and light load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The generalized turning-off procedure of MOSFET . . . . . . . Loss breakdown a power loss versus different input voltage and output power, b comparison with same voltage rating silicon IPD60R180C7 under 24 V 150 W operation condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block diagram of the unified control strategy . . . . . . . . . . . . PWM generation unit of unified phase-shift control method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MPPT algorithm applied for the converter . . . . . . . . . . . . . . Waveform of the maximum power point measurement . . . . . Waveform operating with MPPT algorithm . . . . . . . . . . . . . Zoomed in waveforms in maximum power point . . . . . . . . . Photograph of the presented micro-converter . . . . . . . . . . . . ZVS condition of a Leg A, b Leg B at 36 V input voltage and 300 W output power . . . . . . . . . . . . . . . . . . . . . . . . . . . ZCS condition of the secondary-side diodes at 29 V input voltage and 250 W output power . . . . . . . . . . . . . . . . . . . . . Experimental result of the micro-converter: a 24 V input voltage and 200 W output power; b 29 V input voltage and 100 W output power; c 36 V input voltage and 300 W output power; d 36 V input voltage and 30 W output power . . . . . The total efficiency measured with the prototype . . . . . . . . . DAB converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Potential working modes in ZVS performance when the converter works in forward power flow: a Mode 1f; b Mode 2f; c Mode 3f; d Mode 4f . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 171 . . 172 . . 175 . . 176 . . 176 . . 177 . . 178 . . 179 . . 180 . . 181 . . 183

. . 184 . . 184 . . . . . .

. . . . . .

185 186 186 187 187 188

. . 189 . . 189

. . 189 . . 190 . . 194

. . 195

List of Figures

Fig. 9.3

Fig. 9.4

Fig. 9.5

Fig. 9.6 Fig. Fig. Fig. Fig.

9.7 9.8 9.9 9.10

Fig. 9.11

Fig. 9.12 Fig. 9.13 Fig. 9.14

Fig. 9.15

Fig. 9.16 Fig. 9.17 Fig. 9.18 Fig. 9.19 Fig. 9.20

Fig. 10.1

xxi

Relationship between D2 and u for different output powers in Mode 2f: a Irms_Mode2f versus D1 for different output powers; b Irms_Mode2f versus u for different output powers . . . . . . . . Curves of the duty cycles versus u for M = 0.75: a Curves of the expressions in (9.2) and (9.8); b Trajectories according to optimal working modes; c Improved trajectories for seamless transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Curves of the duty cycles versus u for M = 1.5: a Curves of the expressions in (9.10) and (9.15); b Trajectories according to optimal working modes; c Improved trajectories for seamless transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three-dimensional (3D) surfaces of D1 and D2 versus Vbat and u: a D1 versus Vbat and u; b D2 versus Vbat and u . . . . Surfaces of output power versus Vbat and u . . . . . . . . . . . . . Flowchart of the modulation scheme . . . . . . . . . . . . . . . . . . Closed-loop control diagram . . . . . . . . . . . . . . . . . . . . . . . . . Rms current in the transformer versus the load power for different modulation schemes and different battery voltages: a Vbat = 400 V (M = 0.75), b Vbat = 200 V (M = 1.5) . . . . . Peak current in the transformer versus the load power for different modulation schemes and different battery voltages: a Vbat = 400 V (M = 0.75), b Vbat = 200 V (M = 1.5) . . . . . Experimental prototype for test . . . . . . . . . . . . . . . . . . . . . . . Experimental results without working modes in seamless transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms in steady state: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W; c Vbat = 380 V, Po = 1200 W; d Vbat = 210 V, Po = 70 W; e Vbat = 210 V, Po = 600 W; f Vbat = 210 V, Po = 1200 W . . . . . . . . . . . . . . . . . . . . . . . . Transient experimental results for load step change from 80–1000 W: a Vbat = 380 V (M = 0.79); b Vbat = 210 V (M = 1.43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q1: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W . . Gate signal and drain-source voltage of switch Q4: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W . . Gate signal and drain-source voltage of switch Q5: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W . . Gate signal and drain-source voltage of switch Q8: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W . . Efficiency curves of the DAB converter with the presented modulation scheme, SPS, and DPS: a Vbat = 300 V and Vbat = 380 V, b Vbat = 210 V . . . . . . . . . . . . . . . . . . . . Current-fed bidirectional DC–DC converter . . . . . . . . . . . . .

. . 198

. . 201

. . 202 . . . .

. . . .

203 204 205 205

. . 206

. . 206 . . 207 . . 208

. . 209

. . 210 . . 210 . . 210 . . 211 . . 211

. . 212 . . 216

xxii

Fig. 10.2 Fig. 10.3

Fig. 10.4 Fig. 10.5

Fig. 10.6 Fig. 10.7

Fig. 10.8 Fig. 10.9 Fig. 10.10 Fig. 10.11 Fig. 10.12 Fig. 10.13

Fig. 10.14 Fig. 10.15

Fig. 10.16

Fig. 10.17

Fig. 10.18 Fig. 10.19 Fig. 10.20

List of Figures

Conventional modulation strategies for a current-fed bidirectional DC–DC converter: a PPS and b PPDPS . . . . . Different operation modes of the current-fed bidirectional DC–DC converter: a Mode 1a, b Mode 1b, c Mode 2a, d Mode 2b, e Mode 3a, f Mode 3b, g Mode 4a, and h Mode 4b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modified Mode 1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relationship between D2 and u for different output powers in Mode 2a: a D2 versus u for different output powers and b rms current in the transformer versus u for different output powers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Key waveforms in Mode 2a_m . . . . . . . . . . . . . . . . . . . . . . . Relationship between D2 and u for different output powers in Mode 4a: a D2 versus u for different output powers and b rms current in the transformer versus u for different output powers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modified Mode 4a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modified mode operation in the reverse power flow: a Mode 2b_m and b Mode 4b_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control diagram of the current-fed bidirectional DC–DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modulation scheme for the current-fed bidirectional DC–DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output power per unit (p.u.) versus the control variable d . . Trajectories of the modulation scheme: a output powers in p.u. versus D2 and u, b right lateral view of Fig. 10.13a, c left lateral view of Fig. 10.13a, and d top view of Fig. 10.13a . . Output powers in p.u. versus u for the PPDPS, PPS, and MPPS when D1 = 0.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Time interval for circulating current in different operation modes: a PPS, b PPDPS, c Mode 1a, d Mode 2a_m, and e Mode 4a_m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms of the circulating current in the battery side of the switches versus output power: a Vbat = 40 V and b Vbat = 60 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rms of the circulating current in the battery side of the switches versus output power: a Vbat = 40 V and b Vbat = 60 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switch conduction losses for the PPDPS, PPS, and MPPS: a Vbat = 40 V and b Vbat = 60 V . . . . . . . . . . . . . . . . . . . . . Core losses in the series inductor Lr for the PPDPS, PPS, and MPPS: a Vbat = 40 V and b Vbat = 60 V . . . . . . . . . . . . Measured key waveforms for the 40 V battery voltage: a Po = 200 W, b Po = 500 W, and c Po = 800 W . . . . . . . .

. . 217

. . 218 . . 220

. . 222 . . 222

. . 224 . . 225 . . 225 . . 230 . . 230 . . 231

. . 232 . . 233

. . 233

. . 234

. . 235 . . 236 . . 236 . . 238

List of Figures

Fig. 10.21 Fig. 10.22 Fig. 10.23 Fig. 10.24 Fig. 10.25 Fig. 10.26 Fig. 10.27 Fig. 10.28

xxiii

Measured key waveforms for the 60 V battery voltage: a Po = 200 W, b Po = 500 W, and c Po = 800 W . . . . . . . . Measured key waveforms for the 40 V battery voltage: a Po = −200 W, b Po = −500 W, and c Po = −800 W . . . . Measured key waveforms for the 60 V battery voltage: a Po = −200 W, b Po = −500 W, and c Po = −800 W . . . . Gate signal and drain-source voltage of switch Q1 at Vbat = 40 V: a Po = 200 W and b Po = −200 W . . . . . . . Gate signal and drain-source voltage of switch Q2 at Vbat = 40 V: a Po = 200 W and b Po = −200 W . . . . . . . Gate signal and drain-source voltage of switch Q5 at Vbat = 40 V: a Po = 200 W and b Po = −200 W. . . . . . . . . . . . . Gate signal and drain-source voltage of switch Q8 at Vbat = 40 V: a Po = 200 W and b Po = −200 W. . . . . . . . . . . . . Efficiency curves for the presented MPPS, conventional PPS, and PPDPS at a Vbat = 40 V, b Vbat = 50 V, and c Vbat = 60 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . 238 . . 239 . . 239 . . 240 . . 240 . . 241 . . 241

. . 242

List of Tables

Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table

3.1 4.1 5.1 5.2 5.3 5.4 6.1 6.2 6.3 6.4 6.5 6.6 7.1 7.2 7.3 7.4 8.1 8.2 9.1 10.1 10.2 10.3

Main components and their volume . . . . . . . . . . . . . . . . . . . Major components and their volume . . . . . . . . . . . . . . . . . . Expression for conduction loss in the primary circuit . . . . . Specifications in different converters . . . . . . . . . . . . . . . . . . Detailed specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specification of the converters . . . . . . . . . . . . . . . . . . . . . . . Boundary condition for each mode . . . . . . . . . . . . . . . . . . . ZVS conditions for Q1 and Q4 . . . . . . . . . . . . . . . . . . . . . . . Derived ZVS conditions for Q1 and Q4 . . . . . . . . . . . . . . . . ZVS conditions for Q5 and Q10 and Q8 and Q11 . . . . . . . . . Output power expressions in different working modes . . . . . Detailed specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZVS conditions for Q9 and Q11 . . . . . . . . . . . . . . . . . . . . . . ZVS conditions for Q2 and Q3 . . . . . . . . . . . . . . . . . . . . . . . Derived ZVS conditions for Q2 and Q3 . . . . . . . . . . . . . . . . Detailed specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Micro-converter parameters . . . . . . . . . . . . . . . . . . . . . . . . . Micro-converter specifications . . . . . . . . . . . . . . . . . . . . . . . Detailed specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ZVS conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Boundary condition of the operation modes . . . . . . . . . . . . . Detailed specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . . . . . . . . .

68 88 104 104 107 111 120 125 127 129 133 136 153 153 154 160 182 188 207 217 219 237

xxv

Chapter 1

Introduction

Abstract This chapter presents a brief introduction of the isolated DC–DC converters. The galvanic isolation not only can achieve voltage gain conversion, but also is necessary for the safety consideration in some applications, such as battery chargers, electrical vehicles, and energy storage systems. Soft switching and low current stress can improve the efficiency of wide voltage conversion range. Some typical isolated DC–DC converters, including phase-shift-controlled DC–DC converters, resonant isolated DC–DC converters, voltage-fed bidirectional DC–DC converters, and current-fed bidirectional DC–DC converters, are reviewed in these two aspects to present the prevalent efficiency improvement methods. This chapter also provides a basic foundation for the whole work, and it gives the goal of this book which provides topologies, modulation schemes, and design guidelines for high-frequency isolated DC–DC converters.

1.1

Application of Isolated DC–DC Converters

The demand for isolated DC–DC converters is growing, including telecommunications, data centers, battery chargers, industries and aerospace applications. Isolated DC–DC converters can achieve voltage conversion in different voltage levels. Furthermore, for the safety consideration, the galvanic isolation is also necessary in some cases. Even if a human being touches one terminal of the power supply with galvanic isolation, there will be no leakage current flowing through the human body to the ground. Therefore, galvanic isolation is a basic requirement in some applications. The conventional DC–DC converters consume at least 10% of the total electric power. How to be more efficient than the conventional DC–DC converters is a key concern in the research and industrial fields. Some typical applications of isolated DC–DC converters are introduced as the following.

© Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_1

1

PFC

400V DC Isolated

DC-DC

DC-DC

Introduction

1.8V DC

AC Power Distribution Unit (PDU)

12V DC

Xfmr 15kV AC

400 / 230V AC

1

400V AC

2

P Load

Power supply unit (PSU)

Fig. 1.1 Typical structure of the server power supply

1.1.1

Server Power Supply

With increasing of cloud computing and big data, it is expected that the data center will consume more percentage of the total electricity. Figure 1.1 shows a typical structure of the server power supply, including multiple-stage power conversion [1, 2]. Most of the major devices in the servers are powered by 12 V bus. This 12 V bus architecture was developed in the early 1990s, when the power consumption in the server was very low compared with today’s power level of CPU. In order to reduce the conduction loss in the power conversion, the International Electronics Manufacturing Initiative (iNEMI) undertook a project to develop a new industry standard for isolated DC–DC converters. This converter is used to step down 400 V directly to 12 V and directly placed on the motherboard, as seen in Fig. 1.1. Due to less power conversion stage, the efficiency for the server power supply is greatly improved.

1.1.2

Electrical Vehicle

An oil supply crisis and the prospect of reducing carbon emission promote the automobile manufacturer to develop hybrid vehicles and electrical vehicles (EVs) [3, 4]. Figure 1.2 shows the on/off board charging system and power level of EVs [5]. There are many power converters used to exchange energy for different power levels, including the battery management, power supply for the electric motor from the battery, and battery charging from the grid. Most of them need isolated DC–DC converters. Due to the limited space in the car, all the power converters should be very efficient and compact. The development of EVs is linked to the construction of the public infrastructure for charging or fast charging. The fast-charging station requires more power distribution capacity, high-power PFC, and isolated DC–DC converters.

1.1 Application of Isolated DC–DC Converters

3

Fig. 1.2 On/off board charging system and power level for EVs [5]

Surplus electricity stored in car batteries would have other benefits. Electric cars could act as backup energy storage systems, with the potential to power the households. Electric car owners could also benefit financially from vehicle to grid (V2G), receiving payments from electricity they have sold back to the grid. V2G technology also needs support of bidirectional isolated DC–DC converters.

1.1.3

Solid-State Transformer

The solid-state transformer is essentially the combination of a pulse-width modulation (PWM) converter and high-frequency transformers. The size and weight of the transformer can be considerably reduced compared to the 50/60 Hz transformer. A solid-state transformer usually contains high-frequency transformers, inside AC-to-AC converters or DC-to-DC converters, which provide galvanic isolation and power conversion for different voltage levels. In AC-to-AC solid-state transformers, the prevalent solution is AC-to-DC-to-DC-to-AC converter, in which the isolated DC–DC converter is also a necessary working stage [6, 7]. With the DC power distribution system, DC solid system is becoming a prevalent solution to smart DC grid. Figure 1.3 shows a typical DC solid-state transformer, which contains multiple modular isolated DC–DC converters [8–10]. The input of the converters is connected in series to share the high input voltage, and the output of the converters is connected in parallel to share the high output current. The solid-state transformer can be smaller and more efficient than a conventional transformer because it operates at high frequency. Furthermore, the SST can directly control the power flow and have the ability of fault ride-through.

4

1

Introduction

Low DC Voltage n:1

High DC Voltage n:1

n:1

Fig. 1.3 Circuit diagram of DC solid-state transformer

1.2 1.2.1

Typical Topologies of Isolated DC–DC Converter Phase-Shift Controlled DC–DC Converter

There are many topologies for isolated DC–DC converters, such as forward, flyback, half bridge, full bridge, and push–pull. Phase-shift full-bridge (PSFB) DC– DC converter can achieve zero-voltage switching (ZVS), so it has been widely used in many applications for wide conversion ratio, such as welding machines, battery chargers, and industrial power supplies. The typical circuit of PSFB DC–DC converter is shown in Fig. 1.4. However, the lagging leg of the PSFB DC–DC converter cannot achieve ZVS in light loads, which causes more switching loss and switching noise. In order to extend the ZVS range, an inductor is connected in series with the primary winding of the transformer, which also causes more duty cycle loss [11]. The peak current in the transformer is also increased. Besides, the

1.2 Typical Topologies of Isolated DC–DC Converter Fig. 1.4 Phase-shift full-bridge DC–DC converter

Q1

Q3 A

Vin

Cin

Q1

Vin

Cin Q2

Lf

Llk ir

B

Co

Vo

Ro

Co

Vo

Ro

Dr2

n:1:1

Dr1

Q3 A

Dr1

Tr

Q4

Q2

Fig. 1.5 Phase-shift full-bridge DC–DC converter with the series inductor in the primary side of the transformer

5

Dr3

Lr ir Q4

B Dr2

Dr4

series inductor also excites large voltage spike in the secondary diodes, which deteriorates the reliability. Extra snubber circuits should be added to reduce the voltage spike [12]. Using LC can extend the ZVS of the lagging switches [13], but it also causes more extra conduction loss. Two diodes and a series inductor can achieve ZVS of the lagging switches [14], and the ringing of the secondary diodes can also be reduced. A full bridge combined by two half bridges with a new rectifier stage is present to achieve ZVS and low conduction loss [15]. However, rectifier stage has more devices, which complicate the circuit. The filter inductor also can be placed in series with the primary winding of the transformer [16], as shown in Fig. 1.5. The voltage spike of the rectifier stage can be reduced, but the lagging switches will lose the ZVS performance. Due to the voltage stress reduced to half of the input voltage and the ZVS of the switches, three-level (TL) DC–DC converters are used in high input voltage applications. The phase-shift control can be extended to isolated phase-shift three-level (PSTL) DC–DC converters. Figure 1.6 shows the typical isolated PSTL DC–DC converter, in which the lagging switches also cannot achieve ZVS in light loads. Figure 1.7 shows the key waveforms of the PSTL DC–DC converter. When the duty cycle is very low, there is large circulating current freewheeling in the primary side of the circuit. Therefore, the converter is hard to achieve high efficiency in wide voltage range. In order to achieve ZVS in the lagging switches, a simple method is to use an external inductor in series with the primary winding of the transformer [17]. The inductor may cause large duty cycle loss and limit the gain of the converter. As shown in Fig. 1.7, it also leads to considerable ringing of the secondary rectifiers. An auxiliary network with an inductor and two more clamping diodes is employed at the primary side of the transformer to extend the ZVS of the lagging switches and limit the ringing of the secondary rectifiers [18].

6

1

Introduction

Q Cd Vin

D

iL

DR

Q ir

B

A

Css

vrec

Lf

Co

Ro Vo

Tr D

Q

Tr D R

Cd Q Fig. 1.6 Typical isolated PSTL DC–DC converter

Fig. 1.7 Key waveforms of the PSTL DC–DC converter

Q4

Q1

Q2

Q3

vAB 0 ir

0 Ringing

Q1 Q3

Vin/2

D·Ts/2

Vin/2

Circulating current

vrec iL 0 0

A wide range of soft-switching TL converter is proposed based on an inductor connected across the middle node of the TL half bridge and the neutral node of the flying capacitors [19]. However, the circulating current at the primary side of the transformer is increased. The junction capacitors of the switches can be charged and discharged during the dead time by the magnetizing inductor current in the primary two windings [20, 21]. The converters also have to face circulating current during the freewheeling period. A load adaptive LC network composed of coupling inductors can achieve ZVS in the lagging switches [22, 23]. The current amplitude in the auxiliary circuit is determined by the load power. The current amplitude is minimized at heavy loads and is increased at light loads to achieve ZVS in the switches. In order to reduce the circulating current and conduction loss, a blocking capacitor is used to reset the primary winding current during the freewheeling

1.2 Typical Topologies of Isolated DC–DC Converter

7

Q Cd Q

D ir

DR

Cb

B

Vin

Tr

Da A Da2

vrec Lf C o

C

Q

Tr

D

iL Ro Vo

DR

Cd Q

Fig. 1.8 ZVZCS isolated TL DC–DC converter

Fig. 1.9 Key waveforms of the ZVZCS TL DC–DC converter

Q4

Q1

ir

0 Ringing

Q3

Q2

Q3

vAB 0

Q1

Vin/2 D·Ts/2

Vin/2

Low circulating current

vrec iL 0 0

period, as shown in Fig. 1.8. The key waveforms of the zero-voltage-zero-current switching (ZVZCS) TL DC–DC converter are shown in Fig. 1.9. In order to avoid the current flowing to the reverse direction during the freewheeling period, two diodes are connected in series with the lagging switches [24]. Although the circulating current can be reduced, the conduction loss may not be optimized because of more conduction loss caused by the two additional diodes. Furthermore, the lagging legs will lose the ZVS conditions. Therefore, the converter can work in ZVZCS. For ZVZCS TL DC–DC converters, MOSFETs are used for leading switches to achieve ZVS, and IGBTs are used for lagging switches to achieve zero-current switching (ZCS) [25–27]. However, using IGBTs limits the switching frequency of the converter. The power density cannot be high. Half-bridge (HB) DC–DC converters can be extended to full-bridge (FB) TL DC–DC

8

1

Introduction

converters [28–30]. Due to more switches, there are more degrees of freedom for achieving soft-switching, high efficiency, and high-frequency operation.

1.2.2

Isolated Resonant DC–DC Converter

Resonant DC–DC converters were developed from the middle of last century. The basic circuits of the isolated resonant DC–DC converters and several common resonant tanks are shown in Fig. 1.10. The common resonant tanks can be classified as series resonant tank, parallel resonant tank, LCC resonant tank, LLC resonant tank, and so on. LLC converters have advantages of wide ZVS for MOSFETs and ZCS for rectifier diodes. It is considered as a good candidate to be a second-stage DC–DC converter of battery chargers for EVs. In order to work in wide input or output voltage range, the switching frequency has to swing in wide range, which will degrade the efficiency and make the EMC design difficult. In order to narrow the switching frequency, an LLC converter cascaded with a nonisolated DC–DC converter is a universal two-stage conversion [31–33], in which LLC converter works in DC transformer (DCX) with conversion ratio of one and no-isolated converter regulates the output voltage. The two-stage conversion may not optimize the global efficiency. To get higher efficiency, the output of a DC–DC converter is parallel with a DCX to regulate the output voltage by the duty cycle of DC–DC stage [34]. The DC–DC stage only handles a portion of the output power. A boost-integrated resonant converter is regulated by PWM control with fixed switching frequency. However, two more bulky inductors may degrade the power

Q1

Dr1

Q3 Resonant tank

A Vin

Cin Q2

B

Cs

Co Dr2

Q4

Series resonant tank Parallel resonant tank

Lr

Dr3

Cp

Cs Cp

Ro

Dr4

LCC resonant tank

Lr

Lr

Vo

LLC resonant tank

Lr

Cs Lm

Fig. 1.10 Circuit of the resonant DC–DC converter and several common resonant tanks

1.2 Typical Topologies of Isolated DC–DC Converter

9

density [35]. A hybrid-frequency modulation method for PWM-integrated resonant converters is shown in [36]. The converter can achieve wide input voltage range with low conduction loss, but it cannot achieve wide ZVS performance. A hybrid three-level configuration is proposed for the LLC resonant converter, where the voltage gain is doubled using three-level and two-level working modes [37]. A full-bridge and half-bridge integration for LLC converter can also extend the voltage conversion range [38]. A two-transformer-based LLC converter can also achieve wide gain range [39]. A PSFB converter hybrid with an LLC converter working in constant switching is presented in [40–42]. The outputs of the two converters are connected in series or parallel. The lagging switches in the PSFB converter can achieve ZVS with the aid of the LLC converter. A resonant DC–DC converter is proposed by using a bidirectional ac switch on the output side [43, 44]. There are three operating modes, and the mode transition is implemented according to the value of the input voltage. In order to reduce the current stress in the switches, boundary current mode (BCM) has lower root-mean-square (rms) current as well when delivering the same power [45]. A five-element multi-resonant (LLC– LC) DC–DC converter can attain the wide range output power and voltage regulations by a practical-range pulse-frequency modulation (PFM) [46]. In order to improve the dynamic response for series resonant converters, optimal trajectory control is proposed in [47]. Simplified optimal trajectory control (SOTC) provides fast dynamic response for LLC converters [48]. The optimal trajectory requires load current, which needs more current sensors. A Bang–Bang charge control can achieve good dynamic performance by utilizing the series resonant capacitor voltage level to trigger the MOSFETs’ switching actions [49].

1.2.3

Voltage-Fed Bidirectional Isolated DC–DC Converter

Energy storage system (ESS) has become a significant backup for the power supply [50]. Especially for renewable energy system, they can compensate the possible mismatch of the electrical supply and the load demand [51]. Dual active bridge (DAB), shown in Fig. 1.11, has become a universal solution to isolated bidirectional DC–DC converters in ESS.

Fig. 1.11 DAB converter

iin_c

io_c Q3

Q1

Vbat

A Cbat Q2

Lr

Q7

Q5

Tr

C

D

ir B 1:n Q4

Q6

Q8

Co

Vo

10 Fig. 1.12 Key waveforms of the typical modulation schemes: a SPS, b EPS, and c DPS

1

(a)

vAB vCD

Introduction

Ts/2

Ts/2

ir

(b)

vAB

D Ts

vCD

Ts

ir (c)

vAB vCD

D·Ts/2

D·Ts/2

ir

The DAB converter is first proposed in [52]. The two full bridges generate two 50% duty cycle square waveforms. DAB converter can achieve bidirectional power flow by controlling the single-phase-shift (SPS) angle of the two full bridges [52], as shown in Fig. 1.12a. When the effective input and output voltages are matched, the converter can achieve high efficiency. When the voltage varies in a wide range, the efficiency is degraded because of hard switching and large conduction loss [53]. In order to reduce the circulating current, extended phase-shift (EPS) control is proposed to reduce the backflow power [54, 55], and its key waveforms are shown in Fig. 1.12b. In EPS control, the full bridge in one side of the transformer

1.2 Typical Topologies of Isolated DC–DC Converter

11

generates a two-level square waveform, and the one in the other side generates a three-level waveform by regulating the duty cycle. The duty cycle can also be calculated by particular loss breakdown analysis in [56, 57], which only provides the experimental results of open-loop control. A dual phase-shift (DPS) control is proposed to improve the efficiency [58, 59]. Figure 1.12c shows the key waveforms of DPS, in which the two full bridges in both input and output sides generate three-level waveforms, and the effective duty cycles of the two full bridges are the same. In [60], the DPS modulation scheme is extended in three-level DAB converters. Due to two degrees of freedom in DPS, the current stress can be reduced. In [58], the power loss including conduction loss, switching loss, and core loss is optimized by using Lagrange multiplier, but analytical expressions of the optimal working modes cannot be derived by solving the nonlinear equations. Only offline data can be obtained by using numerical solution instead of analytical solution. In order to simplify the optimized DPS control, the peak current in the transformer is set to be the optimized target in [59]. However, the peak current directly reflects to the core loss. The conduction loss is associated with the rms current in the transformer. In DAB converter, the duty cycles of the two bridges can be regulated dependently. Therefore, the optimized DPS control is actually the local optimal working mode rather than the global optimal working mode for required transmission power. Therefore, triple phase-shift (TPS) modulation scheme is investigated to optimize the efficiency for different power loads [61]. Based on the TPS working mode, triangular current modulation (TCM) [61] and trapezoidal modulation (TZM) [62] can be derived. They are special cases of TPS. In order to simple the analyses, Fourier-based strategies for DAB analyses have been developed [63–65]. The fundamental and harmonic components in voltage and current can be obtained by using Fourier transform. The transferred power and rms current can be derived by fundamental and low-order components. However, this method is lack of accuracy. The minimum peak current is the optimal objective, and the transferred power is calculated by Fourier-based method to simplify the optimal working formulas [66]. Therefore, this modulation scheme is also a proximate solution. A global optimal condition for DAB converters is proposed with minimized rms current during the whole power range [67], but the converter cannot achieve ZVS especially for light loads. Furthermore, a control loop cannot contain both forward and reverse power flows. In [68], a current stress optimized method is used to compare the rms current of different modulation schemes. The analyses in [66, 68] are also based on Karush–Kuhn–Tucker (KKT) conditions, in which the output of the controller builds relationship with the nominal output power. The duty cycle and phase-shift angle are calculated from the nominal output power. Similar conclusions are drawn from the previous works. In light loads, the DAB converter is preferred to work in TCM. In heavy loads, the converters have to switch into EPS to reduce the current stress. However, by using KKT condition or Lagrange multiplier in [66, 68], the analytical expressions for the modulation scheme are very complicated by using many square root operations, which costs too much time for the digital signal process.

12

1

Q3

Q1 A Vbat

Cbat

ir

La B

Q2

Q7

Q5

Lr Cr Tr

Q4

Introduction

C Lm

D

Co

Vo

1:n

Q6

Q8

Fig. 1.13 Series resonant DAB converter

Although DPS can reduce the conduction loss of the switches, not all the switches can achieve ZVS performance. To achieve all the switches in DAB converter working in ZVS, a full-operating range ZVS has been achieved by using commutation inductors in parallel with the active full bridges [69]. However, the commutation inductor causes circulating current in all operation modes. The amount of charge that is required to charge the nonlinear parasitic output capacitances of the switches during commutation is analyzed for ZVS with nearly minimum circulating current [70]. A hybrid half bridge and full bridge to generate a four-level waveform is proposed for wide ZVS and low conduction loss [71]. The essence of these strategies is to extend more degrees of freedom for the soft switching and conduction loss reduction. The auxiliary resonant commutated pole (ARCP) composed of auxiliary inductor and switches can reach full ZVS capacity [72, 73]. In addition, an auxiliary commutated inductor in [74] can be extended to any full-bridge power stages for wide ZVS operation. However, the current in the auxiliary components increases the conduction loss in whole operation modes. Another type of DAB converter is a resonant DAB converter, in which the series inductor is replaced by resonant tank. The resonant tank can be composed by inductor-capacitor (LC) [75], LCL [76], CLC [77], and CLLC [78]. Figure 1.13 shows the series resonant DAB converter [75]. The bidirectional power flow can be regulated by the duty cycles of the two full bridges [79] or the phase-shift angle [80]. In series resonant DAB converter, the rms current and turn-off current are low, which can reduce the conduction loss and turn-off loss. However, the peak current in the switches may be higher than conventional DAB converters. Figure 1.14 shows a hybrid three-level and two-level series resonant DAB converter, which can achieve wide voltage conversion range [81]. In order to achieve ZVS in resonant DAB converters, auxiliary components have to be used, such as La in Fig. 1.13.

1.2.4

Current-Fed Bidirectional Isolated DC–DC Converter

A buck/boost converter cascaded with a DAB converter (BC-DAB) is an excellent solution to a bidirectional DC–DC converter in an energy storage system, since it

1.2 Typical Topologies of Isolated DC–DC Converter

Ci1

Q1

Q7

Q2 C3

Vbat

Q8

Q3

Ci2

Q4

Q5 A

Lr ir

Q11

Q9

Tr

Cr

13

C

D

B 1:n

Q6

Q10

Co

Vo

Q12

Fig. 1.14 Hybrid three-level and two-level series resonant DAB converter

Buck/Boost converter

DAB converter

Q3

Q1

Q7

Q5

Lf 1

Lr

Cf

Q2

Q4

Q11

ir

Cin

Lf 2

Vbat

Q9 Tr

Co

1:n

Q6

Q8

Q10

Vo

Q12

Fig. 1.15 Buck/boost converter cascaded with a DAB converter

meets the requirements of the wide input or output range. The circuit is shown in Fig. 1.15. The buck/boost converter can work in PWM control to regulate, and the effective conversion ratio of the DAB converter can be set to 1. The DAB converter can work in low circulating current conditions. However, the buck/boost converter works in hard switching. A current-fed bidirectional DC–DC converter is proposed in [82], in which a buck/boost converter and a DAB converter are combined by sharing some switches. The converter is shown in Fig. 1.16. By integrating the

Vc

Ccl Vbat

iL1

Lf 1

iL2

Lf 2

Cf

Q2

Q5 ip 1:n is

Q3

Q1 A

Lr B Q4

battery Fig. 1.16 Current-fed bidirectional DC–DC converter

Q7

C D

Tr Q6

Q8

Vo

14

1

C1

Q1 iL

Lf 1

A

ip

Lr B

Vbat

Cf Q 2

C2

Q3 1:n is

Introduction

C3

C D

Tr Q4

Vo

C4

battery Fig. 1.17 Half-bridge current-fed bidirectional DC–DC converter

winding of the filter inductor into the transformer, a winding-coupled bidirectional ZVS converter is proposed in [83]. By using the PPS control, all the switches work in soft switching, the clamping voltage is controlled by the duty cycles of the primary switches, and the bidirectional power flow is controlled by the phase-shift modulation. However, the converters cannot achieve high efficiency for light loads because of the large circulating current. To reduce the circulating current in light loads, an improved PWM plus dual phase-shift (PPDPS) is employed to increase the efficiency [84]. Furthermore, a current-fed semi-DAB [85] is developed by replacing two switches into two diodes. The converter achieves highly efficient unidirectional power flow. All the switches achieve ZVS, and the diodes achieve ZCS. However, when the input voltage is very low, the converter has to handle a large phase-shift angle, which may increase the rms current in the transformer. Therefore, the efficiency is degraded with the low input voltage. The half-bridge isolated current-fed DC–DC converter is proposed in [86], as shown in Fig. 1.17. In [87], the researchers develop a three-phase full-bridge current-fed DC–DC converter without clamp capacitor. However, it still has difficulty in soft startup. In [88], a modified current-fed DC–DC converter can reduce the conduction loss. However, the secondary switches may work in hard switching on some occasions. The current-fed bidirectional isolated DC–DC converter also can be integrated into resonant tank [89]. Current-fed isolated DC–DC converters were extended into multi-port systems for renewable power systems [90, 91] and hybrid energy storage systems [92]. Photovoltaic systems and energy storage systems are integrated in a current-fed DC–DC converter to supply power for the loads [90]. Because of greater degrees of freedom, the photovoltaic system and energy storage system are decoupled in the control loop. A dual input current-fed DAB converter that powered by a fuel-cell– battery system achieves a near-ripple-free DC bus voltage [91]. In [92], researchers develop a current-fed bidirectional DC–DC converter as a symmetrical structure for a battery and super-capacitor system. The above researches show that current-fed bidirectional DC–DC converters are flexible and applicable because they offer greater degree of freedom for control.

1.3 Trend of the DC–DC Converter

1.3

15

Trend of the DC–DC Converter

The conventional power supplies require high efficiency in narrow input or output voltage range. The modern power supplies need high efficiency in wide input or output voltage range, especially for distribution generation system. Taking photovoltaic system, for example, the output voltage of the PV panels is associated with the solar radiation. It will be varied in wide range. In this case, the front-end DC– DC converters for PV systems should have high efficiency in wide input voltage range. Furthermore, the converter needs to be more efficient in wide load range. Conventional isolated DC–DC converters are difficult to achieve these requirements. In order to get high efficiency in wide voltage range and wide load range, the following aspects should be considered: 1. The converter should guarantee soft switching in wide operation range. Especially for MOSFETs, ZVS is necessary to reduce the switching loss, and it also can ease the EMC design. 2. The conduction loss of the switches and the copper loss in the transformer should be as low as possible. The circulating loss, defined as the power loss caused by energy commutating in the energy storage devices of the circuits, should be reduced. In some occasions, the circulating current in the converter is benefit for achieving ZVS. Therefore, the circulating loss should be just enough for ZVS. 3. The core loss of the transformer is associated with the magnetizing inductor. More turns of winding can increase the magnetizing inductor, which can reduce the core loss. However, more turns of winding will increase the copper loss. Therefore, there must be trade-off between the core loss and the copper loss. The same conclusion can be obtained from filter inductor. How to reduce the current ripple of the filter inductor is also a potential solution to improve the efficiency. 4. As reviewed in Sect. 1.2, some converters have more degrees of freedom to regulate the voltage or power, including duty cycle, phase-shift angle, even switching frequency. The ZVS and conduction loss can be optimized by using different modulation variables. How to analyze and select the effective working modes is also a key concern.

1.4

Organization of the Book

Based on the issues of the isolated DC–DC converters, this book is focused on topologies and modulation schemes for unidirectional and bidirectional isolated DC–DC converters. From Chaps. 2–5, new topologies of isolated three-level DC– DC converters are presented to optimize the efficiency. From Chaps. 7 to 10,

16

1

Introduction

improved modulation and control schemes are presented for isolated DC–DC converters in different applications. In Chaps. 2–5, TL DC–DC converters are studied for wide ZVS and low conduction loss. In Chap. 2, a hybrid phase-shift-controlled three-level and LLC DC– DC converter is introduced to achieve full-load ZVS performance. In Chap. 3, a blocking capacitor is used to reset the primary winding current of the TL converter. The rectifier stage is composed of four diodes in the center-tap rectification, forcing the circulating current at the primary side to stay zero during the freewheeling period. In Chap. 4, an improved TL DC–DC converter with two transformers connected in series on the primary side of the transformer is presented to achieve wide ZVS and low conduction loss. Moreover, the current ripple of the filter inductor current is reduced. Chapter 5 is focused on a dual half-bridge cascaded three-level DC–DC converter, in which the circulating current is reduced without loss of ZVS performance. The converter can reduce the current ripple of the filter inductor, which may improve the power density. Chapters 6 and 7 show the modular bidirectional DC–DC converters. Chapter 6 is focused on output series-connected DAB converters for high output voltage applications, and Chap. 7 is focused on parallel-connected DAB converters for low battery voltage applications. In these two chapters, ZVS in full-operation range is achieved by using auxiliary networks. In order to guarantee the currents which are just enough for ZVS in auxiliary networks, modulation trajectories are studied based on boundary of the ZVS condition. Chapter 8 introduces a micro-converter utilizing fixed-frequency BCM control method for PV applications. The leakage inductance current can work in BCM with fixed switching frequency. Chapter 9 presents a modulation scheme for the voltage-fed DAB converter. The potential working modes for ZVS are analyzed. Based on the ZVS working modes, rms current is set as the optimized objective. The modulation scheme builds the relationship of the optimized working mode for the seamless transition, which leads to stable operation during the mode transition. Chapter 10 is focused on the modulation scheme of current-fed bidirectional DC–DC converters for loss reduction. The potential working modes of the current-fed DC–DC converter are analyzed. The optimized modulation scheme for different battery voltages and different loads are developed to achieve full-operation ZVS and low conduction loss.

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1

Introduction

65. Riedel J, Holmes DG, McGrath BP, Teixeira C (2016) Determination of DC link harmonics in dual active bridge DC–DC converters using frequency domain analysis. In: 2016 IEEE 8th international power electronics and motion control conference (IPEMC-ECCE Asia), pp 70–77 66. Huang J, Wang Y, Li Z, Lei W (2016) Unified triple-phase-shift control to minimize current stress and achieve full soft-switching of isolated bidirectional DC–DC converter. IEEE Trans Ind Electron 63(7):4169–4179 67. Tong A, Hang L, Li G, Jiang X, Gao S (2018) Modeling and analysis of a dual-active-bridge-isolated bidirectional DC/dc converter to minimize RMS current with whole operating range. IEEE Trans Power Electron 33(6):174–188 68. Hou N, Song W, Wu M (2016) Minimum-current-stress scheme of dual active bridge DC–DC converter with unified phase-shift control. IEEE Trans Power Electron 31(12):8552–8561 69. Everts J, Krismer F, Keybus J, Driesen J, Kolar JW (2014) Optimal ZVS modulation of single-phase single-stage bidirectional DAB AC–DC converters. IEEE Trans Power Electron 29(8):3954–3970 70. Everts Jordi (2017) Closed-form solution for efficient ZVS modulation of DAB converters. IEEE Trans Power Electron 32(10):7561–7576 71. Xu G, Sha D, Xu Y, Liao X (2018) Hybrid-bridge-based DAB converter with voltage match control for wide voltage conversion gain application. IEEE Trans Power Electron 33(2):1378– 1388 72. Soltau N, Lange J, Stieneker M, Stagge H, De Doncker RW (2014) Ensuring soft-switching operation of a three-phase dual-active bridge DC–DC converter applying an auxiliary resonant-commutated pole. In: 16th European conference on power electronics and applications, pp 1–10 73. Voss J, Bagaber B, De Doncker RW (2017) Full soft-switching capability of the dual-active bridge by using the auxiliary-resonant commutated-pole technique. In: IEEE 8th international symposium on power electronics for distributed generation systems (PEDG), pp 1–8 74. Pahlevaninezhad M, Das P, Drobnik J, Jain PK, Bakhshai A (2012) A novel ZVZCS full-bridge DC/DC converter used for electric vehicles. IEEE Trans Power Electron 27 (6):2752–2769 75. Wu H, Ding S, Sun K, Zhang L, Li Y, Xing Y (2017) Bidirectional soft-switching series-resonant converter with simple PWM control and load-independent voltage-gain characteristics for energy storage system in DC microgrids. IEEE J Emerg Sel Topics Power Electron 5(3):995–1007 76. Twiname RP, Thrimawithana DJ, Madawala UK, Baguley CA (2014) A new resonant bidirectional DC–DC converter topology. IEEE Trans Power Electron 29(9):4733–4740 77. Twiname RP, Thrimawithana DJ, Madawala UK, Baguley CA (2015) A dual-active bridge topology with a tuned CLC network. IEEE Trans Power Electron 30(12):6543–6550 78. Zhang C, Li P, Kan Z, Chai X, Guo X (2017) Integrated half-bridge CLLC bidirectional converter for energy storage systems. IEEE Trans Ind Electron 65(5):3879–3889 79. Jiang T, Zhang J, Wu X, Sheng K, Wang Y (2015) A bidirectional LLC resonant converter with automatic forward and backward mode transition. IEEE Trans Power Electron 30 (2):757–770 80. Yaqoob M, Loo KH, Lai YM (2017) Extension of soft-switching region of dual-active-bridge converter by a tunable resonant tank. IEEE Trans Power Electron 32(12):9093–9104 81. Jiang T, Zhang J, Wu X, Sheng K, Wang Y (2016) A bidirectional three-level LLC resonant converter with PWAM control. IEEE Trans Power Electron 31(3):2213–2225 82. Xiao H, Xie S (2015) A ZVS bidirectional DC–DC converter with phase-shift plus PWM Control scheme. IEEE Trans Power Electron 23(2):6488–6494 83. Li W, Wu H, Yu H, He X (2011) Isolated winding-coupled bidirectional ZVS converter with PWM plus phase-shift (PPS) control strategy. IEEE Trans Power Electron 26(12):3560–3750 84. Shi Y, Li R, Xue Y, Li H (2015) Optimized operation of current-fed dual active bridge DC– DC converter for PV applications. IEEE Trans Ind Electron 30(12):6986–6995

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Chapter 2

Hybrid Phase-Shift-Controlled Three-Level and LLC DC–DC Converter with Active Connection at the Secondary Side

Abstract This chapter presents a hybrid phase-shift-controlled TL and LLC DC– DC converter. The TL DC–DC converter and LLC DC–DC converter have their own transformers, respectively. Compared with conventional half-bridge (HB) TL DC–DC converters, the proposed one has no additional switch at the primary side of the transformer, where the TL converter shares the lagging switches with the LLC converter. At the secondary side of the transformers, the TL and LLC converters are connected by an active switch. With the aid of the LLC converter, ZVS of the lagging switches can be achieved easily even at light load conditions. Wide ZVS range for all the switches can be ensured. Both the circulating current at the primary side and the output filter inductance are reduced. Furthermore, the efficiency of the converter is improved. The features of the proposed converter are analyzed, and the design guidelines are given in the chapter. Finally, the performance of the converter is verified by a 1 kW experimental prototype. Keywords Three-level

2.1


LLC
Phase-shift
Zero-voltage switching

Hybrid Three-Level and LLC DC–DC Converter

In order to achieve wide voltage conversion range, some converters are combined to form hybrid converters. A TL DC–DC converter combined with a full-bridge converter is used to reduce the output filter inductance [1, 2]. However, more additional switches have to be used. Besides, a TL converter using two transformers without additional switches also can reduce the output filter size [3]. Recently, hybrid converters are attractive due to their outstanding performance. The hybrid converters integrate two or more converters into a new one, such as hybrid boost three-level DC–DC converter [4], hybrid dual full-bridge DC–DC converter [5], hybrid resonant and PWM converter [6, 7], and three-phase three-level DC–DC converter [8]. In this chapter, a hybrid TL and LLC DC–DC converter is presented with simple phase-shift control for wide ZVS and low circulating current. Figure 2.1 shows the circuit configuration for the hybrid TL and LLC (HTL–LLC) DC–DC converter, © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_2

23

24

2

Hybrid Phase-Shift-Controlled Three-Level and …

which is composed of an TL DC–DC converter and an HB LLC DC–DC converter. The divided capacitors Cd1, Cd2, and the flying capacitor Css are large enough to be treated as voltage sources of Vin/2. Q1 and Q4 are leading switches; Q2 and Q3 are lagging switches. The TL converter shares the lagging switches Q2 and Q3 with the LLC converter. C1–C4 are junction capacitors of the switches, and C1 = C2 = C3 = C4 = C. Tr1 is the transformer of the TL converter, and Tr2 is the transformer of the LLC converter. The turns ratio of the two transformers Tr1 and Tr2 is n1:1:1 and n2:1:1, respectively. Lk1 is the leakage inductor of Tr1. The magnetizing inductor of Tr1 is large enough to ignore the magnetizing current during the switching period. Lr is the resonant inductor of the LLC converter, and Lm2 is the magnetizing inductor of Tr2. Cr1 and Cr2 are resonant capacitor, and Cr1 = Cr2 = Cr. QR, named as an active switch, works as a controlled rectifier to reduce the conduction loss. Figure 2.2 shows the key waveforms of the HTL–LLC converter. The converter works with a constant switching frequency. The output voltage of the converter is controlled by the phase-shift manner. Gate signal of QR is expressed as QR ¼ Q1
Q3 þ Q2
Q4 . The LLC converter works in open-loop control. The resonant frequency is
 p ffiffiffiffiffiffiffiffiffiffiffiffi expressed as fr ¼ 1 2p 2Cr Lr . The LLC resonant frequency is chosen to be the switching frequency, so the voltage gain of the LLC converter is independent of the load and equal to one [9]. Therefore, the output voltage of the LLC converter is expressed as VLLC ¼

Vin 4n2

ð2:1Þ

Moreover, the rectifier DR3 and DR4 work in ZCS, so the reverse recovery is avoided. In view of the output voltage control, VLLC should be less than the output voltage Vo. There are eight working stages in each half-switching period, as shown in Fig. 2.2. Stage 1 ([t0, t1]) (Fig. 2.3a): Prior to t0, Q1 and Q3 are on, and Q2 and Q4 are off. At time t0, Q3 is turned off. The primary winding current of transformer Tr2 starts to charge and discharge the junction capacitors of Q3 and Q2, respectively. The primary winding current of Tr1 starts to increase. Since DR1–DR4 are reverse biased,

Fig. 2.1 Hybrid TL and LLC converter

Q1 Cd1

Vin

B

Cd2

D1 Q2 ip1 Tr1 A

D2

Q3

Q4

C1

vrec

Tr1

C2 Cr1 Lm2 ip2

iLf Lf

Co Ro Vo

QR

Tr2

Lr

C3

Cr2

C4

DR1 iTL

E

Css

F

DR2 DR3

Tr2 DR4

iLLC Cos VLLC

Active Switch

2.1 Hybrid Three-Level and LLC DC–DC Converter

25

Fig. 2.2 Key waveforms of the HTL–LLC converter

Tr1 and Tr2 do not transfer energy from the primary side to the secondary side, and ipr2 is equal to the magnetizing current of Tr2. The amplitude of the magnetizing current Im2 is expressed as Vin Ts Im2 ¼ ð2:2Þ 16Lm2 where Ts is the switching period. The output filter inductor current iLf freewheels through Cos and the body diode of QR. The primary winding current and voltages of the junction capacitors C2 and C3 are expressed as ipr1 ¼ Im2  Im2 cos½xm ðt  t0 Þ Vin Im2 
sin½xm ðt  t0 Þ vC2 ðtÞ ¼ 2 2Cxm Im2 vC2 ðtÞ ¼
sin½xm ðt  t0 Þ 2Cxm 1 ffi where xm ¼ pffiffiffiffiffiffiffiffi . 2CL k1

ð2:3Þ

26 Fig. 2.3 Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8]

Hybrid Phase-Shift-Controlled Three-Level and …

2

(a) Q1 Cd1

Vin

B

Cd2

D1 Q2

C1 C2

DR1 iTL

E

vrec

Tr1

Cr1

Lm2 Lk1 T A r1 D2

Q3

Lr

C3

Cr2

C4

Q1

C1

Co Ro Vo

QR

Tr2

Q4

iLf Lf

Css

F

DR2 DR3

iLLC Cos VLLC

Tr2 DR4

(b) Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1 D2

Q3

Q4

vrec

Tr1

C2 Cr1 Lm2

iLf Lf

Co Ro Vo

QR

Tr2

Lr

C3

Cr2

C4

DR1 iTL

E

Css

F

DR2 DR3

iLLC Cos VLLC

Tr2 DR4

(c) Q1 Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1 D2

Q3

C1

Tr2

Lr

C3

Cr2

C4

Q1

C1

vrec

Tr1

C2 Cr1 Lm2

Q4

DR1 iTL

E

Css

F

Co Ro Vo

QR

DR2 DR3

iLLC Cos

Tr2

iLf Lf

VLLC

DR4

(d) Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1

vrec

Tr1

C2 Cr1 Lm2

iLf

Lf

Co Ro Vo

QR

Tr2

Lr

Q3

C3

Cr2

Q4

C4

D2

DR1 iTL

E

Css

F

DR2 DR3

iLLC Cos VLLC

Tr2 DR4

2.1 Hybrid Three-Level and LLC DC–DC Converter

27

(e) Q1 Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1

D2

Q3

C1

Tr2 C3

Cr2

Q1

C1

iLf Lf

Co Ro Vo

QR

Lr

C4

vrec

Tr1

C2 Cr1 Lm2

Q4

DR1 iTL

E

DR2 DR3

Css

F

iLLC Cos VLLC

Tr2 DR4

(f) Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1 D2

Q3

Lr

C3

Cr2

Q1

C1

iLf Lf

Co Ro Vo

QR

Tr2

C4

vrec

Tr1

C2 Cr1 Lm2

Q4

DR1 iTL

E

Css

F

DR2 DR3

iLLC Cos VLLC

Tr2 DR4

(g) Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1 D2

Q3

Lr

C3

Cr2

Q1

C1

iLf Lf

Co Ro Vo

QR

Tr2

C4

vrec

Tr1

C2 Cr1 Lm2

Q4

DR1 iTL

E

Css

F

DR2 DR3

iLLC Cos

Tr2

VLLC

DR4

(h) Cd1

Vin

B

Cd2

D1 Q2 Lk1 T A r1

D2

Q3

Q4

Fig. 2.3 (continued)

C3 C4

vrec

Tr1

C2 Cr1 Lm2

Tr2

DR1 iTL

E

iLf Lf

Co Ro Vo

QR

Lr

Css

Cr2

F

DR2 DR3

iLLC Cos

Tr2 DR4

VLLC

28

2

Hybrid Phase-Shift-Controlled Three-Level and …

Stage 2 ([t1, t2]) (Fig. 2.3b): At time t1, the drain-source voltage of Q2 reaches zero, and ipr2 flows through the body diode of Q2. ipr2 is equal to Im2. ipr1 increases linearly. The output filter inductor current iLf freewheels through Cos and the body diode of QR. ipr1 in this stage is expressed as ipr1 ðtÞ ¼ ipr1 ðt1 Þ þ

Vin ðt  t1 Þ 2Lk1

ð2:4Þ

Stage 3 ([t2, t3]) (Fig. 2.3c): At time t2, Q2 is switched on with ZVS. The inductor Lr starts to resonate with Cr1 and Cr2. DR3 is forward biased. The LLC circuit starts to transfer power to the output. iLf still freewheels through Cos and the body diode of QR. ipr1 still increases linearly as expressed in (2.4). Stage 4 ([t3, t4]) (Fig. 2.3d): At time t3, DR1 is forward biased. The TL circuit transfers energy through Tr1 to the output. At this time, the voltage of vrec is larger than VLLC, so the body diode of QR is reverse biased. The LLC circuit still charges the capacitor Cos. ipr1 in this stage is expressed as ipr1 ðtÞ ¼ ipr1 ðt3 Þ þ

Vin =2  n1 Vo ðt  t3 Þ Lk1 þ n21 Lf

ð2:5Þ

Stage 5 ([t4, t5]) (Fig. 2.3e): When Q1 is turned off at t4, and the voltages across the junction capacitors C1 and C4 are charged and discharged linearly by the energy stored in the output filter inductor Lf. Since vrec is larger than VLLC, the body diode of QR is still reverse biased. Stage 6 ([t5, t6]) (Fig. 2.3f): When C1 reaches Vin/2 and C4 reaches zero, the body diode of Q4 is forward biased. Simultaneously, when the voltage vrec is less than VLLC, the body diode of QR is forward biased. iLLC starts to increase and flows through the body diode of QR, while iTL decreases. The LLC circuit starts to transfer energy to the output. Stage 7 ([t6, t7]) (Fig. 2.3g): At time t6, Q4 and QR are turned on with ZVS. The primary winding current of Tr1 decreases and freewheels through D1 and Q2. iTL decreases, while iLLC increases and flows through QR. Stage 8 ([t7, t8]) (Fig. 2.3h): Stage 8 starts when ipri1 and iTL reach zero. Then DR1 and DR2 are both off, and vrec is equal to VLLC. The filter inductor current iLf is equal to iLLC. iLf freewheels through QR and Cos.

2.2 2.2.1

Analysis of the HTL–LLC Converter DC Conversion Ratio

The DC conversion ratio of the converter in continuous conduction mode (CCM) can be derived from the volt-second balance for the output filter. It yields

2.2 Analysis of the HTL–LLC Converter

29



 Vin  Vo Deff þ ðVLLC  Vo Þð1  Deff Þ ¼ 0 2n1

ð2:6Þ

where Deff is the effective duty cycle. Substituting (2.1) into (2.6), the DC conversion ratio of the converter is expressed as M¼

Vo Deff 1  Deff ¼ þ Vin 2n1 4n2

ð2:7Þ

The effective duty cycle is expressed as Deff ¼ D  Dloss ¼ D 

4Vo Lk1 4Lk1 ¼DM Vin Ro n1 Ts Ro n1 Ts

ð2:8Þ

where Ro is the load resistance; Ts is the switching period; and Lk1 is the leakage inductance of Tr1. Substituting (2.8) into (2.7), the DC conversion ratio in view of duty cycle loss is written by M¼

D þ 1D Vo 4n2 2n1 ¼ Vin 1 þ 2  1 Lk1 n1 n2 Ro n1 Ts

ð2:9Þ

For conventional TL converters (shown in Fig. 1.6) analyzed in the same manner, the DC conversion ratio is expressed as D

M¼

Vo 2n1 ¼ Vin 1 þ R4Ln2k1T o s

ð2:10Þ

1

Figure 2.4 shows DC conversion ratio versus duty cycle for specifications n1 = 4, Lk1 = 10 lH, Ts = 10 ls, Ro = 2.5 X, and different n2. The figure illustrates that the DC conversion ratio of the HTL–LLC converter is larger than the conventional TL converter. Figure 2.5 shows the DC conversion ratio versus the load resistance for specifications n1 = 4, n2 = 4, Lk = 10 lH, and D = 0.5. As seen, with the increase of the load resistance, the DC conversion ratio increases, which means that the duty cycle loss decrease when the load current decreases, and vice versa. The power distribution ratio of the two transformers is expressed as g¼

PTr1 ðVin =2n1 ÞDeff ILf 2n2 Deff ¼ ¼ PTr2 ðVin =4n2 Þð1  Deff ÞILf n1 ð1  Deff Þ

ð2:11Þ

Hybrid Phase-Shift-Controlled Three-Level and …

2

Fig. 2.4 DC conversion ratio versus duty cycle

DC conversion ratio M

30

HTL-LLC converter with n2=3 HTL-LLC converter with n2=4

HTL-LLC converter with n2=5 HTL-LLC converter with n2=8 Conventional TL converter Duty cycle D

DC conversion ratio

Fig. 2.5 DC conversion ratio versus the load resistance

Load resistance Ro (Ω)

According to (2.7) and (2.11), the power distribution ratio is rewritten as g¼

4n2 M  1 1  2n1 M

ð2:12Þ

Figure 2.6 shows the load power percentage of the two transformers and the duty cycle versus input voltage with specifications Vin = 500–600 V, Vo = 50 V, n1 = 4, n2 = 4, Lk = 10 lH, and Ro = 2.5 X. The two solid lines are the load power percentage of the two transformers, and the dashed line is the duty cycle of the converter. For constant output voltage, the duty cycle decreases with the increase of the input voltage. Meanwhile, the LLC transformer undergoes more load power and the TL transformer undergoes less power, as the duty cycle decreases.

31 0.8

TL transformer

0.7 0.6 0.5

Duty cycle 0.4

LLC transformer

Duty cycle D

Percentage of load power (%)

2.2 Analysis of the HTL–LLC Converter

0.3 0.2

Vin (V) Fig. 2.6 Load distribution between the two transformers and the duty cycle with different input voltages

2.2.2

Power Losses of the Active Switch

The active switch QR works as a controlled rectifier. If the active switch QR is replaced by a diode, the key waveforms of the converter are the same as that shown in Fig. 2.2. However, the voltage drop across the diode causes larger conduction loss especially in low output voltage and high output current conditions. After the output current flows through the body diode of QR, QR is turned on with ZVS. Due to the ZVS of QR, the switching loss is negligible. By using low voltage MOSFETs, the voltage drop is much lower than the diode. Therefore, the conduction loss is dramatically reduced.

2.2.3

ZVS Condition of Switches

In order to achieve ZVS for leading switches, the primary winding currents of the transformer should make their junction capacitor voltage to reach zero before the switch is turned on. In this working stage, the primary current is reflected from the energy stored in the output filter inductor, which is similar to the conventional HB TL converter. Conventionally, the output filter is large enough to achieve ZVS even at light loads. For the conventional TL DC–DC converter, the ZVS of lagging switches is achieved by the energy stored in the leakage inductor. For the HTL–LLC converter, the ZVS of lagging switches is achieved by the energy stored in the magnetizing inductor of Tr2. Taking Stage 1 for example, in order to achieve ZVS for lagging switches, vc2 should reach zero within the dead time, so the ZVS condition derived form (2.3) can be expressed as the following.

32

2

vC2 ¼

Hybrid Phase-Shift-Controlled Three-Level and …

Vin Im2 Vin Vin Ts   sin xm tdead ¼ sin xm tdead  0 2 2Cxm 2 32Lm2 Cxm

ð2:13Þ

Therefore, the magnetizing inductor Lm2 for the ZVS condition should be selected as follows: Lm2 

Ts sin xm tdead 16Cxm

ð2:14Þ

where tdead is the dead time between Q2 and Q3. The ZVS condition of the lagging switches is independent of the load. With the aid of the magnetizing inductor of the LLC transformer, the ZVS of lagging switches can be achieved within a wide load range.

2.2.4

Filter Inductor and Current Ripple

For conventional TL DC–DC converter, the rectifier voltage vrec is zero during the freewheeling period, so the voltage across the filter inductor is −Vo. Therefore, the current ripple of the filter inductor DiLf c is expressed as DiLf

c

¼

Vin ð1  DÞDTs 4n1 Lf

ð2:15Þ

As seen in Fig. 2.7, for the HTL–LLC converter, vrec is equal to VLLC during the freewheeling period, so the voltage across the filter inductor is VLLC − Vo. The current ripple of the filter inductor for the HTL–LLC converter is expressed as

Fig. 2.7 Idealized rectifier voltage vrec a conventional TL converter b HTL–LLC converter

(a)

Vin/2n1

vrec

Vo

t (b)

Vin/2n1 VLLC

vrec

Vo

t

2.2 Analysis of the HTL–LLC Converter

DiLf ¼

33

h i 1 Vin 1  D  ð1DÞn DTs 2n2 4n1 Lf

ð2:16Þ

As seen in both (2.15) and (2.16), with the same duty cycle, the current ripple of the HTL–LLC converter is less than the conventional TL converter. For the desired output current ripple DILf = 0.5 A and specifications n1 = 4, n2 = 4.5, Ts = 10 ls, Ro = 2.5 X, and Vo = 50 V, the output filter inductance as the function of input voltages is shown in Fig. 2.8. As seen in Fig. 2.8, compared with the conventional TL converter, the filter inductance of the HTL–LLC converter is dramatically reduced. Furthermore, the filter size and copper loss of the inductor can be reduced.

2.2.5

Current Stress of the Primary Semiconductors

The primary currents of the transformers for the conventional TL converter and HTL–LLC converter are shown in Fig. 2.9a and b. Figure 2.9c shows the currents of the primary semiconductors. As seen in Fig. 2.9a, ignoring the duty cycle loss and output current ripple, the primary winding rms current of the conventional rms HB TL DC–DC converter Ipr1 c can be expressed as rms Ipr1

c



Vo n1 Ro

ð2:17Þ

Therefore, the rms current of the leading switches Q1 and Q4 is approximately qffiffiffi Vo pffiffiffiffiffiffiffiffiffi D rms evaluated as Ipr1 c 2  n1 Ro n1 M . Furthermore, the rms current of the lagging .pffiffiffi rms 2. The current freewheels through the switches Q2 and Q3 is expressed as Ipr1 c

Fig. 2.8 Filter inductance as the function of input voltage for the desired current ripple

L f (μ H)

clamping diode and lagging switch during the freewheeling interval. Ignoring the

Conventional TL converter

HTL-LLC converter

V in (V)

34

2

Hybrid Phase-Shift-Controlled Three-Level and …

(a)

(b)

(c)

Fig. 2.9 Primary winding current of the transformers and the currents of the primary semiconductors a conventional TL converter, b HTL–LLC converter, c currents of the primary semiconductors

2.2 Analysis of the HTL–LLC Converter

35

output current ripple and duty cycle loss, the rms current of the primary clamping diodes for conventional TL converter is expressed as

irms D1;D2

conv

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Z Ts  rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffi  u1 2 Vo 2 Vo 1D Vo 1 t  n1 M ¼ dt ¼  Ts DT2s n1 Ro 2 n1 R o n1 Ro 2

ð2:18Þ

As seen in Fig. 2.9b and c, when the TL transformer transfers power to the output, the current flowing through the leading switch is approximately equal to Vo n1 Ro . During the Stage 5–8, the current flows through the leading switch and clamping diode  . to charge the capacitor Css, and the current is approximately equal to

Vo Ro

VLLC

Vin 2

¼ 2nV2oRo . Therefore, ignoring the output current ripple and duty

cycle loss, the rms current of the leading switches for the HTL–LLC converter is approximately evaluated as irms Q1;Q4

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u  !   Z Ts  u 1 Z DT2s  Vo 2 2 Vo 2 Vo 1 1 1 t ¼ dt þ dt ¼ þ  D Ts n1 Ro Ro 8n22 2n21 8n22 0 DT2s 2n2 Ro sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi   Vo 1 1 1 4n1 n2 M  n1 þ   Ro 8n22 2n2  n1 2n21 8n22

ð2:19Þ The rms current of the clamping diodes is equal to

irms D1;D2

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Z Ts  rffiffiffiffiffiffiffiffiffiffiffiffi  u1 2 Vo 2 Vo 1D Vo 1 4n1 n2 M  n1 t  ¼ dt ¼  T Ts D 2s 2n2 Ro 2 2n2 Ro 2n2 Ro 2 2ð2n2  n1 Þ ð2:20Þ

In terms of [10], the primary rms current of Tr2 is expressed as rms Ipr2

Vin ¼ 32n22 Re

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2n42 Ts2 R2e þ 8p2 L2m2

ð2:21Þ

where Re = Ro/(1 − D). During the Stage 3–Stage 8, the primary winding current of Tr2 is expressed as ipr2 ðtÞ ¼  where / ¼  arcsin

pVffiffiin Ts rms 16 2Lm2 Ipr2

pffiffiffi rms 2Ipr2 sin½2pfr ðt  t2 Þ þ /

ð2:22Þ

 . Therefore, the rms current of the lagging

switches for the HTL–LLC converter is evaluated as

36

2

irms Q2;Q3

Hybrid Phase-Shift-Controlled Three-Level and …

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi #ffi u "Z DTs  2 Z Ts u1 2 2   Vo 2 ¼t þ ipr2 ðtÞ dt þ ipr2 ðtÞ dt Ts Ts 0 n1 Ro D2 vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2 u pffiffiffi rms u 2 rms Ipr2 2Vo Ipr2 ½cosðpD þ /Þ  cosð/Þ t Vo D  þ ¼ pn1 Ro 2 2n21 R2o vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2ffi u pffiffiffi rms u 2 rms Ipr2 2Vo Ipr2 ½cosðpD þ /Þ  cosð/Þ tVo ð4n1 n2 M  n1 Þ  þ  pn1 Ro 2 2n21 R2o ð2n2  n1 Þ ð2:23Þ

The rms current of the primary semiconductors is associated with the turns ratio of the transformers. In order to minimize the conduction loss, the turns ratio of the transformer should be optimum designed. The detailed turns ratio design and conduction loss are analyzed in Sect. 2.3.3.

2.2.6

Voltage Stress of the Secondary Diodes

The equivalent circuit of the secondary side in Stage 4 is shown in Fig. 2.10, where CR is the junction capacitance of the active switch. Output filter inductor is large enough, so the output filter inductor current is regarded as a current source. The initial state in this stage is vCR(0) = 0, iTL(0) = ILf, and iLLC(0) = 0. vCR(t), iTL(t), and iLLC(t) are expressed as 

 Vin Vin 1 iTL ðtÞ ¼  sinðxn ðt  t3 ÞÞ þ ILf 2 2n1 4n2 n1 Lk1 xn   Vin Vin 1 iLLC ðtÞ ¼   sinðxn ðt  t3 ÞÞ 2 2n1 4n2 n1 Lk1 xn   Vin Vin vCR ðtÞ ¼  ½1  cosðxn ðt  t3 ÞÞ 2n1 4n2

ð2:24Þ

n12 Lk1 iTL

Fig. 2.10 Equivalent circuit of the secondary side in Stage 4

vCR Vin 2n1

Vin 4n2

CQR iLLC

ILf

2.2 Analysis of the HTL–LLC Converter

37

1 ffi. Therefore, ignoring the reverse recovery of the body diode, where xn ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffi n21 Lk1 CQR  Vin the maximum voltage of the active switch QR is equal to Vnin1  2n . The maximum 2

voltage over the diodes DR1 and DR2 is expressed as vDR1;DR2

max

¼ 2ðvCR

max

þ VLLC Þ ¼

2Vin Vin  n1 2n2

ð2:25Þ

Moreover, the maximum voltage of the diodes DR3 and DR4 is equal to Vin 2VLLC ¼ 2n . In terms of (2.24), in order to reduce the ringing of the output diode, 2 the junction capacitance of the active switch QR should be small enough. For conventional TL DC–DC converter analyzed in the same manner, the maximum voltage at the rectifier output is expressed as vrec max ¼ Vnin1 . Therefore, the maximum voltage of the diodes DR1 and DR2 for conventional TL converter is equal to 2vrec max ¼ 2Vn1in , which is larger than that of the HTL–LLC converter.

2.3

Design Considerations

This section introduces a design example of the HTL–LLC converter with 550– 600 V input voltage and 50 V/20 A output. Therefore, the rated load resistance is 2.5 X. A switching frequency of 100 kHz is adopted.

2.3.1

Turns Ratio of the Two Transformers

In order to design the two transformers, the power ratio of the two transformers should be chosen to the desired value. The power ratio can be designed within a range of ½gmin ; gmax . As seen from (2.12), with the increase of the DC conversion ratio M, the power ratio g increases. Therefore, gmin is related with the minimum DC conversion ratio Mmin, and gmax is related with the maximum DC conversion ratio Mmax. They are given as the following. 8 4n2 Mmin 1 < gmin ¼ 12n 1 Mmin ð2:26Þ 4n M : g ¼ 2 max 1 max 12n1 Mmax Rearranging (2.26), the turns ratio of the two transformers is written by 8 max Mmax gmin þ Mmin Mmax < n1 ¼ Mmin g2M max Mmin ðgmax gmin Þ : n ¼ ðMmax Mmin Þgmax gmin þ Mmax gmax Mmin gmin 2 4Mmax Mmin ðg g Þ max

min

ð2:27Þ

38

2

Hybrid Phase-Shift-Controlled Three-Level and …

According to the specifications shown in this section, the maximum DC con50 version ratio is Mmax ¼ VinVomin ¼ 550 ¼ 0:0909, and the minimum DC conversion 50 ratio is Mmin ¼ VinVomax ¼ 600 ¼ 0:0833. In this chapter, the power ratio distribution of the two transformers is desired to be approximately 2. Therefore, the maximum power ratio of the two transformers gmax is designed to be 2.33, when the TL transformer supplies 70% load power and the LLC transformer supplies 30% load power. The minimum power ratio of the two transformers gmin is designed to be 1.5, when the TL transformer supplies 60% load power and the LLC transformer supplies 40% load power. Then, the turns ratio of the two transformer obtained from (2.27) is expressed as

8  1:5 þ 0:08330:0909 ¼ 3:99 < n1 ¼ 0:083322:330:0909 0:0833  0:0909  ð2:331:5Þ : n ¼ ð0:09090:0833Þ  1:5  2:33 þ 0:0909  2:330:0833  1:5 ¼ 4:51 2 4  0:0833  0:0909  ð2:331:5Þ

ð2:28Þ

Consequently, the turns ratio of the two transformers is chosen as n1 = 4 and n2 = 4.5. At minimum input voltage, the effective duty cycle in light of (2.7) is 0.51. At the maximum input voltage, the effective duty cycle is 0.4.

2.3.2

Magnetizing Inductance of the LLC Transformer

Fig. 2.11 Magnetizing inductance of Tr2 versus the leakage inductance of Tr1

Lm2(μH)

With the specification of C = 180 pF, Ts = 10 ls and tdead = 100 ns, the magnetizing inductance of Tr2 versus the leakage inductance Lk1 in terms of (2.14) is shown in Fig. 2.11. As seen, with the increase of Lk1, the magnetizing inductance Lm2 increases. In this case, the magnetizing current of Tr2 can be reduced, and the circulating current can be reduced. However, larger Lk1 causes larger duty cycle

Hard switching region

ZVS region

Lk1(μH)

2.3 Design Considerations

39

loss. Therefore, there is a trade-off between the duty cycle loss and circulating current for the ZVS of the lagging switches. In this chapter, the leakage inductance Lk1 is chosen as 10 lH. Therefore, the ZVS condition of lagging switches is Lm2  207 lH. Eventually, the magnetizing inductor Lm2 is designed as 200 lH.

2.3.3

Current Stress Comparison of the Primary Semiconductors

Current stress of the switches in per unit (p.u.)

According to the turns ratio of the transformers and magnetizing inductance of Tr2 in this section, the rms currents of the switches in per unit as the function of the input voltage in terms of (2.19) and (2.23) are shown in Fig. 2.12. As seen in Fig. 2.12, the current stress of the HTL–LLC converter is much lower than the conventional TL converter. Equation (2.19) indicates that the rms current of the leading switches is associated with the duty cycle. Figure 2.4 shows that the duty cycle of the HTL–LLC converter is much lower than that of the conventional TL converter for the same DC conversion ratio. Therefore, the rms current of the leading switches can be reduced dramatically. Figure 2.9a illustrates the circulating current of the conventional TL converter. During the freewheeling period, the lagging switches have to handle large circulating currents, which causes large conduction loss. Figure 2.9b illustrates that ipr1 is reset to zero when the output inductor works in the freewheeling period, leading to the reduction of the rms current for lagging switches. Moreover, during the freewheeling period, the LLC circuit still transfers energy to the output. Only the magnetizing inductor current of

Lagging switches of the conventional TL converter Leading switches of the conventional TL converter

Lagging switches of the HTL-LLC converter Leading switches of the HTL-LLC converter

Vin (V)

Fig. 2.12 Rms current of the switches in per unit as the function of the input voltage

40

2

Hybrid Phase-Shift-Controlled Three-Level and …

Tr2 freewheels at the primary side. Therefore, the HTL–LLC converter works in low conduction loss, achieving high efficiency. Figure 2.13 shows the rms current of the primary clamping diodes in per unit as the function of the input voltage. For the turns ratio of the transformers and the magnetizing inductance of Tr2 designed in this section, the conduction loss of the clamping diodes is less than the conventional TL converter.

2.3.4

Resonant Capacitance Cr

The voltage across the resonant capacitor is expressed as vCr1 vCr2

pffiffiffi rms 2Ipr2 Vin ipr2 ðtÞdt ¼  cos½2pfr ðt  t2 Þ þ / 4 4pfr Cr p ffiffi ffi Z rms 2Ipr2 Vin 1 Vin ipr2 ðtÞdt ¼  þ ¼ cos½2pfr ðt  t2 Þ þ / 2Cr 4 4 4pfr Cr Vin 1 þ ¼ 2Cr 4

Z

ð2:29Þ

Therefore, the maximum voltage of the resonant capacitor is expressed as VCr

max

pffiffiffi rms 2Ipr2 Vin þ ¼ 4 4pfr Cr

ð2:30Þ

Current stress of the primary clamping diode in per unit (p.u.)

With the increase of the resonant capacitor, the maximum voltage of the capacitor can be reduced. When VCr_max is desired to be less than 250 V, Cr should be larger than 21 nF. Then, the resonant capacitance Cr is chosen as 30 nF in this chapter.

Conventional TL converter

Proposed converter

Vin (V) Fig. 2.13 Rms current of the switches in per unit as the function of the input voltage

2.3 Design Considerations

2.3.5

41

Resonant Inductance Lr

The resonant frequency is equal to the switching frequency. Therefore, the resonant inductance Lr is equal to Lr ¼

1 ¼ 42:26ðlHÞ 8p2 fr2 Cr

ð2:31Þ

Then, Lr is chosen as 43 lH.

2.3.6

Selection of the Secondary Semiconductors

According to the analyses in Sect. 2.2.6, the voltage stress of the DR1 and DR2 is 2V V 600 equal to inn1 max  in2n2max ¼ 2600 4  24:5 ¼ 233ðVÞ. The voltage stress of QR is equal to

Vin

Vin max 600 2n2 ¼ 4 Vin max 600 4n2 ¼ 44:5 ¼

max

n1



600  24:5 ¼ 83ðVÞ. The voltage stress of DR3 and DR4

is equal to 33:5ðVÞ. The current stress of all the secondary semiconductors can be designed no less than 20 A. In terms of the voltage stress and current stress, the secondary semiconductors can be determined.

2.4

Experimental Verifications

In order to verify the performance of the HTL–LLC converter, a 1 kW prototype is built. The specifications of the prototype are given as follows: Vin = 550–600 V, Vo = 50 V, n1 = 4, n2 = 4.5, Cd1 = Cd2 = Css = 20 lF, C = 180 pF, Lr = 43 lH, Cr = 30 nF, Lm2 = 200 lH, Lf = 110 lH, Co = 200 lF, Cos = 30 lF. Therefore, the resonant frequency of the LLC circuit is 99.1 kHz. The switching frequency is 100 kHz. Two pieces of FQP8N60C in parallel are selected as each primary switch. The primary clamping diode is DSEP12-12A. The active switch is FDP150N10. The rectifiers DR1 and DR2 are two pieces of MBR20200CT. Two RC snubber circuits are parallel connected with DR1 and DR2. The snubber circuit is composed of a 400 X resistor in series with a 1 nF capacitor. The rectifiers DR3 and DR4 are DSSK 20-015A. The experimental results are shown in Figs. 2.14, 2.15, 2.16, 2.17. Figure 2.14 shows the key waveforms at different input voltages and output power, where P is the output power. Figure 2.14a shows the experimental waveforms when Vin = 550 V and P = 1000 W. Figure 2.14b shows the experimental waveforms when Vin = 600 V and P = 1000 W. With the increase of the input

42 Fig. 2.14 Measured key waveform of the HTL–LLC converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 200 W

2

Hybrid Phase-Shift-Controlled Three-Level and …

(a) vAB 250V/div

ipr1 ipr2

5A/div

vrec

2A/div 20V/div

Time base:2μs/div

(b) vAB ipr1 ipr2 vrec

250V/div 5A/div 2A/div 20V/div

Time base:2μs/div

(c) vAB ipr1

250V/div 2A/div

ipr2 vrec

2A/div 20V/div

Time base:2μs/div

voltage, the duty cycle of the HTL–LLC converter decreases, while the amplitude of ipr2 increases. It demonstrates that the LLC circuit transfers more power to the load as the input voltage increases. Figure 2.14c shows the experimental waveforms when Vin = 550 V and P = 200 W. The current amplitudes of ipr1 and ipr2 are both reduced as the output power decreases. As expected, the currents ipr1 for the three cases mentioned previously are all reset to zero during the freewheeling period, which minimizes the conduction loss of the primary circuit. Figure 2.15 shows current of Q4, current of the clamping diode D1, and gate signal and drain-source voltage of switch Q4. Figure 2.15a shows the ZVS operation of the leading switches at heavy loads. Figure 2.15b shows the ZVS operation

2.4 Experimental Verifications Fig. 2.15 Current of Q4, primary current of the clamping diode D1, and gate signal and drain-source voltage of switch Q4, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W

43

(a)

Time base:2μs/div

iQ4 iD1

vds4

ZVS vgs4

5A/div 2A/div 100V/div 10V/div

(b) Time base:2μs/div

iQ4 2A/div iD1

vds4

ZVS vgs4

2A/div 100V/div 10V/div

Fig. 2.16 Current of Q4, current of Tr2, and gate signal and drain-source voltage of switch Q3 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W

(a)

(b)

44

2

Fig. 2.17 Gate signal and drain-source voltage of QR at Vin = 550 V and P = 1000 W

Hybrid Phase-Shift-Controlled Three-Level and …

Time base:2μs/div

ipr1 ipr2 vgs_QR

vds_QR

ZVS

5A/div 2A/div 5V/div 25V/div

Efficiency

of the leading switches at light loads. Before Q4 is turned on, the current of Q4 is negative and the current flows through its body diode. Figure 2.16 shows current of Q3, primary current of Tr2, and gate signal and drain-source voltage of switch Q3. Figure 2.16a shows the ZVS operation of the lagging switches at the heavy load. Figure 2.16b highlights the ZVS operation of the lagging switches at the light load. As seen in the experimental results, before Q3 is turned on, the current of Q3 is negative and the current flows through its body diode. Therefore, ZVS for all the switches is achieved over the wide load range. Figure 2.17 highlights the ZVS operation of active switch QR. The measured efficiency curves for the HTL–LLC converter, the conventional TL converter, and the HTL–LLC converter replacing the active switch to a diode are shown in Fig. 2.18. Compared with the conventional TL converter, the efficiency of the HTL–LLC converter is greatly improved. At Vin = 600 V, the maximum improvement at light loads is more than 3.5%, and the improvement at heavy loads is more than 3%. For the HTL–LLC converter replacing the active switch to a diode, the efficiency is not effectively improved. Although the ZVS of the switches is achieved and circulating current is reduced at the primary side, the replaced diode causes large conduction loss especially at heavy loads. As the input voltage

Power (W)

Fig. 2.18 Efficiency for the HTL–LLC converter, the conventional TL converter, and the HTL– LLC converter replacing the active switch to a diode

2.4 Experimental Verifications

45

increases, more power is transferred to the load from the LLC circuit. More conduction loss is generated by using the replaced diode. Therefore, when the input voltage increases, the efficiency of the HTL–LLC converter with the replaced diode decreases.

2.5

Conclusion

In this chapter, a hybrid TL and LLC converter by sharing the lagging switches is introduced for higher efficiency. Since the switches only withstand half of the input voltage, the HTL–LLC converter is suitable for high input voltage applications. The LLC circuit can extend the ZVS range of the lagging switches. The output current ripple and circulating current of the primary side are reduced. Connecting the hybrid TL output and LLC by the active switch based on the presented switching sequence can significantly increase the conversion efficiency further during the wide load range. The good performance of the HTL–LLC converter and design method has been verified by a 1 kW experimental prototype.

References 1. Liu F, Ruan X (2007) ZVS combined three-level converter—a topology suitable for high input voltage with wide range applications. IEEE Trans Ind Electron 54(2):1061–1072 2. Liu F, Yan J, Ruan X (2010) Zero-voltage and zero-current-switching PWM combined three-level DC/DC converter. IEEE Trans Ind Electron 57(5):1644–1654 3. Kim D, Kim J, Moon G (2013) A three-level converter with reduced filter size using two transformers and flying capacitors. IEEE Trans Power Electron 28(1):2140–2150 4. Zhang Y, Sun J, Wang Y (2014) Hybrid boost three-level DC–DC converter with high voltage gain for photovoltaic generation systems. IEEE Trans Power Electron 28(8): 3659–3664 5. Kim Y, Lee I, Cho I, Moon G (2014) Hybrid dual full-bridge DC–DC converter with reduced circulating current, output filter, and conduction loss of rectifier stage for RF power generator application. IEEE Trans Power Electron 29(3):1069–1081 6. Yu W, Lai J, Lai W, Wan H (2012) Hybrid resonant and PWM converter with high efficiency and full soft-switching range. IEEE Trans Power Electron 27(12):4925–4933 7. Gu B, Lin C, Chen B, Dominic J, Lai J (2013) Zero-voltage-switching PWM resonant full-bridge converter with minimized circulating losses and minimal voltage stresses of bridge rectifiers for electric vehicle battery chargers. IEEE Trans Power Electron 28(10):4925–4933 8. Liu F, Hu G, Ruan X (2013) Three-phase three-level DC/DC converter for high input voltage and high-power applications adopting symmetrical duty cycle control. IEEE Trans Power Electron 29(1):56–65 9. Ivensky G, Bronshtein S, Abramovitz A (2011) Approximate analysis of resonant LLC DC– DC converter. IEEE Trans Power Electron 26(11):3274–3284 10. Lu B, Liu W, Liang Y, Lee FC, van Wyk JD (2006) Optimal design methodology for LLC resonant converter. In: IEEE applied power electronics conference and exposition, March 2006, pp 19–23

Chapter 3

Hybrid Three-Level and Half-Bridge DC–DC Converter with Reduced Circulating Loss and Output Filter Inductance

Abstract A hybrid three-level (TL) and half-bridge (HB) DC–DC converter is introduced in this chapter. The TL DC–DC converter and HB converter have their own transformers, respectively. Compared with conventional TL DC–DC converters, the presented one has no additional switch at the primary side of the transformer, where the TL converter shares the lagging switches with the HB converter. In order to reduce the circulating current in the primary side, a blocking capacitor is used to reset the primary winding current of the TL converter. Moreover, the rectifier stage is composed of four diodes in the center-tap rectification, forcing the circulating current at the primary side to stay zero during the freewheeling period. The magnetizing inductor of the HB transformer can extend the ZVS operation range of the lagging switches even at light loads. Furthermore, the presented converter can reduce the output filter inductance. Due to the advantages mentioned above, the efficiency of the converter is improved dramatically. The features and design guidelines of the presented converter are given in the chapter. Finally, the performance of the converter is verified by a 1 kW experimental prototype. Keywords Three level switching

3.1


Phase shift
Reduced circulating current
Zero-voltage

Hybrid Three-Level Plus Half-Bridge DC–DC Converter

For high power density and low circulating current, hybrid TL DC–DC converters with more than one transformer have been proposed [1–5]. The transformers are connected in series at the primary or secondary side to reduce the voltage across the filter inductor during the freewheeling period. However, large circulating current still freewheels at the primary side of the converter [1–4]. In order to solve this issue, a blocking capacitor is used to reset the primary circulating current in the hybrid converter [5]. Furthermore, a two diode should be connected in series with © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_3

47

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

48

the lagging switches to block the reverse flowing path. Therefore, the converter has to work in ZVZCS mode instead of ZVS mode. In this chapter, a hybrid TL and HB (HTL-HB) DC–DC converter with reduced circulating current and output filter inductance is introduced. A blocking capacitor is used to decay the primary circulating current. The lagging leg switches can also achieve ZVS by using the magnetizing inductor current of the HB transformer. At the secondary side of the transformer, a novel rectifier circuit configuration composed of four diodes is introduced, which forces the circulating current decreasing and equaling to zero instead of flowing to the opposite direction during the freewheeling period. Figure 3.1 shows the circuit configuration for the HTL-HB converter, which is composed of a TL DC–DC converter and an HB DC–DC converter. The divided capacitors Cd1, Cd2 and the flying capacitor Css1 and Css2 are large enough to be treated as voltage sources, i.e., VCd1 ¼ VCd2 ¼ Vin =2, VCss1 ¼ VCss2 ¼ Vin =4. The output voltage regulation is implemented by the phase-shift manner. Q1 and Q4 are leading switches; Q2 and Q3 are lagging switches. The TL converter shares the lagging switches Q2 and Q3 with the HB DC–DC converter. C1–C4 are junction capacitors of the switches, and C1 = C2 = C3 = C4 = C. Tr1 is the transformer of the TL converter, and Tr2 is the transformer of the HB converter. The turns ratio of the two transformers Tr1 and Tr2 are n1:1:1 and n2:1:1, respectively. Lk1 and Lk2 are the leakage inductors of Tr1 and Tr2. The magnetizing inductor of Tr1 is designed large enough, thus the magnetizing current during the switching period can be ignored. Lm2 is the magnetizing inductor of Tr2. Cb is the blocking capacitor that is used to decay the primary current of Tr1 and reduce the circulating current. Figure 3.2 shows the key waveforms of the HTL-HB converter. There are eight working stages in each half-switching period. Stage 1 ([t0, t1]) (Fig. 3.3a): Prior to t0, Q1 and Q3 are on, and Q2 and Q4 are off. The primary current in Tr1 stays at zero. The primary current in Tr2 is negative. The output filter inductor current flows through DR3. At time t0, Q3 is turned off. The

Cd1

Vin

B

Cd2

D1

Q1

C1

Q2

C2 Css1 Lm2 ip2

ip1 Cb Lk1

A

Tr1 D2

Q3

Q4 Fig. 3.1 HTL-HB DC–DC converter

Tr2

DR1

Lk2 C

C3 Css2 C4

Tr1 DR2 Tr2

DR3

Tr1 DR4

iLf Lf vrec Co

Ro V o

3.1 Hybrid Three-Level Plus Half-Bridge DC–DC Converter

49

Fig. 3.2 Key waveforms of the HTL-HB converter

voltage across the blocking capacitor is negative. The primary winding current in transformer Tr2, including the current reflected from the output current and the magnetizing current in Tr2, starts to charge and discharge the junction capacitors of Q3 and Q2, respectively. The primary winding current of Tr1 starts to increase. Q1 and D2 conduct to charge the flying capacitors Css1 and Css2. Since DR1 and DR3 are forward biased and DR2 and DR4 are reverse biased, the current in DR1 starts to increase and the current in DR3 starts to decrease. The amplitude of the magnetizing current Im2 is expressed as Im2 ¼

Vin Ts 16Lm2

ð3:1Þ

where Ts is the switching period. Stage 2 ([t1, t2]) (Fig. 3.3b): At time t1, the drain-source voltage of Q2 reaches zero, and ip2 flows through the body diode of Q2. ip1 and ip2 both increase linearly. The blocking capacitor voltage vCb is charged by ip1. Q1 and D2 still conduct to charge the flying capacitors Css1 and Css2. The output filter inductor current iLf freewheels through DR1 and DR3. The current in DR1 continues to increase, and the current in DR3 continues to decrease. ip1 and ip2 in this stage are expressed as

50 Fig. 3.3 Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8]

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

(a)

Q1 Cd1

Vin

B

Cd2

D1

(b) Cd1

Vin

B

Cd2

B

Cd2

D2

D1

D2

Vin

B

Cd2

Q1

C1

A Q3

Tr2

Q1

C1

Q2 Cb Lk1

A Q3

C4

Q1

C1

Q2 ip1 Cb Lk1

A

Q4

Lk2 C

Tr1

Tr1 DR2 Tr2

iLf Lf vrec Co

Ro Vo

DR3

Tr1

Tr1 DR2 Tr2

iLf Lf vrec Co

Ro Vo

DR3

Tr1 DR4

DR1

Lk2 C

C3 Css2 C4

Ro Vo

DR3

DR1

C2 Css1 Lm2 Tr2

Tr2

Lf vrec Co

DR4

C3 Css2

Q4

Q3

Lk2 C

C2 Css1 Lm2 Tr2

DR2

DR1

C3 Css2 C4

Tr1

iLf

DR4

C2 Css1 Lm2

Q4

Tr1

Lk2 C

C3 Css2

D1

D2

Tr2

C4

Tr1

DR1

C2 Css1 Lm2

Q4

Tr1

(d) Cd1

Q3

Q2 ip1 Cb Lk1

ip1 Vin

A

D1

(c) Cd1

Q2 Cb Lk1

Tr1 D2

C1

Tr1 DR2 Tr2

DR3

Tr1 DR4

iLf Lf vrec Co

Ro Vo

3.1 Hybrid Three-Level Plus Half-Bridge DC–DC Converter

(e)

Q1 Cd1

D1 ip1

Vin

B

Vin

B

Cd2

A Q3

(f) Cd1

Q2 Cb Lk1

Tr1 D2

Cd2

C1

C4

Q1

C1

Q2 ip1 Cb Lk1

A Q3

D2

Tr2

Lk2 C

C3 Css2

D1

Tr1

C2 Css1 Lm2

Q4

Tr1

DR1

C4

Q1

C1

Lf vrec Co

Ro Vo

DR3

Tr1

DR1

Lk2 C

C3 Css2

Q4

Tr2

iLf

DR4

C2 Css1 Lm2 Tr2

DR2

51

Tr1 DR2 Tr2

iLf Lf vrec Co

Ro Vo

DR3

Tr1 DR4

(g) Cd1

Vin

B

Cd2

D1 ip1

Q2 Cb Lk1

A

Tr1 D2

DR1

C2 Css1 Lm2 Tr2

Lk2 C

Q3

C3 Css2

Q4

C4

Q1

C1

Tr1 DR2 Tr2

iLf Lf vrec Co

Ro Vo

DR3

Tr1 DR4

(h) Cd1

Vin

B

Cd2

D1

Q2 ip1 Cb Lk1

A

Tr1 D2

Q3 Q4

Fig. 3.3 (continued)

DR1

C2 Css1 Lm2 Tr2

Lk2 C

C3 Css2 C4

Tr1 DR2 Tr2

DR3

Tr1 DR4

iLf Lf vrec Co

Ro Vo

52

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

Vin  2vCb ðtÞ ðt  t1 Þ 2Lk1 Vin ip2 ðtÞ ¼ ip2 ðt1 Þ þ ðt  t1 Þ 4Lk2

ip1 ðtÞ ¼ ip1 ðt1 Þ þ

ð3:2Þ

where vCb(t) is the voltage across the blocking capacitor. Stage 3 ([t2, t3]) (Fig. 3.3c): At time t2, Q2 is switched on with ZVS. iLf keeps on freewheeling through DR1 and DR3. ip1 and ip2 still increase linearly as expressed in (3.2). Stage 4 ([t3, t4]) (Fig. 3.3d): At time t3, DR3 is reverse biased and all the filter inductor current flow through DR1. The TL transformer and the HB transformer transfer energy to the output. The secondary winding current in Tr2 is equal to that in Tr1. Ignoring the output current ripple, vCb is linearly charged by ip1. ip1, ip2 and vrec in this stage is expressed as Vin =2  vCb ðt  t3 Þ Vin þ n1 4n2 ILf ip1 ðtÞ ¼ n1 ILf Vin ip2 ðtÞ ¼  Im2 þ ðt  t0 Þ n2 4Lm2

vrec ðtÞ ¼

ð3:3Þ

Stage 5 ([t4, t5]) (Fig. 3.3e): When Q1 is turned off at t4, the voltages across the junction capacitors C1 and C4 are charged and discharged linearly by the energy stored in the output filter inductor Lf. ip1 starts to decrease, so the current in DR1 decreases and the current in DR2 increases. The magnetizing inductor current in Tr2 is still linearly increasing. Stage 6 ([t5, t6]) (Fig. 3.3f): When C1 reaches Vin/2 and C4 reaches zero, the body diode of Q4 is forward biased. ip1 freewheels through D1 and Q2. The voltage across Cb is applied to the primary winding of Tr1, which forces ip1 to decrease rapidly. The current in DR1 continues decreasing and the current in DR2 continues increasing. Stage 7 ([t6, t7]) (Fig. 3.3g): At time t6, Q4 is turned on with ZVS. The primary winding current of Tr1 continues decreasing and freewheels through D1 and Q2. The current in DR1 continues reducing and the current in DR2 continues increasing. Stage 8 ([t7, t8]) (Fig. 3.3h): Stage 9 starts when ip1 decays to zero. D1 and Q4 still conduct to charge flying capacitors Css1 and Css2. Then, DR2 carries all the filter inductor current, and DR1 and DR4 are reverse biased. Therefore, the flowing path of the secondary current in Tr1 is blocked. The filter inductor current only can flow through DR2 and the secondary winding of Tr2. Without current flowing in secondary winding of Tr1, the primary winding current in Tr1 keeps zero. The voltage across Cb stays constant in this stage. ip2 and vrec in this stage is expressed as

3.1 Hybrid Three-Level Plus Half-Bridge DC–DC Converter

Vin 4n2 ILf Vin ip2 ðtÞ ¼  Im2 þ ðt  t0 Þ n2 4Lm2

vrec ðtÞ ¼

3.2 3.2.1

53

ð3:4Þ

Analysis of the HTL-HB Converter DC Conversion Ratio

In practice, the voltage across the blocking capacitor is very low. Therefore, in order to simplify the analysis, it can be negligible. Moreover, ignoring the duty cycle loss, the DC conversion ratio of the HTL-HB converter in continuous conduction mode (CCM) can be derived from the volt-second balance for the output filter, which can be written by,



 Vin Vin Vin þ  Vo D þ  Vo ð1  DÞ ¼ 0 2n1 4n2 4n2

ð3:5Þ

where D is the duty cycle. Based on (3.5), the DC conversion ratio of the converter is expressed as M¼

Vo D 1 ¼ þ Vin 2n1 4n2

ð3:6Þ

For conventional TL converters, the DC conversion ratio is expressed as M¼

Vo D ¼ Vin 2n

ð3:7Þ

Figure 3.4 shows DC conversion ratio versus duty cycle for different n2 when n1 = 4. The figure illustrates that the DC conversion ratio of the HTL-HB converter is larger than zero. As seen, for different n2, the curves of the conversion ratios are parallel lines. For conventional buck type DC–DC converter, the lowest conversion ratio can reach zero. As seen in (3.6), the lowest conversion ratio for the HTL-HB converter is 1/4n2, which means the lowest conversion ratio is determined by the turns ratio of Tr2. However, for conventional TL DC–DC converter, the gain of the converter can reach zero.

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

54

DC conversion ratio M

HTL-HB converter with n2=4 HTL-HB converter with n2=5

HTL-HB converter with n2=5 HTL-HB converter with n2=8

Duty cycle D

Fig. 3.4 DC conversion ratio versus duty cycle

3.2.2

Voltage of the Blocking Capacitor

During one complete switching period, the time duration during t0 − t3 and t4 − t7 is rather short. Therefore, the maximum voltage across the blocking capacitor is approximately expressed as

vCb

max

1  2Cb

Zt4 t3

ILf DTs ILf dt ¼ n1 4n1 Cb

ð3:8Þ

In terms of (3.8), the maximum voltage of the blocking capacitor is associated with the load current, duty cycle, and the capacitance of Cb. Larger capacitance of Cb can reduce its maximum voltage, but too low voltage can not allow ip1 to be reset to zero. Therefore, Cb should meet the following condition, vCb

max



ILf DTs ILf =n1 \Lk1 4n1 Cb ð1  DÞTs =2

ð3:9Þ

Rewriting (3.9), the maximum value of Cb is expressed as Cb \

Dð1  DÞTs2 8Lk1

ð3:10Þ

Moreover, vCb_max should not be larger than Vin/2, otherwise, the working stage of the converter may become abnormal. The minimum value of Cb should meet the following condition,

3.2 Analysis of the HTL-HB Converter

vCb

max

55



ILf DTs \Vm 4n1 Cb

ð3:11Þ

where Vm is the maximum allowable voltage, which is less than Vin/2. Therefore, the minimum value of Cb is expressed as Cb [

3.2.3

ILf DTs 4n1 Vm

ð3:12Þ

ZVS Condition of Switches

In order to achieve ZVS for leading switches, their junction capacitor voltage should drop to zero before the switch is turned on. In this working stage, the leading switches are charged and discharged by the primary currents in Tr1 and Tr2, which are all reflected from the energy stored in the output filter inductor. Furthermore, the magnetizing inductor current in Tr2 is also an advantage to achieve ZVS of the leading switches. Conventionally, the leading switches are easy to achieve ZVS even at light loads. For the conventional TL DC–DC converter, the ZVS of lagging switches is achieved by the energy stored in the leakage inductor. For the HTL-HB converter, the ZVS for lagging switches is achieved by the primary current in Tr2, which include the energy stored in the leakage inductor and magnetizing inductor of Tr2. At heavy loads, the energy stored in the leakage inductor of Tr2 is large enough to achieve ZVS. However, at light loads, the energy stored in the leakage inductor is too low to achieve ZVS. In this case, the magnetizing inductor current should be large enough to charge and discharge the junction capacitors of the lagging switches. Ignoring the low leakage inductor current of Tr2 at light loads, the equivalent circuit in Stage 2 is shown as the following. According to Fig. 3.5, the following equations are obtained as 8 dip1 Vin > > < vC2 ¼ 2  Lk1 dt vC3 ¼ V2in  vC2 > > : 2C dvC2 ¼ i  I p1 m2 dt

Fig. 3.5 Equivalent circuit in Stage 2 at light loads

ð3:13Þ

Cd1

Lk1

C2 Im2

Css1

C3

Css2

ip1

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

56

Moreover, the initial state in this stage is vC2(0) = Vin/2, vC3(0) = 0, and ip1(0) = 0. Therefore, the primary current in Tr1 and voltages across C2 and C3 are expressed as ip1 ¼ Im2  Im2 cos½xm ðt  t0 Þ Vin Im2 
sin½xm ðt  t0 Þ vC2 ðtÞ ¼ 2 2Cxm Im2 vC3 ðtÞ ¼
sin½xm ðt  t0 Þ 2Cxm

ð3:14Þ

1 ffi where xm ¼ pffiffiffiffiffiffiffiffi . In order to achieve ZVS for the lagging switches, the voltage 2CLk1 across C2 should be discharged to zero within the dead time, which is given by,

Vin Im2 sin xm tdead  2 2Cxm Vin Vin Ts  ¼ sin xm tdead  0 2 32Lm2 Cxm

vC2 ¼

ð3:15Þ

Hence, the magnetizing inductance Lm2 for the ZVS condition should be designed as follows, Lm2 

Ts sin xm tdead 16Cxm

ð3:16Þ

where tdead is the dead time between Q2 and Q3. At light loads, the ZVS condition of the lagging switches is ensured by the magnetizing inductor of Tr2. As seen in (3.16), the ZVS condition is independent of the loads. With the aid of the magnetizing inductor of the Tr2, the ZVS of lagging switches can be ensured within a wide load range.

3.2.4

Current Stress of the Primary Semiconductors

The primary winding currents in the transformers of the conventional TL converter and the HTL-HB converter are shown in Fig. 3.6a and b. Figure 3.6c shows the currents of the primary semiconductors. As seen in Fig. 3.6a, ignoring the duty cycle loss and output current ripple, the primary winding rms current in the conrms ventional TL DC–DC converter Ip1 c can be expressed as rms Ip1 c 

Vo nRo

ð3:17Þ

3.2 Analysis of the HTL-HB Converter

(a)

Q1,Q2 on

57 D1,Q2 on

Q1,Q2 on

ip1

D2,Q3 on

Circulating current

DTs/2

(b)

Q3,Q4 on

D1,Q2 on

Q3,Q4 on

D2,Q3 on

D1,Q2,Q4 on

D1,Q3,Q4 on

D2,Q1,Q3 on

DTs/2

ip2 (c)

iQ1 iQ4 iQ2

D2,Q1,Q3 on

D2,Q1,Q2 on

DTs/2

DTs/2

iQ3 iD1 iD2 Fig. 3.6 Primary winding current of the transformers and the currents of the primary semiconductors a conventional TL converter, b HTL-HB converter, c currents of the primary semiconductors

Therefore, the rms current in leading switches Q1 and Q4 is approximately qffiffiffi pffiffiffiffiffiffiffi Vo rms D evaluated as Ip1 c 2  n1 Ro nM . Furthermore, the rms current of the lagging .pffiffiffi rms switches Q2 and Q3 is expressed as Ipr1 2. The current freewheels through the c clamping diode and lagging switch during the freewheeling interval. Ignoring the output current ripple and duty cycle loss, the rms current in the primary clamping diodes for conventional TL converter is expressed as

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

58

irms D1;D2

conv

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Z Ts
rffiffiffiffiffiffiffiffiffiffiffiffi  u1 2 Vo 2 Vo 1D Vo 1 t  nM ¼ dt ¼  Ts DT2s nRo 2 n1 R o n1 Ro 2

ð3:18Þ

As seen in Fig. 3.6b and c, for the HTL-HB converter, the primary winding current amplitude of Tr1 is equal to Vo =ðn1 Ro Þ. During Stage 5–8, the current flows through the leading switch and clamping diode to  .charge capacitors Css1 and Css2, and the current is approximately equal to

Vo Vin Ro 4n2

Vin 2

¼ 2nV2oRo . Therefore, ignoring

the output current ripple and duty cycle loss, the rms current flowing through the leading switches for the HTL-HB converter is approximately evaluated as

irms Q1;Q4

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u   ! Z Ts
u 1 Z DT2s
Vo 2 Vo 2 Vo 2 t ¼ þ dt þ dt Ts n1 Ro 2n2 Ro 0 DT2s 2n2 Ro sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
 Vo 1 1 1 ¼ þ þ D Ro 8n22 2n21 2n1 n2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

 Vo 1 1 1 n1 þ þ 2n1 M   Ro 8n22 2n2 2n21 2n1 n2

ð3:19Þ

The rms current in the clamping diodes is expressed as irms D1;D2

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  Z Ts
2 1 Vo 2 Vo ¼ dt ¼ pffiffiffi Ts 0 2n2 Ro 2 2n2 Ro

ð3:20Þ

As seen in (3.18), the rms current in the clamping diodes of the conventional TL DC–DC converter is related with the duty cycle and output power. In order to reduce the conduction loss, the duty cycle should be large enough. Comparatively, the rms current in the clamping diodes of the HTL-HB converter is related to the turns ratio of Tr2 and output power. As seen, as n2 increases, the rms current in the clamping diodes decreases. Therefore, in order to reduce the conduction loss, the turns ratio of Tr2 should not be designed too low. If n2 is too low, Tr2 will transfer more power to the load, which may cause more conduction loss. During Stage 1–8, the magnetizing inductor current is expressed as iLm2 ðtÞ ¼ Im2 þ

Vin t 4Lm2

ð3:21Þ

3.2 Analysis of the HTL-HB Converter

59

The rms current in the lagging switches for the HTL-HB converter is evaluated as vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u "Z DTs
  # Z Ts
u1 2 2 Vo Vo 2 Vo 2 t irms ¼ þ iLm2 ðtÞ þ dt þ iLm2 ðtÞ þ dt Q2;Q3 Ts Ts 0 n1 Ro n2 Ro n R 2 o D2 ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi s
 1 1 Vo2 D Vo Vin Ts Dð1  DÞ V2 Vin2 Ts2 ¼ þ  þ 2o 2 þ 2n1 n2 n1 R2o 16Lm2 n1 Ro 2n2 Ro 1536L2m2 ffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

 2

 1 1 n1 Vo n1 n1 Vo Vin Ts Vo2 Vin2 Ts2  þ 2n1 M   2n M  1  2n M þ þ þ 1 1 2n1 n2 2n2 n1 R2o 2n2 2n2 16Lm2 n1 Ro 2n22 R2o 1536L2m2

ð3:22Þ The rms current in the primary semiconductors is related to the turns ratio of the two transformers. In order to minimize conduction loss, the turns ratio of the two transformers should be optimized, which will be discussed in detail in Sect. 3.3.4.

3.2.5

Voltage Stress of the Secondary Diodes and Switch

The equivalent circuit of the secondary side in Stage 4 is shown in Fig. 3.7, where CDR3 and CDR4 are the junction capacitance of DR3 and DR4. Output filter inductor is supposed large enough, so the output filter inductor current can be viewed as a current source. The initial state in this Stage is vDR3(0) = vDR4(0) = 0, is(0) = ILf, and iDR3(0) = iDR4(0) = 0. Assuming CDR3 = CDR4 = CD, vCD4(t), vCD3(t), and is(t) are written by


 Vin Vin þ ½1  cosðxn ðt  t3 ÞÞ n1 2n2
 Vin Vin þ ½1  cosðxn ðt  t3 ÞÞ vDR3 ðtÞ ¼ 2n1 2n2
 Vin Vin 1   sinðxn ðt  t3 ÞÞ þ ILf þ is ðtÞ ¼ n1 2n2 n21 Lk1 þ n22 Lk2 xn

vDR4 ðtÞ ¼

ð3:23Þ

1 ffi. Therefore, ignoring the reverse recovery of the body where xn ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2CD ðn21 Lk1 þ n22 Lk2 Þ diode, the maximum voltage of DR1 and DR4 is equal to 2Vn1in þ Vnin2 , and the maximum

voltage of DR2 and DR3 is equal to Fig. 3.7 Equivalent circuit of the secondary side in Stage 5

Vin n1

þ

Vin n2 .

n12 Lk1

n22 Lk 2

Vin 2n1 Vin 4n2

is CDR4

Vin 4n2

Vin 2n1

vDR4 vDR3

CDR3

ILf

60

3.3

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

Design Considerations

This section introduces a design example of the HTL-HB converter with 550– 600 V input voltage and 50 V/20 A output. Therefore, the rated load resistance is 2.5 X. A switching frequency of 100 kHz is adopted.

3.3.1

Turns Ratio of the Two Transformers

In order to design the two transformers, the power ratio of the two transformers should be chosen to the desired value. As illustrated in Sect. 3.2.4, in order to reduce the conduction loss, Tr2 should not transfer too much power to the load. Therefore, the power ratio of the two transformers is initially selected as 2. At full loads, Tr2 provides approximately 300 W power. Therefore, the turns ratio of Tr2 is expressed as n2 ¼

Vin ILf 550  20 ¼ 9:16 ¼ 4  300 4PTr2

ð3:24Þ

Therefore, the turns ratio of Tr2 is designed as 9:1:1. At the minimum input voltage, the duty cycle of the converter is initially chosen as 0.7. Therefore, in terms of (3.6), the turns ratio of Tr1 is expressed as D 0:7 ¼  50  ¼ 5:54 n2 ¼  1 Vo 2  550  49 2 Vin  4n12

ð3:25Þ

Consequently, the turns ratio of Tr1 is designed as 5.5:1:1. At the minimum input voltage, the effective duty cycle is 0.69. At the maximum input voltage, the effective duty cycle is 0.61. For the conventional TL DC–DC operating within the same duty cycle range, the turns ratio of the transformer can be expressed as 0:7550 in n ¼ DV 2Vo ¼ 250 ¼ 3:85. Therefore, it can be selected as 3.8:1:1.

3.3.2

Filter Inductor and Current Ripple

For conventional TL DC–DC converter, the voltage applied on the filter inductor is Vin/2n1 − Vo during the power transmission, while the value is −Vo during the freewheeling period. Therefore, the current ripple of the filter inductor DiLf c is given by

3.3 Design Considerations

DiLf

61

c

¼

Ts Vin ð1  2n1 Vo =Vin Þ2n1 Vo =Vin 4nLf

ð3:26Þ

As seen in Fig. 3.8, for the HTL-HB converter, ignoring the voltage across the blocking capacitor, the voltage applied on the filter inductor is Vin/2n1 + Vin/ 4n2 − Vo during the power transmission. During the freewheeling period, the value is Vin/4n2 − Vo. The current ripple of the filter inductor for the HTL-HB converter is expressed as DiLf ¼

Ts Vin ð1  2n1 Vo =Vin þ n1 =ð2n2 ÞÞð2n1 Vo =Vin  n1 =ð2n2 ÞÞ 4n1 Lf

ð3:27Þ

For the desired output current ripple DILf = 0.5 A and the turns ratio of the transformer designed in Sect. 3.3.1, the output filter inductance versus input voltages is shown in Fig. 3.9. As seen in Fig. 3.9, compared with the conventional TL converter, the filter inductance of the HTL-HB converter is dramatically reduced. Furthermore, the filter size and copper loss of the inductor can be reduced. Eventually, the filter inductance Lf is designed as 130 lH.

3.3.3

Magnetizing Inductance of the HB Transformer

With the specification of C = 200 pF, Ts = 10 ls and tdead = 100 ns, the magnetizing inductance of Tr2 versus the leakage inductance Lk1 in terms of (3.16) is shown in Fig. 3.10. As seen, with the increase of Lk1, the magnetizing inductance

vrec

(a)

Vin/2n

Vo

t (b) Vin/2n1+Vin/4n2

vrec Vo

Vin/4n2

t Fig. 3.8 Idealized rectifier voltage vrec a conventional TL converter b HTL-HB converter

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

Lf (μH)

62

Conventional TL converter

HTL-HB converter

Vin (V)

Lm2(μH)

Fig. 3.9 Filter inductance as the function of input voltage for the desired current ripple

Hard switching region

ZVS region

Lk1(μH) Fig. 3.10 Magnetizing inductance of Tr2 versus the leakage inductance of Tr1

Lm2 increases. In this case, the magnetizing current in Tr2 can be reduced, and the circulating current is reduced as well. However, larger Lk1 causes larger duty cycle loss. Therefore, there is a trade-off between the duty cycle loss and magnetizing current in Tr2. In this chapter, the leakage inductance Lk1 is chosen as 8 lH. Therefore, the ZVS condition for lagging switches is Lm2  197 lH. Eventually, the magnetizing inductor Lm2 is designed as 190 lH.

3.3.4

Current Stress Comparison of the Primary Semiconductors

According to the turns ratio of the transformers and magnetizing inductance Lm2 in this section, the rms currents of the switches in per unit versus the input voltages in terms of (3.19) and (3.22) are shown in Fig. 3.11. As seen in Fig. 3.11, the current

3.3 Design Considerations

63

stress of the HTL-HB converter is lower than the conventional TL converter. As analyzed in Sect. 3.3.1, in order to achieve the same conversion ratio with the same duty cycle range, the turns ratio of Tr1 for HTL-HB converter is larger than the conventional TL converter, so the current amplitude in the primary winding of Tr1 is lower than the conventional TL converter. Hence, the current stress of leading switches is lower than the conventional TL converter. Figure 3.6a illustrates the circulating current of the conventional TL converter. During the freewheeling period, the lagging switches and clamping diodes have to handle higher circulating currents, causing more conduction loss. Figure 3.6b illustrates that ip1 is reset to zero when the output inductor works in the freewheeling period, reducing the rms current of the lagging switches. Although the primary winding current in Tr2 flows through the lagging switches and clamping diodes, the current stress is also lower than the conventional TL converter. Figure 3.12 shows the rms current in the clamping diodes in per unit versus the input voltage. Due to the reduced circulating current, the rms current in the clamping diodes is lower than the conventional TL converter. Therefore, the HTL-HB converter can obtain higher efficiency.

3.3.5

Blocking Capacitor Cb

The maximum voltage across the blocking capacitor is desired to be less than 100 V. According to (3.10) and (3.12), the capacitance Cb should meet the following requirements. (

ILf DTs 200:6910106 ¼ 125:4ðnFÞ 4n1 Vm ¼ 45:5100 Dð1DÞTs2 0:69ð10:69Þð10106 Þ2 ¼ 334ðnFÞ Cb \ 8Lk1 ¼ 88106

Cb [

Current stress of the switches in per unit (p.u.)

Then Cb is chosen as 150 nF.

Lagging switches of the conventional TL converter Lagging switches of the HTL-HB converter

Leading switches of the conventional TL converter

Leading switches of the HTL-HB converter

Vin (V)

Fig. 3.11 Rms current of the switches in per unit as the function of the input voltage

ð3:28Þ

3 Hybrid Three-Level and Half-Bridge DC–DC Converter … Current stress of the primary clamping diode in per unit (p.u.)

64

Conventional TL converter

HTL-HB converter

Vin (V)

Fig. 3.12 Rms current of the primary clamping diodes in per unit as the function of the input voltage

3.3.6

Selection of the Secondary Semiconductors

According to the analysis in Sect. 3.2.5, the voltage stress of DR1 and DR4 is equal 2V V 600 to inn1 max þ inn2max ¼ 2600 5:5  9 ¼ 284ðVÞ. The voltage stress of DR2 and DR3 is V

V

600 equal to in n1max þ in n2max ¼ 600 5:5 þ 9 ¼ 209ðVÞ. The current stress of all the secondary semiconductors can be designed no less than 20 A.

3.4

Experimental Verifications

In order to verify the performance of the HTL-HB converter, a 1 kW prototype is built. The specifications of the prototype are given as follows: Vin = 550–600 V, Vo = 50 V, n1 = 5.5, n2 = 9, Cd1 = Cd2 = 20 lF, Css1 = Css2 = 4.7 lF, C = 200 pF, Cb = 150 nF, Lm2 = 190 lH, Lf = 130 lH, Co = 220 lF. The switching frequency is 100 kHz. Each primary switch is FDP18N50. The primary clamping diode is DSEP12-12A. Rectifier diodes DR1 and DR4 are FFH30US30DN, whose forward voltage drop is 1 V. Rectifiers DR2 and DR3 are MBR20200CT, whose forward voltage drop is 0.8 V. A RCD snubber circuit is used to reduce the voltage spike of the rectifier diodes. The snubber circuit is composed of a 620 X resistor, a 10 nF capacitor, and a diode. The experimental results are shown in Figs. 3.13, 3.14, and 3.15. Figure 3.13 shows the key waveforms at different input voltages and output power, where P is the output power. Figure 3.13a shows the experimental waveforms when Vin = 550 V and P = 1000 W. Figure 3.13b shows the experimental waveforms when Vin = 600 V and P = 1000 W. With the increase of the input voltage, the duty cycle of the HTL-HB converter decreases. Figure 3.13c shows the experimental waveforms when Vin = 550 V and P = 200 W. The current

3.4 Experimental Verifications

65

(a)

vAB 250V/div

ip1 5A/div

ip2

5A/div

vrec 25V/div Time base:2μs/div

vAB

(b)

250V/div

ip1 5A/div

ip2 5A/div

vrec

25V/div Time base:2μs/div

(c)

vAB 250V/div

ip1

2A/div

ip2

2A/div

vrec 25V/div Time base:2μs/div Fig. 3.13 Measured key waveform of the HTL-HB converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 200 W

amplitudes of ip1 and ip2 are both reduced as the output power decreases. As expected, current ip1 in the three mentioned cases are all reset to zero during the freewheeling period, which minimizes the conduction loss in the primary-side circuit.

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

66

(a)

Time base:2μs/div

iD1 ids4

2A/div 5A/div

vds4 vgs4

100V/div 10V/div

ZVS (b)

Time base:2μs/div

iD1 ids4

1A/div 2A/div

vds4 vgs4

100V/div 10V/div

ZVS Fig. 3.14 Current of Q4, primary current of the clamping diode D1, and gate signal and drain-source voltage of switch Q4, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W

Figure 3.14 shows current in Q4, current in clamping diode D1, gate signal, and drain-source voltage of switch Q4. Figure 3.14a shows ZVS of the leading switches at heavy loads. Figure 3.14b shows the ZVS of the leading switches at light loads. Before Q4 is turned on, the current in Q4 is negative. The junction capacitor of Q4 is discharged until the current flows through its body diode. Figure 3.15 shows current in Q3, primary winding current in Tr2, gate signal, and drain-source voltage of switch Q3. Figure 3.15a shows the ZVS of lagging switches at the heavy load. Figure 3.15b highlights the ZVS operation of lagging switches at the light load. As seen in the experimental results, before Q3 is turned on, the current in Q3 is negative. The junction capacitor of Q3 is also discharged until the current flows through its body diode. Therefore, ZVS for all the switches is achieved over the wide load range. In order to compare the volume of the HTL-HB converter with the conventional one, the prototype of the conventional TL converter is built by using the same switches and rectifier diodes as the HTL-HB prototype. The other main components are shown in Table 3.1.

3.4 Experimental Verifications

67

(a)

(b)

Fig. 3.15 Current of Q4, current of Tr2, and gate signal and drain-source voltage of switch Q3 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W

68

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

Table 3.1 Main components and their volume Output inductor core Output inductor volume Transformer core

Conventional TL converter

HTL-HB converter

Kool Ml 77195 (with 27 turns) 79,599 mm3

Kool Ml 77715 (with 29 turns) 58,353 mm3

EE47/20/16

Tr1

Transformer volume

62,040 mm3

Fly capacitors Fly capacitor volume

630 V 2.2 lF 28 mm  19 mm  11 mm (5852 mm3) 100 V 220 lF (electrolytic capacitor) 1307 mm3

Output capacitor Output capacitor volume

E40/27/12 + I40/ 7.5/12 E33/23/13 + I33/5/ Tr2 13 Tr1 34,000 mm3 Tr2 23925 mm3 250 V 4.7 lF 2ea 24 mm  19 mm  11 mm (5016 mm3 2ea)

As seen in Table 3.1, the smaller inductor core is used for the HTL-HB converter. Due to the reduced output current ripple, the output inductance is lower than the conventional TL converter. Therefore, smaller core and lower filter inductance leads to lower core loss and copper loss. It will be demonstrated in Fig. 3.17. The HTL-HB converter distributes the power between transformer Tr1 and Tr2. Although two transformers are needed, the total transformer volume is still less than the conventional one. Compared with the conventional TL converter, the fly capacitor in the HTL-HB converter is split into two. Although the voltage rating of the flying capacitor is reduced, the total volume of the flying capacitor is a little bit larger than the conventional one. However, synthesizing the volume of the major components, the power density of the HTL-HB converter still can be improved. The measured efficiency curves for the HTL-HB converter, the converter in [2], and the conventional TL converter are shown in Fig. 3.16. Compared with the conventional TL converter, due to the reduced circulating current, the efficiency of the HTL-HB converter is greatly improved. At Vin = 600 V, the maximum improvement at light loads is 4%, and the improvement at heavy loads is more than 2%. For the converter in [2], although the ZVS of the switches is achieved, circulating currents still freewheels at the primary side of the transformer during the freewheeling period. Therefore, the efficiency of the HTL-HB converter is higher than the converter in [2]. Figure 3.17 shows the comparison of the calculated power loss distribution at full load when Vin = 550 V. Due to the reduced circulating current, the switches conduction loss, the clamping diodes conduction loss, and the transformer copper loss are all reduced. By using small volume of the cores, the transformer core loss is

69

Efficiency (%)

3.4 Experimental Verifications

Power (W)

Power loss (W)

Fig. 3.16 Efficiency for the HTL-HB converter, the conventional TL converter, and the converter in [2]

Fig. 3.17 Calculated power loss distribution at rated load when Vin = 550 V

reduced. The lower voltage rating diodes, such as Schottky diodes, are used for DR2 and DR3, whose forward voltage drop is lower. Therefore, the conduction loss in the rectifier stage is reduced. To sum up, the efficiency of the HTL-HB converter is higher than the conventional converter.

3.5

Conclusion

In this chapter, a hybrid TL and HB DC–DC converter by sharing the lagging switches to reduce the circulating current and output filter inductance is introduced for higher efficiency. Since the switches only undergo half of the input voltage, the presented converter is suitable for high input voltage applications. The magnetizing

70

3 Hybrid Three-Level and Half-Bridge DC–DC Converter …

inductor of the HB transformer can extend the ZVS of the lagging switches. The blocking capacitor together with the secondary novel-rectifying configuration can reset the circulating currents at the primary windings. Compared with the conventional TL DC–DC converter, the current stress of the switches and clamping diodes are all reduced, resulting in lower conduction loss. The good performance of the HTL-HB converter and design method has been verified by a 1 kW experimental prototype.

References 1. Liu F, Ruan X (2007) ZVS combined three-level converter—a topology suitable for high input voltage with wide range applications. IEEE Trans. Ind. Electron. 54(2):1061–1072 2. Kim D, Kim J, Moon G (2013) A three-level converter with reduced filter size using two transformers and flying capacitors. IEEE Trans Power Electron 28(1):2140–2150 3. Lin B, Chung S (2014) New parallel ZVS converter with less active switches and smaller output inductance. IEEE Trans Power Electron 29(7):3297–3307 4. Shi Y, Yang X (2014) Wide-range soft-switching PWM three-level combined DC–DC converter without added primary clamping devices. IEEE Trans Power Electron 29(10): 5157–5171 5. Liu F, Yan J, Ruan X (2010) Zero-voltage and zero-current-switching PWM combined three-level DC/DC converter. IEEE Trans Ind Electron 57(5):1644–1654

Chapter 4

Improved ZVS Three-Level DC–DC Converter with Reduced Circulating Loss

Abstract An improved two-transformer three-level (ITT-TL) DC–DC converter is introduced in this chapter. The converter contains two transformers. Like the conventional TL DC–DC converter, there are no additional switches on the primary side of the transformer. The rectifier stage is composed of four diodes in the center-tapped rectification. On the primary side of the transformer, the two transformers are connected in series. The middle node of the two transformers is connected to the neutral point of the split flying capacitors. Because it cooperates with the four-diode rectifier stage, the circulating current on the primary side of the transformer decays to zero during the freewheeling period. The zero-voltage switching (ZVS) of the leading switches is determined by energy stored in the output filter inductor, which is similar to the conventional TL converter. The ZVS of the lagging switches is determined by the energy stored in the magnetizing inductor of a transformer, rather than the energy stored in the leakage inductor. The ITT-TL converter can reduce the output filter inductance. Because of the advantages given above, the efficiency of the ITT-TL converter is far better than that of traditional methods. Finally, a 1 kW prototype was built to verify the performance of the ITT-TL converter. Keywords Three level

4.1


Reduced circulating current
Zero-voltage switching

Improved Two-Transformer Three-Level DC–DC Converter

Hybrid TL DC–DC converters, which combine two or more topologies by sharing some switches, can achieve soft switching or reduce the current ripple of the filter inductor [2–5]. However, a large circulating current still freewheels at the primary side of the circuits. In order to reduce the circulating current and extend ZVS range, a TL DC–DC converter hybrid with LLC converter was proposed in Chap. 2 [6]. In a similar manner, a TL DC–DC converter hybrid with half-bridge DC–DC converter was proposed in Chap. 3 [7]. In these two topologies, the power transmission © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_4

71

4 Improved ZVS Three-Level DC–DC Converter …

72

Q1

C1

Cd1 Css1 Vin

Tr1 Css2

C2

A

Tr2

Tr2 Q3

Cd2 Q4

iLf Lf vrec Vo Co Ro

Tr1

Q2

B

C

DR1

C3 Tr1 DR4 C4

Fig. 4.1 Conventional two-transformer TL DC–DC converter

ratio of the two transformers should be optimized for transformer design in wide conversion range. Figure 4.1 shows a conventional two-transformer three-level (TT–TL) DC–DC converter [1], in which the turns ratio of the two transformers is the same. The two transformers can share the output power, which is benefit for heat dissipation. However, the circulating current still freewheels at the primary side of the transformers during the freewheeling period. In this chapter, an improved two-transformer three-level (ITT–TL) DC–DC converter is introduced to reduce circulating current and output filter inductance. The primary winding of the two transformers is connected in series. The middle node of the two transformers is connected to the neutral point of the split flying capacitors. On the secondary side of the transformer, the corresponding windings are connected in series to form a center-tapped rectifier stage with four diodes. The ZVS condition for the lagging switches is determined by the magnetizing inductor of a transformer instead of the leakage one. In this converter, the current stress on the clamping diodes and primary switches is less than that experienced by the conventional TL converter. The conduction loss is dramatically reduced. Figure 4.2 shows the circuit configuration for the ITT–TL DC–DC converter. The divided capacitors Cd1 and Cd2, and the flying capacitors Css1 and Css2 are large enough to be treated as voltage sources, i.e., VCd1 = VCd2 = Vin/2, VCss1 = VCss2 = Vin/4. The output voltage regulation is implemented by the phase-shift manner. Q1 and Q4 are leading switches; Q2 and Q3 are lagging switches. C1−C4 are junction capacitors of the switches, and C1 = C2 = C3 = C4 = C. The primary windings of two transformers Tr1 and Tr2 in the converter are connected in series. The middle node of the two transformers is connected to the neutral point of the split flying capacitors. The turns ratio of the two transformers is the same as the turns ratio of n:1:1. Lk1 and Lk2 are the leakage inductors of Tr1 and Tr2. The magnetizing inductor of Tr1 was designed large, thus the magnetizing current during the switching period can be ignored. Lm2 is the magnetizing inductor of Tr2.

4.1 Improved Two-Transformer Three-Level DC–DC Converter

Q1 Cd1

Vin

C Cd2

D1

B

Tr1 Css2 D2

Lm2

C2

ip2

iLf

DR1 Tr1

Q2

Css1

ip1

C1

73

DR2

Lf vrec Vo Co Ro

Tr2

A

Tr2

DR3

Q3

C3 Tr1 DR4

Q4

C4

Fig. 4.2 Improved two-transformer three-level (ITT–TL) DC–DC converter

Figure 4.3 shows the key waveforms of the ITT–TL converter. As seen in Fig. 4.3, D is the duty cycle of the converter, and u is the phase-shift angle between the leading switches and lagging switches. There are eight working stages in each half-switching period. Stage 1 ([t0, t1]) (Fig. 4.4a): Prior to t0, Q1 and Q3 are on, and Q2 and Q4 are off. The primary winding current in Tr1 stays at zero, and the primary winding current in Tr2 is negative. The output filter inductor current flows through DR3. At time t0, Q3

Fig. 4.3 Key waveforms of the ITT–TL converter

Q1

Q4

Q3

Q1

Q2

vBC

Q3

Vin/4 Vin/4

DTs/2 Vin/4

vAB

Vin/4

ip1 ip2

Im2

Im2

vrec

Vin/2n Vin/4n

IDR4

IDR3

IDR1

IDR2

IDR4

ILf

t0 t1 t2 t3 t4 t5 t6 t7

t8

IDR3

IDR1

4 Improved ZVS Three-Level DC–DC Converter …

74

(a)

Q1 Cd1

Vin

C Cd2

D1

C1 Tr1

Q2

Css1

C2

Lm2 ip2

ip1

B

Tr1 Css2 D2

DR3

Q3

C3 Tr1 DR4

Q4

(b)

Vin

C4

Q1 Cd1

C Cd2

D1

C1 C2

Lm2 ip2

B

Tr1 Css2 D2

Q3

Vin

C Cd2

D1

B

Tr1 Css2 D2

C2

Vin

C Cd2

Lm2

ip1

B

Tr1 Css2 D2

Vo

DR3

C1

DR1 Tr1

C2

ip2 Q3

DR2

iLf Lf vrec Vo Co Ro

Tr2

A

Tr2

Q4

Co Ro

DR4

Q2

Css1

vrec

C4

Q1 D1

DR2

C3 Tr1

Q4

Cd1

Lf

Tr2

A Q3

iLf

DR1 Tr1

Tr2

(d)

Vo

DR3

C1

Lm2 ip2

ip1

Co Ro

DR4

Q2

Css1

vrec

C4

Q1 Cd1

DR2

C3 Tr1

Q4

(c)

Lf

Tr2

A

Tr2

iLf

DR1 Tr1

Q2

Css1

ip1

DR2

Lf vrec Vo Co Ro

Tr2

A

Tr2

iLf

DR1

DR3 C3 Tr1 DR4 C4

Fig. 4.4 Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8]

4.1 Improved Two-Transformer Three-Level DC–DC Converter

(e)

Q1 Cd1

Vin

C Cd2

D1

Lm2

B

Tr1 Css2 D2

C2

ip2 Q3

DR4

Vin

C Cd2

Lm2

ip1

B

Tr1 Css2 D2

C1 C2

ip2

Tr2 Q3

DR4

Vin

C Cd2

Lm2

ip1

B

Tr1 Css2 D2

C1 C2

ip2 Q3

DR4

Vin

C Cd2

Lm2

ip1

B

Tr1 Css2 D2

DR1 Tr1

C2

ip2

Tr2 Q3

DR2 Tr2

A

Q4

Fig. 4.4 (continued)

C1

Q2

Css1

DR3

C4

Q1 D1

Lf vrec Vo Co Ro

C3 Tr1

Q4

Cd1

DR2

iLf

Tr2

A

Tr2

(h)

DR1 Tr1

Q2

Css1

DR3

C4

Q1 D1

Lf vrec Vo Co Ro

C3 Tr1

Q4

Cd1

DR2

iLf

Tr2

A

(g)

DR1 Tr1

Q2

Css1

DR3

C4

Q1 D1

Lf vrec Vo Co Ro

C3 Tr1

Q4

Cd1

DR2

iLf

Tr2

A

Tr2

(f)

DR1 Tr1

Q2

Css1

ip1

C1

75

DR3 C3 Tr1 DR4 C4

iLf Lf vrec Vo Co Ro

4 Improved ZVS Three-Level DC–DC Converter …

76

is turned off. The junction capacitors of Q3 and Q2 are charged and discharged by the primary winding current in transformer Tr2, which includes the leakage inductor current and magnetizing current of Tr2. At t0, the primary winding current in Tr1 starts to increase. The current for charging flying capacitors Css1 and Css2 flows through Q1 and D2. Since DR1 and DR3 are forward biased and DR2 and DR4 are reverse biased, the current in DR1 starts to increase and the current in DR3 starts to decrease. The amplitude of the magnetizing current Im2 is expressed as Im2 ¼

Vin Ts 16Lm2

ð4:1Þ

where Ts is the switching period. Stage 2 ([t1, t2]) (Fig. 4.4b): At time t1, the drain-source voltage of Q2 reaches zero, and ip2 flows through the body diode of Q2. The voltage across the primary winding of Tr2 is Vin/4. ip1 and ip2 increase linearly. Q1 and D2 still conduct to charge the flying capacitors Css1 and Css2. The filter inductor current iLf flows through DR1 and DR3. The current in DR1 continues to increase, and the current in DR3 continues to decrease. ip1 and ip2 in this stage are expressed as ip1 ðtÞ ¼ ip1 ðt1 Þ þ ip2 ðtÞ ¼ ip2 ðt1 Þ þ

Vin 4Lk1 Vin 4Lk2

ðt  t1 Þ ðt  t1 Þ

ð4:2Þ

Stage 3 ([t2, t3]) (Fig. 4.4c): At time t2, Q2 is switched on with ZVS. iLf keeps on freewheeling through DR1 and DR3. The current in DR1 continues to increase, and the current in DR3 continues to decrease. ip1 and ip2 still increase linearly as expressed in (4.2). Stage 4 ([t3, t4]) (Fig. 4.4d): At time t3, the current in DR3 decays to zero, and DR3 is reverse biased. The filter inductor current flows through DR1. The two transformers start to transfer energy to the output. The secondary winding current in Tr2 is equal to that in Tr1. Ignoring the ringing of the rectifier diodes, the average voltage of vrec in this stage is Vin/2n. Neglecting the output current ripple, ip1 and ip2 in this stage is expressed as ILf n ILf Vin ip2 ðtÞ ¼  Im2 þ ðt  t0 Þ n 4Lm2 ip1 ðtÞ ¼

ð4:3Þ

Stage 5 ([t4, t5]) (Fig. 4.4e): When Q1 is turned off at t4, the voltages across the junction capacitors C1 and C4 are charged and discharged linearly by the energy stored in the output filter inductor Lf. The voltage across the primary winding of Tr1 starts to decrease. ip1 starts to decrease. At the same time, the current in DR1 decreases, and the current in DR2 increases. The magnetizing inductor current in Tr2 is still linearly increasing.

4.1 Improved Two-Transformer Three-Level DC–DC Converter

77

Stage 6 ([t5, t6]) (Fig. 4.4f): When the voltage across C1 reaches Vin/2 and the voltage across C4 reaches zero, the body diode of Q4 is forward biased. At this time, the voltage across the primary winding of Tr1 is −Vin/4. Due to the negative voltage, the primary winding current in Tr1 decreases linearly. Simultaneously, the current in DR1 continues decreasing and the current in DR2 continues increasing. Stage 7 ([t6, t7]) (Fig. 4.4g): At time t6, Q4 is turned on with ZVS. The primary winding current in Tr1 continues decreasing. D1 and Q4 start to charge the flying capacitors Css1 and Css2. The current in DR1 continues decreasing, and the current in DR2 continues increasing. Stage 8 ([t7, t8]) (Fig. 4.4h): Stage 8 starts when ip1 is reset to zero. The voltage across the primary winding of Tr1 is negative, so DR1 is reverse biased. Therefore, the flowing path of the secondary current in Tr1 is blocked. DR2 carries all the filter inductor current. D1 and Q4 still conduct to charge flying capacitors Css1 and Css2. The circulating current in Tr1 is reduced. Ignoring the ringing of the rectifier diodes, the average voltage of vrec in this stage is Vin/4n. ip2 in this stage is expressed as ip2 ðtÞ ¼

4.2 4.2.1

ILf Vin  Im2 þ ðt  t0 Þ n 4Lm2

ð4:4Þ

Analysis of the Converter DC Conversion Ratio

Ignoring the duty cycle loss, the DC conversion ratio of the converter in continuous conduction mode (CCM) can be derived from the volt-second balance for the output filter inductor, which is expressed as,

 Vin Vin  Vo DTs þ  Vo ð1  DÞTs ¼ 0 2n 4n

ð4:5Þ

where D is the duty cycle. Therefore, the DC conversion ratio of the ITT–TL converter is expressed as M¼

Vo 1 þ D ¼ 4n Vin

ð4:6Þ

For conventional TL converters, the DC conversion ratio is expressed as M¼

Vo D ¼ Vin 2n

ð4:7Þ

The lowest conversion ratio for conventional TL DC–DC converter can reach down to 0. Equation (4.6) illustrates that the lowest conversion ratio of the ITT–TL

4 Improved ZVS Three-Level DC–DC Converter …

78 Carrier waveform #1 Carrier waveform #2

Q1 Q2 Q3 Q4

PWM

Phase Shift

Fig. 4.5 Hybrid PWM and phase-shift modulation scheme

converter is 1/4n. In order to meet the short circuit and soft start requirements, the converter can work in hybrid modulation scheme, which is shown in Fig. 4.5. In normal operation, the converter works in phase-shift control. The key waveforms are shown in Fig. 4.3. In specified condition, the converter works in PWM mode. Although the converter will lose soft switching in PWM mode, the output voltage can be regulated down to 0. The start-up of the converter takes very short period, so the hard switching during the soft start period has little impact on the performance of the converter. In short circuit condition, the output power is limited. In this case, the soft switching is also unnecessary. Therefore, all the analysis and design below are based on normal operation.

4.2.2

ZVS Condition of Switches

During the commutations, the leading switches are charged and discharged by the primary currents in Tr1, which are all reflected from the energy stored in the output filter inductor. It is similar to conventional TL DC–DC converters. Therefore, the leading switches are easy to achieve ZVS at both the heavy load and light load. For the conventional TL DC–DC converter, the ZVS of lagging switches is determined by the energy stored in the leakage inductor. In the ITT–TL converter, the ZVS for lagging switches is determined by the energy stored in magnetizing inductor of Tr2, independent of the load power. The magnetizing inductor current should be large enough to charge and discharge the junction capacitors of the lagging switches. In order to guarantee soft switching at light loads, the converter should meet the following condition. Vin Vin Ts
2C  Im2 ttead ¼ ttead 2 16Lm2

ð4:8Þ

4.2 Analysis of the Converter

79

The maximum value of the magnetizing inductance Lm2 is expressed as Lm2 

Ts ttead 16C

ð4:9Þ

where tdead is the dead time of the lagging switches. In this case, the lagging switches can achieve ZVS within a wide load range.

4.2.3

Current Stress of the Primary Semiconductors

The primary winding currents in the transformers of the conventional TL converter and the ITT–TL converter are shown in Fig. 4.6a and b. In Fig. 4.6b, ip1 and ip2 are

Fig. 4.6 Primary winding current of the transformers and the currents of the primary semiconductors a conventional TL converter, b ITT–TL converter, c currents of the primary semiconductors in ITT–TL converter

Q1,Q2 on

(a)

D1,Q2 on

Q1,Q2 on

ip1

D2,Q3 on

Circulating current

DTs/2

(b)

Q3,Q4 on

D1,Q2 on

Q3,Q4 on

D2,Q3 on

D1,Q2,Q4 on

D1,Q3,Q4 on

D2,Q1,Q3 on

DTs/2

ip2 (c)

iQ1

D2,Q1,Q3 on ID

D2,Q1,Q2 on ILf /n DTs/2

iQ4

DTs/2 ID

iQ2

ILf /n+Im2

iQ3 iD1 iD2

ILf /n

ILf /n+Im2

ID ID

4 Improved ZVS Three-Level DC–DC Converter …

80

the primary winding currents of the ITT–TL converter, which have been defined in Fig. 4.3. Figure 4.6c shows the currents in the primary switches. As seen in Fig. 4.6a, ignoring the duty cycle loss and output current ripple, the rms current in qffiffiffi Vo D leading switches Q1 and Q4 is approximately evaluated as nR 2 . The rms current o o in the lagging switches Q2 and Q3 is expressed as pffiffi2VnR . The rms current in the o

primary clamping diodes for conventional TL converter is expressed as

irms D1;D2

conv

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Z Ts
rffiffiffiffiffiffiffiffiffiffiffiffi  u1 2 Vo 2 Vo 1  D ¼t dt ¼ Ts DT2s nRo 2 nRo

ð4:10Þ

As seen in Fig. 4.6c, during Stage 7–8, the current flows through the leading switch and clamping diode charge capacitors Css1 and Css2, and the current is  to. approximately equal to

Vo Vin Ro 4n

Vin 2

Vo ¼ 2nR . The rms current in the clamping diodes o

can be evaluated as the following.

irms D1;D2

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Z Ts
rffiffiffiffiffiffiffiffiffiffiffiffi  u1 2 Vo 2 Vo 1D t ¼ dt ¼ Ts DT2s 2nRo 2 2nRo

ð4:11Þ

Ignoring the output current ripple and duty cycle loss, the rms current in the leading switches for the ITT–TL converter is approximately evaluated as

irms Q1;Q4

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u 2 ! Z Ts
u 1 Z DT2s
Vo 2 2 V Vo 1 3D o t þ ¼ dt þ dt ¼ Ts 8 nRo nRo 8 0 DT2s 2nRo

ð4:12Þ

The magnetizing inductor current of Tr2 in Stage 1–8 is expressed as iLm2 ðtÞ ¼ Im2 þ

Vin t 4Lm2

ð4:13Þ

The rms current in the lagging switches for the ITT–TL converter is evaluated as irms Q2;Q3

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 Z Ts
2 1 Vo Vo2 Vin2 Ts2 ¼ þ iLm2 ðtÞ dt ¼ þ 2 2 Ts 0 nRo 2n Ro 1536L2m2

ð4:14Þ

The detailed current stress comparison between the conventional TL DC–DC converter and the ITT–TL converter will be discussed in Sect. 4.3.4.

4.2 Analysis of the Converter

81 n 2 ( Lk 1 + Lk 2 )

Fig. 4.7 Equivalent circuit of the secondary side in Stage 4 Vin 4n Vin 4n

4.2.4

is vDR3

CDR4

vDR4

CDR3

Vin 4n

ILf

Vin 4n

Voltage Stress of the Rectifier Diodes

The equivalent circuit at the secondary side of the transformers in Stage 4 is shown in Fig. 4.7, where CDR3 and CDR4 are the junction capacitance of DR3 and DR4. Assuming the output filter inductor current is a constant current source, the initial state in this Stage is vDR3(0) = vDR4(0) = 0, is(0) = ILf, and iDR3(0) = iDR4(0) = 0. Assuming CDR3 = CDR4 = CD, vDR4(t), vDR3(t), and is(t) are written by 3Vin ½1  cosðxn ðt  t3 ÞÞ 4n  Vin 3 1  cosðxn ðt  t3 ÞÞ vDR4 ðtÞ ¼ 4 n sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 3Vin 2C
is ðtÞ ¼ ILf þ sinðxn ðt  t3 ÞÞ n2 ðLk1 þ Lk2 Þ 4n vDR3 ðtÞ ¼

where xn ¼ 1

ð4:15Þ

.pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2n2 CD ðLk1 þ Lk2 Þ. Therefore, the maximum voltage of DR1 and

3Vin in DR4 is equal to 7V 4n , and the maximum voltage of DR2 and DR3 is equal to 2n . The maximum voltage stress of DR2 and DR3 is lower than that of DR1 and DR4.

4.3

Design Considerations

This section introduces a design example of the ITT–TL converter with 550–600 V input voltage and 50 V/20 A output. Therefore, the rated load resistance is 2.5 X. A switching frequency of 100 kHz is adopted.

4.3.1

Turns Ratio of the Two Transformers

At the minimum input voltage, the converter should be able to regulate the output voltage. Although the duty cycle of the converter can reach more than 0.9. Considering the duty cycle loss, the effective duty cycle of the converter will be

4 Improved ZVS Three-Level DC–DC Converter …

82

lower. Therefore, the effective duty cycle at the minimum input voltage is initially chosen as 0.7. Therefore, in terms of (4.6), the turns ratio of the transformers is expressed as n¼

1 þ D Vin 1 þ 0:7 550

¼ 4:675 ¼ 4 4 50 Vo

ð4:16Þ

For the conventional TL DC–DC operating within the same duty cycle range, the 0:7550 in turns ratio of the transformer can be expressed as n ¼ DV 2Vo ¼ 250 ¼ 3:85. Therefore, it can be selected as 3.8:1:1.

4.3.2

Filter Inductor and Current Ripple

Figure 4.8 shows the idealized rectifier voltage vrec in conventional and ITT–TL converters. During the power transmission, the voltage applied on the filter inductor in conventional TL converter is Vin/2n − Vo, while that in the ITT-TL converter is Vin/2n − Vo. During the freewheeling period, the voltage applied on the filter inductor in conventional TL converter is −Vo, while that in the ITT-TL converter is Vin/4n − Vo. Therefore, the current ripple of the filter inductor in the conventional TL converter is expressed as DiLf

c

¼

Ts Vin ð1  2n1 Vo =Vin Þ2n1 Vo =Vin 4nLf

ð4:17Þ

The current ripple of the filter inductor in the ITT–TL converter is expressed as DiLf ¼

Fig. 4.8 Idealized rectifier voltage vrec a conventional TL converter b ITT–TL converter

Ts Vin ð1  2nVo =Vin Þð4nVo =Vin  1Þ 4nLf

(a)

ð4:18Þ

vrec

Vin/2n

Vo

t (b) Vin/2n

vrec Vo

Vin/4n

t

4.3 Design Considerations

83

Lf (μH)

Fig. 4.9 Filter inductance as the function of input voltage for the desired current ripple

Conventional TL converter ITT-TL converter

Vin (V) For the desired output current ripple DILf = 0.5 A and the turns ratio of the transformers designed in Sect. 4.3.1, the output filter inductance versus input voltages is shown in Fig. 4.9. As seen in Fig. 4.9, the filter inductance in the ITT– TL converter is lower than that in conventional one. Eventually, the filter inductance Lf is designed as 80 lH.

4.3.3

Magnetizing Inductance of Tr2

The ZVS of the lagging switches can be achieved easily by larger magnetizing inductor current in Tr2. However, it will cause more conduction loss. The magnetizing inductor of Tr2 should meet Eq. (4.9). With the specification of C = 200 pF, Ts = 10 ls and tdead = 100 ns, the ZVS condition for lagging switches is Lm2  312.5 lH. Eventually, the magnetizing inductor Lm2 is designed as 300 lH.

4.3.4

Current Stress Comparison of the Primary Switches

In terms of the parameters designed in this section, the rms currents of the switches in per unit versus the input voltages are shown in Fig. 4.10. As seen in Fig. 4.10, the current stress in the ITT–TL converter is lower than the conventional one. The turns ratio of transformers has been designed in Sect. 4.3.1, and the turns ratio of the transformer in the ITT–TL converter is larger than the conventional one, Therefore, the primary winding current in the ITT–TL converter is lower than the conventional one. Figure 4.6a illustrates the circulating current of the conventional TL converter. The circulating current freewheels through the lagging switches and

4 Improved ZVS Three-Level DC–DC Converter …

Fig. 4.10 Rms current of the switches in per unit as the function of the input voltage

Current stress of the switches in per unit (p.u.)

84

Lagging switches of the conventional TL converter Lagging switches of the ITT-TL converter

Leading switches of the ITT-TL converter

Leading switches of the conventional TL converter

Vin (V)

clamping diodes, causing more conduction loss. Figure 4.6b illustrates that ip1 decays to zero in the freewheeling period, reducing the circulating loss of the primary winding. During the freewheeling period, transformer Tr2 still transmits energy to the output. Therefore, the circulating conduction loss is dramatically reduced. Figure 4.11 shows the rms current in the clamping diodes in per unit versus the input voltage. The rms current in the clamping diodes is lower than the conventional TL converter. To sum up, higher efficiency can be achieved.

4.3.5

Selection of the Rectifier Diodes

Fig. 4.11 Rms current of the primary clamping diodes in per unit as the function of the input voltage

Current stress of the clamping diodes in per unit (p.u.)

As analyzed in Sect. 4.2.4, the voltage stress of DR1 and DR4 is equal to 7Vin 7600 4n ¼ 44:5 ¼ 233:33ðVÞ. The voltage stress of DR2 and DR3 is equal to 3Vin 3600 2n ¼ 24:5 ¼ 200ðVÞ.

Conventional TL converter

ITT-TL converter

Vin (V)

4.3 Design Considerations

4.3.6

85

Output Filter Capacitance

Referring to Chap. 2 in [8], the output filter capacitance Co can be calculated as the following equation Co ¼

DiLf Ts 16
Dv

ð4:19Þ

where Δv is the output voltage ripple. If the output voltage ripple is designed less than 5 mV, the output filter capacitor should be larger than 62.5 lF.

4.4

Experimental Verifications

A 1 kW prototype was built to verify the performance of the ITT–TL converter. The specifications of the prototype are given as follows: Vin = 550–600 V, Vo = 50 V, n = 4.5, Cd1 = Cd2 = 20 lF, Css1 = Css2 = 20 lF, C = 200 pF, Lm1 = 4.1 mH, Lm2 = 300 lH, Lf = 80 lH, Co = 220 lF. The switching frequency is 100 kHz. The primary switch is FDP18N50. The primary clamping diode is DSEP12-12A. Rectifier diodes DR1 and DR4 are FFH30US30DN, whose forward voltage drop is 1 V. Rectifiers DR2 and DR3 are MBR20200CT, whose forward voltage drop is 0.8 V. An RCD snubber circuit, shown in Fig. 4.12a, is used to reduce the voltage spike of the rectifier diodes. The snubber circuit is composed of a 620 X resistor, a 10 nF capacitor, and a diode. Figure 4.12b shows the prototype used for the tests. The experimental results are shown in Figs. 4.13, 4.14, and 4.15. Figure 4.13 shows the experimental waveforms at different input voltages and output power, where P is the output power. Figure 4.13a shows the experimental waveforms when Vin = 550 V and P = 1000 W. Figure 4.13b shows the experimental waveforms when Vin = 600 V and P = 1000 W. With the increase of the input voltage, the phase shift between the leading and lagging switches increases.

(a)

DR1

Lf

Tr1 DR2 Tr2 DR3

vrec

D C

iLf

R

Co Ro

(b) Vo

RCD snubber circuit

Tr1 DR4 Fig. 4.12 a RCD snubber circuit; b Prototype of a 1 kW ITT-TL converter

4 Improved ZVS Three-Level DC–DC Converter …

86

(a)

vBC ip1 vAB ip2

250V/div 5A/div 250V/div 5A/div

Time base:2μs/div

(b)

vBC ip1

250V/div 5A/div

vAB

250V/div

ip2

5A/div

Time base:2μs/div

(c)

vBC ip1

250V/div 2A/div

Current spike

vAB ip2

250V/div 2A/div

Time base:2μs/div Fig. 4.13 Measured key waveform of the ITT–TL converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 200 W

4.4 Experimental Verifications

87

(a)

(b) iQ4

iQ4

5A/div

ip1

5A/div

ip1

vds4

100V/div

vds4

vgs4

1A/div 1A/div 100V/div

vgs4

10V/div

10V/div Time base:2μs/div

Time base:2μs/div

iQ4

iQ4

1A/div

5A/div

ip1

ip1

5A/div

vds4 vgs4

10V/div

vgs4

100V/div

ZVS

1A/div

vds4

10V/div

Time base:1μs/div

100V/div

ZVS

Time base:1μs/div

Fig. 4.14 Current of Q4, current in Tr1, and gate signal and drain-source voltage of switch Q4, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W

(a)

(b) iQ2

5A/div

iQ2

2A/div

ip2

ip2

2A/div

5A/div 100V/div

vds2 vgs2

10V/div

5A/div

ip2

5A/div 10V/div

vds2

10V/div Time base:2μs/div

Time base:2μs/div

iQ2

100V/div

vds2 vgs2

iQ2

2A/div

ip2

2A/div 10V/div

vds2 vgs2

vgs2 ZVS

Time base:1μs/div

100V/div

100V/div

ZVS

Time base:1μs/div

Fig. 4.15 Current of Q2, current in Tr2, and gate signal and drain-source voltage of switch Q2 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 200 W

Figure 4.13c shows the experimental waveforms when Vin = 550 V and P = 200 W. Current ip1 in the three mentioned cases decays to zero during the freewheeling period. Compared with the key waveforms in Fig. 4.3, the current waveforms of ip1 and ip2 have current spike, which is caused by the RCD snubber circuit. Prior to t3, vrec is equal to zero. At the start of Stage 4, Tr1 and Tr2 start to

88

4 Improved ZVS Three-Level DC–DC Converter …

transmit energy to the output. At this time, the capacitor in the RCD snubber circuit is charged. The charge current is reflected to the primary winding current of the transformer, causing current spike in the current waveforms of ip1 and ip2. Figure 4.14 shows current in Q4, current in Tr1, gate signal, and drain-source voltage of switch Q4. Figure 4.14a shows ZVS of the leading switches at heavy loads. Figure 4.14b shows the ZVS of the leading switches at light loads. Before Q4 is turned on, current in Q4 is negative. The junction capacitor of Q4 is discharged until the current flows through its body diode. Figure 4.15 shows current in Q2, primary winding current in Tr2, gate signal, and drain-source voltage of switch Q2. Figure 4.15a shows the ZVS of lagging switches at the heavy load. Figure 4.15b highlights the ZVS operation of lagging switches at the light load. Before Q2 is turned on, the current in Q2 is negative. The junction capacitor of Q2 is also discharged until the current flows through its body diode. Table 4.1 shows the volume comparison of major component in conventional TL converter and ITT–TL converter. In the prototype of the conventional TL converter, the rectifier diodes are FFH30US30DN. The flying capacitance is 2.2 lF. The turns ratio of the transformer is 3.8:1:1. The same snubber circuit is used to reduce the voltage spike of the rectifier diodes. The output filter capacitance is 220 lF, and the output filter inductance is 180 lH. The material of the inductor core is Kool Ml produced by Magnetics®. The parameters of the core are referred to http://www.mag-inc.com/products/powder-cores/kool-mu. Kool Mµ material’s relatively high saturation level makes it excellent for use in filter inductance. The 10500 gauss saturation level of Kool Mµ cores provides a higher energy storage capability than can be obtained with gapped ferrites of the same size and effective permeability. Therefore, it is less likely to be saturated. As shown in Table 4.1, due to the reduction of the output filter inductor, a smaller core can be used for designing the output filter inductor. The smaller core can not only improve the power density but also reduce the core loss and copper loss. There are two transformers in the ITT–TL converter, but the output power can be distributed in them. The total volume of the transformers in the ITT–TL converter is still less than the volume of the transformer in the conventional TL converter. There is a flying

Table 4.1 Major components and their volume Conventional TL converter

ITT–TL converter

Output inductor volume Transformer core

Kool Ml 77195 (with 38 turns) 79,599 mm3 PQ50

Transformer volume

124,950 mm3

Flying capacitors Flying capacitor volume

630 V 2.2 lF 5852 mm3

Kool Ml 77715 (with 25 turns) 58,353 mm3 Tr1 PQ35 PQ35 Tr2 Tr1 44,100 mm3 Tr2 44,100 mm3 250 V 20 lF 2ea 11,030 mm3 2ea

Output inductor core

4.4 Experimental Verifications

89

Fig. 4.16 Efficiency for the ITT–TL converter and the conventional TL converter

capacitor in the conventional TL converter, whose voltage stress is Vin/2. There are two flying capacitors in the ITT–TL converter, whose voltage stress is Vin/4. Therefore, the voltage stress of the flying capacitor in the ITT–TL converter is lower than the conventional one. Although the volume of the flying capacitors in the ITT–TL converter is larger, the total volume of the ITT–TL converter is still lower than that of the conventional one. Figure 4.16 shows the measured efficiency curves for the ITT–TL converter and the conventional TL converter. Because of the ZVS and reduced circulating current, the efficiency of the ITT–TL converter is higher than the conventional one. The improvement at light loads is almost 1.5%, and the improvement at heavy loads is nearly 1%. Figure 4.17 shows the calculated power loss distribution at rated load when Vin = 550 V. The switch conduction loss, clamping diode conduction loss and the

Fig. 4.17 Calculated power loss distribution at rated load when Vin = 550 V

4 Improved ZVS Three-Level DC–DC Converter …

90

transformer copper loss in ITT–TL converter are all lower than the conventional TL converter. Due to the smaller core in magnetic components, the core loss in the ITT–TL converter is less than the conventional one. In rectifier stage, the voltage drop across DR2 and DR3 is less than that across DR1 and DR4. Therefore, the conduction loss in rectifier stage is less than that in conventional one. The efficiency of the ITT–TL converter is higher than the conventional TL DC–DC converter.

4.5

Conclusion

An improved two-transformer TL isolated DC–DC converter was presented by reducing the circulating current and output filter inductance for higher efficiency. Because the switches only experience half of the available input voltage, the presented converter is suitable for high-input-voltage applications. The two transformers in the ITT–TL converter can distribute the load power. The ZVS of the leading switches can be achieved by the energy stored in the output filter inductor. The ZVS of the lagging switches is determined by the magnetic inductor of a transformer instead of the energy stored in the leakage inductor. With the help of the four-diode rectifier stage, the circulating current on the primary side of the converter can decay to zero during the freewheeling period. Compared with the conventional TL DC–DC converter, the current stress of the switches and clamping diodes is all reduced, resulting in lower conduction loss. In the end, the ideal characteristic and performance of the ITT–TL converter and design method were verified by a 1 kW experimental prototype.

References 1. Kim D, Kim J, Moon G (2013) A three-level converter with reduced filter size using two transformers and flying capacitors. IEEE Trans Power Electron 28(1):2140–2150 2. Lin B, Chung S (2014) New parallel ZVS converter with less active switches and smaller output inductance. IEEE Trans Power Electron 29(7):3297–3307 3. Shi Y, Yang X (2014) Wide-range soft-switching PWM three-level combined DC–DC converter without added primary clamping devices. IEEE Trans Power Electron 29(10):5157– 5171 4. Lin B, Cheng P (2014) New ZVS DC–DC converter with series-connected transformers to balance the output currents. IEEE Trans Power Electron 29(1):246–255 5. Guo Z, Sha D, Liao X (2015) Hybrid phase-shift-controlled three-level and LLC DC–DC converter with active connection at the secondary side. IEEE Trans Power Electron 30 (6):2985–2996 6. Guo Z, Sha D, Liao X (2015) Hybrid three-level and half-bridge DC–DC converter with reduced circulating loss and output filter inductance. IEEE Trans Power Electron 30(12):6628– 6638 7. Deschamps E, Barbi I (1998) A comparison among three-level ZVS-PWM isolated DC-to-DC converters. In: IEEE IECON, pp 1024–1029 8. Erickson RW, Maksimovic D (2001) Fundamentals of power electronics. Springer

Chapter 5

Analysis and Evaluation of Dual Half-Bridge Cascaded Three-Level DC–DC Converter for Reducing Circulating Current Loss

Abstract Three-level (TL) DC–DC converters can meet high input voltage requirement. The isolated TL converters with clamping diodes and flying capacitor are the prevalent TL topologies. However, large circulating current in the primary windings may degrade the efficiency. Although many other TL converters with auxiliary components are proposed and investigated for soft switching, the auxiliary components may increase the weight and size of the converters. The dual half-bridge cascaded (DHBC) TL converter splits the one transformer into two, but no clamping diodes, flying capacitors or other auxiliary components in the primary circuit, which meets the compact size requirement. In order to reduce the circulating current further, an improved dual half-bridge cascaded TL (IDHBC-TL) converter with four rectifier diodes and proper sequence of the transformer windings is introduced in this chapter. Because of the proper sequence of the windings, the circulating currents in the primary side of the transformers decay to zero during the freewheeling period. Although the circulating current is reduced, the primary switches still can achieve zero-voltage switching (ZVS) without any other auxiliary circuits. Besides, the presented converter can reduce the current ripple of the filter inductor, leading to a reduction of the output filter inductance. The evaluation of the good performance in the IDHBC-TL converter is investigated, and the IDHBC-TL converter is compared with some other TL converters. It has compact size and higher efficiency. Lastly, a 1 kW prototype is built to verify the performance of the IDHBC-TL converter.




Keywords Three-level Reduced circulating current Low output current ripple


Zero-voltage switching


© Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_5

91

5 Analysis and Evaluation of Dual Half-Bridge …

92

5.1

Improved Dual Half-Bridge Cascaded Three-Level DC–DC Converter

With the aim of reducing the output filter inductor current ripple, more than one transformer is integrated into the TL converters [1–5]. As analyzed in Chap. 4, an improved two-transformer TL DC–DC converter with novel rectifier stage is presented to reduce the output filter size [6]. The circulating current at the primary circuit is reduced, so the magnetizing inductor current in the transformers has to be used for soft switching. The power distribution between the two transformers varies with the duty cycle of the converter. The load power still cannot be equally shared between the two transformers, so they may not work in optimum. Although the improved two-transformer TL converters can achieve higher efficiency than the conventional TL converter, its DC conversion ratio is limited by only using phase-shift control. A dual half-bridge cascaded (DHBC) TL DC–DC converter, shown in Fig. 5.1a, was composed of two transformers and two half-bridge cells in the primary circuit [7]. The two cells were connected in series to form a TL structure without clamping diodes, flying capacitors or other auxiliary circuits. Therefore, the DHBC-TL DC–DC converter meets the compact requirement. However, as shown in Fig. 5.1b, large circulating current still freewheels at the primary winding of the transformers. In [8], a dual half-bridge cascaded TL (DHBC-TL) DC–DC converter with reduce circulating current is presented. However, the gain of the converter cannot reach down to zero, which cannot meet soft startup, short circuit, and wide output voltage requirements. Figure 5.2 shows the circuit derivation of the improved dual half-bridge cascaded TL (IDHBC-TL) converter TL DC–DC converter. Figure 5.2a shows the DHBC-TL DC–DC converter. The converter shown in Fig. 5.2b is derived by rearranging the sequence of the secondary windings of the transformers. In actuality, the circuits shown in Fig. 5.2a, b are the same converter. By adding two more

(a)

(b) Cd1 B Cd2

ip1 Tr1

Q1

C1

A

DR1

Tr1

Lf vrec Vo Co Ro

C2

Q2

Vin

Tr2 Cd3

D Cd4

ip2

Q1 vAB

Q1

Q2

Q3

Q4

DTs

Q1 Q3

DTs

vCD

Circulating current

ip1

Q3 C

C3

Tr2 Q4

iLf

ip2

Tr1 DR2

C4

IDR4

IDR1

IDR2

IDR1

ILf

Fig. 5.1 Dual half-bridge cascaded TL (DHBC-TL) DC–DC converter: a main circuit, b key waveforms

5.1 Improved Dual Half-Bridge Cascaded Three-Level DC–DC Converter

(a)

93

(b)

Cd1 B Cd2

Lm1

Tr1

Q1 ip1 Lk1

Q2

C1 A

DR1

Tr1 C2

Cd3 D Cd4

Q3 Lm1

Tr2

ip2 Lk2

Q4

Cd1 B

Lf vrec Vo Co Ro

Tr2

Vin

iLf

Cd2

Q1 ip1

Lm1

Tr1

Lk1

Q2

C1 A

Tr1 C2 Tr2

Vin Cd3

C3 C Tr1

D DR2

Cd4

C4

(c) Cd1 B

Lm1

Tr1

Cd2

Q1 ip1 Lk1

C1 A

Q2

Vin Q3

Cd3 D Cd4

ip2

Lm1

Tr2

Lk2

Tr1 C2

DR1

Tr2

DR2

Tr1

DR3

ip2

Tr2

Lk2

Q4

iLf Lf vrec V Co Ro o

Tr1

Q3 Lm1

DR1

C3 C Tr2

DR2

C4

iLf Lf vrec Vo Co Ro

C3 C Tr2

Q4

DR4 C4

Fig. 5.2 Derivation of IDHBC-TL DC–DC converter

diodes in the secondary rectifier stage of the converter shown in Fig. 5.2b, the IDHBC-TL converter, shown in Fig. 5.2c, is derived. Figure 5.3 shows the key waveforms of the IDHBC-TL converter. The on-time of Q1 is complementary to that of Q2 with a dead time for ZVS. The same is true for Q3 and Q4. The output voltage is regulated by the duty cycle of Q1 and Q4, while D is the duty cycle of the converter and Ts is the switching period. The turns ratio of the two transformers is the same with n:1:1. C1–C4 are junction capacitors of the switches, and C1 = C2 = C3 = C4 = C. Lk1 and Lk2 are the leakage inductors of Tr1 and Tr2, and Lk1 = Lk2= Lk. The magnetizing inductance Lm1 and Lm2 in Tr1 and Tr2 are large enough, so the magnetizing inductor current is negligible. Divided capacitors Cd1, Cd2, Cd3, and Cd4 are large enough to be treated as voltage sources. Furthermore, the converter meets VCd1 + VCd2 = Vin/2 and VCd3 + VCd4 = Vin/2. The voltages across divided capacitor Cd1, Cd2, Cd3, and Cd4 are expressed as Vin ð1  DÞ 2 Vin D ¼ 2

VCd1 ¼ VCd4 ¼ VCd2 ¼ VCd3

ð5:1Þ

5 Analysis and Evaluation of Dual Half-Bridge …

94 Fig. 5.3 Key waveforms of the IDHBC-TL converter

Q2 Q4

Q1

Q2

Q3

Q4

Q1 Q3

VCd 1

vAB

VCd 2

DTs

DTs

VCd 3

vCD

VCd 4

ip1 ip2 IDR4 IDR3

IDR1

IDR2

IDR4

IDR3

IDR1

ILf

Ringing

vrec

Vin/2n

t0 t1 t2 t3 t4 t5 t6 t7 t8

VinD/(2n)

There are eight working stages in each half-switching period. Stage 1 ([t0, t1]) (Fig. 5.4a): Before t0, Q2 and Q3 are on, and Q1 and Q4 are off. The primary current in Tr1 is negative. The primary current in Tr2 stays at zero. The output filter inductor current flows through DR3. At time t0, Q2 is turned off. The energy stored in the leakage inductor Lk1 starts to charge and discharge the junction capacitors of Q2 and Q1, respectively. Ignoring the output current ripple, the voltages across Q1 and Q2 are expressed as 8 ILf Vin Vin D > < vQ1 ðtÞ ¼ 2  2 ½1  cosðxn ðt  t0 ÞÞ  2nxn C sinðxn ðt  t0 ÞÞ I vQ2 ðtÞ ¼ Vin2D ½1  cosðxn ðt  t0 ÞÞ þ 2nxLfn C sinðxn ðt  t0 ÞÞ > : I ip1 ðtÞ ¼ xn CVin D
sinðxn ðt  t0 ÞÞ þ nLf cosðxn ðt  t0 ÞÞ

ð5:2Þ

pffiffiffiffiffiffiffiffiffiffiffi where xn ¼ 2CLk , ILf is the average output filter inductor current. The primary winding current in Tr2 starts to increase. DR1 and DR3 are forward biased, and DR2 and DR4 are reverse biased. The current in DR1 starts to increase and the current in DR3 starts to decrease. Stage 2 ([t1, t2]) (Fig. 5.4b): At time t1, the drain-source voltage of Q1 reaches zero, and the body diode of Q1 is forward biased. The output filter inductor current iLf freewheels through DR1 and DR3. The current in DR1 continues to increase, and the current in DR3 continues to decrease. The voltage across the primary winding of Tr1 is VCd1. ip1 and ip2 both increase linearly, and they are expressed as

5.1 Improved Dual Half-Bridge Cascaded Three-Level DC–DC Converter

(a)

Cd1

Q1 ip1

Lm1

B Cd2

Lk1

Tr1

C1 A

Vin Cd3

Q3 ip2

Lm2

D Cd4

Tr2

Lk2

Lk1

Tr1

D Cd4

(c)

Cd1

ip2 Lk2

A

B Cd2

Lk1

Tr1

C3 C

D Cd4

A

(d)

Cd1

ip2 Lk2

Lk1

Tr1

C

D Cd4

A

ip2 Lk2

Q4

C3 C

Tr1

DR3

Lk2

vrec

Co Ro

Cd2

Lk1

Tr1

Cd3

Tr2

D Cd4

(g)

iLf

DR1

ip2

Tr2 Tr1

DR3

vrec

Co Ro

Lk2

Vo

Cd2

C3 C

Cd3 D Cd4

Lk1

DR1

Tr2

DR2

Tr1

DR3

iLf

(h)

Cd1

ip2 Lk2

Cd2

Lk1

Tr1

C

Tr2

D Cd4

ip2 Lk2

Q4

Tr1

DR3

vrec

C o Ro

Vo

Tr2

iLf

DR1

Lf

Tr2

DR2

Tr1

DR3

vrec

C o Ro

Vo

Tr2

DR1 Tr1

C2

Q3 Tr2

DR2

C1 A

Q2

Lm2

Tr2

DR4

Vin Cd3

Lf

C4

Q1 ip1

B

Lf vrec Vo Co Ro

C3

Q4

Lm1

iLf

DR1

Tr1 C2

Q3 Tr2

Vo

Tr2

C1 A

Q2

Lm2

C o Ro

DR4

Vin

Tr2

DR3

vrec

C4

Q1 ip1

Tr1

Tr1

Tr1 C2

Q4

Lm1

DR2

C1

Q2

B

Lf DR2

Cd1

Tr2

DR4

A

Q3 Tr2

Lf

C4

Q1 ip1

Lm1

B Vo

C

Q4

Lm2

DR4 C4

ip2

C3

Vin

Tr1 C2

Q3 Tr2

Tr2

DR2

C1

Q2

Lm2

Cd1

DR4

Vin Cd3

Tr2

C4

Q1 ip1

B Cd2

C3

Q4

Lm1

iLf Lf

Tr1 C2

Q3 Tr2

D Cd4

DR1

C1

Q2

Lm2

Q3

iLf

DR1 Tr1

C2

Q2

Lm2

DR4

Vin Cd3

Cd3

C4

Q1 ip1

Lk1

Tr1

C1 A

Vin

Tr1 C2

Q4

Lm1

Cd2

(f)

Q3 Tr2

Vo

Tr2

C1

Q2

Lm2

DR3

Co Ro

DR4

Vin Cd3

Tr1

vrec

Q1 ip1

Lm1

C4

Q1 ip1

Lm1

B Cd2

C

Q4

(b) Cd1

C3

Tr2

DR2

Cd1 B

Lf

Tr1 C2

Q2

(e)

iLf

DR1

95

C3 C

Tr2

DR2

Tr1

DR3

iLf Lf vrec Vo C o Ro

Tr2 DR4

C4

Fig. 5.4 Topological stages with half-switching cycle: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], f [t5, t6], g [t6, t7], h [t7, t8]

5 Analysis and Evaluation of Dual Half-Bridge …

96

VCd1 Vin ð1  DÞ ðt  t1 Þ ¼ ip1 ðt1 Þ þ ðt  t1 Þ 2Lk Lk VCd3 Vin D ip2 ðtÞ ¼ ip2 ðt1 Þ þ ðt  t1 Þ ¼ ip2 ðt1 Þ þ ðt  t1 Þ 2Lk Lk

ip1 ðtÞ ¼ ip1 ðt1 Þ þ

ð5:3Þ

Stage 3 ([t2, t3]) (Fig. 5.4c): At time t2, Q1 is switched on with ZVS. iLf keeps on freewheeling through DR1 and DR3. ip1 and ip2 still increase linearly as expressed in (5.3). Stage 4 ([t3, t4]) (Fig. 5.4d): The current in DR3 decreases to zero at t3. DR3 is reverse biased. DR1 carries all the filter inductor current. The resonance between the leakage inductor and the junction capacitors of DR3 and DR4 leads to the ringing. Neglecting the ringing of the rectifier diodes, the average voltage of vrec is Vin/2n. The secondary winding current in Tr2 is equal to that in Tr1. The average primary winding currents in Tr1 and Tr2 are expressed as ip1 ðtÞ ¼ ip2 ðtÞ ¼

ILf n

ð5:4Þ

Stage 5 ([t4, t5]) (Fig. 5.4e): When Q1 is turned off at t4, the voltages across the junction capacitors C1 and C2 are charged and discharged linearly by the energy stored in the output filter inductor Lf. The voltage across the primary winding of Tr1 starts to decrease. Stage 6 ([t5, t6]) (Fig. 5.4f): When the voltage across C1 reaches Vin/2 and the voltage across C2 reaches zero, ip1 flows through the body diode of Q2. At this time, the voltage across the primary winding of Tr1 is VCd2. The current in Tr1 continues to decrease. The current in DR1 decreases, while the current in DR2 increases. Stage 7 ([t6, t7]) (Fig. 5.4g): At time t6, Q2 is turned on with ZVS. The primary winding current in Tr1 continues decreasing. At the same time, the current in DR1 continues decreasing and the current in DR2 continues increasing. Stage 8 ([t7, t8]) (Fig. 5.4h): Stage 8 starts when ip1 is reset to zero. Because the voltage across the primary winding of Tr1 is negative, DR1 is reverse biased. DR2 and the secondary winding of Tr2 carry all the filter inductor current. The flowing path of the secondary current in Tr1 is blocked. Only the magnetizing current in Tr1 flows through Q2. Because the magnetizing inductance is large enough, the magnetizing current is negligible. Therefore, the circulating current during the freewheeling period is reduced. Tr2 still transfer energy to the output, so there is no circulating current in Tr2 during this stage. The average voltage of vrec in this stage is VCd2 =n ¼ Vin D=ð2nÞ.

5.2 Analysis and Design Consideration of the Converter

5.2

97

Analysis and Design Consideration of the Converter

This section presents a design example of the IDHBC-TL converter with 550–600 V input voltage and 50 V/20 A output. In the design example, the switching frequency is 100 kHz.

5.2.1

ZVS Condition of Switches

In order to achieve ZVS for Q2 and Q3, their junction capacitor voltage should drop to zero before the switch is turned on. In this working stage, Q2 and Q3 are charged by the currents in the primary windings of the transformers, which are all reflected from the energy stored in the output filter inductor. Consequently, Q2 and Q3 are easy to achieve ZVS even at light load. The circulating current during the freewheeling period is reduced, but the ZVS condition of Q1 and Q4 is still determined by the energy stored in the leakage inductor. The required leakage inductance to achieve ZVS for Q1 and Q4 from a% to 100% load is obtained as    2 1 a%
P 2 1 Vin
Lk

ð2CÞ
2 Vo 2 2

ð5:5Þ

Therefore, the leakage inductance should meet the following condition. Lk 

nCVin2 Vo 2  ða%
PÞ

ð5:6Þ

Figure 5.5 shows the leakage inductance for ZVS versus load percentage, where the rated load power is 1 kW. In order to achieve wide ZVS of the switches, the leakage inductor of the transformers should be large enough. The larger leakage inductor may increase the duty cycle loss. There is a trade-off in the transformer design for the leakage inductor and duty cycle loss. With an increase of the input voltage, more energy is stored in the junction capacitor of the switches, so more energy in the leakage inductance is necessary for ZVS. As seen in Fig. 5.5, the leakage inductance should be increased for ZVS, as the input voltage increases. In order to guarantee soft switching at 25% load, the converter should meet the following condition. Lk 

nCVin2 max Vo 4  100  1012  6002  50 ¼ 14:4 ðlHÞ ¼ 2  0:25  1000 2  ða%
PÞ

ð5:7Þ

From (5.6), the selected leakage inductance Lk1 = Lk2 = 15 lH can guarantee ZVS of Q1 and Q4 from 25% load to 100% load at Vin = 600 V.

5 Analysis and Evaluation of Dual Half-Bridge …

Fig. 5.5 Leakage inductor for ZVS versus load percentage

Leakage inductor (μH)

98

Soft switching

Vin=600V Vin=550V

Hard switching α%

5.2.2

Comparison of the Gain of the Converter

Ignoring the duty cycle loss, the voltage across the filter inductor of IDHBC-TL converter is shown in Fig. 5.6a. The voltage applied on the filter inductor is Vin/ 2n − Vo during the power transmission. During the freewheeling period, the value is VinD/2n − Vo. In term of the volt-second balance for the output filter inductance, the average voltage of the output filter inductor is expressed as vLf ¼

1 2

     Vin Vin D ð1  D  DÞ  Vo  Vo D þ ¼0 2n 2 2n

ð5:8Þ

Therefore, the DC conversion ratio of the converter is expressed as M¼

Vo Dð3  2DÞ ðD  0:5Þ ¼ 2n Vin

ð5:9Þ

In the lowest input voltage, the converter should meet the output voltage requirement. In this occasion, the duty cycle is the largest, and the converter should meet the following condition. n¼

Vin

min Dmax ð3

 2Dmax Þ

2Vo

ð5:10Þ

The voltage across the output filter inductor for DHBC-TL converter is shown in Fig. 5.6b. Analyzed in the same manner, the DC conversion ratio is expressed as MDHBC ¼

Vo D ¼ ðD  0:5Þ Vin n

ð5:11Þ

5.2 Analysis and Design Consideration of the Converter Fig. 5.6 Voltage across the output filter inductor: a IDHBC-TL converter, b DHBC-TL converter, c ITT-TL converter

99

(a) vLf Vin /2n-Vo 0

Ts DTS

Vin D/2n-Vo

(b)

(1-D)TS

(1-D-D)TS /2

vLf

Vin /2n-Vo 0

Ts DTS

(1-D)TS

-Vo

(c)

0 Vin /4n-Vo

t

(1-D-D)TS /2

vLf

Vin /2n-Vo

t

Ts DeffTS

(1-Deff)TS

t

(1-Deff-Deff)TS /2

As seen in Fig. 5.6c, the DC conversion ratio of the ITT-TL converter is calculated as MTTHC ¼

Vo 1 þ 2Deff ðDeff  0:5Þ ¼ Vin 4n

ð5:12Þ

where Deff is defined as the effective duty cycle of ITT-TL converter, which is equal to half of the duty cycle defined in Sect. 4.2.1. Compared with the different TL converters, the gain of the converters versus the duty cycle in specifications of n = 4 is shown in Fig. 5.7. The maximum DC conversion ratios of the different TL converters are the same with 1/(2n). The DC conversion ratio of the IDHBC-TL converter is no less than that of the DHBC-TL converter. The minimum DC conversion ratio of the IDHBC-TL converter can reach down to 0. The gain of the ITT-TL converter is larger than that of DHBC-TL converter and IDHBC-TL converter. The lowest gain of the ITT-TL converter is 1/(4n), which cannot meet the short circuit and soft start requirements. To achieve this aim, the hybrid modulation should be used, which complicates the circuit design [7].

5 Analysis and Evaluation of Dual Half-Bridge …

100 Fig. 5.7 DC conversion ratio versus duty cycle

DC conversion ratio M

ITT-TL converter

IDHBC-TL converter DHBC-TL converter

Duty cycle D

5.2.3

Comparison of the Filter Inductance

As seen in Fig. 5.6a, the current ripple of the filter inductor for the IDHBC-TL converter is expressed as

DiLf

 pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Ts DðVin =2n  Vo Þ Ts Vin ð1  2nVo =Vin Þ 3  9  16nVo =Vin ¼ ¼ ð5:13Þ Lf 8nLf

As seen in Fig. 5.6b, the current ripple of the filter inductor DiLf converter is calculated as DiLf

DHBC

¼

TTHC

¼

in DHBC-TL

Ts Vin ð1  2nVo =Vin ÞnVo =Vin 2nLf

As seen in Fig. 5.6c, the current ripple of the filter inductor DiLf converter is calculated as DiLf

c

Ts Vin ð1  2nVo =Vin Þð4nVo =Vin  1Þ 4nLf

ð5:14Þ TTHC

in ITT-TL

ð5:15Þ

For the desired output current ripple DILf = 0.5 A and n = 4, the output filter inductance versus input voltages in different converters is shown in Fig. 5.8. As seen in Fig. 5.8, compared with the DHBC-TL converter, the filter inductance of the IDHBC-TL converter is reduced by nearly 20%. It is still larger than that in TTHC converter, because the voltage across the filter inductor for ITT-TL converter during the freewheeling period is lower. It also illustrates that the ITT-TL converter

Fig. 5.8 Filter inductance as the function of input voltage for the desired current ripple

Lf (μH)

5.2 Analysis and Design Consideration of the Converter

101

DHBC-TL converter

IDHBC-TL converter

ITT-TL converter

Vin (V)

has lower output voltage range. Eventually, the filter inductance Lf in the IDHBC-TL converter is designed as 120 lH.

5.2.4

Comparisons of Rms Current in the Primary Switches

As seen in Fig. 5.1b, there is large circulating current in DHBC-TL DC–DC converter. The currents of the primary winding transformers and the switches in the IDHBC-TL converter are shown in Fig. 5.9a, b. As seen in Fig. 5.9a, ignoring the period of the duty cycle loss, vAB is positive and ip1 is positive during t0 to t4. At the same time, vCD is positive and ip2 is positive. It means the input source transmits energy to the output through Tr1 and Tr2. During t5 to t8, the output rectifier stage in the iDHBC-TL converter blocks the circulating current path in the primary circuit. ip1 decays to zero, and vAB is negative. Simultaneously, vCD is positive and ip2 still keeps positive. It illustrates that the circulating current in Tr1 during the freewheeling period is suppressed. Meanwhile, the input source still transmits energy to the output through Tr2. After t8, ip1 becomes negative. The input source starts to transmit energy through Tr1 again. Ideally, there is no circulating current in the primary circuit. Ignoring the output current ripple and duty cycle loss, the rms current in Q1 and Q4 for the IDHBC-TL converter is expressed as

5 Analysis and Evaluation of Dual Half-Bridge …

102

(a) vAB

Q2,Q3 on Q1,Q4 off

(b)

Q1,Q3 on Q2,Q3 Q2,Q4 on Q2,Q3 on Q2,Q4 off on Q1,Q3 off Q1,Q4 Q1,Q4 off off

DTs

iQ3

t0

(1-D)Ts

t4

(1-D)Ts

iQ2

vCD ip2

Q1,Q3 on Q2,Q3 Q2,Q4 on Q2,Q3 on Q2,Q4 off Q1,Q3 off on Q1,Q4 Q1,Q4 off off DTs

(1-D)Ts

DTs

ip1

iQ1

Q2,Q3 on Q1,Q4 off

(1-D)Ts

iQ4

DTs

t0

t8

t4

t8

Fig. 5.9 Currents in the primary winding of the transformers and the switches: a primary winding currents, b currents in the switches

iQ1 &Q4

rms

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZDTs   u Vo 2 Vo pffiffiffiffi u1 D ¼t dt ¼ Ts nRo nRo 0

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Vo 3  9  16nVo =Vin ¼ 4 nRo

ð5:16Þ

The rms current in Q2 and Q3 for the DHBC-TL converter is approximately evaluated as

iQ2&Q3

rms

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u Ts  u Z  u1 Vo 2 u ¼t dt Ts nRo Ts 2

ð5:17Þ

Vo ¼ pffiffiffi 2nRo Analyzed in the same manner, the rms current in Q1 and Q4 for IDHBC-TL converter is expressed as

iQ1&Q4

rms DHBC

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZDTs  rffiffiffiffiffiffiffiffi  u Vo 2 Vo pffiffiffiffi Vo nVo u1 D¼ ¼t dt ¼ Ts nRo nRo nRo Vin 0

ð5:18Þ

5.2 Analysis and Design Consideration of the Converter

103

The rms current in Q2 and Q3 is evaluated as

iQ2&Q3

rms DHBC

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1 u 0 Ts u 2 2 ZTs  u 1 B Z  Vo 2 Vo C ¼u dt þ dtA tT @ nR nR s o o DTs

Ts 2

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Vo pffiffiffiffiffiffiffiffiffiffiffiffi Vo nVo ¼ 1D¼ 1 nRo nRo Vin

ð5:19Þ

Fig. 5.10 Rms current of the switches versus the input voltage

Current stress of the switches (A)

Figure 5.10 shows the rms currents of the main switches in the DHBC-TL converter, and IDHBC-TL converter versus the input voltages for specifications n = 4 and Ro = 2.5 X. The current stress of the IDHBC-TL converter is lower than that of the DHBC-TL converter. As analyzed in Sect. 5.3a, the gain of the IDHBC-TL converter is larger than the DHBC-TL converter. Therefore, the duty cycle of the IDHBC-TL converter is lower than the DHBC-TL converter for the same conversion ratio. As seen in (5.11) and (5.12), the rms current in Q1 and Q4 is associated with the duty cycle. Therefore, Q1 and Q4 in the IDHBC-TL converter handle lower current than the DHBC-TL converter. As seen in Fig. 5.9a, b, the reduced circulating current causes the reduction of the current stress in Q2 and Q3. Therefore, compared with the DHBC-TL converter, the conduction loss is dramatically reduced in the IDHBC-TL converter. The conduction loss in the ITT-TL converter is analyzed in Chap. 4. The conduction loss in the primary circuit for different TL converters is expressed in Table 5.1, where RDS(on) is the turned on resistance of the MOSFETs, and VF is the voltage drop across the clamping diodes. According to the above analyses, the conduction loss of the primary switches and clamping diodes per unit with the specifications in Table 5.2 is shown in Fig. 5.11, where the normalized power is presented as ðVo =ðnRo ÞÞ2 . As seen in Fig. 5.11, the conduction loss in ITT-TL converter contains the switch conduction loss and clamping diode conduction loss.

Q2 and Q3 of the DHBC TL converter

Q2 and Q3 of the proposed converter Q1 and Q4 of the DHBC TL converter

Q1 and Q4 of the proposed converter

Vin (V)

5 Analysis and Evaluation of Dual Half-Bridge …

104

Table 5.1 Expression for conduction loss in the primary circuit Conventional TL converter Conduction loss Rms current in Q1 and Q4 ðiQ1&Q4 rms Þ Rms current in Q2 and Q3 ðiQ2&Q3 rms Þ Rms current in clamping diodes D1 and D2 ðiD1&D4 rms Þ

ITT-TL converter

Ppri con loss ¼ 2RDSðonÞ ði2Q1&Q4 qffiffiffiffiffiffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Vo nVo Vo 3nVo 1 nRo Vin nRo 2Vin  4 Vo nRo Vo nRo

qffiffi

DHBC-TL converter rms

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi V02 Vin2 Ts2 þ 1536L 2 2n2 R20 m2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Vo 2nVo 1  Vin 2nRo

1 2

qffiffiffiffiffiffiffiffiffiffiffiffiffi nVo 1 2  Vin

þ i2Q2&Q3 qffiffiffiffiffiffi Vo nRo Vo nRo

IDHBC-TL converter

rms Þ þ 2VF iD1&D2 rms

nVo Vin

qffiffiffiffiffiffiffiffiffiffiffiffiffiffi o 1  nV Vin

0

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

Vo nRo

3

916nVo =Vin 4

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 1þ

Vo nRo

916nVo =Vin 4

0

Table 5.2 Specifications in different converters Conventional TL converter

ITT-TL converter

DHBC-TL converter

IDHBC-TL converter

(on)

FDA18N50 (RDS = 0.265 X)

FDA18N50 (RDS (on) = 0.265 X)

FDA18N50 (RDS (on) = 0.265 X)

FDA18N50 (RDS (on) = 0.265 X)

Clamping diodes

DSEP12-12A (VF = 2.75 V, TJ = 25 °C)

DSEP12-12A (VF = 2.75 V, TJ = 25 °C)

–

–

n

4

4

4

4

Ro

2.5 X

2.5 X

2.5 X

2.5 X

Lm2

–

300 lH

–

–

Switches

Conduc tion loss in primary main switches (p.u.)

Fig. 5.11 Total conduction loss of the primary switches

Conventional TL converter

ITT-TL converter

DHBC-TL converter IDHBC-TL converter

Vin (V)

5.2 Analysis and Design Consideration of the Converter

105

In this occasion, the voltage drop across the clamping diode is larger than that across MOSFETs, which causes more conduction loss. In conventional TL converters, more circulating current flow through the clamping diodes during the freewheeling period, so it has the largest conduction loss among the above converters. Besides, the IDHBC-TL converter has the lowest conduction loss. Above all, DHBC-TL topology not only has the compact structure, but also has lower conduction loss due to the absence of the clamping diodes.

5.2.5

Ringing of the Rectifier Diodes

As seen in Fig. 5.3, the resonance between the leakage inductor and the junction capacitor of the diodes causes the ringing across the rectifier diodes. Large voltage spike may cause the breakdown of the diodes. The equivalent circuit at the secondary side of the transformers in Stage 4 is shown in Fig. 5.12a, where CDR3 and CDR4 are the junction capacitance of DR3 and DR4. The output filter inductor current is regarded as a constant current source. At the start of this stage, vDR3(0) = vDR4(0) = 0, is(0) = ILf, and iDR3(0) = iDR4(0) = 0. Assuming CDR3 = CDR4 = CD, vDR3(t), vDR4(t), and is(t) in the IDHBC-TL converter are expressed as 8 Vin nVo  cosðxn ðt  t3 ÞÞ > < vDR3 ðtÞ ¼ V n V ½1nV vDR4 ðtÞ ¼ nin  in n o cosðxn ðt  t3 ÞÞ qffiffiffiffi > : i ðtÞ ¼ I þ ðV  2nV Þ
C sinðx ðt  t ÞÞ s Lf in o n 3 Lk where xn ¼

ð5:20Þ

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  n2 4CD Lk . Therefore, ignoring the reverse recovery of the body

o diode, the maximum voltage of DR4 and DR1 is equal to 2Vin nV , and the maximum n

voltage of DR2 and DR3 is equal to

(a) Vin (1 − D ) 2n Vin D 2n Vin (1 − D ) 2n Vin D 2n

(b)

is 2

n (Lk1+Lk2) Tr1 Tr2 Tr1 vDR3 Tr2

2ðVin nVo Þ . n

C

vDR4DR3 CDR4

ILf

Vin 4n Vin 4n Vin 4n Vin 4n

The maximum voltage stress of DR2

(c)

is 2

n (Lk1+Lk2) Tr1 Tr2 Tr1 vDR3 C

DR3 Tr2 vDR4

CDR4

ILf

Vin (1 − D ) 2n Vin D 2n Vin (1 − D ) 2n Vin D 2n

is 2

n (Lk1+Lk2) Tr1 Tr2

ILf

Tr1 Tr2 vDR2 CDR2

Fig. 5.12 a Equivalent circuit of the secondary side in the IDHBC-TL converter for Stage 4, b equivalent circuit of the corresponding stage in ITT-TL converter, c equivalent circuit of the corresponding stage in DHBC-TL converter

5 Analysis and Evaluation of Dual Half-Bridge …

Fig. 5.13 Voltage stress of rectifier diodes versus input voltage

Voltage stress of rectifier diodes (V)

106

Voltage stress of rectifier diodes in DHBC-TL converter Voltage stress of DR1 and DR4 in ITT-TL converter

15.625V

12.5V

Voltage stress of DR1 and DR4 in IDHBC-TL converter Voltage stress of DR2 and DR3 in ITT-TL converter

25V

31.25V Voltage stress of DR2 and DR3 in IDHBC-TL converter

Vin (V)

and DR3 is lower than that of DR1 and DR4. Figure 5.12b shows the equivalent circuit of the corresponding stage for analyzing the ringing of the diodes in ITT-TL converter. Calculated in the same way, the voltage stress of DR4 and DR1 in ITT-TL 3Vin in converter is 7V 4n , and the voltage stress of DR2 and DR3 in ITT-TL converter is 2n . Figure 5.12c shows the equivalent circuit of the corresponding stage in DHBC-TL converter. Similarly, the voltage stress of the rectifier diodes in DHBC-TL converter is 2Vnin . Figure 5.13 shows the voltage stress of the rectifier diodes versus input voltages. As seen, the voltage stress of rectifier diodes in the IDHBC-TL converter is low than the other two converters. Therefore, the IDHBC-TL converter is more reliable.

5.3

Experimental Verifications

To verify the aforementioned analyses, a 1 kW experimental prototype is built. The detailed specifications are shown in Table 5.3. The controller of the converter is dual-loop controller, which contains outer voltage control loop and inner current control loop. The control loop keeps the output voltage track the voltage reference. The input voltage and load disturbance can be suppressed. Figure 5.14 shows the prototype used for the test. The experimental results are shown in Figs. 5.15, 5.16, 5.17, and 5.18. Figure 5.15 shows the key waveforms at different input voltages and output power. Figure 5.15a shows the experimental waveforms when input voltage is 550 V and the load power is 1000 W. Figure 5.15b shows the experimental waveforms when input voltage is 600 V and the load power is 1000 W. Figure 5.15c shows the experimental waveforms when input voltage is 550 V and the load power is 250 W. The current amplitudes of ip1 and ip2 are both reduced

5.3 Experimental Verifications

107

Table 5.3 Detailed specifications Items

Symbol

Parameter

Input voltage

Vin

550–600 V

Output voltage

Vo

50 V

Turns ratio of the transformers

N

4

Leakage inductors

Lk1, Lk2

15 lH

Input capacitors

Cd1, Cd2, Cd3, Cd4

20 lF

Primary switches

Q1, Q2, Q3, Q4

FDA18N50 (Coss(300V)  100 pF)

Rectifier diodes

DR1, DR4

FFH30US30DN (VF = 1 V, TJ = 25 °C)

DR2, DR3

MBR20200CT (VF = 0.9 V, TJ = 25 °C)

Output filter inductance

Lf

120 lH

Output filter capacitance

Co

220 lF

Fig. 5.14 Prototype of a 1 kW IDHBC-TL converter

with the decrease of the output power. As expected, circulating currents in the three mentioned cases are all reset to zero during the freewheeling period, which minimizes the conduction loss in the primary-side circuit. Figure 5.16 shows the output voltage of the rectifier stage. During the freewheeling period, the output voltage of the rectifier stage is larger than zero, which reduces the current ripple of the output filter inductor. Figure 5.17 shows current in Q2, and gate signal and drain-source voltage of switch Q2. Figure 5.17a shows ZVS of Q2 at heavy load. Figure 5.17b shows the ZVS of Q2 at light load. Before Q2 is turned on, the current in Q2 is negative. The junction capacitor of Q2 is discharged until the current flows through its body diode.

5 Analysis and Evaluation of Dual Half-Bridge …

108

(a)

Without circulating current

(b)

vAB

250V/div

vCD

250V/div

ip1

5A/div

ip2

5A/div

Time base:2μs/div

vAB

250V/div

vCD

250V/div

ip1

5A/div

ip2

Without circulating current

5A/div

Time base:2μs/div

(c)

vAB

250V/div

vCD

250V/div

ip1 Without circulating current

ip2 Time base:2μs/div

2A/div 2A/div

Fig. 5.15 Measured key waveform of the IDHBC-TL converter a at Vin = 550 V and P = 1000 W, b at Vin = 600 V and P = 1000 W, and c at Vin = 550 V and P = 250 W

Q3 works in the same mode as Q2. Figure 5.18 shows current in Q1, and gate signal and drain-source voltage of Q1. Figure 5.18a shows the ZVS of Q1 at the heavy load. Figure 5.18b illustrates the ZVS operation of Q1 at the light load. As seen in the experimental results, before Q1 is turned on, the current in Q1 is negative. The

5.3 Experimental Verifications

Freewheeling Period

109

vAB

250V/div

vCD

250V/div

vrec

50V/div

Time base:2μs/div Fig. 5.16 Output voltage of the rectifier stage

(a)

(b) iQ2 vgs2

5A/div

iQ2

1A/div

100V/div

vgs2

100V/div

vds2

vds2 10V/div

10V/div

Time base:2μs/div

Time base:2μs/div

iQ2

5A/div

vgs2

10V/div

vds2

ZVS

Time base:400ns/div

iQ2 vgs2 vds2

100V/div

ZVS

1A/div 10V/div 100V/div

Time base:400ns/div

Fig. 5.17 Current of Q2, and gate signal and drain-source voltage of switch Q2, a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 250 W

junction capacitor of Q1 is also discharged until the current flows through its body diode. Q4 works in the same mode as Q1. Therefore, ZVS for all the switches is achieved. Figure 5.19 shows the transient response to a step load change for 50% load to 100% load. The voltage across the DC-link capacitors is associated with the duty cycle of the converter. For the converter working in continuous current mode (CCM), the duty cycle varies in a narrow range with the load changes. Therefore, the voltages across the four DC-link capacitors do not fluctuate. As seen in Fig. 5.19, the converter has transient response during the step load change. Besides, the envelope curve of vAB and vCD almost does not change during the transient procedure. In order to compare the performance of the IDHBC-TL converter with other TL converters, the prototypes are built with specifications in Table 5.4. As shown in

5 Analysis and Evaluation of Dual Half-Bridge …

110

(a)

(b) 5A/div

iQ1

vds1

100V/div

vds1

Time base:2μs/div

10V/div

10V/div

Time base:2μs/div

5A/div

iQ1 vgs1

2A/div

iQ1 vgs1

10V/div

vds1

ZVS

2A/div

iQ1 vgs1

100V/div

vgs1

10V/div

vds1

100V/div

ZVS

Time base:400ns/div

100V/div

Time base:400ns/div

Fig. 5.18 Current of Q1, and gate signal and drain-source voltage of switch Q1 a at Vin = 550 V and P = 1000 W and b at Vin = 550 V and P = 250 W

Vo

50V/div

iLf

vAB vCD

10A/div 250V/div 250V/div

Time base:2ms/div Fig. 5.19 Transient response to a step load change for 50% load to 100% load

Table 5.4, due to the reduction of the output filter inductance, a smaller core can be used for designing the output filter inductor. The smaller core cannot only improve the power density. There are two transformers in the IDHBC-TL converter, but the output power is distributed in them. Without the clamping diodes and flying capacitors, the IDHBC-TL converter is more compact. Figure 5.20 shows the measured efficiency curves for the IDHBC-TL converter, DHBC-TL converter, ITT-TL converter, and conventional TL converter. The efficiency in the IDHBC-TL converter is larger than the other three converters. Figure 5.21 shows the calculated power loss distribution at rated load when Vin = 550 V. Due to the reduced circulating loss, the switches conduction loss and transformer copper loss is all reduced. Besides, the loss in clamping diodes causes more conduction loss in ITT-TL converter and the conventional TL converter. Due to the smaller core in magnetic components, the core loss in the IDHBC-TL

5.3 Experimental Verifications

111

Table 5.4 Specification of the converters Conventional TL converter

ITT-TL DC–DC converter

DHBC-TL DC– DC converter

IDHBC-TL converter

Main switches Clamping diodes Rectifier diodes

FDA18N50

FDA18N50

FDA18N50

FDA18N50

DSEP12-12A

DSEP12-12A

–

–

FFH30US30DN

FFH30US30DN

Input capacitors Flying capacitors Output filter inductance Output inductor core

400 V 20 lF 2ea 630 V 2.2 lF 1ea 160 lH

FFH30US30DN (DR1, DR4); MBR20200CT (DR2, DR3) 400 V 20 lF 2ea

250 V 20 lF 4ea

FFH30US30DN (DR1, DR4); MBR20200CT (DR2, DR3) 250 V 20 lF 4ea

250 V 20 lF 2ea

–

–

80 lH

160 lH

120 lH

Output inductor volume Transformer core

Kool Ml 77,195 (with 24 turns) 79,599 mm3

Kool Ml 77,715 (with 23 turns)

Kool Ml 77,195 (with 24 turns)

Kool Ml 77,715 (with 28 turns)

58,353 mm3

79,599 mm3

58,353 mm3

PQ50/50-3C95

Tr1

Tr1

Tr1

Tr2 Transformer volume

124,950 mm3

Tr1 Tr2

PQ35/ 35-3C95 PQ35/ 35-3C95 44,100 mm3 44,100 mm3

Fig. 5.20 Efficiency curves for different TL converters

Tr2 Tr1 Tr2

PQ35/ 35-3C95 PQ35/ 35-3C95 44,100 mm3 44,100 mm3

Tr2 Tr1 Tr2

PQ35/ 35-3C95 PQ35/ 35-3C95 44,100 mm3 44,100 mm3

5 Analysis and Evaluation of Dual Half-Bridge …

Power loss (W)

112

Fig. 5.21 Calculated power loss distribution at rated load when Vin = 550 V

converter is less than the conventional one. In rectifier stage, the voltage drop across DR2 and DR3 is less than that across DR1 and DR4. Therefore, the conduction loss in rectifier stage is less than that in conventional TL converter and DHBC-TL converter. The calculation loss distribution for different TL converters illustrates that the conduction loss in the IDHBC-TL converter is lower than the others, especially for the switches conduction loss, the clamping diode conduction loss, the transformer copper loss, and the rectifier diode conduction loss.

5.4

Conclusion

In this chapter, an improved DHBC-TL DC–DC converter by reducing the circulating current and output filter inductance is introduced for higher efficiency. Two half bridges are cascaded in series to form a TL structure, so the switches only undergo half of the input voltage. The two transformers in the IDHBC-TL converter distribute the load power. The rectifier stage of the converter consists of four diodes cooperating with the proper sequence of the secondary windings. Because of the presented rectifier circuit, the circulating currents at the primary windings are suppressed in the IDHBC-TL structure, reducing the conduction loss in the primary switches and the primary windings. Furthermore, the switches achieve ZVS despite the reduced circulating current. Besides, the output filter inductance is reduced. The performance of the IDHBC-TL converter is compared with the some other TL converters. The IDHBC-TL converter not only has the compact structure, but also

5.4 Conclusion

113

has higher efficiency. In the end, the good characteristic and performance of the IDHBC-TL converter and design method have been verified by a 1 kW experimental prototype.

References 1. Lin B, Cheng P (2014) New ZVS DC–DC converter with series-connected transformers to balance the output currents. IEEE Trans Power Electron 29(1):246–255 2. Kim D, Kim J, Moon G (2013) A three-level converter with reduced filter size using two transformers and flying capacitors. IEEE Trans Power Electron 28(1):2140–2150 3. Lin B, Chung S (2014) New parallel ZVS converter with less active switches and smaller output inductance. IEEE Trans Power Electron 29(7):3297–3307 4. Shi Y, Yang X (2014) Wide-range soft-switching PWM three-level combined DC–DC converter without added primary clamping devices. IEEE Trans Power Electron 29(10): 5157–5171 5. Baggio JE, Hey HL, Gründling HA, Pinheiro H, Pinheiro JR (2003) Isolated interleaved-phase-shift-PWM DC–DC ZVS converter. IEEE Trans Ind Appl 39(6):1795–1802 6. Guo Z, Sun K, Sha D (2016) Improved ZVS three-level DC–DC converter with reduced circulating loss. IEEE Trans Power Electron 31(9):6394–6404 7. Deschamps E, Barbi I (1998) A comparison among three-level ZVS-PWM isolated DC-to-DC converters. In: Proceedings of IEEE IECON, pp 1024–1029 8. Narimani M, Moschopoulos G (2013) A new DC/DC converter with wide-range ZVS and reduced circulating current. IEEE Trans Power Electron 28(3):1265–1273

Chapter 6

Output-Series-Connected Dual Active Bridge Converters for Zero-Voltage Switching Throughout Full Load Range by Employing Auxiliary LC Networks

Abstract This chapter presents an output-series-connected dual active bridge (DAB) converter for efficient zero-voltage switching (ZVS) by employing dual auxiliary LC networks in high output voltage applications. The dual auxiliary LC networks are integrated into the converter for zero-voltage switching (ZVS) throughout full load range. The gate signals of the output-side switches can control the current in the LC networks. By analyzing the working modes of the converter, the modulation trajectory is designed in terms of the boundaries of the ZVS range. The conduction loss caused by the auxiliary LC networks is adjusted according to the voltage and load power. The modulation scheme can achieve seamless transition between the adjacent working modes. The conduction loss of the presented converter is compared with the conventional output-series dual active bridge converter. Although the conduction loss is increased under light loads, all the switches can achieve ZVS. The reduced switching loss can improve the overall efficiency. Finally, a 1.3 kW experimental prototype was built to verify the effectiveness of the converter and the modulation scheme, which demonstrates the ZVS performance and efficiency improvement. Keywords Output-series Zero-voltage switching

6.1


Dual active bridge
Auxiliary LC networks


Working Modes of the Presented DAB Converter

In order to meet high DC-link voltage requirement, the three-level or series-connected topologies permit low-voltage rating switches to be used in this situation. A three-level DAB converter in different working modes is used in 1 kV DC bus voltage [1]. However, the converter still works in two-level modulation. Clamping diodes and flying capacitors have to be used to decouple the voltage stress of the outer and inner switches. Although the conduction loss is optimized in different operation modes, the switches still work in hard switching. A neutral-point clamped DAB converter is developed to improve the efficiency and balance the © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_6

115

6 Output-Series-Connected Dual Active Bridge Converters …

116

Vbat

Ci

i2

Tr1 C

A B

D 1:n

Q4

Q2

Q7

Q5

Q3 Lr

Q1

Q3

Q6

Q8

Q9

Q11

Co1

Vo

Tr2 A

Lr

F Co2

E B Q4

1:n

Q10

Q12

Fig. 6.1 Input-parallel output-series dual active bridge converter

capacitor voltages [2]. However, the complicated modulation still cannot guarantee wide ZVS. In [3], a high-voltage DAB converter with series-connected half bridges is used in the high-voltage side. Likewise, Fig. 6.1 shows the input-parallel output-series DAB converter suitable for high output DC-link voltage [4]. By sharing the switches in battery side, the output-series dual active bridge (OSDAB) converter can be derived in Fig. 6.2. Compared with the three-level DAB converter, output-series DAB converter is more flexible in high-voltage applications.

Vbat

Ci Q2

Q7

Q5

Q3 Lr

Q1

i2

Tr1 C

A B Q4

D 1:n

Q6

Q8

Q9

Q11

Co1

Vo

Tr2 F

Co2

E 1:n

Q10

Fig. 6.2 Output-series dual active bridge (OSDAB) converter

Q12

6.1 Working Modes of the Presented DAB Converter

Vbat

Ci Q2

A

Q7

Q5

Q3 Lr

Q1

117

Tr1

i2

i1 B Q4

Auxiliary LC networks

i3

1:n1 is1

C D

is2 Q6

Ls1

Ls2

Cs1

Cs2 Q9

Co1

Q8 Q11

Vo

Tr2 F

i4 1:n2

i5

Co2

E Q10

Q12

Fig. 6.3 Output-series dual active bridge converter with dual auxiliary LC network

In this chapter, an output-series DAB converter with dual auxiliary LC networks (OSDAB with LC) is introduced in order to achieve ZVS throughout full load range. Figure 6.3 shows the topology of the OSDAB converter with LC. Vbat is the battery voltage. On the battery side, the power stage is a full bridge. On the output side, the power stage is composed of two full bridges, whose outputs are connected in series. Co1 and Co2 are the output capacitors. The output voltage is Vo. There are two transformers. Their turns ratio is 1:n1 and 1:n2, respectively, where n1 and n2 are equal to n. Lr is the series inductance. The three full bridges are linked with series inductor and two transformers. In the two transformers, the two windings in the battery side are connected in parallel. The power transmitted from the battery to the output is defined as the forward power flow, conversely, is defined as the reverse power flow. Ls1, Ls2, Cs1, and Cs2 constitute two auxiliary LC networks used to achieve wide ZVS. Taking the forward power flow into consideration, the converter can work in four modes, which are shown in Fig. 6.4. The gate signals for Q1  Q12 are 50% duty cycle. As shown in Fig. 6.4, some switches are driven by the same gate signals. vAB is the output voltage of the battery-side full bridge. D1 is its effective duty cycle. Ts is the switching period. vCD and vEF are controlled by the phase shift of the two output-side full bridges, and their waveforms are symmetrical in the horizontal coordinates. u is the phase shift between vAB and vCD. Δu is the phase shift between Q8 and Q5. ua is equal to u  Du=2, and ub is equal to u þ Du=2. ua and ub are illustrated in Fig. 6.4. Due to the symmetry of the forward and reverse power flows, there are also four working modes in reverse power flow. In terms of the range of ua and ub, the boundary conditions of the working modes

6 Output-Series-Connected Dual Active Bridge Converters …

118

(a)

Q1

Q1

Q2

Q3

Q4

Q3

Q6 & Q9

Q5 & Q10

Q6 & Q9

Q7 &Q12

Q8 & Q11

Q 7 & Q12

vAB

φb

vCD

φa ∆φ

Q4

Q8 & Q11

D1 Ts /2

φ Vo /2

Vo /2 Vo /2

vEF

Vo /2

Vo /2

v CF & vDE

Vo /2

is1 &is2 i1

i2 & i5 i3 & i4 t0 t1 t2

(b)

t3

t4

Q1

Q4

Q6 & Q9 Q7 &Q12

vAB

φb

vCD

φa ∆φ

Q1

Q2

Q3

Q3

Q5 & Q10

Q6 & Q9

Q 8 &Q 11

Q 7 & Q 12

Q4

Q 8 &Q 11

D1 T s /2

φ V o /2 V o /2 V o /2

vEF

V o /2

v CF & vDE is1 & is2

i1 i2& i5 i3& i4 t0 t1 t2

t3

t4

Fig. 6.4 Working modes in forward power flow: a Mode 1a, b Mode 2a, c Mode 3, and d Mode 4

6.1 Working Modes of the Presented DAB Converter

(c)

Q1

Q1

Q2

Q3

Q4

Q6&Q9

Q3

Q5&Q10

Q4

Q6&Q9 Q8&Q11

Q7&Q12

Q8&Q11

Q7&Q12

119

Q5&Q10 D 1 T s /2

vAB φa

vCD

φb

φ Vo/2

∆φ

vEF

Vo/2 Vo/2

Vo/2

vCF &vDE is1&is2 i2 &i5 ii13 &i4

t3

t0 t1 t2

(d)

Q2

Q1

Q3

Q4

Q6&Q9 Q7&Q12

Q2

Q1

Q3

Q4

Q5&Q10

Q6&Q9

Q5&Q10

Q8&Q11

Q7&Q12

Q8&Q11

D1 Ts /2

vAB vCD

t4

φb -φa ∆φ

φ Vo /2 Vo /2 Vo /2

vEF

Vo /2

vCF &vDE is1&is2 i1 i2 &i5 i3 &i4 t0 t1 t2 t3 Fig. 6.4 (continued)

t4

Mode 4

Mode 3

Mode 2a

Mode 2b

Working mode Mode 1b

1 2

 D21  upa  upb  12

  12  D21  upa  12  D21  upb  12

  12  D21  upa  upb  12  D21

 ua ub D1 D1 1 1 p   2  2 0 2  2  p

Reverse power flow

Working mode Mode 1a

Boundary condition

Forward power flow

Table 6.1 Boundary condition for each mode

 12 

ua p ua p

ub p


   12  D21
1 D  ub
1 D    2  21  p  2  21 

Boundary condition  12 

120 6 Output-Series-Connected Dual Active Bridge Converters …

6.1 Working Modes of the Presented DAB Converter

121

are shown in Table 6.1. Mode 1a and Mode 1b are the symmetrical working modes, and Mode 2a and Mode 2b are the symmetrical working modes. Mode 3 and Mode 4 are the common working modes in both forward and reverse power flows. Only forward power flow will be analyzed in this chapter. The same conclusion can be drawn for reverse power flow by using the same method. As seen, vCF and vDE are voltages across the two LC networks, which are larger than zero. The capacitances of Cs1 and Cs2 are large enough to filter out the DC voltage offset, which guarantees that the average currents in Ls1 and Ls2 are equal to zero. The voltages across Cs1 and Cs2 are Vo/2. The phase-shift angle Δu can control the current in the auxiliary LC networks. Δu is small value. Otherwise, there is large current in the LC networks, which degrades the efficiency. Therefore, D1 can only be regulated in a wide range to meet the voltage-second balance across the both sides of the transformers. In this case, the converter can be modulated by EPS. In order to meet voltage-second balance across  the both  sides of the transformer, the converter should meet nVbat D1 ¼ V2o 1  Du  V2o . Therefore, the p

effective voltage gain meets the condition: M ¼ Vo =nVbat ¼ 2D1  2. The turns ratio of the transformer should be designed in consideration with the minimum battery voltage. The turns ratio of the transformer can be designed as n ¼ Vo =2Vbat min , where Vbat_min is the minimum battery voltage. Assuming Ls1 = Ls2 = Ls, Cs1 = Cs2 = Cs, and is1 = is2 = is, and defining Xr ¼ 2p Lr =Ts and Xs ¼ 2p Ls =Ts , the currents in converter meet the following conditions. 

i1  is i2 ¼ i5 ¼ 2n i1 i3 ¼ i4 ¼ 2n þ is

ð6:1Þ

Ignoring the dead time of the gate signals, there are four working stages for each working mode in half of the switching period. To explain, the working stages in Mode 1a are shown in Fig. 6.5. Stage 1 ([t0, t1]) (Fig. 6.5a): Prior to t0, Q1, Q3, Q6, Q7, Q9, and Q12 are on, and Q2, Q4, Q5, Q8, Q10, and Q11 are off. At t0, Q3 is switched off and i1 is negative. The junction capacitor of Q4 is discharged, and Q4 is turned on with ZVS. i1 is increased, and is1 and is2 are positive. The currents in this stage are expressed as 

i1 ðtÞ ¼ i1 ðt0 Þ þ is ðtÞ ¼ is ðt0 Þ

Vbat þ Vo =ð2nÞ ðt Lr

 t0 Þ

ð6:2Þ

Stage 2 ([t1, t2]) (Fig. 6.5b): At t1, Q7 and Q12 are turned off. Because i3 and i4 are positive at this time; the junction capacitors of Q8 and Q11 start to be discharged. Until the voltage across Q8 and Q11 reach zero, Q8 and Q11 are turned on with ZVS. i1 is still increased, while is1 and is2 start to decrease. The currents in this stage are expressed as

6 Output-Series-Connected Dual Active Bridge Converters …

122

(a)

Vbat

A

Ci

Tr1

i2

i1 B Q4

Q2

Q7

Q5

Q3 Lr

Q1

i3

C D

1:n

is1

is2 Q6

Ls1

Ls2

Cs1

Cs2 Q9

Co1

Q8 Q11

Vo

Tr2 F

i4 1:n

i5

Co2

E Q10

Q12

Q5

Q7

(b) Q3 Lr

Q1

Vbat

A

Ci

Tr1

i1 B

Q2

i2

Q4

C

i3

D

1:n

is1

is2 Q6

Ls1

Ls2

Cs1

Cs2 Q9

Co1

Q8 Q11

Vo

Tr2 F

i4 1:n

Co2

E

i5

Q10

Q12

Q5

Q7

(c) Q3 Lr

Q1

Vbat

Ci Q2

A

Tr1

i2

i1 B Q4

i3

C D

1:n

is1

is2 Q6

Ls1

Ls2

Cs1

Cs2 Q9

Co1

Q8 Q11

Vo

Tr2 F

i4 1:n

i5

Co2

E Q10

Q12

Fig. 6.5 Topological stages with half-switching period in Mode 1a: a [t0, t1], b [t1, t2], c [t2, t3], and d [t3, t4]

6.1 Working Modes of the Presented DAB Converter

123

(d)

Vbat

Ci

A

i2

Tr1

i1 B Q4

Q2

Q7

Q5

Q3 Lr

Q1

i3

C D

1:n

is1

is2 Q6

Ls1

Ls2

Cs1

Cs2 Q9

Co1

Q8 Q11

Vo

Tr2 F

i4 1:n

i5

Co2

E Q10

Q12

Fig. 6.5 (continued)

(

i1 ðtÞ ¼ i1 ðt1 Þ þ VLbatr ðt  t1 Þ Vo ðt  t1 Þ is ðtÞ ¼ is ðt1 Þ  2L s

ð6:3Þ

Stage 3 ([t2, t3]) (Fig. 6.5c): At t2, Q6 and Q9 are turned off. i2 and i5 are positive and large enough, so the junction capacitors of Q5 and Q10 are discharged. Until the voltage across Q5 and Q10 reach zero, Q5 and Q10 are turned on with ZVS. In this stage, the energy starts to transmit from the battery side to the output side. The currents in this stage are expressed as 

i1 ðtÞ ¼ i1 ðt1 Þ þ is ðtÞ ¼ is ðt2 Þ

Vbat Vo =ð2nÞ ðt Lr

 t2 Þ

ð6:4Þ

Stage 4 ([t3, t4]) [Fig. 6.5d]: At t4, Q1 is turned off. The current in the primary side of the transformer will charge and discharge the junction capacitors of Q1 and Q2. When the voltage across Q1 reaches zero and the voltage across Q2 reaches Vbat, Q2 is turned on with ZVS. The currents in this stage are expressed as 

i1 ðtÞ ¼ i1 ðt1 Þ  Vo =Lðr2nÞ ðt  t3 Þ is ðtÞ ¼ is ðt3 Þ

ð6:5Þ

According to (6.1)–(6.5), currents i1, i2, i3, i4, i5 at the time of t0, t1, t2, and t3 can be derived. The working stages in Mode 2a, Mode 3, and Mode 4 can be analyzed in the same method. The key feature of the working modes will be analyzed in accordance with these currents.

6 Output-Series-Connected Dual Active Bridge Converters …

124

6.2 6.2.1

Key Feature and Modulation Scheme of the Converter ZVS Analyses for Q1–Q4

Because of the symmetry in two halves of the switching period, the ZVS conditions for Q1 and Q2 are the same, and the ZVS conditions for Q3 and Q4 are the same. Therefore, ZVS performance of Q1 and Q4 will be analyzed, and Q3 and Q2 work in the same condition. In order to achieve ZVS for Q1 and Q4, i1 should be negative and large enough, i.e., i1   IZVS1 , where IZVS1 is the minimum current to charge or discharge the junction capacitors during the dead time for ZVS of Q1–Q4. IZVS1 is associated with Coss (output capacitance) of the switches. The proximate evaluation of IZVS1 can be expressed as Vbat CossðQ1Q4Þ =tdead , where tdead is the dead time of the switches. According to i1 at the commutation time, the ZVS boundaries of Q1 and Q4 in different working modes are shown in Table 6.2. Ibase is defined as the normalized current, where Ibase ¼ VnLo Trs . Taking Mode 2a, for example, if D1 is equal to     Du Vo ¼ M2 1  Du 2nVbat 1  p p , the key waveform of i1 is shown in Fig. 6.6a. When Therefore,Q4 works Q4 is turned on, i1 is equal  to zero.   in hard switching. If D1 is

Du M set to be larger than M2 1  Du p , i.e., D1 ¼ 2 1  p þ Dm , the key waveform of

Q4 i1 is shown in Fig. 6.6b. When Q4 is turned on, i1 is less than zero. Therefore,  Du M has the potential to achieve ZVS. Substituting D1 ¼ 2 1  p þ Dm into Table 6.2, the ZVS conditions for Q1 and Q4 are shown in Table 6.3. The ZVS conditions for Q1 and Q4 in different modes can be synthesized to the same. As long Dm 4Lr IZVS1 as Ibase 4M  IZVS1 , i.e., Dm  Vbat Ts , Q1 and Q4 can guarantee ZVS in all the working modes. Dm is designed as

6.2.2

4Lr IZVS1 Vbat Ts

in the following analyses and converter design.

ZVS Analyses for Q5–Q12

Because of the symmetry in two halves of the switching period, the ZVS conditions for Q5, Q6, Q9, and Q10 are the same, and the ZVS conditions for Q7, Q8, Q11, and Q12 are the same. Therefore, the ZVS conditions for Q5 and Q10 and Q8 and Q11 will be analyzed in half of the switching period. The commutations during the dead time for Q5 and Q10 and Q8 and Q11 are shown in Fig. 6.7. To achieve ZVS of Q5 and Q10 and Q8 and Q11, i2, i5, i3, and i4 should be positive and large enough, i.e., i2 ¼ i5  IZVS2 and i3 ¼ i4  IZVS2 , where IZVS2 is the minimum current to charge and discharge the junction capacitor for ZVS of Q5–Q12 during the dead time. The proximate evaluation of IZVS2 can be expressed as Vo CossðQ5Q12Þ =2tdead . The ZVS constraints on Q5 and Q10 and Q8 and Q11 are shown in Table 6.4.

ZVS for Q4

ZVS for Q1

ZVS for Q4

ZVS for Q1

ua 8 1þ p 1
Ibase 8 1 þ upa

i1 ðt2 Þ ¼

i1 ðt1 Þ ¼ Ibase

1


 D 1  upb  4M   IZVS1  ub  D1  p  4M   IZVS1

Mode 4

Mode 3

D
 1 i1 ðt3 Þ ¼ Ibase 4M  18 D1  upa  upb   IZVS1 
 D 1 i1 ðt2 Þ ¼ Ibase 18 D1 þ upb þ upa  4M   IZVS1

Mode 2a D
 1 i1 ðt3 Þ ¼ Ibase 4M þ 18 D1  upa  upb   IZVS1 
 D 1 i1 ðt1 Þ ¼ Ibase 18 1 þ upa  upb  4M   IZVS1


 D 1 i1 ðt3 Þ ¼ Ibase 18 upa þ upb  D1 þ 4M   IZVS1 1
  ua ub D1 i1 ðt0 Þ ¼ Ibase 8 2  p  p  D1  4M   IZVS1

Mode 1a

Table 6.2 ZVS conditions for Q1 and Q4

6.2 Key Feature and Modulation Scheme of the Converter 125

6 Output-Series-Connected Dual Active Bridge Converters …

126

(b)

(a) Q4 is turned on

D1 =

vAB vCD&vFE

M 2

⎛ Δϕ ⎞ ⎜1 − π ⎟⎠ ⎝

Q4 is turned on

vAB vCD&vFE

i1

M ⎛ Δϕ ⎞ ⎜1 − π ⎟⎠ 2 ⎝ Dm

i1

Fig. 6.6 Key waveforms of Mode 2a with specific duty cycle: a D1 = M(1 − Du/p)/2 and b D1 = M(1 − Du/p)/2 + Dm

To achieve ZVS of Q5, Q10, Q8, and Q11 in all the working modes, the following conditions should be satisfied: 1. As shown in Table 6.4 of Mode 1a, the ZVS boundary of Q5 and Q10 is rewritten as Du 



1 IZVS2 ðM  2Þp u   ¼ Dud M M2 nV 8n2 Xr 2n2 Xr bat 4Xs  8n2 Xr

ð6:6Þ

2. In Mode 1a, the ZVS boundary of Q8 and Q11 is rearranged as

1 IZVS2 ðM  2Þp u Du  M M þ 2   2 ¼ Due 8n2 Xr 2n Xr nVbat 4Xs  8n2 Xr

ð6:7Þ

Comparing (6.6) with (6.7), Δue is greater than Δud. Therefore, as long as (6.7) is satisfied, (6.6) must be satisfied. 3. As shown in Table 6.4, the ZVS boundary of Q5 and Q10 in Mode 2a is the same as that in Mode 1a, which is expressed as (6.6). 4. The ZVS boundary of Q8 and Q11 in Mode 2a is rewritten as  4Xs Dm p Du  IZVS2 þ 2 8n Xr Vo

ð6:8Þ

It is independent of u. 5. The ZVS constraints on Q5–Q12 in Mode 3 are the same as Q8 and Q11 in Mode 2a, which is expressed as (6.8). 6. The ZVS boundary of Q5 and Q10 in Mode 4 is the same as that in Mode 1a. 7. The ZVS boundary of Q8 and Q11 in Mode 4 is rearranged as

ZVS for Q4

ZVS for Q1

ZVS for Q4

ZVS for Q1



1 2ua Dm þ 1  D1 þ i1 ðt3 Þ ¼ Ibase 8 p 4M Ibase Dm    IZVS1 4M

1 2u Dm 1  D1  a  i1 ðt0 Þ ¼ Ibase 8 p 4M Ibase Dm    IZVS1 4M Mode 3 

1 2ua Dm þ 1  D1  i1 ðt3 Þ ¼ Ibase 8 p 4M Ibase Dm    IZVS1 4M 

1 2u Dm 1  D1  b þ i1 ðt2 Þ ¼ Ibase 8 p 4M Ibase Dm    IZVS1 4M

Mode 1a

Table 6.3 Derived ZVS conditions for Q1 and Q4 

1 2ua Dm þ 1  D1 þ 8 p 4M Ibase Dm    IZVS1 4M Ibase Dm i1 ðt1 Þ ¼  4M   IZVS1

i1 ðt1 Þ ¼ 

i1 ðt1 Þ ¼ 

Mode 4

Ibase Dm   IZVS1 4M

Ibase Dm   IZVS1 4M

i1 ðt3 Þ ¼ Ibase

Mode 2a

6.2 Key Feature and Modulation Scheme of the Converter 127

6 Output-Series-Connected Dual Active Bridge Converters …

128

(b)

(a) i1/2n i1/2n

i3

is1

is2 Q6

Ls1

Ls2

Cs1 i1/2n i1/2n

Q7

Q5

i1/2n

i2 C D Q8

F

i4

Co2

E Q10

i1/2n

Q12

i3

is1

is2

Ls1

Ls2

Cs1 i1/2n

Q11

Cs2 Q9

i5

Co1

i1/2n

Q7

Q5 i2 C

D

Q6

Q8

Cs2 Q9

Q11 F

i4 i5

Co1

Co2

E Q10

Q12

Fig. 6.7 Commutations during the dead time for Q5 and Q10 and Q8 and Q11: a Q5 and Q10, b Q8 and Q11

Du 



1 IZVS2 ðM  2Þp u  þ MTs M2 nV 8n2 Xr 2n2 Xr bat 4Xs  8n2 Xr

ð6:9Þ

As long as (6.9) is true, (6.6) must be satisfied. Above all, the ZVS boundary of Q5–Q12 can be synthesized to (6.7) in Mode 1a, (6.6) and (6.8) in Mode 2a, (6.8) in Mode 3, and (6.9) in Mode 4.

6.2.3

Modulation Trajectory

In terms of the analyses of the ZVS boundaries of Q5–Q12, the ZVS range can be calculated with specific parameters. Figure 6.8 shows the three-dimensional surface of the ZVS boundary versus Vbat and u, where Lr = 24 lH, Ts = 12.5 ls, Ls = 22 lH, n = 1.5, Izvs1 = 2 A, Izvs2 = 2 A, and Vo = 600 V. The vertical axis is Δu. The space above the surface is the ZVS area, and the space below the surface is hard switching area. Figure 6.9 shows the ZVS range of Q5–Q12 with different battery voltages. Figure 6.9 is the vertical section of Fig. 6.8. The shadowed area in Fig. 6.9 is the ZVS range for Q5–Q12. As seen, with the increase of the battery voltage, the converter becomes more difficult to achieve ZVS. By using the currents in the auxiliary LC networks, i.e., Δu is large enough, and the converter can guarantee ZVS of Q5–Q12. However, it will cause more conduction loss with large

i2 ðt1 Þ ¼ i5 ðt1 Þ 

Du 1 D1 nLr Du  ¼ Ibase 1  þ p 16n 8nM 8Ls p  Dm nLr Du ¼ Ibase   IZVS2 þ 8nM 8Ls p

i3 ðt0 Þ ¼ i4 ðt0 Þ 

Du 1 D1 nLr Du  þ ¼ Ibase 1  p 16n 8nM 8Ls p  Dm nLr Du ¼ Ibase   IZVS2 þ 8nM 8Ls p

ZVS for Q8 and Q11

Mode 3

 IZVS2

 

Du 1 2u Du 1 nLr Du þ  1 þ i3 ðt1 Þ ¼ i4 ðt1 Þ ¼ Ibase 1  p 16n p p 8nM 8Ls p  

1 2 1 u nLr 1 1 Du ¼ Ibase 1 þ þ   16n M 4nM p 8Ls 16n 8nM p

 IZVS2

 Du 1 i2 ðt2 Þ ¼ i5 ðt2 Þ ¼ Ibase 1  p 16n 

2u Du 1 nLr Du þ þ 1 þ p p 8nM 8Ls p  

1 2 1 u nLr 1 1 Du ¼ Ibase 1 þ þ þ  16n M 4nM p 8Ls 16n 8nM p

Mode 1a

ZVS for Q5 and Q10

ZVS for Q8 and Q11

ZVS for Q5 and Q10

Table 6.4 ZVS conditions for Q5 and Q10 and Q8 and Q11

 IZVS2

i3 ðt0 Þ ¼ i4 ðt0 Þ  

Du 1 2u Du 1 nLr Du  1þ  þ ¼ Ibase 1  p 16n p p 8nM 8Ls p  

2 1 1 u nLr 1 1 Du ¼ Ibase 1   þ þ  M 16n 4nM p 8Ls 16n 8nM p

 IZVS2

i2 ðt3 Þ ¼ i5 ðt3 Þ  

Du 1 2u Du 1 nLr Du þ þ 1 þ ¼ Ibase 1  p 16n p p 8nM 8Ls p  

1 2 1 u nLr 1 1 Du ¼ Ibase 1 þ þ þ  16n M 4nM p 8Ls 16n 8nM p

i3 ðt0 Þ ¼ i4 ðt0 Þ 

Du 1 D1 nLr Du  ¼ Ibase 1  þ p 16n 8nM 8Ls p  Dm nLr Du ¼ Ibase   IZVS2 þ 8nM 8Ls p Mode 4

 IZVS2

 Du 1 i2 ðt2 Þ ¼ i5 ðt2 Þ ¼ Ibase 1  p 16n 

2u Du 1 nLr Du  1  þ p p 8nM 8Ls p  

1 2 1 u nLr 1 1 Du ¼ Ibase 1 þ þ þ  16n M 4nM p 8Ls 16n 8nM p

Mode 2a

6.2 Key Feature and Modulation Scheme of the Converter 129

6 Output-Series-Connected Dual Active Bridge Converters …

130

Fig. 6.8 Three-dimensional (3D) surface of the ZVS boundary versus Vbat and u

(a)

(b)

(c)

b

b

a

b

b

M M'

a

b

a

M

M M'

M'

m

m m

P'

N'

N

P

P'

N'

N

P

P' N'

N

P

Fig. 6.9 ZVS range and modulation trajectory for different battery voltages: a Vbat = 200 V, b Vbat = 250 V, and c Vbat = 300 V

Δu. In order to achieve ZVS with low conduction loss, the modulation trajectory should be designed according to the boundary conditions analyzed in Sect. 6.2.2. The designed modulation trajectory is the red solid line shown in Fig. 6.9.

6.2 Key Feature and Modulation Scheme of the Converter

131

In (6.7), setting Δue = 0, u is calculated as u¼

2nIZVS Xr p  ðM  2Þ ¼ un 4 Vbat

ð6:10Þ

The coordinate of the point N in Fig. 6.9 is expressed as (un, 0), which varies with the battery and output voltages. The point M is on the boundary condition between Mode 1a and Mode 2a, which is expressed as 

1 M 2u þ þ Dm  1 p Du ¼ 1 þ M=2 2

ð6:11Þ

Then, in terms of (6.7) and (6.11), the coordinate of the point M in Fig. 6.9 is expressed as (um, Δum), where



8 IZVS M2 p p > >  u ¼ X ð 1 þ 2=M Þ   ð  1 Þ M þ D > m s m < 2Xs ð1 þ 2=M Þ 4n2 Xr nVbat 8n2 Xr

> IZVS ð1  2=M Þp p > > : Dum ¼ 4Xs M þ D  þ ð  1 Þ m 8n2 Xr 4n2 Xr M Vo ð6:12Þ Point M also varies with the battery and output voltages. Therefore, the line MN in Fig. 6.9 is expressed as Du ¼

Dum ðu  un Þ um  un

ð6:13Þ

The modulation trajectory can be illustrated as a flowchart shown in Fig. 6.10. The control diagram is shown in Fig. 6.11. As shown in Fig. 6.11, the output voltage is controlled by a PI controller. The output of the PI controller is the phase-shift angle u. As shown in the flowchart in Fig. 6.10, Δu is calculated in accordance with u. Then, the gate signals of Q1–Q12 are generated in terms of D1, u, Δu. As shown in (6.10) and (6.12), the turning points of the modulation trajectory are associated with Lr and Ls. Due to the manufacture and nonlinearity of the inductor, Lr and Ls may not be equal to their nominal values, which may make the points M and N deviate away from their set points. However, point M is still located on the boundary condition between Mode 1a and Mode 2a, and point N is still located on the horizontal axis. As long as points M and N are located in the shadowed area of Fig. 6.9, the modulation scheme for ZVS is still effective and not very sensitive to the parameter of Lr and Ls. According to the modulation trajectory and closed-loop control diagram, D1 versus phase-shift angle and battery voltage is shown in Fig. 6.12. As depicted in Fig. 6.12, D1 can seamlessly transit between the adjacent working modes. The output power expressions in different working modes are shown in Table 6.5. The output power in different working modes is not associated with the

6 Output-Series-Connected Dual Active Bridge Converters …

132

φm,φn ∆φm

Calculate

Determine φ in terms of the control loop in Fig.6.11, where -π/2 φ π/2 . No Yes (Mode 1a) Yes

∆φ=0

φ φn

-φm

Δϕ = Δϕm (ϕ − ϕ n ) ϕm − ϕn

Yes

φm

No (Mode 1b)

φ φm

No

φ

Yes

φ - φn

∆φ=0

No

Δϕ = −Δϕm (ϕ + ϕ n ) ϕm − ϕn

∆φ=∆φm

Return Fig. 6.10 Flowchart of the modulation trajectory

Fig. 6.11 Closed-loop control diagram

Vref

PI Vo

φ

Modulation D1 trajectory shown ∆φ Q -Q PWM 1 12 in Fig.6.10

parameters of the LC networks, which demonstrates that the LC networks have no impact on the output voltage performance. The output power versus the phase-shift angle and battery voltage in per unit (p. u.) is shown in Fig. 6.13, where Lr = 24 lH, Ts = 12.5 ls, Ls = 22 lH, n = 1.5, Izvs1 = 2 A, Izvs2 = 2 A, and Vo = 600 V. Figure 6.13a shows the relationship among output power, battery voltage, and phase shift in three dimensions. Figure 6.13b is the right lateral view of Fig. 6.13a. In the range of u from −p/2 to p/2, the output power is monotonically increasing. Figure 6.13c shows the curves of the output power versus the phase-shift angle. It illustrates that the converter can achieve seamless transition between the adjacent working modes, which demonstrates that the bidirectional power flow can be controlled by the phase-shift angle.

6.2 Key Feature and Modulation Scheme of the Converter

133

Fig. 6.12 D1 versus phase-shift angle u and battery voltage Vbat

Table 6.5 Output power expressions in different working modes Working mode Mode 1a Mode 2a Mode 3 Mode 4

6.2.4

Output power   MV 2 2u2b 2u2a 2 Po ¼ 8Xbat 2u þ 2u þ 2D p  D p    p 1 a b 1 p p r   MV 2 4u2 4ua D1 þ 4ub þ 2D1 p  D21 p  p b  p Po ¼ 8Xbat r Po ¼

2 MVbat 4Xr

Po ¼

2 MVbat 4Xr

ðua þ ub ÞD1   u2 u2 ua þ ub þ pa  pb

Design of the Auxiliary Inductor Ls

As shown in Fig. 6.9, the slope of the MN should be lower than zero. Otherwise, the modulation trajectory cannot be implemented in seamless transition. Therefore, according to (6.7), the following condition should be satisfied. Ls \

1 2n2

Lr þ n21M

ð6:14Þ

In terms of Fig. 6.13, Lr should be first selected to meet the load requirement in different voltages. Then, Ls can be deigned in terms of (6.14). Ls1 and Ls2 may not be equal to the set values in the circuit, which may cause the difference of currents in Ls1 and Ls2. If the current in the auxiliary is large enough, the modulation scheme is still effective for wide ZVS.

6 Output-Series-Connected Dual Active Bridge Converters …

134

(a)

(b) Mode 1a Mode 3

Po (p.u.)

Po (p.u.)

Mode 2a Mode 4

Mode 2b Mode 1b

Vbat (V)

φ(rad) φ (rad)

(c)

Mode 1a Mode 2a Vbat =300V

Mode 3

Vbat =250V

Po (p.u.)

Vbat =200V Mode 4 Mode 3 Mode 2b Mode 1b

φ (rad)

Fig. 6.13 Output power versus phase-shift angle u and battery voltage Vbat: a three-dimensional surface, b right lateral view of Fig. 6.13a, and c two-dimensional curves of the output power versus u

6.2.5

Switch Conduction Loss Comparison

The rms of i1, i2, i3, i4, and i5 can be evaluated to investigate the conduction loss. The rms of i1 reflects the conduction loss of Q1–Q4; the rms of i2 and i5 reflects the conduction loss of Q5, Q6, Q9, and Q10; the rms of i3 and i4 reflects the conduction loss of Q7, Q8, Q11, and Q12. The rms current in the converter can be defined as

Irms

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZTs u ZTs u u 2u1 u1 2 ¼ t i1 ðtÞdt þ t i22 ðtÞdt n Ts Ts 0

0

0

0

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZTs u ZTs u ZTs u u u 1 u1 u u1 2 2 t t i3 ðtÞdt þ i4 ðtÞdt þ t i25 ðtÞdt þ Ts Ts Ts 0

ð6:15Þ

6.2 Key Feature and Modulation Scheme of the Converter Fig. 6.14 Rms currents in p.u. in the converter versus the output power (dashed lines: conventional OSDAB converter without LC networks; solid lines: OSDAB converter with LC networks)

Irms (p.u.)

135

Dashed lines: OSDAB without LC Solid lines: OSDAB with LC

M = 1.6

M =2 M = 1.3

Po (p.u.) The rms currents versus the output power with different voltage gain are illustrated in Fig. 6.14. The solid lines are the rms currents of the OSDAB with LC, and the dashed lines are the rms currents of the conventional OSDAB converter (shown in Fig. 6.2). The series inductance and turns ratio of the transformers in both converters are the same. The OSDAB is also operated in duty ratio control on the battery side. As shown in Fig. 6.14, the rms current in the conventional OSDAB converter is lower than that in the OSDAB with LC converter under light loads, but ZVS in the OSDAB with LC converter can be achieved. Furthermore, the rms current in the converter is very low under light loads, so the conduction loss does not affect the total loss too much. With the increase of the battery voltage, the conventional OSDAB converter will work in hard switching in wide load range, which lowers the efficiency. All the switches in the OSDAB with LC converter can achieve ZVS even in no load case. The switching loss can be dramatically reduced, and the efficiency can be improved. In heavy loads, the current in the transformer can maintain all the switches in ZVS, so the rms current curves of the two converters coincide in heavy loads. In this case, the OSDAB with LC converter actually works in the same mode as the conventional OSDAB converter. Therefore, the currents in dual LC networks are equal to zero, and the loss caused by LC networks is reduced to zero.

6.3

Experimental Verifications

To verify the output-series DAB converter with dual auxiliary LC networks, a 1.3 kW experimental prototype is built. In energy storage system, the output can be linked to a DC bus to compensate the mismatch of the power supply and load

136

6 Output-Series-Connected Dual Active Bridge Converters … Auxiliary power supply & Sensor board

Fig. 6.15 1.3 kW experimental prototype for test

Drive circuit

Control board

Drive circuit

Cs2 Cs1 Drive circuit

L Ls1 s2

Lr

demands. Therefore, the output voltage is set as a constant value of 600 V, and the battery voltage is 200–300 V. Figure 6.15 shows the prototype of test. The series inductor is selected as 25 lH to meet the load requirement. According to (6.14), Ls should be less than 54 lH. In the experimental prototype, Ls is selected as 22 lH. The detailed specifications are shown in Table 6.6. As seen, the volume of Ls1, Ls2, Cs1, and Cs2 is very small, so they do not affect the power density and do not cost too much. IZVS1 and IZVS2 are evaluated as 2 A. Figure 6.16 shows the key waveforms of vAB, vCD, and vEF, when Vbat = 250 V and Po = 650 W. vCD and vEF are symmetrical with the horizontal axis; the currents in the dual auxiliary LC networks are determined by vCF and vDE. As shown in the Table 6.6 Detailed specifications

Items

Symbol

Parameter

Battery voltage Output voltage Turns ratio of the transformers Switching frequency (period)

Vbat Vo n

200 * 300 V 600 V 1.5

fs (Ts)

Switches Series inductor Auxiliary inductor Ls1 Auxiliary inductor Ls2 Auxiliary capacitor Cs1 Auxiliary capacitor Cs1 Output filter capacitance

Q1–12 Lr Ls1 Ls2 Cs1 Cs2 Co1, Co2 tdead

80 kHz (12.5 ls) FQA28N50 24 lH 22 lH 22 lH 4.7 lF 4.7 lF 20 lF

Dead time

400 ns

6.3 Experimental Verifications

137

vAB (250V/div)

vEF (300V/div)

vCD

2

(300V/div)

Time base:4μs /div

i1 (10A/div)

Fig. 6.16 Measured key waveforms of vAB, vCD, and vEF when Vbat = 250 V, Po = 650 W

figure, the converter works in Mode 2a. The voltage amplitudes of vCD and vEF are almost same, which reflects the voltage balance of the output capacitors. Figure 6.17 shows the waveforms of vCD, vEF, and currents in the auxiliary LC networks. As shown in Fig. 6.17a, when Vbat = 200 V and Po = 650 W, the converter can achieve ZVS even without the LC networks. Therefore, is1 and is2 are controlled to zero. As shown in Fig. 6.17b, when Vbat = 250 V and Po = 650 W, is1 and is2 are adjusted to be large enough for ZVS. In all these cases, is1 and is2 are the same. Figure 6.18 shows the forward power flow when the converter works in light loads. Figure 6.18a shows experimental results when the battery voltage is 200 V. In this case, the converter works in Mode 4. The phase-shift angle Δu causes current difference between i2 and i3, so the converter can achieve ZVS of all the switches in this case. Figure 6.18b, c show the forward experimental results in light loads when the battery voltages are 250 and 300 V, respectively. With the increase of the battery voltage, Δu is adaptively regulated to keep the converter work in ZVS over the wide battery voltage. Figure 6.19 shows the key waveforms for the forward power flow in heavy loads. Figure 6.19a, b show the experimental results when the battery voltages are 200 and 250 V, respectively. In these two cases, the converter works in Mode

(a)

(b) vEF

vEF

(300V/div)

vCD

1

(300V/div)

vCD

1

(300V/div)

(300V/div)

is1

is1

(5A/div) 4

Time base:4μs /div

is2

(5A/div)

i1

(15A/div)

(5A/div) 4

Time base:4μs /div

is2

(5A/div)

i1

(10A/div)

Fig. 6.17 Currents in the auxiliary LC networks: a Vbat = 200 V and Po = 650 W, b Vbat = 250 V and Po = 650 W

6 Output-Series-Connected Dual Active Bridge Converters …

138

(a)

(b) vAB

vAB

(250V/div)

(250V/div)

vCD

vCD

(250V/div)

(250V/div)

i1

i1

(15A/div)

(15A/div)

i2

i2

(5A/div)

3

Time base:4μs /div

(5A/div)

3

i3

(5A/div)

Time base:4μs /div

i3

(5A/div)

(c) vAB

(250V/div)

vCD

(250V/div)

i1

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i3

(5A/div)

Fig. 6.18 Measured key waveforms for the forward power flow in light loads: a Vbat = 200 V, Po = 300 W, b Vbat = 250 V, Po = 300 W, and c Vbat = 300 V, Po = 300 W

(a)

(b) vAB

vAB

(250V/div)

(250V/div)

vCD

vCD

(250V/div)

(250V/div)

i1

i1

(15A/div)

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i2

(5A/div)

3

i3

(5A/div)

Time base:4μs /div

i3

(5A/div)

(c) vAB

(250V/div)

vCD

(250V/div)

i1

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i3

(5A/div)

Fig. 6.19 Measured key waveforms for the forward power flow in heavy loads: a Vbat = 200 V, Po = 1300 W, b Vbat = 250 V, Po = 1300 W, and c Vbat = 300 V, Po = 1300 W

6.3 Experimental Verifications

139

(a)

(b) vAB

vAB

(250V/div)

(250V/div)

vCD

vCD

(250V/div)

(250V/div)

i1

i1

(15A/div)

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i2

(5A/div)

3

i3

(5A/div)

Time base:4μs /div

i3

(5A/div)

(c) vAB

(250V/div)

vCD

(250V/div)

i1

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i3

(5A/div)

Fig. 6.20 Measured key waveforms for the reverse power flow in light loads: a Vbat = 200 V, Po = −328 W, b Vbat = 240 V, Po = −313 W, and c Vbat = 280 V, Po = −300 W

1a. The converter can achieve ZVS of all the switches even if Δu is equal to zero. In Fig. 6.19c, when the battery voltage is 300 V, Δu is regulated to be greater than zero for ZVS. The conventional OSDAB converter will lose ZVS. Figure 6.20 shows the key waveforms for the reverse power flow with light loads. In Fig. 6.20a, the converter works in Mode 4. In Fig. 6.20b, the converter works in Mode 2b. In Fig. 6.20c, the converter works in Mode 3. In these cases, Δu is greater than zero for the ZVS of Q5–Q8. The working modes in Fig. 6.20 are nearly symmetrical with those in Fig. 6.18. Figure 6.21 shows the key waveforms for the reverse power flow with heavy loads. As shown in Fig. 6.21a, b, when the battery voltages are 200 and 240 V and the load power is -1200 W, the converter works in Mode 1b. In Fig. 6.21b, the converter works in Mode 1b, and Δu is a little greater than zero. As illustrated in Fig. 6.21c, with the increase of the battery voltage, the phase-shift angle is decreased and the converter switches to Mode 2b. Figure 6.22 shows the gate signal and drain-source voltage of switch Q1. In all different working modes, i1 is less than zero during the commutation interval. The energy storage in the junction capacitor is discharged by i1, illustrating that Q1 works in ZVS for both forward and reversed power flows. Q2 works in the same mode with Q1, so it can also achieve ZVS. Figure 6.23 shows the gate signal and drain-source voltage of switch Q4. i1 is still less than zero during the commutation interval of Q4. It also illustrates that Q4

6 Output-Series-Connected Dual Active Bridge Converters …

140

vAB

vAB

(250V/div)

(250V/div)

vCD

vCD

(250V/div)

(250V/div)

i1

i1

(15A/div)

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i2

(5A/div)

3

i3

(5A/div)

Time base:4μs /div

(a)

i3

(5A/div)

(b) vAB

(250V/div)

vCD

(250V/div)

i1

(15A/div)

i2

(5A/div)

3

Time base:4μs /div

i3

(5A/div)

(c) Fig. 6.21 Measured key waveforms for the reverse power flow in heavy loads: a Vbat = 200 V, Po = −1200 W, b Vbat = 240 V, Po = −1250 W, and c Vbat = 280 V, Po = −1268 W

(a)

(b) ZVS

vgs1

ZVS

(10V/div)

vds1

vds1

(100V/div)

(100V/div)

1

i1

(7.5A/div)

i1

1

(7.5A/div)

i2

i2

(5A/div)

3

(5A/div)

3

i3

Time base:2μs /div

vgs1

(10V/div)

Time base:2μs /div

(5A/div)

i3

(5A/div)

(c) ZVS

vgs1

(10V/div)

vds1

(100V/div)

i1

1

(7.5A/div)

i2

(5A/div)

3

Time base:2μs /div

i3

(5A/div)

Fig. 6.22 Gate signal and drain-source voltage of switch Q1: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W

6.3 Experimental Verifications

141

(b)

(a) ZVS

vgs4

ZVS

(10V/div)

vds4

vds4

(100V/div)

(100V/div)

1

i1

(7.5A/div)

i1

1

(7.5A/div)

i2

i2

(5A/div)

3

(5A/div)

3

i3

Time base:2μs /div

vgs4

(10V/div)

i3

Time base:2μs /div

(5A/div)

(5A/div)

(c) ZVS

vgs4

(10V/div)

vds4

(100V/div)

i1

1

(7.5A/div)

i2

(5A/div)

3

i3

Time base:2μs /div

(5A/div)

Fig. 6.23 Gate signal and drain-source voltage of switch Q4: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W

(a)

(b) ZVS

vgs5

ZVS

(10V/div)

vds5

(150V/div)

1

vds5

(150V/div)

1

i1

i1

(7.5A/div)

(7.5A/div)

i2

(5A/div)

3

i2

(5A/div)

3

i3

Time base:2μs /div

vgs5

(10V/div)

Time base:2μs /div

(5A/div)

i3

(5A/div)

(c) ZVS

vgs5

(10V/div)

vds5

(150V/div)

1

i1

(7.5A/div)

i2

(5A/div)

3

Time base:2μs /div

i3

(5A/div)

Fig. 6.24 Gate signal and drain-source voltage of switch Q5: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W

6 Output-Series-Connected Dual Active Bridge Converters …

142

(a)

(b) ZVS

vgs8

ZVS

(10V/div)

vds8

vds8

(150V/div)

1

(150V/div)

1

i1

i1

(7.5A/div)

(7.5A/div)

i2

i2

(5A/div)

3

(5A/div)

3

i3

Time base:2μs /div

vgs8

(10V/div)

Time base:2μs /div

(5A/div)

i3

(5A/div)

(c) ZVS

vgs8

(10V/div)

vds8

(150V/div)

1

i1

(7.5A/div)

i2

(5A/div)

3

Time base:2μs /div

i3

(5A/div)

Fig. 6.25 Gate signal and drain-source voltage of switch Q8: a Vbat = 200 V, Po = 300 W, b Vbat = 300 V, Po = 300 W, and c Vbat = 300 V, Po = −300 W

can achieve ZVS. Q3 works in the same modes with Q4, which demonstrates that Q3 can also achieve ZVS. Figure 6.24 shows the gate signal and drain-source voltage of switch Q5. As seen in different working modes, before Q5 is turned on, i2 is large enough to charge and discharge the junction capacitors of Q6 and Q5. Q5 can work in ZVS in both forward and reverse power flows. Q6, Q9, and Q10 operate in the same ZVS constraint as Q5, so they are also easy to achieve ZVS. Figure 6.25 shows the gate signal and drain-source voltage of switch Q8. As seen during the dead time interval of Q8, i3 is large enough to charge and discharge the junction capacitors of Q7 and Q8. It validates the ZVS performance for Q8 in both forward and reverse power flows. Q7, Q11, and Q12 operate in the same working mode as Q8, so they can also achieve ZVS. The measured efficiency curves for the OSDAB converter with and without LC networks are shown in Fig. 6.26. When the battery voltage is 200 V, the OSDAB can achieve ZVS in heavy load even without auxiliary LC networks. Therefore, at 200 V battery voltage, the efficiency curves of the OSDAB converter with and without LC coincide in heavy load. In all the working modes, the OSDAB converter with LC can achieve ZVS, so the efficiency of the OSDAB converter with LC is greatly improved compared with the conventional OSDAB converter. Especially at the 300 V battery voltage and a 1350 W load, an efficiency improvement of more than 2% is achieved.

143

Efficiency

6.3 Experimental Verifications

Po (W)

Loss (W)

Fig. 6.26 Efficiency curves for the OSDAB converters with and without dual LC networks

Vbat=200V

Vbat=250V

Vbat =300V

Fig. 6.27 Loss breakdown in 1.3 kW output power

The calculated loss distribution in 1.3 kW output power is shown in Fig. 6.27. In 200 V battery voltage, the current amplitude is lower than 250 and 300 V battery voltage, so series inductor core loss is lower than that in 250 and 300 V battery voltage. The calculated rms in the series inductor versus the battery voltage in the rated load is shown in Fig. 6.28. The rms current in 250 V battery voltage is lower than that in 200 and 300 V battery voltages, so the copper loss in the series inductor and transformer is lower than that in 200 and 300 V battery voltage. In 200 and 250 V, the converter can achieve ZVS for all the switches even without LC networks. Therefore, the loss caused by LC networks is almost zero. In 300 V battery

144

6 Output-Series-Connected Dual Active Bridge Converters …

Rms current in the series inductor (A)

Fig. 6.28 Rms current in the series inductor versus the battery voltage in 1.3 kW

Vbat (V)

Loss (W)

Fig. 6.29 Loss breakdown in 200 W output power

0.16 0.29 0.41 0.37

Vbat=200V

Vbat=250V

Vbat=300V

voltage, all the switches can achieve ZVS with LC networks. The loss caused by LC networks is very low. Because of the ZVS of all the switching, the switching loss can be ignored, and the efficiency is dramatically improved. Figure 6.29 shows the calculated loss distribution in 300 W output power. When the battery voltage is 200 V, the peak current and rms current in the transformers are very low. Therefore, the conduction loss and core loss are very low. With the increase of the battery voltage, the peak current and rms current in the transformers are increased. The conduction loss and core loss are increased simultaneously.

6.4 Conclusion

6.4

145

Conclusion

This chapter presents an output-series dual active bridge converter with dual auxiliary LC networks. This converter can meet the high output DC-link voltage requirement. The two auxiliary LC networks are connected with the bridge legs of the two output full bridges. With the aid of the dual auxiliary LC networks, the converter can achieve ZVS performance of the output full bridges over full load range and wide battery voltage range. The ZVS boundaries of all the switches have been analyzed, and the modulation trajectory is designed according to the ZVS boundaries. The flowchart of the modulation trajectory can guarantee seamless transition between the adjacent working modes. Therefore, the converter can achieve ZVS with low conduction loss. Although the conduction loss in the OSDAB converter with LC is a little bit greater than the conventional OSDAB converter, the OSDAB converter with LC has a good tradeoff between the ZVS performance and the conduction loss in auxiliary circuit. Finally, the experimental results validate the ZVS performance in the OSDAB converter with LC. The efficiency curves demonstrate the efficiency improvement in the OSDAB with LC networks.

References 1. Liu P, Chen C, Duan S, Zhu W (2012) Dual phase-shifted modulation strategy for the three-level dual active bridge DC–DC converter. IEEE Trans Ind Electron 59(7):2745–2760 2. Filba-Martinez A, Busquets-Monge S, Nicolas-Apruzzese J, Bordonau J (2016) Operating principle and performance optimization of a three-level NPC dual-active-bridge DC–DC converter. IEEE Trans Ind Electron 63(2):678–690 3. Voss J, Bagaber B, De Doncker RW (2007) Full soft-switching capability of the dual-active bridge by using the auxiliary-resonant commutated-pole technique. In: Proceedings of IEEE 8th international symposium on power electronics for distributed generation systems (PEDG), pp 1–8 4. Harrye YA, Aboushady AA, Ahmed KH (2017) Power sharing controller for modular dual active bridge DC/DC converter in medium voltage DC applications. In: IEEE 6th international conference on renewable energy research and applications (ICRERA), pp 602–607

Chapter 7

Dual Active Bridge Converter with Parallel-Connected Full Bridges in Low-Voltage Side for ZVS by Using Auxiliary Coupling Inductor

Abstract A dual active bridge (DAB) converter with parallel-connected full bridges in low-voltage side is introduced in this chapter. A coupling inductor is integrated into the two low-voltage-side full bridges for zero-voltage switching (ZVS) operation throughout the full load range. By analyzing the working modes of the converter, the ZVS range of the converter is derived. To compromise the ZVS and the conduction loss caused by the coupling inductor, the modulation trajectory is designed in terms of the boundary conditions of the ZVS range. The conduction loss of the converter is compared with the conventional parallel-connected dual active bridge converter, which illustrates that the conduction loss of the presented converter is only increased under light loads. Finally, a 1.2 kW experimental prototype is built to verify the converter and modulation scheme, which demonstrates the remarkable ZVS performance and efficiency improvement.







Keywords Parallel-connected Dual active bridge Auxiliary coupling inductor ZVS

7.1




Parallel-Connected DAB in Low-Voltage Side

For safety considerations in the battery energy storage system, the battery voltage can be designed as 12, 24, or 48 V. In these cases, DAB converters should boost the voltage to serval hundred volts. The converter in the low-voltage side has to handle large current in high-power applications. The MOSFETs in parallel connection can enhance the current capacity [1]. However, the current may not be shared equally among them due to different parasitic inductances of the print circuit board (PCB) [2]. Therefore, only two to four MOSFETs in parallel connection are applicable. For more than four switches in parallel connection, the reliability may be degraded. Compared with the switches in parallel, the modular converters in parallel are more flexible and reliably to enlarge the power capacity [3–5]. The load power sharing among the parallel DAB converters is analyzed in [6]. DAB converters are actually current-source converters, so load power can be shared in DAB © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_7

147

148

7

Dual Active Bridge Converter with Parallel-Connected …

converters in parallel by using common phase-shift control, with no need for any current sharing control loop [6]. For medium-voltage DC application, a DAB converter system with a parallel connection in the low-voltage side and series connection in the high-voltage side is proposed to achieve high efficiency because of the ZVS performance [7, 8]. Therefore, the parallel connection in the low-voltage side is an effective solution in high-power applications. In this chapter, a DAB converter with auxiliary coupling inductor for low-voltage battery energy storage system is introduced. Figure 7.1 shows the circuit of the low-voltage-side parallel-connected DAB converter with auxiliary coupling inductor (PCDAB with CI). Vbat is the battery voltage, and Vo is the output high voltage. In low-voltage battery side, the two full bridges have to handle large current, and thus, they are connected in parallel. The two full bridges are linked to the output-side full bridge with two-individual transformers and two inductors. The turns ratio of the transformers is the same as 1:n. The series inductances Lr1 and Lr2 are the same as Lr. Ls1 and Ls2 are the auxiliary inductors to achieve full ZVS operation for the switches in low-voltage side, and Ls1 = Ls2 = Ls. D1 is the effective duty cycle of the output side of the full bridge. The power transmitted from the battery to the output is defined as the forward power flow, and the power from the output to the battery is defined as the reverse power flow. u is the phase shift between vAB and vEF. Δu is the phase shift between Q1 and Q4. Δu is only varied in a very small range. Defining ua ¼ u  Du=2 and ub ¼ u þ Du=2, there are four working modes for different effective duty cycles and phase-shift angles in forward power flow, which are shown in Fig. 7.2. As seen, the current waveforms in Ls1 and Ls2 are the same, so the windings of Ls1 and Ls2 can be winded in a core to form a coupling inductor.

Tr1 Vbat

Ci

A

i1 Q4

Q5

Q7 C

Ci Q6

Lr1 i6

i2

B

Q2

is1

is21:n

Ls1

Ls2

i3 D

i5

E F

Q10

Tr2 Lr2

Q8

Q11

Q9

Q3

Q1

Q12

Vo

Auxiliary coupling inductor

i4 1:n

i7

Fig. 7.1 Low-voltage-side parallel-connected DAB converter with auxiliary coupling inductor

7.1 Parallel-Connected DAB in Low-Voltage Side

(a)

Q2&Q5

Q1&Q6 Q4&Q7

Q1&Q6

Q3&Q8

Q10

Q9

Q11

Q10

vCD vEF

φ

φb

D1Ts/2

Vo

(b)

Q4&Q7 Q10

vCD vEF

Q10 Q11

Q12 Vbat

φ

φb

D1Ts/2

Vo

φa

vAD&vBC is1&is2 i5 i1 &i3 i2 &i4

Vbat

Q10

Q12

Q11

vEF

t1 t2 t3 t4 Q2&Q5

Q4&Q7 Q9

Q3&Q8 Q10

Q12

Q11

Q1&Q6 Q4&Q7 Q9 Q12

Vbat

∆φ φb

vAD&vBC is1&is2 i5

Vbat

Vo

Q1&Q6

vCD Vo

Vo

Vbat

(d)

Q4&Q7 Q9

Q12

Vbat

vAB

Vbat

∆φ

D1Ts/2

t0 Q1&Q6

Q3&Q8 Q9

Q11

vAB

φb

t4 Q2&Q5

Q1&Q6

Q4&Q7 Q9

Vbat

φ

∆φ

vAD&vBC is1&is2 i5 i1 &i3 i2 &i4

Vbat

t1t2t3

Q11

Q12

φa

Vbat

t0

Q10

Vbat

vEF

Vo

Q1&Q6

Q3&Q8 Q9

Q11

vCD

φa

vAD&vBC is1&is2 i5 i1 &i3 i2 &i4

Q10

vAB

Vbat

∆φ

Q2&Q5

Q1&Q6 Q4&Q7

Q12

Q11

Q12

(c)

Q4&Q7 Q9

Vbat

vAB

149

Vbat

φ D1Ts/2

Vo Vo

-φa

Vbat Vbat

i1 &i3 i2 &i4

t0

t1 t2 t3

t4

t0 t1

t2 t3 t4

Fig. 7.2 Key waveforms for working modes in forward power flow: a Mode 1a: 0.5 − D1/ 2  ua/p  ub/p  0.5, b Mode 2a: −(0.5 − D1/2)  ua/p  0.5 − D1/2  ub/p  0.5, c Mode 3: −(0.5 − D1/2)  ua/p  ub/p  0.5 − D1/2, d Mode 4: ua/p  −(0.5 − D1/ 2)  0  0.5 − D1/2  ub/p

Because of the symmetrical working modes in forward and reverse power flow, there are also four working modes in reverse power flow, which are defined as Mode 1b, Mode 2b, Mode 3, and Mode 4. Mode 1b is symmetrical with Mode 1a, and Mode 2b is symmetrical with Mode 2a. Mode 3 and Mode 4 are the common working modes in both forward and reverse power flow. In the chapter, only forward power flow is analyzed, and the similar conclusions for reverse power can be derived. The currents in the PCDAB with CI meet the following conditions.

150

7

Dual Active Bridge Converter with Parallel-Connected …

8 is1 > > > < i 5 > i1 > > : i2

¼ is2 ¼ is ¼ 2i6 ¼ 2i7 ¼ i3 ¼ ni6 þ is

ð7:1Þ

¼ i4 ¼ ni6  is

Taking Mode 1a as an example, the working stages in Mode 1a are shown in Fig. 7.3. In order to simplify the analyses, the dead time of the switches is ignored. Stage 1 ([t0, t1]) (Fig. 7.3a): Prior to t0, Q1, Q4, Q6, Q7, Q10, and Q12 are on, and Q2, Q3, Q5, Q8, Q9, and Q11 are off. At t0, Q10 is switched off, and i5 is positive. The junction capacitor of Q9 is discharged, and Q9 is turned on with ZVS. nVbat is lower than Vo, so i1 starts to decrease. is1 and is2 are positive. The specific currents in this stage are expressed as 8 < i ðtÞ ¼ i ðt Þ þ 2ðnVbat  Vo Þ ðt  t Þ 5 5 0 0 Lr : is ðtÞ ¼ is ðt0 Þ

ð7:2Þ

Stage 2 ([t1, t2]) (Fig. 7.3b): At t1, Q1 and Q6 are turned off, and i1 and i3 are positive. Therefore, i1 starts to discharge and charge the junction capacitors of Q2 and Q1, while i3 starts to discharge and charge the junction capacitors of Q5 and Q6. Q2 and Q5 are turned on with ZVS. The voltages across Ls1 and Ls2 are negative, so is1 and is2 start to decrease. The specific currents in this stage are expressed as 8 2Vo > > ðt  t1 Þ < i5 ðtÞ ¼ i5 ðt1 Þ  Lr V > > : is ðtÞ ¼ is ðt1 Þ  bat ðt  t1 Þ Ls

ð7:3Þ

Stage 3 ([t2, t3]) (Fig. 7.3c): At t2, Q4 and Q7 are turned off, and i2 and i4 are positive. i2 starts to discharge and charge the junction capacitors of Q3 and Q4, while i3 starts to discharge and charge the junction capacitors of Q8 and Q7. When the voltage across Q3 and Q8 is equal to zero, Q3 and Q8 are turned on with ZVS. The voltage across Ls1 and Ls2 is equal to zero, so is1 and is2 keep constant in this stage. The specific currents in this stage are expressed as 8 < i ðtÞ ¼ i ðt Þ  2ðnVbat þ Vo Þ ðt  t Þ 5 5 2 2 Lr : is ðtÞ ¼ is ðt2 Þ

ð7:4Þ

Stage 4 ([t3, t4]) (Fig. 7.3d): At t3, Q12 is switched off, i5 starts to discharge and charge the junction capacitors of Q11 and Q12, until the voltage across Q11 reaches zero. Q11 is turned on with ZVS. The specific currents in this stage are expressed as

7.1 Parallel-Connected DAB in Low-Voltage Side Fig. 7.3 Topological stages with half-switching period for Mode 1a: a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4]

(a)

151

Q11

Q9

Q3

Q1

Tr1 Lr1 Vbat

A

Ci

i1

Q2

Q4

Q5

Q7

i5

C

1:n

is1

is2

Ls1

Ls2

Q10

Q12

i3 D

Q6

Q8

Q1

Q3 A

Ci

i4 1:n

Q11

Q9

i1

Q2

Q4

Q5

Q7

E

i5

C

is1

is2

Ls1

Ls2

Q10

Q12

i3

i4 1:n

Q8

A

i1 Q4

Q5

Q7

i5

C

is1

is2

Ls1

Ls2

Q10

D Q8

Q1

Q3 A

1:n

Q4

Q5

Q7

Q6

i6

i2

i5

D

Co F

is1

is2

Ls1

Ls2

Q10

i7

i3

E

1:n

Tr2 Lr2

Q8

Q11

Q9

B

C

Vo

i4

i1

Q2

Ci

Q12

i7

i3

Q6

Ci

Co F

1:n

Tr1 Lr1 Vbat

E

Tr2 Lr2

Ci

(d)

i6

i2

B

Q2

Q11

Q9

Q3 Tr1 Lr1

Ci

Vo

i7

D

Q1

Vbat

Co F

1:n

Tr2 Lr2

Ci

(c)

i6

i2

B

Q6

Vo

i7

Tr1 Lr1 Vbat

Co F

Tr2 Lr2

Ci

(b)

i6

i2

B

E

i4 1:n

Q12

Vo

152

7

Dual Active Bridge Converter with Parallel-Connected …

8 < i ðtÞ ¼ i ðt Þ  2nVbat ðt  t Þ 5 5 3 3 Lr : is ðtÞ ¼ is ðt3 Þ

ð7:5Þ

In terms (7.1)–(7.5), the currents i1–i5 at the commutating time in Mode 1a can be derived. In the same manner, the currents in Mode 2a, Mode 3, and Mode 4 also can be calculated, and the ZVS performance and conduction loss in different working modes can be analyzed. The detailed features of the converter will be analyzed in the following sections.

7.2

Key Features and Modulation of the Converter

This section will introduce the ZVS analyses and design of the converter with 20–30 V battery voltage and 300 V output voltage. The rated power is 1.2 kW.

7.2.1

ZVS Analyses for Q9–Q12

The ZVS performance of Q9–Q12 is determined by the polarity and amplitude of i5 during dead time. Because of the symmetry of the two halves of the switching period, the ZVS conditions for Q9 and Q10 are the same, and the ZVS conditions for Q11 and Q12 are the same. Therefore, only the ZVS performance of Q9 and Q11 will be analyzed. In order to achieve ZVS for Q9 and Q11 in Mode 1a, i5(t0) should be larger than IZVS1 and i5(t3) should be smaller than −IZVS1, where IZVS1 is the minimum current to charge or discharge the junction capacitor of Q9–Q12 during dead time for ZVS. IZVS1 is associated with the output voltage and Coss (output capacitance) of switches Q9–Q12, the proximate evaluation of IZVS1 can be expressed as Vo CossðQ9Q12Þ =tdead , where tdead is the dead time of the switches. According to the voltage-second balance of the full bridges on both sides of the transformer, D1 can  ub ua  be set as nVVbat 1  þ p p þ Dm . The ZVS conditions in the four working modes o are expressed in Table 7.1. In accordance with Table 7.1, as long as Dm  2LVroIZVS1 Ts , Q9–Q12 can achieve ZVS. In this chapter, Dm is set as

7.2.2

2Lr IZVS1 Vo Ts .

ZVS Analyses for Q1–Q8

The ZVS performance of Q1, Q2, Q5, Q6 is determined by the polarity and amplitude of i1 and i3, and the ZVS performance of Q3, Q4, Q7, Q8 is determined by the polarity and amplitude of i2 and i4. Because of the symmetry of the two halves

7.2 Key Features and Modulation of the Converter

153

Table 7.1 ZVS conditions for Q9 and Q11 Mode 1a   2u nVbat Ts i5 ðt0 Þ ¼ 1 þ a  D1 p 2Lr Dm Vo Ts Dm Vo Ts þ   IZVS1 2Lr 2L   r 2u nVbat Ts i5 ðt3 Þ ¼ 1  a  D1 p 2Lr Dm Vo Ts Dm Vo Ts     IZVS1 2Lr 2Lr Mode 3   2u nVbat Ts i5 ðt0 Þ ¼ 1 þ a  D1 p 2Lr Dm Vo Ts Dm Vo Ts þ   IZVS1 2Lr 2L  r 2ub nVbat Ts 1 i5 ðt1 Þ ¼ D1 þ p 2Lr Dm Vo Ts Dm Vo Ts     IZVS1 2Lr 2Lr

Q9

Q11

Q9

Q11

Table 7.2 ZVS conditions for Q2 and Q3

Q2 Q3

Mode 2a   2u nVbat Ts i5 ðt0 Þ ¼ 1 þ a  D1 p 2Lr Dm Vo Ts Dm Vo Ts þ   IZVS1 2Lr 2Lr i5 ðt2 Þ ¼  Dm2LVor Ts   IZVS1

Mode 4 i5 ðt0 Þ ¼ Dm2LVor Ts  IZVS1

i5 ðt3 Þ ¼  Dm2LVor Ts   IZVS1

Mode 1a

Mode 2a

Mode 3

Mode 4

(7.6) (7.7)

(7.6) (7.8)

(7.8) (7.8)

(7.6) (7.9)

of the switching period, the ZVS conditions for Q1, Q2, Q5, and Q6 are the same, and the ZVS conditions for Q3, Q4, Q7, and Q8 are the same. Therefore, only the ZVS performance of Q2 and Q3 will be analyzed. In order to achieve ZVS for Q2 and Q3 in Mode 1a, i1(t1) and i2(t2) should be larger than IZVS2, where IZVS2 is the minimum current to charge or discharge the junction capacitor of Q1–Q8 during dead time for ZVS. IZVS2 is associated with the output voltage and Coss (output capacitance) of switches Q1–Q8, the proximate evaluation of IZVS2 can be expressed  as Vbat CossðQ1Q8Þ tdead . The ZVS conditions for Q2 and Q3 are shown in Table 7.2.    u u  n2 Vbat Ts 2ub nVo Ts ub ua  Vbat Ts 1  1þ a  b þ þ [ IZVS2 ð7:6Þ p p 4Lr p 4Lr p p 4Ls 

1þ

  ua ub  n2 Vbat Ts 2ua nVo Ts ub ua  Vbat Ts  1  þ þ [ IZVS2 ð7:7Þ p p 4Lr p 4Lr p p 4Ls

 u u  n2 Vbat Ts nD1 Vo Ts ub ua  Vbat Ts 1þ a  b   þ [ IZVS2 p p 4Lr 4Lr p p 4Ls

ð7:8Þ

154

7

Table 7.3 Derived ZVS conditions for Q2 and Q3



1þ

Q2 Q3

Dual Active Bridge Converter with Parallel-Connected … Mode 1a

Mode 2a

Mode 3

Mode 4

(7.10) (7.11)

(7.10) (7.12)

(7.12) (7.12)

(7.10) (7.13)

ua ub  n2 Vbat Ts 2ua nVo Ts ub ua  Vbat Ts  Þ   ð1 þ þ [ IZVS2 ð7:9Þ p p 4Lr p 4Lr p p 4Ls

Substituting ua ¼ u  Du=2 and ub ¼ u þ Du=2 into Table 7.2 can deduce Table 7.3. Du 

Du 



ðnVbat  Vo ÞnTs nVo Ts u I   ZVS2 bat ÞnTs 4Lr 2Lr p þ ðVo nV 4Lr

ð7:10Þ



ðnVbat  Vo ÞnTs nVo Ts u I   ZVS2 Vbat Ts 4Lr 2Lr p  ðVo þ nVbat ÞnTs

ð7:11Þ

p

Vbat Ts 4Ls

p

4Ls

4Lr

  4pLs nDm Vo Ts IZVS2 þ Vbat Ts 4Lr

p ðnVbat  Vo ÞnTs nVo Ts u IZVS2  þ bat ÞnTs 4Lr 2Lr p þ ðVo nV 4Lr Du 

Du 

Vbat Ts 4Ls

ð7:12Þ ð7:13Þ

The ZVS conditions for Q1–Q8 can be synthesized in (7.10)–(7.13). When Vo = 300 V, n = 10, IZVS1 = 1 A, IZVS2 = 2 A, Lr = 140 lH, and Ls = 0.3 lH, the three-dimensional surface of the ZVS boundary conditions versus the phase-shift angle u and battery voltage Vbat is shown in Fig. 7.4. The space above the surface is the ZVS area, and the space below the surface is the hard switching area. The ZVS range in a two-dimensional plane for different battery voltages is shown in Fig. 7.5, which are the vertical section of Fig. 7.4. The shadowed area is the ZVS range. When the battery voltage is 30 V, the effective battery voltage is matched with the output voltage. The converter can achieve ZVS in a wide range. With the decrease in the battery voltage, the hard switching range is increased. When Δu is large enough, the converter can achieve ZVS operation of all the switches in full load range and wide battery voltage range. However, large Δu will cause a large current in Ls1 and Ls2, which increases the conduction loss of the converter. In order to make a trade-off between the ZVS and conduction loss, the modulation strategy should be designed on the surface of the boundary ZVS conditions. In the two-dimensional plane, the ZVS boundary condition is the modulation trajectory in Fig. 7.5. On the modulation trajectory, the converter works in different operation modes. As long as the modulation scheme located on the modulation trajectory, the converter can achieve ZVS for Q1–Q8. According to Fig. 7.5, the turning point M of the modulation trajectory can be determined by the boundary conditions (7.11)

7.2 Key Features and Modulation of the Converter Fig. 7.4 Three-dimensional surface of the ZVS boundary conditions

155

∆φ (rad) Mode 2b Mode 3 Mode 2a

Mode 4 Mode 1a

Mode 1b

Vbat (V) φ (rad) and (7.12), and the turning point N of the modulation trajectory can be determined by the boundary conditions (7.11). Therefore, the coordinates of turning point M is (um, Δum), and coordinates of turning point N is (un, 0), where   8 2pLs ðVo þ nVbat Þ nDm Vo Ts pnVbat pðDm  1Þ > > u ¼ I þ   ZVS2 > m > V 2 V T 4L 2Vo > o bat s r > >   < 4pLs nDm Vo Ts ð7:14Þ Dum ¼ IZVS2 þ > V T 4Lr bat s > >   > > > 2pLr IZVS2 p nVbat > : un ¼  1 2 Vo nVo Ts Therefore, line MN can be expressed as Du ¼

7.2.3

Dum ðu  un Þ um  un

ð7:15Þ

Design of the Auxiliary Inductance Ls

As seen the modulation trajectory in Fig. 7.5, the slope of line MN should be less than zero, otherwise the modulation trajectory will not be a piecewise function. Therefore, according to (7.11), the following condition should be met.

156

7

Dual Active Bridge Converter with Parallel-Connected …

(a)

(b)

M

M m

m

N

N

(d)

(c)

M

M m

m

N

N

Fig. 7.5 ZVS range in two-dimensional plane for different battery voltages: a Vbat = 20 V, b Vbat = 26.5 V, c Vbat = 27 V, d Vbat = 29 V

Lr 2 Vbat þ n

Ls \ nVo

ð7:16Þ

The series inductance Lr should be selected to meet the rated load power. In the prototype design in this chapter, Lr is selected as 140 lH, and Vo = 300 V, n = 1:10, Vbat = 20 * 30 V. According to (7.16), the auxiliary inductance should meet Ls < 0.8 lH. In the auxiliary coupled inductor, the two windings are winded in the same core, so the magnetic flux is double of the individual auxiliary inductors. Therefore, compared with the individual auxiliary inductor, the windings

7.2 Key Features and Modulation of the Converter

157

in the auxiliary inductor are reduced to the quarter. Two-individual inductors can be used in the converter. However, there may be some parasitic differences in the two-individual inductor, even if the same type of core is chosen. By using the coupling inductor with one core, the core difference can be removed. In the prototype design, the Kool Ml (@Magnetics) is selected as the core material. First, in terms of LI2, a proper core is selected. Kool Ml 77310 (@Magnetics) is selected as the core in the experimental prototype. According to the datasheet provided by Magnetics@, the number of turns can be obtained from sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi L  103 N¼ AL

ð7:17Þ

where AL is the inductance factor for the core obtained from the core datasheet. Finally, its maximum magnetic flux density is calculated to confirm that the core is unsaturated. In order to meet Ls < 0.8 lH, the number of turns for each winding in the coupling inductor is one. Finally, Ls is designed as 0.3 lH.

7.2.4

Control Loop of the Modulation Trajectory

In accordance with the modulation trajectory, the control loop is designed as shown in Fig. 7.6. The output voltage reference Vref is compared with the output voltage Vo. The error is controlled by a PI controller, whose output is the phase-shift angle u. The flowchart of the modulation trajectory is shown in Fig. 7.7. By comparing u with um, −um, un, and −un, the working mode is determined. According to the different working modes, Δu is calculated for ZVS. When the output voltage is 300 V, the output power versus the phase-shift angle u in per unit (p.u.) for different battery voltages is shown in Fig. 7.8, which illustrates that the output power is continuously varied with u. The modulation can achieve seamless transitions in adjacent working modes.

Fig. 7.6 Control loop of the modulation scheme

Vref

PI Vo

φ Flowchart shown ∆φ

D1 =

in Fig.7.7

nVbat ⎛ Δϕ ⎞ + Dm ⎜1 − Vo ⎝ π ⎟⎠

PWM Q1-Q12

158

7

Dual Active Bridge Converter with Parallel-Connected …

Fig. 7.7 Flowchart of the modulation trajectory

Determine the control variable φ, . where Calculate D1 φm, φm, φn Yes

-φm

φ φm No

Yes (Mode 1a)

No (Mode 1b)

φ φm

Mode 2a or Yes No φ φn Mode 2b or Mode 3 or ϕ Mode 4 ϕm φ=0 (ϕ − ϕ n ) φ= φm ϕm − ϕn

Yes

φ -φn

No

ϕ

φ=0

ϕm (ϕ + ϕ n ) ϕm − ϕn

φa=φ- φ/2 φb=φ+ φ/2 Return

Fig. 7.8 Output power (p.u.) versus the phase-shift angle u

Vbat =30V Vbat =24V Vbat =20V

Po(p.u.) Mode2a Mode4

Mode1a

Mode1b Mode3 Mode2b

φ(rad)

7.2.5

Conduction Loss Analyses

The rms current of i1 and i3 reflects the conduction loss in Q1, Q2, Q5, and Q6, and the rms current of i2 and i4 reflects the conduction loss in Q3, Q4, Q7, and Q8. The rms current of i5 reflects the conduction loss in Q9–Q12. The rms current in the converter is defined as

7.2 Key Features and Modulation of the Converter

IRMS

159

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZTs u ZTs u u u1 u1 2 ¼t i1 ðtÞdt þ t i22 ðtÞdt Ts Ts 0

0

vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi vffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi u ZTs u ZTs u ZTs u u u 1 2 u1 u u1 þt i23 ðtÞdt þ t i24 ðtÞdt þ t i25 ðtÞdt Ts Ts n Ts 0

0

ð7:18Þ

0

It will be used to analyze the conduction loss of the converter. Figure 7.9 shows the rms current in the converter versus the output power in per unit. The solid lines in Fig. 7.9 are for the PCDAB with CI. The dashed lines in Fig. 7.9 are for the PCDAB without CI (the converter in Fig. 7.1 without the auxiliary coupling inductor), which can be controlled by EPS referred to [6]. As seen in Fig. 7.9, the conduction loss in the PCDAB with CI is larger than that in the converter without the auxiliary coupling inductor under light loads. However, the PCDAB without CI cannot achieve ZVS for all the switches under this circumstance. The rms current in this case is very low, and the increased conduction loss does not have great impact on the efficiency. Furthermore, the ZVS performance under light load can significantly decrease the switching loss. Therefore, the efficiency can be improved under a light load. As the load power increases, the PCDAB without CI also can achieve ZVS, so Δu in the presented modulation trajectory is decreased to zero. In this case, the two converters work in the same mode. The rms current curves of the two converters overlap in the heavy loads. The conduction loss caused by the coupling inductor is adaptively adjusted to make the trade-off between the conduction loss and ZVS performance.

Fig. 7.9 Rms current in the converter versus the output power in per unit

Solid lines: PCDAB with CI Dashed lines: PCDAB without CI

Irms (p.u.)

Vbat=27V Vbat=24V Vbat=20V

Vbat=30V

Po(p.u.)

160

Dual Active Bridge Converter with Parallel-Connected …

7

Table 7.4 Detailed specifications

Items

Symbol

Parameter

Battery voltage Output voltage Turns ratio of the transformers Switching frequency (period) Switches

Vbat Vo 1:n fs (Ts) Q1–8 Q9–12 Lr1, Lr2 Ls1, Ls2

20–30 V 300 V 1:10 80 kHz (12.5 ls) FQA160N08 FQA28N50 140 lH 0.3 lH

Series inductor Auxiliary inductor

7.3

Experimental Validation

A 1.2 kW experimental prototype of the PCDAB with CI is built to verify the performance of the converter. The detailed specifications are shown in Table 7.4. The current waveforms of Lr1 and Lr2 are proximately same, so the windings of the two series inductors also can be winded in a core in the prototype design to improve the power density. Besides, the difference between Lr1 and Lr2 can be reduced. Figure 7.10 shows the prototype for the test. As seen, the volume of the auxiliary coupling inductor is small. Figure 7.11 shows the waveforms of is1 and is2 in the auxiliary coupling inductor, where is1 and is2 are the same. As seen in Fig. 7.11a, the converter works in Mode 2a when Vbat = 20 V, Po = 560 W. Δu is large enough to generate is1 and is2 to achieve ZVS of switches in the battery side in this case. When the battery

Vo+

Vo Q9-12 and drive circuit

Tr1

Lr1 and Lr2

Ls1 Ls2

Tr2 Vbat -

Q1-4, Q5-8 and drive circuit

Vbat+ Auxiliary power supply

Control board

Fig. 7.10 Experimental prototype for test

Sensor board

7.3 Experimental Validation

161

(a)

(b)

2

3

Time base:4μs /div

vAB (25V/div) vCD (25V/div) is2 (20A/div) is1 (20A/div) i5 (10A/div)

2

3

Time base:4μs /div

vAB (25V/div) vCD (25V/div) is1 (20A/div) is2 (20A/div) i5 (4A/div)

Fig. 7.11 Waveforms of currents in the auxiliary coupling inductor: a Vbat = 20 V, Po = 560 W, b Vbat = 30 V, Po = 560 W

(a)

(b) vAB

(25V/div)

vEF

(250V/div)

i5

(10A/div)

i1

(40A/div)

3

Time base:4μs /div

i2

(40A/div)

3

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (5A/div) i1 (20A/div) i2 (20A/div)

Fig. 7.12 Key waveforms in the forward power flow under light load: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W

voltage increases to 30 V, the ZVS range increases. Therefore, is1 and is2 are controlled to zero, and the converter comes into Mode 1a. Figure 7.12 shows key waveforms in the forward power flow under a light load. As seen, the phase shift Δu is always greater than zero to achieve ZVS under a light load. The ZVS range increases as Vbat rises. Consequently, Δu when Vbat = 30 V is smaller than that when Vbat = 20 V and the converter changes working mode from Mode 3 to Mode 4. Figure 7.13 shows key waveforms in the forward power flow under heavy load. In these two cases, the converter works in Mode 1a and it can achieve ZVS of all the switches even there is no current in the auxiliary coupling inductor. Δu is adjusted to zero accordingly. Figure 7.14 shows key waveforms in the reverse power flow under light load. As seen in Fig. 7.14a, the converter works in Mode 3, and the waveforms are nearly symmetrical with those in Fig. 7.12a. Δu is reduced to zero when transmitted power comes to −230 W, and the converter enters Mode 1b as shown in Fig. 7.14b.

162

7

Dual Active Bridge Converter with Parallel-Connected …

(a)

(b)

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

3

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Fig. 7.13 Key waveforms in the forward power flow under heavy load: a Vbat = 20 V, Po = 1125 W, b Vbat = 30 V, Po = 1125 W

(a)

(b)

3

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (10A/div) i1 (40A/div) i2 (40A/div)

3

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (5A/div) i1 (20A/div) i2 (20A/div)

Fig. 7.14 Key waveforms in the reverse power flow under light load: a Vbat = 20 V, Po = −190 W, b Vbat = 30 V, Po = −230 W

Figure 7.15 shows key waveforms in the reverse power flow under heavy load. The converter works in Mode 1b, and the waveforms are nearly symmetrical with those in Fig. 7.13. Figure 7.16 shows the gate signal and drain-source voltage of switch Q2 for different cases. i1 is larger than IZVS2 during dead time, which leads to the ZVS of Q 2. Figure 7.17 shows the gate signal and drain-source voltage of switch Q3. It can be seen that i2 is larger than IZVS2 during dead time. It illustrates that switch Q3 can achieve ZVS in all these cases. Figure 7.18 shows the gate signal and drain-source voltage of switch Q9. As seen in different working modes, i5 is larger than IZVS1 during dead time, which can discharge the junction capacitor of switch Q9. Therefore, switch Q9 can achieve ZVS. Figure 7.19 shows the gate signal and drain-source voltage of switch Q11. i5 is less than −IZVS1 during dead time. It demonstrates that the ZVS performance of Q11 is achieved.

7.3 Experimental Validation

163

(b)

(a)

3

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

3

Time base:4μs /div

vAB (25V/div) vEF (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Fig. 7.15 Key waveforms in the reverse power flow under heavy load: a Vbat = 20 V, Po = −1050 W, b Vbat = 30 V, Po = −1050 W

(a)

(b) Q2 ZVS

2

3

Time base:2μs /div

vgs2 (10V/div) vds2 (25V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

(c)

Q2 ZVS 2

3

Time base:2μs /div

vgs2 (10V/div) vds2 (25V/div) i5 (5A/div) i2 (20A/div) i1 (20A/div)

(d) Q2 ZVS

2

3

Time base:2μs /div

vgs2 (10V/div) vds2 (25V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Q2 ZVS 1

3

Time base:2μs /div

vgs2 (10V/div) vds2 (25V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Fig. 7.16 Gate signal and drain-source voltage of switch Q2: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W

Figure 7.20 shows the gate signal and drain-source voltage of switch Q2 for the PCDAB without CI. The converter also works in EPS, in which the full bridges of the battery side are control by duty cycle and the output full bridge generate two-level square waveform. Without the auxiliary coupling inductor, the converter works in hard switching, which cause large switching loss and switching noise. The measured efficiency curves of the PCDAB with and without CI are illustrated in Fig. 7.21. The PCDAB without CI is modulated by EPS, in which the full bridges of the battery side are controlled by duty cycle and the output full bridge

164

7

Dual Active Bridge Converter with Parallel-Connected …

(a)

(b) Q3 ZVS

2

3

Time base:2μs /div

vgs3 (10V/div) vds3 (25V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

(c)

Q3 ZVS 2

3

Time base:2μs /div

vgs3 (10V/div) vds3 (25V/div) i5 (10A/div) i2 (20A/div) i1 (20A/div)

(d) Q3 ZVS

2

3

Time base:2μs /div

vgs3 (10V/div) vds3 (25V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Q3 ZVS 2

3

Time base:2μs /div

vgs3 (10V/div) vds3 (25V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Fig. 7.17 Gate signal and drain-source voltage of switch Q3: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W

(b)

(a) Q9 ZVS 2

3

Time base:2μs /div

vgs9 (10V/div) vds9 (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

(c)

Q9 ZVS 2

3

Time base:2μs /div

vgs9 (10V/div) vds9 (250V/div) i5 (5A/div) i1 (20A/div) i2 (20A/div)

(d) Q9 ZVS

2

3

Time base:2μs /div

vgs9 (10V/div) vds9 (250V/div) i5 (10A/div) i1 (40A/div) i2 (40A/div)

Q9 ZVS 2

3

Time base:2μs /div

vgs9 (10V/div) vds9 (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Fig. 7.18 Gate signal and drain-source voltage of switch Q9: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W

7.3 Experimental Validation

165

(a)

(b) Q11 ZVS

2

3

Time base:2μs /div

vgs11 (10V/div) vds11 (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Q11 ZVS 2

3

Time base:2μs /div

vgs11 (10V/div) vds11 (250V/div) i5 (5A/div) i2 (20A/div) i1 (20A/div)

(d)

(c) Q11 ZVS 2

3

Time base:2μs /div

vgs11 (10V/div) vds11 (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Q11 ZVS 2

3

Time base:2μs /div

vgs11 (10V/div) vds11 (250V/div) i5 (10A/div) i2 (40A/div) i1 (40A/div)

Fig. 7.19 Gate signal and drain-source voltage of switch Q11: a Vbat = 20 V, Po = 160 W, b Vbat = 30 V, Po = 160 W, c Vbat = 30 V, Po = 1125 W, d Vbat = 20 V, Po = −190 W

(a)

(b) Switching noise Hard Switching

vgs2

Switching Hard Switching noise

(10V/div)

vds2

(25V/div)

2

i5

i5

(10A/div)

i2

i2

(40A/div) Time base:2μs /div

i1

(40A/div)

vds2

(25V/div)

2

(10A/div) 4

vgs2

(10V/div)

(40A/div)

3

Time base:2μs /div

i1

(40A/div)

Fig. 7.20 Hard switching waveforms of switch Q2 for the conventional parallel-connected DAB (PCDAB) converter in battery side: a Vbat = 20 V, Po = 450 W, b Vbat = 25 V, Po = 450 W

generates the two-level square waveform. Under heavy loads, the PCDAB converter can achieve ZVS of all switches. The PCDAB with CI operates the same as the PCDAB converter without CI, with the phase shift Δu being zero. For this reason, the efficiency curves of the two converters coincide under heavy loads. While under light loads, the PCDAB converter without CI loses ZVS of the switches in battery side. However, the PCDAB converter with CI can achieve ZVS of all the switches at a small loss of conduction in the auxiliary coupling inductor.

166

7

Dual Active Bridge Converter with Parallel-Connected … PCDAB with CI for Vbat=30V PCDAB with CI for Vbat=25V PCDAB with CI for Vbat=20V PCDAB without CI for Vbat=30V PCDAB without CI for Vbat=25V PCDAB without CI for Vbat=20V

Fig. 7.21 Efficiency curves of the PCDAB converter with and without CI

In conclusion, the efficiency performance of the PCDAB with CI is better than that without CI. Figure 7.22 shows the transient experimental results for the load step change from 160 to 620 W when Vbat = 25 V. Figure 7.22a shows the output voltage and the load current. Figure 7.22b shows the voltages and currents of the transformer. Figure 7.22c, d are the extended figures of Fig. 7.22b before and after the load step

(b)

(a)

vAB

vo

(100V/div)

(25V/div)

(1A/div)

(250V/div)

1

(10A/div)

(10A/div)

Time base:10ms /div

(40A/div)

vEF

io

i5

i5

i1

i2

3

i1

Time base:10ms /div

(40A/div)

i2

3

(40A/div)

(40A/div)

Fig.7.22(c)

(c)

Fig.7.22(d)

(d) vAB

vAB

(25V/div)

(25V/div)

(250V/div)

(250V/div)

(10A/div)

(10A/div)

vEF

vEF

i5

i5

i1

(40A/div)

3

Time base:4μs /div

i2

(40A/div)

i1

(40A/div)

4

Time base:4μs /div

i2

(40A/div)

Fig. 7.22 Transient experimental results for load step change from 160 to 620 W when Vbat = 25 V: a output voltage (vo) and load current (io), b voltages and currents of the transformer, c extended figure of Fig. 7.22b before the load step change, d extended figure of Fig. 7.22b after the load step change

7.3 Experimental Validation

167

change. When the load power is 160 W, the converter works in Mode 2a. When the load power is 620 W, the converter works in Mode 1a. During the transient process, the converter transfers seamlessly in the two working modes without large current and voltage spikes, which demonstrate the effectiveness of the presented modulation scheme.

7.4

Conclusion

In this chapter, a DAB converter with parallel-connected full bridges in the low-voltage side is introduced to achieve ZVS throughout the full load range by using auxiliary coupling inductor. The boundary ZVS surface is associated with not only the load power but also the conversion ratio. The modulation trajectory is designed according to the ZVS surface. According to the modulation trajectory, the current in the auxiliary coupling inductor can be adjusted to compromise the ZVS performance and conduction loss. The rms current comparison illustrates that the conduction loss in the presented converter is only increased in light load. Finally, the experimental prototype verified the effectiveness of the PCDAB converter with CI and method. It shows that the converter can achieve ZVS in wide battery voltage range and full load range. It can improve the ZVS performance and efficiency of the converter under a light load.

References 1. Hu J, Alatise O, Gonzalez JAO, Bonyadi R, Alexakis P, Ran L, Mawby P (2016) Robustness and balancing of parallel-connected power devices: SiC versus CoolMOS. IEEE Trans Ind Electron 63(4):2092–2102 2. Fabre J, Ladoux P (2016) Parallel connection of 1200-V/100-A SiC-MOSFET half-bridge modules. IEEE Trans Ind Appl 52(2):1669–1676 3. Vazquez A, Rodriguez A, Lamar DG, Hernando MM (2018) Advanced control techniques to improve the efficiency of IPOP modular QSW-ZVS converters. IEEE Trans Power Electron 33 (1):73–86 4. Liu D, Deng F, Gong Z, Chen Z (2017) Input-parallel output-parallel three-level DC/DC converters with interleaving control strategy for minimizing and balancing capacitor ripple currents. IEEE J Emerg Sel Topics Power Electron 5(3):1122–1132 5. Sha D, Guo Z, Liao X (2011) Control strategy for input-parallel–output-parallel connected high-frequency isolated inverter modules. IEEE Trans Power Electron 26(8):2237–2248 6. Shi J, Zhou L, He X (2012) Common-duty-ratio control of input-parallel output-parallel (IPOP) connected DC–DC converter modules with automatic sharing of currents. IEEE Trans Power Electron 27(2):3277–3291

168

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Dual Active Bridge Converter with Parallel-Connected …

7. Stieneker M, De Doncker RW (2015) Dual-active bridge DC–DC converter systems for medium-voltage DC distribution grids. In: IEEE 13th Brazilian power electronics conference and 1st southern power electronics conference (COBEP/SPEC), pp 1–6 8. Todorcevic T, Kessel R, Bauer P, Ferreira JA (2015) A modulation strategy for wide voltage output in DAB-based DC–DC modular multilevel converter for DEAP wave energy conversion. IEEE J Emerg Sel Topics Power Electron 3(4):1171–1181

Chapter 8

An Isolated Micro-converter Utilizing Fixed-Frequency BCM Control Method for PV Applications

Abstract This chapter introduces a BCM controlled micro-converter for PV application in order to provide high conversion efficiency over a wide input voltage operating range. Within the wide input range for the PV panel, there is no need to change the operating modes according to the PV panel voltage. The leakage inductor current can work in boundary conduction mode with fixed switching frequency. The operation mode analysis is given first. Then the operating principle of the boundary conduction mode and its implementation are introduced. Loss breakdown of the prototype using GaN devices is analyzed and compared with same voltage rating silicon MOSFETs. A 300 W micro-converter was fabricated and experimental results are provided to verify the effectiveness of the presented BCM control.








Keywords Micro-converter Fixed frequency Boundary conduction mode (BCM) Photovoltaic (PV) Zero voltage switching (ZVS)




8.1 8.1.1

BCM Operation Analysis Topology Description

A topology for the front-end micro-inverter was proposed by using a bidirectional ac switch on the output side [1–2]. However, there are three operating modes and the mode transition is implemented according to the value of the input voltage. For the boost mode, the leakage inductor current works in DCM. Compared with DCM, the peak value of the leakage inductor current iLr is lower than with BCM control. This causes lower current stress in the switches. Meanwhile, BCM has lower rms current as well when delivering the same power. Therefore, the conduction loss is lower with BCM and the efficiency of the converter will be improved. To achieve BCM, variable switching frequency and fuzzy control technology can be used [3]. However, for real application, the on-line switching frequency calculation is very difficult to be implemented by a low-cost fixed-point DSP and thus the system © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_8

169

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

170

S1

S3 A

D1

C1

C3

1:n Lm

Vin

Cr1

Lr

c

S5

Co

S6

d

B S2

D2

S4 C2

Vo

Cr2

C4

Fig. 8.1 Topology of the micro-converter

dynamic performance is poor. Besides, GaN-based switches can be used to reduce the gate driving loss [4]. Phase-shift control can be implemented between the primary side and secondary side based on the same topology [5]. However, the circulating current and the nonactive current are relatively high. Besides, for the primary-side circuit, the equivalent duty cycle is fixed to be 0.5 based on existing control strategies and this causes more core loss [1–3]. Based on the advantages of dual active bridge (DAB), a fixed-frequency BCM is achieved [6–7]. In this case, GaN transistor is used to reduce the driving and switching loss for hard-switching situations. Figure 8.1 shows the topology of the converter. It resembles an isolated resonant converter with a voltage double output [8], with the addition of S5/S6. On the primary side, S1 through S4 make up a full-bridge switch network. S5/S6 on the secondary side is the bidirectional ac switch, which is implemented as two drain-connected GaN HEMTs for this application.

8.1.2

BCM Modes Analysis

The current in the leakage inductor works in DCM if the switching frequency is fixed with existing control [3]. Making the converter operating at BCM for wide input voltage and output power range becomes very difficult. In this chapter, a phase-shift BCM control method that modulates the primary-side and the secondary-side devices at the same time is introduced, which allows the converter to operate at BCM with fixed frequency in most operation conditions. In order to explain the operation principle, it is necessary to analyze the detailed operating waveforms, which have been demonstrated in Fig. 8.2. The corresponding equivalent circuits for each mode during a whole cycle are shown in Fig. 8.3. In addition, before the analysis, the following assumptions are made: (1) Co is large enough so that Vo can be considered constant during a secondary-side MOSFET switching period Ts.

8.1 BCM Operation Analysis

171

(b)

(a) S1

S1

S2

S4

S3

S4

S4

φ Ts

t1

vAB

D1 Ts

nVin

φ Ts

vCD Vo/2n

D1 Ts

Vin v CD

(2nVin/Vo)D1Ts

Vo/2n

(2nVin/Vo)D1Ts

D2 Ts

iLr

D2 Ts

iLr iLm t0

S3

S5&S6

S5&S6

vAB

S2

iLm t2

t3

t4

t5

t7 t8 t9t 10

t6

(c)

t2

t0 t

1

S1

t4 t6 t3 t5

t7

t9 t11 t8 t10

S2

S4

S3

S5&S6

vAB

D1 Ts

Vin v CD

φ Ts V /2n o

(2nVin/Vo)D1Ts

D2 Ts

iLr iLm t0 t

1

t2

t5 t3 t4

t6

t t t7 t9 10 11 t8

Fig. 8.2 Detailed operating waveforms of BCM with different input voltages: a matched point, b higher than matched point, c lower than matched point

(2) Co is much larger than Cr1 and Cr2. (3) The capacitances of Cr1 and Cr2 are the same and their values are large enough. So that, the voltage across Cr1 or Cr2 can be considered as Vo/2 during a switching period Ts.

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

172

(a)

(b)

S1

S3 A

C1

C3 1:n

S2

C1

C3 1:n

Vo Vin

Cr2

Co

S6

Vo

D Cr2

D2

S4

C2

C4

Cr1

C

S5

Lm

S2

D1

Lr

B

(c)

C4

(d)

S1

S3 A

C1

C3 1:n

Vin

Co

S6

S3 A

C1

C3 1:n

Vo Vin

S2

Co

S6

Vo

D Cr2

D2

S4

C2

C4

Cr1

C

S5

B

Cr2

D1

Lr Lm

D D2

S4

C2

S1

Cr1

C

S5

B S2

D1

Lr Lm

C4

(f)

(e) S1

S3 A

C1

C3 1:n

Co

S6

S3 A

C1

C3 1:n

Vo Vin

S2

Co

S6

Vo

D Cr2

D2

S4

C2

C4

Cr1

C

S5

B

Cr2

D1

Lr Lm

D D2

S4

C2

S1

Cr1

C

S5

B S2

D1

Lr Lm

Vin

C4

(h)

(g) S1

S3 A

C1

C3 1:n

Vin

Co

S6

S3 A

C1

C3 1:n

Vo Vin

S2

Co

S6

Vo

D Cr2

D2

S4

C2

C4

Cr1

C

S5

B

Cr2

D1

Lr Lm

D D2

S4

C2

S1

Cr1

C

S5

B S2

D1

Lr Lm

C4

(j)

(i) S1

S3 A

C1

C3 1:n

B

S5

S1

Cr1

C

Co

S6

S3 A

C1

C3 1:n

Vo Vin

Cr2

B S2

C4

Cr1

C

S5

Co

S6

Vo

D D2

S4

C2

D1

Lr Lm

D D2

S4

C2

D1

Lr Lm

Vin

S2

S3 A

D D2

S4

C2

Co

S6

B

S1

Cr1

C

S5

Lm

Vin

D1

Lr

Cr2

C4

Fig. 8.3 Detailed modes during boundary conduction

Stage 1 [t0 < t < t1]: During period 1 through 2, primary-side switches S1 and S4 are on, resulting in a positive voltage Vin across the primary winding of the transformer. Prior to S5 and S6 turning on, the current is slightly lower than zero due to the effect of the magnetizing inductance. This current is useful for S1 to achieve ZVS. Similar to a conventional PWM boost converter, Lr acts as a boost inductor and the current through it increases linearly according to the following equation.

8.1 BCM Operation Analysis

173

iLr ðtÞ ¼

nVin ðt  t0 Þ Lr

ð8:1Þ

Stage 2 [t1 < t < t2]: At t1, the secondary-side ac switches turn off, resulting in a positive voltage Vo/2 across the secondary winding of the transformer. Since S1 and S4 still conduct, Vin is still applied to the primary winding, resulting in a current change of the inductor according to (8.2). If nVin are equal to Vo/2, the current will keep unchanged until the following period comes. This situation can be defined as “matched point.” If the input voltage is above the point, the leakage inductor current increases linearly with an upslope compared with period 1. Otherwise, the current decreases when the input voltage is below the match point, as is shown in Fig. 8.2b and c. iLr ðtÞ ¼

nVin 2nVin  Vo ðt1  t0 Þ þ ðt  t1 Þ Lr 2Lr

ð8:2Þ

Stage 3 [t2 < t < t3]: S4 turns off at t2, resulting in a short dead time before S3 switching on. During this period, Lr appears as a current source to discharge the parasitic capacitance of S3. Since iLr is large enough, the voltage across S3 becomes zero at t3 allowing it to be turned on under ZVS condition. iLr ðt2 Þ ¼ iLr ðt3 Þ ¼

nVin Vo ðt2  t0 Þ  ðt2  t1 Þ Lr 2Lr

ð8:3Þ

Stage 4 [t3 < t < t4]: At t3, S3 is turned on. Both S1 and S3 are on and the primary winding of the transformer is short circuited. Meanwhile, secondary ac switch still remains off, which adds Vo/2 to the secondary winding. Since the dead time is very short, iLr can be viewed to decrease directly since t2 − t4 to simplify the analysis and the current expression can be written by (8.4). iLr ðtÞ ¼

nVin Vo ðt2  t0 Þ  ðt  t1 Þ Lr 2Lr

ð8:4Þ

Stage 5 [t4 < t < t5]: All gate trigger signals of the primary MOSFETs are fixed PWM signals with 50% duty cycle. So, S1 turns off right before this period comes, resulting in a short dead time to prepare for the turning on S2 and for the coming of the negative half-cycle. During this period, iLr discharges the parasitic capacitance of S3 along with the magnetizing current creating the ZVS turn-on condition for S3. The negative half-cycle is similar due to the symmetry of the topology, which will not be discussed in detail. iLr ðt4 Þ ¼ iLr ðt5 Þ ¼

nVin Vo ðt2  t0 Þ  ðt4  t1 Þ Lr 2Lr

ð8:5Þ

174

8.1.3

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

BCM Operation Condition

If the leakage inductor current works in DCM, the current reaches and stays at zero before the secondary-side switches turn on. If the leakage inductor current works in CCM, the current reaches zero after the secondary-side switches turn on. Therefore, BCM of the leakage inductor current means that the current reaches zero just at the time when the secondary-side switches turn on and do not stays at zero. This condition implies that the leakage inductor current iLr reaches zero at t4 and t9. Setting iLr(t4) in (8.5) to be zero, the equation to achieve the boundary condition can be calculated in (8.6). nVin D1 ¼

Vo D2 2

ð8:6Þ

where: 8 < D2 ¼ 1  u c :u ¼  100% 180

ð8:7Þ

c is the phase angle between the primary side and the secondary side and it is defined as the phase angle between the rising edge of vab and vcd, where vab is the voltage across the primary winding of the transformer and vcd is the voltage across the secondary-side ac switches. Besides, nvab − vcd is the voltage imposed on the inductor Lr and D1 is the duty cycle ratio of vab. As defined, (8.6) can be simplified to (8.8), which means the voltage multiplying its duty cycle is balanced. Equation (8.8) may be derived from the “voltage-second balance” concept as well. nvab D1 ¼ vcd D2

ð8:8Þ

Equation (8.6) connects the primary duty cycle and the phase angle ratio between two sides; it implies that only the angle is chosen as the variable. Thus, only the angle c or the phase angle ratio u is discussed for the following chapter. The positive half-cycle contains periods 1–5 in which only power is transferred during period 1 and period 2 to the output, so the output power can be expressed as follow: 1 Po ¼ Ts

Zt2 iðtÞnVin dt t0

Substituting (8.1) and (8.2) into (8.9) yields the power expression (8.10).

ð8:9Þ

8.1 BCM Operation Analysis

175

Fig. 8.4 Output power ability with different leakage inductance values under different input voltages: a Vin = 24 V, b Vin = 36 V

  nVin Ts Vo 2 2 Po ¼ nVin D1  ðD1  uÞ 2Lr 2

ð8:10Þ

During the boundary conduction, the match point is determined by the transformer turns ratio, which is set around the middle of the MPP voltage range at 29 V. Once, the turns ratio has been decided, the output power amount is mainly determined by the leakage inductance value, as shown in Fig. 8.4. Its value is not preferred to be low for the phase angle will be limited in a very small range. However, if the leakage inductance value is too large, the output maximum power is limited. Hence, to satisfy the operating requirements, the inductance is set to be 78 lH due to trading off. Figure 8.4 illustrates the relation between the output power and phase angle c as well. It is clear that the output power rises at first and then begins to fall when the phase angle increases continuously. Operating in the falling period should be avoided, which requires the angle to be limited to ensure the converter operating in the rising period. To determine the lowest voltage for MPPT, it is necessary to take the derivative of Eq. (8.10) to know when the output power reaches its peak under the same input voltage. After simplifying, the relationship between phase angle ratio and input voltage can be obtained, as shown in (8.11). u¼

Ts Vo2 100%  4n2 Vin2 þ 2nVin Vo þ Vo2 180

ð8:11Þ

Based on (8.10) and (8.11), it can be calculated that when the input voltage is 24 V, u will be around 39.4% and c = 70° to ensure the highest output power about 316 W. For the presented converter needs to operate at around 300 W as its highest output power, in view of the loss, 24 V is just suitable to be the lowest MPPT voltage.

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

176

Fig. 8.5 Power versus phase angle under different input voltages with leakage inductance of 78 lH

Figure 8.5 demonstrates the relationship between power and phase angle, where 36 V is the highest voltage for MPPT and 24 V is the lowest. To satisfy the power requirement and to ensure the presented converter operating in the rising period, the phase angle finally ranges from 0° to 70°. Once the phase angle and the input voltage are limited, the power condition can be fully described when operating in this mode. As seen in Fig. 8.6, it is clear that the highest output power can reach roughly 470 W if the input source has enough power output capability. Though this mode is to operate at BCM, it is interesting to find that there still exist some conditions, where the current is unable to maintain continuously. To explain it, this “voltage-second balance” concept as shown in (8.8) must be satisfied to ensure the converter working at the boundary conduction mode. When the input voltage drops continuously, chances are that the primary angle percentage D1 will increase over 100%, which is impossible for real application. Under this circumstance, D1 will hold on 100% causing the boundary balance (8.6) broken and the leakage inductor current discontinuous as a result. Setting D1 to be 100%, Eq. (8.12) can be obtained to demonstrate the border.

Input

voltag

e (V)

gle (°)

Phase an

Fig. 8.6 BCM power condition with leakage inductance of 78 lH

8.1 BCM Operation Analysis Fig. 8.7 BCM actual power condition when connected to an inventor

177 36 34 32 30 28 26 24

0

10

20

30

40

50

60

70

Phase angle (°)

8 Vo ð1  uÞ > > < Vin ¼ 2n   nV Ts nVin Vo  2n2 Vin2 > in > : Po ¼ 2Lr Vo

ð8:12Þ

As shown in Fig. 8.6, the dashed line is the border between BCM and DCM of the leakage inductor current. Below the border, the current becomes discontinuous. However, when connected to an inverter, the output voltage Vo will be held at 380 V. The zero-power part will not occur under this circumstance. Figure 8.7 is used to describe the actual operating condition more directly. The shading part in Fig. 8.7 is the zero-power part that the converter will actually not operate in this region. It is clear to be seen that compared with the BCM part, region below the dashed line for the DCM one is very small. Hence, the micro-converter can operate at BCM under most circumstances.

8.1.4

ZVS Condition Analysis

From the former analysis in Sect. 8.1.3, it is clear that four MOSFETs of the primary side are not turned on under the same condition. S3 and S4 always turn on when the current in Lr reaches the peak. However, when S1 and S2 are switched on, that current is usually approximately zero, still having to discharge their parasitic capacitance. Under this circumstance, the two different switching legs that make up the full-bridge network are defined in this chapter. As seen in Fig. 8.8, Phase Leg A is comprised of S1 and S2, and Phase Leg B is comprised of S3 and S4. When Leg B switches turn on, the current is higher than the magnetizing current. Hence, compared with Phase Leg A, ZVS condition of Leg B will be easier to satisfy. With enough ability to discharge the parasitic capacitance, Phase Leg B can fully achieve ZVS. When Leg A switches turn on, the current present in the primary-side devices is just the magnetizing current, which is equal to (8.13).

178

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

Phase Leg A

Fig. 8.8 Switching legs definition of the primary-side full-bridge MOSFET network

Phase Leg B

S

S3 A

C3 1:n

C1

Vin

B S2

ILegA

dead

¼

n2 Vin Ts D1 2Lm

C2

S4 C4

ð8:13Þ

where: D1 ¼

h  100% 180

ð8:14Þ

h is the phase angle between Phase Leg A and Phase Leg B. Ts is the switching period of the secondary-side ac switch, which is equal to 5 ls. Idead is the value of the magnetizing current in dead time. The parasitic capacitances in Phase Leg A charges and discharges in parallel, so the equivalent capacitance is equal to one of the MOSFETs, Coss. Adding the values to the capacitor charge balance (8.15), the inequality of the required magnetizing inductance and dead time is obtained (8.16). dv dt

ð8:15Þ

n2 Ts tdead D1 4Coss

ð8:16Þ

i¼C Lm 

where tdead is the length of the dead time. If Lm and tdead are already selected, D1 becomes the only variable needed to be designed. It is the most difficult to achieve ZVS when D1 reaches its lowest value. Since u is limited from the analysis above, D1 will reach its lowest value when u is at its highest according to the power Eqs. (8.6) and (8.7), which means the most difficult condition for ZVS of Phase Leg A occurs at the heaviest load of 300 W if the input voltage is constant. Setting the output power to be 300 W, relation between u and Vin will be written as follows (8.17).

8.1 BCM Operation Analysis

179

Fig. 8.9 Primary phase angle versus different input voltages at 300 W output

pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi b þ b2  4ac u¼ 2a

ð8:17Þ

8 2 < a ¼ Vo ðVo þ nVin Þ  3n2 Vin2 Vo b ¼ 2Vo3 Ts : c ¼ ð2nVin  Vo Þ2 Vo2 Ts2  16nVin Ts Lr Po

ð8:18Þ

where:

Substituting (8.17) into (8.6), relationship between primary phase angle and input voltage can be drawn, as is shown in Fig. 8.9. In the MPPT voltage range, D1 is the lowest at the maximum input voltage 36 V, resulting in the hardest ZVS condition when operating in BCM. Under the most difficult condition, the magnetizing inductance can be optimized to achieve the ZVS. After parameter optimization, Phase Leg A and Leg B both achieve ZVS at 36 V input, 300 W output. From the analysis above, it is obvious that both Leg A and Leg B can achieve ZVS as long as the converter operates in BCM. Thanks to the phase-shift control strategy, zero-current switching (ZCS) can be achieved for all the secondary-side diodes when they are turned off within full range.

8.1.5

Light Load Optimization

In order to realize the presented unified control, the converter must be optimized to compensate for the drawbacks of the previous boundary conduction. From Fig. 8.6, it is not hard to find that the boundary conduction is difficult to be achieved under high input and light load conditions. In order to ensure the converter operating properly within the input voltage and the load range for PV applications, this optimization is necessary.

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

180

Under light load condition, especially at very high input voltage, chances are that the phase angle ratio u could be decreased to negative. That causes the primary side lag behind the secondary side. However, it is impossible for real application due to the unidirectional power flow feature of the converter. When u becomes negative, its amplitude is used to control the phase angle between Phase Leg A and Phase Leg B as an optimal solution. Meanwhile, the secondary ac switches are always off, which is similar to the traditional phase-shift control. As described, u = 0 is the border of the two modes. At the border, the power is expressed as the following according to (8.12). Po ¼

nVin D21 Ts Vo ðnVin  Þ 2Lr 2

ð8:19Þ

Figure 8.10 demonstrates the border of two operating conduction conditions. Below the line, the secondary ac switch remains off. Relatively, the converter operates at boundary conduction above the line or when the input voltage is under 29 V as well. This conduction is used in the soft-start period and high input, light load condition. Figure 8.11 shows the theoretical waveforms of this operating condition. Analysis is very similar to the “buck mode” described in [3].

BCM

DCM

Fig. 8.10 Border of two conduction conditions

DCM

8.2 Loss Analysis

181

S1

S2

S4

S1

S3

S4

S3 vds1

Vin

vds4

Vin ir

iLm

iD1

iD1

iD2

Vcr1

t0

t1 t3 t2

t4

t6 t5

t7

t8

t9

t10

t11 t13 t14 t12 t15

Fig. 8.11 Ideal waveforms of the converter operating in high input voltage and light load

8.2

Loss Analysis

For photovoltaic application, the efficiency of the converter is very important to harvest the energy. Once the magnetic core is selected, the core loss is closely related to DB if the switching frequency is fixed. The peak flux density DB is shown in (8.20) where the unit for it is Tesla (T) and Ae is the effective cross-sectional area of the core, which is available from the core shape datasheet. DB ¼

Vin D1 Ts 2N1 Ae

Pcore ¼ aFsb DBc Ve

ð8:20Þ ð8:21Þ

Equation (8.21) is based on the Steinmetz equation [9] where a, b, and c are coefficients which can be obtained by curve-fitting techniques of the power-loss curves from the core material datasheet.

8 An Isolated Micro-converter Utilizing Fixed-Frequency …

182

8 Þ2 ðuTs Þ3 2 > IS5 ¼ T1s ½ðnVin 3L  > 2 rms > r > > > 2 2 > nVin ðnVin  V2o Ts Þ n Vin Ts 2 > 2 > ¼ u ðD  uÞ þ uðD1  uÞ2 I > 1 rms D1 2 2 > 2L 2L > r r > > > < ðnVin  V2o ÞTs Vo2 Ts 3 þ ðD  uÞ þ ð1  D1 Þ3 1 6L2r 24L2r > > > > > Iavg-Deq ¼ Po > Vo > > 2 2 2 2 > IS1 > rms ¼ n ð0:5IS5 rms þ ID1 rms Þ > > 2 2 > I ¼ 2IS1 rms > > : pri rms PDiode = Iavg-Deq VSD

ð8:22Þ

These six equations above demonstrate the rms current flowing through individual components. IS5_rms is the rms ac switch current and IS1_rms means the primary-side rms switch current. As long as the rms equations are expressed, the conduction loss can be obtained by multiplying the resistance accordingly. Iavg-Deq will be used to analyze the secondary-side diode loss, just as Eq. (8.22) shows, where VSD means the forward voltage of the diode. Meanwhile, Ipri_rms will be useful for calculating the transformer copper loss. Parameters can be seen from Table 8.1. As discussed previously, the current flowing through Leg B switches is different from that in Leg A switches within the dead time. The current through Leg A is already described in (8.13). Leg B has an extra leakage inductor current during the dead time, which is shown in (8.23). The current may be considered constant within the dead time due to the very short time. Hence, dead time conduction loss Eq. (8.24) can be obtained by multiplying the forward voltage of the body diode. ILegB

dead

¼

n2 Vin Ts Vo D1 þ ðTs  D1 Ts Þ 2Lm 2Lr

PDTloss ¼

Table 8.1 Micro-converter parameters

VSD Idead tdead Ts

ð8:23Þ ð8:24Þ

Quantity

Symbol

Value

Primary switches Secondary switches Secondary diodes Transformer core Primary resistance Secondary resistance Dead time

S1–S4 S5–S6 D1–D2 Core Rpri Rsec tdead

Infineon-IPB010N06 N GaNsystem-GS66502B IXYS DSEI8-06A Ferroxcube RM14-3c95 4 turns, 3.8 mR 26 turns, 180 mR 150 ns

8.2 Loss Analysis

183

Fig. 8.12 The generalized turning-off procedure of MOSFET

VCC VGP

vgs

VTH VEE

ig VDS

vds

0 ID

id

0 toff_1

toff_2

toff_3

toff_4

toff

For the analysis of the switching off loss of MOSFETs, the generalized turning-off procedure of MOSFET is illustrated in Fig. 8.12, which can be divided into four stages. During the first and the fourth stage, no power loss is generated since ID or VDS remains zero. For simplification, the second and third turning-off stages can be linearized. Hence, the average turning-off power loss of a MOSFET in a switching period can be described as Eq. (8.25). Besides, turning-on procedure is similar with different driving resistance. P

turnoff

 ¼ 0:5
VDS ID toff

2

þ toff

 3

Ts

ð8:25Þ

where: 8

> p 4nL 4Lr > r > >
 > > Vo Ts 2u Vbat D1 Ts > > >  D1 þ ir ðt1 Þ ¼ > > p 4nL 4Lr > r > < Vo D2 Ts Vbat D1 Ts ir ðt2 Þ ¼  þ > 4nLr 4Lr > > > > V D T V D1 Ts > o 2 s bat > ir ðt3 Þ ¼  þ > > > 4nL 4L r r > >
 > > V T 2u Vbat D1 Ts > o s > : ir ðt4 Þ ¼  þ D1 þ 4nLr p 4Lr

ð9:1Þ

The shaded areas are the backflow currents commutated between the series inductor and input or output capacitors. In order to achieve ZVS of all the switches, the current amplitude at the commutation time should be large enough to charge and discharge the junction capacitor of the switches during the dead time. The minimum current amplitude to charge and discharge is the junction capacitor can be determined by the output capacitance of the switches, which can be obtained from the datasheet of the switches. CossðQ1Q4Þ is defined as the output capacitance of Q1–Q4, and CossðQ5Q8Þ is defined as the output capacitance of Q5–Q8. The current minimum amplitude can be approximately evaluated as IZVS1 ¼ 2Vbat CossðQ1Q4Þ =tdead and IZVS2 ¼ 2Vo CossðQ5Q8Þ =tdead , where IZVS1 is the current amplitude for ZVS of Q1–Q4, while IZVS2 is the current amplitude for ZVS of Q5–Q8. tdead is the dead time. In order to make the trade-off between the conduction loss and ZVS of all the switches in Mode 1f, the following constraints should be met: ir(t0) = −IZVS1, ir(t1)  IZVS1 and ir(t2)/n = ir(t3)/n = −IZVS2. In this case, the backflow current is just large enough for all the switches in ZVS. Therefore, the duty cycles of the two full bridges should be satisfied as the following, 8 > > < D1

Mode1f

> > : D2

Mode1f


 M 4Lr IZVS1 us þ ¼ 1M Vbat Ts D1 Mode1f 4nLr IZVS2 þ ¼ M Vo Ts

ð9:2Þ

where us = 2u/p. With the increase of u, D1 and D2 are increased simultaneously and D2 is larger than D1. The output power is expressed as Po ¼

Vbat Vo Ts u D1 nLr 2p

ð9:3Þ

9.1 Analyses of the Working Modes for DAB Converter

197

(2) Mode 2f (Fig. 9.2b) In Mode 2f, the currents in the transformer at the commutating time are written respective by,
 8 Vo Ts 2u Vbat D1 Ts > > ir ðt0 Þ ¼ 2  D1   > > p 4nLr 4Lr > > >
 > > V T V T 2u > o s bat s > > 1 < ir ðt1 Þ ¼ 4nL  4L p r r
 > V T 2u D o s 1 Vbat Ts > >  D1 þ ir ðt2 Þ ¼ > > 4nLr p 4Lr > > >
 > > V D T V T 2u > bat 1 s o s > : ir ðt3 Þ ¼  2  D1  p 4Lr 4nLr

ð9:4Þ

The output power in this mode is expressed in (9.5). Po ¼

 Vo Vbat Ts  2us  D21 þ 2D1  u2s  1 8nLr

ð9:5Þ

In order to achieve ZVS of all the switches in Mode 2f, the following constraints should be met: ir(t0)  −IZVS1, ir(t1)/n  IZVS2, and ir(t2)  IZVS1. Q2 can achieve ZVS at t2, because ir(t2) is large enough in this mode. As seen  in (9.4), ir(t1) is

associated with the phase-shift angle. As long as u  um2 ¼ p2 1  M þ

4Lr nIZVS2 Vbat Ts

,

Q5–Q8 can achieve ZVS in Mode 2f. ir(t0) is associated with D1 and u. As long as D1 and u are large enough, Q1–Q4 can work in ZVS. The following will analyze the calculation of D1 and u in Mode 2f. The nominal output power Pn is defined as Po/Pbase, where Pbase is equal to Vo Vbat Ts =ð8nLr Þ. The rms current in Mode 2f is calculated in (9.6), where k = Ts/ (4Lr).

2 Irms

Mode2f

ZTs =2

2 2 Vbat k 3D21 M  3D21 Mus  2D31 þ 3D21 3 0  þ 6D1 Mus  6D1 M þ M 2  Mu3s þ 3Mu2s  3Mus þ M

2 ¼ Ts

ir ðtÞ2 dt ¼

ð9:6Þ

The curves Irms_Mode2f versus D1 and u for different output powers are shown in Fig. 9.3, where Ts = 10 ls, Lr = 60 lH, n = 1, Vbat = 400 V, and Vo = 300 V. The area above the shadowed area is the working mode for Mode 2f. As seen in (9.5), there is countless combination of D1 and u for a fix output power, but there is minimum rms current for a specific value of D1 and u. The red solid line is the trajectory for minimum Irms_Mode2f. The next procedure is to get this trajectory. By using Lagrange multiplier method, the evaluation function is shown in (9.7).

9 Modulation Scheme of Dual Active Bridge Converter …

198

(a)

(b)

Fig. 9.3 Relationship between D2 and u for different output powers in Mode 2f: a Irms_Mode2f versus D1 for different output powers; b Irms_Mode2f versus u for different output powers

2 f ðD1 ; us Þ ¼ Irms

Mode2f

þ kðPn  p Þ

ð9:7Þ

where p* is the desired nominal output power. According to (9.7), the following constraint can be obtained for the minimum value of Irms_Mode2f. 8 2 @Irms @f ðD1 ;us Þ @Pn Mode2f > þ k @D ¼0 > < @D1 ¼ @D1 1 2 @I @f ðD1 ;us Þ rms Mode2f n þ k @P @us @us ¼ 0 > @us ¼ > : @f ðD1 ;us Þ ¼ Pn  p ¼ 0 @k In terms of the first and second equations in (9.8), if 2 @Irms

ð9:8Þ

2 @Irms Mode2f @D1

@Pn = @D ¼ 1

n = @P @us , Irms_Mode2f can get the minimum value for a desired output power. Therefore, the duty cycles of the two full bridges should be satisfied as the following. Mode2f

@us

8 > < > :

M þ us  1 þ

D1

Mode2f

¼

D2

Mode2f

¼1

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðM 2 þ 1Þðus  1Þ2 þ 2M ðus  1Þ þ M 2 M

ð9:9Þ

Moreover, D1_Mode2f should be lower than one. As seen in (9.9), the duty cycles of the two full bridges only build the relationship to the phase-shift angle and voltage conversion ratio instead of the desired nominal output power.

9.1 Analyses of the Working Modes for DAB Converter

199

(3) Mode 3f (Fig. 9.2c) In Mode 3f, the effective conversion ratio M is larger than 1. This working mode actually can be viewed as exchanging with the two input and output ports in Mode 1f. Similar to the analysis in Mode 1f, in order to reduce the backflow power and achieve ZVS for all the switches in Mode 3f, the following should be satisfied: ir(t0)/n  −IZVS2, ir(t1)/n = IZVS2, ir(t2) = IZVS1, and ir(t3) = IZVS1. Therefore, the duty cycles of the two full bridges should meet the following constraint. 8 > > < D2

Mode3f

> > : D1

Mode3f


 1 4Lr IZVS2 þ us ¼ M  1 Vbat T 4Lr IZVS1 ¼ þ MD2 Mode3f Vbat Ts

ð9:10Þ

In this constraint, the output power is expressed as Po ¼

Vbat Vo Ts u D2 nLr 2p

ð9:11Þ

(4) Mode 4f (Fig. 9.2d) Mode 4f also can be viewed as exchanging with the two input and output ports in Mode 2f. In this mode, the output power is expressed in (9.12). Po ¼

 Vo Vbat Ts  2us  D22 þ 2D2  u2s  1 8nLr

ð9:12Þ

The rms current in the working mode is expressed in (9.13). Using the same Lagrange multiplier method of Mode 2f, Irms_Mode4f can get the minimum value for a fix output power, when the duty cycles of the two full bridges meet the following constraint.

2 Irms Model4f

2 ¼ Ts

ZTs =2 ir ðtÞ2 dt ¼

2 2 Vbat k 3D22 M 2  2D32 M 2  3D22 Mus 3

0

þ 3D22 M þ 6D2 Mus  6D2 M  Mu3s þ 3Mu2s  3Mus þ M þ 1



ð9:13Þ 8
< D1 ¼ minð1; D1 Mode1 ; D1 Mode2 Þ
 D1 Mode1 4nLr IZVS2 > þ : D2 ¼ min 1; M Vo Ts

ð9:15Þ

where 8 < D1 :

D1

Mode1 Mode2

  M r IZVS1 ¼ 1M jus j þ 4LVbat Ts pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi M þ jus j1 þ ðM 2 þ 1Þðjus j1Þ2 þ 2M ðjus j1Þ þ M 2 ¼ M

ð9:16Þ

D1_Mode1 is the expression combining Mode 1f and Mode 1r for both forward and reverse power flow, which can be derived from (9.2). D1_Mode2 is the expression combining Mode 2f and Mode 2r, which can be derived from (9.9).

9.2 Modulation Scheme for Seamless Transition and Performance Analyses

201

Vbat=400V

(a)

D2_Mode1f

D 1 & D2

D2_Mode2f

D1_Mode2f Mode 1r

Mode 2r

Mode 1f

D1_Mode1f Mode 2f

φ (rad)

D2_Mode2f

D1_Mode2f Value step change

D2_Mode1f

φ (rad)

D1_Mode1f Mode 2r

Mode 1r

Mode 1f

Mode 2f

D2_Mode2f

D1_Mode2f

D1_Mode1f Mode 1r

Mode 2r

Vbat=400V

Mode 1f

D2_Mode1f D 1 & D2

(c)

Vbat=400V

D1 & D 2

(b)

Mode 2f

φ (rad)

Fig. 9.4 Curves of the duty cycles versus u for M = 0.75: a Curves of the expressions in (9.2) and (9.8); b Trajectories according to optimal working modes; c Improved trajectories for seamless transition

9.2.2

Modulation Scheme When M > 1

When the conversion ratio M is larger than 1, the converter works in Mode 3f and Mode 4f. Similar to Sect. 9.2.1, the curves of duty cycles in (9.10) and (9.14) versus u are shown in Fig. 9.5a, where Ts = 10 ls, Lr = 60 lH, n = 1 A, IZVS1 = 1 A, IZVS2 = 1 A, Vbat = 200 V, and Vo = 300 V. Figure 9.5b shows the trajectory in different working modes for ZVS and minimum rms current. There is also value in

9 Modulation Scheme of Dual Active Bridge Converter …

202

Vbat=200V

(a)

D1_Mode3f

D1 & D 2

D1_Mode4f

Mode 3f

Mode 4r

Mode 3r

D2_Mode4f D2_Mode3f Mode 4f

φ (rad)

(c) D1_Mode4f

D2_Mode4f D2_Mode3f

D1_Mode3f

Mode 4r

Mode 4f

D1_Mode4f

D2_Mode4f

φ (rad)

Mode 3f

Mode 4r

Mode 3f

Value step change

Mode 3r

D1 & D2

D1_Mode3f

Vbat=200V

Mode 3r

Vbat=200V

D1 & D2

(b)

D2_Mode3f Mode 4f

φ (rad)

Fig. 9.5 Curves of the duty cycles versus u for M = 1.5: a Curves of the expressions in (9.10) and (9.15); b Trajectories according to optimal working modes; c Improved trajectories for seamless transition

step change at the boundary of Mode 3f and Mode 4f, which is the same as the case of M < 1. The improved trajectory for seamless transition is shown in Fig. 9.5c. The improve trajectory is expressed as (

where

D2 ¼ minð1; D2 Mode3 ; D2 Mode4 Þ  r IZVS1 D1 ¼ min 1; 4LVbat Ts þ MD2 Mode3

ð9:17Þ

9.2 Modulation Scheme for Seamless Transition and Performance Analyses

8 < D2 :D

Mode3

2 Mode4

 þ jus j qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ¼ 1 þ M jus j  M þ ðM 2 þ 1Þðjus j  1Þ2 þ 2M ðjus j  1Þ þ 1 1 ¼ M1



203

4Lr IZVS2 Vbat Ts

ð9:18Þ D2_Mode3 is the expression combining Mode 3f and Mode 3r for both forward and reverse power flow, and D4_Mode4 is the expression combining Mode 4f and Mode 4r.

9.2.3

Unified Modulation Scheme

In Sects. 9.2.1 and 9.2.2, the modulation schemes for M < 1 and M > 1 have been analyzed. The case of M = 1 is the boundary between M < 1 and M > 1. The modulation schemes for both M < 1 and M > 1 should cover the case of M = 1. Otherwise, seamless transition can not be obtained between the cases of M < 1 and M > 1. In terms of (9.15) and (9.17), Fig. 9.6 shows the three-dimensional (3D) surfaces of D1 and D2 versus Vbat and u, where Ts = 10 ls, Lr = 60 lH, n = 1, IZVS1 = 1 A, IZVS2 = 1A, and Vo = 300 V. As illustrated in Fig. 9.6, D1 and D2 are varied smoothly with Vbat and u without sudden change, which illustrates the seamless transition between the cases of M < 1 and M > 1. Based on the improved modulation scheme, Fig. 9.7 shows the surfaces of output power versus Vbat and u. The output power is continuously varied from Vbat and u, which demonstrates that the modulation scheme can cover all the required load power. When u is larger than zero, the converter works in forward power flow and vice versus. Based on the above analyses, D1 and D2 have been built the

(a)

(b)

Vbat (V)

D2 Duty cycle

Duty cycle

D1

M1

φ (rad)

Vbat (V)

M1

φ (rad)

Fig. 9.6 Three-dimensional (3D) surfaces of D1 and D2 versus Vbat and u: a D1 versus Vbat and u; b D2 versus Vbat and u

9 Modulation Scheme of Dual Active Bridge Converter …

204

Po (W)

Vbat (V)

φ (rad)

Fig. 9.7 Surfaces of output power versus Vbat and u

relationship with M and u. Therefore, the control loop can build relationship to u in both forward and reverse power flow. The flowchart of the modulation scheme and control diagram is shown in Figs. 9.8 and 9.9, respectively. The output voltage is controlled by proportional-integral (PI) controller. The output of the controller is the phase-shift angle. D1 and D2 are calculated based on the value of u, which is got through the voltage regulator as shown in Fig. 9.9. According to D1, D2, and u, the gate signals of Q1–Q8 are generated. As seen in the flowchart, only four calculation expressions are necessary for the modulation scheme. Furthermore, there is only one square root operation in each control interval. It is easy to be implemented in high switching frequency applications by employing digital signal processors.

9.2.4

Switch Conduction Loss Comparison

The rms current in the transformer reflects the conduction loss in the switches and transformer. The rms current curves for different modulation schemes are shown in Fig. 9.10, where Ts = 10 ls, Lr = 60 lH, n = 1, IZVS1 = 1, IZVS2 = 1, and Vo = 300 V. The rms current with the presented modulation scheme is compared with that with SPS and optimal DPS (ODPS). In ODPS, the peak current in the transformer is set as the optimized target, which has been presented in [3, 5]. In no load cases, the rms current in ODPS is zero, because the duty cycles of the two full bridges are reduced to zero. In the presented modulation scheme, there is some circulating current in the transformer for ZVS, so the rms current in no loads is larger than that in ODPS. However, in ODPS, at least a pair of switches can not

9.2 Modulation Scheme for Seamless Transition and Performance Analyses

205

Determine the control variable φ, where -π/2 φ π/2 . Sample Vbat and Vo Calculate M Yes (M 1)

M

⎧ D1 = min (1, D1 _ Mode1 , D1 _ Mode 2 ) ⎪⎪ ⎨ ⎛ D1 _ Mode1 4nLr I ZVS 2 ⎞ + ⎪ D2 = min ⎜1, ⎟ M VoTs ⎠ ⎝ ⎩⎪

1

No (M >1)

⎧ D2 = min (1, D2 _ Mode 3 , D2 _ Mode 4 ) ⎪⎪ ⎨ ⎛ 4 Lr I ZVS 1 ⎞ + MD2 _ Mode 3 ⎟ ⎪ D1 = min ⎜1, V T bat s ⎝ ⎠ ⎩⎪

Return Fig. 9.8 Flowchart of the modulation scheme

Vref

PI

φ

D1 Modulation scheme in Fig.9.8 D2

Vo

φ

PWM

Q1-Q8

Fig. 9.9 Closed-loop control diagram

achieve ZVS in all the working modes, which cause more switching loss. For different battery voltages, the presented modulation scheme has lower rms current in both light and heavy loads. Especially, when the battery voltage deviates from the case of M = 1, the advantage of low conduction loss is more obvious.

9.2.5

Peak Current Comparison

The core loss in the series-connected inductor is associated with the peak current in the inductor. The lower peak current in the transformer causes lower core loss of the series inductor. The curves of the peak current in the transformer versus the load power are shown in Fig. 9.11, where Ts = 10 ls, Lr = 60 lH, n = 1, IZVS1 = 1 A, IZVS2 = 1 A, and Vo = 300 V. The presented modulation scheme does not have

9 Modulation Scheme of Dual Active Bridge Converter …

206

(a)

(b)

Irms (A)

Irms (A)

Vbat=400V

Vbat=200V

ODPS

SPS

ODPS SPS

Presented modulation scheme

Presented modulation scheme

Po (W)

Po (W)

Fig. 9.10 Rms current in the transformer versus the load power for different modulation schemes and different battery voltages: a Vbat = 400 V (M = 0.75), b Vbat = 200 V (M = 1.5)

(a)

(b) Ir_peak (A)

Ir_peak (A) Vbat=400V SPS

ODPS

Presented modulation scheme

Vbat=200V SPS

ODPS

Presented modulation scheme

Po (W)

Po (W)

Fig. 9.11 Peak current in the transformer versus the load power for different modulation schemes and different battery voltages: a Vbat = 400 V (M = 0.75), b Vbat = 200 V (M = 1.5)

large peak current in the transformer, which indicates low core loss in the series-connected inductor.

9.3 Experimental Validation

9.3

207

Experimental Validation

A 1.2 kW experimental prototype of the DAB converter is built to verify the unified modulation scheme. The detailed specifications are shown in Table 9.1. The output voltage is control in a constant voltage. Figure 9.12 shows the prototype for test. Figure 9.13 shows the experimental results without seamless transition. Although the converter works in the optimal working modes (as seen in the trajectory shown in Fig. 9.4b), D1 will be suddenly changed at the boundary of the adjacent working modes. As seen in Fig. 9.13, the converter is unstable at this boundary. For safety considerations, the experimental result without seamless transition is verified in low voltage and low power cases.

Table 9.1 Detailed specifications Items

Symbol

Parameter

Battery voltage Output voltage Turns ratio of the transformers Switching frequency (period) Switches Series inductor Output filter capacitance Dead time IZVS1, IZVS2

Vbat Vo n fs(Ts) Q1–8 Lr Co tdead IZVS1, IZVS2

200–400 V 300 V 1 100 kHz (10 ls) FDA50N50 (Fairchild) 60 lH 30 lF 400 ns 1A

Auxiliary Power supply and Sensor board

Q1-4 and drive circuit

Vbat+ VbatVo+

Control board

Lr

Tr

VoFig. 9.12 Experimental prototype for test

Q5-8 and drive circuit

208

9 Modulation Scheme of Dual Active Bridge Converter …

vAB

(100V/div)

vCD

(100V/div)

ir (1A/div)

Time base:40ms /div

Time base:4μs /div

Time base:4μs /div

Fig. 9.13 Experimental results without working modes in seamless transition

Figure 9.14 shows the key waveforms in steady state. Figure 9.14a–c show the waveforms for Vbat = 380 V, in which M is less than 1. In Fig. 9.14a, the output power is 70 W, and the converter works in Mode 1f for the light load. With the increase of the output power, the converter switches into Mode 2f. As seen in Fig. 9.14b, vab is a three-level waveform and vcd is a two-level waveform. If the output power continues to increase, vAB becomes a two-level waveform to reduce the rms current in the transformer. Figure 9.14d–f show the waveforms for Vbat = 210 V, in which M is larger than 1. In Fig. 9.14d, the converter works in Mode 3f for 70 W output power, and vAB and vCD are three-level waveforms. With the increase of the output power, the phase-shift angle becomes larger, and the converter works in Mode 4f. As seen in Fig. 9.14e, vAB becomes a two-level waveform. With the increase of the output power continuously, vCD also becomes a two-level waveform, and the converter actually works in SPS. All the experimental waveforms verify the modulation trajectory shown in Fig. 9.6. Figure 9.15 shows the transient experimental results for the load step change from 80 to 1000 W. Figure 9.15a shows the transient performance for Vbat = 380 V. During the transition, the converter transfers seamlessly from Mode 1f to Mode 2f without large current and voltage overshoot. Figure 9.15b shows the transient performance for Vbat = 210 V, in which the converter seamless transfers form Mode 3f to Mode 4f. Figure 9.15 demonstrates the stability and seamless transition using the presented modulation scheme.

9.3 Experimental Validation

209

(a)

(b)

Vbat=380V, Po=70W

vAB

Vbat=380V, Po=750W

(500V/div)

vCD

vCD

(500V/div)

(500V/div)

ir

Time base:2μs /div

vAB

(500V/div)

ir

(2A/div)

Time base:2μs /div

(5A/div)

(d)

(c)

Vbat=380V, Po=1100W

vAB

Vbat=210V, Po=70W

(500V/div)

vCD

vCD

(500V/div)

(500V/div)

ir

Time base:2μs /div

ir

(5A/div)

(e)

vAB

(500V/div)

Time base:2μs /div

(2A/div)

(f)

Vbat=210V, Po=600W

vAB

Vbat=210V, Po=1100W

(500V/div)

vCD

vCD

(500V/div)

(500V/div)

ir

Time base:2μs /div

(5A/div)

vAB

(500V/div)

ir

Time base:2μs /div

(10A/div)

Fig. 9.14 Key waveforms in steady state: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W; c Vbat = 380 V, Po = 1200 W; d Vbat = 210 V, Po = 70 W; e Vbat = 210 V, Po = 600 W; f Vbat = 210 V, Po = 1200 W

Figure 9.16 shows the gate signal and drain-source voltage of switch Q1 for Vbat = 380 V, i.e., M < 1 case. In both the light load and heavy load, the current at the time of Q1 turn-on is less than zero, which leads to ZVS. Figure 9.17 shows the gate signal and drain-source voltage of switch Q4 for Vbat = 380 V. The voltage across Q4 is discharged to zero before Q4 is turned on, which demonstrates the ZVS performance of Q4. Figure 9.18 shows the gate signal and drain-source voltage of switch Q5 for Vbat = 380 V. The current in the transformer is on less than IZVS2. Therefore, the current flows through the body diode of Q5 before Q5 is turned on. Figure 9.19 shows the gate signal and drain-source voltage of switch Q8 for Vbat = 380 V. The current in the transformer is on less than IZVS2. Therefore, Q8

9 Modulation Scheme of Dual Active Bridge Converter …

210

(a)

(b)

vAB

vAB

(500V/div)

(500V/div)

vCD

vCD

(500V/div)

(500V/div)

(100V/div)

(100V/div)

(5A/div)

(10A/div)

vo

vo

Time base:10ms /div

Time base:4μs /div

ir

ir

Time base:10ms /div

Time base:4μs /div

Time base:4μs /div

Time base:4μs /div

Fig. 9.15 Transient experimental results for load step change from 80–1000 W: a Vbat = 380 V (M = 0.79); b Vbat = 210 V (M = 1.43)

(a)

(b) Q1 ZVS

vds1

Q1 ZVS

(100V/div)

vds1

(100V/div)

vgs8

vgs1

(10V/div)

(10V/div)

ir

ir

(2A/div) Time base:2μs /div

Time base:2μs /div

(5A/div)

Fig. 9.16 Gate signal and drain-source voltage of switch Q1: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W

(b)

(a) Q4 ZVS

vds4

Q4 ZVS

(100V/div)

vgs4

vgs4

(10V/div)

(10V/div)

ir

ir

Time base:2μs /div

(2A/div)

vds4

(100V/div)

Time base:2μs /div

(5A/div)

Fig. 9.17 Gate signal and drain-source voltage of switch Q4: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W

9.3 Experimental Validation

211

(a)

(b) Q5 ZVS

vds5

Q5 ZVS

(100V/div)

vgs5

vgs5

(10V/div)

(10V/div)

ir

Time base:2μs /div

vds5

(100V/div)

ir

(2A/div)

Time base:2μs /div

(5A/div)

Fig. 9.18 Gate signal and drain-source voltage of switch Q5: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W

(a)

(b) Q8 ZVS

vds8

Q8 ZVS

(100V/div)

vgs8

vgs8

(10V/div)

(10V/div)

ir

ir

(2A/div) Time base:2μs /div

vds8

(100V/div)

Time base:2μs /div

(5A/div)

Fig. 9.19 Gate signal and drain-source voltage of switch Q8: a Vbat = 380 V, Po = 70 W; b Vbat = 380 V, Po = 820 W

also can achieve ZVS. Because M < 1 case is symmetrical to M > 1 case. Therefore, When M > 1, the converter also can work in ZVS. The measured efficiency curves of the DAB converter with the presented modulation scheme, SPS, and ODPS are illustrated in Fig. 9.20. When the battery voltage is 300 V, the duty cycles of the two full bridges are equal to one in all the modulation schemes. Therefore, the efficiency curves of the three modulation schemes are the same. When the battery voltage deviates from 300 V, i.e., the voltage conversion ratio deviates from one, the converter with the presented modulation scheme has higher efficiency because of low conduction loss and low peak current in the transformer. As seen the curves for Vbat = 210 V and Vbat = 380 V, the duty cycles of the two full bridges become one with the increase of the load power. In this case, the converter will work in SPS. The rms and peak current of the transformer in the presented modulation scheme also becomes lower than that in ODPS. Furthermore, the presented scheme can maintain wide ZVS performance. Therefore, the efficiency becomes higher than the ODPS. The efficiency curves demonstrate the rms and peak current comparisons in Sects. 9.2.4 and 9.2.5.

9 Modulation Scheme of Dual Active Bridge Converter …

212

Effiiciency Effi

(a)

Po (W)

Efficiency

(b)

Po (W)

Fig. 9.20 Efficiency curves of the DAB converter with the presented modulation scheme, SPS, and DPS: a Vbat = 300 V and Vbat = 380 V, b Vbat = 210 V

9.4

Conclusion

In this chapter, a modulation scheme for DAB converter is introduced for low conduction loss and wide ZVS in wide battery voltage. The key features of the different effective working modes are analyzed. The relationship between the duty cycles of the full bridges and the phase-shift angle is revealed to achieve ZVS and minimum rms current in transformer. The constraints on the different working modes are investigated to compromise the optimized working modes and seamless transition. In all the cases, the duty cycles of the two full bridges are continuously varied from the phase-shift angle. The closed-loop control strategy and the flow chart of the modulation scheme are introduced. The flowchart illustrates that only four expressions are necessary for the modulation scheme, so it is easy to be

9.4 Conclusion

213

implemented. The rms and peak current in DAB converter by using the presented modulation scheme is compared with some previous works. The presented modulation scheme has lower rms current and peak current. Therefore, the conduction loss and the core loss in the series-connected inductor are reduced. Finally, the experimental prototype demonstrates that the presented modulation scheme can achieve higher efficiency in wide battery voltage range.

References 1. Huang J, Wang Y, Li Z, Lei W (2016) Unified triple-phase-shift control to minimize current stress and achieve full soft-switching of isolated bidirectional DC–DC converter. IEEE Trans Ind Electron 63(7):4169–4179 2. Tong A, Hang L, Li G, Jiang X, Gao S (2018) Modeling and analysis of a dual-active-bridge-isolated bidirectional DC/DC converter to minimize RMS current with whole operating range. IEEE Trans Power Electron 33(6):174–188 3. Hou N, Song W, Wu M (2016) Minimum-current-stress scheme of dual active bridge DC–DC converter with unified phase-shift control. IEEE Trans Power Electron 31(12):8552–8561 4. Krismer F, Kolar JW (2012) Closed form solution for minimum conduction loss modulation of DAB converters. IEEE Trans Power Electron 27(1):174–188 5. Zhao B, Song Q, Liu W, Sun W (2013) Current-stress-optimized switching strategy of isolated bidirectional DC–DC converter with dual-phase-shift control. IEEE Trans Ind Electron 60 (10):4458–4467

Chapter 10

An Improved Modulation Scheme of Current-fed Bidirectional DC–DC Converters for Loss Reduction

Abstract Current-fed bidirectional DC–DC converters have attracted much attention in battery energy storage system (BESS) applications due to their zero-voltage-switching (ZVS) performances and greater degree of control freedom. However, high efficiency is difficult to be achieved for both light and heavy load ranges for a current-fed bidirectional DC–DC converter, especially with low battery voltages. In this chapter, a modulation scheme is introduced to improve the conversion efficiency over a wide load range and with variations in the battery voltage. The relationship between the duty cycle of the secondary full-bridge and the phase-shift angle is investigated to lower the power losses with the wide load variations. Based on the operation mode analysis, the control loop with the modified pulse wide modulation (PWM) plus phase-shift modulation scheme is developed. Comparisons of the switch conduction loss and the core loss in the series inductor for the other modulation schemes and the presented modulation scheme are carried out. The results show that lower power losses occur with the improved scheme. The experimental results verify the theoretical analysis and effectiveness of the presented modulation scheme on loss reduction. Keywords Current-fed duction loss

10.1


Dual active bridge
PWM plus phase-shift
Low con-

Operation Modes of the Current-fed Bidirectional DC–DC Converter

10.1.1 Review of the Modulations for the Current-fed Bidirectional DC–DC Converter Figure 10.1 shows the circuit of the current-fed bidirectional DC–DC converter. Lf1 and Lf2 are the DC inductors on the battery side and Lf1 = Lf2 = Lf. The average current in iL1 and iL2 is defined as IL. Lr is the series inductor for the phase-shift modulation. Vbat is the battery voltage. Vo is the output voltage, and Vc is the © Springer Nature Singapore Pte Ltd. 2020 Z. Guo and D. Sha, New Topologies and Modulation Schemes for Soft-Switching Isolated DC–DC Converters, CPSS Power Electronics Series, https://doi.org/10.1007/978-981-32-9934-4_10

215

10 An Improved Modulation Scheme of Current-fed …

216

voltage of the clamping capacitor. The reference of Vc was set to be Vo/n, where n is the turns ratio of the transformer. nVc/Vo = 1 is not the optimized condition for minimum rms current in the transformer at high power [1]. However, if nVc/Vo is not equal to 1, the converter may not maintain ZVS of all the switches [1]. Therefore, nVc/Vo = 1 is a good precondition for all the switches to work in ZVS. Moreover, when nVc/Vo = 1, the peak current in the transformer during heavy load is reduced, and the core loss in the series inductor can be reduced. To synthesize conduction loss and soft-switching analyses, the premise of nVc/Vo = 1 is set. Figure 10.2 shows the modulation strategies for the current-fed bidirectional DC– DC converter. Figure 10.2a is the PWM plus phase-shift (PPS) modulation [2]. On the battery side, Q1–Q4 are modulated by the PWM to control the voltage of the clamping capacitor, where D1 is the duty cycle of Q2 and Q4. Ts is the switching period. The bidirectional power flow is modulated by the phase shift between vAB and vCD, where u is the phase-shift angle. The voltage amplitude of vAB is Vo/n, and the voltage amplitude of vCD is Vo. In Fig. 10.2a, Q5 and Q8 are the same gate signal, and Q6 and Q7 are the same gate signal. Therefore, vCD has a square o D1 Ts o Ts waveform. The peak current in the transformer is expressed as V2nL  V4nL , and this r r will be analyzed in the following section. The peak current is not associated with the phase-shift angle u. Especially under light loads, the transformer and switches have to handle a large current amplitude. The efficiency under light loads becomes very low. Figure 10.2b is the PWM plus dual-phase-shift (PPDPS) modulation [1]. In this modulation scheme, the primary switches work in PWM control, and the secondary full-bridge works in a phase-shift manner. D2 is the effective duty cycle in the secondary full bridge. The power flow is controlled by the phase shift between vAB and vCD. Compared with PPS modulation, the peak current in the transformer is reduced. The time interval for power transmission is the positive or negative voltage overlap of vAB and vCD, which decreases with the increase of the phase-shift angle u in PPDPS. Based on voltage-second balance, the decrease of the time interval causes a large peak current in the transformer for the constant power transmission. This occurs under heavy loads. To overcome the drawback of these modulation schemes, this chapter will introduce the different operation modes for the current-fed bidirectional DC–DC converter.

Vc

Ccl

ibat iL1 Lf1

Vbat

iL2 Lf2 Cf Q2

Q5 ip 1:n is

Q3

Q1 A

Lr

B Q4

battery

Fig. 10.1 Current-fed bidirectional DC–DC converter

Q7 C

Vo D

Tr

Q6

Q8

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

(a) Q2 Q3 Q6 Q7

Q1 Q4 Q5 Q8

D1Ts Q2 Q3 Q6 Q7

vCD LargevAB φ current (1-D1)Ts spike iL1 iL2

(b) Q1 Q4 Q5 Q8

Q2 Q3 Q6 Q7

ip

Q2 Q3 Q6 Q7

vAB

iL1 iL2

Q1 Q4 Q5 Q8 D2Ts/2

φ

D1Ts Q2 Q3

217

Q1 Q4 Q6

Q7

Q5

Q8

Q2 Q3 Q6 Q7

vCD

(1-D1)Ts

ip

Fig. 10.2 Conventional modulation strategies for a current-fed bidirectional DC–DC converter: a PPS and b PPDPS

Table 10.1 ZVS conditions Switches

Current during the switch-on

ZVS conditions during commutation

Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8

ip(t) − max (iL1) min (iL1) − ip (t) −max (iL2) − ip (t) min (iL2) + ip (t) −ip(t)/n ip(t)/n ip(t)/n −ip(t)/n

max (iL1) − ip (t) > ΔIp ip(t) − min (iL1) > ΔIp max (iL2) + ip(t) > ΔIp −min (iL2) − ip(t) >ΔIp ip(t)/n > ΔIs −ip(t)/n > ΔIs −ip(t)/n > ΔIs ip(t)/n > ΔIs

The ZVS conditions for the switches are shown in Table 10.1, where ΔIp is the minimum current amplitude to charge and discharge the junction capacitors of the switches on the battery side for ZVS, and ΔIs is the minimum current to charge and discharge the junction capacitors of the switches on the output side for ZVS. The ZVS conditions for Q1–Q4 are associated with the current ripple of the DC inductor current. If the DC inductor currents iL1 and iL2 have a large current ripple, Q1–Q4 can easily achieve ZVS. The research focus in this chapter is how to optimize the modulation scheme to reduce losses on the premise of the ZVS.

10.1.2 Analyses of the Key Operation Modes Considering the practical operation modes, the converter should have a sufficient time interval to transmit power. As seen in Fig. 10.2, the positive or negative voltage overlap of vAB and vCD needs to be as much as possible. Figure 10.3 shows the operation modes of the current-fed bidirectional DC–DC converter for the case

10 An Improved Modulation Scheme of Current-fed …

218

(a) Q1 Q2 Q3 Q4 Q5 φ vAB

iL1 iL2

Q7Q6 vCD

ip t0t1 t2 t3t4 t5t6

(c) Q1 Q2 Q3 Q4

Q5 Q7 Q6 Q8 vCD φ

vAB iL1 iL2

ip

t0 t1t2 t3t4t5t6

Q2Q3 Q4 Q 5 Q7 Q 6 Q8 vCD φ

(e) Q1 vAB iL1 iL2 ip

t0 t1 t2 t3t4t5 t6

(g) Q1

Q2Q3 Q4 Q8Q5 Q7Q6 vCD vAB φ

iL1 iL2

ip

(b)

Q1 Q2 Q3 Q4 Q7Q6 Q8 Q5 vCD -φ vAB

Q8

ip iL1 iL2

t0 t1t2 t3t4t5t6

(d) Q4 Q1 Q2 Q3 vCD ip iL1 iL2

Q5 Q7 Q6 Q8 -φ vAB

t0 t1 t2 t3 t4 t5 t6

(f)

Q1 Q2Q3 Q4 Q5 Q7 Q6 Q8 v vAB -φ CD

ip iL1 iL2

t0 t1t2 t3t4t5t6

(h) Q4Q1 Q2Q3

Q5 Q7Q6 Q8 vCD vAB -φ ip

t0t1 t2 t3t4t5 t6

iL1 iL2

t0 t1 t2 t3 t4t5t6

Fig. 10.3 Different operation modes of the current-fed bidirectional DC–DC converter: a Mode 1a, b Mode 1b, c Mode 2a, d Mode 2b, e Mode 3a, f Mode 3b, g Mode 4a, and h Mode 4b

when −p/2  u  p/2; these modes take into consideration of the variables D1, D2, and u. Table 10.2 shows the boundary condition of the operation modes, where 0.5  D1  1 and 0  D2  1. The power transmitted from the battery to the output is defined as the forward power flow, where u is greater than zero. The power transmitted from the output to the battery is defined as the reverse power flow, where u is less than zero. Because the forward and reverse power flows are symmetric, only the forward power flow was analyzed. Furthermore, the reverse power flow can be analyzed in the same manner, and the same conclusion can be drawn.

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

219

Table 10.2 Boundary condition of the operation modes Forward power flow (u > 0)

Reverse power flow (u < 0)

Mode 1a: 0 < u < p(D1 − 1 + D1/2) Mode 2a: 0 < max{p(1 − D1 − D2/2), (D2/ 2 + D1−)} < u < min{p(D1 − D2/2), p(1 − D1 + D2/2)} Mode 3a: 0 < u < p(1 − D1 − D2/2) Mode 4a: 0 < p(D1 − D2/2) < u < min {p(1 − D1 + D2/2), p/2}

Mode 1b: p(1 − D1 − D2/2) < u < 0 Mode 2b: max{p(D1 − 1 − D2/2), p(D2/ 2 − D1)} < u < min{p(D1 − 1 + D2/2), p(1 − D1 − D2/2)} < 0 Mode 3b: p(D1 − 1 + D2/2) < u < 0 Mode 4b: max{p(D1 − 1 − D2/2), −p/2} < u < p(D2/ 2 − D1) < 0

For the forward power flow in Fig. 10.3, the ZVS for Q1 and Q2 is determined by the error between the current in the filter inductor Lf1 and the current in the transformer; ZVS for Q3 and Q4 is determined by the sum of the currents in the filter inductor Lf2 and the transformer. Because nVc/Vo = 1, the slew rate of the current in the transformer is zero during the time interval of a positive or negative voltage overlap in vAB and vCD. As long as the current ripple in Lf1 and Lf2 is large enough, ZVS for Q1–Q4 can be achieved. As shown in Mode 1a in Fig. 10.3a, ip(t1) is greater than zero, and ip(t4) is less than zero. According to Table 10.1, Q5 and Q7 have the potential to achieve ZVS. For Mode 2a in Fig. 10.3c, ip(t2) is greater than zero, and ip(t4) is less than zero, hence Q5 and Q7 have the potential to achieve ZVS. For Mode 3a in Fig. 10.3e, ip(t2) and ip(t3) are both greater than zero, in which Q5 has the potential to achieve ZVS. However, Q7 can not achieve ZVS in this case. For Mode 4a in Fig. 10.3e, ip(t2) is greater than zero and ip(t5) is less than zero, so Q5 and Q7 have the potential to achieve ZVS. For Q6, the same conclusion with Q5 can be derived. For Q8, the same conclusion with Q7 can be derived. Not all the switches in Mode 3a can achieve ZVS, but all the switches in Modes 1a, 2a, and 4a have the potential to achieve ZVS. Modes 1a, 2a, and 4a will be the key operation modes analyzed in this chapter. To simplify the analyses in this subsection, the commutation during the dead time interval is ignored. (1) Mode 1a The key waveforms of Mode 1a are shown in Fig. 10.3a. The current in the transformer during half of the switching period is expressed as 8 Ip0 > >

p2 2 \t\t3 Þ > : I  Vo ðt  t Þ ðt \t\t Þ p3 3 3 4 nLr

t0 t1 t2 t3 t4

¼ 0  ¼ 12  D22 Ts D  u Ts  ¼  21  D42  2p u D1 D2 Ts ¼ 1  2  4  2p ¼ 12 Ts

ð10:1Þ

10 An Improved Modulation Scheme of Current-fed …

220

where Vo D2 Ts Vo ð1  D1 ÞTs  4nLr 2nLr Vo Ts  u  ¼ Ip3 ¼ nLr 2p Vo ð1  D1 ÞTs Vo D2 Ts ¼  2nLr 4nLr

Ip0 ¼ Ip1 ¼ Ip2 Ip4

ð10:2Þ

When D2 is equal to 1, Mode 1a becomes the PPS modulation. Substituting o D1 Ts o Ts D2 = 1 into (10.2), the peak current in PPS is expressed as V2nL  V4nL . r r The transmitted power in Mode 1a is expressed as 2 Po ¼ Ts

Zt4 t0

  V 2 Ts u vAB ip dt ¼ 2o ð1  D1 Þ p n Lr

ð10:3Þ

The power is associated with D1 and u but independent of D2. In this mode, the u 1 \ D42  1D phase angle is in the range of 0\ 2p 2 . Equation (10.2) shows that, in order to reduce the peak current, D2 should be reduced. The minimum value of D2 in this mode is 2u p þ 2ð1  D1 Þ. In this case, the key waveforms of the modified Mode 1a are shown in Fig. 10.4. During the switching period, Q1 and Q5 are commutated at the same time, and Q3 and Q6 are commutated at the same time. The peak current amplitude is reduced. (2) Mode 2a The key waveforms of Mode 2a are shown in Fig. 10.3c. The current in the transformer during half of the switching period is expressed as

ip ðtÞ ¼

8 Ip0 > >

> :I  p3

Vo nLr

ðt  t1 Þ

Vo nLr

ðt  t3 Þ

ðt0 \t\t1 Þ ðt1 \t\t2 Þ ðt2 \t\t3 Þ ðt3 \t\t4 Þ

t0 t1 t2 t3 t4

¼ 0  u ¼ D21  D42  2p Ts ¼ 12  D22 Ts   u Ts ¼ 1  D21  D42  2p ¼ 12 Ts

Fig. 10.4 Modified Mode 1a

iL1 iL2 ip

Q1 Q2 Q3 Q4 Q5 Q7Q6 Q8 φ vCD vAB

t0 t1 t2t3

ð10:4Þ

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

221

where Vo D2 Ts Vo ð1  D1 ÞTs  4nLr 2nLr Vo Ts  u  ¼ Ip3 ¼ nLr 2p Vo ð1  D1 ÞTs Vo D2 Ts ¼  2nLr 4nLr

Ip0 ¼ Ip1 ¼ Ip2 Ip4

ð10:5Þ

The transmitted power is expressed as Po ¼

  V 2 Ts D2 D22 u2 D1 D2   2 vAB ip dt ¼ o2 2n Lr 2 8 2p 2 t0  u D2 D2 u D1 u 1   þ  1 þ D1 þ p 2p p 2 2 2 Ts

Zt4



ð10:6Þ

In this mode, the phase angle is in the range expressed by (10.7), in which Eq. (10.8) is satisfied.           D2 D2 D2 D2 þ D1  1 0\max p 1  D1   u  min p D1  ;p ; p 1  D1 þ 2 2 2 2

ð10:7Þ 8    2 dPo Vo Ts u D2 > > > þ ¼  D 1  1 [0 > > p du n 2pLr 2 > > >    2 < dPo Vo Ts D2 u þ ¼ 1  D1  [0 > p dD2 n 4Lr 2 > > >  2 > > > d2 Po Vo Ts > : ¼ [0 dD2 du n 4pLr

ð10:8Þ

Therefore, the output power is increased with the increase of D2 or u. The rms qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi R T =2 current in the transformer is expressed as ip rms ðD2 ; uÞ ¼ T2s 0 s ip ðtÞdt. With

the help of Mathcad 15, the relationship of the D2 and u for different output powers in Mode 2a is shown in Fig. 10.5, where Vc = Vo/n = 134 V, Lr = 14 lH, Vbat = 48 V, and Ts = 12.5 ls. Figure 10.5a shows D2 versus u for different output powers. In order to keep the output power constant, D2 is decreased with the increase of the phase-shift angle u. Figure 10.5b shows the rms current in the transformer versus u for different output powers. For a constant output power, the rms current in the transformer increases with the increase of the phase-shift angle u. Simultaneously, D2 is decreased. Therefore, in order to reduce the rms current in the transformer, the phase-shift angle u should be as low as possible. Hence, the

10 An Improved Modulation Scheme of Current-fed …

222

(a)

(b)

D2

ip_rms (A)

0.8

16

0.7

14

Po=500 W

0.6 0.5

12

0.4

Po=100 W

4

0.1

2 0.2

0.4

0.6

0.8

1

1.2

1.4

Po=200 W

6

0.2

0

Po=300 W

8

Po=200 W

0.3

Po=500 W

10

Po=300 W

0

φ (rad)

Po=100 W

0.2

0.4

0.6

0.8

φ (rad)

1

1.2

1.4

Fig. 10.5 Relationship between D2 and u for different output powers in Mode 2a: a D2 versus u for different output powers and b rms current in the transformer versus u for different output powers Fig. 10.6 Key waveforms in Mode 2a_m

reactive power during the switching period can be reduced. Equation (10.7) shows that the minimum value of u in Mode 2a is expressed as      max p 1  D1  D22 ; p D22 þ D1  1 . As long as D2 > 2(1 − D1), the minimum

D  value of u is equal to p 22  ð1  D1 Þ . The key waveforms of Mode 2a are shown in Fig. 10.6 for this case. Modified Mode 2a coincides with modified Mode 1a. Actually, it is the boundary mode of Mode 1a and Mode 2a, which is defined as Mode 2a_m. The current in the transformer during half of the switching period for Mode 2a_m is expressed in (10.9). The output power is expressed in (10.10). 8 ðt0 \t\t1 Þ < Ip1 ¼ Ip0 I ¼ I ðt1 \t\t2 Þ ip ðtÞ ¼ p2 p1 : I  Vo ðt  t Þ ðt \t\t Þ p2 2 2 2 nLr

t0 t1 t2 t3

¼ 0  ¼ 12  D22 Ts 3  ¼ 2  D1  D22 Ts ¼ 12 Ts

ð10:9Þ

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

223

where Vo D2 Ts Vo ð1  D1 ÞTs  4nLr 2nLr Vo ð1  D1 ÞTs Vo D2 Ts ¼  2nLr 4nLr

Ip0 ¼ Ip1 ¼ Ip2 ¼ Ip3

ð10:10Þ

The transmitted power in Mode 2a_m is expressed as 2 Po ¼ Ts

Zt4 t0

  V 2 Ts u vAB ip dt ¼ 2o ð1  D1 Þ p n Lr

ð10:11Þ

(3) Mode 4a The key waveforms of Mode 4a are shown in Fig. 10.3g. The current in the transformer during half of the switching period is expressed as 8 o Ip0 þ 2V > nLr ðt  t0 Þ > < Vo ðt  t1 Þ Ip1 þ nL r ip ðtÞ ¼ > Ip2 > : Vo Ip3  nL ðt  t3 Þ r

ðt0 \t\t1 Þ ðt1 \t\t2 Þ ðt2 \t\t3 Þ ðt3 \t\t4 Þ

t0 t1 t2 t3 t4

¼ 0  u Ts ¼ D42  D21 þ 2p 1D  u Ts ¼ 2 1  D42 þ 2p ¼ ð1  D1 ÞTs ¼ 12 Ts

ð10:12Þ

where   Vo Ts D1 u Vo ð1  D1 ÞTs   2p nLr 2 2nLr   Vo D2 Ts Vo Ts 1 D2 u   ¼  2p 4nLr nLr 2 4 Vo Ts  u  ¼ Ip3 ¼ nLr 2p   Vo ð1  D1 ÞTs Vo Ts D1 u  ¼  2p 2nLr nLr 2

Ip0 ¼ Ip1 Ip2 Ip4

ð10:13Þ

The transmitted power is expressed as 2 Po ¼ Ts

Zt4 t0



  Vo2 Ts D2 u D22 u2 1 2 þ D1 þ   D1  2  vAB ip dt ¼ 2 p 2 2n Lr 2 4 p 

ð10:14Þ

In this mode, the phase angle is in the range expressed in (10.15), in which Eq. (10.16) is satisfied.

10 An Improved Modulation Scheme of Current-fed …

224

    D2 D2 p 0\p D1  \u\min p 1  D1 þ ; 2 2 2

ð10:15Þ

8    2 > dPo Vo Ts 2u > > ¼ 1  [0 > > p du n 2pLr > > >  2 < dPo Vo Ts ¼ ð1  D2 Þ [ 0 > dD n 4Lr > 2 > > > 2 > d Po > > : ¼0 dD2 du

ð10:16Þ



Therefore, the output power increases with the increase of D2 and u. The rms current in the transformer in this case is expressed as ip rms ðD2 ; uÞ ¼ ffi qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R 2 Ts =2 i ðtÞdt . With the help of Mathcad 15, the relationship of the D2 and u for p Ts 0 different output powers in Mode 4a is shown in Fig. 10.7, where Vc = Vo/ n = 134 V, Lr = 14 lH, Vbat = 48 V, and Ts = 12.5 ls. Figure 10.7a shows D2 versus u for different output powers. Figure 10.7b shows the rms current in the transformer versus u for different output powers. Based on Fig. 10.7, conclusions similar to those for Mode 2a can be drawn. To reduce the rms current in the transformer, D2 should be as large as possible, so u becomes lower. The maximum value of D2 is equal to 1 in Mode 4a. In this case, the key waveforms of Mode 4a are shown in Fig. 10.8, which is defined as Mode 4a_m. Actually, Mode 4a_m is the PPS when the phase-shift angle becomes larger. The current in the transformer during half of the switching period for Mode 4a_m is expressed in (10.17).

(a)

(b) ip_rms (A)

D2

18

1

Po=1000 W

0.9 0.8

16

Po=800 W

0.7

14

Po=500 W

0.6

Po=400 W

0.5 0.4

10

Po=800 W

8

0.3

Po=500 W

6

0.2 0.1

Po=1000 W

12

0.4

0.6

0.8

1

φ (rad)

1.2

1.4

4

Po=400 W 0.4

0.6

0.8

1

1.2

1.4

φ (rad)

Fig. 10.7 Relationship between D2 and u for different output powers in Mode 4a: a D2 versus u for different output powers and b rms current in the transformer versus u for different output powers

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

225

Q1 Q2Q3 Q4 Q8 Q7 Q5 Q6 vCD vAB φ

Fig. 10.8 Modified Mode 4a

iL1 iL2 ip

8 2V < Ip0 þ nLor ðt  t0 Þ ðt0 \t\t1 Þ ðt1 \t\t2 Þ ip ðtÞ ¼ Ip1 ¼ Ip2 : Vo Ip2  nL ðt  t Þ ðt2 \t\t3 Þ 3 r

t0 t1 t2 t3

t0 t1

t2 t 3

¼ 0  u ¼ D42  D21 þ 2p Ts ¼ ð1  D1 ÞTs ¼ 12 Ts

ð10:17Þ

where Ip0 Ip1 Ip3

  Vo Ts D1 u Vo ð1  D1 ÞTs  ¼  2p nLr 2 2nLk Vo Ts  u  ¼ Ip2 ¼ nLr 2p   Vo ð1  D1 ÞTs Vo Ts D1 u  ¼  2p 2nLr nLr 2

ð10:18Þ

The transmitted power is expressed as 2 Po ¼ Ts

Zt4 t0



   V 2 Ts u u2 1 vAB ip dt ¼ o2 D1 þ  D21  2  p 4 2n Lr p

ð10:19Þ

The modified operation modes for the reverse power flow were derived by analyzing the reverse power flow (Mode 1b, Mode 2b, and Mode 4b) in the same manner, as shown in Fig. 10.9.

(a)

(b)

Q1 Q2 Q3 Q4 Q5 Q7Q6 Q8

vCD

-φ vAB

ip iL1 iL2 t0 t1 t2 t3t4 t5

Q1 Q2Q3 Q4 Q8 Q7 Q5 Q6 vCD vAB -φ ip iL1 iL2 t0 t1t2 t3 t4 t5

Fig. 10.9 Modified mode operation in the reverse power flow: a Mode 2b_m and b Mode 4b_m

10 An Improved Modulation Scheme of Current-fed …

226

10.1.3 ZVS Conditions for the Modified Operation Mode In Sect. 10.1.2, the modified operation modes were presented for optimizing the peak current and rms current without considering the ZVS condition of the switches. In this subsection, the ZVS conditions for the modified operation modes will be analyzed. (1) Mode 2a_m According to (10.9) and (10.10), ip should be no less than nΔIs to achieve the ZVS for Q5 and Q7. The following conditions should be satisfied. Vo D2 Ts Vo ð1  D1 ÞTs   nDIs 4nLr 2nLr 4Lr n2 DIs D2  2ð1  D1 Þ þ ¼ D2m þ Dm ; Vo Ts 4Lr n2 DIs D2m ¼ 2ð1  D1 Þ;Dm ¼ Vo Ts Ip0 ¼ Ip1 ¼

ð10:20Þ

Therefore, the minimum duty cycle of D2 is equal to D2m+ Dm. 1 ÞTs Vo . The current ripple of the DC filter inductor is expressed as DIL ¼ D1 ð1D nLf The maximum and minimum current in iL1 and iL2 are expressed in (10.21). IL1 IL1

max

¼ IL2

min

¼ IL2

max

min

DIL D1 ð1  D1 ÞTs Vo ¼ IL þ 2 2nLf DIL D1 ð1  D1 ÞTs Vo ¼ IL  ¼ IL  2 2nLf ¼ IL þ

ð10:21Þ

o where IL is the average current in iL1 and iL2 and IL ¼ 2VPbat . To achieve the ZVS for Q2, the following condition is derived:

Ip2  IL2

min

  Vo Ts  u  D1 ð1  D1 ÞTs Vc ¼  IL   DIp nLr 2p 2Lf   2pnLr 2pnLr D1 ð1  D1 ÞTs Vc u DIp þ IL  Vo Ts Vo Ts 2Lf

ð10:22Þ

By substituting (10.11) into (10.22), the ZVS condition for Q2 is expressed as Lf 

D1 ð1  D1 ÞTs Vo 2nDIp

ð10:23Þ

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

227

The ZVS condition for Q1 is expressed as IL1

max  Ip0 ¼

  D1 ð1  D1 ÞTs Vo Vo Ts  u  IL þ  DIp  2nLf nLr 2p

ð10:24Þ

The ZVS condition for Q1 is expressed in (10.25) by substituting (10.11) into (10.23), and it is the same as the ZVS condition for Q1. Lf 

D1 ð1  D1 ÞTs Vo 2nDIp

ð10:25Þ

(2) Mode 4a_m According to (10.17) and (10.18), the ZVS condition for Q5 and Q7 is expressed in (10.26). ΔIs is very low, and u is greater than p (D1 − 0.5) in this case. Therefore, the ZVS of Q5 and Q7 is easy to achieve. Ip1 ¼

Vo Ts  u   nDIs nLr 2p

ð10:26Þ

The ZVS condition for Q1 in Mode 4a_m is expressed as IL1

max  Ip0 ¼

  D1 ð1  D1 ÞTs Vo IL þ  2nLf    Vo Ts D1 u Vo ð1  D1 ÞTs    [ DIp 2p nLr 2 2nLr

ð10:27Þ

According to (10.19), the phase angle u is expressed as sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi p 2Po n2 Lr u ¼  p D1  D21  2 Vo2 Ts

ð10:28Þ

Equation (10.29) is derived by substituting (10.28) into (10.27). Lf 

2nDIp 

Vo Ts Because 2n 2L r



1 2

Vo Ts 2n2 Lr

þ

1 p



1 2

D1 ð1  D1 ÞTs Vo  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2Po n2 Lr r IL þ þ 2nL  D ð 1  D Þ  1 1 Vo Ts V 2 Ts 1 p

ð10:29Þ

o

 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2Po n2 Lr r IL þ 2nL  D ð 1  D Þ  is greater than zero, the 2 1 1 Vo Ts V Ts o

ZVS condition for Q1 in this case is expressed in (10.30). Lf 

D1 ð1  D1 ÞTs Vo 2nDIp

ð10:30Þ

10 An Improved Modulation Scheme of Current-fed …

228

The ZVS condition for Q2 is expressed as Ip2  IL1

  Vo Ts  u  D1 ð1  D1 ÞTs Vc   I  DIp min L nLr 2p 2Lf   2pnLr 2pnLr D1 ð1  D1 ÞTs Vc u DIp þ IL  Vo Ts Vo Ts 2Lf ¼

ð10:31Þ

Equation (10.32) was derived by Substituting (10.28) into (10.31), Lf 

Because

2nDIp þ Vo Ts nLr

h

Vo T s nLr

D1 ð1  D1 ÞVo Ts qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 D1 ð1  D1 Þ  2PVo2nTsLr þ o

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 2 D1 ð1  D1 Þ  2PVo2nTsLr þ o

nPo Vo ð1D1 Þ

nPo Vo ð1D1 Þ

o Ts  V2nL r

i

ð10:32Þ

o Ts  V2nL is no more than zero, the r

ZVS condition for Q2 is expressed as Lf 

D1 ð1  D1 ÞTs Vo 2nDIp

ð10:33Þ

(3) Mode 1a Because Mode 2a_m and Mode 4a_m do not meet very light load requirements in forward power flow, Mode 1a will be used in this occasion. The ZVS condition for Mode 1a will be analyzed in this subsection. According to (10.1) and (10.2), the ZVS condition for Q5 and Q7 is expressed in (10.34). Vo D2 Ts Vo ð1  D1 ÞTs   nDIs 4nLr 2nLr 4Lr n2 DIs D2  2ð1  D1 Þ þ ¼ D2m þ Dm Vo Ts 4Lr n2 DIs ¼ 2ð1  D1 Þ; Dm ¼ Vo Ts

Ip0 ¼ Ip1 ¼

D2m

ð10:34Þ

Compared with (10.20), the ZVS conditions for Q5–Q7 in Mode 1a are the same as for Mode 2a_m. The ZVS condition for Q1 in Mode 1a is expressed as IL1

max

 Ip2

  D1 ð1  D1 ÞTs Vo Vo Ts  u  ¼ IL þ [ DIp  2nLf nLr 2p

ð10:35Þ

10.1

Operation Modes of the Current-fed Bidirectional DC–DC Converter

229

According to (10.3), the phase angle u is expressed as u¼

pPo n2 Lr Vo Ts ð1  D1 Þ

ð10:36Þ

Substituting (10.36) into (10.35), (10.37) is derived. Lf 

D1 ð1  D1 ÞTs Vo 2nDIp

ð10:37Þ

The ZVS for Q2 is expressed as Ip3  IL2

min

¼

  Vo Ts  u  D1 ð1  D1 ÞTs Vo  IL   DIp nLr 2p 2nLf

ð10:38Þ

Substituting (10.36) into (10.38), (10.39) is derived. Lf 

D1 ð1  D1 ÞTs Vo 2nDIp

ð10:39Þ

The ZVS condition for Mode 2a_m and Mode 1a is actually the same. The ZVS conditions for Mode 2a_m, Mode 4a_m, and Mode 1a are synthesized in Eq. (10.40). 

1 ÞTs Vo Lf  D1 ð1D 2nDIp D2  D2m þ Dm

ð10:40Þ

According to (10.40), the minimum current ripple is calculated based on the ZVS for Q1–Q4. Furthermore, low current ripple causes the reduction of the core loss in Lf1 and Lf2. The maximum inductance of Lf1 and Lf2 for the modified D ð1D ÞT V operation modes is 1 max 2nDI1p max s o .

10.2

Modulation and Control Scheme for the Modified Operation Mode

10.2.1 Modified PWM Plus Phase-Shift (MPPS) Modulation Scheme and Control Diagram The presented MPPS modulation scheme and control based on the modified operation modes are shown in Figs. 10.10 and 10.11, respectively. Figure 10.10 shows the control diagram of the current-fed bidirectional DC–DC converter. As seen in Fig. 10.10, control variable d is the output of the inner-current loop

10 An Improved Modulation Scheme of Current-fed …

230

Vo_ref

Gv(s)

IL_ref

Vo

Gi(s)

d

Fig.10.11 diagram

φ D2

Q5 Q6 Q7 Q8

PWM

ibat

Vc_ref =Vo_ref /n

Gc(s) D1

PWM

Vc

Q1 Q2 Q3 Q4

Fig. 10.10 Control diagram of the current-fed bidirectional DC–DC converter

According to equation (10.40), determine D2m and Dm for the ZVS of Q5-8. D2_min=D2m+Dm Determine the operation mode by control variable d, where -1 d 1 . Very light load condition

Yes

-Dm d Dm

No

d>Dm) Yes Forward power flow Yes No D +dDm

2m

Mode 1a or Mode 1b D2=D2_min φ=d·π/2

Mode 4a_m Mode 2a_m D2 1 D2 D2m+d φ=π[(D2m+d)/2-(1φ=π[D2/2-(1-D1)] D1)]

No (d