Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications (Selected Topics in Electronics and Systems) 981124281X, 9789811242816

Table of contents :
Contents
Preface
Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers
1. Introduction
2. Quantum Dot Superlattice, Minibands and Electron Tunneling Theory
3. QDG-QDC NVM Device Theory
4. Fabrication
5. Results
6. Conclusion
References
Comparison of Buffer Layer Grading Approaches in InGaAs/GaAs (001)
1. Introduction
2. Dislocation Dynamics Model (DTKA Model)
3. Results and Discussion
4. Conclusion
References
A Zagging and Weaving Model for Dislocation Interactions in Heterostructures Containing Strain Reversals
1. Introduction
2. Model for Lattice Relaxation
3. Results and Discussion
4. Conclusion
References
A Modeling Study of Dislocation Sidewall Gettering in II-VI and III-V Semiconductor Heterostructures
1. Introduction
2. Dislocation Dynamics Model
3. Results and Discussion
4. Conclusion
References
Recent Advances in the Modeling of Strain Relaxation and Dislocation Dynamics in InGaAs/GaAs (001) Heterostructures
1. Introduction
2. Dislocation Dynamics Model
3. Results and Discussion
4. Conclusion
References
Design of a Smart Maximum Power Point Tracker (MPPT) for RF Energy Harvester
1. Introduction
2. Configuration of the Proposed RF Energy Harvester System
3. Machine Learning Based MPPT Controller
3.1. Software Simulation
3.1.1. Data Collection and Generation
3.1.2. Feedforward Neural Network (FNN) Model
3.2. Hardware Implementation of the ML Model
4. Results and Discussion
5. Conclusion
References
Quantum-Dot Transistor Based Multi-Bit Multiplier Unit for In-Memory Computing
I. Introduction
II. Proposed Design
A. Quantum-dot Transistor Memory
B. Quantum-dot Transistor Based Multi-bit Multiplier Unit
C. Operating Principle
D. Linearity Analysis
III. Evaluation
A. Performance
B. Statistical Analysis of Process Variations
C. Power Consumption
IV. Conclusion
References
Single Chemical Sensor for Multi-Analyte Mixture Detection and Measurement: A Review
1. Introduction
2. Voltammetry Multi-Analyte Sensor
3. Optical Multi-Analyte Sensor
4. Impedance-Metric Multi-Analyte Sensor
5. Field-Effect Transistor (FET) Multi-Analyte Sensor
6. Multi-Modular Sensor
7. Conclusion
Acknowledgments
References
A Novel Addressing Circuit For SWS-FET Based Multivalued Dynamic Random-Access Memory Array
1. Introduction
2. Multivalued DRAM Architecture
2.1. Unit memory cell
2.2. Row/Column decoder
2.3. Sense amplifier
2.4. Timing and logic circuit
3. SWS-FET ABM Model
4. Conclusion
Acknowledgments
References
A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory
1. Introduction
2. System Overview
2.1. SWS-CMOS inverter-based SRAM unit cell
2.2. SWS-CMOS inverter-based SRAM cell using single two-channel access-transistor
3. Addressing and Peripheral Circuitry
3.1. SWS-FET based Row/Column decoder
3.2. C-SWSFET sense amplifier
4. ABM Model of SWSFET
5. Conclusion
Acknowledgment
References
3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)
1. Introduction
2. 2-D Confined QD-FETs
3. 3-D Confined QD-FETs
4. 2-bit Logic using QD SWS-FETs
5. Integration of QD-SWS Logic with QD-NVRAMs
6. Conclusion
Acknowledgments
References
Systems for Implementing Data Communication with Security Tokens
1. Introduction
2. Man-In-The-Middle (MITM) Attack and the Mitigation
3. Blockchain Networks
4. Out of Band (OOB) Token Approach for Securing Communication Links
5. Control and Management Plane Operations of Security Token Exchange
6. Data Plane Operation for Secure Data Exchange
7. Summary
References
Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs
1. Introduction
2. 1-Bit Full-Adder
3. SRAM Circuit and Simulation
4. Conclusion
References
3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs
1. Introduction
2. SWS-FET Structures
3. Complementary SWS-FET
4. Quantum Simulation
5. Simulation using Analog Behavioral Model
6. SWS-FET 3-Bit Flash Analog-to-Digital Converter (ADC) Circuit
7. Conclusion
Acknowledgments
References
Amaranthine: Humanoid Robot Kinematics
Introduction
Amaranthine Description
A. Amaranthine Hardware Mechanism
B. Amaranthine Configurations
C. Amaranthine Software
Mathematical Model of Amaranthine Robot: Denavit-Hartenberg (DH) Parameters
Amaranthine Forward Kinematics
Workspace and Path Trajectory Simulations of Amaranthine’s Arms
Conclusion
References
Additively Manufactured RF Devices for 5G, IoT, RFID, WSN, and Smart City Applications
1. Introduction
2. Additively Manufactured Passive RF Devices
2.1. Origami-inspired tunable and deployable structures
2.2. Hybrid printed origami-inspired frequency selective surfaces
2.2.1. “Kirigami” inspired mm-wave dielectric reflectarray antenna
2.3. Inkjet printed 2.5D Lange coupler
3. Additively Manufactured Active RF Modules and Systems
3.1. Full-FM-Band, quasi-isotropic, kilometer-range energy harvester
3.1.1. Matching network using inkjet printing
3.1.2. Rectifying circuit fabricated using inkjet printing
3.2. Inkjet printed RF front ends for low-cost backscatter modules
3.2.1. Low form factor UHF backscatter front end
3.2.2. mm-Wave inkjet-printed backscatter modules for IoT applications
4. Conclusion
Acknowledgment
References
QDC-FET and QD-SWS Physics-Based Equivalent Circuit for ABM Simulations
1. Introduction
2. Background Physics-based Equivalent Circuits
3. Physics based SWSFET Equivalent Model
4. Cadence Simulation
5. SIMULINK Simulation
6. Conclusions
Acknowledgments
References
Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic
1. Introduction
2. Quantum Simulation
2.1. Simulation Results
2.2. Equivalent Circuit Approach
3. Low Temperature Logic and Computing
4. Conclusion
Acknowledgments
References
Author Index

Citation preview

NANOTECHNOLOGY FOR ELECTRONICS, BIOSENSORS, ADDITIVE MANUFACTURING AND EMERGING SYSTEMS APPLICATIONS

12462_9789811242816_TP.indd 1

15/6/21 10:57 AM

SELECTED  TOPICS  IN  ELECTRONICS  AND  SYSTEMS Editor-in-Chief: M. S. Shur

ISSN: 1793-1274

Published* Vol. 65: Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications eds. F. Jain, C. Broadbridge, M. Gherasimova and H. Tang Vol. 64: Nanotechnology for Electronics, Photonics, Biosensors, and Emerging Technologies eds. F. Jain, C. Broadbridge, M. Gherasimova and H. Tang Vol. 63: Wide Bandgap Semiconductor Electronics and Devices eds. Uttam Singisetti, Towhidur Razzak and Yuewei Zhang Vol. 62: High Performance Logic and Circuits for High-Speed Electronic Systems eds. F. Jain, C. Broadbridge, M. Gherasimova and H. Tang Vol. 61: High Performance Materials and Devices for High-Speed Electronic Systems eds. F. Jain, C. Broadbridge, H. Tang and M. Gherasimova Vol. 60:

Microelectronics and Optoelectronics The 25th Annual Symposium of Connecticut Microelectronics and Optoelectronics Consortium (CMOC 2016) eds. F. Jain, C. Broadbridge and H. Tang

Vol. 59: Scaling and Integration of High Speed Electronics and Optomechanical Systems eds. Magnus Willander and Håkan Pettersson Vol. 58:

Fundamental and Applied Problems of Terahertz Devices and Technologies Selected Papers from the Russia-Japan-USA-Europe Symposium (RJUSE-TeraTech 2016) by Maxim Ryzhii, Akira Satou and Taiichi Otsuji

Vol. 57: Frontiers in Electronics Selected Papers from the Workshop on Frontiers in Electronics 2015 (WOFE-15) eds. Sorin Cristoloveanu and Michael S. Shur Vol. 56: Fundamental & Applied Problems of Terahertz Devices and Technologies Selected Papers from the Russia–Japan–USA Symposium (RJUS TeraTech-2014) ed. Michael S. Shur Vol. 55: Frontiers in Electronics Selected Papers from the Workshop on Frontiers in Electronics 2013 (WOFE-2013) eds. Sorin Cristoloveanu and Michael S. Shur Vol. 54: Frontiers in Electronics Advanced Modeling of Nanoscale Electron Devices eds. Benjamin Iñiguez and Tor A. Fjeldly Vol. 53: Frontiers in Electronics Selected Papers from the Workshop on Frontiers in Electronics 2011 (WOFE-2011) eds. Sorin Cristoloveanu and Michael S. Shur *The complete list of the published volumes in the series can be found at https://www.worldscientific.com/series/stes

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Selected Topics in Electronics and Systems – Vol. 65

NANOTECHNOLOGY FOR ELECTRONICS, BIOSENSORS, ADDITIVE MANUFACTURING AND EMERGING SYSTEMS APPLICATIONS Editors

F. Jain University of Connecticut, USA

C. Broadbridge Southern Connecticut State University, USA

M. Gherasimova University of Bridgeport, USA

H. Tang Yale University, USA

World Scientific NEW JERSEY

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Published by World Scientific Publishing Co. Pte. Ltd. 5 Toh Tuck Link, Singapore 596224 USA office: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601 UK office: 57 Shelton Street, Covent Garden, London WC2H 9HE

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Selected Topics in Electronics and Systems — Vol. 65 NANOTECHNOLOGY FOR ELECTRONICS, BIOSENSORS, ADDITIVE MANUFACTURING AND EMERGING SYSTEMS APPLICATIONS Copyright © 2022 by World Scientific Publishing Co. Pte. Ltd. All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means, electronic or mechanical, including photocopying, recording or any information storage and retrieval system now known or to be invented, without written permission from the publisher.

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_fmatter

Preface Publish as part of the well-established book series on “Selected Topics in Electronics and System”, edited by Michael Shur, this volume (Volume 65) on Nanotechnology for Electronics, Biosensors, Additive Manufacturing and Emerging Systems Applications, is comprised of 18 peer reviewed articles focus on high-performance materials and emerging devices for implementation of high-speed electronic systems. The papers presented span from novel materials and devices, biosensors and bio-nanosystems, artificial intelligence, robotics and emerging technologies, to applications in each of these fields. Systems for implementing data with security tokens; single chemical sensor for multi-analyte mixture detection; RF energy harvesters; additively manufactured RF devices for 5G, IoT, RFID and smart city applications are also included in this volume on high performance materials for implementing high-speed electronic systems. In the area of material synthesis, modeling of dislocations behavior in various II-VI and III-V heterostructures and their gettering at sidewall bringing novel approaches. Coming hot on the heels, are recent developments on high performance devices include equivalent circuits models at room temperature and 4.2 K; quantum dot nonvolatile memories, 3D-confined quantum dot channel (QDC) and spatial wavefunction switched (SWS) FETs for high-speed multi-bit logic and novel system applications are also featured. In summary, the papers presented in this volume cover various aspects of high-speed electronic systems. We would like to take this opportunity to express our thanks to the authors, participants, and reviewers for their contributions and knowledge sharing on a variety of research areas. Editors: F. Jain (University of Connecticut) C. Broadbridge (Southern Connecticut State University) M. Gherasimova (University of Bridgeport) H. Tang (Yale University)

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_fmatter

Contents Preface

v

Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers N. R. Butterfield, R. Mays, B. Khan, R. Gudlavalleti and F. C. Jain

1

Comparison of Buffer Layer Grading Approaches in InGaAs/GaAs (001)

13

J. Raphael, T. Kujofsa and J. E. Ayers A Zagging and Weaving Model for Dislocation Interactions in Heterostructures Containing Strain Reversals T. Kujofsa and J. E. Ayers

19

A Modeling Study of Dislocation Sidewall Gettering in II-VI and III-V Semiconductor Heterostructures T. Kujofsa and J. E. Ayers

25

Recent Advances in the Modeling of Strain Relaxation and Dislocation Dynamics in InGaAs/GaAs (001) Heterostructures J. E. Ayers, T. Kujofsa, J. Raphael and M. T. Islam

31

Design of a Smart Maximum Power Point Tracker (MPPT) for RF Energy Harvester D. Parvin, O. Hassan, T. Oh and S. K. Islam

41

Quantum-Dot Transistor Based Multi-Bit Multiplier Unit for In-Memory Computing Y. Zhao, F. Qian, F. Jain and L. Wang

53

 

vii

viii

Contents

Single Chemical Sensor for Multi-Analyte Mixture Detection and Measurement: A Review B. Zhang and P.-X. Gao

67

A Novel Addressing Circuit For SWS-FET Based Multivalued Dynamic Random-Access Memory Array R. H. Gudlavalleti, B. Saman, R. Mays, H. Salama, E. Heller, J. Chandy and F. Jain

83

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory R. H. Gudlavalleti, B. Saman, R. Mays, E. Heller, J. Chandy and F. Jain

93

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL) F. Jain, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy and E. Heller

103

Systems for Implementing Data Communication with Security Tokens M. Chang, S. Das, D. Montrone and T. Chakraborty

119

Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs H. Salama, B. Saman, R. Gudlavalleti, R. Mays, E. Heller, J. Chandy and F. Jain

129

3-Bit Analog-to-Digital Converter Using Multi-State Spatial Wave-Function Switched FETs B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy, E. Heller and F. Jain

139

Amaranthine: Humanoid Robot Kinematics S. Asthana, S. R. Karna and I. A. Shelby

151

Additively Manufactured RF Devices for 5G, IoT, RFID, WSN, and Smart City Applications Y. Cui, E. M. Jung, A. Adeyeye, C. Lynch, X. He and M. Tentzeris

163

Contents

ix

QDC-FET and QD-SWS Physics-Based Equivalent Circuit for ABM Simulations R. Mays, R. H. Gudlavalleti, B. Khan, B. Saman, J. Chandy, E. Heller and F. Jain

175

Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic F. Jain, R. H. Gudlavalleti, R. Mays, B. Saman, J. Chandy and E. Heller

187

Author Index

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0001

Quantum Dot Gate (QDG) Quantum Dot Channel (QDC) Multistate Logic Non-Volatile Memory (NVM) with High-K Dielectric HfO2 Barriers N. R. Butterfield*, R. Mays†, B. Khan‡, R. Gudlavalleti§ and F. C. Jain¶ Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269, USA *[email protected]; [email protected] †[email protected] ‡[email protected] §[email protected] ¶[email protected]

This paper presents the theory, fabrication and experimental testing results for a multiple state NonVolatile Memory (NVM), comprised of hafnium oxide high-k dielectric tunnel and gate barriers as well as a Silicon Quantum Dot Superlattice (QDSL) implemented for the floating gate and inversion channel (QDG) and (QDC) respectively. With the conclusion of Moore’s Law for conventional transistor fabrication, regarding the minimum gate size, current efforts in memory cell research and development are focused on bridging the gap between the conventions of the past sixty years and the future of computing. One method of continuing the increasing chip density is to create multistate devices capable of storing and processing additional logic states beyond 1 and 0. Replacing the silicon nitride floating gate of a conventional Flash NVM with QDSL gives rise to minibands that result in greater control over charge levels stored in the QDG and additional intermediate states. Utilizing Hot Carrier Injection (HCI) programming, for the realized device, various magnitudes of gate voltage pulses demonstrated the ability to accurately control the charge levels stored in the QDG. This corresponds to multiple threshold voltage shifts allowing detection of multiple states during read operations. Keywords: quantum dot gate; QDG; quantum dot channel; QDC; NVM; HfO2 tunnel oxide; quantum dot superlattice; QDSL; minibands; intermediate logic states; multistate logic; QDG-QDC-NVM; QDG-QDC FET; flash; direct tunneling

1. Introduction Information is a crucial component of nature and technology and will always be essential, requiring transmission, storage and processing. For the past sixty years, the Field Effect Transistor (FET) in various forms, governed by Moore’s Law, has comprised the memory devices that perform computations. Over the past couple of decades, FET based Solid State Drives (SSD) and Flash Non-Volatile Memory (NVM) have gained market share in bit storage; however, Moore’s Law has come to an end with respect to the conventional FET ¶Corresponding

author.

1

2

N. R. Butterfield et al.

minimum gate size due to short channel effects. This has resulted in novel approaches to continue the progression, of increasing bit density and processing speed while reducing power consumption and cost. Some approaches include the fabrication of cell arrays in three dimension and modification of the conventional FET such as FinFET or the incorporation of nanostructures. An alternative approach is to fabricate devices capable of computation and storage beyond binary, memory cells that distinguish discrete charge levels between logic 1 and 0, or intermediate states. Replacement of the silicon nitride [12] floating gate for conventional flash NVM with a Quantum Dot Gate (QDG) results in the storage of intermediate states and has been reported [1,3,11]. The Quantum Dot Channel (QDC), comprising the inversion layer between source and drain, has demonstrated intermediate state operation of an FET, with the introduction of multiple drain current (𝐼 ) saturation levels during gate voltage (𝑉 ) sweeps [1,2]. 2. Quantum Dot Superlattice, Minibands and Electron Tunneling Theory The Quantum Dot (QD) structure will confine a particle to a point, restricting motion in all three dimensions if its size approaches the de Broglie wavelength of that particle (1.23nm for electron). A physical QD structure is spherical, comprised of an intrinsic semiconductor core with a cladding layer of oxide, the type fabricated for this device were Silicon (Si) core, 4nm diameter, with Silicon Oxide (SiOX) cladding 1nm thick. Electrons tunnel through the cladding layer becoming trapped in the core. When QDs are assembled such that many adjacent dots form a plane, with their cladding touching one another, a QD Superlattice QD(SL) is formed with unique properties. Confined electrons are best analyzed as solutions to Schrödinger Wave Equation, and a QDSL, populated with electrons, experience an interaction of waves due to the thin cladding. This interaction of waves in a QDSL result in the emergence of minibands that are discrete energy states within the respective charge carrier conduction bands. Quantized minibands provide several paths of conduction in a QDC, and allow sharing of information of electrons stored at multi valued logic states in a QDG. Simulations using the Kronig– Penney model have demonstrated miniband energy levels and their widths [2,4]. Figure 1 shows a Si-SiOX QDSL, with wave interaction and miniband energy levels extending through the quantum wells and their respective widths as defined in previous simulations [2,4]. Additionally, it has been calculated and measured that the band gap (𝐸 ) of Si increases by 10% in QDSL to 1.24eV [4]. The wave nature of an electron is a solution to Schrödinger Wave Equation; the resulting waves are a probabilistic distribution which define the probabilities of an electron’s location along that wave confined in a quantum well. Schrödinger Wave Equation is not trivial, the single dimension expression (1) follows [5]. ħ 𝑑 𝜓 𝑥 2𝑚∗ 𝑑𝑥

𝐸

𝜙 𝑥 𝜓 𝑥

0,

(1)

QDG QDC Multistate Logic NVM

3

Fig. 1. Si-SiOX Quantum Dot Superlattice and the emergence of minibands (not drawn to scale).

where ħ is Plank’s constant, E is energy, 𝑚∗ is the electron’s effective mass in the x direction, “x is the position perpendicular to the Si–SiO2 interface, 𝜓 is the timeindependent part of the wave function and 𝜙 is the potential” [5]. For an electron to traverse a thick oxide barrier it must possess an energy level greater than the barriers EC, such as kinetic energy gained during Hot Carrier Injection (HCI) tunneling. If the oxide barrier is thin enough, such that the solutions to Schrödinger Wave Equation extends through the thickness of the oxide (𝑇 ), the electron will tunnel. When this occurs, Schrödinger Wave Equation, is solved in three locations, in the well, in the wall (𝑇 thick) and the other side of wall; the three are linearly combined, producing a probabilistic solution to the wave equation that looks similar to damped harmonic motion. In the device fabricated for this research, it was desired to have a tunnel oxide that exhibited direct tunneling. Direct tunneling occurs in thin barriers 60Å 𝑇 20Å. The probability of electron tunneling under direct tunneling can be defined by the following approximation (2) [5]. 𝑃

𝑒𝑥𝑝

𝑘 𝑥 𝑑𝑥 ,

(2)

where 𝑥 and 𝑥 are the classical turning points and 𝑘 𝑥 is the wave number in the 𝑥 direction. Figure 2 depicts the alignment of the first solution to Schrödinger Wave Equation, 𝜙 𝑥 potential wave and the energy diagram explanation for direct tunneling through a barrier 𝑇 thick with an energy 𝐸 high. When FETs decrease in gate size, correspondingly the 𝑇 must also reduce in order to maintain control over the inversion channel. However, SiOX has a relatively low permittivity (ℰ 3.9), which permits undesired tunnel oxide leakage. Replacement of

4

N. R. Butterfield et al.

Fig. 2. Direct electron tunneling diagram through 60Å

𝑇

20Å thick oxide.

SiOx with a high-k dielectric material, such as hafnium oxide (HfO2), allows for a thinner oxide layers without tunnel oxide leakage while maintaining oxide capacitance (𝐶 ) [6,10]. This is due to the higher permittivity of HfO2 (ℰ 25) that results in reduced tunnel oxide leakage compared to an equivalently oxide thickness (EOT) of SiOx. The expression for EOT (3) follows. 𝐸𝑂𝑇

𝑇

𝑇

∗ℰ ℰ

,

(3)

(oxide thickness) and ℰ (permittivity), relate to the where, both variables 𝑇 high-k material used. This research implemented a tunnel oxide between 10Å < 𝑇 < 20Å of HfO2, and 50Å of HfO2 for the control gate insulation, the EOT for SiOx is 64128Å and 320Å respectively. This permitted direct tunneling to occur, while maintaining low tunnel leakage and adequate 𝐶 . The band gaps for HfO2 is 𝐸 5.7𝑒𝑉 and SiOx is 𝐸 9𝑒𝑉. 3. QDG-QDC NVM Device Theory Replacing floating gate with a QDSL floating gate, comprised of 2 layers of dots, will increase the number states due to the discrete minibands [1,4,9]. To program the QDGQDC NVM, the magnitude of write pulse voltage varies, the minimum voltage pulse required to store charge will populate the first miniband in QD layer 1. Increasing the voltage for subsequent write pulses will populate additional minibands at higher energy level, thereby allowing for the selection of the QD layer and the specific miniband to store charge. When the QDG-QDC NVM cell receives a read pulse, the intermediate states manifest as a range of stored charge possibilities (𝑄 ). This results in multiple threshold voltage shifts (𝛥𝑉 ), and as such, discrete 𝐼 can be detected with external sense circuitry during the linear operation of the devices defined by expression (4) [1,3,8]. 𝐼

𝑊µ 𝐶 𝐿

𝑉

𝑉 𝑉

𝑉 2

,

(4)

QDG QDC Multistate Logic NVM

5

where W and L are the width and length of the inversion channel and µ is the electron mobility in Si = 1400

∗

. Expression (5) [7] defines the relationship between various gate

write voltages, stored charge, capacitance and voltages in the QDG-QDC NVM. 𝑉

𝑉

𝐶 𝐶

𝐶

,

(5)

where 𝐶 is the capacitance that builds between the control and floating gate and 𝐶 is capacitance between the floating gate and body of the substrate along the inversion channel and 𝑉 is the floating gate voltage with respect to ground. Since the floating gate overlaps source and drain, 𝐶 is broken down into several parasitic capacitances in parallel, the primary three, are depicted in Fig. 3. The capacitive model [7], applied 𝑉 , stored 𝑄 in the QDG as well as resulting 𝑉 is defined in Fig. 3.

Fig. 3. Capacitive model related to expression (4).

Fig. 4. Programming of 4 intermediate states (00, 01, 10, 11), applying various 𝑉 𝛥𝑉 detected for read in ideal QDG-QDC NVM.

write pulses and resulting

The electric field due to 𝑉 is reduce by the stored 𝑄 and its opposing field; this effects the ability to open the inversion channel and thus gives rise to multiple 𝛥𝑉 defined by expression (5) [3,7] and ideally plotted in Fig. 4

6

N. R. Butterfield et al.

𝛥𝑉

𝑄 𝐶

,

(6)

The energy band diagram, shown in Fig. 5, is for the device fabricated, during a write pulse applied to 𝑉 . The first solution to the wave equation direct tunnels into the first miniband, state 10, the other state can traverse as “lucky” electrons over the tunnel oxide during HCI. The layer structure is as follows: P-Type silicon substrate, n+ source/drain, with 2 layers of Si core, SiOX clad QD comprising the QDC, 𝑇 = 10-20Å for the HfO2 tunnel oxide, 2 layers of Si core, SiOX clad QD for the floating QDG, insulated by 𝑇 = 50Å for the HfO2 control gate oxide and ohmic contacts 1500Å thick of Aluminum for gate, source and drain. The resulting minibands introduce intermediate states beyond the conventional Flash NVM labeled as states 00, 01 and 10, supporting three solutions to the Wave Equation for electrons to tunnel and program intermediate states. The erased state 11, has 𝑄 0 in the QDG.

Fig. 5. Energy band diagram during write operation of QDG-QDC NVM (not drawn to scale).

The significance of the QDC is to more finely control 𝐼 during write operations by conducting through the minibands of the inversion channel. The following sequence of events describe the QDC’s impact on 𝐼 𝑉 characteristics. With a fixed 𝑉 bias for

QDG QDC Multistate Logic NVM

7

electrons to travel through the inversion channel, and 𝑉 swept from off to saturation, the following occurs: Current begins flowing in first miniband until density of states are full, 𝐼 saturates for a while as 𝑉 increases. This occurs due to the fact that the electric field does not raise the electron’s energy level high enough to populate the second miniband and miniband one is already fully populated. Once 𝑉 increases the electron energy required to populate the second miniband, 𝐼 saturation occurs again for the same reason. As the 𝑉 sweep concludes, the third miniband is populated and conducts current at saturation. The resulting impact on 𝐼 𝑉 characteristics is intermediate saturation levels as shown in Fig. 6 [2], that are experimental results of a similar device fabricated and reported by F. C. Jain et al., 2012 [2].

Fig. 6. Experimental 𝐼 𝑉 plots for QDG-QDC NVM, showing intermediate 𝐼 𝑉 , F. C. Jain et al., 2012 [2].

saturation levels for increased

4. Fabrication The layers are assigned arbitrary colors, in parentheses, which correspond to the fabricated QDG-QDC NVM device structure depicted in Fig. 7. Cleaning of the device and masks with TCE, Acetone and Methanol along with photolithography steps for various masks are processes that are repeated throughout the subsequent steps but are not included in entirety to avoid redundancy. 1) Starting with a clean P-type silicon wafer, 500µm thick, 1200Å of SiOX wet oxide (dark blue) is grown. 2) Spin at 5000rpm positive photoresist S1813, align mask to open source and drain regions and expose to ultra violet (UV). The UV chemically hardens the resist. 3) Developed photoresist with 351 developer to expose the wet oxide and use 10:1 Buffered Oxide Etch (BOE) to etch through the oxide at 10Å per second, exposing the substrate in the source and drain regions.

8

N. R. Butterfield et al.

4) The remaining photoresist is removed with acetone. The wafer is loaded into the physical vapor deposition (PVD) furnace along with an infinite source of phosphorus. Predeposition at 1000°C, the phosphorus source atomizes forming a cloud that deposits on the surface of the source drain regions facilitated by nitrogen flow in the chamber. The phosphorus sources are removed and the atoms are driven in to the lattice forming the doped n+ region source/drain (green wells). 5) Nitride is deposited to protect the n+ source and drain from subsequent steps (dark red). 6) Gate region mask is aligned, exposed and developed to open the channel. BOE:HF, 10:1 etches through the nitride and wet oxide layers to the P channel substrate. Acetone removes the resist. 7) A slower growing but higher quality dry SiOX layer (cyan) is grown via Chemical Vapor Deposition (CVD) at 1000°C growing a 250Å layer. Repeat step 6 to reopen gate region. 8) Etch with BOE:HF, 10:1. The high quality dry SiO2 is bonded to the P-Si, so when etched away 125Å of substrate is also removed leaving a trench in the channel between source and drain for the QDC. 9) Si quantum dots are fabricated (orange core, cyan clad) [4,9]: Highly pure Si powder is milled with ball bearings. A solution is made with benzoyl, siloxy radicals, ethanol and the milled Si powder. The solution is sonicated to promote oxygenation for at least a week, the resulting chemical reaction grows the QD cladding. 10) The solution is centrifuged precipitating larger particulates leaving a colloidal QD suspension in the top of the test tubes. 7.8>pH>6.7 or 4.9>pH ensures the QD remain in suspension and do not amalgamate [4,9]. 11) The wafer is rinsed in deionized water, then methanol and then placed in the QD colloidal solution for 5 minutes. The cladding of the QD is negatively charged and will electrostatically self-assemble over the P type channel, forming two layers of the QDC. 12) A thin layer of HfO2 (yellow) 10-20Å is deposited to provide tunnel oxide insulation between the QDC and QDG. 13) More QD are manufactured and self-assembled to form two layers of the QDG by repeating steps 10 and 11. 14) A thicker layer, 50Å of HfO2 is applied as a control gate dielectric to insulate electrons from tunneling from the QDG to the gate. 15) The source drain contact mask and photolithography were performed. BOE:HF etches at different rates through the various layers until a narrow path reaches the source drain regions. 16) The device is metalized via Aluminum (Al) Sputtering for a 1500Å layer. The metal interconnect mask undergoes photolithography process resulting in the source, gate and drain Al contacts (purple). The finished fabricated QDG-QDC NVM device is shown (not to scale) in Fig. 7.

QDG QDC Multistate Logic NVM

9

Fig. 7. Layer schematic of the fabricated QDG-QDC NVM.

5. Results The device fabricated and schematically show in Fig. 7 was tested for various fixed 𝑉 and the 𝑉 swept from 0V to 6V. It was demonstrated that with a fixed drain voltage of 3V, multistate of the device was observed, as shown by the data collected in Fig. 8. These 𝐼 𝑉 Characteristics shows three traces after gate pulses applied and identical biasing with two distinct 𝐼 𝑉 characteristic shifts are indicated by the superimposed blue arrows in Fig. 8. Trace B3 is 𝐼 𝑉 characteristic for no voltage pulse and a fixed drain voltage of 3V. After a 12V for 100µs pulse to the gate, the same gate sweep was conducted producing A3 trace at a fixed 𝑉 =3V. Then 15V for 100µs pulse to the gate, the same gate sweep was conducted producing AA3 trace at a fixed 𝑉 =3V. There are shifts between all three traces due to the minibands in the QDSL, due to the QDC, however, there is no shift in threshold voltage. This makes using a read pulse not possible to implement since there is not enough separation. For example, a 3V read pulse would have a drain current of approximately

Fig. 8. 𝐼 𝑉 characteristics, B3 (no pulse), A3 (after 12V 100µs write pulse), AA3 (after 15V 100µs write pulse).

10

N. R. Butterfield et al. Table I. Defines the Traces Parameters for Fig. 8 𝑽𝑫𝑺

Trace Name

Condition

1V

2V

3V

Before: Pulse Erased Logic 1

𝐼

0

After 12V, 100µs Write pulse 𝑉

𝐼

0

After 15V, 100µs Write pulse 𝑉

𝐼

0

Before: Pulse Erased Logic 1

𝐼

1µ𝐴

After 12V, 100µs Write pulse 𝑉

𝐼

1µ𝐴

After 15V, 100µs Write pulse 𝑉

𝐼

1µ𝐴

Before: Pulse Erased Logic 1

B3

After 12V, 100µs Write pulse 𝑉

A3

After 15V, 100µs Write pulse 𝑉

AA3

410-6A for trace AA3, 5.210-6A for trace A3 and 710-6A for trace B3. This low level of separation in currents makes this device difficult to distinguish states without a clear shift in threshold voltage. Table I defines the labeling of Fig. 8 and parameters for trials. It is hypothesized and likely that an additional 𝑉 pulse of 18V and a fourth trial would have produced a fourth state. The three trials outlined previously were repeated under identical write gate pulses with fixed 𝑉 and 𝑉 swept from 0V to 6V, see Fig. 9 for experimental data plotted. The QDC effect on intermediate 𝐼 saturation is seen for all 𝑉 =5.5V traces and for trace B4.5. However, these are not as significant as previously reported [1,2]. Table II defines the labeling of Fig. 9.

Fig. 9. 𝐼

𝑉

characteristics, measuring 3 states (00, 10, 11) for 𝑉 =5.5V.

QDG QDC Multistate Logic NVM

11

Table II. Defines the Traces Parameters for Fig. 9 𝑽𝑮𝑺

Condition Before: Pulse Erased Logic 1

3.5V

4.5V

5.5V

Trace Name B3.5

After 12V, 100µs Write pulse 𝑉

A3.5

After 15V, 100µs Write pulse 𝑉

AA3.5

Before: Pulse Erased Logic 1

B4.5

After 12V, 100µs Write pulse 𝑉

A4.5

After 15V, 100µs Write pulse 𝑉

AA4.5

Before: Pulse Erased Logic 1

B5.5

After 12V, 100µs Write pulse 𝑉

A5.5

After 15V, 100µs Write pulse 𝑉

AA5.5

6. Conclusion The QDG-QDC NVM device fabricated and tested as outlined in this paper demonstrates a shift in 𝐼 𝑉 characteristics after various gate pulses. This shift is attributed to the QDC, however the threshold voltage shift is not great enough to implement read pulse to distinguish bit states. Multistate memory devices, with one or more intermediate logic states are still in the research and development phase. As such, it requires additional work to further substantiate operation, improve distinction between states by increasing 𝛥𝑉 shifts and more through testing to determine proper write, read and erase 𝑉 pulse parameters to maximize number of bits programmed. Technologies such as the QDG-QDC NVM among others are required to continue progression beyond Moore’s Law to increase bit density and combat short channel effects. References 1. M. Lingalugari, K. Baskar, P. Y. Chan, P. Dufilie, E. Suarez, J. Chandy, E. Heller, F. C. Jain. Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-Zns as Gate Insulator. Journal of Electronic Materials, 42, 11, 2013. 2. F. C. Jain, S. Karmakar, P.-Y. Chan, E. Suarez. Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II–VI Barrier Layers. Journal of Electronic Materials, 41, 2775–2784, 2012. 3. F. C. Jain, E. Suarez, M. Gogna, F. Alamoody, D. Butkiewicus, R. Hohner, T. Liaskas, S. Karmakar, P.-Y. Chan, B. Miller, J. Chandy, E. Heller. Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II–VI Gate Insulators. Journal of Electronic Materials, 38, 1574–1578, 2009. 4. P. Mirdha. Optimizing Fabrication and Modeling of Quantum Dot Superlattice for FETs and Nonvolatile Memories, Doctor Dissertations, 1686, University of Connecticut, 2017. 5. J. Ranuarez, M. J. Deen, C-H. Chen. A Review of Gate Tunneling Current in MOS Devices. Microelectronics Reliability, 46, 12, 1939–1956, 2006.

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6. Y. Wang, Z. Yu, F. Zahid, L. Liu, Y. Zhu, J. Wang, H. Guo. Direct Tunneling Through High-K Amorphous HfO2: Effects of Chemical. Modification Journal of Applied Physics, 116, 023703, 2014. 7. M. R. Zakaria, M. N. Hashim, U. Hashim, R. M. Ayub, T. Adam, A. W. Al-Mufii. An Overview and Simulation Study of Conventional Flash Memory Floating Gate Device Using Concept F-N Tunneling Mechanism. Fifth International Conference on Intelligent System, Modeling and Simulation, IEEE, 2014. doi: 10.1109/ISMS.2014.142. 8. S. Karmakar. Design of Quaternary Logic Circuit Using Quantum Dot Gate-Quantum Dot Channel FET (QDG-QDCFET). International Journal of Electronics, 101, 10, 1427–1442, 2014. 9. P. Mirdha, B. Parthasarathy, J. Kondo, P.-Y. Chan, E. Heller, F. C. Jain. An Investigation of Quantum Dot Super Lattice Use in Nonvolatile Memory and Transistors. Journal of Electronic Materials, 47, 2, 1371–1382, 2018. 10. H. Harris, K. Choi, N. Mehta, A. Chandolu, N. Biswas, G. Kipshidze, S. Nkishin, S. Gangopadhyay, H. Temkin. HfO2 Gate Dielectric with 0.5 nm Equivalent Oxide Thickness. Applied Physics, 81, 1065, 2002. 11. S. Karmakar, J. Chandy, M. Gogna, F.C. Jain. Fabrication and Circuit Modeling of NMOS Inverter Based on Quantum Dot Gate Field-Effect Transistors. Journal of Electronic Materials, 41, 8, 2012. 12. M.-H. Jung, K.-S. Kim, G.-H. Park, W.-J Cho. Dependence of Charge Trapping and Tunneling on the Silicon Nitride Thickness for Tunnel Barrier Engineered Nonvolatile Memory Applications. Applied Physics Letters, 94, 5, 2009.

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0002

Comparison of Buffer Layer Grading Approaches in InGaAs/GaAs (001) Johanna Raphael1,*, Tedi Kujofsa2,† and J. E. Ayers2,‡ 1Electrical

and Computer Engineering Department, University of Hartford, Hartford, CT 06117, USA 2Electrical and Computer Engineering Department, 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA *[email protected] †[email protected] ‡[email protected]

Metamorphic semiconductor devices often utilize compositionally-graded buffer layers for the accommodation of the lattice mismatch with controlled threading dislocation density and residual strain. Linear or step-graded buffers have been used extensively in these applications, but there are indications that sublinear, superlinear, S-graded, or overshoot graded structures could offer advantages in the control of defect densities. In this work we compare linear, step-graded, and nonlinear grading approaches in terms of the resulting strain and dislocations density profiles using a state-of-the-art model for strain relaxation and dislocation dynamics. We find that sublinear grading results in lower surface dislocation densities than either linear or superlinear grading approaches. Keywords: metamorphic buffers; graded layers; linear grading; non-linear grading; threading dislocations; InGaAs/GaAs

1. Introduction Graded layers are used for accommodation of lattice mismatch in semiconductor devices to control the dislocation density. The surface threading dislocation density decreases with total material thickness but is also influenced by the profile of grading, and it is desirable to use the minimum buffer thickness. Therefore it is of interest to investigate sublinear [1,2], superlinear [1,3], S-graded [4–6], reverse-graded [7], and overshoot [8–10] buffer layers for comparison to the linear and step-graded cases [11–13]. It is believed that dislocation interactions, especially pinning interactions [14,15], influence the performance of graded buffers, but until now models for this behavior have been limited so most studies have been empirical. Here we use a dislocation dynamics model [16,17] with pinning interactions included to compare grading approaches in InxGa1-xAs/GaAs (001) graded layers. For example, Saha et al. [18] found that in InGaAs buffers, sublinear grading ‡Corresponding

author.

13

14

J. Raphael, T. Kujofsa & J. E. Ayers

resulted in lower surface dislocation densities than other profile shapes, whereas more complicated behavior was observed in quaternary InGaAsP graded buffer layers. 2. Dislocation Dynamics Model (DTKA Model) Within the Dodson & Tsao / Kujofsa & Ayers (DTKA) dislocation dynamics model, the rate of relaxation 𝛾 𝑧 at a distance 𝑧 from the interface in a general semiconductor heterostructure is [16,17] 𝑑𝛾 𝑧 𝑑𝑡

𝑧 𝑒𝑥𝑝

𝐾𝐵𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆 𝜎

𝑈 𝑘𝑇

𝜌 𝜁

𝜌 𝑑𝜁 ,

(1)

where 𝛼 is the angle between the Burgers vector and line vector, 𝜆 is the angle between the Burgers vector and the line in the interface plane which is perpendicular to the intersection of the glide plane and the interface, 𝜎 𝑧 is the effective stress, 𝑈 is the activation energy for dislocation glide, 𝑘 is the Boltzmann constant, 𝑇 is the temperature, 𝜌 𝑧 is the cross-sectional density of misfit dislocations, 𝜌 represents an initial density of defects, and 𝐵 and 𝐾 are semi-empirical constants. For InxGa1-xAs, 𝐵 0.48 𝑥1.74 𝑥 0.42 10 𝑐𝑚 𝑑𝑦𝑛 𝑠 , 𝐾 0.33 𝑥23 𝑥 0.41 10 𝑐𝑚 𝑑𝑦𝑛 , and 𝑈 1.3 0.1𝑥 𝑒𝑉 [19]. The effective stress is 𝜎

𝑧

2𝑐𝑜𝑠𝜙 𝑐𝑜𝑠𝜆 ℎ 𝑧

𝐺 1

𝜈 𝜖 𝜁 𝜖 1 𝜈

𝜁

𝑑𝜁,

(2)

where 𝜙 is the angle between the surface normal and the slip plane, 𝜈 is the Poisson ratio, 𝜖 𝑧 is the in-plane strain at a distance 𝑧 from the interface, 𝜖 𝑧 is the equilibrium inplane strain, and 𝜁 is a variable of integration. The areal density of misfit dislocations is 1 𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆

𝜌 𝑧 The length of misfit dislocations 𝐿

𝜕𝑓 . 𝜕𝑧

(3)

𝑈 𝑑𝜏, 𝑘𝑇

(4)

𝑧 is given by 𝑧

𝐿

𝜕𝜖 𝜕𝑧

2𝐵𝜎

𝑒𝑥𝑝

where 𝑡 represents the time of the onset of lattice relaxation, corresponding to the critical layer thickness, and 𝜏 is a variable of integration. The threading dislocation density 𝐷 is found by 𝜕𝐷 𝑧 𝜕𝑧

4𝜌 𝑧 𝐿

𝑧 𝑠𝑔𝑛

𝜌 𝜁 𝑑𝜁

𝐿

𝑧 𝐷 𝑧 ,

(5)

Comparison of Buffer Layer Grading Approaches

15

Fig. 1. Pinning in an epitaxial structure with distributed misfit dislocations, each of which is surrounded by a cylindrical volume in which the glide force acting on a gliding dislocation with an orthogonal misfit component will be negated.

where 𝐿 𝑧 is the average length of misfit segments, and 𝐿 𝑧 is the interaction length for annihilation and coalescence reactions. We assume a dislocation will become pinned if it glides within the pinning radius of an orthogonal dislocation as shown in Fig. 1. Then the maximum length of misfit dislocations may be estimated as 𝐿

𝑧

,

𝜌 𝜁 𝑑𝜁

,

(6)

where 𝜁 is a variable of integration, and the pinning radius is 𝑟

√2𝜅𝐺𝑏/2𝜋𝜎

𝑐𝑜𝑠𝜆 ,

(7)

where 𝜅 is a unitless geometric factor. 3. Results and Discussion We compared sublinear, linear, and superlinear buffer layers of InxGa1-xAs grown on GaAs (001) substrates at 510oC with a growth rate of 0.5 m/hr. The compositional profiles of these “gamma-graded” layers were generated using the universal equation 𝑥

𝑥

𝑧 ℎ

,

(8)

where 𝑥 is the top composition, ℎ is the layer thickness, and the parameter  determines the nature of the profile; values less than one result in sublinearity, values greater than one result in superlinearity, and a value of one corresponds to linear grading. Figure 2 shows the compositional profiles for -graded InxGa1-xAs/GaAs (001) layers having a thickness of 0.5 m and a top indium composition of 0.25. Figure 3 shows the resulting misfit dislocation density profiles. Lower values of  concentrate the misfit dislocations near the

16

J. Raphael, T. Kujofsa & J. E. Ayers

interface while higher values of  skew the misfit dislocation density toward the top surface. Figure 4 illustrates the associated threading dislocation densities. The surface threading dislocation density varies considerably with the value of. Although it is generally 0.25 = 0.25 = 0.5 =1 =2 =4

0.2

0.15

0.1

0.05

0

0

100

200 300 400 distance from interface (nm)

500

Fig. 2. Compositional profiles for -graded InxGa1-xAs layers on GaAs (001) substrates.

threading dislocation density (cm -2)

Fig. 3. Misfit dislocation profiles for -graded InxGa1-xAs layers on GaAs (001) substrates.

Fig. 4. Threading dislocation density profiles for -graded InxGa1-xAs layers on GaAs (001) substrates.

Comparison of Buffer Layer Grading Approaches

17

indium composition x

considered better to avoid concentrations of misfit dislocations, due to pinning interactions, concentration of misfit dislocations near the interface is less harmful than concentration at the surface, so that the surface threading dislocation density varies monotonically with gamma. Next we compared linearly-graded and step-graded (five steps) layers of InGaAs/GaAs (001) with a total thickness of 500 nm, a top composition of 0.25, a growth rate of 0.5 m/hr, and a growth temperature of 510oC. Figure 5 shows the compositional profiles and Fig. 6 shows the threading dislocation density profiles. These results show that although each interface of the step-graded structure introduces a large number of threading dislocations associated with misfit dislocations, the dislocation interaction length is greater in the step-graded structure so the surface threading dislocation density is reduced compared to the linearly-graded case.

Fig. 5. Compositional profiles for linear and step-graded InxGa1-xAs layers on GaAs (001) substrates.

Fig. 6. Threading dislocation density profiles for linear and step-graded InxGa1-xAs layers on GaAs (001) substrates.

4. Conclusion We have applied a dislocation dynamics model, extended to include dislocation pinning interactions, to compare the performance of sublinear, linear, and superlinear graded layers

18

J. Raphael, T. Kujofsa & J. E. Ayers

of InxGa1-xAs on GaAs (001) substrates. For the growth conditions explored here, we find that sublinear grading of InGaAs results in lower surface dislocation densities than linear or superlinear grading, consistent with the findings of Saha et al. [18]. This model is applicable to the further study of general graded and multilayered heterostructures, but this will require detailed experimental studies to determine the material parameters for other ternary and quaternary semiconductors. References 1. D. Sidoti, S. Xhurxhi, T. Kujofsa, S. Cheruku, J. Reed, B. Bertoli, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 39, 1140 (2010). 2. B. Bertoli, D. Sidoti, S. Xhurxhi, T. Kujofsa, S. Cheruku, J. Reed, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Appl. Phys., 108, 113525 (2010). 3. T. Kujofsa and J. E. Ayers, J. Vac. Sci. Technol. B, 32, 031205 (2014). 031205. 4. S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, T. Kujofsa, S. Cheruku, J. P. Correa, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 40, 2348 (2011). 5. T. Kujofsa, A. Antony, S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, S. Cheruku, J. P. Correa, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 42, 3408 (2013). 6. T. Kujofsa and J. E. Ayers, Int. J. High Speed Electron. Sys., 23, 1420005 (2014). doi: 10.1142/ S0129156414200055. 7. B. Bertoli, E. N. Suarez, F. C. Jain and J. E. Ayers, Semicond. Sci. Technol., 24, 125006 (2009). 8. J. F. Ocampo, E. Suarez, D. Shah, P. B. Rago, F. C. Jain and J. E. Ayers, J. Electron. Mater., 37, 1035 (2008). 9. T. Kujofsa and J. E. Ayers, J. Electron. Mater., 42, 3034 (2013). 10. T. Kujofsa and J. E. Ayers, Semicond. Sci. Technol., 31, 125005 (2016). doi: 10.1088/02681242/31/12/125005. 11. T. Kujofsa and J. E. Ayers, J. Electron. Mater., 43, 3047 (2014). doi: 10.1007/s11664-0143205-3. 12. T. Kujofsa and J. E. Ayers, Int. J. High Speed Electron. Syst., 24, 1520009 (2015). doi: 10.1142/ S0129156415200098. 13. T. Kujofsa and J. E. Ayers, J. Electron. Mater., 45, 2831 (2016). doi: 10.1007/s11664-0164377-9. 14. T. Kujofsa and J. E. Ayers, Electrochem. Soc. Trans., 92, 43 (2019). 15. T. Kujofsa and J. E. Ayers, J. Electron. Mater., 49, 6990 (2020). 16. T. Kujofsa, W. Yu, S. Cheruku, B. Outlaw, S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 41, 2993 (2013). 17. T. Kujofsa, S. Cheruku, W. Yu, B. Outlaw, S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 42, 2764 (2013). 18. S. Saha, D. T. Cassidy, and D. A. Thompson, J. Cryst. Growth, 386, 183 (2014). 19. K. Lindstrom, J. Wales, T. Kujofsa and J. E. Ayers, “Evaluation of a Plastic-Flow Model for InGaAs/GaAs (001) Heterostructures,” Materials Science and Technology Conference, Portland, OR (Sept. 29 – Oct. 3, 2019).

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0003

A Zagging and Weaving Model for Dislocation Interactions in Heterostructures Containing Strain Reversals Tedi Kujofsa* and J. E. Ayers† Electrical and Computer Engineering Department, 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA *[email protected] †[email protected]

Strained-layer superlattices (SLSs) have been used to modify the threading dislocation behavior in metamorphic semiconductor device structures; in some cases they have even been used to block the propagation of threading dislocations and are referred to in these applications as “dislocation filters.” However, such applications of SLSs have been impeded by the lack of detailed physical models. Here we present a “zagging and weaving” model for dislocation interactions in multilayers and strainedlayer superlattices, and we demonstrate the use of this model to the threading dislocation dynamics in InGaAs/GaAs (001) structures containing SLSs. Keywords: metamorphic structures; threading dislocations; strained-layer superlattices; dislocation filters; InGaAs/GaAs

1. Introduction Strained-layer superlattice (SLS) structures are used to reduce the dislocation density and improve performance in semiconductor devices [1–3], and these are occasionally referred to as “dislocation filters.” However, use of SLSs in this way has been hindered by the need for empirical design, and we therefore sought to extend the standard dislocation dynamics model to include zagging and weaving [4] for application to SLSs and other multilayered structures. 2. Model for Lattice Relaxation Within the framework of the Dodson & Tsao / Kujofsa & Ayers (DTKA) plastic flow model, the time dependence of the relaxation 𝛾 𝑧 at a distance 𝑧 from the substrate interface in an arbitrary heterostructure is given by [5] 𝑑𝛾 𝑧 𝑑𝑡 †

𝐾𝐵𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆 𝜎

𝑧 𝑒𝑥𝑝

Corresponding author.

19

𝑈 𝑘𝑇

𝜌 𝜁

𝜌 𝑑𝜁,

(1)

20

T. Kujofsa & J. E. Ayers

where 𝛼 is the angle between the Burgers vector and line vector, 𝜆 is the angle between the Burgers vector and the line in the interface plane which is perpendicular to the intersection of the glide plane and the interface, 𝜎 𝑧 is the effective stress, 𝑈 is the activation energy for dislocation glide, 𝑘 is the Boltzmann constant, 𝑇 is the temperature, 𝜌 𝑧 is the cross-sectional density of misfit dislocations, 𝜌 represents an initial density of defects, and 𝐵 and 𝐾 are semi-empirical constants. For InxGa1-xAs, 𝐵 0.48 𝑥1.74 𝑥 0.42 10 𝑐𝑚 𝑑𝑦𝑛 𝑠 , 𝐾 0.33 𝑥23 𝑥 0.41 10 𝑐𝑚 𝑑𝑦𝑛 , and 𝑈 1.3 0.1𝑥 𝑒𝑉 [6]. The effective stress is 𝜎

𝑧

2𝑐𝑜𝑠𝜙 𝑐𝑜𝑠𝜆 ℎ 𝑧

𝐺 1

𝜈 𝜖 𝜁 𝜖 1 𝜈

𝜁

𝑑𝜁,

(2)

where 𝜙 is the angle between the surface normal and the slip plane, 𝜈 is the Poisson ratio, 𝜖 𝑧 is the in-plane strain at a distance 𝑧 from the interface, 𝜖 𝑧 is the equilibrium inplane strain, and 𝜁 is a variable of integration. The areal density of misfit dislocations is 1 𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆

𝜌 𝑧 The length of misfit dislocations 𝐿 𝐿

𝜕𝜖 𝜕𝑧

𝜕𝑓 . 𝜕𝑧

(3)

𝑧 is given by 𝑧

2𝐵𝜎

𝑒𝑥𝑝

𝑈 𝑑𝜏 , 𝑘𝑇

(4)

where 𝑡 represents the time of the onset of lattice relaxation, corresponding to the critical layer thickness, and 𝜏 is a variable of integration. The equation governing the variation of the threading dislocation density 𝐷 is 𝜕𝐷 𝑧 𝜕𝑧

4𝜌 𝑧 𝑧 𝑠𝑔𝑛

𝐿

𝜌 𝜁 𝑑𝜁

𝑧 𝐷 𝑧 ,

𝐿

(5)

𝑧 is the average where 𝜌 𝑧 is the cross-sectional density of misfit dislocations, 𝐿 length of misfit dislocation segments, and 𝐿 𝑧 is the interaction length for annihilation and coalescence reactions between threading dislocations. Here we account for the zagging and weaving of dislocations at mismatched interfaces so the interaction length accumulates with the total length of a jogging dislocation such as that shown in Fig. 1. Therefore 𝐿

𝑧

𝑐𝑜𝑠𝛽𝑎𝑏𝑠 𝐿

𝜉 𝑑𝜉 ,

where  is the angle between the slip plane and the interface.

(6)

Zagging and Weaving Model for Dislocation Interactions

SLS L1

L2

L4

L3

21

z

substrate



Fig. 1. A grown-in dislocation in a strained-layer superlattice (SLS). The alternating lattice mismatches of the superlattice cause the dislocation to weave back and forth at the interfaces.

3. Results and Discussion To investigate the effect of inserting a superlattice in an InGaAs/GaAs (001) structure, we considered four heterostructures grown at 510oC with a growth rate of 0.5 m/hr. Using a SLS design comprising five periods of 10-nm In0.18Ga0.82As/10-nm In0.22Ga0.78As, we found the threading dislocation density profiles for four cases having a superlattice at the interface, midway through a uniform layer, and at the top, as well as the case of no SLS. The uniform material was In0.2Ga0.8As with a total thickness of 1000 nm. The results in Fig. 2 show that the structure without an SLS contains 1.5 10 cm-2 dislocations but insertion of SLS at the interface decreases the dislocation density to 0.37 10 cm-2. Inserting the SLS farther from the interface actually increases the surface dislocation density. Next we considered the strength of the superlattice, varying the step in the composition and comparing to the case of no SLS as shown in Fig. 3. The temperature, growth rate, and total thickness of uniform material was the same as before. While these results show a weak dependence on the compositional step used in the SLS, the best case is the one with the smallest compositional step, containing a five period 10-nm In0.18Ga0.82As/10-nm In0.22Ga0.78As superlattice. 1012 SLS at z = 0 SLS at z = 500 nm SLS at z = 1000 nm no SLS

1011

1010

109

108

107

0

200

400

600

800

1000

1200

distance from interface (nm)

Fig. 2. Threading dislocation density profiles for four InGaAs/GaAs (001) heterostructures containing a SLS at the interface, midway in a uniform layer, and at the surface, compared to the case of no SLS.

T. Kujofsa & J. E. Ayers

threading dislocation density (cm -2)

22

Fig. 3. Threading dislocation density profiles for four InGaAs/GaAs (001) heterostructures containing a SLS at the interface with differing compositional step, compared to the case of no SLS.

In a third study we investigated the effect of the number of periods, for a superlattice located at the interface below a 1000-nm In0.2Ga0.8As uniform layer grown at 510oC with a growth rate of 0.5 m/hr. Each period of the superlattice comprised 10-nm In0.18Ga0.82As/ 10-nm In0.22Ga0.78As. Figure 4 shows the threading dislocation density profiles for four cases corresponding to one period, two periods, five periods, and ten periods of the superlattice. It can be seen that the surface threading dislocation density decreases monotonically with the number of periods in the superlattice. The same can be said for the threading dislocation density at a fixed distance of 1000 nm from the interface, so the variation of the surface density with the number of periods is not purely an effect of the change in thickness. 1012

10

one period two periods five periods ten periods

11

1010

109

108

107

0

200

400

600

800

1000

1200

distance from interface (nm)

Fig. 4. Threading dislocation density profiles for four InGaAs/GaAs (001) heterostructures containing a SLS at the interface with the number of periods varied.

Zagging and Weaving Model for Dislocation Interactions

23

4. Conclusion The dislocation dynamics model described here, extended to account for zagging and weaving in multilayered structures, predicts the dislocation filtering property of superlattices and will be applicable to the design of device structures. We have demonstrated use of the model to study the effect of the placement, strength, and number of periods in a superlattice inserted in an InGaAs/GaAs (001) heterostructure. References 1. Ch. Heyn et al., J. Cryst. Growth, 251, 832 (2003). 2. Md T. Islam, X. Chen, T. Kujofsa and J. E. Ayers, Int. J. High Speed Electron. Syst., 27, 1840009 (2018). doi: 10.1142/S0129156418400098. 3. Md T. Islam, X. Chen, T. Kujofsa and J. E. Ayers, Int. J. High Speed Electron. Syst., 27, 1840028 (2018). https://doi.org/10.1142/S0129156418400281. 4. J. Raphael, T. Kujofsa and J. E. Ayers, Electrochem. Soc. Trans., 97, 79 (2020). 5. T. Kujofsa, W. Yu, S. Cheruku, B. Outlaw, S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 41, 2993 (2013). 6. K. Lindstrom, J. Wales, T. Kujofsa and J. E. Ayers, Materials Science and Technology Conference, Portland, OR (Sept. 29 – Oct. 3, 2019).

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0004

A Modeling Study of Dislocation Sidewall Gettering in II-VI and III-V Semiconductor Heterostructures Tedi Kujofsa* and J. E. Ayers† Electrical and Computer Engineering Department, 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA *[email protected] †[email protected]

Since the invention of dislocation sidewall gettering (DSG) in 2000 the technique has been applied extensively in infrared focal-plane arrays and flat-panel displays. However, development of DSG technology has been guided mostly by empirical trials due to the lack of detailed physical models. Here we demonstrate the application of a dislocation dynamics model to evaluate DSG approaches in both ZnSySe1-y /GaAs (001) and InGaxAs1-x/GaAs (001) heterostructures. We find that the effectiveness of DSG is strongly dependent on composition in both material systems. Keywords: dislocation sidewall gettering (DSG); metamorphic structures; threading dislocations; InGaAs/GaAs; ZnSSe/GaAs

1. Introduction The advent of dislocation sidewall gettering (DSG), also known as patterned heteroepitaxial processing (PHeP) [1–6], brought about an important new way to control threading dislocations in metamorphic semiconductor devices. Figure 1 shows the first demonstration of DSG to remove all threading dislocations from mesa-patterned material in 2000 [1]. Despite the extensive commercialization of this technology in infrared detector arrays and LED flat-panel displays, the physical limitations remain incompletely understood so that device and process design must rely heavily on empirical evaluations. To augment the empirical studies, we have developed a detailed dislocation dynamics model for the efficient study of DSG in various material systems, and we demonstrate its application to ZnSySe1-y /GaAs (001) and InGaxAs1-x /GaAs (001) heterostructures. These scanning electron microscope images show etch pits on As-grown and DSG-processed ZnSe on GaAs.

†Corresponding

author.

25

26

T. Kujofsa & J. E. Ayers

Fig. 1. The first demonstration of DSG in 2000 [1]. (a) As-grown 0.6 m-thick ZnSe/GaAs (001) grown at 360oC exhibited ~108 cm-2 threading dislocations (etch pit density); (b) material cut from the same sample but patterned and annealed at 550oC showed complete removal of threading dislocations in 7070 m mesas.

2. Dislocation Dynamics Model Within the framework of the Dodson & Tsao /Kujofsa & Ayers (DTKA) plastic flow model, the time dependence of the relaxation 𝛾 𝑧 at a distance 𝑧 from the substrate interface in an arbitrary heterostructure is given by [7] 𝑑𝛾 𝑧 𝑑𝑡

𝐾𝐵𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆 𝜎

𝑧 𝑒𝑥𝑝

𝑈 𝑘𝑇

𝜌 𝜁

𝜌 𝑑𝜁 ,

(1)

where 𝛼 is the angle between the Burgers vector and line vector, 𝜆 is the angle between the Burgers vector and the line in the interface plane which is perpendicular to the intersection of the glide plane and the interface, 𝜎 𝑧 is the effective stress, 𝑈 is the activation energy for dislocation glide, 𝑘 is the Boltzmann constant, 𝑇 is the temperature, 𝜌 𝑧 is the cross-sectional density of misfit dislocations, 𝜌 represents an initial density 0.48 of defects, and 𝐵 and 𝐾 are semi-empirical constants. For InxGa1-xAs, 𝐵 10 𝑐𝑚 𝑑𝑦𝑛 𝑠 , 𝐾 0.33 𝑥23 𝑥 0.41 10 𝑐𝑚 𝑑𝑦𝑛 , 𝑥1.74 𝑥 0.42 and 𝑈 1.3 0.1𝑥 𝑒𝑉 [8]. For ZnSySe1-y , 𝐵 2.8 10 𝑐𝑚 𝑑𝑦𝑛 𝑠 , 𝐾 2.0 10 𝑐𝑚 𝑑𝑦𝑛 , and 𝑈 1.0𝑒𝑉 [4]. The effective stress is 𝜎

𝑧

2𝑐𝑜𝑠𝜙 𝑐𝑜𝑠𝜆 ℎ 𝑧

𝐺 1

𝜈 𝜖 𝜁 𝜖 1 𝜈

𝜁

𝑑𝜁 ,

(2)

where 𝜙 is the angle between the surface normal and the slip plane, 𝜈 is the Poisson ratio, 𝜖 𝑧 is the in-plane strain at a distance 𝑧 from the interface, 𝜖 𝑧 is the equilibrium inplane strain, and 𝜁 is a variable of integration. The areal density of misfit dislocations is 𝜌 𝑧

1 𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆

𝜕𝜖 𝜕𝑧

𝜕𝑓 . 𝜕𝑧

(3)

Modeling Study of Dislocation Sidewall Gettering

The length of misfit dislocations 𝐿

𝑧 is given by

𝑧

𝐿

27

2𝐵𝜎

𝑈 𝑑𝜏 , 𝑘𝑇

𝑒𝑥𝑝

(4)

where 𝑡 represents the time of the onset of lattice relaxation, corresponding to the critical layer thickness, and 𝜏 is a variable of integration. The equation governing the variation of the threading dislocation density 𝐷 is 4𝜌 𝑧

𝜕𝐷 𝑧 𝜕𝑧

𝑧 𝑠𝑔𝑛

𝐿

𝐿

𝜌 𝜁 𝑑𝜁

𝑧 𝐷 𝑧 ,

𝑧 is the average length of misfit segments, and 𝐿 where 𝐿 length for annihilation and coalescence reactions, given by 𝐿

𝑧

𝑐𝑜𝑠𝛽𝑎𝑏𝑠 𝐿

𝜉 𝑑𝜉 ,

(5)

𝑧 is the interaction

(6)

where  is the angle between the slip plane and the interface. We assume a dislocation will become pinned if it glides within the pinning radius of an orthogonal dislocation as shown in Fig. 2 [9,10]. Then the maximum length of misfit dislocations may be estimated as

𝐿

𝑧

,

𝜌 𝜁 𝑑𝜁

,

(7)

where 𝜁 is a variable of integration, and the pinning radius is 𝑟

𝑐𝑜𝑠𝜆 ,

√2𝜅𝐺𝑏/2𝜋𝜎

(8)

where 𝜅 is a unitless geometric factor. To evaluate the effectiveness of DSG we determine the approximate maximum width of a square mesa from which all threading dislocations may be removed as twice the lateral spacing of threading dislocations added to the interaction length for dislocations: 𝐿

2 √𝐷

𝐿

.

(9)

28

T. Kujofsa & J. E. Ayers gliding threading dislocation Free surface Epitaxial layer

h*

h

ro Substrate Misfit dislocation

Region where the glide force on the threading dislocation is nulled

Fig. 2. Pinning of a gliding dislocation by another dislocation having an orthogonal misfit segment in a mismatched epitaxial layer having a thickness h. The blocking dislocation is surrounded by a semi-cylindrical volume of radius ro in which the glide force acting on the gliding dislocation will be nulled.

3. Results and Discussion First we calculated the maximum mesa width for complete removal of threading dislocations by DSG from ZnSySe1-y /GaAs (001) grown by a two-step process (1 minute at 595oC and the balance of thickness at 350oC) with a growth rate of 2 m/hr and a total thickness of 0.6 m. All layers were assumed to be annealed for 30 minutes after growth. Figure 3 shows the maximum mesa width for complete removal of dislocations by DSG as a function of composition with annealing temperature as a parameter. These results are in qualitative agreement with experiments, showing that DSG is more effective in ZnSe/GaAs (001) than in ZnSSe/GaAs (001) [1,6].

Fig. 3. Maximum mesa width for complete removal of threading dislocations from 0.6 m-ZnSySe1-y/GaAs (001) as a function of composition with annealing temperature as a parameter.

Modeling Study of Dislocation Sidewall Gettering

29

Similar calculations were done for InGaAs/GaAs (001) heterostructures, assumed to be grown at 510oC with a growth rate of 0.5 m/hr and a total thickness of 0.6 m. All heterostructures were assumed to be annealed for 30 minutes after growth at the temperature indicated. Figure 4 shows the results for this study and indicates that DSG can be highly effective for indium compositions of 10-15% using all of the annealing temperatures considered. However, the effectiveness of DSG is strongly dependent on the composition in InGaAs/GaAs (001).

Fig. 4. Maximum mesa width for complete removal of threading dislocations from 0.6 m-InxGa1-xAs/GaAs (001) as a function of composition with annealing temperature as a parameter.

4. Conclusion These results show that DSG is very effective in ZnSe and less effective in ZnSSe, consistent with the experimental results. They also show that the effectiveness of DSG is strongly dependent on composition in InGaAs/GaAs (001). Within the range of parameters investigated here, best performance was achieved in InxGa1-xAs/GaAs with 𝑥 12%. More work is needed to assess the roles of growth conditions as well as anneal temperature and time. References 1. X. G. Zhang, A. Rodriguez, X. Wang, P. Li, F. C. Jain and J. E. Ayers, Appl. Phys. Lett., 77, 2524 (2000). 2. X. G. Zhang, A. Rodriguez, P. Li, F. C. Jain and J. E. Ayers, “A Novel Approach for the Complete Removal of Threading Dislocations from Mismatched Heteroepitaxial Layers,” Materials Research Society Fall Meeting, Boston, MA (2000). 3. X. G. Zhang, A. Rodriguez, X. Wang, P. Li, F. C. Jain and J. E. Ayers, “A Novel Approach for the Complete Removal of Threading Dislocations from ZnSe on GaAs (001),” 2000 U.S. Workshop on the Physics and Chemistry of II-VI Materials, Albuquerque, NM, USA (2000).

30

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4. X. G. Zhang, A. Rodriguez, P. Li, F. C. Jain and J. E. Ayers, “Complete removal of threading dislocations from ZnSe on GaAs (001) by patterned heteroepitaxial processing,” Connecticut Microelectronics and Optoelectronics Symposium, Storrs, CT (April 3, 2001). 5. X. G. Zhang, A. Rodriguez, P. Li, F. C. Jain and J. E. Ayers, J. Electron. Mater., 30, 667 (2001). 6. X. G. Zhang, A. Rodriguez, P. Li, F. C. Jain and J. E. Ayers, J. Appl. Phys., 91, 3912 (2002). 7. T. Kujofsa, W. Yu, S. Cheruku, B. Outlaw, S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 41, 2993 (2013). 8. K. Lindstrom, J. Wales, T. Kujofsa and J. E. Ayers, “Evaluation of a Plastic-Flow Model for InGaAs/GaAs (001) Heterostructures,” Materials Science and Technology Conference, Portland, OR (Sept. 29 – Oct. 3, 2019). 9. T. Kujofsa and J. E. Ayers, Electrochem. Soc. Trans., 92, 43 (2019). 10. T. Kujofsa and J. E. Ayers, J. Electron. Mater., 49, 6990 (2020).

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0005

Recent Advances in the Modeling of Strain Relaxation and Dislocation Dynamics in InGaAs/GaAs (001) Heterostructures J. E. Ayers1,*, Tedi Kujofsa1,†, Johanna Raphael2,‡ and Md Tanvirul Islam1,§ 1Electrical and Computer Engineering Department, 371 Fairfield Way, Unit 4157, Storrs, CT 06269-4157, USA 2Electrical and Computer Engineering Department, University of Hartford, Hartford, CT 06117, USA *[email protected] †[email protected] ‡[email protected] §[email protected]

In this paper we describe state-of-the-art approaches to the modeling of strain relaxation and dislocation dynamics in InGaAs/GaAs (001) heterostructures. Current approaches are all based on the extension of the original Dodson and Tsao plastic flow model to include compositional grading and multilayers, dislocation interactions, and differential thermal expansion. Important recent breakthroughs have greatly enhanced the utility of these modeling approaches in four respects: i) pinning interactions are included in graded and multilayered structures, providing a better description of the limiting strain relaxation as well as the dislocation sidewall gettering; ii) a refined model for dislocation-dislocation interactions including zagging enables a more accurate physical description of compositionally-graded layers and step-graded layers; iii) inclusion of back-and-forth weaving of dislocations provides a better description of dislocation dynamics in structures containing strain reversals, such as strained-layer superlattices or overshoot graded layers; and iv) the compositional dependence of the model kinetic parameters has been elucidated for the InGaAs material system, allowing more accurate modeling of heterostructures with wide variations in composition. We will describe these four key advances and illustrate their applications to heterostructures of practical interest. Keywords: metamorphic structures; strain relaxation; threading dislocations; InGaAs/GaAs

1. Introduction Metamorphic (partially relaxed) realization of semiconductor devices has become increasingly important for materials such as InGaAs with no lattice-matched substrate. Development of metamorphic materials and devices has been guided mainly by timeconsuming empirical studies, so there has existed a strong need for modeling tools which could augment or perhaps even eliminate the need for empirical work prior to device design. Simple modeling approaches have been available for strain relaxation in *Corresponding

author.

31

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J. E. Ayers et al.

mismatched semiconductor epilayers since the development of the Dodson and Tsao model [1], applicable to a single, uniform layer on a mismatched substrate. What has been needed is a more detailed model, applicable to multilayered and graded structures, which includes dislocation-dislocation interactions and is capable of describing dislocation densities. Important recent breakthroughs have addressed these gaps in modeling, rendering a predictive model (“virtual laboratory”) for metamorphic heterostructure development in the InGaxAs1-x /GaAs (001) material system. These are: i) the inclusion of pinning interactions [2,3]; ii) a refined model for dislocation-dislocation interactions including zagging to enable a more accurate physical description of compositionally-graded layers and stepgraded layers [4,5]; iii) inclusion of back-and-forth weaving of dislocations to provide a better description of dislocation dynamics in structures containing strain reversals, such as strained-layer superlattices or overshoot graded layers [6]; and iv) determination of the compositional dependence of the model kinetic parameters for the InGaAs material system, allowing more accurate modeling of heterostructures with wide variations in composition [7]. In this paper we describe these recent advances and illustrate their application to InGaxAs1-x /GaAs (001) heterostructures. 2. Dislocation Dynamics Model The Dodson and Tsao model (1) describes lattice relaxation in a single, uniformcomposition heteroepitaxial layer. It is assumed that the strain is uniform throughout the layer and all misfit dislocations are located at the interface with a linear density of 𝜌 . The lattice relaxation 𝛾 in the layer is given by 𝛾 𝑓 𝜖, where 𝑓 is the lattice mismatch strain and 𝜖 is the actual strain, and the time rate of change of the lattice relaxation isa 𝑑𝛾 𝑑𝑡

𝑏 𝑠𝑖𝑛𝛼 𝑠𝑖𝑛𝜙

𝑑𝜌 , 𝑑𝑡

(1)

where 𝑏 is the length of the Burgers vector, 𝛼 is the angle between the Burgers vector and line vector, and 𝜙 is the angle between the surface normal and the slip plane. Dodson and Tsao used a phenomenological model for dislocation multiplication, giving the time dependence of the misfit dislocation density as 𝑑𝜌 𝑑𝑡

𝐾𝜌 𝑉𝜎

(2)

,

where 𝑉 is the dislocation glide velocity, 𝜎 is the effective stress, and 𝐾 is a phenomenological parameter. The effective stress is given by 𝜎 aIn

2𝐺 1

𝜈 𝑐𝑜𝑠𝜙 𝑐𝑜𝑠𝜆 𝜖 ℎ 1 𝜈

𝜖

,

(3)

their description, Dodson and Tsao did not explicitly include the geometric factor 𝑠𝑖𝑛𝛼 𝑠𝑖𝑛𝜙 which accounts for the mixed character of the dislocation as well as the inclination of its Burgers vector, but these factors were implicitly included in their final result.

Strain Relaxation and Dislocation Dynamics

33

where 𝐺 is the shear modulus, 𝜆 is the angle between the Burgers vector and that direction in the interface which is perpendicular to the intersection of the slip plane and the interface, 𝜈 is the Poisson ratio, 𝜖 is the in-plane strain, and 𝜖 is the equilibrium in-plane strain. The glide velocity is assumed to be thermally activated and linear in the effective stress: 𝑉

𝐵𝜎

𝑒𝑥𝑝

𝑈/𝑘𝑇 ,

(4)

where 𝑈 is the activation energy for dislocation glide, 𝑘 is the Boltzmann constant, 𝑇 is the temperature, 𝐵 and is a constant. Combining equations (1), (2), and (4), we obtain 𝑑𝛾 𝑑𝑡

𝐵𝐾𝑏 𝑠𝑖𝑛𝛼 𝑠𝑖𝑛𝜙𝜎

𝑒𝑥𝑝

(5)

𝑈/𝑘𝑇 𝜌 .

Because the initial value of 𝜌 is zero it is necessary to add a term 𝜌 which represents initial dislocation sourcesb: 𝑑𝛾 𝑑𝑡

𝐵𝐾𝑏 𝑠𝑖𝑛𝛼 𝑠𝑖𝑛𝜙𝜎

𝑒𝑥𝑝

𝑈/𝑘𝑇 𝜌

𝜌

.

(6)

Because the Dodson and Tsao model does not include the time dependence of the layer thickness, equilibrium strain, or temperature, it provides an approximate description for a uniform-composition layer, which is considered to appear spontaneously and then anneal for a time equal to the growth time at a temperature equal to the growth temperature. An important development was the extension of the Dodson and Tsao plastic flow model to account for time-dependent thickness, temperature, and equilibrium strain as well as compositional grading and multilayered structures by Kujofsa et al. [8], leading to the so-called Dodson & Tsao /Kujofsa & Ayers (DTKA) model, which will now be described. The DTKA model allows a more accurate description of a single uniform layer while also enabling application to arbitrary structures and processes, including changes in temperature and growth rate. Thermal strain due to differences in thermal expansion coefficients were also included. The time dependence of the relaxation 𝛾 𝑧 at a distance 𝑧 from the substrate interface in an arbitrary heterostructure is given by [8] 𝑑𝛾 𝑧 𝑑𝑡

𝐾𝐵𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆 𝜎

𝑧 𝑒𝑥𝑝

𝑈 𝑘𝑇

𝜌 𝜁

𝜌 𝑑𝜁 ,

(7)

where 𝛼 is the angle between the Burgers vector and line vector, 𝜆 is the angle between the Burgers vector and the line in the interface plane which is perpendicular to the 𝑧 is the effective stress, 𝑈 is the intersection of the glide plane and the interface, 𝜎 activation energy for dislocation glide, 𝑘 is the Boltzmann constant, 𝑇 is the temperature, bDodson and Tsao accounted for the initial dislocation sources indirectly, by adding a non-physical 𝛾 term, but 0 with similar effect.

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J. E. Ayers et al.

𝜌 𝑧 is the cross-sectional density of misfit dislocations, 𝜌 represents an initial density of defects, and 𝐵 and 𝐾 are semi-empirical constants. For InxGa1-xAs, recent work has yielded parabolic fits for the kinetic parameters as functions of the indium mole fraction (7). These are given graphically in Fig. 1, and analytic expressions for the best fits are as follows: 𝐵 0.48 𝑥1.74 𝑥 0.42 10 𝑐𝑚 𝑑𝑦𝑛 𝑠 , 𝐾 0.33 𝑥23 𝑥 0.41 10 𝑐𝑚 𝑑𝑦𝑛 . Activation energies for glide of 60o dislocations in InAs have been measured by Yonenaga [9] using temperatures in the range 200 450 °C and stresses up to 20 𝑀𝑃𝑎. In that work the activation energies for glide were found to be 1.4 𝑒𝑉 for both 𝛼 and 𝛽 dislocations in undoped material. Somewhat smaller activation energies were found for 𝛼 dislocations in InAs doped with S or Zn. Choi et al. [10] determined glide velocities in GaAs in the temperature range 150 500 °C with stresses up to 20 𝑀𝑃𝑎. They found activation energies which varied with stress and doping as well as the type of dislocation. Activation energies were in the range 1.0 1.4 𝑒𝑉 for 𝛼 dislocations and 0.7 1.6 𝑒𝑉 for 𝛽 dislocations. Here we adopt activation energy values equal to 1.4 𝑒𝑉 for InAs and 1.3 𝑒𝑉 for GaAs, and apply a linear interpolation for InxGa1-xAs alloys, but in future work a more detailed model could be employed, accounting for the variation of the activation energy with stress, doping, and type of dislocation. The activation energy for dislocation glide in InxGa1-xAs has therefore been approximated for this work as 𝑈 1.3 0.1𝑥 𝑒𝑉 [7]. 10

1.8

-9

parabolic fit experiment

1.6 1.4 1.2 1 0.8

0.6

0

0.2

0.4

0.6

0.8

1

indium mole fraction x

Fig. 1. Parabolic fits for the compositional dependence of the kinetic parameters B and K in InxGa1-xAs [7].

The effective stress is 𝜎

𝑧

2𝑐𝑜𝑠𝜙 𝑐𝑜𝑠𝜆 ℎ 𝑧

𝐺 1

𝜈 𝜖 𝜁 𝜖 1 𝜈

𝜁

𝑑𝜁 ,

(8)

where 𝜙 is the angle between the surface normal and the slip plane, 𝜈 is the Poisson ratio, 𝜖 𝑧 is the in-plane strain at a distance 𝑧 from the interface, 𝜖 𝑧 is the equilibrium inplane strain, and 𝜁 is a variable of integration. The equilibrium strain profile is determined for an arbitrary heterostructure using a numerical minimum-energy approach [11] or an

Strain Relaxation and Dislocation Dynamics

35

electric circuit model for the heterostructure [12]. The areal density of misfit dislocations is 1 𝑏 𝑠𝑖𝑛𝛼 𝑐𝑜𝑠𝜆

𝜌 𝑧

The length of misfit dislocations 𝐿

𝐿

𝑧

𝜕𝜖 𝜕𝑧

𝜕𝑓 . 𝜕𝑧

(9)

𝑈 𝑑𝜏 , 𝑘𝑇

(10)

𝑧 is given by

2𝐵𝜎

𝑒𝑥𝑝

where 𝑡 represents the time of the onset of lattice relaxation, corresponding to the critical layer thickness, and 𝜏 is a variable of integration. The equation governing the variation of the threading dislocation density 𝐷 is 4𝜌 𝑧

𝜕𝐷 𝑧 𝜕𝑧

𝑧 𝑠𝑔𝑛

𝐿

𝜌 𝜁 𝑑𝜁

𝐿

𝑧 𝐷 𝑧 ,

(11)

where 𝐿 𝑧 is the average length of misfit segments, and 𝐿 𝑧 is the interaction length for annihilation and coalescence reactions. We assume a dislocation will become pinned if it glides within the pinning radius of an orthogonal dislocation as shown in Fig. 2. Then the maximum length of misfit dislocations may be estimated as

𝐿

𝑧

,

𝜌 𝜁 𝑑𝜁

,

(12)

where 𝜁 is a variable of integration, and the pinning radius is 𝑟

√2𝜅𝐺𝑏/2𝜋𝜎

𝑐𝑜𝑠𝜆 ,

(13)

where 𝜅 is a unitless geometric factor. In order to include zagging and weaving at mismatched interfaces, an example of which is given in Fig. 3, it is assumed that the interaction length accumulates with the total line length of misfit dislocations at these interfaces 𝐿

𝑧

𝑐𝑜𝑠𝛽𝑎𝑏𝑠 𝐿

𝜉 𝑑𝜉 ,

where 𝛽 is the angle between the slip plane and the interface.

(14)

36

J. E. Ayers et al. gliding threading dislocation Free surface Epitaxial layer

h*

h

ro Substrate Misfit dislocation

Region where the glide force on the threading dislocation is nulled

Fig. 2. Pinning of a gliding dislocation by another dislocation having an orthogonal misfit segment in a mismatched epitaxial layer having a thickness h. The blocking dislocation is surrounded by a semi-cylindrical volume of radius ro in which the glide force acting on the gliding dislocation will be nulled.

L1



L2

L3

L4

z

substrate

Fig. 3. A grown-in dislocation in a structure with abrupt mismatched interfaces.

3. Results and Discussion The full dislocation dynamics model was applied to several InxGa1-xAs/GaAs (001) structures. First we considered the lattice relaxation as a function of time for a 75 nm layer of In0.26Ga0.74As/GaAs (001) grown at 450oC and then annealed at this same temperature for the balance of 1000 s. This structure exhibits saturation of the experimentallydetermined strain relaxation (13) as shown in Fig. 4. This saturation is predicted by the model only when pinning is included, as shown in the figure. Therefore the inclusion of pinning is necessary for layers which are thin or contain small residual strains. Next we considered the threading dislocation density as a function of thickness for InAs/GaAs (001) layers grown at 510oC, and compared the model calculations to experimental data published by Sheldon et al. [14]. As shown in Fig. 5, there is good agreement between the model and experimental threading dislocation densities. To investigate the effect of inserting a strained-layer superlattice (SLS) in an InGaAs/ GaAs (001) structure, we considered four heterostructures grown at 510oC with a growth rate of 0.5 m/hr. Using a SLS design comprising five periods of 10-nm In0.18Ga0.82As/ 10-nm In0.22Ga0.78As, we found the threading dislocation density profiles for four SLS positions: at the interface, midway through a uniform layer, and at the top of a uniform layer, as well as the case of no SLS. The uniform material was In0.2Ga0.8As with a total thickness of 1000 nm. The results in Fig. 6 show that the structure without an SLS contains

Strain Relaxation and Dislocation Dynamics

37

1.5 10 𝑐𝑚 dislocations but insertion of SLS at the interface decreases the dislocation density to 0.37 10 𝑐𝑚 . Inserting the SLS farther from the interface does not afford any benefit. Another application of the dislocation dynamics model is the design of patterned structures to make use of dislocation sidewall gettering (DSG). Figure 7 shows the maximum mesa width for the complete removal of threading dislocations by DSG in 600 nm-thick InGaAs/GaAs (001), for heterostructures grown at 510oC with a growth rate of 0.5 m/hr and then annealed for 30 minutes at the temperature indicated. It can be seen that the DSG behavior depends strongly on the composition as well as the temperature.

Fig. 4. In-plane lattice constant as a function of time for a 75 nm layer of In0.26Ga0.74As/GaAs (001) grown at 450oC and then annealed at this same temperature for the balance of 1000 s. The experimental results were reported by Whaley and Cohen [13].

Fig. 5. Threading dislocation density as a function of thickness for InAs/GaAs (001) grown at 510oC. The experimental results were reported by Sheldon et al. [14].

J. E. Ayers et al.

threading dislocation density (cm -2)

38

DSG Mesa Width ( m)

Fig. 6. Threading dislocation density profiles for four InGaAs/GaAs (001) heterostructures containing a SLS at the interface, midway in a uniform layer, and at the surface, compared to the case of no SLS.

Fig. 7. Maximum mesa width for complete removal of threading dislocations from 0.6 m-InxGa1-xAs/GaAs (001) as a function of composition with annealing temperature as a parameter.

4. Conclusion We have described recent advances to the modeling of strain relaxation and dislocation dynamics in InGaAs/GaAs (001) heterostructures to create a predictive model and a “virtual laboratory” for heterostructure design. These are: i) the inclusion of pinning interactions; ii) a refined model for dislocation-dislocation interactions including zagging to enable a more accurate physical description of compositionally-graded layers and stepgraded layers; iii) inclusion of back-and-forth weaving of dislocations to provide a better description of dislocation dynamics in structures containing strain reversals, such as strained-layer superlattices or overshoot graded layers; and iv) determination of the compositional dependence of the model kinetic parameters for the InGaAs material system.

Strain Relaxation and Dislocation Dynamics

39

Using this dislocation dynamics model, we have demonstrated several applications to InGaAs/GaAs (001) structures, including the prediction of strain and dislocation density in single heterostructures, dislocation filtering by superlattices, and dislocation sidewall gettering in patterned material. References 1. B. W. Dodson and J. Y. Tsao, Appl. Phys. Lett., 51, 1325 (1987); Appl. Phys. Lett., 52, 852 (1988). 2. T. Kujofsa and J. E. Ayers, Electrochem. Soc. Trans., 92, 43 (2019). 3. T. Kujofsa and J. E. Ayers, J. Electron. Mater., 49, 6990 (2020). 4. J. Raphael, T. Kujofsa and J. E. Ayers, Electrochem. Soc. Trans., 97, 79 (2020). 5. M. Cai, T. Kujofsa, X. Chen, Md T. Islam and J. E. Ayers, Int. J. High Speed Electron. Syst., 27, 1840022 (2018). 6. J. E. Ayers, T. Kujofsa, J. Raphael, Md T. Islam, J. Wales, K. Lindstrom and Y. Song, Electrochem. Soc. Trans., 97, 17 (2020). 7. K. Lindstrom, J. Wales, T. Kujofsa and J. E. Ayers, “Evaluation of a Plastic-Flow Model for InGaAs/GaAs (001) Heterostructures,” Materials Science and Technology Conference, Portland, OR (Sept. 29 – Oct. 3, 2019). 8. T. Kujofsa, W. Yu, S. Cheruku, B. Outlaw, S. Xhurxhi, F. Obst, D. Sidoti, B. Bertoli, P. B. Rago, E. N. Suarez, F. C. Jain and J. E. Ayers, J. Electron. Mater., 41, 2993 (2013). 9. I. Yonenaga, J. Appl. Phys., 84, 4209 (1998). 10. S. K. Choi, M. Mihara and T. Ninomiya, Jpn. J. Appl. Phys., 16, 737 (1977). 11. B. Bertoli, E. N. Suarez, J. E. Ayers and F. C. Jain, J. Appl. Phys., 106, 073519 (2009). 12. T. Kujofsa and J. E. Ayers, Semicond. Sci. Technol., 31, 115014 (2016). 13. G. J. Whaley and P. I. Cohen, Appl. Phys. Lett., 57, 144 (1990). 14. P. Sheldon, K. M. Jones, M. M. Al-Jassim and B. G. Yacobi, J. Appl. Phys., 63, 5609 (1988).

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0006

Design of a Smart Maximum Power Point Tracker (MPPT) for RF Energy Harvester Dilruba Parvin*,‡, Omiya Hassan*, Taeho Oh† and Syed Kamrul Islam* *Electrical

Engineering and Computer Science, University of Missouri, Columbia, Missouri 65211, USA †Electrical Engineering and Computer Science, University of Tennessee, Knoxville, Tennessee 37996, USA ‡[email protected]

Continuous enhancement of the performance of energy harvesters in recent years has broadened their arenas of applications. On the other hand, ample availability of IoT devices has made radio frequency (RF) a viable source of energy harvesting. Integration of a maximum power point tracking (MPPT) controller in RF energy harvester is a necessity that ensures maximum available power transfer with variable input power conditions. In this paper, FPGA implementation of a machine learning (ML) model for maximum power point tracking in RF energy harvesters is presented. A supervised learningbased ML model-feedforward neural network (FNN) has been designed which is capable of tracking maximum power point with optimal accuracy. The model was designed using stochastic gradient descent (SGD) optimizer and mean square error (MSE) loss function. Simulation results of the VHDL translated model demonstrated a good agreement between the expected and the obtained values. The proposed ML based MPPT controller was implemented in Artix-7 Field Programmable Gate Array (FPGA). Keywords: MPPT; RF energy harvester; FPGA; VHDL; hardware

1. Introduction Recently energy harvesters are becoming integral parts of applications such as biomedical implantable devices, wearable and portable devices, Internet of Things (IoT) etc. [1– 4]. Generally, energy harvesters use ambient energy as the energy source such as mechanical, thermal, radio frequency, solar etc. [5–8]. With the increased density of IoT devices in this era, RF energy has become omnipresent in the surroundings which makes it an appropriate source of energy harvesting [9]. The power density of RF energy is low compared to other ambient energy sources such as mechanical and thermal energy. Accordingly, the power received by the RF energy harvester is low requiring integration of an efficient power management system to increase the efficiency of such a system. Besides, for a given input power an energy harvester can

‡Corresponding

author.

41

42

D. Parvin et al.

operate at a maximum power point (MPP) to transfer the maximum energy to the load. With the variation of input power, the maximum power point of the system deviates from its desired value which results in variation of the output power [10]. Maximum power point tracking is a technique in which the system is operated at the maximum power point by matching the load resistance to the source resistance [11]. To date several classical MPPT methods have been adopted in the design of energy harvesters. MPPT algorithms for application in energy harvesters can be divided into four types: offline methods, online methods, intelligent based techniques, and hybrid techniques [12]. Online algorithms such as perturb and observe (P&O) and incremental conductance (INC) are used in most applications but suffer from low tracking speed and high fluctuations near the maximum power points [13]. On the other hand, offline algorithms such as fractional open circuit voltage (FOCV) algorithm and fractional short circuit current (RSCC) algorithm are relatively easier to implement in comparison to their online counterparts but offer less precision [14]. Besides, these conventional algorithms cannot differentiate between global and local maximum power points and demonstrate poor tracking performance under the condition of rapid input power variation [12]. Recently artificial intelligence techniques such as artificial neural network (ANN) and fuzzy logic controller (FLC) are being applied to track the maximum power point accurately with rapid input power variation [15,16]. In this work, a feedforward neural network based MPPT controller has been proposed in order to track the maximum power point of an RF energy harvesting system. The FNN model has been implemented in Artix-7 FPGA using Vivado Design Suite HLx and was validated by the simulation results on ModelSim-Intel FPGA package. The paper is organized as follows. Section 2 provides overview of the system configuration of the proposed RF energy harvester. In Section 3, the design process of the proposed machine learning based MPPT controller is described. Section 4 presents the results and the performance evaluation of the proposed system with concluding remarks in Section 5. 2. Configuration of the Proposed RF Energy Harvester System As demonstrated in Fig. 1, the RF energy harvester comprises of a matching circuit, an active rectifier, a DC-DC boost converter and an MPPT controller. A receiving antenna receives RF signals from ambient RF sources and converts the electromagnetic signal into electrical signal. The electrical signal output of the receiving antenna is then passed through a matching circuit that minimizes the loss due to impedance mismatch between the rectifier and the antenna and boosts the voltage to ensure the operation of the rectifier. The fully differential active rectifier added to the system is capable of providing rectified output voltage with high power conversion efficiency (PCE). The DC-DC boost converter steps up the voltage received from the rectifier and stores it into storage devices such as rechargeable batteries. The smart MPPT control circuit drives the DC-DC boost converter to reach the maximum power point by checking the input power (Pin) of the system, the input impedance (RIN) and the input voltage (VIN) of the DC-DC boost converter during one

Smart MPPT for RF Energy Harvester

43

Fig. 1. Complete system configuration of RF energy harvester with smart MPPT controller.

Fig. 2. Circuit diagram of the DC-DC boost converter.

switching period. The main components of the converter are shown in Fig. 2. The output voltage of the rectifier, VIN_RECT is boosted by the converter. The NMOS switch (MN1) is the sample and hold switch and the PMOS switch (MP1) is the free-wheeling current switch of the converter. An NMOS (MN2) and a PMOS (MP2) have been chosen as switching devices of the converter due to their very low threshold voltage values and ease of control of the device operation. Operating the boost converter with the duty cycle corresponding to the maximum power point will allow the converter to track the maximum power point successfully. SW_Low and SW_High are the low side and high side switch control signal of the converter respectively. In this case, SW_Low will be much greater than SW_High. Therefore, by controlling SW_Low the converter can be operated at the maximum power point. The output voltage of the DC-DC boost converter, VOUT can be expressed as Eq. (1) [16]. 𝑉 1 . (1) 1 𝐷 𝑉 where, D is the duty cycle of the converter.

44

D. Parvin et al.

3. Machine Learning Based MPPT Controller The design of the proposed machine learning based MPPT controller follows the steps as illustrated in Fig. 3. The data is first collected from the RF energy harvester [17] followed by the development of the ML model which is then trained using the data. Upon obtaining the optimal training accuracy, the learned parameters of the ML model are extracted. The ML model with optimal accuracy is then simplified and implemented into reprogrammable hardware such as field programmable gate array (FPGA). The hardware descriptive language, VHDL was used for the hardware implementation purpose.

Fig. 3. Design steps of the proposed ML based MPPT controller.

3.1. Software Simulation In order to build a hardware friendly model to effectively track MPPT, the ML model is developed first. The developed ML model further needs to be trained using the synthetic dataset that was created by manipulating the collected dataset. The process of development of the ML model and the data generation for the model are discussed in the following subsections. 3.1.1. Data Collection and Generation In order to train the ML model, data was collected from fractional open circuit voltage (FOCV) based MPPT controller integrated RF energy harvester [17]. The input attributes of this model are RF input power (Pin), input voltage (VIN) and input impedance (RIN) of the DC-DC boost converter. The output of the ML model is the duty cycle (SW_Low) of the DC-DC boost converter at a particular instant. Upon collection of the data, various combinations of the dataset were made in order to generate more training samples. Fig. 4 presents a small portion of the training dataset. The dataset was further divided into two portions: training and testing. The ML model was trained with 70% data and the remaining 30% was used to test the performance of the ML model.

Smart MPPT for RF Energy Harvester

45

Fig. 4. Small portion of the training dataset.

3.1.2. Feedforward Neural Network (FNN) Model A feedforward neural network architecture has been chosen as the ML model for tracking the maximum power point. FNN is the simplest form of neural network able to associate the input patterns with corresponding output patterns through non-linear mapping [18]. The basic unit of the FNN is the neuron which tries to mimic the behavior of biological neurons by using a mathematical function [19]. In the FNN, information flows from the input layer towards the output layer through a series of multiplication and addition operations. Due to its simplistic algorithm, FNN is considered as optimal design architecture for hardware implementation. A three-layer FNN architecture as demonstrated in Fig. 5 has been chosen in order to predict the duty cycle of the DC-DC boost converter. The FNN algorithm applied in the proposed system is presented in Fig. 6. The selected model was trained by using the machine learning library scikit-learn and Keras. In order to avoid overfitting issue, Stochastic Gradient Descent (SGD) optimizer was used while training the network. To evaluate the learning of the developed network, mean square error (MSE) was used as loss function. Fig. 7 shows the error loss plot for the proposed network during training and testing phases. Increasing the number of iterations (epochs) allows the model to learn better and thus decreases the error. At 500 epochs the model reaches convergence. Fig. 8 demonstrates that with the increment of epochs, the accuracy of the model increases. The model obtained 79.19% testing accuracy at 500 epochs which is considered optimal for the system.

46

D. Parvin et al.

Fig. 5. Proposed neural network architecture for tracking MPP.

Fig. 6. Proposed FNN algorithm for duty cycle prediction of the converter.

Smart MPPT for RF Energy Harvester

47

Fig. 7. Mean square error loss during training and testing of the FNN model.

Fig. 8. Training and testing accuracy of the FNN model.

3.2. Hardware Implementation of the ML Model The FNN model with optimal accuracy was translated into hardware system design. The neurons of the hardware system were designed by using trained weights and biases of the neural network. Typically, 32-bit floating-point library is used to perform mathematical operation with weights and biases. To reduce the power consumption, the weights and biases were converted into 8-bit integers in which 7 bits of the data indicate values of weights and biases and remaining 1 bit represents the sign bit. In order to reduce the power consumption further, shifters were used instead of multipliers. 4. Results and Discussion The selected three-layer FNN architecture was trained by using various optimizers such as ADAM, Stochastic Gradient Descent and RMSprop as presented into Table 1. From the table it can be concluded that by using Stochastic Gradient Descent optimizer 79.19% of accuracy can be obtained with batch size of 200. The evaluation of the models learning was checked by using mean square error loss function. The FNN model was implemented into hardware by using the parameters trained with Stochastic Gradient Descent optimizer to obtain optimal accuracy.

48

D. Parvin et al. Table 1. Testing Accuracy of the Proposed FNN Model with Different Optimizers. Optimizer

Accuracy (%)

Stochastic Gradient Descent

79.19

ADAM

73.93

RMSprop

74.61

The weights and biases of the optimized FNN model were then translated into hardware logic blocks by using VHDL. The logic blocks were implemented into hardware by using Vivado HLx Software. The RTL level schematics of the FNN is depicted in Fig. 9 whereas Fig. 10 shows the components of a single neuron block. A comparative study on the hardware utilization of FPGA for similar MPPT algorithms is presented in Table 2. From the table it can be observed that the proposed hardware model for MPPT algorithm uses significantly fewer number of LUTs and FFs in comparison to other similar works in literature and therefore has less power consumption. The simulation results of the FNN model using Xilinx ISE Software are shown in Fig. 11. The inputs of the FNN model are 8-bit binary signals (blue). The output signal of the FNN model is 1 bit (pink). The clock signal (dark red) of the model has duty cycle of 50 ns with a period of 100 ns. Rest of the signals are 8-bit internal signals (black). The

Fig. 9. RTL view of the FNN based MPPT controller implemented using Vivado HLx IP block design software.

Fig. 10. RTL view of the components of neuron implemented using Vivado HLx IP block design software.

Smart MPPT for RF Energy Harvester

49

Table 2. Comparative Study on Hardware Utilization. Publications

MPPT Algorithm

This Work

Neural Network

[20]

[21]

[22]

Fuzzy Logic

Neural Network

Fuzzy Logic

Resource

Utilization

Available

Utilization %

LUT

291

32600

0.89

FF

204

65200

0.31

IO

24

210

11.43

LUT

1928

10240

18

FF

2668

10240

26

IO

27

234

8

LUT

5029

28,800

17

FF

-

-

-

IO

18

440

4

LUT

1336

63400

2

FF

11

1337

0.8

IO

15

210

7

Fig. 11. Simulation results obtained by ModelSim Xilinx Edition-III (MXE-III) v6.0a.

FNN based MPPT controller starts working with a clock signal of 50% duty cycle. Then the behavior of the controller is observed, and the time required to reach to maximum power point is calculated automatically. With each clock cycle the system progresses through the required sequence of blocks of the model. Table 3 shows the electrical characteristics of the MPPT controller. For the given set of inputs where Pin is 1.8 mW, RIN is 2.44 kΩ, and VIN is 0.32 V, the value of the duty cycle obtained from the simulation is ‘1’ which is expected. The proposed FNN based MPPT controller reaches maximum power point very fast (within 800 ns). Therefore, the proposed FNN model is capable of predicting the duty cycle of the converter in real time. The simplistic hardware model proposed in this work can be integrated as the MPPT controller of DC-DC boost converter to attain the maximum power point to ensure maximum available power extraction.

50

D. Parvin et al. Table 3. Electrical Characteristics of the Proposed MPPT Block. Description

Value

Input Power of RF Energy Harvester, Pin

1.8 mW

Input Voltage of DC-DC Boost Converter, VIN

0.32 V

Input Impedance of DC-DC Boost Converter, RIN

2.44 kΩ

Output Voltage of DC-DC Boost Converter, VOUT

1V

5. Conclusion In this work a simple architecture of FNN has been proposed which possesses the capability to track the maximum power point of the proposed RF energy harvester successfully. The proposed machine learning model has been calibrated to obtain optimal accuracy. The trained model was designed and implemented into FPGA using VHDL in order to check its functionality. In future, the proposed model will be realized into a compact fully integrated CMOS circuit so that it can be integrated with RF energy harvester. Integration of this MPPT block will allow tracking of the maximum power point automatically for a wide range of input power variation. References 1. M. Stoopman, S. Keyrouz, H. J. Visser, K. Philips, Serdijn, Co-design of CMOS Rectifier and Small Loop Antenna for Highly Sensitive RF Energy Harvesters. IEEE Journal of Solid-State Circuits, 49, 3 (2014). 2. Z. Hameed, K. Moez, A 3.2 V -15 dBm Adaptive Threshold-Voltage Compensated RF Energy Harvester in 130 nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 62, 4, 2015. 3. Y. Lu, H. Dai, m.-K. Law, S-W. Sin, S.-P. U, R. P. Martins, A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting. IEEE Transactions on Circuits and Systems II: Express Briefs, 64, 2, 2017. 4. S. Kotani, A. Sasaki, T. Ito, High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs. IEEE Journal of Solid-State Circuits, 42, 1, 2009. 5. J. Zhang, Z. Fang, C. Shu, J. Zhang, Q. Zhang, C. Li, A Rational Piezoelectric Energy Harvester for Efficient Wind Energy Harvesting. Sensors and Actuators, 262, 1, 2017. 6. A. L. Cottrill, A. T. Liu, Y. Kunai, V. B. Koman, A. Kaplan, S. G. Mahajan, P. Liu, A.R. Toland, M. S. Strano, Ultra-High Thermal Effusivity Materials for Resonant Ambient Thermal Energy Harvesting. Nature Communications, 9, 664, 2018. 7. M. Caselli, M. Ronchi, A. Boni, Power Management Circuits for Low-Power Energy Harvesters. Journal of Low Power Electronics and Applications, 10, 3, 2020. 8. J. Park, H. Joshi, H. G. Lee, S. Kiaei, U. Y. Ogras, Flexible PV-Cell Modelling for Energy Harvesting in Wearable IoT Applications. ACM Transactions on Embedded Computing Systems, 16, 5s, 2017. 9. V. Kuhn, C. Lahuec, F. Seguin, C. Person, A Multi-Band Stacked RF Energy Harvester with RF-to-DC Efficiency Upto 84%. IEEE Transactions on Microwave Theory and Techniques, 63, 5, 2015.

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10. H. Rezk, M. AL-Oran, M. R. Gomaa, M. A. Tolba, A. Fathy, M. A. Abdelkareem, A. G. Olabi, A. H. M. El-Syed, A Novel Statistical Performance Evaluation of Most Modern OptimizationBased Global MPPT Techniques for Partially Shaded PV System. Renewable and Sustainable Energy Reviews, 115, 109372, 2019. 11. A. Youssef, M. E. Telbany, A. Zekry, Reconfigurable Generic FPGA Implementation of Fuzzy Logic Controller for MPPT of PV Systems. Renewable and Sustainable Energy Reviews, 82, 1, 2018. 12. M. Sharma, A. Achra, V. Gali, M. Gupta, Design and performance analysis of interleaved inverter topology for photovoltaic applications, 2020 International Conference on Power Electronics & IoT Applications in Renewable Energy and its Control (PARC), Uttar Pradesh, India, 28–29 February 2020. 13. S. D. Al-Majidi, M. F. Abbod, H. S. Al-Raweshidy, A Modified P&O-MPPT Based on Pythagorean Theorem and CV-MPPT for PV Systems, Proceedings on 2018 53rd Int. Universities Power Engineering Conference UPEC, Glasgow, UK, 4 –7 September 2018. 14. D. Baimel, S. Tapuchi, Y. Levron, J. Belikov, Improved Fractional Open Circuit Voltage MPPT Methods for PV Systems. Grid Connected Photovoltaic Systems, 8, 3, 2019. 15. S. Chang, Q. Wang, H. Hu, Z. Ding, H. Guo, An NNwC MPPT-Based Energy Supply Solution for Sensor Nodes in Buildings and its Feasibility Study. Energies, 12, 101, 2019. 16. L. Bouselham, M. Hajji, B. Hajji, A. E. Mehdi, H. Hajjaj, Hardware Implementation of Fuzzy Logic MPPT Controller on a FPGA Platform, 3rd Int. Renewable and Sustainable Energy Conference (IRSEC), Marrakech, Morocco, 10 –13 December 2015. 17. T. Oh, D. Parvin, O. Hassan, S. Shamsir, S. K. Islam, MPPT integrated DC-DC boost converter for RF energy harvester, IET CDS, 14, 7, 2020. 18. G. Bebis, M. Georgiopoulos, Feed-Forward Neural Networks. IEEE Potentials, 13, 4, 1994. 19. P. G. Asteris, P. C. Roussis, M. G. Douvika, Feed-Forward Neural Network Prediction of Mechanical Properties of Sandcrete Materials. Soft Sensors and Intelligent Algorithms for Data Fusion, 17, 6, 2017. 20. A. Messai, A. Mellit, A. Massi Pavan, A. Guessoum, H. Mekki, FPGA-Based Implementation of a Fuzzy Controller MPPT for Photovoltaic Module. Energy Conversion and Management, 52, 7, 2011. 21. F. Chekired, A. Mellit, S. A. Kalogirou, C. Larbes, Intelligent Maximum Power Point Trackers for Photovoltaic Applications using FPGA Chip: A Comparative Study. Solar Energy, 101, 4322– 4328, 2014. 22. M. Y. Allani, F. Taedo, D. Mezghani, A. Mami, FPGA Implementation of a Photovoltaic System Using a Fuzzy Logic Controller Based on Incremental and Conductance Algorithm. Engineering, Technology & Applied Research, 9, 4, 2019.

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0007

Quantum-Dot Transistor Based Multi-Bit Multiplier Unit for In-Memory Computing Yang Zhao*, Fengyu Qian†, Faquir Jain‡ and Lei Wang§ Department of Electrical and Computer Engineering, University of Connecticut, Storrs, CT 06269, USA *[email protected] †[email protected] ‡[email protected] §[email protected]

In-memory computing is an emerging technique to fulfill the fast growing demand for highperformance data processing. This technique provides fast processing and high throughput by accessing data stored in the memory array rather than dealing with complicated operation and data movement on hard drive. For data processing, the most important computation is dot product, which is also the core computation for applications such as deep learning neuron networks, machine learning, etc. As multiplication is the key function in dot product, it is critical to improve its performance and achieve faster memory processing. In this paper, we present a design with the ability to perform in-memory multi-bit multiplications. The proposed design is implemented by using quantum-dot transistors, which enable multi-bit computations in the memory cell. Experimental results demonstrate that the proposed design provides reliable in-memory multi-bit multiplications with high density and high energy efficiency. Statistical analysis is performed using Monte Carlo simulations to investigate the process variations and error effects. Keywords: in-memory computing; non-volatile memory; quantum-dot transistor; multiplier

I. Introduction Von Neumann architecture has been used for most computing systems. Even nowadays, the most state-of-the-art computer systems are still based on this architecture, which is characterized by separating memory storages and processing units. However, with the rapid development of emerging applications such as Internet-of-things (IoT), machine learning, biological medical systems, etc., computer systems have faced a lot of challenges. Due to the huge amount of data processing, the bottleneck of data movement between the storage and processing cores becomes a major concern in this big data era. Therefore, it is urgent to explore new solutions of computation architecture that can achieve faster processing and high throughput. In-memory computing is one of the promising approaches and has attracted a lot of attention recently. In general, in-memory computing enables computation  

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inside the memory array, which reduces the data movement between the processor and memory. Thus, in-memory computing is able to bypass the bottleneck by performing the computation with less energy consumption and smaller area overhead. The biggest difference between in-memory computing and conventional Von-Neumann architecture is the way they deal with data processing. In the conventional Von-Neumann architecture, the memory and processing units are separated. In order to perform a computational operation, data is transferred between the memory and processing unit. Due to the high frequency on data transfers, it brings large energy consumption and limits the throughput. While in the in-memory computing architecture, it performs the operations inside the memory without data transfer. Thus, this approach is able to provide energy efficiency and real time data computation. Many existing work on in-memory computing have been reported. In [1], a configurable 8T SRAM is proposed. This design provides several operations including left shift, right shift, and storage function. In [2], a 6T SRAM approach is proposed to perform logic computation such as AND, OR and XOR. In [3], the authors propose an 8T SRAM cell as a multibit dot product engine. The same research group extends their work in [4] to enable in-memory Boolean computations. Nonvolatile memory (NVM) is a semiconductor device that can maintain the stored data even after power-off. NVM can provide high density integration and energy-efficient operations, and thus is a promising candidate for in-memory computing. NVM devices such as resistive RAM (ReRAM), magnetic RAM (STT-MRAM) and phase change memory (PCM) are widely discussed for in-memory computing circuits. Some work have been done using these new memory devices. In [5], memristors-based ReRAMs have been used for logic operations. In [6], a ReRAM-based processing-in-memory architecture is proposed for graph computing shows. In [7], a design for in-memory computing with STTMRAM has been reported to perform logic, arithmetic, and vector operations. For neural network application, several groups have applied emerging devices for network acceleration. In [8], a ReRAM-based in-memory computing architecture is proposed for recurrent neural network accelerators. It was evaluated with some operations used in neural networks such as matrix multiplications and nonlinear functions. It should be noted that these existing schemes are practically difficult due to the fabrication complexity of integrating different components on the same chip. Also, few work explore multi-bit operations with small area overhead. In this work, we propose a cost-efficient solution using quantum dot memory. Specifically, we propose a multi-bit multiplier unit by using only two quantum-dot transistors. We also perform linearity analysis, parameter variations and power analysis. The proposed technique shows great linearity as a multiplier, and provides high accuracy and low power consumption. As mentioned above, dot product is the most important operation used in neural networks. Thus, the proposed technique can be applied in the applications for deep learning and AI. The rest of this paper is organized as follow. Section II discusses the quantum-dot transistor as a non-volatile memory device and proposes an in-memory multi-bit multiplier unit cell including the circuit design and operating principle. Section III presents the

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simulations to demonstrate the multibit multiplication and statistical analysis of linearity and power consumption. Section IV concludes the paper. II. Proposed Design In this section, we first review the quantum-dot technology, followed by a brief discussion of quantum-dot transistors as memory devices. Then, we present the quantum-dot transistor based dot product unit with detailed design methods and operation principals. A. Quantum-dot Transistor Memory Quantum-dot gate memory is one of nonvolatile memories that has not been discussed for applications of in-memory computing. It has potential to achieve the required operation with high precision due to its characteristics with multi-bit state logic. From the device physics perspective, a quantum dot is referred to as a semiconductor nanocrystal with sub10nm size [9]. As the size of nanocrystal reduced, quantum physics will take in charge and open up opportunities for innovative architectures. In particular, the electrons inside of nanocrystal show the characteristics of quantized energy levels rather than the continuous energy bands. Studies carried out for this new nanotechnology have attracted a lot of attentions in the semiconductor industry. The basis of quantum-dot transistors is that nanoscale conductors are placed in the oxide layer between the gate and channel of a transistor. The distribution of quantum dots is related to the external applied potential voltage, and the transistor can be programmed to the expected state by appropriate tuning. Based on the operation of the transistor, the threshold voltage can be modulated to store different logic states by the total number of charges that are accumulated with capacitance formed by the quantum dots. In order to investigate the programmable performance of quantum-dot transistors, the characteristic curves are measured by applying appropriate gate voltages. Then, the total number of captured charges can be calculated. The quantum-dot gate memory has been reported in [10–13]. Unlike conventional memory which has only two states, the quantum-dot gate memory has many states between high and low. Thus, multiple states can be stored in the device. Figure 1 depicts the cross-

Fig. 1. Cross-section view of a quantum-dot transistor.

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section schematic of a quantum-dot transistor. It shows that a quantum-dot layer is added into the oxide of the transistor. The threshold voltage of the transistor is determined by the amount of charges present in the quantum-dot floating gate, which means the threshold voltage can be precisely controlled by applying different gate or drain voltages [12]. Therefore, this device can be used as a multi-bit nonvolatile memory to reduce the total number of transistors in the memory. In conventional memory circuits, 6-T SRAM is used to store only one bit. In contrast, one quantum-dot transistor can store multiple bits. As a result, smaller area and lower power dissipation can be achieved. B. Quantum-dot Transistor Based Multi-bit Multiplier Unit Analog circuits are able to perform the computation of neurons in neural networks and thus they are used in many systems. As shown in Fig. 2(a), a set of inputs xi and weights wi perform weighted sum ∑ 𝑥 ∙ 𝑤 [14], where the dot product is used as a part of this operation. In Fig. 2(b), an analog circuit performs the operation of the neuron computation. The analog currents I(xi) go through the resistors with values of R(wi), which are proportional to the weights wi. From the Kirchhoff’s law, the output voltage is equal to Vout = R(wi)I(xi). This example shows a way to achieve neuron computation by using low-complexity analog circuits. Compared with the digital circuit implementation that requires adders, multipliers and other digital blocks, the analog circuit implementation enables a more cost-efficient way of performing dot products. Motivated by neuron computation and the rapid development of nonvolatile memory devices, in this paper we propose a new design of multi-bit multiplier unit for in-memory computing. The proposed design is shown in Fig. 3, where quantum-dot transistor T1 acts as a memory cell with the stored multi-bit value, and quantum-dot transistor T2 is the sensing device that provides the multiplication functionality. The reference voltage Vref applied on the drain of T1 provides the operation bias of the entire circuit. Resistor R0 acts as a voltage divider and is used to propagate the multi-bit logic value from T1 to the gate

Fig. 2. (a) Neuron computation and (b) its analog circuit implementation.

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Fig. 3. The proposed multi-bit multiplier unit.

of T2. The data is stored in the quantum-dot transistor T1 and this value can be represented as a voltage in this circuit. Thus, it will be propagated to the gate of T2 as an analog voltage VGS, which is determined by the stored value. In other words, T1 acts like a variable resistor and the resistance is determined by the quantum dot distribution which is related to the stored value. As a result, different voltages are propagated as a function of the stored multibit value in T1. It is then followed by the second transistor T2 with the input signal of Vin. The output IDS is proportional to VGS ·Vin according to the IV characteristics of transistors. In Fig. 3, R0 is chosen based on the resistance level of T1. As mentioned above, T1 is treated as a variable resistor where the resistance is determined by the quantum dot distribution in the channel. As a matter of fact, the resistance range is related to the fabricated device parameters including width, length, tunneling gate thickness, injected quantum dots, etc. The modeling and fabrication of quantum-dot transistor has been discussed in [5,12]. In order to obtain a proper value of R0, the circuit can be simulated for a fixed VA. For sub90nm technology, VDD is normally less than 1.2V; so we use the reference voltage Vref as 1V in our design. Based these parameters, we can select R0 to get the desired VGS at point A. For example, if VGS needs to be in the range of 0.4V to 0.65V so that the output current is in the linear region, we can perform simulations to determine the value of R0 for this goal. C. Operating Principle In this subsection, we describe the basic operation of the proposed multi-bit multiplier unit. Note that the multi-bit value in T1 can be mapped into an analog voltage and propagated to point A as VGS. Transistor T2 generates output current IDS as a function of input voltage Vin and VGS. For CMOS transistors, the current IDS in the linear region can be expressed as:

(1)

where kn is the gain factor and is depended on the transconductance (µn · Cox) and ratio of the transistor, VGS is gate-to-source voltage, VDS is drain-to-source voltage, and VTH is the threshold voltage of the transistor.

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The proposed multi-bit multiplier unit needs to maintain in the linear region so that the current IDS is approximately proportional to VGS · VDS. Note that VDS is the input voltage Vin applied on the drain of T2, while VGS is the corresponding voltage of the multi-bit value in T1. Thus, the output current has a linear relation with VGSS · Vin as: (2) As an example, assume that the multi-bit value stored in T1 has two-bit precision. Let the stored value be ‘01’ which is mapped to an analog voltage VGS. The input Vin is also a two-bit value (for instance Vin is ‘11’) and is mapped to an analog voltage VDS applied on the drain of T2. If Vin and VDS are in the proper range, transistor T2 will be in the linear range. The output current IDS is a function of the multiplication of Vin and VDS, which can be converted to a four-bit value ‘0011’. D. Linearity Analysis As shown in (1), some non-linear components will affect the accuracy of multiplication. Here we present a regression analysis to study this problem. The coefficient of determination, denoted as R-squared value, is used to measure the goodness-of-fit for linear models. This statistic indicates the variance in an observed variable with respect to its ideal values generated from a linear model. The R-squared value is always in the range of 0 to 100%, and a larger R-squared value shows better linearity in the observed variable (with respect to certain parameters). For our study, let IDSi be a set of output currents with n values as IDS1, IDS2, ..., IDSn, and each value has an ideal value f1, f2..., fn, which is the result of a linear model, e.g., if only the product of VDS and Vin is considered, IDS would increase linearly with Vin for a given VDS. If 𝐼 is the mean of the IDSi, then the total sum of squares is given by:

(3)

and the sum of squares of residuals is given by: (4) The coefficient of determination (R-squared) can be obtained as: (5) If the measured IDSi matches the linear model exactly, then SSres = 0 and R2 = 1, which indicates a perfect linearity without non-linear errors. However, several components, such as VGS and VTH will affect the linearity of the multibit multiplication unit. From (1), in order to get a better multiplication result with less non-linear errors, we need a larger VGS but a smaller VTH. Also, VDS should be selected within a reasonable range. It cannot be too small; Otherwise, it will limit the dynamic range of the multi-bit multiplication unit. On

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linearity of computation. As an example, if VGS is 0.65V, VTH is 0.25V, and the value of Vin is in the range from 0.025V to 0.1V, we can get the output currents IDS for different values of Vin, and R-squared value can be calculated to be R2 = 99.91%, which shows a great linearity of multiplication. More results are provided under different situations to evaluate the accuracy of our design in the following section.

Fig. 4. IDS versus Vin characteristics curve with VTH = 0.25V.

III. Evaluation In this section, we evaluate the proposed technique. We first show simulation results and then study parameter variations and perform power analysis. A. Performance We simulate the proposed design in a 90nm CMOS process with the device model modified for quantum-dot transistors. Figure 4 shows the IV characteristics for the output current IDS with respect to the input voltage Vin. Note that only when the VDS of T2 is between 0.025V and 0.1V, T2 is in the linear region for different VGS. For the purpose of demonstration, we choose four lines to represent a 2-bit by 2-bit multiplication and summarize the results in Table I. The values for VGS are 0.4V, 0.45V, 0.50V and 0.55V, mapped to 2-bit digital values 00, 01, 10 and 11, respectively. The values for Vin are 0.025V, 0.050V, 0.075V and 0.100V, mapped to 2-bit digital values 00, 01, 10 and 11, respectively. For 2-bit by 2bit multiplication, the result is a 4-bit value. The output current IDS and the expected 4-bit digital values are shown in Table I.

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  Clearly, IDS follows a linear trend with respect to the product of VDS and Vin, e.g., for a given VDS, IDS increases almost linearly with Vin. As discussed in Section II-D, some errors exist due to the non-linear components in the IV characteristics (see (1)). For example, when Vin = 0.10V and VGS = 0.50V, the measured IDS is 0.890µA, whereas the ideal value should be 0.95µA if only the product of VDS and Vin is considered. Also, for the case of multiplication of 10 and 01, the result should be similar to the case of 01 multiplying 10 since they both are calculated as 0110. Our results show that the current outputs are 0.890µA and 0.872µA for both cases, indicating a good match. To study the impact of the errors due to the non-linearity in (1), we use R-squared values as discussed in Section II-D. Figure 5 shows the current outputs and those from the corresponding linear models (e.g., results from the product of VDS and Vin only). We can see that current outputs are almost proportional to the input voltage with great linearity, and the R-squared values for VGS of 0.65V to 0.4V are between 0.9991 and 0.9865, very close to 100%. Table II shows the error percentage due to the nonideality for 2-bit by 2-bit multiplications. We can see that most of the output errors are less than 5%. Thus, the nonlinear errors have a very little impact on the proposed technique.

Fig. 5. Fitted line for linear models with R-squared values.

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  B. Statistical Analysis of Process Variations For analog computing, process variations introduced during the manufacturing of IC devices may affect the circuit performance. This can be a potential issue in the proposed multi-bit multiplication circuit due to the reduced logic margin. In order to investigate this problem, Monte Carlo simulations were performed to analyze the performance of the proposed circuit. We primarily consider the variations in threshold voltage, transistor width and length, and resistance caused by IC fabrication. The circuit model in [15] was used to carry out our Monte Carlo simulations. We assume that process variations follow a Gaussian distribution with a tolerance of 5%. By performing operating point analysis, an ideal current is generated through the circuit and the output currents under different VGS are generated. For all the cases, Vin is a DC voltage sweeping from 0 to 0.5V and VGS is applied on the gate of transistor. A zoomed view of output current IDS is shown in Fig. 6 to illustrate the Monte Carlo simulation results. As we can see, process variations cause IDS to vary in the range of 0.849µA to 0.852µA at Vin = 0.095V, and IDS also follows a Gaussian distribution.

Fig. 6. The statistical measurement of the current IDS.

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In order to investigate the accuracy of output current for each VGS and Vin combination, Monte Carlo simulations have been conducted to obtain the output current distribution. The histogram of statistical distribution of IDS for 1000 simulations is shown in Fig. 7 for several combinations of VGS and Vin. Specifically, Fig. 7(a) is for the case of VGS = 0.45V and Vin = 0.075V, which represents the binary inputs 01 and 10, respectively. It can be seen that the output current is quite similar to Gaussian distribution with small variances, indicating good consistence in multi-bit multiplications in the presence of process variations.

Fig. 7. Statistical distribution of IDS for different VGS and Vin: (a) VGS = 0.45V and Vin = 0.075V, (b) VGS = 0.50V and Vin = 0.050V, (c) VGS = 0.50V and Vin = 0.075V, and (d) VGS = 0.55V and Vin = 0.10V.

C. Power Consumption There are several advantages of using quantum-dot transistors for high-density in-memory computation. The most important one is improved energy efficiency compared with conventional SRAM circuits. As a nonvolatile memory device, quantum-dot transistor multibit multiplication unit can reduce power consumption by having data stored on chip for less access to external memory. Furthermore, less data movement leads to fast execution time, which can also transfer to a low power design.

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In this subsection, we evaluate the power consumption of the proposed design for inmemory computing applications. According to the existing reports, for traditional CMOS 6T SRAM, energy consumption can vary from 1pJ to 10pJ per dot product operation. In addition, some works [16 –18] have reported more advanced 8T/10T memory cells for in memory computing, which can achieve average energy per dot product operation from 17.25f J to 29.67f J. Switch analog circuits (SAC) is also reported as an energy-efficient approach to implement mixed-signal multiplication kernels for applications like machine learning. This design achieves energy per dot product operation from 0.1pJ to 1pJ. In comparison, the energy per dot product operation of the proposed design is estimated to be 15.5fJ based on simulation results. Figure 8 compares the energy efficiency with some conventional implementations.

Fig. 8. Average energy per dot product operation in different implementations.

Note that using 8T or 10T memory cells for in-memory computing results in 1.5X area increase over 6T memory cells. In contrast, the proposed design only requires two quantum-dot transistors, and thus can reduce the total number of transistors significantly. This offers great benefits for highdensity memory array design to deal with massive data processing in the big data era. Further improvement for the proposed technique can be achieved by replacing the resistor R0 (see Fig. 3) with a QD-NVM. In order to make the QD-NVM work as are resistive load, the gate and drain need to be connected and more discussion can be found in [19]. This brings up a few advantages. First, the DC power consumption on R0 will be reduced as the resistor is replaced with a non-volatile device. Also, this resistive load can be programmed precisely to the required level by using different programming voltages. As a result, the resolution of the multi-bit multiplication unit is improved and quantization errors will be reduced.  

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IV. Conclusion In this paper, we have proposed a multi-bit multiplier unit using quantum-dot transistors for in-memory computing. The proposed scheme can achieve multi-bit multiplication with high accuracy. Furthermore, the design only uses two quantum-dot transistors, which significantly reduces area overhead and power consumption. We have verified the functionality through Monte Carlo simulations and conducted error analysis. The proposed scheme can be used as a dot product compute engine in a memory array. Dot product is the core computation in data intensive applications such as neural network, machine learning and artificial intelligence. Thus, the proposed technique has a great potential to be used as a computing accelerator in these applications. Future work is directed towards further optimization in energy efficiency and a full-fledged system design. References 1. H. Chen, J. Li, C. Hsu, and C. Sun, “Configurable 8T SRAM for enabling in-memory computing,” in 2019 2nd International Conference on Communication Engineering and Technology (ICCET), April 2019, pp. 139 –142. 2. Q. Dong, S. Jeloka, M. Saligane, Y. Kim, M. Kawaminami, A. Harada, S. Miyoshi, D. Blaauw, and D. Sylvester, “A 0.3V VDDmin 4+2T SRAM for searching and in- memory computing using 55nm DDC technology,” in 2017 Symposium on VLSI Circuits, June 2017, pp. C160– C161. 3. A. Jaiswal, I. Chakraborty, A. Agrawal, and K. Roy, “8T SRAM cell as a multibit dot-product engine for beyond von Neumann computing,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2556 –2567, Nov 2019. 4. A. Agrawal, A. Jaiswal, C. Lee, and K. Roy, “X-SRAM: Enabling in-memory Boolean computations in CMOS static random access memories,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 12, pp. 4219 – 4232, Dec 2018. 5. J. Borghetti, G. Snider, P. Kuekes, J. J. Yang, D. Stewart, and S. Williams, “Memristive switches enable stateful logic operations via material implication,” Nature, vol. 464, pp. 873– 876, 04, April 2010. 6. L. Han, Z. Shen, Z. Shao, H. H. Huang, and T. Li, “A novel ReRAM-based processing-inmemory architecture for graph computing,” in 2017 IEEE 6th Non-Volatile Memory Systems and Applications Symposium (NVMSA), Aug 2017, pp. 1–6. 7. S. Jain, A. Ranjan, K. Roy, and A. Raghunathan, “Computing in memory with spin-transfer torque magnetic ram,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 3, pp. 470–483, March 2018. 8. Y. Long, T. Na, and S. Mukhopadhyay, “ReRAM-based processing-in-memory architecture for recurrent neural network acceleration,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 26, no. 12, pp. 2781–2794, Dec 2018. 9. R. Joga, “Quantum dot floating gate transistor with multi-wall carbon nano tube channel for non-volatile memory devices,” in 2012 International Conference on Communication Systems and Network Technologies, May 2012, pp. 774 –779. 10. H. Zhang, Y. Zhang, Y. Yu, X. Song, H. Zhang, M. Cao, Y. Che, H. Dai, J. Yang, and J. Yao, “Ambipolar quantum-dot-based low-voltage nonvolatile memory with double floating gates,” ACS Photonics, vol. 4, no. 9, pp. 2220 –2227, July 2017.

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11. Y. Darma and A. Rusydi, “Quantum dot based memory devices: Current status and future prospect by simulation perspective,” AIP Conference Proceedings, vol. 1586, no. 1, pp. 20–23, Feb 2014. 12. J. Kondo, M. Lingalugari, P.-Y. Chan, E. Heller, and F. Jain, “Quantum dot channel (QDC) field effect transistors (FETss) and floating gate nonvolatile memory cells,” Journal of Electronic Materials, vol. 44, no. 9, pp. 3188–3193, Sep 2015. 13. J. A. Chandy, and F. C. Jain, “Multiple valued logic using 3-state quantum dot gate FETs,” in 38th International Symposium on Multiple Valued Logic (ISMVL, 2008), May 2008, pp. 186 – 190. 14. R. S. Amant, A. Yazdanbakhsh, J. Park, B. Thwaites, H. Esmaeilzadeh, A. Hassibi, L. Ceze, and D. Burger, “General-purpose code acceleration with limited-precision analog computation,” in 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), June 2014, pp. 505–516. 15. P. R. Kinget, “Device mismatch and tradeoffs in the design of analog circuits,” IEEE Journal of Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224, June 2005. 16. A. K. Rajput, and M. Pattanaik, “Implementation of Boolean and arithmetic functions with 8T SRAM cell for in-memory computation,” in 2020 International Conference for Emerging Technology (INCET), 2020, pp. 1–5; W. Simon, J. Galicia, A. Levisse, M. Zapater, and D. Atienza, “A fast, reliable and wide-voltage-range in-memory computing architecture,” in 2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, pp. 1–6 17. W. Simon, J. Galicia, A. Levisse, M. Zapater, and D. Atienza, “A fast, reliable and wide-voltagerange in-memory computing architecture,” in 2019 56th ACM/IEEE Design Automation Conference (DAC), 2019, pp. 1–6. 18. I. Nahlus, E. P. Kim, N. R. Shanbhag, and D. Blaauw, “Energy-efficient dot product computation using a switched analog circuit architecture,” in 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED), 2014, pp. 315–318. 19. S. Karmakar, M. Gogna, and F. Jain, “Fabrication of QDNVM-based comparator,” Micro Nano Letters, vol. 14, no. 9, pp. 947–951, 2019.

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0008

Single Chemical Sensor for Multi-Analyte Mixture Detection and Measurement: A Review Bo Zhang* and Pu-Xian Gao† Department of Materials Science and Engineering & Institute of Materials Science, University of Connecticut, Storrs, CT 06269-3136, USA *[email protected] †[email protected]

Multi-analyte chemical sensor aims to transform subtle variations in multiple analytes’ physical or chemical properties into distinct output signals. Chemically responsive nanostructure array (nanoarray) promises as a competitive sensor platform due to its robust physical properties, tunable chemical composition, and high surface area for analyte interaction. Specifically, the well-defined size, shape, and tunable surface structure and properties make it feasible to develop either new sensing modes on single device or integrated multi-modular sensors. In conjunction with the well-developed resistor-type sensors and sensor arrays, the complementary utilization of and intercorrelation with the electrochemical, optical, voltammetry modes in the multi-modular sensing strategies could provide multi-dimensional measurements to different analytes in a complex mixture form, where species information could be accurately and robustly separated from spatially collective responses. This review intends to provide a survey of the recent progress on multi-analyte sensing strategies and their unique structure design, as well as the related sensing mechanics in interaction of analytes and sensitizer and the behind mechanism for analytes’ differentiation. Keywords: multi-analyte mixture; nanoarray; chemical sensor

1. Introduction As of today, sensors represent a reliable and standard approach in analytical research and on-board measurement [1–3]. Initially, the efficient detection was carried out in a “lock and key” design (i.e., a single sensor versus a specific analyte). Such a sensing strategy can only provide limited selectivity when dealing with multiple analytes or a analyte mixture scenario, while suffers from cross-reactions to chemical species which are structurally and chemically similar to the target analyte [4–6]. Thus, selective detection can only be achieved when a specific target analyte is identified in presence of controlled backgrounds or interferences [7]. To overcome the poor selectivity in the conventional point-to-point sensors, more sophisticated analysis heavily relies on the spectroscopy-based instruments such as FTIR [8], GC-MS [9], and IR spectrometers [10], which allow the differentiation

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of multiple analytes or separation of mixture into its constituents. Additionally, for the practical on-board detection, multiple sensors are usually bundled together as a sensor array for multi-analyte measurements or multi-dimensional measurements towards a specific analyte. But such strategies would be less cost-effective and more space consuming [11]. On the other hand, severe cross-sensitivities tend to be inevitable in detecting or measuring analytes of similar physical or chemical properties [12,13]. In the meantime, the advances in nanoscience and nanotechnology are driving the miniaturization of sensor devices to nanoscale or even smaller [14–16]. As an example, nanostructure array (nanoarray), a miniaturized array form of nanomaterials, provides a higher response than their bulk counterpart due to its robust structure, long-term uniformity, remarkable ratio of surface area to volume, and highly populated adsorption sites for analyte interaction [17–20]. Moreover, many strategies have been developed to further adjust the pristine structures and properties, and improve their sensing performance (i.e., sensitivity, selectivity, and stability) [15,21]. For instance, hierarchical nanostructures can be built via decoration of noble metal nanoparticles on pristine structures to create heterostructures to optimize the detection limit and enhance selectivity by enlarging sensitivity difference between target analyte and interference [22,23]. Meanwhile, the size reduction of sensor material makes it feasible to be integrated into a small chip, forming high-density sensor array [24–26], where each sensor element provides a unique response towards a specific analyte. Together with other elements’ responses, a special signature for a certain target is established and gas recognition is therefore achieved. However, high concentration sensors and associated electrical feedthrough may greatly increase the cost of sensor array fabrication and the risk of malfunction [27]. To decrease the fabrication cost and workload, more attentions lately have been focused on developing alternative sensing modes or multi-modular sensing strategies. It is known that the sensing mechanism of a resistor-type sensor is due to the electrical resistance variation upon exposure to target analytes [28,29]. As stated earlier, it can suffer from a poor selectivity due to the cross sensitivities as well as one-dimensional resistance changes [30]. As for a sensor array architecture, a low cross sensitivity is not required for individual sensor element, the response diversity towards different analytes is usually relied on the number of sensor elements. In addition to resistor mode, other sensing modes such as surface plasmon resonance, impedance-metric, field effect transistor, and voltammetry have been considered as competitive candidates for multi-analyte detection and measurement. Their corresponding configurations and operating principles are depicted in Scheme 1. Specifically, electrochemical voltammetry measurement can allow simultaneous detection of variant analytes based on their distinct oxidation-reduction reactions. Different analytes may yield different cyclic voltammograms to provide sufficient footprint for selective sensing [31]. Surface plasmonic resonance is another selective sensing mode owing to their characteristic molecular structure recognition ability with respect to the distinct wavelength-dependent absorption response when exposed to different gases or biochemicals [32]. In addition to the individual sensing modes as illustrated in Scheme 1, efficient and selective sensing can be achieved through the distinct

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Scheme 1. Schematic illustration of different operating sensing modes: (a) voltammetry mode, (b) surface plasmon resonance mode, (c) impedance-metric mode, and (d) field effect transistor mode.

but intercorrelated sensing feedbacks of multiple sensing modes from a single sensing material, forming an alternative approach for multi-analyte detection and measurement. Utilizing the diverse sensing behavior in different sensing modes, the characteristic signature for a specific analyte can be readily and precisely obtained with proper data processing techniques. It is noted that the key of using a single device to detect and measure multi-analyte mixture is to choose a proper sensing mode which could build a distinct response pattern based on their unique analyte-sensor interactions. Thus, a concise review is presented here to survey the recent development of the state-of-the-art multi-analyte sensors and the behind sensing mechanistic understanding thus far. These chemical sensors are generally classified by the transduction approaches used to trace subtle variation of analytes. The concept of sensor design and performance will be reviewed in various practical cases for multi-analyte differentiation. Finally, the behind operating mechanism will be highlighted, especially on the analyte-sensor interaction. 2. Voltammetry Multi-Analyte Sensor The Voltammetry mode obtains the signature information about analytes by measuring the current as the potential is varied [33]. The analytical data in voltammetry mode originates from the voltammogram where current produced by analyte is plotted with respect to the potential of working electrode. In comparison to resistance metric or amperometry mode measured in a constant bias, the potential is varied in steps or continuously while the current is measured as the dependent variable. Thus, the half-cell reactivity of analyte is investigated and revealed as the loop-shape response in voltammetry [34]. When applied

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in a mixture scenario consisting of several redox analytes or ions, the selectivity in amperometry mode is often insufficient as current-based responses are usually too close to be individually discriminated. However, the potential-based current response in voltammogram contains a large amount of information, for which multivariable analysis can be used to extract the characteristic response for each analyte [35]. This has been further developed into the concept of “electronic tongue”, the supplementary design of “electronic nose” for gas detection [36–38]. In comparison to traditional bulk materials as working electrode, the choice of nanoarrays brings up advantages such as a much higher surface area, excellent mechanical and structural stabilities, and a better re-usability. Kumar et al. [39] proposed a new type of molecularly imprinted polymers (MIPs) for selective analysis of uracil and 5fluorouracil, which are frequently involved in the biosynthesis of numerous enzymes necessary for cellular function. Fig. 1(a) depicts the synthetic flowchart, where the usage of Ag as substrate is due to its oxidative characteristic revealed at low voltage. The detailed surface structure is revealed by atomic force microscopy (AFM), as shown in Figs. 1(b) and 1(c). The adsorption of uracil and 5-fluorouracil on MIP were driven by a special 𝜋 𝜋 interaction, which would yield different morphologies. The selective sensing was carried out by Differential Pulse Anodic Stripping Voltammetry (DPASV). As shown in the Figs. 1(d) and 1(e), the DPASV curves increase with increasing analytes’ concentration. Owing to the special nanoarray working electrode, the peaks representing two analytes are highly asymmetric. It is worth pointing out that peaks of analytes (5-FU or Ura) can be individually differentiated by potential. The DPASV response of 5-FU contains one major peak at -0.8 V and a minor peak to the right side, while the spectra of uracil only have one peak at -0.75 eV. Moreover, the linear regression functions were summarized in the inset figures, where the detection limit reaches 0.5 ng/mL and 0.33 ng/mL for Uracil and 5fluorourcil, respectively. In addition to chemical analyte detection, the environmental monitoring capabilities of pH, humidity, and temperature could be extended based on the voltammetry mode [40]. The structure and morphology of as-prepared nickel phosphate (Ni3(PO4)2ꞏ8H2O) are revealed in Figs. 1(f) ~1(i). The Fig. 1(j) depicts cyclic voltammogram (CV) of nickel phosphate electrode, where current density for oxidation peak increases with increasing glucose concentration from 10 µM to 2 mM. The slope of linear calibration line (Fig. 1(k)) suggests an excellent sensitivity of 24.39 mA mM-1 cm-2, while the deviation at the high glucose concentration may be due to the passivation of electrode and overwhelming accumulation of analytes locally. Additionally, the pH value can be measured based on potential difference between the reference and the working electrodes according to Nernst equation [41]. Fig. 1(l) displays the open-circuit potential as a function of pH, with the corresponding sensitivity around 34.18 mV/pH.

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Fig. 1. (a) Schematic process of synthesis of molecularly imprinted polymers (MIPs) nanoarray onto silver surface. AFM images of (b) MIP-Ura, and (c) MIP-5-FU nanoarrays. Differential Pulse Anodic Stripping Voltammetry (DPASV) spectra of (d) Ura and (e) 5-FU at MIP nanoarray electrodes. Reprinted with permission from Ref. 39, copyright (2015) the Royal Society of Chemistry. (f, g) Scanning electron microscopy (SEM) images of nickel phosphate (Ni3(PO4)2ꞏ8H2O) nanostructure at low and high magnifications. (h, i) Transmission electron microscopy (TEM) images of as prepared Ni3(PO4)2ꞏ8H2O nanoflakes array and individual nanoflake. (j) Cyclic Voltammograms (CV) of Ni3(PO4)2ꞏ8H2O measured at various glucose concentrations. (k) The linearly derived function of current density versus glucose concentration. (l) Open circuit response curve for pH value measurement from 2 to 8. Reprinted with permission from Ref. 40, copyright (2016) American Chemical Society.

3. Optical Multi-Analyte Sensor In the past few decades, extensive interests have been drawn to the surface plasmon resonance (SPR) based optical sensing for various analytes ranging from chemicals to biochemicals. Surface plasmons (SP) are defined as inherent oscillations of free electrons

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at the boundaries between metal and dielectric, which are often divided into propagating surface plasmons (PSP) and localized surface plasmons (LSP) [42]. PSP could be excited on the metallic films via prism coupler, optical waveguides coupler, diffraction gratings, and optical fiber coupler [43,44], while LSP can be boosted on metallic nanoparticles. It is noted that both can produce a remarkable enhancement of electromagnetic field in the nearfield region, leading to extensive applications in surface enhanced Raman scattering (SERS), fluorescence enhancement (FE), refractive index (RI), biomolecular interaction detection, and etc. [45–47]. With the advent of nanotechnology, various nanostructures become the research frontier, where application of LSP as transduction signals becomes the focus of sensors or biosensors [48–52]. The operating principle of SPR based sensors relies on the localized surface plasmonic shift resulted from changes in dielectric environment of the vicinity of nanostructure upon exposure to various analytes. Many reports have pointed out that anisotropic nanostructures such as nanorod are inherently much more sensitive to the local refractive index perturbation desired for sensing [53,54]. Generally, the wavelength shift of the plasmonic peak of spherical particles is around 1~2 nm which is too small to be distinguished in practical detection, while anisotropic nanostructures demonstrate a plasmonic shift of more than 10 nm [55–57]. For instance, Tang et al. demonstrated a multiplexed Au nanorod (AuNR) array for multi-analyte analysis [58]. The AuNR arrays were synthesized by a seed-mediated chemical growth using cetyltrimethylammonium bromide (CTAB) and sodium oleate (NaOL) biosurfactants. As shown in the SEM image (Fig. 2(a)), the nanorod assembly is truly a monlayer with good dispersion over the substrate. The detections towards rabbit igG and human igG were carried out using AuNR biochip as shown in Figs. 2(b) and 2(c). The red shift of spectra shows a linear response to the analyte with sensitivities of 0.21 nm/nM towards rabbit DNA and 0.27 nm/nM towards rabbit and human igG, respectively. The responses at specific wavelengths of 630 nm and 840 nm were summarized in Figs. 2(d) and 2(e), in which the cross-sensitivities to dual analytes were effectively avoided by wavelength shift. Owing to the differences in volumes of analyte molecule and binding types between AuNR and igG, different wavelength-shift responses towards human/rabbit igG were demonstrated at 630 nm and 840 nm. Thus, the SPR based optical method can generally differentiate multiple analytes by identifying their plasmon wavelength and concentration information would be reflected by the wavelength shift due to the optical adsorption of biochemicals. For semi-transparent or opaque samples, optical fibers could be applied as surface carriers to assist investigating of nanoarrays’ optical properties. Additionally, the optical fiber structure could enhance the performance of the local surface plasmon resonance (LSPR) sensor [59,60]. Jiang et al. proposed a graphene/ITO nanorod based U-bent optical fiber LSPR sensor for DNA detection [61]. The graphene/ITO nanoarrays (Fig. 2(f)) were directly grown on the surface of U-bent optical fiber following the schematic as revealed in Fig. 2(g). Upon exposure to different analytes, the refractive index (RI) of the fiber would be significantly altered, leading to plasmon wavelength shift. In this work, noncomplementary (NC) DNA and full complementary (FC) DNA were applied as analytes

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to examine the multi-analyte detection capabilities. Obvious red shift was observed for FC DNA detection while no shift was identified in detecting NC DNA as revealed in Figs. 2(h) and 2(i). As no bonding was formed between probe DNA and NC DNA, the refractive

Fig. 2. (a) SEM image of gold nanorod biochip surface functionalized with antibody molecules. UV-vis absorption spectra monitoring wavelength shift towards (b) rabbit igG and (c) human igG detection with calibration lines in inset figures. 3D bar chart showing minimal cross-sensitivities of two analytes on Au nanorod arrays at (d) 630 nm and (e) 840 nm. Reprinted with permission from Ref. 58, copyright (2014) Elsevier B.V. (f) SEM image of as prepared graphene/ITO nanorod arrays. (g) Synthetic schematic of graphene/ITO U-bent fiber optical sensor. LSPR spectra of sensor after exposure to (h) NC-DNA and (i) FC-DNA. Summarized resonance wavelength shift versus analyte detection in (j) line chart and (k) bar chart. Reprinted with permission from Ref. 61, copyright (2019) by the authors. Licensee MDPI, Basel, Switzerland.

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index variation would be too weak to be distinguished. On the contrary, the accumulation of FC DNA around probe DNA provides linearly enhanced plasmon peak shift, as summarized in Figs. 2(j) and 2(k). 4. Impedance-Metric Multi-Analyte Sensor Another electrochemical detection approach besides the voltammetry mode is impedancemetric mode, which applies AC bias to binary sides of sensors [62]. Unlike the DC based amperometry and voltammetry sensing mode, the variation of dielectric properties is reflected in responses revealed as imaginary part of impedance and phase change [27]. Thus, the impedance spectroscopy is a useful technique to investigate and separate electrochemical responses of multi-analyte based on their frequency-dependent behavior. In AC bias domain, the sensing responses could be interpreted using a typical Randles Circuit [63]. The sensor-analyte interactions may have significant impact on dielectric properties’ alternation. For instance, the chemisorption of NO, NO2, and SO2 on metal oxide may induce the formation of nitrites, nitrates, and sulfates, respectively, leading to remarkable changes of dielectric properties revealed as giant responses in imaginary part of impedance. Moreover, the contributions of dielectric permittivity and electric conductance responses also vary with wavelength. Such a diverse frequency-dependent response behavior serves as the characteristic footprint for the multiple analytes to be detected.

Fig. 3. (a) SEM image of as prepared Pt-CeO2 nanowires. (b) Equivalent circuit of Pt-CeO2 nanowire-based impedance sensor. (c) Impedance response towards various gaseous analytes in the form of Bold Plot. Nyquist plots of impedance response towards (d) C3H8 and (e) CO. Reprinted with permission from Ref. 64, copyright (2013) Elsevier B.V.

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Lei et al. designed a Pt-CeO2 nanowire based impedance-metric gas sensor in harsh environment [64]. The metal-ceramic nanowires were prepared via a two-step procedure including electrospinning and a subsequent calcination process. The nanowires were uniform and well-distributed with an average diameter of around 177 nm as shown in Fig. 3(a). Fig. 3(b) presents the equivalent circuit model that characterizes the response upon exposure to gaseous analytes. The parallel element (R2//CPE1) represents the gas dependent interface, the major contribution to impedance response. The Bold plot in Fig. 3(c) demonstrates the response towards various reducing and oxidative gaseous analytes (i.e., CO, O2, SO2, and NO). However, the selectivity is insufficient to separate only based on impedance response even at the low frequency region. When expressed in Nyquist plot, Figs. 3(d) and 3(e) record the impedance response patterns in the frequency domain and C3H8 and CO can be easily differentiated. Owing to different surface reaction, the contribution of permittivity response and resistance response would be significantly different below 500 Hz, resulting in the characteristic sensing behavior in the impedance spectra. 5. Field-Effect Transistor (FET) Multi-Analyte Sensor The incorporation of FETs and nanoarrays in a sensor device has enabled a robust and feasible platform to achieve high current amplification and sustain an enhanced signal-tonoise ratio [65]. A typical FET-sensor has similar operating mechanism to the Metal– Oxide–Semiconductor Field-effect Transistors (MOSFETs), while its the gate is replaced by an electrolyte and an external voltage can be applied via a reference electrode [66]. For an n-channel FET sensor, the positive gate voltage will lead to the formation of a conductive channel under the interface region. On the contrary, the formation of conductive channel requires a negative gate voltage in a p-type FET sensor. Generally, FET-based sensor response results from variation in the electric field at the oxide surface due to analyte molecules binding to the surface [67]. The ultrahigh surface area and thin thickness of nanoarray based FET sensor may facilitate the analyte adsorption and complete depletion of conductive channel [68]. Hahn et al. reported an efficient ZnO nanorod array-based FET sensor for simultaneous detection of glucose, cholesterol, and urea [69]. As depicted in Fig. 4(a), the sensor structure adopts ZnO nanorod as the conduction pathway and the electrons yielded from the enzymatic reactions on the nanorod surface may transfer through to seed layer and subsequently to electrode. Fig. 4(b) illustrates the uniform deposition of as grown ZnO nanoarray on the patterned areas. The enzyme immobilization was conducted to divide three different analyte-sensitive areas and the existence of enzyme on ZnO nanorods was confirmed in the top view SEM image. Owing to the three distinct enzyme breakdown reactions, the variation of protonation state of ZnO nanorods may result in three characteristic ID-VG response patterns towards glucose, cholesterol, and urea as shown in Figs. 4(c) ~ 4(e), respectively. However, such a methodology heavily relies on the predoped enzymes, and detection capabilities are limited to the three known analytes with controlled interferences. To eliminate the limitation of enzyme categories in biosensing,

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Fig. 4. Caption on facing page

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Benkstein et al. incorporated the temperature control and gate control as the auxiliary detection approach [70]. As chemisorption is temperature activated process, the electrical properties of semiconducting sensing material are sensitive to variation of temperature and electrostatic gating conditions. As such, recording the sensing patterns in different temperatures and gating conditions would be an alternative approach to simultaneously differentiate multiple analytes. The FET configuration of Tin Oxide nanowire array is displayed in Fig. 4(f), which is composed of a micro hotplate and center-situated back-gate electrode installed on a silicon nitride membrane. The raw data as functions of temperature and gate voltage were recorded in Figs. 4(g) and 4(h). The subsequent data processing was carried out based on linear discriminant analysis (LDA) technique, which was mostly used to derive an optimal linear transform that mapped the measurements to a lowerdimensionality space on the basis of preservation of most data features [71]. The successful analyte classification was achieved in 3 dimensional scatter plots (Figs. 4(i) and 4(j)), where the LDA were carried out at gate bias Vgs = 0 V and -2.5, 0 V, respectively. As indicated by the bar chart summarizing the recognition rate (Fig. 4(k)), 98 % recognition rate is achieved on the basis of data-set recorded under -2.5 V, 0 V and 192 °C ~ 373 °C. 6. Multi-Modular Sensor The core concept of multi-analyte sensing on a single device is to develop promising modes which could provide multi-dimensional responses to build a unique footprint or signatures for different analytes. However, the increasing complexity of database may increase the cost or difficulty of device fabrication and deployment. For instance, the optical mode requires an external optic source to induce surface plasmon resonance and such methodology is limited in harsh environment. Additionally, sensor based on single mode including voltammetry, FET, or impedance usually is limited in analytes’ category and range. The auxiliary detection approaches such as temperature and gate controls are often required to extend their detection capabilities. As such, incorporating multiple sensing modes on a single device can provide a good solution to gain the balance of data-set complexity and cost. Gao et al. designed a bimodular ZnO nanoarray sensor for three different oxidative gases (i.e. NO2, SO2, and O2), and such methodology is proven effective in detecting reducing gas without using any auxiliary approach [27]. The device configuration of ZnO

Fig. 4. (a) The schematic configuration of ZnO nanorod FET biosensor with immobilized enzymes. (b) Top and lateral view SEM images of ZnO nanorod after and before enzyme immobilization. ID-VG responses of ZnO nanorod FET sensor with step-enhanced (c) glucose (0 ~ 75 mM), (d) cholesterol (0 ~ 55 mM), and (e) urea (0 ~ 40 mM) in 0.05 M PBS buffer. Reprinted with permission from Ref. 69, copyright (2015) the Royal Society of Chemistry. (f) Design of Tin Oxide nanowire FET sensor with micro hotplate. (g) Conductance response measured at 3 different temperatures at Vgs = 0 V. (h) Dynamic conductance taken at 5 different Vgs at 373 °C. LDA based scatter plot using raw data at (i) 194 °C, Vgs = 0 V and (j) 194 °C ~ 373 °C, Vgs = -2.5 V, 0 V, where color of dots represents the analyte species. Reprinted with permission from Ref. 70, copyright (2012) the Royal Society of Chemistry.

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nanoarray sensor is illustrated in Fig. 5(a) with a highly uniform ZnO nanowire array grown on interdigitated electrodes (Figs. 5(b) and 5(c)). The resistance-metric or impedance-metric responses are insufficient to differentiate three different analytes as their responses always have overlap in a wide detection range (from several ppm to 3%) as depicted in Figs. 5(d)~5(f). However, the impedance mode may reflect the alternation of dielectric permittivity while resistance only records the variation of frequency constant conductance, while the correlation between dual sensing modes is summarized in Fig. 5(h). As such, owing to different surface chemisorptions, the unique signature is established for NO2, SO2, and O2, respectively. With the assistance of Principal Component Analysis (PCA) and Machine Learning (ML) methods, the data-set was processed and projected on a 2D plane shown in Fig. 5(i), where the data points belonging to the same species aggregate to certain clusters, with the decision boundaries established for species recognition and prediction.

Fig. 5. (a) Schematic showing ZnO nanorod array bimodular sensor set-up. (b) low magnified and (c) enlarged SEM image depicting the ZnO nanorod arrays on interdigitated electrode region. (d) Conductance response in resistance-metric mode toward 2–500 ppm NO2, 5–500 ppm SO2, and 1000 ppm to 3 % O2. The corresponding electrochemical impedance spectra in the presence of (e) O2, (f) SO2, and (g) NO2 with different concentrations. The alternative current (AC) bias is set 0.2 V, with an operating frequency ranges from 1 Hertz to 1 Mega Hertz. (h) The Scheme showing relationship of resistance-metric mode and impedance-metric mode built in the single nanorod sensor. (i) Graphic pattern recognition of three different oxidative gaseous analytes and test points within or beyond the training-set. Reprint with permission from Ref. 27, copyright (2020) WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

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It is noted that multi-modular sensing strategies possess unprecedented advantages over single operating mode towards the complex sensing scenario. Firstly, the signature built by multimode sensor is more easily to be differentiated. As demonstrated in the IV curve extracted from voltammetry, FET mode, although the different chemical species could be distinguished by figuring out their characteristic response curves, the inevitable overlap and similarities still exist. Thus, the detection species and accuracy are significantly limited. Secondly, the target analytes and interference are always blended in the mixture, so the single operating mode would be insufficient to quantitively analyze the components. On the contrary, the multi-modular sensing strategies enable us to study the co-adsorption scenario in different modes and subsequently estimate the components’ concentrations sufficiently. 7. Conclusion In this review, we have surveyed the latest progress on the single nanoarray-based sensor for multi-analyte detection, including their design, operating principle, and the mechanism of differentiating multiple analytes individually in their mixture form. According to categories of transducing signals, the most extensively applied sensing strategies are voltammetry, surface plasmon resonance, field-effect transistor, and impedance-metric modes. In comparison to the amperometry mode, their multi-analyte detection capabilities originate from their characteristic response pattern dependent on wavelength, frequency, or potential, respectively. In addition to the merits offered by these sensing modes, the disadvantages are discussed in the higher deployment cost, limitation of analyte categories and concentration, and restriction in harsh environment. As such, integrating two or more sensing modes on a single device would be a promising strategy to gain the balance of low cost, simplified fabrication, wide detection window in both categories and concentration range in the development of future multi-functional sensors. To date, the development of multi-analyte detection and measurement in a laboratory setting is still mostly based on the supervised sensing with known target analyte or controlled interference. In many cases the analyte is introduced individually or with inert balance gas. However, in practice, analytes are often yielded in the form of mixture with several sensitive components or strong redox interferences to the deployed sensors. All of these components would contribute to the overall response, therefore the detection and measurement towards analytes mixture is still a highly challenging task. In this scenario, future sensor development needs more focus on studying the complex mixture adsorption including competitive adsorption and interaction among mixture components. Additionally, adding multi-analyte or mixture function into single device would inevitably increase the size and complexity of raw data-sets. Thus, various advanced data processing techniques and new scientific interpretations are expected in the near future to facilitate the automatic species recognition and concentration quantification. Extending forward for a global sensing scenario, various other sensing tasks and datasets can be fused together with the chemical sensing task and datasets here for a system sensing eventually, including both physical and chemical characteristic signatures.

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0009

A Novel Addressing Circuit for SWS-FET Based Multivalued Dynamic Random-Access Memory Array R. H. Gudlavalleti*, B. Saman†, R. Mays*, H. Salama*, Evan Heller‡, J. Chandy* and F. Jain*,§ *Department

of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA of Electrical Engineering, Taif University, Taif, Saudi Arabia ‡Synopsys Inc., Ossining NY, USA §[email protected]

†Department

Multivalued memory increases the bits-per-cell storage capacity over conventional one transistor (1T) MOS based dynamic random-access memory (DRAM) by storing more than two data signal levels in each unit memory cell. A spatial wavefunction switched (SWS) field effect transistor (FET) has two vertically stacked quantum-well/quantum-dot channels between the source and drain regions. The charge location in upper or lower quantum channel region is based on the input gate voltage. A multivalued DRAM that can store more than two bits-per-cell was implemented by using one SWSFET (1T) device and two capacitors (2C) connected to each source regions of the SWS-FET device. This paper proposes the architecture and design of peripheral circuitry that includes row/column address decoding and sensing circuit for a multivalued DRAM crossbar arrays. The SWS-FET device was modeled using analog behavioral modeling (ABM) with two transistors using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit schematic simulations are presented. A compact multivalued DRAM architecture presents a new paradigm in terms of application in Neural systems that demand storage of multiple valued levels. Keywords: multivalued; DRAM; memory addressing; peripheral circuitry; SWS-FET

1. Introduction Technology scaling has been conventional approach toward improving storage density and bandwidth for dynamic random-access memory (DRAM) memory [1]. Research work toward increasing memory density was done by increasing the number of bits per unit cell i.e., storing multivalued logic bits. In DRAMs, this means storing and consequently sensing multiple voltage levels on the cell capacitor. Methods for multilevel storing of the supply voltage onto a single capacitor using conventional MOS device as an access transistor in unit memory cell was demonstrated [2–5]. Alternatively, a multivalued DRAM based on spatial wavefunction (SWS) field effect transistor (FET) has been reported [6]. In this approach, a unit memory cell has one NMOS SWS-FET (1T) with two capacitors (2C) that can store multiple data bits. The SWS-FET has two quantum wells/dots as channel between the source and drain region. The charge location in the channel quantum wells/dots region §Corresponding

author.

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is determined by the input gate voltage. The data signal bits can be stored or retrieved from the capacitors connected to each source of the n-SWS-FET device by varying the input gate voltage above or below the threshold voltage pertaining to each channel region. Also, multivalued digital logic design based on the SWS-FET device architecture was also shown to increase the computation capability in the digital systems [7] and for distributed inmemory computing integrating with QD-NVRAMs [8]. This paper describes the architecture of the multivalued DRAM and proposes the peripheral circuitry that implements the address decoding and sensing for the memory array. In the next section, the architecture of multivalued DRAM cell array is presented. Section 3 presents the addressing scheme and details of the peripheral circuitry and Sec. 4 contains results and discussion that includes Cadence simulations and finally the conclusion. 2. Multivalued DRAM Architecture The multivalued DRAM architecture is shown in Fig. 1(a). The architecture consists of (i) the unit memory cell, peripheral circuits such as (ii) row/column decoder to address each memory cell, (iii) sense amplifier to amplify and restore it back to the cell, and (iv) timing and control logic (not shown in the figure) circuit. The details for each of the blocks are given below. 2.1. Unit memory cell The unit memory cell of the DRAM includes one SWS-FET (1T) and two capacitors (2C) as shown in Fig. 1(b) [6]. The SWS-FET device has upper and lower quantum-well/ quantum-dot channels (W1, W2) as the electron transport layer between source (S1, S2)

Fig. 1. Proposed multivalued DRAM Architecture and (inset) SWS-FET based unit DRAM memory cell.

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and drain (D1, D2), respectively. As the gate voltage is raised above the lower threshold (VthL), electrons appear in an n-SWS-FET in the lower quantum well (W2) and this inversion channel connects Source (S2) to drain (D2). As the gate voltage is increased above VthU, electrons transfer to the upper quantum well (W1) and now source (S1) and drain (D1) are connected electrically. The SWS-FET device structure and quantum simulations that show the electron transfer between the quantum wells with input gate voltage was reported in [9]. The digital logic bits are encoded based on the spatial location of the electrons in the channel region. The writing and reading of the multivalued digital logic bits ‘0’, ‘1’ and ‘2’ to the 1T2C SWS-FET DRAM unit memory cell (shown in Fig. 1(b)) can be performed by varying the input gate voltage i.e., wordline (WL) signal. Logic ‘0’ corresponds to ground (0 V), logic ‘1’ corresponds to 0.3 V, and logic ‘2’ corresponds to 0.9 V. When the input gate voltage i.e., wordline signal is above lower channel threshold voltage (VthL), a logic ‘0’ and logic ‘1’ can be stored/retrieved from capacitor (CS2). When wordline signal is above the threshold voltage of the upper channel, VthU, logic ‘0’, ‘1’ and ‘2’ can be stored/retrieved from capacitor (CS1). 2.2. Row/Column decoder The DRAM memory crossbar array architecture is shown in Fig. 1(a). Unlike conventional MOS based DRAM cell and its peripheral circuits [10], the SWS-FET based DRAM has one wordline (WL) signal to the access memory cell and two bitline line (BL1 and BL2) data signals to store or retrieve data signals. Each memory cell can be accessed using the row and column decoder that are addressed using external memory controller. The row decoder generates multivalued wordline data signal to the access transistor. The column decoder generates two bitline signals, BL1 and BL2. Two methods have been proposed for the implementation of row/column decoder logic circuit. Method I: The row line decoder logic circuit generates 2n output bits for n-input bit combinations. A 2-to-4 decoder logic circuit is shown in Fig. 2(a). In the proposed method, one of the X[1-4] bits goes high for each of the logic input bit combinations of ‘A’ and ‘B’ similar to conventional binary line-decoder circuit. Here, A and B are either logic ‘0’ or logic ‘2’ bits. An additional logic circuit represented by block ‘S’ (shown in Fig. 2(b)), decides the output as logic level ‘1’ or ‘2’ based on X[1-4] and C input bits. The same decoder logic can be used to implement column decoder. The inverter, NAND and NOR logic circuits used in the decoder are shown in Fig. 3. Here a n-SWS-FET only based logic circuit implementation is shown, however a complementary SWS-FET logic can be implemented [11]. Table I shows the truth table for row and column selection for a 4×4 array SWSFET DRAM. When WL is logic ‘0’, the SWS-FET is OFF or not active. To access all DRAMs in a particular row, corresponding WL needs to be activated. In this table, A and B are the input bits to the row decoder that are used to select each row of memory cell and third bit LR [row decoder] (or LC [column decoder]) is used to select lower well or upper well. Similar logic truth table can used for column decoder to select a memory column array.

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Fig. 2(a). Decoder.

Fig. 2(b). Schematic for Block ‘S’.

(a)

(b)

Fig. 3. Enhancement NMOS based (a) Nand (b) NOR and (c) Inverter.

Table I. Row decoder logic truth table A

B

D = LR or LC, for LR,C=Logic 1 or 2

0

0

D[L]

0

0

0

0

2

0

D[L]

0

0

2

0

0

0

D[L]

0

2

2

0

0

0

D[L]

(c)

Novel Addressing Circuit for SWS-FET based Multivalued DRAM Array

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Method II: Alternatively, a second method for row/column decoder logic circuit that is more advantageous compared to method I is proposed. The truth-table to address each row/ column of a 4×4 and 12×12 DRAM crossbar array is shown in the Tables II and III respectively. Table II shows the truth table with two input combination bits for a 4×4 memory array and Table III shows the truth table for 12×12 array for 3-input bits. For each input bit increase, the array size increases 9 times. For a 3-input conventional MOS based 1-T, 1-C DRAM the array size is 8×8. Therefore, an SWSFET has 2.25 times the conventional DRAM. Extrapolating for an 8-bit input, conventional MOS DRAM has an array of 256×256 and SWSFET DRAM has 2916×2916 array. Therefore, the storage density increases by 129 times for 8-bit at the cost of increased metal lines and complex logic implementation. Table II. Decoder logic: 2-input truth table: 4×4 array A

B

WL1

WL2

WL3

WL4

0

0

x

x

x

x

0

1

1

0

0

0

0

2

2

0

0

0

1

0

0

1

0

0

2

0

0

2

0

0

1

1

0

0

1

0

1

2

0

0

2

0

2

1

0

0

0

1

2

2

0

0

0

2

Table III. 3-input truth table: 12×12 array A

B

C

WL1

WL2

WL3

WL4

WL5

WL6

WL7

WL8

WL9

0

0

0

x

x

X

x

x

x

x

x

x

0

0

1

1

0

0

0

0

0

0

0

0

0

0

2

2

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

0

0

2

0

0

2

0

0

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

1

2

0

0

2

0

0

0

0

0

2

1

0

0

0

1

0

0

0

0

2

2

0

0

0

2

0

0

1

0

1

0

0

0

0

1

0

1

0

2

0

0

0

0

2

1

1

0

0

0

0

0

0

1

2

0

0

0

0

0

0

WL10

WL11

WL12

x

x

x

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

2

0

0

0

0

0

0

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R. H. Gudlavalleti et al. Table III. (Continued )

A

B

C

WL1

WL2

WL3

WL4

WL5

WL6

WL7

WL8

WL9

WL10

WL11

WL12

1

1

1

0

0

0

0

0

0

1

0

0

0

0

0

1

1

2

0

0

0

0

0

0

2

0

0

0

0

0

1

2

1

0

0

0

0

0

0

0

1

0

0

0

0

1

2

2

0

0

0

0

0

0

0

2

0

0

0

0

2

0

1

0

0

0

0

0

0

0

0

1

0

0

0

2

0

2

0

0

0

0

0

0

0

0

2

0

0

0

2

1

0

0

0

0

0

0

0

0

0

0

1

0

0

2

2

0

0

0

0

0

0

0

0

0

0

2

0

0

2

1

1

0

0

0

0

0

0

0

0

0

0

1

0

2

1

2

0

0

0

0

0

0

0

0

0

0

2

0

2

2

1

0

0

0

0

0

0

0

0

0

0

0

1

2

2

2

0

0

0

0

0

0

0

0

0

0

0

2

2.3. Sense amplifier A binary sense amplifier is a fully differential amplifier that consists of two back-to-back inverters connecting two adjacent bitlines, BL and 𝐵𝐿. Before sensing, both inverters are detached from the power supply and precharged on both ends to half of the bitline voltage. In this mode, the inverters do not perform the inversion. A read begins by raising a wordline to VDD (or boosted VDD), allowing the stored charge to be shared with the bitline. This charge sharing creates an imbalance between the voltage levels of BL and 𝐵𝐿. The sense amplifier detects this imbalance and amplifies it to recreate the original data and to restore it back to the cell. In the current SWS-FET based architecture, the sense amplifier is connected to each of the BL output with one sense amplifier connected between 0 V and

Fig. 4(a). Sense amplifier.

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Fig. 4(b). Schematic simulation of clocked sense amplifier using n-SWS-FET.

0.3V; and the other connected between 0 V and 0.6 V power supplies. The EN is selected corresponding to the supply voltages required to be regenerated. Figure 4(b) is the simulation output of the sense amplifier circuit. Initially, the data placed on BL (half of logic ‘2’ data voltage level) is transferred to cross-coupled inverter DATA and 𝐷𝐴𝑇𝐴 by enabling SW and disabling EN. When SW goes low and EN is high, sense amplifier restores the logic ‘0’ and logic ‘2’ levels. The sense amplifier uses n-SWSFET inverter therefore the high output goes VDD-Vth. However, for a complementary SWSFET inverterbased design [12] the output can be restored to VDD level. 2.4. Timing and logic circuit An external memory controller asserts row-address strobe (RAS), each time address bits placed on the address bus. The address bits are buffer by row-address buffer and then sent to row-address decoder. Similarly, the address bits are sent to column-address decoder. The row address decoder then accepts the address bits and selects of the large rows of storage cells. The data values contained in the selected row of storage cells are then sensed and kept active by the array of sense amplifiers. The column address bits decoded to select one column out of large array columns. The data for that column is then placed onto the data bus or overwritten with data from the data bus depending on the write enable (WE) signal. 3. SWS-FET ABM Model The SWS-FET was modeled using two conventional FET devices and an analog behavioral model (ABM). The ABM model is represented by an equation that implements the output voltage variations corresponding to the upper and lower quantum well/quantum dot

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threshold voltage variations for the input gate voltage. The circuit model of a SWS-FET was developed using Berkeley short channel IGFET model (BSIM3), and the simulations are done in Cadence. The schematic symbol for the SWS-FET is shown in Fig. 5(a). As shown in the ID-VG characteristics in Fig. 5(b), the current in the lower well (W2) increases when gate voltage, VG is greater than Vth1 and current in upper well (W1) increases for gate voltage VG is greater than Vth2 but, the current in lower well W1 is reduced.

(a)

(b) Fig. 5. SWS-FET (a) ABM Model (b) SWS-FET IDS-VGS characteristics.

Figure 6 shows the write and read operation for the DRAM cell. The top panel (green line) represents the input gate (WL) voltage for two input voltage levels, the red line and blue line represents the two bitline BL1 and BL2 respectively. The yellow line shows the write and read from the upper well connected to capacitor CS2 and pink line in the bottom panel shows write and read write and read from the lower well connected to capacitor CS1.

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Fig. 6. The simulation of CMOS DRAM & 2Bit SWSFET DRAM [6].

4. Conclusion In conclusion, this paper presents an architecture for the multivalued SWS-FET DRAM memory. Two methods are presented to decode the row/column memory address. The second method for the decoding logic can drastically increase the storage density for the SWS-FET DRAM memory array. Neural systems demand storage of multiple valued levels in application such as neural networks, and a compact multivalued DRAM architecture presents a new paradigm. Acknowledgments This work is based on SWS-FET and quantum dot FET foundation laid by the support of completed grants including Office of Naval Research contracts (N00014-02-1-0883 and N00014-06-1-0016), and National Science Foundation grants (NER and ECS 0622068). References 1. S. Lee, Technology scaling challenges and opportunities of memory devices, 2016 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA. 2. T. Okuda and T. Murotani, A four-level storage 4-Gb DRAM, IEEE Journal of Solid-State Circuits, 32, pp. 1743–1747, 1997.

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3. J. C. Koob, S. A. Ung, B. F. Cockburn and D. G. Elliott, Design and characterization of a multilevel DRAM, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 19, pp. 1583–1596, 2011. 4. M. Aoki, Y. Nakagome, M. Horiguchi, S. Ikenaga and K. Shimohigashi, A 16-levels/cell dynamic memory, 1985 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, New York, NY, USA, 1985. 5. P. Gillingham, A sense and restore technique for multilevel DRAM, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43, pp. 483– 486, 1996. 6. H. Salama, B. Saman, E. Heller, R. H. Gudlavalleti, R. Mays and F. Jain, Twin drain quantum well/quantum dot channel spatial wavefunction switched (SWS) FETs for multi-valued logic and compact DRAMs, International Journal of High Speed Electronics and Systems, 27, 1840024, 2019. 7. F. Jain, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Multi-Bit SRAMs, registers, and logic using quantum well channel SWS-FETs for low-power, high-speed computing, International Journal of High Speed Electronics and Systems, 27, 1840020, 2018. 8. F. Jain, R. H. Gudlavalleti, R. Mays, B. Saman, P. Y. Chan, J. Chandy, M. Lingalugari and E. Heller, Integration of quantum dot gate (QDG) in SWS-FETs for multi-bit logic and QD-NVRAMs for distributed In-Memory computing, International Journal of High Speed Electronics and Systems, 28, 1940018, 2019. 9. F. Jain, B. Saman, R. Gudlavalleti, J. Chandy and E. Heller, Multi-state 2-Bit CMOS logic using n- and p-quantum well channel spatial wavefunction switched (SWS) FETs, International Journal of High Speed Electronics and Systems, 27, 1840020-1, 2018. 10. R. C. Foss and R. Harland, Peripheral circuits for one-transistor cell MOS RAM’s, IEEE Journal of Solid-State Circuits, 10, 255–261, 1975. 11. B. Saman, P. Mirdha, M. Lingalugari, P. Gogna, F. C. Jain, E-S. Hasaneen and E. Heller, Logic gates design and simulation using spatial wave-function switched (SWS) FETs, International Journal of High Speed Electronics and Systems, 24, 03&04, 2015. 12. F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Low-threshold II–VI lattice-matched SWS-FETs for multivalued low-power logic, Journal of Electronic Materials 50, 2618–2629, 2021.

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0010

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory R. H. Gudlavalleti*, B. Saman*,†, R. Mays*, Evan Heller ‡, J. Chandy* and F. Jain*,§ *Department

of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA of Electrical Engineering, Taif University, Taif, Saudi Arabia ‡Synopsys Inc., Ossining NY, USA §[email protected]

†Department

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented. Keywords: multivalued circuits; spatial wavefunction switching; SWS; SRAM; peripheral circuitry; addressing; SRAM-based in-memory computing

1. Introduction We recently reported a 2-bit SRAM cell using cross-coupled SWS-CMOS inverters [1,2], where two conventional n-MOS transistors were used as access FETs. This paper present replacement of two conventional n-MOS access transistors by single two-channel SWSFET to control the access to the storage cell during read and write operations. This results in further reduction in area of novel 2-bit SRAM cells. The use of two-channel SWS-FET has been proposed in a companion paper [3] for addressing 2-bit DRAM. Increasing demand for on-chip memory and rapid advancements of machine learning and artificial intelligence, reducing the delay and energy associated in accessing memory would improve efficiency [4,5]. Also, by increasing bit-per-cell storage the performance can be further improved. Spatial wavefunction switched (SWS) field effect transistor (FET) based design was shown to perform multivalued logic computation, [4] and storage in memories [6–8]. This approach increases computation capability in digital systems and §Corresponding

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storage density in memory arrays respectively compared to conventional CMOS based designs. A spatial wavefunction switched (SWS) field effect transistor (FET) is a multithreshold device due to vertically stacked two-quantum well/quantum dot channels in the gate region. The charge locations in the upper or lower quantum-wells/-dots in the channel region is based on the input gate voltage. This property of the device allows to encode logic levels at each threshold level of the device. This paper also presents the peripheral circuitry for multivalued SRAM cell reported in [2]. In the next section, an overview of the system architecture for multivalued-SRAM cell array is presented. Section 3 presents the proposed SRAM unit and peripheral circuitry. Section 4 presents with the results and discussion that includes SWSFET device model, Cadence simulation and finally the conclusion. 2. System Overview The memory architecture for a conventional six transistor (6T) based SRAM crossbar array cells is shown in Fig. 1 [9]. The architecture consists (i) unit memory cell, peripheral circuits such as (ii) row/column decoder to address each memory cell, (iii) sense amplifier to amplify, and restore it back to the cell, and timing and control logic (not shown in the figure) circuit. The row/column decoder generate signals to activate each row and column cells corresponding to the input address bits. The row-selected word line connects one row of data cells to their bit-line columns. Meanwhile, one column-selected sense amplifier is connected to the data bus based on the column address. The sense amplifier sends differential data signals and amplifies the differential bit-line data to full rail-to-rail values before sending onto the bus. The timing and control logic synchronizes the read/write and store operations. The architecture (shown in Fig. 1) is implemented for SWS-CMOS inverter-based SRAM array. However, each of the addressing and peripheral circuits are implemented using Complementary SWSFET (C-SWSFET) to read/write quaternary logic states. The details for each of the blocks are discussed in following sections.

Fig. 1. Conventional SRAM architecture.

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2.1. SWS-CMOS inverter-based SRAM unit cell The conventional six-transistor (6T) SRAM cell consists of two cross-coupled inverters and two word-line-activated pass transistors connected to complementary bitlines. As shown in Fig. 2(a) [2], the SRAM cell consists of SWS-CMOS inverters as the crosscoupled pair that can store multiple supply levels encoded as logic bits. In this paper, quaternary logic states ‘1’- ‘4’ are stored in the memory cell corresponding to 0 V, 0.4 V, 0.8 V and 1.2 V voltage signals, respectively. Figure 2(b) shows the symbolic representation of CMOS-SWS cross-coupled inverters with two-access transistors MN5, MN6. The simulation results are shown in Fig. 2(c). When wordline (WL) signal (green solid line) goes high, the corresponding bitline (BL) (violet solid line) and 𝑏𝚤𝑡𝑙𝚤𝑛𝑒 (𝐵𝐿

(a)

(b)

(c) Fig. 2. (a) Circuit schematic of CMOS spatial wavefunction switching (SWS)-Static Random-Access Memory (SRAM) unit cell. (b) Symbolic representation of SWS-CMOS cross-coupled inverter with two-access transistors MN1, MN2. (c) DATA (top panel), write pulse (middle panel), and stored DATA bar (bottom panel).

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orange solid line signal is transferred to the SRAM DATA (solid light red color) and 𝐷𝐴𝑇𝐴 (solid dark red color) respectively. 2.2. SWS-CMOS inverter-based SRAM cell using single two-channel access-transistor In the proposed SWS-CMOS inverter based SRAM unit cell shown in Fig. 3(a), a single n-SWSFET access transistor to activate memory cell for read/writing bits onto the memory cell. This five transistor (5T) C-SWSFET reduces the cell area and increases the number of the bits stored per unit cell. As shown in Fig. 3(b), when input voltage of the access transistor i.e., the wordline voltage WL > VthU, the upper well of the n-SWSFET is selected and the data bits corresponding to 0 V, 0.4 V and 0.8 V can be read/write similar to the

(a)

(b)

(c)

Fig. 3. Proposed circuit schematic of CMOS SWSFET based SRAM unit cell in with single n-SWSFET access transistor in (a), Operation when (b) WL > VthL and (c) WL > VthU.

Fig. 3(d). Schematic simulations of one n-SWSFET access transistor based SRAM unit given in Fig. 3(a).

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cell in Fig. 3(b) shown in Sec. 2.1. When wordline voltage WL > VthL, the lower well of the n-SWSFET is selected and first two logic states ‘1’,‘2’ can be accessed separately as shown in Fig. 3(c). The simulation results show the output transition on data stored in cell connected to lower channel (DATA_L) and upper channel (DATA_U) when wordline (WL) voltage, V(WL) > VthU and VthL > V(WL) > VthU respectively, in top panel of Fig. 3(d). 3. Addressing and Peripheral Circuitry 3.1. SWS-FET based Row/Column decoder The C-SWSFET dynamic based NOR and NAND logic decoder circuits are shown in Figs. 4(a) and 4(b) respectively. In the C-SWSFET based dynamic NOR logic decoder for a 2-input, 4-output array, A0 and A1 are the input address selection bits for the memory. The input ‘ϕ’ signal either selects upper or lower channel of the p-SWSFET and A0, A1 signal generates the quaternary logic state to select one of the corresponding wordline, WL[1-4] bits.

Fig. 4(a). Dynamic NOR logic-based CMOS-SWS decoder.

Fig. 4(b). Dynamic NOR logic-based CMOS-SWS decoder.

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R. H. Gudlavalleti et al. Table I. Truth table for row decoder (when ϕ is low) for array using memory cell in Fig. 2(a). A0

A1

WL0

WL1

WL2

WL3

0

0

3

0

0

0

0

3

0

3

0

0

3

0

0

0

3

0

3

3

0

0

0

3

Table II. Truth table for Column decoder (when ϕ is low) for array using memory cell in Fig. 2(a). A

B

0

0

B[L] = Logic [1-4] to be stored or retrieved from Bitline (BL) B[L]

0

0

3

0

3

0

0

3

3

0

0

0

B[L]

0

0

0

B[L]

0

0

0

B[L]

Tables I and II show the truth table for row and column decoder circuit. The decoding logic circuit for row and column decoder is similar. However, an additional transistor that acts as a switch is added at each output of the dynamic NOR column decoder, that allows one of the logic input bits [0-3], to be written or retrieved on to/from the bitline (BL) data respectively. Similarly, the dynamic NAND based decoder can also be implemented as shown in Fig. 5 and truth table for the C-SWSFET dynamic NAND based row decoder logic is given in Table III.

Fig. 5. Dynamic NOR logic-based CMOS-SWS decoder. Table III. Truth table for row decoder (when ϕ is low) for array using memory cell in Fig. 2(a). A0

A1

WL0

WL1

WL2

WL3

0

0

0

3

3

3

0

3

3

0

3

3

3

0

3

3

0

3

3

3

3

3

3

0

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The column decoder circuit for C-SWSFET based SRAM cell in Fig. 3(a) is similar to column decoder for C-SWSFET SRAM cell in Fig. 2(a). However, the row decoder needs to generate Logic ‘2’ and Logic ‘3’ level for wordline input. The column decoder in Fig. 4(a) is used for row-decoder, but B[L] will be either Logic ‘2’ or Logic ‘3’. 3.2. C-SWSFET sense amplifier The sense-amplifier circuit for each column of the memory array is shown in Fig. 6. This topology utilizes a back-to-back SWS-CMOS based inverter for regeneration, where the coupled nodes are driven by BL/ 𝐵𝐿. Before sensing, both inverters are detached from the power supply by turning on SW and pre-charged on both ends corresponding to the voltage states. In this mode, the inverters do not perform the inversion. When SW is turnoff and EN, 𝐸𝑁, the imbalance causes the circuit to latch to either VDD1/VDD2 and VSS1/VSS2 depending upon the EN/𝐸𝑁 voltage levels. Figures 6(a) and 6(b) show the schematic simulation showing data restore to 0 V/1.2 V and 0.4 V/0.8 V in sense amplifier when SW is turn-off, EN is turn-on from 0 V to 1.2 V and 0 V to 0.8 V respectively. 4. ABM Model of SWSFET The circuit model of a SWSFET was developed using Berkeley short channel IGFET model (BSIM 3), and the simulations are done using Cadence. In the Cadence simulator, the SWSFET channels are represented by two conventional transistors with each one having a different threshold voltage which is characteristic of a SWSFET.

Fig. 6(a). C-SWS-FET based sense amplifier.

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Fig. 6(b). Schematic simulation showing data restore to 0V and 1.2V in sense amplifier when EN is turn-on (toggled from 0V to 1.2V) and SW is turn-off.

Fig. 6(c). Schematic simulation showing data restore to 0V and 1.2V in sense amplifier when EN is turn-on (toggled from 0V to 0.8V) and SW is turn-off.

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(a)

(b) Fig. 7. SWSFET (a) ABM Model symbol for n-SWSFET (b) n-SWSFET and p-SWSFET IDS-VGS characteristics.

The schematic symbol for the SWS-FET is shown in Fig. 7(a) and ID-VG characteristics for n-SWS-FET (dotted yellow, solid blue line) and p-SWS-FET (dotted red line, solid green line) are given in Fig. 7(b). For n-SWS-FET, the current in the lower well (W2) increases when gate voltage, VG is greater than Vth1 and current in upper well (W1) increases for gate voltage VG is greater than Vth2 but, the current in lower well W1 is reduced. Similar characteristics can be seen for p-SWS-FET but the gate to source polarity is reversed. 5. Conclusion Novel addressing, using one two-channel SWS-FET as an access transistor is presented to address 2-bit SRAM cells based on CMOS-SWS inverters. This SRAM cell reduces the

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cell area with more bit storage per cell. We have also presented CMOS-SWS based peripherical circuits and addressing scheme to read/write data bits to the memory cell reported in [8]. Artificial intelligence and machine learning applications demand multiple valued storage levels in application such as neural networks, a multivalued static randomaccess memory (SRAM) can increase the memory density by increasing the bits-per-cell store capacity. Acknowledgment This work is based on SWS-FET and quantum dot FET foundation laid by the support of completed grants including Office of Naval Research contracts (N00014-02-1-0883 and N00014-06-1-0016), and National Science Foundation grants (NER and ECS 0622068). References 1. F. Jain, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Multibit SRAMs, registers, and logic using quantum well channel SWS-FETs for low-power, high-speed computing, International Journal of High Speed Electronics and Systems, 28, 1940024, 2019. 2. F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Low-threshold II–VI lattice-matched SWSFETs for multivalued low-power logic, Journal of Electronic Materials, 50, 2618–2629, 2021. 3. R. H. Gudlavalleti, B. Saman, R. Mays, H. Salama, E. Heller, J. Chandy and F. Jain, A novel addressing circuit for SWS-FET based multi-valued dynamic random access memory array, International Journal of High Speed Electronics and Systems, 29, 2040009 (2020). 4. J. Zhang, Z. Wang and N. Verma, In-memory computation of a machine learning classifier in a standard 6T SRAM array, IEEE Journal of Solid-State Circuits, 52, 915–924, 2017. 5. S. Yin, Z. Jiang, J. Seo and M. Seok, XNOR-SRAM: In-memory computing SRAM macro for binary/ternary deep neural networks, IEEE Journal of Solid-State Circuits, 55, 1733–1743, 2020. 6. F. Jain, R. H. Gudlavalleti, R. Mays, B. Saman, P. Y. Chan, J. Chandy, M. Lingalugari and E. Heller, Integration of quantum dot gate (QDG) in SWSFETs for multi-bit logic and QD-NVRAMs for distributed in-memory computing, International Journal of High Speed Electronics and Systems, 28, 1940018, 2019. 7. F. Jain, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Multi-bit SRAMs, registers, and logic using quantum well channel SWSFETs for low-power, high-speed computing, International Journal of High Speed Electronics and Systems, 27, 1840020, 2018. 8. M. Lingalugari, P. Mirdha, J. Chandy, E. Heller and F. Jain, QD floating gate NVRAM using QD channel for faster erasing, Electronics Letters, 54, 36, 2018. 9. N. H. E. Weste and D. Harris, CMOS VLSI Design A Circuits and Systems Perspective, MA, Reading: Addison-Wesley, 2005.

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0011

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL) F. Jain*,§, B. Saman*,†, R. H. Gudlavalleti*, R. Mays*, J. Chandy* and Evan Heller‡ *Department

of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA of Electrical Engineering, Taif University, Taif, Saudi Arabia ‡Synopsys Inc., Ossining NY, USA §[email protected]

†Department

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several twochannel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM). Keywords: QD-FETs; two-bit logic; SWSFET; QD-SWS-FET; QDSL

1. Introduction The spatial wavefunction switched field-effect transistor (SWS-FET) has two or more vertically stacked quantum well or quantum dot channels, and the location of electrons in lower, upper, both and none encodes the logic states (01), (10), (11) and (00), respectively [1]. The current in a SWS-FET is routed between source and drain according to the magnitude of the applied gate voltage, which selects the channel. This provides a 4-state/ 2-bit FET operation. The variation of drain voltage provides an additional mechanism to produce additional states similar to a QDC-FET [2]. Figure 1(a) illustrates an n-channel SiGe-Si SWS-FET structure (Si well and SiGe barrier) and a p-channel SiGe-Si SWS-FET structure (SiGe well for holes and Si barrier) [3,4]. Simulations are shown in Figs. 1(b) and 1(c) for n-FET. At Vg = 0.2V, the electrons are in Si quantum well W2 (Fig. 1(b)), and as the gate voltage is increased to 0.8V, the wavefunctions are transferred to the upper Si well W1 (Fig. 1(c)). Parameters used in §Corresponding

author. 103

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simulation are listed in Table I. Unlike other SWS-FET, here the gate insulator is a latticematched ZnS/ZnMgS/ZnMgSSe quantum well barrier stack.

Fig. 1(a). Cross-section of SWS-CMOS inverter using Si well and SiGe barrier for n-FET and SiGe well and Si barrier for p-FET.

Fig. 1(b). Electron wavefunctions are confined to lower quantum well W2 at Vg = 0.2V.

Fig. 1(c). Electron wavefunctions transferred to upper well W1 at Vg = 0.8V.

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)

Fig. 1(d). Hole wavefunctions in the upper SiGe well W1 at Vg = -0.8V.

Fig. 1(e). Hole wavefunctions transferred to lower SiGe well W2 at Vg = -0.4V.

Table I. n-Si Channel/SiGe Barrier (Type II) SWS-FET Structure Layer ZnS

 (eV)

Eg (eV)

me

mh

r

Nd (cm-3)

Na (cm-3)

0.0025

3.5

3.80

0.13

0.38

8.0

0.00E+00

0.00E+00

*

0.0025

4.15

1.04

0.19

0.49

11.9

0.00E+00

0.00E+00

SiGe(.5)

0.0015

4.0

0.89

0.13

0.38

14

0.00E+00

0.00E+00

*

0.0050

4.15

1.04

0.19

0.49

11.9

0.00E+00

0.00E+00

Si QW1

Si QW2

*

Thickness m

SiGe(.5)

0.0100

4.0

0.89

0.13

0.38

14

0.00E+00

0.00E+00

SiGe(.75)

0.0500

3.9

1.05

0.13

0.38

14

0.00E+00

1.00E+16

Si

0.1000

3.8

1.1

0.19

0.49

11.9

0.00E+00

1.00E+16

QWs are tensile strained

105

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Figures 1(d) and 1(e) show simulation for p-FET and parameter are similar as in Table I except for the substrate doping is n-type. In n-FET SWS structures electrons are confined in Si wells and SiGe layers serve as barriers on p-Si substrates. However, in the case of SWS p-FET structures holes are confined in SiGe wells and Si layers serve as barriers on n-Si substrates. Figure 1(d) shows hole wavefunctions are in the upper SiGe well W1 at Vg=-0.8V and transfer to lower SiGe well W2 as the gate voltage is Vg=-2V. These SWSFETs can be configured as quantum wire channels if the gate width is in 8–9nm range. Quantum dot channel (QDC) SWS-FETs exhibiting transfer of electrons and change in current in a twin drain device is illustrated in Fig. 2(a). This fabricated FET incorporated two channels (QD-1and QD-2) each comprising two layers of SiOx cladded Si quantum dots. Each channel is accessed by their dedicated drains D1 (shallow) and D2 (deep). The

Fig. 2(a). Two SiO2 cladded Si quantum dot channels or superlattice (QDSL) channels in twin-drain configuration.

Fig. 2(b). Drain current - voltage (ID-VD) characteristics showing currents in deep drain (D2) and shallow D1 drain as a function of gate voltage VG.

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ID-VD characteristics showing electron transfer from QD-2 (deep drain D2) to QD-1 (shallow drain D1) is shown in Fig. 2(b) in an experimentally fabricated SWS-FET [1]. This 1D-confined QD SWS-FET exhibits 4-states. Quantum dot channels are also called quantum dot superlattice (QDSL) channels as electron wavefunctions in adjacent dots overlap due to the thin (1–2nm) SiOx/SiO2 barrier. The incorporation of quantum dot layers in the gate region enables the formation of QDG-FETs. Quantum dot gate (QDG) FETs are reported using Si or [5], which exhibit intermediate states in the ID-VG characteristics by varying the threshold voltage as the gate voltage is increased. This is due to transfer of electrons from the QD channel(s) to the gate QD layers. Thus, the integration of quantum dot in a SWS structure opens another way of achieving higher number of states (e.g. 8-states) and 3-bit operation. 2. 2-D Confined QD-FETs The use of GeOx-cladded Ge quantum dot layers between Si source and drain regions, provide carrier confinement along the channel length in SWS quantum dot channel (QDC) FET configuration. Another approach is to incorporate two GeOx cladded Ge quantum dot superlattice (QDSL) channels without Si0.5Ge0.5 well and a Si0.75 Ge0.25 buffer. Figure 3(a) shows a cross-sectional (top) and 3-D view (bottom) of a 2-D confined p-FET using Ge QD channels between p+ source and drains. Here, n-Si layer is thin and it permits selfassembly of GeOx cladded Ge quantum dot superlattice (QDSL) channels. Figure 3(b) shows the simulations. Here, each channel comprises 2 layer QDSL. Figure 3(b1) illustrates holes in upper QD layer and Fig. 3(b2) shows holes in the lower QD layer. Simulation parameters are listed in Table II. The gate voltage magnitudes can be adjusted by adjusting the gate electrode material affinity. Figure 4(a) shows the QD n-SWS-FET structure. Here, Top figure shows the crosssection and Bottom figure illustrates a twin-drain 3-D schematically. The simulation of electron wavefunctions in the lower QD-2 channel are shown in Fig. 4(b1). Following the transfer, as Vg is increased, the wavefunctions in the upper QD-1 channel are shown in Fig. 4(b2). Table III lists the parameters used in simulation.

Fig. 3(a). Cross-section (left) SWS p-FET using two Ge QD layers in twin drain format (drain D1 is not shown), (right) 3-D view of 2-D confined p-FET using Ge QD channels.

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Fig. 3(b1). Hole wavefunctions in the upper Ge quantum dot channel QD-1.

Fig. 3(b2). Hole wavefunctions transferred to the lower Ge quantum dot channel QD-2. Table II. GeOx-Ge QDs on Si SWS p-MOS Structure (** variable) Layer

Thick (m)

 (eV)

Eg (eV)

mh

me

r

Nd (cm-3)

Na (cm-3)

HfO2

0.0025

1.75*

5.8

0.13

0.08

19.0

0.00e+00

0.00e+00

GeOx

0.0010

2.25

5.70

0.16

0.16

4.4

0.00e+00

0.00e+00

Ge – QD1

0.0030**

4.55

0.67

0.28

0.08

16.0

0.00e+00

0.00e+00

GeOx

0.0020

2.25

5.70

0.16

0.16

4.4

0.00e+00

0.00e+00

Ge – QD2

0.0030**

4.55

0.67

0.28

0.08

16.0

0.00e+00

0.00e+00

GeOx

0.0010

2.25

5.70

0.16

0.16

4.4

0.00e+00

0.00e+00

Si

0.0040

3.8

1.1

0.49

0.19

11.9

1.00e+16

0.00e+00

Si

0.1000

3.8

1.1

0.49

0.19

11.9

0.00e+00

4.00e+16

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)

Fig. 4(a). 3D confined n-SWS QDFET using two Ge QDSL channels between n+ source and drains.

Fig. 4(b1). Electron wavefunctions are in the lower Ge quantum dot channel QD-2.

Fig. 4(b2). Electron wavefunctions transferred to the upper Ge quantum dot channel QD-1. Fig. 4(b). Simulations showing electron wavefunction transfer.

109

110

F. Jain et al. Table III. GeOx/Ge QDs on Si SWS n-MOS Structure (** variable) Layer

Thick (m)

 (eV)

Eg (eV)

mh

me

r

Nd (cm-3)

Na (cm-3)

HfO2

0.0025

1.75*

5.8

0.13

0.08

19.0

0.00e+00

0.00e+00

GeOx

0.0010

2.25

5.70

0.16

0.16

4.4

0.00e+00

0.00e+00

Ge – QD1

0.0030**

4.55

0.67

0.28

0.08

16.0

0.00e+00

0.00e+00

GeOx

0.0020

2.25

5.70

0.16

0.16

4.4

0.00e+00

0.00e+00

Ge – QD2

0.0030**

4.55

0.67

0.28

0.08

16.0

0.00e+00

0.00e+00

GeOx

0.0010

2.25

5.70

0.16

0.16

4.4

0.00e+00

0.00e+00

Si

0.0040

3.8

1.1

0.49

0.19

11.9

1.00e+16

0.00e+00

Si

0.1000

3.8

1.1

0.49

0.19

11.9

0.00e+00

4.00e+16

3. 3-D Confined QD-FETs Limiting the channel width W to 7-9nm in Ge QD channel SWS-FETs provides 3-D confinement. This is shown in Fig. 5(a), where both channels are shown with their respective source and drain. That is, we now have four layers of QDs forming two quantum do channels hosting electrons in 6-7nm inversion layer, 7-9nm width (W) and 7-9 nm channel length L. Si source (S1 and S2) and drains (D1 and D2) provide natural band offsets to confine carriers along the channel. Conventional quantum confinement in 3-D leads to quantum dot FETs, single electron transistors (SETs), and quantum cell automata (QCA) devices. All of these are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. Compare this with a single electron transistor or quantum dot FET hosting few electrons. Kastner [6] reported quantum dot transistors, and this was followed by Kummamuru et al. [7] quantum-dot cellular automata (QCA) latches and shift registers operating at milli-Kelvin. Nanostructures QCA has been predicted to operate at room temperature. 3-D confined Ge QD channel SWS-FET with channel length 7-9nm (between Si source and drain) and width 7-9 nm operate at room temperature FET. This is due to the unique property of self-assembled GeOx cladded Ge array (e.g. 3×3×3 dots) forming a quantum dot superlattice (QDSL). The density of states (DOS) in conduction and valence sub-bands of QDSL, which are separated by 0.1-0.3eV with a very narrow energy width (1-2 meV) of sub-bands has been modeled [2] using modified Kronig-Penney model. In comparison to single electron transistors or elements of quantum dot cellular automata (QCA), the proposed QD-FET has over 27 electrons (one electron per dot). There is no fan-out issue in logic gates. In addition, the states are 16 or more providing 4-bit operation at room temperature. Another feature of SWS-FETs is their adaptability to wraparound FIN-FET configuration as reported elsewhere [4]. Experimentally fabricated long-channel Ge QD FET with HfO2 gate insulator has been reported [4] and results are shown in Fig. 5(b). The simulation of current transport in a

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3-Ge QD layer FET is shown in Fig. 5(c). This simulation shows an intermediate state just from the QDSL, which combines 3-GeOx cladded Ge quantum dot layers. A 3-D confined 7nm channel shown in Fig. 5(a) is expected to result in many more states. Figures 5(d1) and 5(d2) show simulation of wavefunctions locations as a function of gate voltage.

Fig. 5(a). 3-D confined QD n-SWS-FET with 7-9nm gate width (W) and channel length (L).

Fig. 5(b). Experimental ID-VG characteristics.

Fig. 5(d1). Wavefunctions in QD-3, Vg=0.1V.

Fig. 5(c). Simulated ID-VG characteristics for a three layer Ge QDC FET with Si source and drain.

Fig. 5(d2). Wavefunctions in QD-1, Vg=0.4V.

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Figure 5(d1) shows the electron wavefunctions in lowest quantum dot layer QD-3 at Vg = 0.1V and Fig. 5(d2) shows wavefunctions transfer to the top QD-1 when Vg is raised to 0.4V. Simulation parameters are similar to Table III. The difference is that we have 3 cladded Ge QD layers, and they are assembled on a thin SiO2 layer (~0.12 micron) grown on p-Si substrate. The integration of a 3-D confined QD n-SWS-FET with QD-p-SWS-FET, as shown in Fig. 6, results in a CMOS inverter similar to shown in Fig. 1(a). Here, the n-drains (D2 and D1) for NMOS are not shown adjacent to p-drains (D2 and D1).The inverter truth table is shown in Table IV.

Fig. 6. Cross-section of a CMOS inverter incorporating 3-D confined Ge QD SWS n-FET and p-FET. Table IV. Truth Table for SWS-CMOS inverter Input

Output

Logic ‘0’

Logic ‘3’

Logic ‘1’

Logic ‘2’

Logic ‘2’

Logic ‘1’

Logic ‘3’

Logic ‘1’

4. 2-bit Logic using QD SWS-FETs Earlier, we have reported static random-access memory (SRAM) cells [8] using two crosscoupled CMOS-SWS inverters. Here, we present a 2-bit NOR logic gate schematic and its ABM simulation using SWS-FETs as shown in Fig. 7(a). The NOR configuration comprises 4 nSWS-FETs and 3 pSWS-FETs. The three pSWS transistors set for pull-up path and the four nSWS transistors provide pull-down the path. In this circuit configuration, VDD1 corresponds to Logic ‘3’, VDD2 to Logic ‘2’, VSS2 to Logic ‘1’, and VSS1 to Logic ‘0’. For the simulations below, we have set VDD1=1.2V, VDD2=0.8V, VSS2=0.4V, and VSS1=0V. These pSWS and nSWS are operated at different threshold voltages (vth1,vth2,VuL) as shown in Fig. 7(a). The circuit is designed to operate in two general cases (Case-1 and Case-2). In Case-1, both inputs are in the low states (IN1 and IN2=Logic ‘0’ or Logic ‘1’),

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and the pull-up path is on and the pull-down path is cutoff. Case-2 occurs when one or both inputs are in the high states (IN1 or IN2=Logic ‘2’ or Logic ‘3’) where the pull-down path is on and pull-up path is cutoff. In Case-1, if the inputs (IN1, IN2) value are both low states, pSWSB1 is turned on and one of pSWSA1 or pSWSA2 is also turned on, which sets the output to Logic ‘3’ (=VDD1) if IN1 and IN2 are both in Logic ‘0’. However, if one or both inputs are in Logic ‘1’, the output is equal to Logic ‘2’ (=VDD2). In this case (Case-1) all nSWS transistors (nSWSA1, nSWSA2, nSWSB1 and nSWSB2) are turned off, cutting off remain paths to VSS1 or VSS2. In Case-2, the pull-up path is cut off and the nSWS transistors drive the output as follow,  



Case-2-1: when one or both inputs is Logic ‘3’, the nSWSA1 and/or nSWSB1 upper wells are turned on, which sets the output to Logic ‘0’ (=VSS1). Case-2-2: when one input value is set to Logic ‘2’ and the other input is in any logic except for logic ‘3’, the lower wells of either or both of the nSWSA1 and nSWSB2 transistors are turned on, hence driving the output to Logic ‘1’ (=VSS2). To prevent Case-2-2 from interfering with the other case, nSWSB2 and nSWSA2 transistors (nSWSx) have been added, where nSWSx transistor has a lower threshold for lower well W2 (vth2) to pass the VSS2 voltage for Logic ‘3’ inputs. Moreover, nSWSA1 and nSWSB1 transistors (nSWS1) have higher threshold for lower well W2 (vth2=0.25V).

The upper panel in Fig. 7(b) shows ID-VG characteristics for lower threshold nSWSx, where the red dotted line and green solid line for lower and upper channels, respectively. In Fig. 7(b) lower panel, p-SWS-FET ID-VG characteristics is represented by yellow dotted line and blue solid line for lower and upper channels, respectively. Similarly, the green solid line and red dotted line shows the ID-VG of n-SWS-FET in lower and upper channels. Figure 7(c) shows the BSIM based analog behavioral model (ABM) simulation [9,10]. The top panel and bottom panel of Fig. 7(c) shows all input combinations and output of the 2-bit SWS-NOR gate of Fig. 7(a). Figure 7(c) shows the simulation results for the SWS-FET NOR schematic shown in the Fig. 7(a). The proposed Quaternary NOR logic circuit gets extracted by using Cadence tool 0.18um technology. In Quaternary logic, the inverted max input logic is represented by NOR gate logic as shown in Table V. In the simulation plot, the solid green and dotted red line show all input combinations to the NOR gate. The yellow dotted line represents the ideal output based on the truth table given in Table V. The output of the NOR gate i.e., the blue solid line follows the ideal output. The output deviates by 0.1 V-0.15 V in few instances due to pull-up/pull-down resistance differences in the p-SWS-FET and n-SWSFET. However, the differences are within the noise margin levels. Full- and half-Adders using 2-bit CMOS-SWS NORs and inverters can be designed.

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Fig. 7(a). Schematic of 2-input NOR using 4 n-SWS and 3 p-SWS FETs.

Fig. 7(b). Simulated ID- Vg for 2-bit NOR using 3 p-SWS and 4 n-SWS FETs.

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Fig. 7(c). Analog Behavioral Model (ABM) simulation of 7-FET CMOS SWS NOR. Table V. Truth Table for Quaternary NOR Gate In1/In2

In1 (0)

In1 (1)

In1 (2)

In1 (3)

In2 (0)

3

2

1

0

In2 (1)

2

2

1

0

In2 (2)

1

1

1

0

In2 (3)

0

0

0

0

5. Integration of QD-SWS Logic with QD-NVRAMs The integration of multi-bit fast erase/fast-write multi-bit quantum dot nonvolatile randomaccess memory, QD-NVRAM [11] with QD n-SWS-FETs schematically is shown in Fig. 8(a). The QDAC layer and floating gate is formed by 4-layers of quantum dot. The floating gate (two bottom layers of quantum dots) and quantum dot access channel (QDAC) connected to a dedicated erase line is shown not to scale in comparison to SWS-FET on the right. Methodology used in quantum simulations for QD-NVRAMs and SWS-FET is reported [12,13,4]. As a fully integrated 2-bit processing platform, we envision including CMOS-SWS NOR logic and adders, SWS-SRAMs and registers on one chip. Figure 8(b) illustrates potential integration in physical layer of 2-bit SWS logic, using NORs and inverters, 2-bit SRAMs, and registers. The integration of 3-D confined Quantum Dot SWS-FETs is expected to construct 3-bit/4-bit inverters, logic, and SRAM and NVRAMs on one chip. The energy separations in quantum dot superlattice (QDSL) for Ge QD channels ensure room temperature operation. Lower temperatures will improve the noise margins.

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Fig. 8(a). 3-D schematic showing integration of a QD-NVRAM cell with 3D-confined SWS-FET.

Fig. 8(b). QD-NVRAM integrated with 2-bit.

6. Conclusion Using a multi-channel SWS configurations provide a new design paradigm for multistate/ multibit FETs. The incorporation of quantum dot gate (QDG) enables another dimension for additional intermediate ‘I’ states. Both, SWS- and QDG-FETs, in long-channel configurations, have been experimentally verified. Experimental evidence of intermediate states in SiOx-cladded Si SWS-FET and in GeOx-cladded Ge QD single channel FETs have been shown in Figs. 2 and 5, respectively. Current transport simulations in Ge QDC FET [Fig. 5(b)] also show the presence of an intermediate state. Furthermore, we have presented short-channel versions of these devices, including quantum dot channel (QDC) SWS-FETs incorporating Ge QDSL layers, which can confine carriers along the channel length between Si source and drain. The large bandgap discontinuities of the materials comprising these channels is the discriminating technology. The additional degree of quantum confinement in short-channel devices provides 3-D confinement, which is anticipated to enable additional intermediate states. Circuits exhibiting 2-bit operation, based on long-channel devices, have been designed and simulated. With the enablement of 3-D confinement in short-channel QD-FETs, 3 or 4-bit operation (e.g. inverters, SRAMs, NOR, adders, field-programmable gate arrays, FPGAs) is predicted.

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Multi-bit/multi-state 3D-confined Si/Ge cladded quantum dot layers in SWS-FETs configuration is another design paradigm to SET logic (6,7) and more recent four-qubit Si/SiGe quantum processors [14,15]. Acknowledgments This paper is based on SWS-FET and quantum dot FET research carried out by the support of completed grants including Office of Naval Research contracts (N00014-02-1-0883 and N00014-06-1-0016), and National Science Foundation grants (NER and ECS 0622068). Authors gratefully acknowledge the support of Dr. M. Lingalugari (currently at Synopsys Corp.) for QD-NVRAM fabrication, Dr. Pik-Yiu Chan (UCONN) for the fabrication of QD-SWS twin-drain FETs and Dr. LaComb (NUWC) for guidance in mask fabrication. References 1. F. Jain, M. Lingalugari, B. Saman, P.-Y. Chan, P. Gogna, E.-S. Hasaneen, J. Chandy, and E. Heller, Multi-state Sub-9 nm QDC-SWS FETs for compact memory circuits, 46th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego (CA), December 2–5 (2015). 2. F. Jain, M. Lingalugari, J. Kondo, P. Mirdha, E. Suarez, J. Chandy, and E. Heller, Quantum dot channel (QDC) FETs with wraparound II-VI gate insulators: numerical simulations, Journal of Electronic Materials, 45, 5663 (2016). 3. F. Jain, B. Saman, R. Gudlavalleti, J. Chandy, and E. Heller, Multi-state 2-bit CMOS logic using n- and p-quantum well channel spatial wavefunction switched (SWS) FETs, International Journal of High Speed Electronics and Systems, 27, 1840020 (2018). 4. F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy, and E. Heller, Low-threshold II-VI lattice-matched SWS-FETs for multivalued low-power logic, Journal of Electronic Material, 50, 2618–2629 (2021). 5. M. Lingalugari, K. Baskar, P.-Y. Chan, P. Dufilie, E. Suarez, J. Chandy, E. Heller, and F. Jain, Novel multistate quantum dot gate FETs using SiO2 and lattice-matched ZnS-ZnMgS-ZnS as gate insulators, Journal of Electronic Materials, 42, 3156 (2013). 6. M. A. Kastner, The single electron transistor, Reviews of Modern Physics, 64, 3, 849–858, (1992). 7. R. K. Kummaru, A. O. Orlov, R. Ramasubramanium, C. S. Lent, G. H. Bernstein and G. L. Snider, Operation of a quantum dot cellular automata (QCA) shift register and analysis of error, IEEE Transactions on Electron Devices, 50, 9, 1906–1913 (2003). 8. R. H. Gudlavalleti, B. Saman, R. Mays, H. Salama, E. Heller, J. Chandy, and F. Jain, A novel addressing circuit for SWS-FET based multi-valued dynamic random access memory array, International Journal of High Speed Electronics and Systems, 29, 2040009 (2020). 9. G. Casinovi, and J.-M. Yang, Multi-level simulation of large analog systems containing behavioral models, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, 13, 1391 (1994). 10. B. Saman, P. Gogna, E.-S. Hasaneen, J. Chandy, E. Heller, and F. C. Jain, Spatial wavefunction switched (SWS) FET SRAM circuits and simulation, International Journal of High Speed Electronics and Systems, 26, 1740009 (2017).

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11. M. Lingalugari, P. Mirdha, J. Chandy, E. Heller, and F. Jain, Quantum dot floating gate nonvolatile random access memory using quantum dot channel for faster erasing, Electronic Letters, 54, 36 (2018). 12. E. K. Heller, S. K. Islam, G. Zhao, and F. C. Jain, Analysis of In0.52Al0.48As/In0.53Ga0.47As/InP quantum wire MODFETs employing coupled well channels, Solid-State Electronics, 42, 901 (1999). 13. E. Heller, and F. Jain, Performance of 30 nm Gate Length InAlAs-InGaAs MODFETs: Comparison of conventional and asymmetric coupled-well transport channel configurations, International Journal of Infrared and Millimeter Waves, 22, 101 (2001). 14. A. J. Sigillito, J. C. Loy, D. M. Zajac, M. J. Gullans, L. F. Edge, and J. R. Petta, Site-selective quantum control in an isotopically enriched 28Si/Si0.7Ge0.3 quadruple quantum dot, Physics Review Applied, 11, 061006 (2019). 15. T. F. Watson, S. G. J. Phillips, E. Kawakami, D. R. Ward, P. Scarlino, M. Veklhorst, D. E. Savage, M. G. Lagally, M. Friesen, S. N. Coppersmith, M. A. Eriksson, and I. M. K. Vandersypan, A Programmable two-bit quantum processor in Silicon, Nature, 555, 633 (2018).

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0012

Systems for Implementing Data Communication with Security Tokens Milton Chang*, Santanu Das, Dale Montrone and Tapan Chakraborty DomaniSystems Inc., Shelton, CT, USA * [email protected]

This paper proposes a novel scheme for inter-connecting IOT devices with servers. To overcome the drawbacks and other shortcomings of existing IoT network schemes, a new approach to IoT device certification and inter-connecting IoT devices to other network devices (e.g., aggregators and servers) is described. The proposed approach ensures that the overall IoT network is “hardened” against attack and meets the stringent requirements of mission critical applications. Keywords: IOT; servers; service token; traffic tokens; blockchain; DApp; Ethereum

1. Introduction The Internet of Things (IoT) is the network of physical devices, vehicles, home appliances, and other items that have embedded electronics, software, sensors, actuators, and connectivity, which exchange data, creating opportunities for direct integration of the physical world into computer-based systems. This results in economic benefits because of efficiency improvements and reduced human labor. The number of IoT devices increased 31% year-over-year to 8.4 billion in 2017 [1] and it is estimated that there are 30 billion devices in service by the end of 2020. The global market value of IoT in terms of dollars added to the economy is projected to be $7.1 trillion by the end of 2020 [1]. Examples of IoT devices range from sensors like temperature and pressure sensors to more complex devices configured for monitoring air pollution to nuclear radiation as well as actuators controlling elevators and HVAC equipment. The systems and devices described in this article are applicable to these and many other types of IoT devices as well. Figure 1 shows a high-level overview of a typical network of IoT devices connected to and controlled by one or more servers. This typical arrangement is inherently vulnerable to Denial of Service (DOS) and Man in the Middle (MITM) type of attacks to both the IoT devices as well as the servers. The traditional approach to securing such a network architecture has been to (i) have each and every IoT device go through a certification process and (ii) secure the network links interconnecting the IoT devices and the servers using https [2] protocol or other secure transmission schemes. *Corresponding

author. 

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Fig. 1. Internet and security risks.

One common certification approach being used in the industry is based on the X.509 standard which is defined by the International Telecommunications Union’s Standardization sector (ITU-T). While this approach is acceptable for some regular applications, it is totally inadequate for mission critical applications. To start with, in typical deployments, the X.509 certificate [3] once obtained is valid for two years, and as a result, the IoT device and the network it is connected to remain vulnerable to nefarious activity for a long time if the X.509 certificate is obtained or otherwise compromised by a bad actor. Further, any change of ownership, public key, and other attributes during this period can be cumbersome and expensive because of the X.509 procedures. The simplicity of the X.509 structure has made it extremely popular, but the simple structure of X.509 also renders it more vulnerable to attack than more complicated schemes. As pointed out earlier, the security of the scheme in Fig. 1 depends on the combination of X.509 certificate approach associated with the IOT devices and securing the network links interconnecting the IoT devices and the servers using https [2] protocol or other secure transmission schemes. While HTTPS [2] protocol utilizing TLS [4] is quite popular, it is vulnerable to the attack by sophisticated hackers who usually use phishing scams to perform HTTPS bypassing to obtain authorized passwords, thus, to gain access to network devices and the communications between devices. HSTS [5] is now the preferred solution to deal with the vulnerability associated with HTTPS. While the HTTPS/HSTS links are quite robust though not widely deployed, the network structure in Fig. 1 is still vulnerable to DoS attacks. Moreover, though HTTPS/HSTS is helpful in preventing a MITM [5] attack for browser-based Internet access, its effectiveness is not bulletproof to MQTT based IoT access as MQTT hub is discoverable thus prone to be hacked by a malicious actor who can connect it to an unprotected MQTT server [6]. To overcome the above-described drawbacks and other shortcomings of existing IoT network schemes, a new approach to IoT device certification and interconnecting IoT devices to other network devices (e.g., aggregators and servers) is described. The proposed approach ensures that the overall IoT network is “hardened” against attack and meets the stringent requirements of mission critical applications.

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2. Man-In-The-Middle (MITM) Attack and the Mitigation Traditionally, Man-In-the-Middle (MITM) attacks are closely related to Address Resolution Protocol (ARP) [7] poisoning attacks; thus, prevention of ARP poisoning is still an active research area. The weakness rooted in ARP can be easily taken advantage of given that the Linux operating system and ARP tables can be changed unilaterally without consent from involved parties. ARP spoofing can be done using well known common Linux commands. The tools like Bettercap [8] and others are used by the hackers to exploit this weakness of Linux and associated ARP tables. Once, MITM is able to position itself between a victim and a network component or server, the MITM can compromise the network in a matter of time. A common mitigation approach to use with the end devices is to be interconnected using a Virtual Private Network (VPN) assuming the VPN server at the other end is secure. This approach could be costly and not practical for many IoT applications. An alternative is presented in this paper which is based on using internet for interconnecting IOT devices and the servers and having an Out Of Band (OOB) Blockchain Network to distribute security tokens associated with the communications among IOT devices and the servers [9]. 3. Blockchain Networks Blockchain is a distributed ledger that can contain financial and/or non-financial transactions. The ledger is replicated (distributed) across a number of nodes in near real-time over a peer-to-peer network. Every participant “owns” the same copy of the ledger and gets updates when any transaction is added. Every participant helps determine the intrinsic “immutability” of all existing records. Blockchain uses cryptography and digital signatures to prove identity, authenticity and to enforce read/write access rights. It has mechanisms to make it difficult to change historical records, or at least make it easy to detect when someone is trying to change it. Figure 2 illustrates a typical Blockchain System Architecture with Smart Contract capability. The business logic to perform financial and/or non-financial transactions required for a particular application is implemented using a programming approach called ‘Smart Contract’. In recent years, a Blockchain platform known as Ethereum [10] has seen wide adoption, bringing Blockchain technology to the mainstream. Ethereum based Blockchain is implemented using the so-called ‘Permission-less’ concept. While this approach is perfectly acceptable for many applications, it cannot meet the onerous security requirements associated with enterprise applications. In Ethereum platform [10], Smart Contract is constructed using a programming language called ‘Solidity’. The Blockchain applications currently in use does not provide a user friendly interface to the smart contracts; thus, a separate Decentralized Application (DApp) is used to connect user with the smart contract. This forms a Client-Server relation-

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Fig. 2. The typical Ethereum blockchain system architecture with smart contract capability.

ship where the DApp is the client; and the Blockchain node with Smart Contract is the server. 4. Out of Band (OOB) Token Approach for Securing Communication Links Traditionally, Internet is used to connect the IoT devices with the server. When the number of devices explodes it becomes prohibitive in cost to maintain high throughput data connections and at the same time utilize advanced encryption/decryption methods like RSA or ECDSA for each data connection. To avoid the explosion of cost, symmetric encryption methods like DES or AES are used in these applications. Internet of Things (IoT) devices communicate with their servers only periodically in most applications; thus, a protocol is needed to resume the communication after a long silence. Also, the symmetric key used need to be updated occasionally. This results in a vulnerability as during the key exchange to resume the communication, the link can be hacked, and the encryption keys can also be broken given sufficient computing resources and time. Internet being an open network, it cannot be used without the protection of the most advanced encryption technology. The resulting cost of using this advance protection technology defeats the purpose of using a cost-effective communications solution like using the Internet.

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To address this issue, this paper proposes the use of a separate network, called Domani Token Network to distribute the security tokens among IOT devices and the servers. This approach allows the use of Internet to cost effectively inter-connect IOT devices and servers without having to use expensive and encryption technology in the Internet links.

Fig. 3. Service token created by DomaniToken manager transferred through DomaniToken network.

As shown in Fig. 3, the proposed scheme, in addition to the conventional Internet only approach, an out of band network connecting both the IoT device and its server is used in parallel. This out of band (OOB) DomaniToken network not only connects to the end points but also the DomaniToken manager. This DomaniToken manager is implemented using the combination of Smart Contract and DApp. In contrast to traditional IoT systems, the IoT devices and service Aggregator of Fig. 3 are not discoverable because they do not respond to open Internet query like ping. Instead, the IoT devices of the systems described herein require a “token” for communications. This token is like a certificate or other type of authorization that enables the IoT device to respond to a query originating from another certified/validated device with a pairing token. These tokens are administered through a physically or logically separate network which is different than the network used for interconnecting the IoT devices, aggregators, and servers among each other for regular data communication. Using one network for distributing and administering tokens among the IoT devices and the Internet for data communications among IOT devices and servers make the arrangement more difficult for hackers to infiltrate. In operation, the “tokens” are created by the token manager and the endpoints. In some scenarios, the token manager is a server connected to a separate token distribution network,

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called DomaniToken network as shown in Fig. 3. The aggregators and the servers are connected to both (i) DomaniToken networks, the token distribution network and (ii) Internet, the network which is used for transporting data between IoT devices and the servers and/or other network components. There are two types of tokens involved in enforcing the security scheme: (i) service tokens, as shown in Fig. 3, and (ii) traffic tokens as shown in Fig. 4. Each service token and each traffic token have an expiration date/time.

Fig. 4. Traffic token transferred through DomaniToken network between already paired endpoints.

The service token pairs an endpoint/aggregator with a server has a lifetime which is relatively long compared to the traffic token. The traffic token is also used for pairing one device (e.g., an aggregator) to another device (e.g., a server) but this pairing is for a particular stream of messages. The traffic token life in this scheme is measured in seconds to minutes whereas the service token life is measured in days, months, or even years, depending on the configuration. In other words, a typical traffic token expires (i.e., is no longer valid) in a few seconds, minutes, or perhaps hours after being issued, whereas a typical service token expires (i.e., is no longer valid) in a few days, months, or even years after being issued. In some applications, the expiration of a traffic token or a service token may be measured in volume of data rather than time. For example, a traffic token in some applications may expire after the traffic token has been used for transmitting 10 MB, 100 MB, 1 GB, or some other amount of data. Similarly, a service token in some applications may expire after the service token has been used for transmitting some amount of data (rather than a period of time). In some cases, a traffic token and/or a service token may expire after

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some combination of time and data transmitted. For example, a traffic token may expire 1 hour from issuance or after being used to transmit 1 GB of data, whichever occurs first. The service token authorizes a device on the network to send and receive data to and from other authorized devices on the network. This service token can be revoked at any time, thereby rendering the device unable to send data to or receive data from other authorized devices on the network. 5. Control and Management Plane Operations of Security Token Exchange Whenever an IoT device/Aggregator is deployed into the field, it is provisioned with a Unique ID (UID) and a key pair of public key and private key. The key pair can comply with RSA or ECDSA. In some implementation, the public key can be used as an UID to publicly identifies a distinct IoT device/endpoint. DomaniToken manager is used to authorize the connection between the IoT device/ aggregation and its server. The IoT device is also provisioned with a set of servers which their UID. DomaniToken manager can perform this provisioning with its own UID and key pair. Due to security reasons, this DomaniToken networks and DomaniToken manager are implemented using Blockchain technologies including Smart Contract and Decentralized Application Software (DApp(s)). The allocation of the functions is based on considerations balancing various aspects concerning Privacy, Availability, Integrity, and Non-repudiation (PAIN). For example, decisions to authorize and revoke the Service Tokens between two endpoints can be implemented using a DApp; validation of an endpoints and the Service Tokens is implemented using a Smart Contract. This blockchain based DomaniToken network can be deployed using a dedicated private network or a Virtual Private Network (VPN) depend on the level of security and privacy the service requires. Once an endpoint device, either an IoT device or its server, is authorized and need to send data to its corresponding recipient, this endpoint device will generate a symmetric key or a asymmetric key pair as the Traffic Token depending on the level of security the data communication service via Internet requires. As mentioned in the previous section, these keys are for short term use. The lifetime last for a short period time like minutes and seconds. Once the lifetime expires, a new key must be used. The exchange of Traffic Tokens must be encrypted using the recipient’s public key and to be decrypted using the recipient’s private key. The strategy to change or rotate Traffic Tokens between authorized endpoints must be synchronized. The synchronization message may not require strict encryption/decryption practice to reduce the computation requirements. Various methods could be used to reduce the complexity of the Traffic Token exchange. For example, reliable acknowledge mechanism may not be required depending on the Service Level Agreement (SLA) for the number of packet loss can be tolerated. As Blockchain technology is used, non-repudiation characteristics can be demonstrated by the fact that any action to interact with the DomaniToken networks by any device cannot be erased. Evidence of Intrusion attempt will stay as a part of the Blockchain record. The inherent high availability characteristic of the Blockchain technology ensure the high availability of the IoT networks since no single point of failure would cripple the service.

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Recent development of Application Specific Blockchain like Tendermint [11] and Cosmos [12] further reduce the total cost and improve the performance achievable, thus, making Blockchain implementation of DomaniToken networks more attractive. 6. Data Plane Operation for Secure Data Exchange As mentioned in the previous sections, either Symmetric or Asymmetric keys can be used for Data Exchange. However, the use of the encryption and decryption keys between the endpoints must be synchronized as their lifetimes are short. The synchronization protocol is through the OOB Control and Management network instead of using the Internet which the Data Plane is using. This does not preclude the use of special characters or packet format to assist in synchronization. The sender of the communicating endpoint would encrypt the data using the current valid encryption key or Traffic Token before the data is forwarded to the recipient through the Internet. The recipient shall decrypt the received data packet using the valid Traffic Token. Under extreme conditions, Data Plane Operation could also use the OOB DomaniToken network. For instance, if the Internet connectivity is no longer available and the DomaniToken network is still in operation, data exchange could be conducted via the DomaniToken network at a reduced throughput. Though it may not be economical as the Internet, the high cost could be worth the additional availability provided by this approach. For example, only certain metadata could be allowed to be transported using the DomaniToken networks when Internet is not available. Since in this arrangement, the IoT devices do not respond to external requests using regular communication request messages, the devices are not discoverable when common device scanning methods like NMAP [13] are used. This results in a more secure IoT network. 7. Summary This paper presents a novel method and system for interconnecting Internet of Things (IoT) Devices, specially configured Aggregator and Server systems among each other in a secure way for mission critical applications like Industrial Automation, Healthcare, Smart Grid Control, etc. The scheme described in Figs. 3 and 4, instead of using only one Internet facing interface for all operation, administration, and management (OAM) functions, uses a second interface separated from Internet Control and Management Plane. This approach is more robust and hardened against network attackers than prior known solutions because of the use of (a) a secure dedicated network for token administration, (b) a separate network for interconnecting devices on the network, e.g., IoT devices, aggregators, and servers and (c) two different types of tokens—a first token (i.e., the service token) associated with devices but of limited life and easily revocable and the second token (i.e., the traffic token) pairing message streams between devices which has a limited life compared to the first token.

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The use of emerging Application-Specific Blockchain like Cosmos makes the cost of adopting Blockchain Technologies further reduced; thus, the DomaniToken networks scheme is cost-effective to be widely deployed for not only the mission critical applications like Industrial IoT but also privacy sensitive applications like Point of Care (POC) medical applications. References 1. https://www.gartner.com/en/newsroom/press-releases/2017-02-07-gartner-says-8-billionconnected-things-will-be-in-use-in-2017-up-31-percent-from-2016 2. https://en.wikipedia.org/wiki/HTTPS 3. https://en.wikipedia.org/wiki/X.509 4. https://en.wikipedia.org/wiki/Transport_Layer_Security 5. https://en.wikipedia.org/wiki/Man-in-the-middle_attack 6. https://blog.avast.com/mqtt-vulnerabilities-hacking-smart-homes 7. Address Resolution Protocol (ARP). https://en.wikipedia.org/wiki/Address_Resolution_Protocol 8. https://www.bettercap.org/ 9. Sin-Min Chang and Santanu Das, DomaniSystems, Inc. “Systems and methods for implementing data communication with security tokens,” US Patent, US10547594B2, January 2020. 10. Ethereum, https://ethereum.org/en/ 11. https://tendermint.com/ 12. https://cosmos.network/intro 13. https://nmap.org/book/port-scanning-tutorial.html

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0013

Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs H. Salama1, B. Saman1,2, R. Gudlavalleti1, R. Mays1, E. Heller 3, J. Chandy1 and F. Jain1,* 1ECE,

University of Connecticut, Storrs, CT, USA 2Taif University, Taif, Saudi Arabia 3Synopsys Inc., Ossining NY and San Jose, CA, USA *[email protected]

This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs. Keywords: SWSFETs; 2-bit SRAMs; SWS-SRAMs; SWS 1-bit adder

1. Introduction Spatial wavefunction switched (SWS-FETs) comprises of vertically stacked quantum well/quantum dot channels allowing the drain current flow in multiple channels in a single transistor [1]. Figure 1(a) shows a two quantum wells channel SWS-FET structure, where Si quantum wells are sandwiched between two SiGe barriers. Figure 1(b) shows a twoquantum dot channel SWS-FET where each quantum dot channel (QC) comprises of two layers of quantum dots (QDs) [6]. Figure 1(c) shows the ID-VD characteristics of a 2-QD channel SWS-NMOS-FET. Quantum dot layers have also been reported as nonvolatile memories [7] and nonvolatile random-access memories (NVRAMs) [8].

Fig. 1(a). A two quantum well channel nSWS-FET. *Corresponding

author.

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Fig. 1(b). A two quantum dot channel SWS-FET

Fig. 1(c). ID-VD characteristics of 2-QD channel SWSNMOS-FET.

The spatial location of electrons, confined in quantum wells or quantum dot layers in spatial wavefunction switched (SWS) field-effect transistors (FETs), is used to encode the logic states (00), (01), (10) and (11). Logic state (00) is when no electrons are present in any channel (W2/W1, QC2/QC1). When the gate voltage VG is above threshold VTH2, the lower quantum well (W2) or quantum dot channel QC2 (for quantum dot channel SWS) is populated. This is logic state (01). As the gate voltage increases above VUL, some electrons transfer to the upper quantum well (W1) or dot channel QC1. This is state (10) [11]. This is associated with a decrease in drain current ID in channel W2 or QC2 and flow of drain current in well W1/QC-1. As the gate voltage is further increased above threshold VTH1, all electrons are transferred to upper well W1 or QC1. This is logic state (11). Based on the operation of SWS, the threshold voltages are defined as follows [10], 𝑉

𝑉

when 𝑉

𝑉

𝑉

𝛼 𝑉

matching parameter, 𝛼 𝑉 𝑉

𝑉

𝑉 𝑉

1(a) 𝑉

𝑉

1(b)

𝑉 𝑉

𝑉 𝑉

1(c)

𝑉

1(d)

𝑞𝜖 𝑛

𝐶 10 2

1

𝑉 2𝜙 2 𝑉 𝐶 10 𝑞𝜖 𝑛

1

1(e)

VGS is the gate-source voltage, VGSeff is the effective gate-source voltage, VPolyEff is the voltage drop in the poly silicon gate, COX is the gate capacitance, VFB is the flat band voltage, Φf is the surface potential, q is the electron charge, δ = 0.01 is the parameter for DC VDSeff, and ϵs is the permittivity. Equations 1(a)-1(e) are used in the analog behavioral model (ABM) to establish SWS-FET model. SWS-FETs have been used to implement various logic gates. For example, an inverter design using 2 n-channel SWS-FETs is shown in Fig. 2 [2,3]. Similarly, a SWS NAND using three n-channel SWS-FETs is shown in Fig. 3 [2,3].

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Fig. 2. SWS-FET inverter.

Fig. 3. SWS-FET NAND.

Figure 4 shows the schematic circuits for XNOR and XOR, respectively. XNOR is implemented with four and XOR with six n-SWS-FETs [3].

Fig. 4. SWS-FET XNOR/XOR.

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The accuracy of the SWS-FET logic is verified by SWS-FET model in Cadence. The model is based on an integration of the Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM) [3,5,9]. This paper presents the design of a 1-bit full adder circuits using high-mobility nchannel spatial wavefunction switching (SWS) FETs which provide a significant reduction of cell area (52% smaller in size) and power dissipation. 2. 1-Bit Full-Adder A conventional CMOS 1-bit full adder has 3 NAND and 2 XOR gates (44 transistors as: 3*4+2*16) is shown in Fig. 5. It is based on XOR-NAND design. Table 1 is the truth table for a 1-bit full adder [4]. Use of SWS-FETs is shown to result in reduced number of transistors which in turn results in lower power consumption as well as delay.

Fig. 5. Full adder circuit. TABLE 1. TRUTH TABLE A

B

C

Sum

Cout

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1

In this work, we combine SWS-NAND (Fig. 3) and XOR (Fig. 4) to implement a 1-bit full adder circuit. This combination uses twenty-one n-channel SWS-FETs. Nine n-channel SWS-FETs are employed for the three SWS-NAND gates and twelve n-channel SWSFETs for the two SWS-XOR blocks. The simulation of 1-bit full adder is carried out using Cadence and the waveforms, and results are shown in Fig. 6(a). The simulation analysis is carried out with three inputs (A, B, C) and two outputs (Sum and Carry out Cout) of full- adder. Table 2 shows SWSFET parameters used.

Compact 1-Bit Full Adder and 2-Bit SRAMs

Fig. 6(a). The simulation of CMOS and SWS-FET full adder.

Fig. 6(b). The delay of CMOS and SWS-FET full adder.

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H. Salama et al. TABLE 2. SIMULATION MODEL PARAMETERS Parameter

L

W

Vth

n-MOS

20nm

100nm

0.2 V

p-MOS

20nm

200nm

-0.12 V

W1-SWS-FET

20nm

50nm

0.3 V

W2-SWS-FET

20nm

100nm

0.1 V

Figure 6(a) shows the cases of all three input A, B, and C. The plot in Fig. 6(a) indicates the full adder output sum for SWS-full adder (solid green line) and CMOS-Full adder (dash red line). Moreover, the bottom plot in Fig. 6(a) shows the full adder carry output (Cout) as SWS-full adder (solid green line) and CMOS-full adder (dash red line). The inputs bit waveform (A, B, C) is generated from the cadence simulation. The output Sum is high and Cout is low if one input bit is only high (as time periods 0.1us to 0.3us and 0.4us to 0.5us). In case of two inputs are high, the output Sum is low and Cout is high (as time periods 0.3s to 0.4us and 0.5us to 0.7us). IF all outputs (Sum and Cout) are high when all input are high (period 0.7us to 0.8us). The simulation results are as expected in the truth table as tabulated in Table 1. As can be seen, the outputs for the SWS full adder are equivalent to those from the CMOS full adder. Output has some rouge pulses due to switch from one well to other, but it is sufficient to function as adder. The simulation waveform of delay is shown in Fig. 6(b). The top plot shows the full adder output sum delay, where SWS-full adder is the solid green line and CMOS-Full adder is the dash red line. Moreover, the bottom plot in Fig. 6(b) shows the full adder delay of Cout output for both SWS-full adder (solid green line) and CMOS-Full adder (dash red line). SWS-FETs based 1-bit full adder circuit reduce the number of transistors by 52% (21/44-1) compared with conventional CMOS (44 transistors: 21 n-MOS and 21 p-MOS). SWS-FET full- adder has the same accuracy as that of CMOS. Table 3 compares the time delay with conventional CMOS. The delay is below 10ps for a 20 nm node. TABLE 3. SIMULATION RESULT Circuit

# Transistors

Delay Sum

Delay Cout

CMOS

44

60ps

40ps

SWSFET

21

factor of 2X; hole mobility for Si0.5Ge0.5 is 1480 cm2/V-s) than Si quantum wells. This results in W/L ratio of both n-SWS-FET and p-SWS-FET to be similar. The switching of hole wavefunction from SiGe well W2 to well SiGe well W1 is shown for a p-channel SWS-FET in Fig. 5(b). In a two QW n-channel SWS-FET, when the gate to source voltage (VGS) is below threshold of lower well (Vth2), both wells W1 and W2 are in off mode so both currents in lower well (IDS2) and upper well (IDS1) are zero. As the gate voltage is set above Vth2, the

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electrons are confined in well W2, resulting in drain current, IDS2, flowing in W2. As VGS becomes greater than the threshold voltage of the upper well (Vth1), the electrons transfer from W2 to W1, and drain current IDS1 flows in W1, and IDS2 drops off. At transition voltage (VUL), W2 is in an off mode [1–4,7]. Tables II, III and IV show the operation modes of MOS-FET, n- and p-SWS-FET, respectively. Table II. Operations for conventional FETs n-MOS

p-MOS

VGS < Vth

VDS >VGS -Vth>0

VDS >0

VGS > Vth

VDS >0

Table III. Switching modes for two Quantum Well n-SWS-FET Gate voltage VG

VGS < Vth2

Well-1

Off mode IDS1≈0

Well-2

Off mode IDS2≈0

VGS > Vth2 VGS > VUL VGS > Vth1

VGS >> Vth2 VGS >> VUL VGS >> Vth1

Off mode IDS1≈0

On mode IDS1>0

On mode IDS1>>0

On mode IDS2>>0

≈ Off mode IDS2→ 0

Off mode IDS2≈0

VGS > Vth2 VGS < VUL VGS < Vth1

Table IV. Switching mode for two Quantum Well p-SWS-FET Gate voltage VG

VGS Vth2

Well-1

On mode ISD1>>0

On mode ISD1>0

Off mode ISD1≈0

Off mode ISD1≈0

Well-2

Off mode ISD2≈0

≈ Off mode ISD2→ 0

On mode ISD2>>0

Off mode ISD2≈0

5. Simulation using Analog Behavioral Model SWS-FET model is based on the integration of Berkeley Short-channel IGFET Model (BSIM4.6) and the Analog Behavioral Model (ABM). The twin-drain n-SWS-FET is modeled by combining two BSIM equivalent circuits (BSIM-EC) as shown in Fig. 6 [6,7]. ABM blocks are used to represent changes in threshold voltage (for the lower quantum well W2), all capacitances, and the current sources [8]. The resistances (RD1, RD2, and RS) are calculated based on device geometry [9]. Drain current sources IDS2 (lower well W2) and IDS1 (upper well W1) are obtained from BSIM transistor model [1–3,7]. The capacitances (CGB, CGD1, CGS1, CGD2, CGS2, CBD and CBS) are obtained from Meyer’s capacitance model [9–12]. CGDO and CGSO are the overlap capacitors. Figure 7 shows Cadence simulation of IDS2 and IDS1 versus VGS for two QW n- and pSWS-FET. The plot was obtained using BSIM 4.6.0 for 20 nm parameters and VDD = 1 V, Vth1 = 0.3 V, VUL = 0.25 V, Vth2 = 0.2 V, L = 20nm, W1 = 40 nm, and W2 = 100 nm.

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Fig. 6. The model of the twin drain SWS-FET by BSIM-EC.

Fig. 7. BSIM-EC twin drains 20nm n- and p- SWS-FET modeled IDS-W2 (--) and IDS-W1 (―).

Figure 8 shows SWS-FET logic gates [7] comprising of NAND, NOR, XNOR, and XOR. Here, the number of transistors is reduced to three in NAND and NOR compared with conventional CMOS where 4 FETs (2-nMOS and 2-pMOS) are needed. In the case of XNOR, 4 n-SWS-FETs are used as compared to 16 transistors in case of CMOS technology. Thus SWS-FET circuits offer lower FET count [13–16]. Figure 9 shows the simulations of NOT, NAND, and NOR logic gates for the 20 nm n-SWS-FET devices.

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Fig. 8. n-SWS-FET NAND gate (top left), NOR gate (bottom left), and XNOR/XOR gate (right) [7].

Fig. 9. Effect of floating gate quantum dot thickness cladding on tunneling time normalized to 10Å cladding.

6. SWS-FET 3-Bit Flash Analog-to-Digital Converter (ADC) Circuit The design of 3-bit flash Analog-to-Digital Converter (ADC) using n-SWS-FETs has been reported using two different architectures [14 –16] as shown in Figs. 10(a) and 10(b). In both the architectures, a multi-channel SWS-FET serves as a switch which selects one of the comparators depending on the gate voltage. Even though, both the architectures I and II have a smaller device count than would be required to perform the ADC function than a conventional CMOS circuit, a current comparator circuit (not shown in reference) at the output of each SWS-FET drain node is further required to process the output voltage. This would increase the size and complexity of the design.

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Fig. 10. 3-Bit flash ADC n-SWS-FET architecture I (a) and architecture II (b).

This paper proposes a Threshold Inverter Quantization (TIQ) based voltage comparator using SWS-FET transistors. The conventional circuit would need 23-1=7 Threshold Inverter Quantization (with different W/L) and more than 7 CMOS inverters to work as voltage comparator (7+7=14 n-MOS and 7+7=14 p-MOS). A 3-bit ADC comparator design integrating complementary SWS-FETs (e.g. a two-well n-SWS-FET and p-SWSFET) is shown in Fig. 11. This design has 6 SWS-FET transistors (four n-SWS-FET and two p-SWS-FET). The circuit works as a voltage comparator. In the ADC design, the outputs S1 to S5, selected by the magnitude of input analog signal applied, change between VDD or VSS. This is provided by the switching properties of SWS-FETs. The S1-S5 outputs are fed to encoder. Figure 12 shows an encoder circuit using n-SWS-FET gates. This results in reduced number of transistors. The simulation of a 3-Bit ADC is shown in Fig. 13 at 10 MHz and 100 MHz sine wave input.

Fig. 11. 3-Bit Flash ADC Comparator using n- and p- SWS-FET.

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Fig. 12. 3-Bit ADC encoder using n-SWS-FET.

Table V shows number of SWS-FETs and conventional CMOS-FETs used for 3-bit ADCs. The SWS encoder is designed with 26 n-SWS-FETs while the same encoding circuit would be implemented with 46 CMOS transistors (23 n-MOS and 23 p-MOS). The total number of the FETs is reduced from 74 in conventional CMOS architecture to 32 using complementary SWS. Table V. The number of transistors for SWS-FET and Conventional CMOS Circuit

Reduction %

CMOS

C-SWS-FET

n-MOS

p-MOS

Total

n-SWS-FET

p-SWS-FET

Total

3-Bit ADC Comparator

78.5%

14

14

28

4

2

6

3-Bit ADC Encoder

43.5%

23

23

46

26

0

26

Total for 3-Bit ADC

56.7%

37

37

74

30

2

32

Fig. 13. SWS-FET 3 Bit ADC output (―) and input (--) at 10 MHz and 100 MHz.

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7. Conclusion In summary, we have demonstrated simulation of 3-bit analog-to-digital converters based on two quantum well channel complementary SWS-FETs. The number of the FETs is reduced from 74 in conventional CMOS architecture to 32 using complementary SWSFETs. This reduces cell area and power dissipation, making SWS-FETs a promising technology for analog applications. The novelty is using SWS-FETs for Threshold Inverter Quantization (TIQ) for voltage comparators. A circuit model is created using two BSIM equivalent circuits, and simulations are performed in Cadence for 20 nm and 180 nm channel length SWS-FETs for encoder and comparators, respectively. Quantum dot based SWS-FETs offer formation of sub-7nm devices that compatible with quantum dot nonvolatile random-access memories (QDNVRAM) [17]. This would pave the way to implement compact artificial intelligence hardware platforms. Acknowledgments This work was in part supported by Office of Naval Research contracts (N00014-02-10883 and N00014-06-1-0016), National Science Foundation grants (NER and ECS 0622068), and Connecticut Innovation grant. The authors gratefully acknowledge the assistance of Prof. T-P. Ma and Mr. C. Tillinghast of Yale University for the use of their laboratory facilities. The authors would like to acknowledge Dr. Murali Lingalugari (Synopsys) and Dr. Pial Mirdha (Global Foundries) for their assistance in the development of quantum dot SWS-FETs, NVM and NVRAMs. References 1. F. C. Jain, B. Miller, E. Suarez, P.-Y. Chan, S. Karmakar, F. Al-Amoody, M. Gogna, J. Chandy, and E. Heller, “Spatial Wave-function-Switched (SWS) InGaAs FETs with II–VI Gate Insulators,” Journal of Electronic Materials, 40, 8, 1717–726, 2011. 2. F. Jain, M. Lingalugari, B. Saman, P.-Y. Chan, P. Gogna, E.-S. Hasaneen, J. Chandy and E. Heller, “Multi-State Sub-9 nm QDC-SWS FETs for Compact Memory Circuits,” 46th IEEE Semiconductor Interface Specialists Conference (SISC), December 2–5, 2015. 3. F. Jain, M. Lingalugari, J. Kondo, P. Mirdha, E. Suarez, J. Chandy and E. Heller, “Quantum Dot Channel (QDC) FETs with Wraparound II–VI Gate Insulators: Numerical Simulations,” Journal of Electronic Materials, 45, 11, 5663–5670, 2016. 4. S. Karmakar, J. A. Chandy and F. C. Jain, “Unipolar Logic Gates Based on Spatial WaveFunction Switched FETs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23, 4, 609–618, 2015. 5. P. Gogna, “Quaternary Logic and Applications Using Multiple Quantum Well Based SWSFETs,” International Journal of VLSI Design & Communication Systems VLSICS, 3, 5, 27–42, 2012. 6. S. Borisov and A. S. Korotkov, “Procedure for Building a MOS Transistor High Frequency Small-signal Model,” Radio Electronics and Communications Systems, 53, 7, 356–366, 2010. 7. B. Saman, P. Mirdha, M. Lingalugari, P. Gogna, F. C. Jain, El-Sayed Hasaneen and E. Heller, “Logic Gates Design and Simulation Using Spatial Wave-function Switched (SWS) FETs,” International Journal of High Speed Electronics and Systems, 24, 03n04, 2015.

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8. Cadence SPICE Reference Manual, 20 November 2015. 9. S.-D. Kim, C.-M. Park and J. Woo, “Advanced Model and Analysis of Series Resistance for CMOS Scaling into Nanometer Regime. II. Quantitative Analysis,” IEEE Transactions on Electron Devices, 49, 3, 467–472, 2002. 10. M. A. Cirit, “The Meyer Model Revisited: Why Is Charge Not Conserved? (MOS Transistor),” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 8, 10, 1033– 1037, 1989. 11. T. Zaki, S. Scheinert, I. Horselmann, R. Rodel, F. Letzkus, H. Richter, U. Zschieschang, H. Klauk and J. N. Burghartz, “Accurate Capacitance Modeling and Characterization of Organic Thin-Film Transistors,” IEEE Transactions on Electron Devices, 61, 1, 98–104, 2014. 12. P. E. Allen and D. R. Holberg, CMOS Analog Circuit Design, 3rd Edition, New York: Oxford University Press, 2011. 13. P. Gogna, E. Suarez, M. Lingalugari, J. Chandy, E. Heller, E.-S. Hasaneen and F.-C. Jain, “GeZnSSe Spatial Wave-function Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic,” Journal of Electronic Materials, 42, 11, 2013. 14. B. Saman, P. Gogna, E.-S. Hasaneen, E. Heller and F.C. Jain “Spatial Wave-function Switched (SWS) FETs SRAM Circuits and Simulation,” Submitted to International Journal for HighSpeed Electronics and Systems (IJHSES), 9, 2016. 15. S. Karmakar, “Design of Three Bit Analog-To-Digital Converter (ADC) Using Spatial Wavefunction Switched (SWS) FETS,” International Journal of VLSI Design and Communication Systems VLSICS, 4, 3, 1–14, 2013. 16. S. Karmakar and F. C. Jain, “Design of Three bit ADC and DAC Using Spatial Wave-function Switched SWSFETs,” Silicon, 8, 3, 369–379, 2016. 17. M. Lingalugari, P. Mirdha, J. Chandy, E. Heller and F. Jain, “Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Quantum Dot Channel for Faster Erasing,” Electronic Letters, 54, 36–37, 2018. 18. F. Jain, R. H. Gudlavalleti, R. Mays, B. Saman, P.-Y. Chan, J. Chandy, M. Lingalugari and E. Heller, “Integration of Quantum Dot Gate, (QDG) in SWS-Fes for Multi-bit Logic and QDNVRAMs for Distributed and In-Memory Computing,” International Journal of High Speed Electronic Systems, 28, 3&4, 1940018, 2019.

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0015

Amaranthine: Humanoid Robot Kinematics Shefalika Asthana*, Srikanth R. Karna† and Irine Ann Shelby‡ Department of Electrical Engineering, University of Bridgeport, Bridgeport, USA *[email protected] †[email protected] ‡[email protected]

Humanoid robots are employed in a wide range of fields to replicate human actions. This paper presents the mechanism, configuration, mathematical modeling, and workspace of a 3D printed humanoid robot – Amaranthine. It also discusses the potential scope of humanoid robots in the present day and future. Robots can be programmed for automation as per the demand of the task or operations to be performed. Humanoid robots, while being one of the small groups of service robots in the current market, have the greatest potential to become the industrial tool of the future. Introducing a Humanoid Robot-like Amaranthine holds huge scope majorly in the fields of medical assistance, teaching aid, large industries where heavy-duty operations require application-specific software, etc. Amaranthine was 3D printed and assembled at the RISC Lab of University of Bridgeport. Keywords: MyRobotLab; Denavit-Hartenberg; Arduino; MATLAB; humanoid robot; forward kinematics; OpenCV

Introduction Humanoid robots are the most emerging and challenging research field in Robotics. With each passing day, robots are moving out from factory floors and entering our homes assisting in our daily lives. Humanoid robots are employed in a wide range of fields to replicate actions and help humans. To manufacture such robots at a large scale will be very costly as a lot of machinery and raw material will be required. They hold a lot of potential in terms of research. Regardless of the application area, one of the common problems tackled in humanoid robotics is the understanding of human-like information processing and the underlying mechanisms of the human brain in dealing with the real world [2]. Inspired from the open-source platform INMOOV, the parts were 3D printed and assembled AMARANTHINE with multiple features [1]. Previously many papers have been published working on various aspects of INMOOV [3]. This paper focuses on the mechanism, configuration, mathematical calculations and workspace of the humanoid robot using MATLAB.

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Amaranthine is a 3D printed robot where all the parts including head, hands, torso, back, and shoulder were assembled with different types of servo motors depending on the load for each joint. Amaranthine is controlled through voice commands using Arduino Mega microcontrollers powered by MyRobotLab. It can be programmed for different types of automation tasks as per the demand of the operations to be performed. Amaranthine Robot System is a human-sized humanoid robot with a stationary pedestal, torso, 6-(dof ) head with dual 5-(dof ) arms, stereo vision system, tactile stimulation from a metal fingertip sensor to sense the heat sensation and point cloud data collection from Kinect placed in the torso. The Amaranthine arm design has 5-dof robot arms. The 5-dof robotic arms are classified as vertically articulated with 5 revolute joints. It is a very dependable and safe robotic system designed for educational purpose. This system helps in gaining theoretical and practical experience in robotics, automation and control systems. In the next section overview of the Amaranthine Humanoid Robot has been discussed, followed by kinematics analysis and equations via MATLAB including forward kinematics solutions. Amaranthine Description Amaranthine’s physical attributes are that it is about 2’ tall and weighs about 8.2 kgs. The regular pose with all zero joint angles of the Amaranthine can be seen in Fig. 1 below.

Fig. 1. AMARANTHINE humanoid robot, zero pose.

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The zero pose is the rest position of the robot is the same as in humans which is the normal resting balance position [11]. Amaranthine build up can be divided into 5 sections as discussed further in this paper. A. Amaranthine Hardware Mechanism Amaranthine parts have been 3D printed in the RISC Lab of University of Bridgeport with MakerBot Replicators. The filament used for printing the parts is Polylactic Acid and Acrylonitrile Butadiene Styrene commonly known as PLA and ABS respectively in the industry. All the parts of the robot from gears, eyes to big chest covers have been 3D printed. Multiple printers were used to print these parts so that the process of assembling can be done faster. The gears have been printed with 30% infill with 3 shells so that these parts are strong enough to handle the load of the servo motors and its movements while the chest and head covers are printed with 15% infills and 2 shells so that the weight of the robot is not much. Figure 2 shows 3D printed parts before assembling of hand with servo motors. The Amaranthine arm has 5 high torque servo motors which are responsible for its actuation to move the arms around as per the programmed commands. This creates a naturally complaisant arm that would be supported in its workspace when communicating with objects and human beings. Each 5-dof arm has a peak torque of 2.5 Nm for the first four active joints (the shoulder and the elbow), while the wrist joint has a peak torque of 1.07 Nm. Which is an ample amount of force to lift weights up to five pounds. Fingers of the robot comprises of 16-dof. Each finger is attached to the metal strip to sense the heat of an object and due to this sensor, it can analyze the pressure required by it to hold an object. The head of Amaranthine comprises of 5 servo motors which control the movement of neck, eyes and jaw. The eyes are fixed with HD cameras which can record and click

Fig. 2. 3D printed parts of Hand before assembling.

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pictures or movements as per the instructions given to Amaranthine. Ears are fixed with 10 Watts speakers for audio. The torso is not in motion but withholds an important part in the whole set up. It holds all the nervo boards connecting all the servo motors, camera and speakers. It also holds Kinect XBOX-360 which is placed below the chest. It works on 3 vital points video camera, depth sensor and a multi-array microphone. Here, Kinect is being used to capture human gestures and replicate those actions by Amaranthine. Through Kinect it sees and understands the world around and captures in 3D view. Torso also has a PIR motion sensor to sense the motion of a human being around the robot and do certain actions. B. Amaranthine Configurations Each part in the humanoid robot has different configurations and set up. The servo motors in the head configuration are responsible for the jaw movement when Amaranthine converses with the user. Eye movements are managed by 2 small servo motors and the head tilt/pan are managed my 3 servo motors attached to neck. Each servo motors have been calibrated using Arduino for specific angle movement. The eye camera is connected to a computer screen where the real time video and pictures are captured via OpenCV. The high torque servo motors used in both the arms have been reconstructed by removing the potentiometer from these motors which control the degree of movement. The potentiometers removed from these motors are being used separately from the outer side to control these motors. potentiometers play an important role in control of these motors, they are being used as a separate entity so that the servo movement of the hand can be ranged for wider ranges. The objective of this paper is to study the forward kinematics of Amaranthine. There is neither a spherical shoulder nor a spherical wrist in this robot of 5-dof arms (i.e. 3 successive coordinate frames are meeting at the same origin). A 3-dof shoulder, a 1-dof elbow, and a 1-dof wrist were considered for designing this robot. Both 5-dof arms include angle position and joint torque sensing. Each arm has five servo motors in the fore-arm to control the actions of the fingers and thumb. Each bicep is equipped with two servo motors to control the forearm and bicep movement. The fingers are also controlled by 5 servo motors placed in the forearm connected through ribbon cables and fishing lines as clearly seen in Fig. 3. The ribbon cables are attached to Arduinos for the command control and power supply. Temperature sensors on each finger-tips to sense the heat of the substance/human fingers or body along with silicone grippers to hold objects firmly. Kinect is not connected to Arduino board but to a computer screen via a USB cable to see the 3D view of the surrounding. It captures motion data of the surroundings which can be used to study in different motion states and replicate actions. The robot consists of Nervo Board Shield (Printed Circuit Boards) for the connections made in the head and torso, operated with two ARDUINO MEGA 2560s. The ARDUINO MEGA fixed in the right arm controls most of the robot movements while the other MEGA

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controls the left arm. The camera has a maximum resolution of 720p HD video which can be used to recognize faces and save data. Amaranthine can be connected to 3 screens to visualize and capture data from the camera, Kinect and the temperature and PIR sensors.

Fig. 3. Servo motors controlling finger movement.

Fig. 4. Nervo Boards for the head and both arm movements.

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C. Amaranthine Software The Amaranthine Robot is programmed and controlled through MyRobotLab, an opensource GUI Java service based framework which is generally used for robotics and creative machine control. It runs on the Java update 8u141 and offers services like machine vision JavaCV/OpenCV, speech recognition from Sphinx 4, text to speech from FreeTTS, motor control, servo control, GUI control and microcontroller communication. It basically uses Arduino microcontrollers serial communications and turns Arduino into a I/O-slave [5]. Mathematical Model of Amaranthine Robot: Denavit-Hartenberg (DH) Parameters The Denavit-Hartenberg (DH, Denavit and Hartenberg, parameters are presented in this section, for each of the arms (two 5-dof arms) for the Amaranthine Robot. The DenavitHartenberg (DH) Parameters are the four parameters associated with a convention for attaching reference frames to the links of spatial kinematic chain or robotic manipulator. Using the basic conventions of the Denavit-Hartenberg principle, the DH tables for the Right and Left arms of Amaranthine were calculated (see Tables 1 and 2). The link lengths and joint offset length was calculated using Kinect gives the picture of the object in skeleton form. It shows the image in X-Y-Z dimension with the link measurements. Table 1. DH table of 5-dof Right Arm Joint Angle (θ)

Joint Number

Joint Type

Link Length (a)

Twist Angle (α)

Joint Offset length (d)

1

Revolute

152.4

-90 deg

39.4

𝜃

2

Revolute

180.6

-90 deg

0

𝜃

3

Revolute

282.6

90 deg

28.4

𝜃

4

Revolute

266.7

-90 deg

12.7

𝜃

5

Revolute

228.6

0 deg

0

𝜃

Table 2. DH table of 5-dof Left Arm Joint Angle (𝜽)

Joint Number

Joint Type

Link Length (a)

Twist Angle (α)

Joint Offset length (d)

1

Revolute

152.4

90 deg

39.4

𝜃

2

Revolute

180.6

90 deg

0

𝜃

3

Revolute

282.6

-90 deg

28.4

𝜃

4

Revolute

266.7

90 deg

12.7

𝜃

5

Revolute

228.6

0 deg

0

𝜃

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Using these DH table of the arms, the forward kinematic equations were calculated and workspace of the both the arms followed by the path trajectory simulations to observe the position, velocity and acceleration of each [8]. Amaranthine Forward Kinematics In Forward Pose Kinematic Analysis, the position of the end-effector (X, Y, Z) for a specific pose is calculated using the available link lengths (a) and joint displacements (θ,d) respective to the pose. On substituting the D-H parameters for each individual joint, different matrices are obtained. Multiplying all the five matrices for each joints, a link transformation matrix (4  4 matrix) is attained. The first three elements in the last column of this matrix give the (X, Y, Z) coordinates that define the position of the end-effector, here being the fingers. The equations obtained for each co-ordinate point for the amaranthine arm after calculation are: 𝑋

𝑌

𝑍

𝑎 𝑐

𝑎 𝑐

𝑎 𝑐

𝑎 𝑠 𝑐𝑐 𝑠 𝑠 𝑠 𝑐 𝑠 𝑠 𝑐 𝑠 𝑐 𝑎 𝑐 𝑐 𝑐 𝑐 𝑐 𝑠 𝑎 𝑠 𝑐 𝑐 𝑠 𝑠 𝑠 𝑐 𝑐 𝑎 𝑐 𝑠 𝑠 𝑎 𝑐 𝑠 𝑑 𝑎 𝑐𝑐 𝑎 𝑐

𝑐 𝑠

𝑑

𝑎 𝑠 𝑠 𝑐 𝑠 𝑐 𝑠 𝑐 𝑠 𝑠 𝑠 𝑐 𝑐 𝑎 𝑐 𝑠 𝑐 𝑐 𝑠 𝑠 𝑎 𝑠 𝑠 𝑐 𝑠 𝑐 𝑠 𝑠 𝑐 𝑎 𝑐 𝑐 𝑎 𝑠 𝑠 𝑠 𝑑 𝑎 𝑐 𝑠 𝑎 𝑠

𝑐 𝑐

𝑑

𝑐 𝑐 𝑐 𝑐

𝑐 𝑠 𝑐 𝑐

𝑠 𝑐 𝑐

𝑐 𝑠 𝑠 𝑎 𝑐

𝑎 𝑠 𝑠 𝑠 𝑐 𝑑 𝑎 𝑠 𝑑

𝑎 𝑐

𝑠𝑐

𝑐 𝑎 𝑠

𝑠 𝑠 𝑑

This is a generalized equation obtained. Substituting specific values for the Joint angle (θ) in the above equations, the coordinates for the position of the end-effector can be calculated [10,12,14]. Workspace and Path Trajectory Simulations of Amaranthine’s Arms The ‘Workspace of the Manipulator’ can be defined as “the set of points that can be reached by its end-effector.” In the previous section it stated the theoretical calculation of forward kinematic equations for both the arms of Amaranthine, now, the simulated the workspace of both the arms in MATLAB using Robotics Toolbox was derived. The maximum and minimum workspace limits for the functioning of the arms were set, like human arm movement limits. ‘Path Planning’ can be defined as “generating a feasible path from a start point to a goal point. It usually consists of a set of connected points”, while ‘Trajectory Planning’ is defined as “generating a time schedule for how to follow a path given constraints such as position, velocity and acceleration”. Here, after running the simulation of Trajectory Planning of Right and Left arms, the DH table mathematical model created is verified. This can be further understood and explained in Table 3:

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S. Asthana, S. R. Karna & I. A. Shelby Table 3. Computational comparison between the Right and Left Arm Right Arm

Left Arm

Virtual Arms Model

Computational 3D Model of Amaranthine

MATLAB 3D Simulation

Amaranthine: Humanoid Robot Kinematics Table 3. (Continued ) Right Arm

Left Arm

Workspace in XY plane

Path Trajectory

Position, Velocity and Acceleration

159

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From the 3 table represents the comparison study of Right and Left Arms. The First figure is the Virtual model of arms of the Amaranthine Robot and in the second figure it’s the 3D computational model where each revolute joint is presented with its rotational axis. and simulations of workspace for both the arms. It is followed by MATLAB simulation images of the arms in 3D view as well as in the XY plane. From the simulations it is inferred that the blue color portion marked in the simulation results is identified as the area of the workspace in which the robot arm can move with the major influence on the dimensions of workspace is exerted by the dimensions of links of the robots and the mechanical limitations of the joints. Thus, looking at the whole workspace of both the arms created together, the geometrical structure of the workspace turns out to be a sphere. Infering from 5dof manipulator’s workspace, it gives the possibility of mechanism optimization and the interaction process optimization. The last two figures in the table are the plotting of the path trajectories of both the Right and Left arms with the calculation of their position, velocity and acceleration of each. These path trajectories trace the path by the end-effector of the manipulator to access a specific point. Conclusion This paper has presented a detailed kinematic analysis for the two 5-dof Amaranthine (INMOOV) Humanoid Robot arms. The Denavit-Hartenberg Parameters for each serial chain, accurate length parameters, and joint angle limits were given. The 5-dof forward kinematics solutions were developed, with analytical results. It is observed that the workspaces for both arms are the mirror images of one and another. The path and trajectory for both the arms were plotted in MATLAB and was observed that they were also mirror images of each and other and on the other hand the position, velocity and acceleration graphs were the same for both the arms. References 1. INMOOV website, http://inmoov.fr/ to study the .STL files and to study different parts of the robot assembling and build. 2. Human-Robot Interfaces for Interactive Receptionist Systems and Wayfinding Applications, https://www.researchgate.net/publication/327714444_Human-Robot_Interfaces_for_ Interactive_Receptionist_Systems_ and_Wayfinding_Applications. 3. InMoov Humanoid Robot, http://eps.novia.fi/assets/Sidor/2/1545/InMoov-Humanoid-spring2019-Final-report.pdf. 4. Fu, K. S., Rafael C. Gonzalez, and C. S. G. Lee, 1987, Robotics: Control, Sensing, Vision, and Intelligence. CAD/CAM, Robotics, and Computer Vision. New York: McGraw-Hill. 5. MyRobotLab. http://myrobotlab.org/. 6. J.J. Craig, 2005, Introduction to Robotics: Mechanics and Control, Third Edition. Upper Saddle River, NJ: Pearson Prentice Hall. 7. S. Cremer, L. Mastromoro, and D.O. Popa, 2016, “On the Performance of the Baxter Research Robot,” IEEE International Symposium on Assembly and Manufacturing (ISAM), August.

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8. J. Denavit and R.S. Hartenberg, 1955, A Kinematic Notation for Lower-Pair Mechanisms Based on Matrices, Journal of Applied Mechanics: 215-221. 9. Z. Ju, C. Yang, Z. Li, L. Cheng, and H. Ma, 2014, “Teleoperation of Humanoid Baxter Robot using Haptic Feedback,” International Conference on Multisensor Fusion and Information Integration for Intelligent Systems (MFI 2014), Beijing China, September. 10. D.L. Pieper, 1968, “The Kinematics of Manipulators Under Computer Control,” PhD thesis, Stanford University, Department of Mechanical Engineering. 11. Rethink Robotics, 2016, “Baxter Research Robot: Technical Specification Datasheet & Hardware Architecture Overview.” 12. e Silva, T.M. Tennakoon, M. Marques, and A.M. Djuric, 2016, “Baxter Kinematic Modeling, Validation, and Reconfigurable Representation,” SAE Technical Paper 2016-01-0334. 13. D.E. Whitney, 1969, Resolved Motion Rate Control of Manipulators and Human Prostheses, IEEE Transactions on Man-Machine Systems. 14. C. Yang, H. Ma, and M. Fu, 2016, “Robot Kinematics and Dynamics Modeling,” Chapter 2 in Advanced Technologies in Modern Robotic Applications, 27– 48.

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 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0016

Additively Manufactured RF Devices for 5G, IoT, RFID, WSN, and Smart City Applications Yepu Cui*, Eui Min Jung, Ajibayo Adeyeye, Charles Lynch, Xuanke He and Manos Tentzeris School of Electrical and Computer Engineering, Georgia Institute of Technology, 85 5th St NW, Atlanta, Georgia 30308, USA *[email protected]

With the development of inkjet-/3D-/4D-printing additive manufacturing technologies, flexible 3D substrate with complex structures can be patterned with dielectric, conductive and semi-conductive materials to realize novel RF designs. This paper provides a review of state-of-the-art additively manufactured passive RF devices including antennas and frequency selective surfaces (FSS), couplers, where origami-inspired structure enables unprecedented capabilities of on-demand continuous frequency tunability and deployability. This paper also discusses additively manufactured active RF modules and systems such as inkjet printed RF energy harvester system with high sensitivity and efficiency for Internet of Things (IoT), smart cities and wireless sensor networks (WSN) applications, inkjet-printed RF front ends, and inkjet-printed mm-wave backscatter modules. Keywords: additive manufacturing; inkjet printing; 3D printing; origami; coupler; frequency selective surface; antenna; energy harvester; backscatter; 5G; IoT; RFID; smart city

1. Introduction With the exponential growth of 5G enabled devices such as smartphones, self- driving cars, internet of things (IoT), smart cities, wireless sensor networks (WSN), etc., additive manufacturing technologies (AMT) have drawn great attention in recent years for their ability to dramatically lower the fabrication cost by using minimal amount of materials, reducing set-up time, and utilizing inexpensive substrates [1,2]. Making it an ideal process to realize wireless devices over traditional fabrication methods which generally involve chemical etching. Inkjet printing is one of the commonly used AMT to realize electronic devices due to its ability to selectively deposit a variety of materials onto flexible substrates to create 2D or 2.5D patterns. With 3D printing technology, complex geometry can be realized in a layer-by-layer manner with high resolution using flexible or rigid materials. In the past few years, the concept of combining inkjet printing technology with 3D printing technology has attracted notable attention for its potential to produce fully additively manufactured mm-wave high-performance RF modules and systems with conformal structures, reconfigurability and deployability. *Corresponding

author.

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This paper provides a review of state-of-the-art additively manufactured RF devices for a variety of wireless applications. Section 2 discusses passive RF designs fabricated using AMT, including hybrid printed shape-changing tunable mm-wave origami-inspired frequency selective surfaces (FSS), a 3D printed “Kirigami” inspired deployable mm-wave dielectric reflectarray antennas, as well as an inkjetprinted Lange couplers with 2.5D structures. Section 3 discusses additively manufactured active RF modules and systems including an inkjet printed full-FMband quasi-isotropic kilometer-range energy harvester, an inkjet printed low-cost backscatter front end, and a mm-wave inkjet printed backscatter module for IoT applications. Section 4 summarizes and concludes the paper. 2. Additively Manufactured Passive RF Devices 2.1. Origami-inspired tunable and deployable structures The ever-growing number of mobile devices is pushing network providers and authorities to allocate more frequency bands to fulfill the continuously increasing data traffic. Therefore, RF devices for the next generation communication systems need to be able to tune the frequency response adaptively over a wider frequency band. Traditionally, tunable RF devices are realized by active components such as diodes or switches [3] that can provide fast response. However, active components can be bulky, expensive, fragile and difficult to design. Therefore, origami-inspired RF structures have attracted a lot of attention in recent years due to their ability to tune the resonance frequency mechanically by folding or unfolding the substrate [4,5]. Origami-inspired foldable structure also enables the possibility of deployable devices for space-limited extraterrestrial and terrestrial applications. 2.2. Hybrid printed origami-inspired frequency selective surfaces Traditional fabrication processes to realize origami-inspired RF designs commonly use paper as substrate, which involves labor-intensive manual cutting and folding that dramatically limit the durability and accuracy for real life and mm-wave applications.

Fig. 1. Fabrication process for hybrid printed origami FSS [6].

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Fig. 2. Prototypes of hybrid printed Miura-Ori FSS: single-layer configuration (left), multi-layer configuration (right) [7] mm-wave frequency bands.

AMT such as inkjet printing and 3D printing provide an effective toolkit to realize origamiinspired RF designs. Y. Cui et al. [6] presents a hybrid printing process shown in Fig. 1 combing 3D printing and inkjet printing technologies to realize complex origami-inspired tunable FSS. With 3D printing technology, an origami substrate can be printed as a single sheet of flexible photopolymer, demonstrating good strength and durability. With inkjet printing technology, 3D printed surface can be modified with SU-8 dielectric material and then metalized with highresolution silver nanoparticle (SNP) patterns. The hybrid printed origami FSS can be realized in both single- [6] and multi-layer [7] configurations based on the application scenarios. The prototypes in Fig. 2 have shown promising performance in 5G. 2.2.1. “Kirigami” inspired mm-wave dielectric reflectarray antenna With high resolution stereolithography (SLA) 3D printing technology and flexible photopolymers, origami-inspired structures can be introduced to dielectric based RF designs to enable deployability to save space. Y. Cui et al. [8] proposed a “Kirigami” inspired

 

(a)

(b)

Fig. 3. Prototype of the “Kirigami” dielectric reflectarray antenna: (a) deployed, (b) retracted [8].

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mm-wave dielectric reflectarray antenna design with flat foldable unit cells featuring an unprecedented reduction in volume as compared to conventional solid block unit cells. The design can be folded to 33% of the full-scale volume as shown in Fig. 3. 2.3. Inkjet printed 2.5D Lange coupler To evaluate inkjet printing technologies for packaging applications, initial simple RF structures were created to evaluate inkjet printed RF structures. A good technology demonstrator is the Lange coupler [9]. Lange couplers are quadrature couplers which offer equal power splitting and 90 degree phase shift and at a larger bandwidth compared to branchline quadrature couplers, making them a versatile component for wireless communication networks. A defining trait of Lange couplers is the interdigitated fingers which connect the separate branches of the ports. These connections are typically fabricated in multilayer structures using vias or using bond wires which arch over other fingers of the coupler. These come with a few drawbacks. For multilayer structures, the dielectric loading effect will introduce more loss, and for wirebonds, the exposed wire creates an area of potential mechanical failure. These fabrication methods requires multiple tools and fabrication steps which increase the manufacturing time and cost. With inkjet printing, the fabrication process is drastically simplified into one tool — the inkjet printer. Inkjet-printed dielectrics can form a 2.5D small ramp structures in lieu of bondwires or vias, creating a crossover path. The all inkjet-printed Lange coupler is shown in Fig. 4 and the measured results are shown in Fig. 5, demonstrating a good 3 dB power split and 90 degree phase shift. SNP ink is used as the conductor layer while SU-8 photoresist is used to create the ramp structure. The measurement has good input matching along its bandwidth, and equal power split of 1 dB imbalance between both ports from 5.4 to 11.4 GHz, with near identical split between 5.8 GHz to 9.7 GHz. Figure 5 also shows the phase difference between the two ports, showing that there is 90 degree phase shift along the same frequency range.

 

(a)

(b)

(c)

Fig. 4. Fully inkjet-printed Lange coupler on RO4003C with resistive isolation termination. (a) Size comparison, (b) crossover connections, and (c) full view [9].

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(a)

167

(b)

Fig. 5. (a) Lange coupler S-parameters demonstrating a close agreement with the measured and simulation results with around 1 dB difference between the measurement and simulation. (b) Phase shift between the through and coupled ports shows a close proximity to 90 degrees around its designed frequency of 8 GHz. At higher frequencies, the tapering phase difference naturally deviates from 90 degrees [9].

3. Additively Manufactured Active RF Modules and Systems 3.1. Full-FM-Band, quasi-isotropic, kilometer-range energy harvester E. M. Jung et al. [10] demonstrated that aggregating power from all nearby broadcasting towers is possible with a full-FM-band, omnidirectional harvesting system. Not requiring careful alignment to the most prominent source makes the system well suited for massdeployment applications such as precision agriculture and structural health monitoring. As much as 923µW was harvested at 1.54km away from the nearest tower. 29% antenna FBW (fractional bandwidth), 2.0dBi realized gain, 23% matching network FBW, 56% RF-to-dc η (efficiency), and -17dBm sensitivity (-11dBm for cold-start) were achieved. It is capable of harvesting outside ambient FM energy indoors to power a wireless sensor node without needing to periodically shut down. This section describes the matching network and the rectifying circuit which were fabricated using inkjet printing. 3.1.1. Matching network using inkjet printing The matching network and the rectifying circuit were fabricated using an MG Chemicals 555 FR4 (flame retardant 4) substrate (35µm double-sided copper cladding, 1.6mm FR4 laminate, = 4.2 at 1GHz, δ = 0.015 at 1GHz). SU-8 photoresist was ink-jet printed using a Fujifilm DMP-2850 printer to form a masking layer for the pad layout. The pattern was etched in a ferric chloride bath. The backside copper was protected to form a ground plane. Via holes were drilled and copper rings were inserted to form connections. Components were soldered on to the board. Figure 7 shows a fabricated sample of the matching network and the rectifying circuit. Anritsu MS46522B VNA (vector network analyzer) was used to measure the S11 of the matching network. Two of the lumped elements were replaced with ones that have different values after this initial measurement in order to shift the S11 dip from lower to higher

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frequencies so that it aligns with the FM broadcasting band. Later samples showed that using impedance measurement of the diodes in the simulation rather than diode model reduces the simulation-measurement discrepancy and the need for post-fabrication adjustments. The measured S11 of the matching network is shown on Fig. 6. At an input power level of -20dBm, the S11 is < -10dB across the FM broadcasting band. The -10dB matching FBW for the matching network is 23% at -20dBm. Even at -10dBm, the maximum S11 is approximately -10dB within the band. At 0dBm, the S11 is < -10dB for the majority of the band, and the maximum S11 is approximately -8dB within the band. A 3.3kΩ resistor was connected to the output of the rectifier to represent the PMU (power management unit). Noticeable differences between the simulation and measurement results exist, especially at -20dBm where two distinct resonance points are visible in the simulation result but not in the corresponding measurement result. The is due to the post-fabrication adjustments described earlier. 3.1.2. Rectifying circuit fabricated using inkjet printing Rectifier measurements were performed by connecting a Rohdes & Schwarz SMJ100A vector signal generator to the input of the matching network, connecting a resistor to the output of the rectifier, and measuring the voltage across the resistor with an Agilent 34401A multimeter. Figure 8 shows the η and the sensitivity of the rectifier with respect to frequency. The flatness of the curves indicate the consistency of the rectifier’s performance across the FM frequency band. Maximum η of 17%, 40%, and 56% are respectively achieved at -20dBm, -10dBm, and 0dBm.

Fig. 6. S11 of the matching network with a 3.3kΩ load [10].

Fig. 7. A photograph of the matching network and the rectifier [10].

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Fig. 8. Rectifier η and sensitivity with respect to frequency. 3.3kΩ load [10].

(The minimum η are respectively 14%, 31%, and 42%.) Discrepancies between the simulation and measurement results primarily originate from the simulation measurement discrepancies in the matching network, since the input power to the rectifier is fed through the matching network. The input requirement to operate the PMU is 100mV and 5µW (330mV and 15µW for cold-start). With a 3.3kΩ resistor connected to the output of the rectifier, this requirement translates to 129mV (330mV for cold-start). Sensitivity was measured by finding the input power level which produces this output voltage. The best and worst sensitivity were respectively measured to be -17dBm and -16dBm (-11dBm and -10dBm for cold-start). Figure 9 shows the η and the output voltage of the rectifier with respect to the matching network input power. The η increases as the input power increases, because the efficiency of HSMS285B improves from -20dBm to 0dBm [11]. Optimizing the matching network while setting the input power to 0dBm instead of -20dBm would further improve the η beyond 56% but would compromise sensitivity.

Fig. 9. Rectifier η and output voltage with respect to the matching network input power. 3.3kΩ load [10].

Fig. 10. Rectifier η with respect to varying load resistance [10].

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Figure 10 shows the η of the rectifier with respect to varying load resistance. It indicates the rectifier’s ability to cope with fluctuating load resistance. The highest η are achieved with 3.3kΩ and 10kΩ. The η starts to decrease with 1kΩ and 33kΩ but still maintains double-digit values at -10dBm and 0dBm. 3.2. Inkjet printed RF front ends for low-cost backscatter modules 3.2.1. Low form factor UHF backscatter front end The development of backscattering front ends that can function in harsh environments is essential for man sensing applications. Here, a low-cost, ultra-low power and ultra-light weight backscatter front-end is presented operating in the 915 MHz UHF (ultra high frequency) band that shows desirable performance when operated in very close proximity to a large metal plate which is known to degrade RF performance. The modulator front end consists of an antenna, a transistor and a pair of RF-DC isolation inductors. The device is designed such that it has best performance when placed orthogonally with respect to a metal plane. In order to achieve this characteristic, a Yagi-Uda antenna configuration is employed with a meandered dipole used as the driven element so that the metal plane can function as a reflector for the chosen antenna. An RF low-noise field effect transistor (FET) is selected as the switching mechanism to enable load modulation between open and short circuit, thus the arms of the dipole are connected to the drain and source pins of the transistor. This particular transistor is selected due to its favorable properties such as extremely low input gate capacitance and low gate-to-source current leakage, so that the overall power consumption of the switch (evaluated to be 0.416 µW at 1 MHz) is low. The material on which the device is manufactured plays an important role in its overall form factor and since the goal here is to make the device ultra-light and flexible. The substrate XT/duroid 8000 from Rogers Corporation is chosen. The substrate is 50 µm thick and has a permittivity of 3.23 with loss tangent of 0.0035. Due to the thinness of the substrate, conventional means of manufacturing prove unsuitable, hence an inkjet masking procedure where Mirochem SU-8 is inkjet printed onto the copper clad surface of the substrate. The SU-8 behaves like a positive photoresist so that the portions of the copper not covered by

Fig. 11. Flexible profile of the fabricated device [12].

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Fig. 12. Device mounted vertically on metal plane [12].

SU-8 are etched away using an iron-chloride solution. The result is a simple, lightweight (0.25g) and extremely low-power backscatter modulator operating in the 915 MHz band and capable of delivering -67 dBm of received power at a distance of 1 m while mounted on a metal sheet [12]. 3.2.2. mm-Wave inkjet-printed backscatter modules for IoT applications In recent years, there has been a significant increase in the utilization for RFID (radiofrequency identification) technology in IoT applications. This increased development and usage of this technology is due to the low manufacturing costs and low-power consumption. However, these RFID systems typically operate in the UHF band which inherently has limitations on the available bandwidth of operation and requires large bulky reader and tag systems. Thus, in an effort to increase the available bandwidth while designing more compact system architectures, research and development of millimeterwave identification (mmID) tags has become more extensive. P. Pursula et al. [13] presented the feasibility and demonstration of replacing RFID technology with mmID technology. Furthermore, the authors propose the use cases of high-data-rate communications and a mmID being interrogated with automotive radar modules for tracking purposes. Further demonstration of highdata-rate communication on the order of gigabit per second was demonstrated by J. Kimionis et al. [14]. Additionally, the proposed mmID tag was additively manufactured on 7 mil flexible liquid crystal polymer (LCP) substrate ( 0.002), inkjet-printed with SNP, operating at 24 GHz, and can be viewed in Fig. 13. Therefore, making this system ideal for short range high-data rate communication for wearable devices. Another application that is highly attractive application of this mmID technology is localization and spatial identification of miniaturized tags. This is made possible through the utilization of frequency-modulated continuous wave (FMCW) radar modules for the reader of these mmID systems. As presented by A. O. Adeyeye et al. [15], high fidelity

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Fig. 13. Inkjet-printed mmID for high data rate communication [14].

 

(a)

(b)

Fig. 14. (a) mmWave Miniaturized tag layout for IoT localization applications. (b) Perspective view of mmWave Miniaturized tag for IoT localization applications [15].

spatial localization of a miniaturized mmID tag is presented. The fully integrated tag was fabricated on a flexible LCP substrate ( 3.14, tan(δ) = 0.0025) with a thickness of 180 µm through the same inkjet-printed masking procedure described in Sec. 3.2.1. In Figs. 14(a) and 14(b), one can view the circuit layout and a perspective view of the miniaturized mmID. As stated previously, this proposed tag was localized at a maximum range of 0.3 m with a standard deviation of 1.02 cm. The tag response on the FMCW radar can be viewed in Fig. 15 with the tag response and the clutter of the environment labeled. The primary benefit of modulating the transmitted radar chirp signal back to the reader is the signal-to-noise ratio (SNR) that can be achieved. Clutter near the DC component of the received spectrum is generated through nearby reflectors and self-interference between the transmitter and receiver of the radar module. Through backscatter modulation, the frequency component that encapsulates the ranging information is shifted up in frequency away from this system noise. This miniaturized, flexible mmID displays great potential for

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Fig. 15. Received signal spectrum displaying miniaturized tag response [15].

future applications of localized sensing particularly with the spatial identification of biosensors and other IoT tracking applications. 4. Conclusion This paper has reviewed recent advances of both passive and active RF devices as well as RF systems realized with additive manufacturing processes including inkjet printing, 3D printing, and hybrid printing technologies. The utilization of AMT enables unprecedented capabilities of realizing flexible electronics, conformal electronics, zero-power systems, and mechanically reconfigurable devices in a lowcost and environmentally friendly manner. With high resolution and scalability, AMT can find tremendous potential in numerous future wireless applications such as 5G, IoT, RFID, WSN and smart cities. Acknowledgment The authors would like to thank National Science Foundation (NSF) for supporting this work. References 1. J. G. Hester et al., “Additively Manufactured Nanotechnology and Origami-Enabled Flexible Microwave Electronics,” Proceedings of the IEEE, vol. 103, no. 4, pp. 583–606, 2015, doi: 10.1109/JPROC.2015.2405545. 2. A. Eid et al., “Inkjet-/3D-/4D-Printed Perpetual Electronics and Modules: RF and mm-Wave Devices for 5G+, IoT, Smart Agriculture, and Smart Cities Applications,” IEEE Microwave Magazine, vol. 21, no. 12, pp. 87–103, 2020, doi: 10.1109/MMM.2020.3023310. 3. P. W. Wong and I. Hunter, “Electronically Tunable Filters,” IEEE Microwave Magazine, vol. 10, no. 6, pp. 46–54, 2009, doi: 10.1109/MMM.2009.933593. 4. S. Yao, Y. Bonan, Y. Shafiq and S. V. Georgakopoulos, “Rigid Origami Based Reconfigurable Conical Spiral Antenna,” 2018 IEEE International Symposium on Antennas and Propagation USNC/URSI National Radio Science Meeting, Boston, MA, 2018, pp. 179–180, doi: 10.1109/ APUSNCURSINRSM.2018.8608655.

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5. S. I. H. Shah, M. M. Tentzeris and S. Lim, “Low-Cost Circularly Polarized Origami Antenna,” IEEE Antennas and Wireless Propagation Letters, vol. 16, pp. 2026–2029, 2017, doi: 10.1109/ LAWP.2017.2694138. 6. Y. Cui, S. A. Nauroze and M. M. Tentzeris, “Novel 3D-Printed Reconfigurable Origami Frequency Selective Surfaces With Flexible Inkjet-Printed Conductor Traces,” 2019 IEEE MTT-S International Microwave Symposium (IMS), Boston, MA, USA, 2019, pp. 1367–1370, doi: 10.1109/MWSYM.2019.8700994. 7. Y. Cui et al., “A Novel Additively 4D Printed Origami-inspired Tunable Multi-layer Frequency Selective Surface for mm-Wave IoT, RFID, WSN, 5G, and Smart City Applications,” 2021 IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, USA, 2021. 8. Y. Cui, S. A. Nauroze, R. Bahr and E. M. Tentzeris, “3D Printed One-shot Deployable Flexible “Kirigami” Dielectric Reflectarray Antenna for mm-Wave Applications,” 2020 IEEE/MTT-S International Microwave Symposium (IMS), Los Angeles, CA, USA, 2020, pp. 1164 –1167, doi: 10.1109/IMS30576.2020.9224010. 9. X. He and M. M. Tentzeris, “Inkjet Printed Lange Coupler for Antenna Systems,” 2019 IEEE International Symposium on Antennas and Propagation and USNC-URSI Radio Science Meeting, Atlanta, GA, USA, 2019, pp. 91–92, doi: 10.1109/APUSNCURSINRSM.2019. 8889138. 10. E. M. Jung et al., “A Wideband, Quasi-Isotropic, Kilometer-Range FM Energy Harvester for Perpetual IoT,” IEEE Microwave and Wireless Components Letters, vol. 30, no. 2, pp. 201– 204, 2020, doi: 10.1109/LMWC.2019.2957653. 11. C. H. P. Lorenz et al., “Breaking the Efficiency Barrier for Ambient Microwave Power Harvesting With Heterojunction Backward Tunnel Diodes,” IEEE Transactions on Microwave Theory and Techniques, vol. 63, no. 12, pp. 4544–4555, 2015, doi: 10.1109/TMTT.2015. 2495356. 12. Adeyeye, A., Y. Cui, A. Eid, J. Hester and M. Tentzeris, “A Winning Backscatter Modulator: A Quarter-Gram, Ultrahigh-Frequency RFID for On-Metal Operation,” IEEE Microwave Magazine, vol. 21, no. 3, pp. 96–100, 2020. 13. P. Pursula et al., “Millimeter-Wave Identification—A New Short-Range Radio System for Low-Power High Data-Rate Applications,” IEEE Transactions on Microwave Theory and Techniques, vol. 56, no. 10, pp. 2221–2228, 2008, doi: 10.1109/TMTT.2008.2004252. 14. J. Kimionis, A. Georgiadis and M. M. Tentzeris, “Millimeter-wave backscatter: Aquantum leap for gigabit communication, RF sensing, and wearables,” 2017 IEEE MTT-S International Microwave Symposium (IMS), Honololu, HI, 2017, pp. 812–815, doi: 10.1109/MWSYM.2017. 8058702. 15. A. O. Adeyeye, J. Hester and M. M. Tentzeris, “Miniaturized Millimeter Wave RFID Tag for Spatial Identification and Localization in Internet of Things Applications,” 2019 49th European Microwave Conference (EuMC), Paris, France, 2019, pp. 105–108, doi: 10.23919/ EuMC.2019.8910740.

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0017

QDC-FET and QD-SWS Physics-Based Equivalent Circuit for ABM Simulations R. Mays,* R. H. Gudlavalleti,* B. Khan*, B. Saman,*,† J. Chandy,* Evan Heller‡ and F. Jain*,§ *Department

of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA of Electrical Engineering, Taif University, Taif, Saudi Arabia ‡Synopsys Inc., Ossining NY, USA §[email protected]

†Department

This paper investigates physics based equivalent circuits for spatial wavefunctions switched (SWS) field-effect transistors (FETs). This will lead to improved analog behavioral models (ABMs) for 2-bit/4-state logic gates, SRAMs, and registers. Model parameters related to 65 nm technology were used to simulate ID-VD characteristics, transconductance g m and channel conductance g D using Cadence. SWSFET physics based analytical equations were used to simulate using MATLAB SIMULINK and compare with Cadence simulations. Equivalent circuit utilizes different values of equivalent oxide thickness for the lower W2 and upper W1 quantum well channels. The methodology is similarly applicable to two-channel quantum dot FET. The methodology can be further extended to model and simulate multiple channel SWS-FET devices. Keywords: SWSFETs; quantum dots; QDC; QD-SWS

1. Introduction SWS-FETs having three quantum well channels in MOS and MOS-gate MODFETs have been recently reported [1]. They have the potential to be implemented in the design and fabrication of 3-bit logic gates with about 50% less device count than conventional CMOS multi-valued logic (MVL) devices. The two-quantum dot channel SWS-FETs have been fabricated [2] as shown in Fig. 1(a), and their experimental ID-VD characteristics are given in Fig. 1(b). As the gate voltage is increased, electrons first appear in the lower quantum dot channel connected to drain D2. Drain D2, referred to as the deep drain, has electrical access to the lower two layers of SiO2-cladded Si quantum dots. The drain current in the QD-1 channel increases until the electrons start tunneling to the upper channel QD-1, which is comprised of the upper two quantum dot layers. For a range of VG , the electrons are in both channels. Finally, all electrons transfer to the upper QD-1 channel.

§Corresponding

author.

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Fig. 1(a). 3-D schematic of a SWS-FET with two quantum dot channels.

Fig. 1(b). Drain current (ID) and voltage (VD) characteristics.

2. Background Physics-based Equivalent Circuits SWS-FETs have been modeled using Analog Behavioral Model (ABM) [3]. This model takes the various VTH values and utilizes them in a BSIM based model for logic gates, half, and full adders. We present in this paper a physics based equivalent circuit to simulate SWS channels QD2/W2 and QD1/W1 by defining threshold VTH values depending on the carrier locations in well W2, in both wells W2 and W1, and finally in well W1. Figure 2 highlights the intrinsic model in yellow showing current source gm*VGS, output resistance gSD=1/rd and four capacitances CGS, CGD, CBS and CBD for an N-FET. The gate capacitance CG components CGS, CGD, and gmVGS current source, gSD are VGS and VDS dependent.

Fig. 2. QDC-FET equivalent circuit model including extrinsic parasitic capacitances over intrinsic model. The model is more complex in Cadence nodes (65nm or lower).

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3. Physics based SWSFET Equivalent Model One of the aims for the model was to explore the possibility of relating the parameters presented in Fig. 2 as a function of carrier location. For example, when carriers in are W2/QD-2, Cox is different as the gate is not only separated by d, the tunnel oxide thickness but also by the thickness of the quantum well W2 or QD-2. The dielectric constant of SiOxSi QD is about 8 (and 12 for GeOx-Ge dots). Therefore, CG is different, and we can estimate it by using the well 2 oxide capacitance, expressed by Coxw2= (’ox*o)/(dTunnel + 4nm*2 top Si QD). This allows for the writing of the gate capacitance and drain current of well 2: .

Additionally, the gate capacitance can be written generally as where

and

Similarly,

. From a cursory view, this appears

to be greater than Coxw2 as expressed above. Moreover,

. The drain current change will

be higher in W1. . This appears to be greater than CgW2 as seen in

This gives the expression above.

Another area of exploration is gm, the slope of ID-VG, which changes as a function of VDS and VGS. CASE I. The generic intrinsic equivalent circuit (Fig. 2) is modified when carrier are in state (01) in bottom channel W2. This is shown in Figs. 3(a) and 3(b). .

This gives

.

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CASE II. The intrinsic equivalent circuit is shown in Fig. 3(b) when we are in state (11) or (10) in upper channel. This gives

. This appears to be greater than CgW2.

Similarly, gmW1 is higher. . This appears to be greater than Coxw2. . The drain current change will be higher in W1.

Fig. 3(a). Electron in Channel W2/QD-2 in a SWS-FET equivalent circuit model.

Fig. 3(b). Electron in Channel W1/QD-1 in a SWS-FET equivalent circuit model.

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CASE III. In this case, both channels are occupied (11). Now the capacitance and gm values are somewhere between the two above cases. This is illustrated in Fig. 4.

Fig. 4. Electrons in both Channels W2/QD-2 and W1/QD1. That is, tunneling from W2 to W1. SWS-FET equivalent circuit model.

4. Cadence Simulation In this section, we present SWS-FET characteristics based on 65nm technology model parameters. Figure 5 shows the drain current as a function of gate voltage when electrons are in lower channel W2/QD2 and in upper channel W1/QD1. The parameters are listed in Table 1.

Fig. 5. Drain current as a function of gate voltage in lower and upper SWS channels.

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Parameter

Description-Process related Parameters

Nominal value

TOX

Electrical gate equivalent oxide thickness

2E-9

Unit m

TOXU

Effective Electrical gate equivalent oxide thickness from upper channel to gate

10E-9*

m

TOXL

Effective Electrical gate equivalent oxide thickness from lower channel to gate

18E-9*

m

U0

Low-field mobility for upper channel

215.93648

cm2/(Vs)

VthL

Threshold voltage at Vbs = 0 (Lower channel)

0.31803

V

VthU

Threshold voltage at Vbs = 0 (Upper channel)

0.61

V

CGSO

Non LDD region gate-source overlap capacitance per unit W

5.725430e-11

F/m

CGDO

Non LDD region gate-drain overlap capacitance per unit W

5.725430e-11

F/m

CJS CJD

Bottom junction capacitance per unit area at zero bias

CJN=1.2700e-003 CJD=CJS

F/m²

CJSWS CJSWD

Gate-edge sidewall junction capacitance per unit length

CJSWN=6.4000e-011 CJSWD=CJSWS

F/m

CJSWGS CJSWGD

Isolation-edge sidewall junction capacitance per unit area

CJSWGN=3.0500e-10

F/m

*The oxide cladding layer thickness is 2nm that results in 4nm for one layer of Si quantum dots and 8nm for two layers of Si quantum dots.

The transconductance plots for channel W2 and channel W1 are shown in Figs. 6(a) and 6(b), respectively. During conduction in lower channel W2/QD2, the transconductance peaks and goes down in magnitude after the peak current. This is due to tunneling of electrons to the upper channel W1/QD1 as the gate voltage is increased. This is a unique feature attributed to SWS-FETs.

Fig. 6(a). Transconductance as a function of gate voltage.

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The gm characteristics in upper channel (Fig. 6b) is similar to conventional FETs.

Fig. 6(b). Transconductance gm as a function of gate voltage in upper channel W1.

Figure 7 shows the channel conductance gD for the lower and upper channels. Figure 7(a) shows channel conductance gD when electrons are in lower channel along with the drain current ID. Channel conductance gD for the upper W1 channel and drain current are shown in Fig. 7(b).

Fig. 7(a). Channel conductance gD for the lower W2 channel.

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Fig. 7(b). Channel conductance gD for the upper W1 channel.

5. SIMULINK Simulation Based on the equations presented in section 3 for CGsW2 and CGSW1, a mathematics approach towards determining whether CGSW1 was greater than CGsW2 was completed. Table 2 denotes the parameters utilized for this simulation. Table 2. The table of relevant parameters used for the Simulink simulation. Parameter

Description

Units

Value

VGS

Gate-Source Voltage

V

0-1.5

VTO (Well 2)

Well 2 Threshold voltage

V

0.3

VTO (Well 1)

Well 1 Threshold voltage

V

0.61

VDS

Drain-Source Voltage

V

1.2

VUL

Transition Voltage

V

0.55

TOXL

Effective gate thickness from gate to lower channel

nm

18

TOXU

Effective gate thickness from gate to upper channel

nm

10

W/L

Width/Length ratio

-

120/88

εSi

Relative permittivity of Silicon

-

11.7

εSiOx

Relative permittivity of Silicon Dioxide

NA

Doping Concentration

Φf Tox

-

3.9

cm-3

2x1016

Surface Potential

V

.849

Thickness of tunnel Oxide

nm

2

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In principle, solving for the capacitance in this regard calls for the surface potential Φf, the threshold voltage VTH, the flat-band voltage VFB, and the channel to body voltage, which is dependent on whether the device is in accumulation mode [3]. Φf was determined by the following equation

where k is Boltzmann’s constant, T is the ambient temperature of 300 K, q is the charge of the electron, and ni is the concentration of intrinsic silicon. This is utilized in part to calculate the flatband voltage, which is determined by

where COX is determined via the equations mentioned previously, and VSB was taken to be zero for these calculations. Determining the depletion width was done via the equation

where νc is the aforementioned channel to body voltage, which is equal to VGS-VFB when VGS -VTH is greater than 2Φf and 0 otherwise. Using this relation for the depletion width, the depletion capacitance, and by proxy, Cgsw can be calculated. Based on these equations and parameters, the following graph was produced.

Fig. 8. The Simulation of CGS of well 1 and well 2 vs VGS. A time ramp from 0 to 1.5 was utilized to represent the increasing VGS for this simulation.

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It can be seen from this figure that CGS for well 1 does indeed exceed the capacitance for CGS of well 2 by more than double. In calculating the transconductance for each of the wells, the ID-VG curves of the wells needed to be calculated. The equations above in section 1 for calculating ID were utilized for this calculate

for the cases of cutoff, linear, and saturation respectively. However, due to the current going through well 2 being dependent on well 1, a matching parameter is included in the threshold value for the ID calculations for well 2, namely

where VUL is the transition voltage, that is, where the current begins to transition to the upper well. From this, for the ID calculations for well 2 requires the threshold voltage to become 𝑉 → 𝑉 𝛼 based on this, the ID-VG curves for the two well system were created. Utilizing the data produced in Fig. 9, the transconductance (gm) was calculated via applying a derivative to this data, which yielded the following:

Fig. 9. The Simulation of ID vs VG for both Well 1 & Well 2.

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Fig. 10(a). The transconductance of the lower well (Well 2), as a function of VG .

Fig. 10(b). The transconductance of the upper well (Well 1), as a function of VG .

It should be noted that, despite the numerical values being different between these simulations and the simulations presented in the previous section, that the general trends are the same, giving further credence to the assertion that the capacitance in well 1 is indeed greater than that of well 2. 6. Conclusions We have shown a physics-based equivalent circuit simulations of the two-channel SWSFETs. The results prove promising for simulating quantum well or quantum dot based channels. Work is in progress to correlate the threshold voltages used with the quantum

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simulations [4]. Additionally, we plan to verify our model for SWS-FETs used as access transistors in 2-bit SRAMs [5] and 2-bit DRAMs [5]. Acknowledgments This paper is based on SWS-FET and quantum dot FET research carried out by the support of completed grants including Office of Naval Research contracts (N00014-02-1-0883 and N00014-06-1-0016), and National Science Foundation grants (NER and ECS 0622068). Authors gratefully acknowledge the support of Dr. Pik-Yiu Chan (UCONN) for the fabrication of QD-SWS twin-drain FETs. References 1. F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Low-Threshold II-VI lattice-matched SWS-FETs for Multi-Valued low-power logic. Journal of Electronic Materials, 50, 2618–2629, 2021. 2. F. Jain, M. Lingalugari, B. Saman, P.-Y. Chan, P. Gogna, E.-S. Hasaneen, J. Chandy and E. Heller, Multi-State Sub-9 nm QDC-SWS FETs for Compact Memory Circuits. 46th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego (CA), 2–5 December 2015. 3. B. Saman, P. Gogna, E.-S. Hasaneen, J. Chandy, E. Heller and F. C. Jain, Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation, International Journal of High Speed Electronics and Systems, 26, 1740009, 2017. 4. F. Jain, M. Lingalugari, J. Kondo, P. Mirdha, E. Suarez, J. Chandy and E. Heller, Quantum Dot Channel (QDC) FETs with Wraparound II-VI Gate Insulators: Numerical Simulations. Journal of Electronic Materials, 45, 5663, 2016. 5. R. H. Gudlavalleti, B. Saman, R. Mays, E. Heller, J. Chandy and F. Jain, A Novel Peripheral Circuit for SWSFET based Multivalued Static Random-Access Memory, International Journal of High Speed Electronics and Systems, 29, 2040010 (2020).

 2022 World Scientific Publishing Company https://doi.org/10.1142/9789811242823_0018

Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic F. Jain*, R. H. Gudlavalleti*, R. Mays*, B. Saman†, J. Chandy* and E. Heller‡ *Department

of Electrical and Computer Engineering, University of Connecticut, Storrs, CT, USA of Electrical Engineering, Taif University, Taif, Saudi Arabia ‡Synopsys Inc., Ossining NY, USA *[email protected]

†Department

Multi-state room temperature operation of SiOx-cladded Si quantum dots (QD) and GeOx-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (~1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density nQM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multibit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing. Keywords: 4.2K FET model; quantum dot FETs; SWS-FETs

1. Introduction An array of thin oxide barrier/cladding (~1nm) on quantum dots (3-5nm) forms a quantum dot superlattice (QDSL). SiOx-Si and GeOx-Ge QDSLs have exhibited an order or more separation between mini-energy bands than observed in conventional GaAs-AlGaAs, InGaN-GaN, ZnCdSe-ZnSSe, and InGaAsP-InP superlattices [1]. For instance, the minienergy band separation is 0.3-0.4eV in place of 0.02eV, at room temperature, resulting in the observation of distinct steps in electrical characteristics of FETs incorporating QDSL layers. The QDSL channels have been incorporated to fabricate multi-state/multi-bit FETs in configurations including: (1) quantum dot channel (QDC) FETs [1], (2) vertically-stacked multiple QD/QW channel spatial wavefunction switched (SWS) FETs [2,3], (3) quantum dot gate (QDG) FETs [4], and (4) combined QDG/QDC-FETs [3]. In addition, the *Corresponding

author.

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assembly of cladded quantum dots on amorphous p-Si provides an alternative to form higher mobility thin film transistors (TFTs). It also opens a pathway to design CMOS-like logic [5,6]. Figure 1(a) shows ID-VD characteristics of a long Ge quantum dot channel FET [1,3]. The quantum model that was used predicted ID-VD characteristics at various gate voltages VG as shown in Fig. 1(b).

Fig. 1(a). Experimental ID-VD characteristics of a Ge QDC-FET.

Fig. 1(b). Simulated ID-VD characteristics.

Figure 2(a) shows experimental characteristic (inset) [1] and computed current-voltage Id-Vg characteristics of a Si QDC-FET for three different drain voltage Vd , and Fig. 2(b) shows the simulated electron density in the inversion layer at room and liquid nitrogen temperatures [3].

Fig. 2(a). Experimental characteristic (inset) and computed current-voltage Id-Vg characteristics of a Si QDCFET for three different drain voltage Vd.

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Fig. 2(b). Carrier density as a function of Fermi level at 77K and 300K.

2. Quantum Simulation In our simulation, we consider quantum dot channel as a quantum dot superlattice (QDSL) with its energy mini-bands, intra-band separations and mini-band energy widths for Si and Ge QDs, respectively [3]. Having computed the QDSL parameters, a 2dimensional electron distribution nQM is obtained by solving the 1-D Poisson’s equation [Eq. (1)] and Schrödinger’s equation [Eq. (3)] self-consistently [3,7,8].

  (  )  q(nQM  n  N D  N A  p).

(1)

Here, is the permittivity of quantum dots,  is the electrostatic potential, nQM is the 2D electron gas in the channel, n and p are the 3D electron and hole concentrations, and ND+ and NA- are the ionized donor and acceptor concentrations. The 2-D carrier concentration nQM is expressed by Eq. (2), where EF is the Fermi level, En and n define the eigen energy and wavefunction of bound states, and  is the Heaviside Step function. Schrödinger’s Eq. (3) provides En and n for a given potential energy V. The value is V is determined by the band offsets Ec at the well-barrier interface and electrostatic potential .

nQM   n

E  En m*   EF  En  ln[1  exp( f ) |  n |2 2  kT

2  1    n    En  V  n  0 m 2 *  

(2)

(3)

Eq. (4) is an empirical relation expressing the influence of gate voltage accounting for the carriers in energy mini-bands (i). Here, the threshold voltage VTHi and shift VTHi depend on the concentration of electrons (dependent of VG) which in turn determines the

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occupancy of number of energy mini-bands. Here, W is the gate width, L is the channel length, ni is the mobility, VDS is the drain voltage, W I D ,QDAC =  L

1   ''  n    Co   μ ni V G - VTHi  ΔVTHi   VDS V DS  2    i 0  

(4)

Multi-step transport in QDC-FETs can be obtained using gradual channel approximation combined with the carrier density, as function of Fermi level, calculated from the QDSL band structure and DOS (see below). Following the approach in Sze [9] and Taur and Ning [10], without assuming the Boltzmann distribution for the carrier density, an integral expression for the drain current may be written as Eq. (5),

Id  

qW n L

VD  s

n( ,V )

  E ( ,V ) d dV   0

(5)

B

where VD is the drain voltage, and S is the surface potential, and B is the majority carrier quasi-Fermi level in the substrate. The integration for the drain voltage should be replaced by summation as in Eq. (4) to precisely account for the mini-energy bands. Furthermore, in the case of Spatial wavefunction switched (SWS) FET with more than one QD channels, we need to account for the location of inversion layer charge (qn). This can be adjusted by the flat band voltage VFB as expressed by Eq. (6).

 S (V )  VG  VFB 

 E ( S ,V ) Ci

 

(6)

An expression for the electric field is obtained by multiplying the Poisson Equation [Eq. (1)] by d/dx and integrating each side with respect to E or , 

E ( ,V ) 

 2kT  q  q   qV    + p + n - ni  exp   B  +exp  (-ND+NA)       kT  kT   kT    

(7)

The low temperature simulations for Ge and Si QDC are shown in the next section. 2.1. Simulation Results

Figure 3(a) shows the carrier density plots at 77°K and 4.2°K in the first step. The carrier density magnitude reduces by a factor of 2 to 2.5 as compared at 77°K shown in Fig. 2(b). The charge density is calculated over a range of Fermi levels. For each Fermi level, the charge in the QDSL was determined from the density of state (DOS) which was determined by integrating the band structure over the 1st Brillouin Zone. The band structure was determined by a 3-D Kronig-Penny model where each direction was treated

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independently for V [Eq. (8a)] and energy E [Eq. (8b)],

V ( r )  V X ( x )  VY ( y )  V Z ( z )

(8a)

E ( q )  E X ( q X )  EY ( qY )  E Z ( q Z )

(8b)

Here, V is the potential due to the QD core and cladding, and each E(q) is the energy solution of the K-P characteristic equation, for each direction, at wavevector q [19]. We are simplifying the calculations by assuming a superlattice of ‘square’ QDs.

Fig. 3(a). Carrier density versus Fermi level at 77°K and 4.2°K in the inversion layer.

Figure 3(b) compares at 77, 4.2 and 0.025°K. Here, all steps are shown with Fermi level value up to 1.1eV.

Fig. 3(b). Carrier density at three temperatures with all steps up to Fermi level of 1.1eV.

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Figure 3(c) shows the expanded view of first step at 77°K, 4.2°K, and at 25 milliKelvin. The difference between 4.2°K and 25 milli-Kelvin cannot be resolved in the plots shown.

Fig. 3(c). Expanded view of first step at 77°K, 4.2°K, and at 25 milliKelvin.

2.2. Equivalent Circuit Approach We extend our recent [11] physics-based equivalent circuit approach to SWS-FET modeling to 77°K. Figure 4 shows the equivalent circuit when electrons are in channel W2. Figure 4(b) shows the simulated of drain current in lower channel W2 at 77°K using 65nm node model. The transconductance gm is shown in Fig. 4(c) in the lower channel W2. Figures 4(d) and 4(e) illustrate drain current and gm for the upper channel. It appears that gm in the lower channel is reduced significantly in the lower channel. Comparing the upper and lower channel, the simulation does not take into account the

Fig. 4(a). Equivalent circuit of Si QD SWS-FET when electrons are in channel W2.

Modeling of QDC Si FETs at Sub-Kelvin for Multi-State Logic

Fig. 4(b). Simulation of drain current in lower channel W2 at 77°K.

Fig. 4(c). Simulation of gm in lower channel W2 at 77°K.

Fig. 4(d). Simulation of drain current in upper channel W1 at 77°K.

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Fig. 4(e). Simulation of gm in upper channel W1 at 77°K.

Fig. 5. Simulation of ID-VD in upper channel W1 300 - 4.2°K for VG=1.2V.

tunneling in SWS channels. The inadequacy of 65nm node model becomes clearer if we see Fig. 5, which computes drain current as a function of drain voltage at a gate voltage of 1.2V. The drain current increases abruptly at 53°K and becomes very high at 4.2°K. 3. Low Temperature Logic and Computing Low-temperature device and circuit modeling will: (1) improve performance of novel 2bit CMOS-like inverters, SRAMs, and NOR gates [12], (2) enable low noise margins operation of logic gates which process 3-bit, 4-bit and higher bit simultaneously, and (3) potentially implement quantum computing logic using more than few electrons per bit [13–18]. Furthermore, 3D-confinement using 7-9nm channels in Si/Ge cladded quantum dot layers in QDC-QDG and SWS-FETs configurations opens a new pathway to design QD-FETs. This is a design paradigm that offers an alternative to single electron transistor (SET) or quantum cell automata (QCA) logic [13,14] and recent Si/SiGe quantum

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processors [15–17] using gate defined Si quantum dots. By contrast, self-assembly of SiOx-cladded Si quantum dots assemble on p-Si layers providing an inherent separation between adjacent quantum dots, QDC-, and SWS-FETs. This aspect is shown in Fig. 6. Figure 6(a) shows a 3D view of a single source/drain QDC-FET with SiOx-cladded Si (or GeOx-cladded Ge dots) grown on thin oxide. This is a variation of 3D confined SWS FET with two sources and two drains [6,12] using cladded Ge dots as a SWS-FET of Fig. 6(c).

Fig. 6(a). 3D view of a single source/drain QDC-FET with SiOx-cladded Si dots.

Fig. 6(b). Transfer gate Tx enabled bit/signal transfer from gate G1 to G2.

Fig. 6(c). SWS-FET version of 3D confined channel using GeOx-cladded Ge quantum dots.

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Figure 6(b) shows a novel structure where a transfer gate x is shown between two gates G1 and G2. Transfer gate enables the transfer of charge from gate G1 to FET with gate G2. The transfer gate region has no quantum dots and its length can be few nanometers to enable tunnel transfer, if necessary. Figure 6(c) shows a 2-source/2-drain SWS-FET with 3D confined GeOx-cladded Ge quantum dot channel. Here, S1 and D1 are the source and drain for the upper channel QD1 and S2 and D2 are for the lower channel QD-2. Here, the channel width W is about 2-2.5 times the channel length L. 4. Conclusion

Our quantum simulation model predicts ID-VD behavior in QDC-FETs well into milliKelvin temperatures. It incorporates the gradual channel model using the potential and inversion layer charge density nQM, obtained by the self-consistent solution of Schrodinger and Poisson’s equation, has predicted multi-state operation at 4.2°K and 25 milli-Kelvin temperatures. However, the difference between 4.2°K and 25 milli-Kelvin cannot be resolved in the plots shown and this part needs additional investigation. Figure 5 clearly illustrates the inadequacy of the currently used 65nm node FET model when used at below 53°K. By contrast, quantum simulation predicts operation at 4.2°K and below. There is a decrease in charge density by a factor of 2 to 2.5 going from 77°K to 4.2°K. This would affect the drain current- drain voltage characteristics as a function of gate voltage. The integration of multi-bit fast erase/fast-write multi-bit quantum dot nonvolatile random-access memory, QD-NVRAM [18] with 3D confined QD n-SWS-FETs is recently reported [12]. With the enablement of 3-D confinement in short-channel QD-FETs, 3 or 4-bit logic operations [e.g. inverters, SRAMs, NOR, adders, field-programmable gate arrays, (FPGAs)] is predicted. In addition, the role of self-assembled QDs with transfer gate provides a pathway to implement qubits. Acknowledgments

This paper is based on SWS-FET and quantum dot FET research carried out by the support of completed grants including Office of Naval Research contracts (N00014-02-1-0883 and N00014-06-1-0016), and National Science Foundation grants (NER and ECS 0622068). Authors gratefully acknowledge the support of Dr. M. Lingalugari (currently at Synopsys Corp.) for QD-NVRAM fabrication, Dr. Pik-Yiu Chan (UCONN) for the fabrication of QD-SWS twin-drain FETs and Dr. LaComb (NUWC) for guidance in mask fabrication. References 1. F. Jain, S. Karmakar, P.-Y. Chan, E. Suarez, M. Gogna, J. Chandy and E. Heller, Quantum Dot Channel (QDC) Field-Effect Transistors (FETs) Using II-VI Barrier Layers. Journal of Electronic Materials, 41(10), 2775–2784, 2012. 2. F. Jain, M. Lingalugari, B. Saman, P.-Y. Chan, P. Gogna, E.-S. Hasaneen1, J. Chandy and E. Heller, Multi-State Sub-9 nm QDC-SWS FETs for Compact Memory Circuits. 46th IEEE Semiconductor Interface Specialists Conference (SISC), San Diego (CA), 2–5 December 2015.

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3. F. Jain, M. Lingalugari, J. Kondo, P. Mirdha, E. Suarez, J. Chandy and E. Heller, Quantum Dot Channel (QDC) FETs with Wraparound II-VI Gate Insulators: Numerical Simulations. Journal of Electronic Materials, 45, 5663, 2016. 4. M. Lingalugari, K. Baskar, P-Y. Chan, P. Dufilie, E. Suarez, J. Chandy, E. Heller and F. Jain, Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators. Journal of Electronic Materials, 42, 3156, 2013. 5. F. Jain, B. Saman, R. Gudlavalleti, J. Chandy and E. Heller, Multi-state 2-Bit CMOS Logic Using n- and p-Quantum Well Channel Spatial Wavefunction Switched (SWS) FETs. International Journal of High Speed Electronics and Systems, 27, 1840020-1, 2018. 6. F. Jain, B. Saman, R. Gudlavalleti, R. Mays, J. Chandy and E. Heller, Low-Threshold II-VI Lattice-Matched SWS-FETs for Multi-Valued Low-Power Logic. Journal of Electronic Materials, 50, 2618–2629, 2021. 7. E. K. Heller, S. K. Islam, G. Zhao and F. C. Jain, Analysis of In0.52Al0.48As/In0.53Ga0.47As/InP Quantum Wire MODFETs Employing Coupled Well Channels. Solid-State Electronics, 42, 901–914, 1999. 8. T. Kerkhoven, A. T. Galick, U. Ravaioli, J. H. Arends and Y. Saad, Efficient Numerical Simulation of Electron States in Quantum Wires J. Appl. Phys. 68, 3461–3469, 1990. 9. S. M. Sze, Physics of Semiconductor Devices, Wiley, 1981. 10. Y. Taur and T. H. Ning, Modern VLSI Devices, Cambridge, 2009. 11. R. Mays, R. H. Gudlavalleti, B. Khan, B. Saman, J. Chandy, Evan Heller and F. Jain, QDC-FET and QD-SWS Physics-based Equivalent Circuit for ABM Simulations. International Journal of High Speed Electronics and Systems, 29(1/2), 2040022, 2020. 12. F. Jain, B. Saman, R. H. Gudlavalleti, R. Mays, J. Chandy and Evan Heller, 3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattices. International Journal of High Speed Electronics and Systems, 29(1/2), 2040011-1 to 2040011-7, 2020. 13. M. A. Kastner, The Single Electron Transistor. Reviews of Modern Physics, 64(3), 849–858, 1992. 14. R. K. Kummaru, A. O. Orlov, R. Ramasubramanium, C. S. Lent, G. H. Bernstein and G. L. Snider, Operation of a Quantum Dot Cellular Automata (QCA) Shift Register and Analysis of Error. IEEE Transactions on Electron Devices, 50(9), 1906–1913, 2003. 15. A. J. Sigillito, J. C. Loy, D. M. Zajac, M. J. Gullans, L. F. Edge and J. R. Petta, Site-selective Quantum Control in an Isotopically Enriched 28Si/Si0.7Ge0.3 Quadruple Quantum Dot. Physics Review Applied, 11, 061006, 2019. 16. T. F. Watson, S. G. J. Phillips, E. Kawakami, D. R. ward, P. Scarlino, M. Veklhorst, D. E. Savage, M. G. Lagally, M. Friesen, S. N. Coppersmith, M. A. Eriksson, I. M. K. Vandersypan, A Programmable Two-Bit Quantum Processor in Silicon. Nature, 555, 633, 2018. 17. R. Maurand, X. Jehl, D. Kotekar-Patil, A. Corna, H. Bohuslavskyi, R. Lavieville, L. Hutin, S. Barraud, M. Vinet, M. Sanquer and S. De Franceschi, A CMOS Silicon Spin Qubit. Nature Communications, 7, 13575, 2016. 18. M. Lingalugari, P. Mirdha, J. Chandy, E. Heller and F. Jain, Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Quantum Dot Channel for Faster Erasing. Electronic Letters, 54, 36, 2018. 19. C-W. Jiang and M. A. Green, Silicon Quantum Dot Superlattices: Modeling of energy bands, densities of states, and mobilities for silicon tandem solar cell applications. Journal of Applied Physics, 99, 114902, 2006.

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Author Index Karna, S. R., 151 Khan, B., 1, 175 Kujofsa, T., 13, 19, 25, 31 Lynch, C., 163 Mays, R., 1, 83, 93, 103, 129, 139, 175, 187 Montrone, D., 119 Oh, T., 41 Parvin, D., 41 Qian, F., 53 Raphael, J., 13, 31 Salama, H., 83, 129, 83, 93, 103, 129, 139 Saman, B., 175, 187 Shelby, I. A., 151 Tentzeris, M., 163 Wang, L., 53 Zhang, B., 67 Zhao, Y., 53

Adeyeye, A., 163 Asthana, S., 151 Ayers, J. E., 13, 19, 25, 31 Butterfield, N. R., 1 Chakraborty, T., 119 Chandy, J., 83, 93, 103, 129, 139, 175, 187 Chang, M., 119 Cui, Y., 163 Das, S., 119 Gao, P.-X., 67 Gudlavalleti, R. H., 1, 83, 93, 103, 129, 139, 175, 187 Hassan, O., 41 He, X., 163 Heller, E., 83, 93, 103, 129, 139, 175, 187 Islam, M. T., 31 Islam, S. K., 41 Jain, F., 1, 53, 83, 93, 103, 129, 139, 175, 187 Jung, E. M., 163

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