Nano Devices and Sensors 9781501501531, 9781501510502

Table of contents :
Contents
Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs
Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation
Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory
Resistive Switching Characteristics and Mechanisms in Silicon Oxide Memory Devices
A Synaptic Device Built in One Diode–One Resistor (1D–1R) Architecture with Intrinsic SiOx-Based Resistive Switching Memory
On-chip Wide Range Bidirectional Current Sensor for Li-ion Battery Management System
A 12-bit 1-MS/s 26-µW SAR ADC for Sensor Applications
A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission
Impacts of ESD Reliability by Different Layout Engineering in the 0.25-µm 60-V High-Voltage LDMOS Devices
Impact-Based Area Allocation for Yield Optimization in Integrated Circuits
Editors
List of authors

Citation preview

Juin J. Liou, Shien-Kuei Liaw, Yung-Hui Chung (Eds.) Nano Devices and Sensors

Also of interest The Fundamentals of Electrical Engineering Felix Hüning, 2014 ISBN 978-3-11-034991-7, e-ISBN 978-3-11-034990-0, e-ISBN (EPUB) 978-3-11-030840-2

Signals and Systems Gang Li, Liping Chang, Chen Li ISBN 978-3-11-037811-5, e-ISBN 978-3-11-037954-9, e-ISBN (EPUB) 978-3-11-041684-8

Nanophotonics Dennis Couwenberg (Publishing Editor), 1 issue per year ISSN 2192-8614

Opto-Electronics Review Leszek Jaroszewicz (Editor in Chief), 4 issues per year ISSN 1896-3757

Energy Harvesting and Systems Shashank Priya, 4 issues per year ISSN 2329-8766

Nano Devices and Sensors  Edited by Juin J. Liou, Shien-Kuei Liaw, Yung-Hui Chung

Editors Prof. Juin J. Liou University of Central Florida Dept. Electrical & Computer Engineering 4328 Scorpius Street Orlando FL 32816, USA [email protected]

Prof. Yung-Hui Chung National Taiwan University of Science and Technology Keelung Rd., No. 43, Sec. 4 Taipei 106, Taiwan [email protected]

Prof. Shien-Kuei Liaw National Taiwan University of Science and Technology Keelung Rd., No. 43, Sec. 4 Taipei 106, Taiwan [email protected]

ISBN 978-1-5015-1050-2 e-ISBN (PDF) 978-1-5015-0153-1 e-ISBN (EPUB) 978-1-5015-0155-5 Set-ISBN 978-1-5015-0154-8 Library of Congress Cataloging-in-Publication Data A CIP catalog record for this book has been applied for at the Library of Congress. Bibliographic information published by the Deutsche Nationalbibliothek The Deutsche Nationalbibliothek lists this publication in the Deutsche Nationalbibliografie; detailed bibliographic data are available on the Internet at http://dnb.dnb.de. © 2016 Walter de Gruyter Inc., Boston/Berlin Cover image: Petrovich9/Signature Collection/istock by Getty Images Typesetting: Lumina Datamatics Printing and binding: CPI Books GmbH, Leck © Printed on acid-free paper Printed in Germany www.degruyter.com

Editorial/Foreword The chapters in this edited book are written by some authors who have presented very high quality papers at the 2015 International Symposium of Next-Generation Electronics (ISNE 2015) held in Taipei, Taiwan. The ISNE 2015 was intended to provide a common forum for researchers, scientists, engineers, and practitioners throughout the world to present their latest research findings, ideas, developments, and applications in the general areas of electron devices, integrated circuits, and microelectronic systems and technologies. The scope of the conference includes the following topics: A. Green Electronics B. Microelectronic Circuits and Systems C. Integrated Circuits and Packaging Technologies D. Computer and Communication Engineering E. Electron Devices F. Optoelectronic and Semiconductor Technologies. The technical program consisted of 4 plenary talks, 23 invited talks, and more than 250 contributed oral and poster presentations. Plenary speakers were recognized experts in their fields, and their talks focused on leading-edge technologies including: “The Future Lithographic Technology for Semiconductor Fabrication,” by Dr. Alek C. Chen, Asia ASML, Taiwan. “Detection of Single Traps and Characterization of Individual Traps: Beginning of Atomistic Reliability Physics,” by Prof. Toshiaki Tsuchiya, Shimane University, Japan. “The Art and Science of Packaging High-Coupling Photonics Devices and Modules,” by Prof. Wood-Hi Cheng, National Chung-Hsing University, Taiwan. “Prospect and Outlook of Electrostatic Discharge (ESD) Protection in Emerging Technologies,” by Prof. Juin J. Liou, University of Central Florida, USA. After a rigorous review process, the ISNE 2015 technical program committee has selected 10 outstanding presentations and invited the authors to prepare extended chapters for inclusion in this edited book. Of the 10 chapters, five are focused on the subject of electronic devices, and the others cover the circuit designs for various applications. The authors are working at the academia in Austria, United States, Korea, and Taiwan. The guest editors would like to take this opportunity to express our sincere gratitude to all the members of the ISNE 2015 technical program committees for reviewing the papers and selecting the manuscripts for the edited book. We also thank all the authors for their valuable and excellent contributions to the book.

VI  Editorial/Foreword

Guest Editors: Juin J. Liou University of Central Florida, USA S. K. Liaw National Taiwan University of Science and Technology, Taiwan Y. H. Chung National Taiwan University of Science and Technology, Taiwan

Contents Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs  1 Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation  29 Amit Prakash and Hyunsang Hwang Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory  49 Yao-Feng Chang, Burt Fowler, Ying-Chen Chen, Fei Zhou, Xiaohan Wu, Yen-Ting Chen, Yanzhen Wang, Fei Xue, and Jack C. Lee Resistive Switching Characteristics and Mechanisms in Silicon Oxide Memory Devices  73 Yao-Feng Chang, Burt Fowler, Ying-Chen Chen, Fei Zhou, Chih-Hung Pan, Kuan-Chang Chang, Tsung-Ming Tsai, Ting-Chang Chang, Simon M. Sze, and Jack C. Lee A Synaptic Device Built in One Diode–One Resistor (1D–1R) Architecture with Intrinsic SiOx-Based Resistive Switching Memory  91 Tzung-Je Lee and Yen-Ting Chen On-chip Wide Range Bidirectional Current Sensor for Li-ion Battery Management System  113 Yung-Hui Chung, Chia-Wei Yen, and Cheng-Hsun Tsai A 12-bit 1-MS/s 26-μW SAR ADC for Sensor Applications  135 Chang-Hsi Wu, Hong-Cheng You, and Shun-Zhao Huang A 5.2/5.8 GHz Dual Band On-Off Keying Transmitter Design for Bio-Signal Transmission  159

VIII  Contents

Shen-Li Chen, Chun-Ju Lin, and Yu-Ting Huang Impacts of ESD Reliability by Different Layout Engineering in the 0.25-μm 60-V High-Voltage LDMOS Devices  177 Billion Abraham, Arif Widodo, and Poki Chen Impact-Based Area Allocation for Yield Optimization in Integrated Circuits  199 Editors  215 List of authors  217

Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless Cylindrical Surrounding-Gate MOSFETs Abstract: When the traditional planar metal-oxide-semiconductor-field-effect transistors (MOSFETs) encounter insurmountable bottleneck of static power dissipation, junctionless transistor (JLT) becomes a promising candidate for sub-22 nm nanoscale devices due to its simpler fabrication process and better short-channel performances. Subthreshold behaviors dominate the standby power of nanoscale JLTs. In this chapter, a physics-based analytical model of electrostatic potential for both silicon and germanium short-channel junctionless cylindrical surrounding-gate (JLCSG) MOSFETs operated in the subthreshold regime is proposed, in which the full twodimensional (2D) Poisson’s equation is solved in the channel region by a method of series expansion. The expression of the proposed electrostatic potential is completely rigorous and explicit. Based on this result, the expressions of threshold voltage, subthreshold drain current, and subthreshold swing for JLCSG MOSFETs are derived. Subthreshold behaviors are studied in detail by changing different device parameters and bias conditions, including doping concentration, channel radius, gate length, gate equivalent oxide layer thickness, drain voltage, and gate voltage. Results predicted by all the analytical models agree well with numerical solutions from the three-dimensional simulator. These analytical models can be used to investigate the operating mechanisms of nanoscale JLCSG MOSFETs and to optimize their device performances. Keywords: Junctionless transistor, analytical model, germanium devices, shortchannel effects, subthreshold behaviors, surrounding-gate devices.

1

Introduction

Planar metal-oxide-semiconductor-field-effect transistor (MOSFET) has been the workhorse of integrated circuit industry since it was born in 1960 [1]. Performances for planar MOSFETs have been steadily improved due to the scaling down law, which is famous as Moore’s law [2]. However, as the gate length of MOSFET scales into sub-22

Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu, Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084, China.

2  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

nm node, the standby power challenge due to the subthreshold leakage current and the gate tunneling leakage current has become a primary roadblock for low-power applications. The gate tunneling leakage current could be remarkably removed by high-k/metal gate technology [3]. The increase in subthreshold leakage current is mainly caused by the short-channel effects (SCEs), mostly including the threshold voltage roll-off, drain-inducing barrier lowering (DIBL) effect and transverse velocity saturation effect. SCEs result from sharing control over the channel among the source region, drain region, and gate electrode. Multigate transistors, such as double-gate MOSFET, triple-gate MOSFET, Ω–gate MOSFET, ∏–gate MOSFET, and surroundinggate MOSFET, have been proposed to suppress the SCEs by encircling the device channel and the gate controllability could be boosted [4]. Meanwhile, it’s another serious challenge for semiconductor manufacture process to produce ultra-sharp source/drain junctions in the range of several nanometers for the nanoscale transistors. Junctionless transistor (JLT) has been proposed to solve this problem [5]. The JLT is basically a gated resistor where the source region, drain region, and channel region have the same dopant type and concentration without any junctions between them. The advantages of JLTs compared with its inversion-mode MOSFET counterpart are that: (1) it drastically simplifies the fabrication process; (2) it eliminates the lateral impurity diffusion and solves the problem of sharp doping profile formation; (3) it was demonstrated that the short-channel performances, such as DIBL effect and subthreshold slope degradation, were improved when the device sizes were aggressively scaled down [6]; (4) the mobility degradation in the high electric field region is relaxed [7]; (5) the gate dielectric thickness scaling is also relaxed in terms of the intrinsic delay time [5]. Nevertheless, it requires the full depleted channel when JLT works at the off-state in order to turn the device off completely. This is very difficult for the planar structure owing to its weak gate controllability. Thus, multigate structures or three-dimensional (3D) structures can be a good choice to suppress the subthreshold leakage current for JLTs. In practice, almost all of the experimental verifications for JLT concept adopt 3D architectures [8–11]. Another method is replacing the silicon-on-insulator (SOI) substrate with bulk substrate [12]. This method is ideal because the subthreshold leakage current depends on the effective channel layer thickness. In a bulk substrate structure, the effective channel layer thickness can be less than the physical thickness due to the depletion-layer width of p–n junction between the channel and substrate (well) with controllable well doping concentration and/or well bias. Theoretically, the surrounding-gate configuration has the best short-channel performances [13]. As a consequence, junctionless cylindrical surrounding-gate (JLCSG) transistor becomes one of the promising candidates for next-generation digital switch device. In addition, germanium (Ge) has been considered as one of the promising channel materials in replacement of silicon (Si) for future high-speed CMOS technology because of its high electron mobility (3,900 cm²/Vs), hole mobility (1,900

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



3

cm²/Vs), and best Si compatibility. Ge has been widely investigated in recent years [14–16]. Generally speaking, Ge p-MOSFETs have better performances, whereas Ge n-MOSFETs have exhibited poor drive current and inversion mobility, lower than universal Si mobility, as reported by several different research groups worldwide due to the difficulties in the surface passivation and n-type dopant activation [17–20]. As a result, Ge complementary metal-oxide-semiconductor transistor (CMOS) structure is difficult to be achieved. However, recently, Shoichi Kabuyanagi group [21] demonstrated the high electron mobility in Ge n-channel junctionless FETs compared with Si n-channel MOSFETs. This phenomenon is the resultant effect of the bulk conduction mechanism of junctionless transistors and material properties of Ge. As a result, Ge nchannel JLCSG MOSFET is noteworthy. In this chapter, an analytical short-channel electrostatic model was proposed for Si and Ge JLCSG MOSFETs and their subthreshold behaviors were studied extensively by both proposed analytical model and a 3D commercial numerical simulator [22]. The modeled data are in good agreement with simulated data.

2 Silicon junctionless cylindrical surrounding-gate transistors Si material dominates the present semiconductor manufacturing industry and has best mature fabrication technology because of its good properties and very low cost. Therefore, Si-based JLTs should be studied first. In fact, almost all of the experimental reports on JLTs are based on Si material [23–25].

2.1 The working principle for JLCSG transistor JLT is a kind of intrinsic depletion mode device contrary to the traditional inversionmode MOSFET. Figure 1(a) shows the landscape of an n-type JLCSG MOSFET. Figure 1(b) presents the corresponding cross-sectional schematic diagram along channel direction and coordinates. At zero-gate voltage, a high workfunction (WF) difference between the gate metal and channel material has to be achieved to deplete the entire channel of JLCSG transistors with a suitable threshold voltage value. The operation regimes can be generally classified as full depleted region, partly depleted region, flat-band channel region, and accumulation region [26]. Figure 2 presents the responding energy band diagrams for the four operation regimes. Vth is the longchannel threshold voltage for the n-type JLCSG transistor [27].

4  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Drain

Source

(a)

Gate

Vds

Lg

(b)

Vgs

Gate

(0,0) z Nd

tox Drain

Source

Oxide layer

Silicon channel Nd

r

R Nd

Vds

Oxide Oxidelayer layer Gate

Vgs

Fig. 1: (a) The landscape of an n-type Si JLCSG MOSFET; (b) cross-sectional schematic diagram along channel direction and coordinates of the device.

VTH ¼ VFB −

qNd R2 qNd R − 4εsi 2Cox

ð1Þ

Eg Nd Þ=q þ vt lnð Þ 2 ni

ð2Þ

and VFB ¼ ðφm − K −

where VFB is the flat band voltage; q is the electronic charge; Nd is the doping concentration of the channel; R is the radius of the channel; εsi is the dielectric constant of Si; Cox is the capacitance per unit area of the gate dielectric, Cox ¼ εox =½Rlnð1 þ tox =RÞ;[28] εox is the permittivity of the oxide layer; tox is the equivalent oxide layer thickness, defined as ðεox thigh − k Þ=εhigh − k ; thigh − k ; εhigh − k are the thickness and permittivity of the high-k gate dielectric materials, respectively [29]. φm is the workfunction of the gate metal. K is the electron affinity of Si. Eg is the band gap of Si. ni is the intrinsic carrier concentration of Si. vt is the thermal voltage, defined as kT/q. It can be observed

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless

(a) Vgs< VTH



5

(b) VTH< Vgs< VFB

qvtln(Nd/ni)+Ein

Vgs

φs

φ(r,z)

Ef

φ0

tox

R

R

(c) Vgs = VFB

tox

(d) Vgs > VFB

Ef Vgs

Fig. 2: The energy band diagrams for a n-type JLCSG transistor (a) full depleted region; (b) partly depleted region; (c) flat band region; (d) accumulation region. The potential φðr; zÞ is defined as the sum of intrinsic Si midgap level (Ein) and qvtln(Nd/ni) referenced to the Fermi level (Ef).

from Eqn. (1) that design parameters: R, tox, Nd, and φm must be optimized to achieve better subthreshold performances because the subthreshold leakage current is very sensitive to Vth. Eqn. (1) also indicates the biggest shortcoming of JLTs for digital logic application: the performances depend strongly on the geometry (R, tox, and Lg) as well as on the doping level of the channel (Nd) and the process variation is bigger than that of junction-based MOSFETs. However, these parameters can be used to finely tune the operation point of the device, which makes the application of JLTs in low-power sensing systems very promising [30]. It is noteworthy that Vth can be a positive value for the normally off device and be a negative value for the normally on device by adjusting device parameters. Thus, JLTs can satisfy the requirement of multithreshold electronics system easily, which has emerged as a promising technique to reduce leakage power dissipation and boot high performances at the same time [31].

2.2

Short-channel effects (SCEs) and subthreshold behavior model

SCEs are very important nonideal secondary effects, mainly including threshold voltage roll-off, DIBL effect, and transverse velocity saturation effect, and so on.

6  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

SCEs dominate the subthreshold leakage current, which is the most important component of static power dissipation. For nanoscale JLCSG MOSFETs, analytical models are urgently needed to guide the device design and circuit simulation. However, most studies have concentrated on long-channel models of JLCSG MOSFETs [27, 28, 32, 33], in which the one-dimensional (1D) Poisson’s equation is solved based on the gradual channel approximation (GCA). These models are not suitable for short-channel JLCSG MOSFETs, where two-dimensional (2D) effects play a key role. A few studies have been reported that investigate the subthreshold behaviors of JLCSG MOSFETs, in which the quasi 2D Poisson’s equation is solved based on the parabolic-profile approximation (PPA) [34–36]. However, PPA is a purely conceptual hypothesis and lacks real physical meaning. For a cylindrical surrounding-gate structure, the conventional separation of variables for series solution to 2D Poisson’s equation will introduce a transcendental equation of eigenvalues, which can only be solved numerically [37]. In next sections, a method of series expansion [38, 39] is applied to determine the analytical solutions of the 2D Poisson’s equation of JLCSG MOSFETs. This method can avoid the difficulties described above. Thus, the proposed 2D electrostatic potential model is completely rigorous and explicit. Using this model, analytical models for the metrics such as threshold voltage, subthreshold drain current, and subthreshold swing are derived to depict the subthreshold characteristics. The accuracy of all the developed analytical models is verified by numerical simulation using a 3D commercial device simulator.

2.3

An analytical model for Si short-channel junctionless cylindrical surrounding-gate MOSFETs

2.3.1

Electrostatic potential model

As shown in Figure 1(b), because the doping concentration is very high in the source and drain regions, the voltage drop across these two regions can be ignored. In the subthreshold regime, mobile carriers can be ignored [35]. Furthermore, it is presumed that the channel is fully depleted because of an ultra-small channel radius. For a uniform doped body, Poisson’s equation for channel region is ∂2 φ 1 ∂φ ∂2 φ qNd þ ¼ þ εsi ∂r 2 r ∂r ∂z 2

ð3Þ

where − R  r  R and 0  z  Lg . R is the radius of the channel; Lg is the gate length. φ is the electrostatic potential.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless

From refs. [38, 39], φ can be written as φðr; zÞ ¼ Vref

Vds þ zþ Lg

sffiffiffiffiffi 1 2X nπ An ðrÞsin z Lg n¼1 Lg



7

ð4Þ

where Vref is the electrostatic potential of the source region relative to the cathode of the power supply. Vds is the drain voltage. In this work, Vref is 0.53 V at room temperature. Substitute Eqn. (4) into (3), An(r) is an auxiliary parameter and satisfies equation: d 2 An ðrÞ 1 dAn ðrÞ þ − λ2n An ðrÞ ¼ fn dr 2 r dr

ð5Þ

where λn ¼ and qNd fn ¼ − εsi λn

nπ Lg

ð6Þ

sffiffiffiffiffi 2 ½1 − ð − 1Þn  Lg

ð7Þ

The general solution of Eqn. (5) is An ðrÞ ¼ cn I0 ðλn rÞ þ dn K0 ðλn rÞ −

fn λ2n

ð8Þ

where I₀(x) is the zero-order first kind of imaginary Bessel function, and K₀(x) is the zero-order second kind of imaginary Bessel function. Coefficients, cn and dn are defined by following boundary conditions: φðr; 0Þ ¼ Vref

ð9Þ

φðr; LÞ ¼ Vds þ Vref

ð10Þ

∂φ | ¼0 ∂r r¼0

ð11Þ

Cox ½Vgs − VFB − φðR; zÞ ¼ εsi

∂φ | ∂r r¼R

ð12Þ

Eqns. (9) and (10) denote boundary conditions at the source and drain regions, respectively. It is easy to be verified that Eqn. (4) satisfies the boundary conditions of Eqns. (9) and (10) automatically. Eqn. (11) is valid because of the symmetry of the device. Eqn. (12) is derived from Gauss’s theorem at the interface of the gate dielectric layer and silicon channel. From Eqns. (8)–(12), we get

8  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

dn ¼ 0 sffiffiffiffiffi fn 2 Lg cn ¼ 2 þ ð − 1Þn ðVds þ VFB − Vgs Þ Lg nπ λn sffiffiffiffiffi    2 Lg εsi − λn I1 ðλn RÞ þ I0 ðλn RÞ ðVFB − Vgs Þ = Cox Lg nπ

ð13Þ



ð14Þ

where I₁(x) is the first-order first kind of imaginary Bessel function. At last, we obtain the expression electrostatic potential: sffiffiffiffiffi  1  Vds 2X fn nπ cn I0 ðλn rÞ − 2 sin z zþ ð15Þ φðr; zÞ ¼ Vref þ Lg Lg n¼1 Lg λn where cn is given by Eqn. (14). To verify the accuracy of the developed models, the results of analytical models were compared with those of a 3D numerical simulation tool. There are few mobile carriers in the channel when the JLCSG device is operated in the subthreshold regime. Quantum effects can be ignored when R  5 nm in the developed models and simulation [36]. For both analytical calculation and simulation, a dopant-dependence mobility model: Masetti model [40] is used. The device temperature is 300 K, and the workfunction of the gate metal is 4.8 eV. It should be noted that the Eqn. (15) is an infinite series and we have to used first several terms to approximate φðr; zÞ. The convergence of An should be tested firstly. Actually, An converges very quickly with respect to argument n, as presented in Figure 3. It can be observed that high-order terms ðn  4Þ are far less than the first three terms. As the gate length increases, the error due to high-order terms increases. This fact indicates that our model is more suitable for short-channel devices ð10 nm  Lg  40 nmÞ. Even though, the first three order approximations have enough precision to calculate the model expressions for any given gate length and channel radius and the first three order approximations are employed to compute the electrostatic potential, subthreshold drain current and subthreshold swing, only the first order term is considered in the threshold voltage model for simplification. Figure 4 illustrates the central electrostatic potential along channel direction for different gate lengths. The modeled data match well with simulated data. It can be seen that as the gate length decreases, the position of the minimum central potential is pulled up and leading to a lower threshold voltage. This phenomenon is called the threshold voltage roll-off [41] and deteriorates the device subthreshold performances.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless

1.2

Convergence of An(0)

1.0

An(0)/A1(0)

0.8



9

Lg = 10 nm Lg = 20 nm

R = 6 nm tox = 0.5 nm

Lg = 30 nm

Nd = 1 x 1019 cm–3

Lg = 40 nm

Vds = 0.5 V

0.6

Vgs = –0.5 V

0.4 0.2 0.0 1

2

3 4 Order of harmonic wave, n

5

6

Fig. 3: Ratio of An(0)/A₁(0), showing the convergence of coefficient, An(0). Higher order terms (n  4) are far less than the first three terms.

Central electrostatic potential (V)

Figure 5 presents the electrostatic potential distribution in the channel center as a function of channel radius. Analytical results for the proposed model are in good agreement with the 3D simulation results. It is clear that, as the channel radius increases, the minimum central potential along the channel direction is elevated, which suggests that the gate gradually loses control over the channel. This fact leads to a smaller threshold voltage for a larger channel radius, degrading the subthreshold characteristics. Hence, a smaller channel radius is desired to reduce the leakage current.

1.2

Lg = 15 nm

1.0

Lg = 20 nm

Lines: numerical simulation Symbols: analytical model

Lg = 25 nm 0.8

R = 6 nm Vgs = –0.2 V tox = 0.5 nm

0.6 0.4

Nd= 1 x 1019 cm–3

0.2 0.0 –0.2 0

2

4 6 8 10 12 14 16 18 20 22 24 Position along channel direction, z (nm)

Fig. 4: Central electrostatic potential along channel direction for different gate lengths. The simulated device parameters are Vgs = –0.2 V, R = 6 nm, Vds = 0.5 V, Nd = 1 × 10¹⁹ cm–3, and tox = 0.5 nm.

10  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Central electrostatic potential (V)

1.2 Lines: numerical simulation Symbols: analytical model

1.0

R = 6 nm R = 7 nm R = 8 nm

Lg = 20 nm Vgs = –0.2 V tox = 0.5 nm

0.8 0.6

Nd = 1 x 1019 cm–3

0.4 0.2 0.0 –0.2 0

5 10 15 Position along channel direction, z (nm)

20

Fig. 5: Central electrostatic potential along channel direction for different radiuses. The simulated device parameters are Lg = 20 nm, Vgs = –0.2 V, Vds = 0.5 V, tox = 0.5 nm, and Nd = 1 × 10¹⁹ cm–3.

It is shown in Figure 6 that the central electrostatic potential distribution for different equivalent oxide layer thicknesses, tox. It is clear that, as the equivalent oxide layer thicknesses steadily increases, the position of the minimum central potential is pulled up, which shows that the gate electrode gradually loses control of the channel. This is because a thicker equivalent oxide layer will resist the vertical electric field from the metal gate penetrating into the channel, resulting in the degradation of threshold behaviors. Therefore, to suppress the SCEs, thin equivalent oxide thickness is preferred.

Central electrostatic potential (V)

1.0 Lines: numerical simulation Symbols: analytical model Lg = 20 nm

0.8 0.6

tox = 0.5 nm

Vgs = –0.2 V

tox = 0.8 nm

Vds = 0.5 V

tox = 1.1 nm

R = 6 nm

0.4

Nd = 1 x 1019 cm–3

0.2 0.0 0

5

10

15

20

Position along channel direction, z (nm) Fig. 6: Central electrostatic potential distribution along channel direction for different equivalent oxide layer thicknesses. The simulated device parameters are Lg = 20 nm, Vgs = –0.2 V, Vds = 0.5 V, R = 6 nm, and Nd = 1 × 10¹⁹ cm–3.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



11

Central electrostatic potential (V)

It is observed in Figure 7 that the central electrostatic potential distribution for different drain voltages. It is obvious that, as Vds steadily increases, the position of the minimum central potential is raised, which shows that the channel can be turned on more easily. The phenomenon is called drain inducing barrier lowering (DIBL) effect [42].This is a kind of important SCEs. 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 –0.1

Lines: numerical simulation Symbols: analytical model Lg = 20 nm Vgs = –0.2 V

Vds = 0.1 V Vds = 0.3 V Vds = 0.5 V

tox = 0.5 nm Nd = 1 x 1019 cm–3

0

5 10 15 Position along channel direction, z (nm)

20

Fig. 7: Central electrostatic potential along channel direction for different drain voltages. The simulated device parameters are Lg = 20 nm, Vgs = –0.2 V, R = 6 nm, and Nd = 1 × 10¹⁹ cm–3.

Figure 8 shows the electrostatic potential at r = 0 nm along the channel direction for different gate voltages. The center electrostatic potential is proportional to Vgs because of the capacitive coupling effect between the gate dielectric-layer capacitance and channel capacitance. The analytical model curves match well with the simulated curves for a wide range of gate voltages, even for devices with a short gate length (Lg = 20 nm), which indicates the validity of the developed model for calculating the potential profile.

12  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Central electrostatic potential (V)

1.2 Lines: numerical simulation Symbols: analytical model

1.0

Vgs = –0.2 V

tox = 0.5 nm

0.8

Vgs = 0 V

Lg = 20 nm

0.6

Vgs = –0.4 V

Vds = 0.5 V Nd = 1 x 1019 cm–3

0.4 0.2 0.0 –0.2 –0.4 0

5

10

15

20

Position along channel direction, z (nm)

Fig. 8: Central electrostatic potential along channel direction for different gate voltages. The simulated device parameters are Lg = 20 nm, Vds = 0.5 V, R = 6 nm, and Nd = 1 × 10¹⁹ cm–3.

2.3.2

Threshold voltage model

Figure 9 presents the 2D electrostatic potential contours of channel cut plane along z direction. The data are calculated from numerical simulation. It can be observed that along z direction, there exists a minimum potential position (z = z₀) for given position r. Different points along z direction can be treated as many switches in a series. So, the minimum potential position along z direction will switch on at last and determines the onset of conduction. On the other hand, there exists a maximum potential position along r direction for given position z. Different points along r direction can be treated as many switch in parallel, so the maximum potential position will switch on at first and also determines the onset of conduction. Above all, because of the device symmetry, the position (0, z₀) will conduct current firstly and determines the subthreshold behaviors of JLCSG MOSFETs. The position (0, z₀) is called the most leaky path or the virtual electrode [43, 44]. Similar to the definition of long channel threshold voltage, the short-channel threshold voltage, Vths, is defined as the gate voltage when φð0; z0 Þ reaches Vref −2kT/q; in this situation, the electron density at the virtual electrode is Ndexp(−2). This value is far less than Nd. Therefore, the mobile electrons in the channel can be ignored. Such a definition is equivalent to the constant drain current method of Vth extraction [35].

Channel position along r direction (nm)

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless

4



13

–0.10 –0.050

2 0.30

0.30

0

0

0 0.10 0.40

–2

0.10

0.40

(0, z0) 0.20

–0.050

0.20

–0.10

–4 0

2

4 6 8 10 12 14 16 Channel position along z direction (nm)

18

20

Fig. 9: The 2D electrostatic potential contours of channel cut plane along z direction. The data are calculated from numerical simulation. The simulated device parameters are Lg = 20 nm, tox = 2 nm, R = 5 nm, Vgs = –1 V, and Vds = 0.05 V.

φð0; z0 Þ ¼ Vref

Vds þ z0 þ Lg

sffiffiffiffiffi  1  2X fn nπ cn − 2 sin z0 rn Lg n¼1 Lg

ð16Þ

z₀ can be found by letting ∂φð0; zÞ |z¼z0 ¼ 0 ∂z

ð17Þ

For a long-channel device, only the first-order term is considered and z₀ can be approximated as   Lg Vds ð18Þ z0 ¼ arccos π 2½2ðVFB − Vgs Þ þ Vds  From Eqn. (18), it can be observed that z₀ is equal to Lg/2 for Vds = 0 V. When Vds ¼ 6 0V, the position of the minimum potential is slightly closer to the source region, slightly less than Lg/2. The value of z0 is calculated to be 0.4Lg – 0.5Lg. In the proposed analytical threshold voltage model, z0 is set to be 0.45 Lg for simplification. Let φð0; z0 Þ be equal to zero; for the first-order approximation, namely only n = 1 is reserved, one obtains Vths

" # Vds z0 kT qNd Lg 2 1 π ð Lg þ2 q Þ ¼ VFB þ ð Þ ð1 − a1 Þ þ Vds − a1 0 sinðπz εsi π 2 2 Lg Þ

ð19Þ

14  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

where a1 ¼

εsi λ1 I1 ðRλ1 Þ þ I0 ðRλ1 Þ Cox

ð20Þ

For a long-channel device with r1 R  1 andz0 ≈ Lg =2, a second-order Taylor expansion for a1 , Eqn. (19) can be reduced to Vthl Vthl

  qNd R qNd R2 1 π R2 π 2 εsi Rπ 2 Vds kT ¼ VFB − − þ Vds − ð1 þ þ Þð þ2 Þ 4εsi 4L2g 2Cox L2g 2 2Cox 2 2 q

ð21Þ

Eqn. (21) is identical to the threshold voltage for long-channel JL cylindrical surrounding-gate MOSFETs described by Eqn. (1). The deviation between them is from two reasons: different definitions of threshold voltage; the first order approximation and the effect of drain voltage are only included in Eqn. (21) whereas they are not contained in (Eqn. 1). Figure 10 displays a comparison between the analytical results and the numerical results for the threshold voltage versus channel radius and gate length. It can be observed that the threshold voltage is very sensitive to the channel radius because the leaky path is inside the bulk instead of at the silicon/gate dielectric layer interface. This is inherently different from the conventional inversion mode MOSFETs. Moreover, the threshold voltage is reduced as the gate length decreases. This effect is known as the threshold voltage roll-off, which is a kind of typical SCEs. To effectively suppress this effect, the channel diameter should be much smaller than the gate length. 0.50

Threshold voltage, Vths (V)

0.45 0.40 0.35 tox = 0.5 nm

0.30

Vds = 0.05 V 0.25

Nd = 1 x 1019 cm–3

R = 5 nm R = 6 nm R = 7 nm

0.20 Lines: numerical simulation Symbols: analytical model

0.15 0.10 10

20

30

40

50

60

Gate length, Lg (nm)

Fig. 10: Comparison of Vth versus channel length between the analytical model and simulation results with different radiuses. The simulated device parameters are tox = 0.5 nm, Vds = 0.05 V, and Nd = 1 × 10¹⁹ cm–3.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



15

Threshold voltage, Vths (V)

0.45 0.40 0.35 0.30

R = 6 nm Vds = 0.05 V

tox = 0.5 nm tox = 0.8 nm

0.25

Nd = 1 x 1019 cm–3

tox = 1.1 nm

0.20

Lines: numerical simulation Symbols: analytical model

0.15 10

20

30 40 Gate length, Lg (nm)

50

60

Fig. 11: Comparison of Vth versus channel length between the analytical model and simulation results with different equivalent oxide layer thicknesses. The simulated device parameters are R = 6 nm, Vds = 0.05 V, and Nd = 1 × 10¹⁹ cm–3.

Figure 11 displays a comparison between the analytical results and the numerical results for the threshold voltage versus equivalent oxide layer thickness and gate length. It is obvious that as tox increases, Vths decreases obviously. This trend agrees with the reported results [34–37].

2.3.3

Subthreshold drain current model

Using the obtained expression of the channel potential solution, the subthreshold current density can be calculated. Gradual channel approximation (GCA) is used. Jðr; zÞ ¼ qun nðr; zÞ

dφn ðzÞ dz

ð22Þ

where μn is the effective electron mobility. φn is the electron quasi Fermi potential, which is 0 V and Vds at source end and drain end, respectively. n(r, z) is the electron concentration and the distribution of electrons is assumed to be restricted to Boltzmann statistic law   qðφðr; zÞ − φn − Vref Þ ð23Þ nðr; zÞ ¼ Nd exp kT Aforementioned, the drain current flows through the bulk/volume instead of the interface between the channel and the gate dielectric. Thus, the impurity scattering mechanism dominates carrier mobility degradation. Masetti model is used to

16  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

compute the carrier effective mobility in according to the experimental data of Si MOSFETs [40]. By integrating the current density J(r, z) through the cross-sectional area in polar coordinates, the subthreshold drain current with respect to z can be expressed as [37] Ids ¼ 2πqµn

dφn × dz

{

Z 0

R

 qðφðr; zÞ − φn − Vref Þ dr rNd exp kT 

}

A simple integration from 0 to L along the z direction, Ids can be rewritten as     qVref qVds 1 − exp − kT 2πNd un kTexp − kT Ids ¼ Z L 1  dz  Z R qφðr;    z Þ 0 dr rexp kT 0

ð24Þ

ð25Þ

Drain current, Ids (A)

where k is the Boltzmann’s constant and T is absolute temperature. Figure 12 shows that the subthreshold drain current from both numerical simulation and analytical model varies with the gate voltage for different gate lengths. It can be seen that that the subthreshold leakage current increases when the gate length decreases. This results from the threshold voltage roll-off effect. 10–2 10–3 10–4 10–5 10–6 10–7 10–8 10–9 10–10 10–11 10–12 10–13 10–14 10–15 10–16

Lines: numerical simulation Symbols: analytical model

Lg = 15 nm Lg = 25 nm Lg = 35 nm R = 6 nm tox = 1.1 nm Vds = 0.5 V Nd = 1 x 1019 cm–3, μn = 108 cm2/Vs, Ref. (40) 0.0

0.2

0.4 0.6 Gate voltage, Vgs (V)

0.8

1.0

Fig. 12: Subthreshold drain current versus gate voltage for different gate lengths. The simulated device parameters are R = 6 nm, tox = 1.1 nm, Vds = 0.5 V, and Nd = 1 × 10¹⁹ cm–3.

Figure 13 presents a comparison of the transfer characteristics between the analytical model and numerical simulation results for different doping concentrations. The

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



17

Drain current, Ids (A)

values of effective electron mobility for different doping concentrations are calculated by the Masett model. The results from the analytical model are in good agreement with those of simulation. It is observed that the leakage current increases dramatically when the doping concentration slightly enlarges. Higher doping concentration makes the depletion of carriers more difficult, degrading the subthreshold behaviors. Thus, the on-state to off-state drain current ratio can be improved by controlling doping concentration of the channel, such as using the nonuniform doping technique [45]. Figure 14 plots a comparison of the transfer characteristics between the analytical model and numerical simulation results for different channel radiuses. The results from the model agree with those from numerical simulation. The model curves begin to deviate from the simulation curves when the JLCSG transistor starts to operate beyond the subthreshold region because of the non-ignorable mobile carriers. As the channel radius increases linearly, the leakage current is dramatically enlarged because the gate controllability over the channel decreases. Therefore, the off-state current could be suppressed using an adequately small channel radius for a given gate length. 10–3 10–4 Lines: numerical simulation 10–5 Symbols: analytical model 10–6 R = 6 nm 10–7 tox = 1.1 nm –8 10 Lg = 25 nm –9 10 –10 V ds = 0.5 V 10 10–11 10–12 10–13 Nd = 1 x 1019 cm–3, μn = 108 cm2/Vs, Ref. (40) 10–14 19 –3 2 –15 N d = 0.8 x 10 cm , μn = 117 cm /Vs 10 19 –3 –16 Nd = 0.6 x 10 cm , μn = 130 cm2/Vs 10 –17 10 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 Gate voltage, Vgs (V) Fig. 13: Comparison of Ids–Vgs curves between the analytical model and simulation results with different doping concentrations. The simulated device parameters are tox = 1.1 nm, Vds = 0.5 V, Lg = 25 nm, and R = 6 nm.

To study the influence of different gate lengths and drain voltages on the subthreshold behaviors of the JLCSG transistor devices, the transfer characteristics from the analytical model are compared with the results from numerical simulation. As shown in Figure 15, excellent agreement is achieved in the subthreshold region, indicating that the developed model is valid. On one hand, for a given channel radius,

18  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Drain current, Ids (A)

the threshold voltage roll-off effect is clearly observed. On the other hand, for a fixed gate length, a large drain voltage can increase the on-state current, but it also degrades the subthreshold behaviors because of the DIBL effect. The DIBL coefficient could be defined as the difference in the threshold voltage when the drain voltage is increased from 0.05 to 1.0 V [DIBL = Vths(Vds = 0.05 V) – Vths(Vds = 1 V)]. The DIBL coefficients for JLCSG transistor devices with Lg = 15 nm and 25 nm are extracted to be approximately 200 and 54 mV/V, respectively. 10–3 Lines: numerical simulation 10–4 Symbols: analytical model 10–5 10–6 10–7 10–8 R = 6 nm 10–9 –10 R = 7 nm 10 R = 8 nm 10–11 –12 10 10–13 Lg = 25 nm tox = 1.1nm 10–14 10–15 WF = 4.8 eV 10–16 Vds = 0.5 V 10–17 Nd = 1 x 1019 cm–3, μn = 108 cm2/Vs, Ref. (40) 10–18 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0

Gate voltage, Vgs (V)

Drain current, Ids (A)

Fig. 14: Subthreshold drain current versus gate voltage for different radiuses. The simulated device parameters are Lg = 25 nm, tox = 1.1 nm, Vds = 0.5 V, and Nd = 1 × 10¹⁹ cm–3. 10–3 Lines: numerical simulation 10–4 Symbols: analytical model 10–5 10–6 10–7 Lg = 25 nm, Vds = 1 V 10–8 Lg = 25 nm, Vds = 1 V –9 10 Lg = 25 nm, Vds = 0.05 V 10–10 10–11 Lg = 25 nm, Vds = 0.05 V 10–12 Lg = 15 nm, Vds = 1 V 10–13 Lg = 15 nm, Vds = 1 V –14 10 Lg = 15 nm, Vds = 0.05 V 10–15 R = 6 nm 10–16 tox = 1.1 nm Lg = 15 nm, Vds = 0.05 V 10–17 μn = 108 cm2/Vs, Ref. (40) 10–18 –0.4 –0.2 0.0 0.2 0.4 0.6 0.8 1.0 Gate voltage, Vgs (V)

Fig. 15: Comparison of Ids–Vgs curves between the analytical model and numerical simulation results with different gate lengths and drain voltages. The simulated device parameters are tox = 1.1 nm, R = 6 nm, and Nd = 1 × 10¹⁹ cm–3.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless

2.3.4



19

Subthreshold swing model

The subthreshold swing, SS, is defined as the changes in the gate voltage required increasing or reducing the subthreshold drain current by one decade. From Eqn. (25), SS is given by 2 0 3−1 1 6 B 7 C 6 B 7 C 6 B2πN u kTexpð − qVref Þ1 − expð − qVds ÞC 7 ∂Vgs d n 6 B 7 C kT kT ¼ 6∂ B SS ¼ C=∂Vgs 7 Z L 7 C ∂logðIds Þ 6 B 1 6 B 7 C   dz Z R 4 @ 5 A qφðr;     z Þ 0 dr r exp kT 0

ð26Þ

In this model, the subthreshold drain current cannot be written as an explicit expression of the applied voltages, and the integral equation has to be solved numerically. This may limit the use of this model in circuit simulation, because it leads to an increase of the simulation time, compared with the explicit models. However, due to rapid decay of the Fourier–Bessel series shown in Figure 3, the first three terms dominate the whole series. Therefore, in compact modeling processes, to obtain a better computation efficiency, one can use the first three terms of the series to calculate the subthreshold drain current. Figure 16 presents the subthreshold swing versus gate length for different equivalent oxide layer thicknesses. SS values increase significantly as the oxide becomes thicker because the gate gradually loses control of the channel. Hence, a thin equivalent oxide thickness is preferred to suppress the SCEs. To obtain a small tox and suppress the gate tunneling current, the high-k dielectric materials are proposed [3]. High-k dielectric materials can eliminate the gate tunneling current with thicker physical thickness and keep strong gate controllability at the same time. It can be observed that for short-channel JLCSG transistor, the degradation is more serious. For long channel devices, the ideal value of SS is approximately 60 mV/decade. This limitation is known as the ‘Boltzmann tyranny’. To overcome this bottleneck, many new device structures have been proposed, such as the impact-ionization FET (I-MOS) [46], tunneling FET [47], nanoelectromechanical FET [48] and negative capacitance FET [49]. Figure 17 displays a comparison between the analytical results and the numerical results of subthreshold swing versus radius. As R increases, the gate controllability over the center channel gets weaker, and the leakage current increases. This phenomenon degrades the subthreshold swing.

20  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Subthreshold swing, SS (mV/dec)

100

Lines: numerical simulation Symbols: analytical model tox = 0.5 nm

90

tox = 0.8 nm tox = 1.1 nm 80

WF = 4.8 eV Vds = 0.5 V 70

R = 6 nm

60 15

20

25

30

35

40

45

Gate length, Lg (nm)

Fig. 16: Subthreshold swing versus the gate length for various equivalent oxide layer thicknesses. The simulated device parameters are R = 6 nm, Vds = 0.5 V, and Nd = 1 × 10¹⁹ cm–3.

Subthreshold swing, SS (mV/dec)

130

Lines: numerical simulation Symbols: analytical model

120 110

R = 6 nm R = 7 nm R = 8 nm

100 90

tox = 1.1 nm

80

WF = 4.8 eV Vds = 0.5 V

70 60 15

20

25 30 35 Gate length, Lg (nm)

40

45

Fig. 17: Subthreshold slope versus the gate length for various radiuses. The simulated device parameters are tox = 6 nm, Vds = 0.5 V, and Nd = 1 × 10¹⁹ cm–3.

3

Germanium junctionless cylindrical surrounding-gate MOSFETs

Germanium has been considered as one of channel materials in replacement of Si with great promise for future high-speed CMOS technology because of its high electron mobility (3,900 cm²/Vs) and hole mobility (1,900 cm²/Vs). In fact, Ge was

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



21

the first material used in semiconductor devices even though Si governs semiconductor electronics industry since Si transistor was invented. This resulted from the bad interfacial quality of Ge MOSFETs with a big leakage current. As a consequence, the effective carrier mobility is very low due to the interfacial scattering. However, it could be different for JLTs due to the bulk conduction mechanism of junctionless transistors [21]. The proposed analytical model is also suitable for Ge JLCSG MOSFET only with Ge material parameters replacing those of Si as shown in Figure 18. Lg Gate

Vgs tox Drain

Source

Oxide layer

Germanium channel

(0,0) z Nd

Nd

r

R Nd

Vds

Oxide layer Gate

Vgs

Fig. 18: Cross-sectional schematic diagram along channel direction and coordinates of an n-type Ge JLCSG MOSFET.

2D electrostatic potential contours of the Ge channel cut plane along z-direction calculated from the analytical model are compared with simulation results of numerical simulator in Figure 19 for a Ge JLCSG MOSFET. The electrostatic potential distribution in Ge JLCSG MOSFET is similar to the potential distribution in Si JLCSG MOSFET as shown in Figure 9. The agreement is quite good (with relative error less than 5%). It is clear that electrostatic potential at r = 0 nm has a minimum in the z-direction. The minimum is located approximately midpoint between the source and the drain. Potential variation in the r-direction is much less than that in the z-direction.

22  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

Channel position along r direction (nm)

6

Dash line: Sentaurus TCAD Solid line: Model

4

0.15

–0.15

0.05

0.15 0.05 0.25

2 0.25 –0.10 0

0

(z0,0)

0.05

–0.05 –0.10

–2

0.20

–4 –6

0.10

0.10

0

2

–0.15

0.20

4 6 8 10 12 14 16 Channel position along z direction (nm)

18

20

Fig. 19: The 2D electrostatic potential contours of channel cut plane along z direction for a n-type Ge JLCSG MOSFET. The simulated device parameters are Lg = 20 nm, tox = 1 nm, R = 6 nm, Vgs = 0.0 V, and Vds = 0.05 V.

Figure 20 presents the electrostatic potential distribution in the channel center as a function of channel radius for a Ge JLCSG MOSFET. Analytical results for the proposed model are in good agreement with the 3D simulation results. Similar to the Si JLCSG MOSFET, as the channel radius increases, the minimum central potential is upraised. This means a smaller threshold voltage for a larger channel radius, degrading the subthreshold characteristics. Hence, a smaller channel radius is desired to reduce the leakage current.

Central electrostatic potential (V)

0.4 Lines: numerical simulation Symbols: analytical model

0.3

R = 6 nm R = 7 nm R = 8 nm

0.2 0.1 0.0 –0.1 –0.2

Vds = 0.05 V Vgs = 0 V tox = 0.5 nm Nd = 1 x 1019 cm–3

0

5 10 15 Position along channel direction, z (nm)

20

Fig. 20: Central electrostatic potential along channel direction for different radiuses. The simulated device parameters are Lg = 20 nm, Vgs = 0 V, Vds = 0.05 V, tox = 0.5 nm, and Nd = 1 × 10¹⁹ cm–3.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



23

Figure 21 displays a comparison between the analytical results and the numerical results for the threshold voltage versus channel radius and gate length. The threshold voltage is very sensitive to the channel radius because the most leaky path is inside the bulk instead of at the silicon/gate dielectric layer interface. This is inherently different from the conventional inversion mode MOSFETs. A bigger R can weaken the gate control ability over channel center obviously due to the mechanism of bulk conduction. Moreover, the threshold voltage is reduced as the gate length decreases. To effectively suppress this effect, the channel diameter should be much smaller than the gate length. 0.68 0.66

Threshold voltage, Vth (V)

0.64

Lines: numerical simulation Symbols: analytical model

0.62 0.60 0.58 0.56 0.54 0.52

tox = 0.5 nm

0.50

Vds = 0.05 V

0.48

Nd = 1 x 1019 cm–3

0.46

R = 5 nm R = 6 nm R = 7 nm

0.44 20

30 40 Gate length, Lg (nm)

50

60

Fig. 21: Comparison of Vth versus channel length between the analytical model and simulation results with different radiuses. The simulated device parameters are tox = 0.5 nm, Vds = 0.05 V, and Nd = 1 × 10¹⁹ cm–3.

Figure 22 plots a comparison of the transfer characteristics between the analytical model and numerical simulation results for different channel radiuses for a Ge JLCSG MOSFET. The results from the analytical model are in good agreement with those from simulation. When the channel radius increases, the subthreshold leakage current is dramatically enlarged because the gate controllability over the channel decreases. Therefore, the off-state leakage current could be suppressed using an adequately small channel radius for a given gate length. However, it also can be seen that the on-state current also increases with R increasing. Therefore, R must be a tradeoff parameter to obtain a big on/off drain current ratio. The electron mobility of Ge is around three times than that of Si calculated from Masetti model, as shown in Figures 14 and 22. The Ge parameters for Masetti model are extracted from the experimental data [50, 51].

24  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

10–3

Symbols: numerical simulation Lines: analytical model

10–4

Drain current, Ids (A)

10–5

R = 6 nm R = 7 nm R = 8 nm

10–6 10–7 10–8 10–9

Vds = 0.5 V

10–10

Nd = 1 x 1019cm–3 Lg = 25 nm

10–11

tox = 1.1 nm

10–12

μn = 315 cm2/Vs, Ref. (50, 51)

10–13 0.0

0.2

0.4 0.6 0.8 Gate voltage, Vgs ( V)

1.0

1.2

Fig. 22: Subthreshold drain current versus gate voltage for different radiuses. The simulated device parameters are Lg = 25 nm, tox = 1.1 nm, Vds = 0.5 V, and Nd = 1 × 10¹⁹ cm–3.

Figure 23 displays a comparison between the analytical results and the numerical results of subthreshold swing versus radius for a Ge JLCSG MOSFET. As R increases, the controllability of the gate over the channel gets weaker, and the subthreshold leakage current increases as shown in Figure 22. This phenomenon degrades the subthreshold performances.

Subthreshold swing (mV/dec)

130 Lines: numerical simulation Symbols: analytical model

120

R = 6 nm R = 7 nm R = 8 nm

110 100

tox = 0.5 nm

90

Vds = 0.5 V Nd = 1 x 1019 cm–3

80 70 60 15

20

25

30

35

40

Gate length, Lg (nm) Fig. 23: Subthreshold swing versus the gate length for various radiuses. The simulated device parameters are tox = 0.5 nm, Vds = 0.5 V, and Nd = 1 × 10¹⁹ cm–3.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless



25

4 Summary A series of analytical models were developed to describe the subthreshold behaviors of Si and Ge JLCSG MOSFETs by solving the full 2D Poisson’s equation. The electrostatic potential, threshold voltage, subthreshold drain current and subthreshold swing were examined in detail by the established analytical models and numerical simulation. Threshold voltage roll-off and the DIBL effect were also discussed comprehensively. Interfacial traps between the semiconductor channel and gate dielectric layer aren’t included in our analytical models and numerical simulation for simplicity. It is reasonable for Si JLCSG MOSFET whereas the interfacial trap effects are more serious for Ge JLCSG MOSFET. The effects of interfacial traps should be covered in our analytical model in our future work. The results predicted by the proposed models are in good agreement with those of numerical simulation. These models provide physical insight into the physics of Si and Ge JLCSG devices. The proposed analytical models can also be included in the compact models of JLCSG transistors. Acknowledgment: This work was funded in part by the National Science and Technology Major Project (No. 2011ZX02708-002 and No. 2013ZX02303-003), the Tsinghua National Laboratory for Information Science and Technology (TNList) Crossdiscipline Foundation, and by the National Natural Science Foundation of China (No. 61306105).

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26  Chunsheng Jiang, Renrong Liang, Jing Wang, and Jun Xu

[9]

[10] [11]

[12] [13] [14] [15]

[16] [17] [18]

[19]

[20]

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Barraud S, Berthomé M, Coquand R, Cassé M, Ernst T, Samsonm M P, Poiroux T. Scaling of trigate junctionless nanowire MOSFET with gate length down to 13 nm. IEEE Electron Devices Lett. 2012, 33, 1225–7. Lee C-W, Nazarov A N, Ferain I, Akhavan N D, Yan R, Razavi P, et al. Low subthreshold slope in junctionless multigate transistors. Appl. Phys. Lett. 2010, 96, 102–106. Song Y, Zhang C, Dowdy R, Chabak K, Mohseni P K, Choi W, et al. III–V Junctionless gate-allaround nanowire MOSFETs for high linearity low power applications. IEEE Trans. Electron Dev. 2014, 35, 324–6. Gundapaneni S, Ganguly S, Kottantharayil A. Bulk planar junctionless transistor (BPJLT): An attractive device alternative for scaling. IEEE Electron Devices Lett. 2011, 32, 261–3. Colinge J P. FinFETs and Other Multi-Gate Transistors, Springer, New York, 2008. Pillarisetty R. Academic and industry research progress in germanium nano devices. Nature 2011, 479, 324–8. Brunco D P, Jaeger B D, Eneman G, Mitard J, Hellings G, Satta A, Heyns M M. Germanium MOSFET devices: Advances in materials understanding, process development, and electrical performances. J. Electrochem. Soc. 2008, 155, 552–61. Rosenberg J J, Martin S C. Self-aligned germanium MOSFETs using a nitrided native oxide gate insulator. IEEE Electron Devices Lett. 1988, 9, 639–40. Thareja G, Liang J, Chopra S, Adams B, Patil N, Cheng S L, Nishi Y. High performances germanium n-MOSFET with antimony dopant activation beyond 1×1020 cm–3. IEDM Tech. Dig 2010, 245–8. Whang S J, Lee S J, Gao F, Wu N, Zhu C X, Pan J S, Kwong D L. Germanium p-& n-MOSFETs fabricated with novel surface passivation (plasma-PH 3 and thin AlN) and TaN/HfO 2 gate stack. IEDM Technical Digest. 2004, 307–10. Chui C O, Kim H, McIntyre P C, Saraswat K C. A germanium NMOSFET process integrating metal gate and improved hi-/spl kappa/dielectrics. In Electron Devices Meeting, 2003. IEDM’03 Technical Digest 2003, 18.3.1–18.3.4. Shang H, Lee K L, Kozlowski P, D’Emic C, Babich I, Sikorski E, Haensch W. Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate. IEEE Electron Devices Lett. 2004, 25, 135–7. Kabuyanagi S, Nishimura T, Nagashio K, Toriumi A. High electron mobility in Germanium junctionless n-MOSFETs. ECS Trans. 2013, 58, 309–15. Synopsys. T. Sentaurus User’s Manual, Version D-2010.03, 2010. Lee C W, Borne A, Ferain I, Afzalian A, Yan R, Akhavan N D, Colinge J P. High-temperature performances of silicon junctionless MOSFETs. IEEE Trans. Electron Dev. 2010, 57, 620–5. Choi S J, Moon D I, Kim S, Duarte J P, Choi Y K. Sensitivity of threshold voltage to nanowire width variation in junctionless transistors. IEEE Electron Devices Lett. 2011, 32, 125–7. Souza M D, Pavanello M A, Trevisoli R D, Doria R T, Colinge J. Cryogenic operation of junctionless nanowire transistors. IEEE Electron Devices Lett. 2011, 32, 1322–4. Juan P D, Choi S J, Choi Y K. A full-range drain current model for double-gate junctionless transistors. IEEE Trans. Electron Dev. 2011, 58, 4219–25. Duarte J P, Choi S J, Moon D I, Choi Y K. A nonpiecewise model for long-channel junctionless cylindrical nanowire FETs. IEEE Electron Devices Lett. 2012, 33, 155–7. Jin X S, Liu X, Hyuck-In K, Jong-Ho L. A continuous current model of accumulation mode (junctionless) cylindrical surrounding-gate nanowire MOSFETs. Chin. Phys. Lett. 2013, 30, 0385021–038502-4. Kim S K, Kim W D, Kim K M, Hwang C S, Jeong J. High dielectric constant TiO2 thin films on a Ru electrode grown at 250 C by atomic-layer deposition. Appl. Phys. Lett. 2004, 85, 4112–4.

Subthreshold Behaviors of Nanoscale Silicon and Germanium Junctionless

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[44] [45] [46] [47] [48]

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Georgiev Y M, Yu R, Petkov N, Lotty O, Nightingale A M, Duffy R, Holmes J D. Silicon and germanium junctionless nanowire transistors for sensing and digital electronics applications. In Functional Nanomaterials and Devices for Electronics, Sensors and Energy Harvesting 2014, 367–88. Kao J, Chandrakasan A, Antoniadis D. Transistor sizing issues and tool for multi-threshold CMOS technology. In Proceedings of the 34th Annual Design Automation Conference 1997, 409–14. Sorée B, Magnus W, Pourtois G. Analytical and self-consistent quantum mechanical model for a surrounding gate MOS nanowire operated in JFET mode. J. Comput. Electron. 2008, 7, 380–3. Cheralathan M, Cerdeira A, Iniguez B. Compact model for long-channel cylindrical surrounding-gate MOSFETs valid from low to high doping concentrations. Solid State Electron. 2011, 55, 13–8. T.-K. Chiang. A new quasi-2-D threshold voltage model for short-channel junctionless cylindrical surrounding gate (JLCSG) MOSFETs. IEEE Trans. Electron Dev. 2012, 59, 3127–9. Hu G, Xiang P, Ding Z, Liu R, Wang L, Tang T. Analytical models for electric potential, threshold voltage, and subthreshold swing of junctionless surrounding-gate transistors. IEEE Trans. Electron Dev. 2014, 61, 688–95. Chiang T K. A quasi-two-dimensional threshold voltage model for short-channel junctionless double-gate MOSFETs. IEEE Trans. Electron Dev. 2012, 59, 3127–9. Li C, Zhuang Y, Di S, Han R. Subthreshold behavior models for nanoscale short-channel junctionless cylindrical surrounding-gate MOSFETs. IEEE Trans. Electron Dev. 2013, 60, 3655–62. Jiang C, Liang R, Wang J, Xu J. A two-dimensional analytical model for short-channel junctionless double-gate MOSFETs. AIP Advances 2015, 5, 057122. Hu G X, Liu R, Tang T A, Ding S J, Wang L L. Theory of short-channel surrounding-gate metal–oxide–semiconductor field-effect-transistors. Jpn. J. Appl. Phys. 2007, 46, 1437. Masetti G, Severi M, Solmi S. Modeling of carrier mobility against carrier concentration in arsenic-, phosphorus-, and boron-doped silicon. IEEE Trans. Electron Dev. 1983, 30, 764–9. Liu Z H, Hu C, Huang J H, Chan T Y, Jeng M C, Ko P K, Cheng Y C. Threshold voltage model for deep-submicrometer MOSFETs. IEEE Trans. Electron Dev. 1993, 40, 86–95. Mutlu A A, Rahman M. Two-dimensional analytical model for drain induced barrier lowering (DIBL) in short-channel MOSFETs. In Southeastcon, Proceedings of the IEEE 2002, 340–4. Kloes A, Weidemann M, Goebel D, Bosworth B T. Three-dimensional closed-form model for potential barrier in undoped FinFETs resulting in analytical equations for and subthreshold slope. IEEE Trans. Electron Dev. 2008, 55, 3467–75. Chen Q, Agrawal B, James D M. A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs. IEEE Trans. Electron Dev. 2002, 49, 1086–90. Mondal P, Ghosh B, Bal P. Planar junctionless transistor with non-uniform channel doping. Appl. Phys. Lett. 2013, 102, 133505. Choi W Y, Song J Y, Lee J D, Park Y J, Park B-G. A novel biasing scheme for I-MOS (impact-ionization MOS) devices. IEEE Trans. Nanotechnol. 2005, 4, 322–5. Ionescu A M, Riel H. Tunnel field-effect transistors as energy efficient electronic switches. Nature 2011, 479, 329–37. Akarvardar K, Eggimann C, Tsamados D, Singh C Y, Wan G C, Ionescu A M, Howe R T, Wong H S P. Analytical modeling of the suspended-gate FET and design insights for low-power logic. IEEE Trans. Electron Dev. 2008, 55, 48–59. Salahuddin S, Datta S. Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett. 2008, 8, 405–10. Mitard J, Shea C, Jaeger D B, Pristera A, Wang G, Houssa M, et al. Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI. In VLSI Symp. Tech. Dig. 2009, 82–3. Hellings G, Eneman G, Krom R, Jaeger D B, Mitard J, Keersgieter D A, Meyer D K. Electrical TCAD simulations of a germanium pMOSFET technology. IEEE Trans. Electron Dev. 2010, 57, 2539–46.

Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation Abstract: With complementary metal-oxide semiconductor feature size rapidly approaching ultimate scaling limits, the electron spin attracts much attention as an alternative to the electron charge degree of freedom for low-power reprogrammable logic and nonvolatile memory applications. Silicon, the main element of microelectronics, appears to be the perfect material for spin-driven applications. Despite an impressive progress in understanding spin properties in metal-oxide-semiconductor field-effect transistors (MOSFETs), spin manipulation in a silicon channel by means of the electric field–dependent Rashba-like spin–orbit interaction requires channels much longer than 20 nm channel length of modern MOSFETs. Although a successful realization of the spin field-effect transistor seems to be unlikely without a new concept for an efficient way of spin manipulation in silicon by purely electrical means, it is demonstrated that shear strain dramatically reduces the spin relaxation, thus boosting the spin lifetime by an order of magnitude. Spin lifetime enhancement is achieved by lifting the degeneracy between the otherwise equivalent unprimed subbands by [110] uniaxial stress. The spin lifetime in stressed ultra-thin body silicon-on-insulator structures can reach values close to those in bulk silicon. Therefore, stressed silicon-on-insulator structures have a potential for spin interconnects. Keywords: Ultra-thin body SOI, shear strain, spin–orbit interaction, inter- and intravalley scattering, spin relaxation, spin lifetime enhancement, spin field-effect transistor, tunneling magnetoresistance.

1 Introduction Continuous miniaturization of complementary metal-oxide semiconductor (CMOS) devices has made possible a tremendous increase in performance, speed, and density of modern integrated circuits. Numerous outstanding technological challenges have been resolved on this exciting journey. Among the most crucial technological changes recently adopted by the semiconductor industry was the introduction of a new type of multigate three-dimensional (3D) transistors [1]. This technology, combined with strain techniques and high-k dielectrics/metal gates, offers great performance and power

Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr, Institute for Microelectronics, TU Wien, Gußhausstraße 27–29/E360, A-1040 Wien, Austria; E-mail: iue.tuwien.ac.at.

30  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

advantages over the planar structures and allows continuous scaling down to 14 nm feature size [2]. There are good indications that device miniaturization with some technological adaptations will continue its pace down to the 10-nm technology node. A multigate 3D device architecture potentially allows device scaling beyond 10 nm, where transport in the channel is supposed to become nearly ballistic. However, even though the transistor size is scaled down, the load capacitance per unit area of a circuit stops decreasing. This suggests that the on-current must stay constant in order to maintain appropriate high-speed operation, which clearly puts limitations to the continuation of the increase in the performance of integrated circuits, and the need for research to find alternative technologies and computational principles becomes urgent. The principle of metal-oxide-semiconductor field-effect transistor (MOSFET) operation is fundamentally based on the charge degree of freedom of an electron: The electron charge interacts with the gate-induced electric field, which can close the transistor by creating a potential barrier. Another intrinsic electron property, the electron spin, attracts at present much attention as a possible candidate for complimenting or even replacing the charge degree of freedom in future electron devices [3, 4]. The electron spin state is characterized by one of the two of its possible projections on a given axis and could be potentially used in digital information processing. In addition, it takes an amazingly small amount of energy to invert the spin orientation, which is necessary for low-power applications. Even more, the electron spin as a vector may be pointed not only up or down but rather in any direction on a unit Bloch sphere. This opens the way to use the whole Bloch sphere of states to process and store information by initializing, manipulating, and detecting the spin orientation. Because the electron spin is a purely quantum mechanical object, the set of states on a Bloch sphere is called a quantum bit, or a qubit, as opposed to a bit of classical binary information. A quantum computer uses qubits for information processing. Due to their quantum mechanical nature, several qubits could form a superposition and be in an entangled state. The initially proposed quantum computation scheme [5] was based on spins in quantum dots. A successful implementation of spins based on quantum computer requires the possibility of efficient spin initiation, coherent manipulation, and reliable readout. An unprecedented advantage in these fields has been achieved by the researchers in the last decade [6]. The experiments on electron spins in semiconductors were performed at cryogenic temperatures, where a relaxation time of several seconds in silicon was demonstrated [7]. Although these results are encouraging, the development of a robust two-qubit gate becomes a pressing challenge [8] before proceeding to a larger computational network. Until recently, silicon, the main material used by modern microelectronics, was remaining aside from the main stream of spin-related applications. Certainly, the use of silicon for spin-driven devices will greatly facilitate their integration with MOSFETs on the same chip. In addition, silicon possesses several unique properties extremely attractive for spin-driven applications. It is predominantly composed of nuclei of the ²⁸Si isotope without magnetic moment, which favors longer spin lifetime. Another

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source of spin relaxation, the spin–orbit interaction, is also weak in silicon. Because of these properties, electron spin states of conduction electrons in silicon should show better stability and lower decoherence, which make silicon a perfect candidate for spin-driven device applications. Although it should be straightforward to inject spinpolarized carriers into silicon from a ferromagnetic contact, due to a fundamental conductivity mismatch problem [9] between a ferromagnetic metal contact and the semiconductor, the problem was without solution for a long time. A special technique [10] based on the attenuation of hot electrons with spins antiparallel to the magnetization of the ferromagnetic film allowed creating an imbalance between the electrons with spin up and spin down in silicon, thus injecting spin-polarized current. The spincoherent transport through the device was studied by applying an external magnetic field, causing precession of spins during their propagation from source to drain. The detection is performed with a similar hot electron spin filter. Although the drain current is fairly small due to the carriers’ attenuation in the source and drain filters as compared to the current of injected spins, the experimental setup represents a first spin-driven device, which can be envisaged working at room temperature. Contrary to the MOSFET, however, the described structure is a two-terminal device. Nevertheless, the first demonstration of coherent spin transport through an undoped 350 μm thick silicon wafer [11] has triggered a systematic study of spin transport properties in silicon [12].

2 Silicon spin field-effect transistor The spin field-effect transistor (SpinFET) is a future semiconductor spintronic device promising a performance superior to what can be achieved with the present transistor technology. SpinFETs are composed of two ferromagnetic contacts (source and drain), linked by a nonmagnetic semiconductor channel region. The ferromagnetic contacts inject and detect spin-polarized electrons, analogous to polarizer and analyzer as indicated already long ago by Datta and Das [13]. Because of the effective spin–orbit interaction into the channel, which depends on the perpendicular effective electric field, the spin of an electron injected from the source starts precessing. In order to distinguish this electric field-dependent spin–orbit interaction from the intrinsic electron spin–orbit interaction acting on any electron moving in a crystal potential, we term the electric field-dependent spin–orbit interaction as coupling. The electrons with spin, or, to be more precise, with the direction of the magnetic moment, aligned to the drain magnetization direction can easily leave the channel to the drain, thus contributing to the current. The total current through the device depends on the relative angle between the magnetization direction of the drain contact playing the role of an analyzer and the electron spin polarization at the end of the semiconductor channel. An additional current modulation is achieved by tuning the strength of the spin–orbit interaction in the semiconductor region, which

32  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

depends on the effective electric field and can be controlled by purely electrical means by applying a gate voltage. Although the SpinFET was proposed two decades ago [13], it has not been experimentally demonstrated up to now. In order to realize the SpinFET, the following requirements must be fulfilled [14]. First, an efficient spin injection in the channel (and detection) must be realized. Second, because the electron spin in the channel is not a conserved quantity and thus relaxes due to spin-flip processes, the corresponding scattering mechanisms must be detected and analyzed. It is important to identify the possibilities compatible with modern MOSFET technology, which can enhance the spin lifetime and spin diffusion length in the silicon channel. Finally, purely electrical means of spin manipulation in the channel must be identified to control the spin and thus the current flow to the drain. An example of such a manipulation is the gate voltage–dependent effective spin–orbit interaction defining the degree of the spin precession. Next we briefly discuss recent achievements and challenges for the practical realization of the SpinFET. Spin injection into silicon and other semiconductors by purely electrical means from a ferromagnetic metal electrode was not very successful until recently. The fundamental reason has been identified as an impedance mismatch problem [9]. Even though there is a large spin imbalance between the majority and minority spins in a metal ferromagnet, both channels with spin up and spin down are equally populated in a semiconductor due to the relatively small density of states as compared to that for the minority spins in a ferromagnet. In other words, because of the large resistance of the semiconductor, the voltage applied to the contact between the ferromagnet and the semiconductor drops completely within the semiconductor. Therefore, the properties of the contact are dominated by the nonmagnetic semiconductor, thus resulting in a current without spin polarization. One solution to overcome the impedance mismatch problem is the use of hot electron injection [10]; however, the efficiency of spin injection and detection is very limited. Another solution to the impedance mismatch problem is the introduction of a potential barrier between the metal ferromagnet and the semiconductor [15]. In this case the influx of carriers from the ferromagnet into the semiconductor is reduced to such an extent that the majority spins supply just enough carriers to support the complete occupancy of the corresponding states in the semiconductor. Under such conditions the minority spin flow in semiconductors will be a fraction of that for the majority spins defined by the spin polarization in the ferromagnet. This guarantees the existence of a spin-polarized current and the spin injection into the semiconductor. A successful experimental proof of spin injection at low temperature from an iron electrode through Al₂O₃ [16, 17] was demonstrated only in 2007. At room temperature spin injection into silicon was first demonstrated in 2009 [18]. The authors took heavily doped silicon samples to avoid an extended depletion layer causing large tunnel barriers. It was actually this depletion layer, not the impedance mismatch problem, that prevented for a long time all the successful electrical demon-

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stration of spin injection into silicon. It then follows that the tunnel contacts have to be optimized in order to facilitate spin injection: They must not be too thick to make the signal observable, but at the same time they must not be too transparent to avoid the impedance mismatch problem [12, 19]. Recently, tunnel contacts made of single-layer graphene [20] have been shown to deliver a contact resistance close to the optimum [21]. Electrical spin injection through silicon dioxide at temperatures as high as 500 K has also been demonstrated [22]. The tunnel barrier in the contact of a ferromagnet to a semiconductor introduces spin-dependent interface resistances [12], defining the tunnel spin polarization. Due to the additional spin-filtering effect in MgO, the high-quality tunneling stack made of a Fe and MgO (001) crystalline barrier is expected to provide spin polarization up to 70% at room temperature [23]. Spin injection using MgO dielectric as a tunnel junction has been successfully demonstrated at room temperature [24, 25]. Currently, a reliable injection of spin into doped silicon has been demonstrated from a number of ferromagnetic electrodes through several dielectric tunnel barriers. Regardless of an ultimate success in demonstrating spin injection into silicon at room temperature, there are unsolved challenges that may put the results obtained in question or even compromise our present understanding of the spin injection process in general. There exists a several orders of magnitude discrepancy between the signal measured and the theoretical value [12]. The reasons for the discrepancies are heavily debated [12, 26, 27], and it is apparent that more research is needed to resolve this controversy. Spin can be injected into silicon by other techniques as well. The injection of spins by heat [28] is one of them, for which a spin current through the contact exists without a charge current. Another technique is spin charge pumping by inducing magnetic excitations in a material that is in contact with a semiconductor [29]. This technique is free of the impedance mismatch problem and can generate pure spin currents at room temperature [30]. The magnons are excited by the microwave. Although this technique is extremely useful to demonstrate spin injection and study spin transport in semiconductors, it remains to be seen if it is efficient enough for device applications [31]. The use of ferromagnetic contacts made of semiconductors would be another possible solution to the impedance mismatch problem. Unfortunately, no semiconductors with ferromagnetic properties surviving up to room temperature are known [32]. Another solution to resolve the impedance mismatch problem is to use half-metallic ferromagnets [33]. For the functionality of the Datta–Das SpinFET, the possibility to transfer the excess spin injected from the source to the drain electrode is essential. The excess spin is not a conserved quantity: While diffusing, it gradually relaxes to its equilibrium value, which is zero in a nonmagnetic semiconductor. It was demonstrated that spin can propagate through a 350-μm silicon wafer at liquid nitrogen temperatures. The lower estimation for the spin lifetime at room temperature obtained within the threeterminal injection scheme is of the order 0.1–1 ns [12]. The spin lifetime is determined by the spin-flip processes. Several important spin relaxation mechanisms are identified

34  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

[3, 4]. In silicon at elevated temperatures the spin relaxation due to the Elliot–Yafet mechanism [3, 4] becomes important. The Elliot–Yafet mechanism is mediated by the intrinsic interaction between the orbital motion of an electron and its spin. Due to the spin dependence, the microscopic spin–orbit interaction does not conserve the electron spin; thus it generates spin flips, which is the Yafet process. When the microscopic spin–orbit interaction is taken into account, the Bloch function with a fixed spin projection is not an eigenfunction of the total Hamiltonian. Because the eigenfunction always contains a contribution with an opposite spin projection, even spin-independent scattering with phonons generates a small probability of spin flips, which is the Elliot process. A good agreement between the experimentally observed and calculated spin lifetime as a function of temperature has been achieved, confirming that in bulk silicon the Elliot– Yafet mechanism is the dominant spin relaxation mechanism at ambient temperatures [34]. The main contribution to the spin relaxation was identified to be optical phonon scattering between the valleys residing at different crystallographic axis or f-phonon scattering [35, 36]. The intervalley scattering gets enhanced at high electric fields due to the accelerated f-phonon emission process [37], which results in an unusual behavior, when the reduction of the carrier transition time between the injector and the collector is accompanied by a contraction of spin polarization. However, a relatively large spin relaxation experimentally observed in electrically gated lateral-channel silicon structures [38, 39] indicates that the extrinsic interface-induced spin relaxation mechanism becomes important. This may pose an obstacle in realizing spin-driven CMOS-compatible devices, and a deeper understanding of fundamental spin relaxation mechanisms in silicon inversion layers, thin films, and fins is needed. The theory of spin relaxation must account for the most relevant scattering mechanisms that are due to electron–phonon interaction and surface roughness (SR) scattering. In order to evaluate the corresponding scattering matrix elements, the wave functions must be provided. To find the wave functions, an approach based on an effective k·p Hamiltonian appears to be rigorous enough to capture the most important physics while still allowing to keep the computational efforts bearable. The effective k·p Hamiltonian must include the effective spin–orbit interaction [35], which, apart from scattering, is the main ingredient of the Elliot–Yafet spin relaxation mechanism. In addition, the confinement potential is included. It is also desirable to have other effects such as a sufficiently accurate model of the conduction band valley, nonparabolicity and warping, and external stress [40] incorporated.

3 Subband wave functions in silicon-on-insulator structures The conduction band of bulk silicon consists of three pairs of valleys near the edges of the Brillouin zone along the [100], [010], and [001] crystallographic axes. Each state is

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation

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described by the valley index, the wave vector k, and the spin orientation (spin up and spin down) on a chosen axis. The Hamiltonian satisfying all the requirements listed earlier is written in the vicinity of the X-point of the Brillouin zone. It considers the two closest to the X-point valleys described by the basic functions X₁ and X₂′ augmented with the two possible spin projections: X1" ; X1# ; X2" 0 ; X2# 0 ; where ↑ and ↓ indicate the spin projection at the quantization z-axis. The Hamiltonian of the valley pairs along the [001]-axis is then given as [41] 
H1 H 3 ð1Þ H¼ H3y H2 with H1 , H2 , and H3 defined as " H1 ¼ " H2 ¼

# 2 2 2 ℏ2 k2z ℏ2 k0 kz ℏ ðkx þ ky Þ − þ þ UðzÞ I; 2ml ml 2mt # 2 2 2 ℏ2 k2z ℏ2 k0 kz ℏ ðkx þ ky Þ þ þ þ UðzÞ I; 2ml ml 2mt 2

ℏ2 kx ky 6 Dεxy − M H3 ¼ 6 4 ð−ky − kx iÞΔSO

ð2Þ

ð3Þ

3 ðky − kx iÞΔSO 7 7: ℏ2 kx ky 5 Dεxy − M

ð4Þ

Here I is the identity 2 × 2 matrix, mt and ml are the transversal and the longitudinal silicon effective masses, k0 = 0:15 × 2π=a is the position of the valley minimum relative to the X-point in unstrained silicon, εxy denotes the shear strain component, −1 M −1 ≈ m−1 t − m0 , and D = 14 eV is the shear strain deformation potential. The spin– orbit term τy ðkx σ x − ky σ y Þ with

|

Δso ¼ 2

X hX1 |pj |nihn|½rV × p |X 0 i j

En − EX

2

|

ð5Þ

couples states with the opposite spin projections from the opposite valleys. The matrices σ x and σ y are the spin Pauli matrices and τy is the y-Pauli matrix in the valley degree of freedom space. In the Hamiltonian (2.1) UðzÞ is the confinement potential, and the value Δso = 1.27 meV nm computed by the empirical pseudopotential method (see Figure 1) is close to the one reported by Li and Dery [35].

36  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

1.5

ΔE (meV)

1

0.5 EPM fit with Δso = 1.27 meV 0

0

0.2

0.4

0.6 k (nm

0.8

1

–1)

Fig. 1: Empirical pseudopotential calculations of the spin–orbit interaction strength by evaluating the gap opening at the X-point between X₁ and X₂′ for finite kx.

In the presence of strain and confinement, the fourfold degeneracy of the n-th unprimed subband is partly lifted by forming an n+ and n− subladders (the valley splitting); however, the degeneracy of the eigenstates with the opposite spin projections n ± *i and n ± +i within each subladder is preserved. The degenerate states are chosen to satisfy h* n ± | f | n ± +i ¼ 0

ð6Þ

f ¼ cosθ σ z þ sinθ ðcosφ σ x þ sinφ σ y Þ;

ð7Þ

with the operator f defined as

where θ is the polar and φ is the azimuth angle defining the orientation of the injected spin. In general, the expectation value of the operator f computed between the spin-up and spin-down states from different subladders is nonzero, when the effective magnetic field direction due to the spin–orbit interaction is different from the injected spin quantization axis. f ¼ h* n ± | f | n ± +i 6¼ 0

ð8Þ

The Hamiltonian (2.1) is suitable for describing unprimed subbands in (001) thin silicon films. If the confinement is strong, the primed subbands lying higher in energy because of a much smaller quantization mass mt are disregarded, and all the properties including low field transport and spin relaxation can be evaluated

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation

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37

with the help of the wave functions of the lowest unprimed subbands evaluated with Eqn. (1). In the case when the confinement potential is approximated with an infinite square well, the unprimed subband energy difference can be approximated as [41]: sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ! 2yn2 B 1−yn2 −η2 k0 t ð9Þ Δ En ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi sin 2 2 2 1−yn2 k0 t ð1−yn −η Þð1−yn Þ

j

j

yn , η, and B are defined as πn ; k0 t

ð10Þ

ml B ; ℏ2 k20

ð11Þ

yn ¼ η¼ and

sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  2 ℏ2 kx ky : B¼ Δ 2so ðk2x þ k2y Þ þ Dεxy − M

ð12Þ

Here t is the film thickness. To obtain Eqn. (9) we have generalized the theory [42] for valley splitting by including spin–orbit coupling. It is interesting to note that because the spin–orbit interaction provides coupling between the states with the opposite spin projections but from the opposite valleys, the spin–orbit coupling term in Eqn. (9) also leads to a subband splitting in the presence of a confining potential. However, because two possible ways of coupling the state with spin-up (down) from one valley to the spin-down (up) state in the opposite valley are allowed, the double-spin degeneracy of the eigenstates is not lifted. The spin degeneracy is preserved in a general case for arbitrary momentum, when shear strain is introduced. A linear combination of these two degenerate states with opposite spin projections allows creating the wave function with a spin projection up or down on any arbitrarily chosen axis. It is usually assumed that because the unprimed subbands are originating from the two equivalent [001] valleys, they are double degenerate [43]. However, this is true only in the parabolic band approximation when the two valleys are independent. Due to the presence of the off-diagonal terms, the Hamiltonian (2.1) couples the [001] valleys, resulting in the unprimed subband degeneracy lifting described by Eqn. (9). The degeneracy between the subbands is exactly recovered, when the oscillating term is zero. However, this degeneracy is insignificant, because it does not result in any peculiar behavior of the spin relaxation scattering matrix elements. In contrast, the minimum of the B term in Eqn. (9) reveals a very strong increase of the intersubband spin relaxation. Under these conditions the subband splitting is purely determined by the linear dependence

38  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

on the effective spin–orbit interaction. This linear dependence of the splitting is similar to the Zeeman splitting in a magnetic field. Thus, the spin–orbit-induced splitting can be interpreted as an effective magnetic field, while the pairs of states X1" ; X2# 0 and X1# ; X2" 0 it couples have similarities with the Zeeman spin-up and spin-down states split because of the effective field. Spin along the z-direction starts precessions in the in-plane effective field, resulting in a large mixing between the opposite spin states from the different valleys. This mixing results in large spin relaxation matrix elements defining hot spin relaxation spots. These hot spots should be contrasted against the hot spots in bulk silicon [35] appearing at the edge of the 3D Brillouin zone. The origin of the spin relaxation hot spots in thin films lies in the unprimed subband degeneracy in a confined electron system. Because the hot spots are determined by the minimum of Eqn. (12), they are located in the middle of the two-dimensional Brillouin zone in an unstrained film, thus contributing strongly to the spin relaxation. However, when shear strain is applied, the spin relaxation hot spots are pushed toward higher energies. Moving the hot spots above the Fermi energy outside the occupied states region will result in reduced spin relaxation and an increase of the spin lifetime with shear strain.

4 Analytical evaluation of the wave functions Because spin hotspots determine the strong dependence of the spin relaxation scattering matrix elements on the relative angle between the incoming and scattered waves, the assumption of the independence of the subband wave functions on the in-plane momentum frequently employed to estimate the momentum relaxation cannot be used to evaluate the spin lifetime. Indeed, because spin–orbit effects are linear in in-plane momentum, the calculation of the SR scattering matrix elements at the center of the 2D Brillouin zone usually done for mobility calculations would result in the complete loss of all the effects due to spin–orbit interaction. Therefore, to accurately compute the spin lifetime numerically, one needs to know the subband wave functions as a function of the in-plane wave vector. Numerical evaluation of the wave functions with subsequent integrations makes the task prohibitively expensive. To simplify the problem, we obtain the wave functions in a semianalytical manner. For this purpose we rotate the Hamiltonian (2.1) by means of the following unitary transformation. The four basic functions X1" ; X1# ; X2" 0 ; X2# 0 for the two [001] valleys pffiffiffiffiffiffiffiffiffi Δ so k2x þk2y with spin up, spin down are transformed by Eqns. (13–20) with tanðΘÞ ¼ . ℏ2 k x k y Dεxy −

M

The transformation effectively decouples the spins with opposite direction in different valleys.

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation

2



39

3

kx −iky 7 16 0 0 Ψ 1 ¼ 4ðX1" þ X2" Þ þ ðX1# þ X2# Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5 2 k2x þ k2y 2

ð13Þ

3

kx −iky 7 16 0 0 Ψ 2 ¼ 4ðX1" þ X2" Þ − ðX1# þ X2# Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5 2 k2 þ k2 x

ð14Þ

y

2

3

kx −iky 7 16 0 0 Ψ 3 ¼ 4ðX1" −X2" Þ þ ðX1# −X2# Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5 2 k2 þ k2 x

ð15Þ

y

2

3

kx −iky 7 16 0 0 Ψ 4 ¼ 4ðX1" −X2" Þ − ðX1# −X2# Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi5 2 k2 þ k2

ð16Þ

    Θ Θ Χ 1 ¼ Ψ 1 cos − i Ψ 3 sin 2 2

ð17Þ

    Θ Θ þ i Ψ 4 sin Χ 2 ¼ Ψ 2 cos 2 2

ð18Þ

    Θ Θ − i Ψ 1 sin Χ 3 ¼ Ψ 3 cos 2 2

ð19Þ

    Θ Θ þ i Ψ 2 sin Χ 4 ¼ Ψ 4 cos 2 2

ð20Þ

x

y

The Hamiltonian (2.1) can be cast into a form in which spins with opposite orientations in different valleys are independent. 
H1 H3 ð21Þ H¼ H3 H2 H1 , H2 , and H3 are written as: " H1 ¼ " H2 ¼

# 2 2 2 ℏ2 k2z ℏ ðkx þ ky Þ þ − δ þ UðzÞ I; 2ml 2mt # 2 2 2 ℏ2 k2z ℏ ðkx þ ky Þ þ þ δ þ UðzÞ I; 2ml 2mt

ð22Þ

ð23Þ

40  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr 2

3

ℏ2 k0 kz 6 m l H3 ¼ 6 4 0 with δ ¼

0

7 7 ℏ2 k0 kz 5 ml

ð24Þ

ffi rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi   Dεxy −

ℏ 2 kx ky 2 M

þ Δ 2SO ðk2x þ k2y Þ.

The wave functions for the Hamiltonian (22–24) can be found in a closed form [42]. This significantly simplifies the computation of the spin relaxation and momentum scattering matrix elements; relaxation and scattering rates; and, finally, the spin relaxation time and the electron mobility. Next we outline the procedure for evaluating the electron spin relaxation.

5 Spin relaxation suppression in stressed silicon films We are considering three mechanisms that contribute to the spin and momentum relaxation: SR and intra- and intervalley (for spin relaxation) scattering by acoustic phonons. The spin and momentum relaxation times are calculated by thermal averaging [35, 36, 44] as:

Z

1 ¼ τ

1 τðK1 Þ f ðεÞð1−f ðεÞÞdK1

Z

Z

f ðεÞdK1 Z

dK1 ¼

ð25Þ

;

2π 0

Z

1

|

0

|K1 | ∂εðK1 Þ ∂K1

|

ð26Þ

dφ dε:

The SR momentum (spin) relaxation rate is calculated in the following way: Z 2π 1 2ð4Þπ X 1 ℏ4 |K2 | 2 2 πΔ L ⋅ ¼ 2 2 i;j τSR ðK1 Þ ℏð2πÞ εij ðK2 −K1 Þ 4m2l | ∂εðK2 Þ | 0 ∂K2


 ⋅

dΨ iK1 σ dz



dΨ jK2 −σ dz

2

 −ðK2 −K1 Þ2 L2 dφ; exp 4 z¼ ± t 

2

ð27Þ

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation



41

ε is the electron energy, K1;2 are the in-plane wave vectors before and after scattering, εij is the dielectric permittivity, L is the autocorrelation length, Δ is the mean square value of the SR fluctuations, Ψ iK1 and ΨjK2 are the wave functions, and f ðεÞ is the Fermi function, and σ ¼ þ1 is the spin projection to the [001] axis. The momentum relaxation time is evaluated in the standard way [45]. The spin relaxation rate due to the transversal acoustic phonons is calculated as 1 4πkB T ¼ 2 τTA ðK1 Þ ℏρvTA

XZ

2π 0

|K2 |

Þ | ∂εðK ∂K | 2

2




∂εðK2 Þ

∂K2 1− ∂εðK Þ 1

∂K1

 Z Z  qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  f ðεðK2 ÞÞ 1 t t 0 exp − q2x þ q2y |z−z | ⋅ f ðεðK1 ÞÞ 2 0 0



 y 0 0

⋅ Ψ yK2 − σ ðzÞMΨ K1 σ ðzÞ Ψ K2 − σ ðz ÞMΨ K1 σ ðz Þ ⋅ " ⋅

ð28Þ

#

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 8q2 q2 −ðq2 þ q2 Þ2 dφ x y x y q2x þ q2y − jz−z ′ j dzdz′ ; q2x þ q2y 2π

where kB is the Boltzmann constant, T is the temperature, ρ ¼ 2329mkg2 is the silicon density, vTA ¼ 5300ms is the transversal phonons velocity, ðqx ; qy Þ ¼ K1 −K2 , and M is the matrix 4 × 4. Written in the basis for the spin relaxation rate the matrix M is 2 3 D 0 0 0 6 2 D7 6 7 6 0 0 0 7 6D 2 7 M¼6 : ð29Þ 0 7 0 0 6 7 6 2 7 4 5 D 0 0 0 2 Here D = 14 eV is the shear deformation potential: The intravalley spin relaxation rate due to the longitudinal acoustic phonons is calculated as XZ 2π |K |
∂εðK2 Þ f ðεðK2 ÞÞ  1 Z tZ t  qffiffiffiffiffiffiffiffiffiffiffiffiffiffi 0  1 4πkB T 2 ∂K2 1− ∂εðK exp − q2x þ q2y |z−z | ⋅ ¼ 2 ∂εðK2 Þ 1Þ τLA ðK1 Þ ℏρvLA 2 0 0 0 | ∂K | f ðεðK ÞÞ 1 ∂K1 2 h i h i ⋅ Ψ yK2 −σ ðzÞMΨ K1 σ ðzÞ  Ψ yK2 −σ ðz 0 ÞMΨ K1 σ ðz 0 Þ ⋅
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  4q2x q2y 0 0 dφ q2x þ q2y jz−z j þ 1 dzdz ⋅ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi3 2π q2x þ q2y

ð30Þ

Here, vLA = 8,700 m/s is the speed of the longitudinal phonons and the matrix M is defined with Eqn. (29).

The intervalley spin relaxation rate contains the Elliot and Yafet contributions [36], which are calculated in the following way:

42  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

1 4πkB T ¼ 2 τLA ðK1 Þ ℏρvLA 1 ⋅ 2

XZ

2π 0

|K2 |

Þ | ∂εðK ∂K | 2

2

"

∂εðK2 Þ ∂K2 f ðεðK2 ÞÞ 1− ∂εðK 1Þ ∂K1 f ðεðK1 ÞÞ

# ⋅


 Z t
dφ y y 0 0 Ψ K2 −σ ðzÞM Ψ K1 σ ðzÞ Ψ K2 −σ ðzÞM Ψ K1 σ ðzÞ dz : 2π 0

ð31Þ

The matrix M 0 is written as


MZZ M ¼ y Mso 0




MZZ

DZZ ¼ 0

 MSO : MZZ

ð32Þ

 0 : DZZ

ð33Þ

 0 Dso ðry −irx Þ : Mso ¼ Dso ð−ry −irx Þ 0


ð34Þ

ðrx ; ry Þ ¼ K1 þ K2 , DZZ = 12 eV, Dso = 15 meV/k₀, with k0 = 0.15 ⋅ 2π=a defined as the position of the valley minimum relative to the X-point in unstrained silicon [36]. A strong increase of the spin lifetime [46] is demonstrated in Figure 2 for a 2.5 nm thick film.

103

Relaxation time (ns)

OP LA TA

102

SR Total

101

100 0

0.5

1

1.5

εxy (%) Fig. 2: Spin relaxation time with its contributions mediated by optical phonons (OP), longitudinal acoustic (LA), and transversal acoustic (TA), as well as due to the scattering on surface roughness (SR). Film thickness is 2.5nm, room temperature.

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation



43

The spin lifetime is boosted by almost two orders of magnitude. The fact that the inplane momentum dependence of the subband wave functions must be preserved significantly increases the demands for computational resources and requires extensive code parallelization. For film thickness below 3 nm, the SR scattering mechanism dominates the spin relaxation for all electron concentration and shear strain values. For films thicker than 3 nm, acoustic phonon–mediated spin relaxation starts playing an important role as shown in Figure 3. Film thickness is 2.5 nm, room temperature.

Relaxation time (ns)

103

102

OP LA TA SR

101

Total 100

0

1

0.5

1.5

εxy (%)

Fig. 3: Spin relaxation time with its contributions in a 4 nm thick film.

Spin relaxation due to optical phonons is the weakest among the considered mechanisms. In contrast to the momentum relaxation defined by the intrasubband transitions, the main contribution to the spin relaxation comes from the intersubband scattering processes. This is due to the presence of the spin hot spots at which the spin-up and spin-down states from the unprimed subbands split by the spin–orbit interaction are strongly coupled. The position of the hot spots defined by εxy ¼

ℏ2 jkx ky j MD

ð35Þ

is pushed to higher momentum states away from the subband minimum as the value of the shear strain increases. As the spin relaxation hot spots move above the Fermi level

44  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

into unoccupied state region, the spin relaxation is strongly reduced, which results in a significant spin lifetime increase with shear strain applied. Interestingly, at high stress the value of the spin relaxation is comparable to that in bulk silicon. This makes siliconon-insulator structures very attractive for spin-driven applications, in particular, for spin interconnects.

6 Spin manipulation in silicon FETs at room temperature Utilizing spin properties of electrons for future microelectronic devices opens great opportunities to reduce device power consumption. As outlined earlier, the ferromagnetic source contact injects spin-polarized electrons to the semiconductor region [13]. At the drain contact only the electrons with spin aligned to the drain magnetization can easily leave the channel and contribute to the current. Thus, the total current through the device depends on the relative angle between the magnetization direction of the drain contact and the electron spin polarization at the end of the semiconductor channel. Current modulation is achieved by tuning the strength of the spin–orbit coupling in the semiconductor region. The spin–orbit coupling is taken in the Rashba form [47, 48], with the spin–orbit coupling strength depending on the effective electric field and thus the gate voltage [47]. The electric field–dependent spin–orbit coupling splits the degeneracy between the spin-up and spin-down states moving with the same velocity in the same direction, thus opening the way to manipulate the degree of spin precession in the channel. In the absence of the spin–orbit coupling and the external magnetic field, the electrons propagate with their spin orientation conserved. The strength of the spin–orbit coupling determines the minimum length of the semiconductor channel sufficient to change the orientation of the spin to the opposite. In silicon, the spin–orbit coupling is relatively weak [49–51]. Figure 4 shows the modulation of the channel resistance in [001] oriented channel as a function of the spin–orbit coupling strength β for a channel with the length of 8 μm. In order to facilitate the spin injection and detection, the tunnel barriers U between the channel and the source and drain of the dimensionless strength z = 2mf*U(2π/h)²kF−1, where mf* and kF are the effective mass and the Fermi vector in the ferromagnetic contacts, respectively. Figure 4 demonstrates that the modulation of the resistance in the channel is preserved at room temperatures and may reach about 60%, which is sufficient for applications.

Silicon-on-Insulator for Spintronic Applications: Spin Lifetime and Electric Spin Manipulation



45

T = 0K T = 50K T = 100K T = 300K

0.2

TMR

0.1

0

–0.1

–0.2

0

10

20 β (μeVnm)

30

Fig. 4: TMR dependence on the value of the Dresselhaus spin–orbit interaction for EF = 2.47 eV, δEc = 2.154 eV, P = 0.4, z = 3, t = 8 μm, V = 1 meV.

At the same time, this modulation is inferior to the maximum-reported tunneling magnetoresistence ratio of about 600% in magnetic tunnel junctions at room temperature. Due to the weak spin–orbit coupling, the channel length L should be at least L¼

h ; βmn

ð36Þ

where mn is an effective mass in the silicon channel. For typical values of the spin–orbit coupling β, this value is in several microns range. This length is much longer than 20 nm channel length in modern cutting-edge MOSFET transistors. To reduce the length of a channel in a SpinFET, a much more efficient way to manipulate spins by purely electrical means is required. The remaining option to build a reprogrammable MOSFET by using ferromagnetic source and drain is still of great interest. Indeed, although magnetic tunnel junctions possess much larger ratio of tunneling magnetoresistances for parallel and antiparallel layer magnetization orientation, these are still two-terminal devices and the realization and usefulness of MOSFETs with magnetic source and drain are pending to be explored from the points of view of both technology and applications.

46  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

7 Conclusion The spin–orbit interaction effects included into the effective low-energy k · p Hamiltonian allow the investigation of the valley splitting as well as momentum and spin relaxation mediated by the SR and phonon scattering in a thin-film SOI MOSFET in a wide range of parameters. To evaluate the wave function dependence on the inplane momentum and spin relaxation time, the k · p Hamiltonian was solved analytically. We have demonstrated that the valley splitting minimum due to the vanishing ℏ2 k k Dεxy − Mx y ¼ 0 leads to an extremely strong spin relaxation. This is because the splitting is solely determined by the spin–orbit field strongly coupling spin-up and spin-down states from different valleys. With shear strain increased, these hot spots are pushed to high energies outside the occupied states. This results in a sharp decrease of spin relaxation and thus in a giant, almost two orders of magnitude, increase of the spin lifetime. This is in contrast to the mobility that can be improved by a factor of two. As shear strain is now routinely used to boost mobility, it is a viable option to increase the spin lifetime in ultra-thin body silicon-on-insulator structures, making them promising for future spin interconnects. Acknowledgment: This work was supported by the European Research Council through the grant #247056 MOSILSPIN. The computational results are achieved on the Vienna Scientific Cluster (VSC).

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48  Viktor Sverdlov, Dmitri Osintsev, and Siegfried Selberherr

[30]

[31] [32]

[33]

[34] [35] [36] [37] [38] [39] [40] [41]

[42] [44]

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Amit Prakash and Hyunsang Hwang

Multilevel Cell Storage and Resistance Variability in Resistive Random Access Memory Abstract: Multilevel per cell (MLC) storage in resistive random access memory (ReRAM) is attractive in achieving high-density and low-cost memory and will be required in future. In this chapter, MLC storage and resistance variability and reliability of multilevel in ReRAM are discussed. Different MLC operation schemes with their physical mechanisms and a comprehensive analysis of resistance variability have been provided. Various factors that can induce variability and their effect on the resistance margin between the multiple resistance levels are assessed. The reliability characteristics and the impact on MLC storage have also been assessed. Keywords: Emerging memory, non-volatile storage, resistive random access memory (ReRAM), multilevel cell storage (MLC), variability, conductive filament, high density storage, memory margin, MLC reliability.

1

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Semiconductor memory, which is an electronic device used for data storage, becomes a key component in today’s electronic systems. The dominant memory technologies of the present time are Dynamic Random Access Memory (DRAM) and Flash. Both these memories store data as electronic charge and are known to suffer from further scaling issues [1, 2]. The DRAM, which is a volatile memory, offers extremely long endurance (~10¹⁴ program/erase cycles) and fast (λ

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Fig. 7: Energy band diagrams plotting electron potential energy versus distance along the conductive filament in the HRS. (a) Switching region with length lGAP = 6 nm filled with (SiH)₂ defects for device biased to 2.6 V. (b) Energy barrier of 0.83 eV to electron transport from Si–H–Si defects into (SiH)₂ defects and trap-assisted tunneling (TAT) to induce the SET transition at 3.4 V. Tunneling distance x and characteristic tunneling length λ are labeled in both plots to demonstrate the dependence of x on device bias. (c) Energy band diagram plotting electron potential energy versus distance along the conductive filament in the LRS. Switching region is filled with Si–H–Si, SiH + SiSi(5), and H₃O+ defects showing available TAT pathway at 1.8 V bias. The effective bandgaps of the Si–H–Si and SiH + SiSi(5) defects and the 2.5 eV separation between Si–H–Si and H₃O+ are labeled. (d) Energy barrier of 0.13 eV to electron hopping from Si–H–Si to SiH + SiSi(5), and F–N tunneling into H₃O+ defects to induce the RESET transition at 2.6 V. Increasing bias above 2.6 V allows electron injection into neighboring H₃O+ defects at 2.9 V and 3.3 V (dashed horizontal arrows), thus forming a conductance gap in the HRS.

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3 Conclusion In summary, we have elucidated device characteristics and defect-related resistive switching mechanisms in intrinsic unipolar SiOx-based ReRAM. This research investigates SiOx materials explicitly for use in next-generation nonvolatile memory applications and aims to advance memory device performance through novel device structures and better fabrication techniques.

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Yao-Feng Chang*, Burt Fowler, Ying-Chen Chen, Fei Zhou, Chih-Hung Pan, Kuan-Chang Chang, Tsung-Ming Tsai, Ting-Chang Chang, Simon M. Sze, and Jack C. Lee

A Synaptic Device Built in One Diode–One Resistor (1D–1R) Architecture with Intrinsic SiOx-Based Resistive Switching Memory Abstract: We realize a device with biological synaptic behaviors by integrating silicon oxide (SiOx) resistive switching memory with Si diodes to further minimize total synaptic power consumption due to sneak-path currents and demonstrate the capability for spike-induced synaptic behaviors, representing critical milestones for the use of SiO₂-based materials in future neuromorphic computing applications. Biological synaptic behaviors such as long-term potentiation, long-term depression, and spike-timing dependent plasticity are demonstrated systemically with comprehensive investigation of spike waveform analyses and represent a potential application for SiOx-based resistive switching materials. The resistive switching SET transition is modeled as hydrogen (proton) release from the (SiH)₂ defect to generate the hydrogenbridge defect, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms (SiH)₂. The experimental results suggest a simple, robust approach to realize programmable neuromorphic chips compatible with largescale complementary metal-oxide semiconductor manufacturing technology. Keywords: 1D–1R, resistive switching, synaptic device, silicon oxide.

1

Introduction

In recent years, resistive random access memory (ReRAM) has drawn much interest as a promising candidate for next-generation nonvolatile memory (NVM)

*Corresponding author: Yao-Feng Chang, Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX 78758, USA, E-mail: [email protected]. Ying-Chen Chen, Fei Zhou, and Jack C. Lee, Microelectronics Research Center, The University of Texas at Austin, Austin TX 78758, USA. Burt Fowler, PrivaTran, LLC, 1250 Capital of Texas Highway South, Bldg 3, Ste 400, Austin TX 78746, USA. Ting-Chang Chang, Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan. Chih-Hung Pan, Kuan-Chang Chang, and Tsung-Ming Tsai, Department of Materials and Optoelectronic Science, National Sun Yat-Sen University, Kaohsiung 804, Taiwan. Simon M. Sze, Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan.

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due to its potential scalability beyond 10 nm feature size using a crossbar structure, fast switching speed, low operating power, and good reliability [1–3]. Traditional charge-based NVM typically includes a charge “trapping layer” within a transistor configuration that requires a high thermal budget and large footprint (typically 6F², where F = minimum feature size) [4, 5]. Resistive switching (RS) memory operates by controlling device resistance with an external electrical manipulation [6–9], leading to better electrical performance, smaller design area (4F²), and excellent cycling endurance [10]. Based on the 2013 International Technology Roadmap for Semiconductors (ITRS), ReRAM is one of two recommended candidate technologies for emerging memory devices [11]. Also, resistive-based memories represent a new class of devices compatible with applications that go beyond traditional electronics configurations, for example, three-dimensional (3D) stacking, nanobatteries, neuroelectronics and Boolean logic operations [12–17]. Neuroelectronics and synaptic electronics are interesting applications for ReRAM that aim to build artificial synaptic devices that emulate the computations performed by biological synapses [15, 18–22]. These emerging fields of research have potentially better efficiency in solving complex problems and outperform real-time processing of unstructured data than conventional von Neumann computational systems [23]. There have been many studies of binary metal oxide-based and perovskite oxide-based resistance switching characteristics for synapse-like electronic device development [24, 25], which can have operating instability issues due to difficulty in controlling stoichiometric compositions [26, 27]. Therefore, a simple process that is compatible with conventional complementary metal-oxide semiconductor (CMOS) fabrication allows multilayer compositional engineering and provides good electrical stability and high yield, which are critical requirements for neuroelectronics realization [28]. Silicon oxide (SiOx) has long been used as gate dielectrics for metal-oxide-semiconductor field-effect transistors. In addition to excellent insulating properties, resistive switching properties have been observed in SiOx materials as early as 1962 by Hickmott and 1967 by J. G. Simmons and R. R. Verderber, with additional modeling being done by G. Dearnaley in the 1970s [29–31]. They observed that a simple metal-insulator-metal structure (e.g., Au/SiOx/Al, MIM) can form an active memory device based on its repeatable negative resistance phenomenon. Recently, Yao et al. have reported SiOx-based resistive switching behaviors in vacuum, indicating that this traditionally passive material can be converted to an active memory element and controlled by external electrical activation [32–37]. The amount of recent reports also describe and indicate using SiO₂ as the active switching medium in resistive switching memory devices [38–41]. We have further demonstrated a Si diode (1D) with low reverse-bias current integrated with a SiOx-based memory element (1R) using nanosphere lithography and deep Si etching to pattern a P++/N+/N++ epitaxial Si wafer [42]. The above achievements for intrinsic SiOx-based ReRAM indicate: (1) high device yield, forming-free operation, reduced operating voltage, excellent scalability (to dimensions < 40 nm in 1D–1R architectures without sacrificing the device performance, such as the retention of multilevel states

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and endurance reliability) and good device stability; (2) pulsed programming in the 50 ns-regime and low reverse current with large rectification ratio to meet low-energy consumption criteria (> 10⁶ for high-conductance states and negative-bias current) for integrated 1D–1R nanopillar architectures; and (3) wide programming resistance dynamic range (potentially up to 10⁸), multilevel states, and excellent reliability. However, the resistive switching mechanisms in SiOx are not well understood, and use as an electronic synaptic device has not previously been demonstrated. In this work, SiOx-based resistive switching memory elements (1R) are integrated with Si diodes (1D) using conventional CMOS processing to demonstrate a 1D–1R device with synaptic behaviors. The Si diode provides low reverse-bias current and high-power efficiency for future neuromorphic computing array architectures. Unlike other binary or complex metal oxide materials [43–46], SiOx has been used in CMOS manufacturing for over 50 years due to its excellent electrical isolation properties, low-cost, high chemical stability, compatibility with mainstream integrated circuit materials, high-throughput processing and large-area production using chemical vapor deposition (CVD). A 1D–1R architecture fabricated at the wafer-scale using conventional CMOS processing can therefore be well-controlled in thickness, size, and electrical characteristics by precisely controlling the doping levels of the diode layers and the temperature and flow-rate of the oxide CVD process [47]. Synaptic device performance is characterized in a prototype 1D–1R array configuration. Robust biological synaptic behaviors such as long-term potentiation (LTP), long-term depression (LTD), and spike-timing dependent plasticity (STDP) are demonstrated with excellent uniformity, low operational variability, and good suppression of static power consumption [43–46]. A bio-inspired proton exchange resistive switching model is used to help characterize this novel application for SiOx materials. The SET transition in the resistive switching memory is modeled as hydrogen (proton) release from the (SiH)₂ defect to generate a conductive hydrogen bridge, and the RESET transition is modeled as an electrochemical reaction (proton capture) that re-forms nonconductive (SiH)₂. The synaptic behaviors exhibited by the 1D–1R device demonstrates good potential for using a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology.

2 Experiment Devices were fabricated at XFAB Inc. in Lubbock, TX. Secondary electron microscopy (SEM) images show a top-down view of a 1D–1R test structure (Figure 1(a)), a tilted (45o) view of the 1R device (Figure 1(b)) and a cross-section image of the 1R device showing layer information (Figure 1(c)). The 1R device was fabricated by implanting the Si substrate to form an n-type lower electrode. The active SiOx memory layer was

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then deposited to a thickness of 40 nm using plasma-enhanced chemical vapor deposition (PECVD) with proper thickness-dependence resistive switching optimization. An n-type polysilicon layer was deposited onto the SiOx layer to form the top electrode. An opening in the polysilicon layer was made after all thermal oxidation and implant anneal steps were complete (Figure 1(b)). A first dielectric layer was then deposited over the polysilicon top electrode. Tungsten plugs were used to make electrical contact to the n-type Si lower electrode and the polysilicon top electrode. After all the back-end dielectrics and a passivation layer were deposited, the back-end dielectric layers were removed using reactive ion etch (RIE) to the Si substrate. This RIE step cleared out the SiOx layer inside the hole, and created a SiOx sidewall where the memory device is formed (Figure 1(c)). Polymer residue that remained after the post-RIE cleaning steps was removed by a 30-second buffered oxide etch (BOE). The pn diode used in the 1D–1R test structures was formed by an implanted p-well inside a deep n-well, and is a standard device available from XFAB with 40 V reverse-bias breakdown voltage, 1 nA reverse-bias leakage current, and 0.5 V forward voltage. The dimension for 1R device is 22 μm and for 1D device is 2020 μm. A Lake Shore Cryotronics vacuum probe chamber (< 1 mTorr) and Agilent B1500A device analyzer were used to electroform devices and measure the DC/AC I-V response. The SET process programs the device to a conductive, low-resistance state (LRS). The RESET process programs each device to a low-conductance, high-resistance state (HRS). A Kratos Axis Ultra HSA X-ray Photoelectron Spectrometer (XPS) equipped with a monochromatized aluminum x-ray source was used to analyze several SiOx materials deposited in our laboratory using different methods. Calibration of the binding energy scale was set by fixing the C-(C,H) peak at 284.4 eV. Figure 1(d) shows XPS analysis results for the O-1s and Si-2p binding energies in thermal oxide grown by low-pressure chemical vapor deposition (LPCVD) and PECVD oxide. The existence of stoichiometric SiO₂ can be observed in thermal oxide (binding energy Si: 103.2 eV; O: 532.5 eV) with essentially no sub-oxide bonding being detected. In contrast, the PECVD oxide has nonstoichiometric SiOx (x is about 0.93 based on the peak position and orbital valence) composition in the switching layer, as indicated by the peak binding energies in the XPS spectra (Si: 530.5 eV; O: 101.9 eV and 100.9 eV) [48–50], which may promote lowenergy defect generation during the electroforming process.

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3

Results and discussions

Figure 2(a–d) shows I-V characteristics for DC voltage sweeps applied to the SiOxbased 1D–1R devices fabricated by the conventional CMOS process. Voltage was applied to the 1D top electrode (p-type Si) with bottom 1R electrode (n-type Si) at ground. All testing was done in vacuum. To establish reversible resistive switching in each SiOx-based 1R ReRAM device, a forward/backward voltage sweep (Figure 2(a)) was used to electroform a conductive filament, where current is observed to increase dramatically at 22.5 +/– 2.9 V during the forward voltage sweep. Electroforming is completed during the backward voltage sweep from the maximum sweeping voltage to 0 V, resulting in a LRS. After electroformation, resistive switching performance of 1D–1R is stabilized by cycling the device multiple times using voltage sweeps (Figure 2(b)). The SET process is a 10 V forward/backward sweep without any compliance current limit (CCL) to program the device to the LRS. The RESET process is done by sweeping the voltage to 17 V, where current decreases as the voltage is swept from about 10 V to 17 V; and the device is programmed into a HRS. The HRS/ LRS resistance ratio is at least ~10³ at 1 V bias, which satisfies sensing requirements

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[3, 51]. For diode characteristics, the forward current can reach 100 mA at 2 V, which indicates a forward current level high enough to support the RESET process. The reverse current is below 110–12 A at –5 V. Compared with Schottky diodes, the advantages of Si-based PN diodes include low reverse-current, high reverse-bias breakdown voltage, and fewer stability issues. The quality of the Si-based PN diode can dramatically affect diode reverse or forward current characteristics, as well as power consumption (describe below). Also, the chosen Si-based PN diode configuration has high reverse breakdown voltage (> 40 V), which is important for SiOx-based ReRAM operating in an array. Figures 2(c) and 2(d) demonstrate the gradual change of resistive states by modulating the voltage sweep range during the SET and RESET process, respectively. Specifically, SET and RESET voltages were changed from 3.5 V to 9.5 V in 0.5 V increments and from 11 V to 18 V in 0.5 V decrements, respectively, thus potentially enabling multilevel programming in a single memory cell. It may be noted that the electroforming voltages measured here (~28 V) are somewhat higher than those measured in previous work on metal-oxide-semiconductor device architectures or nanopillar type 1D–1R architectures [30, 32], which may be due to fewer electrically active defects being near the SiOx sidewall as a result of the fabrication process. For example, several high temperature steps (> 650 °C) were done after PECVD SiO₂ deposition, namely: polysilicon deposition, thermal oxidation, and implant anneals, which might densify the SiO₂ layer, reduce the as-deposited defect levels, increase the soft breakdown threshold, and thus increase the filament formation energy during the subsequent electroforming process. Interestingly, the RESET voltage (the voltage at which LRS current begins to decrease) is greater than or equal to the SET voltage (where HRS current increases sharply), which is possibly a unique characteristic in SiOx-based ReRAM as compared to other materials systems [25, 52]. The difference between RESET and SET voltages can potentially be controlled by optimizing the series resistance in the circuit and choice of electrode materials [53]. The switching voltage is independent of device scalability and SiOx thickness reduction. Figure 2(e) shows multilevel retention performance of SiOx-based 1D–1R devices obtained by controlling the maximum SET voltage from 3 V to 9 V. The readout current of LRS and HRS is measured at 1 V every 60 seconds after each programming operation. The retention reliability test demonstrates multilevel operation by using different SET voltages, and no degradation is observed for more than 10³ seconds, thus confirming the stable, nonvolatile nature of the SiOx-based 1D–1R devices. In recent studies, a possible proton-exchange model consistent with the observed resistive switching I-V response has been proposed, as shown in Figure 2(f) [53–55]. Several studies have used transmission electron microscopy (TEM) to document the presence of Si nanocrystals within the CF [32, 35, 56], but it is not yet clear whether resistive switching (RS) is the result of an overall increase in nanocrystal size or whether switching occurs in “GAP” regions in between nanocrystals. Most models of ReRAM switching involve the drift or diffusion of O2– ions (or oxygen

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vacancy defects) [28], but these models cannot explain the I-V response (such as backward scan effect, as shown in Figure 2(a)) or the ambient effects on resistive switching observed in the SiOx device [57, 58]. The models used to describe the possible SiOx-based RS mechanisms differ from most conventional models by considering that the defects responsible for RS may remain localized within the switching region so that resistive switching occurs when a collection of defects are driven between conductive and nonconductive forms [58]. Based on the reported electrical and structural properties of known SiOx defects [53], it has been further understood how the possible proton exchange reactions can dramatically alter the conductivity of specific defects, leading to a model description where the LRS has a large concentration of conductive defects within the switching region, and, conversely, when the device is programmed to the HRS, most of the defects are converted to their nonconductive form. The electrically conductive hydrogen bridge (Si-H-Si) is viewed as the most likely defect responsible for the LRS due to its shallow defect level below the conduction band for electron transport, and the trigger-voltage from HRS to LRS is close to the activation energy of defect transformation ([SiH]₂ to Si-H-Si) [53, 54]. Electrochemical reactions that form the nonconductive (SiH)₂ defect are discussed as potential mechanisms that enable localized switching without incorporating ion diffusion or drift mechanisms into the model. The transitions between HRS and LRS are modeled as being initiated by hydrogen desorption from (SiH)₂ to form Si-H-Si, and as electron injection into a fixed positive-charge defect that induces proton release and an electrochemical reaction with Si-H-Si to re-form (SiH)₂, respectively. The RS model not only provides insights into multilevel operational characteristics but also implies a possible biomimetic chemical reaction similar to reactive oxygen species (ROS–like) production for future device characterizations [59–61].

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Figures 3(a–h) show contour plots of the current-change ratio achieved by modulating the AC pulse height and pulse width applied to 1D–1R devices for both SET and RESET switching events, leading to optimized waveform designs for a biological synaptic device. The current-change ratio is defined as log₁₀ (IFINAL/IINITIAL), where IINITIAL and IFINAL are the currents measured at 1 V before and after applying the programing waveform, respectively. The SET switching events (S) increase current through the device, leading to positive current change ratios, whereas RESET switching events (R) decrease device current and lead to negative current change ratios. The pulse mappings are generated using the Agilent B1500A device analyzer in a threestep process: (1) Initial states are programmed using a fixed DC voltage before the pulse waveform is applied (see Figure 4 for the detailed state mapping procedure); (2) The pulse waveform is applied; and (3) Device state is read by measuring the current at 1 V before and after each pulsed switching event. One can observe by inspecting the contour lines in Figure 3 that when larger pulse heights (higher voltages) are applied to the device, shorter pulse widths are needed to achieve a similar currentchange ratio. In general, we find that a single 1R device operates at higher speed and requires lower programming voltages as compared to a 1D–1R device [62]. The higher operating voltages and lower operating speed of the integrated 1D–1R device may result from higher parasitic resistance in the Si electrodes, their contacts and the diode, as well as higher parasitic capacitance in the diode, all of which can act to degrade the pulse mapping results shown in Figures 3(a) and 3(b). It should be noted that current sneak-path issues in arrays of 1R devices would cause misread problems and substantially increase standby power consumption. The 1D–1R devices are used to suppress sneak-path currents, and perform much better than 1R devices in an array architecture. From Figures 3(a) and 3(b), it can be calculated that the switching energies to achieve at least a one-order-of-magnitude change in resistance in the 1D–1R architecture are about 0.01 pJ for SET and 1.54 nJ for RESET operations. However, due to the suppression of sneak-path current, the standby power during a 1 V read operation can be dramatically reduced in 1D–1R devices (1 pW) as compared to 1R devices (1 μW). Minimizing the total power consumption by sneak-path issue is as crucial as reducing the synaptic dissipation. Most importantly, the pulse mapping results not only demonstrate the potential for multilevel programming by properly designing the pulse waveforms for SET and RESET operations, but also demonstrate the potential to realize biological synaptic behaviors. Figures 3(c)–(h) demonstrate the optimization waveform

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design for biological synaptic behaviors in 1D–1R SiOx-based resistive switching memories. The long-term potentiation (LTP)/long-term depression (LTD) are a longlasting enhancement/reduction in signal transmission between two neurons, which can be realized by designing the SET and RESET pulse waveform to use either identical (fixed pulse width and pulse height, as shown in Figures 3(c)–(f)) or nonidentical (variable pulse width or pulse height, as shown in Figures 3(g) and 3(h)) pulsing methods. Both methods can be used to demonstrate a SiOx-based synaptic device. It may be noted that when the dynamic range was evaluated in detail and the tradeoffs between high dynamic range and gradual multilevel programming performance (Figures 3(e)–(h)) were considered, it was found that nonidentical pulse waveform methods may have certain advantages. (Dynamic range is defined as the maximum achievable resistance of the HRS divided by the minimum resistance of the LRS.) Although nonidentical pulsing might require a more complex neuromorphic circuit, our results show that this approach enables more efficient programming to target states while maintaining a larger dynamic range (Figures 3(g)–(h)). The use of nonidentical pulse heights ranging from 4 V to 10 V in 0.3 V increments (for LTP) and ranging from 11 V to 17 V in 0.3 V decrements (for LTD) allow the dynamic range to be mapped for pulse widths ranging from 100 ns to 1 ms, thereby realizing biological synapse behaviors in the SiOx-based 1D–1R architecture (Figures 4(g)–(h)). The switching energy is defined as I  V  δt, where δt is the pulse width. For δt = 100 ns, the smallest switching energies are ~6 fJ and ~130 pJ for LTP and LTD, respectively. The larger energy for LTD is mainly due to the lower resistance of the LRS (~93 kΩ) compared to the HRS (~ 260 MΩ), which results in higher current (118.28 μA) for the RESET process than for the SET process (15.38 nA). In order to minimize synaptic energy consumption, all three components–programming current (~nA level switching), pulse amplitude (< 1 V), and programming time (< 10 ns)–need to be minimized. In SiOx-based ReRAM and other material systems, an exponential voltage–time relationship is commonly observed [63, 64]. A small increase in programming voltage will decrease programming time exponentially. Hence, low programming energy is obtained by minimizing the programming time (traded off by increasing the pulse amplitude slightly) for ReRAM. Further decrease in synaptic energy consumption in switching process to fJ levels will be challenging but important to build very largescale systems [65]. Such flexible artificial control built with synaptic devices could provide a suitable platform for a broad range of computing applications, as shown in Figure 5. Some of the advantages that SiOx-based synaptic devices provide over other resistive switching materials include a higher dynamic range (~10⁴) [51] and the potential to achieve as many as 60 multilevel states in both LTP and LTD by changing the increment/decrement of the voltage step, as shown in Figure 5 (a). These advantages may arise as the result of there being a large number of defects within the switching region of the memory device. Switching is modeled as a change in conductivity of a group of defects within the switching region. In this framework, defects are not created or

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destroyed, but are simply driven between conductive and nonconductive forms by proton exchange reactions that are known to occur in SiOx materials (Figure 2(f)) [54, 66–104]. The SET and RESET switching transitions can be described in more detail with the aid of the electron energy band diagrams shown in Figure 5(b), which were constructed using the thermodynamic and switching charge-state energy levels reported by Peter Blochl in 2000 [104]. The ideal energy band diagrams in Figure 5(b) represent only a single electron pathway through the memory device, whereas in reality there are likely many such percolation pathways in parallel. The SET transition is modeled as being the result of trap-assisted electron tunneling through (SiH)₂ defects that stimulates H desorption and reaction of H+ with absorbed water (SiOH)₂ to form conductive Si-H-Si and H₃O+ (Figure 2(f)). Trap-assisted tunneling can only occur when the bias across the switching region is ≥2.6 V, which is the effective band gap of the (SiH)₂ defect and compares well with the observed minimum SET voltage of ~2.5 V in the I-V response [53, 54]. The RESET transition is modeled as being the result of Fowler-Nordheim electron tunneling into the H₃O+ defect to stimulate proton release and electrochemical reactions that re-form (SiH)₂ and (SiOH)₂ (Figure 2(f)). More detailed explanations of the defect energy levels and effective bandgaps are provided in Table 1. The band diagrams shown in Figure 5(b) are found to be consistent with measured electron energy barriers [54] and electroluminescence results reported for similar devices [56]. Table : Defect positive (+), neutral () and negative (–) switching charge-states, unoccupied switching charge-state energy levels that form an effective conduction band-edge (EC), thermodynamic energy levels (ETH), occupied switching charge-state energy levels that form an effective valence band-edge (EV) and effective bandgap energies (ΔEG) referenced to the Si midgap energy in units of eV [104]. Defect

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for demonstration of spike-timing-dependent plasticity (STDP). By design of preneuron and post-neuron spikes in neuromorphic circuits, the strength of the conductance change can be modulated based on the delta spike timing (Δt) between the two neurons (Figures 5(c)–(d)). Figures 5(e)–(f) demonstrates a total of 10 different states of STDP biological behavior for depression and potentiation with n = 2, 4, 6, 8, 10 and as a function of spike width modulation, ranging from 100 ns to 1 ms. For example, the depression of conductance change strength can be achieved by using multistep spike heights from –4 V to 0 V in the pre-neuron state and a single spike height fixed at 13 V in the post-neuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs, as shown in Figures 5(e)–(f). When the time delay difference is –10  (n–1) μs, where n is an even number, the total spike waveform (post-neuron spike minus pre-neuron spike) applied to the synapse gap junction region can adjust the conductance ratio between two neurons over the range from 10–3 to 0.1 in the depression direction (RESET process) as compared with the initial LRS conductance (Figure 5(f)). Similarly, the potentiation of conductance change strength can be achieved by using multistep spike heights from 4 V to 8 V in the pre-neuron state and a single spike height also fixed at 13 V in the post-neuron state, with both neurons having a fixed pulse width of 10 μs and a firing period of 20 μs. When the time delay difference is 10  (n–1) μs, where n is an even number, the total spike waveform (post-neuron spike minus pre-neuron spike) applied to the synapse gap junction region can in this case adjust the conductance ratio between neurons over the range from 10³ to 0.01 in the potentiation direction (SET process) as compared with the initial HRS conductance (Figure 5(e)). It may be noted that the 1D–1R architecture not only avoids sneak-path issues and lowers standby power consumption, but also helps to realize STDP behaviors. Without the 1D rectification characteristics in reverse-bias polarity, the above spiking forms cannot be implemented due to the unipolar nature of the 1R device, specifically in the potentiation behaviors under negative bias. In the 1R case, an applied voltage above the RESET threshold voltage (for example, –9 V) can trigger the RESET process and induce depression behaviors instead of potentiation behaviors. Also, for depression behaviors, when the time delay difference is smaller than the spiking width, the remaining 4 V spike height in this case would not fire the synapse towards a LRS in the depression direction (see Figure 3(h)). Therefore, by carefully designing the firing pulses between neurons in the neuromorphic circuit, a biological synapse behavior can be demonstrated with 1D–1R SiOx-based resistive switching memories.

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Figure 6 shows robust electrical reliability and low variation in a 1D–1R-array structure that can potentially be used in future neuromorphic computing applications. Figure 6(a) shows a portion of a test chip containing a 1616 bit cell array. Each bit cell is comprised of a Si PN diode isolation element and a SiO₂-based resistive memory element. Electroforming yield of the 256 bit cells in the array was 98%. Of these yielding devices, 100% passed a quick, 10-cycle switching performance test without failure. Figure 6(b) shows the average and  3-sigma variation of resistive switching behaviors in the 16  16 bit cell array cycle using a 10 V double-sweep for SET and 20 V single-sweep for RESET. In this case, the 3-sigma LRS/HRS current ratio at 1 V read bias was at least 6  10³. A gradual change in the SET transition is observed over the voltage range from 3.5 V to 6 V, thus allowing programming of the multilevel states that are required for a robust neuromorphic circuit design, and which are accompanied by excellent sub-μs transitions with at least 10 resistance ratio after 10⁵ cycles (Figure 6(c)). A 2 2 array of integrated 1D–1R bit cells with unipolar programming strategy shows excellent write/read disturbance immunity after 10⁶ pulses for unselected devices and a clear programming window > 100 (Figure 6(d)). In addition to 1D–1R device arrays, the hybrid CMOS/synaptic device architecture shown in Figure 6(e) has been successfully demonstrated as shown in Figure 6(f) by the I-V resistive switching plots. The 1D–1R architecture with SiOx-based resistance switching devices and the structure of artificial neural networks map naturally onto hybrid CMOS/synapse circuits that can be designed on a single chip (Figure 7) to provide predictable results with an ultimate scaling potential of CMOS technology to the sub-10-nm level, which could possibly challenge the complexity and connectivity of the human brain.

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Summary

In summary, we have demonstrated potentiation, depression, and spike timing dependent plasticity in a synaptic device built using a SiOx-based 1D–1R architecture. Proton-induced resistive switching behaviors in the SiOx memory element were discussed, where the SET threshold is modeled as proton desorption from the (SiH)₂ defect to generate the conductive hydrogen bridge, Si-H-Si, and the RESET transition is modeled as proton release and capture to re-form nonconductive (SiH)₂. The electrical results demonstrate that the technology has good potential for providing a simple and robust approach for large-scale integration of programmable neuromorphic chips using CMOS technology, and represent a critical milestone regarding the potential use of SiO₂-based resistive memory as a synaptic device in future synthetic biological computing applications.

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Tzung-Je Lee*, Member, IEEE, and Yen-Ting Chen

On-chip Wide Range Bidirectional Current Sensor for Li-ion Battery Management System Abstract: An on-chip wide range bidirectional current sensor for monitoring Li-ion battery model 18650 is proposed in this paper. In order to detect the bidirectional current, two feedback sensing loops are employed. The feedback sensing loops generate differential sensed current signals. The output summation driver is included to convert the differential current signals to a single-ended output voltage signal and improve the driving ability. The proposed design is implemented using a typical 0.25 μm 1P3M 60V BCD process. The core area is 0.2943 mm × 0.5640 mm. Based on the post layout simulation results, the sensing current is from –1.0 A to +1.0 A. The transimpedance is simulated to be 1.407 V/A. The inaccuracy error is from −0.2010% to 0.1030%. The measurement results reveal that the linear error is −0.390% to 0.215% given a sensing current from −0.8 A to +0.8 A. Keywords: on-chip, bidirectional, current sensor, Li-ion battery.

I Introduction Recently, because it possesses the high energy density without any memory effect, as shown in Table 1, Li-ion battery has become a popular energy storage element in various applications, e.g., the electrical vehicle, the portable consumer electric products, the solar photovolatic system, and the energy backup system in smart building [1]. For using the Li-ion battery efficiently and safely, it requires a BMS (battery management system) to monitor the voltage, current and temperature of the batteries [2]. Besides, it requires the over voltage, over current, and over temperature protection for the Li-ion batteries used in the SOA (Safe Operation Area) [3, 4]. Moreover, the SOC (State-of-charge) and SOH (State-of-health) can be estimated to indicate the state of batteries, thus, the users can know when to recharge their batteries and when to replace the batteries [5]. Coulomb integration is a popular method to estimate the SOC and SOH [5]. It requires a bidirectional current sensor to detect the current flowed in or out the batteries, as shown in Fig. 1. Moreover, the proper charging and discharging currents are 0.5 C (= 1.1 A) and 0.2 C (= 0.44 A), respectively,

*Corresponding author: Tzung-Je Lee, Department of Computer Science and Information Engineering, Cheng Shiu University, Kaohsiung 83347, Taiwan, E-mail: [email protected]. Yen-Ting Chen, Department of Computer Science and Information Engineering, Cheng Shiu University, Kaohsiung 83347, Taiwan.

114  Tzung-Je Lee and Yen-Ting Chen

for the Li-ion batteries model ICR18650NH, as shown in Table 2 [6]. Thus, the wide range bidirectional current sensor is required. Table : Comparison of the Li-ion battery to other rechargeable battery. Characteristic Nominal voltage (V) Energy density (Wh/Kg) Energy density (Wh/L) Self-discharge/month (Ah) Memory effect

Li-ion

Lead-acid

NiCd

NiMH

. − − % No

. − − % Yes

. − − % Yes

. − − % Yes

Table : Specifications of the Li-ion battery. Cell type

ICRNH . . . . .C (=. A) C (=. A) .C(=. A) Charge:  to + °C Discharge: – to + °C

Typical capacity (Ah) Normal voltage (V) Min. Discharging voltage (V) Max. Charging voltage (V) Standard discharging current (A) Fast discharging current (A) Standard charging current (A) Temperature range (°C)

Load

Power source

Power management controller SOC/SOH estimation

Bidirectional DC/DC converter

V1 Rsen

Ibat

VOUT V2

Li-ion battery cell

Bidirectional current sensor

Fig. 1: Block diagram of Li-ion battery management system (BMS).

On-chip Wide Range Bidirectional Current Sensor



115

Hall effect sensor is an easy method to sense the current [3]. As shown in Fig. 2 (a), the battery current, Ibat1, is sensed by the voltage type Hall effect sensor and then be transferred into the voltage signal, Vout-. The voltage, Vout-, is then amplified by the inverting amplifier, which is composed of an OPA and two resistors, R₃₁ and R₃₂. The diodes, D₃₁ and D₃₂, are used to avoid the leakage current to the ground. The final output voltage, Vout1, is then obtained. In this prior work, the Hall effect sensor occupies the system size dramatically. Besides, it uses many discrete OPAs and resistors such that the system area is increased. MOS current mirrors are used in the on-chip design to reduce the system area, as shown in Fig. 2 (b) [7] and Fig. 2 (c) [8]. In Fig. 2 (b), the large battery current, Ibat2, flows through Mp and then outputs to the loads with the current, Ibat23. By setting the MOS currents, IM1 ~ IM5, as a very small quantity, the output current, Ibat23, would be approximately equating to Ibat2, as shown in Eqn. (1) and (2). IM1 ¼ IM2 ¼ IM3 ¼ IM4 ¼ IM5 ¼ Ibias ≪Ibats ≪Ibat2

ð1Þ

Ibat2 ¼ Ibat23 þ IM3 ≈Ibat23

ð2Þ

In order to sustain the large current, the feature size of Mp is very large. By choosing the feature size ratio of Mp and Mps carefully, a small replica current, Ibats, is generated by Mps, as shown in Eqn. (3). Ibats ¼ Ibat2 ⋅

ðW=LÞMps ðW=LÞMp

ð3Þ

Similarly, if the MOS currents, IM2 and IM4, are very smaller than Ibats, as shown in Eqn. (1), the current, IS, is approximately equaling to Ibats. Ibats ¼ IS þ IM4 ≈IS

ð4Þ

Moreover, the output voltage is the voltage drop across the resistor, RS, by the current, IS. Vsen2 ¼ IS ⋅ RS

ð5Þ

By combining the Eqn. (3) ~ (5), the output voltage is derived by Eqn. (6). Vsen2 ¼ Ibat2 ⋅ RS ⋅

ðW=LÞMps ðW=LÞMp

ð6Þ

It shows that the output voltage, Vsen2, is linearly related to the battery current, Ibat2. However, there are many ideal assumptions required for the current values, as shown in Eqn. (1), (2) and (3). Besides, the drain voltages of M3 and M4 are not identical, which results in the current mismatch in the current sensor. Those nonideal factors increase the linearity error for the current sensing. Thus, it is difficult to achieve the high accuracy.

116  Tzung-Je Lee and Yen-Ting Chen

In Fig. 2 (c), Rsen3 is used to sense the battery current. Similarly, it is assumed that the current mirrors in Fig. 2 (c) are ideally identical. Thus, the gate voltages, the drain voltages and the source voltages of HP1 ~ HP3 are identical, respectively. Moreover, the terminal voltages of HN1 ~ HN3 are identical, respectively. Thus, it results in that Va = Vb such that the battery current is sensed by the resistor Rsen3. By setting the resistance equaling to K × Rsen3, the current flowing through the internal resistor are Ibat3/K. Because of the current mirror, the MOS currents are identical, as shown in Eqn. (7). 1 Ibat3 ð7Þ IHP1 ¼ IHP2 ¼ IHP3 ¼ IHP4 ¼ ⋅ K 2 The output voltage, Vout3, is the voltage drop across N1 resulted from the current IHP4. Thus, the output Vout3 is expressed by Vout3 ¼

1 Ibat3 ⋅ RN1 ⋅ 2 K

ð8Þ

Notably, the current sensor in Fig. 2 (c) is implemented using 60 V high voltage devices such that it is capable for the high voltage applications. Similarly, Eqn. (8) is a linear equation based on many ideal assumptions. Thus, the linearity error is quite large because of the mismatches of the MOS transistors. It is difficult to achieve the high accuracy. In Fig. 2 (d), the on-chip temperature compensation and dynamic error-correction techniques are employed to improve the precision of the on-chip current sensor [9]. Rshunt is used to sense the battery current, Ibat4. The sensed voltage, Vshunt, is sampled by the ADC (Analog-to-digital converter) with temperature compensation. The digitized signal is then corrected by the chopping technique. Thus, the output digital signal, Dout, is linear related to the battery current, Ibat4, in the serious environment due to the process variation and temperature variation. However, it is complicated to implement. Fig. 2 (e) reveals the on-chip OPA in a feedback loop [4], [10]. In Fig. 2 (e), the battery current, Ibat5, is sensed by the resistor, Rsen5. Because of the virtual short and virtual open of the operational amplifier, the voltages, V₅₁, V₅₂, and V₅₃ are identical. Thus, the current through Rp is zero. Because the voltage drops across Rsen5 and RA are the same, the current through RA, IRA, is linearly related to the battery current, Ibat5, which is expressed by Eqn. (9). IRA ¼

Rsen5 ⋅ Ibat5 RA

ð9Þ

The output voltage, Vout5, is the voltage drop of RB caused by the current, IRA. Thus, Vout5 is derived by Eqn. (10).

On-chip Wide Range Bidirectional Current Sensor

Vout5 ¼ RB ⋅

Rsen5 ⋅ Ibat5 RA



117

ð10Þ

Eqn. (10) is a linear equation based on only 1 operational amplifier, 4 resistors, and 1 diode. The diode is used to avoid the inverse leakage current. It is easy to implement the large current sensing. However, only one direction current is sensed. Fig. 2 (f) reveals the bidirectional current sensor combining two feedback loops with two output resistors. It is used for the bidirectional current sensing and the differential output signals are obtained [11]. Similar to the Eqn. (10), the output voltages, Vout61 and Vout62, are generated and expressed by Eqn. (11) and (12), respectively, when the positive battery current, Ibat6, is sensed. Vout61 ¼ −R65 ⋅

Rsen6 ⋅ Ibat6 R62

ð11Þ

Vout62 ¼ þR66 ⋅

Rsen6 ⋅ Ibat6 R63

ð12Þ

When the negative current, −Ibat6, is sensed, the output voltages, Vout61 and Vout62, are expressed as Eqn. (13) and (14), respectively. Vout61 ¼ þR65 ⋅

Rsen6 ⋅ Ibat6 R62

ð13Þ

Vout62 ¼ −R66 ⋅

Rsen6 ⋅ Ibat6 R63

ð14Þ

Thus, the bi-directional current sensing is achieved by using two loops. However, the output signals are differential. It is difficult for system integration. Besides, the driving ability is low because of the small output driving current provided by the PMOS transistors. Thus, this paper proposes an on-chip wide range bidirectional current sensor using two feedback sensing loops and an output summation diver to provide the single-ended output signal with large driving ability. Based on the post layout simulation results, it is easy to achieve the sensed current in the range from −1.0 A to + 1.0 A. Moreover, the linearity error is less than ± 0.20%.

118  Tzung-Je Lee and Yen-Ting Chen

(a)

R32

+12V

+12V

Vout1–

Vout1 R31 D31

D32

–12V

Voltage-type hall effect sensor –12V Ibat1

(b)

Vin

Mp

Mps Ibats

Ibat2

Negative feedback

Ibat23 Vx

Vo

Va

Ibias

Is

M4

M3

M5 + R1

(c) Vbat3 Ibat3 K

HP1

M2

M1

M5

Ibat3

Vb

Rsen3 K x Rsen3 Va HP2

HP3

HP4 Vout3

HN3

HN1 HN2

N1

Vout2 –

On-chip Wide Range Bidirectional Current Sensor

RLoad

(d)

chop sys

RShunt

Ibat4

ADC

VShunt

VREF 1+z–1 2

1:4 I 4I – +

I

4I +

VBE

– ΔVBE

R A

Dout

16A 4A

Bias circuit (e) +

64A

Bipolar core Ibat5

Vsen5 – Rsen5

V53 RP

IN

LOAD RA V52

V51 Bias circuits

Vout5 RB

GND

Digital Backend



119

120  Tzung-Je Lee and Yen-Ting Chen

(f) –Ibat6

Ibat6

Rsen6

CHARGER

R61

R64 R62

R63

Vbat6

L O A D

Vout61 R65

Vout62 R66

Fig. 2: Schematics of the traditional current sensors by using (a) Hall effect sensor, (b) MOS current mirror, (c) temperature compensation and error correction, (d) OPA in a feedback loop, and (e) OPAs in two feedback loops.

II On-chip wide range bidirectional current sensor Fig. 3 shows the schematic of the proposed wide range bidirectional current sensor, which is composed of the external sensing resistor Rsen, the feedback sensing loop 1, the feedback sensing loop 2, and the output summation driver. Rsen is in series with the battery current path and senses the battery current, Ibat, according to the voltage drop at Rsen. The feedback sensing loop 1 is employed by the resistors R₂₁, R₂₂, the MOS transistor MP₂₁ and the operational amplifier OPA1 to generate the current I₂. The feedback sensing loop 2 is constructed by the resistors R₂₃, R₂₄, the MOS transistor MP₂₂ and the operational amplifier OPA2 to generate the current I₄. The sensed current signals, I₂ and I₄, are coupled to the output summation driver which is composed of the resistors R₂₅, R₂₆, and OPA3. Finally, the single-ended output voltage signal, VOUT is obtained.

2.1 DC Analysis When the battery current, Ibat, flows through the resistor, the voltage drop at Rsen is derived by V1 −V2 ¼ Ibat ⋅ Rsen

ð15Þ

On-chip Wide Range Bidirectional Current Sensor

121

(From the bidirectional DC/DC converter)

Ibat

(To the battery cell)



Rsen Feedback sensing loop 1

V2

Feedback sensing loop 2

V1

R21 R24

R22 I2 V1–

V1+

–

I4 MP22

MP21

–

+

V2–

+ OPA2

OPA1

V3+ VREF

I3

R23

I1

V2+

OPA3 VOUT

R25 V3–

Output summation driver

R26

Fig. 3: Schematic of the proposed bidirectional current sensor.

The sensed current signals, I₂ and I₄, are expressed by the voltage drop across the resistors R₂₂ and R₂₄, respectively. I2 ¼

V1 −V1− R22

ð16Þ

I4 ¼

V2 −V2− R24

ð17Þ

Because of the virtual short in the OPAs, we have V1þ ¼ V1−

ð18Þ

V2þ ¼ V2−

ð19Þ

V3þ ¼ V3−

ð20Þ

Besides, I₁ = I₃ = 0 is obtained because they flow into the input node of the OPAs with the infinity impedance. Thus, the voltage drop across R₂₁ and R₂₃ are zero and the positive input voltages of OPA1 and OPA2 are expressed by

122  Tzung-Je Lee and Yen-Ting Chen

V1 ¼ V2þ

ð21Þ

V2 ¼ V1þ

ð22Þ

By taking Eqn. (15) and Eqn. (18) ~ (22) into Eqn. (16) and Eqn. (17), The sensed current, I₂ and I₄, are derived by I2 ¼ I4 ¼

V1 −V2 Rsen ¼ ⋅ Ibat R22 R22

ð23Þ

V2 −V1 Rsen ¼− ⋅ Ibat R24 R24

ð24Þ

The output voltage, VOUT, is expressed by V3– and the voltage drop at R₂₆. Because of the virtual short equation in Eqn. (20) and the sensed current signals in Eqn. (23) and (24), VOUT is derived by VOUT ¼ V3− − I2 ⋅ R26 ¼ V3þ − I2 ⋅ R26 ¼ ðVREF þ I4 ⋅ R25 Þ − I2 ⋅ R26
 R25 R26 ⋅ Rsen ⋅ Ibat ¼ VREF − þ R24 R22

ð25Þ

It reveals that the output voltage, VOUT, is ideally a linear equation of the battery current, Ibat.

2.2 Nonideal Analysis However, the linearity is destroyed by the offset of the OPAs and the variation of the resistors in different corners. Because of the offset in OPAs, the virtual short equations are modified by V1þ ¼ V1− þ VOS1

ð26Þ

V2þ ¼ V2− þ VOS2

ð27Þ

V3þ ¼ V3− þ VOS3

ð28Þ

where VOS1, VOS2, and VOS3 denote the offset voltages of OPA1, OPA2 and OPA3, respectively. Thus, the sensed current signals, I₂ and I₄, are derived by I2 ¼

Rsen VOS1 ⋅ Ibat þ R22 R22

ð29Þ

Rsen VOS2 ⋅ Ibat þ R24 R24

ð30Þ

I4 ¼ −

On-chip Wide Range Bidirectional Current Sensor



123

Moreover, according to Eqn. (28) ~ (30), the output voltage is expressed by V OUT ¼ V3− −I2 ⋅ R26 ¼ V3þ −VOS3 −I2 ⋅ R26 ¼ ðVREF þ I4 ⋅ R25 Þ−I2 ⋅ R26 −VOS3
 R25 R26 R26 R25 ⋅ Rsen ⋅ Ibat −VOS3 − ¼ VREF − þ ⋅ VOS1 þ ⋅ VOS2 ð31Þ R24 R22 R22 R24 Besides, the real resistance is denoted by the summation of the ideal resistance and the diffused resistance, ΔR, in different corners. Rreal ¼ Rideal þ ΔR

ð32Þ

−VOS3 −

gain error R25 þ ΔR25 ⋅ VOS1 þ ⋅ VOS2 R24 þ ΔR24

ð33Þ

9 > > > > > > > > > > > > > > > > > > > > > > > > > > > =

> > > > > > > > > > > > > > > > > > > > > > > > > > > ;

R26 þ ΔR26 R22 þ ΔR22

9 > > > > > > > > > > > > =

> > > > > > > > > > > > ;

Thus, the expression of the output voltage with offset of OPAs and diffusion resistances is obtained by taking (32) into Eqn. (31).
 R25 þ ΔR25 R26 þ ΔR26 ⋅ Rsen ⋅ Ibat þ VOUT ¼ VREF − R24 þ ΔR24 R22 þ ΔR22

offset It reveals the gain error and the offset caused by VOS and ΔR. Vreg MP11

Vb101

M P12

Vn

MP01

MP10 p-type input stage MP02 Vp

MP05

MN12

Vb102 Vb102 MN11

Bias stage

MN02 n-type input stage MN10

Input stage

Vb103

MP06

M Vb102 P14

MP08

Vb101

VOUT

Vb102

Vb103

Miller RC

MN07 MN08 MN05

MN01

MP09

IB

MP07 MP13

MP04

MP03

Vb103

MN06

MP15 Miller RC

MN03

MN04 Gain stage

Fig. 4: Schematic of the Wide Range Operational Amplifier.

MN09 Output stage

124  Tzung-Je Lee and Yen-Ting Chen

2.3 Wide Range Operational Amplifier (OPA) Fig. 4 reveals the schematic of the Wide Range Operational Amplifier. The OPA is composed of four stages, the bias stage, the input stage, the gain stage, and the output stage. The bias stage is to provide the operation current for the OPA by using diode-connected MOS strings. The input stage is composed of the p-type and the ntype MOS transistors. The p-type MOS transistors provide the required voltage gain for the low input voltage and the n-type MOS transistors operate for the high input voltage. The wide input range is achieved. The gain stage is composed of the cascade MOS transistors to increase the voltage gain. The two MOS resistors and the two capacitors are utilized for the Miller frequency compensation. The output stage is to provide the required driving ability. The open loop DC gain, Av0, is expressed by multiplication of the transconductance of the input stage, gmI, the output resistance of the gain stage, RI, and the voltage gain of the push-pull output stage, gmII · RII. Av0 ¼ gmI ⋅ RI ⋅ gmII ⋅ RII

ð34Þ

where 8
Vmax; : gmp1 þ gmn1 if Vmin < Vin < Vmax

ð35Þ

RI ¼ ½ðgmn6 ⋅ ron6 Þ ⋅ ron4 jj½ðgmp6 ⋅ rop6 Þ ⋅ rop4 

ð36Þ

1 ¼ gmn ⋅ ro2 2

ð37Þ

gmII ¼ gmn9 þ gmp9

ð38Þ

RII ¼ ron9 jjrop9

ð39Þ

gmI ¼ and

Referring to Eqn. (35), the transconductance is provided by the p-type and/or the n-type input stages in the full input voltage swing. Thus, it could provide the required voltage gain in the wide input voltage range. Moreover, the voltage gain is increased by the output resistors of the cascode MOSFET, RI, and the gain of the push-pull output stage. Besides, the compensation capacitor CC contributes a Miller capacitance with the value of CC multiplied by the voltage gain of the output stage at the gate terminals of MP09 and MN09. It results in the 3-dB pole, fp0, for the Wide Range Operational Amplifier. Moreover, the compensation MOS resistors contribute the zero, fz0, for the Wide Range Operational Amplifier. Thus, the transfer function, Av(f), is expressed by Eqn. (40).

On-chip Wide Range Bidirectional Current Sensor

  Av0 ⋅ 1 þ j fz0f  Av ðf Þ ¼  1 þ j fp0f



125

ð40Þ

where fp0 ¼ −

1 RI ⋅ ð1 þ jgmII ⋅ RII jÞ ⋅ CC

ð41Þ

1 RMP15 ⋅ CC −CC =gm;n09

ð42Þ

fz0 ¼ −

Notably, RMP15 denotes the equivalent resistance of MP15. gm,n09 refers to the transconductance of MN09. On the other hand, MP14 and MP09 are designed to provide the same equivalent resistance and transconductance, respectively. Thus, the same zero is induced for the signal in the drain of MP06. Because the battery current is at the low frequency, thus, the required bandwidth for the Wide Range OPA is easy to be achieved by choosing the appropriate pole and zero. In order to reduce the input referred offset voltage, the random offset and the systematic offsets of the Wide Range OPA are discussed in the following subsections.

2.3.1 Random offset The random offset is resulted from the mismatches in MOSFETs. In the input stages of the Wide Range OPA, the mismatches result in the variation in W/L and Vth, such that the drain current of the MOSFET, ID, is affected. The drain current in the saturation region is given by
 1 W ðVGS −Vth Þ2 ð43Þ ID ¼ μn Cox 2 L
 1 W 2 ¼ μn Cox VOV 2 L

ð44Þ

where VOV (= VGS–Vth) is the overdive voltage. Besides, the transconductance of the MOSFET in the saturation region, gmn, is expressed with the double drain current divided by the overdive voltage. gmn ¼

2 ⋅ ID VOV

ð45Þ

By considering the variation in the threshold voltage caused by mismatches in the n-type input stage, MN02 is assumed to be ideal and MN01 possesses the mismatched

126  Tzung-Je Lee and Yen-Ting Chen

threshold voltages. Thus, the real threshold voltage, Vthn,01, is expressed by the summation of the ideal threshold voltage, Vthn, and the error threshold voltage, ΔVthn. Vthn;01 ¼ Vthn þ ΔVthn

ð46Þ

Vthn;02 ¼ Vthn

ð47Þ

Thus, the drain current of MN01, ID1, is derived by the ideal drain current with the additional terms of ΔVthn. Besides, the second-order term of ΔVthn is ignored if ΔVthn