Multilevel Inverters: Control Methods and Advanced Power Electronic Applications 0323902170, 9780323902175

Table of contents :
Front-Matter_2021_Multilevel-Inverters
Front Matter
Copyright_2021_Multilevel-Inverters
Copyright
Contributors_2021_Multilevel-Inverters
Contributors
Preface_2021_Multilevel-Inverters
Preface
Chapter-1---Pulse-width-modulation-and-control-methods-f_2021_Multilevel-Inv
Pulse width modulation and control methods for multilevel inverters
Introduction
Modulation theory
Pulse modulation methods
PWM role in power electronics
PWM methods for multilevel inverters
Sinusoidal PWM
Selective harmonic elimination PWM (SHE-PWM)
Space vector PWM (SVM-PWM)
Third harmonic injection PWM (THI-PWM)
PLL control methods used in multilevel inverters
Synchronous reference frame (SRF) PLL
αβ PLL
Double synchronous reference frame (DSRF) PLL
Sinusoidal signal integrator (SSI) PLL
Dual second-order generalized integrator (DSOGI) PLL
Enhanced PLL
Control structures for grid-connected inverters
Synchronous reference frame control
Stationary reference frame control
Natural frame control
References
Chapter-2---Hysteresis-control-methods_2021_Multilevel-Inverters
Hysteresis control methods
Introduction
MB hysteresis current control
MOB hysteresis current control
TB hysteresis current control
MB hysteresis voltage control
Hysteresis voltage regulation
Adaptive band low-frequency hysteresis voltage control (AB-LF-HVC)
Description of the studied inverter
Design example
Fundamentals of AB-LF-HVC
Adaptive hysteresis control implementation
Simulated results
Comparison and discussion
Conclusions
References
Chapter-3---Proportional-resonance-control-and-applic_2021_Multilevel-Invert
Proportional resonance control and applications
Introduction
Challenges in inverter systems control
Literature review
Problem statement and description
Problem formulation
System modeling
Effect of parameter variations on system performance
Frequency response of the system
Proposed multifrequency proportional resonant controller
State feedback control
Resonant controller
Polytopic model for uncertain systems
Stability according to Lyapunov
Pole clustering regions
Generalized Lyapunov theorem
H optimization
Controller synthesis with robust D-stability-based LMI approach
Control design algorithm
Results and discussion
Simulation results
Bessel polynomials
Robust control
Stability analysis for parametric variations
Bessel polynomials
Robust control
Conclusion
References
Chapter-4---Model-predictive-control-of-multilevel-diode_2021_Multilevel-Inv
Model predictive control of multilevel diode-clamped converters
Introduction
Power circuit of multilevel diode-clamped converters
Mathematical modeling
Modeling of the converter output currents
Modeling of the DC capacitor voltages
Modeling of the common-mode voltage
Predictive current control scheme
Reference currents calculation
Extrapolation of reference currents
Predictive model
Cost function minimization
Selection of weighting factors
Selection of prediction horizon (h)
Control algorithm
Simulation results
Steady-state analysis
Transient analysis
Robustness against dc-link perturbations
Switching frequency reduction
Common-mode voltage minimization
Conclusion
References
Chapter-5---Model-predictive-control-of-modular-multile_2021_Multilevel-Inve
Model predictive control of modular multilevel converters
Introduction
Power circuit of modular multilevel converter
Converter and submodule configuration
Control objectives
Mathematical modeling of an MMC
Model of DC-link current
Model of output current
Model of circulating current
Model of submodule capacitor voltage
Model of arm voltage
Model predictive control of an MMC
Challenges and issues
Methodologies
Direct model predictive control
Control algorithm
Results and analysis
Indirect model predictive control
Control algorithm
Voltage balancing strategy
Results and analysis
Conclusions
References
Chapter-6---Multilevel-converters-for-renewable-energ_2021_Multilevel-Invert
Multilevel converters for renewable energy systems
Introduction
Overview of multilevel converters for renewable energy
Back-to-back connected multilevel converters for wind energy
BTB neutral-point clamped converter
BTB active neutral-point clamped converter
BTB flying capacitor converter
BTB double-star four-level converter
BTB modular multilevel converter
BTB current source converter
Passive generator-side multilevel converters for wind energy
Vienna rectifier and NPC inverter
MV diode rectifier, 3L boost converter, and NPC inverter
MV diode rectifier, Buck converter, and current source inverter
Multiphase generator-side multilevel converters for wind energy
Cascaded BTB converters with six-phase PMSG
Cascaded PGS converters with six-phase PMSG
Cascaded converters with multiphase PMSG
Direct AC-AC multilevel converters for wind energy
Central multilevel inverters for photovoltaic energy
Neutral-point clamped inverter
T-type inverter
Current source inverter
String multilevel inverters for photovoltaic energy
Multistring multilevel inverters for photovoltaic energy
Conclusion
References
Chapter-7---Multilevel-inverter-applications-for-electr_2021_Multilevel-Inve
Multilevel inverter applications for electric vehicle drives
Introduction
Multilevel inverter topologies for EVs
Cascaded H-bridge multilevel inverter
Neutral point clamped inverter
Active neutral point clamped (ANPC) inverter
T-type NPC inverter
Multilevel inverter control systems for EVs
Field-oriented control
Direct torque control
Model predictive control
Sliding mode control (SMC)
References
Chapter-8---STATCOM-and-DSTATCOM-with-modular-multilev_2021_Multilevel-Inver
STATCOM and DSTATCOM with modular multilevel converters
Introduction
Basic principle of operation
STATCOM DC side capacitor
Multilevel converter topologies
Modular multilevel converter
Basic switching control techniques
SM voltage equalization
Circulating current compensation
DC capacitor design
Arm filter design
Mathematical modeling and control of the MMC-STATCOM
Current control
Positive- and negative-sequence detectors
The positive- and negative-sequence current control
The generation of quadrature signals for the zero-sequence
The zero-sequence current control
The DC terminal voltage control
Applications of STATCOM in modern electric networks
PCC voltage compensation
Control of the PCC positive-sequence voltage
Control of the PCC negative-sequence voltage
Zero-sequence voltage compensation
Simulation of the PCC voltage compensation using the MMC-STATCOM
Case 1
Case 2
Case 3
Practical issues
Consumer imbalance assessment methodology
STATCOM energization scheme
Appendix
References
CHAPTER-9---Solid-state-transformers-with-multilevel-_2021_Multilevel-Invert
Solid state transformers with multilevel inverters
Introduction
Architecture of SSTs
Isolation configurations of SSTs
Multilevel inverter configurations used in SSTs
Conclusions
References
Index_2021_Multilevel-Inverters
Index
A
B
C
D
E
F
G
H
I
L
M
N
O
P
Q
R
S
T
U
V
W
Z

Citation preview

Multilevel Inverters

Multilevel Inverters Control Methods and Advanced Power Electronic Applications

Edited by

Ersan Kabalcı Department of Electrical and Electronics Engineering, Faculty of Engineering and Architecture, Nevsehir Haci Bektas Veli University, Nevsehir, Turkey

Academic Press is an imprint of Elsevier 125 London Wall, London EC2Y 5AS, United Kingdom 525 B Street, Suite 1650, San Diego, CA 92101, United States 50 Hampshire Street, 5th Floor, Cambridge, MA 02139, United States The Boulevard, Langford Lane, Kidlington, Oxford OX5 1GB, United Kingdom Copyright © 2021 Elsevier Inc. All rights reserved. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or any information storage and retrieval system, without permission in writing from the publisher. Details on how to seek permission, further information about the Publisher’s permissions policies and our arrangements with organizations such as the Copyright Clearance Center and the Copyright Licensing Agency, can be found at our website: www.elsevier.com/permissions. This book and the individual contributions contained in it are protected under copyright by the Publisher (other than as may be noted herein). Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary. Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. Library of Congress Cataloging-in-Publication Data A catalog record for this book is available from the Library of Congress British Library Cataloguing-in-Publication Data A catalogue record for this book is available from the British Library ISBN 978-0-323-90217-5 For information on all Academic Press publications visit our website at https://www.elsevier.com/books-and-journals

Publisher: Brian Romer Acquisitions Editor: Graham Nisbet Editorial Project Manager: Sara Valentino Production Project Manager: Sojan P. Pazhayattil Cover Designer: Victoria Pearson Typeset by SPi Global, India

Contributors Pedro Gomes Barbosa Department of Electrical Engineering, Faculty of Engineering, Federal University of Juiz de Fora, Minas Gerais, Brazil Allal El Moubarek Bouzid Electrical and Computer Engineering Department, Universit
e du Qu
ebec a` TroisRivie`res, Trois-Rivie`res, QC, Canada; Laboratoire des Sciences du Num
erique de Nantes (LS2N), Ecole Centrale de Nantes, Nantes, France Aydın Boyar Department of Electrical and Electronics Engineering, Faculty of Engineering and Architecture, Nevsehir Haci Bektas Veli University, Nevsehir, Turkey Hicham Chaoui Intelligent Robotic and Energy Systems Research Group, Department of Electronics, Carleton University, Ottawa, ON, Canada Apparao Dekka Department of Electrical Engineering, Lakehead University, Thunder Bay, ON, Canada Samuel Neves Duarte Department of Electrical Engineering, Faculty of Engineering, Federal University of Juiz de Fora, Minas Gerais, Brazil Freddy Flores-Bahamonde Department of Engineering Sciences, Universidad Andres Bello, Santiago, Chile Ricardo Lizana Fuentes Department of Electrical Engineering, Universidad Cato´lica de la Santı´sima Concepcio´n, Concepcio´n, Chile Mohamed Assaad Hamida Laboratoire des Sciences du Num
erique de Nantes (LS2N), Ecole Centrale de Nantes, Nantes, France Azeddine Houari IREENA Laboratory, University of Nantes, Saint-Nazaire, France Ersan Kabalcı Department of Electrical and Electronics Engineering, Faculty of Engineering and Architecture, Nevsehir Haci Bektas Veli University, Nevsehir, Turkey Yasin Kabalcı Department of Electrical and Electronics Engineering, Faculty of Engineering, € Nigde Omer Halisdemir University, Nigde, Turkey

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Contributors

Samir Kouro Electronics Engineering Department, Universidad T
ecnica Federico Santa Marı´a, Valparaı´so, Chile Oswaldo Lopez-Santos Program of Electronics Engineering, Universidad de Ibagu
e, Ibagu
e, Colombia Marco Rivera Faculty of Engineering, Universidad de Talca, Curico´, Chile Jose Rodriguez Faculty of Engineering, Universidad Andr
es Bello, Santiago, Chile Deepak Ronanki Department of Electrical Engineering, Lakehead University, Thunder Bay, ON, Canada Diego S. Dantonio Program of Electronics Engineering, Universidad de Ibagu
e, Ibagu
e, Colombia Carlos A. Torres-Pinzo´n Faculty of Electronic Engineering, Universidad Santo Toma´s, Bogota´, Colombia Venkata Yaramasu School of Informatics, Computing, and Cyber Systems (SICCS), Northern Arizona University, Flagstaff, AZ, United States

Preface The multilevel inverters are one of the most widely researched power converter types in industrial and residential applications. In the past years, multilevel inverters have gained much attention in the applications of medium-voltage and high-power ranges owing to their various advantages such as low common mode voltage, decreased voltage stress on power semiconductors, low dv/dt ratio compared to two-level topologies, and low total harmonic distortion. The multilevel inverters are efficient in eliminating the harmonic component of voltage and current waveforms compared to two-level inverter topologies at the same power ratings. The improvements in microgrid and distributed generation applications such as integration of wind turbines, solar power plants, and hybrid distribution system have promoted researches on multilevel inverters in terms of device configurations and control methods. The recent applications of multilevel inverters are numerous including adjustable speed drives, motor drives, active filters, integration of renewable energy sources, flexible AC transmission systems (FACTS), and static compensators. Although the most common multilevel inverter topologies are classified into three categories as diode clamped, flying capacitor MLI, and cascaded H-Bridge, many emerging topologies and multilevel inverter configurations exist in the literature and industrial applications. The purpose of this book is to present a broader view of recent control methods and advanced applications of multilevel inverter topologies. Multilevel Inverters Control Methods and Advanced Power Electronic Applications is a book aimed to highlight conventional and developed control methods of multilevel inverters. The emergent application areas of multilevel inverters that have been brought by latest technological improvements are also presented in the book. Several theoretical researches, case analysis, and practical implementation processes are put together in this book that aims to act as research and design guides to help the graduates, postgraduates, and researchers in electrical and electronics engineering and energy systems. The book presents significant results obtained by leading professionals from the industry, research, and academic fields that can be useful to diverse groups in specific areas analyzed in this book. This book comprises of nine chapters providing detailed introduction of control methods and emergent applications of multilevel inverters. Chapter 1 presents the conventional pulse width modulation schemes and implementation methods in detail. The synchronous reference frame (SRF), αβ, double synchronous reference frame (DSRF), sinusoidal signal integrator (SSI), dual second-order generalized integrator (DSOGI) and enhanced phase locked loop (ePLL)-based controllers are also presented with application examples from literature. Chapter 2 highlights the use of hysteresis control techniques applied to multilevel inverters. Firstly, a general classification of different methods applied to control

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Preface

multilevel inverters is presented. Thereafter, hysteresis current control (HCC) and hysteresis voltage control (HVC) are presented to illustrate the use of the technique in grid-connected and stand-alone applications, respectively. Chapter 3 provides comprehensive presentation of robust control strategy of proportional resonant controller based on the linear matrix inequalities control theory. The development of mathematical model of a multilevel inverter connected to the grid is presented in the chapter. Chapter 4 reviews model predictive control scheme for the current control, balancing of dc capacitor voltage, switching frequency reduction, and common-mode voltage mitigation in multilevel diode-clamped converters. The continuous-time and discrete-time models of control variables of multilevel converters are formulated in terms of switching states. The feasibility of the model predictive control scheme is verified by MATLAB simulation results on three- to six-level diode-clamped converters. Chapter 5 presents direct model predictive control (DMPC) and indirect model predictive control (IMPC) schemes for a modular multilevel inverter. The steadystate and dynamic performance of DMPC and IMPC schemes are verified through simulation studies. The simulation results show the output current tracking, SM capacitor voltage regulation, and circulating current reduction for modular multilevel inverter application. Chapter 6 provides an overview of multilevel converters in wind and photovoltaic energy systems. The most successful multilevel inverter configurations are addressed along with few promising topologies available in the literature. The multilevel converters are analyzed in four categories for wind energy systems, while the central, string, and multistring inverter configurations are discussed in photovoltaic energy systems with respect to the configuration and operation. Chapter 7 deals with the applications of multilevel inverters through electric vehicles, hybrid electric vehicles, and plug-in hybrid electric vehicles. The literature survey on electric vehicles, multilevel inverter topologies used in traction control, and control methods are analyzed and presented in this chapter. Chapter 8 presents static synchronous compensator (STATCOM) and distribution static synchronous compensator (DSTATCOM) as key applications of multilevel inverters in transmission and distribution systems. The mathematical modeling and improvement of controller are presented in detail in the chapter where applications are discussed with the simulation studies. Chapter 9 presents a survey on solid-state transformer architectures, which are the most recent applications of multilevel inverters and modular solid-state transformer researches. The main classification of solid-state transformer is dealt with input stage, transformation stage and output stage, and device configurations achieved with design procedures through the chapter. Multilevel Inverters Control Methods and Advanced Power Electronic Applications aims to help electrical and electronics engineers for their future researches in the field power electronics and converters. The book also explores the recent

Preface

progress in several application areas of multilevel inverters including machine drives, active filters, static var. compensator, microgrid control, and their performance evaluation in terms of grid integration. I hope this book is helpful for young researchers and practitioners in the area of electrical engineering. Editor and authors made all efforts to have a useful and comprehensive book for readers.

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Pulse width modulation and control methods for multilevel inverters

1

Ersan Kabalcıa, Aydın Boyara, and Yasin Kabalcıb a

Department of Electrical and Electronics Engineering, Faculty of Engineering and Architecture, Nevsehir Haci Bektas Veli University, Nevsehir, Turkey bDepartment of Electrical and Electronics € Engineering, Faculty of Engineering, Nigde Omer Halisdemir University, Nigde, Turkey

1.1 Introduction Multilevel inverters (MLIs) have been proposed for increasing the power level and improving the power factor as compared to conventional two-level inverters. The application areas of MLIs are residential use in uninterruptible power supplies (UPSs); single-phase motor drives in home appliances; industrial applications in traction control, adjustable speed drives, and four-quadrant drive systems; utility interactions of renewable energy sources (RESs); static compensators (STATCOMs); VAR compensators; power factor controllers; and unified power flow controllers (UPFCs). All these applications require increased reliability in terms of lower switching losses, increased power factor, and low total harmonic distortion (THD) for ensuring robust operation. The evolution of MLIs can be analyzed in two main areas, as topology improvements and controller improvements. This section deals with modulation schemes and controller infrastructures of MLIs, which are required in many applications such as motor drives and grid-connected operations. Pulse width modulation (PWM), which is based on comparing the modulating and carrier signal for generating the switching pulses, is the fundamental switching and control strategy used in MLI control. Since their first applications, many improved variations of the PWM method have been developed in order to increase the overall efficiency and controllability of MLIs. The PWM method used to control the switching sequences of inverters is directly responsible for controlling the output waveforms of current and voltage, while defining the efficiency of the inverter by managing the switching losses and THD ratios [1, 2]. The modulator is fed by a number of measurement or control inputs in order to improve on the controller-based modulator, which is convenient for commutating switching devices of the inverter. While a fundamental modulator generates output signals as a function of modulating and carrier signal comparison, the controller triggers the modulator regarding outcomes of decision-making algorithms, which use physical measurements such as Multilevel Inverters. https://doi.org/10.1016/B978-0-323-90217-5.00009-5 Copyright # 2021 Elsevier Inc. All rights reserved.

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CHAPTER 1 Pulse width modulation and control methods

current, voltage, phase angle, rotational speed, and so on, as required depending on application type. The modulation methods used in the control of MLIs are defined as fundamental switching frequency methods and high switching frequency methods, with regard to carrier frequencies. The fundamental switching frequency methods are similar to line frequency or natural commutation of thyristors, with single or two commutation signals at each period. However, the high-frequency method generates thousands of switching signals at each period due to its higher carrier frequency at several kilohertz rates. The most widely used fundamental switching frequency methods are selective harmonic elimination PWM (SHE-PWM), space vector PWM (SVM), angle calculation, and nearest level control methods. While SHE-PWM and SVM are used in high-frequency switching, sinusoidal PWM (SPWM) is another widely used method in this category [1, 3]. Another definition of MLI control schemes including the PWM methods is based on control loops and reference types, as listed in Fig. 1.1. The reference-based control methods are improved with a modified PWM modulator that is triggered by any reference signal inherited from the sensor or actuators located at the physical measurement points of an MLI and connected system. The reference values can be rotational speed of a motor drive, current or voltage magnitudes of a utility grid, state of charge (SoC) of an energy storage system, active and reactive power rates of a controlled compensator, or any number of similar variations, depending on the application where the MLI is located. The carrier-based PWM methods are operated in open loop without any feedback signal or in closed-loop current control, where the load current is used as a triggering feedback in the modulator. Any type of addressed PWM methods can be used in these controllers as the core modulator, and feedback signals applied to the controller are obtained from current sensors located at the output of the MLI for tracking. These controllers are improved by using either any type of

FIG. 1.1 A general diagram showing control schemes used in multilevel inverters [1].

1.2 Modulation theory

conventional proportional-integral-derivative (PID) observers or with advanced decision-making algorithms based on fuzzy logic controllers, genetic algorithms, evolutionary algorithms, or neural networks. The optimized harmonics stepped pulse width modulation (OHS–PWM) is another high-frequency switching control method shown in Fig. 1.1. This chapter presents a brief introduction to modulation theory in order to provide further understanding of modulator and controller design. Afterward, the conventional PWM methods introduced are described in more detail, with modulator architectures and design criteria. The control methods and controller design research studies are described in the following subsections, followed by soft computing methods used in controller development studies. The presented modulator and controller applications are discussed in terms of requirements, reliability, and application areas in the remainder of this chapter.

1.2 Modulation theory Examples of analog signals include speech, music, images, or video. These signals are mainly classified according to their bandwidth, flexible range, or the type of signal. The transmitted analog signal is represented by m(t), which is considered as a low-pass signal with a bandwidth of W (i.e., M(f) ≡ 0 where jf j > W) [4, 5]. The power of the related signal can be expressed as 1 Pm ¼ lim T!∞ T

ZT=2 jmðtÞj2 dt

(1.1)

T=2

The message signal m(t) is then superimposed with the carrier signal c(t) given in Eq. (1.2) to send over the communication channel: cðtÞ ¼ Ac cos ð2πfc t + ϕc Þ

(1.2)

where Ac, fc, and ϕc represent amplitude, frequency, and phase of the carrier, respectively. The rate of ϕc varies with the shift in the origin of time. Therefore, the time origin is selected in such a way that ϕc ¼ 0, which helps to sustain the generality of the signal. It is assumed that either amplitude, frequency, or phase of the carrier signal c(t) is varied when modulated with the message signal m(t), such that the modulated signal becomes a function of the amplitude, frequency, or phase of the message signal. Hence, the nature of the message signal m(t) is transformed from low-pass to bandpass after the modulation process and lies adjacent to the carrier frequency fc. The following features are attained after modulating the message signal with the carrier signal [4, 5]. Ø The lowpass signal is converted into a passband signal such that passband features of the channel are harmonized by the spectrum of the transmitted bandpass signal. For example, the signal frequency must be enhanced in the range

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CHAPTER 1 Pulse width modulation and control methods

of gigahertz for transmission over the channel when sending speech over microwave links in telephony transmission. In simpler terms, speech signals are converted from the low-frequency range (up to 4 kHz) to the gigahertz range using modulation, or a combination of several modulation methods. Ø The construction of the transmitter is simplified and it becomes more efficient in terms of cost and energy consumption when a higher frequency band is used. For example, huge antennas are required when signals are transmitted at low frequency ranges using electromagnetic waves. However, smaller antennas can be deployed after using a modulation technique that converts the low-frequency band into higher frequencies. This not only simplifies the construction of the transmitter (and the receiver), but also reduces the cost and probably the energy consumption. Ø The simultaneous transmission of signals from various message sources can now be realized using multiplexing methods such as frequency-division multiplexing (FDM) and time-division multiplexing (TDM). Ø After the modulation process, the bandwidth of the transmitted signal is expanded to provide better noise and interference immunity against noisy channels.

1.2.1 Pulse modulation methods Pulse modulation is employed to modify a binary pulse signal used to signify the information for transmission. The transmission of information using binary techniques can facilitate the regeneration of degraded signals and provide noise tolerance. Clipper circuits can be used to get rid of any noise that has been combined with the binary signal along the path. Moreover, a Schmitt trigger, comparator, or similar circuit can be used to reshape the signal to remove any distortion that occurred in the signal. The features of binary methods can be used to enhance the quality of communications when information is transmitted via a carrier comprising binary pulses. Pulse modulation systems were established to benefit from these qualities. To adjust a binary (on/off) or pulsed carrier, an analog information signal is typically used by some means. The carrier is sent in short bursts whose interval and amplitude match up to the modulation, rather than transmitting a continuous carrier using pulse modulation. The short duty cycle of the carrier is carefully chosen to assure that the carrier remains off for a longer period than the bursts. Thus, the average carrier power can be set low by using this arrangement, even if high peak powers are encountered. The peak power pulses can navigate a longer distance and more efficiently stunt any noise in the system at a given average power. There are three main forms of pulse modulation: pulse-amplitude modulation (PAM), pulse-width modulation (PWM), and pulse-position modulation (PPM) [4–6]. An analog modulating signal and the different waveforms generated by PAM, PWM, and PPM modulators are shown in Fig. 1.2. It is mandatory to sample analog signals in all three cases for analog-to-digital (A/D) conversion. All the sampling points, which are equally spaced with constant time interval t and subject to the

1.2 Modulation theory

FIG. 1.2 Comparison of pulse modulation methods over a random analog message signal.

Nyquist conditions, are marked on the analog waveform. According to the Nyquist criteria, the sampling rate of the analog signal should be kept at least twice the highest frequency component of the analog signal. The amplitude of the PAM signal with a series of constant-width pulse changes in accordance with the analog signal is as shown in Fig. 1.2. Since the duty cycle is low, narrow pulses are achieved, which means the width of the pulse is shorter than the sampling period. The PWM signal consists of only two levels of amplitude (with its binary nature), whereas the width of the pulse or duration of the pulse depends on the amplitude of the analog signal.

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CHAPTER 1 Pulse width modulation and control methods

It is also worth noting that the widths of the pulses are usually narrow at low analog voltages, while the wider pulse widths are realized at the higher value of amplitudes. However, the position of the pulses varies according to the amplitude of the analog signal in PPM. These pulses are usually very narrow; therefore, they may be utilized in a baseband form to modulate a high-frequency radio carrier in different applications. According to their shape, the carrier is set as either ON or OFF. PAM is the simplest and cheapest in terms of implementation among the available three forms of pulse modulation [5, 6]. A major drawback of the PAM technique is that it can be easily affected by noise, since the pulses change according to the amplitude. Moreover, clipping techniques also cannot be applied to remove noise because there is a possibility that they will also eliminate the modulation. On the other hand, PWM and PPM allow clipping to decrease the noise level, due to their binary nature. The pulse modulation methods have remained very popular for many decades, but in recent years their use has been remarkably reduced. PWM is most commonly used out of the three and is found in a variety of applications, such as remote-control purposes (model airplanes, boats, and cars), switch-mode power supplies (DC-DC converters, regulators, etc.), motor speed control, and class D audio switching power amplifiers.

1.2.2 PWM role in power electronics The electronic switches based on semiconductors allow the conversion of the form of electrical energy from one level of voltage/current/frequency into another form in power electronic converters [7, 8]. Generally, the control elements used in electrical circuits operate in the linear active region. In contrast, electronic switches based on semiconductors operate in only one of two states (either fully ON or fully OFF), which makes them more versatile than the earlier ones. In a power electronic converter, modulation is the process that switches the electronic devices from one state to another. Every group of power converters utilizes its own suitable modulation approaches for enhancing the circuit operation for their group to meet a set criterion. Different issues must be taken into account while planning modulation approaches for a specific group of converters, such as switching frequency, distortion, losses, harmonic generation, and speed of response. Generally, the output voltage of a power inverter is a pure sinusoidal waveform having nominal distortion. However, the output voltage is a series of rectangular waveforms in some specific inverters. Use of the appropriate modulation approaches is vital to control these rectangular waveforms to produce the required waveforms, which is considered to be one of the major concerns for the controlling of power inverters. This can be achieved by devising a suitable modulation control scheme to acquire a required voltage of a fundamental frequency and to remove approximately all the higher-order harmonics. Depending on the nominal rated power, the PMW method is considered a highspeed process in modern converters that varies from a few kilohertz (in motor control applications) to several megahertz (in resonant converters for power supply applications). The AC output of power electronic converters is controlled by the broadly

1.3 PWM methods for multilevel inverters

used PWM scheme. The duty cycle of converter switches can be changed at a high frequency to realize a desired average low-frequency output voltage or current using this scheme. Modulation theory has gotten a lot of attention from researchers in the field of power electronics for almost three decades, and it continues to receive considerable acknowledgment and attention. Essentially, whole modulation techniques try to generate trains of switching pulses that have the identical fundamental volt-second average as the desired reference waveform. However, these trains of switched pulses contain undesired harmonic components that need to be eliminated. To achieve this objective, the functionality of any PWM technique has two parts. The first is to calculate the converter switching ON times, which helps in producing the requested (low-frequency) output voltage or current, and then to find out the most efficient way of ordering the switching operation to reduce undesirable harmonic distortion, switching losses, or other particular performance criteria [7, 8]. The PWM scheme has different types, depending on its implementation method. However, in all these types, the primary objective is to produce a high-quality sinusoidal output voltage waveform with the requested fundamental frequency and magnitude after several filtering processes. The overall voltage distortion cannot be minimized in the case of inverters due to harmonics. Therefore, an appropriate switching-control mechanism is required that can minimize the magnitudes of lower-order harmonic voltages, but the problem is that it will also enhance the magnitudes of higher-order harmonic voltages for compensation. This problem can be tackled by utilizing lower sizes of filters and capacitors to filter the harmonic voltages corresponding to higher frequencies. It is also very interesting to note that filters are not required in many of the loads, such as motor loads, that have the potential to restrain high-frequency harmonic currents. The quality of voltage obtained by a PWM inverter is determined by a comprehensive harmonic analysis of the produced waveform. The related load phase voltage waveform can be acquired after eliminating the third and multiples of third harmonic components from the pole voltage waveform. It is easier to visualize and examine the pole voltage waveforms of a three-phase inverter; therefore, the harmonic analysis of load phase and line voltage waveforms can be performed by taking advantage of the harmonic analysis of the pole voltages. It is understood that the third and multiples of third harmonic elements available in the pole voltage waveforms will not cause any problems for the load phase and line voltages. The details of the different PWM methods utilized in power electronics are explained in the following section.

1.3 PWM methods for multilevel inverters This section describes the design properties and features of conventional modulation schemes, which are defined as sinusoidal PWM, space vector PWM, selective harmonic elimination PWM, and third harmonic injection PWM methods.

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CHAPTER 1 Pulse width modulation and control methods

1.3.1 Sinusoidal PWM One of the popular switching methods used in power converter systems is the sinusoidal pulse width modulation (SPWM) approach. This method is based on comparing the sinusoidal reference voltage with a triangular carrier signal in order to form converter gate signals [2]. Typical applications of this approach for traditional twolevel inverters are illustrated for both unipolar and bipolar PWM methods in Fig. 1.3. While the carrier signal (VC) is compared with only one reference waveform (Vr) in the unipolar approach, as seen in Fig. 1.3A, the Vc is compared with dual reference waveforms in the other one, in which the utilized references have reversed phases. One of the most crucial problems of high-power applications is the power consumption issue. Therefore, the main frequency SPWM control approach has been recommended to reduce switching losses. In addition, the SPWM control techniques with multicarriers that have been classified based on carrier signal type (e.g., vertical or horizontal) have been proposed to improve multilevel inverter performance. Whereas phase dissipation (PD), phase opposition dissipation (POD), and alternative phase opposition dissipation (APOD) methods are based on vertical carrier type, the phase-shifted (PS) control method is considered a horizontal carrier type. It is worth

FIG. 1.3 SPWM techniques. (A) Unipolar SPWM, (B) Bipolar SPWM.

1.3 PWM methods for multilevel inverters

FIG. 1.4 Multicarrier SPWM control strategies. (A) PD, (B) POD, (C) APOD, (D) PS.

highlighting that the use of the PD-PWM technique is more beneficial in neutralpoint clamped (NPC) systems, while the PS-PWM provides advantages in both cascaded H-bridges and flying capacitors. The aforementioned control methods are depicted in Fig. 1.4 [9, 10].

1.3.2 Selective harmonic elimination PWM (SHE-PWM) The selective harmonic elimination (SHE) PWM method has been developed for eliminating low-order harmonics and providing both low total harmonic distortion (THD) and low distortion factor (DF) values at the signal acquired from the power inverter [9, 11]. When compared to the SPWM or SVPWM, this PWM approach provides decreased switching losses, and, as a result of this superiority, the SHE-PWM can be utilized to manage power converters with both lower switching frequencies and reduced power consumption. Therefore the SHE-PWM method can reach a wide range of applications in high-power converter systems. Furthermore, the possibility of generating electromagnetic interference on neighboring systems is very low due to its low-power operation. One of the most important drawbacks of this approach is its computational complexity. Nonlinear equations comprising trigonometric

9

10

CHAPTER 1 Pulse width modulation and control methods

expressions of this technique, which lead to multiple solution sets and the obligation to employ lookup tables, should be solved to present a good solution. In addition, this approach is inappropriate for multilevel inverters since the high number of voltage levels will increase the equation size [9]. However, this technique has received much attention in the literature because it is more advantageous than the conventional techniques. These advantages include ensuring lower switching frequency, providing direct control opportunity via harmonics of the output waveform, and keeping the circuit topology advantages by releasing triple harmonics uncontrolled in threephased systems [12]. In order to eliminate harmonics, this method first aims to detect switching angles of harmonics, and then tries to acquire Fourier series expansion of the output signal. Eq. (1.3) presents the Fourier series expansion of an 11-level inverter system [1]: V ðωtÞ ¼

∞ X

4Vdc ð cos ðnθ1 Þ + cos ðnθ2 Þ + … + cos ðnθ5 Þ  sin ðnωtÞÞ nπ n¼1, 3, 5, …

(1.3)

where n stands for the harmonic order of the multilevel inverter. The needed switching angles to remove the 5th, 7th, 11th, and 13th harmonic orders at the fundamental switching frequency can be derived for the considered multilevel inverter as follows [1]: cos ðθ1 Þ + cos ðθ2 Þ + cos ðθ3 Þ + cos ðθ4 Þ + cos ðθ5 Þ ¼ 5  ma cos ð5θ1 Þ + cos ð5θ2 Þ + … + cos ð5θ5 Þ ¼ 0 cos ð7θ1 Þ + cos ð7θ2 Þ + … + cos ð7θ5 Þ ¼ 0

(1.4)

cos ð11θ1 Þ + cos ð11θ2 Þ + … + cos ð11θ5 Þ ¼ 0 cos ð13θ1 Þ + cos ð13θ2 Þ + … + cos ð13θ5 Þ ¼ 0

where ma shows the modulation index parameter of the modulator system. Properly selecting switching angles leads to a decrease in the THD value of the voltage signal. The Newton–Raphson iteration method should be applied to obtain angle values due to the nonlinearities of Eq. (1.4). Thanks to the Newton–Raphson iteration method, the switching angle values are determined to be θ1 ¼ 6.57 degrees, θ2 ¼ 18.94 degrees, θ3 ¼ 27.18 degrees, θ4 ¼ 45.14 degrees, and θ5 ¼ 62.24 degrees for the value of ma of 0.8. In real-time applications, it is possible to determine feasible switching angle values and keep them in a look-up table stored in internal or external memory. Although the switching-angle calculation process of this method may be considered a drawback, the Newton–Raphson iteration method eases the procedure. Nevertheless, the exact values cannot be acquired at the final stage since the initial values are determined based on assumption or prediction. Therefore, a high number of switching angles and/or DC sources will limit the acquisition of precise results [1].

1.3.3 Space vector PWM (SVM-PWM) The space vector modulation PWM (SVM-PWM) technique is an alternative switching method in which numerous vector states are employed for modulating the

1.3 PWM methods for multilevel inverters

reference signal. It is a digital modulation approach that essentially aims to form PWM load line voltages. The SVM determines the switching vectors by the use of control algorithm variables, which correspond to several points in the complex space of (α,β). Since the determination of sectors and the selection of switching sequences are troublesome tasks, this method is inappropriate for a high number of voltage levels. For instance, (m  1)2 vector combinations per sector and m3 switching sequences are required for an m-level inverter system. Also, the number of main space vectors is (3m2  3 m + 1) for this condition. The common-mode voltage and switching losses can be decreased by properly choosing the switching combinations and modulation vectors as well as the use of floating capacitors [1, 13]. As given in Eq. (1.5), three-phase parameters are converted from a reference frame with three phases to an orthogonal stationary reference frame with two axes, thanks to the Clarke transformation, which is also called the αβ  transformation [14]: "

Vα Vβ

#

1 1 32 Va 3  2 2 76 7 26 6 7 ¼ 6 pffiffiffi pffiffiffi 7 54 Vb 5 34 3 3 0  Vc 2 2 2

1 

(1.5)

The magnitude of the reference voltage vector can be written as follows [15]:   qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi Vref  ¼ V 2 + V 2 α

β

(1.6)

and the vector angle can be expressed as [15]: θ ¼ tan 1

Vβ Vα

(1.7)

Fig. 1.5 illustrates the space vector diagram of a three-level inverter where vector intersections are used to depict 27 different switching states through vectors. In this diagram, zero-voltage vectors are shown via three-state switching components such as 000, 111, or 1  11. Also, the vectors here can be categorized into three sets as small vectors (V1–V6), medium vectors (V8, V10, V12, V14, V16, V18), and large vectors (V7, V9, V11, V13, V15, V17). If it is assumed that the vector Vref is located in the second region (D2) of the sector S1, voltage vectors V1, V2, V8 are able to constitute this reference vector at the time of sampling (TS). In addition, the duration of the voltage vector affects Vref. Therefore, the expression for the active duration (ON state) of voltage vectors can be expressed as follows [1]: Vref  Ts ¼ V1  ta + V2  tb + V8  tc

(1.8)

where ta, tb and tc stand for ON state durations and they can be calculated as follows: ta ¼ Ts  2n sinθ π  tb ¼ 2n sin + θ  Ts 3 π  tc ¼ Ts  2n sin  θ 3

(1.9)

11

12

CHAPTER 1 Pulse width modulation and control methods

FIG. 1.5 Space vector diagram of a three-level inverter with sector and subsectors.

where n ¼

 pffiffi  Vref 4 3 3 Vdc Ts [1]. The result of these expressions provides only one Vref

value in a specific region of the selected sector. Therefore, the calculations should be expanded for each switching sequence [1].

1.3.4 Third harmonic injection PWM (THI-PWM) Another PWM-based control method is the third harmonic injection PWM (THIPWM) commonly employed in three-phase power systems rather than single-phase ones. In this method, two sinusoidal waveforms are combined to obtain a reference signal and the frequency of one sine wave is selected three times higher than the other one. Later, triggering pulse signals are created by comparing the reference waveform with the carrier signal. The reference of the THI signal checks the amplitude of the third harmonic component for ensuring the required quality of the output. This process and the flattened structure of the reference signal reduce the switching losses. Since the third harmonic components are removed, this method enables more

1.3 PWM methods for multilevel inverters

FIG. 1.6 Injection of third harmonic into sinusoidal signal.

efficient use of DC sources [16, 17]. The THI reference signal, which is analytically given in Eq. (1.10), is generated by combining the fundamental sine wave and third harmonic signal attenuated by 1/6. This process leads to increasing the fundamental component of the sine wave by 15%, which is depicted in Fig. 1.6 [18].   1 Vref ¼ 1:15 sinωt + sin3ωt 6

(1.10)

Fig. 1.7 illustrates a THI-PWM method example in which a single-phase 2-legs 5-level inverter system is considered. The reference signals are shown in the carrier band region and they are regularly compared with the carrier signals. When the reference value is higher than the value of the carrier signal, the status of the switch associated with the carrier is changed to ON. Similarly, when the reference value is lower than the value of the carrier signal, the status of the switch associated with the carrier is changed to OFF [18]. Surprisingly, the THI-PWM method presents excellent improvements over the traditional PWM method. Moreover, the THI-PWM method ensures up to a 15% extension in the linear modulation region over that of the traditional PWM method. Thus this method is regarded as superior to the SVPWM method and it provides convenience in implementation. Furthermore, by switching at high frequency, harmonic distortion elimination can be realized through this technique [19].

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CHAPTER 1 Pulse width modulation and control methods

FIG. 1.7 Third harmonic injection PWM method.

1.4 PLL control methods used in multilevel inverters The two main types of applications of MLIs are utility applications, which are essential for integrating RESs to the utility grid and include compensators and active filter applications such as STATCOM, D-STATCOM, UPFC, and VAR compensators, and industrial applications, such as motor drives, adjustable speed drives, fieldoriented control (FOC) of motors, and so on. This section examines control methods of MLIs implemented for these applications. The PLL as a controller is used to force the output waveform of the controlled system to track the reference, which usually comes from the utility grid in which the MLI is used to integrate distributed generation sources. Although many different

1.4 PLL control methods used in multilevel inverters

FIG. 1.8 Block diagram of a phase-locked loop.

PLL controllers have been proposed in the existing literature, almost all of them are based on three basic components, as seen in Fig. 1.8, responsible for phase detection, filtering in a loop, and voltage-controlled oscillation. The components of a PLL controller are thus the phase detector (PD), loop filter, and voltage-controlled oscillator (VCO). The PD acts as the fundamental comparator between the measured and reference value and generates the error signal er referring to the difference of the phase angles. The loop filter is responsible for decreasing the error rate and removing the unnecessary coefficients in the control signal for generating the appropriate tracking command. The loop filter ensures the reliability and stability of the PLL while increasing the dynamic response characteristic. The VCO generates the estimated phase angle that minimizes the error between the measured and reference signal, decreasing the PLL error in the next cycle, to ensure the tracking feature. The input voltage from the three-phase grid is denoted with Vabc in Fig. 1.8, while fr is the frequency generated by the loop filter [20]. Three-phase PLL configurations are widely seen in MLI applications in gridforming or grid-conditioning systems. The main contributions of the PLL to these MLI systems are harmonic and noise elimination and improvements in the dynamic response or behaviors in steady and transient states. Moreover, PLL-assisted MLI control systems provide rapid calculation and increased optimization in operation. A wide variety of PLL controllers are reviewed in the following sections, based on a detailed literature survey.

1.4.1 Synchronous reference frame (SRF) PLL The synchronous reference frame PLL (SRF-PLL) is one of the most widely used control methods in three-phase systems. The block diagram proposed in [21] is illustrated in Fig. 1.9, where three-phase grid voltages Vabc are obtained in a rotational reference frame. The three-phase rotational frame is converted to a stationary frame, as shown, using the dq transformation. The direct and quadrature components are dispatched for active and reactive power control, respectively. The conversion from rotational frame to stationary frame is similar to that done in the SVM control method, where abc components are converted to the αβ axis by the Clarke transformation to generate the stationary frame variables (Vα, Vβ), and then transformed to the dq axis by the Park transformation. The generation steps are analytically represented in Eqs. (11, 12). Once the reference frame transformation is completed, the

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CHAPTER 1 Pulse width modulation and control methods

FIG. 1.9 Block diagram of SRF-PLL.

estimated phase angle of the utility grid θ∗ is used as a feedback signal to the Park transformation for compensating dq components [21–24]. The Clarke and Park transformation matrices are represented as follows, respectively, where θ∗ denotes the estimated phase angle and θ represents the phase angle of the utility grid: "

Vα Vβ

"

Vd Vq

#

2

3 1 1 2 Va 3  1  26 2 2 76 7 ¼ 6 pffiffiffi pffiffiffi 7 4 Vb 5 34 3 35 0  Vc 2 2 "

# ¼

cos ðθ∗ Þ

sin ðθ∗ Þ

 sin ðθ∗ Þ cos ðθ∗ Þ

#

Vα Vβ

(1.11)

(1.12)

The SRF-PLL is proposed to be operated in unbalanced grid voltages where the transformation components generate double the fundamental grid frequency that can be used in the phase detector. The Park transformation voltage coefficients represent direct and quadrature components as a two-axis output, and the estimated phase angle is identical with the phase angle of the grid under balanced and undistorted grid conditions. In these operation conditions, Vd would be equal to the magnitude of the grid voltage, while Vq represents zero as depicted in Eqs. (1.13 and 1.14) [21, 25, 26]. Vd ¼ Vm cos ðθ  θ∗ Þ

(1.13)

Vq ¼ Vm sin ðθ  θ∗ Þ

(1.14)

The loop filter of an SRF-PLL should provide precise dynamic performance based on the estimated phase angle calculated, and rapid locking response due to the finetuning loop filter. In regular and balanced grid conditions, the filter ensures both conditions simultaneously, and the grid voltage and phase angle are obtained rapidly and precisely. When grid disturbances and unbalanced operations occur, the bandwidth of the loop filter should be decreased to provide the same precise operation, to overcome high-order harmonic content and unstable conditions. This causes an

1.4 PLL control methods used in multilevel inverters

increment in synchronization time, which decreases the sensitivity of the dynamic response and is followed by unstable responses. This issue is tackled by including a low-pass filter in the PLL controller, which increases the system stability and facilitates the tracking capability of the system. The loop filter of the SRF-PLL is mostly composed of a regular PI controller for managing the Vq component. The PI parameters are required to be determined accurately for detecting the phase angle of the utility grid rapidly. This duty may cause some unstable operations under unbalanced or disturbed grid conditions, which decreases the reliability of the PLL controller. Therefore, it should be noted that the SRF-PLL operates accurately under steady grid conditions but requires various filtering solutions such as low-pass, adaptive notch, or dynamic filters for unbalanced grid operations [27–29].

1.4.2 αβ PLL The phase angle of the grid voltage is basically obtained by filtering the measured abc voltages, where filters are operated either in the αβ stationary reference frame or the dq synchronous rotating reference frame. Fig. 1.10 shows the generation of phase angle by using the stationary reference frame in a matrix transform method. Although various type of filters can be used to determine components of utility grid voltage, fundamental filters cause delays in obtaining the phase angle. The αβPLL methods use a similar transformation in the dq synchronous rotating reference frame, where it sets the phase angle of the PLL to zero, given in Eq. (1.15), for transforming the abc rotating reference frame components to the stationary αβ reference frame. The Vd and Vq values are calculated similarly to the SRF-PLL method, while the estimated phase angle of αβPLL θαβPLL is obtained as shown in Eq. (1.18), where it is convenient for small Δθ values [30, 31]. "

Vd Vq

#

2 3 "





 # Va cos θαβPLL  120 cos θαβPLL + 120 6 7 2 cos θαβPLL ¼



 4 Vb 5

 3 sin θαβPLL sin θαβPLL  120 sin θαβPLL + 120 Vc

(1.15)

 Vd ¼ Vm cos θGrid  θαβPLL

(1.16)

FIG. 1.10 Block diagram of αβPLL.

17

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CHAPTER 1 Pulse width modulation and control methods

 Vq ¼ Vm sin θGrid  θαβPLL

(1.17)

 Δθ ¼ θGrid  θαβPLL  sin θGrid  θαβPLL



 , Δθ  sin ðθGrid Þ cos θαβPLL  sin θαβPLL cos ðθGrid Þ

(1.18)

The closed loop control shown in the block diagram of αβPLL (Fig. 1.10) is responsible for forcing the Δθ difference to zero due to the operation of the PI controller. Since the αβPLL has similar problems to the SRF-PLL control in unbalanced grid conditions, it is not widely preferred over regular filter operations and requires featured loop filter solutions for improving the efficiency.

1.4.3 Double synchronous reference frame (DSRF) PLL The deficiencies of SRF-PLL and αβPLL methods under unbalanced and disturbed grid operations are overcome by the double synchronous reference frame PLL (DSRF-PLL), which uses decoupled positive and negative components of the grid voltage. The block diagram of DSRF-PLL designed with positive and negative synchronous reference frames, denoted as Decoupling A and Decoupling B, is illustrated in Fig. 1.11. In this method, two separate SRF-PLL frames are operated to generate Vdq + and Vdq  reference frames, with their resultant angular speeds. The outcomes of angular speeds and corresponding phase angle of each reference frame are obtained as + ω and θ +, and  ω and θ , respectively. The block diagrams of Decoupling A and Decoupling B sections generating positive and negative sequences in the DSSRF-PLL are shown in Figs. 1.12 and 1.13. The decoupling network of the DSRF-PLL is used to eliminate the effects of positive and negative frames on each other. Unlike the regular SRF-PLL, which deals with only the positive sequence of the utility grid, the DSRF-PLL overcomes

FIG. 1.11 Block diagram of DSRF-PLL.

1.4 PLL control methods used in multilevel inverters

FIG. 1.12 Block diagram of Decoupling A in DSRF-PLL.

FIG. 1.13 Block diagram of Decoupling B in DSRF-PLL.

unbalanced and distorted grid voltage due to its positive and negative calculation algorithm. The analytical representations of positive and negative sequences are given in the following equations, where the resultant terms denote DC terms for each sequence and oscillation coefficients of complementary sequences [30, 31].  

1 cos ð2ωtÞ Vdq + ¼ Tdq +  Vαβ ¼ V + + V 0 sin ð2ωtÞ

(1.19)

 

1 cos ð2ωtÞ + V+ Vdq ¼ Tdq  Vαβ ¼ V 0 sin ð2ωtÞ

(1.20)

19

20

CHAPTER 1 Pulse width modulation and control methods

The main duty of complementary decoupling blocks is to remove the coupling effect between the positive and negative ones and facilitate the operation of the low-pass filter in transient or unbalanced conditions [31].

1.4.4 Sinusoidal signal integrator (SSI) PLL The sinusoidal signal integrator PLL (SSI PLL) decouples the positive sequence component of utility voltage and generates a voltage-tracking scheme, the block diagram of which is shown in Fig. 1.14. The SSI PLL method benefits from integrator applications in sinusoidal signal dispatching. The positive and negative sequences of grid voltage are dispatched by filtering the three-phase grid; the reference frame is transformed to the αβ plane and then dq frame outputs are obtained. The generalized integrator methods used in SSI ensure accurate tracking of the sinusoidal reference without any steady-state error, and it is adjusted with a certain frequency. The frequency selective compensation method can be used to eliminate many harmonics related to tuning the tracking frequency. Therefore the SSI PLL can be used to improve THD performance of the controller as compared to others. Only a limited number of research studies on SSI PLL are available in the literature at this writing, but some novel studies on proportional SSI have recently appeared. This control method is aimed at implementation primarily in single-phase applications with few modifications [20, 32, 33]. The proportional SSI PLL controller is tuned based on the fundamental frequency ω and it is operated in the stationary αβ reference frame. Each SSI regulator is adjusted to certain frequencies for harmonic orders represented as k*ω and the positive and negative sequences are considered to be (k  1)*ω and k*ω, respectively [32, 33].

FIG. 1.14 Block diagram of a SSI PLL.

1.4 PLL control methods used in multilevel inverters

1.4.5 Dual second-order generalized integrator (DSOGI) PLL The single-phase applications of PWM-based MLIs require a zero-crossing detector (ZCD) for acquiring the triggering instant of the reference waveform for detecting the phase angle. Although the zero-crossing detection is a convenient and simple method, it may cause failure of the PLL due to disturbances or unbalanced situations in the utility grid. In order to overcome the fault potential of simple ZCD methods, second-order generalized integrator (SOGI) PLL methods have been proposed [34–36]. SOGI is designed to generate orthogonal signals representing the sample of the acquired input waveform in terms of magnitude and decreased harmonic orders for detecting the phase angle and frequency of measurement. The analytical structure of SOGI is very simple and provides a rapid dynamic response. The phasedetection section of the PLL generates an orthonormal signal and applies an inverse Park transform, while the filtering section is generated by a PI regulator as a low-pass filter, and a phase angle integrator is used as the VCO section. The block diagram of a dual SOGI PLL (DSOGI-PLL) is presented in Fig. 1.15, where PLL operation is performed in four steps: Clarke transformation, SOGI-based quadrature signal generator (SOGI-QSG), positive and negative sequence calculator, and SRF-PLL for each positive and negative sequences. The orthogonal signals acquired from the input measurement are decoupled as vα and vβ using two SGs that are generated by the SOGI control block in the DSOGI-PLL. The detailed block diagram of the SOGI-based QSG is shown in Fig. 1.16, where the nominal value of grid frequency is depicted by ωf, used as the feed-forward control variable in the SOGI QSG. The transfer function of SOGI is defined as given in Eq. (1.9), while the closed loop transfer functions are given in Eqs. (1.21, 1.23). HSOGI ðsÞ ¼ Hd ðsÞ ¼

FIG. 1.15 Block diagram of DSOGI-PLL.

ωf s s2 + ω2f

kωf s V’ ðsÞ ¼ 2 v s + kωf s + ω2f

(1.21)

(1.22)

21

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CHAPTER 1 Pulse width modulation and control methods

FIG. 1.16 Block diagram of SOGI-based QSG.

FIG. 1.17 Detailed diagram of sequence calculator block.

Hq ðsÞ ¼

kω2f qv ðsÞ ¼ 2 v s + kωf s + ω2f

(1.23)

where k is the effecting coefficient for the bandwidth of the closed-loop system [35]. The tuning of the SOGI PLL is dependent on frequency variations and it can cause disturbances if the utility voltage fluctuates. Therefore it requires adaptive tuning corresponding to the resonance frequency, which is tuned by using the frequency provided by the PLL algorithm. The quadrature signal pairs shown in Fig. 1.17 are applied to the sequence calculator block. The generated positive and negative output signals are used for generating the rotating reference frame parameters, and then applied to the SRF-PLL [37].

1.4.6 Enhanced PLL The enhanced PLL (EPLL) method is proposed as a much more convenient solution than conventional PLL methods providing only phase lock. The output of EPLL is not only locked to the phase angle of the input waveform, but is also locked to other

1.5 Control structures for grid-connected inverters

parameters such as amplitude and frequency. EPLL generates instant estimations by tracking the phase, amplitude, and frequency of the fundamental input waveform. In addition, EPLL generates a 90-degree shifted sample of the measured input signal, which facilitates estimation of the phase angle of the input parameter. The EPLL proposed in Ref. [38] is made up of the block diagrams of conventional PLL structure with phase detector, loop filter, and VCO sections. The three-phase EPLL block diagram is shown in Fig. 1.18, where each EPLL section includes three independent control parameters, K, KPKV, and KIKV, where the parameter K determines the speed of convergence of amplitude [20, 38]. The proposed method shown in the block diagram decouples the positive sequence components of each line voltage and tracks the phase angle of the separated phase voltage. The parameter KV in the block diagram is used to control the dynamic response of the PLL, and determines the convergence speed of peak value estimation. A low-pass filter connected at the end of the integrator block at each phase and output estimation block improves the response of the VCO and provides smooth estimation of phase angle in disturbed or unbalanced operations of the utility grid [20, 38]. The modified EPLL is proposed as a novel PLL method composed of a DSOGI-PLL and EPLL. In this PLL method, the DSOGI-PLL is used as the positive sequence detector while the EPLL is responsible for phase tracking; the block diagram of the proposed system is seen in Fig. 1.19 [20]. To briefly summarize and compare the PLL methods introduced here, it can be seen that almost all PLL methods are based on dq or αβ reference frame transformations on the input voltage, which enable the controller to neglect the zero sequence components and phase angle tracking is not affected by the DC components of the input measurement. The SSI-PLL is suitable for steady and balanced utility grid conditions, while it is affected under unbalanced grid conditions and dynamic response is lost or settled in longer times. The EPLL and DSOGI PLL algorithms represent a much more robust response in phase-tracking operations due to their complex controllers in the VCO section.

1.5 Control structures for grid-connected inverters The grid connection of inverters is accomplished by phase angle tracking and reference frame control of a PLL-based control strategy. The reference frame control is performed in either a synchronous, stationary, or natural reference frame. The control methods applied to the grid-connected inverter are usually improved by the aid of two cascaded loops. These control loops are defined as the inner and outer control loops, which are respectively responsible for current control and voltage control. The inner loop, which has faster dynamic response compared to the outer one, is used to regulate the grid current, while the outer loop controls the DC-link voltage. The current control ensures the management of power quality-related duties such as harmonic elimination and power control, in addition to current protection. The voltage controller outer loop manages the power flow by compensating the DC-link voltage. The following parts of this section deal with control methods operated in the reference frames described earlier.

23

FIG. 1.18 Block diagram of EPLL.

1.5 Control structures for grid-connected inverters

FIG. 1.19 Block diagram of modified EPLL.

1.5.1 Synchronous reference frame control The synchronous reference frame control, which is also known as dq control, is based on a reference frame transformation module for transforming the current and voltage parameters of the utility grid to a reference frame rotating synchronously. This transformation is obtained by use of the Clarke and Park transformation methods, which convert the abc to αβ and αβ to dq. The result of this transformation is the generation of DC components of measured parameters, and filtering and control processes are easily accomplished. A block diagram of dq transformation-based control is shown in Fig. 1.20. In the represented control infrastructure, the DC-link voltage is controlled based on the required output power level. The output generates control commands for the active current that manages active power, and it allows the reactive power coefficient to be set to zero if requested. If reactive power control is also desired in this system, the reactive power reference Q∗ should be imposed on the

FIG. 1.20 Block diagram of synchronous reference frame control.

25

26

CHAPTER 1 Pulse width modulation and control methods

controller architecture. If the reactive power has to be controlled, a reactive power reference must be imposed on the system. The dq control structure is made up of PI controllers, due to their satisfactory reaction for regulating the DC parameters. The transfer function of a PI-based controller in dq coordinates is presented as: 2

6 ðdqÞ GPI ðsÞ ¼ 4

Kp + 0

Ki s

3

0

7 Ki 5 Kp + s

(1.24)

where Kp is the proportional gain and Ki is the integral gain of the controller [28]. The phase angle of grid voltage should be decoupled by using an abc to dq transformation for ensuring that the controlled current is in phase with the grid voltage. Therefore some methods such as filtering the grid voltage and using arctan functions for decoupling the phase angle have been proposed in the literature. However, PLL is a standard application for acquiring the phase angle of utility voltage [28, 39, 40].

1.5.2 Stationary reference frame control The literature survey on reference frame control has addressed the issue that synchronous reference frame control suffers reliability problems due to the conventional PI controller. Moreover, the dq transformation causes complex coupling terms in three-phase systems. Even if certain control strategies have been developed in dq synchronous reference frames, they require an accurate model based on the PI controller. The alternative control method proposed to overcome these complexities of synchronous reference frames is stationary frame control, which is based on a proportional-resonant (PR) controller instead of the conventional PI in dq control. The PR controller in the αβ stationary frame is equivalent to a PI controller in the dq synchronous frame. A block diagram of a stationary reference frame controller based on a dq to αβ transformation and PR controller is seen in Fig. 1.21 [28, 32, 41, 42].

FIG. 1.21 Block diagram of stationary reference frame control.

1.5 Control structures for grid-connected inverters

The analytical representation of the PR transfer function in stationary reference frame control is given by 2

3 Ki s + 0 K p 6 7 ðαβÞ s2 + ω2 GPR ðsÞ ¼ 4 Ki s 5 0 Kp + 2 s + ω2

(1.25)

where ω is the resonance frequency of the controller, Kp is the proportional gain, and Ki is the integral gain of the controller [28].

1.5.3 Natural frame control The natural frame control based on an abc frame requires independent current control for each phase of the utility grid. In this case, two current measurements will be enough in three-phase systems, since the third-phase current is determined by Kirchoff’s current law. The independent controllers in two or three measurement cases were improved by using hysteresis and dead-beat controllers, as presented in the literature [28]. A block diagram of a widely used natural frame controller is shown in Fig. 1.22, where the DC-bus voltage is used to generate the active current reference in the d-axis. The phase voltages are obtained from a PLL controller where the phase angle is obtained and each phase current value is generated for comparison to the dq-abc transformation. The dq frame is first transformed to an αβ stationary frame by using an inverse Park transformation and then to the abc natural reference frame by an inverse Clarke transformation, as seen in the figure. If the current controller is made up of hysteresis and dead-beat controllers, the requirement for the PWM modulator is removed, and switching signals are generated by the current controller block. This generation can also be performed by PI or PR controllers driving a regular PWM, or any other modulator, for generating the switching orders. Although the PI controller is a widely used synchronous reference frame for dq control, it is possible to adapt it to a natural abc frame. The transfer function of a natural reference frame PI controller is represented in Eq. (1.26) for a three-phase system [28]. pffiffiffi pffiffiffi 3 Ki s Kp Ki s + 3Ki ω0 Kp Ki s  3Ki ω0



     Kp + 2 6 2 2 2 s + ω0 2  s2 + ω20 2  s2 + ω20 7 6 7 6 7 pffiffiffi 6 K K s  pffiffi3ffiK ω 7 2 K s K K s + 3 K ω 6 p i i 0 i p i i 07 abc



 GPI ðsÞ ¼  6   +   K 7 (1.26) p 3 6 2 2 s2 + ω20 2  s2 + ω20 2  s2 + ω20 7 6 7 pffiffiffi pffiffiffi 6 7 4 Kp Ki s + 3Ki ω0 5 Kp Ki s  3Ki ω0 Ki s



     K + p 2 2 2 2 2 2 2 2 s + ω0 2  s + ω0 2  s + ω0 2

The PR controller introduced in the αβ stationary reference frame can also be adapted to a natural abc frame by using the transfer function presented in Eq. (1.27) for a three-phase system [28].

27

FIG. 1.22 Block diagram of natural reference frame control.

1.5 Control structures for grid-connected inverters

pffiffiffi pffiffiffi 3 Ki s Kp Ki s + 3Ki ω0 Kp Ki s  3Ki ω0



     6 2 2 s2 + ω20 2  s2 + ω20 2  s2 + ω20 7 7 6 7 6 pffiffiffi pffiffiffi 7 6 6 2 3Ki ω0 Ki s Kp Ki s + 3Ki ω0 7 7 (1.27) 6  Kp  Ki s 



  Gabc ð s Þ ¼ +   K p PI 3 6 2 s2 + ω20 2  s2 + ω20 2  s2 + ω20 7 7 6 2 7 6 pffiffiffi pffiffiffi 7 6 5 4 Kp Ki s + 3Ki ω0 Kp Ki s  3Ki ω0 Ki s



   +   K p 2 2 s2 + ω20 2  s2 + ω20 2  s2 + ω20 2

Kp +

The hysteresis band controller can be implemented as an alternative to a PI or PR controller depending on the transfer function, given by Eq. (1.28), where an adaptive band is required to be determined for the fixed switching operation. However, the hysteresis band controller generates the switching signals and isolated neutral point use is also required, as in PI and PR controllers. The a0 parameter is defined in the equation of the hysteresis band (HB), seen in Eq. (1.28) for the load connection type in [43]: "   # Vg di∗ 2 0:25a0 Vdc L2T HB ¼ 1 2 + fsw LT a0 Vdc LT dt

(1.28)

where LT denotes the load inductance, fsw is the switching frequency, and Vg is the grid voltage. The dead-beat controller, which can be used as an alternative to the HB controller, forces the system to generate zero error. The transfer function of the controller in its digital implementation is given by [28]: 1 1  az1 ðabcÞ GDB ¼  b 1  z1

(1.29)

where a and b are represented as follows: a¼e b¼

R  L T Ts T

 R  1  T Ts e LT  1 RT

(1.30) (1.31)

The dead-beat controller is operated with one sample delay since it regulates the current when it reaches the reference value at the end of each switching period. An observer is required for regulating the delay time, as shown in Fig. 1.23, where the current reference modifies the reference for regulating the delay time at each switching period [28].

FIG. 1.23 Block diagram of the dead-beat controller.

29

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CHAPTER 1 Pulse width modulation and control methods

The transfer function of the observer is presented in Eq. (1.32) in discrete form as ðabcÞ

FDB ¼

1 1  z1

(1.32)

which forces the next current reference to be as shown in Eq. (1.33): 0

ðabcÞ

i∗ ¼ FDB ði∗  iÞ

(1.33)

The regulated output of the dead-beat controller provides a rapid controller dynamic with simple controller infrastructure. The frame-based controllers should be evaluated according to their complexity, reliability, and dynamic response rates. The synchronous reference frame controllers lack simplicity due to their cross-coupling parameters and voltage feedforward requirements, in addition to phase angle generation. On the other hand, PI-based control may cause instability under unbalanced grid conditions. The stationary reference frame controller improved by using PR controllers benefits from current regulation, and it provides lower complexity compared to synchronous reference frame controllers. Moreover, the phase angle detection may not be required, since the filtered utility voltage can be sufficient for generating the reference current. The last reference frame controller, based on the natural frame, can be the most complex controller if the hysteresis band is used in the current regulation stage. The dead-beat controllers decrease the complexity of the natural frame controller, where each phase requires an individual controller for achieving the current reference generation.

References [1] I. Colak, E. Kabalci, R. Bayindir, Review of multilevel voltage source inverter topologies and control schemes, Energy Convers. Manag. 52 (2011) 1114–1128. https://doi.org/ 10.1016/j.enconman.2010.09.006. [2] N.S. Hasan, N. Rosmin, D.A.A. Osman, A.H. Musta’amal@Jamal, Reviews on multilevel converter and modulation techniques, Renew. Sust. Energ. Rev. 80 (2017) 163–174. https://doi.org/10.1016/j.rser.2017.05.163. [3] N. Prabaharan, K. Palanisamy, A comprehensive review on reduced switch multilevel inverter topologies, modulation techniques and applications, Renew. Sust. Energ. Rev. 76 (2017) 1248–1282. https://doi.org/10.1016/j.rser.2017.03.121. [4] J.G. Proakis, M. Salehi, Fundamentals of Communication Systems, Pearson Education India, 2007. [5] L.W. Couch, Digital & Analog Communication Systems, Pearson Higher Ed, 2012. [6] F. Louis, Principles of Electronic Communication Systems, McGraw-Hill, Boston, 2008. [7] D.G. Holmes, T.A. Lipo, Pulse Width Modulation for Power Converters: Principles and Practice, John Wiley & Sons, 2003. [8] S.K. Peddapelli, Pulse Width Modulation: Analysis and Performance in Multilevel Inverters, Walter de Gruyter GmbH & Co KG, 2016. [9] A. Sinha, K. Chandra Jana, M. Kumar Das, An inclusive review on different multi-level inverter topologies, their modulation and control strategies for a grid connected photovoltaic system, Sol. Energy 170 (2018) 633–657. https://doi.org/10.1016/j.solener.2018. 06.001.

References

[10] M. Barghi Latran, A. Teke, Investigation of multilevel multifunctional grid connected inverter topologies and control strategies used in photovoltaic systems, Renew. Sust. Energ. Rev. 42 (2015) 361–376. https://doi.org/10.1016/j.rser.2014.10.030. [11] M.S.A. Dahidah, V.G. Agelidis, Selective harmonic elimination PWM control for cascaded multilevel voltage source converters: a generalized formula, IEEE Trans. Power Electron. 23 (2008) 1620–1630. https://doi.org/10.1109/TPEL.2008.925179. [12] T. Sudhakar Babu, K. Priya, D. Maheswaran, K. Sathish Kumar, N. Rajasekar, Selective voltage harmonic elimination in PWM inverter using bacterial foraging algorithm, Swarm Evol. Comput. 20 (2015) 74–81. https://doi.org/10.1016/j.swevo.2014.11.002. [13] I. Ahmed, V.B. Borghate, Simplified space vector modulation technique for seven-level cascaded H-bridge inverter, IET Power Electron. 7 (2014) 604–613. https://doi.org/ 10.1049/iet-pel.2013.0135. [14] T. Lahlou, V.I. Muresan, I. Bolvashenkov, H.G. Herzog, Space vector modulation for 17-level cascaded H-bridge inverter for use in battery energy storage systems, in: 2018 Thirteenth International Conference on Ecological Vehicles and Renewable Energies (EVER), 2018, pp. 1–6. https://doi.org/10.1109/EVER.2018.8362379. [15] A.M. Massoud, S.J. Finney, B.W. Williams, Mapped hybrid spaced vector modulation for multilevel cascaded-type voltage source inverters, IET Power Electron. 1 (2008) 318–335. https://doi.org/10.1049/iet-pel:20070409. [16] A. Rahman, M. Rahman, M.R. Islam, A study of THD minimization of three phase inverter using modified THPWM, in: 2017 3rd International Conference on Electrical Information and Communication Technology (EICT), 2017, pp. 1–4. https://doi.org/ 10.1109/EICT.2017.8275225. [17] I. Colak, R. Bayindir, E. Kabalci, A modified harmonic mitigation analysis using Third Harmonic Injection PWM in a multilevel inverter control, in: Proceedings of 14th International Power Electronics and Motion Control Conference EPE-PEMC 2010, 2010, pp. T2-215–T2-220. https://doi.org/10.1109/EPEPEMC.2010.5606607. [18] M.E. Tamasas, M. Saleh, M. Shaker, A. Hammoda, Comparison of different third harmonic injected PWM strategies for 5-level diode clamped inverter, in: 2017 IEEE Power and Energy Conference at Illinois (PECI), 2017, pp. 1–6. https://doi.org/10.1109/PECI. 2017.7935718. [19] M.F. Yaakub, S.H. Mohamad, S. Ahmad, A.Z. Jidin, F.H.M. Noh, N.A. Azlan, Simulation of three-phase cascaded H-bridge multilevel inverter with THIPWM, in: 2016 IEEE International Conference on Power and Energy (PECon), 2016, pp. 484–488. https://doi. org/10.1109/PECON.2016.7951610. [20] V. Khatana, R. Bhimasingu, Review on three-phase PLLs for grid integration of renewable energy sources, in: 2017 14th IEEE India Council International Conference (INDICON), 2017, pp. 1–6. https://doi.org/10.1109/INDICON.2017.8488071. [21] F. Sevilmis¸ , H. Karaca, Performance analysis of SRF-PLL and DDSRF-PLL algorithms for grid interactive inverters, Int. Adv. Res. Eng. J. 3 (2019) 116–122. https://doi.org/10. 35860/iarej.412250. [22] A. Timbus, M. Liserre, R. Teodorescu, F. Blaabjerg, Synchronization methods for three phase distributed power generation systems—an overview and evaluation, in: 2005 IEEE 36th Power Electronics Specialists Conference, 2005, pp. 2474–2481. https://doi.org/ 10.1109/PESC.2005.1581980. [23] F. Iov, M. Ciobotaru, F. Blaabjerg, Power electronics control of wind energy in distributed power systems, in: 2008 11th International Conference on Optimization of Electrical and Electronic Equipment, 2008, pp. XXIX–XLIV. https://doi.org/10.1109/OPTIM. 2008.4602332.

31

32

CHAPTER 1 Pulse width modulation and control methods

[24] F. Sevilmis¸ , H. Karaca, Simulation of three-phase grid interactive inverter for wind energy systems, in: 2015 IEEE 15th International Conference on Environment and Electrical Engineering (EEEIC), 2015, pp. 1169–1174. https://doi.org/10.1109/EEEIC.2015. 7165333. [25] A. Nagliero, R.A. Mastromauro, M. Liserre, A. Dell’Aquila, Synchronization techniques for grid connected wind turbines, in: 2009 35th Annual Conference of IEEE Industrial Electronics, 2009, pp. 4606–4613. https://doi.org/10.1109/IECON.2009.5414859. [26] F. Xiong, W. Yue, L. Ming, W. Ke, L. Wanjun, A novel PLL for grid synchronization of power electronic converters in unbalanced and variable-frequency environment, in: The 2nd International Symposium on Power Electronics for Distributed Generation Systems, 2010, pp. 466–471. https://doi.org/10.1109/PEDG.2010.5545832. [27] B. Meersman, J. De Kooning, T. Vandoorn, L. Degroote, B. Renders, L. Vandevelde, Overview of PLL methods for distributed generation units, in: 45th International Universities Power Engineering Conference UPEC2010, 2010, pp. 1–6. [28] F. Blaabjerg, R. Teodorescu, M. Liserre, A.V. Timbus, Overview of control and grid synchronization for distributed power generation systems, IEEE Trans. Ind. Electron. 53 (2006) 1398–1409. https://doi.org/10.1109/TIE.2006.881997. [29] R. Amin, S.A. Zulkifli, A framework for selection of grid-inverter synchronisation unit: harmonics, phase-angle and frequency, Renew. Sust. Energ. Rev. 78 (2017) 210–219. https://doi.org/10.1016/j.rser.2017.04.074. [30] L. Hadjidemetriou, E. Kyriakides, F. Blaabjerg, A new hybrid PLL for interconnecting renewable energy systems to the grid, IEEE Trans. Ind. Appl. 49 (2013) 2709–2719. https://doi.org/10.1109/TIA.2013.2265252. [31] Z. Ali, N. Christofides, L. Hadjidemetriou, E. Kyriakides, Y. Yang, F. Blaabjerg, Threephase phase-locked loop synchronization algorithms for grid-connected renewable energy systems: a review, Renew. Sust. Energ. Rev. 90 (2018) 434–452. https://doi. org/10.1016/j.rser.2018.03.086. [32] Y. Xiaoming, W. Merk, H. Stemmler, J. Allmeling, Stationary-frame generalized integrators for current control of active power filters with zero steady-state error for current harmonics of concern under unbalanced and distorted operating conditions, IEEE Trans. Ind. Appl. 38 (2002) 523–532. https://doi.org/10.1109/28.993175. [33] R.I. Bojoi, G. Griva, V. Bostan, M. Guerriero, F. Farina, F. Profumo, Current control strategy for power conditioners using sinusoidal signal integrators in synchronous reference frame, IEEE Trans. Power Electron. 20 (2005) 1402–1412. https://doi.org/10.1109/ TPEL.2005.857558. [34] L. Pan, C. Zhang, Phase-locked loop based second order generalized integrator for electric vehicle single-phase charger, Energy Procedia 105 (2017) 4021–4026. https://doi. org/10.1016/j.egypro.2017.03.848. [35] M. Ciobotaru, R. Teodorescu, F. Blaabjerg, A new single-phase PLL structure based on second order generalized integrator, in: 37th IEEE Power Electronics Specialists Conference, IEEE, Jeju, Korea, 2006, pp. 1–6. https://doi.org/10.1109/PESC.2006.1711988. [36] A. Nicastri, A. Nagliero, Comparison and evaluation of the PLL techniques for the design of the grid-connected inverter systems, in: 2010 IEEE International Symposium on Industrial Electronics, IEEE, Bari, Italy, 2010, pp. 3865–3870. https://doi.org/10. 1109/ISIE.2010.5637778. [37] I. Setiawan, M. Facta, A. Priyadi, M.H. Purnomo, Comparison of three popular PLL schemes under balanced and unbalanced grid voltage conditions, in: 2016 8th International Conference on Information Technology and Electrical Engineering (ICITEE), 2016, pp. 1–6. https://doi.org/10.1109/ICITEED.2016.7863282.

References

[38] M. Karimi-Ghartemani, M.R. Iravani, A method for synchronization of power electronic converters in polluted and variable-frequency environments, IEEE Trans. Power Syst. 19 (2004) 1263–1270. https://doi.org/10.1109/TPWRS.2004.831280. [39] Y. Guan, J.M. Guerrero, X. Zhao, J.C. Vasquez, X. Guo, A new way of controlling parallel-connected inverters by using synchronous-reference-frame virtual impedance loop—part I: control principle, IEEE Trans. Power Electron. 31 (2016) 4576–4593. https://doi.org/10.1109/TPEL.2015.2472279. [40] Y. Han, X. Fang, P. Yang, C. Wang, L. Xu, J.M. Guerrero, Stability analysis of digitalcontrolled single-phase inverter with synchronous reference frame voltage control, IEEE Trans. Power Electron. 33 (2018) 6333–6350. https://doi.org/10.1109/TPEL.2017. 2746743. [41] C. Zou, B. Liu, S. Duan, R. Li, Stationary frame equivalent model of proportionalintegral controller in dq synchronous frame, IEEE Trans. Power Electron. 29 (2014) 4461–4465. https://doi.org/10.1109/TPEL.2013.2296789. [42] D.N. Zmood, D.G. Holmes, Stationary frame current regulation of PWM inverters with zero steady-state error, IEEE Trans. Power Electron. 18 (2003) 814–822. https://doi.org/ 10.1109/TPEL.2003.810852. [43] B.K. Bose, An adaptive hysteresis-band current control technique of a voltage-fed PWM inverter for machine drive system, IEEE Trans. Ind. Electron. 37 (1990) 402–408. https:// doi.org/10.1109/41.103436.

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CHAPTER

Hysteresis control methods

2

Oswaldo Lopez-Santosa, Diego S. Dantonioa, Freddy Flores-Bahamondeb, and Carlos A. Torres-Pinzo´nc a

Program of Electronics Engineering, Universidad de Ibagu e, Ibagu e, Colombia bDepartment of Engineering Sciences, Universidad Andres Bello, Santiago, Chile cFaculty of Electronic Engineering, Universidad Santo Toma´s, Bogota´, Colombia

2.1 Introduction The new energy scenario has been pushing permanent advances in power electronic converters and control. Academia and industry have both played fundamental roles in developing and integrating power systems for low-, medium-, and high-power applications with high efficiency and reliability. In fact, due to the high penetration of different energy sources and loads (solar, wind energy, energy storage systems, and electric vehicles), a more flexible and dynamic energy matrix has been formed, evolving toward more modular, efficient, and distributed architectures [1]. This is the case of multilevel convereters (MCs), which have emerged in the last years over the classic converters as an interesting solution in high-power applications [2–7]. Currently, MCs are used in many applications, such as solar and wind energy, railway traction, storage technologies (battery, hydropumped), high-voltage direct-current (HVDC) transmission, reactive power compensation, and electromobility, just to name a few [5, 7–15]. Compared to conventional two-level topologies, multilevel converters present different advantages, making them more suitable for high- and medium-power solutions. Among these advantages are better output signal quality, reduced total harmonic distortion (THD), low dV/dt, smaller input and output filters (if needed), higher efficiency, lower common voltages, lower cost, reduced voltage stress in power semiconductors, as well as modularity and scalability. In addition to their proven qualities, important research efforts are focused on improving their efficiency, power density, and cost [2, 7, 8]. In fact, recent advances have been motivated to increase the power density by working with higher frequencies and reaching smaller power units [16–18]. With respect to the control, during the last few decades several techniques have been researched and developed in order to obtain an accurate sinusoidal output voltage waveform in multilevel inverters. As illustrated in Fig. 2.1, the different Multilevel Inverters. https://doi.org/10.1016/B978-0-323-90217-5.00002-2 Copyright # 2021 Elsevier Inc. All rights reserved.

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CHAPTER 2 Hysteresis control methods

FIG. 2.1 Classification of control methods for multilevel inverters.

approaches can be classified according to two main features: (a) switching frequency, which can be fundamental frequency or high frequency; and (b) control type, which can use one or more closed loops or none [19, 20]. Based on the switching frequency, techniques differentiate fundamental switching frequency and high-frequency modulations. In both cases, it is possible to find the well-known space vector (SVM), sinusoidal PWM (SPWM), and space vector PWM (SV-PWM) modulations. Conversely, the optimized harmonic stepped-wave selective harmonic elimination is limited to fundamental frequency modulation. According to the control technique they use, multilevel inverters can integrate an open-loop scheme using SPWM, SV-PWM, and sigma-delta PWM, in the three cases producing the output signal with off-line computed references. Also, they can use linear and nonlinear closed-loop techniques such as proportional-integral (PI) or proportional-resonant (PR) compensators [21–23], and strategies such as fuzzy logic [24, 25], sliding mode [26], passivitybased [27], and predictive [28]. Although all these techniques present good performance, the more commonly adopted control techniques by industry are SPWM and SVM, because they provide low THD, easy deployment, and robustness [19]. The hysteresis control methods are also widely used in applications of both gridtie and stand-alone inverters. The basic concept of HC is to switch the output voltage level (for more than two level cases) appropriately if the measured current or voltage goes above or below a given hysteresis band. Implementation of this control technique is simple, since it requires only comparators, as shown in Fig. 2.2 for threephase systems. HC has been commonly used in conventional two-level converters showing a high effectiveness, ensuring high power quality in different applications [29, 30].

2.1 Introduction

FIG. 2.2 Three-phase systems involving HC: (A) grid-connected (HCC); and (B) stand-alone (HVC).

Besides, it has the advantage of reaching good regulation and robustness for the output current and voltage. The proper selection of a suitable hysteresis band is the most important issue in the effectiveness of the control. The key features to take into account are related to the maximum desirable switching frequency for the converter and the maximum THD of the output voltage or current. However, classical hysteresis control is based on a constant hysteresis band resulting in switching frequency variation over the fundamental inverter period. Thus the behavior obtained by means of a good selection of hysteresis band has a direct influence on filter design, semiconductor selection, current ripple, and AC voltage variation. Note that other critical issues have to be considered when applying HCC to three-phase inverters, such as the coupling between phase currents induced by the effect of interferences between the switching voltages among phases (usually in three-phase systems without a neutral point). Consequently, to minimize this problem several authors have proposed decoupling hysteresis approaches or just addressing a small dead zone between the hysteresis bands. To illustrate the operating principle of HC techniques, Fig. 2.3 depicts the nonlinear hysteresis function of a generic system, where h defines the limits of the hysteresis band, and δ represents a small dead zone inserted to avoid overlapping between neighboring loops.

37

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CHAPTER 2 Hysteresis control methods

FIG. 2.3 Three-level hysteresis function.

Although HC is a very simple technique with high robustness compared with other techniques, its application in multilevel inverters requires the use of an additional logic operator due to the larger number of voltage levels, which is commonly called the multilevel hysteresis modulator (MHM). The MHM is in charge of selecting the voltage level at any time and correlates the corresponding level with a specific hysteresis band in order to minimize the error. A summarized classification of hysteresis-based controllers is presented in Fig. 2.4.

FIG. 2.4 Classification of HCCs for multilevel inverters.

2.2 MB hysteresis current control

This chapter explains the three most-used HCC methods, which are time-based (TB), multiband (MB), and multioffset-band (MOB), as well as adaptive hysteresis. Complementarily, the multiband (MB) HVC is briefly described, together with a hysteresis voltage regulation technique (HVR), both relating to stand-alone applications.

2.2 MB hysteresis current control The multiband (MB) HCC is one of the most applied techniques in multilevel inverters due to its simplicity and good performance compared to other hysteresis methods [31–34]. The MB-HCC uses more than one constant hysteresis band, related to the number of voltage levels of the system. The switching commands or the selection of each band is based on the evolution of the current error. With the aim of understanding its operation, a cascade multilevel inverter approach is analyzed [34, 35]. It is well known that, based on the approximation (n
1)/2, it is possible to define the number of output voltage levels. Therefore, for a three-level inverter case, only one H-bridge inverter is needed, as shown in Fig. 2.5. As can be observed in Fig. 2.6, the result of this control is a three-level output voltage defined with the levels +Vdc, 0 and
Vdc. Based on its principle, to achieve current control, several bands are associated with the current reference, where the load current has to be inside the inner or principal band. For this case, two hysteresis bands B1 and B2 are defined. Thus the inner hysteresis band sets the switching operation between the adjacent voltage levels and the outer limit band B1 establishes the switching action to the additional voltage levels. The switch is commanded by the current error ei, in such a way that if the error current is into the inner band, the output voltage will remain between +Vdc and zero. When the current error crosses the lower or higher limits of the inner band, the output voltage level will change to a higher or

FIG. 2.5 Basic block diagram of a current controller for an inverter-controlled system using three-level hysteresis modulation.

39

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CHAPTER 2 Hysteresis control methods

FIG. 2.6 Waveforms describing operation of MB HCC technique.

lower voltage level (between
Vdc and zero). Hence, the system switches to the other level available in order to conduct the error current toward zero. Note that, for inverters producing a high number of levels, if the new selected level does not minimize the error ei, a new next lower or higher voltage level should be selected. Consequently, the process will remain the same until achieving a zero-current error. Finally, the width of the hysteresis band depends on maximum THD, load current value, input voltage, and desired switching frequency [36].

2.3 MOB hysteresis current control Conversely to the MB technique, in the MOB approach the hysteresis band is set with an offset causing an overlapping between them, as shown in Fig. 2.7. In the same manner as the previous method, the hysteresis bands are over the zero current error line. Thus fixed voltage levels are applied in such a way that the error current goes through the limit of the band with a slope. This technique is also commonly applied in cascade multilevel configurations, because a wide number of voltage levels can be covered. In Fig. 2.7, a MOB MHM example for a three-level inverter is depicted. The figure shows how the voltage levels are switched right after the current error ei exceeds the limits of the hysteresis bands B1 and B2. The switching pattern is changed when the sign of the current error and its respective slope is the same over the higher or lower limits, i.e., positive error and positive slope in t1, and negative error and negative slope in t2. In addition, note that the zero-voltage level is switched at the lower limit of B1 and B2,
V2dc in the higher limit of B1, and + V2dc at the lower limit of B2.

2.3 MOB hysteresis current control

FIG. 2.7 Waveforms describing operation of MOB hysteresis.

Another case important to analyze is the use of the MOB hysteresis applied to cascade multilevel inverters. In this type of structure, the bands are related to each inverter, as illustrated in Fig. 2.8, where bands B1 and B2 are employed to control the first inverter, while B3 and B4 are used to control the second inverter [37, 38]. The operating principle is the following: For the first inverter, the band B1 is used to switch the output voltage between + Vdc and zero, and the band B2 is employed to switch the output voltage between
Vdc and zero. Similarly, for the second inverter the band B3 is used to switch the output voltage between + Vdc and zero, and the band B4 is employed to switch the output voltage between
Vdc and zero. The advantage of the MOB technique compared to the MB technique is basically a simplification of the MB technique implementation. However, although [39] describes the good performance of this technique for a three-level inverter, some operational drawbacks result in a poor-quality voltage waveform if the same controller is applied to a converter with a higher number of levels [40]. The problem occurs when the current error is not minimized by the voltage level, resulting in an increased error away from the zero line. This operation is repeated in the subsequent switching cycles, degrading the voltage waveform. To overcome the drawbacks of conventional MOB modulation, a modified MOB (MMOB) strategy is proposed in Refs. [34, 35], where instead of a fixed hysteresis band, two smaller offsets are used, providing a reliable and robust control. Basically, the conventional MOB techniques require n
1 offset bands for an n
level inverter, while the MMOB technique applies n
2 offsets for an n
level inverter in both positive and negative current error regions.

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CHAPTER 2 Hysteresis control methods

FIG. 2.8 Waveforms describing operation of MOB hysteresis.

2.4 TB hysteresis current control Different from the previous modulation techniques, time-based modulation uses only one hysteresis band to detect when the current error is out of the limits [31]. Once the error exceeds one of the limits, a state machine programmed in a digital controller switches the inverter to a lower or higher voltage level until the correct switching state is reached to reverse the error back to zero. For a better understanding of the control, Fig. 2.9 illustrates the modulation scheme of the TB MHM. It is possible to observe that only one hysteresis band is used, B2. Thus the output voltage of the inverter switches initially between +Vdc and zero where the current error ei is forced toward zero at any time. Once the system is not able to return the error to zero, ei crosses the upper limit of the hysteresis band, provoking the state machine to switch to another voltage level. In the case of a three-level inverter, this next level selected is between
Vdc and zero. The TB MHM presents a good tracking performance without a DC tracking error problem. However, this method has more complexity in its deployment, primarily the need for very fast switching devices to respond to the TB requirements. Different improvements have been proposed in order to add robustness to this technique, such as a current error slope detection algorithm to switch the voltage levels in Ref. [39], or an outer band placed to obtain better performance for extreme voltage levels or high-level inverters for rapid current error reduction during

2.5 MB hysteresis voltage control

FIG. 2.9 Waveforms describing operation of TB multilevel hysteresis modulation.

transient conditions [41]. In addition, in the same way as for MOB modulation, an efficient modified TB MH control is proposed in Ref. [40]. This modification implies two new issues, the n
2 outer bands for n
level inverters and the replacement of the current error detection algorithm with one that only detects the sign of the error slope [34, 35]. Although good performance is achieved in all the previously reviewed HCC techniques, the research community is still working to infer expressions as a function of the switching frequency, due to its different constraints in the design process [42–44]. In this sense of trying to optimize the switching frequency, techniques involving a variable amplitude of the hysteresis band have been proposed in Refs. [45–47]. These techniques adapt the amplitude of the hysteresis band according to the variation of the system parameters, and consequently a regulated switching frequency is obtained. In Ref. [45] an adaptive hysteresis band technique is used in the current regulation of an active shunt filter, where the hysteresis bandwidth is modified according to the modulation frequency, the input DC voltage, and the current error slope. Also, in Ref. [46], the authors present a hybrid fuzzy adaptive hysteresis for an active power filter, giving more stability and robustness to the system.

2.5 MB hysteresis voltage control Multiband hysteresis voltage control was proposed by Gupta and Ghosh in 2008 applied to a cascade multilevel inverter topology as an implementation technique for a sliding mode-based controller [33]. Subsequent works published in 2010 and

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FIG. 2.10 Multiband hysteresis voltage function.

2012 provided a better characterization of the method, giving more basis for understanding the method, its design, and implementation [43, 44]. In these works, the control of the inverter was accomplished using a feedback loop measuring the output voltage and using the same principle as the MB hysteresis current control presented earlier. The selected sliding surface is a linear combination of the voltage error and its derivative. What is interesting in these works is the hierarchical switching scheme proposed by the authors, allowing that only one of the stages of the inverter commutates into its corresponding hysteresis band, contributing to reducing the switching losses and reducing the switching stress in the semiconductors. Fig. 2.10 depicts the MB hysteresis function used for HVC as an implementation of the sliding mode control technique. The case depicted in the figure provides a fivelevel modulation, which corresponds to a two-stage cascade multilevel inverter.

2.6 Hysteresis voltage regulation For many years, tap-changing regulators have been used to stabilize the voltage of several applications into permissible levels, despite undervoltages and overvoltages [48]. Fig. 2.11 shows two different topologies of tap-changing voltage regulators: Fig. 2.11A corresponds to the single-transformer configuration, which is an effective cost solution for low-voltage applications (only one auto-transformer is required),

2.6 Hysteresis voltage regulation

FIG. 2.11 Topologies of tap-changing regulators: (A) single transformer topology; and (B) double transformer topology.

while Fig. 2.11B corresponds to a double-transformer configuration, which allows increased levels of power and voltage. Because the time constant of the closed loop is one or more times the period of the output signal, the antiparallel configuration of thyristors is enough to provide the required bidirectional AC power flow capability of the switches. Naturally, the use of better-performing semiconductors helps to improve the response of the device. The control of tap-changing regulators uses the measurement of either the peak value or the RMS value of the output voltage signal in order to increase or decrease

45

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CHAPTER 2 Hysteresis control methods

FIG. 2.12 Representation of the hysteresis voltage control of the tap-changing regulators as a function of the transformer gain.

the position of the tap selector, and then change the turns relation used in the autotransformer. In the sense of Fig. 2.11A, when the tap corresponding to v4 is selected, the output voltage is higher than that obtained when the tap v1 is selected. The relation of this logic with the output voltage can be represented as shown in Fig. 2.12, where each of the lines with a positive slope corresponds to a tap of the autotransformer and the horizontal lines define the two limits of the hysteresis band. This method enforces the peak value or the RMS value to stay between vmax and vmin. As can be inferred, a safe design process implies the definition of some inner hysteresis bands defining the crossing point of the lines with the hysteresis limits: the input voltage corresponding to the crossing point of a line with the upper limit (vmax) must be higher than the crossing point of the following line with the lower limit (vmin). This condition avoids improper commutations, similar to that occurring in the MB HCC technique. The same principle can be employed to control the output voltage of multilevel inverters by means of the inclusion of a voltage regulation loop, which can change the number of output levels used to build the output signal. Considering that an integer number of levels of equal magnitude are used to produce the output, the higher the number of levels, the higher the amplitude of the signal. Then, when a change is produced in the input voltage (vi) and the output load (Po), the output voltage can come off of the hysteresis band, forcing the inverter to increase or decrease the number of levels. The correspondence of the tap-changing regulation logic with that of the inverter is presented in Fig. 2.13, where the slope of the lines is now defined by consecutive integer numbers a1, a2, …, an, which represent the maximum number of levels of the output signal for each case. The accuracy of the regulation and the range of regulated operation increase according to the number of levels that the signal can provide (for some details and validation of the method, see Ref. [49]).

2.7 Adaptive band low-frequency hysteresis voltage control (AB-LF-HVC)

FIG. 2.13 Representation of the hysteresis voltage regulation in multilevel inverters according to the number of output levels.

2.7 Adaptive band low-frequency hysteresis voltage control (AB-LF-HVC) The use of an adaptive hysteresis band is commonly related to the objective to force a constant switching frequency operation in the inverters. However, in this case, the use of variable hysteresis is proposed to ensure the appropriate tracking of the voltage reference. The method uses the hysteresis comparator to enforce the consecutive increase or decrease of the output levels. Then, the signal is built in two sections, one increasing the levels from the maximum negative level to the maximum positive level, and the other decreasing the levels between the same limits. This section is devoted to presenting a new HVC technique that is illustrated using a 31-level single-phase transformer-based cascade multilevel inverter.

2.7.1 Description of the studied inverter Commercially, the best-known topologies of multilevel inverters are the cascade H-bridge (CHB), the H-bridge neutral point clamped (HNPC), and the modular multilevel converter (MMC) [50, 51]. Among them, the transformer-based cascade architectures provide robustness and low complexity at the expense of the use of low-frequency transformers, which increases their cost, weight, and size. Their disadvantages constrain their development for low-power applications but, on the other hand, their advantages allow them to be widely used for high-power applications [52–56]. The power circuit of cascade multilevel inverters is simpler than in other multilevel topologies, facilitating the control of the H-bridges using conventional PWM strategies. As a result, a good output voltage regulation can be obtained, ensuring a high-quality output waveform for a wide range variation of

47

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CHAPTER 2 Hysteresis control methods

FIG. 2.14 Circuit diagram of the inverter selected as a case study for the proposed control.

the load or the input voltage. An alternative control technique is illustrated here, which can produce a high-quality output voltage without the need for highfrequency modulation. Consider the transformer-based asymmetric cascaded multilevel inverter in Fig. 2.14, which has four stages fed by a single DC source vin. Each stage is composed of a full-bridge converter and a transformer with turns ratio 1 : Nx. The output voltages of bridges are the same input voltage of the transformers, defined as vpx. The secondary sides of the transformers, called vx, are series connected to produce the output voltage vo. The state (on or off) of the switching elements SX1, SX2, SX3 and SX4 defines the switching pattern for each output level. For stage 1, the output of the bridge (which is the same voltage at the primary side of the transformer vp1) is the positive voltage vin when S11 and S14 are on and S12 and S13 are off. Conversely, the output of the same bridge is the negative voltage
vin when S11 and S14 are off and S12 and S13 are on. Also, an output of zero can be produced either when S11 and S12 are off and S13 and S14 are on, or, when S11 and S12 are on and S13 and S14 are off. The output voltage of each full-bridge result is defined by: vpx ¼ vin Swx ðtÞ

(2.1)

where Swx(t)  {
1, 0, 1}, this variable being defined as the instantaneous switching pattern. Then, the secondary side voltage of a transformer is: vx ¼ vpx Nx

(2.2)

2.7 Adaptive band low-frequency hysteresis voltage control (AB-LF-HVC)

In consequence, the output voltage of the inverter is defined by: vo ¼ v1 + v2 + v3 + v4 ¼

4 X vx

(2.3)

0

vo ¼ vin ½N1 Sw1 ðtÞ + N2 Sw2 ðtÞ + N3 Sw3 ðtÞ + N4 Sw4 ðtÞ

From Eq. (2.3), the asymmetric relation of the studied inverter implies that v1 6¼ v2 6¼ v3 6¼ v4, which corresponds to N1vin 6¼ N2vin 6¼ N3vin 6¼ N4vin. Consider then that for a positive value of k, the turns ratios N1 ¼ 6k, N2 ¼ 7k, N3 ¼ 8k, and N4 ¼ 9k produce the asymmetric sequence (6:7:8:9), which is selected as a case study. The possible switching patterns producing M consecutive levels at the output of the inverter are listed in Table 2.1. As can be noted, as main features, the inverter can produce all levels between zero and M and some of these levels can be produced by using until three different switching patterns are obtained. These properties provide uniform power distribution between the four stages of the inverter (for details see Ref. [53]). The design of the turns ratios of the transformers is performed by considering that the nominal output voltage is obtained by a selected value of M. Consider now that the desired voltage at the output of the inverter is: vo ¼ vo
ref ¼ A sinωt

(2.4)

where A is the amplitude and ω ¼ 2πf is the angular frequency of the output signal. Then, k ¼ MvAin and the turns ratios are 

N1, 2, 3, 4 ¼

6A 7A 8A 9A , , , Mvin Mvin Mvin Mvin



(2.5)

Then, from Eq. (2.3), the same output voltage can be obtained from a wide range of input voltages by changing the value of M.

2.7.1.1 Design example The studied multilevel inverter is used to provide an output voltage of 110 V and 60 Hz from a nominal input voltage of 48 Vdc. The inverter is fed by a battery bank that can provide voltages between 42 Vdc when the batteries are in their discharge limit and 56 Vdc during the equalization charge regime. The turns ratios of the transformers are computed for nominal conditions using Eq. (2.5) for M ¼ 15, obtaining: N1, 2, 3, 4 ¼ f1:29635, 1:5124, 1:7284, 1:9445g

Without changing the switching pattern of the inverter, the output voltage will be approximately 96 V for an input voltage of 42 Vdc and 128 V for an input voltage of 56 Vdc. Then, the idea is that by changing the number of levels of the output signal, its RMS voltage can be controlled. For M ¼ 17 and an input voltage of 42 Vdc, the output voltage is 109 V (1% error) and, for M ¼ 13 and an input voltage of 56 Vdc, the output voltage is 111 V (1% error). From this reasoning, the proposed hysteresis control approach is developed.

49

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CHAPTER 2 Hysteresis control methods

Table 2.1 Possible switching patterns of the inverter stages obtaining consecutive output levels. Positive level

Stage 1 (N1 5 6)

Stage 2 (N2 5 7)

Stage 3 (N3 5 8)

Stage 4 (N4 5 9)

0

0 1
1
1 0 0
1 0
1
1 1
1 1 1 1 0 0 1 1 0 1 0 0
1
1 0
1 1 1 1 1 1 0 0 0

0
1 1 1
1 0 0
1 1 0 1
1 1 0 0 1 1
1 0 0
1 1 0 1 1
1 0 1 1 0 1 0 1 1 0

0
1 1 0 1
1 1 0
1 0 0 1
1 1 0 1 0 1
1 1 0
1 0 1 0 1 1 1 0 1
1 0 1 0 1

0 1
1 0 0 1 0 1 1 1
1 1 0
1 0
1 0 0 1 0 1 1 1 0 1 1 1
1 0 0 1 1 0 1 1

1

2

3 4 5 6 7

8

9 10 11 12 13 14 15 16 17

2.7 Adaptive band low-frequency hysteresis voltage control (AB-LF-HVC)

2.7.2 Fundamentals of AB-LF-HVC Consider that the ideal output voltage of the inverter is defined by Eq. (2.4). On the other hand, consider that the real output voltage of the inverter is a multilevel signal built using M discrete levels of equal amplitude K. By comparing these two signals during a period of the nominal frequency (see Fig. 2.15), it can be deduced that level change events appear when the reference signal crosses the multilevel signal in the middle point between the present level and the following level.With this definition, the corresponding angles during the first quarter of a cycle are: θm ¼ sin
1

  2m
1 2M

(2.6)

where m ¼ 1, 2, …M. The angles for the rest of the signal can be easily obtained by symmetry as π
θm for the second quarter of the cycle, π + θm for the third quarter of the cycle, and 2π
θm for the last quarter of the cycle [11]. In other words, the duration of the intervals in which the output voltage signal remains in the same level is defined between two switching events, such as ωt ¼ θM and ωt ¼ θM
1. The angles defining the rest of the signal can be obtained by symmetry. For the example presented in Fig. 2.7, K ¼ 1 and A ¼ M ¼ 4. The multilevel signal is exactly constrained inside a hysteresis band defined by the reference signals: vref + ¼ M sin ωt +

K 2

(2.7)

vref
¼ M sin ωt


K 2

(2.8)

FIG 2.15 Multilevel signal building: reference and hysteresis band envelopes.

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FIG. 2.16 Multilevel signal building and comparison reference.

which can be easily obtained from Eq. (2.8). Then, the control method will consist of producing a change of level in the instant in which the instantaneous output voltage is equal to one of the reference signals (3)–(4). As depicted in Fig. 2.16, the hysteretic behavior is induced by the events in which the output signal reaches a piecewise signal built using Eqs. (2.7 and 2.8) as follows:

vref

8 vref
> > > > > < vref + ¼ > > > > > : vref


0  ωt < π=2 π  ωt < 3π=2 2

(2.9)

3π  ωt < 2π 2

Consider now that input voltage and output load can vary over a wide range. Then, the values of M and K must adapt automatically to face a defined range of operating conditions. Fig. 2.17 gives an example of this property, considering that the output signal starts a cycle having M ¼ 4 and K ¼ 1 and remains so until the zero crossing point dividing the positive and negative half-cycles (Condition 2.1). Once this zero crossing point is reached, the signal is produced using M ¼ 8 and K ¼ 1/2 (Condition 2.2). This result complements the example given in the previous section and explains why the hysteresis band must be adapted in the face of a change in the number of levels in the output signal.

2.7 Adaptive band low-frequency hysteresis voltage control (AB-LF-HVC)

FIG. 2.17 Multilevel signal building by considering a change in the number of levels from the positive half-cycle to the negative one.

2.7.3 Adaptive hysteresis control implementation Consider that a sinusoidal voltage reference is compared with the output signal of the inverter, obtaining a voltage error as follows: ev ¼ vref ðωtÞ
vo ðωtÞ

(2.10)

The voltage error signal can then be represented simultaneously with the hysteresis band limits, as depicted in Fig. 2.18. As can be noted, for this example a signal of normalized amplitude is built with one cycle using 9 levels and the other using 11

FIG. 2.18 Representation of the voltage error signal together with different hysteresis bands.

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FIG. 2.19 Circuit diagram of the converter used to test the proposed control.

levels. As was mentioned earlier, the amplitude of the hysteresis band for each cycle adapts according to the number of levels used in the previous half-cycle. The zoom of the third quarter of the first cycle allows the commutation events in the inverter to be defined and the dead time introduced to ignore the crossing events that do not imply a new commutation, which are always immediately after a real commutation event. Implementation of the proposed control requires the use of a digital device to store the lookup table with the gate signals required in the bridges, to produce every possible output level and also the lookup table with the reference. Internally, a memory pointer allows consecutive access to the addresses of the tables, taking into account comparison events. The sinusoidal reference is reproduced according to an inner sampling frequency to properly provide the desired output frequency. As depicted in Fig. 2.19, the voltage error is processed by the hysteresis comparator, which provides the up-and-down orders to the memory pointers. Each cycle, the maximum or minimum value produced in the counter allows updates of the amplitude of the hysteresis band for the subsequent cycle.

2.7.4 Simulated results To validate the proposed hysteresis voltage control approach, the parameters in Table 2.2 were used to build a simulation in PSIM software. The results depicted in Fig. 2.20 were obtained from a single simulation of three fundamental frequency cycles at 60 Hz, applying two disturbance events to show the operation of the control in the face of changes in the input voltage and the output load. In the simulation test, the inverter starts operating in nominal conditions, i.e., an input voltage of 48 V and an output load of 633 W, producing a 31-level signal. Once the first cycle finishes at 16.66 ms, the output power increases suddenly, until reaching 3.12 kW. The output voltage is immediately constrained into the new hysteresis

Table 2.2 Parameters of the simulated model. Parameter

Symbol

Value

Unities

Nominal input voltage Nominal output voltage Nominal power Nominal frequency Equivalent series resistance

vin Vo Po f Rs

48 110 3.2 60 0.07

V V kW Hz Ω

FIG. 2.20 Waveforms of output voltage, output current, reference signals of the inverter control, and voltage at the input side of the transformers.

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CHAPTER 2 Hysteresis control methods

band, producing a 35-level signal. Once the second cycle finishes at 33.33 ms, the input voltage is increased to 62.8 V, introducing a new disturbance in the system without changing the output load. Again, the voltage is constrained into a new hysteresis band, this time producing a 27-level signal. The THD of the output voltage for the three intervals was measured as 2.8%, 2.4%, and 3.3%, respectively. These results are in good agreement with the international standards of harmonic content [57]. The deviation of the RMS value of 110 V in the output voltage for the three intervals was measured as lower than 0.3%, which also remains within allowable levels. The zoom performed for the three intervals in the region close to ωt ¼ π/2 at the top of Fig. 2.19 allows clear differentiation of the way in which the inverter is producing the output signal in good agreement with theoretical predictions.

2.7.5 Comparison and discussion The application of the HVC to multilevel inverters is focused on stand-alone applications because it is very useful for ensuring an adequate output voltage. The PWMbased techniques can provide a more accurate tracking of a sinusoidal reference signal, but they do so at the expense of the use of high frequency and then increasing the switching losses. The MB HVC shows a similar performance because it also requires several commutations per period to shape the output voltage but provides increased robustness and rapid response. The main limitation of these methods is that performance depends on the switching frequency, which in fact is limited by the semiconductors used, which are much slower as their potential capacity increases. The proposed HVC requires a few commutations per period, which are limited by the maximum number of positive levels of the inverter. Then, when asymmetric multilevel inverters are used, a complete sequence of integer consecutive levels is available, in which cases the method provides a simple, effective, and efficient alternative for control. For inverters of 27 or more levels, a THD below 4% can be ensured. Complementarily, it is worth highlighting that digital implementation of the method can be embedded in low-cost devices, since only simple mathematics, memory addressing, and logic operations are required.

2.8 Conclusions A review of hysteresis control methods applied to multilevel inverters was presented in this chapter. The main advantages of this nonlinear control technique are related to its simple implementation, performing time response, and robustness. The possibility of using this technique to control the output current or output voltage of the inverters was also discussed, showing that this flexibility enlarges its application to both gridconnected and stand-alone cases. The three most relevant hysteresis current control techniques were described in a tutorial manner, showing their mode of operation and discussing their advantages

References

and drawbacks. After that, the use of the hysteresis technique to control the output voltage was discussed, reviewing two approaches, one regulating the amplitude or the RMS voltage and the other forming the shape of the voltage waveform. Finally, a new hysteresis voltage control method was introduced and explained, providing an alternative to reduce the commutation of semiconductors. Details on the implementation of the method and simulated results were provided, incentivizing its future experimental validation.

References [1] D. Manz, R. Walling, N. Miller, B. LaRose, R. D’Aquila, B. Daryanian, The grid of the future: ten trends that will shape the grid over the next decade, IEEE Power Energ. Mag. 12 (3) (2014) 26–36. [2] L.G. Franquelo, J. Rodriguez, J.I. Leon, S. Kouro, R. Portillo, M.A.M. Prats, The age of multilevel converters arrives, IEEE Ind. Electron. Mag. 2 (2) (2018) 28–39. [3] M. Priya, P. Ponnambalam, K. Muralikumar, Modular-multilevel converter topologies and applications—a review, IET Power Electron. 12 (2) (2019) 170–183. [4] M.N. Raju, J. Sreedevi, R.P. Mandi, K.S. Meera, Modular multilevel converters technology: a comprehensive study on its topologies, modelling, control and applications, IET Power Electron. 12 (2) (2019) 149–169. [5] S. Kouro, et al., Recent advances and industrial applications of multilevel converters, IEEE Trans. Ind. Electron. 57 (8) (2010) 2553–2580. [6] A. Dekka, B. Wu, R.L. Fuentes, M. Perez, N.R. Zargari, Evolution of topologies, modeling, control schemes, and applications of modular multilevel converters, IEEE Trans. Emerg. Sel. Topics Power Electron. 5 (4) (2017) 1631–1656. [7] A. Perez, S. Bernet, J. Rodriguez, S. Kouro, R. Lizana, Circuit topologies, modeling, control schemes, and applications of modular multilevel converters, IEEE Trans. Power Electron. 30 (1) (2015) 4–17. [8] A.B. Acharya, M. Ricco, D. Sera, R. Teoderscu, L.E. Norum, Performance analysis of medium-voltage grid integration of pv plant using modular multilevel converter, IEEE Trans. Energy Convers. 34 (4) (2019) 1731–1740. [9] S. Kouro, J.I. Leon, D. Vinnikov, L.G. Franquelo, Grid-connected photovoltaic systems: an overview of recent research and emerging pv converter technology, IEEE Ind. Electron. Mag. 9 (1) (2015) 47–61. [10] S. Rivera, et al., Multilevel direct power control—a generalized approach for gridtied multilevel converter applications, IEEE Trans. Power Electron. 29 (10) (2014) 5592–5604. [11] S. Alepuz, A. Calle, S. Busquets-Monge, S. Kouro, B. Wu, Use of stored energy in PMSG rotor inertia for low-voltage ride-through in back-to-back NPC converter-based wind power systems, IEEE Trans. Ind. Electron. 60 (5) (2013) 1787–1796. [12] S. Rivera, B. Wu, S. Kouro, V. Yaramasu, J. Wang, Electric vehicle charging station using a neutral point clamped converter with bipolar DC bus, IEEE Trans. Ind. Electron. 62 (4) (2015) 1999–2009. [13] D. Ronanki, S.S. Williamson, Modular multilevel converters for transportation electrification: challenges and opportunities, IEEE Trans. Transp. Electrification 4 (2) (2018) 399–407.

57

58

CHAPTER 2 Hysteresis control methods

[14] M.M. Bhesaniya, A. Shukla, Current source modular multilevel converter: detailed analysis and STATCOM application, IEEE Trans. Power Delivery 31 (1) (2016) 323–333. [15] S.M. Goetz, Z. Li, X. Liang, C. Zhang, S.M. Lukic, A.V. Peterchev, Control of modular multilevel converter with parallel connectivity—application to battery systems, IEEE Trans. Power Electron. 32 (11) (2017) 8381–8392. [16] A.Q. Huang, Q. Zhu, L. Wang, L. Zhang, 15 kV SiC MOSFET: an enabling technology for medium voltage solid state transformers, CPSS Trans. Power Electron. Appl. 2 (2) (2017) 118–130. [17] A.Q. Huang, Medium-voltage solid-state transformer: technology for a smarter and resilient grid, IEEE Ind. Electron. Mag. 10 (3) (2016) 29–42. [18] D. Kinzer, S. Oliver, Monolithic HV GaN power ICs: performance and application, IEEE Power Electron. Mag. 3 (3) (2016) 14–21. [19] P. Chaturvedi, Conventional multilevel inverter: topologies and control strategies, in: Modeling and Control of Power Electronics Converter System for Quality Improvements, Elsevier, 2018, pp. 85–120. [20] I. Colak, E. Kabalci, R. Bayindir, Review of multilevel voltage source inverter topologies and control schemes, Energ. Conver. Manage. 52 (2011) 1114–1128. [21] S. Kouro, P. Lezana, M. Angulo, J. Rodriguez, Multicarrier PWM with DC-link ripple feedforward compensation for multilevel inverters, IEEE Trans. Power Electron. 23 (1) (2008) 52. [22] S. Alepuz, S. Busquets-Monge, J. Bordonau, J.A. Martinez-Velasco, C.A. Silva, J. Pontt, J. Rodriguez, Control strategies based on symmetrical components for grid-connected converters under voltage dips, IEEE Trans. Ind. Electron. 56 (6) (2009) 2162–2173. [23] P. Lezana, C.A. Silva, J. Rodriguez, M.A. Perez, Zero-steady-state error input-current controller for regenerative multilevel converters based on single-phase cells, IEEE Trans. Ind. Electron. 54 (2) (2007) 733–740. [24] C. Cecati, F. Ciancetta, P. Siano, A multilevel inverter for photovoltaic systems with fuzzy logic control, IEEE Trans. Ind. Electron. 57 (12) (2010) 4115–4125. [25] H. Azeem, S. Yellasiri, V. Jammala, B. Shiva Naik, A. Kumar Panda, A fuzzy logic based switching methodology for a cascaded H-bridge multi-level inverter, IEEE Trans. Power Electron. 34 (10) (2019) 9360–9364. [26] G. Eshwar Gowd, P.C. Sekhar, D. Sreenivasarao, Real-time validation of a sliding mode controller for closed-loop operation of reduced switch count multilevel inverters, IEEE Syst. J. 13 (1) (2019) 1042–1051. [27] G. Sandoval, H. Miranda, G. Espinosa-Perez, V. Ca´rdenas, Passivity-based control of an asymmetric nine-level inverter for harmonic current mitigation, IET Power Electron. 5 (2) (2012) 237–247. [28] C.-C. Hua, C.-W. Wu, C.-W. Chuang, A digital predictive current control with improved sampled inductor current for cascaded inverters, IEEE Trans. Ind. Electron. 56 (5) (2009) 1718–1726. [29] A. Shukla, A. Ghosh, A. Joshi, A. Chuang, Hysteresis modulation of multilevel inverters, IEEE Trans. Power Electron. 26 (5) (2011) 1396–1409. [30] J. Peter, R. Ramchand, Nearly constant switching frequency hysteresis controller for VSI fed IM drives based on current error space vector, in: 2016 IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), Trivandrum, 2016, pp. 1–5. [31] M. Marchesoni, High performance current control techniques for applications to multilevel high-power voltage source inverters, IEEE Trans. Power Electron. 7 (1) (1992) 189–204.

References

[32] R. Gupta, A. Ghosh, A. Joshi, Cascaded multilevel control of DSTATCOM using multiband hysteresis modulation, in: Proceedings of the IEEE Power & Energy Society General Meeting, 2006, pp. 1–7. [33] R. Gupta, A. Ghosh, A. Joshi, Switching characterization of cascaded multilevelinverter-controlled systems, IEEE Trans. Ind. Electron. 55 (3) (2008) 1047–1058. [34] A. Shukla, A. Ghosh, A. Joshi, Hysteresis modulation of multilevel inverters, in, IEEE Trans. Power Electron. 26 (5) (2011) 1396–1409. [35] P.C. Loh, G.H. Bode, P. Tan, Modular hysteresis current control of hybrid multilevel inverters, IEEE Proc. Electr. Power Appl. 152 (1) (2005) 1–8. [36] F. Zare, G. Ledwich, A hysteresis current control for single-phase multilevel voltage source inverters: PLD implementation, IEEE Trans. Power Electron. 17 (5) (2002) 731–738. [37] G.H. Bode, D.G. Holmes, Implementation of three level hysteresis current control for a single phase voltage source inverter, in: 2000 IEEE 31st Annual Power Electronics Specialists Conference. Conference Proceedings (Cat. No. 00CH37018), Galway, Ireland, vol.1, 2000, pp. 33–38. [38] A. Elnady, A comparative study for the common current regulators of multilevel and cascaded inverters, in: CCECE 2010, Calgary, AB, 2010, pp. 1–4. [39] G.H. Bode, D.N. Zmood, P.C. Loh, D.G. Holmes, A novel hysteresis current controller for multilevel single phase voltage source inverters, in: Proc. IEEE PESC’01, 2001, pp. 1845–1850. [40] A. Shukla, A. Ghosh, A. Joshi, Improved multilevel hysteresis current regulation and capacitor voltage balancing schemes for flying capacitor multilevel inverter, IEEE Trans. Power Electron. 23 (2) (2008) 518–529. [41] A. Shukla, A. Ghosh, A. Joshi, Hysteresis current control operation of flying capacitor multilevel inverter and its application in shunt compensation of distribution systems, IEEE Trans. Power Delivery 22 (1) (2007) 396–405. [42] X. Mao, R. Ayyanar, H.K. Krishnamurthy, Optimal variable switching frequency scheme for reducing switching loss in single-phase inverters based on time-domain ripple analysis, IEEE Trans. Power Electron. 24 (4) (2009) 991–1001. [43] R. Gupta, A. Ghosh, A. Joshi, Multiband hysteresis modulation and switching characterization for sliding-mode-controlled cascaded multilevel inverter, IEEE Trans. Ind. Electron. 57 (7) (2010) 2344–2353. [44] R. Gupta, A. Ghosh, Frequency-domain characterization of sliding mode control of an inverter used in DSTATCOM application, IEEE Trans. Circuits Syst. Regul. Pap. 53 (3) (2006) 662–676. [45] M. Kale, E. Ozdemir, An adaptive hysteresis band current controller for shunt active power filter, Electr. Pow. Syst. Res. 73 (2) (2005). [46] Y. Suresh, A.K. Panda, M. Suresh, Real-time implementation of adaptive fuzzy hysteresis-band current control technique for shunt active power filter, IET Power Electron. 5 (7) (2012) 1188–1195. [47] L. Wang, C. Lam, M. Wong, N. Dai, K. Lao, C. Wong, Non-linear adaptive hysteresis band pulse-width modulation control for hybrid active power filters to reduce switching loss, IET Power Electron. 8 (11) (2015) 2156–2167. [48] J.V. Lopez, S.M. Garcia, J.C.C. Rodriguez, R.V. Garcia, S.M. Fernandez, C.C. Olay, Electronic tap-changing stabilizers for medium-voltage lines optimum balanced circuit, IEEE Trans. Power Deliv. 27 (2012) 1909–1918. [49] O. Lopez-Santos, C.A. Jacanamejoy-Jamioy, D.F. Salazar, J.R. Corredor-Ramı´rez, G. Garcia, L. Martinez-Salamero, A single-phase transformer-based cascaded

59

60

CHAPTER 2 Hysteresis control methods

[50]

[51] [52]

[53] [54]

[55]

[56] [57]

asymmetric multilevel inverter with balanced power distribution, IEEE Access 7 (2019) 98182–98196. J. Venkataramanaiah, Y. Suresh, A. Kumar-Panda, A review on symmetric, asymmetric, hybrid and single DC sources based multilevel inverter topologies, Renew. Sustain. Energy Rev. 76 (2017) 788–812. J. Rodrı´guez, J.S. Lai, F.Z. Peng, Multilevel inverters: a survey of topologies, controls and applications, IEEE Trans. Ind. Electron. 49 (4) (2002) 724–738. R.R.A. Farakhor, H. Ardi, S. Najafi Ravadanegh, Symmetric and asymmetric transformer based cascaded multilevel inverter with minimum number of components, IET Power Electron. 8 (6) (2015) 1052–1060. M.R. Banaei, H. Khounjahan, E. Salary, Single-source cascaded transformers multilevel inverter with reduced number of switches, IET Power Electron. 5 (9) (2012) 1748–1753. J.S. Lee, H.W. Sim, K.B. Lee, J. Kim, Combination analysis and switching method of a cascaded H-bridge multilevel inverter based on transformers with the different turns-ratio for increasing the voltage level, IEEE Trans. Ind. Electron. 65 (6) (2017) 4454–4465. A.F. Ajami, H. Ardi, Minimisations of total harmonic distortion in cascaded transformers multilevel inverter by modifying turn ratios of the transformers and input voltage regulation, IET Power Electron. 7 (11) (2013) 106–114. F.S. Kang, A modified cascaded transformer-based multilevel inverter and its efficient switching function, Electr. Pow. Syst. Res. 79 (2009) 1648–1654. IEEE recommended practice and requirements for harmonic control in electric power systems, in: IEEE Std 519–2014 (Revision of IEEE Std 519–1992), 2014, pp. 1–29.

CHAPTER

Proportional resonance control and applications

3

Allal El Moubarek Bouzida,b, Mohamed Assaad Hamidab, Hicham Chaouic, and Azeddine Houarid a

Electrical and Computer Engineering Department, Universit
e du Qu
ebec a` Trois-Rivie`res, Troisb ` Rivieres, QC, Canada Laboratoire des Sciences du Num
erique de Nantes (LS2N), Ecole Centrale de Nantes, Nantes, France cIntelligent Robotic and Energy Systems Research Group, Department of Electronics, Carleton University, Ottawa, ON, Canada dIREENA Laboratory, University of Nantes, Saint-Nazaire, France

3.1 Introduction The increasing penetration of distributed power generation systems (DPGSs), including renewable energy sources and small nonrenewable sources, is increasingly important in today’s electrical systems. However, this augmentation makes the grid more and more complex and it becomes more difficult to control. However, for the integration of DPGSs to be possible, the use of synchronous power controllers (SPCs) has become a subject of intense interest, as an interface between the different DPGSs and the loads/AC power grid infrastructures, to allow matching the generated power to the standards of the power system. Nevertheless, regardless of the SPC topology used and its modulation strategy, switching harmonics will be generated due to its operation. In order to reduce the injection of harmonics, attenuate the high-frequency switching noise that the SPC generates, and provide a voltage with a low distortion at the point of common coupling (PCC) in stand-alone mode or as a grid-tied inverter or to feed some local loads, as well as to meet the specific rules for grid connection, passive filters must be connected between the inverter and the power grid. There are several types of passive coupling filters used, the most common being: (i) first order—L; (ii) second order—LC; and (iii) third order—LCL (high-performance application). However, the type of coupling filter installed in SPCs may cause undesirable interactions, such as resonances between the different sources or instability. The LCL filter presents several advantages that make it very attractive to use. Among these advantages are the precision in obtaining a zero error in steady state, attenuation of the high-frequency switching noise that the SPC generates, provision of a voltage with a low distortion at the PCC, and the simple implementation. Despite these advantages of the LCL filter, its connection with an SPC is Multilevel Inverters. https://doi.org/10.1016/B978-0-323-90217-5.00003-4 Copyright # 2021 Elsevier Inc. All rights reserved.

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more difficult to control due to its high-order dynamics, which contain lightly damped poles placed at the filter resonant frequency, making the controller design more complex. These critical points become a complex problem in power systems. They can be a source of instability that compromises the stability of the system and can cause a degradation of the robustness in the face of variations of the parameters of the system, which in turn modifies the resonant frequency of the LCL filter. This last problem is an important point to consider in networks with high penetration of renewable sources with many loads, or in isolated networks with low density of consumption, where the impedance of the network is very high. In view of the foregoing, this chapter proposes as a contribution an advanced robust control law based on the internal model principle in synchronous and stationary frames, to ensure a good tracking of sinusoidal reference signals with zero error and rejection of harmonic components in steady state due to output voltage distortion. This controller guarantees system stability with high performance and mitigates the problems of network-connected converters through LCL filters. To this end, this chapter focuses on the design of a multifrequency proportional resonant controller (RC) tuned in the fundamental frequency and in the most important harmonic components for the primary control of SPCs subject to parametric uncertainties and nonlinear loads. The multifrequency proportional RC parameter design is formulated in terms of linear matrix inequalities (LMIs), considering parametric uncertainties, load variations, and disturbances by means of polytopic linear time-varying models in which the controller parameters are fixed (robust) and determined by solving a convex optimization problem with LMI constraints. The formulation of the optimization problem is based on multiple Lyapunov stability matrices, using a LyapunovKrasovskii functional, relying on a polytopic time-varying model that allows representation of any time variation of filter parameters inside bounded real intervals, which ensure the robust stability of the control system, and incorporation of performance specifications to obtain a good trade-off between the transient response (D -stability) and disturbance attenuation. Thus after defining the plant model, controller topology, and method of representing performance requirements through LMIs, the resulting controller gains are resolved using MATLAB® computational packages. The results of the proposed methodology are evaluated with numerical examples and validated through experimental results to verify the performance of the proposed controller in facing the issues described earlier.

3.2 Challenges in inverter systems control 3.2.1 Literature review

In the literature, three categories of RCs can be distinguished: proportional resonant [1, 2]; vector proportional integral [3]; and variations of these RCs [4, 5], which enhance the stability margins but cannot guarantee a closed-loop pole position independent of the LCL filter used. Under these three principal categories, several

3.3 Problem statement and description

solutions have been proposed in the literature. In Samavati and Mohammadi [6], a cascaded current- and voltage-control scheme was developed based on the virtual impedance concept. The proposed control allows simultaneous improvement of the grid-injected current and local load voltage in islanded and grid-connected microgrids. In Husev et al. [7], an optimized proportional RC was designed, considering the computational delay from the digital control system. In Oso´rio et al. [8], a grid-tied inverter robust current controller was proposed under magnetic soft saturation and uncertain grid impedance. A polytopic model was used for the controller development by taking into account the inductance variations. To reduce the steady-state current deviation, a capacitive-coupling grid-connected inverter [9] was proposed to apply a quasiproportional RC. The developed controller produced the voltage reference for use of carrier-based PWM. The proposed solution allows the minimization of output current ripples. Generally, the proportional RC parameters are tuned manually. In Husev et al. [7], an optimized tuning process of the RC controller was developed by taking the computation time delay into account. To adapt the controller parameters to the grid parameter variations, Khalfalla et al. [10] proposed an adaptive proportional RC. A fourth-order filter was used with the adaptive RC to estimate the resonance frequency online, and then the grid impedance variations. Kumar et al. [11] proposed a modified proportional RC used for an inner current control loop, and an indirect vector controller at a rotating reference frame was developed for the outer DC-link voltage loop. The proposed controller allowed a reduction in the steady-state current error. In Saim et al. [12], an innovative approach was proposed to compensate for the resonance phenomena without knowing the system parameters, by not affecting the control bandwidth. This approach was applied in islanded microgrids. To improve the performance of microgrids, Bouzid et al. [13] proposed a three-degrees-of-freedom cascaded voltage/current controller for the DG. The controller design was based on the H ∞ theory. In these works, the stability of the closed-loop system and the robustness against parameter uncertainties have rarely been studied, knowing that the system can be affected by grid impedance uncertainties and by grid voltage disturbances.

3.3 Problem statement and description 3.3.1 Problem formulation

The complexity of electrical grids continues to grow. Moreover, obtaining the parameters of the power grid is a major obstacle for the realization of a control project, since they are not precisely known values, and in addition are time-varying. To meet this challenge, it is very important to develop an efficient control system that should be able to ensure good tracking of the output voltage reference in the presence of grid impedance uncertainties, harmonics, broad-band frequency, and grid voltage disturbances. The grid impedance uncertainties strongly affect the stability of the current controller; this problem is due to the low-pass filters employed with the

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CHAPTER 3 Proportional resonance control and applications

high-frequency harmonics produced by the PWM, especially when these filters are designed for nominal cases. To deal with these problems, this work proposes to use the LMI approach for designing an optimal controller that accomplishes the following objectives: • • •

Positioning the closed-loop pole in order to have faster response. Ensuring the stability of the system in the presence of grid impedance uncertainties. Ensuring a good sine reference tracking with rejection of all disturbances, especially voltage harmonics from the grid, e.g., and pulse-width modulated (PWM) signals from the inverter [14].

In the following section, the system modeling is introduced. Since a state feedback controller is used, the system is represented by a state space model.

3.3.2 System modeling The aims of this section are to present the connected power converters using a statespace model. This model will be used at a larger stage for the design of a state feedback controller. The control objective is to manage the power flow between the different sources, such as wind turbines, photovoltaic panels, and the power grid. The power flow is then controlled by the current injected to the network. For that, a performant current control strategy is developed. The developed strategy should ensure a good dynamic response, combined with a good distance rejection capability [15]. Consider a voltage source converter (VSC) connected to the mains via an LCL filter, given in Fig. 3.1. The filter inductors are modeled as a series inductance with a resistor, which represents the intrinsic resistance of the inductor. Subscripts c and g are used to identify the converter side and grid side elements, respectively. The network side inductance is represented by two inductors: Lg1 as part of the filter and Lg2 representing the network inductance. Usually the value of Lg2 is unknown. Therefore it will be considered as a parametric variation. The last

i ca (t) R c

vta VCC

vtb vtc

Lc

Rc

L g1

i ga

i cb(t)

i gb

i cb(t)

i gc +

Cf

vca (t) −

FIG. 3.1 Network-connected VSC converter through LCL filter.

L g2

vga (t)

3.3 Problem statement and description

component of the filter is the capacitor, Cf. The variables ick, igk, υck, υtk, and υgk are the converter side current, the current injected into the network, and the capacitor voltage, converter terminal voltage, and mains voltage, respectively, where k  a; b; c is used to represent the three phases of the system. Finally, VDC represents the direct bus voltage (DC). Considering the balanced operation of the VSC, each phase of Fig. 3.1 can be treated independently, in order to simply analyze the monophasic equivalent of phase “a” as illustrated in Fig. 3.2. By disregarding the switching harmonics, one can obtain the circuit model shown in Fig. 3.2 by applying Kirchhoff’s laws. The system of differential equations labeled (1) represents the dynamics of the LCL filter for phase a of the system, noting that Lg ¼ Lg1 + Lg2. 8 dica > > ¼ υta  υca  Rc ica > Lc > dt > > < diga ¼ υca  υga  Rg iga Lg > dt > > > > > : Cf dυca ¼ ica  iga dt

(1)

The system of Eqs. (1) can be represented in state space as follows: 3 3 2 Rc 1 dica 2 3 0 2 3 2 3 1 Lc 7 Lc 6 dt 7 6 0 6 7 i ca 6 7 6 6 7 7 6 diga 7 6 6 1 7 Rg 1 76 7 6 Lc 7 6 7 7 0 4 iga 5 + 6 0 7υta + 6 6 dt 7 ¼ 6 4 Lg 5υga Lg Lg 7 4 5 7 6 7 6 7 υca 4 dυ 5 6 4 1 1 5 0 0 ca 0 dt Cf Cf 2 3 ica 6 7 y ¼ ½0 1 04 iga 5 2

(2)

υca

By rewriting the system (2) in its compact form and by adding the differential equations of phases b and c, the complete state-space model of the converter is obtained as follows: d xabc ¼ Aabc xabc + Buabc uabc + Bwabc wabc dt y ¼ Cabc xabc

Rc

− +

vta (t)

Rg

Lc +

i ca (t)

L g1

L g2

i ga (t) Cf

vca (t)

(3)

−

FIG. 3.2 Single-phase equivalent circuit diagram of the LCL filters.

vga (t)

65

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CHAPTER 3 Proportional resonance control and applications

where xa is the state vector, υta is the control input, υga is the disturbance input (network), and ya is the system output. A, Bu, Bw and Ca are the dynamic matrix, the control input matrix, the disturbance input matrix, and the output matrix, respectively. That matrices and vectors are given by: 3 3 2 033 033 Bu 033 033 7 7 6 6 Aabc ¼ 4 033 A 033 5, Buabc ¼ 4 033 Bu 033 5, 033 033 A 033 033 Bu 2 3 2 3 Bw 033 033 C 033 033 Bwabc ¼ 4 033 Bw 033 5, Cabc ¼ 4 033 C 033 5 033 033 Bw 033 033 C 2

A

(4)

xTabc ¼ ½ ica iga υca icb igb υcb icc igc υcc , uTabc ¼ ½ ua ub uc ,

(5)

wTabc ¼ ½ υga υgb υgc 

The three-phase system behind this can be transformed into a decoupled biphasic system using coordinate transformation abc to αβ [16]. In order to be able to perform such a transformation, it is necessary to describe the equations so that the same state variables of the three phases can be organized sequentially. This can be achieved by the following linear transformation: xabc ¼ Txabc

(6)

where xTabc ¼ ½ ica icb 2 1 60 6 6 60 6 6 60 6 T ¼6 60 6 60 6 60 6 6 40

icc iga 0 0 0 0 0 1 0 0 0 1 0 0

igb igc 0 0 0 0 0 0 0 0 1 0 0 0

0 0 0 0

1 0 0 0

0 0 1 0

0 0 0 0

0 0 0 1

0 0 0 0

0 0 0 0 0 0 0

υca υcb υcc , 3 0 0 0 07 7 7 0 07 7 7 0 07 7 0 07 7: 7 1 07 7 0 07 7 7 0 05 0 1

Applying the transformation (6) to the system (3) gives d xabc ¼ Aabc xabc + Buabc uabc + Bwabc wabc dt y ¼ Cabc xabc

(7)

Aabc ¼ TAabc T 1 Buabc ¼ TBuabc Bwabc ¼ TBwabc Cabc ¼ Cabc T 1

(8)

where

3.3 Problem statement and description

After reorganizing the state variables using the previous linear transformation, the system can be referenced in the coordinates αβ0. The Clarke transformation matrix is given by: 2

3 1 1  1  6 7 6 pffiffi2ffi p2ffiffiffi 7 7 26 3 3 7 Tαβ0 ¼ 6 0  6 7 36 2 2 7 4 5 1 1 1 2 2 2

(9)

The term 2/3 is used to ensure amplitude invariance. However, due to the order of the vector of the state variables, it is not possible to directly use the transformation matrix (7), and it is necessary to increase the matrix as follows: 2

a Tαβ0

3 Tαβ0 033 033 ¼ 4 033 Tαβ0 033 5 033 033 Tαβ0

(10)

Therefore using (9) and (10), the vectors in the αβ coordinates are given by: a xαβ0 ¼ Tαβ0 xabc a uαβ0 ¼ Tαβ0 uabc

(11)

a wαβ0 ¼ Tαβ0 wabc

Substituting (11) in (7) gives the αβ coordinate system dxαβ0 ¼ Aαβ0 xαβ0 + Buαβ0 uαβ0 + Bwαβ0 wαβ0 dt yαβ0 ¼ Cαβ0 xαβ0

(12)

The state, control, and disturbance vectors are given by: xαβ0 ¼ ½ icα icβ ic0 igα igβ ig0 υcα υcβ υc0  uαβ0 ¼ ½ uα uβ u0 

(13)

wαβ0 ¼ ½ wα wβ w0 

Since the matrices are obtained by: a a Aαβ0 ¼ Tαβ0 Aabc Tαβ0 1 a a Buαβ0 ¼ Tαβ0 Buabc Tαβ0 1 a a Bwαβ0 ¼ Tαβ0 Bwabc Tαβ0 1

(14)

a Cαβ0 ¼ Cabc Tαβ0 1

Finally, one can rewrite the system (12) as follows: dxαβ0 ¼ Aαβ0 xαβ0 + Buαβ0 uαβ0 + Bwαβ0 wαβ0 dt yαβ0 ¼ Cαβ0 xαβ0

(15)

xαβ0 ¼ ½ icα igα υcα icβ igβ υcβ ic0 ig0 υc0 

(16)

where

67

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CHAPTER 3 Proportional resonance control and applications

and Aαβ0 ¼ T 1 Aαβ0 T Buαβ0 ¼ T 1 Buαβ0 Bwαβ0 ¼ T 1 Bwαβ0

(17)

Cαβ0 ¼ Cαβ0 T

Expansion of (15) gives:

32 3 2 32 3 2 3 2 Aαβ0 033 033 Buαβ0 031 031 xα uα xα d6 7 6 76 7 6 76 7 4 xβ 5 ¼ 4 033 Aαβ0 033 54 xβ 5 + 4 031 Buαβ0 031 54 uβ 5 dt 033 033 Aαβ0 031 031 Buαβ0 x0 x0 u0 2 32 3 wgα Bwαβ0 031 031 + 4 031 Bwαβ0 031 54 wgβ 5 wg0 031 031 Bwαβ0

(18)

Due to the fact that the system is three wire, that is, there is no way to circulate a zero sequence current, the rows and columns relative to the coordinates 0 can be disregarded. Thus, due to decoupling, the system (18) reduces to the following two independent systems: dxα ¼ Aα xα + Buα uα + Bwα vgα dt y ¼ Cα xα

(19)

dxβ ¼ Aβ xβ + Buβ uβ + Bwβ vgβ dt y ¼ Cβ xβ

(20)

Aα ¼ Aβ ¼ A Buα ¼ Buβ ¼ Bu Bwα ¼ Bwβ ¼ Bw Cα ¼ Cβ ¼ C

(21)

where

Note that the matrices are the same as the single-phase system (2) in the abc coordinates. For control design purposes, it is possible to use only one of the axes, for example α. The projected gains can later be used on the other axis. Considering, therefore, one of the monophasic systems and omitting the α and β subscripts of the variables to simplify the notation, we can write dx ¼ Ax + Bu vt + Bw vg dt y ¼ Cx

where

(22)

2

3 Rc 1 2 3 0 2 3 6 Lc 2 3 1 Lc 7 0 6 7 i ca 6 7 6 7 6 1 7 6 7 6 Lc 7 6 0 Rg 1 7 7 A¼6 , x ¼ 4 iga 5, Bu ¼ 6 0 7, Bw ¼ 6 4 L g 5, C ¼ ½ 0 1 0  Lg Lg 7 4 5 6 7 6 7 υca 4 1 1 5 0 0 0 Cf Cf

(23)

3.3 Problem statement and description

3.3.3 Effect of parameter variations on system performance When proposing to perform the mathematical modeling of a nonlinear real system, it is expected that this model would present variations, arising from the linearization of the system around an operating point, changes in operating conditions, or inaccuracy in the estimation of the actual parameters of the model. It is considered possible to group the uncertain terms of the system into a δ vector with N uncertain parameters δ ¼ [δ1, …, δN], where each δi parameter is limited between a minimum and a maximum value, as shown here: h i δi  δi , δi

(24)

The δ vector values are grouped in a hyperrectangle in the parametric space ℝN. The parameters that vary in this system, according to the operating point, are the converter side inductance Lc, the capacitor Cf of the LCL filter, the grid side inductance Lg1 of the LCL filter, and the grid inductance Lg2. Thus the uncertain parameters are modeled as: Lc ΔLc , ΔLc ¼ fLc ℜ + : Lc

min

 Lc  Lc

max g

 Cf ΔCf , ΔCf ¼ Cf ℜ + : Cf

min

 Cf  Cf

max

(25)



 Lg1 ΔLg1 , ΔLg1 ¼ Lg1 ℜ + : Lg1 min  Lg1  Lg1

max

 Lg2 ΔLg2 , ΔLg2 ¼ Lg2 ℜ + : Lg2 min  Lg2  Lg2

max

(26)  

(27) (28)

The goal of the control is to find a K-state feedback gain that ensures stability, performance, and disturbance rejection for all possible cases [A(δ), Bu(δ), Bw(δ)]. In order to facilitate the analysis of the dynamic behavior of the filter, the system can be represented in transfer functions. For this reason it is necessary to use Eq. (29), which relates the output of a function, Y(s), to the input U(s): Y ðsÞ ¼ CðsI  AÞ1 B U ðsÞ

(29)

Since system (22) has two inputs υt and υg, one can apply the superposition theorem, resulting in two transfer functions: I g ðsÞ ¼ CðsI  AÞ1 Bu Vt ðsÞ

(30)

I g ðsÞ ¼ CðsI  AÞ1 Bw Vg ðsÞ

(31)

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CHAPTER 3 Proportional resonance control and applications

The output variable in both transfer functions is the mains current. Substituting the matrices given in (23) into (30) and (31) gives, respectively, the following transfer functions: I g ðsÞ 1       ¼ Vt ðsÞ Cf Lg Lc s3 + Cf Lc Rg + Cf Lg Rc s2 + Lg + Lc + Cf Rc Rg s + Rg + Rc

(32)

  Lc Cf s2 + Rg Cf s + 1 I g ðsÞ       ¼ Vg ðsÞ Cf Lg Lc s3 + Cf Lc Rg + Cf Lg Rc s2 + Lg + Lc + Cf Rc Rg s + Rg + Rc

(33)

Since the resistances Rg and Rc are small compared to the impedances of the other components of the LCL filter at operating frequency, they can be neglected to facilitate analysis. Therefore, the simple transfer functions are I g ðsÞ 1   ¼ Vt ðsÞ Cf Lg Lc s3 + Lg + Lc s

(34)

  Lc Cf s2 + 1 I g ðsÞ   ¼ Vg ðsÞ Cf Lg Lc s3 + Lg + Lc s

(35)

From the nonzero root of the denominator of (34), one can determine the resonance frequency of the transfer function as: fres ¼

where

ωres 2π

sffiffiffiffiffiffiffiffiffiffiffiffiffiffi Lg + Lc ωres ¼ Cf Lg Lc

(36)

(37)

For numerical analysis, the parameters listed in Table 3.1 were used.

3.3.3.1 Frequency response of the system In this study, the LCL filter is connected to the inverter in order to attenuate the harmonics coming from the PWM signal. Based on plant model matrices given in Eq. (22), we can observe that the latter depend on the uncertain parameters Lc, Cf, and Lg, where Lg ¼ Lg1 + Lg2. The objective of this section is to show the influences of the parametric uncertainties on the system. By substituting the parameter values given in Table 3.1 in Eqs. (32) and (33), one can plot and analyze the frequency responses of the system to show the impact of parametric variations on this last. In this study we may note that in each case the nominal value for each parameter has been adopted. For the parameter Lg2, the nominal case is considered Lg2 ¼ 0 mH or, equivalently, Lg ¼ 0.3 mH. Fig. 3.3 shows the frequency response between the control input υt and the output ig from Eq. (32) for filter and grid parameters. From this figure, we observe that after the resonant peak frequency fres ¼ 6838, 82 Hz calculated from Eqs. (34) and (35), the system has an attenuation of 60 dB.

Table 3.1 System parameters. Inverter parameters System rated power Grid voltage Grid frequency Nominal current

Pbase Vbase fg Ibase

10 kW 230 V 50 Hz 14.5 A

Lg1 Lc Cf fres Rg Rc RCf

3 mH 1 mH 30 μF 880 Hz 0.5 Ω (3.0%) 1.0 Ω (6.0%) 0.1 Ω (0.6%)

Lg2 Rg2

1 mH (10%) 0.1 Ω (15%)

Vdc

2.5 kHz 3 μs 750 V

LCL filter Nominal grid side inductance Nominal converter side inductance Nominal filter capacitance Filter resonance Grid side ESR Converter side ESR Capacitor ESR Weak grid Grid inductance Grid resistance VSC Inverter switching frequency Dead time DC-bus voltage

Bode Diagram

Magnitude (dB)

0 -20 -40 -60 -80 -100 -45

Phase (deg)

-90 -135 -180 -225 -270 102

103

104

Frequency (rad/s)

FIG. 3.3 Frequency response of input Vt by output Ig with nominal parameters.

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CHAPTER 3 Proportional resonance control and applications

Bode Diagram 20

Magnitude (dB)

0 -20 -40 -60 -80 270

Phase (deg)

72

225 180 135 90 102

103

104

105

Frequency (rad/s)

FIG. 3.4 Frequency response of input Vg by output Ig with nominal parameters.

On the other hand, for frequencies around the resonant frequency there is a signal amplification. As the same, Fig. 3.4 shows the frequency response between the disturbance input υg and output ig from Eq. (33). As can be seen, the resonance peak is also located at fres ¼ 838.82 Hz, since both transfer functions have the same denominator. Besides the resonance, it is also possible to notice the presence of the bandreject effect, caused by the pair of complex conjugated zeros. Similarly, the central frequency of the notch is obtained by equating the numerator from 33 to zero. In this case, the frequency is fres ¼ 529.986 Hz. From Figs. 3.3 and 3.4, we can observe that the LCL filters have an advantage of good characteristic attenuation of 60 dB per decade at high frequencies. However, these filters have the constraint of presenting a resonance capable of producing unwanted harmonic amplifications and harmonics from the network, thus causing the distorting of the current being injected into the network, which may lead to poor performance or produce system instability. Moreover, it impairs its compatibility with low total harmonic distortion requirements given by standards such as IEEE 2011 [17]. Based on the results obtained previously, use of active or passive damping techniques for the resonance is required. Passive damping is based on the insertion of passive elements in the filter [18]. Active damping is based on the design of a controller ensuring stability and reduces the resonance peaks without adding dissipative elements. For example, see Figs. 3.3 and 3.4, where the closed-loop system displays frequency responses with significant reduction in resonance peaks shown. Active damping techniques are more attractive techniques than passive damping techniques

3.3 Problem statement and description

because they allow the addition of robustness to parametric uncertainties without loss of performance, contrary to passive damping techniques, in which additional power losses are experienced [2]. In this section, the influence of uncertainty on the value of the LCL filter with inductance Lg2 on the frequency domain response can be observed. In this study, the inductance of the network is uncertain and varied from a minimum to a maximum value belonging to the range given in Table 3.1. The same case exists for LCL filter parameters, which varied from a minimum to a maximum value belonging to the range given in Table 3.1. By using the resonance frequency Eq. (36), we can calculate the values of resonance frequency for the minimum value of the LCL filter and Lg2min and the maximum value of the LCL filter and Lg2max. Thus, for the response between the control input υt and the output ig, we obtain the resonance frequency peak located at fres ¼ 733.7043 Hz for Lg2min and the resonance frequency peak located at fres ¼ 1348 Hz for Lg2max. The same equation is used to calculate the variation of the Lg2 parameter: for the response to the disturbance from input υg to output ig, we obtain the resonance frequency peak located at fres ¼ 733.7043 Hz for Lg2min and the resonance frequency peak located at fres ¼ 1360 Hz for Lg2max. From Figs. 3.5 and 3.6, it is interesting to note that there is a strong influence of uncertainty on Lg2 on resonance displacement for the frequency response from input Vt to output Ig and for the frequency response to the disturbance from input υg to output Ig, respectively. This uncertainty in the parameter influences system performance, in some cases making the system unstable [19]. Thus from the preceding results and the observations of Figs. 3.5 and 3.6, we can conclude that it is necessary

FIG. 3.5 Frequency response of input Vg by output Ig with uncertain parameters.

73

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CHAPTER 3 Proportional resonance control and applications

FIG. 3.6 Frequency response of input Vt by output Ig with uncertain parameters.

to design a robust controller that includes the uncertainty range of the network inductance to ensure good performance and damping of the resonance for all parameters. Therefore it is very attractive to apply robust control techniques for this system that allow parametric uncertainties to be taken into account, in order to guarantee good stability and better performance, not only for the nominal values of the system, but also for a range of values.

3.4 Proposed multifrequency proportional resonant controller 3.4.1 State feedback control

The controller of a VSC connected network through an LCL filter shall have the following characteristics: steady-state error following a constant reference will be zero, rapid dynamic response without causing a surge in output current, robustness in the presence of parametric variation and disturbance rejection [20]. Fig. 3.8 shows the structure of the current controller H ∞ proposed together with the system, which according to the modeling performed in the previous section represents a composition of the multilevel inverter and the output filter. As can be seen in Fig. 3.8, the control strategy employed will rely on the action of an integrator in the control loop to make the steady-state error null following the current reference. For this reason, it is necessary to adapt the system model so that the desired integral action is

3.4 Proposed multifrequency proportional resonant controller

FIG. 3.7 Augmented open-loop system.

incorporated into the controller. Next, an augmented system model will be determined so as to insert an integrator into the control action thereof that can eliminate the steady-state error of the current reference tracking. The integral action controller in Eq. (39) has as input the system error e, which is the difference between the reference to be reached rref and the output y. ð η ¼ edt;

(38)

e ¼ η_ ¼ rref  y ¼ rref  Cx

(39)

The open-loop augmented system with the plant equation given by system (22) plus the integral control structure is illustrated in Fig. 3.7 and modeled in Eq. (40). The augmented system can be written as: ex + Beue e + Ber rref u + Bew w e x_ ¼ Ae e y ¼ Ce x

(40)

where the matrices and vectors of the space increased system are as follows: Ae ¼











x Bu Bw 0 A 0 e e e , Ce ¼ ½ C 0 , , e x¼ , Bu ¼ , Bw ¼ , Br ¼ η 1 C 0 0 0

(41)

If system (40) is controllable, the closed-loop poles can be arbitrarily placed using the following control action based on complete state feedback: uðtÞ ¼ K e xðtÞ

(42)

The feedback gain K is composed as follows: K ¼ ½ KP KI 

(43)

where KI  ℝ represents the integrator gain inserted in the control plant. Fig. 3.8 presents the closed-loop system with feedback gains. Substituting the control action (42) in the open-loop system model given by (40) gives the following closed-loop equation for the system:  e + Br r x + Bew w e x_ ¼ Ae + Beu K e e y ¼ Ce x

(44)

75

76

CHAPTER 3 Proportional resonance control and applications

FIG. 3.8 Increased system in closed loop.

Therefore, the control design comes down to finding the feedback vector K in order to guarantee the predefined performance and stability.

3.4.2 Resonant controller One controller used in many similar applications to that presented herein is the RC. This controller tends to be efficient when working with tracking periodic references, such as those discussed in this chapter. Such controllers still have the characteristic of being able to offer rejection to harmonic components coming from the distribution network [21], provided they are properly designed for such. It is also important to remember that the control system in question must allow the current injected into the grid, ig, to track with good-quality sinusoidal references, and to reject harmonics from the grid voltage, e.g. These objectives can be achieved using RCs such as those proposed by Francis and Wonham [22] and Zmood and Holmes [23]. According to the internal model principle, for systems in which the signals to be followed and rejected are sinusoidal, as in the case studied, it is necessary to include the model poles of these signals in the controller. Such controllers are called RCs [23–25]. The following transfer function is usually used in the implementation of the ideal RC: Cr ðsÞ ¼

s2

s2 + ω2h

(45)

where ωh is the frequency of the signal to be followed or rejected. In some applications a damping factor ξ is inserted at the poles of Eq. (45) to avoid discrete implementation problems regarding the position of resonant poles at the edge of the unit circle [26]. Given a RC with transfer function Cra ðsÞ ¼

s2

s2 , + 2ξωh s + ω2h

(46)

3.4 Proposed multifrequency proportional resonant controller

note that by making ξ ¼ 0 the controller in Eq. (46) reduces to that of Eq. (45). Controllers like this allocate imaginary pole pairs at the frequency of the reference to be traced and the frequencies of the disturbances to be rejected. In order to present the way in which the new resonant control tuning method was developed, initially it is necessary to obtain the state-space representation of the transfer function presented in Eq. (45) [26, 27] as in system (47):



0 1 0 η_ ¼ u η+ ω2h 2ξωh 1 η

where

Ach ¼

(47)



0 1 0 , Bch ¼ 2 ωh 2ξωh 1

According to Li et al. [28], this controller can have as many harmonic components added as required. The subscript h represents the order of the compensated harmonic frequency. Several RCs like Eq. (46) can be used in parallel. In this work will be added components in the 5th, 7th, and 11th harmonics, besides the fundamental, at 50 Hz. Thus the following shows the representation of the RC with all components included: 2

3 2 3 2 3 ηc1 Ac1 ⋯ 022 Bc1 e η ¼ 4 ⋮ 5, Aech ¼ 4 ⋮ ⋱ ⋮ 5, Bech ¼ 4 ⋮ 5 ηch 022 ⋯ Ach Bch

(48)

The augmented system can be seen in Eqs. (49) and (50), where the new expanded states correspond to the states of the augmented RC (48) rather than the error integral. " # " " # " #" # " # # A 018 x_ Bu 0 x Bw _e e+ e ¼ w ue + + r ref x¼ e e η_ Bech C Aech 0 0 Bech η

y ¼ ½C 0



x e η

(49)

(50)

Thus a resonant current controller based on state feedback with H ∞ performance and robust to parametric variations can be designed. To this end, we will use the results of the following sections which, in addition to guaranteeing the H ∞ system performance, give this robustness to parameter variation and performance improvement through robust pole allocation.

3.4.3 Polytopic model for uncertain systems Usually the mathematical model of a system does not accurately represent dynamics, for example by simplifying complex system dynamics or even because of inaccuracy in the value of some physical system parameters. In a number of practical situations, a dynamic system may change, for example due to a change in load or when some system parameters vary over time. This uncertain feature of the model can affect the

77

78

CHAPTER 3 Proportional resonance control and applications

closed-loop control system, thereby degrading its performance or even destabilizing the closed-loop system. Generally, the model uncertainties can be considered to refer to differences or errors between the mathematical model and the real system. For example, we consider a physical parameter partially known as an uncertain parameter in a given allowable set of values. In other situations, unknown dynamics can be modeled as one or more unknown operators, but limited by a variable of known value. An uncertain linear system can be described in state space by the following representation: x_ ¼ Aðδi ÞxðtÞ + Bu ðδi ÞuðtÞ y ¼ Cðδi ÞxðtÞ + Dðδi ÞuðtÞ

(51)

with Aðδi Þ ¼ A0 + Cðδi Þ ¼ C0 +

XN

δ A , …,δN AN , i¼1 i i XN δ C ,…,δN CN , i¼1 i i

Bu ðδi Þ ¼ Bu0 + Dðδi Þ ¼ D0 +

XN

δ B ,…, δN BuN i¼1 i ui

XN

δ D , …,δN DN i¼1 i i

The matrices A(δi), B(δi), C(δi), and D(δi) are constants and functions of an uncertainty vector (δi) with i ¼ 0, 1, …, N. The dependence of these matrices on δi can assume varying degrees of complexity, depending on how the elements of the matrices depend on uncertainty. To represent the uncertainties of the inverter module, a polytopic representation was used [29]. The representation of system uncertainties by a polytopic assumes that the possible values of uncertainty are contained in a polytopic, the polytope being defined as a closed set composed of the intersection of N planes. The important feature of the polytope is that any point in its set can be represented by the convex sum of a finite number of points called vertices. According to the theory of representation of parametric uncertainties across polytopes, system (51) can be represented as: (

ðA, Bu , CÞðδðtÞÞ

N X

δi ðtÞðA, Bu , CÞi :

i¼1

N X

)

δi ðtÞ ¼ 1, δi ðtÞ > 0

(52)

i¼1

Fig. 3.9 shows a graphical representation of a polytope with m ¼ 5 vertices. In this chapter, we assume an uncertain parameter with two possible values, minimum and maximum, resulting in a polytopic representation of only four vertices.

3.4.4 Stability according to Lyapunov Normally, stability in control systems is ensured around a point of operation, and it is not clear at what point it can be guaranteed. Therefore, it is necessary to find a way to ensure stability in systems in which their operating point varies. Around 1980 Lyapunov established his concept of stability for a system’s energy-based uncertain systems. Definition 4.1 (Lyapunov Stability). If the energy of a system is continuously dissipated, the system must eventually settle at a point of equilibrium. This stability can be

3.4 Proposed multifrequency proportional resonant controller

FIG. 3.9 Polytopic set with vertices Vi, for i ¼ 1, …, 5.

assessed by its energy function [30]. For a scalar function V(x) to be characterized as an energy function, the following theorem must be obeyed: Theorem 4.1 (Energy Function). The function must be globally positive, that is, V (0) ¼ 0, and for x 6¼ 0 ) V(x) > 0, for the entire state space. This implies that function V has a unique minimum at the origin. As a consequence, the derivative of this function must be negative, V̇ < 0. Energy functions are characterized in linear systems by a relationship of their squared state variables, such as the energy of a capacitor and inductor. Thus, based on this principle, the analysis of the stability of an energy function, according to Theorem 4.1, will take place as follows: V ðxÞ ¼ xT Px > 0

(53)

In order for the function to stabilize in the permanent state, its derivative must be negative. Therefore, using the chain rule in Eq. (53), we obtain: 

V ðxÞ ¼ xT Px_ + x_ T Px < 0

(54)

Let this be a linear system, with the matrix A fix given by: x_ ¼ Ax

(55)

When placed in expression (54), this results in the following LMI: xT PAx + ðAxÞT Px < 0 xT PAx + AT xT Px < 0 x ðPA + A PÞ < 0 T

T

(56)

79

80

CHAPTER 3 Proportional resonance control and applications

Thus it is found that the inequality obtained in (56) is satisfied if, and only if, there is a positive symmetric P matrix that satisfies the following inequality: PA + AT P < 0

(57)

Lyapunov’s principle of stability ensures that the system will be stable at each operating point, with a satisfying positive symmetric P matrix being found by inequality (57). However, it is necessary to ensure that a single matrix P is obtained that satisfies inequality (57) so as to ensure stability across the whole field of polytopic uncertainty. Thus Lyapunov’s stability theorem can be extended to uncertain closed-loop systems with a state feedback gain given by u ¼ Kxa; this concept is known as quadratic stability [31]. Definition 4.2 An uncertain linear system is said to be quadratically stable if there is a state feedback K gain such that the closed-loop system is quadratically stable. The concept of quadratic stability ensures that the system will be stable across the range of parametric variations of a polytopic nature, provided that it is stable on all vertices of this polytopic. In order to check the stability of the closed-loop system given by Eq. (44), we rewrite this system according to Eq. (55), and we obtain the following equation:  e x_ ¼ Ae + Beu K e x

(58)

Using the concept of stability of Lyapunov given in inequality (57), the following inequality is obtained:   T P Ae + Beu K + Ae + Beu K P < 0

(59)

In order to eliminate nonlinearities between the matrices P and K in inequality (59), a variable substitution is performed, demonstrated in Bernussou et al. [32], resulting in the following quadratic stability theorem: Theorem 4.2 System (40) will be stable through a feedback control action of states u ¼ Ke x, with e x  ℝn, if and only if there is a positive symmetric matrix W  ℝn  n and a matrix P  ℝn  n such that

W >0 e + W AeT + Beu P + BeT PT < 0 AW u

(60)

with a state feedback gain given by K ¼ PW1. The solution of (60) only ensures that the closed-loop system is asymptotically stable, i.e., all closed-loop poles have a negative real part. However, in addition to ensuring stability, it is important to allocate the poles so that the response satisfies the specs over time. Fortunately, the project using LMIs easily allows the inclusion of several constraints, such as regional pole allocation.

3.4 Proposed multifrequency proportional resonant controller

3.4.5 Pole clustering regions As previously stated, in order to determine the feedback gain K, it is necessary to choose a priori the location of the closed-loop poles. In selecting these poles, consideration should be given not only to stability but also to performance, i.e., transient response. Additionally, practical constraints should be considered, such as actuator saturation. The principle of pole selection is summarized here [33, 34]: • •

•

To ensure the required convergence rate, the poles must maintain a certain distance from the imaginary axis. The imaginary parts of the poles are related to the resonant frequencies of the response. To reduce the number of oscillations, the imaginary parts must be reduced. Basically, the magnitude of the input increases with the magnitude of the poles. To limit the input (in this case the control action), the value of the poles cannot be too high.

Importantly, for applications with static converters, the value of ρ will always be limited by the minimum desired attenuation of the switching frequency. To guarantee the improvement in transient response, the poles should be chosen within the hatched region (regions representing limits on the system’s eigenvalues) shown in Fig. 3.10 [34]. Definition 4.3 Let D be a region in the complex plane. If there are square matrices L and M such that D ¼ fzC; fD ðzÞ < 0g

[z]

(61)

[z]

[z]

ρ [z]

−q

[z]

θ

σ

(a )

σ.

FIG. 3.10 Typical LMI regions.

(b) Disc .

(c ) Setor .

[z]

81

82

CHAPTER 3 Proportional resonance control and applications

D is called an LMI region and is usually denoted by D ðL; MÞ ; note that fD ðzÞ ¼ L + zM + zMT

(62)

called the characteristic function. According to Definition 4.3 we have the following matrices L and M for the regions shown in Fig. 3.13: •

Region σ allows the guarantee of an upper limit on settling time: D ðσ Þ ¼ fδi ℂ : ℜðδi Þ < σ, σ > 0, σℝg, L ¼ 2σ; M ¼ 1

•

Disc ρ allows the guarantee of a lower limit on settling time (prevents excessive control action):

D ðρÞ ¼ fδi ℂ : jδi + qj < ρ, ρ > 0, ρℝg, L ¼

•

(63)



ρ q 0 1 , M¼ q ρ 0 0

(64)

Sector θ is chosen as an upper bound on damping ratio ξ:



jℑðδi Þj sinθ cos θ  θ, θ½ 45∘ 63:43∘ , θℝ , L ¼ 0, M ¼ D ðθÞ ¼ δi ℂ : tan  cosθ sinθ jℜðδi Þj (65)

where pi, i ¼ 1, …, n are the closed-loop poles of the system. It is further possible to form LMI regions composed of the preceding regions, according to the following proposition. Remark. Proposition Let D 1 and D 2 be two LMI regions with characteristic functions fD 1 \ fD 2 , respectively. Therefore, D ¼ D 1 \ D 2 is also an LMI region whose characteristic function is fD ¼

fD 1 0 0 fD 2

(66)

3.4.6 Generalized Lyapunov theorem In defined LMI regions, it is possible to generalize the Lyapunov theorem to these regions as follows: Theorem 4.3 Let D be an LMI region whose characteristic function is fD ðzÞ ¼ L + zM + zMT

(67)

The matrix A of the system x ¼ Ax is said to be D -stable if and only if there exists a symmetric positive definite matrix P such that LP + MðAPÞ + MT ðAPÞT < 0

(68)

3.4 Proposed multifrequency proportional resonant controller

Saying that a system is D -stable means that the poles of the system lie within the region formed by the characteristic equation fD . Theorem 4.3 can be seen as a generalization of Lyapunov’s theorem. The proof of this theorem can be found in Duan and Yu [30]. The preceding theorem can also be used to obtain the state feedback matrix as follows. Substituting for the matrix A of Eq. (68) by the closed-loop matrix (A + BuK) given in Eq. (58) gives LP + MððA + Bu K ÞPÞ + MT ððA + Bu K ÞPÞT < 0

(69)

Again, the previous equation is not an LMI. As before, we can use the substitution of variables W ¼ KP, resulting in the following inequality: LP + MAP + MT PAT + MBu W + MT W T BTu < 0

(70)

This development results in Theorem 4.4. Theorem 4.4 The system x˙ ¼ Ax +Buu is stable by a state feedback u ¼ Kx if and only if there exist symmetric positive definite matrices P and W that satisfy LMI (70). In this case, the feedback matrix is given by K ¼ WP1

(71)

Finally, bearing in mind Proposition 4.5, using Theorem 4.4, and the matrices L and M given in Eqs. (63), (64), and (65), one can construct the region D ðσ, ρ, θÞ shown in Fig. 3.11, according to Theorem 4.5. ex + Beue Theorem 4.5 (LMI Regions) The closed-loop poles of the system e x_ ¼ Ae u are located in the region S(σ, θ, ρ), highlighted in Fig. 3.11, if and only if there exist symmetric positive definite matrices P and W such that the following LMIs are feasible: 

T



T

A P + PA + B u W + B u W T + 2σP < 0

FIG. 3.11 LMI regions D ðσ, ρ, θÞ .

(72)

83

84

CHAPTER 3 Proportional resonance control and applications     3  T  T   T T T T cos ð θ Þ A sin ð θ Þ A P + PA + B W + B W P  PA + B W  B W u u u u 6 7 6    7 < 0 4 5  T  T  T  T cos ðθÞ  A P + PA  B u W + B u W T sin ðθÞ A P + PA + B u W + B u W T 2

"

ρP

T



T

PA + W T B u



A P + BuW ρP

(73)

# 0, it is desired that: kGðsÞk∞ < ξ

(78)

3.5 Controller synthesis with robust D -stability-based LMI approach

The following theorem, adapted from Gahinet and Apkarian [36], guarantees a minimum level of disturbance attenuation. Theorem 4.6 The system in (40) is D with state feedback u ¼ Kxa and jjG(s)jj∞ = dt Lf
 diβ 1 > ¼ vβ
eβ
Riβ : > ; dt Lf

(4.1)

In Eq. (4.1), the three-phase measured load currents (ia, ib, ic) and back emf (ea, eb, ec) are converted to the αβ frame by the following transformation matrix: 2 1 1 32 3   fa 1

2 fα 7 6 ¼ 4 pffiffi2ffi p2ffiffiffi 5 4 fb 5 fβ 3 3 3 fc 0
2 2 Tabc=αβ |fflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl{zfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflfflffl}

(4.2)

103

104

CHAPTER 4 MPC of multilevel diode-clamped converters

where f denotes the generic variable such as voltage, current, back emf, etc. For a three-phase balanced system, fa + fb + fc ¼ 0; thus, fα becomes equal to fa. The coefficient 2/3 is arbitrarily added to the equation to preserve equal magnitudes for three- and two-phase variables after transformation [23]. For the motor drives application, the back emf can be estimated using the guidelines given in [19]. vα and vβ in Eq. (4.1) are stationary frame converter output voltages and can be obtained by applying the transformation matrix Tabc/αβ on the following three-phase voltages (with respect to the negative dc-rail N): 2

3 2 3 2 3 Sa ½1 vaN
 Sa ½m
1 4 vbN 5 ¼ ðvC1 Þ4 Sb ½1 5 + … + vC1 + … + vC1ðm
1Þ 4 Sb ½m
1 5 Sc ½1 Sc ½m
1 vcN

(4.3)

where vC1 and vC1(m
1) are dc capacitor voltages. Sa, Sb, and Sc represent the voltage levels of a three-phase converter. For a 5L-DCC, the relation between the Sx and switching states is summarized as demonstrated below: Sx ½0 Sx ½1 Sx ½2 Sx ½3 Sx ½4

if if if if if

9 sx1 sx2 sx3 sx4 ¼ 1 > > > sx1 sx2 sx3 sx4 ¼ 1 > = sx1 sx2 sx3 sx4 ¼ 1 > sx1 sx2 sx3 sx4 ¼ 1 > > > ; sx1 sx2 sx3 sx4 ¼ 1

(4.4)

where sx1, sx2, sx3, and sx4 are the switching signals of the phase x  {a, b, c}. The switching pairs (sx1 , sx1 Þ, ðsx2 , sx2 Þ, ðsx3 , sx3 Þ, ðsx4 , sx4 Þ are complementary in nature. Similar analysis can be carried out for other MLDCCs. The continuous-time model of load currents in Eq. (4.1) can be converted to the discrete-time model by approximating the derivative with the help of the forward Euler method, that is [10] di iðk + 1Þ
iðkÞ ¼ dt Ts

(4.5)

where Ts is the sampling time used in the discrete-time conversion and control. By substituting Eq. (4.5) into Eq. (4.1), the discrete-time model for the load currents can be obtained as 9 iα ðk + 1Þ
iα ðkÞ 1 > ¼ ½vα ðkÞ
eα ðkÞ
Riα ðkÞ > = Ts Lf  iβ ðk + 1Þ
iβ ðkÞ 1 > ¼ vβ ðkÞ
eβ ðkÞ
Riβ ðkÞ : > ; Lf Ts

The above expression can be simplified as iα ðk + 1Þ ¼ Kv½vα ðkÞ
eα ðkÞ 
Ki iα ðkÞ iβ ðk + 1Þ ¼ Kv vβ ðkÞ
eβ ðkÞ
Ki iβ ðkÞ

(4.6)

(4.7)

where Kv and Ki are discrete-time parameters: Kv ¼

Ts RT s and Ki ¼ 1
Lf Lf

(4.8)

4.3 Mathematical modeling

The variables in Eq. (4.7) can be expressed for a two-samples-ahead prediction as follows: iα ðk + 2Þ ¼ Kv½vα ðk + 1Þ
eα ðk + 1Þ 
Ki iα ðk + 1Þ iβ ðk + 2Þ ¼ Kv vβ ðk + 1Þ
eβ ðk + 1Þ
Ki iβ ðk + 1Þ:



(4.9)

For the two-samples-ahead prediction used in this work, vα(k + 1) ¼ vα(k) and vβ(k +1) ¼ vβ(k). The extrapolated back emf eα(k + 1) and eβ(k + 1) in Eq. (4.9) can be estimated using present and past sample values by the second-order Lagrange extrapolation [10]: eα ðk + 1Þ ¼ 3eα ðkÞ
3eα ðk
1Þ + eα ðk
2Þ eβ ðk + 1Þ ¼ 3eβ ðkÞ
3eβ ðk
1Þ + eβ ðk
2Þ:



(4.10)

The models in Eqs (4.1)–(4.10) correlate the output currents to the switching signals. With the appropriate selection of switching signals, the converter output currents can be regulated precisely. Note that the model given in Eq. (4.9) can be used for grid connection as well, where the load inductor and resistor are replaced by the inductive filter on the grid side and its internal resistance, and the back emf by the grid voltage (which is usually measured for synchronization).

4.3.2 Modeling of the DC capacitor voltages Another important requirement in the MLDCCs is to balance the dc capacitor voltages; otherwise, the semiconductor device voltage stress increases. To facilitate the discussion, a 5L-DCC is considered and its simplified dc-link model is represented in Fig. 4.3. The relationship between inverter branch currents (i1, i2, i3, i4) and dc capacitors current (iC1, iC2, iC3, iC4) is formulated as shown below: iC4 ¼ idc
i4 iC3 ¼ iC4
i3 iC2 ¼ iC3
i2 iC1 ¼ iC2
i1 :

9 > > > =

(4.11)

> > > ;

By solving the models in Eq. (4.11), the dc capacitors current is obtained as follows: 9 > > > =

iC4 ¼ idc
i4 iC3 ¼ idc
i4
i3

> iC2 ¼ idc
i4
i3
i2 > > ; iC1 ¼ idc
i4
i3
i2
i1 :

(4.12)

The positive dc-branch current idc does not contribute to the voltage drift of the capacitors; therefore, Eq. (4.12) can be simplified as [11] iC4 ¼
i4

9 > > > =

iC3 ¼
i4
i3 > iC2 ¼
i4
i3
i2 > > ; iC1 ¼
i4
i3
i2
i1 :

(4.13)

105

106

CHAPTER 4 MPC of multilevel diode-clamped converters

FIG. 4.3 Simplified representation of the power circuit model for a 5L-DCC.

The inverter branch currents (i1, i2, i3, i4) can be expressed in terms of load currents (ia, ib, ic) and MLDCC voltage levels as follows: i4 ¼ Sa ½4ia + Sb ½4ib + Sc ½4ic i3 ¼ Sa ½3ia + Sb ½3ib + Sc ½3ic i2 ¼ Sa ½2ia + Sb ½2ib + Sc ½2ic i1 ¼ Sa ½1ia + Sb ½1ib + Sc ½1ic :

(4.14)

By combining the models in Eqs (4.4) and (4.14), we have i4 ¼ sa1 sa2 sa3 sa4 ia + sb1 sb2 sb3 sb4 ib + sc1 sc2 sc3 sc4 ic i3 ¼ sa1 sa2 sa3 sa4 ia + sb1 sb2 sb3 sb4 ib + sc1 sc2 sc3 sc4 ic i2 ¼ sa1 sa2 sa3 sa4 ia + sb1 sb2 sb3 sb4 ib + sc1 sc2 sc3 sc4 ic i1 ¼ sa1 sa2 sa3 sa4 ia + sb1 sb2 sb3 sb4 ib + sc1 sc2 sc3 sc4 ic:

(4.15)

By substituting Eq. (4.15) in Eq. (4.13), the dc capacitors current can be related to the load currents as demonstrated below: 9 iC4 ¼ Ka4 ia + Kb4 ib + Kc4 ic > > = iC3 ¼ Ka3 ia + Kb3 ib + Kc3 ic iC2 ¼ Ka2 ia + Kb2 ib + Kc2 ic > > ; iC1 ¼ Ka1 ia + Kb1 ib + Kc1 ic:

(4.16)

The gains Kx4, Kx3, Kx2, Kx1 are a function of voltage level of the phase x  {a, b, c} as shown in Table 4.3. This approach can be summarized for an m-level DCC as follows: iCj ¼

X

x¼a, b, c

Kxj ix , j ¼ 1…m
1:

(4.17)

4.3 Mathematical modeling

The gains Kxj for phase x  {a, b, c} can be generalized as Kx1 ¼ sgn ð0
Sx Þ Kx2 ¼ sgn ð1
Sx Þ sgn ðSx Þ Kx3 ¼ sgn ð2
Sx Þ sgn ðSx Þ sgn ðSx
1Þ ⋮ ⋮ Kxðm
2Þ ¼ sgn ððm
3Þ
Sx Þ sgn ðSx Þ sgn ðSx
1Þ… sgn ðSx
ðm
4ÞÞ

(4.18)

Kxðm
1Þ ¼ sgn ððm
2Þ
Sx Þ sgn ðSx Þ sgn ðSx
1Þ… sgn ðSx
ðm
3ÞÞ

where sgn(.) is a signum function:

8 <
1 if x < 0 sgn ðxÞ ¼ 0 if x ¼ 0 : 1 if x > 0:

(4.19)

The relation between the dc capacitor voltages and current can be expressed in continuous time as vC1 dt ⋮

¼

iC1 C1 ⋮

(4.20)

vCðm
1Þ iCðm
1Þ ¼ dt Cðm
1Þ

where iC1 and iC(m
1) are the currents through the capacitors C1 and C(m
1), respectively. By applying the forward Euler approximation Eq. (4.5) to the continuous-time model in Eq. (4.20), the discrete-time model for dc capacitor voltages is obtained as follows [19]: vC1 ðk + 1Þ

¼

⋮

v C ðk Þ

+

⋮

vCðm
1Þ ðk + 1Þ ¼ vCðm
1Þ ðkÞ +

Ts iC1 ðkÞ C1 ⋮ Ts iCðm
1Þ ðkÞ:

(4.21)

Cðm
1Þ

The above expression can be generalized for the two-samples-ahead prediction horizon as vC1 ðk + 2Þ ⋮

¼

vC ðk + 1Þ

+

⋮

vCðm
1Þ ðk + 2Þ ¼ vCðm
1Þ ðk + 1Þ +

Ts iC1 ðkÞ C1 ⋮ Ts iCðm
1Þ ðkÞ:

(4.22)

Cðm
1Þ

These currents iC1 and iC(m
1) can be estimated using the measured load/grid currents (ia, ib, ic) and switching states of the converter [20]. The dynamics in Eqs (4.18)–(4.22) suggest that the dc capacitor voltages is also a function of switching signals. The proper selection of switching signals leads to accurate balancing of the dc capacitor voltages.

107

108

CHAPTER 4 MPC of multilevel diode-clamped converters

4.3.3 Modeling of the common-mode voltage The modeling of common-mode voltage (CMV) is different for odd-level (3L and 5L) and even-level (4L and 6L) DCCs. In odd-level DCCs, the CMV exists between the neutral point of the load/motor/grid (n) and the midpoint of dc capacitors (o) [24]. The CMV in odd-level DCC can be expressed in terms of switching states as follows: vcm ¼ vno ¼

m
1 1 X 1 X Sx
m + 1 : vCj m
1 j¼1 3 xa, b, c 2

(4.23)

For a 3L-DCC, the above expression can be simplified as vcm ¼ vno ¼

vC1 + vC2 ðSa
2Þ + ðSb
2Þ + ðSc
2Þ : 6 2

(4.24)

In even-level DCCs, the number of dc-link capacitors is odd and there exists no midpoint. The CMV is measured between the neutral point of the load/motor/grid (n) and the negative dc-rail (N) [16]: vcm ¼ vnN ¼

vaN + vbN + vcN 3

(4.25)

where vaN, vbN, and vcN are converter terminal voltages [refer to Eq. (4.3)]. The systems in Eqs (4.3), (4.23), and (4.25) depict that the CMV is related to the switching signals. In odd-level DCCs, the CMV can be reduced to zero value with the proper selection of switching signals. In the even-level DCCs, there exists no switching state which would achieve a zero CMV value [16], but it can be reduced to some extent with the optimal selection of switching states. Additional hardware such as the common-mode choke is required in even-level DCCs to reduce the CMV to zero.

4.4 Predictive current control scheme Based on the generalized model discussed before, a PCC scheme is presented in this section for an m-level converter (Fig. 4.4). As displayed, no PI controllers or modulators are used in the inner current control loop. The power flow in grid-connected and motor drives is from the dc-link to the ac-side of the converter, whereas the power flow in the generator case is opposite. The control scheme requires feedback measurements (i.e., vC1… vC(m
1), ia, ib, and ic), loads parameters (i.e., R and L), list of possible switching state combinations, discrete-time predictive model, and cost function minimization. The main control objective is to force load currents (ia, ib, and ic) to track the reference currents (i∗a, i∗b, and i∗c ) during all operating conditions with the balancing of dc capacitor voltages, switching frequency reduction, and CMV minimization. The PCC scheme is intuitive to understand and easy to implement in real time. The main parts of the PCC scheme are discussed as follows.

4.4 Predictive current control scheme

FIG. 4.4 Block diagram of the PCC scheme for a multilevel diode-clamped converter.

4.4.1 Reference currents calculation The dc bus voltage vdc(k) and three-phase load currents ia, ib, and ic are measured for use with the predictive model. Depending on the application, the reference currents i∗α(k) and i∗β(k) are calculated by the outer control loop. For example, the fieldoriented control (FOC) and voltage-oriented control (VOC) schemes are commonly used to calculate the reference currents for motor drives and grid-connected converters, respectively [23]. The reference currents are defined by the user to simplify the analysis. By changing the reference currents generation, the control discussed here can be simply extended to any application.

4.4.2 Extrapolation of reference currents The cost function deals with current error calculation in the (k + 2) sampling instant. To support this function, the reference currents (not load currents) are extrapolated from the (k)th instant to the (k + 2) sampling instant. The reference currents are extrapolated to the (k + 2) sampling instant by the second-order Lagrange extrapolation [10]: i∗α ðk + 1Þ ¼ 6i∗α ðkÞ
8i∗α ðk
1Þ + 3i∗α ðk
2Þ i∗β ðk + 1Þ ¼ 6i∗β ðkÞ
8i∗β ðk
1Þ + 3i∗β ðk
2Þ



(4.26)

109

110

CHAPTER 4 MPC of multilevel diode-clamped converters

4.4.3 Predictive model With the help of the measured dc capacitor voltages and the possible switching state combinations, the multilevel converter output voltages are predicted based on Eq. (4.3). The discrete-time model in Eq. (4.9) uses the measured load currents, discrete-time parameters (Kv and Ki), and converter output voltages in Eq. (4.3) to predict the future values of load currents, iα(k + 2) and iβ(k + 2). The measured load currents (ia, ib, and ic) and offline computed coefficients (Kx1…Kx1(m
1)) in Table 4.3 are used to calculate the dc capacitors currents iC1(k)…iC(m
1)(k). The future values of dc capacitor voltages, vC1(k + 2)…vC(m
1)(k + 2), are predicted based on estimated dc capacitors currents and measured dc capacitor voltages [see model in Eq. (4.22)]. The CMV for odd-level and even-level converters is estimated based on models in Eqs (4.23) and (4.25), respectively.

4.4.4 Cost function minimization The objective of the cost function minimization subsystem is to identify the minimum cost function value and corresponding switching state combination. All the control objectives are expressed as cost functions. By minimizing the cost functions during each sampling interval, the control goals can be met. The main objective for the DCC is to regulate the converter output currents which is expressed as i2  2 h gtrack ðkÞ ¼ i∗α ðk + 2Þ
iα ðk + 2Þ + i∗β ðk + 2Þ
iβ ðk + 2Þ :

(4.27)

The dc capacitor voltages balancing objective is expressed as another subcost function: X

gdc ðkÞ ¼ λdc

 2 vCj ðk + 2Þ
vCj + 1 ðk + 2Þ

(4.28)

j¼1, …, m
1

where λdc is the weighting factor for the dc capacitor voltages balancing task. Table 4.3 Relationship between switching states and coefficients of capacitors current for a 5L-DCC x  {a, b, c}. sx

sx1

sx2

sx3

sx4

vxN

Kx1

Kx2

Kx3

Kx4

4 3 2 1 0

1 0 0 0 0

1 1 0 0 0

1 1 1 0 0

1 1 1 1 0

vC4 + vC3 + vC2 + vC1 vC3 + vC2 + vC1 vC2 + vC1 vC1 0


1
1
1
1 0


1
1
1 0 0


1
1 0 0 0


1 0 0 0 0

4.4 Predictive current control scheme

The switching frequency minimization can be achieved by penalizing the subcost function as shown below: gswc ðkÞ ¼ λswc

X

swcx

(4.29)

x¼a, b, c

where λswc is the weighting factor for the switching frequency minimization. swcx represents the number of switch changes involved in phase x  {a, b, c}, and they can be calculated as shown in Table 4.4. Sx,op(k) is the optimal voltage vector in the previous sample. The CMV minimization objective is expressed by the following subcost function: gcm ðkÞ ¼ λcm jvcm j

(4.30)

where λcm is the weighting factor for CMV reduction. The final cost function combining the subcost functions in Eqs (4.27)–(4.30) is given as follows: gðkÞ ¼ gtrack ðkÞ + gdc ðkÞ + gswc ðkÞ + gcm ðkÞ

(4.31)

The whole design procedure is performed during the (k)th sampling interval, and the optimal switching state corresponding to the minimum cost function is applied to the MLDCC at the next sampling instant.

4.4.5 Selection of weighting factors The selection of values for the weighting factors is very important. Unfortunately, in state-of-the-art predictive control, no analytical or numerical formulas are available for the calculation of weighting factor values, but the guidelines given in [25] can be used. The main objective of the controller is to regulate the load current, and thus the λtrack value can be set to 1. The second requirement is balancing of dc capacitor voltages. A very high value for λdc will create perfect balance in the capacitors voltage, but with higher tracking errors and THD for the load currents. Similarly, a low value for λdc leads to a drift in the capacitors voltage, but very good regulation of load currents. A good compromise is to select λdc such that the drift in capacitors voltage is around 1% of nominal dc-link voltage. Using the per-unit method, the weighting factor can be calculated as λdc ¼

IB∗ : v∗dc

(4.32)

where I∗B and v∗dc are rated as reference current and dc-link voltage, respectively.

111

Table 4.4 Calculation of number of switch changes for x  {a, b, c}. Sx(k + 1) swcx

[0]

[1]

[2]

[3]

[4]

[5]

…

[m 2 1]

Sx,op(k)[0] Sx,op(k)[1] Sx,op(k)[2] Sx,op(k)[3] Sx,op(k)[4] Sx,op(k)[5] ⋮ Sx,op(k)[m 2 1]

0 2 4 6 8 10 ⋮ 2(m
1)

2 0 2 4 6 8 ⋮ 2(m
2)

4 2 0 2 4 6 ⋮ 2(m
3)

6 4 2 0 2 4 ⋮ 2(m
4)

8 6 4 2 0 2 ⋮ 2(m
5)

10 8 6 4 2 0 ⋮ 2(m
6)

… … … … … … ⋮ …

2(m
1) 2(m
2) 2(m
3) 2(m
4) 2(m
5) 2(m
6) ⋮ 0

4.4 Predictive current control scheme

The selection of λswc is specific to the applications involving the MLDCCs. For megawatt-level applications, the device switching frequency should be maintained below 1 kHz to allow proper heat dissipation [10]. From Table 4.4, it can be observed that the number of switch changes (swc) increases with voltage levels in DCC. To achieve a desired switching frequency value, the weighting factor λswc decreases with the increase in voltage levels in DCC. In odd-level MLDCCs, a minimal value of λcm should be selected such that the CMV becomes zero. In even-level MLDCCs, the selection criteria for λcm should consider the load current tracking error and THD limit imposed by the application.

4.4.6 Selection of prediction horizon (h) Many MPC applications are reported to use the one-sample-ahead prediction horizon (h ¼ 1) (see Fig. 4.5A), as this approach involves a lower computational burden [22]. To compensate for the computational delay caused by the digital signal processor, another approach based on a modified two-samples-ahead prediction horizon (h ¼ 2) can be used, and this method is given in Fig. 4.5B [26]. With this approach, the switching state which minimizes the cost function at the (k + 2) instant is selected and applied at the sampling instant (k). As shown in Fig. 4.5B, the same voltage vectors are used in the (k + 1) and (k + 2) predictions to reduce the number of calculations: vα ðk + 1Þ ¼ vα ðkÞ vβ ðk + 1Þ ¼ vβ ðkÞ:

(4.33)

FIG. 4.5 Prediction of control variables for a 4L-DCC: (A) classical one-sample-ahead prediction and (B) modified two-samples-ahead prediction.

113

114

CHAPTER 4 MPC of multilevel diode-clamped converters

4.4.7 Control algorithm The control algorithm with the two-samples-ahead prediction is shown in Fig. 4.6. The measured output currents and dc capacitor voltages are used by the predictive controller. The algorithm is initialized by setting the switching state number i to 0 and optimal g value to ∞. Then the algorithm enters the loop. The variables at the (k + 1) and (k + 2) instants are predicted using all the possible switching states of the converter. The predicted variables at the (k + 2) instant are evaluated by a cost function g(k). The optimal voltage vector in the previous sampling instant is used by the subcost function gswc(k). The switching states which produce a minimal cost function value gop are chosen and applied to the converter directly. It should be emphasized that the control scheme can be applied to any level DCC without any change in the software configuration, except the switching states definition in the initialization file.

FIG. 4.6 Two-samples-ahead PCC algorithm for an m-level DCC.

4.5 Simulation results

4.5 Simulation results To validate the PCC scheme for MLCDCCs, simulations are carried using the MATLAB/Simulink software with the parameters as indicated in Table 4.5. To simplify the analysis, low power converter parameters are used; however, the control scheme also works at the MW-power level without any software modification. The sampling time is considered as Ts ¼ 100 μs. A two-samples-ahead prediction horizon (h ¼ 2) is used and the control delay is ignored. The simulation results are presented for 3L- to 6L-DCCs under the same operating conditions. The output current tracking error (ei), dc capacitor voltages balancing error (evc), total harmonic distortion (THD), and average device switching frequency (fsw) are calculated according to the guidelines given in [10].

4.5.1 Steady-state analysis Fig. 4.7 shows the simulation results in steady state with rated reference currents [I∗ ¼ 10 A (rms) and 60 Hz] for three fundamental cycles. The dc-link voltage Vdc is set to 350 V. The mean value of dc capacitor voltages is Vdc/(m
1). The switching frequency reduction and CMV suppression are not included in the cost function. The load currents 3L to 6L DCCs track to their references with less steady-state error and the dc capacitor voltages is balanced with 1% error. The results indicate that the THD in output currents decreases with the increase in voltage levels of DCC. The tracking error is noticed to be higher during the peaks and valleys of the current waveform. The drift in dc capacitor voltage increases with the increase in voltage levels of DCC; however, the error is