Micro and Nanoelectronics Devices, Circuits and Systems: Select Proceedings of MNDCS 2022 9811923078, 9789811923074

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Lecture Notes in Electrical Engineering 904

Trupti Ranjan Lenka Durgamadhab Misra Lan Fu   Editors

Micro and Nanoelectronics Devices, Circuits and Systems Select Proceedings of MNDCS 2022

Lecture Notes in Electrical Engineering Volume 904

Series Editors Leopoldo Angrisani, Department of Electrical and Information Technologies Engineering, University of Napoli Federico II, Naples, Italy Marco Arteaga, Departament de Control y Robótica, Universidad Nacional Autónoma de México, Coyoacán, Mexico Bijaya Ketan Panigrahi, Electrical Engineering, Indian Institute of Technology Delhi, New Delhi, Delhi, India Samarjit Chakraborty, Fakultät für Elektrotechnik und Informationstechnik, TU München, Munich, Germany Jiming Chen, Zhejiang University, Hangzhou, Zhejiang, China Shanben Chen, Materials Science and Engineering, Shanghai Jiao Tong University, Shanghai, China Tan Kay Chen, Department of Electrical and Computer Engineering, National University of Singapore, Singapore, Singapore Rüdiger Dillmann, Humanoids and Intelligent Systems Laboratory, Karlsruhe Institute for Technology, Karlsruhe, Germany Haibin Duan, Beijing University of Aeronautics and Astronautics, Beijing, China Gianluigi Ferrari, Università di Parma, Parma, Italy Manuel Ferre, Centre for Automation and Robotics CAR (UPM-CSIC), Universidad Politécnica de Madrid, Madrid, Spain Sandra Hirche, Department of Electrical Engineering and Information Science, Technische Universität München, Munich, Germany Faryar Jabbari, Department of Mechanical and Aerospace Engineering, University of California, Irvine, CA, USA Limin Jia, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China Janusz Kacprzyk, Systems Research Institute, Polish Academy of Sciences, Warsaw, Poland Alaa Khamis, German University in Egypt El Tagamoa El Khames, New Cairo City, Egypt Torsten Kroeger, Stanford University, Stanford, CA, USA Yong Li, Hunan University, Changsha, Hunan, China Qilian Liang, Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX, USA Ferran Martín, Departament d’Enginyeria Electrònica, Universitat Autònoma de Barcelona, Bellaterra, Barcelona, Spain Tan Cher Ming, College of Engineering, Nanyang Technological University, Singapore, Singapore Wolfgang Minker, Institute of Information Technology, University of Ulm, Ulm, Germany Pradeep Misra, Department of Electrical Engineering, Wright State University, Dayton, OH, USA Sebastian Möller, Quality and Usability Laboratory, TU Berlin, Berlin, Germany Subhas Mukhopadhyay, School of Engineering & Advanced Technology, Massey University, Palmerston North, Manawatu-Wanganui, New Zealand Cun-Zheng Ning, Electrical Engineering, Arizona State University, Tempe, AZ, USA Toyoaki Nishida, Graduate School of Informatics, Kyoto University, Kyoto, Japan Luca Oneto, Department of Informatics, Bioengineering., Robotics, University of Genova, Genova, Genova, Italy Federica Pascucci, Dipartimento di Ingegneria, Università degli Studi “Roma Tre”, Rome, Italy Yong Qin, State Key Laboratory of Rail Traffic Control and Safety, Beijing Jiaotong University, Beijing, China Gan Woon Seng, School of Electrical & Electronic Engineering, Nanyang Technological University, Singapore, Singapore Joachim Speidel, Institute of Telecommunications, Universität Stuttgart, Stuttgart, Germany Germano Veiga, Campus da FEUP, INESC Porto, Porto, Portugal Haitao Wu, Academy of Opto-electronics, Chinese Academy of Sciences, Beijing, China Walter Zamboni, DIEM - Università degli studi di Salerno, Fisciano, Salerno, Italy Junjie James Zhang, Charlotte, NC, USA

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Trupti Ranjan Lenka · Durgamadhab Misra · Lan Fu Editors

Micro and Nanoelectronics Devices, Circuits and Systems Select Proceedings of MNDCS 2022

Editors Trupti Ranjan Lenka Department of Electronics and Communication Engineering National Institute of Technology Silchar Silchar, India

Durgamadhab Misra Department of Electrical and Computer Engineering New Jersey Institute of Technology Newark, NJ, USA

Lan Fu Department of Electronic Materials Engineering Australian National University Canberra, ACT, Australia

ISSN 1876-1100 ISSN 1876-1119 (electronic) Lecture Notes in Electrical Engineering ISBN 978-981-19-2307-4 ISBN 978-981-19-2308-1 (eBook) https://doi.org/10.1007/978-981-19-2308-1 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Preface

The book presents state-of-the-art research and developments in micro- and nanoelectronics devices, circuits and systems through select papers of 2nd Springer International Conference on Micro/Nanoelectronics Devices, Circuits and Systems (MNDCS-2022) held during January 29–31, 2022, virtually hosted by the Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India, in association with IEEE ED NIT Silchar Student Branch Chapter and IEEE Kolkata Section Nanotechnology Council Chapter. The high-quality contributions cover emerging trends in semiconductor materials and device technology, integrated circuit (IC) technology, system-on-chip (SoC), MEMS, and sensors for emerging applications. The contributed papers from India, Bangladesh, Italy, and USA are included in this book. The micro- and nanoelectronics devices include semiconductor device physics, quantum electronics, heterostructure transport, compact device modeling, nanowire LED, organic LED, MOSFET, OTFT, FinFET, TFET, HEMT, THz devices, photonics devices, UWB semiconductor materials, 2D materials, nanotechnology: nanowires, nanostructures, carbon nanotubes, graphene, flexible electronics, and high-efficiency solar cells: Perovskite, CZTS, Kesterite, and novel photovoltaic concepts as outlined in chapters on various emerging applications. From device tracks, the best paper was awarded to “Growth of Vertically Aligned TiO2 Nanowire Photo-anode for Developing Dye-sensitized Solar Cell.” The micro- and nanoelectronics circuits part includes analog VLSI circuits, digital VLSI circuits, mixed-mode VLSI circuits, bioelectronics circuits, circuit optimization techniques, reconfigurable circuits, HDL-based FPGA design, and semiconductor memories: DRAM and SRAM. They are listed in various chapters for emerging applications such as 5G technology, IOT, and biomedical electronics. From circuit tracks, the best paper was awarded to “Design and Analysis of CMOS based DRAM Cell Structures for High Performance Embedded System.” The micro- and nanoelectronics systems in various chapters include System on Chip (SoC), MEMS/NEMS, antennas, sensors, actuators, nanogenerators, energy harvesters (piezoelectric and MEMS based), micromachining, microfluidics, Labon-Chip, healthcare systems, embedded system design, biomedical systems, IoT, and v

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Preface

smart systems. From micro- and nanosystems tracks, the best paper was awarded to “Modulated Scattering Technique (MST) Devices Hybridized with RF-MEMS MicroSwitches for Next Generation IoT and 5G Smart Sensors.” Silchar, India Newark, USA Canberra, Australia

Trupti Ranjan Lenka Durgamadhab Misra Lan FU

Acknowledgements

The editors acknowledge the Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India, for providing the platform to organize 2nd Springer International Conference on Micro/Nanoelectronics Devices, Circuits and Systems (MNDCS-2022) held virtually during January 29–31, 2022. The editors also acknowledge IEEE ED NIT Silchar Student Branch Chapter and IEEE Kolkata Section Nanotechnology Council Chapter for their technical collaboration and providing international platform to organize MNDCS-2022. Acknowledgment also goes to all the authors and co-authors for their valuable and quality contributions and presentations in the MNDCS-2022. All the potential reviewers of MNDCS-2022 are also well acknowledged for their voluntary contributions for selecting good-quality manuscripts. The keynote speakers (Prof. Subramanian S. Iyer, UCLA, USA; Prof. Lan FU, The Australian National University, Australia; Dr. Jacopo Iannacci, Fondazione Bruno Kessler, Italy; Prof. Patrick Fay, University of Notre Dame, USA; Prof. Nowshad Amin, Institute of Sustainable Energy, Universiti Tenaga Nasional, Malaysia; Prof. Sanket Goel, BITS Pilani, Hyderabad campus, India; Prof. Neerish Revaprasadu, University of Zululand, South Africa; Prof. Luisa Petti, Free University of BozenBolzano, Italy; Prof. Sriram Krishnamoorthy, UCSB, USA; Prof. P. Susthitha Menon, Universiti Kebangsaan Malaysia (UKM), Malaysia; Prof. Merlyne De Souza, The University of Sheffield, UK) and the invited speakers (Dr. Ravi Teja Velpula, New Jersey Institute of Technology, Newark, USA, and Prof. Kamrul Alam Khan, Jagannath University, Bangladesh) of the MNDCS-2022 are highly acknowledged for their keynote and invited talks, respectively, on micro- and nanoelectronics devices, circuits, and systems. All the chairs/co-chairs and organizing committee of the MNDCS-2022 are also well acknowledged for the successful organization of the international conference. Finally, the editors acknowledge Springer Nature for being the publishing partner of the MNDCS-2022.

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Contents

Micro/Nanoelectronics Devices Development of Ni-Doped Zinc Oxide Films via Sol-Gel Synthesis . . . . . . Soumya Sundar Parui, Vipul Kheraj, Nidhi Tiwari, and Ram Narayan Chauhan

3

Modeling and Optimization Study of HIT-CBTSSe Tandem Solar Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Vallisree, Trupti Ranjan Lenka, and J. Mrudula

11

High-k Dielectric Influence on Recessed-Gate Gallium Oxide MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pharyanshu Kachhawa and Nidhi Chaturvedi

21

Design and Temperature Analysis of Si0.8 Ge0.2 -Based Extended Gate Gate-All-Around TFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Navaneet Kumar Singh, Rajib Kar, Durbadal Mandal, and Dibyendu Chowdhury

31

Optimization of Subthreshold Parameters of Graded-Channel Gate-Stack Double-Gate (GC-GS-DG) MOSFET Using PSO-CFIWA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dibyendu Chowdhury, Bishnu Prasad De, Sumalya Ghosh, Navaneet Kumar Singh, Rajib Kar, and Durbadal Mandal

41

A Comparative Study on Electrical Characteristics of Bulk, SOI, and DG MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Asutosh Patnaik, Narayan Sahoo, and Ajit Kumar Sahu

51

Optical Analysis of Far-Field Intensity on Organic Light-Emitting Diode to Reduce Surface Plasmon Losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . B. M. Chaya, Koushik Guha, M. Venkatesha, A. Vaishnavi, and K. Narayan

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Analog Performance of Normally-On Si3 N4 /AlN/β-Ga2 O3 HEMT . . . . . . Meenakshi Chauhan, Abdul Naim Khan, Raghuvir Tomar, and Kanjalochan Jena

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Modulation of Electronic Properties in Double Quantum Well-Based FET Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ajit Kumar Sahu, Narayan Sahoo, and Asutosh Patnaik

79

Comparative Analysis of Different Types of Gate Field Plate AlGaN/GaN HEMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pichingla Kharei, Achinta Baidya, and Niladri Pratap Maity

89

Advantages of Polarization Engineered Quantum Barriers in III-Nitride Deep Ultraviolet Light-Emitting Diodes: An Electron Blocking Layer Free Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ravi Teja Velpula, Barsha Jain, Samadrita Das, Trupti Ranjan Lenka, and Hieu Pham Trung Nguyen

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Investigation on Thermodynamic Properties of Novel Ag2 SrSn(S/Se)4 Quaternary Chalcogenide for Solar Cell Applications: A Density Functional Theory Study . . . . . . . . . . . . . . . . . . . . 103 Ashutosh Srivastava, Trupti Ranjan Lenka, Jesuraj Anthoniappen, and S. K. Tripathy Impact of Carcinogenic Benzene on Electronic Properties of Mnand Fe-Doped MoSe2 Monolayer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Neha Mishra and Bramha P. Pandey Growth of Vertical TiO2 -Nanowire Photoanode for Application of Dye-Sensitized Solar Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Biraj Shougaijam and Salam Surjit Singh Multiband Photodetection Using TiO2 Thin Film Deposited on Si Substrate Using E-beam Evaporation Technique . . . . . . . . . . . . . . . . . . . . . 131 Salam Surjit Singh and Biraj Shougaijam Evolution of Tunnel Field-Effect Transistor and Scope in Low Power Applications: A Detailed Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Ramesh Potharaju and Bijit Choudhuri Design and Analysis of Non-uniform Body with Dual Material FET-Based Digital Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Jagritee Talukdar and Kavicharan Mummaneni Performance Analysis of Metal–Ferroelectric–Insulator– Semiconductor Negative Capacitance FET for Various Channel Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Malvika, Bijit Choudhuri, and Kavicharan Mummaneni

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Impact of Tapered Dielectric on a Gallium Nitride Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) Towards Biosensing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Ananya Dastidar and Tapas Kumar Patra Carrier Transport and Radiative Recombination Rate Enhancement in GaN/AlGaN Multiple Quantum Well UV-LED Using Band Engineering for Light Technology . . . . . . . . . . . . . . . . . . . . . . . 187 Samadrita Das, Trupti Ranjan Lenka, F. A. Talukdar, Ravi Teja Velpula, and Hieu Pham Trung Nguyen Comparative Study of Electrical Performances of Bio-Electrochemical Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Monika Paul, K. A. Khan, and Bithi Paul Performance Evaluation of Silver-Doped CZTSe Kesterite Solar Cell with p+ -CZTSe as BSF Layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 A. Benisha Chris and Soumyaranjan Routray Design and Simulation of Si and Ge Double-Gate Tunnel Field-Effect Transistors with High-κ Al2 O3 Gate Dielectric: DC and RF Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Sambhu Prasad Malik, Ajeet Kumar Yadav, and Robin Khosla Performance Assessment of Electrostatically Doped Dual Pocket Vertical Tunnel Field-Effect Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Amit Bhattacharyya, Shaonli Paul, Papiya Debnath, Debashis De, and Manash Chanda A High Efficiency Class AB AlGaN/GaN HEMT Power Amplifier for High Frequency Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 Madhukar Saini and Trupti Ranjan Lenka The Anisotropy and Birefringence of Monolayer WS2 Semiconductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 R. Santosh, U. Nageswara Rao, M. Jagan Mohan Rao, Suresh Kumar Yattirajula, and V. Kumar Implementation of Zinc Sulfide (ZnS) as a Suitable Buffer Layer for CZTS Solar Cell from Numerical Analysis . . . . . . . . . . . . . . . . . . . . . . . . 257 Pratap Kumar Dakua and Deepak Kumar Panda The Effect of Quantum Well Base in GaAs-Based HBT . . . . . . . . . . . . . . . 265 Amit Kumar Jha and Manas Ranjan Jena Micro/Nanoelectronics Circuits Power and Area Trade-Off for Accuracy-Controlled Multiplier for Image Compression Using DCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Mukesh Kumar Sukla and Kabiraj Sethi

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Carry Select Adder Using Binary Excess-1 Converter and Ripple Carry Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 S. Arunakumari, K. Rajasekahr, S. Sunithamani, and D. Suresh Kumar Design and Analysis CMOS-Based DRAM Cell Structures for High-Performance Embedded System . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Prateek Asthana, Ritesh Kumar Kushwaha, Anil Kumar Sahu, and Neeraj Kumar Misra Optimized RTL Design of a Vending Machine Through FSM Using Verilog HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 Pulumati Chidananda Datta, Chappa Vinay Kumar, Rajan Singh, and Kavicharan Mummaneni Advances in Sensing Methodology for Resistive RAM . . . . . . . . . . . . . . . . . 317 Shaik Shaima, G. Jagaruthi, Sai Vandana, and E. Raghuveera Micro/Nanoelectronics Systems Optimization of RF MEMS Switch Using Linear Vector Quantization Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Lakshmi Narayana Thalluri, N. Britto Martin Paul, K. V. V. Kumar, Koushik Guha, S. S. Kiran, and N. D. Bhushana Babu Analysis of Micro-RF Switches Role in Reconfigurable Antenna Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Chilaka Dimpu Deepthi, Lakshmi Narayana Thalluri, and Koushik Guha Ultrahigh Sensitive Mercury Ion Detector Using AlGaN/GaN HEMT-Based Sensor and System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Shivanshu Mishra, Pharyanshu Kachhawa, Amber Kumar Jain, Kaushal Kishore, and Nidhi Chaturvedi Design and Simulation Analysis of a Piezoresistive Cantilever Beam for Low-Pressure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 M. Lakshmi Prasanna and V. R. Anitha A Novel General Purpose Switched Capacitor/Varactor Design Concept in RF-MEMS Technology for Emerging 5G/6G and Super-IoT Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Jacopo Iannacci, Girolamo Tagliapietra, Lakshmi Narayana Thalluri, and Koushik Guha Design and Analysis of MEMS Varactor for Ka Band Applications . . . . . 377 Anusmita Kakati, P. S. Ganaraj, Koushik Guha, and M. Kavicharan Design and Simulation of Parallel Plate-Comb Type Mems Capacitive Accelerometer Using COMSOL . . . . . . . . . . . . . . . . . . . . . . . . . . 389 C. S. Likhith, K. Asha, and Narayan Krishnaswamy

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Modulated Scattering Technique (MST) Devices Hybridized with RF-MEMS Micro-switches for Next Generation IoT and 5G Smart Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 Massimo Donelli, Mohammedhusen Manekiya, and Jacopo Iannacci Study of Metal-Porous GaN-Based 1D Photonic Crystal Tamm Plasmon Sensor for Detection of Fat Concentrations in Milk . . . . . . . . . . . 415 Abinash Panda and Puspa Devi Pukhrambam Reliability Analysis of Thermally Actuated MEMS Micromirror . . . . . . . 427 Vikram Maharshi and Ajay Agarwal RF-MEMS Technology and Beamforming in 5G: Challenges and Opportunities for a Pair with a Still Untapped Potential . . . . . . . . . . . 437 Girolamo Tagliapietra and Jacopo Iannacci Study the Impact of Green Synthesized Silver Nanoparticles on Bio-voltaic Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Bithi Paul, K. A. Khan, and Monika Paul Design, Simulation and Optimization of Circular, Square and Hexagonal Shaped Diaphragms for PMUT Application . . . . . . . . . . . 467 G. Bhargav and Akshdeep Sharma PKL Electrochemical Technologies for Electrical Energy Storage Using AgNPs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 K. A. Khan, Md. Akhtar-Uz-Zaman Shabuj, Md. Sayed Hossain, and Salman Rahman Rasel Design and Performance Analysis of Different MEMS-Based Piezoelectric Energy Harvesters for Energy Scavenging Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Bhaskar Jyoti Das, Osor Pertin, and Koushik Guha Kidney Disease and Its Replacement Techniques Utilizing MEMS-Microfluidics Technology: A Systematic Review . . . . . . . . . . . . . . . 505 Abhishek Zade, Jasti Sateesh, Koushik Guha, K. Srinivasa Rao, and K. Narayan Statistic Methods Encountering Simulations: An Application of the Response Surface Method to the Understanding of RF-MEMS Reconfigurable Power Attenuators . . . . . . . . . . . . . . . . . . . . . 521 Alessio Bucciarelli, Girolamo Tagliapietra, and Jacopo Iannacci

About the Editors

Trupti Ranjan Lenka is an Assistant Professor in the Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, India. He received a B.E. degree in Electronics and Communication Engineering from Berhampur University, Odisha, in 2000, M.Tech. degree in VLSI Design from Dr. A. P. J. Abdul Kalam Technical University, Lucknow, in 2007 and a Ph.D. degree in Microelectronics Engineering from Sambalpur University, Odisha, in 2012. He was Visiting Researcher at Helen and John C. Hartmann Department of Electrical and Computer Engineering, New Jersey Institute of Technology (NJIT), Newark, New Jersey, the USA, in 2019, and Solar Energy Research Institute of Singapore (SERIS), National University of Singapore (NUS), Singapore, in 2018. He received Distinguished Faculty Award by NIT, Silchar, in 2019. He has supervised 10 Ph.D. and 19 M.Tech. students. He has published 90 journal research papers, 10 chapters, and 47 conference papers to his credit and delivered 15 invited talks. His research interests include nanoelectronics: III-nitride heterojunction devices (HEMT, NW LED), solar photovoltaics, energy harvesting using MEMS, and nanotechnology. Currently, he is handling 03 sponsored research projects funded by DST-SERB (ASEANIndia Collaborative R&D project), and CSIR-EMR-II on the development of highefficiency perovskite solar cells, and Visvesvaraya YFRF by MeitY, Government of India. Durgamadhab Misra is a Professor in the Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey, the USA. He received the M.S. and Ph.D. degrees in electrical engineering from the University of Waterloo, Waterloo, ON, Canada, in 1985 and 1988, respectively. His current research interest areas are nanoelectronic/optoelectronic devices and circuits, especially in nanometer CMOS gate stacks and device reliability. He is a Fellow of IEEE and Distinguished Lecturer of IEEE Electron Devices Society (EDS), serving in the IEEE EDS Board of Governors. He is also a Fellow of the Electrochemical Society (ECS). He received the Thomas Cullinan Award from the Dielectric Science and Technology Division of ECS. He edited and co-edited over 50 books and conference proceedings in his field of research. He has also published more than 200 technical articles in xv

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About the Editors

peer-reviewed journals and international conference proceedings and delivered 125 invited talks. He supervised 20 Ph.D. students and 45 M.S. students. Lan Fu received her Ph.D. degree from the Australia National University (ANU) in 2001 and is currently a Full Professor at the Research School of Physics, ANU. She is Chair of IEEE Nanotechnology Council Chapters and Regional Activities Committee, Associate Editor of IEEE Photonics Journal, and Member of Editorial Board of Opto-Electronic Advances. She is also a Member of the Australian Academy of Science National Committee on Materials Science and Engineering, Secretary of the Executive Committee of Australian Materials Research Society (AMRS), and Australian Research Council College of Experts. Her main research interests include design, fabrication, and integration of optoelectronic devices (LEDs, lasers, photodetectors, and solar cells) based on low-dimensional III-V compound semiconductor structures including quantum wells, self-assembled quantum dots, and nanowires grown by metal-organic chemical vapor deposition (MOCVD).

Micro/Nanoelectronics Devices

Development of Ni-Doped Zinc Oxide Films via Sol-Gel Synthesis Soumya Sundar Parui, Vipul Kheraj, Nidhi Tiwari, and Ram Narayan Chauhan

Abstract The structural, optical, and magnetic characteristics of undoped and Nidoped ZnO [Zn(1−x) Nix O] films synthesised by the sol-gel technique were reported in this work. The films’ polycrystalline nature is confirmed by X-ray diffraction structural investigation. The intensity of the corresponding diffraction peak (101) increases with increasing Ni doping concentrations. The average crystallite size of the films ranges from 13 to 21 nm. The optical studies of ZnO film have shown a high transmittance (~80%) in the visible range with a large bandgap (E g ~ 3.23 eV). The optical bandgap is initiated to be reducing (E g ~ 1.75 eV) abruptly for the [Zn(1−x) Nix O] film. The vibrating sample magnetometer analysis exhibit the diamagnetic properties of the film after Ni doping. The Ni-doped ZnO films seem to be a viable option for solar applications. Keywords Zinc oxide · X-ray diffraction · UV-visible spectrometer · VSM · Spin coating technique

1 Introduction The curiosity of zinc oxide (ZnO) films has shown a significant development due to broad bandgap (E g ∼ 3.3 eV at 300 K) in semiconductor applications. Rare earthbased materials such as ZnO, CuO, and TiO2 have received a lot of attention since of their potential to be employed in a variety of applications such as spintronics, solar cells, optoelectronics, and photo-catalysts [1, 2]. Transition metals (Fe, Co, Ni, and S. S. Parui · V. Kheraj Department of Physics, Sardar Vallabhbhai National Institute of Technology Surat, Surat 395007, India e-mail: [email protected] N. Tiwari Energy Research Institute, Nanyang Technological University, Singapore, Singapore R. N. Chauhan (B) Department of Physics, National Institute of Technology Patna, Patna, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_1

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others) have recently been popular as doping components in ZnO materials due to their appealing optical ad photoluminescence properties. ZnO is an n-type semiconducting material with a hexagonal wurtzite structure that has an enormous exciton binding energy (60 meV) and spacious bandgap (3.37 eV). The nickel-doped zinc oxide (NZO) is a type of II-IV semiconductor that has numerous properties including chemical stability, large transparency, and high electron mobility plays an important role in optoelectronic devices [3]. The NZO thin films have great transparency and luminescence properties in the visible range [4]. There are several techniques used to make transition metal-doped ZnO thin films by utilising a variety of deposition processes, such as sol-gel spin coating method [5], pulsed laser deposition [6], chemical spray pyrolysis [7], co-precipitation [8], wet chemical method [9], radiofrequency magnetron sputtering [10], and electron beam evaporation [11]. The sol-gel spin coating is one of these approaches that have many advantages like easy to fabricate, low equipment cost, wide range of deposition area making the films with changing its thickness just adjusting some factors such as the temperature, time, rotational speed, and the density of the solution. In this paper, the sol-gel spin coating technique is utilised to fabricate the NZO films for investigation of the structural, optical as well as the magnetic properties.

2 Experimental The sol-gel spin coating procedure was used to create pure ZnO and NZO films on a glass substrate. To achieve the precursor solution, zinc acetate dehydrates [Zn(CH3 COO)2 , 2H2 O] and nickel nitrate hexahydrate [Ni (NO3 )2 , 6H2 O] were used as preliminary resources. The pure ZnO film was made by dissolving 2.1948 g of zinc acetate dehydrate in 10 ml ethanol and adding 1 ml mono-ethanolamine (C2 H7 NO, MEA) as solvent, and then stirring the transparent solutions at 80 °C for 60 min. The NZO precursor solution was arranged in a similar fashion. With the addition of MEA, [Ni (NO3 )2 , 6H2 O] was mixed with ZnO precursor solution in the molar ratio (X = 0.01, 0.03, 0.05). The glass substrates were washed with soap solution before deposition, and then distilled water and acetone were used to clean them progressively. For producing ZnO and NZO films, the final solutions were evenly deposited on rotating glass substrates at 3000 rpm for 60 s (Fig. 1). This procedure is rehashed numerous times in order to achieve a comparable thickness of the films. After each coating step, the films were excited at 150 °C for 5 min to separate the organic residues. Finally, using an MC 5438 Max-Thermo furnace, all of the films were annealed for an hour in an ambient environment at 450 °C. The X-ray diffraction has been used in a Bruker D8 advance using CuKα radiation (wavelength λ = 1.54056 Å) to evaluate the structural characteristics. The ultraviolet-visible spectrometer (Perkin Elmer Lambda 950) and vibrating sample magnetometer (Microsense EasyVSM 20130523-01) were used to appraise the characteristics of both optical and magnetic properties of the films.

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Fig. 1 Flow diagram of pure and NZO films, arranged by spin coating technique

3 Results and Discussion The X-ray diffraction patterns of NZO films with different Ni concentrations (X = 0, 0.01, 0.03 and 0.05) were depicted in Fig. 2. As per JCPDS card no 089-0510, all films exhibited polycrystalline nature with wurtzite type hexagonal structure. The

Fig. 2 X-ray diffraction of pure and NZO films with various Ni doping ratios

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peak intensity of (100), (002), (101), (102), (110), (103), and (112) planes varies with Ni doping concentrations. No other diffraction peaks of respective oxides were detected, showing a perfect Ni doping into ZnO lattice. A small shift towards the right is observed with increasing Ni concentrations due to the replacement of Ni with Zn in the lattice, inducing the change in the strain [12]. The (101) plane seems to have a higher intensity than the other planes, and the intensity of the (002) plane appears to be diminishing as Ni doping content increases. This result is consistent with Yilmaz et al. [13], who obtained comparable behaviour. With increasing Ni doping level, the average crystallite size improves from 13 to 21 nm, according to Scherrer’s formula [14]. This can be attributed to geometrical misalignment between the crystalline lattices of films and substrates at inter-phase boundaries [15]. The transmission spectra of NZO films are depicted in the 300–800 nm region (Fig. 3a). In the visible spectrum, ZnO has such a large transmittance (about 80%), but when the Ni doping concentrations increases, the transmittance drops gradually. The reduction in transmission at the band edge (i.e. increase in absorption) exhibited good crystallinity [16]. Jlassi et al. have shown a similar result of a gradual reduction in transmission with Ni doping [17]. The lattice defect grows in tandem with the rise in Ni doping concentrations. The replacement of Ni ions to the ZnO lattice improved absorption (Fig. 3b), leading to a reduction in transmittance as Ni doping content increased [18]. This enormous absorbance in the visible range makes it a promising candidate as an absorbing material for solar cell applications [19]. The bandgap was shifted from 3.23 eV to 1.75 eV, as demonstrated in Fig. 4a, b, respectively. Wahab et al. got a similar reduction in the bandgap while increasing the Ni content [20]. Kayani et al. informed that cumulation of defect states of Ni doping ions in the bandgap caused the drop in bandgap energy [21]. With increasing the crystallite size, the bandgap gradually decreased and vice-versa, which is in decent agreement with the literature [22, 23]. The fact that we were able to achieve a bandgap of 1.75 eV utilising a low-cost spin

Fig. 3 a The Transmission spectra, b absorption spectra of pure ZnO and NZO films, respectively

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Fig. 4 a Variation of (αhV)2 with hν of undoped film and b doping 0.01 at. % of Ni

coating deposition process makes this work unique. Due to the general sp-d coupling as electrons occupying 3d orbitals, the energy levels under the conduction bandgap of ZnO are generated by the abatement in bandgap caused by Ni doping ions, as observed by Anbuselvan et al. [24]. Magnetic measurements of the NZO films were executed at ambient temperature by using VSM (Fig. 5). The VSM measurements of NZO films revealed no magnetic loop, indicating that films are diamagnetic. This means that local-spin polarised electrons and conduction electrons have no exchange interaction [25].

Fig. 5 M-H plots of NZO films at room temperature

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4 Conclusion The undoped and NZO films were effectively developed by a basic sol-gel method supported with a spin coater system with different doping (Ni) concentrations (x = 0, 0.01, 0.03, 0.05). To acquire structural, optical, and magnetic characteristics, the deposited films were represented using X-ray diffraction, UV-visible spectroscopy, and VSM measurements. From XRD spectra, it has been observed that films are polycrystalline nature with wurtzite crystal structure. With increasing Ni doping percentage, the average crystallite size of the films improved, reaching from 13 to 21 nm. The optical spectra of ZnO film displayed a high transmittance (~80%) in the wavelength sort of 300–800 nm, and Ni doping significantly minimised the bandgap energy to 1.75 eV (x = 0.01), which confirms the applicability of the films as an absorber layer in solar cell applications. Acknowledgements This work is funded by DST / SERB (India) under grant number of ECR/2016/001937.

References 1. Ruhle S, Anderson AY, Barad HN, Kupfer B, Bouhadana Y, Rosh-Hodesh E, Zaban A (2012) All-oxide photovoltaics. J Phys Chem letters 3(24):3755–3764 2. Li BB, Xiu XQ, Zhang R, Tao ZK, Chen L, Xie ZL, Zheng YD, Xie Z (2006) Study of structure and magnetic properties of Ni-doped ZnO-based DMSs. Mater Sci Semicond Process 9(1-3):141–145 3. Liu E et al (2008) Ni doped ZnO thin films for diluted magnetic semiconductor materials. Curr Appl Phys 8(3–4):408–411 4. Farag AAM et al (2011) Photoluminescence and optical properties of nanostructure Ni doped ZnO thin films prepared by sol–gel spin coating technique. J Alloy Compd 509(30):7900–7908 5. Caglar Y et al (2009) Morphological, optical and electrical properties of CdZnO films prepared by sol–gel method. J Phys D: Appl Phys 42(6):065421 6. Liu Y, Zhao L, Lian J (2006) Al-doped ZnO films by pulsed laser deposition at room temperature. Vacuum 81(1):18–21 7. Owoeye VA et al (2019) Microstructural and optical properties of Ni-doped ZnO thin films prepared by chemical spray pyrolysis technique. Mater Res Express 6(8):086455 8. Raja K, Ramesh PS, Geetha D (2014) Synthesis, structural and optical properties of ZnO and Ni-doped ZnO hexagonal nanorods by Co-precipitation method. Spectrochim Acta Part A Mol Biomol Spectrosc 120:19–24 9. Rana AK et al (2016) Synthesis of Ni-doped ZnO nanostructures by low-temperature wet chemical method and their enhanced field emission properties. RSC Adv 6(106):104318– 104324 10. Siddheswaran R et al (2015) Reactive magnetron sputtering of Ni doped ZnO thin film: investigation of optical, structural, mechanical and magnetic properties. J Alloy Compd 636:85–92 11. Giri PK et al (2007) Studies on zinc oxide nanorods grown by electron beam evaporation technique. Synth React Inorg, Met-Org, Nano-Met Chem 37(6):437–441 12. Liu Y et al (2009) Influence of annealing temperature on structural, optical and magnetic properties of Mn-doped ZnO thin films prepared by sol–gel method. J Magnet Magnet Mater 321(20):3406–3410

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13. Yilmaz M (2014) Characteristic properties of spin coated ZnO thin films: the effect of Ni doping. Phys Scr 89(9):095802 14. Cullity BD (1956) Elements of X-ray diffraction. Addison-Wesley Publishing 15. Pandey B et al (2009) Synthesis of nanodimensional ZnO and Ni-doped ZnO thin films by atom beam sputtering and study of their physical properties. Physica E 41(7):1164–1168 16. Patil SK, Shinde SS, Rajpure KY (2013) Physical properties of spray deposited Ni-doped zinc oxide thin films. Ceram Int 39(4):3901–3907 17. Jlassi M et al (2014) Effect of nickel doping on physical properties of zinc oxide thin films prepared by the spray pyrolysis method. Appl Surf Sci 301:216–224 18. Bouaoud A et al (2013) Transparent conducting properties of Ni doped zinc oxide thin films prepared by a facile spray pyrolysis technique using perfume atomizer. Mater Chem Phys 137(3):843–847 19. Parui SS et al (2021) Zinc oxide and cupric oxide based thin films for solar cell applications. Mater Today: Proc 41:233–236 20. Grace Masih V, Kumar N, Srivastava A (2018) Diminution in the optical band gap and near band edge emission of nickel-doped zinc oxide thin films deposited by sol-gel method. J Appl Spectroscopy 84(6) 21. Kayani ZN et al (2015) Dip coated nickel zinc oxide thin films: structural, optical and magnetic investigations. Superlattices Microstruct 77:171–180 22. Bayram O et al (2019) Investigation of structural, morphological and optical properties of nickel-doped zinc oxide thin films fabricated by co-sputtering. J Mater Sci: Mater Electron 30(4):3452–3458 23. Ma Z et al (2020) Structural, electrochemical and optical properties of Ni doped ZnO: Experimental and theoretical investigation. Optik 219:165204 24. Anbuselvan D et al (2021) Room temperature ferromagnetic behavior of nickel-doped zinc oxide dilute magnetic semiconductor for spintronics applications. Physica E 129:114665 25. Yasmin A, Jakir Hossan Md, Ariful Islam Nahid Md (2018) Synthesis and characterization of Ni-doped ZnO thin films for diluted magnetic semiconductor by spin coating technique. In: 2018 International conference on computer, communication, chemical, material and electronic engineering (IC4ME2). IEEE, New York

Modeling and Optimization Study of HIT-CBTSSe Tandem Solar Cell S. Vallisree , Trupti Ranjan Lenka , and J. Mrudula

Abstract In the present work, HIT-CBTSSe tandem solar cell device model was developed using Silvaco TCAD simulator. As a first step, HIT and CBTSSe solar cells were modeled and validated. As a next step, the tandem structure is modeled using ITO as tunneling material between CBTSSe top cell and HIT bottom cells. Tandem structure is modeled and simulated, and it initially yields efficiency of 14.53%. The photon absorption profile and the external quantum efficiency are analyzed and the unequal absorption between the top and bottom modules is found to limit the efficiency. The model is optimized, and the maximum attainable efficiency is 22.2%. Keywords Device modeling · HIT · CBTSSe · Tandem solar cell

1 Introduction In the present era, multi-junction solar cells have gained interest and the recent research is focusing on the development of mechanically stacked and monolithic configurations for exceeding the Shockley-Queisser limit. Multi-junction solar cells were reported by several researchers with more than one junctions for improving the overall light absorption, open circuit voltage and hence the efficiency of the device [1]. Photovoltaic devices based on CBTSSe absorber has been reported by Shin [2]. Chen et al. reported solution processed process for the deposition of CBTS films with band gap of 2.01 eV [3] with power conversion efficiency of 1.72%. Huafei GuO has reported CBTS-based thin film solar cell by introducing a maskant layer [4] between the CBTS absorber and CdS buffer which has reduced the recombination and reported efficiency increase from 0.27 to 1.21%. Modeling study was carried out S. Vallisree (B) · J. Mrudula Department of Electronics and Communication Engineering, Geethanjali College of Engineering and Technology, Hyderabad, India e-mail: [email protected] T. R. Lenka Department of Electronics and Communication Engineering, National Institute of Technology, Silchar, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_2

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by Yousaf et al. [5] for efficiency enhancement of CBTS solar cell by introducing a back surface field as Cu2 O material and reported efficiency of 9.72%. Teymur et al. [6] has studied the material and optoelectronic properties of Cu2 BaSn(S,Se)4 for its suitability in solar cell applications. Triple junction solar cells with CBTSSe absorber in top cell, CZTS as middle cell absorber material and ACZTSe as bottom cell absorber material has been reported in [7]. A bipolar transistor architecture with CBTSSe/CdS/ACZTSe materials has been proposed by [8] where CBTSSe/CdS junction is similar emitter/base junction and ACZTSe acts as a collector for collecting the charge carriers generated and the optimized efficiency is found to be 21.63%. Crovetto et al. initially developed a CBTS solar cell with TaS2 as back contact and then the tandem solar cell was fabricated with wide band gap CBTSSe and Silicon as top cell and bottom cell absorber materials with a thin Ti(O,N) material between the sub cells which acts as a recombination and diffusion layer between the sub cells [9]. The tandem cells showed a higher V oc , however J sc and FF were low for the tandem device. Hence it becomes essential to carry out modeling studies for understanding the device physics and carrier transport mechanism in tandem solar cell. Si-CZTS tandem solar cell model has been developed and causes of low efficiency has been investigated in [10] and the carrier transport mechanism of Si/CZTS heterojunction model is developed and investigated in [11]. HIT-CZTS tandem solar cell has been modeled and performance analysis has been carried out in [12]. CBTSSe material having energy gap of 1.9 eV can act as excellent top cell absorber material for the designing of multi-junction solar cells. In the present study, HIT-CBTSSe tandem solar cell has been modeled and optimized to minimize the electrical and optical losses. The present work would help the fabrication researchers for optimization of various material and design parameters for maximizing light absorption and minimize the electrical losses in the tandem solar cells. The simulation methodology used for the modeling is described in Sect. 2 and the pertaining results and discussion is elaborated in Sect. 3 as follows.

2 Simulation Methodology The HIT-CBTSSe tandem solar cell has been modeled with HIT sub cell as bottom cell and CBTSSe cell as top module as shown in Fig. 1. Initially, the HIT sub cell was modeled and validated in [13]. The material parameters were obtained from [14–16] and dimensions of the CBTSSe device were taken from [2]. ITO is used as a tunneling material between the sub cells as it can act as conducting material and passes infrared portion of the light to the bottom cell [10]. The device is illuminated with AM 1.5 spectrum. Initially, the potential at every point in the mesh is evaluated by selfconsistent solution of poisson’s equation and carrier continuity equations [17]. SRH recombination and radiative recombination models are used appropriately depending on the type of the materials used for modeling the tandem structure.

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Fig. 1 CBTSSe-HIT tandem solar cell model

Table 1 Material parameters used for modeling the HIT-CBTSSe tandem solar cell Parameters

CBTSSe

ZnS

CdS

i-ZnO

AZO

Si

a-Si

Eg (eV)

1.9

3.58

2.42

3.37

3.37

1.12

1.7

Permittivity

5.4

9

10

9

9

11.8

11.8

Electron affinity (eV)

3.6

3.8

3.75

4.0

4.0

4.05

3.9

Conduction band DOS

5.64 × 1018

6.35 × 1018

1.8 × 1019

2.2 × 1018

2.2 × 1018

2.8 × 1019

1021

Valence band DOS

5.64 × 1019

6.03 × 1019

2.4 × 1018

1.8 × 1019

1.8 × 1019

1.04 × 1019

1021

Donor concentration (cm−3 )

–

1.1 × 1017

1.1 × 1017

1.5 × 1017

1× 1018

–

1020

Acceptor concentration (cm−3 )

5 × 1015

–

–

–

–

4.31 × 1015

1020

Electron mobility (cm2 /Vs)

30

230

160

100

50

990

5

Hole mobility (cm2 /Vs)

10

40

15

20

5

269

1

Thickness (µm) 0.1

0.1

0.1

0.08

0.3

180

0.005

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Transfer Matrix method is employed as the model comprises different layers. Optical generation rate is obtained by correlating the field amplitudes of both transmitted and reflected wave to the amplitude of incident wave as follows.     E(Z ) = E z j cos(ϕ) − i H z j sin(ϕ)/Y ( j)

(1)

H (Z ) = H (z i ) cos(ϕ) − i E(z i ) sin(ϕ)/Y (i )

(2)

G(z) =

λ |E(z)|2 α hc 2η

(3)

3 Results and Discussion The key parameters of HIT solar cell are extracted and the efficiency is found to be 17.45% [12]. The HIT-CBTSSe tandem structure initially yields efficiency of 14.18% which is lower than the HIT solar cell as shown in Table 2. The electrical losses could occur either due to the unequal amount of absorption of light by top and bottom modules or due to the carrier recombination which occurs throughout the tandem structure. Hence, the photon absorption profile and the external quantum efficiency were analyzed for top and bottom cells which are depicted in Fig. 2. Though the overall absorption of light is good enough, it is revealed that the electrical losses are high in the top and bottom modules.

3.1 Performance Analysis of HIT-CBTSSe Tandem Solar Cell From the above graphs in Fig. 1, even though the total absorption by the tandem structure is good enough, the external quantum efficiency of top and bottom cells were sufficiently low. This reveals that the electrical losses contribute mainly to the low efficiency of the device rather than optical losses. In Fig. 2a, the EQE is low for the wavelength range of 300 to 500 nm. The optical losses in CdS material is suggested to cause this low EQE. Hence, the thickness of CdS buffer is reduced to Table 2 Solar cell parameters extracted for HIT solar cell and HIT-CBTSSe tandem cell Model

J sc (mA cm−2 )

V oc (V)

FF (%)

η (%)

HIT solar cell

29.93

0.728

80.13

17.45

HIT-CBTSSe solar cell

10.3

1.79

76.86

14.18

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Fig. 2 a Photo generation rate of top and bottom cells and inset figure shows the photo generation rate in the top cell and b EQE graphs and total absorption profile of tandem structure in Fig. 1

30 nm to minimize the optical losses. Then the thickness of CBTSSe absorber is varied from 950 to 200 nm and the EQE graphs are extracted as shown in Fig. 3. For 950 nm thickness of CBTSSe absorber, the EQE graphs of individual cells was limited and there is considerable amount of overlapping portion of the spectrum. Upon reducing the thickness of CBTSSe absorber, the EQE of top and bottom cells have been improved and surprisingly the overlapping portion of the spectrum is reduced and efficient utilization of the spectrum is observed. The solar cell parameters are extracted as shown in Fig. 4. The short circuit current density increases with CBTSSe thickness and beyond 300 nm thickness, there is a reduction in current density as the current matching is disturbed again. The open circuit voltage increases with the reduction in CBTSSe thickness. Fig. 3 External quantum efficiency graphs of top and bottom cell for varying CBTSSe thickness

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Fig. 4 Solar cell parameters extracted for varying CBTSSe thickness

3.2 Photo Generation Rate and Recombination Profile The photon absorption rate for varying thickness of CBTSSe absorber in the top cell is shown in Fig. 5a and the inset figure shows the photon absorption in the

Fig. 5 a Photon absorption rate in the HIT-CBTSSe tandem structure with the inset showing the photon absorption in the top cell and the bottom cell interface

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top cell and the bottom cell near the interface region. On reducing the thickness of CBTSSe thickness, the overall photon absorption in the CBTSSe absorber decreases with the decrease in top cell absorber thickness and more number of photons are absorbed by the bottom cell. The recombination rate shows a drastic increase for CBTSSe thickness of 200 nm owing to the fact that a greater number of carrier generation in the bottom cell. Because of the finite diffusion length of the carriers, the recombination rate increases with the presence of a greater number of charge carriers in the bottom cell.

3.3 Electron and Hole Current Densities in Tandem Solar Cell The electron and hole current densities are analyzed for varying thickness of CBTSSe absorber. There is a clear mismatch in the current observed between the sub cells for CBTSSe thickness of 950 nm. On reducing the thickness of CBTSSe absorber from 950 to 200 nm, the current losses due to resistive heating is reduced at CBTSSe thickness of 300 nm and it again increases beyond 300 nm. From the solar cell parameters from Fig. 4 and electron hole current densities in Fig. 6, it is revealed that CBTSSe thickness of 300 nm is found to be the optimum thickness for top cell absorber material. With 300 nm CBTSSe thickness, the maximum efficiency obtained is 22.2%.

Fig. 6 a Electron (solid) and hole (dotted) current densities of tandem structure. b Electron and hole current densities in the top cell and near the interface

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4 Conclusion HIT-CBTSSe tandem solar cell was modeled by providing appropriate material parameters and optical constants from literature. Initially, the modeled tandem structure yielded efficiency of 14.53%. The photon generation profile and external quantum efficiency graphs revealed that though the overall absorption of light is huge enough, low EQE is observed in the top and bottom cells. This is because of the unequal absorption of light and the electrical losses which occur due to resistive heating of the device. From the simulation results, it is unveiled that the optimum thickness of CBTSSe is found to be 300 nm where the electrical losses are minimized, and the efficiency is found to be 22.2%.

References 1. Green MA, Dunlop ED, Hohl-Ebinger J, Yoshita M, Kopidakis N, Hao X (2021) Solar cell efficiency tables (version 58). Prog Photovoltaics Res Appl 29(7):657–667. https://doi.org/10. 1002/PIP.3444 2. Shin D, Zhu T, Huang X, Gunawan O, Blum V, Mitzi DB (2017) Earth-abundant chalcogenide photovoltaic devices with over 5% efficiency based on a Cu2 BaSn(S,Se)4 absorber. Adv Mater 29(24):1606945. https://doi.org/10.1002/ADMA.201606945 3. Chen Z et al (2018) Solution-processed trigonal Cu2 BaSnS4 thin-film solar cells. ACS Appl Energy Mater 1(7):3420–3427. https://doi.org/10.1021/ACSAEM.8B00514 4. Guo H et al (2018) Dual function of ultrathin Ti intermediate layers in CZTS solar cells: sulfur blocking and charge enhancement. Sol Energy Mater Sol Cells 175:20–28. https://doi.org/10. 1016/j.solmat.2017.09.052 5. Khattak YH, Baig F, Toura H, Beg S, Soucase BM (2019) Efficiency enhancement of Cu2 BaSnS4 experimental thin-film solar cell by device modeling. J Mater Sci 54(24):14787– 14796. https://doi.org/10.1007/S10853-019-03942-6 6. Teymur B et al (2021) Optoelectronic and material properties of solution-processed earthabundant Cu2 BaSn(S,Se)4 films for solar cell applications. Nano Energy 80:105556. https:// doi.org/10.1016/J.NANOEN.2020.105556 7. Saha U, Alam MK (2019) A heterojunction bipolar transistor architecture-based solar cell using CBTSSe/CdS/ACZTSe materials. Sol Energy 184:664–671. https://doi.org/10.1016/J. SOLENER.2019.04.044 8. Saha U, Alam MK (2018) Proposition of an environment friendly triple junction solar cell based on earth abundant CBTSSe/CZTS/ACZTSe materials. Phys Status Solidi – Rapid Res Lett 12(1):1700335. https://doi.org/10.1002/PSSR.201700335 9. Crovetto A et al (2019) TaS2 back contact improving oxide-converted Cu2 BaSnS4 solar cells. ACS Appl Energy Mater 3(1):1190–1198. https://doi.org/10.1021/ACSAEM.9B02251 10. Sivathanu V, Lenka TR (2021) Modeling and performance optimization of two-terminal Cu2 ZnSnS4 –silicon tandem solar cells. Int J Energy Res 45(7):10527–10537. https://doi.org/ 10.1002/ER.6540 11. Vallisree S, Sharma A, Thangavel R, Lenka TR (2020) Investigations of carrier transport mechanism and junction formation in Si/CZTS dual absorber solar cell technology. Appl Phys A Mater Sci Process 126(3):163. https://doi.org/10.1007/s00339-020-3343-9 12. Vallisree S, Lenka TR (2022) Performance analysis of HIT-CZTS tandem solar cell towards minimizing current losses. Lect Notes Electr Eng 781:227–236. https://doi.org/10.1007/978981-16-3767-4_21

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13. Lenka TR, Misra D, Biswas A (eds) (2021) Micro and nanoelectronics devices, circuits and systems: select proceedings of MNDCS 2021. In Micro and nanoelectronics devices, circuits and systems. Springer, Singapore 14. Saha U, Alam MK (2018) Proposition of an environment friendly triple junction solar cell based on earth abundant CBTSSe/CZTS/ACZTSe materials. Phys Status Solidi - Rapid Res Lett 12(1):1700335. https://doi.org/10.1002/pssr.201700335 15. Sivathanu V, Rajalingam T, Lenka TR (2018) Modelling of CZTS/ZnS/AZO solar cell for efficiency enhancement. In: 2018 3rd international conference on microwave and photonics, ICMAP 2018, 2018, vol 2018-January, pp 1–2. https://doi.org/10.1109/ICMAP.2018.8354643 16. Vallisree S, Thangavel R, Lenka TR (2018) Modelling, simulation, optimization of Si/ZnO and Si/ZnMgO heterojunction solar cells. Mater Res Express 6(2):025910. https://doi.org/10. 1088/2053-1591/aaf023 17. Silvaco Inc. (2010) Atlas user’s manual - device simulation software

High-k Dielectric Influence on Recessed-Gate Gallium Oxide MOSFETs Pharyanshu Kachhawa

and Nidhi Chaturvedi

Abstract This paper reports on the effects of different dielectrics on recessedgate gallium oxide MOSFETs in terms of analog and RF performance. Different gate dielectrics like SiO2 , Al2 O3 and HfO2 are considered as gate dielectric material, and their effects are analysed. High-k dielectric HfO2 provides better electrical performance compared to other dielectric materials. High-k dielectric offers good threshold voltage and better DIBL, output conductance, low leakage current with increased drain current response which can be traded-off with a bit increased intrinsic capacitance, GBW and low cut-off frequency. High-k dielectric-based gallium oxide MOSFETs show its potential applications in high-voltage, high-power switching applications with a good Ion /Ioff ratio of 6.75 × 109 . Keywords Gallium oxide · High-k dielectric · Gate capacitance · Output conductance

1 Introduction Gallium oxide is attracting much attention for the next-generation power electronics applications due to its material properties. Gallium oxide enjoys its beauty of ultra-wide band gap of 4.85 eV, very high critical electric field of 8 MV/cm and feasibility of high-quality crystal growth using conventional melt techniques [1, 2]. In addition to that, gallium oxide shows very high figure of merits such as baliga FOM and specially Johnson FOM (vsat × E c ) which is 3–8 times compared to SiC and GaN. These materialistic properties make gallium oxide a potential candidate for the high-voltage, high-power switching applications. High-performance power electronics applications requires high density devices with low-power consumption and better performances with miniaturized devices. These performances are limited by P. Kachhawa (B) · N. Chaturvedi CSIR-Central Electronics Engineering Research Institute, Pilani, India e-mail: [email protected] Academy of Scientific and Innovative Research (AcSIR), Ghaziabad, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_3

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Moore’s law where after a limit device dimensions can not be reduced further. Generally, gate length and gate dielectric thicknesses are scaled down to achieve the better performance which leads to nonlinearity in device with poor control. Hence, high-k dielectrics can be used for better performance which provides better interface charges and less trap density which helps in reducing leakage current with decreasing gate dielectric thickness [3–5]. From power electronics circuit point of view, generally power MOSFETs are operated in enhancement mode for their less complex circuit and fail-safe operation [6, 7]. Earlier, recessed-gate GaN HEMT-based devices are explored for the power electronics applications, which successfully demonstrate the normally off devices with high breakdown voltages greater than 600 V [8]. Later on, these devices are restricted up to range of 650 V due to its materialistic limitations. Hence, new generation material with high critical electric field limit (gallium oxide— 8 MV/cm) is explored for high-voltage operation due to its ultra-wide band gap which surpasses the existing wide band gap semiconductors like SiC and GaN. First gallium oxide-based device (MESFET) was demonstrated by Highashiwaki group from NICT, Japan, which attracted so much attention of researchers towards this material [9]. Gallium oxide-based depletion mode devices with good current densities were demonstrated with high breakdown voltages up to 2.3 KV [7, 10, 11]. Gallium oxide-based E-mode devices can be achieved by using various techniques like using thin channel layer, gate recess and unintentionally doped (UID) layer between channel and substrates which helps to deplete the channel easily [6, 12, 13]. Absence of p-doping limits the e-mode operation in gallium oxide devices, earlier gallium oxide-based normally off device was reported using wrap-fin gate which shows Vgs = 0 V and Vbr greater than 600 V, but this limits the current density to 1 mA/mm [14]. Other solutions to thin channel layer and UID layer require thick gate dielectrics to avoid merging of contacts (overlapping). Hence, symmetrical recessed-gate technique is used in this manuscript to deplete the channel and to achieve the normally off operation and to check the effects of different gate dielectrics on the performance of the device. In this work, a TCAD-based simulation of recessed-gate (E-mode) gallium oxide MOSFETs is analysed with different gate dielectrics. Various electrical performance parameters like drain current, Ion /Ioff ratio, transconductance, output conductance, DIBL, etc., are analysed. In addition to that, RF performance parameters like gate capacitance, cut-off frequency and gain-band width product are also presented.

2 Device Dimension and Simulation Set-up Gallium oxide-based MOSFETs simulations are carried out using Silvaco TCAD platform. The gallium oxide channel layer is doped with 1018 cm−3 , whereas source and drain regions are highly doped with a concentration of 3 × 1019 cm−3 for low contact resistance. The simulated structure consists of a source to drain distance (L sd ) of 20 µm , gate length of 2 and 100 µm gate width (as shown in schematic in Fig. 1).

High-k Dielectric Influence on Recessed-Gate Gallium Oxide MOSFETs

23

Fig. 1 Simulation schematic

Low field temperature-dependent mobility for mobility calculation, BOLTZAMAN statistics for carrier transport, FLDMOB for high field saturation and lattice self-heating models are considered for simulation. Newton solving method is used for numerical solutions with better convergence. The recessed-gate thickness for thick gallium oxide epilayer is being optimized in our earlier work [15]. Similarly, the device is gate recessed, and 15 nm active channel layer is left for enhancement mode operation. To analyse the effect of various dielectrics on analog and RF performance of the device different dielectrics like aluminium oxide (Al2 O3 , k = 10), silicon dioxide (SiO2 , k = 3.9) and hafnium oxide (HfO2 , k = 25) are used. Different gate dielectrics SiO2 , Al2 O3 and HfO2 are incorporated with their interface densities of 6×1011 , 2.3×1011 and 1.3×1011 /cm2 , respectively, with keeping same dielectric thickness of 10 nm [16–18].

3 Result Analysis Enhancement mode gallium oxide MOSFETs is simulated by recessing the gate with active channel thickness of 15 nm. The transfer characteristics are shown in Fig. 2 which shows good threshold voltage of 0.34 V for the high-k gate dielectric HfO2 which provides better functioning for the device. HfO2 provides better drain current density of 164 mA/mm and shows an improved drain current of 6.69 and 5.54% compared to Al2 O3 and SiO2 gate dielectrics as shown in Fig. 3. Ion /Ioff ratio is an important parameter for device characterization for switching applications which limits performance of the device. Generally, miniaturized devices lack with Ioff current or leakage current issues which can be improved by using high-k dielectric materials. HfO2 -based device reports a good Ion /Ioff ratio of 6.7E11 compared to Al2 O3 (1.3E11) and SiO2 (9.3 E10) which further reduces leakage current in the device. This shows its capability for digital logic circuit as well. Threshold voltage and off-current variations are represented in Fig. 4. Other important parameters sub-threshold swing (SS) and drain-induced barrier lowering (DIBL) are explored for gallium oxide-based device with different gate

24 Fig. 2 Transfer characteristics

Fig. 3 Drain characteristics

Fig. 4 Off-current and threshold voltage variation with different dielectrics

P. Kachhawa and N. Chaturvedi

High-k Dielectric Influence on Recessed-Gate Gallium Oxide MOSFETs

25

Fig. 5 Drain-induced barrier lowering (DIBL) values for different dielectrics

dielectric. As gate oxide tunnelling and hot carrier injection are common factors to leakage current, hence, these parameters should be suppressed for better performance of the device. Sub-threshold swing values of 98.25 mV/dec, 89.77 mV/dec and 71.53 mV/dec are found for SiO2 , Al2 O3 and HfO2 , respectively. Similarly, for DIBL a value of 237 mV/V, 146.9 mV/V and 134 mV/V is found for SiO2 , Al2 O3 and HfO2 , respectively, as represented in Fig. 5. High-k gate dielectrics shows reduced value for both SS and DIBL which improves gate control and shows its potential for highvoltage switching applications. Transconductance (gm ) and output conductance are important parameters which also determine the gain of the device. Higher transconductance improves carrier transport efficiency in the device which are recommended for analog applications. HfO2 dielectrics-based structure shows the highest gm of 24.1 mS/mm compared to Al2 O3 (20.8 mS/mm) and SiO2 (18.6 mS/mm) as presented in Fig. 6. Similarly, low output conductance is desired for better gain of the device. HfO2 shows less output conductance in sub-threshold region compared to other dielectrics (as shown in Fig. 7) so a trade-off can be created as per the required applications. Impact of the temperature on the devices performance can be related in the similar manner. As the temperature increases, the Ioff current increases due to the vibrations and carrier scattering which leads to the decrement in the Ion current. High temperature leads to low drain current which results into increased Vth of the device. Similarly, the high temperature increases thermal voltage and reduces Ion /Ioff which leads to increased sub-threshold swing (SS) for the device.

3.1 RF Performance Additionally, RF performance of recessed-gate gallium oxide-based devices with different gate dielectrics is also explored. Main important factors for frequency parameter include intrinsic gate capacitances (Cgs and Cgd ), cut-off frequency and GBW product [19, 20]. The intrinsic capacitances are important figure of merit and

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Fig. 6 Transconductance characteristics of the simulated structure

Fig. 7 Output conductance of the simulated device

being extracted using small signal AC analysis after obtaining DC solutions. These capacitances are extracted at single frequency of 1 MHz by ramping the gate voltage from −5 to 10 V. It is clearly indicating that the intrinsic capacitances increase with increasing high-k dielectric materials (shown in Figs. 8 and 9) which happens due to improved fringing field in case of high-k dielectric materials. Hence, high-k dielectric HfO2 shows highest capacitances of 0.2 pF/mm compared to Al2 O3 (0.17 pF/mm) and SiO2 (0.18 pF/mm) for gate to source capacitance and HfO2 (0.22 pF/mm) compared to Al2 O3 (0.2 pF/mm) and SiO2 (0.19 pF/mm) in gate to drain capacitance terms. Another factor which is used to analyse the RF performance of the device is cutoff frequency. Cut-off frequency of the device is a crucial FOM which is defined as the frequency corresponds to unity current gain of the device. Cut-off frequency is also calculated using expression f T = 2π(Cggsm+Cgd ) , where the current gain is unity for

High-k Dielectric Influence on Recessed-Gate Gallium Oxide MOSFETs

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Fig. 8 Gate capacitance and cut-off frequency

Fig. 9 Intrinsic capacitance (Cgd ) and GBW variation

gallium oxide devices. It is observed that cut-off frequency decreases with increasing k value of gate dielectrics (as shown in Fig. 8(inset)). This depends on overall total capacitance (Cgs + Cgd ) and peak transconductance value for the individual one. Hence, in case of HfO2 , a trade-off is required to be made for specific applications in terms of cut-off frequency and capacitance . Furthermore, gain bandwidth product (GBW) is also calculated as FOM for performance evaluation. High-k dielectric HfO2 shows better GBW than other dielectrics material like Al2 O3 and SiO2 (as shown in Fig. 9 (inset)). A consolidated Table 1 shows all extracted analog and RF performance parameters for different dielectrics. Overall, with this study, HfO2 gate dielectric shows better transconductance, with reduced gate leakage, and traded-off gate parasitic capacitances which promises its strong candidature for high-voltage switching applications. Furthermore, due to the absence of p-type dopants, gallium oxide-based devices are

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Table 1 Parameter extraction for different dielectrics for recessed-gate gallium oxide MOSFET Dielectrics

Threshold voltage (V)

Transconductance Sub(mS/mm) threshold swing (mV/dec)

DIBL (mV/V)

Gate capacitance (pF)

f T (GHz)

GBW (GHz)

SiO2

1.22

18.6

98.25

237

0.28

12.0

22.51

Al2 O3

0.95

20.8

89.77

146.9

0.29

9.52

24.6

HfO2

0.34

24.1

71.53

134

0.32

10.27

26.08

limited to unipolar operations. Low thermal conductivity of the gallium oxide material degrades the performance of the devices. This can be improved up to some extent in means by replacing the substrate with high thermal conductive substrates like silicon and SiC which will further reduce the overall cost of the device as well. This will improve the device reliability and performance as well.

4 Conclusion The presented work reports comparison of recessed-gate gallium oxide MOSFETs with different gate dielectrics based on analog and RF parameters. The optimized high-k dielectric H f O2 shows better response in terms of threshold voltage of 0.34 V, high drain current density of 164 mA/mm, Ion /Ioff ratio of 6.7E11, peak gm of 24.1 mS/mm, SS of 71.53 mV/dec, DIBL value of 134 mV/V and can be traded-off with intrinsic capacitance of 0.323 pF and cut-off frequency 10.27 GHz in comparison with low-k dielectrics like Al2 O3 and SiO2 . These improved performance parameters show its potential for high-voltage power switching applications. Acknowledgements This work was supported by the CSIR-SRF Direct Scheme at Central Electronics Engineering Research Institute [Grant Number-31/0007(11993)/2021-EMR-I, HCP-0012]. The authors would like to acknowledge Director, CSIR-CEERI, for providing the resources.

References 1. Pearton S, Yang J, Cary IV PH, Ren F, Kim J, Tadjer MJ et al (2018) A review of ga2o3 materials, processing, and devices. Appl Phys Rev 5(1):011301 2. Higashiwaki M, Jessen GH (2018) Guest editorial: the dawn of gallium oxide microelectronics, 060401 3. Suzuki K, Tanaka T, Tosaka Y, Horie H, Arimoto Y (1993) Scaling theory for double-gate SOI MOSFET’s. IEEE Trans Electron Dev 40(12):2326–2329. https://doi.org/10.1109/16. 249482Dec 4. Wong H-P (2002) Beyond the conventional transistor IBM J Res Devel 46(2.3):133–168. https:// doi.org/10.1147/rd.462.0133

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5. Ferain I, Colinge C, Colinge JP (2011) Multigate transistors as the future of classical metaloxide-semiconductor field-effect transistors. Nature 479:310–316. https://doi.org/10.1038/ nature10676 6. Chabak KD, McCandless JP, Moser NA, Green AJ, Mahalingam K, Crespo A et al (2017) Recessed-gate enhancement-mode β-ga2o3 mosfets. IEEE Electron Dev Lett 39(1):67–70 7. Chabak KD, Leedy KD, Green AJ, Mou S, Neal AT, Asel T, Heller ER et al (2019) Lateral β-Ga2O3 field effect transistors. Semicond Sci Technol 35(1):013002. https://doi.org/10.1088/ 1361-6641/ab55fe 8. Saito W, Takada Y, Kuraguchi M, Tsuda K, Omura I (2006) Recessed-gate structure approach toward normally off high-Voltage AlGaN/GaN HEMT for power electronics applications. IEEE Trans Electron Dev 53(2):356–362:013002. https://doi.org/10.1109/TED.2005.862708 9. Higashiwaki M, Sasaki K, Kuramata A, Masui T, Yamakoshi S (2012) Gallium oxide(ga2o3) metal-semiconductor field-effect transistors on single-crystal β-ga2o3 (010) substrates. Appl Phys Lett 100(1):013504. https://doi.org/10.1063/1.3674287 10. Tetzner K, Bahat E, Treidel OH, Popp A, Bin Anooz S, Wagner G, Thies A et al Lateral 1.8 kV β-Ga2O3 MOSFET with 155 MW/cm2 power Figure of merit. IEEE Electron Dev Lett 40(9):1503–1506. https://doi.org/10.1109/LED.2019.2930189 11. Mun JK, Cho K, Chang W, Jung HW, Do J (2019) 2.32 kV breakdown voltage lateral β-Ga2O3 MOSFETs with source-connected field plate. ECS J SolidState Sci Technol 8(7):Q3079. https:// doi.org/10.1149/2.0151907jss 12. Wong MH, Nakata Y, Kuramata A, Yamakoshi S, Higashiwaki M (2017) Enhancement-mode ga2o3 mosfets with si-ion-implanted source and drain. Appl Phys Express 10(4):041101. https:// doi.org/10.7567/APEX.10.041101 13. Zhou H, Si M, Alghamdi S, Qiu G, Yang L, Peide DY (2016) High performance depletion/enhancement-mode β-ga2o3 on insulator (gooi) field-effect transistors with record drain currents of 600/450 mA/mm. IEEE Electron Device Lett 38(1):103–106, 041101. https:// doi.org/10.1109/LED.2016.2635579 14. Chabak K, Moser N, Green A, Walker D, Tetlak S et al (2016) Enhancement-mode Ga2O3 wrap-gate fin field-effect transistors on native (100) β-Ga2O3 substrate with high breakdown voltage. Appl Phys Lett 109:213501. https://doi.org/10.1063/1.4967931 15. Kachhawa P, Chaturvedi N (2021) A simulation approach for depletion and enhancement mode in β-Ga2O3 MOSFET. IETE Tech Rev 1–9. https://doi.org/10.1080/02564602.2021.2004936 16. Zeng K, Jia Y, Singisetti U (2016) Interface state density in atomic layer deposited SiO2/βGa2O3 (-201) MOSCAPs IEEE Electron Device Lett 37:906–909 17. Zhou H, Alghmadi S, Si M, Qiu G, Peide DY (2016) Al2O3/β-Ga2O3 (-201) interface improvement through piranha pretreatment and postdeposition annealing. IEEE Electron Device Lett 37:1411–1414 18. Shahin DI et al (2018) Electrical characterization of ALD HfO2 high-k dielectrics on (201) β-Ga2O3 Appl. Phys Lett 112:042107 19. Pradhan KP, Mohapatra SK, Sahu PK, Behera DK (2014) Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectron J 45:144–151, 042107. https://doi.org/10.1016/j.mejo.2013.11.016 20. Yadavaz N, Chauhan RK (2020) Review-recent advances in designing gallium oxide MOSFET for RF application. ECS J Solid State Sci Technol 9:065010

Design and Temperature Analysis of Si0.8 Ge0.2 -Based Extended Gate Gate-All-Around TFET Navaneet Kumar Singh , Rajib Kar , Durbadal Mandal , and Dibyendu Chowdhury

Abstract In this paper, extended gate Gate-All-Around Tunnel FET (EG-GAATFET) is designed. Various temperatures like 300, 400, and 500 K are used for variation of gm , gm2 , gm3 , and cut-off frequency (f T ) with V gs . The temperature’s influence on I ON , I OFF , subthreshold slope (SS), I ON /I OFF , and threshold voltage (V th ) are also studied. The ON-current and transconductance (gm ) are found to be better for higher temperatures (T = 500 K). The leakage current, subthreshold slope, and current ratio are better for lower temperatures, whereas the threshold voltage (V th ) is improved for higher temperatures. The cut-off-frequency (f T ) is better at higher temperatures for lower gate voltage than better at higher gate voltage. Additionally, the designed device also shows better linearity performance at higher temperatures. Keywords Extended gate · GAA · Temperature analysis · Linearity

1 Introduction In the upcoming days, Moore’s law would be pertinent only for downscaling power consumption in consort with process size [1]. Shrinking the MOSFET’s size yields several problems related to leakage power, gate-induced-drain-lowering (GIDL), subthreshold slope (SS), drain-induced-barrier-lowering (DIBL), fabrication process, and numerous second-order effects [2]. These difficulties force the authors to explore new devices whose working principle differs from thermionic emission. For this, Tunnel Field-Effect-Transistor (TFET) has invented to change the traditional MOSFETs. TFETs hold SS < 60 mV/decade, lower leakage current, and reduce the SCEs owing to their inherent tunnelling barrier [3, 4]. The OFF-current (I d at V gs = 0 V) is low in TFET owing to band-to-band tunnelling. Instead, TFET N. K. Singh (B) · R. Kar · D. Mandal National Institute of Technology, Durgapur, West Bengal 713209, India e-mail: [email protected] D. Chowdhury Haldia Institute of Technology, Haldia, West Bengal 721657, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_4

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suffers from ambipolar current and a small ON-current. The ambipolar current can be lessened by deploying a drain region with a light doping profile and gate-drain overlapping [5]. The Gate-All-Around (GAA) offers improved electrostatic-control of channel that boosts the GAA characteristics by growing the inversion charge carriers [6, 7]. Integration of low-bandgap materials, Si0.8 Ge0.2 at source end reduces the tunnelling path, thus improving the ION [8]. In this paper, low-bandgap material towards source side and the charge plasma technique are employed to enhance the performance of EG-GAA-TFET. The article is prearranged into four sections. Device dimensions, device structure, and simulation methodology are discussed in Sect. 2. The temperature’s influence on linearity and electrical parameters is enlightened in Sect. 3. The second and third-order transconductance is considered for linearity analysis. These values must be as small as possible. The inferences of presented work is described in Sect. 4.

2 Device Design and Simulation Parameters The 2-dimensional view of extended gate Gate-All-Around Tunnel FET (EG-GAATFET) is revealed in Fig. 1. The GAA has a cylindrical gate electrode around the cylindrical channel. This structure helps to improve the gate controllability, which enhances the drain current. The extended gate further enhances the channel controllability. The low-bandgap material Si0.8 Ge0.2 at the source is used to improve performance of EG-GAA-TFET. Charge plasma technique and physical doping are used in the above-proposed device to provide appropriate doping. Additionally, the extended gate is used for better gate controllability. Spacer length at source and drain side is 10 nm and 15 nm, respectively. The height of both the spacers is 2 nm. The source, channel, and drain lengths are the same and are equal to 20 nm. The other structural dimensions are detailed in Table 1.

Fig. 1 Two-dimensional view of EG-GAA-TFET

Design and Temperature Analysis of Si0.8 Ge0.2 -Based … Table 1 Derive parameters of EG-GAA-TFET

33

S. No.

Device parameters

Values

Units

1

Source/Drain/channel length

20

nm

2

Spacer1 length

10

nm

3

Spacer2 length

15

nm

4

Source work function

5.88

eV

5

Gate work function

4.72

eV

6

Drain work function

3.9

eV

7

Silicon film thickness

10

nm

8

Spacer1/Spacer2 height

2

Source doping

10 11

9

nm

1×

1020

/cm3

Channel doping

1×

1019

/cm3

Drain doping

5 × 1018

/cm3

Fig. 2 Calibration of EG-GAA-TFET structure with the reference data [10]

Silvaco TCAD software is used to design and study the temperature’s influence on numerous parameters [9]. In simulation, numerous models used are bandgap narrowing model (BNG), Field dependent mobility (FLDMOB), Shockley-Read Hall recombination model (SRH), and Concentration-dependent mobility (CONMOB). The Kane model is considered to represent band-to-band tunnelling in the device. The calibration of the presented structure, EG-GAA-TFET, with the reference data [10] has been revealed in Fig. 2.

3 Results and Discussion In this paper, the authors have analysed the temperature’s influence on cut-offfrequency (f T ), third-order transconductance (gm3 ), and second-order transconductance (gm2 ) as discussed in Sect. 3.1. The variation of electrical parameters, e.g. I ON ,

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I OFF , I ON /I OFF , V th , and SS of the presented EG-GAA-TFET with temperature, is conferred in Sect. 3.2. Figure 3 express the drain current (I d ) variations with V gs for numerous temperatures. The plot shows that both I ON and I OFF increase with temperature, whereas the I ON /I OFF ratio decreases. As the temperature increases, the energy of the electrons increases, thus causing a higher drain current. Therefore, the circuit performance worsens at elevated temperature [11]. Figure 4 shows the transconductance (gm ) variation with V gs for different temperature values. The transconductance, which is calculated as a derivative of drain current with V gs at constant V ds , is the current driving capability of the device [12]. From the plot, it is clear that higher transconductance is achieved for a higher temperature value. A more considerable value of transconductance is preferred for any device. 10-5

T=300K T=400K T=500K

10-6 Drain current, I d (A)

Fig. 3 Temperature’s Influence on drain current in EG-GAA-TFET

10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -0.5

0.0

0.5

1.0

1.5

2.0

1.5

2.0

Gate Voltage, Vgs (V)

1.2x10-6 Transconductance, gm (A/V)

Fig. 4 Temperature’s Influence on transconductance (gm ) in EG-GAA-TFET

1.0x10-6

T=300K T=400K T=500K

8.0x10-7 6.0x10-7 4.0x10-7 2.0x10-7 0.0 -0.5

0.0

0.5

1.0

Gate Voltage, Vgs (V)

Design and Temperature Analysis of Si0.8 Ge0.2 -Based …

35

3.1 Temperature’s Influence on Linearity Parameters The second and third-order transconductance can be defined as gm2 = ∂ 2 Id /∂ Vgs2 and gm3 = ∂ 3 Id /∂ Vgs3 , respectively. A device to be linear, gm2 and gm3 must be tiny [13]. Figure 5 displays the gm2 variation with gate-to-source voltage for numerous temperature values. From the graph, it is obvious that gm2 is better for smaller temperature values. The peak value transconductance increases with temperature. Figure 6 displays the gm3 variation with V gs for the temperature values of 300, 400, and 500 K. The graph shows that gm3 is small for some of the gate voltages and significant for some other values of the gate voltages at a constant temperature. So, gm3 will be valid only for the gate voltage range for which it is lower. Figure 7 displays the variation of gate-capacitance (C gg ) with V gs for numerous temperature values. The gate capacitance (C gg ) is the totalling of gate-drain (C gd ) and gate-source capacitance (C gs ) [14]. The graph shows that gate capacitance upsurges with the rise in temperature, which improves the drive current (I ON ) as revealed in Fig. 3. 2.0x10-6

Fig. 5 Temperature’s Influence on gm2 in EG-GAA-TFET

-6

gm2 (A/V2)

1.5x10

T=300K T=400K T=500K

-6

1.0x10

5.0x10-7 0.0 -5.0x10-7 -0.5

0.0

0.5

1.0

1.5

2.0

1.5

2.0

Gate Voltage, Vgs (V)

Fig. 6 Temperature’s Influence on gm3 in EG-GAA-TFET

8.0x10-5 6.0x10-5

T=300K T=400K T=500K

gm3 (A/V3)

4.0x10-5 2.0x10-5 0.0 -2.0x10-5 -4.0x10-5 -6.0x10-5 -8.0x10-5 -0.5

0.0

0.5

1.0

Gate Voltage, Vgs (V)

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N. K. Singh et al.

Fig. 7 Temperature’s influence on gate capacitance in EG-GAA-TFET Cgg (F)

10-15

T=300K T=400K T=500K

10-16

10-17

-0.5

0.0

0.5

1.0

1.5

2.0

1.5

2.0

Gate Voltage, Vgs (V)

6x109 Cutoff frequency, f T (Hz)

Fig. 8 Temperature’s influence on cut-off frequency in EG-GAA-TFET

T=300K T=400K T=500K

5x109 4x109 3x109 2x109 1x109 0 -0.5

0.0

0.5

1.0

Gate Voltage, Vgs (V)

The cut-off frequency indicates the highest frequency that a discrete device can escalate. The cut-off-frequency can be stated as f T = gm /2πCgg [13, 15]. Figure 8 displays the cut-off frequency change with V gs for various temperatures. From the graph, it is palpable that the peak of f T is found at temperature 400 K. For T = 500 K, the cut-off frequency is higher for the lower value of V gs, and it is lower for higher V gs . Figure 9 demonstrates the EBD of the presented EG-GAA-TFET. The graph indicates that electrons at the source side in the valance band can tunnel and reach the conduction band of the device at the drain end.

3.2 Influence of Temperature on Device Electrical Performance The temperature’s influence on electrical performance indicators such as I ON , I OFF , I ON /I OFF , V th , and SS is analysed for various temperatures (T = 300 K, 350 K,

Design and Temperature Analysis of Si0.8 Ge0.2 -Based … Fig. 9 Energy-band-diagram (EBD) of proposed EG-GAA-TFET

37

1.0

Conduction Band Energy Valence Band Energy

Energy (eV)

0.5 0.0

e-

-0.5 -1.0 -1.5 -2.0 -2.5 0.00

0.01

0.02 0.03 0.04 0.05 Device Length ( in µm)

0.06

400 K, 450 K, and 500 K) as revealed in Fig. 10. Figure 10a displays the variation of ON-current with temperature. From the graph, it is obvious that I ON increases with temperature. The leakage current in a device is the drain current value at V gs = 0 V. The leakage in the device should be as small as possible. Figure 10b displays the plot of I OFF with temperature. From the plot, it is clear that leakage in the device increases with temperature. Figure 10c shows the trend of decreasing the current ratio with temperature. From Figure 10a, b, it can be noted that I ON increases linearly, and I OFF increases exponentially with temperature. Thus, the ratio I ON /I OFF decreases with temperature. From Fig. 10d, it is evident that threshold voltage is improved with increasing temperature, whereas Fig. 10e depicts that subthreshold slope is better for lower temperature value. The considerable difference in threshold voltage results in a tremendous variation in the drain current of the MOSFET.

4 Conclusion The presented structure, EG-GAA-TFET has excellent electrostatic-control of the channel owing to cylindrical Gate-All-Around. The extended gate further improves the control of the channel. A material with low-bandgap is considered at source end to enhance performance of the presented device. The temperature’s influence on linearity parameters gm2 and gm3 are analysed. The drain current and transconductance are improved for higher temperatures. The cut-off frequency is also evaluated, and higher f T is observed for higher temperatures. Additionally, the temperature’s influence is also studied on electrical parameters, e.g. I ON , I OFF , I ON /I OFF , V th , and SS. The analysis of presented structure ensures that current ratio and threshold voltage decrease with a temperature rise, whereas leakage and subthreshold slope increase with temperature.

38

N. K. Singh et al. 3.5x10-8

ION

(b)

6.0x10-13 IOFF (A)

2.5x10-8 -8

ION (A)

IOFF

8.0x10-13

(a)

3.0x10-8

2.0x10

1.5x10-8

4.0x10-13

-8

1.0x10

2.0x10-13

5.0x10-9 0.0 -5.0x10-9

0.0 300

350

400

450

300

500

350

3.5x105

1.50 Threshold voltage, Vth (V)

ION/IOFF

3.0x105

(c) ION/IOFF

2.5x105 2.0x105 1.5x105 1.0x105 4

5.0x10

0.0

300

350

400

450

Subthreshold slope (mV/decade)

450

500

(d)

1.40 1.35 1.30 1.25 1.20

500

Threshold voltage

1.45

300

350

Temperature (K)

110

400

Temperature (K)

Temperature (K)

400

450

500

Temperature (K)

Subthreshold slope

105

(e)

100 95 90 85 300

350

400

450

500

Temperature (K)

Fig. 10 Effect of temperature on a I ON b I OFF c I ON /I OFF d V th and e subthreshold slope in EG-GAA-FFET

References 1. Schaller RR (1997) Moore’s law: past, present and future. IEEE Spectr 34:52–59 2. Yu B, Chang L et al (2002) FinFET scaling to 10 nm gate length. In: Digest international electron devices meeting, pp 251–254. https://doi.org/10.1109/IEDM.2002.1175825 3. Kumar N, Mushtaq U, Amin SI, Anand S (2019) Design and performance analysis of dual-gate all around core-shell nanotube TFET. Superlattices Microstruct 125:356–364 4. Kumar MJ, Janardhanan S (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE Trans Electron Devices 60:3285–3290 5. Luong GV, Narimani K et al (2016) Complementary strained Si GAA nanowire TFET inverter with suppressed ambipolarity. IEEE Electron Device Lett 37:950–953

Design and Temperature Analysis of Si0.8 Ge0.2 -Based …

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6. Sachid AB, Lin HY, Hu C (2017) Nanowire FET with corner spacer for high-performance, energy-efficient applications. IEEE Trans Electron Devices 64:5181–5187 7. Liu L, Han Q et al (2017) Analog and RF analysis of gate all around silicon nanowire MOSFETs. In: 2017 Joint international EUROSOI workshop and international conference on ultimate integration on silicon (EUROSOI-ULIS), July 2017, Athens, Greece. https://doi.org/10.1109/ ULIS.2017.7962575 8. Kumar N, Amin SI, Anand S (2020) Design and performance optimization of novel core-shell dopingless GAA-nanotube TFET with Si0.5Ge0.5-based source. IEEE Trans Electron Devices 67:789–795 9. ATLAS Device Simulation Software (2019) Silvaco Int., Santa Clara, CA 10. Kumar N, Raman A (2019) Design and analog performance analysis of charge-plasma based cylindrical GAA silicon nanowire tunnel field-effect transistor. SILICON 12:2627–2634 11. Saha JK, Chakma N, Hasan M (2018) Impact of channel length, gate insulator thickness, gate insulator material, and temperature on the performance of nanoscale FETs. J Comput Electron 17:1521–1527 12. Do QT, Blekker K, Regolin I, Prost W, Tegude FJ (2017) High transconductance MISFET with a single InAs nanowire channel. IEEE Electron Device Lett 28:682–684 13. Singh NK, Kar R, Mandal D (2021) Design of Si0.45 Ge0.55 -based core–shell-type dual-material dual-gate nanotube TFET with source pocket technique. Appl Phys A. https://doi.org/10.1007/ s00339-021-04388-x 14. Singh NK, Kar R, Mandal D (2021) Simulation and analysis of ZnO-based extended-gate gatestack junctionless NWFET for hydrogen gas detection. Appl Phys A. https://doi.org/10.1007/ s00339-021-04421-z 15. Singh S, Singh S, Naugarhiya A (2020) Optimization of Si-doped HfO2 ferroelectric material-based negative capacitance junctionless TFET: impact of temperature on RF/linearity performance. Int J Mod Phys B 34(27):2050242

Optimization of Subthreshold Parameters of Graded-Channel Gate-Stack Double-Gate (GC-GS-DG) MOSFET Using PSO-CFIWA Dibyendu Chowdhury, Bishnu Prasad De, Sumalya Ghosh, Navaneet Kumar Singh, Rajib Kar, and Durbadal Mandal Abstract This work optimized the performance parameters of the Graded-Channel Gate-Stack Double-Gate (GC-GS-DG) MOSFET using a meta-heuristic technique. The meta-heuristic algorithm applied for this study is PSO with Constriction Factor and Inertia Weight Approach (PSO-CFIWA). The drawbacks of PSO are the premature convergence and stagnation problem. The PSO-CFIWA eliminates these drawbacks. Both the current at OFF-state (I OFF ) and subthreshold swing (SS) are considered in the formulation of overall objective/cost function (CF). The weighted sum approach method is used to obtain the overall CF. Compared with the previous literature, the PSO-CFIWA shows much better results in device design. Keywords Subthreshold swing · OFF current · DG MOSFET · PSO-CFIWA · Device parameter optimization

1 Introduction The Double-Gate MOSFET (DG MOSFET) is useful to reduce the short channel effects (SCEs). The device performance can be improved by channel engineering and gate engineering schemes, which lead to rapid growth in the semiconductor industry. The gate work function improved the analog/RF performances of the asymmetric DG MOSFET [1]. Considering channel engineering, the article [2] investigated the performance parameters of the symmetric DG MOSFET to reduce leakage power. Md. S. A. Faisal et al. proposed a DG MOSFET for high speed logic applications [3]. In [4], the Taguchi method is proposed to investigate the DIBL and signal-to-noise D. Chowdhury (B) Department of ECE, HIT, Haldia, India e-mail: [email protected] B. P. De School of Electronics Engineering, KIIT University, Bhubaneswar, India D. Chowdhury · S. Ghosh · N. K. Singh · R. Kar · D. Mandal Department of ECE, NIT, Durgapur, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_5

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ratio (SNR) for Vertical Double-Gate NMOS. Chiang et al. [5] developed an SCEdegraded NM (Noise Margin) model for the Junction-Less DGFET (JL-DGFET). Gao et al. [6] studied the behavior of CMOS logic gates and investigated the average DC power dissipation for JL-DGFET. The genetic algorithm is applied to study the swing factor of the DG MOSFET [7]. F. Djeffal et al. have explored the subthreshold behavior of GC-GS-DG MOSFET in [8]. A genetic algorithm called MOGA is used to study the electrical performances of GC-GS-DG MOSFET in [9]. Vimala et al. [10] studied the electrical parameters of gate-all-around (GAA) MOSFETS. Adak et al. [11] computed the different subthreshold parameters of GC-GS-DG MOSFET by varying the thickness of High-K oxide. Hasan et al. [12] studied the performance of a DG MOSFET based on GaN to mitigate the SCEs. An analytical model is proposed for a generic DG MOSFET [13] to determine potential distribution at the gate overlap and underlap regions. Narendar et al. [14] compared the analog/RF performance parameters of the GC-GS-DG MOSFET with dual-material in gate. Ramezani et al. [15] introduced an insulator packet (IPs) in the structure of DG MOSFET at the source and drain side junction which one impacts on carrier diffusion and lateral electric field at the channel, as a result improved the SCEs and leakage current than the conventional structure. Mendiratta et al. [16] proposed an asymmetric Junction-less DG MOSET with the heavily doped electron pocket to investigate the sensing behavior to detect the biomolecules. Gowthaman et al. [17] has developed a capacitive model for the Cylindrical Surrounding DG MOSFET to analyze the performance and also improved the SCEs applying high-k dielectric as a gate oxide. Pakaree et al. [18] constructed a differential amplifier using a DG MOSFET and analyzed the small signal behavior which is improved than the other MOSFETs devices. Chakrabarti et al. [19] also investigated the development of the SCEs for fully depleted dual-material DG MOSFET by the variation of the doping concentration, gate-to-source voltage and thickness of the high-k dielectric. Ramezani et al. [20] proposed a Junction-less DG MOSFET with n+ charge plasma at the source and drain side which one improved the various electrical parameters than the conventional MOSETs. As a result of superior electric fields the leakage current and SCEs are minimized. Darwin et al. [21] investigated the various electrical parameters for the DMDG MOSFET and also analyzed the electric field applying the parabolic approximation technique to improve the SCEs and off-state current. Here, the optimization of subthreshold parameters for the GC-GS-DG MOSFET (as depicted in Fig. 1) is carried out using the PSO-CFIWA [22, 23]. The primary focus of this work is to minimize the objective functions, I OFF and SS. Both the functions will be simultaneously optimized and considered multi objectives while formulating the problem. The rest of this paper is arranged as follows: the cost function formulation is discussed in the next section. A brief of the PSO-CFIWA algorithm is discussed in Sect. 3. Simulated outcomes are described in the next section. Lastly, a conclusion is drawn in Sect. 5.

Optimization of Subthreshold Parameters of Graded-Channel …

43

Fig. 1 A cross-sectional view of the GC-GS-DG MOSFET

2 Subthreshold Parameters of the Device In this part, a compact model for the subthreshold behaviors of the considered device described. The Subthreshold Swing (SS) of the GC-GS-DG MOSFET can be represented as follows S = S0 [1 + ΔS]−1

(1)

where at room temperature, the value of S 0 is 60 mV/dec. Here, ΔS is a degradation coefficient of SS [8, 9] and can be found using as follows ( ( ) ( ) ( )) ( ) 1 − sinh Lλ γ + sinh xmin 1λ−L 1 (α + β) − sinh Lλ1 − sinh L−L λ ( / ) ΔS = (2) sinh L 1 λ x ( ) ) (L) ( ( ) 1 sinh( min λ ) 1 . cosh , γ = , With α = sinh Lλ1 . cosh L 1λ−L , β = sinh L−L λ λ sinh( Lλ ) / εSi .toxeff .tSi . where L represent channel length and length L 1 is of the Region I, t1 λ= 2.ε1 is the oxide thickness (εox = ε1 ) layer, t2 is the high-dielectric layer thickness (ε2 ), toxeff = t1 + εε21 t2 is the thickness of effective oxide, and the surface potential of the device at its minimum value is represents by xmin 1 . The subthreshold current density in the weak inversion region can be denoted [8, 9] by.

Jn (y) = q Dn

) n min (y) ( 1 − e−Vds / Vt L

(3)

where V t represent the thermal voltage, and diffusion constant represents by Dn, n min (y) is the carrier concentration at minimum potential along channel and drain to source voltage represent by V ds .

44

D. Chowdhury et al.

By integrating (3) with respect to the thickness of silicon film, the current at subthreshold region can be determined using (4) Isub = 2

) ( )) Vt ( ( ψmin / Vt K1 e − eψs min / Vt + K 2 eψmin / Vt − eψs min / Vt Es

(4)

where E S denotes a constant electric field and is expressed as E s = / at oxide and 2(ψmin − ψs min ) tsi , ψs min = ψmin (xmin , 0) is the minimum potential / ) ( silicon interface, the minimum potential denoted as ψmin = ψ xmin , tsi 2 . K 1 and / )( ) ( K 2 are two constant and denoted as K 1 = qμn W Vt n i2 L 1 NAL 1 − e−VP / Vt and / )( ) ( K 2 = qμn W Vt n i2 (L − L 1 )N AH 1 − e−(Vds −VP )/ Vt . The doping levels of Region I and II are indicated by N AL and N AH , respectively, and W represents the device width. The OFF-state current in the subthreshold region is given by [8, 9] IOFF = Isub |Vgs =0 .

(5)

The optimization problem focusing multi-objective is constructed as: Minimize I OFF and ΔS The weighted sum approach method is used to obtain the overall CF and is presented as [9] CF = w1 |ΔS| + w2 IOFF

(6)

where w1 and w2 are the weight functions. For the device designer, both the I OFF and ΔS are equally important to get higher gain, lower power dissipation and high speed. Hence, both w1 and w2 are considered as 0.5. The input vector, M, of variables is constructed as follows: ) ( X = tsi , t1 , t2 , ε2 , L , L 1 , NAH , NAL , Vds , Vg , ϕMS . The parameters such as drain induced barrier lowering (DIBL), threshold voltage roll-off (V roll-off ) and threshold voltage (V th ) have high impacts on the device performance.

3 Evolutionary Techniques Employed PSO is discussed in the literature [22]. A modified PSO called PSO-CFIWA [23] is utilized for the evaluation process. Through the trial and error method, the controlling parameters of the PSO-CFIWA are set and are shown in Table 1.

Optimization of Subthreshold Parameters of Graded-Channel … Table 1 Control parameters OFPSO-CFIWA

A.

B.

Parameters

45 PSO-CFIWA

Population size (p)

120

Optimization problem dimension (q)

11

positive weighting factors (C1 )

2.05

Positive weighting factors (C2 )

2.05

Constriction Factor (CFa )

0.73

The maximum value of weighting function (wmax )

1.0

The maximum value of weighting function (wmin )

0.4

Iteration cycle

500

Particle Swarm Optimization (PSO) PSO is a well-known evolutionary technique having a wide range of applications. Eberhart et al. [24] proposed the PSO concept based on bird flocking/fish schooling. PSO is efficient in optimization and easy to implement. PSO has less chance to entrap by local optima. Each bird knows its best value so far (pbest). Each bird knows the best value in the group (gbest) so far. The velocity and position vectors are updated as ) ( Vi(k+1) = w × Vik + C1 × rand1 × pbestik − X ik ( ) + C2 × rand2 × gbest k − X ik

(7)

X i(k+1) = X ik + Vi(k+1)

(8)

where w is the weighting function, C1 and C2 , involved in the second and third term, are two factors used for weighting; rand1 and rand2 denotes two random numbers lies within [0, 1]; V and X are the velocity and position, respectively; subscript i indicates the value corresponding to ith bird and superscript k indicates the value corresponding to kth iteration; pbest is the personal solution and gbest is the group best solution. Also, superscript (k + 1) indicates the updated solution. PSO-CFIWA The equation of the velocity is modified in PSO-CFIWA [22, 23] as ) ( Vik+1 = C Fa × (wk+1 ∗ Vik + C1 ∗ rand1 ∗ pbesti − X ik ) ( + C2 ∗ rand2 ∗ gbest − X ik ) The CFa denotes constriction factor and is expressed as

(9)

46

D. Chowdhury et al.

2 | CFa = | √ | | |2 − φ − φ 2 − 4φ |

(10)

where φ = C1 + C2 , and φ > 4. ( ) At (k + 1)th iteration, the inertia weight wk+1 is wk+1 = wmax −

wmax − wmin × (k + 1) kmax

(11)

where wmin = 0.4; wmax = 1.0; kmax = Maximum iteration cycles. According to (8), each bird is updating their position. The solution is improved in PSO-CFIWA qualitatively.

4 Discussions of Simulation Results Here, the subthreshold parameters are optimized of the considered device using the synthesis performed geometrically. The overall optimization is performed for the cost function (CF) using the PSO-CFIWA algorithm. The PSOCFIWA is executed using MATLAB R2007b and ran on Intel Core i5-8250U [email protected] GHz. The structural parameters (tsi , L , L 1 , t1 , t2 ) and the electrical param( ) eters ε2 , Vds , Vg , NAH , NAL , ϕMS are optimized using the PSO-CFIWA. To achieve the best design parameters set, the proposed algorithm is performed for the 50 times. The optimized parameters values are given in Table 2. The GC-GS DG MOSFET structure is designed using these optimal values in SILVACO TCAD. The simulated outcomes are presented in Figs. 2, 3 and 4. Figure 2 reveals the output current versus gate voltage characteristics in log scale at V ds = 0.5 V. From this curve, parameters, current at both off-state and on-state and subthreshold swing is achieved. The threshold voltage is found from the I D versus V gs curve which is displayed in Fig. 3. Figure 4 displays the device transfer characteristics for different V ds . Figure 5 also shows the transfer characterizes, but for the different channel length. It can be observed that the current is increased when the channel length is decreased. PSOCFIWA-based design results in t si = 5 nm, t 1 = 0.25 nm, t 2 = 0.30 nm, L = 22 nm, ε2 = 25, Fm = 4.63 eV, N AH = 2.7752 × 1019 cm−3 , N AL = 9.9861 × 1017 cm−3 , V ds = 0.5 V, V gs = 1 V, I OFF = 1.94 × 10−12 A/µm, ΔS = 0.0011167, CF = 5.58 × 10–4 , V th = 0.6183 V, V roll-off = −0.3180 V, and DIBL = 12.51 mV/V. Figure 6 demonstrates the convergence of the proposed algorithm while evaluating the optimal values and it is found that the execution time is 25 s. The TCAD simulation outcomes are reported in Table 2. From Table 2, it can be seen that in this work the channel length is optimized and also in case of channel thickness compared to the literature [9, 11, 14]. The PSO-CFIWA shows better efficiency in designing of optimal GC-GS-DG MOSFET as compared to the conventional designs [11, 14] and MOGA [9].

Optimization of Subthreshold Parameters of Graded-Channel …

47

Table 2 PSO-CFIWA-based optimal parameters for GC-GS-DG MOSFET Symbol

Conventional design 1 Conventional design 2 MOGA [9] [14] [11]

PSO-CFIWA

t si (nm)

10

10

5

5

t 1 (nm)

~0.6

1

1.00

0.25

t 2 (nm)

~0.5

2

1.32

0.30

L (nm)

50

26

30

22

L1 (nm)

25

13

14.50

11

V gs (V)

1

1

0.1

1.0

V ds (V)

0.1

1

0.5

0.5

E2

24

22

39.58

25

4.33

4.63

Fm (eV) N AL

(cm−3 )

N AH

(cm−3 )

S (mV/dec)

–

–

2×

1016

1×

1015

62.46

1×

1015

5×

1×

1016

9.28 ×

72.7

9.9861 × 1017

1015 1016

60.60

2.7752 × 1019 60.07

ΔS

–

–

–

0.0011167

IOFF (A/µm)

–

5 × 10–10

4.23 × 10–13

1.94 × 10–12

CF

–

–

6.0495 × 10–3 5.58 × 10–4

t (s)

–

–

62

25

I ON /I OFF

0.75 × 106

3.25 × 106

1.96 × 1010

3.36 × 1010

V th (V)

–

0.306

0.54

0.6183

–

−1.18 ×

65

0.06

V roll-off (V)

–

DIBL (mV/V) 11.31 Fig. 2 OFF-state current for GC-GS-DG MOSFET

10–5

−0.3180 12.51

48 Fig. 3 I D versus V gs characteristic for GC-GS-DG MOSFET

Fig. 4 I D —Ramp versus V gs plot for GC-GS-DG MOSFET

Fig. 5 Transfer characteristics for different channel length of GC-GS-DG MOSFET

D. Chowdhury et al.

Optimization of Subthreshold Parameters of Graded-Channel …

49

Fig. 6 Convergence profile curve for PSO-CFIWA

5 Conclusion In this work, PSO-CFIWA is utilized to optimize the subthreshold parameters of the GC-GS-DG MOSFET. The five subthreshold parameters are computed as (1) minimization of I OFF , ΔS, V roll-off , DIBL and (2) maximization of I ON . Both the design and performance parameters of the GC-GS-DG MOSFET are optimized using the PSO-CFIWA algorithm. Electrical parameters are verified with the simulation data performed in TCAD tools. Simulation results show that the PSO-CFIWA proved itself a better optimizer as compared to the other algorithm used in literature for the design of GC-GS-DG MOSFET.

References 1. Basak A, Sarkar A (2020) Drain current modelling of asymmetric junctionless dual material double gate MOSFET with high K gate stack for analog and RF performance. Silicon. https:// doi.org/10.1007/s12633-020-00783-w 2. Yadav VK, Rana AK (2012) Impact of channel doping on DG-MOSFET parameters in nano regime-TCAD simulation. Int J Comput Appl 37(11):0975–8887 3. Faisal MdSA, Hasan MdR, Hossain M, Islam MS (2017) Projected performance of sub-10 nm GaN-based double-gate MOSFETs. Circ Comput Sci 2(2):15–19 4. Kaharudin KE, Salehuddin F, Zain ASM, Aziz MNIA (2016) Implementation of Taguchi method for lower drain induced barrier lowering in vertical double gate NMOS Device. J Telecommun Electron Comput Eng 8(4):11–16 5. Chiang T-K (2016) A short-channel-effect-degraded noise margin model for junctionless double-gate MOSFET working on subthreshold CMOS logic gates. IEEE Trans Electron Dev 63(8) 6. Gao H-W, Wang Y-H, Chiang T-K (2018) A new device-parameter-oriented DC Power Model for symmetric operation of junctionless double-gate MOSFET working on low-power CMOS subthreshold logic gates. IEEE Trans Nanotechnol 17(3)

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7. Bentrcia T, Djeffal F, Meguellati M (2015) Analytical investigation of swing factor for nanoscale double gate MOSFET including gatework-function effect. In: Proceedings of the World Congress on engineering Vol I, July 1–3, 2015, London 8. Djeffal F, Meguellati M, Benhaya A (2009) A two-dimensional analytical analysis of subthreshold behaviour to study the scaling capability of nanoscale graded channel gate stack DG MOSFETs. Physica E 41:1872–1877 9. Bendib T, Djeffal F, Arar D (2011) Subthreshold behaviour optimization of nanoscale graded channel gate stack double gate (GCGSDG) MOSFET using multi-objective genetic algorithms. J Comput Electron 10(1–2):210–215 10. Vimala P, Arun Samuel TS (2019) A simulation study on the impact of InP barrier on InGaAs/InP hetero junction gate all around MOSFET. J Nano Res 60:113–123 11. Adak S, Swain SK, Dutta A, Rahaman H, Sarkar CK (2016) Influence of channel length and high-K oxide thickness on subthreshold DC performance of graded channel and gate stack DGMOSFETs. NANO: Brief Reports Rev 11(9):1650101(1–6). https://doi.org/10.1142/S17 93292016501010 12. Hasan MdR (2017) Influence of device performance of Sub-10 nm GaN Based DG-MOSFETs over conventional Si-based SG-MOSFETs. In: Proceedings of the 2017 4th international conference on advances in electrical engineering, pp 697–702, 28–30 September 2017, Dhaka, Bangladesh 13. Vaddi R, Agarwal RP, Dasgupta S (2012) Compact modeling of a generic double-gate MOSFET with Gate–S/D underlap for subthreshold operation. IEEE Trans Electron Devices 59(10):2846–2849. https://doi.org/10.1109/TED.2012.2208464 14. Narendar V, Girdhardas KA (2018) Surface potential modeling of graded-channel gatestack (GCGS) high-K dielectric dual-material double-gate (DMDG) MOSFET and analog/RF performance study. Silicon 10:2865–2875. https://doi.org/10.1007/s12633-018-9826-z 15. Ramezani Z, Orouji AA (2018) A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects. Int J Electron 105(3):361–374. https://doi.org/10.1080/ 00207217.2017.1357206 16. Mendiratta N, Tripathi SL, Padmanaban S, Hossain E (2020) Design and analysis of heavily doped n+ pocket asymmetrical junction-less double gate MOSFET for biomedical applications. Appl Sci 10(7):2499 17. Gowthaman N, Srivastava VM (2021) Capacitive modeling of cylindrical surrounding doublegate MOSFETs for hybrid RF applications. IEEE Access 9:89234–89242. https://doi.org/10. 1109/ACCESS.2021.3090956 18. Pakaree JE, Srivastava VM (2019) Realization with fabrication of double-gate MOSFET based differential amplifier. Microelectron J 91:70–83. https://doi.org/10.1016/j.mejo.2019.07.012 19. Chakrabarti H, Maity R, Maity NP (2019) Analysis of surface potential for dual-materialdouble-gate MOSFET based on modeling and simulation. Microsyst Technol 25:4675–4684. https://doi.org/10.1007/s00542-019-04386-3 20. Ramezani Z, Orouji AA, Ghoreishi SA, Amiri IS (2019) A nano junctionless double-gate MOSFET by using the charge plasma concept to improve short-channel effects and frequency characteristics. J Electron Mater 48:7487–7494. https://doi.org/10.1007/s11664-019-07559-y 21. Darwin S, Arun Samuel TS (2020) A holistic approach on junctionless dual material double gate (DMDG) MOSFET with high k gate stack for low power digital applications. Silicon 12:393–403. https://doi.org/10.1007/s12633-019-00128-2 22. Mandal D, Ghoshal SP, Bhattacharjee AK (2010) Design of concentric circular antenna array with central element feeding using particle swarm optimization with constriction factor and inertia weight approach and evolutionary programming technique. J Infrared Milli Terahertz Waves 31(6):667–680 23. De BP, Kar R, Mandal D, Ghoshal SP (2014) Design of symmetric switching CMOS inverter using PSOCFIWA. In: Proceedings of IEEE ICCSP’ 14, pp 1818–1824, 3–5 April 2014, Melmaruvathur, Tamil Nadu, India 24. Kennedy J, Eberhart R (1995) Particle swarm optimization. In: Proceedings of IEEE international conference on neural network, vol 4, pp 1942–1948

A Comparative Study on Electrical Characteristics of Bulk, SOI, and DG MOSFET Asutosh Patnaik, Narayan Sahoo, and Ajit Kumar Sahu

Abstract Transistors are the foundation for electronic circuits and are continuously modifying in design from their insertion into the semiconductor industry to follow Moore’s law. The scaling of conventional bulk metal oxide semiconductor fieldeffect transistors (MOSFETs) improves IC performance in driving capability and switching speed up to a specific limit. The limiting factors in the bulk MOSFET downscaling are power consumption due to short-channel effects (SCEs) like draininduced barrier lowering, gate-induced drain leakage, V th roll-off, leakage current, and subthreshold slope degradation. New device architectures like silicon on insulator MOSFET (SOI MOSFET), double-gate MOSFET (DG MOSFET) are emerged to continue the scaling trends which have low leakage and low threshold voltage without any degradation in the performance. In this paper, we make a comparative study on the electrical characteristics of the conventional planar MOSFET, SOI MOSFET, and DG MOSFET. We extract the electrical characteristics of the above structures by using the nanoHUB tool and show that for the same design parameters DG MOSFET exhibits large I on current as well as low DIBL, and low subthreshold swing as compared with SOI and bulk MOSFET. From the graph obtained, the values of I on , I off subthreshold slope are calculated, and it has been proved that due to the presence of two gates in DG MOSFET on either side of the channel, which makes the gate-to-channel coupling doubled resulting in the suppression of SCEs and higher I on . Keywords Bulk MOSFET · SOI · Short-channel effect · Drain-induced barrier lowering · Double-gate MOSFET

A. Patnaik (B) Department of Electrical and Electronics Engineering, C. V. Raman Global University, Bhubaneswar, Odisha, India e-mail: [email protected] N. Sahoo · A. K. Sahu Department of Electronic Science, Berhampur University, Berhampur, Odisha, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_6

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1 Introduction In 1965, Moore predicted that the transistor used in the chip would be doubled after every two years [1]. Since 1970, the downscaling of transistors has been continuously changing. There is a continuous effort for shrinking the device structure like gate length or width to enhance the device density and better performance of the transistors [2]. Downscaling is also made by changing other parameters of the structure like oxide thickness, the depletion layer’s width, varying the doping density in the substrate, and modifying the architecture. However, the continuous scaling of conventional transistors to nanometer regime is resulting in a substantial change in the device’s electrical characteristics, such as short-channel effects (SCEs) [3]. Because of these effects, there is degradation in the device performance. To eliminate or minimize the effect, many researchers have proposed their ideas arriving at many new structures of transistors without changing the behavior of the conventional one. Starting from planar MOSFET, new designs such as bulk MOSFET (built on bulk Silicon wafers), partially depleted (PD) and fully depleted (FD) silicon on insulator (SOI) MOSFETs, double-gate (DG) FETs, trigate FETs, FinFETs, gate-all-around (GAA) transistors have explored [4]. Antoniadis et al. [5] compared the subthreshold characteristics for 70/40 dual channel and p-MOSFETs and found that the subthreshold swing is 72 mV/decade for both the devices. They have shown that for n-MOSFETs and p-MOSFETs, the I off current approximately equals 300 nA at drain voltage V d = 0.8 V. Harrison et al. [6] studied the two families of highly performing double-gate MOSFET devices, and found that for oxide thickness of 2 nm and gate length of 70 nm, very high drive currents (I on ) of 1954 μA/μm and 1333 μA/μm are obtained. Here, we focused to study and compare the electrical characteristics of conventional MOSFETs, SOI MOSFET, and DGFETs by using the nanoHUB tool. The state of art of the electrical characteristics, i.e., SCEs, DIBL, and subthreshold swing are expressed in Sect. 2. Section 3 discusses the simulations and calculation of SCEs of bulk, SOI, and DG MOSFET. Section 4 focuses on comparative analysis among the transistors. Section 5 gives the conclusion of the work.

2 State of Art The short-channel effect occurs when length of the channel in MOSFET has decreased in the order the length of depletion layer width of the drain and source junctions. The SCEs are manifested by an increase in the subthreshold swing, reduction in I on /I off ratio, decrease in the threshold voltage and resulting in DIBL. The ratio I on /I off is an important factor for having high on current (higher I on ) and low power leakage (lower I off ) for any semiconductor device. If in a device leakage current is large, i.e., I off is large, then power consumption of the device will be higher

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[7]. So, to minimize the power consumption, I off should be low, and the ratio should be large. Drain-induced barrier lowering (DIBL) is one kind of short-channel effect that occurs when the proximity between the drain and source tends to decrease. When the two regions came close to each other, they are electro-statistically coupled, resulting flow of carriers from source junction to drain junction, even the transistor is in the off state. This leads to an increase in I off value, which is undesirable. The DIBL is calculated [8] from the I d ~ V g characteristics of transistors discussed in the subsequent sections. It is defined as the change in threshold voltage (V th ) per one-volt change in drain bias. Subthreshold swing (S) is another short-channel effect that occurs below the threshold voltage (V t ). To obtain S value, the transfer characteristics are plotted in a semi-log graph. The slope is found at this subthreshold characteristic [9] which is given by   d log(Id ) Slope = dVgs

(1)

The subthreshold behavior is given by S = 1/slope or the gate voltage (V gs ) necessary to change the drain current (I d ) by one decade or log(I d ) by one. Mathematically, it is represented as:   Cb kT mV/decade 1+ S = ln(10) q Cox

(2)

where k is the Boltzmann’s constant, q is the electronic charge, T is the temperature, C b is the bulk capacitance, and C ox is the oxide capacitance.

3 Results and Discussions 3.1 Structures MOSFETs are the basic backbone of the integrated circuits (ICs). The technology of the long channel is used in the conventional planar MOSFET or bulk MOSFET as shown in Fig. 1a. If the channel is shortened, then many drastic changes [10] occur in the transistors. The short-channel effects (SCEs) like decrease in I on /I off ratio, draininduced-barrier-lowering (DIBL), subthreshold voltage degradation, and variations in threshold voltage occur. To follow Moore’s law, further advancement in transistor technology leads to SOI MOSFET as shown in Fig. 1b. In this technology, a silicon layer above the insulator layer is placed [11–13]. A thin layer of SiO2 is used as the insulator for reducing the short-channel effects. As a result, the gate-control ability over the channel is greater than the bulk MOSFET. The main advantages of using

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Fig. 1 Two-dimensional (2D) view of a bulk MOSFET b SOI MOSFET c DG MOSFET

this technology are as follows: lower parasitic capacitance [14] resulting less power consumption, faster-switching speed than the conventional MOSFET, lower leakage currents. To further improve the short-channel effects, the recent advancement in transistor technology is the DG MOSFET [15]. Figure 1c depicts the 2D view of DG MOSFET. It has two gates, namely the front gate (G1 ) and the back gate (G2 ). Depending upon the oxide thickness [16] at both front and back, DG MOSFET can be symmetric or asymmetric. Due to the presence of a double gate, the device has better control of charge and has the quality of faster-switching speed. This results in a reduction of SCEs in DG MOSFET allows further scaling of the gate length [17].

3.2 Simulations The simulation of bulk, SOI, and DG MOSFET are done using the nanoHUB tool to study its electrical characteristics. We consider the same parameters for all the above structures and are given in Table 1. The drift-diffusion model has been used for simulating and extracting different electrical characteristics of different MOSFET structures as explained above.

3.3 Device Characteristics and Calculations The current–voltage characteristics of any device provide a better understanding of the physical process involved in the operation. From these characteristics, many important parameters are calculated that can be used in further optimizing the device. Here, we have obtained the output characteristics (drain current, I d with respect to drain to source voltage, V ds ) and transfer characteristics (drain current, I d with respect to gate-to-source voltage, V gs ) of all simulated transistors and computed the different figures of merit, namely I on , I off , subthreshold swing, and DIBL. We present the output characteristics of bulk, SOI, and DG MOSFET in Fig. 2a–c, respectively.

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Table 1 Values of input parameters for simulation of bulk, SOI, and DG MOSFET Input parameters

Values

Source/Drain length

50 nm

Channel length

100 nm

Junction depth

20 nm

Oxide thickness

2 nm

Substrate thickness

50 nm

Device width

1000 nm

Channel doping concentration

1e+18 /cm3

Source/Drain doping concentration

2e+20 /cm3

Substrate doping

5e+16 /cm3

Gate electrode

Poly Si

Si band gap at 300 K

1.12 eV

Electron saturation velocity

1.03e+7 cm/s

Electron mobility

1400 cm2 /Vs

Oxide dielectric constant

3.9

Fig. 2 Output characteristics of a bulk MOSFET b SOI MOSFET c DG MOSFET

Fig. 3 Transfer characteristics of a bulk MOSFET b SOI MOSFET c DG MOSFET

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Fig. 4 Calculation of I on , I off , S, DIBL of a bulk MOSFET b SOI MOSFET c DG MOSFET

Also,we depict the transfer characteristics of bulk, SOI, and DG MOSFET in Fig. 3a– c, respectively. To study the behavior of bulk, SOI, and DG MOSFET in the subthreshold range, we plot the transfer characteristics by considering the log scale on the y-axis and is shown in Fig. 4a–c, respectively. Based upon the results obtained, we calculate the different figure of merits such as I on /I off , DIBL, and subthreshold swing (S). Calculation of I on /I off : I on is the maximum drain current at V ds = V gs = V max . (a)

(b)

(c)

Bulk MOSFET: From the transfer characteristics of Fig. 4a, we note that at V ds = V gs = V max = 1 V, I on ≈ 631 μA/μm. I off is the maximum off current at V gs = 0 V and V ds = Vmax . We also note that at V ds = V max = 1 V, and V gs = 0 V, I off = 0.1 μA/μm. SOI MOSFET: From the I d versus V g of Fig. 4b, it is found that at V ds = V gs = V max = 1 V, I on ≈ 717 μA and V ds = V max = 1 V, and V gs = 0 V, I off = 0.23 μA. DG MOSFET: From the I d versus V g of Fig. 4c, for V d = 1 V, it is found that V ds = V gs = V max = 1 V, I on ≈ 2084 μA and Ioff = 9.9 μA.

Calculation of subthreshold swing (S) (a)

(b)

(c)

Bulk MOSFET: For approximately, 1 decade change in drain current, the gate voltage change is calculated at V d = 1.0 V and is given by V g = 0.078 V = 78 mV. S for bulk MOSFET is 78 mV/decade. SOI MOSFET: For SOI, approximately, 1 decade change in drain current, the gate voltage change is calculated at V d = 1 V and is given by V g = 0.072 V = 72 mV. S for SOI MOSFET is 72 mV/decade. DG MOSFET: For DG MOSFET, approximately, 1 decade change in drain current, the gate voltage change is calculated at V d = 1 V and is given by, V g = 0.067 V = 67 mV. S for DG MOSFET is 67 mV/decade.

Calculation of DIBL

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(a)

(b) (c)

57

Bulk MOSFET: For V d at 1 V and 0.05 V, the threshold voltages (V t1 and V t2 ) are 0.167 V and 0.211 V, respectively. From these values, DIBL is calculated as 46 mV/V. SOI MOSFET: For V d at 1 V and 0.05 V, the threshold voltages are 0.122 V and 0.156 V, respectively. From these values, DIBL is calculated as 35 mV/V. DG MOSFET: From simulation analysis, at V d = 1 V and 0.05 V, the threshold voltages are respectively, 0 mV and 11 mV. So, the DIBL is calculated as 11 mV/V.

4 Comparative Analysis To compare the electrical characteristics of bulk, SOI, and DG MOSFET, we present the comparative analysis of the figure of merits for different structures in Table 2. It shows that DG MOSFET exhibits large I on current as well as low DIBL and low subthreshold swing as compared with SOI and bulk MOSFET structures. In order to more clarification, we also plot the potential distribution between source and drain for bulk, SOI, and DG MOSFET as in Fig. 5. This signifies that the potential height in DG MOSFET is low as compared to other MOSFET structures. As a result, the threshold voltage decreases, and current conduction between source and drain occurs even at Table 2 Comparison of I on , I off , S, and DIBL in bulk, SOI, and DG MOSFET structures Device type

I on (in μA)

I off (in μA)

I on /I off ratio

S (mV/Decade)

DIBL (in mV/V)

Bulk MOSFET

631

0.1

6310

78

46

SOI MOSFET

717

0.23

3117

72

35

DG MOSFET

2084

9.9

210

67

11

Fig. 5 Potential distribution between drain and source of bulk, SOI, and DG MOSFET

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the low gate-to-source voltage in the case of DG MOSFET. Finally, it is concluded that there is more charge sharing occurs between the sources and drain region in bulk MOSFET as compared with SOI MOSFET where the buried oxide minimizes this. This enhances the I on of SOI MOSFET as compared with bulk MOSFET. However, in the case of DG MOSFET where two gates on either side of the channel double the gate-to-channel coupling leading to better control over the current from source to drain, resulting in the suppression of SCEs and higher I on as compared with SOI and bulk MOSFET. Table 2 gives the comparative result of all short-channel effects of bulk, SOI, and DG MOSFET.

5 Conclusion Here, we study and compare the short-channel effects performed by bulk, SOI, and DG MOSFET having 100 nm channel length. We consider same design parameters for all the three structures and performed simulation by using the nanoHUB tool. We show that DG MOSFET exhibits large I on current as well as low DIBL and low subthreshold swing as compared with SOI and bulk MOSFET. Due to the presence of two gates in DG MOSFET on either side of the channel, the gate-to-channel coupling became doubled. So, it has good control over the current from source to drain, resulting in the suppression of SCEs and higher I on .

References 1. Moore GE (1965) Cramming more components onto integrated circuits. Electronics, pp 114– 117 2. Dennard RH, Gaenssien F, Yu HN, Rideout L, Bassous E, LeBlanc A (1974) Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J Solid-State Circuits 9(5):256–258 3. Wong HSP, Frank DJ, Solomon PM, Wann CHJ, Welser JJ (1999) Nanoscale CMOS. In: Proceedings of the IEEE, pp 537–570 4. Colinge JP (2008) FinFETs and other multi-gate transistors. Springer, Ireland 5. Antoniadis DA, Aberg I, Chleirigh CN, Nayfeh OM, Khakifirooz A, Hoyt JL (2006) Continuous MOSFET performance increase with device scaling: the role of strain and channel material innovations. IBM J Res Dev 50(4/5):373–376 6. Harrison S et al (2003) Highly performant double gate MOSFET realized with SON process. In: IEEE International electron devices meeting, vol 3, pp 449–452 7. Siebel OF, Schneider MC, Montoro CG (2012) MOSFET threshold voltage: definition, extraction, and some applications. Microelectron J 43(5):329–336 8. Beigi K, Hashemi A (2019) Increasing ION /IOFF by embedding a low doped buried layer in the channel of a dual-material double-gate junctionless MOSFET. Int J Numer Model 9. Ghibaudo G, Pananakakis G (2018) Analytical expressions for subthreshold swing in FDSOI MOS structures. Solid State Electron 149:57–61 10. Chang L, Hu C (2000) MOSFET scaling into the 10 nm regime. Superlattices Microstruct 28(5/6):351–355

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11. Yan RH, Ourmazd A, Lee KF (1992) Scaling the Si MOSFET: from bulk to SOI to bulk. IEEE Trans Electron Devices 39(7):1704–1710 12. Celler GK, Cristoloveanu S (2003) Frontiers of silicon-on-insulator. J Appl Phys 93(9):4955– 4978 13. Colinge JP (2004) Silicon-on-insulator technology: materials to VLSI, 3rd edn. Kluwer Academic Publisher, New York 14. Madadi D, Orouji AA (2020) Investigation of short channel effects in SOI MOSFET with 20 nm channel length by a β-Ga2 O3 layer. ECS J Solid State Sci Technol 9(4) 15. Taur Y, Lin HH (2018) Modeling of DG MOSFET I-V characteristics in the saturation region. IEEE Trans Electron Devices 65(5):1714–1720 16. Xie Q, Wang Z, Taur Y (2017) Analysis of short-channel effects in junctionless DG MOSFETs. IEEE Trans Electron Devices 64(8):1714–1720 17. Kansal H, Medury AS (2021) Improved short channel electrostatics through design of partially junction-less double-gate MOSFETs. AIP Adv 11:025006

Optical Analysis of Far-Field Intensity on Organic Light-Emitting Diode to Reduce Surface Plasmon Losses B. M. Chaya, Koushik Guha, M. Venkatesha, A. Vaishnavi, and K. Narayan

Abstract In this article, we are explaining the electromagnetic models to simulate the effect of plasmon coupling at metal cathode and to analyze the OLED with nanograted cathode for reduction of surface plasmon loss. The modeling and analysis of the bottom-emitting organic light-emitting diode (OLED) using nano-grating metal cathode structures is presented. OLED is modeled and simulated by using finite difference time domain (FDTD) approach. The light extraction efficiency (LEE) has been improved by introducing nano-grating cathode structure that reduces surface plasmon (SP) losses. The proposed OLED without grated cathode and the device with nano-grated cathode comparison is shown. The intensity of far field is also studied for various cathode materials on an OLED device. It was found to be optimum for a wavelength of 540 nm for aluminum as a cathode material. Keywords Organic light-emitting diode · Far-field intensity · Light extraction efficiency · Finite difference time domain

1 Introduction Intensive organic light-emitting diodes (OLEDs) research and development have been carried out over recent years for high-performance color displays and applications for lighting. Although a low efficiency of out coupling still significantly limits the overall quality, since the multilayer structure can leave a fraction of the light because of its significant difference between emissive refractive index layers (n = 1.7 to 2.0), air (n = 1.0) and glass (n = 1.5). In a traditional OLED, 20% of light is produced from the glass substrate is related directly to the air and approximately the same amount [1]. The energy is lost due to waveguide mode excitation that spreads B. M. Chaya (B) · M. Venkatesha · A. Vaishnavi · K. Narayan Sai Vidya Institute of Technology (Affiliated to Visvesvaraya Technological University), Rajanukunte, Bengaluru, Karnataka, India e-mail: [email protected] K. Guha Department of ECE, National Institute of Technology, Silchar, Assam, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_7

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throughout the organic layers or polaritons or surface plasmon’s (SPs) onto surface, that is, electromagnetic waves that pass between the organic surface and the metal cathode interface. The combination of waveguide and SP modes causes losses. Normally, 50% in traditional OLEDs is based on small molecules [2, 3]. The most obvious way to minimize SP losses is to simply increase the gap since the relationship to SPs exists between the molecules that emit and the metallic cathode, via near-field optics. This has the disadvantage of increasing the overall thickness of the organic layers, as well as providing more waveguide modes; hence, waveguide losses are frequently merely redistribution from SP to SP losses [1]. In comparison, by using non-isotropic emitters oriented more horizontally by their dipole moment transformation, that is, parallel to the plane of the substrate, the relation to SPs can be reduced significantly. Since dipoles in comparison to perpendicular ones dissipate significantly less energy into SPs, the efficacy of light out coupling can be increased by a factor of approximately 1.5. The meaning of polymer OLEDs [4, 5] has long been known for emitter orientation. Few emitter materials in fluorescent organic thin films used in OLEDs based on small molecules have lately been reported to provide this type of effect [6]. The multilayer stack has different refractive indices. Due to this, there will be nonlinearities in the device. The OLED structure has various losses present in it, due to the varying refractive indices and various energy levels of the layers. As in [7, 8] explains the various losses exist in the devices like substrate-mode losses, organic losses, and the surface plasmon losses that are present in the dielectric metal-layer interface. In this work, the surface plasmon losses which is about 40% in the OLED are addressed. As in [4], the OLED device is simulated using finite difference time domain method. By incorporating nano-grating cathode, the light emission from OLED is enhanced compared to conventional OLED. Section 1 describes introduction; Section 2 involves design of OLED structure with nano-grating metallic cathode structure; Sect. 3 outlines the methodology involved to design OLED. Section 4 presents the numerical results of an OLED.

2 Design of Organic Light-Emitting Diode with Nano-Grated Cathode Structure Figure 1 shows the multilayered OLED structure with nano-grated cathode structure. The device consists of anode, nano-grated cathode, emissive layer, hole transport layer, glass substrate. The materials are chosen for the above structure as in [9] and same updated using nano-grating cathode structure shown in Table 1. A nanograting structure that is made up of aluminum and the grating pitch was calculated using Bragg’s law and was approximated to 504 nm. Here, grating structure was etched inside the cathode structure as shown in Fig. 2.

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Fig. 1 OLED with nano-grated cathode structure

Glass Substrate Anode - Indium tin oxide (ITO) Hole transport layer (HTL) Organic layer/ emission layer (EML) Grated Metallic Cathode structure

Table 1 OLED device materials Materials used

Work function (eV)

Refractive index [n]

Indium tin oxide (ITO)—anode

4.7

1.80

Nano-grated cathode-Al—cathode

4.1

1.03

BCP-(2, 9 Dimethyl-4, 7-diphenyl-1, 10 3.2 phenanthroline)-hole blocking layer (HBL)

1.68

(Copper (II) phthalocyanine)-CuPC hole 3.1 injection layer (HIL)–

0.47

TPD-(N, N’Bis(3-methylphenyl)-N,N’-diphenyl benzidine)-hole transport layer (HTL)

2.6

1.67

Alq3-Tris (8-hydroxyquinoline)Aluminum

5.62-HOMO, 2.85-LUMO

1.68

Glass substrate

–

1.53

OLED Layers

Height of Grating Pitch Fig. 2 Modeled OLED structure using nano-grating

Nano-grating cathode structure has a period of 504 nm obtained from Bragg’s law. The height of the grating is chosen to be 160 nm. The dipole is 50 nm (d) is placed above the center of a pitch. The result indicates that significant reduction of Plasmon losses can be achieved with nano-grating cathode when the distance between the dipole and the interface is less than about 100 nm. As the distance increases, the plasmon loss of flat structure decreases to insignificant level, while that of nano-grating cathode remains at around 40%.

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Figure 2 shows the modeled OLED structure using nano-grating cathode placed below the emissive layer interface. The modeling of the OLED structure is done using lumerical FDTD [10]. Table 1 shows details of the materials database and corresponding work function used in proposed OLED. The work function gives the details on how much energy is dissipated for a device to emit light. The OLED device uses emissive layer Alq3-Tris(8-hydroxyquinoline) aluminum emits green light. The surface plasmon losses are formed when dipole source is coupled to surface plasmon polariton (SPP). The SPP is confined at organic metal electrode interface. The wavelength of SPP is specified in the perfectly matched layer (PML) to absorb outgoing waves as discussed in [11, 12]. This OLED device can be utilized as a source of input and also in Lab-on-a-Chip (LoC) biosensors as outlined [13].

3 Methodology Modeling the suggested device employs the FDTD approach. As shown in [10, 12, 14], the frequency domain is calculated using Maxwell’s equations in order to mimic the field distribution inside a multilayer stack OLED material. An electric dipole is placed at the emissive layer in the OLED. All the layers used in the OLED have boundary conditions chosen to be perfectly matched layers (PML). The mesh is applied to cathode dimensions in the proposed structure. PML at the top boundary assumes infinite half space for glass substrate, and the substrate/air interface effect is not included in the simulation. The OLED device has the substrate is thick, and it is not treated in the FDTD optical computations. The characteristics of surface plasmon polarities are high intensity, confinement at the metal-dielectric region, and attenuation of electric intensity as it propagates away from the source. Therefore, at the cathode interface, the SPP wave is excited, and the principle of plasmon loss is revealed by the FDTD simulation. Hence, the simulation reveals the main mechanism of the plasmon loss is excitation of the SPP wave at the cathode interface [11, 12]. The height of the OLED incorporates a nano-grating structure, given by Bragg’s law represented in Eq. 1 [12], 2dsinθ = nλ

(1)

where d = pitch of grating, n = net refractive index (RI) of OLED, λ is the operating wavelength. In this present work, the operating wavelength is chosen to be 540 nm. As mentioned in [15], viewing angle (θ ) for a particular wavelength normal to the substrate is shown in Eq. 2, K 0 sinθ = ±K g ± m(2π/A)

(2)

In the above equation, m is an integer; K 0 is a wave vector in the air, and K g is the wave vectors for ITO/organic layer; A is the grating pitch. For the OLED design,

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the pitch is selected as 504 nm. The pitch of the grating is kept constant and simulate for various grating heights.

4 Numerical Simulation and Results The following section will ensure the coupling of plasmon in planar OLED is high. It also provides information about how much light is coupled into emissive layer. It is also shown that with nano-grating cathode surface plasmon polariton coupling is greatly suppressed. Figure 3 shows the contours of the far-field electric intensity profile of OLED obtained for conventional/planar cathode-based OLED structure. From the profile, it is observed that the electric field intensity of the designed grated cathode OLED is significantly higher when compared with the conventional OLED. Figure 4 shows angular far-field intensity plots for nano-grated cathode-based OLED. The study is performed out on a variety of cathode materials with varying work functions. With reference to viewing angle, the field intensity plots for the different cathode materials are seen. From the plot, it is found that cathode with aluminum material has enhanced electric field intensity with wide viewing angle. The other materials used for the cathode like magnesium, silver, and lithium fluoride have less angular far-field intensity compared to cathode with aluminum material. Figure 5 shows the analysis of nano-grating height of a cathode; the heights of cathode are varied from 120 to 180 nm. The plot shows the variations in the far-field analysis to optimize the height of the nano-grated cathode. From the analysis, it is found that the nano-grating height of the cathode to be 160 nm (Table 2). Figure 6 shows the comparative plot of OLED with nano-grated cathode and OLED with planar cathode layer. The optimised values of the grating in the OLED structure is height of 160nm, pitch 504nm at an operating wavelength of 540nm. The proposed OLED has enhanced far-field intensity of 1.05 × 10−5 V/m compared to conventional OLED with far-field intensity to be 4.08 × 10−6 V/m.

5 Conclusion In this paper, the nano-grated cathode is incorporated in the OLED design on the cathode organic-layer interface to reduce the SP losses. The FDTD method is used as single simulation run and checks nonlinear material properties. High accurate analytic output is obtained by the lumerical FDTD commercial software. The conventional/planar OLED model without nano-grating of the cathode layer produces farfield electric intensity around 7.48 × 10−6 V/m, whereas OLED proposed model with nano-grated OLED produces far-field electric intensity of 1.11 × 10–5 V/m, and the study also reveals that the aluminum is the appropriate cathode material to be used in OLED for the better efficiency. The far-field intensity is substantially increased

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Fig. 3 Far-field contours of the OLED a Conventional/planar OLED, b Nano-grated cathode OLED

in this work, ensuring the significant reduction in the surface plasmon losses in the device compared to the conventional OLED. Fabrication of Lab-on-a-Chip with such “in-built” source of light could be taken up as a research project in the future.

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Fig. 4 Far-field electric field intensity plots for different cathode materials

Fig. 5 Plot of nano-grated cathode with different grating heights

Table 2 Grated heights of nano-grated cathode

Grated height (in nm)

Light extraction output [V/m]

120

6.18 × 10–6

140

6.97 × 10–6

160

1.05 × 10–5

180

4.08 × 10–6

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Fig. 6 Comparative plot of planar and nano-grated OLED design

Acknowledgements The authors would like to thank Vision Group on Science and Technology (VGST), Department of IT, BT & ST, Government of Karnataka, India. Grant number: VGST—RGS/F, GRD—823, FY 2018-19 for funding this research work.

References 1. Nowy S, Krummacher BC, Frischeisen J, Reinke NA, Brütting W (2008) Light extraction and optical loss mechanisms in organic light-emitting diodes: influence of the emitter quantum efficiency. J Appl Phys 104(12):123109 2. Nowy S, Frischeisen J, Brütting W (2009) Simulation based optimization of light out coupling in organic light emitting diodes. Proc SPIE 7415:74151C 3. Smith LH, Wasey JAE, Samuel IDW, Barnes WL (2005) Light out-coupling efficiencies of organic light-emitting diode structures and the effect of photoluminescence quantum yield. Adv Funct Mater 15(11):1839–1844 4. Kim J-S, Ho PKH, Greenham NC, Friend RH (2000) Electroluminescence emission pattern of organic light-emitting diodes: Implications for device efficiency calculations. J Appl Phys 88(2):1073–1081 5. Ziebarth JM, McGehee MD (2005) A theoretical and experimental investigation of light extraction from polymer light-emitting diodes. J Appl Phys 97(6):064502 6. Frischeisen J, Yokoyama D, Adachi C, Brütting W (2010) Determination of molecular dipole orientation in doped fluorescent organic thin films by photoluminescence measurements. Appl Phys Lett 96(7):073302 7. Frischeisen J, Niu Q, Abdellah A, Kinzel JB, Gehlhaar R, Scarpa G, Adachi C, Lugli P, Brütting W (2011) Light extraction from surface Plasmons and waveguide modes in an organic light-emitting layer by nano imprinted gratings. Opt Express 19:A7–A19 8. Chutinan A, Ishihara K, Asano T, Fujita M, Noda S (2005) Theoretical analysis on light extraction efficiency of organic light-emitting diodes using FDTD and mode-expansion methods. Org Electron 6:3–9 9. Chaya BM, Venkatesha M, Shruthi N, Narayan K (2018) FDTD modeling and simulation of organic light emitting diode with improved extraction efficiency using moth-eye anti-reflective

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coatings. In: Proceedings of the 6th international conference on photonics, optics and laser technology (PHOTOPTICS 2018), pp 266–272 Lumerical FDTD Solutions 7.5, Inc. Available at: https://www.lumerical.com/tcad-products/ fdtd Wei M-K, Lin CW, Yang C-C, Kiang Y-W, Lee J-H, Lin H-Y (2010) Emission characteristics of organic light emitting diodes and organic thin films with planar and corrugated structures. Int J Mol Sci 11:1527–1545 Xiao Y, Yang JP, Cheng PP, Zhu JJ, Xu ZQ, Deng YH, Lee ST, Li YQ, Tang JX (2012) Surface Plasmon-enhanced electroluminescence in organic light emitting diodes incorporating Au nanoparticles. Appl Phys Lett 100:013308 Krishnaswamy N, Srinivas T, Rao GM, Varma MM (2013) Analysis of integrated optofluidic lab-on-a-chip sensor based on refractive index and absorbance sensing. IEEE Sensors J 13(5) Taflove A (1988) Review of the formulation and application of the finite-difference time-domain method for numerical modeling of electromagnetic wave infractions with arbitrary structures. Wave Motion 10:547–582 Wang L, Amano J, Hung P-C (2016)Simulating Plasmon effect in nanostructured OLED cathode using finite element method. Konica Minolta technology report, vol 13, pp 101–106

Analog Performance of Normally-On Si3 N4 /AlN/β-Ga2 O3 HEMT Meenakshi Chauhan , Abdul Naim Khan , Raghuvir Tomar, and Kanjalochan Jena

Abstract The present paper shows the normally-On AlN/ β-Ga2 O3 HEMT designed with Si3 N4 as a dielectric between gate and AlN layer. The insertion of the dielectric Si3 N4 enhances the efficiency and reliability of the conventional HEMT reducing the gate leakage current and short channel effects. The proposed device is simulated in a Commercial Silvaco Technology Computer Aided Design (TCAD) to obtain the important DC and RF characteristics such as drain current, transconductance, gate leakage current, capacitance and cut-off frequency. The simulated results are satisfactory and the device can be useful for high frequency and low power applications. Keywords 2 DEG · β-Ga2 O3 · Group III material · Dielectric · Passivation · Transconductance

1 Introduction The ultra-wide band gap semiconductor material with Eg = 4.9 eV, namely, βGa2 O3 (BGO) have shown tremendous properties such as higher breakdown electric field (8 MV/cm), wide spectra of n-type dopants with shallow donor impurities like Si, Ge, Sn, F and Cl compared to other wide band gap semiconductors. Furthermore, its higher figure of merit (200 cm2 /Vs electron mobility and 1.5 × 107 cm/selectron M. Chauhan (B) · A. N. Khan · R. Tomar · K. Jena Department of Electronics and Communication Engineering, The LNM Institute of Information Technology, Jaipur, Rajasthan 302031, India e-mail: [email protected] A. N. Khan e-mail: [email protected] R. Tomar e-mail: [email protected] K. Jena e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_8

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velocity) and superior DC performance are proved advantageous for power electronic and high frequency devices. As a result, various devices are designed using BGO such as optoelectronic devices like Schottky diodes; semiconductor devices such as metalsemiconductor Field-effect Transistor(MOSFET) or metal oxide FET; high electron mobility transistors (HEMTs) such as (Alx Ga1−x )2 O3 /Ga2 O3 and microwave devices. In devices operating at radio frequencies, the choice of gate length and aspect ratio is very crucial such that BGO MOSFETs with different dimensions: gate length = 3.8 μm/0.14 μm; current gain cut-off frequency 3.3 GHz/5 GHz have shown better performance. The thermal characteristics of BGO MOSFETs are affected by traps in the device [1, 2]. To design the above-mentioned devices, various materials corresponding to their unique ability such as nitrides—GaN/InN (Group III material) for wide band gap, high polarization and better thermal stability have been exploited. However, these materials have posed certain hindrances such as high cost, native substrate requirement and wider lattice mismatch within GaN epilayer [3, 4]. In consideration to such issues, the BGO material is found as a potential substrate for developing nitridebased epilayers at low lattice mismatch. Apart from these traits, the higher carrier mobility (200 cm2 /Vs) leads to enhanced electron-phonon interactions and higher electron effective mass in Ga2 O3 ; however, the device fails at deploying applications with high power requirement. This drawback further attenuates the DC switching performance of the device [5, 6]. Within the wideband gap material, the BGO devices have broad gate periphery, high Figure of Merit with electron saturation velocity of 1.5 × 107 cm/s, which is quite justifiable in using BGO devices over GaN devices [7, 8]. The cut-off frequency for AlGaN/GaN devices is reported to be 180 GHz [9] while BGO devices have 167 GHz [10]. In this paper, we have designed a normally-On AlN/ β-Ga2 O3 HEMT with Si3 N4 as a dielectric between gate and AlN layer. Dielectric is used as a passivation layer to reduce the gate leakage current and other short channel effects [11]. The drain current, transconductance, gate capacitance and cut-off frequency analysis is done by using appropriate simulation models.

2 Integrants of Gate Leakage Current The research on gate leakage current in AlGaN/GaN HEMT has been done intensively but it is in cradle for BGO HEMT. Till date, techniques to reduce gate leakage current prominently involve insertion of dielectric layer. Literature for implementation of different dielectric like SiO2, Al2 O3 , HfO2 , and Si3 N4 in HEMT are existing [12, 13]. Gate leakage current refers to the leakage current due to high density positive interfacial charge at gate dielectric interface. It occurs mainly due to surface processing and passivation issues. Thus, gate leakage current enhances due to tunneling effect between source and gate caused by traps. During long term high voltage stress on the device, the dielectric interfaces at the channel play an important

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role in restoring it [14]. The three main constituents of gate leakage current are: (a) Poole Frenkel Emission (PFE), (b) Trap assisted Tunneling (TAT), (c) Fowler Nordheim Tunneling (FNT). The mathematical expression for Gate leakage current density is given by [13] JG = JTAT + JPF + JFN where J TAT is trap assisted tunneling current, J PF is Poole Frenkel emission, J FN is Fowler Nordheim Tunneling. The trap assisted tunneling current density, which is main constituent of gate leakage current, is given by Eq. 1 [15]  [ ]  q(VGS − V0 ) −1 JTAT = J0 exp ηkT

(1)

where J 0 , V 0 and η are parameters used to fit experimental data, q is fundamental electronic charge, k is Boltzmann’s constant, T is temperature. The Poole Frenkel emission describes the mechanism of trapping electrons in dielectric material, which is given by Eq. 2 [13] [ JPF = CPF E exp

−q(ΦE −

√ ] q E/π ε0 εs ) kT

(2)

where C PF is a constant, E is electric field across the barrier, Ft is barrier height for the e− emission from the trap state, ε0 is permittivity of vacuum, εs is permittivity of Ga2 O3 . The Fowler Nordheim Tunneling (FM) is tunneling of electrons through a rounded triangular barrier created in a conductor when electric field is applied to the device. The current density due to FM tunneling is given by Eq. 3 [12] JFN

) ( / 3 = AE exp −8π 2m e (q∅b ) 2

(3)

where A is constant, me is effective electron mass, Fb is schottky barrier height, h is Planck’s constant. These equations specify that TAT and PF are responsible when low electric field is generated while FN tunneling plays its role during high electric field in the device [15].

3 Device Design, Structure and Simulation Parameters The performance analysis of the proposed device- BGO HEMTs is simulated and analyzed at RF and DC level using ATLAS TCAD tool. Figure 1 represents the proposed device schematic with doping levels at zero biasing condition (thermal

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Fig. 1 Schematic of the investigated BGO HEMT

1 μm

0.25 μm 50nm 1 μm GATE

10 nm 10nm

DRAIN

Si3N4 AlN β-Ga2O3

50nm

25nm

SOURCE

1 μm

β-Ga2O3 semi-insulating substrate

3.30 μm

equilibrium).The BGO layer is doped with n-type impurity (1016 ) cm−3 ; the drain and source region underneath device is doped using n-type material (1 × 1018 cm−3 ), thus, giving a gaussian profile. For doping of Si dopants, a Czochralski method is followed. The profile peak is received at y = 0.025 μm which follows the decaying gaussian doping distribution laterally with L SD = 0.007 μm extending up to barrier layer edge. The material layers were deposited such that: a 10 nm AlN barrier with 50 nm semi-insulated BGO buffer layer and 10 nm 2DEG channel were provided with Si3 N4 passivating layer ≈25 nm. The Ni/Au material L G = 50 nm for gate with Schottky barrier of 0.9 eV and work-function (φ M ) 2.3 eV, Ti/Au/Ni source-drain contact of 1 μm and ohmic contacts (φ M ) = 3.15 eV. The source-gate spacing (L SG ) =0.25 μm, source-drain (L SD ) = 0.13 μm, and gate-drain (L GD ) spacing = 1 μm are utilized, respectively. The BGO material parameters with total conduction band density (N C ) = 3.6 × 1018 cm−3 and valence band density (N V ) = 2.86 × 1020 cm3 are calculated from effective masses of electron and hole. The undoped layer is AlN while the default material parameters utilized in the paper are mentioned in [4–6] with electron-affinity (χ = 1.4 eV). A heterojunction made of AlN/β-Ga2 O3 is assumed perfectly matched with 2.4% mismatch only. A polarization model is exploited to reduce the mismatch, giving charge density of 5.671 × 1013 cm−2 at heterointerface for spontaneous polarization of the AlN zone. Recently, β-Ga2 O3 FETs achieved a maximum density of 1012 cm−2 , Contrary to which the proposed device has utilized an extremely polarized AlN layer to impart higher density of 1013 cm−2 .

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4 Simulation Results and Discussion The drain current (I ds ) as a function of drain voltage (V ds ) at constant gate voltage (V g = 5 V) is plotted in Fig. 2. The graph clearly shows the drain current rising steeply, with lower drain biasing. Compared to AlGaN/GaN HEMT [16], the graph signifies higher mobility in 2DEG AlN/β-Ga2 O3 HEMT. The simulated transfer I-V characteristic curves in linear and log scale are represented in Fig. 3a, b, respectively. In the I D − V GS linear curve, the threshold voltage of −0.9 is expected with I D = 0.1 mA/mm and peak value of transconductance (gm ) = 0.917 S/mm and V GS = −7 V. A major enhancement in I DMAX value for experimental devices is endorsed to spontaneous polarization and higher 2DEG carrier density (nearly 1013 cm−2 ). However, the simulated I-V characteristics did not consider the device’s thermal effects or heat flow. A capacitance-voltage (C-V) analysis of small-signal is performed at 1 MHz frequency. The characteristics of V gs and gate-source capacitance (C gs ) is shown in Fig. 4a, which provided C gs = 0.37 pF/mm and overall gate capacitance C gg = 0.5 pF/mm values. The narrow electron distribution of the charge density confirmed a 2DEG formation at 5 nm underneath the gate giving charge density of 5 × 1013 cm−2 . The characteristic curves of gm and I DS with V GS are shown in Fig. 4b reflecting the peak gm at V G = 2 V. The device shows better driving efficiency, since it has high transconductance due to enhanced current. The cut-off frequency (f T ) has dependence on transconductance (direct proportionality) as well as total capacitance (inverse proportionality). The cut-off frequency, f T vs gate voltage V G curve at V ds =10 V is shown in Fig. 5. The cut-off frequency is defined as a function of equivalent capacitance (C eq ) with respect to transconductance (gm ) variation. Mathematically, cut-off frequency is given by following Eq. (4) Fig. 2 Output characteristics of AlN/β-Ga2 O3 HEMT with L g = 50 nm and L SD = 0.007 μm

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Fig. 3 a Transfer characteristics of the BGO HEMT (L g = 500 nm) on a log scale at V DS = 5 V. b Transfer characteristics of the BGO HEMT (L g = 500 nm) on a linear scale at V DS = 5 V

fT =

gm 2πCeq

(4)

At lower gate bias the values of f T and current density lower within the channel region. When the gate voltage rises from threshold value, the cut-off frequency (f T ) acquires maximum value and afterward it maintains a constant frequency curve.

5 Conclusion The β-Ga2 O3 HEMT with Si3 N4 as dielectric layer, underneath the gate electrode is designed in Silvaco ATLAS tool [17] The Ga2 O3 is a miraculous ultra-wide bandgap material having bright potential to firm its foot in nanotechnology. Various characteristics such as output, transfer, capacitance-voltage, transconductance and cut-off frequency are extracted for the designed Ga2 O3 HEMT by 2-D simulation. The thin barrier layer of AlN escalates the 2DEG at the interface. In addition, the Si3 N4 layer reduces the gate leakage current and indicates a positive shift in threshold voltage. The research suggests AlN/β-Ga2 O3 HEMT to be a promising and extraordinary contender in power electronics applications.

Fig. 4 a Capacitance-voltage characteristics of the BGO HEMT b Transconductance voltage characteristics of BGO HEMT

Gate Capacitance, Cgg (F)

Analog Performance of Normally-On Si3 N4 /AlN/β-Ga2 O3 HEMT

77

2.0×10 -12 (a)

1.5×10 -12

1.0×10 -12

5.0×10 -13 Vds =5V

-2

-1

0

1

2

3

4

5

6

Gate Voltage, Vgs (V) Transconductance, g m (S/µm)

10 0

(b)

10 -2 10 -4 10 -6 10 -8 V ds =5V

10 -10 -2

-1

0

1

2

3

4

5

6

Gate Voltage, Vgs (V)

Fig. 5 Cut-off frequency, f T with V gs at V ds = 10 V

References 1. Higashiwaki M, Jessen GH (2018) Guest editorial: the dawn of gallium oxide microelectronics. Appl Phys Lett 112(6):060401. https://doi.org/10.1063/1.5017845 2. Pearton SJ, Yang J, Cary PH IV, Ren F, Kim J, Tadjer MJ, Mastro MA (2018) A review of Ga2 O3 materials, processing, and devices. Appl Phys Rev 5(1):011301. https://doi.org/10.1063/1.500 6941

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3. Zhang Y et al (2018) Demonstration of high mobility and quantum transport in modulationdoped β-(Alx Ga1−x )2 O3 /Ga2 O3 heterostructures. Appl Phys Lett 112(17), Art. No. 173502 4. Masataka H et al (2016) Recent progress in Ga2 O3 power devices. Semicond Sci Technol 31(3), Art. No. 034001 5. Kumar S, Pratiyush AS, Dolmanan SB, Tripathy S, Muralidharan R, Nath DN (2017) UV detector based on InAlN/GaN on-Si HEMT stack with photo-to-dark current ratio >107 . Appl Phys Lett 111(25), Art. No. 251103 6. Sasaki K, Kuramata A, Masui T, Víllora EG, Shimamura K, Yamakoshi S (2012) Devicequality β–Ga2 O3 epitaxial films fabricated by ozone molecular beam epitaxy. Appl Phys Exp 5(3):035502-1–035502–3 7. Jayant Baliga B (1989) Power semiconductor device figure of merit for high frequency applications. IEEE Electron Device Lett 10(10):455–457 8. Ueda N, Hosono H, Waseda R, Kawazoe H (1997) Synthesis and control of conductivity of ultraviolet transmitting β–Ga2 O3 single crystals. Appl Phys Lett 70(26):3561–3563 9. Chung W, Zhao X, Wu Y-R, Singh J, Palacios T (2008) Effect of image charges in the drain delay of AlGaN/GaN high electron mobility transistors. Appl Phys Lett 92(9), Art. No. 093502 10. Pomeroy W et al (2019) Raman thermography of peak channel temperature in β-Ga2 O3 MOSFETs. IEEE Electron Device Lett 40(2):189–192 11. Wong MH, Morikawa Y, Sasaki K, Kuramata A, Yamakoshi S, Higashiwaki M (2016) Characterization of channel temperature in Ga2 O3 metal-oxide-semiconductor field-effect transistors by electrical measurements and thermal modeling. Appl Phys Lett 109(19), Art. No. 193503 12. Swain R, Jena K, Lenka TR (2016) Modeling of forward gate leakage current in MOSHEMT using trap assisted tunneling and Poole Frenkel emission. IEEE Trans Electron Devices 63(6) 13. Sathaiya DM, Karmalkar S (2006) Thermionic trap-assisted tunneling model and its application to leakage current in nitride oxides and AlGaN/GaN high electron mobility transistors. J Appl Phys 99(9):093701 14. Jauss SA, Schwaiger S, Daves W, Noll S, Ambacher O (2015) Charge trapping in gate-drain access region of AlGaN/GaN MIS-HEMTs after drain stress. In: Proceedings of the 45th European solid-state device research conference (ESSDERC), Sep. 2015, pp 56–59. https:// doi.org/10.1109/ESSDERC.2015.7324712 15. Maeda N et al (2007) Insulator engineering in GaN-based MIS HFETs. Proc SPIE 6473:647316 16. Esposto M, Chini A, Rajan S (2011) Analytical model for power switching GaN-based HEMT design. IEEE Trans Electron Devices 58(5):1456–1461 17. Device Simulation Software (2009) ATLAS User’s Manual, Silvaco, Santa Clara, CA, USA

Modulation of Electronic Properties in Double Quantum Well-Based FET Structure Ajit Kumar Sahu, Narayan Sahoo, and Asutosh Patnaik

Abstract We modulate the electronic properties of symmetric as well as asymmetric Al0.3 Ga0.7 As/GaAs double quantum well (DQW)-based FET structure. The asymmetry in the DQW structure is achieved by considering doping only in the side barrier toward the surface. The subband energies E n , areal electron densities n, and subband occupancy of electrons N n are obtained from the self-consistent solution of Schrodinger and Poisson equation. Here, we analyze the impact of applied electric field F on E n , n, N n, and the potential profile V(z) for different doping concentrations N D . For F = 0, n is equally distributed in each well for symmetric doped structure. When F is applied along the growth direction, the electrons shift from the right to the left side well close to the substrate. Hence, the interface roughness and remote columbic scattering reduce leading to improve the transport properties, e.g., mobility and enhancing the device performance. We also compared the distribution of n and variation of N n in symmetric and asymmetric structures with applied F. Keywords Double quantum well · Symmetric and symmetric structures · Areal electron density

1 Introduction For the last few decades, AlGaAs/GaAs double quantum well (DQW)-based fieldeffect transistor (FET) structures are very popular due to their superior transport as well as optical properties. These devices are emerged due to scaling limits of Si-based devices and are used in high speed and high-frequency applications like CMOS technology, optoelectronic industries, etc. [1]. However, there is still a need A. K. Sahu · N. Sahoo (B) Department of Electronic Science, Berhampur University, Berhampur, Odisha, India e-mail: [email protected] A. Patnaik Department of Electrical and Electronics Engineering, C. V. Raman Global University, Bhubaneswar, Odisha, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_9

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for improvement of this technology as the electrons are placed close to the interface of thin channel FET structures [2]. It increases both the surface roughness and the columbic scattering which normally deteriorates the mobility in the channel and decreases the device performance [2]. It is shown that the application of applied electric field F modifies the potential V (z) of the structure leading to change in the energy levels E n as well as the wave function distributions ψ n inside the wells, thereby affecting the transport properties drastically [3, 4]. Sahoo et al. have revealed that in the presence of F, as electron density increases in an asymmetric single quantum well (SQW) structure, it enhances mobility μ [5]. Inoue et al. calculated electronic states and studied mobility as a function of F in an SQW structure [6]. Huang et al. have developed a charge control model for Al0.3 Ga0.7 As/GaAs SQW-based FET structure [7]. Sahoo et al. have also reported that μ increases with F in PQW structure [8]. Also, they have studied the oscillatory behavior of μ vs F in a DQW structure and shown that the oscillation nature of μ increases by the increase in surface electron density [9]. Kulah et al. significantly increase the 2DEG mobility of inverted AlGaAs/GaAs interface by tuning growth parameters [10]. Although there have been many works on the effect of F to modulate the electronic properties in a single quantum well [3–8] but very few papers reported in DQW-based FET structures. Here, we study the impact of F on low-temperature areal electron density (n) distribution of Al 0.3 Ga0.7 As/GaAs DQW-based symmetric and asymmetric FET structures. In the symmetric structure, the side barriers are doped with doping concentration N D = 2, 3, and 4 × 1024 m−3 . Whereas in the case of the asymmetric doped structure, only the side barrier nearer to the surface is doped with doping concentrations N D = 4, 6, and 8 × 1024 m−3 . The other structure parameters in both cases remain the same. Here, the Schrodinger and Poisson equations are solved self-consistently using Aestimo 1D solver [11]. We show that in the case of symmetric structure as F increases, the areal electron density n shifts from the right to left side well nearer to the substrate side. This reduces the interface scattering and columbic interaction in the FET structure leading to an increase in mobility and subsequently increasing the device performance. We also show that this shifting of electrons is more prominent for higher N D values. However, in the case of asymmetric doping, all the dopants are doped in the right side barrier, although the same F is applied, the electron concentration in the right side well is more as compared to that of the left side well. Resulting transition of subband states from double to single at F = 4, 5, and 6 V/m for N D = 4, 6, and 8 × 1024 m−3 , respectively. The saturation of Moore’s law generates much interest in exploring the replacement of the Si channel in scaled logic FETs. Higher electron mobility with finite potential barrier height reduces leakage current and makes the III-V compound semiconductors-based FET structures suitable for the future scaled logic circuit. With the help of band engineering low-dimensional heterostructures, e.g., quantum well (QW) can be formed in the channel of FET. Application of F perpendicular to the interface plane of a QW changes V (z) leading to change in E n , ψ n , and subband states of the system. The results reflected in this work on shifting of wave functions away from the interface through applied F can reduce the interface roughness scattering effectively and enhance the mobility of the carrier in the channel. The ability

Modulation of Electronic Properties in Double Quantum …

81

to manipulate the subband electronic states and roughness scattering through F has to lead many interesting functional devices.

2 Model Development We consider both symmetric and asymmetric Al0.3 Ga0.7 As/GaAs DQW-based FET structure as shown in Fig. 1a and b, respectively. Here, L W is the well width separated by the central barrier of width L CB . The side barriers are modulation δ-doped with Si of width L D having doping concentration N D at a space distance of L S in Fig. 1a, but in Fig. 1b, the side barrier close to the surface is doped. We use Aestimo 1D solver and obtained the subband energies E n , wave function distribution ψ n , subband electron densities N n , and areal electron density n(z) by solving the Schrodinger and Poisson equation self-consistently [11, 12]. E n and ψ n are obtained from the solution of Schrödinger equation along the z-axis: −

  1 d h d Ψ (z) + V (z)Ψ (z) = E n Ψ (z) 2 dz m ∗ (z) dz

(1)

where m* is the effective mass of electron, and h = h/2π is reduced plank’s constant. The potential V (z) in Eq. 1 is given by V (z) = VS (z) = +VF (z) + VH (z) Fig. 1 a Schematic structure of Al 0.3 Ga0.7 As/GaAs DQW-based symmetric and b asymmetric FET structure

(2)

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V S (z) is the structure potential given by  VS (z) =

Vx , L2CB < |z| < L CB Vb , otherwise

(3)

ΔE c where Vx = α× E g , Eg is the bandgap of GaAs, α = ΔE is the band offset parameter g   2 [11]. ΔE c = 3 E g1 − E g2 is the conduction band offset, ΔE g = E g1 − E g2 is band offset between Alx Ga1-x As and GaAs, and E g1 and E g2 are band gap of Alx Ga1-x As and GaAs, respectively.

Vb = 0.693x + 0.222x 2 eV

(4)

where V b is the band offset between the heterostructure GaAs and Alx Ga1-x As [13, 14] and x is Al concentration in Al x Ga1-x As. VF (z) = e × F × z

(5)

V F (z) is the potential obtained due to applied electric field F. e and z are the charge and position of the electron, respectively. V H (z) is the Hatree potential and obtained by solving Poisson equation [5, 6]: d 2vH 4π e2 = [N0 (z) − n(z)] 2 dz ε0

(6)

where ε0 is dielectric constant of GaAs, N D , n(z) are the impurity and areal electron concentration, respectively, and n (z) can be obtained as [5, 6]: n(z) =



Nn |Ψ (z)|2 , −∞ < z < ∞

(7)

n

where N n is the number of electrons in the nth subband [5, 6]:  Nn =

m∗k B T π h2

  1 + exp(E F − E n ) ln kB T

(8)

where E F , k B , and T are the Fermi energy, Boltzman’s constant, and temperature, respectively. Here, we consider maximum two number of energy levels are occupied at T = 0 K. The basic procedure adopted for calculation of the above parameters is as follows: First, the Schrodinger equation is solved for the considered input potential, i.e., square DQW and calculate E n and Ψ n (z). After that, the Poisson equation (Eq. 5) is solved using the above E n and Ψ n (z) obtained Hatree potential V H (z). The sum of V H (z)

Modulation of Electronic Properties in Double Quantum …

83

along with potential due to external field V F (z) is plugged into Eq. 1 and again calculated E n and Ψ n (z). This self-consistency loop will continue until desired error level is achieved, i.e., 10–10 orders.

3 Results and Discussion Here, we study the impact of F on the subband energy levels E n , subband electron concentrations N n , and areal electron density n in Al0.3 Ga0.7 As/GaAs DQW-based symmetric and asymmetric FET structure. The structure parameters are considered as well width L W = 10 nm, spacer thickness L S = 5 nm, central barrier thickness L CB = 2 nm, and doping region width L D = 2 nm. For symmetry structure, the side barriers are modulation Si-doped of concentrations N D = 2, 3, and 4 × 1024 m−3 . Whereas in the case of asymmetry structure, only the side barrier close to the surface is doped having concentrations N D = 4, 6, and 8 × 1024 m−3 . Here, m* and ε0 for GaAs are 0.067 and 12.85, respectively [13]. The band offset V b between GaAs/Al0.3 Ga0.7 As is 228 meV [13]. We present the structure potential profiles and areal electron densities n for N D = 2, 3, and 4 × 1024 m−3 in Fig. 2a and b, respectively, with applied field F = 0 V/m. Figure 2b shows that n increases with ND and the electron distribution are symmetric in both the wells due to the symmetric nature of doping concentration in the side barriers. As N D increases, the band bending at the interface of the well and barrier increases. This is because of the development of a higher internal F obtained from the solution of Poisson’s equation. We also note that maximum electron concentrations lie at the center of each well. When an external F is applied, it changes the potential profile V (z) depending on the magnitude as well as the polarity of F. The change in V (z) also affects E n ,

Fig. 2 a Potential profile V and b areal electron density n as function of position z of the symmetric DQW structure for F = 0 V/m having different N D

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Table 1 The values of E n , E F , N n for symmetric and asymmetric DQW structure with applied F ND (1024 m−3 ) DQW F structure (V/m)

Ef (meV) E n (meV)

0

2

Symmetric

E1

N n (1015 m−2 ) E2

N1

N2

1036.71

1019.908 1025.231 4.761

3.238

3

1009.28

985.2300 1005.074 6.812

1.187

6

976.74

948.5701 1005.254 8.000

0.000

1069.46

1045.898 1050.639 6.681

5.318

1040.73

1009.855 1029.25

3.244

1010.01

969.8656 1007.939 11.413

0.586

1101.52

1071.169 1075.404 8.610

7.389

1071.54

1033.834 1052.83

10.707

5.292

1039.53

992.7026 1030.128 13.339

2.660

969.744

943.7021 967.5534 7.380

0.619

Asymmetric 945.209

927.7315 934.4091 4.951

3.048

918.221

896.0625 912.119

1.723

970.256

0 3

3

Symmetric

6 0 3

4

6 0 3

4

6 0 3

6

6 0 3 6

8

Symmetric

8.755

6.276

931.7799 966.4881 10.934

1.065

Asymmetric 945.793

916.5374 932.6861 8.295

3.704

918.808

894.6764 900.5487 6.840

5.159

970.804

920.0755 965.4292 14.478

1.521

Asymmetric 946.453

904.8485 931.7092 11.830

4.169

886.8336 895.751

6.726

919.523

9.273

Ψ n , areal electron density n (e/m2 ) as well as the number of occupied subbands N n . This leads to a drastic change in the electro-optical properties of DQW-based devices. Here, we applied positive F from 0 to 6 V/m and calculate E n , n, and N n for symmetric and asymmetric doped structures which are presented in Table 1. To analyze the distribution of electron concentration in each well for F = 3 V/m, we present the potential profile and its corresponding n as a function of z for N D = 2, 3, and 4 × 1024 m−3 in Fig. 3a and b, respectively. We note that the applied F contributes an additional potential resulting in more band bending toward the substrate side. This leads to the shifting of the electrons from the well lying toward the surface to the substrate side of the structure (as shown in Fig. 3b). It is worth noting that the electrons due to the shifting are lying far away from the interface between semiconductor and oxide leading to improvement of channel conductivity. This will also reduce the interface scattering and columbic interaction in FET structure which leads to an increase in mobility and subsequently increases the device performance. We present the potential profile and electron distribution for F = 0 of an asymmetric structure having N D = 4, 6, 8 × 1024 m−3 in Fig. 4a and b, respectively. It is observed that the electron concentration is more in the well which is present near the surface side compared to that of the well lying close to the substrate side. This is due to the asymmetric nature of doping as shown in Fig. 4a. As N D increases, the

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Fig. 3 a Potential profile V and b areal electron density n as function of position z of the symmetric DQW structure for F = 3 V/m having different N D

Fig. 4 a Potential profile V and b areal electron density n as function of position z of the asymmetric DQW structure for F = 0 V/m having different N D

band bending is prominent in the surface side whereas band bending is negligible in the substrate side well. The electron distribution is also asymmetric due to the asymmetric nature of doping, the electron density is more toward the surface side compared to that of the substrate side. To analyze the impact of F in asymmetric DQW structure, we present potential profile and n for N D = 4, 6, and 8 × 1024 m−3 for F = 3 V/m in Fig. 5a and b, respectively. We note that in Fig. 5a, there is doping only toward the surface side and without any applied field, there is more band bending toward the surface side (SS), and this band bending increases with an increase in N D . As there are no dopants toward the SS, the barrier potential height is constantly leading to no band bending. However, when a field F = 3 V/m is applied from the substrate side as shown in Fig. 5b, the band bending height decreases in the surface side leading to the shifting

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Fig. 5 a Potential profile V and b areal electron density n as function of position z of the asymmetric DQW structure for F = 3 V/m having different N D

of some of the electrons from the right side well toward the left side well of the structure. From Table 1, we note that for symmetric structure with fixed N D , (E.g., N D = 2, 3, or 4 × 1024 m−3 ), as F increases E 1 , E 2 , and E F decreases. However, in the case of N D = 2, double subband is occupied up to F = 3 V/m, but in the case of N D = 3 and 4 for all the values of F, two subbands are occupied, and the transport properties will be controlled by intersubband interaction. However, as F increases for all the cases of N D , the electron concentration in the lowest subband increases whereas in the upper subband decreases. However, in the case of asymmetric DQW structure with fixed N D, (E.g., N D = 4, 6, or 8 × 1024 m−3 ), as F increases, E 1 , E 2, and E F also decrease. Moreover, two subbands are occupied for all values of N D for all the values of F. We note that, as F increases, the electron concentration in the lowest subband decreases up to F = 4 V/m, 5 V/m, and 6 V/m for the case of N D = 4, 6, or 8 × 1024 m−3 , respectively. However, the electron concentration in the upper subband with F is reversed. Here, F is applied along the z-axis. As F increases, an additional potential, i.e., V F (z) = eFz is added with the structure potential Vs(z). As a result, the final potential profile including the Hartree potential V H (z) is bent more toward the left side of the structure, i.e., along the opposite side of the growth direction. This leads to a reduction in energy levels E n as well as the Fermi level E F results increasing the electron concentration (N n ) in the lowest subband. As the sum of N n in the lower and upper energy state is fixed, N n in the lower state is increasing with increasing F, leading to a reduction of N n in the upper subband states. To compare our results with the existing work, we note that Ozturk et al. reported the effect of F on the two dimensional donor concentrations N d 2D of Si δ-doped GaAs QW structure [3]. In our proposed work, we compared the effect of diffusion of donor impurities along the z-axis. Here, we have studied the electronic structure of Si modulation doped at the side barriers of GaAs/Al0.3 Ga0.7 As DQW structure. We have

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shown the effect of F on V z , E n , ψ n , and the areal electron density (n) distribution for both symmetric and asymmetric doped DQW structures. As compared to the earlier case, here, the areal density of electrons is more controlled simply by shifting the wave functions from one well to the other far away from the interface through applied F, which can enhance the electron mobility.

4 Conclusion Here, we study the impact of external F on areal electron density n for symmetric as well as asymmetric Al0.3 Ga0.7 As/GaAs modulation doped DQW-based FET structure. The Schrodinger and Poisson equations are solved self-consistently using Aestimo 1D solver and calculate subband energy E n , electron occupancy in each subband states N n , n and study as a function of F. Our results reveal that in symmetric doped structure as the magnitude of F enhances, n shifts to the left side well which lies far away from the surface side of the structure. This reduces the interface scattering and columbic interaction in FET which leads to an increase in mobility and subsequently increases the device performance. However, in the case of asymmetric doping, all the dopants are doped in the right side barrier, and although the same F is applied, the electron concentration in the right side well is more as compared to that of the left side well. Also, as F increases, the electron concentration in the lowest subband decreases up to F = 4 V/m, 5 V/m, and 6 V/m for the case of N D = 4, 6, or 8 × 1024 m−3 , respectively. However, the electron concentration in the upper subband with F is reversed. Acknowledgements Ajit K Sahu acknowledges the financial support received by UGC through the grant no. F.82-44/2020 (SA-III).

References 1. Del Alamo JA (2011) Nanometre-scale electronics with III-V compound semiconductors. Nature 479:317–323 2. Lin J, Antoniadis DA, Del Alamo JA (2015) Impact of intrinsic channel scaling on InGaAs quantum-well MOSFETs. IEEE Trans Electron Devices 62:3470–3476 3. Ozturk E, Ergun Y, Sari H, Sokmen I (2001) Electronic properties of Si δ-doped GaAs under an applied electric field. Semicond Sci Technol 16:421–426 4. Osvald J (2004) Electronic properties of a near surface Si δ-doped GaAs under an applied electric field. J Phys D Appl Phys 37:2655–2659 5. Sahoo N, Sahu T (2014) Electric field induced oscillating electron mobility in asymmetric wide GaAs/Alx Ga1-x As quantum well structure. J Appl Phys 116:1–5 6. Inoue K, Sakaki H, Yoshino J, Hotta T (1985) Self-consistent calculation of electronic states in AlGaAs/GaAs/AlGaAs selectively doped double-heterojunction systems under electric fields. J Appl Phys 58:4277–4281

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7. Huang Y, Chien H, Wang W (1994) Charge control model of the double delta-doped quantumwell field-effect transistor. IEEE Trans Electron Devices 41:1351–1356 8. Sahoo N, Sahu T(2014) Multisubband electron mobility in a parabolic quantum well structure under the influence of an applied electric field. J Semicond 35 9. Sahu T, Sahoo N (2015) Oscillating electron mobility in GaAs/Alx Ga1−x As double quantum well structure under applied electric field. Superlattices Microstruct 77:162–170 10. Kulah E, Reichl C, Scharnetzky J, Alt L, Dietsche W, Wegscheider W (2021) The improved inverted AlGaAs/GaAs interface: its relevance for high-mobility quantum well and hybrid systems. Semicond Sci Technol 36:85013 11. Hebal H, Koziol Z, Lisesivdin SB, Steed R (2021) General-purpose open-source 1D selfconsistent Schrödinger-Poisson Solver: Aestimo 1D. Comput Mater Sci 186:110015 12. Sahu T, Palo S, Sahoo N (2012) Electric field induced enhancement of multisubband electron mobility in strained GaAs/InGaAs coupled quantum well structures. Phys E Low-dimensional Syst Nanostructures 46:155–159 13. Adachi S (1985) GaAs, AlAs, and Alx Ga1−x As: Material parameters for use in research and device applications. J Appl Phys 58:R1–R29 14. Sahoo N, Panda AK, Sahu T (2017) Electron mobility in Alx Ga1−x As based square-parabolic double quantum well HEMT structure−effect of asymmetric doping profile. Physica Status Solidi(b) 254:1700221

Comparative Analysis of Different Types of Gate Field Plate AlGaN/GaN HEMT Pichingla Kharei, Achinta Baidya, and Niladri Pratap Maity

Abstract Aluminium gallium nitride/gallium nitride (AlGaN/GaN) (AlGaN/GaN) have become a major focus for all electronic devices based on GaN, due to the beneficial merger of material properties, including a good thermal conductivity, a wide band gap, high peak and saturated electron velocity, high critical breakdown field, and the capability to set up high-quality hetero-interfaces that forms a high sheet density two-dimensional electron gas (2DEG). Various structures have been proposed to increase the breakdown voltage (V br ) of the device. One of them is introduction of a field plate (FP). In this paper, various types of FPs are considered and compared with respect to the V br characteristics and analogue characteristics. Keywords Field plate (FP) · 2DEG · Breakdown voltage (V br )

1 Introduction Researchers worldwide has recognized gallium nitride (GaN) as the chosen large bandgap semiconductor material owing to its suitable material properties such as high saturation velocity, mobility, thermal conductivity and electric field [1]. Since 2010 GaN power transistors are in volume manufacturing. Nonetheless, as first mentioned in 1993, AlGaN/GaN HEMT is basically normal-ON [2]. Hence their main applications were focused on devices with low voltage and high frequency. In comparison, transistors normally needed for power switching applications are OFF. It is not just essential for security reasons yet additionally decreasing the leakages in current, thereby reducing power loss, simplifying the driving circuit and improving stability of the device [3]. In 1996 an initial demonstration of the AlGaN/GaN HEMT enhancement mode was made [4]. Several approaches were also made to generate normally off GaN-based HEMTs [5, 6]. Some of the challenges faced by the current researchers include improving the V br , enlarging the cut-off frequency (f T ) and reducing the P. Kharei (B) · A. Baidya · N. P. Maity Mizoram University, Aizawl, Mizoram, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_10

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device’s ON-resistance (RON ). Use of FPs greatly enhances the V br [7]. Good physical design is necessary to improve the V br at the same time decreasing RON and increasing f T [8, 9]. TCAD software [10] is used here to study the influence of the FPs on the V br and analogue characteristics of AlGaN/GaN HEMT is given in this paper.

2 Device Structure The adopted structure consists of an n-doped 20 nm AlGaN layer and a GaN channel of 50 nm and SiN passivation layer of 1.2 µm. The length of the gate is 0.5 µm. Space between gate and drain (L gd ) is 3.4 µm and that of source and gate (L sg ) is 1.7 µm. The work function of Schottky gate contact is 5.2 eV. The ATLAS TCAD device simulator is used for simulations, is used. Different simulated structures of gate-FP AlGaN/GaN HEMTs are given in Fig. 1. Physical parameters used in this experiment are listed in Table 1.

Fig. 1 Different gate-FP AlGaN/GaN HEMT structures

Table 1 Material properties of AlGaN/GaN HEMT Property

Units

Mobility of electrons

cm2

900

600

Mobility of holes

cm2 /V-s

10

10

Bandgap

eV

3.4

3.96

/V-s

GaN

AlGaN

Conduction band effective density of states

1018

cm−3

2.20

2.68

Valence band effective density of states

1019 cm−3

2.48

2.03

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In Fig. 1a, AlGaN/GaN HEMT with no FP is given. This is the conventional structure of AlGaN/GaN HEMT. It gives higher frequency as compared with the FPs connected AlGaN/GaN HEMT. Addition of FPs increases the V br . The single gateFP configuration works well to reduce electric field concentration. In this research, we looked into AlGaN/GaN HEMT structures with varied FP designs—G Gate-FP [Fig. 1b], Gate-FP [Fig. 1c], T Gate-FP [Fig. 1d], and F Gate-FP [Fig. 1e]. L

3 Result and Discussion Device structures with various gate-FP designs are simulated in Silvaco and the resulting transfer and V br characteristics are given in Figs. 2 and 3. Comparative analysis for different gate-FP HEMT structures are given in Table 2. In Fig. 2, transfer characteristics of these different structures are given at V DS = 0.05 V and at gate voltage (V G ) sweeping to 0 V from −4 V. This analysis is done at a FP length of 1.7 µm and a gate distance of 2.5 µm from the source. With no FP the V br obtained is 262 V. The increase in V br at this FP length is not much, with a V br of 263 V for -Gate-FP HEMT. The highest V br of 741 V is obtained in G Gate-FP AlGaN/GaN HEMT. The AC analysis for different types of gate-FP AlGaN/GaN HEMT Structures is given in Fig. 4. We can see from Table 3, how the parameters of each structures differ with the positions of the FPs attached to the gate. There is an increase in the capacitance as we introduce the FPs. With FP connected at the gate, the gate to drain capacitance increases [11], degrading the device’s frequency characteristics. L

Fig. 2 Comparison of transfer characteristics for different FP positions

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Fig. 3 Comparison of drain characteristics for different FP positions Cases

Types of gate-FP

I

Without-FP

II

G Gate-FP

III

L

Table 2 Different types of gate-FP structures

IV

T Gate-FP

V

F Gate-FP

Fig. 4 Comparison of Cg-Vg characteristics

Gate-FP

RON (Ohms/mm)

6.39

6.45

AlGaN/GaN HEMT

G Gate-FP HEMT

6.39

6.45

6.48

Gate-FP HEMT

T Gate-FP HEMT

F Gate-FP HEMT

L

Without Gate-FP

0.007

10–12

1.25 ×

1.45 × 10–12

0.007

1.23 × 10–12

1.53 × 10–12

0.007

0.007

1.18 × 10–12

1.22 × 10–12

Gm (S/mm) 0.007

10–12

1.50 ×

1.43 × 10–12

Cgd_max (F/mm) 1.15 × 10–12

Cgs_max (F/mm)

1.39 × 10–12

Table 3 Comparative analysis of varied gate-FP AlGaN/GaN HEMT f T (GHz)

0.45

0.43

0.46

0.46

0.49

f max (Hz)

877

860

889

890

928

V br (V)

724

730

263

741

262

I ds_Leakage (A/mm)

0.1

0.09

0.1

0.1

0.1

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Fig. 5 Comparison of transconductance

It also significantly enhances the device’s transient operation [12]. Regarding the leakage current, T gate-FP AlGaN/GaN HEMT structure is less as compared to other structures considered in this paper. The longer FP length leads to higher output power. The capacitance between the FP and the drain is however, converted to Cgd, leading to negative Miller feedback that results in reduction of f T /f max (Current-gain and power-gain cut-off frequencies) [13]. The single-FP device’s on-resistance grew rapidly as the voltage was applied and its modulation is highly influenced by the electric field distribution [14] (Fig. 5).

4 Conclusion ATLAS TCAD software was used to develop and analyse AlGaN/GaN HEMTs with no FP and varied gate-FP structure placements. The transfer and output characteristics of varied AlGaN/GaN HEMT structures have been accomplished. The field plate electrode was optimized to increase the V br at the gate edge from the drain side. The FP optimization enabled the peak electric field to be separated under the gate edge and the electric intensity along the channel to be reduced. The G Gate-FP HEMT achieved the highest V br in this experiment. Inclusion of FPs have some negative effects on maximum frequency and capacitance.

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References 1. Mishra UK, Parikh P, Wu Y-F (2002) AlGaN/GaN HEMTs-an overview of device operation and applications. Proc IEEE 90(6):1022–1031. https://doi.org/10.1109/JPROC.2002.1021567 2. Khan A, Bhattarai AR, Kuznia J, Olson D (1993) High electron mobility transistor based on a GaN-Alx Ga1-x N heterojunction. Appl Phys Lett 63:1214–1215. https://doi.org/10.1063/1. 109775 3. Zeng F, An J, Zhou G, Li W, Wang H, Duan T, Jiang L, Yu H (2018) A comprehensive review of recent progress on GaN high electron mobility transistors: devices fabrication and reliability. Electronics 7:377. https://doi.org/10.3390/electronics7120377 4. Khan A, Chen Q, Sun C, Yang J, Blasingame M, Shur M, Park H (1996) Enhancement and depletion mode GaN/AlGaN heterostructure field effect transistors. Appl Phys Lett 68:514– 516. https://doi.org/10.1063/1.116384 5. Hu X, Simin G, Yang J, Asif Khan M, Gaska R, Shur MS (2000) Enhancement mode AlGaN/GaN HFET with selectively grown pn junction gate. Electron Lett 36(8), 753–754. https://doi.org/10.1049/el:20000557 6. Greco G, Iucolano F, Roccaforte F (2017) Review of technology for normally-off HEMTs with p-GaN gate. Mater Sci Semicond Process. https://doi.org/10.1016/j.mssp.2017.09.027 7. Ando Y, Okamoto Y, Miyamoto H, Nakayama T, Inoue T, Kuzuhara M (2003) 10- W/mm AlGaN-GaN HFET with a field modulating plate. IEEE Electron Device Lett 24(5):289–291. https://doi.org/10.1109/LED.2003.812532 8. Uren MJ, Karboyan S, Chatterjee I, Pooth A, Moens P, Banerjee A, Kuball M (2017) Leaky dielectric model for the suppression of dynamic RON in carbon-doped AlGaN/GaN HEMTs. IEEE Trans Electron Devices 64(17):2826–2834 9. Jin D, del Alamo JA (2013) Methodology for the study of dynamic ON-resistance in highvoltage GaN field-effect transistors. IEEE Trans Electron Devices 60(10):3190–3196 10. Silvaco Atlas TCAD tool version 3.10.18 R 11. Weiwei K (2008) TCAD simulation and modeling of AlGaN/GaN HFETs. PhD, North Carolina State University 12. Brannick A, Zakhleniuk NA, Ridley BK, Shealy JR, Schaff WJ, Eastman LF (2009) Influence of field plate on the transient operation of the AlGaN/GaN HEMT. IEEE Electron Device Lett 30(5):436–438. https://doi.org/10.1109/LED.2009.2016680 13. Wu YF, Saxler A, Moore M, Wisleder T, Mishra UK, Parikh P (2005) Field-plated GaN HEMTs and amplifiers. In: IEEE compound semiconductor integrated circuit symposium, 2005. CSIC ‘05, Palm Springs, CA, 2005, p 4. https://doi.org/10.1109/CSICS.2005.1531800 14. Saito W et al (2007) Suppression of dynamic on-resistance increase and gate charge measurements in high-voltage GaN-HEMTs with optimized field-plate structure. IEEE Trans Electron Devices 54(8):1825–1830. https://doi.org/10.1109/TED.2007.901150

Advantages of Polarization Engineered Quantum Barriers in III-Nitride Deep Ultraviolet Light-Emitting Diodes: An Electron Blocking Layer Free Approach Ravi Teja Velpula , Barsha Jain , Samadrita Das, Trupti Ranjan Lenka , and Hieu Pham Trung Nguyen Abstract The p-type AlGaN electron barrier layer (EBL) has been widely used to suppress electron leakage from the active region of AlGaN-based deep ultraviolet (UV) light-emitting diodes (LEDs). However, the conventional EBL can reduce the electron leakage partially and invertedly affects the hole injection due to the formation of positive polarization sheet charges at the hetero-interface. Recently, EBL-free LED structures have received significant attention due to the improved carrier transportation and reduced electron leakage. In this context, we present a novel band-engineered EBL-free AlGaN UV LED structure that uses polarizationcontrolled composition-graded convex quantum barriers (QBs) instead of traditional QBs and analyzed its performance theoretically. Our proposed structure opens a new path to control the electron leakage due to both a gradual increase in the effective conduction band barrier height and mitigated electrostatic field in the active region. As a result, the internal quantum efficiency and output power of the reported EBLfree structure are boosted significantly compared to the traditional AlGaN UV LED at ~260 nm emission wavelength. Experimental demonstration of such a unique LED design can show the way to generate high-power deep UV light sources for practical applications. Keywords Polarization · Convex quantum barriers · Electron blocking layer (EBL) · Electron leakage · Internal quantum efficiency (IQE)

R. T. Velpula · B. Jain · H. P. T. Nguyen (B) New Jersey Institute of Technology, University Heights, Newark, NJ 07102, USA e-mail: [email protected] R. T. Velpula e-mail: [email protected] S. Das · T. R. Lenka Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Silchar, Assam 788010, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_11

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1 Introduction Recently, AlGaN ultraviolet (UV) light-emitting diodes (LEDs) got massive attention due to their immense applications such as surface disinfection, including recent SARS-CoV-2 and viruses, air/water purification, biochemical sensing, cancer cell elimination, curing, and many more [1, 2]. Also, these UV LEDs exhibits many advantages, including compact in size, longer lifetime, quick response time, low power consumption, optically tunable emission in UV region, environment-friendly material composition compared to the bulky, and toxic conventional UV lamp technology [3]. However, the current AlGaN deep UV LEDs still exhibit poor external quantum efficiency (EQE) and lower output power due to lack of bulk substrate, high dislocation density, and high resistive p-AlGaN due to inefficient p-type doping with high Al composition, poor carrier confinement in the active region, electron leakage from the active region, and limited LEE due to dominant TM polarization fields [4, 5]. To improve the EQE and optical power of deep UV LEDs, it is necessary to improve the material/epitaxial growth quality and engineer the epitaxial layers. In this context, p-doped (Mg-doped) higher Al composition bulk AlGaN has been introduced as an electron blocking layer (EBL) between the active region and pregion to mitigate the electron leakage from the active region [6]. However, this could suppress the electron leakage problem partially, not completely. In addition to this, hole injection efficiency is severely affected due to the creation of positive polarization sheet charges at the interface of the last quantum barrier and EBL [7], which is another new challenge that has been added to the list. Another challenge of EBL is the higher Mg ionization energy requirement for higher Al composition p-AlGaN layers [8]. Further, the above-mentioned challenges have been addressed by engineering the active region or EBL [9–13]. As a result, the problems raised due to the integration of EBL are solved but with limited success. In this study, we propose a highly efficient EBL-free LED where graded convex quantum barriers (QBs) are utilized instead of conventional QBs. The carrier concentration in multiple QWs is increased; the electron leakage is reduced from the active region and leads to achieving higher output power due to a gradual increase of conduction band barrier heights (CBBHs) at each QBs, reduced valence band barrier height (VBBH) at the interface of the last QB and p-region, and reduced polarization fields at the QB/QW interfaces compared to the conventional EBL-based structure.

2 Device Structure The reference and proposed devices structures are shown in Fig. 1. In this study, we have utilized the Crosslight APSYS tool to systematically study the electrical and optical properties of AlGaN deep UV LEDs. The reference structure, LED1, consists of a 3 µm n-Al0.65 Ga0.35 N layer, five 3 nm Al0.55 Ga0.45 N QWs stacked by five 12 nm Al0.65 Ga0.35 N QBs, 20 nm p-Al0.75 Ga0.25 N EBL, 50 nm p-Al0.65 Ga0.35 N

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Fig. 1 a Schematic diagram of LED1 (reference structure), conduction band diagram of b LED1, and c LED2

hole injection layer (HIL), and finally a 120 nm p-GaN contact layer. The doping concentration of the n-AlGaN layer is 5 × 1018 cm−3 , EBL is 3 × 1019 cm−3 , HIL is 2 × 1019 cm−3 , and the p-contact layer is 1 × 1020 cm−3 . The proposed structure, LED2, is the same as LED1 except for QBs where Al composition is graded from 0.65 to (0.65 + n x%) for the first 6 nm and (0.65 + n x%) to 0.65 for the last 6 nm and completely removed the EBL. n = 1, 2, 3, 4, 5, i.e., number of QB. Figure 1c illustrates the proposed structure, i.e., LED2 with x = 2. The device area is 400 × 400 µm2 .

3 Results and Discussions Figure 2a and b are presenting the calculated energy-band (E-B) diagrams of LED1 (conventional structure) and LED2 (proposed structure EBL-free structure). The calculated effective CBBH for electrons in LED1 due to QBs are 168.29 meV,

Fig. 2 Calculated energy-band diagram of a LED1, and b LED2

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166.23 meV, 164.24 meV, 160 meV, 47.2 meV, and due to EBL is 227.37 meV, as shown in Fig. 2a. From Fig. 2b, the same values in LED2 are 166.22 meV, 190.48 meV, 218.19 meV, 208.39 meV, and 228.58 meV, which are progressively increasing and higher than LED1. This concludes that electrons of LED2 required higher energy to overcome the proposed barriers to overflow to p-region when compared to LED1. Therefore, LED2 can accommodate more electrons in the QWs and have lower electron leakage than LED1. The electron concentration in QWs of both LEDs is shown in Fig. 3a. As expected, LED2 exhibits a higher electron concentration in the QWs. The integrated electron concentration of QWs in LED2 is 7.8 × 1012 cm−2 , and it is 5.5 × 1012 cm−2 for LED1. The effective VBBH for holes due to EBL is 373.22 meV in LED1, which is higher than the VBBH for holes, i.e., 323.65 meV due to the last QB in LED2. This is because of the presence of significant lattice misalignment between the last QB and EBL in LED1. Further, it leads to band bending between the last QB and EBL due to generated polarization fields. Besides, due to the presence of graded QBs in LED2, the polarization fields mitigate at the hetero-interfaces in LED2 [14]. Overall, holes in LED1 required higher energy to be injected into the active region.

Fig. 3 Calculated a electron concentration, b hole concentration, c radiative recombination rate, and d output power of LED1 and LED2

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Fig. 4 Calculated IQE and output power of LED2 at 60 mA current injection when x% varies from 1 to 5% in the Al composition of proposed convex QBs

Also, traditional bulky higher Al composition p-AlGaN EBL is responsible for the formation of positive polarization sheet charges at the interface of the last QB and EBL, which depletes the holes in that region and reduces the hole injection into the active region [7]. Altogether, LED2 exhibits higher hole concentration in the multiple QW active region though it consists of higher VBBHs at each QB because of the mentioned above regions, as shown in Fig. 3b. The integrated hole concentration of QWs in LED2 is 5.76 × 1012 cm−2 , and it is 4.85 × 1012 cm−2 for LED1. Figure 3c shows the calculated radiative recombination rates of LED1 and LED2. It is also understood clearly from Fig. 3b that LED2 reports higher radiative recombination due to the enhanced carrier concentrations in the multiple QWs. The integrated radiative recombination rate of LED2 is 3.73 × 1018 cm−2 s−1 is higher than 2.73 × 1018 cm−2 s−1 of LED1. As a result, higher output power, i.e., 5.05 mW, was observed in LED2 at 60 mA current injection, whereas it was calculated as 3.78 mW in LED1. The calculated output power of both LEDs is shown in Fig. 3d. It is known that severe electron leakage happens at higher current injection which reduces IQE and output power. The proposed structure QBs in LED2 can mitigate the electron leakage and exhibit higher output power. Further, we have estimated the performance of LED2 when the x% value varies from 1 to 5%, and corresponding IQE and output power information at 60 mA current injection is reported in Fig. 4. With the increase of x% from 1 to 4% in the convex QBs, IQE and output power boosted almost linearly, and these values are almost the same with 5%. This improvement is because of the reduced polarization fields at the hetero-interfaces of QWs and QBs in the proposed convex QBs in LED2, even at higher Al in the middle of the QBs.

4 Conclusion In conclusion, we have numerically demonstrated the high-performance EBL-free AlGaN deep UV LED structure with the utilization of graded convex QBs and systematically analyzed its performance. The proposed structure improved the carrier

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concentration and radiative recombination rate in the multi-QW active region, thus recording higher output power than the conventional LED.

References 1. Kneissl M, Seong T-Y, Han J, Amano H (2019) The emergence and prospects of deep-ultraviolet light-emitting diode technologies. Nat Photonics 13(4):233–244 2. Buonanno M, Welch D, Shuryak I, Brenner DJ (2020) Far-UVC light (222 nm) efficiently and safely inactivates airborne human coronaviruses. Sci Rep 10(1):1–8 3. Muramoto Y, Kimura M, Nouda S (2014) Development and future of ultraviolet light-emitting diodes: UV-LED will replace the UV lamp. Semicond Sci Technol 29(8):084004 4. Cho J, Schubert EF, Kim JK (2013) Efficiency droop in light-emitting diodes: Challenges and countermeasures. Laser Photonics Rev 7(3):408–421 5. Kneissl M, Rass J (2016) III-Nitride ultraviolet emitters. Springer 6. Hirayama H et al (2009) 222–282 nm AlGaN and InAlGaN-based deep-UV LEDs fabricated on high-quality AlN on sapphire. Physica Status Solidi (A) 206(6):1176–1182 7. Velpula RT et al (2020) Improving carrier transport in AlGaN deep-ultraviolet light-emitting diodes using a strip-in-a-barrier structure. Appl Opt 59(17):5276–5281 8. Nam K, Nakarmi M, Li J, Lin J, Jiang H (2003) Mg acceptor level in AlN probed by deep ultraviolet photoluminescence. Appl Phys Lett 83(5):878–880 9. Li Y et al (2013) Advantages of AlGaN-based 310-nm UV light-emitting diodes with Al content graded AlGaN electron blocking layers. IEEE Photonics J 5(4):8200309–8200309 10. So B et al (2018) Improved carrier injection of AlGaN-based deep ultraviolet light emitting diodes with graded superlattice electron blocking layers. RSC Adv 8(62):35528–35533 11. Zhang Z-H et al (2018) Nearly efficiency-droop-free AlGaN-based ultraviolet light-emitting diodes with a specifically designed superlattice p-type electron blocking layer for high mg doping efficiency. Nanoscale Res Lett 13(1):122 12. Jain B, Velpula RT, Velpula S, Nguyen H-D, Nguyen HPT (2020) Enhanced hole transport in AlGaN deep-ultraviolet light-emitting diodes using a double-sided step graded superlattice electron blocking layer. JOSA B 37(9):2564–2569 13. Cheng Liu B, Zhang J (2020) AlGaN-delta-GaN quantum well for DUV LEDs. Photonics 7(4):13 14. Zhang Z-H et al (2014) Self-screening of the quantum-confined Stark effect by the polarization induced bulk charges in the quantum barriers. Appl Phys Lett 104(24):243501

Investigation on Thermodynamic Properties of Novel Ag2 SrSn(S/Se)4 Quaternary Chalcogenide for Solar Cell Applications: A Density Functional Theory Study Ashutosh Srivastava, Trupti Ranjan Lenka, Jesuraj Anthoniappen, and S. K. Tripathy Abstract Novel semiconductor materials to be used as absorber materials in solar cell, and their thermodynamic behavior needs to be analyzed at large as solar cell devices undergo temperature variations. Therefore, density functional theory-based analysis has been carried out to examine the thermodynamic properties of novel quaternary chalcogenide material Ag2 SrSn(S/Se)4 in its kesterite and stannite structures, in 0–1100 K temperature range at 0 GPa pressure. Ag2 SrSnS4 (Sta) has the highest calculated melting point of 638 K and hardest amount all four structures. Vibrational heat capacity at constant volume (Cv ) for all four structures is saturated at 199.45 Jmol−1 K−1 . Vibrational entropy increases with increase in temperature. It is observed that stannite structures of both materials are prone to dimension changes with temperature, due to higher value of coefficient of thermal expansion (α). The change in internal energy of the crystal is linear with respect to temperature. Keywords Chalcogenides · Thermodynamic property · Melting point · DFT

1 Introduction Thin film solar cells (TFSCs) have won the trust of the photovoltaic researchers, owing to their excellent electrical characteristics along with low fabrication cost [1]. Copper-based quaternary chalcogenides and copper zinc tin sulfide (Cu2 ZnSnS4 , CZTS) have entered the solar cell arena as the clean material having earth crust abundant elements, with well suited energy bandgap of 1.4 eV-1.5 eV and good absorption coefficient [2]. The highest power conversion efficiency (PCE) of 12.6% for CZTS/Se based solar cell device has been reported by IBM in the year 2013 [3]. A. Srivastava (B) · T. R. Lenka · S. K. Tripathy National Institute of Technology Silchar, Silchar, Assam, India e-mail: [email protected] J. Anthoniappen Department of Physics, University of San Carlos, Talamban Campus, 6000 Cebu City, Philippines © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_12

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In past two decades, there is no improvement in PCE of CZTS/Se-based solar cells due to antisite defects present in the material. This become the key factor which is responsible for such stagnation in PCE [4]. Hence, researchers have put emphasis to find alternative novel absorber materials, that can replace CZTS in TFSC and improve the solar cell performance. Recently, the structural and optoelectronic properties A2 XSnS4 (A = Cu, Ag, and X = Mn, Be, Ca, Mg, Ni, and Fe) have been studied using theoretically and experimentally techniques [5–7]. However, in addition to the aforesaid properties, investigation of thermodynamic and mechanical properties plays a key role in order to use material as an absorber layer [8, 9]. Isik et al. have recently studied thermodynamic properties of Bi12 GeO20 compound to validate its applications in devices working in ultraviolet applications [10]. Also, very recently, Lu et al. have studied thermodynamic behavior novel C40-type CrSi2 , MoSi2, and WSi2 disilicides using first principles, for optical shielding purposes [11]. Quaternary chalcogenide material Ag2 SrSnS/Se4 obtained by replacing Cu by Ag and Zn by Sr in CZTS/Se can be employed as an absorber layer material in TFSC [12]. In the present work, investigations are done on the thermodynamic properties of Ag2 SrSnS/Se4 in its kesterite and stannite phases in temperature range of 0–1100 K, employing quasi-harmonic Debye model employing first principles calculations [13]. In Sect. 2, computational methodology used in the entire work has been discussed. Thermodynamic properties of all four structures are discussed in detail in Sect. 3. The conclusion of the work is discussed in Sect. 4.

2 Computational Details In this work, thermodynamic properties of novel chalcogenide Ag2 SrSnS/Se4 materials are studied. All calculations have been performed using Vienna ab initio simulation package (VASP). For electronic interactions, generalized gradient approximation (GGA) functional of Perdew-Burke-Ernzerhof (PBE) [14] is utilized. The cutoff energy of 520 eV and 480 eV, respectively, for Ag2 SrSnS4 and Ag2 SrSnSe4 in their kesterite and stannite phases have been taken. Explicitly, Monkhorst–Pack k-mesh of 5 × 5 × 5 was used for non-local exchange. A tight convergence criterion of 1 meV/Å for atomic forces has been set and for electronic iterations, convergence criterion of 1 × 10–6 eV was allotted.

3 Results and Discussion 3.1 Thermodynamic Properties Using quasi-harmonic approximation (QHA) [13], we have investigated the thermodynamic properties of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes),

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and Ag2 SrSnSe4 (Sta) in the temperature range 0–1100 K at 0 Gpa pressure. Debye temperature links the elastic properties of any material with the thermodynamic properties, and it corresponds to the normal mode of vibrations of a crystal. The Debye temperature can be calculated using Eq. (1) [9]:

θD =

  1/ 3 h 3n N A ρ Vm K B 4π M

(1)

where N A is the Avogadro number, M is the molecular weight of the unit cell, V m is the mean sound velocity, n is the atoms count in the unit cell, h is the Plank’s constant, and K B is the Boltzmann constant. The calculated values of Debye temperature are listed in Table 1. In order to coin new solar cell materials, it is very much important to investigate its melting point. For tetragonal structures using elastic constants (C 11 and C 33 ), melting point (T m ) can be computed using the below given empirical formula [15].   2C11 + C33 Tm = 354 + 4.5 3

(2)

The calculated values of melting point are given in Table 1. It is evident from Table 1 that Ag2 SrSnS4 in both phases have high-melting point, making it suitable for solar cell absorber material applications. Also, the high-melting point temperature for Ag2 SrSnS4 shows that the atoms in its crystal lattice are tightly arranged. Mathematically, heat capacity is the derivative of the internal energy of a material in context to ambient temperature or physically it can be understood as the amount of heat required to bring one degree change in temperature of the material [16]. Figure 1 shows the variations in heat capacity at constant volume vs temperature for all four materials studied here. It can be observed from Fig. 1 that C v varies by T −3 at lower temperature and at higher temperature its becomes almost constant reaching to its Dulong–Petits limit, which is numerically calculated as 3nNA KB (199.45 Jmol−1 K−1 ), where symbols have their usual meaning [17]. Also from Fig. 1, it is observed that at Debye temperature, a small break is observed in Cv plot for all four structures, which can be attributed to dependence of Debye temperature on atomic size, ambient temperature, and bond nature exist in the material. Figure 2 shows the calculated vibrational entropy of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta) against temperature. From Fig. 2, Table 1 Vickers hardness (H v ), Melting point (T m ), and Debye temperature (Θ D ) of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta)

Absorber layer material

Hv

T m (K)

Θ D (K)

Ag2 SrSnS4 (Kes)

−2.32

615

160.2

Ag2 SrSnS4 (Sta)

−2.34

638

157.3

Ag2 SrSnSe4 (Kes)

−1.69

589

164.8

Ag2 SrSnSe4 (Sta)

−2.24

582

134.3

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Fig. 1 Vibrational heat capacity of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta)

Fig. 2 Vibrational entropy of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta)

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Fig. 3 Calculated values of coefficient of thermal expansion of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta)

it can be observed that entropy keeps increasing as the temperature is increasing, which is consistent with the basic physics as entropy increases with lattice vibrations and electronic excitation as the temperature increases. Also the electronic transitions inside the material escalate with the absorbed energy. Variations in coefficient of thermal expansion vs temperature are depicted in Fig. 3, for all four structures being studied here. In terms of physics, coefficient of thermal expansions is a material property that indicates the material expansion when exposed to temperature variations. The variation pattern of α is similar to Cv, where at lower temperature, it rapidly varies and becomes almost constant at higher temperature. From Fig. 3, it can be understood how the dimensions of all four material changes on thermal exposure, which is quite interesting for materials to be explored as thin film materials. It is observed from Fig. 3, that stannite structures of both materials have higher α value at the point of saturation showing they will be more prone to dimension changes with temperature. In other words, we can also say that kesterite structures will not undergo dimensions deformation when used in solar cells. Change in internal energy of a material is calculated using the formula, E Vib (T ) = E(T ) − E(0)

(3)

where E(T ) is the vibrational internal energy at temperature T of the system and E (0) is the zero-point energy of the crystal. The calculated values of zero-point energy are 11.98, 11.77, 12.34, and 10.05 kJ/mol, respectively, for Ag2 SrSnS4 (Kes),

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Fig. 4 Change in vibrational internal energy of Ag2 SrSnS4 (Kes), Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta)

Ag2 SrSnS4 (Sta), Ag2 SrSnSe4 (Kes), and Ag2 SrSnSe4 (Sta). Figure 4 shows the change in internal energy variations, with respect to temperature for all four structures. It is evident from Fig. 4 that, as the temperature is increased, the internal energy of the crystal is also increased, showing linear increment in internal energy change occurring between two different temperature.

3.2 Vickers Hardness Mechanical properties of a material are not just analyzed by the elastic modulus but also by the hardness of the material. Using the calculated values of shear modulus and Young’s modulus, Vickers hardness has been calculated using empirical relation given below [18]. HV = (2k 2 G)0.585 − 3, where k = G/B

(4)

From Table 1, we can observe that Ag2 SrSnS4 (Sta) is the hardest of all the four structures. Furthermore, it is also seen that stannite structures are harder than the kesterite structures for both the materials.

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4 Conclusion In this work, kesterite and stannite phases of novel Ag2 SrSnS/Se4 chalcogenide materials have been studied using GGA-PBE method of DFT. The Vickers hardness and various thermodynamic properties have been investigated and found that Ag2 SrSnS4 (Sta) is the hardest material among all four studied structures. Also, it is established that kesterite structures have higher Debye temperature as compared to stannite one for both the materials. Ag2 SrSnSe4 (Kes) has the highest Debye temperature of 164.8 K. Also, the melting point of all four materials is nearly same and quite high, showing that they all can withstand good temperature exposure. Further, the stannite structures of both materials have higher value of coefficient of thermal expansion (α) at saturation point, showing them to be more prone to dimension changes with temperature. This study will encourage to carry out experimental validation. Further, this study will surely encourage the fabrication of Ag2 SrSnS/Se4 chalcogenide-based solar cells. Acknowledgements The authors are thankful to CSIR, New Delhi, Government of India, for granting under Extra Mural Research-II scheme (File No. 70(0076)/19/EMR-II). We are also thankful to Prof. Sivaji Bandyopadhyay, Director, National Institute of Technology, Silchar, for his continuous encouragement and inspiration in conducting this work.

References 1. Green MA, Ho-Baillie A, Snaith HJ (2014) The emergence of perovskite solar cells. Nat Photonics 8(7):506–514. https://doi.org/10.1038/nphoton.2014.134 2. Kowsar A et al (2019) Progress in major thin-film solar cells: Growth technologies, layer materials and efficiencies. Int. J. Renew. Energy Res. 9(2):579–597 3. Wang W et al (2014) Device characteristics of CZTSSe thin-film solar cells with 12.6% efficiency. Adv Energy Mater 4(7):1–5. https://doi.org/10.1002/aenm.201301465 4. Bourdais S et al (2016) Is the Cu/Zn disorder the main culprit for the voltage deficit in Kesterite solar cells? Adv Energy Mater 6(12):1–21. https://doi.org/10.1002/aenm.201502276 5. Srivastava A et al (2020) Structural, electronic and optical properties of Ag2 MgSn(S/Se)4 quaternary chalcogenides as solar cell absorber layer: An Ab-initio study. Sol Energy 209(July):206–213. https://doi.org/10.1016/j.solener.2020.08.094 6. Rondiya S, Wadnerkar N, Jadhav Y, Jadkar S, Haram S, Kabir M (2017) Structural, electronic, and optical properties of Cu2 NiSnS4 : A combined experimental and theoretical study toward photovoltaic applications. Chem Mater 29(7):3133–3142. https://doi.org/10.1021/acs.chemma ter.7b00149 7. Chen R, Persson C (2017) Electronic and optical properties of Cu2 XSnS4 (X = Be, Mg, Ca, Mn, Fe, and Ni) and the impact of native defect pairs. J Appl Phys 121(20):1. https://doi.org/ 10.1063/1.4984115 8. He X, Shen H (2011) First-principles study of elastic and thermo-physical properties of kesterite-type Cu2 ZnSnS4 . Phys B Condens Matter 406(24):4604–4607. https://doi.org/10. 1016/j.physb.2011.09.035 9. He X, Pi J, Dai Y, Li X (2013) Elastic and thermo-physical properties of stannite-type Cu2 ZnSnS4 and Cu2 ZnSnSe4 from first-principles calculations. Acta Metall Sin (English Lett) 26(3):285–292. https://doi.org/10.1007/s40195-012-0248-4

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10. Isik M, Surucu G, Gencer A, Gasanly NM (2021) First principles study of Bi12 GeO20 : Electronic, optical and thermodynamic characterizations. Mater Today Commun. 27:102299. https://doi.org/10.1016/j.mtcomm.2021.102299 11. Lu Y, Duan Y, Peng M, Yi J, Li C (2021) First-principles calculations of electronic, optical, phononic and thermodynamic properties of C40-type TMSi2 (TM = Cr, Mo, W) disilicides. Vacuum 191:110324. https://doi.org/10.1016/j.vacuum.2021.110324 12. Srivastava A, Tripathy SK, Lenka TR, Hvizdos P, Menon PS, Lin F, Aberle AG (2021) Device simulation of Ag2 SrSnS4 and Ag2 SrSnSe4 based Thin-Film solar cells from scratch. Adv Theory Simul. https://doi.org/10.1002/adts.202100208 13. Blanco MA, Francisco E, Luaña V (2004) GIBBS: Isothermal-isobaric thermodynamics of solids from energy curves using a quasi-harmonic Debye model. Comput Phys Commun 158(1):57–72. https://doi.org/10.1016/j.comphy.2003.12.001 14. Perdew JP, Burke K, Ernzerhof M (1998) Perdew, Burke, and Ernzerhof reply. Phys Rev Lett 80(4):891. https://doi.org/10.1103/PhysRevLett.80.891 15. Fine ME, Brown LD, Marcus HL (1984) Elastic constants versus melting temperature in metals. Scr Metall 18(9):951–956. https://doi.org/10.1016/0036-9748(84)90267-9 16. Liu X et al (2019) First-principles calculations of mechanical and thermodynamic properties of tetragonal Be12 Ti. RSC Adv 9(10):5302–5312. https://doi.org/10.1039/c8ra08711c 17. Srivastava A, Tripathy SK, Lenka TR, Menon PS, Lin F, Aberle AG (2021) An ab-initio investigation of mechanical and thermodynamic properties of Ag2 MgSn(S/Se)4 in kesterite and stannite phases. Appl Phys A 127(8):590. https://doi.org/10.1007/s00339-021-04741-0 18. Chen XQ, Niu H, Li D, Li Y (2011) Modeling hardness of polycrystalline materials and bulk metallic glasses. Intermetallics 19(9):1275–1281. https://doi.org/10.1016/j.intermet.2011. 03.026

Impact of Carcinogenic Benzene on Electronic Properties of Mnand Fe-Doped MoSe2 Monolayer Neha Mishra and Bramha P. Pandey

Abstract The impact of adsorption of benzene molecule on pristine and doped (Mn, Fe) MoSe2 monolayer is shown in this paper. The benzene, being a non-magnetic molecule by nature, has health-threatening effects on human body. The adsorption of benzene is focused on two configurations, namely pristine and doped MoSe2 monolayer. The higher adsorption energy is witnessed for Fe-doped MoSe2 monolayer. Likewise, the charge transfer also excels for Fe-doped MoSe2 monolayer in benzene adsorption rather than the other configurations. However, the individual charge transfer between surrounding atoms is higher for Mn atom. To show the capability of MoSe2 monolayer to detach the adsorbed benzene molecule, the recovery time is estimated. It is observed that with higher adsorption energy, the recovery time is increased. It is difficult to remove the adsorbed molecule from the surface at lower temperature, so to facilitate easy removal, the temperature is increased to high value of 498 K. Thus, it is concluded that MoSe2 monolayer is suitable for designing of green sensors with lower recovery time and high adsorption energy. Keywords Charge transfer · Adsorption · MoSe2 · C6 H6 · Recovery time

1 Introduction The pursuit for new materials with exceptional properties is always in prioritized by the research community. In this direction, the family of layered two-dimensional transitional metal dichalcogenide (2D TMDs) material is an indispensable pioneer due to ubiquitous (structural, electronic, optical, and magnetic) properties. These 2D materials are preferred choice for surface study due to large surface-to-volume ratio with numerous adsorption sites for incoming agents (molecules, atoms) [1]. The 2D MoSe2 monolayer is a suitable choice to study the surface dynamics with and without interaction of external agents owing the exceptional properties [2]. Researchers are N. Mishra · B. P. Pandey (B) Department of Electronics and Communication Engineering, Madan Mohan Malaviya University of Technology, Uttar Pradesh, Gorakhpur, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_13

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enhancing the properties of the 2D materials with different approaches like doping, external electric field, gas adsorption, catalytic reduction, and many other [3]. The 2D TMDs belong to the hexagonal closed packed (hcp) crystals, with different polytropes such as 2H (semiconducting), 1 T (metallic), and 3R, respectively [4]. To study, the adsorption of gas molecules and modulation in properties upon adsorption 2H polytype is opted. The orient of 2D monolayers includes centered transition metals M (Mo and W) surrounded by chalcogenide atoms X (S, Se, and Te) from top and bottom. They possess stiff covalent bonding in the intralayer and universal Van der Waals in the interlayers. Experimentally, there are different methods to extract the monolayers from their bulk counterpart such as chemical vapor deposition (CVD), mechanical exfoliation, wet chemical, hydrothermal, and Scotch method [5]. The most preferred is mechanical exfoliation method with reduced defects, lowered roughness leading to smooth surface extraction [6]. The transition from bulk to monolayer adds a feature of tunable bandgap, as a unique feature to these 2D materials. This is due to the shift of peaks from G to other high symmetric points such as K, L, M, and A and thus known as direct-bandgap (Eg ) materials. The bandgap can be tuned up to ~2 eV in the 2D TMD monolayers as compared to their bulk states [7]. The other properties involve bandgap splitting, lack of inversion symmetry which gives rise to phenomena of valleytronics, etc., aligning them suitable for nano-electronic devices such as photo-detectors, solar absorbers, and efficient gas sensors [8]. The study of adsorption of benzene on 2D (two-dimensional) material is reported on WS2 , MoS2 , and WTe2 monolayer, showing the monolayers as direct-bandgap semiconductors post-benzene gas adsorption [9]. However, the impact of benzene gas adsorption on MoSe2 monolayer has not been studied so far. There is no evidence about the change in semiconducting nature of MoSe2 monolayer due to benzene gas adsorption. Thus, this motivates the authors, to study the adsorption impact of benzene gas molecule on MoSe2 monolayer. In this study, the cancer causing benzene is adsorbed on the MoSe2 surface, and relative change in the properties is reported. The benzene molecule has threatening impact on human health. The lifestyle habits like chewing tobacco and smoking are a common source of benzene. It is a cause of lung cancer, a source of damage to the blood forming organs, has detrimental impact on bone marrow in human body. Also, it lowers the red blood cells causing ammonia. Due to these reasons, the International Agency for Research on Cancer (IARC), body of WHO that is concerned to the study of cancer agents, declares it as “cancer causing” with the reason that benzene is responsible for acute myloid leukemia, and other cancer types like acute lymphocytic leukemia, chronic lymphocytic leukemia, multiple myeloma, and non-Hodgkin lymphoma in human body [10]. The paper is composed of five sections, where Sect. 1 introduces to the study of carcinogenic benzene and features of TMD materials, while Sect. 2 gives the details of simulation set up computationally and extraction of the electronic properties, further, Sect. 3 discusses the extracted electronic parameters with Sect. 4 showing the recovery time, and thus, Sect. 5 concludes the paper with the scope of future progresses to augment the performance of the gas sensors based on these materials.

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2 Computational Details The calculations are estimated using Spanish Initiative of Electronic Simulation with thousands of atoms (SIESTA) under the frame of density functional theory (DFT) through first-principle calculations [11]. The spin-polarized calculations for 4 × 4 × x1 MoSe2 monolayer are performed with energy cut-off of 550 eV, force tolerance of 1 × 10–5 eV/Å, and convergence criteria of 10–5 eV. The Grimme D2 method is adopted to include the two-body interaction in our calculation [12]. The optimizations are supported with generalized gradient approximation (GGA) exchange functional under Perdue–Burke–Erzenhoff (PBE) interactions [13, 14]. The k-points are set to 8 × 8 × 1 (10 × 10 × 1) for geometry optimization (electronic calculations) with the Monkhorst K-grid scheme [15]. The basis set is extracted using double-zeta polarization (DZP) with split-type parameter of 0.15 Ry. The pseudopotential files are GGA of PBE for Mo, Se, Mn, Fe, C, and H, respectively. The interaction between benzene molecule and monolayer atoms is explored with charge transfer, calculated in units of electrons (e) by Hirshfield analysis [16]. The inter-slab interactions are avoided using a vacuum of 12 Å along the z-direction.

3 Result and Discussion 3.1 Geometrical Information The MoSe2 monolayer crystallizes into hexagonal closed packing with P6m2 space group. The Se-Mo-Se atoms contribute to a honey comb-like structure with periodicity in two lattice dimensions, namely a = b = 13.27 Å and c = 33.19 Å separately. Next, the optimized structure of MoSe2 monolayer in front and side view is displayed in Fig. 1a. The benzene molecule (C6 H6 ) with a hexagonal ring layout is opted for adsorption as displayed in Fig. 1b.

3.2 Adsorption Energy with Charge Transfer The adsorption energy and charge transfer with benzene as adsorbent on pristine and doped (Mn, Fe) MoSe2 monolayer is studied in this section. The adsorbent is located at a height of 2 Å in the relaxed for both pristine and doped geometries. The adsorption energy denoted by Eads is used to predict the extent of interaction of incoming molecule with the monolayer surface. The adsorption energy for benzene adsorbed on pristine MoSe2 monolayer is calculated to be −4.415 eV, −67.24 eV for Mn-doped MoSe2 monolayer and –73.43 eV for Fe-doped MoSe2 monolayer, respectively, as shown in Fig. 2. The equation governing the adsorption energy is given by (1) [7].

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Fig. 1 a Front view b Side view of benzene adsorbed on pristine MoSe2 monolayer

C6H6/MoSe2 ML -4.415 eV

C6H6/Fe-MoSe2 ML -73.43 eV

C6H6/Mn-MoSe2 ML -67.24 eV

Fig. 2 Schematic showing increase in adsorption energy from pristine to doped (Mn, Fe) MoSe2 ML

E ads = E gas+monolayer − E gas − E monolayer

(1)

Here, E gas+monolayer denotes total energy of the adsorbed gas molecule on the monolayer; next, E gas is the energy of the adsorbed gas molecule, and lastly, E monolayer is the total energy of the MoSe2 monolayer. Another parameter of interest is the charge transfer between the adsorbed C6 H6 molecule and MoSe2 monolayer in both pristine and doped cases. It is estimated using Hirshfeld atomic population method. The equation in frame for calculation of

Impact of Carcinogenic Benzene on Electronic Properties … Fig. 3 Charge transfer shift from pristine to doped (Mn, Fe) MoSe2 ML

115 C6H6/MoSe2 ML -0.622e

C6H6/Fe-MoSe2 ML 21.686e

C6H6/Mn-MoSe2 ML 22.536e

the charge transfer is given as (2) [17]. QTotal = Qads − Qiso

(2)

Therefore, for the pristine monolayer, the charge transfer is estimated to be -0.622e for pristine MoSe2 monolayer, 22.536e for Mn-MoSe2 monolayer, 21.686e for FeMoSe2 monolayer as shown in Fig. 3. Moreover, it is noticed that a charge transfer of 1.919 (2.782) e occurs between doped Mn (Fe) and surrounding Se atoms. Here, negative sign denotes the electron donating nature, while positive value shows the electron withdrawing nature of the adsorbent benzene molecule toward the pristine and doped monolayer.

4 Recovery Time Recovery time is used to predict the desorption capability of the monolayer surface. As adsorption is used to account the interaction ability of the incoming molecule on the surface monolayer, recovery time estimates the time the incoming molecule remains attached on the surface of monolayer. Lower is the recovery time of the incoming molecule better will be the performance of gas sensor. The empirical equation governing the recovery time and adsorption energy is given by (3) [18–21]. −E a

τ = A−1 ∗ e 2K T

(3)

where A is Arrhenius factor estimated to be 10–14 for N2 O gas molecule, E ads is the adsorption energy (in eV), and T is the temperature (in K). The process of desorption is facilitated with the increase of temperature. Thus, the temperature is increased from 298 to 498 K, and the recovery time is estimated to vary from 9.56 × 10–13 to 4.68 × 10–13 for pristine MoSe2 monolayer, 0.0973 to 1.81 × 10–6 for benzene adsorbed on Mn-doped MoSe2 monolayer and 1.182 to 8.05 × 10–6 for benzene adsorption on Fe-doped MoSe2 monolayer, respectively, as listed in Table 1. Thus, we observe that recovery is minimized to higher temperature of 498 K for

116 Table 1 Variation of recovery time with temperature for absorbed C6 H6 molecule on pristine and doped (Mn, Fe) MoSe2 ML

N. Mishra and B. P. Pandey Configuration

Temperature (in K) Recovery time (in sec)

MoSe2 ML

298

9.57 × 10–13

398

6.12 × 10–13

498

4.68 × 10–13

Mn- MoSe2 ML 298

Fe-MoSe2 ML

0.0973

398

1.07 × 10–4

498

1.81 × 10–6

298

1.182

398

6.92 × 10–4

498

8.05 × 10–6

both the pristine and doped MoSe2 monolayer. Also, we notice that recovery time is minimized for pristine MoSe2 monolayer as compared to Mn and Fe-doped MoSe2 monolayer configurations at a temperature of 498 K. Lastly, the parameter selectivity predicts the reliability of the 2D TMD-based ML. It is governed by the following equation below [18, 19]. η=

R g − Ra Ra

(4)

Here, Rg and Ra are resistances symbolizing under gas adsorption and in pristine state that is related to change in charge transfer in direct proportion as Q . Here, Ra Rg is analogous to charge transfer during the gas adsorption which is 22.536 e (21.686 e) for C6 H6 adsorbed on Mn (Fe)-doped MoSe2 monolayer, respectively. Ra represents charge transfer in pristine state for Mn (Fe)-doped MoSe2 monolayer which is observed to be 1.267e (2.00e) separately [22, 23]. Thus, the selectivity for Mn (Fe)-doped configuration is 16.786 (9.843), higher for Mn-doped MoSe2 monolayer relative to Fe-doped MoSe2 monolayer. In the study, it is observed that with the variation in transfer of charges upon the adsorption of gas molecule in both the pristine and doped configurations the selectivity is increased. Further, this aligns with the increase in adsorption energy, which increases the charge transfer as illustrated in subsection 3.2.

5 Conclusion The impact of benzene molecule on pristine and doped (Mn, Fe) MoSe2 monolayer in terms of electronic properties (such as adsorption energy, charge transfer, and recovery time) is explored in this paper. The benzene molecule is a carcinogenic in nature and a major cause of different hazardous outcomes for human health. It damages the bone marrow and reduces the platelets in human blood. The adsorption

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of benzene on Fe-doped MoSe2 monolayer is higher than the Mn-doped configurations by 8.42% and 93.9% for pristine MoSe2 monolayer. The charge transfer is observed to be maximized for Fe-doped MoSe2 monolayer by 31.02% than the other studied configurations. The employment of MoSe2 monolayer for effective sensing of benzene molecule is described through the recovery time. It is shown that higher adsorption energy of the configuration has higher recovery time also. It concludes that higher adsorption of the benzene molecule takes more time to detach from the surface, hence, increasing the recovery time. It is in alignment with Fe-doped MoSe2 monolayer with higher absolute adsorption energy of 73.43 eV and recovery time of 8.05 × 10–6 s, respectively. The study of disease causing benzene molecule on the surface of MoSe2 monolayer presents its capability as a nano-sensor and widens the space for eco-friendly sensors for health care as future scope of work.

References 1. Burghaus U (2019) Gas-surface interactions on two-dimensional crystals. Surf Sci Rep 74:141– 174 2. Babar V, Vovusha H, Schwingenschlo U (2019) Density functional theory analysis of gas adsorption on monolayer and few layer transition metal dichalcogenides: Implications for sensing. ACS Appl Nano Mater 9:6076–6080 3. Yuan XB, Tian YL, Zhao XW, Yue WW, Hua GC, Ren JF (2018) Spin polarization properties of benzene/graphene with transition metals as dopants: First principles calculations. Appl Surf Sci 439:1158–1162 4. Yuan XB, Cai LL, Tian YL, Hua GC, Rena JF (2018) Electric field induced spin polarization oscillation in nonmagnetic benzene/Cu (100) interface: First principles calculations. Appl Surf Sci 427:156–161 5. Donarelli M, Ottaviano L (2018) 2D materials for gas sensing applications: A review on graphene oxide, MoS2 , WS2 and phosphorene. Sensors 18:1–45 6. You B, Wang X, Chen G, Zheng Z (2017) Prediction of electronic structure of van der Waals interfaces: Benzene adsorbed monolayer MoS2 , WS2 and WTe2 . Physica E 88:87–96 7. Shokria A, Salami N (2016) Gas sensor based on MoS2 monolayer. Sens Actuators, B Chem 236:378–385 8. Bui VQ, Le HM, Kawazoe Y, Kim Y (2016) Adjusting band gap and charge transfer of organometallic complex adsorbed on MoS2 monolayer using vertical electric-field: a first-principle investigation. J Phys: Condens Matt 29:1–13 9. You B, Wang X, Chen B, Zheng Z (2017) Prediction of electronic structure of van der Waals interfaces: Benzene adsorbed monolayer MoS2 , WS2 and WTe2 . Phys E: Low-Dim Sys and Nano 88:87–96 10. Exposure To Benzene (2010) A major public health concern. WHO, Geneva, Switzerland 11. Soler JM, Artacho E, Gale JD, Garcia A, Junquera J, Ordejón P, Sánchez-Portal D: The SIESTA method for ab initio order-N materials simulation. J Phys: Condens Matt 14:2745 12. Grimme S (2006) Semi empirical GGA-type density functional constructed with a long-range dispersion correction. J Comput Chem 27:1787–1799 13. Hammer B, Hansen LB, Nørskov JK (1999) Improved adsorption energetics within densityfunctional theory using revised Perdew- Burke-Ernzerhof Functionals. Phys Rev B: Condens Matter Mater Phys 59:7413 14. Perdew JP, Burke K, Ernzerhof M (1996) Generalized gradient approximation made simple. Phys Rev Lett 77:3865

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15. Monkhorst HJ, Pack JD (1976) Special points for Brillouin-zone integrations. Phys Rev B 13:5188–5192 16. Hirshfeld FL (1977) Bonded-atom fragments for describing molecular charge densities. Theor Chim Acta 44:129–138 17. Henkelman G, Arnaldsson A, Jonsson H (2006) A fast and robust algorithm for Bader decomposition of charge density. Computational Mat Sci 36:354–360 18. Peng S, Cho K, Qi P, Dai H (2004) Ab initio study of CNT NO2 gas sensor. Chem Phys Lett 387:271–276 19. Ma S, Su L, Jin L, Su J, Jin Y (2019) A first-principles insight into Pd-doped MoSe2monolayer: A toxic gas scavenger. Phys Lett A 383:1–9 20. Mishra N, Pandey BP (2020) Detection of N2 O gas using 2D MoSe2 Monolayer: A DFT theory. In: 2020 International Conference on Electrical and Electronics Engineering (ICE3), Gorakhpur, India, 306–310 21. Mishra N, Pandey BP, Kumar S (2021) Impact of N2 O gas adsorption upon electronic properties of 2D MoSe2 monolayer: A DFT approach. IEEE Sens J 21:9756–9762 22. Mishra N, Pandey BP, Kumar B, Kumar S (2021) Enhanced electronic and magnetic properties of N2 0 gas adsorbed Mn-Doped MoSe2 monolayer. IEEE Trans Elec Dev, 1–8 23. Mishra N, Pandey BP, Kumar B, Kumar S (2021) Phase transition impact on electronic and optical properties of Fe-doped MoSe2 monolayer via N2 O adsorption. Superlat Micro 160:107083

Growth of Vertical TiO2 -Nanowire Photoanode for Application of Dye-Sensitized Solar Cell Biraj Shougaijam and Salam Surjit Singh

Abstract In this article, we propose to develop dye-sensitized solar cells (DSSCs) based on vertically aligned TiO2 -nanowire (NW) and Ag nanoparticle (NP) assisted vertically aligned TiO2 -NW (TAT) photoanode fabricated by the glancing angle deposition (GLAD) technique on FTO substrates. The scanning electron microscope (SEM) analysis reveals that the Ag-NP assisted vertically aligned TiO2 -NW photoanode was deposited on FTO substrates. The average length and diameter of the NW have been measured to be ~ 350 nm and ~ 90–100 nm, respectively. And, the X-ray diffraction (XRD) investigation reveals the presence of small crystals of TiO2 and Ag from the weak peaks. Further, the absorption spectrum analysis shows that the incorporation of Ag-NP in TiO2 -NW increases the intensity of absorption in the visible region. The calculated bandgap of the annealed Ag-NP (30 nm)-assisted TiO2 -NW (TAT@30 nm) sample using photoluminescence (PL) analysis is ~3.12 eV. Finally, the performance of two types of DSSC devices based on TiO2 -NW and TAT@30 nm photoanode was analyzed. It is observed that the TiO2 -NW-based DSSC device shows better performance in terms of photo-conversion efficiency compared to the TAT@30 nm photoanode-based device. Keywords DSSCs · GLAD · FTO · Nanowire · Nanoparticle · TiO2

1 Introduction The importance of creating a sustainable energy conversion device to overcome the issue of increasing energy demand is increasing day by day. It is understood that fossil fuel is one of the primary energy sources that is going to be exhausted one day, which will impact the environment and surrounding ecosystem. So, researchers are continuously improving the renewable energy sources, i.e., wind energy from the air, solar energy from sunlight and hydro energy from the ocean. Among these energy B. Shougaijam (B) · S. S. Singh Department of Electronics and Communication Engineering, Manipur Technical University, Takyelpat, Manipur 795004, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_14

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sources, solar cells play a major role in producing electrical energy as a huge amount of sunlight reaches the earth’s surface. To capture or convert maximum energy from sunlight, lots of design and development have been done on photovoltaic technology (PT), which is based on silicon, perovskite, graphene, III-V nitrites and DSSCs solar cells [1–3]. Among these, DSSCs became attractive after O’Regan and Gratzel’s reported the outstanding properties of DSSCs like the multicolor option, easy integration into building architecture, ease of fabrication, low cost and affordable source of renewable energy [4]. This solar cell working is similar to the photosynthesis cycle of the plant leaves, where the DSSCs work on the principle of photoelectrochemical (PEC) reaction in which the dye molecule behaves as a molecular electron pump by trapping the visible light, generating excited electrons and transferring them into the conduction band of a wide bandgap semiconductor, i.e., TiO2 nanostructured. This excited electron in the TiO2 nanostructure is then pumped to the counter electrode and electron recombination takes place in the liquid electrolyte medium of the DSSCs. During the process of energy generation, the oxidized dye molecule is subsequently recombined back to the ground state lower after accepting an electron from the surrounding redox electrolyte of the sensitized TiO2 nanostructure. The DSSCs consist of four different modules: photoanode, dye, electrolyte and counter electrode. Among these, the photoanode plays a big role in the photon conversion process and the dye sensitizer impacts the performance of the DSSCs. TiO2 has a high bandgap, resistance to photo corrosion and nontoxicity compared to other metal oxides like ZnO2 , SnO2 , Cu2 O, WO3 and In2 O3 [5, 6]. Naturally, TiO2 crystal can be in three forms, i.e., anatase, rutile and brookite, which belong to the transition metal oxide [6–8]. Due to superior charge transport and stability, anatase TiO2 is mostly used in making photoanodes for DSSCs. The morphology and size of the TiO2 nanoparticle have a huge impact on the power conversion efficiency (PEC) of the DSSCs. TiO2 has a bandgap of ~3.2 eV and does not promote chemical reactions in the absence of light, hence, it is a chemically inert substance. As a part of the research in nanoscience and technology, the material is becoming smaller down to the nanometer range by changing the morphological structure. Hence, the chemical and physical properties of the nanomaterial change as the nanomaterial’s size decrease [9]. So, there has been recent progress in the synthesis of TiO2 nanomaterial like nanorods (NRs), nanowires (NWs) and nanotubes (NTs), which possess different properties because of the different synthesis techniques, unique microstructure and high surface-to-volume ratio that enhance the delocalized carrier charge particle, thereby increasing the charge transportation. This 1D nanostructure can be used in designing photoanodes for the DSSCs application, which can enhance the efficiency through rapid electron transport capability. Moreover, the synthesis of nanomaterial can be done in different ways, like the sol–gel method, the hydrothermal method, chemical vapor deposition (CVD) and PVD techniques, etc. [10, 11]. Furthermore, TiO2 -NW enhanced the performance of the energy sensing because of more reaction sites due to the high surface area and larger extension of the depletion region. In addition to that, TiO2 -NW has confined conductive channels which can reduce charge recombination, hence enhancing charge transportation as compared to other bulk structures. Yang et al. reported that porous TiO2 TF was deposited by the GLAD

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using e-beam deposition. Also, it was reported that TiO2 film has the largest internal surface area, which enhances the dye absorption of the DSSCs [12]. Again, Wong et al. reported that TiO2 photoanodes were prepared using an e-beam. It is also observed that the efficiency of 6.1% was achieved at an inclined GLAD angle of 73º which improves the light trapping nature of the TiO2 photoanode as it is a columnar structure [13]. The highest reported PCE of DSSCs is ~13.5%, which is fabricated using the chemical process on screen-printed TiO2 film. [14]. Even though the efficiency of the DSSCs is much lower than that of Si solar cells, they have a remarkable performance under low light intensity, which can be used in indoor lighting. So, in this work, the GLAD method was used to grow vertically aligned TiO2 -NW as photoanodes on FTO for DSSC application without using any catalyst. Further, an attempt has been made to harness the surface plasmon resonance (SPR) effect of Ag-NP and vertically aligned NW to improve the efficiency of DSSCs. Therefore, an effort is made to develop DSSC based on TiO2 -NW and Ag-NP embedded vertical TiO2 -NW photoanode deposited by the GLAD method on FTO substrates for the DSSC application. The samples were analyzed using SEM and XRD (RigaKu Ultima IV, Cu Ka radiation, k = 0.1540) analysis for morphology and structural analysis, respectively. Finally, the performance of two types of DSSCs, i.e., TiO2 -NW and Ag-NPs-assisted TiO2 -NW photoanode-based devices is analyzed.

2 Experimental Details 2.1 Materials TiO2 and Ag (both 99.999% pure) were procured from Tecnisco Advanced Materials Pte Ltd, Singapore. N719 ruthenium dye sensitizer (95% pure) was purchased from SRL Pvt. Ltd., FTO/glass (12–14 Ω/cm2 ) from MTI Corporation, USA, and Iodolyte HI-30 electrolyte was purchased from Solaronix, Switzerland. For the deposition of the TiO2 and Ag, the material is loaded into the crucible and put into the evaporation chamber. Before creating the vacuum, the chamber was polished properly by applying acetone. Further, the vacuum is created inside the chamber and the samples are inclined at 81° during the NW and NP deposition.

2.2 Photoanode Preparation FTO glass substrate ~12–14 Ω/cm2 was properly cleaned sequentially by rinsing it into the deionized water (DI) water (Oxford Lab Fine Chem LLP (CAS No. 773218-5)) for 1 min each and drying it in the open air for 5 min before putting inside the chamber. The vertically oriented TiO2 -NW and Ag-NP-assisted vertically aligned

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TiO2 -NW (TAT) are deposited on FTO-coated glass substrates by the GLAD using ebeam evaporator (Model No. Smart Coat 3.0, HHV India). This GLAD mechanism, which is installed inside the chamber, allows the change of the angle by moving the axis of it. In our previous work, the details of the fabrication process of TiO2 NW and TAT samples were discussed [18]. Here, the process is explained in brief. The samples are kept at an inclined angle of 81° and rotated at 30 rpm to form a vertically aligned TiO2 nanostructure. In the first round of deposition, TiO2 -NW (350 nm) samples were deposited on an FTO-coated glass (1 cm × 1 cm) substrate by employing the GLAD method. For another group of samples, TiO2 -NW (175 nm) was initially deposited on glass (1 cm × 1 cm). Further, Ag-NP (30 nm) was deposition above the TiO2 -NW (175 nm). Again, TiO2 -NW (175 nm) was deposited above the Ag-NP (30 nm)/TiO2 -NW (175 nm). Finally, we achieved the staking of TiO2 -NW (175 nm)/Ag-NP (30 nm)/TiO2 -NW (175 nm) (TAT@30 nm) samples by employing GLAD method. For every TiO2 (30 nm) deposition, deposition was done for 12 min at the rate of ~0.6 Å/sec. And, the Ag (30 nm) deposition rate was kept constant at 0.8/sec for 7 min. Similarly, vertically aligned TiO2 -NW with Ag 60 nm (TAT@60 nm) and Ag 90 nm (TAT@90 nm) samples are prepared using the same process and parameters. All these processes are performed under high-vacuum conditions of ~2 × 10–5 mbar. The pressure of the chamber was maintained at ~6 × 10–6 mbar before the start of deposition. However, during the deposition, the pressure drops to ~2 × 10–5 mbar. Further, the photoanode samples for DSSCs fabrication are annealed at 500 °C for 3 h. And, the samples were cooled down slowly and processed for dye loading.

2.3 Dye Preparation and Counter Electrode Preparation 6 mg of N719 (95%, SRL Pvt. Ltd.) dye salt powder is mixed with a 0.5 mM concentration of ethanol using a vortex (Ependorf MixMate) at 200 rpm for 20 min to make 10 ml of N719 dye solution. The resulting dye solution is kept for 1 day for stabilization, as shown in Fig. 1 (inset). The absorption peak of the N719 sample is measured using a UV–Vis spectrophotometer (AN-UV-6500 N ANTech), which reveals four bands at ~ 504 nm, ~ 376 nm and ~ 308 nm, having a shoulder peak at ~ 252 nm. The two peaks in the visible band are attributed to metal-to-ligand charge transfer (MLCT), which is shown in Fig. 1 [15]. The TiO2 -NW and TAT-coated FTO glass samples are immersed in the N719 dye for 24 h, which is kept at room temperature in a dark room. To remove the excess dye, the TiO2 photoanode sample is washed gently with ethanol after taking it out of the dye solution and dried for 3 min in the open air. Again, plastisol T/SP paste from the solaronix was coated on FTO substrate using the doctor blade technique for making the counter electrode (CE). Here, the 3 M scotch tape covers all four edges of the sample by keeping a 2 × 2 cm space at the center of the FTO glass. This sample is placed in the furnace for annealing at 450 ºC for 1 h, which will activate the Pt particles.

Growth of Vertical TiO2 -Nanowire Photoanode … Fig. 1 Shows optical absorption spectrum of the N719 dye sample

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2.4 Fabrication of DSSCs The dye-sensitized TiO2 photoanode and Pt-coated counter electrode were preheated at 100 °C before being sandwiched together. In addition, we applied three drops of iodine (I-/I3-) electrolyte to the TiO2 -coated FTO glass as a charge transfer agent. Lastly, the Pt-coated counter electrode is sandwiched and sealed with the TiO2 photoanode by using a paper clip to complete the DSSCs module and further proceed to the characterization.

3 Results and Discussion 3.1 Sample Structural Analysis The morphology of the as-deposited TAT@30 nm sample was analyzed using a SEM instrument. The spongy nature observed from the image of the SEM as shown in Fig. 2a inset is due to the shadowing effect during deposition [16]. It is also observed that NW cluster formation from the images due to the larger diameter NW that are formed. As seen in Fig. 2a inset, the average diameter of the TiO2 -NW is ~90–100 nm. Figure 2b shows the cross-sectional image of TAT@30 nm. This image proves that vertical TAT@30 nm is successfully growth onto the FTO substrate by employing the GLAD technique. These vertical nanostructures enhanced the efficiency of the DSSC solar cell by enhancing the surface area of the active layer as compared to thin-film [17]. It is fascinating to observe that the TAT@30 nm was successfully fabricated on the FTO substrate, as observed in Fig. 2b. And, the measured average length of (TAT@30 nm) is ~350 nm ± 5 nm.

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Fig. 2 a SEM image of the as-deposited TAT@30 nm and the inset represents the magnified image showing the porous nature of the sample and b a cross-sectional image of the TAT@30 nm sample

3.1.1

XRD Analysis

The as-deposited TiO2 -NW and Ag-NP (30 nm, 60 nm and 90 nm) assisted vertically aligned TiO2 -NW samples are analyzed by X-ray diffraction (XRD). Figure 3a shows the XRD results of the as-deposited TiO2 -NW, TAT@30 nm, TAT@60 nm and TAT@90 nm samples. The weak peaks observed at 2θ = 25.76°, 37.58°, 48.4° and 63.4° are attributed to TiO2 crystals with the corresponding orientation of (101), (103), (200) and (204), respectively, (JCPDS No. 75-1753). The weak peaks may be corresponding to the small grain size of TiO2 crystal grains. Again, the peaks at 38.27°, 34.72° and 77.33° are related to the (111), (220) and (310) planes of Ag crystals (JCPDS No. 04-0783). It is observed that the annealing of TiO2 -NW improves the crystalline of TiO2 , which is evident from Fig. 3b. Kiema et al. reported that

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deposition of obliquely deposited titanium oxide layers for DSSCs using reactive ebeam evaporation, which attributes the same weak peak. Further, as-deposited TiO2 film was annealed for 3 h at 500 ˚C to produce crystalline TiO2 [18].

3.2 UV–Vis Spectroscopy and Photoluminescence Spectroscopy The optical properties of TiO2 -NW and TAT specimen fabricated on an FTO substrate were analyzed under the wavelength range of 340 nm to 800 nm using UV–Vis spectrophotometer. The recorded absorption intensity of deposit samples is shown in Fig. 4a. The absorption spectrum of TiO2 -NW shows a higher absorption peak in the ultraviolet range. This peak may be attributed to electron excitation from the outermost valence band (VB) to the conduction band (CB) of the TiO2 [19]. Moreover, the absorption spectrum of the TiO2 -NW is significantly enhanced in the visible region after the incorporation of different NP sizes, i.e., 30 nm, 60 nm and 90 nm. This significant improvement at around 400 to 600 nm in the absorption spectrum may be due to the SPR effect of Ag-NP [20]. Further, room temperature photoluminescence (PL) analysis of the Ag-NP-assisted TiO2 -NW sample was done using an excitation wavelength of 340 nm by putting a 370 nm filter. The broad PL intensity of the as-deposited and annealed TAT@30 nm samples is plotted in Fig. 4b. A broad emission peak at ~397 nm was observed from as-deposited and annealed TAT@30 nm samples. It was also observed that the PL intensity of the annealed TAT@30 nm specimen increased compared to the as-deposited sample, which may be due to the increase in the crystalline of the TiO2 by reducing the oxygen vacancies. as-deposited TiO2-NW

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3.3 Device Characterization The electrical performance of the fabricated DSSCs is characterized at room temperature by using a source meter (Keithley 2450) connected to the computer and the photocurrent measurement was taken under light illumination irradiance at 100 mW/cm2 powered by a solar simulator (SS150, Scientech, Canada). Figure 5 shows the dye absorbed photoanode, counter electrode and DSSC device. Figure 6 shows the I-V graph of DSSCs based on TiO2 -NW and TAT@30 nm photoanodes. And, Table 1 shows the cell performance of DSSCs devices and the corresponding photovoltaic parameters. The PCE of the TiO2 -NW is 0.61% and the corresponding opencircuit voltage (V oc ) and short-circuit current density (J sc ) of the cell are ~0.51 V and ~3.21 mA/cm2 . The efficiency of the DSSCs is reduced to ~0.24 percent after the incorporation of Ag nanoparticles, with the corresponding V oc and J sc being ~0.34 V and ~2.11 mA/cm2 , respectively. So, there is a difference between the J sc that depends on the light conversion activity and the structure of the photoanode, which determines the electron diffusion PCE of the solar cell. It is observed that TiO2 -NW photoanode-based DSSC device shows better efficiency compared to TAT@30 nm photoanode-based device. The reduction in performance of DSSC after the incorporation of Ag-NP may be due to the size of Ag-NP embedded on TiO2 -NW, where the Ag-NP acts as an

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Fig. 5 a Fabricated counter electrode, b dye absorbed photoanode and c DSSC device based on TiO2 -NW photoanode 0.0 TiO2-NW based device

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Fig. 6 I-V graphs of DSSCs based on TiO2 -NW and TAT@30 nm photoanode

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Table 1 Photovoltaic performance of TiO2 -NW and TAT@30 nm photoanode-based DSSCs Photoanode

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I m (mA)

FF

ï%

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3.21

0.32

1.94

0.37

0.61

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0.34

2.11

0.21

1.13

0.34

0.24

electron sink, or may be because to the Schottky junction creation between Ag-NP and TiO2 , which thereby acts as a blocking layer to the transport of electrons toward the electrode. However, the TiO2 -NW-based device improves the accessibility of the entire surface to the dye and corresponding electrolyte medium, leading to a direct and shorter path for the transportation of the electrons. Marquesa et al. reported that an efficiency of ~1.2% from the DSSC fabricated using the tape casting method. It was also observed that the highest efficiency was achieved by using 4-tert-butyl pyridine electrolytes [21]. Again, Erande et al. reported a PCE of 0.2% in which the TiO2 film was deposited using chemical method [22]. It was that the natural dye, which was acting as a sensitizer of DSSCs, was less efficient. Even though the efficiency of our DSSC device based on TiO2 -NW is higher than the DSSCs using natural dye. The efficiency of our device is still low, which may be due to the thinnest of photoanode. So, the efficiency may be further improved by increasing the TiO2 -NW photoanode thickness.

4 Conclusion In conclusion, the GLAD method was used to develop TiO2 -NW and Ag-NP-assisted TiO2 -NW photoanodes on an FTO substrate for the development of DSSCs. The SEM analysis reveals the successful deposition of nanowires. The XRD investigation reveals the presence of Ag-NP and TiO2 crystals in the nanowires. The absorption enhancement from the Ag-NP-assisted TiO2 -NW samples observed in the absorption spectrum may be due to the SPR effect of Ag-NP present in the TiO2 -NW. The TiO2 NW-based DSSC device shows better efficiency compared to the Ag-NP-assisted TiO2 -NW photoanode-based DSSC device. It may be concluded that the size of the Ag-NP incorporation at the mid-point of the TiO2 -NW needs to be reduced. Therefore, this simple and low-cost fabrication technique may be employed for developing DSSCs and other optoelectronic device applications. Acknowledgements The authors acknowledge the Department of Science and Technology (DST), Science and Engineering Research Board (SERB), Govt. of India, for funding this work under File No. ECR/2018/000834. Also, the authors would like to thank NIT, Durgapur and NIT Nagaland for FE-SEM and XRD analysis, respectively.

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Multiband Photodetection Using TiO2 Thin Film Deposited on Si Substrate Using E-beam Evaporation Technique Salam Surjit Singh and Biraj Shougaijam

Abstract In this paper, a simple E-beam evaporation process was used to manufacture TiO2 thin film (TF) on a Si substrate for multiband photodetection. The existence of tiny crystal grains of anatase and rutile TiO2 is shown by XRD examination of the As-deposited TiO2 -TF sample. The absorbance of annealed TiO2 -TF is increased in the UV region and extends into the visible range with maxima at ~400 nm and ~570 nm. The bandgap of annealed TiO2 -TF derived from the Tauc plot is ~3.2 eV, which is similar to the bandgap of annealed TiO2 -TF extracted from the Gaussianfitted PL spectra. Finally, the TiO2 -TF/Si-based photodetector device operated at − 3 V under low-intensity green light has an excellent responsivity value of ~0.496 A/W, which is quite intriguing. Furthermore, the photodetector devices developed had a rise and fall times of ~0.154 and ~0.123 s, respectively. As a result, this low-cost E-beam evaporation approach might be used to make visible light detectors based on TiO2 -TF for optoelectronic applications. Keywords E-beam evaporation · Photodetector · Responsivity · TiO2 · Thin film

1 Introduction Light detection is one of the most important processes in optoelectronic applications. Information extraction from the optical light signal is converted using a photodetector, which will give out the corresponding electrical signal [1]. Photodetectors play a big role in converting the different wavelengths of light into their equivalent electrical information. The ability to detect different wavelengths of light is, however, dependent on the bandgap of the photodetector material. The photodetector can be of different types, such as PN [2], Metal–semiconductor-metal (MSM) [3] and metal– oxide–semiconductor (MOS) [4]. Besides, the metal oxide semiconductor is mostly used for designing photodetectors as there is the presence of electronic bandgaps in S. S. Singh · B. Shougaijam (B) Department of Electronics and Communication Engineering, Manipur Technical University, Takyelpat, Manipur 795004, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_15

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the metal oxide material, which can excite it easily as different energies of photons fall on it. In addition to that, structured modification of the PN junction can yield photodetector performance which can be applied in a wide range of applications [5]. The photodetector can also be used in applications such as fibre-optic communication, medical products, radar, night vision and heat sensing to detect diverse wavelengths of light from UV to long-wave IR wavelengths [6, 7]. Researchers have put a lot of work into developing multiband photodetectors using quantum dots, inorganic nanomembranes and organic perovskite. But, the developed photodetector systems are still constrained by their less response time and restricted range [8–10]. Furthermore, there are numerous challenges to developing a good response photodetector as the communication system requires minimal transmission loss. Due to the high demand for optoelectronic devices for optical communication purposes, many researchers are trying to develop low-cost optical detectors using different semiconductor materials or by changing the structural properties of the material. The metal oxide layer can tune the response range from UV to IR by changing the material properties and structural modification. Metal oxide like SiO2 [11], CeO2 [12], WO3 [13] and GaO3 [14] is used for designing photodetectors that work in different applications. However, TiO2 is a good candidate due to its high photocatalysis efficiency, non-toxicity, good chemical and thermal stability. TiO2 crystals generally occur in the rutile, anatase and brookite phases. Out of those, anatase TiO2 is the most stable one. TiO2 has an optical bandgap of ~3.2 eV [15]. Moreover, it is very important to get a uniform thin film structure with a highly porous structure, which will impact the performance of the device. However, the thin film’s characteristics are highly influenced by the deposition process used, which has an impact on the thin film’s properties. TiO2 thin film can be prepared using radio-frequency (RF) magnetron sputtering [16], hydrothermal [17], pulsed laser deposition (PLD) [18], chemical vapour deposition [19], atomic layer deposition [20], etc. Another low cost and simple fabrication technique that can be employed to fabricate TiO2 thin film (TF) is electron beam (E-beam) evaporation. This fabrication technique is also more advantageous as compared to other fabrication processes due to its catalytic-free process [21]. Nowadays, many researchers have reported producing UV photodetectors using TiO2 nanostructure as TiO2 is a wide bandgap semiconductors, hence its high absorbance in the UV region. Again, TiO2 is a prominent candidate for other optoelectronics applications like dye-sensitized solar cells [22], water splitting [23], gas sensors [24], etc. Wang et al. reported that the UV photodetector is designed using a double-layer TiO2 nanostructure [25]. Zhang et al. further reported that the heterojunction UV photodetector made of TiO2 /NiO, which improves photodetector response [26]. Again, Ji et al. revealed that RF magnetron sputtering was used to deposit TiO2 multi-layer thin film for manufacturing high-efficiency UV photodetector [27]. But, there are just a few examples of TiO2 -based photodetectors that can detect several bands of light. The E-beam deposited TiO2 -TF has very rich oxygen defects [28]. These defects can be utilized for detecting various wavelength ranges from UV to near IR [29]. So, in this work, E-beam evaporation will be employed to deposit TiO2 -TF on Si to develop a low-cost multiband photodetector utilizing the defects present in the thin film.

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In this paper, E-beam evaporation system is used to deposit TiO2 -TF on a ptype silicon substrate. X-ray diffraction (XRD) is used to determine the structural characteristics. A UV–Vis spectrophotometer and photoluminescence (PL) are also used to evaluate the optical characteristics. A source measuring unit (Keithley 2400) is used to examine the I-V characteristics under low-intensity lighting.

2 Experimental Details The TiO2 -TF is synthesized on p-type Si substrates using an E-beam evaporator (Smart Coat 3.0, HHV India). The Si substrate is bathed in acetone, methanol and deionized (DI) water for 2 min before deposition. After drying out the Si substrate for 5 min at room temperature, the Si substrate is mounted on a substrate holder and placed into the E-beam chamber. The Si-mounted substrate is kept at a 21 cm distance from the evaporation source, and then, the vacuum chamber is evacuated at a pressure of ~7 × 10–6 mbar. First, the TiO2 -TF of thickness ~200 nm is deposited on the Si substrate using source material as TiO2 (99.999% purity, Tecnisco Advanced Materials Pte Ltd., Singapore). The release of oxygen gas from the source material when it is heated lowers the vacuum pressure during the growth phase. The chamber pressure is maintained at ~2 × 10–5 mbar during the deposition. All the deposition processes are monitored using the digital thickness meter (DTM), which is mounted inside the E-beam chamber. The deposition rate is controlled at 1.1 Å/sec using DTM, and the thickness of the TiO2 can be easily monitored. Furthermore, before contact deposition, the deposited samples are annealed at 500 °C for 1 h to enhance device performance. Finally, a circular Au-TF of a thickness ~30 nm is evaporated onto the samples by masking them with the aluminium sheet that will act as the top electrode. The area of the circular Au-TF is ~7.84 × 10–3 cm2 . X-ray diffraction (XRD) (X-Pert Pro Pan analytical) operated at 30 mA and 40 kV is also used to analyse the materials. The absorption spectrum and photoluminescence (PL) spectrum of the samples were also characterized using optical spectrophotometer (AN-UV-6500 N, ANTech) and a fluorescence spectrophotometer (F-7000, HITACHI).

3 Results and Discussion 3.1 XRD Analysis The As-deposited TiO2-TF sample was analysed by employing XRD. The diffracted pattern of the As-deposited TiO2 -TF is shown in Fig. 1. The diffraction result shows weak peaks from the anatase TiO2 crystal at 2θ = 25.76°, 37.58°, 48.4° and 55.7° corresponding to crystal lattices of 101, 004, 200 and 211, respectively (JCPDS No. 75–1753). Also, the sample gives rutile TiO2 crystal peaks at 2θ = 41.09°

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Fig. 1 XRD result of As-deposited TiO2 -TF

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and 69.19° related to (111) and (310) crystal planes, respectively (JCPDS No. 211276). Therefore, the XRD analysis reveals that the TiO2 -TF deposited by E-beam evaporation techniques forms mixed phases of polycrystalline. Similarly, Hossain et al. reported that the TiO2 deposited by E-beam evaporation gives a mixed phase of TiO2 crystals [30].

3.2 Optical Properties Analysis The optical measurement was done using UV–Vis spectrophotometer under the wavelength of ~340 nm to ~700 nm, as shown in Fig. 2a. When compared to the visible range, the As-deposited TiO2 -TF exhibits superior absorption in the UV. The annealed TiO2 -TF, on the other hand, exhibits slide absorption in the UV and visible regions about ~400 nm and ~550 nm wavelengths. Because of its large bandgap, TiO2 is usually active in the UV. However, this sample exhibits noticeable absorbance amplification, which might be attributable to oxygen defects in the TiO2 bandgap energy [28]. As shown in Fig. 2b, the bandgap was derived from the Tauc plot by extrapolating the linear section of the spectrum. It reveals that the annealed TiO2 -TF deposited by E-beam evaporation has a bandgap of ~3.2 eV. This bandgap result is quite similar to the bandgap obtained by other researchers deposited by the same method and other deposition techniques [31, 32]. Furthermore, as shown in Fig. 2b, the Tauc plot indicates a mid-bandgap of ~ 2.52 eV, which might be connected to oxygen defects. These defects may be utilized for visible light detection. The annealed sample’s photoluminescence (PL) spectrum was also examined using a HITACHI fluorescence spectrophotometer (F-7000) with an excitation of 340 nm wavelength using a filter of 370 nm. According to the PL spectrum analysis, the peak is observed at ~399 nm (~3.1 eV), as illustrated in Fig. 3a. This PL peak corresponds to the near bandgap of annealed TiO2 -TF. Similar PL peaks are also reported in the literature for TiO2 -TFs [33, 34]. Further, the PL spectrum was fitted

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with a Gaussian curve to study the defects present in the annealed TiO2 -TF sample. In this case, the main bandgap extracted from the fitting curve was found to be ~3.17 eV (~391 nm), which is very near to the bandgap extracted from the Tacu plot. This peak is also slightly larger than the near band gap observed at ~3.1 eV (~399 nm). In addition, as shown in Fig. 3b, the fitting curve of the PL spectra confirms the existence of defects at ~429 nm and ~496 nm. The defect produced from the fitting curve at ~496 nm (~2.5 eV) supports the Tauc plot result, indicating the presence of a mid-bandgap at ~2.52 eV.

3.3 Photodetector Device Analysis An attempt has been made to realize a visible light photodetector based on TiO2 -TF deposited on Si using a simple E-beam evaporation technique. The I-V measurement of the TiO2 -TF/Si device was measured using the Keithley 2400 source measurement unit in dark conditions and under the exposure of various light sources like blue (~450 nm) and green (~550 nm) lights. A power metre (OPHIR PD300-1W, USA)

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was used to measure the optical power intensity of blue and green light at 3 cm from the LED. The measured power intensities of green and blue are ~1.19 μW/cm2 and ~1.18 μW/cm2 , respectively. It is observed that the fabricated photodetector device gives an interesting rectifying behaviour under dark and different colours of light source, as shown in Fig. 4, which is due to the junction (PN) formation between the TiO2 -TF and Si substrate. This device shows maximum light detection under green light (~550 nm) exposure. Further, the responsivity (R) of different wavelengths of light is calculated using the formula given in Eq. (1). R=

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where I ph denotes the photocurrent produced and Pin denotes the incident light power. The device’s predicted responsivity for blue (~450 nm) and green (~550 nm) lights, using Eq. 1, is ~0.19 A/W and ~ 0.50 A/W, respectively. As a consequence, the manufactured photodetector device may be employed as a green light photodetector, according to this finding. As demonstrated in Fig. 5a, the photodetector’s speed was also tested for green light (~550 nm). Under green light illumination, the measured

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rise and fall periods of the photodetector are ~0.145 s and ~0.123 s, respectively, as shown in Fig. 5b. In comparison with the photodetector documented in the literature, this device has a faster response time [35, 36]. Therefore, this device can be employed in vehicles for the detection of traffic lights, especially green light, for self-driving cars and other optoelectronic applications.

4 Conclusion In conclusion, we have successfully fabricated TiO2 -TF on a Si substrate using a simple E-beam evaporation system. The XRD analysis of the As-deposited TiO2 -TF sample reveals the polycrystalline nature of TiO2 -TF with mixed phases of anatase and rutile TiO2 . The annealed TiO2 -TF gives a bandgap of ~3.2 eV from the modified absorption spectrum, which supports the bandgap obtained from the PL analysis. Also, the PL analysis reveals the presence of defect levels above the midpoint of the bandgap. Finally, the device characterization reveals the PN junction formation between the TiO2 -TF and Si substrate. The measured dark current is 9.61 nA, and the photocurrent under blue and green lights are ~0.229 μA and ~0.590 μA, respectively, for the fabricated TiO2 -TF/ Si device biased at −3 V. Under blue (~450 nm) and green (~550 nm) light, the photodetector device has good responsivity of ~0.194 A/W and ~0.496 A/W, respectively. Furthermore, in both on and off situations, the TiO2 -TFbased photodetector device has a quick switching response time. Therefore, this fabricated device based on TiO2 -TF by E-beam evaporation may be utilized as a multiband photodetector for many other electronic applications.

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Acknowledgements The authors would like to express their gratitude to the Department of Science and Technology (DST), Science and Engineering Research Board (SERB), Government of India, for funding under File No. ECR/2018/000834. The authors further thank the Department of Chemistry at NIT Manipur for providing PL and XRD facilities.

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Evolution of Tunnel Field-Effect Transistor and Scope in Low Power Applications: A Detailed Review Ramesh Potharaju and Bijit Choudhuri

Abstract The emerging novel device tunnel field-effect transistor (TFET) has fascinated the scientific community with its distinct features such as lower subthreshold slope (SS), small leakage currents and minimized short channel effects. Hence, TFET was found to be an appropriate device for low power and high-frequency applications. The prime objective of this manuscript is to elaborate on recent significant contributions made by the researchers to surpass its limitations such as ambipolar behavior, low ION /IOFF ratio and to improve subthreshold swing (SS). The influence of temperature (200–400 K) and ferroelectric material on the device performance was also reviewed in detail. Keywords MOSFET · Subthreshold swing (SS) · TFET · Ambipolar conduction · BTBT · DIBL · Short channel effects (SCEs)

Acronyms and Abbreviations MOSFET TFET CMOS BTBT CNT TAT DIBL

Metal oxide semiconductor field-effect transistor Tunnel field-effect transistor Complementary metal–oxide–semiconductor Band-to-band tunneling Carbon nanotube Trap assisted tunneling Drain induced barrier lowering

R. Potharaju (B) · B. Choudhuri Department of Electronics and Communication Engineering, National Institute of Technology, Silchar,, Assam 788010, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_16

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1 Introduction Nowadays, power dissipation has become a serious constraint in low power VLSI applications. For decades, the most popular device, MOSFET has undergone massive geometrical changes to overcome its limitations raised by the scaling trends and initiated exploration of novel device architectures such as junction-less transistors (JLT), carbon nanotube FET (CNTFET), FinFET and tunnel FET (TFET). TFET is like a PIN diode with an extra control terminal called the gate. Its construction is indistinguishable from the traditional MOSFET except that the doping profiles in source region and drain regions are opposite. Figure 1 portrays its cross-sectional view of basic construction. TFET’s current conduction is due to the band-to-band (BTBT) quantum tunneling mechanism which is distinguishable from the conventional MOSFET, where current conduction is because of thermionic emission of charge particles. Hence, TFET exhibits high thermal stability. Immunity against short channel effects made the TFET a more popular promising device for low power applications. Its distinct attractive features are lower OFF state current and steeper transfer characteristics with subthreshold swing lower than 60mv/decade [1, 2] which is not limited by the Boltzmann limitation. Shortcomings of the TFET are lower ON current and ambipolar behavior. The first one is caused by BTBT phenomena and the second one is due to negatively biased channel-drain junction that results in lower ION /IOFF ratio, which is undesirable for digital applications. Under certain biasing conditions, OFF current across the channel-drain junction increases exponentially. This exponential increase occurs due to the BTBT mechanism across the junction. This is known as the ambipolar characteristic of TEFT, which is unenviable for realizing complementary digital circuits [3]. In this article, various recent device geometries are reviewed, and a comparative analysis is made. This paper is organized into five parts. The second part describes the different device models, and operating principles and highlights their main achievements and drawbacks. A comparison of different models is made in the third section. The fourth part concludes this article. (a)

(b)

Fig. 1 a Structure of conventional TFET b variation in band diagram under ON/OFF conditions

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2 Latest Tunnel FET Architectures (1)

Junction-less Dual Gate Tunnel FET with SiGe Pocket (2021)

This novel device architecture was launched by S. Bhattacharya et al. ON current in the device was magnified by using high dielectric constant material (HfO2 with K = 25) and a material with larger work function potential (5.7 eV) for the Gate contact [4]. Further higher value of I ON /I OFF ratio is achieved by reducing the tunneling paths with the provision of narrow bandgap material Si0.7 Ge0.3 /P+ pocket near the source end [2]. Cross-sectional view and improved transfer characteristics of the proposed model can be understood from the [5]. A double-gate structure achieves better control over the drain current. The device exhibits an appreciable ON/OFF current ratio (1011 ), a steeper subthreshold slope (63.5 mV/dec) and a lower value of DIBL (22.2 mV/V) [4]. The performance assessment of this device is made under varying temperatures (200–400 K). The visual TCAD (Cogenda) device simulator was used for the design and simulation, taking a gate length of 18 nm. The device simulation was also made by taking various gate contact/oxide combinations, several pocket materials, different gate lengths and by varying the proportion of Ge in SiGe. The authors suggested that their work can be extended by combining n-type and p-type junction-less double-gate TFETs to fabricate complementary doublegate TFET which are in tune with CMOS devices. From transfer characteristics, it is concluded that the SiGe pocket in combination with Pt/Hf O2 exhibits excellent transfer characteristics. (2)

Carbon nanotube-based tunnel FET using underlap arrangement (2021)

K. Tamersit et al. modified the geometry of carbon nanotube-based tunnel FET with all around gate to enhance its performance by introducing the underlap structure [6]. Design and simulation work was done using non-equilibrium greens’s function (NEGF). Scaling flexibility and the broad operating regime made the CNTFETs the best alternative to the conventional Silicon MOSFETs [7]. Authors investigated that the introduction of underlap arrangement has a great influence on the device performance in terms of reduction in leakage current and improvement in ON current, taking a gate length of 5 nm. Eventually, current ratio and subthreshold swing were greatly improved. Due to its semiconductor properties, authors incorporated zigzag carbon nanotube with (n,0) crystal arrangement to their novel device. Figures portray the device structures before and after the improvement [6]. From the device structures, we can observe that they are identical except that gate underlap structure was introduced in latter one. N-type ohmic contacts were used for source and drain [8]. It was identified that band-to-band tunneling causes ON state current in the device whereas direct tunneling process between source and drain causes leakage state current [9]. ID versus V GS characteristics of this latest architecture before and after the modification are given in [6]. It is examined that with the expense of ON current, BTBT swing factor and leakage currents were significantly improved with the adoption of

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underlap device geometry. Finally, authors suggested that further investigation in terms of experimental and computational approaches are required under sub 5 nm technology node for high frequency and low power applications. (3)

Pocket doping L-shaped tunnel FET (TFET) (2021)

In this novel architecture, H. W. Kim et al. introduced a highly doped p-type pocket for n-channel device underneath the gate [10] to an already existing L-shaped TFET and analyzed by TCAD simulators. This concept originated from a traditional Lshaped TFET, where a larger tunneling area was achieved by extending the source region [11]. Structure of L-shaped TFET before and after modification is provided in [11]. The main objective of this model is to eliminate the unwanted tunneling at the corner of the source due to accumulated higher the electric field. This is achieved by reducing the band bending between the pocket doping region (RPOC ) and source. This would be an outstanding achievement to improve the switching characteristics of TFET, i.e., the ON/OFF current ratio is significantly enhanced [10]. Further average SS (subthreshold swing) of 26mv/decade is achieved, and ON current gets doubled compared to the existing L-shaped TFETs. The impact of pocket doping under the gate on TFET transfer characteristics before and after modification is given in [10]. Moreover, I ON and SS are greatly improved with doping concentration at pocket doping under the gate region. Investigation revealed that corner tunneling occurs at the source side due to increased electric field when V GS = 0.4 V and conventional tunneling when V GS crosses 0.4 V. Such phenomena result in poor switching characteristics of the device. The authors have varied different dimensions of the device, and comparative analysis has been provided. One among them is the channel thickness (T CH ), and its effect on transfer characteristics were given in [10] where ON current is appreciably improved. Further, it is also observed that the height of the source region improves the ON current without affecting the SS. It is also noted that for larger values of V GS and higher pocket doping concentration, the corner tunneling becomes dominant and short channel effects are significantly less in the latest architecture. Likewise, several improvements have been made, such as steeper switching characteristics. Authors have also claimed that the implementation of the proposed device is simple. And they have optimized the doping concentration of pocket NPOC to be 2.5 × 1019 cm−3 and obtained ION of 0.3 uA/um and SS of 26 mV/decade. Finally, proposed L-shaped TFET design process flow is given but authors did not highlight any shortcomings and future scope. (4)

Vertical tunneling-based DM-DG-Tunnel FET (2021)

A new device architecture of vertical tunneling-based dual material double-gate tunnel field-effect transistor (VTDMDG-TFET) was introduced by K. S. Singh et al. The authors have combined the two existing approaches (double-gate dual material) to combine their individual merits. The geometrical representation of the latest device architecture was given in [12]. It consists of two metal gates namely tunnel gate to control ON current and auxiliary gate to control leakage current. The entire

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analysis, simulation and optimization were done using a technology computer aided design tool (TCAD). This structure is proved to be efficient for improving the ON current, I ON /I OFF ratio, better transconductance and subthreshold swing (SS) [12]. Higher ON current was obtained by sing HfO2 as a gate dielectric material. Tunneling in other directions is greatly restricted by depositing the SiO2 in required regions. Transfer characteristics represent an excellent curve by choosing the optimum device dimensions of t Si = 10 nm, works functions of auxiliary gate and its length are 4 eV and 30 nm, respectively, whereas work function of tunnel gate and its length are 4.4 eV, 20 nm, respectively [12]. Further, an average subthreshold slope of 32.8 mV/decade, a current ratio of 2.67 × 1013 and transconductance (gm ) of 23.03 × 10−4 A/V were obtained at the optimum device structure. (5)

Single-Gate L-shaped TFET (2021)

Here, authors have proposed a new model, and a comparison has been made with double-gate TFET. The novel architecture single-gate L-shaped TFET is given in [13]. Due to the L-shaped structure, the tunneling area and perpendicular tunneling probability are significantly increased by giving large ON state current [13]. The drive of current of 6 × 10−4 A/μm was achieved with an enhanced BTBT at the interface of the source and the channel [13]. Ambipolar conduction is suppressed by using different bandgap materials at the drain and source ends. Having smaller energy gap SiGe compound used at the source side can reduce the tunneling barrier between source and channel. Hetero-dielectric material HfO2 -SiO2 is used for gate dielectric to have greater control on current. The conventional double-gate TFET exhibits ambipolar behavior but suppressed in the L-shaped TFET [13]. The authors have optimized the device dimensions and made a lot of analysis using different materials for gate, source and gate. Optimum lengths for source and drain were found to be 37 nm. Along with that parasitic capacitance of Cgd = 0.66 fF and Cgs = 0.52 Ff, the ON state current of 8.63 × 10−4 amp/μm and OFF state current of 3.51 × 10−18 amp/μm, threshold voltage of 0.82 V and subthreshold swing of 10.4 mV/decade were calculated for the given model [13]. Silvaco atlas TCAD tool was used for simulation. (6)

Dielectric modulated TFET (2020)

S. Bhattacherjee et al. introduced an innovative approach. In this model they split the dielectric material of top gate into two portions such that the source side dielectric was varied while drain side dielectric was kept constant. The impact of such asymmetric dielectric was studied by considering several device dimensions, and optimization was done. The structure of asymmetric dielectric TFET is given in [14]. Initially, dielectric-1 values were chosen in between 3.9 and 28 but optimized to 5–20 by keeping the current ratio and intrinsic delay in mind. The simulation was carried out by using ATLAS [14]. ON state band diagram represents enhanced tunneling process due to thinner energy barrier.

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It was observed that choosing SiO2 in region2 and HfO2 in region1 provided better performance among various dielectric materials selected for the region1. Clear illustration was provided [14] describing the influence of modulated dielectric material on current ratio. The critical point here is when the same HfO2 is used in both regions; a high value of ON current was obtained with the expense of leakage current, but the same limitation was eliminated by choosing HfO2 in region1 and SiO2 in region2 that resulted in a fantastic improvement in the current ratio. (7)

Tunneling FET with Drain Underlap (2020)

In this model, the existing double-gate p-type intrinsic n-type tunnel FET was modified, and an advanced architecture was introduced to address the ambipolar behavior of the device [15]. It consists of one extra layer (pocket) between the source and the channel. Tunneling probability was enhanced by achieving greater electric field association between the gate terminal and the channel. Alignment of gate with the metallurgical junction at source terminal and pocket facilitates the better field coupling. By the adoption of drain underlap structure, the ambipolar current is suppressed significantly. Further, we can notice that the device characteristics under ON state condition were independent of gate-drain underlap structure, but a significant influence is observed on OFF state current. This is because of a constant electric field across the interface of the source and the channel and negligible/partial drop across underlap region [15]. The authors have changed the spacer materials with high-k dielectrics and noticed an increase in ambipolar current. Further, it is identified that drain current saturates earlier in underlap drain device than a non-underlap device. Optimum spacer length of 8 nm has resulted in the best device performance [15]. Design and two-dimensional simulations were done using ATLAS Silvaco [16]. (8)

Graphene Nanowire TFET (2020)

S. Chauhan et al. came up with a new approach to achieve an extremely small subthreshold swing [17]. The graphene-based gate all around (GAA) TFET comprised of narrower energy gap material at the source end and a material with larger energy gap at the drain end. Due to distinct properties of graphene [18], such as excellent electrical conductivity, excellent electron mobility, higher mechanical and thermal stability, authors have chosen that. Despite having those attractive qualities, graphene also has some limitations in terms of the doping process, ambipolar behavior. But those limitations can be eliminated by adopting several advanced approaches such as using large bandgap materials for drain and hetero-dielectric gate. Amazing properties of graphene are excellent carrier mobility, exorbitant current conductivity (13 times more than the copper), very hard and very good heat conductivity [19–21]. Such distinct characteristics attracted the researchers to make use of its advantages in designing high-speed electronic chips. TFET with minimum SS is highly important for high-frequency applications [22]. In this graphene nanowire device, SS of 3mv/decade was obtained [17]. But it was observed that ION /IOFF current ratio is less (107 ) when compared to silicon nanowire

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TFET (1012 ). Due to their very high conductivity, graphene can support larger ON currents and does not require high-k gate materials to have better control on the channel. Santauras TCAD device simulator was used for the design and analysis. Authors suggest that further investigation on the properties of graphene is to be done to surpass its shortcomings. TFETS with graphene nanowires found their applications in sensors, solar panels and high-speed electronic circuits. (9)

CNT-based tunnel FET with electrostatic doping (2019)

CNT-based and electrostatically doped DGTEFT is a new TFET model [23] presented by Amandeep Singh et al. Due to the unique characteristics of CNT (carbon nanotube), it is used as a channel, and dynamic configuration of source and drain was done using polarity gates by electrostatic doping. Device structure of traditional CNTFET, ED CNTFET and their respective transfer characteristics can be observed in [23]. The mobility degradation problem is not present in carbon nanotubes [24]. An alternate approach of electrostatic doping was adopted to dope the CNT for which conventional doping techniques are not applicable [25], reducing fabrication cost and complexity. p+ and n+ regions are created using two polarity gates, namely PG-1 and PG-2 at source and drain side, respectively. Polarity gate potentials of −0.75 V and + 0.75 V were used to form source and drain regions. SS was found to be 24.8 mV/dec, which was near to the value of conventional CNTFET (25.1 mV/dec). Spacers (spaces between polarity gate terminals and main gate terminals at the source and drain sides) add additional resistance to resistance offered by channel and barrier width. Hence, ON current is lower than the conventional CNTFET. The presented device was designed and simulated using NanoTCAD ViDES [26] that is a quantum tunneling simulation tool based on (NEGF) non-equilibrium green function. Diameter of nanotube and potential applied across polarity gates significantly influenced the device performance [23]. Symmetric doping is also achieved by choosing appropriate bias voltages. Moreover, by reversing the polarities of bias voltages, we can realize p-type device as well. (10)

Tunnel FET with Step-gate (2019)

Tunnel field-effect transistor having a gate in step form is a new device architecture designed by M. Liu et al. in order to extinguish the ambipolar behavior of the tunnel FET. The architecture of this device was given in [27]. It has an oxide layer with two different thicknesses extended to overlap some portion of drain. The energy gap across the interface of channel and drain junction raises at V gs 1012

–

[37]

15 JL I-TFET

50

50

4.38 × 10−6

–

–

–

[38]

16 FE DM GAA FET

45

–

1.45 × 10−6

0.279 × −18 52.1 × 1011

12.4

[41]

17 ADG-TFET

20/40 –

3.02 × 10–4

9.14 × 10–15

35–54

[42]

1

JL DG-TFET

2

18

3.3 × 1010

18 TFET with DP

100

–

36 μA /um –

–

62

[39]

19 GNR-based TFET

–

85

–

4.96 × 104

2.76

[21]

20 SiGe Source-based HJ TFET

50

–

2.8 × 10−4 –

7.53 × 1013

14.41

[43]

0.0092 (pA),

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4 Conclusion An exhaustive study was carried out to analyze various advanced tunnel FET architectures. The top twenty-four device architectures and their transfer characteristics have been scrutinized along with their key findings. Comparative analysis was made in terms of ION , ION /IOFF current ratio, ambipolar current and subthreshold swing (SS). Influence of ferroelectric materials and temperature (200–400 K) on performance of the device was presented in detail. Having amazing properties, graphene nanowire TFET could be the best charming research topic for upcoming generations. This article could be the best reference for young researchers to get familiarized with the advanced architectures of TFET. Acknowledgements The authors would like to thank NIT Silchar, India, for providing financial support.

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Design and Analysis of Non-uniform Body with Dual Material FET-Based Digital Inverter Jagritee Talukdar

and Kavicharan Mummaneni

Abstract The paper reports design and analysis of the non-uniform body with dual material TFET-based digital inverter. The analysis includes the transient characteristics of the inverter in appearance and non-appearance of interface trap charges. Gaussian distribution of interface trap charge with various concentrations has been taken into account. Further, different delay parameters of the circuit have been calculated, and it is observed that fall time delay of the circuit is less than that of rise time delay. Finally, it is found that the propagation delays of the proposed TFET-based digital inverter are 9.75 ps and 6 ps in occurrence and non-occurrence of interface trap charges, respectively. Keywords TFET · Digital inverter · Trap charges · Transient characteristics

1 Introduction Lately, researchers discovered novel devices to preserve the Moore’s law which are capable of maintaining better performance as well as lower cost at the same time [1]. Complementary metal oxide semiconductor (CMOS) devices are one of the best solutions up to the feature size of micrometre range. But when technology entered the nanometre range, various short channel effects of MOSFET-based devices made it intolerable in commercial applications [2]. Therefore, many novel devices have been discovered by a lot of researchers, and one of the discoveries that seems promising for future technology roadmap is tunnel field effect transistors (TFET), without any fabrication complexity [3]. In TFET, carrier conduction depends on the tunnelling of electrons from valance band to conduction band of source and channel, respectively [4]. Because of this unique feature of TFET, it is highly in contradiction of short channel effects, and also the main grandeur is the subthreshold swing of TFET which is scalable up to 10 mV/decade [5]. But the only disadvantage linked with TFET devices are its low ON current, which can be improved by developing various J. Talukdar (B) · K. Mummaneni Department of Electronics and Communication Engineering, NIT Silchar, Silchar, Assam, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_17

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structural and material modifications into it [6]. Hence, to enhance the ON current, researchers discovered many novel geometries of TFET which can withstand as the most reliable device for commercial use. The most prominent amongst them are double gate TFET structures [7], TFET with group III–V-semiconductor as channel material [8], silicon on insulator-based TFET [9], L-shaped gate TFET [10], GAATFET [11], TFET with high-K dielectric material [12], non-uniform channel TFET [13], carbon-based TFETs [14], hetero-junction TFET [15], dual gate TFET [16], etc. Out of these TFET structures, it has been observed that the use of high-k dielectric material at oxide layer improved the ON current of the TFET devices without any further modification in the conventional TFET structure. However, the problem with high-k dielectric is along with ON current, it also increases OFF and ambipolar current in the device. Hence, [13] come up with hetero dielectric TFET structure which uses two different dielectrics to increase ON current as well as maintaining OFF current at the same time. In addition, it was reported that inclusion of two different gate materials can lead to lesser miller capacitance [17, 18]. The miller capacitance is the primary parameter to decide the applicability of the structure in circuit applications. In this work, a digital inverter has been developed using the existing non-uniform body with dual material-based TFET, and its performance has been analyzed for occurrence and non-occurrence of trap charges at the interface. The occurrence of interface trap charges degrades the tunnelling field of the device thus its performance deteriorates. Hence, by using the NUTFET-DMS structure, an improved TFET-based digital inverter has been reported, and analysis has been carried out considering reliability issues. The structure of the article is as follows: Sect. 2 and Sect. 3 confer the device structure and simulation methodologies, respectively. Next, Sect. 4 considers the results and finally presents the conclusion in Sect. 5.

2 Device Structure The schematic of Fig. 1 represents the non-uniform TFET with dual material source TFET. The body of the structure is made non-uniformed to modulate the effective mass of the carriers. It has been reported that adjacent to the source the body thickness is kept high which helps to lower effective mass, and reverse is true in the drain side of Fig. 1 wer3D schematic view of non-uniform TFET with dual material source

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the structure. Thus, the asymmetric arrangement of the body facilitates enhanced ON current in the device along with lower OFF and ambipolar current at the same time. Further, it is well known that in TFET with increase in gate to source voltage increases SS; therefore, in this structure, the dual material in the source side is incorporated which helps to reduce the average SS [13].

3 Simulation Methodologies The schematic of Fig. 1 has been simulated using Sentaurus TCAD simulator [19]. The details of simulation parameters have been provided in Table 1. The structure has channel, source, and drain length of 40 nm, 30 nm, and 30 nm, respectively. High-doping concentration has been used in the source, and the drain of the structure hence, Fermi–Dirac Statistics Transport has been used in the simulation. In addition, doping-dependent mobility model and Shockley–Read–Hall (SRH) model are activated for mobility and recombination of carriers. The non-local band-to-band tunnelling models (BTBT) and band gap narrowing model are activated as current conduction mechanism in TFET is band-to-band tunnelling. The models of the simulated structure have been calibrated accordingly by tuning the tunnelling masses. Figure 2 presents the calibrated graph of NUTFET-DMS with experimental results of [20, 21]. For the consideration of interface trap charges, Gaussian distribution has been enabled. Table 1 Device simulation parameters for NUTFET-DMS

Parameters

Values

Si bandgap

1.11 eV

Ge bandgap

0.67 eV

Source doping

1 × 1020 cm−3

Drain doping

1 × 1018 cm−3

Channel doping

1 × 1015 cm−3

Dielectric constant of HfO2

22

Dielectric constant of SiO2

3.5

Work function of aluminium

4.2 eV

Channel thickness

15 nm

Reduced channel thickness,

7 nm

Dielectric thickness of HfO2

0.7 nm

Dielectric thickness of SiO2

1 nm

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Fig. 2 Schematic of NUTFET-based digital inverter

4 Results and Discussion The schematic of TFET-based complementary logic circuit has been shown in Fig. 2 with load capacitance of 2 fF. The NUTFET-DMS device is used for construction of the digital inverter (Fig. 2), and its performance is investigated in presence and absence of interface trap charges. A positive gate bias on an n-type NUTTFET-DMS results into accumulation of n-channel in the interface. An adequate gate voltage will enable flow of charge carriers from valance band to the conduction band of the source and channel, respectively. Similarly, p-channel NUTTFET-DMS gets turn ON when application of gate bias with opposite polarity leads to accumulation of holes Fig. 3 Transient characteristics of non-uniform TFET with dual material source-based digital inverter for occurrence and non-occurrence of interface trap charges

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in the channel surface. Figure 3 represents the transient characteristics of NUTFETDMS-based digital inverter. From the figure, it can be observed that when there are no interface trap charges a perfect inverter characteristic can be obtained from the reported TFET structure. Further, the transient characteristics of the NUTFETDMS-based digital inverter have been observed in presence of Gaussian distribution of interface trap charges by varying the concentration from 1 × 1013 /cm2 to 10 × 1013 /cm2 . It can be observed that when trap charges appear in the interface, and the concentration increases gradually undershot appears in the output characteristics of the inverter. This is due to the fact that with occurrence of interface trap charges, the value of C gd in the device increases due to deduction of channel to drain potential. In presence of 10 × 1013 /cm2 of interface trap charges, an increase in undershot of 14% can be noticed in the inverter. The improved output characteristics are because of the use of low-k dielectric with higher thickness near the drain side of the device with an underlap of 1 nm. In literature, it is reported that TFET-based inverter encounters large overshoot and undershoot because of its exceptional current conduction process as compared to conventional MOSFET [7]. The existence of the band-to-band tunnelling effects the gate-drain capacitance (C gd ) of the device in such a way that it dominates the total gate capacitance (C gg = C gd + C gs ) [22]. However, from the Fig. 4, it can be perceived that the reported NUTFET-DMS delivers a quite low value of C gd . As the use of low-k dielectric adjacent to the drain side of the structure along with a higher thickness in the same side [13]. From the study, it can be perceived that the non-uniform TFET-based digital inverter performs well because of the presence of higher body thickness near the tunnelling junction which decreases the effective mass of the carrier leading to higher mobility than that of the other reported structures. The rise time, fall time, and propagation delay for the structures are 7 ps, 5 ps, and 6 ps (10.2 ps, 9.3 ps, 9.75 ps), respectively, for absence (presence) of interface trap charge. It can be perceived that the fall time is lesser than that of the rise time in TFET-based digital inverters. Moreover, the presence of interface trap charges has an adverse effect over the delay parameters due to degraded I on /I off ratio [23]. Finally, it can be portrayed that the Fig. 4 Influence of interface trap charges on NUTFET-DMS capacitance

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NUTFET-DMS-based digital inverter possesses less delay, making it more suitable for inverter-based designs such as operational transconductance amplifier (OTA), power transfer module, also for suitable use in biomedical and healthcare circuits and systems, etc.

5 Conclusion The work presents the transient characteristics of proposed non-uniform body with dual material TFET (NUTFET-DMS)-based complementary digital inverter. The inverter is made up of n-type and p-type of NUTFET-DMS act as pull down and pull up device, respectively. The NUTFET-DMS includes non-uniform body with dual material source by accounting occurrence and non-occurrence of Gaussian distribution of trap charges at the device interface. The occurrence of interface trap charges of concentration 1 × 1014 /cm2 can lead to 14% undershoot in the characteristics. Further, various timing parameters such as rise time, fall time, and preparation delay are calculated and found to be 7 ps, 5 ps, 6 ps and 10.2 ps, 9.3 ps, 9.75 ps for occurrence and non-occurrence of interface trap charges, respectively.

References 1. Moore GE (2006) Cramming more components onto integrated circuits. IEEE Solid-State Circuits Soc Newslett 11(3):33–35 2. Chaudhry A, Kumar MJ (2004) Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: a review. IEEE Trans Device Mater Reliab 4(1):99–109 3. Turkane S, Kureshi AK (2016) Review of tunnel field effect transistor (TFET). Int J Appl Eng Res 11(7):4922–4929 4. Lu H, Seabaugh A (2014) Tunnel field-effect transistors: state-of-the-art. IEEE J Electron Dev Soc 2(4):44–49 5. Cao W, Yao CJ, Jiao GF, Huang D, Yu HY, Li M (2011) Improvement in reliability of tunneling field-effect transistor With p-n-i-n structure. IEEE Trans Electron Devi 58(7):2122–2126 6. Dubey PK (2019) Tunnel FET: devices and circuits, nanoelectronics, devices, circuits and systems. Adv Nanomat, 3–25 7. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-k gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733 8. Mehta JU, Borders WA, Liu H, Pandey R, Datta S, Lunardi L (2016) III–V tunnel FET model with closed-form analytical solution. IEEE Trans Electron Dev 63(5):2163–2168 9. Mitra SK, Goswami R, Bhowmick B (2016) A hetero-dielectric stack gate SOI-TFET with back gate and its application as a digital inverter. Superlattices Microstruct 92:37–51 10. Goswami PP, Bhowmick B (2019) Optimization of electrical parameters of pocket doped SOI TFET with L shaped gate. SILICON. https://doi.org/10.1007/s12633-019-00169-7 11. Madan J, Chaujar R (2017) Gate drain underlapped-PNIN-GAA-TFET for comprehensively upgraded analog/RF performance. Superlattices Microstruct 102:17–26 12. Ilatikhameneh H, Ameen TA, Klimeck G, Appenzeller J, Rahman R (2015) Dielectric engineered tunnel field-effect transistor. IEEE Electron Device Lett 36(10):1097–1100 13. Talukdar J, Mummaneni K (2020) A non-uniform silicon TFET design with dual-material source and compressed drain.https://doi.org/10.1007/s00339-019-3266-5

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14. Gao Y, Low T, Lundstrom M (2009) Possibilities for VDD = 0.1V logic using carbon-based tunneling field effect transistors. In: Symposium on VLSI Technology, pp 180–181 15. Avci UE, Young IA (2013) Heterojunction TFET scaling and resonant-TFET for steep subthreshold slope at sub-9nm gate-length. In: 2013 IEEE International Electron Devices Meeting, 4.3.1–4.3.4. https://doi.org/10.1109/IEDM.2013.6724559 16. Talukdar J, Rawat G, Singh K et al (2020) Comparative analysis of the effects of trap charges on single- and double-gate extended-source tunnel FET with δp+ SiGe pocket layer. J Elec Materi 49:4333–4342 17. Yang Y, Tong X, Yang L, Guo P, Fan L, Yeo Y (2010) Tunneling field-effect transistor: Capacitance components and modeling. IEEE Electron Device Lett 31(7):752–754 18. Talukdar J, Rawat G, Singh K et al (2021) Low frequency noise analysis of single gate extended source tunnel FET. SILICON 13:3971–3980 19. TCAD Sentaurus Device User’s Manual (2010) Synopsys, Inc., Mountain View, CA, USA 20. Biswas A, Dan SS, Royer CL, Grabinski W, Ionescu WAM (2012) TCAD simulation of SOI TFETs and calibration of non-local bandto-band tunneling model. Microelectron Engineering 98:334–337 21. Goswami R, Bhowmick B, Baishya S (2016) Effect of scaling on noise in circular gate TFET and its application as a digital inverter 53:16 24 22. Jiang Y, Sato S, Omura Y, Mallik A (2016) Aspects and reduction of miller capacitance of lateral tunnel FETs. In: 2018 IEEE International Meeting for Future of Electron Devices, Kansai (IMFEDK), 1–2 23. Wangkheirakpam VD, Bhowmick B, Pukhrambam PD (2020) Investigation of N+ pocketdoped junctionless vertical TFET and its digital inverter application in the presence of true noises. Appl Phys A 126:798

Performance Analysis of Metal– Ferroelectric–Insulator–Semiconductor Negative Capacitance FET for Various Channel Materials Malvika, Bijit Choudhuri, and Kavicharan Mummaneni

Abstract With the advancement in integrated circuit (IC) miniaturization, limiting the power usage has become a significant issue for both academia and industrial researchers. Negative capacitance field-effect transistors (NCFETs) have recently grabbed a lot of attention compared to several established ultralow-power devices with sub-threshold swing (SS) less than 60 mV/decade. In every device, the channel plays a crucial role in the transport mechanisms of the device, thus impacting its performance and operational attributes. In this work, we analyze the effects of different channel materials such as gallium nitride (GaN), gallium arsenide (GaAs), and silicon (Si) on the transfer characteristics of single-gate NCFET in the presence of spacer. In addition, the effects of these materials on the trans-conductance are also studied. The simulation results reveal that the GaAs-based channel provides a better ON–OFF current (I ON -I OFF ) ratio and trans-conductance, but SS performance degrades badly. Furthermore, it has been observed that the Si-based channel offers improved SS in comparison with the other two materials. Several key performance metrics of the device such as ON-current, OFF-current, and SS are investigated, and the comparison of various parameters of the device based on different channel materials is summarized. Keywords NCFET · Ferroelectric · ON–OFF current ratio · Sub-threshold swing

1 Introduction Internet-of-Things (IoT) paradigms like smart-wireless sensor networks (WSNs), real-time wearable computing, and mobile edge computing (MEC) up-scale the necessities of ultralow-power integration systems [1]. The advancements in the sensor networks demand for continuous growth in the downscaling of device size due to its size, weight, and power (SWAP) constraints. At transistor level, reducing supply voltage is the ultimate approach to scale-down the device power consumption. Malvika (B) · B. Choudhuri · K. Mummaneni Department of Electronics and Communication Engineering, NIT Silchar, Silchar, Assam, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_18

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However, as supply voltage (V dd ) is reduced, it consequently reduces the transistor’s drive current as well. When the drive current is lowered, the delay of circuit increases, and OFF-state leakage current continues to flow throughout this duration, which is undesirable from the low-power design aspect. For digital technology and WSNs applications, it is desirable for the system to be functional and possesses low latency in accomplishing its tasks and then uphold in rest mode for the remaining time. Thus, switching energy is an essential parameter for low-power devices in specific scenarios for long durability and non-interruptible operations. So, to obtain effective switching energy, I ON –I OFF switching ratio must be large at certain V dd [2]. The sub-threshold slope (SS) is desired to be low for this pertaining requirement of high switching; SS is usually denoted as; (

∂ψs SS = ∂ VG   (a)

)−1 (

∂log10 I D ∂ψs   (b)

)−1 (1) 

where Ψ s is surface potential, I D is drain current, and V G is the gate voltage. The term (a) of Eq. 1 indicates the electrostatics of metal-oxide-semiconductor (MOS) capacitor which indicates how effectively gate voltage can tilt the silicon band. Further, the term (b) of Eq. 1 defines the conductance which describes the amount of induced current by the bending of band. In the traditional metal–oxide–semiconductor fieldeffect transistor (MOSFET), the term (a) does not surpass one because of the voltage divider that is present between the silicon channel and the gate dielectric. Due to the reason that the diffusion transport dominates the transport in sub-threshold region, whose distribution is given by the Boltzmann distribution, the term (b) is equal to approximately 2.3kT/q. As a result, minimum constraint possessed by SS is 60 mV/decade. To circumvent the 60 mV/decade bottleneck, researchers have investigated various steep-slope transistors including impact ionization MOSFET (IMOS) [3, 4], tunneling FET (TFET) [5, 6], and nano-electromechanical switches (NEM) [7] in which term (b) has been improved. On the other hand, IMOS, TFET, and NEM have their own drawbacks such as; for IMOS devices, the hot-carrier degradation of oxides occurs in the presence of high lateral electric field, high breakdown voltage, and less drive current are major challenges. Whereas, TFET possesses complicated fabrication process, and reliability issue persists for the NEMFET. The negative capacitance field-effect transistor (NCFET) proposed by Salahuddin et al. [8] is a promising and novel technology which is still in its early stage. NCFETs are capable to overcome the Boltzmann limit and remarkably acquire a sub-60 mV/decade steep SS by engineering the term (a) in Eq. 1. The design of an NCFET is similar to the MOSFET, except the incorporation of ferroelectric (FE) thin film in the gate stack. This addition of FE layer has nonlinear properties which provides negative capacitance (NC) paving the way for this revolutionary technology [9]. Equation 2 depicts the relations between capacitance and voltage;

Performance Analysis of Metal–Ferroelectric-Insulator–Semiconductor …

(

∂ VG ∂ψs

) =1+

CS Cfe

169

(2)

where C S is the capacitance of semiconductor and C fe is the capacitance of the ferro( ) ∂ VG electric layer. The C fe of the NCFET must be negative which makes ∂ψs less than1, and thus, SS less than 60 mV/decade can be obtained. NCFETs use the same transport mechanisms as traditional MOSFETs, allowing them to drive larger currents than TFETs due to the increased channel charge density provided by boosted surface potential at iso-OFF-current. As a result, NCFETs have sparked interest because of their potential to reduce the SS of 60 mV/decade constraints and outperform the traditional MOSFETs in terms of drive current. Furthermore, NCFET is a symmetric device in terms of drain and source that becomes advantageous in the advancement and commercialization of novel device technology. However, the NCFET is a potential choice for a steep-slope device although it suffers from the process integration problems. The usage of traditional ferroelectric materials including barium titanate (BTO), lead zirconate titanate (PZT), and strontium bismuth tantalite (SBT) [10, 11] causes problems at nano-meter scale in stabilizing the MOSFET channel charge density and large polarization charge density because of their incompatibility with the current CMOS technology. Recently, ferro-electricity has been observed in thin hafnium oxide (HfO2 ) film which has the potential to overcome the above limitations [12–17]. The fabrication technique will become compatible with CMOS technology when HfO2 -based ferroelectric is used for NCFET at thin-film morphology [18]. To encourage technology development and research of NCFETs with doped HfO2 -based ferroelectric for IoT applications, it should be verified that NCFETs can be structured with hafnium oxidedoped ferroelectric as well as the earlier described ferroelectric material at ultralow supply voltage. In our work, we have considered the single-gate NCFET with spacer, wherein the silicon-doped ferroelectric material is used. The effect of different channel materials in the process of designing device for an energy efficient NCFET with a Si: HfO2 ferroelectric and spacer for ultralow power applications is being proposed. Furthermore, to validate the design of the device and ferroelectric parameters, various HfO2 -based FE data are thoroughly researched and referred. Our major contribution of this work is to carry out the analysis for studying the behavior of device attributes and performance under various channel materials. Section 2 provides the descriptive device structure of the NCFET followed by the comprehensive discussions of the simulation method. Section 3 presents the results and its analysis, whereas the conclusion is discussed in Sect. 4 based on the obtained research results.

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2 Device Structure and Simulation The structure of single-gate NCFET (SGNCFET) with spacer is depicted in Fig. 1. To study the electrical characteristics of the NCFET, metal–ferroelectric–insulator– semiconductor (MFIS) design is taken into consideration. In the proposed structure, the thickness of oxide is taken as 0.6 nm, and the ferroelectric thickness is 7 nm. The thickness of gate metal and source/drain is 5 nm and 15 nm, respectively. The source and drain are n+ doped, whereas substrate is p-type silicon semiconductor. The doping concentration of source, drain, and substrate is 1 × 1018 /cm3 , 1 × 1018 /cm3 , and 1 × 1020 /cm3 , respectively. In the structure, silicon-doped ferroelectric material is utilized, and the parameters of the ferroelectric material are obtained from the relationship between polarization and electric field. The attributes of the proposed structure are explored using different materials in the channel region such as gallium nitride, silicon, and gallium arsenide. The choice of these three materials is done by comprehensively studying their adaptability in various research works. The impact of these channel materials on different parameters such as ON-current, OFF-current, SS, threshold voltage, ON–OFF ratio, and trans-conductance is rigorously investigated. The simulation of the SGNCFET is carried out in Sentaurus TCAD software [19], and the results are discussed in Sect. 3. For the simulation of underlying MOSFET, dynamic non-local band-to-band model, drift–diffusion model, Fermi– Dirac statistics, and Shockley–Reed–Hall recombination are taken in consideration. The 2-dimension (2D) electrostatics and 1D static Landau–Khalatnikov (LK) equations are leveraged to deduce the gate voltage amplification and drain current-gate voltage (I D -V G ) characteristics [20–22]. The various parameters of ferroelectric are calculated from the LK Eq. (3).

Fig. 1 Schematic structure of SGNCFET

Performance Analysis of Metal–Ferroelectric-Insulator–Semiconductor …

√ √ −3 3 E C 3 3 EC α= , andβ = · · 2 4Pr 2 8Pr3

171

(3)

where E C and Pr are coercive field and remnant polarization which is taken between the range of the experimental data of hafnium-based FE materials [23, 24].

3 Results and Discussion In this section, the ID -VG characteristics, ON-current, OFF-current, threshold voltage, SS, and trans-conductance of SGNCFET are illustrated for different channel materials. Figure 2 represents the I D -V G curve of the device. When GaAs is incorporated in the channel, it degrades SS of the device drastically, whereas ON–OFF ratio is enhanced. Further, it can be observed from the curve that silicon channel material improves SS and provides better ON-current and OFF-current as compared to GaN [25]. It can be noticed from Fig. 3 that ON-current and switching ratio of GaAs channel material are better than the other two materials. Additionally, GaAs provides higher trans-conductance depicted in Fig. 4. However, SS and threshold voltage is lesser for silicon channel material compared to both GaAs and GaN material. The change in the threshold voltage of the device by using GaAs, GaN, and Si as the channel material is demonstrated in Fig. 5. The decreasing trend in the threshold voltage can easily be observed when materials are selected from GaAs to Si [26]. The comparison of several parameters of the device based on various channel materials is summarized in Table 1. Fig. 2 I D -V G characteristics of SGNCFET for different channel materials

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Fig. 3 ON-current, OFF-current, and current ratio of the SGNCFET for different channel materials

Fig. 4 SS, trans-conductance, and threshold voltage of the SGNCFET for different channel materials 0.5 THRESHOLD VOLTAGE

Threshold Voltage (V)

Fig. 5 Plot of threshold voltage with the variation in channel materials

0.4 0.3 0.2 0.1

GaAs

GaN Channel Material

Si

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173

Table 1 Comparison of several parameters based on various channel materials Channel I ON (mA/µm) I OFF (A/µm) Threshold SS Transconductance I ON /I OFF materials voltage (mv/decade) (mS/µm) (V) GaAs

3.09

9.40 × 10–13 0.417

66

30

0.32 × 1010

GaN

1.17

3.07 × 10–11 0.394

50.9

12

0.38 × 108

Si

1.35

1.90 × 10–11 0.39

36.2

9.5

0.71 × 108

4 Conclusion The study comprises of the impacts of various channel materials such as GaAs, GaN, and Si on the SGNCFET device with spacer. In this work, variation of channel material has been included for the analysis of the transfer characteristics and transconductance of the SGNCFET device. The comparison of various parameters with different channel materials is investigated, and it is concluded that using GaAs in channel surpasses the Boltzmann limit of 60mv/decade which is not preferable for steep-slope devices. Whereas, GaN has obtained the SS value of 50.9 mv/decade along with ON-current of 1.17 mA/µm which is worse than Si material. Furthermore, the curve of ID -VG in logarithmic scale is plotted which yields that using silicon as channel material in NCFET device results in a much steeper slope of 36.2 mV per decade than any other channel material. Additionally, the ON-current and current ratio of silicon channel material are 1.35 mA/µm and 0.71 × 108 , respectively which is proposed to be a better contender for the device material.

References 1. Aitken R, Chandra V, Myers J, Sandhu B, Shifren L, Yeric G (2014) Device and technology implications of the Internet of Things. In: 2014 Symposium on VLSI Technology (VLSITechnology): Digest of Technical Papers, pp 1–4. https://doi.org/10.1109/VLSIT.2014.689 4339 2. Fuketa H, Yasufuku T, Iida S, Takamiya M, Nomura M, Shinohara H, Sakurai T (2007) Tech Dig Int Electron Devices Meeting, 559–562 3. Choi WY, Song JY, Lee JD, Park YJ, Park B-G (2005) 100-nm n-/p-channel IMOS using a novel self-aligned structure. IEEE Electron Device Lett 26:261–263 4. Ramaswamy S, Kumar MJ (2014) Junction-less impact ionization MOS: proposal and investigation. IEEE Trans Electron Devices 61:4295–4298 5. Han G, Wang Y, Liu Y, Zhang C, Feng Q, Liu M, Zhao S, Cheng B, Zhang J, Hao Y (2016) GeSn quantum well P-channel tunneling FETs fabricated on Si (001) and (111) with improved subthreshold swing. IEEE Electron Device Lett 37:701–704 6. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479:329–337

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7. Kam H, Lee DT, Howe RT, King T-J (2005) A new nano-electro-mechanical field effect transistor (NEMFET) design for low-power electronics. In: IEEE International Electron Device Meeting, Washington, DC. https://doi.org/10.1109/IEDM.2005.1609380 8. Salahuddin S, Datta S (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett 8(2):405–410 9. Khan AI, Chatterjee K, Wang B, Drapcho S, You L, Serrao C, Bakaul SR, Ramesh R, Salahuddin S (2015s) Negative capacitance in a ferroelectric capacitor. Nat Mater 14(2):182–186. https:// doi.org/10.1038/nmat4148 10. Auciello O (1997) A critical comparative review of pzt and sbt-based science and technology for non-volatile ferroelectric memories. Integr Ferroelectr 15(1–4):211–220 11. Das RR, Majumder SB, Katiyar RS (2002) Comparison of the electrical characteristics of pzt and sbt thin films. Integr Ferroelectr 42:323–334 12. Hyuk Park M, Joon Kim H, Jin Kim Y, Lee W, Moon T, Seong Hwang C (2013) Evolution of phases and ferroelectric properties of thin Hf0.5Zr0.5O2 films according to the thickness and annealing temperature. Appl Phys Lett 102(24):242905. https://doi.org/10.1063/1.4811483 13. Park MH, Kim HJ, Kim YJ, Lee W, Moon T, Kim KD, Hwang CS (2014). Study on the degradation mechanism of the ferroelectric properties of thin Hf0.5Zr0.5O2 films on TiN and Ir electrodes. Appl Phys Lett 105(7):072902. https://doi.org/10.1063/1.4893376 14. Starschich S, Griesche D, Schneller T, Waser R, Böttger U (2014) Chemical solution deposition of ferroelectric yttrium-doped hafnium oxide films on platinum electrodes. Appl Phys Lett 104(20):202903. https://doi.org/10.1063/1.4879283 15. Müller J, Böscke TS, Schröder U, Mueller S, Bräuhaus D, Böttger U, Frey L, Mikolajick T (2012) Nano Lett 12(8):4318–4323. https://doi.org/10.1021/nl302049 16. Müller J, Yurchuk E, Schlosser T, Paul J, Hoffmann R, Müller S, Martin D, Slesazeck S, Polakowski P, Sundqvist J, Czernohorsky M, Seidel K, Kücher P, Boschke R, Trentzsh M, Gebauer K, Schröder U, Mikolajick T (2012) Tech Dig Symp (VLSI Technology), pp 25–26 17. Shiraishi T, Katayama K, Yokouchi T, Shimizu T, Oikawa T, Sakata O, Uchida H, Imai Y, Kiguchi T, Konno TJ, Funakubo H (2016) Impact of mechanical stress on ferroelectricity in Hf0.5Zr0.5O2 thin films. Appl Phys Lett 108(26):262904. https://doi.org/10.1063/1.4954942 18. Boscke TS, et al (2011) Ferroelectricity in hafnium oxide: CMOS compatible ferroelectric field effect transistors. In: 2011 International Electron Devices Meeting, 24.5.1–24.5.4 19. TCAD Sentaurus Device User’s Manual (2010) Synopsys, Inc., Mountain View, CA, USA. 20. Landau LD, Khalatnikov IM (1954) Dok Akad Nauk, SSSR 46:469–472 21. Landau LD, Khalatnikov IM (1965) In collected papers. L.D. Landau, Elsevier, pp 626–629 22. Kim KD, Park MH, Kim HJ, Kim YJ, Moon T, Lee YH, Hyun SD, Gwon T, Hwaung CS (2016) J Mater Chem C 4:28 23. Chandra P, Littlewood PB (2007) A Landau primer for ferroelectrics. In: Physics of Ferroelectrics, Springer-Verlag, Berlin, Germany, pp 69–116 24. Lo VC (2003) Simulation of thickness effect in thin ferroelectric films using Landau– Khalatnikov theory. J Appl Phys 93(5):3353–3359 25. Rahman T, Khan AF, Nawal N (2019) 1st Int Conf Adv Sci, Eng Rob Tech (ICASERT), 1–6 26. Bidenko P, Lee S, Han J-H, Song JD, Kim S-H (2018) IEEE J Elec Dev Soc 6:910–921

Impact of Tapered Dielectric on a Gallium Nitride Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) Towards Biosensing Applications Ananya Dastidar

and Tapas Kumar Patra

Abstract This paper presents the sensitivity analysis of an AlGaN/GaN single gate MOSHEMT with a tapered high-κ dielectric with a cavity under the gate for neutral biomolecules. The device performance exhibits an enhanced gm and reduced leakage current by using a tapered dielectric on a single gate MOSHEMT over a conventional dielectric single gate MOSHEMT. Variation in drain current, transconductance, and threshold voltage plays an important role when heterostructures are used for biosensing applications. This has been exploited in studying device sensitivity toward neutral biomolecules by using dielectric modulation. The simulated reference MOSHEMT with a tapered dielectric exhibited a maximum drain current of 1474 mA/mm and a high transconductance of 814.6 mA/mm while the MOSHEMT with a conventional dielectric exhibited a maximum drain current of 651.4 mA/mm and maximum transconductance of 771.6 mS/mm. With neutral biomolecule in the cavity, the maximum variation in drain current, transconductance, and threshold voltage was obtained for glucose oxidase as 310 mA/mm, 0.06 V, and 73.7 mS/mm, respectively. All simulations have been carried out using the 2D simulator Visual Technology Computer-Aided Design tool. Keywords Sensitivity · MOSHEMT · Tapered dielectric · Visual TCAD · Biosensor

1 Introduction Currently, the semiconductor industry is shifting its focus from pure silicon-based devices to semiconduction compounds like GaAs [1], GaN [2], and InP [3]-based devices. GaN-based MOSHEMT is being fabricated for multiple target applications and owing to its superior performance than MOSFETs or HEMTs-based devices and provides a new window for its design, manufacture, and production. Future high-power devices will make the transmission of data across radio channels faster A. Dastidar (B) · T. K. Patra College of Engineering and Technology, Bhubaneswar, Odisha, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_19

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176 Fig. 1 Tapered oxide [23]

A. Dastidar and T. K. Patra

tox1

tox2

and reliable. Furthermore, these devices can be used in imaging radar systems [4] that will help make autonomous systems more accurate, and MOSHEMT as a high resolution-precision biosensor system [5] will supplement the medical diagnosis and aid in the field of biomedical research and development. In MOSHEMTs, the presence of an oxide layer adds the additional advantage of lowering leakage current over HEMTs. Use of high-κ oxides like Al2 O3 [6], HfO2 [7, 8], ZrO2 [9, 10], TiO2 [11], HfSiOx [12], ZnO [13] as gate dielectric and metal [14] as the gate material increases the gate field effect. Further, the use of thicker dielectric layers aids in the reduction of gate leakage [15]. Different structural engineering like modification of the gate [16], varying the dimensions of different layers like— oxide layer [17], barrier layer [18, 19], spacer layer [20], channel engineering [12], threshold voltage engineering [21], have been carried out to improve or study their influence on device performance for different application domains. In this paper, we propose to find the effect of tapered oxide on a single gate MOSHEMT and study its use in biosensing applications. The impact of tapered field oxide on MOSFET has shown a reduction of on resistance and an improved breakdown voltage for use in power integrated circuits [22]. Tapering of the oxide can be carried out by growing an oxide of the thickness (t ox1 ) and another region having an oxide of the thickness (t ox2 ) as shown in Fig. 1. Intermediate to these two regions is the tapered oxide that is obtained by a meticulous etching process to set the angle of the taper [23]. Many papers have implemented various structural engineered HEMT/ MOSHEMT for biosensing applications [24– 28]. Different structural changes like gate structure engineering [29], use of high-κ materials as gate oxide [30, 31], and dielectric modulation [32, 33] have been carried out to study its impact on MOSHEMT device characteristics. Gate oxide with abrupt profiles has been used to study the impact on device performance, but the impact of a tapered dielectric on the device performance has not been presented as per the knowledge of the authors. This paper presents the influence of a tapered dielectric with a cavity under the gate on the MOSHEMT characteristics as well as the applicability of this device for neutral biomolecule detection. The paper is divided into four sections—Sect. 1 gives a background, with Sect. 2 elaborating dimension and simulation setup of the single gate MOSHEMT with tapered dielectric. The results and discussions on sensitivity analysis for neutral biomolecule sensing have been presented in Sect. 3, while conclusions have been drawn in the final section.

Impact of Tapered Dielectric on a Gallium Nitride Metal Oxide Semiconductor …

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Fig. 2 Single-gate MOSHEMT with a tapered dielectric (SGMH-TD)

2 Device Dimensions and Simulation Setup 2.1 Single Gate MOSHEMT with Tapered Oxide Here, we present a single gate MOSHEMT with a tapered dielectric (SGMH-TD) simulated using the 2D Visual TCAD device simulator from Cogenda as shown in Fig. 2. The heterostructure has been simulated with a high-κ dielectric (oxide) to study its impact on device characteristics. The Tapered Oxide Single Gate MOSHEMT has a 20 nm oxide thickness in region 1 (t 1 + t ox ), tapered oxide in region 2 has a thickness (t ox + dt), and 10 nm oxide thickness in region 3 (t ox ). The region with thickness dt corresponds to the tapered oxide whose angle (θ ) can be adjusted by changing the length of the tapered region or thickness of t 1 . Here, we have considered t 1 = tox = 10 nm and θ = 45°. The junctions—source (S), drain (D)—have been implemented with source/ drain doping with a Gaussian profile with doping levels of 1020 /cm3 . The gate (G) is metal (aluminum) with a gate length of 20 nm. The channel has been implemented as a 100 nm undoped (intrinsic) GaN layer and a uniformly doped GaN layer with doping levels of 1017 / cm3 on a silicon substrate. The spacer layer is also an undoped GaN layer over which the gate dielectric is grown. To reduce leakage current, high-κ dielectric HfO2 (κ = 25) has been used as the gate dielectric. The models used in our simulated device were calibrated with a single gate AlGaN/ GaN MOSHEMT [34] as shown in Sect. 3.

2.2 Single Gate MOSHEMT with a Tapered Dielectric and a Cavity Under the Gate To study the applicability of our device in biosensing applications, the heterostructure has been simulated with a cavity under the gate. Reported structures, with a cavity

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Fig. 3 a Single gate MOSHEMT structure with conventional dielectric with a cavity under the gate (SGMH-CUG), b single gate MOSHEMT structure with tapered dielectric and a cavity under the gate (SGMH-TD-CUG)

under the gate [33, 35–37], used SiO2 and/or Al2 O3 as the gate dielectric, but here we study the influence of using a high-κ dielectric HfO2 (κ = 25) in our proposed structure. The two devices under consideration are the single gate MOSHEMT with conventional dielectric with a cavity under the gate (SGMH-CUG) and single gate MOSHEMT with tapered dielectric with a cavity under the gate (SGMH-TD-CUG) as shown in Fig. 3. The CUG is filled with different neutral biomolecules, and the effect of the device characteristics is exploited to calculate the device’s sensitivity toward biosensing applications.

3 Results and Discussions 3.1 Device Calibration The device model was calibrated with the experimental results in [34]. Figure 4 presents a typical output characteristic of the single gate MOSHEMT. The device was simulated for the drain to source voltage (V ds ) from 0 to 15 V with the gate to source voltage (V gs ) of 1 V. The maximum variation in drain current is 3.57% at V ds = 12 V. The device shows reasonable agreement between the experimental [34] and simulated characteristics, which validates our simulation model.

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Fig. 4 Calibration of the simulation model with experimental output characteristic of a single gate MOSHEMT

3.2 Single Gate MOSHEMT with a Tapered Dielectric The single gate MOSHEMT with tapered dielectric and cavity under the gate (SGMH-TD-CUG) has been simulated using the 2D simulator Visual TCAD from Cogenda. The transfer characteristics were obtained for V gs = −1.8 V to 1.8 V for V ds = 0.1 V, 1 V, and 1.8 V as shown in Fig. 5. The maximum drain current obtained was 172.93 mA/mm, 1030 mA/mm, and 1474 mA/mm for V ds = 0.1 V, 1 V, and 1.8 V, respectively. The maximum transconductance of 172.5 mS/mm, 814.6 mS/mm, and 1070 mS/mm was obtained for V ds = 0.1 V, 1 V, and 1.8 V, respectively. The extracted threshold voltage is −0.04 V, −0.26 V, and -0.39 V for V ds = 0.1 V, 1 V, and 1.8 V, respectively. So, we can say that the device can be used for low-power Fig. 5 Transfer characteristics of SGMH-TD-CUG for V ds = 0.1 V, 1 V, and 1.8 V (Inset transconductance of SGMH-TD-CUG for V ds = 0.1 V, 1 V, and 1.8 V)

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Fig. 6 Transfer characteristics of SGMH-TD-CUG and SGMH-CD-CUG for V ds = 1 V. (Inset transconductance of SGMH-TD-CUG and SGMH-CD-CUG for V ds = 1 V)

applications. The I off leakage currents were obtained as 2.58 μA/μm, 42.89 μA/μm, 101.8 μA/μm for V ds = 0.1 V, 1 V, and 1.8 V, respectively. We also have implemented and compared the input characteristics of an SGMHTD-CUG) with a single gate MOSHEMT with conventional dielectric and cavity under the gate (SGMH-CD-UG). The transfer characteristics and transconductance curve has been presented in Fig. 6. The reference SGMH-CD-CUG and SGMH-TDUG have been simulated by considering a cavity filled with air (κ = 1). The single gate MOSHEMT with tapered dielectric and cavity under the gate exhibited the maximum drain current of 1030 mA/mm, the maximum transconductance of 814.6 mS/mm, and the threshold voltage was extracted graphically to be −0.26 V at V ds = 1 V. On the other hand, the single gate MOSHEMT with conventional dielectric and cavity under the gate exhibited the maximum drain current of 651 mA/mm, the maximum transconductance of 771.6 mS/mm, and the threshold voltage was extracted graphically to be −0.21 V at V ds = 1 V. The I off leakage currents were obtained as 42.89 μA/μm and 29.5 μA/μm at V ds = 1 V for SGMH-CD-CUG and SGMH-TD-UG, respectively. The I on current was found to be 520.4 μA/μm and 716.8 μA/μm for SGMH-CD-CUG and SGMH-TD-UG, respectively. Sensitivity Analysis The sensitivity of the proposed device SGMH-TD-CUG has been calculated based on the following equations. The drain current sensitivity analysis can be carried out using the following equation: S Ids =

ΔIds ref mol Ids

=

ref mol bio mol − Ids Ids ref mol Ids

(1)

Impact of Tapered Dielectric on a Gallium Nitride Metal Oxide Semiconductor … Table 1 Neutral biomolecules and their permittivity [33]

Neutral Biomolecule

κ

Uricase

1.54

Urease

1.64

Streptavidin

2.1

Protein

2.5

Biotin

2.63

Cholesterol Oxidase (ChOx )

3.28

Glucose Oxidase (GOx)

3.46

181

ref mol where Ids is the drain to source current with reference molecule (air with κ = 1) bio mol is the drain to source current with biomolecule in the cavity. in the cavity and Ids The threshold voltage sensitivity analysis can be carried out using the following equation:

SVt =

Vtref mol − Vtbio mol ΔVt = Vtref mol Vtref mol

(2)

Here, Vtref mol is the threshold voltage of the SGMH-TD-CUG with reference molecule (air with κ = 1) in the cavity and Vtref mol is the threshold voltage of the SGMH-TD-CUG with biomolecule in the cavity. The transconductance sensitivity analysis can be carried out using the following equation: Sgm =

Δgm g ref mol − gmbio mol = m ref mol gm gmref mol

(3)

Here, gmref mol is the threshold voltage of the SGMH-TD-CUG with reference molecule (air with κ = 1) in the cavity, and gmbio mol is the threshold voltage of the SGMH-TD-CUG with biomolecule in the cavity. The different neutral biomolecules that have been considered in this paper are mentioned in Table 1. By changing the permittivity of the cavity under the gate variation in drain current, transconductance and threshold voltage is recorded for sensitivity analysis. The reference molecule is air (κ = 1) which is considered for the reference device. The transfer characteristics for V ds = 1 V and output characteristics for V gs = 1 V with the cavity filled with neutral biomolecules have been presented in Figs. 7 and 8, respectively. The leakage current performance improves when a cavity is filled with neutral biomolecules. Figure 7 shows the variation of drain current at constant V ds for V gs −1.8 to 1.8 V. The variation increases with the increase in the permittivity (κ) of the biomolecule which suggests that this device could be used for biomolecule detection for neutral biomolecules with higher permittivity. Figure 8 shows the variation of drain current at constant V gs for V ds ranging from 0 to 1.8 V. The variation does show an increase with the increase in the

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Fig. 7 Transfer characteristics with different biomolecules in the cavity of SGMH-TD-CUG for V ds = 1V

Fig. 8 Output characteristics with different biomolecules in the cavity of SGMH-TD-CUG for V gs = 1V

permittivity (κ) of the biomolecule, but it is not significant which suggests that this character would not be suitable for biomolecule detection. The variation in drain current, threshold voltage, and transconductance of the SGMH-TD-CUG with different neutral biomolecules in the cavity has been presented in Tables 2, 3, and 4. The largest drain current sensitivity, threshold voltage sensitivity, and transconductance sensitivity have been obtained for GOx to be 31.1%, 23.08%, and 9.05%, while the smallest drain current sensitivity, threshold voltage sensitivity, and transconductance sensitivity have been obtained for Uricase as 8.74%, 5.77%, and 1.80%, respectively suggesting a major influence of dielectric modulation on the sensitivity analysis of a device. Thus, we see that the neutral biomolecules assumed to have filled the CUG completely affect the characteristics of the device that may be exploited toward biosensing applications.

Impact of Tapered Dielectric on a Gallium Nitride Metal Oxide Semiconductor …

183

Table 2 Variation in drain current of the SGMH-TD-CUG with different biomolecules Biomolecule in the cavity of SGMH-TD-CUG

ΔIds (mA/mm) This work

[33]

[35]

Uricase (κ = 1.54)

90

35.1

217

Urease (κ = 1.64)

100

41.3

–

Streptavidin (κ = 2.1)

140

70.6

175

Protein (κ = 2.5)

150

94.9

140

Biotin (κ = 2.63)

170

103.2

−

ChOx (κ = 3.28)

300

138.4

62.4

GOx (κ = 3.46)

310

147.1

−

Table 3 Variation in threshold voltage of the SGMH-TD-CUG with different biomolecules Biomolecule in the cavity of SGMH-TD-CUG

ΔVt (V) This work

[38]

[39]

Uricase (κ = 1.54)

0.015

0.150

0.047

Urease (κ = 1.64)

0.02

–

–

Streptavidin (κ = 2.1)

0.035

0.118

–

Protein (κ = 2.5)

0.04

0.093

–

Biotin (κ = 2.63)

0.045

–

–

ChOx (κ = 3.28)

0.055

0.0038

–

Gox (κ = 3.46)

0.06

–

–

Table 4 Variation in transconductance of the SGMH-TD-CUG with different biomolecules

Biomolecule in the cavity of SGMH-TD-CUG Δgm (mS/mm) This work Uricase (κ = 1.54)

14.6

Urease (κ = 1.64)

18.4

Streptavidin (κ = 2.1)

28.4

Protein (κ = 2.5)

35.7

Biotin (κ = 2.63)

43.9

ChOx (κ = 3.28)

65

Gox (κ = 3.46)

73.7

4 Conclusion In this paper, we have simulated an AlGaN/ GaN single gate MOSHEMT with tapered HfO2 as gate oxide with a cavity under the gate with a gate length of 20 nm that exhibited a maximum drain current of 1474 mA/mm at V ds = 1.8 V. The threshold voltage for the normally on SGMH-TD-CUG was extracted to be −0.26 V for V ds

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= 1 V. By variation of the dielectric to model different neutral biomolecules in the cavity under the gate, sensitivity analysis based on variation in device parameters like drain current, transconductance, and threshold voltage has been performed. The maximum drain current sensitivity, maximum threshold voltage sensitivity, and maximum transconductance sensitivity have been obtained for GOx to be 31.1%, 23.08%, and 9.05%, respectively. The results obtained show that the AlGaN/GaN single gate MOSHEMT with tapered dielectric and cavity under the gate provides a promising approach for biomolecule detection and biomedical applications.

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Carrier Transport and Radiative Recombination Rate Enhancement in GaN/AlGaN Multiple Quantum Well UV-LED Using Band Engineering for Light Technology Samadrita Das, Trupti Ranjan Lenka, F. A. Talukdar, Ravi Teja Velpula, and Hieu Pham Trung Nguyen Abstract Graded composition in the barriers of multi-quantum was depicted and incorporated upon a c-plane GaN/AlGaN light emitting diodes (LEDs) constructed above a sapphire substrate for carrier transportation enhancement and lowering of efficiency droop. Because of their potential applications in various fields, ultra-violet LEDs formed on gallium nitride (GaN) materials have been the topic of interest for various researchers. The simulation outcomes exhibit that optimized light emitting diode having an aluminum constitution graded between 26% and ~2% in per triangular barrier demonstrates largest internal quantum efficiency (IQE) (38%) around 100 A/cm2 indicating significant rise compared to the conventional device having square barriers. This improvement has been ascribed to the modified energy band structures that upgrade the uniformity during transportation of carriers and also enhance the recombination rate in every GaN quantum well. As a result of this, the IQE of the device improves. The simulated LED device with graded quantum barrier structure acquires lower series resistance and substantially minimized efficiency droop characteristics of nearly 3.6% with respect to 11.8% for conventional

S. Das (B) · T. R. Lenka · F. A. Talukdar Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam 788010, India e-mail: [email protected] T. R. Lenka e-mail: [email protected] F. A. Talukdar e-mail: [email protected] R. T. Velpula · H. P. T. Nguyen Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, NJ 07102, USA e-mail: [email protected] H. P. T. Nguyen e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_20

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device, supporting carrier enhancement (both electron as well as hole) transport in our designed device. Keywords Ultra-violet (UV) · Light emitting diode (LED) · Gallium nitride (GaN) · Internal quantum efficiency (IQE) · Multiple quantum well (MQW) · Quantum barrier (QB) · Electron blocking layer (EBL)

1 Introduction Ultra-violet light emitting diodes (LEDs) are of immense importance because of their potential applications in optical communication, pharmaceutical appliances, water and air purification, household lightning, and many more. Gallium nitride (GaN), a promising material for generating UV luminescence over a wide range of spectrum, has attracted many researchers’ attention [1, 2]. GaN shows a wide band gap ranging from 0.7 eV, 3.4 eV to 6.2 eV. However, this band gap can be widely tuned when mixed with aluminum (Al) or indium (In) to prepare AlGaN or InGaN alloys, respectively [3, 4]. Moreover, GaN being an environmental friendly material has better biocompatibility and low price of manufacturing [5]. Because of these properties, GaN can be used for creating high-efficiency semiconductor-based materials such as LEDs and laser diodes (LDs) with shorter wavelength luminescence and lower threshold [6, 7]. From the last few years, research has been going on regarding the optimization of the GaN-based LED device structure design [8, 9]. This optimization is beneficial to improve the efficiency in the symmetry of carrier transport, better injected charge carriers, and confinement of carriers in the quantum wells which further enhances the radiative recombination rate leading to the breakthrough in the internal quantum efficiency (IQE) [10–12]. In our paper, we have presented a distinctive design of the quantum barriers (QB) in GaN/AlGaN multiple quantum well (MQW) devices by graded composition inside the entire barrier across [0001] axis. The IQEs, energy band diagrams, carrier injection, luminescence power, current– voltage, radiative recombination characteristics of the UV-based LEDs consisting of GaN/AlGaN MQWs having graded composed quantum barriers were analyzed, and contrasts during the transportation of carriers between graded QBs-based LEDs and conventional LED were studied and displayed.

2 Device Structure and Numerical Framework The simulation of the above mentioned properties of the UV-based LED was achieved with the use of computer-aided simulation program Silvaco ATLAS TCAD which is designed to analyze and optimize LEDs based on wurtzite semiconductor

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Fig. 1 Schematic diagram of GaN-based UV-LEDs

compounds. A GaN/AlGaN LED having a peak wavelength of ∼ 360 nm is presented using this software as shown in Fig. 1. Here, the device structure is constructed above a sapphire-based substrate with a thickness of 80 µm, an n-doped AlGaN coating layer (doping concentration: 1 × 1020 cm−3 , width: 1.8 µm, Al content: 18%), four pairs of AlGaN (7 nm)/GaN (3 nm) MQWs, p-doped AlGaN layer which acts as the electron blocking layer (EBL) [13] (doping concentration: 2 × 1018 cm−3 , width: 20 nm, Al content: 20%), a p-doped AlGaN cladding layer (doping concentration: 1 × 1018 cm−3 , width: 180 nm, Al content: 15%), and finally p-doped GaN contact layer (doping concentration: 2.5 × 1018 cm−3 , width: 80 nm). The basic device structure configuration was optimized and is considered as the conventional LED in our study. For the betterment of this particular structure’s performance, the square barriers of the conventional LED have been replaced with graded composition AlGaN barriers. Along the n-side in every QB, the Al composition is integrated to 26% (Al0.26 Ga0.74 N) while in the p-side, the Al composition is defined by the variable x which is in the range (0 ≤ x ≤ 26%). The Al composition in each QB gradually reduces from 26% to x (Alx Ga1-x N, 0 ≤ x ≤ 0.15) across [0001] axis from n-side along p-side in all the QBs of this device. The calculations were accomplished using the carrier mobilities of 90 (electrons) and 15 (holes) cm2 V−1 s−1 , and the operating temperature was set as 300 K.

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3 Results and Analysis Internal Quantum Efficiency (IQE): The IQEs of the device with varying values of x in Alx Ga1-x N in the graded composition QBs with respect to the forward current density have been displayed in the Fig. 2. As shown, efficiency of the conventional device (x = 0.26) has the lowest value compared to the other cases of graded composition of the LED (0 ≤ x ≤ 0.15). After reducing the band gap of Alx Ga1-x N from n-side toward p-side in every QB across [0001] direction, the IQE at the same injection current density remarkably rises. Due to better prospective, the efficiencies at 100 A/cm2 are displayed in comparison with the function x in the inset of Fig. 2. While reducing values of x from 0.26 to ~0.02, the efficiency increases from 27 to 38% and then vaguely minimizes while x approaches 0. Finally, it is concluded that the upgraded LED (x = 0.02) acquires top most efficiency at 100 A/cm2 observing 40.7% rise in IQE while compared to the conventional LED having square barriers. One of the most essential results is the lessening of the efficiency droop [(ηpeak – η100 A/cm 2 )/ηpeak ] which is minimized from 11.8% (conventional LED) to 3.6% (graded quantum barrier LED x = 0.18). From this result, it establishes that the design of barriers with graded composition does contribute during the decrease of efficiency droop. Also, the graph between efficiency droop at 100 A/cm2 with respect to the Al composition x for conventional as well as graded LED is shown in Fig. 3. Energy Band Diagrams: For a thorough study regarding the different IQE with varying values of x, the band energy structures of the multiple QWs of the original LED (x = 0.26) and graded LED having x as 0.18 performed in 150 A/cm2 forward bias were measured. The simulated results shown in Fig. 4a and b depict the dissimilarities and the tendency of variation of the band energy diagrams, where the band gap of every QB is altered from uniform to graded composition. The gray lines in the figures represent the quantum wells of the device. Band diagram of conventional LED Fig. 2 Behavior of internal quantum efficiencies versus forward current densities with varying values of x. The inset shows the values of IQEs as a function of x at 100 A/cm2

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Fig. 3 Behavior of efficiency droop versus aluminum composition at 100 A/cm2

Fig. 4 a Behavior of band energy diagrams of conventional LED (x = 0.26) b graded quantum barrier LED (x = 0.18) at 150 A/cm2

(i.e., x = 0.26) depicts a triangular designed shape due of the presence of forward bias and internal polarization field [14]. Furthermore, aluminum composition in all the QBs is gradually decreased from n to p-side across [0001] direction, the triangular shape of QB’s band diagram ( )changes. The energy band gap E g of Alx Ga1 - x N can be measured as – E g (Alx Ga1−x N) = E g (AlN)x + E g (GaN)(1 − x) − 1.3x(1 − x) where E g (AlN) = Band gap energy of AlN = 6.2 eV. E g (GaN) = Band gap energy of GaN = 3.42 eV [15] This mathematical formula shows that the band gap of Alx Ga1-x N decreases with a decrease in the Al composition. Henceforth, the band gap of every QB reduces

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while moving from n-side approaching p-side, thus influencing the effective barrier heights for electrons as well as holes. Carrier Concentration: The above band energy diagrams of this device lead to electron as well as hole concentration distribution in the multi-QWs of various LEDs as displayed in Figs. 5 and 6, respectively. The conventional LED (x = 0.26) indicates hole concentration of 2 × 1018 cm−3 and 4.25 × 1018 cm−3 in the initial two quantum wells from the n to p-side, while the concentration of holes is much lower in the other two quantum wells. These results specify that graded QB LED has superior hole transport lessening the hole concentration at the final well. On the opposite, the conventional LED has the most electron concentration of 7.2 × 1018 cm−3 occurring in the initial QW, while this concentration reduces while moving from n toward p-side in case of graded QB LED. The electron distribution, as observed in graded QB device, appears to have better uniformity, compared to conventional LED, which may proportionate to superior transportation of holes [16]. Current–Voltage: The current–voltage characteristics of conventional and graded QB LED (x = 0.18) are shown in Fig. 7. The device’s series resistance is minimized from 4.36 Ω (original LED) to 3.23 Ω (graded QB LED) indicating a definite level of the enhancement in the transportation of holes. Consequently, the forward anode voltage at 750 mA decreases from 3.4 V (conventional device) to 3.23 V (graded QB LED). Radiative Recombination: The distribution of radiative recombination in the active quantum well of conventional (x = 0.26) and graded QB LEDs at an injection current density of 150 A/cm2 is simulated and illustrated in Fig. 8. From the graph, the radiative recombination in graded QB LED is more symmetrical compared to the conventional one. In our conventional LED (x = 0.26), recombination basically occurs in primary well, indicating a radiative recombination rate of 2.98 × 1027 cm−3 s−1 . However, the recombination rates of remaining three QWs are approximately zero. This is probably because of the deficient spatial distribution overlap between the carriers [17]. From Fig. 4, maximum electrons still accumulate inside initial well, while the hole concentration in the last well is less than the previous wells. However in conventional LED, both the carriers are centered at the wells close to p-GaN; hence, the radiative recombination is extremely effective at that location. Above outcomes suggest that in order to diminish the droop behavior of the LED without deteriorating total recombination, more attention has to be given to the spatial distribution between the holes and electrons [18]. Power: Figure 9 illustrated the luminous power vs. anode current for the UVLED conventional (x = 0.26) and graded QB LED. The light output is observed to be amplified accordingly with graded QB LED compared to conventional LED, because graded QB benefits from superior electron confinement capability and larger hole injection efficiency. These superior optical properties are also attributed to the decrease in the polarization field in the MQWs [19]. This improved light power

Carrier Transport and Radiative Recombination Rate Enhancement in GaN/AlGaN …

Fig. 5 Behavior of electron concentration near MQWs with varying values of x at 150 A/cm2

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Fig. 6 Behavior of hole concentration near MQWs with varying values of x at 150 A/cm2

means that more carriers radiating will recombine in the QW of graded QB LED, thus effectively improving the light efficiency of GaN/AlGaN LED [20].

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Fig. 7 Behavior of I-V characteristics of conventional LED (x = 0.26) and graded quantum barrier LED (x = 0.18)

4 Conclusion To summarize, UV-LEDs of GaN/AlGaN MQWs having specially designed graded composition AlGaN QBs are numerically explored. After reducing the band gap of AlGaN across [0001] axis from n toward the p region in every QB, the efficiencies of the device enhance. The upgraded LED having x = 0.02 acquires topmost IQE of ~38% at 100 A/cm2 which is 40.7% more compared to conventional LED (i.e., 27% at x = 0.26) having square barriers. The reason of this improvement is attributed to the modified band energy diagrams in the graded composition of AlGaN QBs. This also improves the uniformity in the transportation of carriers and the radiative recombination rate distributions in every GaN QW. The hole transport in MQWs was notably intensified at current density of 150 A/cm2 which is beneficial for droop reduction. The current–voltage curve indicated that the graded device has reduced series resistance compared to the original one, and the droop was decreased from 11.8% in conventional LED to only 3.6% in graded QB LED. Furthermore, there is also a 14.28% increase in the luminous power of the device at a current of 150 mA (x = 0.18) in contrast to that in case of conventional LED (x = 0.26).

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Fig. 8 Behavior of radiative recombination rates near MQWs with varying values of x at 150 A/cm2

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Fig. 9 Behavior of luminous power versus forward current with varying values of x

Acknowledgements The authors sincerely acknowledge DST-SERB, Govt. of India sponsored MATRICS Project No. MTR/2021/000370, DST-SERB sponsored ASEAN-India R&D Project No. CRD/2018/000068 and Visvesvaraya Young Faculty Research Fellowship by Ministry of Electronics and Information Technology (MeitY), Govt. of India, for kind support.

References 1. Usman M, Mushtaq U, Munsif M, Anwar AR, Kamran M (2019) Enhancement of the optoelectronic performance of p-down multiquantum well N-GaN light-emitting diodes. Phys Scr 94(10). https://doi.org/10.1088/1402-4896/ab28c0 2. Tao H, Xu S, Zhang J, Li P, Lin Z, Hao Y (2019) Numerical investigation on the enhanced performance of N-Polar AlGaN-based ultraviolet light-emitting diodes with superlattice p-type doping. IEEE Trans Electron Devices 66(1):478–484. https://doi.org/10.1109/TED.2018.287 8727 3. Nagasawa Y, Hirano A (2018) A review of AlGaN-based deep-ultraviolet light-emitting diodes on sapphire. Appl Sci 8(8). https://doi.org/10.3390/app8081264 4. Usman M, et al (2019) Zigzag-shaped quantum well engineering of green light-emitting diode. Superlattices Microstruct 132(June):106164. https://doi.org/10.1016/j.spmi.2019.106164 5. Kim G, Kim JH, Park EH, Kang D, Park B-G (2014) Extraction of recombination coefficients and internal quantum efficiency of GaN-based light emitting diodes considering effective volume of active region. Opt Express 22(2):1235. https://doi.org/10.1364/oe.22.001235 6. Meng Y, et al (2019) Growth and characterization of amber light-emitting diodes with dualwavelength InGaN/GaN multiple-quantum-well structures. Mater Res Express 6(8). https:// doi.org/10.1088/2053-1591/ab256d 7. Wang CH, et al (2010) Efficiency droop alleviation in InGaN/GaN light-emitting diodes by graded-thickness multiple quantum wells. Appl Phys Lett 97(18). https://doi.org/10.1063/1. 3507891 8. Lin Z, Chen X, Zhu Y, Chen X, Huang L, Li G (2018) Influence of thickness of p-InGaN layer on the device physics and material qualities of GaN-based LEDs with p-GaN/InGaN heterojunction. IEEE Trans Electron Devices 65(12):5373–5380. https://doi.org/10.1109/TED. 2018.2872525

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9. Usman M, Anwar AR, Munsif M, Malik S, Islam NU (2019) Analytical analysis of internal quantum efficiency with polarization fields in GaN-based light-emitting diodes. Superlattices Microstruct 135(September):106271. https://doi.org/10.1016/j.spmi.2019.106271 10. Kim MH et al (2007) Origin of efficiency droop in GaN-based light-emitting diodes. Appl Phys Lett 91(18):1–4. https://doi.org/10.1063/1.2800290 11. Park JH, et al (2013) Enhanced overall efficiency of GaInN-based light-emitting diodes with reduced efficiency droop by Al-composition-graded AlGaN/GaN superlattice electron blocking layer. Appl Phys Lett 103(6). https://doi.org/10.1063/1.4817800 12. Sheng Xia C, Simon Li ZM, Lu W, Hua Zhang Z, Sheng Y, Wen Cheng L (2011) Droop improvement in blue InGaN/GaN multiple quantum well light-emitting diodes with indium graded last barrier. Appl Phys Lett 99(23). https://doi.org/10.1063/1.3665252 13. Lin B-C et al (2014) Hole injection and electron overflow improvement in InGaN/GaN lightemitting diodes by a tapered AlGaN electron blocking layer. Opt Express 22(1):463. https:// doi.org/10.1364/oe.22.000463 14. Mehta K et al (2018) Theory and design of electron blocking layers for III-N-based laser diodes by numerical simulation. IEEE J Quantum Electron 54(6):1–11. https://doi.org/10.1109/JQE. 2018.2876662 15. Hirayama H, Fujikawa S, Kamata N (2015) Recent progress in AlGaN-based deep-UV LEDs. Electron Commun Japan 98(5):1–8. https://doi.org/10.1002/ecj.11667 16. Charash R et al (2009) Carrier distribution in InGaN/GaN tricolor multiple quantum well light emitting diodes. Appl Phys Lett 95(15):2007–2010. https://doi.org/10.1063/1.3244203 17. Zhou S, Lv J, Wu Y, Zhang Y, Zheng C, Liu S (2018) Reverse leakage current characteristics of InGaN/GaN multiple quantum well ultraviolet/blue/green light-emitting diodes. Jpn J Appl Phys 57(5). https://doi.org/10.7567/JJAP.57.051003 18. Chang J et al (2016) AlGaN-based multiple quantum well deep ultraviolet light-emitting diodes with polarization doping. IEEE Photonics J 8(1):1–7. https://doi.org/10.1109/JPHOT.2016.251 6257 19. Wang TY, et al. (2020) AlGaN-based deep ultraviolet light emitting diodes with magnesium delta-doped AlGaN last barrier. Appl Phys Lett 117(25). https://doi.org/10.1063/5.0026911 20. Li H, Chang CJ, Kuo SY, Wu HC, Huang H, Lu TC (2019) Improved performance of near UV GaN-Based light emitting diodes with asymmetric triangular multiple quantum wells. IEEE J Quantum Electron 55(1):1–4. https://doi.org/10.1109/JQE.2018.2883158

Comparative Study of Electrical Performances of Bio-Electrochemical Cell Monika Paul, K. A. Khan, and Bithi Paul

Abstract Plant extract can be the alternated cost-effective and ecofriendly source of electrolyte for the electrochemical cell. In this study, six types of plant extract electrolyte have been used on the electrochemical cell, and the electrical performances of six bio-electrochemical cells were investigated. The highest average voltage (1.14 V), current (21.25 mA) were obtained for PKL extract cell, and the lowest performances were found for aloe vera cell. The power and capacity were also calculated for this all cell. All electrical performances of PKL extract cell were more significant than other plants extract electrolyte cells. The electrical performances of all of these bioelectrochemical cells have been graphically represented in this paper. This comparative study regarding the performances of different electrochemical cells may open a promising platform for ecofriendly, cost-effective power production. Keywords Bio-electrochemical cell · Plant extract · Voltage · Current · Capacity · Cost-effective · Electricity

1 Introduction The rising energy demand has driven researchers to harvest the maximum electricity by using the ecofriendly and cost-effective approach. Now a days, many efficient technologies have been introduced to development of renewable energy system such as hydrogen-rich syngas production [8], microbial fuel cells [1, 4, 8, 9], and hydrogen gas production [10]. Moreover, microorganism source has also been reported to the

M. Paul (B) Department of Zoology, National University, Gazipur, Bangladesh e-mail: [email protected] K. A. Khan Department of Physics, Jagannath University, Dhaka, Bangladesh B. Paul Department of Physics, American International University-Bangladesh, Dhaka, Bangladesh © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_21

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generation of electricity [4]. Though use of microorganism amplifies the power generation of electrochemical cell but still, it is very difficult to determine the contribution mechanism of microorganism for power generation [2, 7]. Besides this, many technologies have been utilized to find the alternative energy source for the production of low-cost electricity by using different bio-electrolytes in the electrochemical cell [5, 6, 11]. Various vegetative plants and fruits juice have been used as a source of bio-electrolytes for the power production of electrochemical cells [5]. In recent days, PKL cells are becoming a very interesting and suitable renewable energy source for low-cost power generation [5]. In this paper, a comparative analysis has been done by using six plant extracts as electrolytes for the electrochemical cell. The bio-electrochemical cells have been constructed by using PKL juice, aloe vera juice, aurum leaf juice, lemon juice, myrobalan juice, and tomato juice as the source of bio-electrolytes. In the electrochemical cell, zinc and copper plates have been used as anode and cathode, respectively. Zn/Cu electrodes and 32% extract, 68% water-electrolyte were used for all electrochemical cells. The short-circuit current and open-circuit voltage were recorded for all cell. The maximum power and capacity were also calculated. All of these cells have shown electrical characteristics, and the findings indicate that PKL cell showed the highest capacity and maximum power among all cells.

2 Materials and Methods PKL and aurum leaves were collected from Jagannath University campus, and juice of leaves was prepared by blender machine. Aloe vera, myrobalan, tomato, and lemon were collected from the local market, and juices were prepared by using the blender machine. All kind of juices were filtered properly. After filtration, PKL, aloe vera, aurum leaf, lemon, myrobalan, and tomato juice were used as electrolytes in the electrochemical cell to generate the electricity. Six bio-electrochemical cells were designated separately for six types of plant electrolytes. Zn and Cu electrodes were used for all electrochemical cells. The electrical performances of PKL, aloe vera, aurum leaf, lemon, myrobalan, and tomato juice electrolyte-based cells were monitored with time duration.

3 Experimental Setup of Cells Zinc and copper plates were taken as anode and cathode, respectively, for electrochemical cells. PKL juice, aloe vera juice, aurum leaf juice, lemon juice, myrobalan juice, and tomato juice were used as an electrolyte for the electrochemical cells. An ammeter and a voltmeter were connected for each cell. The experimental setup for bio-electrochemical cells has been shown in Fig. 1.

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Fig. 1 Experimental setup of bio-electrochemical cell

4 Chemical Reactions of Bio-Electrochemical Cells (a)

At Zinc: Zn = Zn2+ + 2e− [Here, Zn2+ = Product ion]

Here, Zn is called sacrificial element (b)

At Copper: Cu++ + 2e− = Cu [Here, Cu2+ = Reactant ion. Here]

–––––––––––––––––––––––––––––––––––––––––– Adding: Zn + Cu2+ = Zn2+ + Cu [Where Cu2+ = Reactant ion, and Zn2+ = Product Ion] (c) (d)

At Zinc: Zn = Zn2+ + 2e− [where Zn2+ = Product ion] At plant extract electrolyte: 2H+ + 2e− = H2 [Here, H+ = Reactant ion]

–––––––––––––––––––––––––––––––––––––––––– Adding: Zn + H+ = Zn2+ + H2 [Here, H+ = Reactant ion, and Zn2+ = Product ion] Total reaction: Zn + Cu2+ + H+ = Zn2+ + Cu + H2 [where Cu2+ = Reactant ion, H+ = Reactant ion, and Zn2+ = Product Ion] The total potential of electrochemical cell can be determined by the Nernst equation: E = E 0 _ RT /n F ln (Q) Here, E and E 0 are the cell voltage and cell voltage at standard state condition, respectively. R is represented as molar gas constant, and the value of R is 8.314 J mole−1 K−1 ]. F is called Faraday constant; n represents the No. of transferred electrons. The temperature of electrolyte is denoted by T. Q is the reaction

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quotient constant which is equivalent to [Product Ion] ÷ [Reactant Ion] [3]. At a constant temperature, the potential of the voltaic cell depends on the quotient constant. When Q is less than 1 (Q < 1), then lnQ becomes negative which gives the higher potential of cell. Since Q is the ratio of [Product Ion] and [Reactant Ion], as much as the Reactant Ion increases, the value of Q will be decreased [less than 1]. Plant electrolyte contains weak organic acids which provides reactant ions H+ during the reaction.

5 Results and Discussions Two fundamental parameters (voltage and current) were recorded for six cells with the time duration, and the maximum power (Pmax ), capacity were calculated for all electrochemical cells. Figure 2 shows the open-circuit voltage with the time duration

Fig. 2 Open-circuit voltage of bio-electrochemical cells with the time duration

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PKL Cell

120

80

40

0 0

Aloe Vera Cell

40

30

20

10

0 0

96 144 192 240 288 336 384 432 480 528

48 96 144 192 240 288 336 384 432 480 528

Time Duration (Hrs)

50

Short Circuit Current ,ISC (mA)

48

Aurum Leaf Cell 40

30

20

10

Time Duration (Hrs) 80

Short Circuit Current ,ISC (mA)

Short Circuit Current ,ISC (mA)

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Short Circuit Current ,ISC (mA)

for all cells. Figure 3 shows the short-circuit current for PKL cell, aloe vera cell, aurum leaf cell, lemon cell, myrobalan cell, and tomato cell. Figure 4 shows the capacity of all electrochemical cells. Figure 5 shows the comparison data of all electrical parameters of cells. Figure 6 represents the calculated average electrical data of six cells.

60 50 40 30 20 10 0

0

Lemon Cell

70

48 96 144 192 240 288 336 384 432 480 528

0

90

Myrobalan Cell 40 30 20 10

0

48 96 144 192 240 288 336 384 432 480 528 Time Duration (Hrs)

Short Circuit Current ,ISC (mA)

Short Circuit Current ,ISC (mA)

50

0

48 96 144 192 240 288 336 384 432 480 528 Time Duration (Hrs)

Time Duration (Hrs)

Tomato Cell

80 70 60 50 40 30 20 10 0

0

48 96 144 192 240 288 336 384 432 480 528 Time Duration (Hrs)

Fig. 3 Short-circuit current of bio-electrochemical cells with the time duration

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1.4

Aloe Vera cell

PKL Cell

1.2

0.8

Capacity (AH)

Capacity (AH)

1.0 0.8 0.6 0.4 0.2 0.0 -0.2

0.6 0.4 0.2 0.0

0

48

96

0

144 192 240 288 336 384 432

48

96 144 192 240 288 336 384 432

Time Duration (Hrs)

Time Duration (Hrs) 1.4

Aurum Leaf cell

1.2

0.8

Capacity (AH)

1.0

Capacity (AH)

Lemon cell

1.0

0.8 0.6 0.4 0.2

0.6 0.4 0.2 0.0

0.0 0

48

96 144 192 240 288 336 384 432

Time Duration (Hrs)

0

48

96 144 192 240 288 336 384 432

Time Duration (Hrs)

Fig. 4 Capacity of bio-electrochemical cells with the time duration

5.1 Open-Circuit Voltage of Cells In Fig. 2, PKL electrochemical cell shows the highest open-circuit voltage and shortcircuit current which resultant as maximum power for PKL cell. Initially, it starts at 0.95 V, and after a few hours, it reaches 1.15 V and remains steady for the next seven days. After then, the open-circuit voltage was decreased for a few hours, and again, it was increased. The maximum open-circuit voltage for PKL cell was found at 1.18 V. For the aloe vera cell, the open-circuit voltage starts from 1.35 V, but dramatically, it was decreased to 0.75 V within a few hours and remains almost the same for the next 300 h. It was again increased and remains constant at around 0.90 V. The starting open-circuit voltages for both aurum leaf cell and myrobalan cell were recorded at around 1.10 V, and the final voltages were also the same at 0.97 V. For the lemon cell, maximum open-circuit voltage was found at 1.40 V, and it remained constant at

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1.3 1.2 1.1 1.0 0.9 0.8 0.7

160

Short Circuit Current (mA)

Open Circuit Voltage (volt)

Aurum Leaf Cell Aloe vera Cell Myrobalan Cell Tomato Cell

PKL Cell Lemon Cell

1.4

205

0

100

200

300

400

PKL Cell Lemon Cell

140 120 100 80 60 40 20 0 0

500

100

Time Duration (hr)

200

300

400

500

Time Duration (hr) 1.8

0.16 PKL Cell Lemon Cell

0.14

Aloe vera Cell Aurum Leaf Cell Myrobalan Cell Tomato Cell

Aurum Leaf cell Aloe Vera cell PKL Cell Tomato cell Myrobalan cell Lemon cell

1.6 1.4

0.12 0.10

Capacity (AH)

Maximum Power (watt)

Aloe vera Cell Aurum Leaf Cell Myrobalan Cell Tomato Cell

0.08 0.06 0.04

1.2 1.0 0.8 0.6 0.4 0.2

0.02

0.0

0.00 0

100

200

300

400

500

-0.2

0

48

Time Duration (hr)

Fig. 5 Comparative analysis of electrical properties of six cells

Fig. 6 Average electrical performances of six cells

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0.90 V till the ending time. In the beginning, the open-circuit voltage for the tomato cell was found at 1.15 V, and it was decreasing with the time duration, and finally, it reached 0.80 V. The comparative open-circuit voltage for all of those six cells was shown in Fig. 5.

5.2 Short-Circuit Current Figure 3 showed the recorded short-circuit current for all cells. The maximum current for PKL cell was recorded at 150 mA, and for aloe vera cell, aurum leaf cell, lemon cell, myrobalan cell, and tomato cell current were found at around 40 mA, 45 mA, 74 mA, 46 mA, and 83 mA, respectively. Moreover, for all of these six cells, the short-circuit current was decreased after a few hours then remain almost constant with the time duration till the end. The comparative short-circuit current has been shown in Fig. 5.

5.3 Capacity of Cells Capacity is a very important electrical parameter for an electrochemical cell. Higher capacity indicated the higher performance of the cell. In this study, capacity has been calculated by the formula of capacity = load current (I L ) × discharge time (T d ). Figure 4 represents the capacity of all cells with the time duration. It is very interesting to say that PKL cell again showed the highest capacity, and aloe vera cell showed the lowest capacity among all of six cells. For all cells, capacity was increasing with the time duration then started to decrease finally. The average capacity of the PKL cell was found at 0.436 AH which indicates the PKL cell is more sustainable for power production.

5.4 Maximum Power (Pmax ) of Cells The maximum power of all six cells was calculated by the following formula: Power = Voltage × Current. Figure 5 shows the comparative data of open-circuit voltage, and short circuit current, and maximum power six bio-electrochemical cells. It is clearly shown that among all cells PKL cell shows greater maximum power.

5.5 Average Performances of Cells Figure 6 represents the average electrical performances of all electrochemical cells.

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Table 1 Comparative analysis of all bio-electrochemical cell Name of cell

Average Average Average Average capacity, open-circuit short-circuit maximum power, C (AH) voltage, V oc (volt) current, I sc (mA) Pmax (watt)

PKL cell

1.14

21.25

0.030

0.436

Aloe vera cell

0.82

8.16

0.007

0.255

Aurum leaf cell 0.98

18.58

0.018

0.383

Lemon cell

0.96

15.94

0.016

0.310

Myrobalan cell

0.92

14.13

0.013

0.264

Tomato cell

0.90

14.40

0.014

0.094

Figure 6 indicates that the maximum average voltage and current were observed for PKL cell. The minimum average voltage and current were recorded for the aloe vera cell. As a result, the maximum power and minimum power have been calculated for PKL cell and aloe vera cell, respectively. Eventually, it can be considered that all six cells are feasible for electricity production, and PKL cell shows the maximum values for all these electrical parameters among all electrochemical cells. Table 1 represents the average electrical performances of six cells.

6 Conclusion In this study, six bio-electrochemical cells have been successfully constructed, and important electrical properties like open-circuit voltage, short-circuit current, maximum power, and capacity have been examined for all cells. PKL cell showed the highest performances for V oc , I sc , Pmax , and capacity, whereas aloe vera cell showed the lowest values of these electrical parameters among all cells. Since it is very interesting to the production of electricity by bio-electrochemical cells, the comparative study of electrical properties of different electrochemical cells will be very effective to enhance the development a cost-effective, ecofriendly bio-electrochemical cell.

References 1. Chaturvedi V, Verma P (2016) Microbial fuel cell: a green approach for the utilization of waste for the generation of bioelectricity. Bioresour Bioprocess 3:38. https://doi.org/10.1186/s40643016-0116-6 2. Chaudhuri SK, Lovley DR (2003) Electricity generation by direct oxidation of glucose in mediatorless microbial fuel cells. Nat Biotechnol 21:1229–1232. https://doi.org/10.1038/ nbt867 3. Ciribelli BN, Colmati F, de Souza EC (2020) Nernst equation applied to electrochemical systems and centenary of his Nobel Prize in chemistry. IJIER 8:670–683. https://doi.org/10. 31686/ijier.vol8.iss11.2803

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4. Ismail ZZ, Jaeel AJ (2013) Sustainable power generation in continuous flow microbial fuel cell treating actual wastewater: influence of biocatalyst type on electricity production. Sci World J 2013:1–7. https://doi.org/10.1155/2013/713515 5. Khan KA, Hassan L, Obaydullah AKM, Azharul Islam SM, Mamun MA, Akter T, Hasan M, Alam MdS, Ibrahim M, Rahman MM, Shahjahan M (2020) Bioelectricity: a new approach to provide the electrical power from vegetative and fruits at off-grid region. Microsyst Technol 26:3161–3172. https://doi.org/10.1007/s00542-018-3808-3 6. Khan KA, Mamun MA, Ibrahim M, Hasan M, Ohiduzzaman M, Obaydullah AKM, Wadud MA, Shajahan M (2019) PKL electrochemical cell: physics and chemistry. SN Appl Sci 1:1335. https://doi.org/10.1007/s42452-019-1363-x 7. Park DH, Zeikus JG (2003) Improved fuel cell and electrode designs for producing electricity from microbial degradation. Biotechnol Bioeng 81:348–355. https://doi.org/10.1002/bit.10501 8. Thakur S, Das B (2021) Bio-electrochemical evaluation of two-stage constructed wetland microbial fuel cells with high strength raw domestic wastewater and simultaneous energy recovery. Water Environ J. wej.12714. doi: https://doi.org/10.1111/wej.12714 9. Tharali AD, Sain N, Osborne WJ (2016) Microbial fuel cells in bioelectricity production. Front Life Sci 9:252–266. https://doi.org/10.1080/21553769.2016.1230787 10. Wang Y-H, Wang B-S, Liu Y-P, Chen Q-Y (2013) Electricity and hydrogen co-production from a bio-electrochemical cell with acetate substrate. Int J Hydrogen Energy 38:6600–6606. https:// doi.org/10.1016/j.ijhydene.2013.03.043 11. Zheng T, Li J, Ji Y, Zhang W, Fang Y, Xin F, Dong W, Wei P, Ma J, Jiang M (2020) Progress and prospects of bioelectrochemical systems: electron transfer and its applications in the microbial metabolism. Front Bioeng Biotechnol 8:10. https://doi.org/10.3389/fbioe.2020.00010

Performance Evaluation of Silver-Doped CZTSe Kesterite Solar Cell with p+ -CZTSe as BSF Layer A. Benisha Chris and Soumyaranjan Routray

Abstract A systematical innovative model using CZTSe which is earth-abundant and non-toxic material based on p/n junction and silver-doped CZTSe which increases crystallization quality of CZTSe kesterite material with CZTSe as BSF layer of p+ /p/n junction solar cell was modeled toward high photovoltaic characteristic. It is observed that the configuration of CdS/ACZTSe/CZTSe exploits enhancement of depletion region using the primary absorber layer (ACZTSe) and (CZTSe) BSF layer which reduces the recombination rate and enhances the short circuit current Jsc . In our model, carriers are improved through the absorber layer. There is a substantial decrease in recombination losses after using ACZTSe as the active layer and CZTSe as p+ layers. We endeavor further ACZTSe thicknesses thus determining the optimum obtainable performance of 35.21% at its 3.0 µm ACZTSe thickness with 0.7093 V open-circuit voltage, 57.05 mA/cm2 power in a short circuit, and the fill factor 87.0% under AM1.5 global illumination and more than 80\% of quantum efficiency is achieved. This proposal’s modeling advances the efficiency of ACZTSe kesterite solar cells. Keywords ACZTSe · BSF layer · Kesterite · Solar cells

1 Introduction These days, a thin-film solar cell with a Kesterite structure based on CZTS, CZTSe, and CZTSSe is a beneficial semiconductor saves money and develops long-term solar cell devices [2, 3]. The kesterite structure is derived from the chalcopyrite Cu, In, Ga, and Se2 as CIGS solar cell, at which two In+3 or Ga+3 atoms in CIGS are replaced by one Zn+2 and one Sn+4 atom, respectively [5]. Conversely, the highest current conversion acquired using kesterite compounds about 12.6% that is still less than CIGS devices achieved conversion efficiency around 23.35% [4]. The limited output of kesterite thin-film solar cells is primarily due to lower absorber layer band A. Benisha Chris · S. Routray (B) SRM Institute of Science and Technology, Chennai 603203, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_22

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gap, high recombination rates [10]. On the other side, issues include scarcity of adequate configuration of the energy bands at the contact among the absorber and the buffer, development at undesirable secondary aspects, and the interface reducing performance [7]. One strategy for increasing photo voltaic cell efficiency rate is to create a back-surface field (BSF) layer, which propels the minority charge carrier forward improves its electrical performances in the proposed cell, particularly the efficiency [1, 6]. Additionally, since maximum width of Ag+ (1.14A) is superior to Cu+ (0.74A), by introducing Ag ions prevent Cu/Zn antisite defects [11]. Recently reported that I–II antisite is reduced when copper (Cu) is converted to silver (Ag) improving the performance of (ACZTSe) solar cells [12]. In this research paper, the impact of CZTSe fine photovoltaic cell and silvermixed CZTSe (ACZTSe) with CZTSe as (BSF) layers has been compared indeed investigated. To improve performance, we designed a new material structure of n/p/p+ kesterite solar cell as CdS, silver (Ag) mixed CZTSe as (ACZTSe), and CZTSe layers for n, p, and p+-doped areas, respectively. Furthermore, to optimize the solar cell’s capability, we varied ACZTSe thickness (active layer). The Silvaco ATLAS TCAD tool is employed to address the research problem of CdS/CZTSe structure with our novel structure CdS/ACZTSe/CZTSe at the standard AM1.5 global spectrum.

2 Device Structure Figure 1a, b illustrates the structure of our proposed n/p and n/p/p+ CZTSe solar cells. In n/p structure, CdS acts as the n doped (buffer layer) and CZTSe acts as the p doped (absorber layer). By expanding the depleting area throughout its entire layer, we were able to improve the minority carriers by designing an n/p/p+ structure where an additional part of ACZTSe is mounted between CZTS/CdS in this case, ACZTSe operates as an active layer, and CZTSe acts as a BSF layer. We altered the thicknesses in this investigation to optimize the efficiency of our configuration. As a function of wavelength, each material’s refractive index (n) and extinction coefficient (k) were calculated. During the design process, models such as Drift-Diffusion, FERMI DIRAC, and CVT (Concentration voltage and temperature), Auger, SRH, and OPTR (optical recombination) were evaluated using Silvaco ATLAS TCAD. This kind of model generates mobility, Fermi-Dirac carrier statistics, and electron recombination rate, and more detailed model phenomena are revealed in [9]. Table.1 lists several important parameters of the materials used in our proposed structures. In this table, E g stands for band gap, μn and μp for electron and hole mobility, N A and N D for accepter and donor density, χ is the dielectric constant, and B is radiative coefficient. As a result, for the first time, the CdS/ACZTSe/CZTS structure is investigated and revealed.

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Fig. 1 Device configuration for kesterite solar cell based on a CdS/CZTSe b CdS/ACZTSe/CZTSe structures

Table 1 Material parameters used in simulation [6, 8, 13] Parameters

CZTSe

ACZTSe

CdS

ZnO

AZO

Thick (µm)

2 µm

Varied

1 µm

1 µm

1 µm

E dc

7

8.5

9

9

9

E g (eV)

1.05

1.15

2.4

3.3

3.3

χ (eV)

4.1

4.14

4.2

4.4

4.4

μn

(cm2 /V.s)

60

1

100

100

100

μp (cm2 /V.s)

20

0.9

25

25

31

N A (cm−3 )

7 × 1017

1 × 1014

0

0

1×

ND

(cm−3 )

0

NC

(cm−3 )

2.2 ×

N V (cm−3 ) B

1018

1.8 × 1019 7.2 ×

10−10

2.2 ×

1018

1.8 × 1019 1×

10−18

0 1017

1.8 ×

1019

2.4 × 1018 1×

10−9

1×

0 1018

2.4 ×

1018

1.8 × 1018 1×

10−9

1 × 1020 3 × 1018 1.7 × 1019 1 × 10−9

3 Result and Analysis Figure 2a, b shows energy band diagrams for the proposed structures CdS/CZTSe and CdS/ACZTSe/CZTSe, which explain the properties of the solar cells. From band alignment, it is discovered that the depletion area extends beyond 1.6 µm for n/p/p+ configuration and has a spikey texture (type-I) shape, suggesting that strikes in the

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Fig. 2 Illustrates alignment of energy band a CdS/CZTSe and b CdS/ACZTSe/CZTSe structures

positive energy band between CdS /ACZTSe/ and CZTSe would be important in enhancing electron-hole separation. Figure 3a determines the electric field distribution in both proposed structures. A relatively high electric field is observed in CdS/ACZTSe/CZTSe. This might be attributed to differences in band gap of materials in CdS/ACZTSe/CZTSe, which amplifies the ions and extends the electric field in our modified layout through drift mechanism, which improves the carrier lifetime. As a result, potential development in these n/p/p+ regions is higher than in the n/p region shown in Fig. 3b. When compared to the p/n, structure from Fig. 4a reveals that the recombination establishments of the p+/P/n interface are very low. It conforms that the use of BSF layer material reduces minority carrier transport and recombination near the surface terminal. Figure 4b compares the I-V characteristic of cathode current with and without silver-mixed CZTSe layer. In both cases, the Voc is almost unaffected and jsc is enhanced in CdS/ACZTSe/CZTSe structure than the CdS/CZTSe structure as ACZTSe reduces antisites defects, increases short carrier lifetime, improves crystalline quality, and BSF layer reduces surface recombination. From Fig. 5a, b, the spectral response shows that internal quantum efficiency (IQE) and external quantum efficiency (EQE) follow each other almost at the same

Fig. 3 Illustrates a potential b electric field of CdS/CZTSe and CdS/ACZTSe/CZTSe structures

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Fig. 4 Illustrates comparison of CdS/ACZTSe/CZTSe structures

213

a recombination b IV curve of CdS/CZTSe and

Fig. 5 Illustrates a internal b external quantum efficiency of CdS/CZTSe and CdS/ACZTSe/CZTSe structures

rate, which concludes that IQE/EQE is high for the CdS/ACZTSe/CZTSe structure due to the high absorption coefficient of silver-mixed CZTSe. In the BSF layers, the electric field transfer carriers are enhanced. Finally, Table 2 compares the performance of CdS/CZTSe and CdS/ACZTSe/CZTSe solar cells which has reached an efficiency 35.24%. As seen in the introduction, Kesterite materials have sparked having lot of focus as absorbent materials for photovoltaics. This new framework simplifies the creation of higher-performing CZTSe-based devices, bringing the existing state of the art up to date. Table 2 Comparison of device performance of CZTSe and ACZTSe/CZTSe Device structure

J sc (mA/cm2 )

V oc (V)

FF (%)

Eff. (%)

CZTSe

49.24

0.661

84.31

27.45

ACZTSe/CZTSe

57.05

0.709

87.00

35.21

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4 Conclusion The simulation results prove that silver-mixed CZTSe as active layer optimization and CZTSe as BSF layer improves carrier transport with an efficiency of 35.21%, resulting in an increase in J sc of around 57.06 mA/cm2 . The existence of the p+/p/n configuration increases the electric field and reduces the recombination rate. I-V characteristics, spectral response, EQE and IQE, and other output parameters were measured under one-sun illumination. These investigation will pave the way for further research into silver-mixed CZTSe, for mass manufacturing of next-generation photovoltaic systems.

References 1. Anderson NG (1995) Ideal theory of quantum well solar cells. J Appl Phys 78(3):1850–1861. Abderrezek M, Djeghlal ME, et al (2020) Comparative study on cu2znsn (s, se) 4 based thin film solar cell performances by adding various back surface field (bsf) layers. Chinese J Phys 63:231–239 2. Andrade Arvizu JA (2021) Band gap grading strategies for high efficiency kesterite based thin film solar cells 3. Gour KS, Karade V, Babar P, Park J, Lee DM, Singh VN, Kim JH (2021) Potential role of kesterites in development of earth-abundant elements-based next generation technology. Solar RRL 5(4):2000815 4. Grenet L, Emieux F, Choubrac L, M´arquez JA, De Vito E, Roux F, Unold T (2020) Surface preparation for 10% efficient cztse solar cells. Progr Photovoltaics: Res Appl 5. He M, Sun K, Suryawanshi MP, Li J, Hao X (2020) Interface engineering of pn heterojunction for kesterite photovoltaics: a progress review. J Energy Chem 6. Khattak YH, Baig F, Toura H, Ullah S, Mar´I B, Beg S, Ullah H (2018) Effect of cztse bsf and minority carrier life time on the efficiency enhancement of czts kesterite solar cell. Curr Appl Phys 18(6):633–641 7. Maklavani SE, Mohammadnejad S (2020) Reduction of interface recombination current for higher performance of p+-cztsxse (1–x)/p-czts/n-cds thin-film solar cells using kesterite intermediate layers. Sol Energy 204:489–500 8. Saha U, Alam MK (2019) A heterojunction bipolar transistor architecture-based solar cell using cbtsse/cds/acztse materials. Sol Energy 184:664–671 9. Silvaco I (2011) Atlas user’s manual. Santa Clara, CA, Ver 5 10. Sravani L, Routray S, Pradhan K (2020) Toward quantum efficiency enhancement of kesterite nanostructured absorber: a prospective of carrier quantization effect. Appl Phys Lett 117(13):133901 11. Wang D, Wu J, Liu X, Wu L, Ao J, Liu W, Sun Y, Zhang Y (2019) Formation of the front-gradient bandgap in the ag doped cztse thin films and solar cells. J Energy Chem 35:188–196 12. Yang S, Wang S, Liao H, Xu X, Tang Z, Li X, Wang T, Li X, Liu D (2019) The impact of different ag/(ag+ cu) ratios on the properties of (cu 1–x ag x) 2 znsns 4 thin films. J Mater Sci Mater Electron 30(12):11171–11180 13. Zandi S, Saxena P, Razaghi M, Gorji NE (2020) Simulation of cztsse thin-film solar cells in comsol: three-dimensional optical, electrical, and thermal models. IEEE J Photovoltaics 10(5):1503–1507

Design and Simulation of Si and Ge Double-Gate Tunnel Field-Effect Transistors with High-κ Al2 O3 Gate Dielectric: DC and RF Analysis Sambhu Prasad Malik, Ajeet Kumar Yadav, and Robin Khosla

Abstract Steep subthreshold slope and high current on–off ratio are among the major challenges of tunnel field-effect transistors (TFETs) for low-power complementary metal-oxide-semiconductor (CMOS) device applications. This work presents the performance comparison of Si and Ge double-gate tunnel field-effecttransistors (DGTFETs) based on DC and RF analysis. As compared to Si-based DGTFET, the Ge-based DGTFET depicts an improved performance such as high ION of ~8.61 × 10−5 A/μm, low I OFF of ~1.33 × 10−12 A/μm, I ON /I OFF ratio of ~6.4 × 107 , good sub-threshold swing of ~24.4 mV/dec, and better RF performance revealed from transconductance, parasitic capacitances, cut-off frequency, transit time, power delay product, and transconductance generation efficiency. Therefore, Ge-based TFET is a superior candidate for low-power CMOS device applications. Keywords Multigate · TFET · Subthreshold swing · RF performance

1 Introduction The continuous acceleration of power dissipation is the fundamental roadblock in the growth of the integrated circuit (IC) technology. The performance improvement of ICs due to scaling had maintained the integrity of Moore’s law since the past decades without compromising manufacturing cost [1, 2]. The metal-oxide-semiconductor field-effect transistors (MOSFET) feature size scaling in nanoscale regime results in different short-channel effects (SCEs) such as higher subthreshold swing (S), draininduced barrier lowering (DIBL), hot carrier effects, and so on [3]. S is defined as the amount of gate voltage (V GS ) needed to obtain drain current (I D ) variation of at least one decade. MOSFET is not suited for low-power applications due the fundamental limit of 60 mV/dec S at 300 K that restricts the supply voltage to ~1 V [4]. Numerous device concepts are proposed to obtain S < 60 mV/dec, such as impact-ionization S. P. Malik · A. K. Yadav · R. Khosla (B) Department of Electronics and Communications Engineering, National Institute of Technology (NIT) Silchar, Assam 788010, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_23

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FET (IFET) [5], negative capacitance FET (NCFET) [6], and tunnel FET (TFET) [7]. From the aforesaid, the TFET is a prominent candidate to achieve S below 60 mV/dec with the possibility of unidirectional current conduction and low-power operation with supply voltage < 0.5 V. The exceptional performance of TFET is due to its unique attribute of quantum mechanical band to band tunneling (BTBT) instead of thermionic emission [8]. However, the major challenge of TFET to be an alternative for state-of-the-art CMOS technology is low ON current, ambipolar current conduction, and poor performance of experimentally demonstrated TFET devices [9]. Further, the controllability of the transistor, i.e., I ON /I OFF ratio reduces for nanoscale regime devices. Materials engineering is expected as the solution for performance enhancement of TFET devices. Numerous semiconductor materials such as Si, Ge, SiGe, GeSn, InGaAs, and so on are investigated for TFET devices [3, 4, 10–13]. Further, the use of high-κ dielectric in the gate stack, pocket doping, asymmetric structure, and reduced drain doping have been suggested to suppress ambipolar current [7, 9]. Moreover, multigate structures are anticipated to increase the controllability over the channel for improving the on-current and hence the I ON /I OFF ratio [14]. Nevertheless, scarce experimental reports are available for TFET devices with comparable performance to state-of-the-art CMOS technology. Thus, the scientific community is driving significant efforts to rally the TFET devices performance using innovative device structures, materials and gate engineering. Boucart et al. [15] proposed a Si-based DGTFET structure with high-κ HfO2 dielectric, and Shoron et al. [16] investigated the temperature dependence of drain current in Si and GaAs-based DGTFET with high-κ Al2 O3 dielectric. Jiang et al. [17] studied the effect of direct source to drain tunneling in DGTFET structures with Si, Ge, and III-V (InAs, GaAs) as channel materials. However, limited literature is available on the DC ad RF analysis of Si and Ge-DGTFET [15, 18]. In this work, the DC and RF analysis of DGTFET with high-κ Al2 O3 is investigated with variation in channel materials (Si and Ge). Here, Ge is used as an alternative channel material in TFET devices due to its high mobility and low bandgap which is expected to produce high drive current at reduced supply voltage [11]. The performance of Ge TFET devices is compared with Si TFET devices. Additionally, high-κ Al2 O3 is used as gate dielectric due to its optimum material properties, such as moderate dielectric constant (κ ~ 9), wide bandgap (~8.7 eV), good thermal and kinetic stability, high-quality atomic layer deposition processing, minor defects, preferable for alternate semiconductor materials such as Ge, III-IV, and so on [19]. Besides, the double-gate TFET (DGTFET) structure is used as compared to planar TFET for better controllability of the channel and ease of analysis using two-dimensional (2-d) device simulations.

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2 Device Structure and Simulation Setup Figure 1 depicts DGTFET device structure with variation in semiconductor material Si (Fig. 1a) and Ge (Fig. 1b). The basic structure of TFET contains two contact regions (Source and drain), one intrinsic channel region covered by a dielectric material and gate contact. The device parameters of both the structures are presented in Table 1. Here, for n-type TFET, the channel is intrinsic; the source and drain regions are doped with p+ and n+ impurities, respectively. The mechanism of current conduction in TFET is administered by the BTBT and band alignments at the interfaces. However, high-doping profile source electrode, a narrow inter-band tunneling barrier amid the source-channel junction induced by the gate voltage are needed for high drive current or BTBT current [12]. The BTBT current depends upon tunneling probability T (E), related as [20]:

Fig. 1 Double-gate (DG) n-type TFET structure: (a) Si-based DGTFET, ( b) Ge-based DGTFET

Table 1 Device parameters of Si-based TFET [Structure 1] and Ge-based TFET [Structure 2]

Parameter

[Structure 1] [Structure 2] (cm−3 )

1 × 1020

1 × 1020

1×

1016

1 × 1016

Drain doping (N D ) (cm−3 )

1 × 1018

1 × 1018

Source length (L S ) (nm)

30

30

Channel length (L C ) (nm)

15

15

Drain length (L D ) (nm)

30

30

Body thickness (T Si /T Ge ) (nm)

10

10

Oxide (Al2 O3 ) thickness (T OX ) (nm)

2

2

Equivalent oxide thickness (EOT) (nm)

~1

~1

Gate work function (Φ m ) (eV)

4.12

4.12

Source doping (N A )

Channel doping (N C )

(cm−3 )

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S. P. Malik et al.

⎛

⎞ 3 √ ∗E 2 −4λ 2m g ⎠ T (E) = exp⎝ 3q h(E g + Δ φ)

(1)

where λ, E g , m*, Δφ, q, and è are the screening tunneling length, bandgap of semiconductor, effective carrier mass, energy range where tunneling occurs, charge of electron, and reduced Planck’s constant. The devices are simulated using Silvaco (Atlas) device simulator. The main challenges faced by Ge-based devices are device modeling and less accurate standardized parameters such as interface trap, bulk traps, impact ionization, tunneling, and different effective mass of carriers [21]. The physical model specifications and results are calibrated with data stated in [16]. The Shockley–Read–Hall (SRH), non-local BTBT, bandgap narrowing (BGN), Fermi–Dirac distribution (FDD), and Lombardi concentration–voltage–temperature (CVT) device physics models were used for both the structures. Here, SRH model estimates the generation and recombination of charge carriers; non-local BTBT model is enabled for estimation of planar devices tunneling charge carriers; BGN model is used for heavily doped region; FDD model is used to evaluate the degenerate material properties, and Lombardi CVT model envisages the mobility.

3 Results and Discussions 3.1 DC Performance Figure 2a indicates energy band diagram of both the structures at V GS = 0 V (OFF state). With no gate voltage (V GS = 0 V) is applied, the energy barrier is more at source-channel junction, with high screening length that leads to limited tunneling

Fig. 2 Energy band diagram of Si [Structure 1] and Ge-DGTFET [Structure 2], (a) “OFF” state (b) “ON” state

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Fig. 3 Transfer characteristics (I D vs. V GS ) of DGTFET for [Structure 1] and [Structure 2] (a) I D on linear scale (b) I D on log scale

and thus low off-state current. As V GS increases, the energy band diagram of the intrinsic part shifts down that leads to narrow tunnel barrier width as shown in Fig. 2b, and thus results in the high drive current (I ON ) in the “ON” state. Figure 3 shows the transfer characteristics of Si and Ge-DGTFET device structures. It is observed that the ION of [Structure 1] and [Structure 2] is ~4.69 × 10–6 A/μm and ~8.61 × 10–5 A/μm at V GS of 1 V, respectively. Thus, [Structure 2] has higher ON current than [Structure 1], while OFF current in [Structure 1] is ~6.85 × 10–14 A/μm and [Structure 2] is ~8.61 × 10–12 A/μm at V GS of 0 V. Hence, the I OFF of [Structure 2] is nearly two orders more than [Structure 1] due to the low bandgap of Ge that leads to higher T (E). Thus, the employment of Ge semiconductor material in DGTFET increases the ON current and correspondingly increases the OFF current due to high mobility, low bandgap, and low effective mass of Ge. Additionally, gate-induced drain leakage (GIDL) contributes significantly to leakage current. In general, GIDL occurs when there is band banding greater than bandgap (E g ) of the semiconductor, i.e., smaller bandgap material Ge [Structure 2] has more IOFF current than comparatively higher bandgap materials Si [Structure 1] [22]. However, the S is found to be ~22.68 mV/dec and ~24.4 mV/dec for [Structure 1] and [Structure 2], respectively, and there is trivial variation in the S value with variation of semiconductor material. Therefore, Ge-DGTFET is a potential candidate for logic applications due to its high I ON /I OFF ratio and low S of ~24.4 mV/dec. Table 2 summarizes the DC performance parameters of [Structure 1] and [Structure 2]. Table 2 DC performance of Si-based TFET [Structure 1] and Ge-based TFET [Structure 2]

DC parameter

[Structure 1]

[Structure 2]

I ON (A/μm)

4.69 × 10–6

8.61 × 10–5

I OFF (A/μm)

6.85 × 10–14

1.33 × 10–12

I ON /I OFF ratio

0.68 ×

0.64 × 108

S (mV/dec)

22.68

108

24.4

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Fig. 4 Output characteristics (I D vs. V DS ) showing delayed saturation effect (a) Si-based DGTFET [Structure 1] (b) Ge-based DGTFET [Structure 2]

The output characteristics (I D vs. V DS ) of the DGTFETs are depicted in Fig. 4 showing delayed saturation effect at low V DS . It is one of the unique properties of TFET compared to MOSFET counterparts. The lightly doped channel region in p++ i-n+ TFET is physically treated as a source-channel junction in series with a channel resistor. For drain voltage from 0 to ~0.1 V (Region I), the majority of the applied potential drop across the source-channel junction, which results in the narrow interband tunneling barrier for current conduction. Here, the output characteristics curve exhibits soft and broad transition before the current pinch off/saturation in Region II. For higher drain voltage (Region III), the majority parts of the applied potential drop across the included channel resistance; thus, current increases and plays an essential role for current saturation. Thus, degenerate source doping is required to mitigate the delayed saturation effect and better ID current. The PIN forward leakage current is an important parameter for TFET analysis as it poses a significant challenge for TFET-based circuit design. Figure 5 shows Fig. 5 Output characteristics (|I D | vs. V DS ) showing PIN forward leakage current of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2]

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the PIN forward leakage current in the output characteristics (|I D | vs. V DS ) of Sibased DGTFET [Structure 1] and Ge-based DGTFET [Structure 2]. In the |I D | − V DS characteristics, when V DS < 0 V, the electrons flow from drain to source due to drift (forward bias) rather than the band to band tunneling in the p-i-n structure that results in abrupt increase of current called the p-i-n forward leakage current which is barely controlled by the gate voltage. The drain current is ~67.4 and ~636 μA/μm at V DS of 0 V for Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2], respectively.

3.2 RF Performance Some of the RF analysis parameters, such as transconductance, cut-off frequency, parasitic capacitors, power delay product, and transit time, play a crucial role in analog circuit performance [13, 23]. Parasitic capacitances (Cgg , Cgd , and Cgs ) in a device determine stored charge in gate, drain, and source. These capacitances are responsible for circuit oscillations, signal delay, and power dissipation [23]. Figure 6 shows the capacitance versus gate voltage (V GS ) characteristics of SiDGTFET [Structure 1] and Ge-DGTFET [Structure 2] at constant V DS of 0.5 V. It is revealed that the capacitance C gs of both the structures decreases with an increase in gate voltage as a result of source to channel tunneling [24]. Cgd and Cgg of both the structures increase with higher gate voltage owing to the accumulation of charges at the gate-channel interface [25]. The overall gate capacitance (Cgg ) is related using Eq. (2) as: Cgg = Cgs + Cgd

Fig. 6 Capacitance versus gate voltage (V GS ) characteristics of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2] at V DS of 0.5 V

(2)

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Fig. 7 Transconductance versus V GS characteristics of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2] at V DS = 0.5 V

where Cgs and Cgd are the capacitance between gate source and gate drain, respectively. Further, the transconductance (gm ) represents the amplification capability of a device in an analog circuit, and related as: gm =

∂ ID ∂ VGS

(3)

From Eq. (3), it is evident that the device with higher I d offers a higher transconductance. Figure 7 shows the transconductance vs. V GS characteristics of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2] at V DS of 0.5 V. It is observed that [Structure 2] transconductance is greater than [Structure 1]. This benefit is due to the deployment of Ge material in the entire structure. In agreement to the DC analysis, it has been observed that the ON current of [Structure 1] is less than [Structure 2] which is an(apparent reason for decrease of transconductance. The ) transconductance efficiency ηg depicts the efficiency of a device for converting current or power into transconductance and related using Eq. (4), as follows: ηg =

gm ln(10) = ID S

(4)

where ηg for conventional MOSFETs is restricted to ~38.5 V−1 due to the limited S in accordance with Boltzmann’s tyranny. Here, ηg of Si-DGTFET and Ge-DGTFET is ~101.7 V−1 and ~95 V−1 , respectively. Therefore, ηg of Si-DGTFET and GeDGTFET is comparable. For better device analog performance, ηg should be high because higher ηg value enables the device to operate at low supply voltage. Furthermore, the cut-off frequency is an important parameter for RF analysis, which determines the highest amplified signal by the device, related as [24]:

Design and Simulation of Si and Ge Double-Gate Tunnel Field …

ft =

gm 2πCgg

223

(5)

The cut-off frequency depends on the transconductance (gm ) and overall gate capacitance (Cgg ). Figure 8 shows the cut-off frequency versus V GS characteristics of Si-DGTFET [Structure 1] and Ge-DGTFET [Structure 2] at V DS of 0.5 V. The cut-off frequency of Si-DGTFET is ~109 Hz, while for Ge-DGTFET is ~1010 Hz possibly due to high gm and low Cgg . Thus, the f T of Ge-DGTFET is one order more than Si-DGTFET that proves Ge-DGTFET to be superior than Si-DGTFET for device applications. Moreover, the transit time determines the speed of a device in a circuit, e.g., high-speed device has low transit time. Figure 9 presents the transit time versus V GS characteristics of Si-DGTFET [Structure 1] and Ge-DGTFET [Structure 2] at V DS of 0.5 V. The transit time of Structure 2 is 4.1 μs which is much less than ~67 μs for Fig. 8 Cut-off frequency versus V GS characteristics of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2] at V DS of 0.5 V

Fig. 9 Transit time versus V GS characteristics of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2] at V DS of 0.5 V

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Fig. 10 Power delay product (PDP) versus V GS characteristics of Si-based DGTFET [Structure 1] and Ge-based DGTFET [Structure 2] at V DS of 0.5 V

Structure 1 at 0 V. Mathematically, the transit time is related using Eq. (6). As transit time is inversely proportional to cut-off frequency, thus, higher cut-off frequency results in lower transit time and takes more time to perform a specific operation. τ=

1 2π f t

(6)

Finally, for low-power applications, power delay product (PDP) is a key parameter to benchmark the performance of a device. PDP gives a value about the amount of energy consumed by the device to perform a specific operation [26] and related as: 2 PDP = cgg × VDD

(7)

Here, V DD is applied drain voltage (0.5 V). Figure 10 shows PDP of both the structure at V DD of 0.5 V. The PDP of Structure 2 is ~1.4 × 10–16 which is reasonably smaller than PDP of Structure 1 of ~1.5 × 10–16 at 1 V. Thus, Ge-based DGTFET is exceptional candidate for low-power device applications.

4 Conclusion In summary, the performance comparison for the Si and Ge double-gate tunnel fieldeffect transistor (DGTFET) has been investigated using DC and RF analysis. As compared to Si-DGTFET, the Ge-DGTFET shows better ION current, sub-60 mV/dec subthreshold swing of ~24.4 mV/dec, I ON /I OFF ratio of ~108 . Furthermore, RF analysis of Ge-based DGTFET revealed higher transconductance (2.72 × 10–4 S/μm), high cut-off frequency (7.56 × 1010 Hz), comparable transconductance generation efficiency (~95 V−1 ), low overall capacitance (5.75 × 10–16 F), fast transit time

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(4.14 × 10–6 s), and trivial power delay product (1.43 × 10–16 ) as compared to SiDGTFET. Thus, Ge-based DGTFET is an excellent candidate for low-power device applications.

References 1. Moore GE (1998) Cramming more components onto integrated circuits. Proc IEEE 86(1):82– 85. https://doi.org/10.1109/JPROC.1998.658762 2. Khosla R, Sharma SK (2021) Integration of ferroelectric materials: an ultimate solution for next-generation computing and storage devices. ACS Appl Electron Mater 3(7):2862–2897. https://doi.org/10.1021/acsaelm.0c00851 3. Ionescu AM, Riel H (2011) Tunnel field-effect transistors as energy-efficient electronic switches. Nature 479(7373):329–337. doi: https://doi.org/10.1038/nature10679 4. Esseni D, Pala M, Palestri P, Alper C, Rollo T (2017) A review of selected topics in physics based modeling for tunnel field-effect transistors. Semicond Sci Technol 32(8). doi: https:// doi.org/10.1088/1361-6641/aa6fca 5. Abelein U et al (2007) Improved reliability by reduction of hot-electron damage in the vertical impact-ionization MOSFET (I-MOS). IEEE Electron Device Lett 28(1):65–67. https://doi.org/ 10.1109/LED.2006.887629 6. Salahuddin S, Datta S (2008) Use of negative capacitance to provide voltage amplification for low power nanoscale devices. Nano Lett 8(2):405–410. https://doi.org/10.1021/nl071804g 7. Bhuwalka KK, Schulze J, Eisele I (2005) A simulation approach to optimize the electrical parameters of a vertical tunnel FET. IEEE Trans Electron Devices 52(7):1541–1547. https:// doi.org/10.1109/TED.2005.850618 8. Zhang Q, Zhao W, Seabaugh A (2006) Low-subthreshold-swing tunnel transistors. IEEE Electron Device Lett 27(4):297–300. https://doi.org/10.1109/LED.2006.871855 9. Hraziia A, Vladimirescu AA, Anghel C (2012) An analysis on the ambipolar current in Si double-gate tunnel FETs. Solid State Electron 70:67–72. doi: https://doi.org/10.1016/j.sse. 2011.11.009 10. Choudhary S, Schwarz D, Funk HS, Khosla R, Sharma SK, Schulze J (2021) Impact of charge trapping on epitaxial p-Ge-on-p-Si and HfO2Based Al/HfO2/p-Ge-on-p-Si/Al structures using Kelvin Probe force microscopy and constant voltage stress. IEEE Trans Nanotechnol 20:346– 355. https://doi.org/10.1109/TNANO.2021.3069820 11. Convertino C, Zota CB, Schmid H, Ionescu AM, Moselund KE (2018) III-V heterostructure tunnel field-effect transistor. J Phys Condens Matter 30(26):aac5b4. doi: https://doi.org/10. 1088/1361-648X/aac5b4 12. Haehnel D, Fischer IA, Hornung A, Koellner AC, Schulze J (2015) Tuning the Ge(Sn) tunneling FET: influence of drain doping, short channel, and Sn content. IEEE Trans Electron Devices 62(1):36–43. https://doi.org/10.1109/TED.2014.2371065 13. Singh G, Amin SI, Anand S, Sarin RK (2016) Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation. Superlattices Microstruct 92:143–156. https://doi. org/10.1016/j.spmi.2016.02.027 14. Goswami PP, Khosla R, Bhowmick B (2019) RF analysis and temperature characterization of pocket doped L-shaped gate tunnel FET. Appl Phys A Mater Sci Process 125(10):1–12. https:// doi.org/10.1007/s00339-019-3032-8 15. Boucart K, Ionescu AM (2007) Double-gate tunnel FET with high-κ gate dielectric. IEEE Trans Electron Devices 54(7):1725–1733. https://doi.org/10.1109/TED.2007.899389 16. Shoron OF, Siddiqui SA, Zubair A, Member S, Khosru QDM (2010) A simple physically based model of temperature effect on drain current for nanoscale TFET. In: IEEE international conference of electron devices and solid-state circuits (EDSSC), pp 8–11, [Online]. Available: https://doi.org/10.1109/EDSSC.2010.5713783

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Performance Assessment of Electrostatically Doped Dual Pocket Vertical Tunnel Field-Effect Transistor Amit Bhattacharyya, Shaonli Paul, Papiya Debnath, Debashis De, and Manash Chanda

Abstract A recent doping-less (DL) charge plasma tunnel FET (TFET) structure has been suggested to diminish ambipolar features with improved analog/RF figure of merits (FoMs) Additionally, the DL arrangement gives fabrication ease and security against random dopant fluctuations (RDFs) on the contrary with the conventionaldoped TFET. Here, dual (front and back gate) n+ -pockets have been formed by inserting tunneling electrodes only close to source/channel junction. An assessment of the performances of proposed electrostatically doped dual pocket vertical TFET (ED-DP-V-TFET) configuration with conventional lateral and single-pocket TFET has been performed in terms of device characteristics. The proposed model suggests superior performance over its TFET contender. Besides, the suggested model is investigated for analog/RF FoMs with the variation of WF of tunneling electrode (TE) and oxide thickness (T ox ) under TE using ATLAS device simulation software. Simulated results confirm the efficacy of the proposed structure in the RF/analog domain. Keywords Ambipolarity · Charge plasma · Parasitic capacitance · Random dopant fluctuations (RDFs) · Analog/RF figure of merits (FoMs)

A. Bhattacharyya (B) Department of ECE, Haldia Institute of Technology, Haldia, India e-mail: [email protected] S. Paul · M. Chanda Department of ECE, Meghnad Saha Institute of Technology, Kolkata, India P. Debnath Department of BSH, Techno International New Town, Kolkata, India D. De Department of CSE, Maulana Abul Kalam Azad University of Technology, Kolkata, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_24

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1 Introduction Dimensions of the devices are diminished to nanometer scale [1] with newest enhancement in the field of MOS technology. Significant leakage current [2] and superior sub-threshold (V TH ) swing (almost greater than 60 mV/decade at T = 300 K) have been specified as rigorous issues for scaled designs. TFETs have realized major interests by prevailing these restraints. Due to band-to-band tunneling (BTBT) experience for conduction approach, TFET provides fewer sub-threshold swing (SS) and diminished off-state current (I OFF ) but lesser on-state current (ION ) [3]–4. Plethoras of TFET arrangements have been highlighted in literature to enhance I ON . Mainly, high k-gate dielectric materials [5], narrow band gap materials [6], double-gate TFET configuration [7], doping-less TFET (DLTFET) [8], n+-source pocket-based TFET [9] are the most significant ones. Recently, electrostatically doping (ED) takes potential for recognizing ultra steep interfaces and efficiently reconciling the random dopant fluctuation (RDF) results. RDF induces fluctuations in threshold voltage (V TH ) and I ON which are undesirable. In ED, the charge beneath both gates in the Si is mainly resolved by charge carriers, and the depletion charge may be avoided regardless of the doping concentration in the silicon film [10]–11. Hence, this perception of ED has been deliberated in TFETs [8]. In addition, DLTFET defeats the problems of RDF [3], and offers defend against parametric variation sensitivity [12]. Here, by inserting a tunneling electrode, dual (front and back gate) n + -pockets have been formed in lower and upper surface of the silicon substrate, nearly source/channel junction given in Fig. 1. Moreover, these dual n+-pocket arrangement in DLTFET structure can be realized exclusive of incorporating dopant diffusion and obtain enhanced ION [13]–15. Therefore, DPTFET outshines owing to the lateral and vertical tunneling phenomenon over lateral (L) [16] and single-pocket (SP) TFET [17] in terms of device characteristics.

2 Structural Descriptions with Simulation Approach A schematic cross-sectional outlook of the recommended configuration is shown in Fig. 1a. Design factors have been selected according to IRDS [18]. Here, TFET construction with double-gate structure is developed to merely achieve the fine-set up device-level simulation framework [16]. A platinum metal electrode of work function (fM ) = 5.92 eV (metal electrode of Hafnium, fM = 3.9 eV) is employed [19]–20 to obtain P+ category (N + category) charge plasma near the source-end (drain end) region. Furthermore, silicon substrate thickness (T si ) < length of Debye, i.e., ((εS V T )/(qηi ))1/2 , where εS , ηi , and V T signify permittivity, electron concentration of Si body, and the thermal voltage, correspondingly [8]. Hence, T si = 10 nm is assumed by following the literature [7, 8, 11–13]. Also, the quantum mechanical effect is not included for the ease of calculation [21] and consideration of 10 nm of T si . The design aspects of ED-DP-V-TFET as demonstrated in Fig. 1 are, length of gate region (L Gate

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Fig. 1 a Cross-sectioned outlook of proposed ED-DP-V-TFET configuration. b Proposed model calibration (I DS − V GS curves) with reported records in [8]

= L G1 + L G2 ) = 50 nm, extent of source/drain region (L S /L D ) = 100 nm, length of tunneling electrode (L TE ) = 9 nm, tunneling electrode’s work function (fTE ) = 3.9 eV, carrier concentration of Si (ηi ) = 1015 /cm3 , spacer length for gate/source (L Gap,S ) of 3 nm, spacer length for gate-drain region (L Gap,D ) = 15 nm, useful in favor of lesser ambipolar current [8]. The thickness of SiO2 as oxide layer (T ox ) is dissimilar in various sections. So, as to avoid the possibility of silicide growth, a layer of SiO2 of T oxS = 0.5 nm (T oxD = 3 nm) is sandwiched among body surface and source (drain) side metal electrode on both top and bottom sides of the silicon substrate. Moreover, this SiO2 layer evades gate/channel leakage also [8]. Tox under dual metal gate, i.e., T oxG = 3 nm. In the proposed model, the thickness of TE (T TE ) exceeds over the thickness of the dual metal gate (T M1 , T M2 ) on dual sides of the substrate to enhance the gate modulation and consequently tunneling current [15], and hence, T ox under TE is assumed to be too slim and has a thickness akin to T oxS . Silvaco ATLAS device simulator, V5.19.20 [21], has been used to carry out device simulation. A non-local BTBT representation is favored which can exercise creation rate near tunneling intersection. Furthermore, field and concentrationdependent mobility, i.e., FLDMOB and CONMOB, Shockley–Read–Hall (SRH) recombination-generation representation, drift-diffusion, the Fermi–Dirac carrier distribution, Lombardi (CVT) model, are considered throughout the simulation. To authenticate and normalize these representations and schemes, simulation outcomes are standardized next to Kumar et al. [8] work before inserting the metal electrode

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Fig. 2 Possible fabrication flow for the proposed ED-DP-V-TFET architecture

into the proposed structure, and the same are displayed as in Fig. 1b. Here, at V DS = 0.7 V and V GS = 1.2 V, I ON of [8] attains almost 2.54 × 10−6 A/μm, while that of proposed work attains at 1.59 × 10−6 A/μm. Hence, a good agreement between the consequences of the two works at V DS = 0.7 V, as can be evidenced from Fig. 1b, declares the accuracy of the model calibrations. A possible fabrication scheme for the ED-DP-V-TFET is demonstrated in Fig. 2. While inserting a tunneling electrode, dual (front and back gate) n+-pockets have been formed. Line as well as point tunneling may be recognized by a pocket (n+) TFET, while the pocket has doping category somewhat dissimilar to that of source region [22]. In general, vertical TFET, showing tunneling in the direction of two paths, i.e., point tunneling (lateral) and line tunneling (vertical) [22], has been proposed as probable option to lateral TFETs [16]. This configuration assists an enhancement in ON-current (I ON ), low SS, and high ON-to-OFF current ratio (I ON /I OFF ) as evaluated to traditional TFET that is exclusively supported on L-tunneling. Thus, here, we obtain the benefit of vertical and lateral tunneling, and hence, the proposed configuration is termed as vertical TFET. Here, L Gap,S is significant for better tunneling probability and higher I ON . Table 1 exhibits the change of I ON through L Gap,S in favor of the projected structure. Hence, I ON has decreased since L Gap,S is increased commencing 3–9 nm. So, to obtain optimal I ON , 3 nm of L Gap,S is preferred all through the simulation work. Here, Table 1 shows low ION value for L Gap,S variation. Owing to the degree of lattice matching with InP

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Table 1 L GapS versus I ON

Fig. 3 Model validation in terms of electron concentration among L-TFET [16], SP-TFET [17], and proposed ED-DP-V-TFET configuration at V DS = 0.7 V, V GS = 1.2 V. Inset picture shows the existence of hump structure in the proposed model

substrate, GaAs0.5 Sb0.5 /In0.53 Ga0.47 As compound semiconductor can be a promising hetero-material [19, 22], to improve ION via reducing the height and width of the barrier. The proposed model has been validated in terms of electron concentration plot under ON-state situation (V DS = 0.7 V, V GS = 1.2 V) by evaluating it with that of rest existing structures akin to L-TFET [16], SP-TFET [17], respectively, as depicted in Fig. 3. A hump structure in the inset picture depicts virtual pocket formation along L TE = 9 nm in the proposed ED-DP-V-TFET model. Here, an improvement of 0.89% is achieved in electron concentration.

3 Results and Discussions 3.1 Evaluation of Short-Channel Effects (SCE) Parameters Here, Table 2 summarizes the comparative analysis of SCE parameters for variations of permittivity (k) of oxide layer like SiO2 (k = 3.9), Al2 O3 (k = 10), HfO2 (k = 22), La2 O3 (k = 30), and TiO2 (k = 80) [23]. It has been observed that an enhanced I ON

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Table 2 Impact of variations of k Oxide layer

SS (mV/decade)

I ON (A/μm)

V DS = 0.7 V

V DS = 0.7 V (μA)

V DS = 0.15 V

DIBL (mV/V) V DS = 0.15 V (μA)

k = 3.9

70.55

78.73

19.9

0.687

72.48

k = 10

66.07

69.55

39

1.3

68.75

k = 22

60.25

62.85

110

2.64

57.74

k = 30

55.23

60.61

210

6.55

42.53

k = 80

48.27

53.82

531

18.4

31.25

for both V DS = 0.7 and 0.15 V is obtained, while k increases. So, SS for both V DS and lower DIBL has been observed. Also, threshold voltage (V TH ) reduces accordingly. Low SS signifies enhanced gate controlling over the channel section. Outcomes have been detailed in Fig. 4a. In general, n-TFET illustrates usual transistor performance with elevated ONcurrent for positive V DS . While the TFET functions near the ambipolar area, the turn-off capability of the configuration is influenced, providing the reduced circuit constancy [24]. Though not shown here, it has been observed that while V DS < 0’,

Fig. 4 Variations of a transfer characteristics b gm and TGF c AV d V EA with V GS for different k of oxide layer

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i.e., negative potential, V GS mislays control over I DS of the configuration, and TFET shows considerable leakage current (PIN-forward leakage) with this negative V DS [24]. This leakage badly effects the power utilization and consistency of TFET digital performances. Thus, PIN-forward leakage features are required in proposing circuits to improve hardware protection. Consequently, the benefits of the TFET may merely be carried into action, while it efforts in the tunneling zone and evades functioning in rest sections. At less V DS , the potential along the channel is pinned with the huge inversion charge carriers. Conversely, for sufficiently high V DS , the charge carrier depletion outcomes in elevated channel impedence, and V DS can not enter through the tunneling intersection, thus reasoning output saturation current. This occurrence is considered as delayed saturation effect evaluated through the traditional MOSFET [24]. Owing to this effect of the TFET, the slope of voltage transfer characteristics of the inverter supported on the TFET will get diminished [24].

3.2 Analog Performance Analysis The analog performances of our proposed model can be illustrated by the subsequent FoMs akin to transconductance (gm ), device efficiency, or transconductane generation factor, TGF (gm /I DS ), intrinsic gain Av (gm *RO ), and early voltage (V EA ), respectively, where RO denotes output resistance of the device.

3.3 Impact for Variation of k of Oxide Layer In this section, the variation of I DS with k of the gate oxide layer at V DS = 0.7 V has been detailed. For aluminum (Al) as TE, low value of BTBT on-set voltage (V ON ) and large values of I ON have been observed. I DS improves when k of oxide layer increases from 3.9 to 80 as shown in Fig. 4a. TiO2 (k = 80) shows maximum I ON and I OFF among the other preferred gate oxide layers, while SiO2 (k = 3.9) reveals the minimum I ON and I OFF . When k of gate oxide layer increases, gate oxide capacitance (C ox ) also increases and results higher potential drop fSi inside the intrinsic semiconductor [25] as expressed by, ( / )−1 ϕSi = (VGS − Vfb ) 1 + CSi Cox

(1)

where C Si = ∈ Si /T si , C ox = ∈ ox /T ox , V GS , and V fb denote intrinsic semiconductor capacitance, gate oxide capacitance, applied gate potential, and flat band potential, respectively.

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Transconductances (gm = ∂I DS /∂V GS ) have a major effect upon Av . With TiO2 , gm,max is 1.19 × 102 % more than SiO2 at V GS = 0.9 V, given in Fig. 4b. At higher V GS , gm falls for all oxide layers. In reality, gm is characterized by the proficient gate modulation by TE and the narrow tunneling width [26]. Moreover, advanced gm is enviable for analog presentations as it illustrates better carrier transfer efficacy. Here, Fig. 4b–d show the deviations of device efficiency (gm /I DS ), Intrinsic Gain (AV = gm *RO ) and Early voltage (V EA = I DS /gds ) with respect to V GS correspondingly. The Device Efficiency or TGF (gm /I DS ) depicts how expertly I DS is utilized to recognize a specific importance of gm . Hence, for SiO2 , TGFmax turns into 61% more compared to TiO2 at V GS = 0.1 V as shown in Fig. 4b. As k of oxide layer enhances, I DS increases and gds rises ensuing reduction in output resistance (Ro ). Iinitially, AV increases with the rise in gm , however, for higher V GS as gm falls, AV also falls. Besides, for higher k value, gds rises and RO falls that reduces AV , given in Fig. 4c. With SiO2 AV,max becomes 1.34 × 102 % better than TiO2 at V GS = 0.1 V as given in Fig. 4c. Figure 4d shows 50% improvement in V EA,max for SiO2 over TiO2 at V GS = 0.4 V.

3.4 RF Performance Analysis Here, the RF performances of the recommended structure have been detailed as to FoM parameters like gate-to-drain capacitance (C gd ), gate-to-source capacitance (C gs ), unity gain cut-off frequency (f τ ), transconductance-frequency product (gm f τ /I DS ) and gain-bandwidth product (GBWP).

3.5 Impact for Variation of k of Oxide Layer Lesser parasitic capacitance offers an improved gate-controlled channel section to develop RF presentations. Alteration of C gd as well as C gs by V DS = 0.7 V in favor of different oxide layers is specified in Fig. 5a. Every one of the capacitances can be obtained from small-signal AC investigation at 1 MHz. Figure 5a illustrates that together C gs as well as C gd attain inferior (superior) merit in the sub-V TH (superV TH ) section as rising V GS will generate extra fringing contours throughout oxides. Furthermore, beyond the total capacitance C gg (= C gs + C gd ), C gd directs in favor of every k as V GS attains to 0.95 V. As V GS is lesser than 0.95 V, C gs governs. However, the net gate capacitance (C gg ) enhances with the rise of k, given in Fig. 5a. The f τ (= gm /2π (C gs + C gd )) relies on gm as well as C gg robustly. For lesser (superior) V gs as gm enhances (reduces) and C gg diminishes (enhances). So, f τ enhances (reduces) for V gs < 0.95 V (> 0.95 V). SiO2 achieves 37.5% more f τ,max than TiO2 given in Fig. 5b. TFP (= gm f τ /I ds ) diminishes with enhanced k value of oxide layer and becomes maximum at lower V gs . 50.62% reduction in TFPmax is observed in Fig. 5c when k increases from 3.9 to 80. In fact, TFP performs an important role in high frequency function of operational amplifier. Figure 5d illustrates the deviation of GBWP (=

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Fig. 5 Deviations of a C gs and C gd b f τ c TFP d GBWP with V GS for different k of oxide layer

gm /20π C gd ) of proposed model with V GS at V DS = 0.7 V. This is examined that GBWP realizes its utmost enrichment of 88.4% for k = 80 over k = 3.9.

4 Performance Assessment Between L-TFET, SP-TFET, and Proposed Model Hence, the performances among L-TFET [16], SP-TFET [17], and proposed model have been compared. Tables 3 and 4 highlight a comparison on device characteristics including bottom of conduction band energy (E CB,Bottom ) and maximum electron concentration (N e,max ) under ON-state condition (V DS = 0.7 V, V GS = 1.2 V), I ON,max for output characteristics and maximum tunneling rate (PT,max ) among all the structures. All the horizontal contours are established at a depth of 1 nm from the oxide-semiconductor interface. Tables 6 and 7 illustrate the performance assessment on maximum value of analog/RF FoMs akin to gm , TGF, AV , V EA , C gs , C gd , f τ , TFP, and GBWP. The proposed model suggests superior performance over its TFET contender, and consequently, simulated results confirm the efficacy of the proposed structure in RF/analog domain.

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Table 3 Assessment of analog performances Parameters

V GS = 1.2 V, V DS = 0.7 V, FM1 = 3.9 eV, FM2 = 4.5 eV [16]

[17]

Value

ΔQ (%)

Value

gm,max (mS)

0.326

0

0.615

TGFmax (/V)

78.2

0

64.1

AV,max

112

0

220

V EA,max (V)

40.17

0

33.62

Proposed ΔQ (%)

Value

ΔQ (%)

88.95

0.917

181.2

−18.03

69.1

96.42

305

172.3

27.02

−32.7

−16.3

23.78

ΔQ (%) denotes % of improvement which is measured with respect to Kanungo et al. [16]

Table 4 Assessment of RF performances Parameters

V GS = 1.2 V, V DS = 0.7 V, FM1 = 3.9 eV, FM2 = 4.5 eV, AC freq. = 1 MHz [16] Value

[17] ΔQ (%)

Value

Proposed ΔQ (%)

value

ΔQ (%)

C gs,max (fF/μm)

0.54

0

0.45

−16.6

0.31

−42.6

C gd,max (fF/μm)

1.41

0

1.15

−18.43

0.89

−36.9

f τ,max (GHz)

26.6

0

61.3

130.2

121.7

357

TFPmax (GHz/V)

3780

0

4740

25.4

5570

47.35

GBWPmax (GHz)

3.68

0

8.52

131.5

16.40

345.6

ΔQ (%) denotes % of improvement which is measured with respect to Kanungo et al. [16]

5 Conclusion The proposed structure affords fabrication ease and protection against RDFs in contrast with the conventional doped TFET. In this work, an electrostatically doped dual pocket vertical TFET (ED-DP-V-TFET) structure has been formed, and its analog/RF performance is examined for different permittivity (k) of oxide layer. Easy fabrication and almost zero RDF make it attractive TFET. The I ON enhances with (i) increase in k, (ii) decrease in WF of TE, and (iii) reduction of T ox under TE. As I ON enhances, gm and gds increase, and they have significant impact on TGF, Ro , AV , and V EA while varying with respect to V GS . Extreme improvement of 1.19 × 102 %, 61%, 1.34 × 102 %, and 50% can be achieved in gm,max , TGFmax , AV,max , and V EA,max , respectively. Moreover, increase in I ON enhances C gs and C gd which can contribute significant impact on f τ , TFP, and GBPW while changing relating to V GS . Hence, 37.5, 75.7, and 95.74% utmost enhancement can be accomplished in f τ,max , TFPmax , and GBWPmax , correspondingly. To validate the efficiency of EDDP-V-TFET, relative comparisons have been executed through the lateral (L) and

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SP-TFET regarding device characteristics, analog/RF FoMs. The proposed ED-DPV-TFET outshines owing to incidence of point as well as line tunneling occurrence and moreover due to DP constructions.

References 1. Xie Q, Xu J, Taur Y (2012) Review and critique of analytic models of MOSFET short-channel effects in subthreshold. IEEE Trans Electron Devices 5(6):1569–1579. doi: https://doi.org/10. 1109/TED.2012.2191556 2. Bangsaruntip S, Cohen GM, Majumdar A, Sleight JW (2010) Universality of short-channel effects in undoped-body silicon nanowire MOSFETs. IEEE Electron Device Lett 31(9):903– 905. https://doi.org/10.1109/LED.2010.2052231 3. Colinge JP (2008) FinFETs and other multi-gate transistors. Springer, New York, NY, USA, pp 2–4 4. Damrongplasit N, Kim SH, Liu T-JK (2013) Study of random dopant fluctuation induced variability in the raised-ge-source TFET. IEEE Electron Device Lett 34(2):184–186. https:// doi.org/10.1109/LED.2012.2235404 5. Tirkey S, Sharma D, Raad BR, Yadav DS (2018) A novel approach to improve the performance of charge plasma tunnel field-effect transistor. IEEE Tlectron Devices 65(1):282–289. https:// doi.org/10.1109/TED.2017.2766262 6. Patel J, Sharma D, Yada S, Lemtur A, Suman P (2019) Performance improvement of nano wire TFET by hetero-dielectric and heteromaterial: at device and circuit level. Microelectron J 85:72–82. https://doi.org/10.1016/j.mejo.2019.02.004 7. Kumar N, Raman A (2019) Design and investigation of charge-plasma based work function engineered dual-metal heterogeneous gate Si-Si0.55Ge0.45 GAA-cylindrical NWTFET for ambipolar analysis. IEEE Trans Electron Devices 66(3):1468–1474. https://doi.org/10.1109/ TED.2019.2893224 8. Singh KS, Kumar S, Nigam K (2020) Impact of interface trap charges on analog/RF and linearity performances of dual-material gate-oxidestack double-gate TFET. IEEE Trans Device Mater Rel 20(2):404–412. https://doi.org/10.1109/TDMR.2020.2984669 9. Kumar MJ, Janardhanan S (2013) Doping-less tunnel field effect transistor: design and investigation. IEEE Trans Electron Devices 60(10):3285–3290. https://doi.org/10.1109/TED.2013. 2276888 10. Chang H-Y, Adams B, Chien P-Y, Li J, Woo JCS (2013) Improved subthreshold and output characteristics of source-pocket Si tunnel FET by the application of laser annealing. IEEE Trans Electron Devices 60(1):92–96. https://doi.org/10.1109/TED.2012.2228006 11. Gupta G, Rajasekharan B, Hueting RJE (2017) Electrostatic doping in semiconductor devices. IEEE Trans Electron Devices 64(8):3044–3055. https://doi.org/10.1109/TED.2017.2712761 12. Bashir F, Alharbi AG, Loan SA (2018) Electrostatically doped DSL Schottky barrier MOSFET on SOI for low power applications. IEEE J Electron Devices Soc 6:19–25. https://doi.org/10. 1109/JEDS.2017.2762902 13. Sahu C, Singh J (2015) Potential benefits and sensitivity analysis of dopingless transistor for low power applications. IEEE Trans Electron Devices 62(3):729–735. https://doi.org/10.1109/ TED.2015.2389900 14. Ram MS, Abdi DB (2015) Dopingless PNPN tunnel FET with improved performance: design and analysis. Superlattices Microstruct 82:430–437. https://doi.org/10.1016/j.spmi. 2015.02.024 15. Abbassi SA, Bashir F, Loan SA, Alamoud ARM, Nizamuddin M, Rafat M (2016) Hetero gate material and dual oxide dopingless tunnel FET. In: Proceedings of the IMECS, Hong Kong, pp 1–3

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16. Bashir F, Loan SA, Rafat M, Alamoud ARM, Abbasi SA (2015) A high performance gate engineered charge plasma based tunnel field effect transistor. J Comput Electron 14(2):477–485. https://doi.org/10.1007/s10825-015-0665-5 17. Kanungo S, Chattopadhyay S, Gupta PS, Rahaman H (2015) Comparative performance analysis of the dielectrically modulated full-gate and short-gate tunnel FET-based biosensors. IEEE Trans Electron Devices 62(3):994–1001. https://doi.org/10.1109/TED.2015.2390774 18. Verma M, Tirkey S, Yadav S, Sharma D, Yadav DS (2017) Performance assessment of a novel vertical dielectrically modulated TFET-based biosensor. IEEE Trans Electron Devices 64(9):3841–3848. https://doi.org/10.11109/TED.2017.2732820 19. Hoefflinger B (2020) IRDS-international roadmap for devices and systems, rebooting computing, S3S. In: Murmann B, Hoefflinger B (Eds) NANO-CHIPS 2030, the frontiers collection. Springer, Cham. doi: https://doi.org/10.1007/978-3-030-18338-7_2 20. Bhattacharyya A, Chanda M, De D (2020) GaAs0.5 Sb0.5 /In0. 53 Ga0. 47 As heterojunction dopingless charge plasma-based tunnel FET for analog/digital performance improvement. Superlattices Microstruct 142:106522. https://doi.org/10.1016/j.spmi.2020.106522 21. Raad BR, Sharma D, Kondekar P, Nigam K, Yadav DS (2016) Drain work function engineered doping-less charge plasma TFET for ambipolar suppression and RF performance improvement: a proposal, design, and investigation. IEEE Trans Electron Devices 63(10):3950–3957. https:// doi.org/10.1109/TED.2016.2600621 22. ATLAS Device Simulation Software (2016) Silvaco Int., Santa Clara, CA, USA 23. Bhattacharyya A, Chanda M, De D (2019) Performance assessment of new dual-pocket vertical heterostructure tunnel FET-based biosensor considering steric hindrance issue. IEEE Trans Electron Devices 66(9):3988–3993. https://doi.org/10.1109/TED.2019.2928850 24. Lide DR (2008) CRC handbook on chemistry and physics 89th edn. Taylor & Francis, London, pp 12–114 25. Lin Z, Chen P, et al. (2020) Challenges and solutions of the TFET circuit design. IEEE Trans Circ Syst I Reg Pap 1–14 26. Gupta PS, Rhaman H, Kanungo S, Dasgupta PS (2012) Analysis and study of different parameters affecting the I–V characteristics of tunnel-FET transistor. In: Proceedings of the IEEE international conference devices, circuits systems, pp 89–93 27. Duan X, Zhang J, Wang S, Li Y, Xu S, Hao Y (2018) A high-performance gate engineered InGaN dopingless tunnel FET. IEEE Trans Electron Devices 65(3):1223–1229. https://doi.org/ 10.1109/TED.2018.2796848

A High Efficiency Class AB AlGaN/GaN HEMT Power Amplifier for High Frequency Applications Madhukar Saini and Trupti Ranjan Lenka

Abstract GaN HEMT is chosen for many high frequency applications such as Power Amplifiers because of its desirable properties. Most semiconductors fail at high frequency applications because of their thermal and bias limitations. It is very difficult to operate the amplifier at high frequency and high power ratings. The HEMT transistors can operate at high electric fields and high frequencies. The heterojunction structure provides more no of free electrons without any doping which significantly improves the mobility and the current. The hetero-structure also blocks the current flow in unwanted directions. This paper explains about GaN HEMT transistor and its practical application as a Power Amplifier. CREE CGH40010F GaN (10 W) device is chosen and developed at the schematic level. The schematic provides 15.5 dB gain and 66% efficiency. Keywords GaN HEMT · Heterojunction · Power amplifier

1 Introduction In microwave frequency applications, Vacuum Electronic Devices (VED) like Traveling Wave Tube and Klystron modulator but they are heavy and bulky. In comparison, solid-state devices have advantages like (i) Low maintenance. (ii) Instantaneous operation. (iii) Cheaper and less bulky [1]. When it comes to solid-state devices, devices that are made by silicon were used very widely. But there are some limitations that make them unsuitable for Microwave, such as 5G applications [2]. (i) Reduced electron velocity in the semiconductor produces reduced current. (ii) Thermal limitations of the semiconductor. (iii) Bias limitations. (iv) Achieving the required frequency at high power ratings is difficult. M. Saini (B) · T. R. Lenka Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Assam, India e-mail: [email protected] T. R. Lenka e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_25

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Table 1 Comparison of parameters in different materials Material

E g (eV)

εr

K (W/o K-cm)

E c (V/m)

Si

1.12

11.9

1.5

3 × 105

SiC

2.86

10.0

4

3.8 × 106

GaN

3.4

9.5

1.3

2 × 106

Diamond

5.6

5.5

20–30

5 × 106

To increase the current, we need to increase the cross-sectional area, which leads to an increase in capacitance. Thus, the speed of the device reduces. High capacitance and low impedance reduce the operating frequency [3]. We are not using silicon made devices in high frequency applications because of the above reasons. The material should withstand the conditions and have some desirable properties to use solid-state devices in microwave applications. That is the reason why we are going to use GaN made HEMT structures in High frequency power amplifiers [3].

2 Desirable Properties of GaN Before GaN HEMT, many structures were proposed, such as MESFET, AlGaAs/GaAs HEMT, to increase mobility and to operate at high frequencies. But later, GaN material came into the discussion, which has many advantages over GaAs/AlGaAs, such as (i) high breakdown field. (ii) Large energy gap. (iii) Low dielectric constant. (iv) Thermal conductivity can be achieved by using SiC as substrate [3] (Table 1).

2.1 High Saturation Velocity The disadvantage of other materials compared to the GaN is they saturate at high electric fields, which means we cannot increase the mobility at the higher electric field. But we can do that in GaN materials. There is no further increase in the velocity after a specified electric field, generally at high electric fields. For GaN, Generally in the order of 100 kV/cm (Fig. 1).

3 HEMT Structure and Its Working The High Electron Mobility Transistor (HEMT) is designed on the principle of the Heterojunction, which gives us a large number of free carriers without any

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Fig. 1 Velocity comparison of different materials

doping. Because of this hetero-structure, there are fewer ionized scatterings, and it significantly improves mobility.

3.1 Hetero-Structure When two semiconductors of different bandgaps are attached, a junction called heterojunction forms. The formation itself provides free electrons without any doping.

3.2 2-Dimensional Electron Gas (2DEG) The triangular well shown in Fig. 2 is the lowest energy state, it fills with the electrons, and there is no way to move the electrons in the z-direction. The direction through the z-direction is quantized, as shown in Fig. 2. This gives us the advantage of an electron moving in the desired direction. As current through the one direction is quantized, it is named as 2-dimensional electron gas.

3.3 Working Principle In GaN HEMT, the large energy bandgap AlGaN is grown upon a smaller bandgap GaN material to form a heterojunction [4]. Here in the HEMT structure, the free electrons do not face any ions because of less doping which significantly improves mobility. The cross-sectional view of the GaN HEMT is shown in Fig. 3 [5]. As discussed in 2DEG, the low energy state triangular well fills with the electrons. Those electrons do not have any path to travel across the cross-section, which gives us the advantage of moving the electron in the desired direction. The gate voltage controls the electron flow in 2DEG. Here the Schottky junction is formed between

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Fig. 2 Formation of hetero-structure and 2DEG

Fig. 3 Cross-sectional view of GaN HEMT

the metal gate and GaN semiconductor. By applying the gate voltage varying the diode barrier, which controls the flow of electrons in the 2DEG channel [6].

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4 HEMT as Power Amplifier The power amplifier is an electronic device that boosts the input power level to drive the loads, such as speakers and RF transmitters. The signal must have high power levels to travel over long distances in radio frequency transmission. Power amplifiers are classified based on the location of Q—point. Ex. Class—A, Class—B, Class—C and Class—AB, etc. When designing a high frequency power amplifier, parameters like efficiency, power dissipation, and harmonic distortion have to be considered. The power efficiency is nothing but how much of our DC input power is converted into RF output power [2]. η=

Pout Ptotal

(1)

The device’s power dissipation has to be less because high power dissipation makes the device hot, affecting other semiconductor chips on the board. When designing a power amplifier, certain things like stability, gain, and impedance matching should be considered [7]. There are some stability calculation methods like stability circles, K factor and μ factor, in which μ factor is the most commonly used one. The equation of μ-factor given in Eq. (2) and it has to be greater than at our given frequency. 1 − |S11 |2 | μ= | >1 | S22 − ΔS ∗ | + |S12 S21 |

(2)

Δ = S11 S22 − S12 S21

(3)

11

Transducer power gain of the amplifier G T = PPavsL . It is nothing but the ratio of the power delivered to the load to the power available from the source [1]. GT =

( )( ) |S21 |2 1 − |⎡S |2 1 − |⎡L |2 PL = Pavs |1 − ⎡S ⎡in |2 |1 − S22 ⎡L |2

(4)

Maximum gain can be achieved when ⎡in = ⎡s∗ and ⎡out = ⎡L∗ [1]. To get the load values for the impedance matching, we will do the load pull analysis. Load pull analysis is nothing but choosing an optimum load at which the device can deliver more power as well as efficiency. The efficiency is often very low at maximum getable power, and the gain is significantly less at maximum getable efficiency. A designer has to decide the load based on the requirement. Load pull analysis significantly improves the power amplifiers’ gain and efficiency, which reduces the reflections and losses due to the RF signal. It is suggested that the optimum load that we are choosing should be near to the 50 Ω real point on the smith chart so that the matching network requires a smaller number of RF traces.

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For the reduced power losses and reflections, impedance matching should be done. Impedance matching is one of the essential parts of a power amplifier design. As we operate the device at high frequencies, lumped elements cannot perform as they are supposed to. This is where the transmission lines comes into the picture. In a lossless transmission line, the input impedance is given by ⎡ Z in (l) = Z 0

Z L + j Z 0 tan βl Z o + j Z L tan βl

⎤ (5)

Z L and Z o are load impedance and characteristic impedance, respectively.

5 Design and Simulation Results In this paper, we chose CREE CGH40010F as our power amplifier. The selected device is operated at 2.4 GHz, and its biasing is done at V GS = −2.7 V and V DS = 28 V. This is biased to operate in the Class AB mode [8]. The device is unstable at the operating frequency when stability and gain analysis is done on the raw transistor (μ = 0.725). It is observed that the stability modifications show a negative impact on the gain of the raw transistor. It is suggested to the designers to take care of the gain while doing stability modifications. The designed schematic maintains stability over high frequencies (from 1 GHz) (Fig. 4). Load pull analysis has been done, and the power device is giving desirable gain and efficiency at the load value 19.15 + j11.95 (Fig. 5). Before doing the load pull analysis, for the input power (Pavs ) of 28 dBm, the transistor provides a fundamental output power of 37.522 dBm and a drain efficiency of 37.26%. Load pull analysis was performed for the Pavs of 28 dBm. The load we choose produces 40.577 dBm fundamental output power and 66.09% drain efficiency. It is

Fig. 4 μ-factor and gain (after stability modifications)

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245

Fig. 5 a Load pull contours, b power distribution over the harmonics, and c P1 dB compression point

Table 2 Improvement in Pout and drain efficiency after load pull

Stage

Pin (Pavs ) (dBm)

Pout (dBm)

Drain efficiency (%)

Before load pull

28

37.522

37.26

40.58

66.09

After load pull 28

observed that at the P1 dB compression point, the output power is shifted from 32.96 dBm to 37.135 dBm. The complete load pull data is given in Tables 2 and 3. It is observed that the load we chose gives desirable results. The impedance matching has been done to the 50 Ω termination on both sides for the chosen impedances. After doing the impedance matching, the simulated results passed our requirements. Essential parameters like gain and power distribution over the harmonics have shown below in Figs. 6 and 7. The schematic level design of the selected device gives the desired results.

6 Conclusion This paper explains the importance and working of GaN HEMT transistor in high frequency applications. The CREE CGH 40010F (GaN HEMT) transistor is selected and biased in such a way that it will operate in Class AB mode. It is producing 40.461 dBm output power for the input of 28 dBm. The schematic provides 15.5 dB gain and 63% PAE efficiency (66% Drain efficiency). The layout design and EM simulation have to be performed. With this design the achieved results are significantly more compared to the results given in the datasheet of the chosen transistor. Complete simulations are performed in Advanced Design System (ADS). It is observed that the developed schematic meets our requirements. There is still some scope to improve the efficiency without affecting the gain.

P1dB power (dBm)

32.962

36.136

37.135

Source and load impedance (Ω)

Z s = 50, Z L = 50

Z s = 50, Z L 19.15 + j11.95

Z s = 3.19 − j4.7, Z L = 19.15 + j11.95

Table 3 Load pull data

22.5

25

22.5

Pin at p1dB (dBm)

15.72

12.135

11.442

Maximum gain

11.815

9.362

0.118

Efficiency at maximum gain (%)

28.22

27.635

8.442

Pout at maximum gain (dBm)

12.5

15.5

-3

Pin at maximum gain (dBm)

65.851

65.819

47.448

Efficiency at maximum PAE (%)

10.754

7.061

6.32

Gain at maximum efficiency

41.254

41.061

40.32

Pout at maximum efficiency (dBm)

30.5

34

34

Pin at maximum efficiency (dBm)

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Fig. 6 Gain after impedance

Fig. 7 Power distribution over the Harmonics

References 1. Pozar DM (2011) Microwave engineering, 4th edn. 2. Karneko T, Shiikuma K, Kunihiro K (2014) GaN HEMT high efficiency power amplifiers for 4G/5G mobile communication base stations. IEEE 3. Javorka P (2014) Fabrication and characterization of AlGaN/GaN high electron mobility transistor. IEEE 4. Cripps SC (2002) Advanced techniques in RF power amplifier design 5. Nakajima S (2008) GaN HEMTs for 5G base station applications. IEEE 6. Kikkawa T, Nagahar M, Okamoto N (2001) Surface charge controlled AlGaN/GaN power HEMT without current collapse and gm depression. Int Electron Dev Meet Tech Digest

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7. Gadallah A, Allam A, Abdel-Rehman AB, Jia H, Pokharel RK (2017) A high-efficiency lowpower 2.4 GHz class AB PA for WBAN applications using load pull. IEEE 8. Pazhouhesh P, Kitchen J (2020) A broadband class AB power amplifier with second harmonic injection. IEEE

The Anisotropy and Birefringence of Monolayer WS2 Semiconductor R. Santosh , U. Nageswara Rao , M. Jagan Mohan Rao , Suresh Kumar Yattirajula, and V. Kumar

Abstract The structural, electronic, and optical properties of transition metal dicalcogenide (WS2 ) semiconductors were calculated using DFT calculations. For the first time, the anisotropy and birefringence of WS2 are calculated in different energy regions. The estimated structural and electronic properties are in consider with the reported values. Keywords Transition metal dichalcogenide · Anisotropy · Birefringence

1 Introduction In recent years, 2D materials have received much attention due to their outstanding properties and promising applications [1, 2]. Graphene transistors have a low on– off ratio due to the zero bandgap [3]. The monolayer TMDs have direct bandgap which is applicable for opto-electronic materials and devices. The representation of TMDs is MX2 (M = Mo and W, X = S and Se); among them, tungsten disulphide (WS2 ) is having a growth of interest due to its high emission quantum yield, nonbuckling photon emission, etc. [4, 5]. Several DFT calculations are used to study the properties of WS2 [6, 7]. Till now, the optical properties such as anisotropy and birefringence have not been studied. Therefore, authors have taken much interest in calculating the optical properties of WS2 in different directions of light incidence. In this paper, the lattice constant (a), bond lengths (d S-W ), bond angle (8S-W-S ), and energy bandgap (E g ) of WS2 are calculated. The optical properties are calculated in both the directions of light incidence. R. Santosh (B) Velagapudi Ramakrishna Siddhartha Engineering College, Vijayawada, India e-mail: [email protected] R. Santosh · U. N. Rao · M. J. M. Rao Geethanjali College of Engineering and Technology, Medchal, Telangana 501301, India S. K. Yattirajula · V. Kumar Indian Institute of Technology (Indian School of Mines), Dhanbad, Jharkhand 826004, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_26

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2 Methodology The calculations were performed using the CASTEP simulation package [8]. The calculation is based on a generalized gradient approximation (GGA) using the Perdew–Berke–Ernzerhof (PBE) scheme [9]. An ultrasoft pseudopotential representation with a kinetic energy limit of 272.02 eV was used [10]. Optimization is performed by the BFGS algorithm [11]. The Gaussian smearing scheme is used with smearing width of 0.1 eV. The outer valence of the W and S atoms in calculation of total energy is 5s2 5p6 5d4 6s2 and 3s2 3p4 .

3 Results and Discussion 3.1 Electronic and Optical Properties The tungsten disulfide (WS2 ) belongs to a hexagonal structure with a space group of P63 /mmc. The side and top views of WS2 are shown in Fig. 1. The optimized lattice constant ‘a’ is 3.196 Å, which is in consider with the experimental value 3.153 Å

Fig. 1 a side and b top views of WS2 semiconductor. Yellow and blue circles indicate sulfur and tungsten atoms

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251

[12] and reported value 3.19 Å [13]. The symmetrical constraints of unit cell α, β, and γ are 90° , 90° , and 120° . The calculated bond length (d S-W ) and the bond angle (θ S-W-S ) are 2.426 Å and 80.922° , respectively. The d S-W value is in congruency with the experimental value 2.405 Å [12] and reported value 2.414 Å [7]. The band structure is calculated along the high symmetry points of Brillion zone and displayed in Fig. 2. The estimated direct bandgap for monolayer WS2 is 1.958 eV. This value is in consonance with the reported work [7]. The dielectric function is important in optical properties in which it is estimated in parallel (E⊥c) and perpendicular (E||c) polarizations of electric field. The imaginary part of dielectric function ε2 (ω) is calculated using the relation specified in Momida et al. [14]. The ε2 (ω) in different energy regions shown in Figs. 3 and 4. In E⊥c, conduction begins (E th ) after an optical bandgap of 2.1 eV and increases sharply with increasing transitions from the highest occupied valence state to the lowest occupied Fig. 2 Calculated band structure of WS2 along the high symmetry points

Fig. 3 Dielectric function ε(ω) in parallel polarization of electric field

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Fig. 4 Dielectric function ε(ω) in perpendicular direction of light incidence

conduction state. The transitions from S to W reach the maximum at 4.9 eV. While in E||c, conduction begins at 3.1 eV and reaches its maximum at 7.5 eV. The ε1 (ω) is determined using the method described by Kronig et al. [15] and shown in Fig. 5. The dielectric constant at zero frequency ε(0) is listed(in Table 1. ) The uniaxial anisotropy is 0.2, which is calculated using the relation δε = ε⊥ − ε|| /εtot . It indicates WS2 semiconductor shows strong anisotropy. Figures 3, 4, and 5 show WS2 is anisotropic material, which is applicable in linear and nonlinear optoelectronic applications. Figure 5 indicates the WS2 shows metallic behavior in the near UV region. The refractive index is calculated and shown in Fig. 6. The static refractive index n(0) is listed in Table 1. It has a highest value at 3.5 and 6.8 eV for Fig. 5 Real part of ε(ω)

The Anisotropy and Birefringence of Monolayer WS2 Semiconductor Table 1 Calculated optical parameters in different directions of light incidence

Parameters

E⊥c

253 E||c

ε(0)

9.122

5.722

n(0)

3.020

2.392

Δn(0)

0.629

E th (eV) èωp (eV)

2.139 21.90

3.339 21.92

Fig. 6 Calculated refractive index in different direction of light incidence

parallel and perpendicular directions of light incidence. The birefringence is calculated and shown in Fig. 7. The static birefringence at zero frequency Δn(0) is 0.6, and it increases with increase of photon energy. In the visible (VIS) region, the birefringence of WS2 increases from red to violet in positive direction. The maximum birefringence is 1.5, which occurs at 3.5 eV. The phase change has been obtained while crossing VIS to UV region. In middle UV region, Δn changes in negative direction. This discussion shows that the monolayer WS2 is an optically anisotropic material, which is applicable in remote sensing, biometric, and biomedical applications. The electron energy loss function (EELF) is displayed in Fig. 8. The EELF spectra show peaks in the middle UV region, which in turn called plasmon energies (èωp ). The calculated èωp is listed in Table 1. The EELF spectra shows, there is no energy loss electron in the low energy region, indicates WS2 is subtle for IR and visible regions.

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Fig. 7 Calculated birefringence

Fig. 8 Electron energy loss function in different polarizations of electric field of WS2 semiconductor

4 Conclusions The WS2 semiconductor shows the anisotropy in the entire electromagnetic spectrum, with the uniaxial anisotropic value of 0.2. The birefringence increases in VIS region from red light to violet. The phase change occurs in birefringence while crossing from VIS to UV region. The WS2 is an optically anisotropic material which is applicable in second harmonic generation, remote sensing, and biometric applications.

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References 1. Novoselov KS, Geim AK, Morozov SV, Jiang D, Zhang Y, Dubonos SV, Grigorieva IV, Firsov AA (2004) Electric field effect in atomically thin carbon films. Science 306:666 2. Xu W, Liu W, Schmidt JF, Zhao W, Lu X, Raab T, Diederichs C, Gao W, Seletskiy DV, Xiong Q (2017) Correlated fluorescence blinking in two-dimensional semiconductor heterostructures. Nature 541:62–67 3. van den Brink J (2010) Graphene: what lies between Nat. Mater 9:291 4. Yuan L, Huang L (2015) Exciton dynamics and annihilation in WS2 2D semiconductors Nanoscale, Vol 7, pp 7402 5. Peimyoo N, Shang J, Cong C, Shen X, Wu X, Yeow EKL, Yu T (2013) Nonblinking, intense two-dimensional light emitter: monolayer WS2 triangles. ACS Nano 7:10985 6. Ahuja U, Dashora A, Tiwari H, Kothari DC, Venugopalan K (2014) Comp Mat Sci 92:451 7. Luan Q, Chuan-Lu Y, Mei-Shan W, Xiao-Guang M (2017) First-principles study on the electronic and optical properties of WS2 and MoS2 monolayers. Chin J Phys 5:1930–1937 8. Segall MD, Philip JD, Lindan MJ, Probert CJ, Pickard PJ, Hasnip S, Clark J, Payne MC (2002) First-principles simulation: ideas, illustrations and the CASTEP code. J Phys Condens Matter 14:2717–2743 9. Perdew JP, Burke K, Ernzerhof M (1996) Generalized gradient approximation made simple. Phys Rev Lett 77:3865–3868 10. Vanderbilt D (1990) Soft self-consistent pseudopotentials in a generalized eigenvalue formalism. Phys Rev B 41:7892–7895 11. Fischer TH, Almlof J (1992) General methods for geometry and wave function optimization. J Phys Chem 96:9768–9774 12. Rodriguez Gutierrez H, Perea-Lopez N, Elías A (2013) Extraordinary room-temperature 12 photoluminescence in WS2 monolayers. Nano Lett 1:5007 13. Florentino L, Terrones M, Terrones H (2014) Electronic, magnetic, optical, and edge-reactivity properties of semiconducting and metallic WS2 nanoribbons. 2D Mat 2:015002 14. Momida H, Hamada T, Takagi Y, Yamamoto T, Uda T, Ohno T (2007) Dielectric constants of amorphous hafnium aluminates: first-principles study. Phys Rev B 75:195105 15. Kronig RL (1926) On the theory of the dispersion of X-rays. J Opt Soc Am 12:547–557

Implementation of Zinc Sulfide (ZnS) as a Suitable Buffer Layer for CZTS Solar Cell from Numerical Analysis Pratap Kumar Dakua and Deepak Kumar Panda

Abstract In this paper, zinc sulfide (ZnS) is taken as a suitable buffer layer in the copper zinc tin sulfide (CZTS) solar cell. The solar cell parameters have been calculated by considering the thickness and the bandgap of the ZnS layer using SCAPS 1D software. This proposed device model witnessed a good performance in all the parameters such as an efficiency of 22.08% with open-circuit voltage of 0.93 V, short-circuit current of 28.27 mA/cm2, and fill-factor of 82.61% through ZnS as a buffer layer for the copper zinc tin sulfide (CZTS) solar cell. When the absorber layer thickness is between 2 and 4 µm, we can obtain the high efficiency. By choosing the ZnS bandgap between 3.1 and 3.25 eV, the efficiency will be higher as obtained in the proposed study. Keywords CZTS solar cell · Buffer layer · SCAPS 1D

1 Introduction Solar energy is the ultimate option for generating electricity to fulfill the world energy requirement. Using the principle of photovoltaic effect, the sunlight can directly have converted to electricity. Many work has been carried out to obtain low-cost high-efficient solar cell by world over [1]. Different generation has used different technology to get the low-cost solar cells by using different materials. Among them, silicon (Si), CdTe, CIGS, CZTS are in the front line of interest. The first-generation solar (Si-based) shows an optimum efficiency of ~24% by New South Wales. But, due to low through put and high cost, it is not good option to impact the world’s energy need. In contrast, CdTe and CIGS fascinated as an interesting candidate to offer a good efficiency of around 21%. But, due to the toxic content of the materials and also due to unavailability, these materials also not sustained a long. To meet these challenges, coper zinc tin sulfide (CZTS) has shown nobel advantages over CIGS and CdTe. CZTS is considered as a capable absorber layer for the next-generation P. K. Dakua (B) · D. K. Panda School of Electronics, VIT-AP Campus, Vijayawada 522237, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_27

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thin film-based solar cell [2, 3]. The photovoltaic properties of a solar cell are highly impacted by the buffer layer. It provides a band alignment between the window and absorber layer also affects the band structure. The solar cell performance is also affected by the bandgap and the thickness of the ZnS buffer layer. This work presents the numerical simulation of different buffer layer for CZTS solar cell using SCAPS 1D software. The choice of a suitable buffer-layer material is very significant for solar cell performance. Here, in case of solar cell, the ZnS layer is a middle layer in between the CZTS and window layer. It forms a PN junction for electrical conduction with p-type absorber layer. An n-type material with a larger bandgap material is generally used for buffer layer. Cadmium sulfide (CdS) having a bandgap of 2.45 eV is used as a buffer layer so far in CZTS solar cells. But, due to toxicity of cadmium in CdS, substitute buffer layer material is in interest. Having a bandgap of 3.5–3.8 eV, ZnS is a n-type semiconductor is one of suitable buffer-layer material for CZTS solar cell. This work presents to obtain the concert of CZTS solar cell by implementing cadmium-free ZnS as buffer layer.

2 Device Structure and Approach The solar cell structure has been designed using SCAPS-1D solar cell simulator, for numerical study. This software is used to modeling different solar cell devices. It takes a number of input parameters and performs the AC as well as DC measurements including different solar cell performance parameters. The proposed CZTS-based solar cell in this work is presented in Fig. 1. The device comprises of SLG soda lime glass as substrate, Mo used as a back contact, CZTS as an absorber layer, and the buffer layer used here is the ZnS [4]. The parameters used for simulation have been taken from the literatures which is presented in Table 1. During the simulation, the temperature is kept at 300 K with AM 1.5, and the spectrum 1000 W/m2 light power is used. To achieve the better results for the designed solar cells, the simulations will take in three steps: Sunrays

Fig. 1 Proposed device structure of CZTS solar cell [5–8]

ZnS CZTS Mo SLG

Buffer Layer

Absorber Layer

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Table 1 Required values of different parameters for simulation in SCAPS-1D [5–8] Parameters

Mo

ZnS

CZTS

Thickness (nm)

100

0.03–0.08

2000

Bandgap (eV)

1.7

3.10–3.40

1.5

Electron affinity (eV)

4.2

4.5

4.5

Dielectric permittivity

13.6

CB-effective density of states

(1/cm3 )

VB-effective density of states

(1/cm3 )

10

2.2 ×

1018

1.8 ×

1019

Electron thermal velocity (cm/s)

1×

Hole thermal velocity (cm/s)

1 × 1017

Electron mobility

(cm2 /Vs)

Hole mobility (cm2 /Vs)

1. 2.

3.

1017

10

1.5 ×

1018

2.2 × 1018

1.9 ×

1018

1.8 × 1019

1017

1×

1 × 1017

1 × 1017

1 × 1017

100

100

100

25

25

25

Keeping the absorber layer fixed at 2000 nm, the buffer-layer thickness will be varied between 50 and 150 nm to obtain the optimum thickness. The buffer-layer thickness will be fixed, and the thickness of the CZTS absorber layer will be changed between 200 and 2000 nm to find the optimum thickness for CZTS absorber layer. After obtaining the optimum thickness of the buffer layer and the absorber layer, the solar cell parameters will be studied as a function of temperature.

In this work, the CZTS solar cell performance was studied by implementing zinc sulfide as the buffer layer by using SCAPS 1D software to simulate the electrical characteristics of the solar cell. The device structure is shown in Fig. 1. The structure compromises of an n-type ZnS buffer layer with p-type CZTS absorber layer. By varying the thickness of the absorber layer from 1 to 4 µm, the solar cell performance parameters have been recorded. Similarly, the bandgap of the buffer layer will be changed from 3.10 to 3.40 eV to measure the performance of the proposed device [9]. Here, the buffer-layer thickness is altered from 0.03 micron to 0.080 microns to notice its role on CZTS solar cell performance. Simultaneously, the temperature is also taken into consideration to evaluate the performance by varying the temperature from 300 to 400 K.

3 Results and Discussion 3.1 Deviation of Absorber Layer Thickness The absorber layer thickness is considered from 1 to 4 µm to investigate the influence of the CZTS layer in the solar cell output performance. The buffer-layer thickness is taken around 40 nm during the simulation as shown in Fig. 2. The conversion

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Fig. 2 CZTS solar cell performance with absorber thickness

efficiency of the device increases with increase in the CZTS-layer thickness. As considering the thick absorber layer, the diffusion length increases so that the charge carrier in p-type absorber also increases. Due to this, a more number of charge carriers will be generated which allows a more number of photons with larger wavelength to be absorbed. The depletion layer thickness also rises with rise in the absorber layer thickness. Because of the electric field created by the depletion region, the charge carriers can drift to the n-type ZnS buffer layer. Considering the thickness of the absorber layer-3 microns, the performance constraints of the solar cell remain persistent as shown in Fig. 2. It defines that without considering the optimal thickness, there will be no such significant variations in the solar cell parameters. Here, in the study, the optimum thickness of the absorber layer was taken as 3000 nm. By considering the optimal thickness of 3000 nm, the conversion efficiency is obtained 21.89%, open-circuit voltage of 0.94 V, short-circuit current of 28.18 mA/cm2 , and fill-factor of 82.71%.

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3.2 Variation of ZnS Buffer-Layer Thickness Zinc Sulfide is non-toxic, cheap, and earth-abundant material. The ZnS-layer thickness is changed from 0.030 microns to 0.080 microns to search the effect of this layer in the cell performance. Higher efficiency will be obtained by choosing as much as thinner the buffer layer [5, 6]. The maximum number of photons will be transmitted to the CZTS layer by lowering the generation of charge carriers in the ZnS buffer layer due to the thinner buffer layer [7, 8, 10]. In this simulation, the highest efficiency was recorded by choosing the bufferlayer thickness as 40 nm. The efficiency will be increased by taking thinner buffer layer as shown in Fig. 3. Fig. 3 CZTS solar cell performance with buffer-layer thickness

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Fig. 4 CZTS solar cell performance with ZnS bandgap

3.3 Effect of ZnS-Layer Bandgap Bandgap variation of ZnS buffer layer is important for the solar cell. The ZnS bandgap is changed from 3.10 to 3.40 eV. Due to the higher bandgap, it is helpful for minimizing the absorption toward the lower wavelengths. The deviation of Voc, Jsc, FF, and efficiency with th ZnS buffer-layer bandgap is presented in Fig. 4.

3.4 Temperature Effects For finding the performance of the solar cell, it is important for considering the operating temperature. The semiconductor properties such as absorption coefficients, bandgap, and carrier concentration will be affected by temperature. This study considered the effect of temperatures by selecting temperature value from 300 to 400 K. The

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Fig. 5 CZTS solar cell performance with temperature variation

solar cell parameters decrease with increase in the temperature as shown in Fig. 5. If the temperature increases, the electrons combine with holes before reaching the depletion layer and get collected.

4 Conclusion In the context of bandgap and thickness of the ZnS buffer layer, ZnS is used as a suitable buffer layer to replace the conventional CdS layer for the CZTS solar cell through the numerical analysis. By increasing the thickness of CZTS layer, the higher efficiency will be obtained. Similarly, the short-circuit current and the cell efficiency may be increased by increasing the ZnS-layer thickness. By regulating the bandgap of the material, further, we can increase the efficiency of the solar cell. With a 22.08 percent efficiency, open-circuit voltage (Voc|) = 0.93 V, short-circuit current (Jsc) = 28.27 mA/cm2, and fill-factor = 82.61% has been obtained by implementing ZnS as a buffer-layer material for CZTS solar cell using SCAPS 1D software.

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References 1. Chopra KL, Paulson PD, Dutta V (2004) Thin-film solar cells: an overview. Progr Photovoltaic Res Appl 12:62–69 2. Kheraj V, Patel KK, Patel SJ, Shah DV (2013) Synthesis and characterization of Copper Zinc Tin Sulphide (CZTS) compound for absorber material in solar-cells. J Cryst Growth 362:174–177 3. Wang H (2011) Progress in thin film solar cells based on Cu2ZnSnS4. Int J Photoenergy 801292 4. Inamdar AI, Lee S, Jeon K, Lee CH, Pawar SM, Kalubarme RS, Park CJ, Im H, Jung W, Kim H (2013) Optimized fabrication of sputter deposited Cu2ZnSnS4 (CZTS) thin films. Sol Energy 91:196–203 5. Fella CM, Romanyuk YE, Tiwari AN (2013) Technological status of Cu2ZnSn(S, Se)4 thin film solar cells. Sol Energy Mater Sol Cells 119:276–277 6. Hossain MI, Chelvanathan P, Zaman M, Karim MR, Alghoul MA, Amin N (2011) Prospects of Indium Sulphide as an alternative to Cadmium Sulphide buffer layer in CIS based solar cells from numerical analysis. Chalcogenide Letters 8(5):315–324 7. Abermann S (2013) Non-vacuum processed next generation thin film photovoltaics: towards marketable efficiency and production of CZTS based solar cells. Sol Energy 94:37–70 8. Haque F, Rahman KS, Islam MA, Rashid MJ, Akhtaruzzaman M, Alam MM, Alothman ZA, Sopian K, Amin N (2014) Growth Optimization of ZnS thin films by RF magnetron sputtering as prospective buffer layer in thin film solar cells. Chalcogenide Lett 11(4):189–197 9. Li L, Zhang BL, Cao M, Sun Y, Jiang JC, Hu PF, Shen Y, Wang LJ (2013) Facile synthesis of Cu2ZnSnS4 nanocrystals and its use for dyesensitized solar cells applications. J Alloy Compd 551:24–29 10. Bouznitt Y, Beggah Y, Boukerika A, Lahreche A, Ynineb F (2013) New co-spray way to synthesize high quality ZnS films. Appl Surf Sci 284:936–941 11. Wei A, Liu J, Zhuang M, Zhao Y (2013) Preparation and characterization of ZnS thin films prepared by chemical bath deposition. Mater Sci Semicond Process 16:1478–1484 12. Hwang DH, Ahn JH, Hui KN, Hui KS, Son YG (2012) Structural and optical properties of ZnS thin films deposited by RF magnetron sputtering. Nanoscale Res Lett 7:26 13. Nair PK, Nair MTS, Garcia VM, Arenas OL, Pena Y, Castello A, Ayala IT, Gomezdaza O, Sanchez A, Campos J, Hu H, Suarez R, Rincon ME (1998) Semiconductor thin films by chemical bath deposition for solar energy related applications. Sol Energy Mater Sol Cells 52:313–344 14. Shao L-X, Chang K-H, Hwang H-L (2003) Zinc sulfide thin films deposited by RF reactive sputtering for photovoltaic applications. Appl Surf Sci 212–213:305–310 15. Amin N, Hossain MI, Chelvanathan P, Zaman M, Sopian K (2012) Prospects of Cu2ZnSnS4 (CZTS) solar cells from numerical analysis. In: 6th international conference on electrical and computer engineering, ICECE 2010, Dhaka, Bangladesh 16. Olopade MA, Oyebola OO, Adeleke BS (2012) Investigation of some materials as buffer layer in copper zinc tin sulphide (Cu2ZnSnS4) solar cells by SCAPS-1D. Pelagia Redearch Library 3(6):3396–3400

The Effect of Quantum Well Base in GaAs-Based HBT Amit Kumar Jha and Manas Ranjan Jena

Abstract The improvement in DC and RF characteristics of Quantum Well base in GaAs HBT (Hetero Junction Bipolar Transistor) is presented. Based on an experimentally validated model of the Silvaco TCAD tool, the properties of the GaAs HBT are simulated. Our results are indicative that Quantum Well base in HBT has the best DC characteristics like the current gain (760) and the lowest offset voltage (5.9 mV). However, the RF performance of the HBT is observed to be poor with the unity gain cut-off frequency recording a value of f T = 1 MHz. Keywords Quantum well · QWBHBT · Linearity

1 Introduction The study and modelling of HBT where base is considered as quantum well have described. A base as a quantum well is nothing but the thickness (dimension) of the base comparable to de Broglie wavelength of electrons in a semiconductor which depend on the effective mass of electron. Initially, we take base thickness 1000 Å and later made the base thickness 300 Å and the dc characteristics and gummel plot have been simulated. The simulation was carried out by Silvaco ATLASTM tools, and the fitting parameters and models were taken from Atlas Manual as references. Our analysis based on the work done in Mil’shtein et al. [1]. The de Broglie wavelength of electron in GaAs is approximately 300 Å; thus, the quantized level of allowed state can be achieved at this dimension. Here, in the present case the base thickness is considered as 240 Å and it allowed us to take quantum effect into attention. The “well” refers here is the approximation of Kronig-Penney model, which is one-dimensional periodic potential for an electron. The possible allowed states that the electron can live in are determined by the Schrödinger equation. In the A. K. Jha (B) · M. R. Jena Department of Electronics and Communication Engineering, Veer Surendra Sai University of Technology Burla, Sambalpur, Odisha, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_28

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Fig. 1 Approximated band diagram for InGaP/GaAs/InGaP heterostructure

Fig. 2 Double heterointerface at both interface of InGaP and GaAs

case of double heterostructure, potential V (x) is a periodic square wave as shown in Fig. 1. A Quantum Well Base Heterojunction Bipolar Transistor (QWBHBT) in which the material is taken as GaAs and the heterojunction is formed between InGaP/GaAs/InGaP. There is double heterointerface formed due to large bandgap of semiconductor InGaP as shown in Fig. 2. As GaAs is the material of base, the thickness of this layer is varied, and their effective mass of electron computed from the de Broglie wavelength relation [2]. The double-side barrier and the base having quantum well gives the device which has transconductance is negative. Following the similar principle, in device named as BiQRTT abbreviated as Bipolar Quantum Resonant Tunnelling Transistor in which there are two barriers at both interface and a quantum well base was developed. The thickness-dependent NBHBT (narrow base heterostructure bipolar transistor) in which the dimension of the base reduced and resulting the decreases in the base recombination current and transit time of the base and hence the DC current gain increasing [3]. We used TCAD (Technology Computer-Aided Design) Silvaco, a commercial package of ATLAS for our design. To accommodate quantum effect, Drift-Diffusion Mode-Space Method (DD_MS) were used [6, 7].

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2 Schematic Design of the Proposed QWBHBT The schematic construction as shown in Table 1 under simulation is given in Fig. 3. In which, collector at the bottom which consists of n-type GaAs, a base layer having thickness initially 1000 Å, and later it will change to 240 Å intentionally. The doping of the base layer is of the order of 10–19 cm−3 with p-type GaAs. A highly doped n-type InGaAs as cap layers followed by n-type GaAs region at emitter contact have shown at the top of the device. A layer of higher band gap n-type InGaP sandwiched between two higher bandgap p-GaAs and formed heterojunction. The same schematic structure is followed in the simulation of QWBHBT; only modification in the thickness of the base layer has been done for the purpose of making quantum well base and the doping is slightly less than earlier case as 1018 cm−3 and the thickness is 240 Å and it is well suitable for the wavelength of electron passing through it. The emitter layer adjacent to the base is kept as it was earlier but at this time an additional layer of InGaP of thickness 400 Å is added and doping for both InGaP region is of p-type. A double heterojunction which is formed by the combination of InGaP/GaAs/InGaP resulting a bottomless quantum well. This quantum well act as a barrier for the electrons which is introduced into the collector. The application of a wider energy gap E g in emitter (E) side and a smaller bandgap in base (B) Table 1 Device specification and doping concentration HBT with quantum well base

HBT without quantum well base Length (Å)

Doping (cm−3 )

E

B

C

E

B

C

2000 without Cap

1000

13,500

2650 with cap layer of InGaP

240

13,500

1019

1018

1016

1018

1017

1016

Fig. 3 Device structure with quantum well base

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Fig. 4 Band alignment with a graded E–B heterojunction b an abrupt E–B heterojunction

section permits us to obtain very large InE /IpE ratios and therefore to preferentially inject Electrons rather than holes. This can be used to improve the performance of a BJT. The band diagram of such a heterojunction BJT is shown in Fig. 4. The width for both structure is kept at 40 mm.

3 Results and Discussion 3.1 DC Characteristics The gummel plot for both the device is shown in Fig. 5. In which, the base is removed, and emitter terminal is grounded. The device D.C characteristics can be determined from the gummel plot, and due to quantum well base, this device exhibited less turn-on voltage than the general HBT. Fig. 5 Gummel plot comparisons of the QWBHBT and HBT

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Fig. 6 Plot of DC gain (β) for both devices

Figure 6 shows current gain for both devices. Also, it can be easily shown from this plot the value for β in case of QWBHBT is very high as compared to nonquantum well HBT device. This is because across the thin neutral region of base the recombination current is reduced as the thickness of base is reduced.

3.2 I–V Characteristics In Fig. 7, I C versus V CE characteristics for three values of base current IB have plotted for both HBTs. In Fig. 7, output characteristics for QW base HBT are shown in which there are three values of base current have been taken and respective collector current can be shown. There is an interesting fact comes out from this plot as when value of base current is rise, collector current reduces, and hence, dc gain also reduces. This effect due to quantum well in the base region becomes more effective with high value of base Fig. 7 I–V characteristics for QW BASE HBT

Negative Transconductance

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current. So, at a very low value of base current, we can get more dc gain than device which does not have QW base. Enhance in value of β is plotted in Fig. 6. In reported journal [1], author was taken commercial HBT in which there is no cap layer of InGaP. Since we have taken a cap layer of InGaP, so, when collector current approaches zero, i.e. β becomes zero at base current is 3E–5A. Reported value at β = 0 for I B = 3E– 4A and this slightly differ due to cap layer [2]. Negative transconductance which is encircled in Fig. 7, shown due to effect of semi-metal behaviour of base rather than semiconductor which is doped. When the voltage at collector terminal is low and current flowing through base is relatively high, this effect is occurred. In Fig. 8, output characteristics of without quantum well device is given in which there is no negative transconductance effect. A barrier in form of cap layer is inserted in the emitter region. We try to extrapolate I–V curve for both HBTs, and it turns out to be very low as shown in Figs. 9 and 10. Region behind low offset voltage is that it would take very Fig. 8 I–V characteristics for HBT without QW BASE

Fig. 9 Offset voltage plot for QW BASE

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Fig. 10 Offset voltage plot for without QW BASE HBT

small time to turn on these devices like a cap layer without quantum well base HBT and HBT with quantum well base [2]. In case of QW base HBT, large amount of free electron present in base which can easily be transmitted into depleted region of collector at junction. Availability of free electron in base region behaves like metal despite of doping is uniform in this region. Adverse effect of this is that normal transistor behaviour failed, and it becomes difficult to operate this device as transistor. When the output current is high, mobility experienced by electron which is in very large number is changing from low mobility base region to high mobility collector region. Due to changing of mobility and current due to recombination, we will get high β for the thin base as compared to thick base as well as low offset voltage. Implication of HBT in which base is kept very thin in growing the epitaxial layer for the creation of negative resistance by process of resonant tunnelling in QWHBT. Early voltage for without QW base HBT from output characteristics is indicated in Fig. 11. When base current is small, magnitude of early voltage is greater than large base current. Output resistance which is characterised by slope of I–V curve is related to early voltage and transconductance of device. So, change in collector current as compared to base current is relatively low so it becomes difficult to extrapolate I–V characteristics and find intersection point at I C = 0A in case of QW base HBT that is why here early voltage characteristics for this device is not mentioned.

3.3 Small Signal Characteristics In Fig. 12, AC gain versus frequency is plotted in terms of h21 parameter. The characteristics shows very less cut-off frequency in contrast to reference Fig. 10: Offset Voltage Plot for Without QW BASE HBT Fig. 10: Early Voltage Characteristics for

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Fig. 11 Early voltage characteristics for without QW BASE HBT

Fig. 12 Current gain plot for both device

Without QW BASE HBT paper [1] as they reported in GHz range of cut-off frequency and comparison with non-quantum well base device it is five times larger. The exact reason behind this is not found and leads to contradiction, and further research about this is going on. The reason as mentioned in [1] is that due to less dimension of base, transit time becomes less and frequency f T in case of QW base HBT. But if dimension is low, resistance offered by this layer becomes high as compared to high dimensional base and dc gain should be less. This is not the present scenario justified. Further, the unilateral power gain is plotted against frequency in Fig. 13. The maximum frequency f max predicted in simulation is in MHz range. Information regarding oscillation frequency for such device is found in literature [2, 3]. Simulation results show f max is almost same for both devices and value is in range of MHz.

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Fig. 13 Unilateral power gain plot for both device

Fig. 14 Minimum noise figure plot for both HBT

3.4 Minimum Noise Figure Simulation results for NFmin are given in Fig. 14; it suggests that QW base HBT having less NFmin as compared to non-Quantum Well base HBT [3]. So, it can have better linearity than this and application as amplifier, this device is well suited. Although from circuit application point of view, NFmin is also dependent on dc gain as well as resistance of base layer.

4 Simulation-Based Comparison Analysis In Table 2, comparison between Quantum well device and conventional HBT is given. Performance parameter is simulated, and accordingly, all these given values are gathered in this table. Although reported value for such type of devices for some

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Table 2 Comparison between Quantum well device and conventional HBT Performance parameter

HBT without quantum well base

HBT with quantum well base

Simulation result Reported result [1, Simulation result Simulation result 2] DC gain (β)

250

100

760

750

Cut-off frequency, f T

1 MHz

1–10 GHz

1 MHz

50 GHz

Offset voltage, Voffset

45 mV

−21.6 mV

5.9 V

Not reported yet

Early voltage, VA

−20.65 V

7.69 V

Not reported yet

Not reported yet

2 dB

6.07 dB

Not reported yet

Minimum noise 16.03 dB figure, NFmin

parameters are agreed with the results simulated, some of important figure of merits are not perfectly matched with reported results.

5 Conclusion The Quantum Well base in HBT is studied. The use of QW base in HBT is providing an improvement in DC current gain which is highest. The poor performance in RF characteristics is to be improved further by introducing verity of cap layer along with reducing base spread resistance.

References 1. Mil’shtein S, Churi A, Palma J (2008) Bipolar transistor with quantum well base. Microelectron J 39(3–4):631–634 2. Jena MR, Panda AK, Dash GN, Cap-layer and charge sheet effect in InP based pnp d-doped heterojunction bipolar transistor 3. Capasso F, Kiehl RA (1985) Resonant tunnelling transistor with quantum well base and highenergy injection: a new negative differential resistance device. J Appl Phys 58(3):1366–1368 4. Swe HMT, Tun HM, Latt M (2020) Analysis of quantum-well heterojunction emitter bipolar transistor design. American J Nano Res Appl 9(1):9–15. doi: https://doi.org/10.11648/j.nano. 20200801.12 5. Dombala H, Zinaddinov M, Kia O, Mil’shtein S, Non-graded base Si/Ge heterojunction transistor 6. Adachi S (Ed) (1993) Properties of aluminium gallium arsenide (No. 7). IET 7. Simulation AUSMD (2011) Software, Silvaco. Inc., Santa Clara, CA, pp 330–331 8. Atlas DS (2005) Atlas user’s manual. Silvaco International Software, Santa Clara, CA, USA 9. NSM Archive—Physical Properties of Semiconductors

Micro/Nanoelectronics Circuits

Power and Area Trade-Off for Accuracy-Controlled Multiplier for Image Compression Using DCT Mukesh Kumar Sukla and Kabiraj Sethi

Abstract Approximate computing pervades for different error-tolerant applications to accomplish low-power and higher frequency. A programmable accuracycontrolled multiplier (ACM) is proposed to control the accuracy by generating partial products. The accuracy will be controlled by setting up the control bits to mux out the actual multiplier and/or approximate multiplier out. The trade-off in power and area is observed at different error rate. The experiment is demonstrated for image compression using discrete cosine transform (DCT) method to measure the SNR for standard cameraman gray image. This work is resulted with mean error distance (MED) of 3.12 and 23.825 dB SNR. The core logic resulted in maximum 31.63% reduction in static power and 7.48% reduction in critical path delay for approximate multiplier. The core area is reduced up to 27.79%, and an improvement in SNR is achieved up to 3.44% at a cost of 20.84% area over head while synthesized using 45 nm. Keywords Accuracy-controlled · Multiplier · Approximate · Programmable · SNR · Power · Area · Trade-off

1 Introduction Due to the increasing demands for transmission of data in image and video form, compression and decompression methods are having a significant role. Image compression is the key for efficient storage and transmission. Several compression techniques are implemented like discrete cosine transform (DCT) and wavelet transform (WT) for different images. Approximate computing can be adopted with M. K. Sukla (B) · K. Sethi Department of EL&TC Engineering, Veer Surendra Sai University of Technology, Burla 768018, India e-mail: [email protected] K. Sethi e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_29

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Input Image

Block Splitting

Compressed Image

Approximate DCT

Quantization

Decoding

Scanning

Fig. 1 Image compression method

tolerant accuracy to realize even better performance in core area and power consumption. Dynamic control in system performance provides a trade-off between accuracy, power, and design area [1]. Fortunately, there are alternative techniques of image compression and decompression available today. They are grouped into two categories: lossless and lossy image compression. The JPEG technique is majorly used form of lossy image compression and that falls into the discreet cosine transform. The DCT method works by splitting images into groups of differing frequencies. The less important frequencies are filtered during quantization and hence called as “lossy” components as a process of compression. Only the most important frequencies are retrieved in the decompression process as shown in Fig. 1. Hence, reconstructed images are having additional distortion, and the levels of distortion can be manipulated during the compression stages [2]. The approximate computing features the best for a trade-off between the accuracy and hardware resources. Depending on the computation quality, the application runtime will vary significantly. It is a preference to bring quality-configurable systems that meets the requirement of computational effort and quality according to the application at a cost of the increased power and/or delay. In order to achieve additional benefit for such error-tolerant applications, an area-optimized, low-error rate approximate multiplier is proposed. In addition, the design can be reconfigured to control the error for higher order multiplier.

2 Literature Review An approximate multiplier is designed by using adder logic to achieve better performance with XNOR logic at the lower-bit positions [2]. Accurate adders are realized to carry out the multiplication with diminished carry propagation. The input bits are grouped together to perform the operation. The MSB group is realized with accurate arithmetic, and the LSB group is executed with approximate arithmetic operation to reduce the error distance (ED) [4]. The logic optimization is achieved by using

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279

majority logic-based design. The 2-bit majority logic is used in higher bit operation efficiently [5]. Works have been published in the area of approximated arithmetic circuit design and applications. OR gates are used in the place of Ex-OR for most approximation circuits to optimize the power and area to a greater extent by introducing errors at the lower significant bits (LSBs) only [14]. A unique technique is implemented to relax the binary bits for a binary multiplier dynamically and called dynamic range unbiased multiplier (DRUM). This compresses the operand bits to a group of k-bits out of n-bits where k < n throwing LSBs away to reduce the complexity in hardware [16]. The reduced input bits are multiplied. Additional controllability is achieved to control the accuracy by masking the carry bit. The accumulation of the partial products happens using masked adders for lower blocks and/or higher blocks [17]. A reduced partial product method is implemented as a fundamental building block for higher order approximation for applications within specified error limit. The partial products are added up using an array method or Wallace method[23]. The methods are demonstrated in Figs. 2 and 3 to generate the output and redundant. An array multiplier passes carry-out to one step ahead to the next significant column. Number of adder stages are reduced in Wallace method which causes a speed up in performance. The variable error control methods can be applied by multiplexing the approximate multipliers with accurate one. Fig. 2 Array architecture [23]

Fig. 3 Wallace tree architecture [23]

280 Table 1 Different configurations and control bits

M. K. Sukla and K. Sethi Type

Configuration

Control

T1

4 WTM

1111

T2

1 WTMs at MSB + 3 DMs at LSB

1000

T3

2 WTMs at MSB + 2 DMs at LSB

1100

T4

3 WTMs at MSB + 1 DMs at LSB

1110

T5

1 WTM + 1 DM + 1 WTM + 1 DM

1010

T6

1 WTMs at MSB + 3 RPMs at LSB

1000

T7

2 WTMs at MSB + 2 RPMs at LSB

1100

T8

3 WTMs at MSB + 1 RPMs at LSB

1110

T9

1 WTM + 1 RPM + 1 WTM + 1 RPM

1010

T10

4 DMs

0000

T11

2DMs at MSB + 2 RPM at LSB

0000

T12

4 RPMs

0000

3 Accuracy-Controlled Multiplier (ACM) The Wallace tree multiplier (WTM) is implemented to achieve the minimum propagation delay at the accumulation stage. The multiplication operation can be performed by grouping the operand bits. In extension to the reduced partial product method, the approximation is used in different group of operand bits. The 8-bit multiplier can be implemented with alternative combination of approximate multipliers to reduce the error distance (ED) as compared to all approximation. The architectures are shown here in Table 1 with Wallace tree multiplier (WTM), Dadda multiplier (DM), and reduced partial product multiplier (RPM). The approximate multipliers at the MSB part result large error distance (ED). For selective applications and/or on need basis, we can configure the architecture to manipulate the ED without affecting other parameters. But there is a trade-off between power and area. The architecture shown in Fig. 4 can be configured by removing the exact multiplier at the suitable positions. Different configurations are realized by varying the control bits to study the error distance, and the architectures are realized individually to compare the power and area. The ED is controlled by muxing the output of the 2-bit multipliers and then accumulated to produce the end result. Wallace tree adder is used to provide lesser propagation delay.

4 Simulation Results The RTL implementation is done for the multipliers and compiled using CADENCE Verilog simulator. The top module is synthesized using 45 nm standard cell library to compare the core area, power consumption, and critical path delay.

Power and Area Trade-Off for Accuracy-Controlled Multiplier …

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Fig. 4 Mux-based accuracy-controlled architecture

Fig. 5 Functional simulation with sample input a[7:0] = 8’d255 and varying b[7:0] for control bits “1010”

4.1 Implementation and Functional Verification The modules are implemented using Verilog HDL and verified with different test cases as shown in Fig. 5 for a sample run. The testbench is developed to 216 possible test samples to measure the number of erroneous responses and to record the maximum error. The mean error distance (MED) by summing up the error distances (EDs). Table 2 shows the multiplier output for random inputs and error counts and maximum error in Table 3.

4.2 Synthesis The report is generated using 45 nm standard cell library for analysis. The delay along the critical was observed to be 1039 ps for T9 and 1149 ps for T2. T12 is implemented with 291 µm2 and T2 with 404 µm2 . The static power is measured to be 18.271 nw for T12 and 20.378 nw for T6 as shown in Table 4 for 8-bit operations.

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Table 2 Responses for constant sample input for different architectures Type

A[7:0]

B[7:0]

P[7:0]

A[7:0]

B[7:0]

P[7:0]

T1

255

255

65,025

127

127

16,129

T2

255

255

64,761

127

127

15,865

T3

255

255

64,889

127

127

15,993

T4

255

255

65,017

127

127

16,121

T5

255

255

64,889

127

127

15,993

T6

255

255

63,375

127

127

15,759

T7

255

255

64,175

127

127

15,919

T8

255

255

64,975

127

127

16,079

T9

255

255

64,175

127

127

15,919

T10

255

255

62,713

127

127

15,865

T11

255

255

61,999

127

127

15,791

T12

255

255

50,575

127

127

15,247

ER%

Table 3 Error rate and mean error distance summary Type

Wrong count

Sum error

Max error

T1

0

0

0

MED 0

T2

23,380

2,703,360

264

35.67

41.25

T3

16,575

1,392,504

136

25.29

21.24

T4

10,239

81,912

8

15.62

1.24

T5

17,536

1,392,640

136

26.76

21.25

T6

26,656

6,758,400

1650

40.67

103.125

T7

19,600

3,481,600

850

29.9

53.125

T8

12,543

204,750

50

19.14

3.12

T9

19,600

3,481,600

850

29.9

53.125

T10

27,704

23,674,880

2312

42.27

361.25

T11

30,071

25,760,814

3026

45.88

393.08

T12

30,625

59,187,200

14,450

46.73

903.125

The library is chosen with worst case model for NMOS and PMOS (SS) at room 27 °C.

5 Experimental Setup DCT The proposed architectures are implemented to perform image compression using DCT with accurate multiplier and approximate multipliers on original cameraman image as shown in Fig. 6.

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Table 4 Power, area, and delay report Type

Area (µm2 )

Delay (ps)

Static power (nw)

Dynamic power (nw)

Total power (nw)

T1

403

1123

26.725

13,469.684

13,496.409

T2

404

1148

27.047

13,590.16

13,617.207

T3

404

1148

26.924

13,274.436

13,301.36

T4

403

1148

26.828

13,412.551

13,439.379

T5

404

1148

26.95

13,659.987

13,686.937

T6

319

1039

20.378

11,039.883

11,060.261

T7

347

1039

22.484

11,774.487

11,796.971

T8

375

1039

24.61

12,524.457

12,549.067

T9

347

1039

22.504

11,747.192

11,769.696

T10

404

1148

27.169

13,802.922

13,830.091

T11

347

1039

22.73

12,251.16

12,273.89

T12

291

1039

18.271

10,466.318

10,484.589

Fig. 6 Original image

The DCT method separates images considering the different frequency components. As a part of compression, quantization eliminates redundant frequencies and hence commonly termed as “lossy” operation. The most important frequency components are used to reconstruct the image which results in distortion. The distortion levels are adjusted during the compression process, and a trade-off can be made for power saving devices and area optimization to reduce the complexity. The JPEG method uses both color and gray images. This article uses gray cameraman image as a standard to derive the signal-to-noise ratio (SNR) for all the architectures. Table 5 shows the measured SNR in dB and relative increase and decrease with reference to the accurate multiplier (T1). The compressed images are shown in Fig. 7.

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Table 5 SNR and reduction with respect to exact multiplier

Type

SNR (in dB)

SNR reduction (%)

T1

23.23882

0

T2

23.20144

0.16

T3

23.27297

−0.14

T4

23.36142

−0.51

T5

23.28672

−0.2

T6

23.12872

0.44

T7

23.18398

0.23

T8

23.82515

−2.52

T9

23.75125

−2.21

T10

23.11588

0.52

T11

23.00101

1.02

T12

23.02387

0.92

(a)

(b)

(c)

(d)

(e)

(f)

(g)

(h)

(i)

(j)

(k)

(l)

Fig. 7 Compressed image using—a T1 b T2 c T3 d T4 e T5 f T6 g T7 h T8 i T9 j T10 k T11 l T12

6 Result and Discussion The critical path delay is minimum for the architecture with WTM at MSB and reduced partial product (approximate) at LSB for various combinations shown in T6, T7, T8, and T9 with intermediate core area as shown in Fig. 8. Also, similar result is obtained for reduced partial product method in T11 and T12. The static power and dynamic power are falling in the same plane as area and delay which is

Power and Area Trade-Off for Accuracy-Controlled Multiplier …

285

Fig. 8 Area and delay trade-off

shown in Figs. 8, 9, and 10. The major difference is marked in MAX_ERROR and ERROR_COUNT. T8 produces MAX_ERROR of 50 with 12,543 wrong hits at a rate of 19.14 with mean error distance (MED) 3.12 as shown in Table 3.

Fig. 9 Area and power trade-off

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Fig. 10 Power and delay trade-off

The experimental result proved the architecture the best fit for image compression application with increase in SNR by 2.52% with reference to the standard DCT with WTM. The normalized form of area, power, and delay is shown in Fig. 11.

Fig. 11 Power, area, and delay comparison

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Table 6 SNR and reduction with respect to exact multiplier Type

Using LOA [14]

XOR/XNOR based [13]

K = 6 [22]

Proposed work [T8]

Error rate (ER)

58.9%

93.5%

61.97%

19.14%

MED

–

–

153.69

3.12

SNR

–

–

Static power

–

–

23.825 4.2 uw

0.024 uw

7 Conclusion The approximate multipliers are implemented and used to design ADCT. The SNR is increased up to 2.52% using the combination of Wallace multiplier and reduced partial product method. The proposed architecture gives less error rate and higher SNR at a cost of static power and core area as shown in Table 6. The proposed architecture is having less error rate as compared to [22] and improved SNR. The static power is less. The implementation is optimized in terms of core area and delay as shown in Table 4. The path delay is 1039ps for T9 which is same as T12 corresponding to 962.46 MHz. The core area is reduced up to 27.79%, and an improvement in SNR is achieved up to 3.44% at a cost of 20.84% area over head. Acknowledgements The implementation and experimental work are conducted at EDA Lab, VSSUT, Burla. We acknowledge the financial support extended by TEQIP-III, VSSUT, Burla.

References 1. Yang T, Ukezono T, Sato T (2019) Design of a low-power and small-area approximate multiplier using first the approximate and then the accurate compression method. In: Proceedings of the 2019 on great lakes symposium on VLSI, pp 39–44 2. Kim S, Kim Y (2017) High-performance and energy-efficient approximate multiplier for errortolerant applications. In: International SoC design conference (ISOCC), Seoul, pp 278–279 3. Osta M, Ibrahim A, Chible H, Valle M (2017) Approximate multipliers based on inexact adders for energy efficient data processing. In: New generation of CAS (NGCAS), Genova, pp 125–128 4. Kavipranesh VV, Janarthanan J, Amruth TN, Harisuriya TM, Prabhu E (2018) Power and delay efficient exact adder for approximate multiplier. In: International conference on advances in computing, communications and informatics (ICACCI), Bangalore, pp 1896–1899 5. Liu W, Zhang T, McLarnon E, Neill MO, Montuschi P, Lombardi F (2019) Design and analysis of majority logic based approximate adders and multipliers. In: IEEE transactions on emerging topics in computing 6. Varma KR, Agrawal S (2018) High speed, low power approximate multipliers. In: International conference on advances in computing, communications and informatics (ICACCI), Bangalore, pp 785–790 7. Yadav P, et al (2018) Low power approximate multipliers with truncated carry propagation for LSBs. In: IEEE 61st international midwest symposium on circuits and systems (MWSCAS), Windsor, ON, Canada, pp 500–503

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8. Venkatachalam S, Lee HJ, Ko S (2018) Power efficient approximate booth multiplier. In: 2018 IEEE international symposium on circuits and systems (ISCAS), Florence, pp 1–4 9. Ravi S, Nair GS, Narayan R, Kittur HM (2015) Low power and efficient Dadda multiplier. Res J Appl Sci Eng Technol 53–57 10. Sampson A, Nelson J, Strauss K, Ceze L (2014) Approximate storage in solid-state memories. ACM Trans. Comput. Syst. 32(3, 9)L1–23 11. Han J, Orshansky M (2013) Approximate computing: an emerging paradigm for energyefficient design. In: 18th IEEE European test symposium (ETS), Avignon, pp 1–6 12. Chippa VK, et al (2013) Analysis and characterization of inherent application resilience for approximate computing. In: DAC 13. Yang Z, Jain A, Liang J, Han J, Lombardi F (2013) Approximate xor/xnor-based adders for inexact computing. In: Proceedings of the nanotechnology (IEEE-NANO), pp 690–693 14. Mahdiani HR, Ahmadi A, Fakhraie SM, Lucas C (2010) Bio-inspired imprecise computational blocks for efficient VLSI implementation of soft-computing applications. In: IEEE transactions on circuits and systems I: regular papers, vol 57, no 4, pp 850–862 15. Yang T, Sato T, Ukezono T (2019) An approximate multiply-accumulate unit with low power and reduced area. IEEE computer society annual symposium on VLSI (ISVLSI). FL, USA, Miami, pp 385–390 16. Hashemi S, Bahar RI, Reda S (2015) DRUM: a dynamic range unbiased multiplier for approximate applications. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 418–425 17. Yang T, Ukezono T, Sato T (2018) A low-power yet high-speed configurable adder for approximate computing. In: IEEE international symposium on circuits and systems (ISCAS), Florence, pp 1–5 18. Ye R, Wang T, Yuan F, Kumar R, Xu Q (2013) On reconfiguration-oriented approximate adder design and its application. In: IEEE/ACM international conference on computer-aided design (ICCAD), pp 48–54 19. Bhardwaj K, Mane PS, Henkel J (2014) Power- and area-efficient approximate wallace tree multiplier for error-resilient systems. In: Fifteenth international symposium on quality electronic design, pp 263–269 20. Jain G, Jain M, Gupta G (2017) Design of radix-4,16,32 approx booth multiplier using error tolerant application. In: 6th international conference on reliability, infocom technologies and optimization (trends and future directions) (ICRITO), pp 314–320 21. Prajwal N, Amaresha SK, Yellampalli SS (2017) Low power ASIC implementation of signed and unsigned wallace-tree with vedic multiplier using compressors. In: International conference on smart technologies for smart nation (SmartTechCon), pp 750–753 22. Islam MK, Moznuzzaman M, Khatun MF, Yesmin R (2015) A proposed modification of baseline JPEG standard image compression technique. Int J Sci Eng Res 6(8):180–186 23. Neil HEW, Harris D (2010) CMOS VLSI design—a circuit and systems perspective, 4th edn. Addison Wesley

Carry Select Adder Using Binary Excess-1 Converter and Ripple Carry Adder S. Arunakumari, K. Rajasekahr, S. Sunithamani, and D. Suresh Kumar

Abstract Many processor architectures, such as digital signal processors and microprocessors, rely on arithmetic circuits. The efficient implementation and design of arithmetic units necessitates the creation of binary adder structures in a similar manner. A ripple carry adder has a tiny surface area yet is slower. Carry propagation is also one of the reasons why the total for each bit is generated sequentially after the preceding carry arrives. The primary idea behind this study is to replace the RCA in a normal CSLA with a binary to excess-1 converter (BEC) to achieve high speed, area efficiency, and low power consumption. The following architectures are implemented using Verilog HDL as a programming language, and their simulation results are also shown. Keywords Binary to excess-1 converters (BEC) · Carry select adder (CSLA)

1 Introduction The large chip designing became easy by this complex chip design is implemented easily only by using VLSI systems. By this, major work was done easily in the limited amount of time so it is most efficient and fast way of implementation of chip design. S. Arunakumari Department of ECE, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India K. Rajasekahr (B) Department of ECE, N S Raju Institute of Technology (Autonomous), Sontyam, Andhra Pradesh, India e-mail: [email protected] S. Sunithamani Department of ECE, Koneru Lakshmaiah Education Foundation, Vaddeswaram, Guntur, Andhra Pradesh, India e-mail: [email protected] D. Suresh Kumar Department of ECE, Lendi Institute of Engineering and Technology, Jonnada, Andhra Pradesh, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_30

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Our work was to the adding of the two numbers can be done fast and efficient manner. The carry select adder (CSLA) that consists of the RCA was being replaced by the (BEC-1) binary excess-1; by this replacement, the area and the power consumption were achieved through this modification. Our work was 128-bit addition which was achieved fast without any delay in the system by this adding of 128-bits becomes easy, and the results are being observed using the VLSI software [1]. Adding was the problem that to be overcome using this design; by this, space occupancy of the design was taken low and maximum power consumption was reduced to minimum efficient; adding of the numbers was done easily using the BEC properly, and we can achieve the outputs efficiently. The proposed 128-bit carry select adder compared with the carry skip adder (CSKA) and regular 128-bit carry select adder [2].

2 Literature Survey By using standard RCA–RCA, the number of the adders was increased; by this, the complexity of the system was increased and the increase in the adders; the delay will be seen longer due to the carry that was forwarded to the next input of the system; the delay will increase; by the delay, the maximum amount of the power was drawn by the system [3]. Not only the power was increased by adding the various number of adders of the space was also increased; by this, the complexity was also increased designing the circuit. Just by replacing the system by removing the RCA and replacing it with a BEC, the adders can be reduced to maximum extent and the processing speed was also increases. By this replacement, space occupancy can be limited. Power drawn by the previous system was more compared to the modified version of this system. By this, the performing addition of 128-bit was done fast and efficient manner. Reduction of adder cells will decrease the area occupancy and power consumption [4].

3 Existing Technique The existing technique that which consists of the RCA–RCA and the mux which was placed along with this RCA was connected in series, thereby the output of the one system was given input to another system [5]; the below diagram shows the regular RCA–RCA regular system (Fig. 1). A two-bit RCA is taken with A and B as input, and carry input is given to first RCA. Inputs for first RCA are A [1:0] and B [0:1]. The sum of two-bit RCA is 2, and carry out is 1. This is based on the basic operation of RCA. The carryout is given to a multiplexer and then consider a two RCA of two-bit each A [2:3], B [2:3] inputs are given to RCA. Enabling bits 0 and 1 are given to RCA’s, and now the sum is 4 and carry is 2. The output 4 is given to the 6:3 multiplexer, and output is based on

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291

Fig. 1 RCA–RCA architecture

chosen multiplexer. Multiplexer sum is 2, and the carry output of RCA’s is given to CY. The output of the 6:3 multiplexer is given to succeeding 8:4 multiplexer. Next, consider a 2 RCAs of 3-bit each A [4:6], B [4:6]as inputs, enabling bits 0 and1 are given for this sum is 6 and carry is 2. Sum is given to 8:4 multiplexer; multiplexer sum is 3, and the carry of RCA’s is given to CY; this mux output is given to the succeeding multiplexer 10:5. Now, take 2 RCAs of 4-bit each A [7:10], B [7:10]as inputs, enabling bits 0 and1 are given for this sum is 8 and carry is 2. Sum is given to 10:5 multiplexer; multiplexer sum is 4, and the carry of RCA’s is given to CY; this mux output is given to the succeeding multiplexer 12:6. At last consider 2 RCAs of 4-bit each A [11:15], B [11:15] as inputs, enabling bits 0 and1 are given. For this, sum is 10 and carry is 2. Sum is given to 12:6 multiplexer; multiplexer sum is 5, and the carry of RCA’s is given to CY, and carry out is taken from CY. This is the basic operation RCA–RCA (regular) 16-bit CSLA.

4 Proposed Technique This proposed technique was that which RCA was being replaced by the BEC; by this, the actual gate level of the circuit was reduced at minimum; by this, reduction of the number of gates of the power taken by each full adder circuit was greatly reduced. This is the main modification of this circuit design. By the addition of the binary excess-1 converter, the computation of the addition was done fast and accurate; by this, the time consumption and the power were being conserved (Fig. 2). Linear CSLA with modifications for 16-bits: It is divided into eight groups. Below are the steps that lead to a delay and the methodology for evaluating an area. The area and delay methods for Group 1 to Group 4 are the same as for 16-bit RCSLA. (2) Depending on the arrival of c (10), c (9), c (4), c (5), c (4), c (4), c (4), c (4), c (4),

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Fig. 2 Proposed RCA with BEC architecture

c (4), c (4), c (4), c (4), c (4), c (4), c (4), c (2). The modified regular linear CSLA has 727 gates in total.

5 Results and Discussions See Figs. 3, 4, 5, 6, 7, 8, 9, and 10.

Fig. 3 16-bit CSLA using RCA

Fig. 4 16-bit CSLA using BEC-1

Carry Select Adder Using Binary Excess-1 Converter …

Fig. 5 32-bit CSLA using RCA

Fig. 6 32-bit CSLA using BEC-1

Fig. 7 64-bit CSLA using RCA

Fig. 8 64-bit CSLA using BEC-1

Fig. 9 128-bit CSLA using RCA

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Fig. 10 128-bit CSLA using BEC-1

6 Conclusion This study proposes a simple method for reducing the size and power of CSLA architecture. This work’s reduced number of gates provides a significant benefit in terms of both space and electricity savings. For VLSI hardware implementation, the modified CSLA design is low area, low power, simple, and efficient. Using the XILINX ISE Tool, the RCA–RCA and RCA–BEC structures are simulated, synthesized, and implemented using the VERILOG language. In the future, it may be possible to replace the BEC with a different design that provides higher performance than the RCA–BEC combo. In laptops nowadays, we use 64-bit microprocessors. As a result, if the number of bits is raised, it can be increased up to.

References 1. Kala Priya K, Satyanarayana Raju K (2014) Carry select adder using BEC and RCA. Int J Adv Res Comp Commun Eng (IJARCCE) 3(10) 2. Ceiang TY, Hsiao MJ (1998) Carry-select adder using single ripple carry adder. Electron Lett 34(22):2101–2103 3. Ramkumar B, Kittur HM (2012) Low power and area efficient carry select adder. IEEE Trans 20 4. Devi P, Girdher A, Singh B (2010) Improved carry select adder with reduced area and low power consumption. Int J Comp Appl 3(4):14–18 5. Kim Y, Kim LS (2001) 64-bit carry-select adder with reduced area. Electron Lett 37(10):614– 615 6. DeHon A, Wilson MJ (2004) Nanowire-based sub lithographic programmable logic arrays. In: Proceedings of the International symposium on field-programmable gate arrays, pp 123–132 7. Kim Y, Kim L-S (2001) 64-bit carry-select adder with reduced area. Electron Lett 37(10):614– 615 8. Rabaey JM (2001) Digital integrated circuits—a design perspective. Prentice-Hall, Upper Saddle River, NJ 9. Palnitkar S (2005) Verilog HDL: a guide to digital design and synthesis, 2nd edn. 10. Bedrij OJ (1962) Carry-select adder. IRE Trans Electron Comput 340–344

Design and Analysis CMOS-Based DRAM Cell Structures for High-Performance Embedded System Prateek Asthana, Ritesh Kumar Kushwaha, Anil Kumar Sahu, and Neeraj Kumar Misra

Abstract Dynamic random access memory (DRAM) has performed the basic element for designing in embedded system. Various DRAM cell topologies in deep submicron level are designed and analyzed in this study. Memory blocks have become a critical component for overall system performance in today’s digital data processors and controllers. Selecting a DRAM cell structure from the many options increases design time and effort greatly. DRAM topologies in two, three, four transistor are implemented on 32 nm technology scale. A three-transistor and one-diode-based DRAM topology is also designed and compared with all the structures. The threetransistors and one-diode implementation shows significantly better retention time with comparable average power consumptions. The power dissipation, retention time, and read and write access times of the cells are compared. Tanner EDA is used to perform all design and simulation work. Keywords DRAM · Retention time · CMOS · Power consumption · 32 nm technology

1 Introduction Memories are a crucial part in the design in any electronic device that requires data storage. Data are stored in memories, which may then be retrieved as needed. The two types of memory utilized in current electronic systems are random access memory (RAM) and read-only memory (ROM). Random access memory can be further classified into dynamic and static random access memories based on their way of P. Asthana (B) · A. K. Sahu · N. K. Misra Department of Electronics and Communication Engineering, Bharat Institute of Engineering and Technology, Hyderabad, India e-mail: [email protected] R. K. Kushwaha Department of Electronics and Communication Engineering, Chandigarh University, Gharuan, Mohali, Punjab, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_31

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storing the data bits. Static random access (SRAM) is more costly than dynamic random access (DRAM), but it uses less energy. Per bit of memory, SRAM consumes more transistors. In comparison to DRAM, SRAM is more static and quicker. Cache memories are the most common application for them. In contrast to SRAM, DRAMs are dynamic and slower. DRAMs are mostly utilized as primary memory. DRAM is commonly used in personal and mainframe computers, as well as engineering workstations, for primary memory. For storing a single bit in logic circuits, DRAM memory cells are utilized for read and write operations. A single DRAM cell may store logic high bit of data in the form of charge inside the capacitor. The capacitor’s charge diminishes with time. As a result, refreshing signals are utilized to keep the data in the capacitor up to date. When the data are read by the read, it also refreshes it. The number of transistors utilized in the design distinguishes these designs. Power dissipation increases as the number of transistors grows. DRAM is a type of random access memory that is used as the main memory for workstations. It is one of the most used and cost-effective random access memories. The charge that is stored in a memory cell changes with time. DRAM cells with low power consumption and a small footprint are favored for high-density memory [4, 5]. Embedded DRAM cell structure is built into a logic-optimized integrated circuit (such as an applicationspecific integrated circuit, microprocessor, or whole system on a chip) (eDRAM). Embedded DRAM necessitates DRAM cell designs that can be manufactured without interfering with the manufacturing of high-performance logic’s fast-switching transistors, as well as modifications. The manuscript is organized as follows. Dynamic random access memory is discussed in Sect. 2. Section 3 discusses the schematics of different types of DRAM topologies along with their working output waveform. The three-transistors and one-diode DRAM cell structure is discussed in Sect. 4. A comparison of DRAM cell characteristics is shown in Sect. 5, while Sect. 5 concludes the manuscript.

2 Dynamic Memory DRAM may store binary data as charge inside a capacitor, and the value of the stored bit is determined by the absence or presence of stored charge. DRAM is a type of memory that can write and read single bits of data. In comparison to SRAM, it uses lesser number of transistors per bit. Storage node suffers from junction leakage current as the stored charge diminishes with time. The major source of power consumption is leakage current. As a result, periodic updating of data must be kept in order to avoid data deterioration and keeping it for a longer period of time is one of the disadvantage as compared to SRAM. DRAM structures tiny memory cell having low cost and high density. The output circuitry plays a vital role in functioning of DRAM cell. The output circuitry for the DRAM cell consisting of a sense amplifier and precharge transistor is shown in Fig. 1. We used three distinct DRAM cells in this paper: 2T, 3T, and 4T. All of the circuit’s read and write operations are shown using TSPICE. The power dissipation, retention

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Fig. 1 Output circuitry for DRAM cell structure

time and read and write access times of the cells are compared to determine the best DRAM cell structure.

2.1 Two-Transistor DRAM The two-transistor DRAM cell has one read transistor performing reading operation, while the other transistor is performing the writing operation. The charge is held in a parasitic capacitor in this reduced form of a 3T DRAM cell. The capacitance at the storage node is the sum of parasitic capacitances of T2’s gate and T1’s drain [7]. The write bit line (WBL) is enabled during the write operation, and the WWL, i.e., write word line is set to high logic, causing the first transistor to switch on and store charge in the parasitic capacitance. For read operation, read word line (RWL) is switched to a logic low voltage, causing the second (read) transistor to switch on. When the value 1 is placed in the memory, a large current is pulled from RBL to RWL. As the leakage current is high, the 2T dram cell has a very short holding time. The current that leaks in between the terminals of T2, as well as the current that leaks between the gate and the substrate, hence, the transistor is unable to hold the value for a longer time period. The cell’s retention time usually determines, the frequency of updation. As a result, the data retention of this 2T DRAM cell necessitates additional refresh cycles. As technology improves, the time required to retain information will decrease. The benefits of a 2T DRAM cell include the fact that it takes up less space and that the read operation is non-caustic. Figure 2 shows the structure of 2T DRAM cell. The working waveform performing write and read logic 1 and 0 is shown in Fig. 3.

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Fig. 2 Two-transistor DRAM cell structure

Fig. 3 Working waveform of DRAM cell performing write 1, read 1, write 0, and read 0 operation

Fig. 4 Three-transistor DRAM cell structure

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Fig. 5 Working waveform of DRAM cell performing write 1, read 1, write 0, and read 0 operation

2.2 Three-Transistor DRAM Three transistors make up a 3T DRAM cell. Write access is provided by transistor M1, while read access is provided by transistor M3. The storage device is the transistor M2, is turned on and off, based on the charge at its gate capacitance. The parasitic capacitor is used to store data here. As the word line write signal is enabled, the charge from the write bit line is stored in the gate of M2 via the transistor M1 during the write operation. As the data are read via the bit line, the word line is activated. The read procedure is fast and non-caustic in this type of cell as well. In comparison to other DRAM circuits, the 3T DRAM cell has the longest retention duration; hence, it is commonly employed in on-chip memory systems [2]. Figure 4 shows the structure of 2T DRAM cell on 32 nm technology scale. The working waveform performing write 1, write 0, and read 0 and 1 operations are showed in Fig. 5.

2.3 Four-Transistor DRAM Four transistors make up a 4T DRAM cell. Two transistors are utilized for read and write operation, respectively. The word line is activated during the write operation, as the data are written from the pair of bit lines and stored in the form of charge. The gate and parasitic capacitances of the node linked to a logic high voltage bit line to store charge. The cell must be updated on a regular basis as there is no present channel given in the storage nodes for recovering data lost due to leakage. The transistor is used to discharge the voltage on the bit line to the ground during the read operation. The storage node charge is not degraded in this case; thus, the read operation is not

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Fig. 6 Four-transistor DRAM cell structure

Fig. 7 Working waveform of DRAM cell performing write 1, read 1, write 0 and read 0 operation

harmful. The 4T DRAM cell has a long retention period; thus, it can retain data for a long time [1]. Figure 6 shows the structure of 2T DRAM cell on 32 nm technology scale. The working waveform performing write 1, write 0 and read 0 and 1 operations are showed in Fig. 7.

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Fig. 8 Three-transistor and one-diode DRAM cell structure

3 Three-Transistor and One-Diode DRAM A modified DRAM cell structure is developed from traditional 3T DRAM cell. The 3T1D has an advantage over the SRAM cell in terms of process variation resistance, which allows it to be utilized in small feature sizes. Another benefit of 3T1D DRAM is that it maintains its speed even after reduction of the size of the memory. The data value is stored in 3T1D DRAM using a gated diode rather than a capacitor. When compared to earlier DRAM cell designs, the lack of a capacitor results in a significant reduction in power usage [3, 6]. Figure 8 shows the structure of 2T DRAM cell on 32 nm technology scale. The working waveform performing write 1, write 0 and read 0 and 1 operations are showed in Fig. 9. The write bit line activates the T1 transistor for the write operation. The storage node S stores either a Vdd − Vth voltage or a 0 V depending on the logic value. This voltage is result of charge accumulating on the gates of devices T2 and D1. The capacitance of the gated diode (D1) is high, when Vgs is larger than Vth , and low in otherwise. In the inversion layer, there is a little quantity of charge that is stored. Read bit line is used to read the cell.

4 Performance Parameter Analysis Average power consumption, write and read access times and retention time for 2T, 3T, 4T, and 3T1D DRAM cells are analyzed. An estimation of the average power

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Fig. 9 Working waveform of DRAM cell performing write 1, read 1, write 0 and read 0 operation Table 1 Performance parameter comparison Write access time Read access time Retention time DRAM cell (ps) (ps) (µs) topology 2T 3T 4T 3T1D

15.31 19.53 35.73 299.35

65.31 87.82 100.87 103.41

2.11 3.71 2.61 45.51

Average power consumption (µW) 1.46 1.66 1.73 1.66

consumption of the cell design is calculated as it is subjected and the response time of each topology under all four conditions, i.e., reading and writing ‘1’ and ‘0’. A comparison between the parameter are shown in Table 1.

5 Conclusion The study of 2T, 3T, 4T, and 3T1D DRAM cell for average power consumption, read access time, write access time, and retention time has been carried out. Analysis of read and write access times shows that the smallest cell, i.e., 2T DRAM cell has the least value, while the dioide-based DRAM cell has significantly larger value as compared to other cells. One of the most important characteristic is retention time or the time to refresh the cell; 3T1D DRAM cell has the highest retention time out of all

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these cells. Average power consumption for the cells is around µW. A full memory cell can be constructed with the 3T1D DRAM cell for high-performance embedded systems as these cells would require very less refresh time.

References 1. Akashe S, Mudgal A, Singh SB (20122) Analysis of power in 3T dram and 4T dram cell design for different technology. In: 2012 world congress on information and communication technologies. IEEE, pp 18–21 2. Asthana P (2020) Analysis of dram cell designs for nanometer-scale memories 3. Asthana P, Mangesh S (2014) Capacitor less dram cell design for high performance embedded system. In: 2014 international conference on advances in computing, communications and informatics (ICACCI). IEEE, pp 554–559 4. Asthana P, Mangesh S (2014) Design and implementation of 4T, 3T and 3T1D dram cell design on 32 nm technology. Int J VLSI Des Commun Syst 5(4):47 5. Asthana P, Mangesh S (2014) Performance comparison of 4T, 3T and 3T1D dram cell design on 32 nm technology. JSSATE, ICCSEA, SPPR, VLSI, WiMoA, SCAI, CNSA, WeST, pp 121–133 6. Asthana P, Mishra L (2018) High-speed electronic memories and memory subsystems. In: Advanced electronic circuits: principles, architectures and applications on emerging technologies, p 127 7. Gupta T, Naik P (2017) Comparative analysis of 2T, 3T and 4T dram CMOS cells. In: 2017 international conference on information, communication, instrumentation and control (ICICIC). IEEE, pp 1–6

Optimized RTL Design of a Vending Machine Through FSM Using Verilog HDL Pulumati Chidananda Datta, Chappa Vinay Kumar, Rajan Singh, and Kavicharan Mummaneni

Abstract In this paper, we demonstrate a register-transfer level schematic of a vending machine that facilitates understanding of the actual design and precise circuit analysis. The proposed design shows minimum power consumption for a good range of frequencies. Modeling the machine is done using the finite state machine technique, which uses a list of its states. Subsequent steps include optimization techniques, deriving Boolean expressions, and describing the design (behavioral modeling) using Verilog HDL in Xilinx VIVADO and Xilinx ISE. As a result, we get a readable RTL schematic of a vending machine that accepts three currencies and operates on three different products. For the proposed design, reduced power consumption of 33.59 mW and a reduced gate delay of 1.024 ns at a frequency of 5 MHz are estimated. Design in this paper shows a brief RTL schematic of a fully functional vending machine using mealy finite state machine (FSM). An advantage of this approach is that one can know the flow of signals from input to output. With this, managing the power and timing of the device becomes flexible. One can sort out the requirement of a particular block in the device. In turn, actual power management can be achieved. This paper aims to design a fully functional vending machine in-depth, to the point where a designer can feel the actual hardware producing logic of his interest. Keywords RTL · FSM · Verilog HDL · Xilinx VIVADO · Xilinx ISE · Vending machine · Mealy machine · Moore machine · Boolean · Flip flop · Artex XC7A100T · Spartan3E XA3S100E

P. Chidananda Datta (B) · C. Vinay Kumar · R. Singh · K. Mummaneni Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam, India e-mail: [email protected] C. Vinay Kumar e-mail: [email protected] K. Mummaneni e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_32

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1 Introduction We live in a generation where automation replaces human activity and makes work easy. A vending machine is one such thing that can diminish the waiting time of a customer in getting a product of his interest. A vending machine [1] is an automatic machine that sells the products that a designer wants to sell. A designer can describe a vending machine [2] for performing various activities [3], and it can dispense products for a selected price tag given by a designer, the products like drinks, chocolates, water bottles, and other food items [4], newspapers [5], and many more. It delivers a product to the users based on the amount of money inserted and the selection of the product he made. It is a 24 × 7 usage unit that requires a standard power supply connection to perform all functions. It consists of simple electro-mechanical systems that help automate the vending process, and it can be easily updated with the latest possible features [6, 7]. It can be used by dumping the HDL code into an FPGA board [8]. Step 1 Step 2 Step 3 Step 4 Step 5

Step 6

Users search through the variety of products and decide what they want. When the users decide and select the product. The users insert money equivalent to or more than the product’s price in the form of cash into the vending machine. The users give the desired product’s corresponding input using a keypad present on the machine. The vending machine delivers the product, and it falls in the delivery box. The users collect their product from that box located in the bottom section of the machine. At the end, the machine returns the change (if any), and the users collect it.

FSM: Finite state machine, the transition from one state to another state (next state), is described in terms of input and present state (mealy machine) or in terms of the present state itself (Moore machine). A finite state machine means the circuit that we have designed can operate on finitely many states [9]. That is, the number of states of the circuit is always finite. That can happen only in digital because we have finitely many digits in digital. However, in an analog domain, we can have infinite possibilities, so FSM is nothing but a digital circuit with a finite number of states. FSM is broadly classified into two categories: a Moore machine and the other is a mealy machine [10]. Moore machine: The output is only a function of the present state in the Moore machine. The state is nothing but the stored value inside the system, representing the system’s present condition or the condition in which the system is operating. Mealy machine: In the mealy machine, the output is the function of the present state and the present input. We can convert mealy to Moore but not vice versa. In this paper, we will discuss developing a vending machine using the concept of FSM [11]. The machine operates among a finite number of states performing required transactions. In this paper, we start our discussion with the design of FSM. Here, we use an FSM of six levels, and each level has its meaning and weight. The entire process

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flow can be visualized from it. We use a three-bit binary string to represent each of six states as we can make eight combinations using them. This machine can accept three currencies, three product requests, an input to cancel the process, and input for no activity. Altogether the machine has to work on eight different inputs, these inputs are specified to the machine using a three-bit binary string. Moreover, we also have eight different outputs: five different change outputs and three different product outputs. Again, it is represented by a three-bit binary string. Then we use appropriate methods, including reduction techniques in getting Boolean expressions, described using HDL (Verilog). RTL schematic is seen, power analysis [12] is made, and necessary conclusions are made accordingly.

2 Implementation The entire process flow is described using a flow chart Fig. 1. As discussed earlier, this machine can handle three different products and accepts three different values of money. As a user starts using this machine, he first has to insert some money according to his need, and then he can select a product of his interest. If inserted money value is greater than or equal to the worth of the product, he will get the product he selected, and else he will be given an option to insert money again. Once a user inserts sufficient money for a product of his choice, he can get it by selecting it. A user can terminate the process at many different stages and get back any remaining money. So, a process ends only when a user wants it to end. Until then, the machine will continuously accept inputs from user and acts accordingly. Nevertheless, the machine can give out one product at a time. The circuit got described using Verilog HDL without assuming any predefined values of delays (Fig. 2; Table 1). A clear understanding of actual design starts from a state representation Fig. 3. Our primary focus is on RTL design. The state diagram plays an essential role in this discussion, and a clear representation is complex. Representation is done using two different state diagrams for a single machine, including all the state changes happening in the machine. Initially, the machine will be at state_0. When a user inserts rupees 10, the state gets updated to state_1 and gives an output of ‘0.’ Parallelly, every time the user inserts a rupee 10, the state gets updated to the new state and gives an output of ‘0’ unless the present state is state_5. Any money inserted will be returned at this stage, as it is the maximum state available in the machine. An input of rupees 50 can increment state number by 5. Considering a case where the present state is state_3, an input of rupees 50 will increment the present state to state’ 5’ and produce an output of C2. In this way, the execution of the initial step is managed (Table 2). In this state diagram, Fig. 4 specifies the management of products done by the machine. When the machine is in some nonzero states. Accordingly, a product can be drawn out from it, when the machine is in state 3, products P1(|10) or P2(|30) can be drawn out by selecting that specific input, and if a user tries to get product p5(|50) being in this state, the output will be ‘0,’ and present state remains unchanged. A user can

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Fig. 1 Process flow of the machine

Fig. 2 Brief look at design flow

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Optimized RTL Design of a Vending Machine … Table 1 Description for symbols used in Fig. 3

309

Available money

Equivalent state

|0

State_0

|10

State_1

|20

State_2

|30

State_3

|40

State_4

|50

State_5 Meaning

Symbol C1

Change of |10

C2

Change of |20

C3

Change of |30

C4

Change of |40

C5

Change of |50

Fig. 3 Detailed state transition diagram of the vending machine

Table 2 Description for symbols used in Fig. 4

Symbol

Meaning

Worth

P1

Product 1 (refreshment)

|10

P2

Product 2 (breakfast box)

|30

P3

Product 3 (lunch box)

|50

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Fig. 4 Detailed state transition diagram of the vending machine

get product P3 only when he is in state 5. A user can get product P1 when he is in any of the nonzero states. Few such cases will be discussed in the simulation part of this work (Table 3). As shown in Fig. 5, ‘a,’ ‘b,’ and ‘c’ are the primary inputs to this machine. There were also two input signals, clock and reset. Reset is used only once to initiate flipflops, and the clock signal makes flip-flops work synchronously. According to the action performed by a user, a specific bit stream is generated from input devices and fed to the VMAC. Then depending on the present state and present input, VMAC generates output bits representing change and products. Then these output bits are fed as inputs to output devices.

3 Results and Discussion These results shown in Tables 4 and 5 were obtained by running Verilog HDL code in Xilinx ISE concerning the family of development boards Artix 7 and Spartan 3E. The relevant discussion is made in the following part of this paper. From Fig. 6, three input lines to specify an action at the input of the machine, three output lines (collection) for product output, and five output (collection) lines

Optimized RTL Design of a Vending Machine … Table 3 Pin diagram variables description

abc

311 Input

000

10 rupees

001

20 rupees

010

50 rupees

111

00 rupees

100

Select P1

101

Select P2

110

Select P3

011

Cancel process/reset Output

Fig. 5 Pin diagram of the vending machine

ch[1]

10 rupees change

ch[2]

20 rupees change

ch[3]

30 rupees change

ch[4]

40 rupees change

ch[5]

50 rupees change

pr[1]

Refreshment

pr[2]

Breakfast box

pr[3]

Lunch box

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Table 4 Total power (watt) and total delay (nanoseconds) analysis (reference: Artix 7) Artix 7 (XC7A100T) (MHz)

Time delay (ns)

Power analysis (W) Dynamic power

Static power

Total power

5

1.024

0.00022

0.08216

0.08237

10

0.845

0.00008

0.08223

0.08224

Table 5 Total power (watt) and total delay (nanoseconds) analysis (reference: Spartan 3E) Spartan 3E (XC3S100E) (MHz) Time delay (ns) Power analysis (W) Dynamic power Static power Total power 5

3.032

0.00000

0.03359

0.03359

10

3.032

0.00054

0.03360

0.03414

Fig. 6 RTL schematic of the design

for a change. As this machine needs six states to work, we used three flip-flops, can store three bits altogether, and can store eight different states. Different analyses can be carried out using this RTL schematic according to requirements. The total power consumed by a device is a sum of static and dynamic power. Static power depends on the quality and quantity of the devices used, as it happens due to leakage currents. In about every case, a significant part of the total power

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is contributed by the static power [12]. Dynamic power depends on the frequency of switching and the number of switches in the device, and it is a user-dependent parameter. From Tables 4 and 5, it is clear that static power is almost independent of the frequency used [12], whereas dynamic power changes drastically with frequency. Artex XC7A100T provided minimum total delay compromising on power consumed, whereas family Spartan 3E XC3S100E consumes less power compromising on delay. Choosing one of them is an application-dependent process. Total delay produced by the device is the sum of gate delay and net delay. Gate delay is caused because of gates used, and it depends on the quality and quantity of gates used in the design. Net delay is caused because of wiring and interconnects used in the design, and it depends on the efficiency of connections used in the device. In the RTL schematic Fig. 6, one can certainly see the interconnects and connections between gates. With it, better designs could become possible.

4 Simulation Results and Discussion Simulations were performed using Xilinx VIVADO. Every simulation result displays results for its specified case along with some exceptional cases. State transitions take place only at the positive edge of the input signal clock. In this design, every input has to produce output because of the present state and has to update the present state to its next state. Accordingly, it has to stay long enough till the positive edge clock appears. Initially, all the flip-flops were reset to ‘0.’ From Fig. 7, the initial input to the device is P1. Refer Tables 1, 2, and 3. As the present

Fig. 7 Vending refreshment (product P1)

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Fig. 8 Vending breakfast product (product P2)

state is state 0, the output will be 0 for input P1, and the next will be the same as the present state. Similarly, P2 and P3 output remain 0, keeping the next state unchanged. Now when the input is the money of 10 rupees, the state gets updated to state 10. For the present input of P1, the user will get refreshment as product output, and the state gets updated to state 0. From Fig. 8, the initial input of 50 rupees updates the state to state 5, and then the user receives the breakfast box product for input P2. The state gets updated to state 2, consecutive inputs of rupees 20 and rupees 10, the state gets updated to state 5, now in this state because of input P3 user gets lunchbox product. From Fig. 9, because of the consecutive inputs of rupees 10, rupees 20, and rupees 50, a user immediately receives a change of rupees 30 and state gets updated to state 5, then for the input P3, user gets a lunchbox product, and the state gets updated to state 0. So, it is clear that the process continues till the user ends it. The state only gets updated for the positive edge of the input clock signal. For this reason, input has to be maintained for proper durations. As a final note, the output signal because of previous input and the updated state has to be ignored (small bumps in output signal) (can be used for setup and hold time considerations) and the same because of present input is considered.

5 Conclusion Design in this paper has got described in the behavioral style of modeling, and it became possible with the concept of FSM. Because of this approach, the RTL schematic contains logical gates instead of combinational blocks, reducing the total number of gates used. This approach successfully avoids combinational blocks like multiplexers in the RTL schematic, the average power consumed is reduced to less than 43% of the existing design’s average power [12], an in-detail RTL schematic

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Fig. 9 Vending lunchbox and returned change (product P3)

of a desired vending machine is addressed, and the design flow becomes readable. It is a model designed after applying appropriate reduction techniques. As a result, we observed the lowest power consumption when referring to a Spartan designing board. Furthermore, we observed a reduced delay time while referring to an Artix designing board. A board can be selected accordingly with an application. Spartan board can be used to decrease power consumption, while the Artix board can increase throughput. Simulations results validated the perfect functioning of a fully functional vending machine.

References 1. Sibanda V, Munetsi L, Mpofu K, Murena E, Trimble J (2020) Design of a high-tech vending machine. Proc CIRP 91:678–683 2. Gaur A, Mathuria D, Priyadarshini R (2018) A simple approach to design reverse vending machine. In: ACM Woodstock conference 3. Bodhale AP, Kulkarni JS (2017) Case study on different vending machines 4. Mustafa MS, Al-Mayyahi MHN, Barnouti NH (2019) Design and implementation of vending machine embedded control system using FPGA. In: Proceedings of the international conference on information and communication technology, pp 25–30 5. Nimisha K, Mathi I (2017) Smart newspaper vending machine. Asian J Appl Sci Technol (AJAST) 1(1):131–136 6. Kadu S, Jadhav N, Raju Tupe P, Sadigale P (2020) Industrial vending machine

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7. Murena E, Sibanda V, Sibanda S, Mpofu K (2020) Design of a control system for a vending machine. Proc CIRP 91:758–763 8. Jadhv R, Jejurkar M, Kave P, Chaudhari HP (2017) Smart coffee vending machine using RFID. Adv Wireless Mobile Commun 10(4):793–800 9. Monga A, Singh B (2012) Finite state machine based vending machine controller with autobilling features. arXiv:1205.3642 10. Alrehily A, Fallatah R, Thayananthan V (2015) Design of vending ma-chine using finite state machine and visual automata simulator. Int J Comput Appl 115(18) 11. Gladyshev P, Patel A (2004) Finite state machine approach to digital event reconstruction. Digit Investig 1(2):130–149 12. Verma G, Papreja A, Shekhar S, Maheshwari S, Virdi SK (2016) Low power implementation of FSM based vending machine on FPGA. In: 2016 3rd international conference on computing for sustainable global development (INDIACom). IEEE, pp 2054–2058

Advances in Sensing Methodology for Resistive RAM Shaik Shaima, G. Jagaruthi, Sai Vandana, and E. Raghuveera

Abstract Recent days sensing technology in the memory play a vital role, in the “Von Neumann Bottleneck” method, there should be a specified memory was given for the read and write operations. The Sense Amplifier is a key circuit in the edge of power efficient, high-speed random-access memories. This paper describes the design of sense amplifier for a given random access memory and more elaborately on Resistive RAM. Reading of the memory is most important in all memories and it is time-consuming, this paper aims to improve the speed of reading in the memories especially in Resistive RAM. Resistive RAM was built on 1Resistor-1Transistor configurations, the data is stored in the form of resistance, and which is non-volatile in nature. From the resistor we can retrieve the data which is in the form of resistance using the time-based sense amplifier. The sense amplified designed to optimize the delay and to improve the speed of sensing. The schematic of sense amplifier is verified using PYXIS environment with 130 nm CMOS-technology node and it works fine and helps us to improve the reading operations efficiently in the Resistive RAM. These are used in many applications and different fields like security, neuromorphic computing, and non-volatile logic system. Keywords RRAM · Time-based sense amplifier · Non-volatile · 1Resistor-1Transistor

1 Introduction RAM (Random-Access memory) it refers to the volatile or non-volatile memory. The date transfer between multiple memories is one of the key issues in reducing performance in the computing systems. The energy need to access memory from the cache to off-chip DRAM [1] is not acceptable range. Pedram et al. [2] pointed out that for a given 16-bit addition in a 45 nm CMOS technology the energy required for DRAM access is about 3556x, the latency is nearly equal to 100 ns [3], the same S. Shaima · G. Jagaruthi · S. Vandana · E. Raghuveera (B) Koneru Lakshmaiah Education Foundation, Green Fields, Vaddeswaram, Guntur, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_33

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is for 32-bit adder is about 4 ns [4], the data transfer latency results in a specific portion of delay in traditional architecture. Having many advantages with DRAM and SRAM as high speed, high density, high capacity, but they are volatile and the contents or the data will be lost when the power failure occurs. When it comes to non-volatile memory [5] like flash memory, it has its own disadvantages like low performance and low operation speed, where read and write speeds are very slow, it requires high voltage to write which is greater than 10 V. Embedded static random-access memory (SRAMs) are commonly embed into system-on-chip (SoC) architectures to high density of components and better speed. Numerous applications of the embedded SRAMs will affect the performance towards energy consumption, speed, and reliability [6–8]. The most key circuit in the periphery of embedded SRAMs is sense amplifier (SA) [9]. Therefore, designing a fast SA is a challenge [6]. The rest of the paper, the related work carried out is discussed in Sect. 2, the physical structure of ReRAM is discussed in Sect. 3, various sensing methods and the design of sense amplifier is discussed in Sect. 4, results and discussions were described in Sect. 5 and finally the conclusions were made in Sect. 6.

2 Related Work The traditional sense amplifier of latch-type is firstly used in SRAM [10]. Invertors provide +ve feedback to decrease delay, the bit lines SA will attempt to discharge large capacitive bit lines during the decision phase, which increases delay and energy consumption. A High-impedance Input Latch-type Sense Amplifier (HILTSA) introduced by Kobayashi in 1993 [11], which does not require some decoupling at its input. [12–15]. In a Double-tail Sense Amplifier (DTSA), only is used for the input stage and another is used for latching stage. During the pre-charge phase to discharge the output nodes to ground. When the signal CLK is activated, voltage of Di nodes then drops monotonically with a rate, and an input-dependent differential voltage will build up. Compared with DLTSA and HILTSA, the DTSA has an advantage of the balance between speed, offset, and power [16]. The double tail enables both a large current in the latching stage for fast latching and a small current in the input stage (small M9) for low offset while the DTSA costs a larger area. With CMOS technology scaling, the variation of discharge delay of bit lines and the offset voltage of SAs become larger. Therefore, the delay between word line enables signal and the enabled signal of latch-type SAs must keep enough margins to ensure the voltage difference between bit lines BLP, and BLN is larger than the offset of SAs. In order to overcome the problem, a two-level ripple-domino SA is shown in Fig. 4 [17, 18]. Two-level ripple-domino SA (TLRDSA) does not need an enable signal. And, divided bit lines of local and global bit lines could achieve higher speed at the expense of larger area. Balanced Charge-transfer Sense Amplifier (BCTSA) [19]. This paper first adopted the BCTSA to SRAM, which had been studied for DRAM application. The BCTSA is a pair of NMOS transistors operated in the saturation region during the decision phase. CBLSA [20], the read operation starts turning on the transistor. During the

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pre-charge phase, transistors are on, forcing the bit lines and SA’s output nodes to the same voltage. When a bit cell is turned on, the current I cell will flow through the pre-charge device in the CBLSA. A hybrid current-mode sense amplifier (HCMSA) [21], which consists of a P-type current conveyor and a clamped data-line sense amplifier (CDSLA). The P-type current conveyor is composed of four PMOS transistors. The input resistance of current conveyor is low (ideally zero), which realizes a unity-gain current transfer characteristic from input to output. The subsequent circuit is a clamped SA for conversion to voltage mode, which is similar to the CBLSA. A modified hybrid bit-line sense amplifier (MHSA) [22]. During the pre-charge phase, the signal PRE keeps low, which pre-charges the bit lines, DLP and DLN to VDD. During the decision phase, the signal Y sel and SAE are activated, and the transistors form a current conveyor, which makes the nodes DLP and DLN track the changes on the bit lines. Subsequent circuit is similar to CBLSA for conversion to voltage mode.

3 Resistive RAM It has been seen that in certain insulating mediums, the difference in resisting happens due to the applied electric field. This property has been explored for creating future non-volatile memories [23]. The resistance exchanging peculiarity has been seen in an assortment of oxides, however parallel metal oxides have been widely considered as a favored exchanging material for future non-volatile memory applications fundamentally because of their similarity with the CMOS. ReRAM specifically works by using the tactic of making physical defects during a layer of oxide material (see Fig. 1). Those defects were also known as oxygen vacancies, and therefore the ReRAM works like of a semiconductor but with oxygen ions. The vacancies mean two values during a binary numeration system, rather electrons and holes present in a semiconductor. When voltage stress is given, then the resistance can be alternated between two states. In ReRAM stores the data in the form of resistance, so the researchers coined a name “memristor” Where a resistor can change its resistance by the application of the voltage or current stress.

3.1 Time Based Sensing and Read/Write Random Access Time-based sensing (TBS) is a concept for bit cell read. The TBS technique converts bit line voltage to time, then uses a sense amplifier to differentiate between the twobit cell levels in the time domain. When compared to traditional voltage sensing, the TBS technique significantly enhances read yield (CVS). ReRAM that operates at little power and has a rapid write speed. In read operations, however, RRAM has two fundamental challenges: (1) A low read yield due to a

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Fig. 1 The physical structure of ReRAM

wide resistance distribution, and (2) The need for precise bit line (BL) bias voltage regulation to avoid read disturbance. For current-mode read operation of RRAM, this paper presents two process-variation-tolerant schemes: parallel-series referencecell (PSRC) [9] and process-temperature-aware dynamic BL-bias (PTADB). These schemes aim to increase the read speed and yield of RRAM while accounting for read disturbance. The read disturb-induced conductance drift is statistically assessed on a test vehicle based on a 2-bit RRAM [10] array in this research. A vertical and lateral filament development process is used to empirically predict the drift behavior of four states. In addition, a bipolar read scheme is proposed and tested to improve read disturb robustness.

4 Sense Amplifier 4.1 Current Source The use of current source is to generate the constant current to the circuit I read . Here the current source drives the 1T-1R to get the voltage V bl (2) and the sensing margin for the sense amplifier in (see Fig. 2) 1T-1R memory cell one resistor in series with the one NMOS transistor connected in series, the data that is stored in the resistor as the resistance and the transistor helps to select the resistor and to get that resistance. The selection of the resistor is done with the WL (word line) of one transistor for a single bit of data. If 3-bit data to be selected, then three 1T-1R are selected and will be parallel in column wise. Thus, the read operation will be performed. In the time-based sense amplifier (see Fig. 3), the voltage V bl (2) taken as the

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Fig. 2 1T-1R memory cell

Fig. 3 Time-based sense amplifier (voltage to time conversion)

input to the sense amplifier and an extra enable signal will be the input to it. From that voltage it will have an another I bais a current source inside. That helps to convert the voltage equivalent data as the LRS value of IFF leads to the low data and the HRS value of the IFF leads the data high. There are two pulse shaping inverters that helps in the acquiring the data accurately and feeds it to the D-FF (D-flipflop). The EN which provide will give to the time delay circuit it will be given as the clock to the D-FF and thus to get the data out from the D-FF. The data from the Dout as the data that is present in the resistor as the resistance and the data will be in the form of high or low pulses. ReRAM stores the data in the form of resistance but, how to read the data from the 1T-1R as it is stored as resistance. constant current source that provides the current of required amperes that is 30 µA. Since 30 µA helps us in providing the better margin for sensing. By using the CCCS (current-controlled current source) which is readily

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Fig. 4 1T-1R array

available in the library of Mentor Graphics (PYXIS) software current of 30 uA (see Fig. 4), is the circuit with the array of 1R-1T connected transistors. Here 1T-1R Configuration uses access device as transistor for each cell, and the isolating each access cell from its adjacent in the array. Hence the three resistors which are in parallel will form an effective resistance as shown in Eq. (1). Reff = Ra ||Rb ||Rc

(1)

In the circuit the values of the Ra , Rb and Rc were taken accordingly based on the sense amplifier margin. This effective resistance from the array of memory cell and the current Iread from the CCCS will be multiplied and generate the voltage call V bl as given in the Eq. (2) Vbl = Reff ∗ Iread

(2)

Thus, the voltage will be generated from the array of 1T-1R memory cells from each row and the generated voltage will be given to the time-based sense amplifier. The fabrication of the resistor is not possible for designing the circuit the equivalent resistance from the PMOS transistor. The SA will sense the V bl and then there will be a delay for the output is given as the time delay where the amplifier works as the voltage to time conversion circuit. The sensing is done while reading operation is performed and where this has the resistance margin of few kilo ohms and this resistance will be in the range of 3.3 kΩ to the 44.4 kΩ. The effective resistance and the enable signal will control the amplifier that has eight transistors in which

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Fig. 5 Transistor level schematic of SA

two transistors are used as the pulse shaping inverter where is used to generate the pulse from the voltage signal and there it produces the IFF current which means that decides the HRS and LRS states of the resistance where the LRS will have the low voltage value when compared to the HRS. Thus, the difference in the output at the D-flipflop. The I-FF got at the inverter is the pulse that will go high for the HRS value, and it will be low for the LRS value of the resistance. During the Read operation a single bit of data will be read from the small Iread current and by activating only the single WL. The transistor level schematic diagram shown in (see Fig. 5) of sense amplifier is drawn in PYXIS tool and is analyzed for various metrics. It is designed using 130 nm technology, the three arrays of 1T-1R memory cells are used for the purpose of analysis. With this analysis, given the inputs accordingly for the word line for the transistors and the resistance made it with PMOS transistor by calculating tis Ron value. The current I read will drive the 1T-1R array of memory cells and the voltage across the multiplication of the current and the resistance from the resistors will be sent to the sense amplifier circuit.

5 Results and Discussions The EN signal that given to the sense amplifier will produce the EN-Delay for the flipflop as the clock and helps us to retrieve the resistance to the pulses and to get data accurately. Where the EN-Delay was given because of the voltage which is converted to the time pulses. For delay connected the not gates of back-to-back as the delay-circuit. The clock is running from the 0 ns and the output and input to the D-FF is started from 15 ns, and the output of the D-FF is started from the 16 ns. The simulation results of the sense amplifier and the power and delay waveforms shown (see Figs. 6 and 7). For a given data bit of “1” and the ready data from the high pulse from reading the array of 1T-1R array of three columns in parallel and

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Fig. 6 Simulation results of SA

Fig. 7 Power and delay of the SA

performed the read operation. The delay was calculated as 99.998 ns and the power as of average was 805.55 mW.

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6 Conclusion In this paper, a systematic overview of various SAs for SRAM is presented, In addition, this paper also presents a sensing methodology of ReRAM and performance comparison results for these selected SAs in simulation. non-volatile nature helps in fast accessing of data i.e., reading operations. The SA worked efficiently in converting the voltage to the time domain and the pulse shaping inverters and the time delay for the flipflop helps in improving the efficiency in reading. Currently the new advancements in the ReRAM are taking place by replacing the transistor with the selector. i.e., 1R-1S where it can perform the data operations faster than 1R-1T. The charge-transfer SAs have the advantage of high-speed and low-energy.

References 1. Horowitz M (2014) Computing’s energy problem (and what we can do about it). In: IEEE international solid-state circuits conference (ISSCC) digital technical papers, Feb 2014, pp 10–14 2. Pedram A, Richardson S, Horowitz M, Galal S, Kvatinsky S (2017) Dark memory and accelerator-rich system optimization in the dark silicon era. IEEE Des Test 34(2):39–50 3. Wong H-S-P, Salahuddin S (2015) Memory leads the way to better computing. Nature Nanotechnol 10(3):191–194 4. Xiao TP et al (2019) Energy and performance benchmarking of a domain wall-magnetic tunnel junction multibit adder. IEEE J Explor Solid-State Comput Dev. Circuits 5(2):188–196 5. Jain P et al (2019) A 3.6 Mb 10.1 Mb/mm2 embedded non-volatile ReRAM macro in 22 nm FinFET technology with adaptive forming/set/reset schemes yielding down to 0.5 V with sensing time of 5 ns at 0.7 V. In: IEEE international solid-state circuits conference (ISSCC) digital technical papers, Feb 2019, pp 212–214 6. Krishnarnurthy RK, Alvandpour A, De V, Borkar S (2002) High-performance and low-power challenges for sub-70 nm microprocessor circuits. In: Custom integrated circuits conference, pp 125–128 7. Rathod SS, Saxena AK, Dasgupta S (2011) Radiation effects in MOS-based devices and circuits: a review. IETE Techn Rev 28:451–469 8. Zhang LJ, Wu C, Ma YQ, Zheng JB, Mao LF (2011) Leakage power reduction techniques of 55 nm SRAM cells. IETE Techn Rev 28:135–145 9. Seevinck E, van Beers PJ, Ontrop H (1991) Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM’s. IEEE J Solid-State Circuits 26:525–536 10. Sasaki K, Ishibashi K, Yamanaka T, Shimohigashi K, Moriwaki N, Honjo S et al (1990) A 23 ns 4 Mb CMOS SRAM with 0.5 µA standby current. In: IEEE international solid-state circuits conference, pp 130–131 11. Kobayashi T, Nogami K, Shirotori T, Fujimoto Y (1993) A currentcontrolled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J Solid-State Circuits 28:523–527 12. Wicht B, Nirschl T, Schmitt-Landsiedel D (2004) Yield and speed optimization of a latch-type voltage sense amplifier. IEEE J Solid-State Circuits 39:1148–1158 13. Wicht B, Nirschl T, Schmitt-Landsiedel D (2003) A yield-optimized latch-type SRAM sense amplifier. In: Proceedings of 29th European solid-state circuits conference, pp 409–412

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14. Nikolic B, Oklobdzija VG, Stojanovic V, Wenyan J, James Kar-Shing C, Ming-Tak Leung M (2000) Improved sense-amplifier-based flip-flop: design and measurements. IEEE J Solid-State Circuits 35:876–884 15. Wong KL, Yang CK (2004) Offset compensation in comparators with minimum input-referred supply noise. IEEE J Solid-State Circuits 39:837–840 16. Schinkel D, Mensink E, Kiumperink E, van Tuijl E, Nauta B (2007) A double-tail latch-type voltage sense amplifier with 18 ps setup + hold time. In: IEEE international solid-state circuits conference, pp 314–605 17. Pille J, Adams C, Christensen T, Cottier SR, Ehrenreich S, Kono F et al (2008) Implementation of the cell broadband engine in 65 nm SOI technology featuring dual power supply SRAM arrays supporting 6 GHz at 1.3 V. IEEE J Solid-State Circuits 43:163–171 18. Plass DW, Chan YH (2007) IBM POWER6 SRAM “arrays.” IBM J Res Dev 51:747–756 19. Kawashima S, Mori T, Sasagawa R, Hamaminato M, Wakayama S, Sukegawa K et al (1998) A charge-transfer amplifier and an encoded-bus architecture for low-power SRAM’s. IEEE J Solid-State Circuits 33:793–799 20. Blalock TN, Jaeger RC (1991) A high-speed clamped bit-line current-mode sense amplifier. IEEE J Solid-State Circuits 26:542–548 21. Jinn-Shyan W, Hong-Yu L (1998) A new current-mode sense amplifier for low-voltage lowpower SRAM. In: Proceedings of eleventh annual IEEE international ASIC conference, pp 163–167 22. Do AT, Kong ZH, Yeo KS (2007) 0.9 V current-mode sense amplifier using concurrent bitand data-line tracking and sensing techniques. Electron Lett 43:1421–1422 23. Chang TC, Chang KC, Tsai TM, Chu TJ, Sze SM (2016) Resistance random access memory. Mater Today 19(5):254–264

Micro/Nanoelectronics Systems

Optimization of RF MEMS Switch Using Linear Vector Quantization Network Lakshmi Narayana Thalluri, N. Britto Martin Paul, K. V. V. Kumar, Koushik Guha, S. S. Kiran, and N. D. Bhushana Babu

Abstract This paper presents optimization of cantilever-based radio frequency (RF) micro-electro-mechanical system (MEMS) technology switches using artificial neural network (ANN)-based prediction algorithms, i.e., linear vector quantization network. We have created a literature survey-based train dataset and finite element method (FEM) simulation-based test datasets for cantilever structure-based RF MEMS switches. The dataset training is done with different algorithms, i.e., Bayesian regularization and extracted performance indices. Keywords RF MEMS · ANN · Datasets · Training algorithms

1 Introduction High frequency wireless communication applications demand low power consumption and high reliability offering reconfigurable communication modules like filters, phase shifters, and antennas [1]. RF MEMS technology has already proved its ability in the design of reconfigurable device. However, RF MEMS switches are facing L. N. Thalluri (B) · N. Britto Martin Paul Department of Electronics and Communication Engineering, Andhra Loyola Institute of Engineering and Technology, Vijayawada, A.P. 520008, India e-mail: [email protected] K. V. V. Kumar Department of ECE, Universal College of Engineering and Technology, Perecharla, A.P., India K. Guha Department of ECE, National MEMS Design Center, National Institute of Technology, Silchar, Assam 788010, India S. S. Kiran Department of Electronics and Communication Engineering, Lendi Institute of Engineering and Technology, Vizianagaram, A.P. 535005, India N. D. Bhushana Babu Department of ECE, Chalapathi Institute of Engineering and Technology (Autonomous), Guntur, A.P., India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_34

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Hidden Layer Input Layer

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Fig. 1 Basic ANN architecture

potential research challenges in the design of future communication applications [2] (Fig. 1). Now, the wireless communication application demands study RF MEMS switches, with performance optimization. Artificial neural network (ANN) is the promising approach, which helps to optimize the RF MEMS switch performance by predicting the best dimensions and materials. ANN is the potential subdomain in machine learning (ML) and is used in all the ML techniques [3]. A neural network is a multi-layer processing system that is inspired by biological nervous systems and uses simple pieces that operate in parallel. An input layer, one or more hidden layers, and an output layer make up the structure. There are numerous nodes, or neurons, in each layer, with each layer taking the output of the preceding layer as its input, forming neurons that connect the layers. Each neuron’s weights are normally altered during the learning process, and when the weight lowers or increases, the strength of that neuron’s output changes [4].

2 Related Work The RF MEMS technology is a promising hope for the design of high-performance offering RF switches. RF reconfigurable devices like tunable filters, phase shifters, transmission line, and antenna design require RF switches. However, the high data rate offering communication modules demands optimized RF MEMS switches. ANN has great potential in the aspect of optimization of RF MEMS switches. The popular data prediction neural network models are listed in Table 1, i.e., fitting neural network,

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Table 1 State of art on RF MEMS switches optimization References

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[8]

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average test error (ATE), worst case error (WCE)

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Conjugate gradient with Powell/Beale restarts

Mean square error (MSE), Pearson product moment correlation coefficient (r)

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Levenberg–Marquardt

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[14]

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cascade forward net or feed forward network, competitive neural network, selforganizing map network, and linear vector quantization network [5–7]. The neural network training type may be iterative (one training set) and epoch (entire training sets).

2.1 Train Dataset A dataset is designed using cantilever-based RF MEMS switches from the literature with 11-input and 6-output variables as shown in Table 2. The cantilever dimensions are length (l), width (w), thickness (t), and membrane height (mh ). The bottom electrode parameters are electrode length (E l ) and electrode width (E w ). The dielectric parameters are length (Dl ), width (Dw ), and thickness (Dt ).

3 Implementation Low power consumption and high linearity like features making RF MEMS switches become prominent in high-performance communication applications. However, optimization of RF MEMS switches is essential to fulfill the expectations. Incorporation of ANN in the design process of RF MEMS switches helps to predict the optimized switch dimensions and the improving the performance (Figs. 2, 3, 4, 5, 6; Table 3).

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4 Conclusion Cantilever-based RF MEMS switch using artificial neural network (ANN) prediction algorithms, i.e., linear vector quantization network, is presented. We have created a literature survey-based train dataset and finite element method (FEM) simulationbased test datasets for cantilever structure-based RF MEMS switches. The dataset training is done with different algorithms, i.e., Bayesian regularization and extracted performance indices. The linear vector quantization network offers a better accuracy for four epochs.

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Analysis of Micro-RF Switches Role in Reconfigurable Antenna Design Chilaka Dimpu Deepthi, Lakshmi Narayana Thalluri, and Koushik Guha

Abstract This paper discusses a new reconfigurable bidirectional RF transducer, i.e., antenna where both frequency and pattern are reconfigured. The antenna involves with the T-shaped rectangular patch where it will be joined by two latitudinal slits. The slits will linked to a pin diode to gain the essential frequency bands. The design was micro-machined on 70 mm * 70 mm substrate with FR4 as a material and designed using HFSS tool. The frequency reconfiguration can be perceived in between at 4.5, 5.8, 11.4, and 13.6 GHz which are used for the WLAN communications. The reconfiguration of pattern is about − 15°, 15°, 30° angle will be seen in the radiation patterns at the same bands. Keywords Frequency reconfigurable · Multiband antennas · Pattern reconfigurable

1 Introduction Wireless communication has been increasing day by day; wireless devices are supporting more number of applications. The reconfigurable antenna is used in high data speed and communication applications; the number of components and complexity of hardware will reduce [1–3]. There are different techniques of reconfigurability used with the different size and shape of radiating elements [4–7]. Change in substrate material helps to improve the antenna radiation efficiency. However, PIN diode offers high-speed switching compared with other RF switches. In this design, we are using the FR4 as material and BAR64 PIN diode and designed by using HFSS 18 [8–11]. C. D. Deepthi (B) · L. N. Thalluri Department of Electronics and Communication Engineering, Andhra Loyola Institute of Engineering and Technology, Vijayawada, A.P. 520008, India e-mail: [email protected] K. Guha Department of ECE, National MEMS Design Center, National Institute of Technology, Silchar, Assam 788010, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_35

339

340

C. D. Deepthi et al.

Table 1 Challenges of parameter

Parameter

Research challenges

PIN

Design of proper bias lines

Antenna

Frequency selectivity, gain, directivity

2 Problem Statement The capacitance of PIN diode is independent of bias level, and diode possesses very low reverse recovery time. The diode will not accept standard formula for all lowfrequency signals [12–14]. The diodes are used in radio frequency switches, and these are mostly used for RF protection circuits and used as a RF switch [15–18]. There are some challenges involved in designing antenna for WLAN applications, such as antenna size and performance characteristics like bandwidth, gain, and efficiency [19–20] (Table 1).

3 Design Methodology The design will represent the novel reconfigurable antenna, for that we designing the antenna in HFSS 18 (High-frequency structure simulator) and designing the basic structure using FR4 as substrate and antennas shown in, and designing the different antenna using patch and simulating the design and obtaining the frequency of different antennas, we design as shown. The methodology is followed by the structural analysis, RF switches design and biasing, design of reconfigurable antenna and performance analysis [21–22]. The width and length of rectangular patch antenna were c /

width = 2 f0 εeff

(1)

εr +1 2

⎤ ⎡ 1 εR + 1 εR + 1⎣ ⎦ / + = ( ) 2 2 1 + 12 h

(2)

W

( )) ( (εeff + 0.3) Wh + 0.264 c ( ) length = − 0.824h √ 2 f 0 εeff (εeff − 0.258) Wh + 0.8

(3)

Length and width of the feed are given by (Figs. 1 and 2). λ Lf = √ 4 εT Wf =

377(h + 2) √ z εT

(4) (5)

Analysis of Micro-RF Switches Role …

341

Rectangular patch

Substrate Microstrip- line Feed

(a)

(b)

(c)

Fig. 1 Iterative design analysis, a design 1, b design 2, c design 3

Reflection Coeffienct [dB]

5 0 -5 -10 -15 -20 -25

Antenna 1 Antenna 2 Antenna 3

-30 2

3

4

5

6

7

8

9

Frequency [GHz]

Fig. 2 Frequency of different antenna designs

4 Proposed Reconfigurable Antenna The proposed reconfigurable antenna which was designed can be seen in Fig. 3. The dimensions of the antenna were in mm. In this design, we are designing the antenna using HFSS 18 and FR4 as a material with the dimension of 70 * 70, and using the BAR64 PIN diode, four PIN diodes are used. The antenna is in T-shaped rectangular patch will be joined by two latitudinal slits. The execute of PIN diode on operation of antenna is due to resistance given by the diode in the both ON and OFF state. In this design, we are simulating the PIN diodes at different ON and OFF conditions. The simulation is done in the high-frequency structure simulator (Figs. 4, 5, 6; Tables 2, 3, 4, 5).

342

Fig. 3 Proposed antenna with reconfigurability

Fig. 4 Simulated and measured results

C. D. Deepthi et al.

Analysis of Micro-RF Switches Role …

343

Fig. 5 PIN diode lumped model, a diode ON and OFF conditions representation, b DC blocking circuit State 1 State 5 State 8 State 10 State 11 State 12 State 16

0

Reflection Coefficient [dB]

-5 -10 -15 -20 -25 -30 -35 -40 2

4

6

8

10

12

14

16

18

20

Frequency [GHz]

Fig. 6 Frequency at different states of proposed antenna Table 2 Measurements of proposed antenna

Parameter Dimension in mm Parameter Dimension in mm Ws

70

L p4

30

Ls

70

L p5

10

Lf

13

L p6

6

L p1

12

G

5

L p2

11

H

1

L p3

6

I

9

344

C. D. Deepthi et al.

Table 3 Diodes components and their values Component

Value

Rs

2.1 Ω

Rp

300 k Ω

L

1.8 nH

C

0.2 pF

C dc

20 pF

L choke

33 nH

5 Pattern Reconfiguration The reconfiguration of pattern is accomplished through altering the current course in the patch radiator. In a normal framework, adjustment in the period of the excitation current outcomes with the tilting of pattern. In any method, for this situation, the excitation source is kept steady, and the way that the current ventures will be changed. Consequently, in the pattern reconfiguration expresses, the current travels extra separation prompting way distinction, which further delivers a stage contrast. The pattern reconfiguration is inferred by the subclass of State I and V. In State I, D1, D2, D3, and D4 will be in OFF state. The radiation pattern can be tilted up to 15° when the diode is turned ON (Table 6).

6 Radiation Patterns The graphical view of radiation pattern of the antenna was shown in Fig. 7, for the Eplane and H-plane at the different states. The pattern of radiation will be seen in twoor three-dimensional spatial distribution of radiating energy. The radiation pattern is seen at the different conditions for ON and OFF stages. The radiation pattern is observed at the − 15°, 15°, 30° (Table 7).

7 Conclusion In this work, we designed a different structures of a reconfigurable antenna using PIN diodes with both frequency and pattern where they are reconfigured. The shape of the antenna was T attached by two longitudinal slits. The antenna was designed

Analysis of Micro-RF Switches Role …

345

Table 4 Diode switching conditions Diode switching conditions

First resonant band

Second resonant band

Third resonant band

OFF

4.5(2.09–6.36)

8.8(8.65–9.06)

11.3(11.11–11.48)

OFF

ON

8.8(8.65–9.04)

10.1(10.0–10.1)

11.20(11.06– 11.2)

OFF

ON

OFF

5.7(4.43–5.81)

7.0(6.70–7.51)

8.9(8.68–9.08)

OFF

OFF

ON

ON

8.8(8.67–9.07)

11.2(11.0–11.6)

13.5(13.27–20)

OFF

ON

OFF

OFF

4.8(2.85–6.21)

8.8(8.65–9.06)

11.4(11.03–11.60)

OFF OFF

ON ON

OFF ON

ON OFF

8.8(8.62–9.05) 5.6(3.41–6.49)

11.4(11.1–11.6) 8.9(8.65–9.08)

14.3(13.25–20) 10.1(10.07–10.20)

OFF

ON

ON

ON

4.5(1.99–6.51)

8.8(8.64–9.05)

11.5(11.12–11.69)

ON ON

OFF OFF

OFF OFF

OFF ON

8.9(8.70–9.08) 4.6(1.99–6.53)

14.6(13.03–20) 8.8(8.66–9.06)

– 11.3(11.09–11.38)

ON

OFF

ON

OFF

4.6(2.75–5.82)

8.9(8.64–9.09)

11.5(11.35–11.58)

ON

OFF

ON

ON

3.7(1.36–6.46)

8.9(8.66–9.09)

11.4(11.16–11.55)

ON

ON

OFF

OFF

6(5.87–6.58)

9(8.81–9.12)

10.2(10.18–10.29)

ON

ON

OFF

ON

5.8(4.52–6.30)

8.9(8.62–9.08)

10.2(10.11-10.23)

ON

ON

ON

OFF

5.5(3.77–6.28)

8.9(8.70–9.09)

11.4(11.20-11.64)

ON

ON

ON

ON

5.4 6.71)

8.8(8.65–9.07)

10.2(10.18-10.21)

D1

D2

D3

D4

OFF

OFF

OFF

OFF

OFF

OFF

(2.83–

Four th resonant band 17(1 3.31 –20) 13.7( 13.3 9– 20) 10.2( 10.0 9– 10.2 3) – 15.4( 13.3 9– 20) – 11.4( 11.0 6– 11.6 3) 13.9( 13.3 7– 18.2 9) – 15.0( 13.1 5– 20) 11.2( 13.1 0– 20) 13.9( 13.1 4– 20) 11.5( 11.2 2– 11.6 4) 11.5( 11.1 9– 11.6 0) 14.5( 13.1 6– 20) 11.5( 11.2 7– 11.5 8) 14.5( 3.0820)

346

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Table 5 Bands and gain at the particular bands for the specified diode conditions Diode switching conditions

B.W at 1st band

D1

D2

D3

D4

OFF

OFF

OFF

OFF

4.27

OFF

ON

OFF

OFF

3.36

OFF

ON

ON

ON

4.52

ON

OFF

OFF

ON

4.54

ON

OFF

ON

OFF

3.07

ON

OFF

ON

ON

5.1

ON

ON

ON

ON

3.88

Gain (db ) at 1st band

3.413 5 − 0.19 3.449 0 0.890 9 0.769 6 2.667 2 0.636 7

B.W at 2nd band

Gain (db) at 2nd band

B.W at 3rd band

0.41

4.935 5

0.37

0.41

4.475

0.57

5.031 3 4.536 0 4.808 4 4.822 5

0.41 0.4 0.45 0.43

4.556 8

0.42

0.57 0.29 0.23 0.39

0.03

Gain (db) at 3rd band

3.083 5 3.572 6 4.274 5 3.942 4 2.750 8 2.733 4 3.177 5

B.W at 4th band

6.69 6.61 4.92 6.85 6.9 6.86 0.31 16.92

Gain (db) at 4th band

7.484 2 6.989 3 4.130 4 4.553 6 4.367 5 4.236 2 1.511 5 4.331 7

Table 6 Efficiency of the antenna in different stages

State

1

Diode switching conditions D1 D2 D3 D4 OFF OFF OFF OFF

Efficiency (%) at resonant bands 1 44.75

2 48.27

3 33.52

4 42.39

5

OFF

ON

OFF

OFF

23.07

47.49

37.28

44.02

8

OFF

ON

ON

ON

41.38

49.53

37.33

42.53

10 11

ON ON

OFF OFF

OFF ON

ON OFF

28.37 28.19

46.93 48.80

33.52 33.71

45.17 39.05

by using HFSS 18 and FR4 substrate. The frequency reconfiguration is between 4.5, 5.8, 11.4, and 13.6 which are used for WLAN communications. The radiation pattern will be observed at the angle of − 15°, 15°, 30°. The simulation results will be seen in HFSS.

Analysis of Micro-RF Switches Role … E-PLANE (STATE 1,8,12)

H-PLANE (STATE 1,8,12) 11.3GHz

330

10

17GHz

8.8GHz

30

0

300

60

-10

300

5

17GHz

0

330

-20

-30 -40

90

-40 -30

-20

-20

-10

240

-10

120

90

240

15.4GHz 300

0 5

330

300

5

13.9GHz

0

330

4.5GHz 8.8GHz

30

11.5GHz 13.9GHz

-10

300

-10 -15

60

-20

-15

-15

-10

-10 240

120

90

-25

-15

5

8.8GHz 11.5GHz 4.5GHz

300

-10

-30

90

-20

-10

-15

150

13.9GHz 30

0

-25

120

120

210 180

0 2

4.6GHz

330

8.8GHz

30

0

11.3GHz

-2

15GHz

-4

60

-6

300

60

-8 -10 -12 -14

-25 270

-16 270

90

-18

270

90

-16 -14 -12 -10

240

-10 240

330

5

-15

120

-8 240

120

210

5

150

-2 0

0

180

150

120

-4

-5

0

240

-6

-10

-5

0

90

240

-5

150

-5

-20

-5

270

0 210

-20

-20 270

210

-20

-15

-15

-20

60

180

-5

60

-25

90

5

0

11.5GHz

15.4GHz 300

-20 270

-20

0

8.8GHz

8.8GHz 11.4GHz

-5

-15

-5

150

4.8GHz 30

330

-10

4.5GHz 30

0

5

60

180

180

-25

-25

120

210

150

-5

0

0

10

210

5

11.4GHz

-20

270

0

0 10

8.8GHz

-15

-30

270

-30

30

-5

60

0

4.8GHz

0

11.3GHz

-10 -20

H-PLANE (STATE 5,12,16)

4.5GHz

0

8.8GHz

30

0 -10

H-PLANE (STATE 5,12,16)

4.5GHz

0 330

10

347

210

2

5

210

180

150 180

150 180

0

4.6GHz

0 330

5

300

-10

60

-25

90

-25 -25 -20

-15

-15

-10

-10

-5

240

120

-5

5

11.5GHz

-5

11.2GHz

210

60

90

240

120

90

-14 -14 -12

-20

-10

-15

-8

-10

240

120

5

-6 -4

270

90

240

120

-2

0 150

60

-12 270

-25

-5 210

11.5GHz 300

-6 -8

210

180

180

11.2GHz

-4

-10

-30

8.9GHz

30

0

-20

-30

4.6GHz

330

2

-2

-15

-25 270

5

150

300

-10

60

0

0

8.9GHz

0

-20 270

-20

4.6GHz 30

5

11.3GHz

-15

-20

-25

300

-10

330

8.8GHz 15GHz

-5

-15

30

0

15GHz

-5

330

5

11.3GHz

0

4.6GHz

0

8.8GHz

30

0

0

150

2

180

210

150 180

Fig. 7 Radiation pattern of the proposed antenna Table 7 Work related to the proposed antenna Work Dimensions Reconfiguration Elements Features of the seen used B.W. (MHz) antenna (mm2 )

Gain (dBi)

η (%)

[23]

46 × 20

Frequency

4 MEMS 90/125/100

−0.15/3.14/2.57 55/90/75

[24]

58 × 30

Pattern

2-PIN diodes and 1 FSS

150

9.1

NR

[24]

130 × 160

Frequency, pattern

11 switches

200/150/150

5.6/4.6/ 3.3

88.7/87.7/ 89.5

[25]

80 × 45.8

Frequency, pattern

5-PIN diodes

580/290

1.9/2.1

71/51

[26]

120 × 120

Frequency, pattern

12-PIN diodes

63.4/88.3

9.15/10.52

94.9/94.8 (continued)

348

C. D. Deepthi et al.

Table 7 (continued) Work Dimensions Reconfiguration Elements Features of the seen used B.W. (MHz) antenna 2 (mm )

Gain (dBi)

η (%)

[27]

34 × 36

Frequency, pattern

2 switches

100/70

4/5.6

NR

[28]

50 × 50

Frequency, pattern

2-PIN diodes

120/100/100

NR

NR

This 70 × 70 work

Frequency, pattern

4-PIN diodes

240/70/50/240 4.6/5.35

71/83/87/89

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14. Atallah HA, Abdel-Rahman AB, Yoshitomi K, Pokharel RK (2016) Reconfigurable bandnotched slot antenna using short circuited quarter wavelength microstrip resonators. Progr Electromagn Res 68:119–127 15. Nazir I, Rana IE, Mir NUA, Afreen K (2016) Design and analysis of a frequency reconfigurable microstrip patch antenna switching between four frequency bands. Progr Electromagn Res 68:179–191 16. Sharma S, Tripathi CC (2016) A wide spectrum sensing and frequency reconfigurable antenna for cognitive radio. Progr Electromagn Res 67:11–20 17. Koley S, Murmu L, Pal B (2016) A pattern reconfigurable antenna for WLAN and WiMAX systems. Progr Electromagn Res 66:183–190 18. Hussain R, Khan MU, Abu-Al-Saud W, Muqaibel AH, Sharawi MS (2016) Characterization of reconfigurable MIMO antennas for channel capacity in an indoor environment. Progr Electromagn Res 65:67–77 19. Wang F-W, Guo L, Gong S-X (2016) Reconfigurable radar absorbing structure applied to the antenna radar cross section reduction. Progr Electromagn Res 64:179–185 20. Yang L, Zhu Y, Yoshitomi K (2015) CPW-fed reconfigurable clover-shaped antenna with switchable circular polarization. Progr Electromagn Res 60:147–156 21. Lim S-L, Lim EH, Lo F-L (2015) Reconfigurable stepped-impedance slotline power dividers. Progr Electromagn Res 57:109–116 22. Soltani S, Lotfi P, Murch RD (2016) A port and frequency reconfigurable MIMO slot antenna for WLAN applications. IEEE Trans Antennas Propag 64(4):1209–1217 23. Bouslama M, Traii M, Denidni TA, Gharsallah A (2016) Beam switching antenna with a new reconfigurable frequency selective surface. IEEE Antennas Wireless Propag Lett 15:1159–1162 24. Majid HA, Rahim MKA, Hamid MR, Ismail MF (2014) Frequency and pattern reconfigurable slot antenna. IEEE Trans Antennas Propag 62(10):5339–5343 25. Li PK, Shao ZH, Wang Q, Cheng YJ (2015) Frequency- and pattern reconfigurable antenna for multistandard wireless applications. IEEE Antennas Wireless Propag Lett 14:333–336 26. Ramli N, Ali MT, Islam MT, Yusof AL, MuhamudKayat S (2015) Aperture-coupled frequency and patterns reconfigurable microstrip stacked array antenna. IEEE Trans Antennas Propag 63(3):1067–1074 27. Huff GH, Feng J, Zhang S, Bernhard JT (2003) A novel radiation pattern and frequency reconfigurable single turn square spiral micro strip antenna. IEEE Microw Wireless Compon Lett 13(2):57–59 28 Abou Al-Alaa M, Elsadek HA, Abdallah EA (2014) Compact multi-band frequency reconfigurable planar monopole antenna for several wireless communication applications. J Electr Syst Inf Technol (1):17–25. http://dx.doi.org/10.1016/j.jesit

Ultrahigh Sensitive Mercury Ion Detector Using AlGaN/GaN HEMT-Based Sensor and System Shivanshu Mishra , Pharyanshu Kachhawa, Amber Kumar Jain, Kaushal Kishore, and Nidhi Chaturvedi

Abstract In this paper, we propose a gallium nitride (GaN) high-electron-mobility transistor-based (HEMT) sensor and developed circuit for point of care detection of mercury contamination in water. The platform, GaN HEMT, has been fabricated for three different epitaxial structures and four different device designs. The drain current of GaN HEMTs for various designs for a specific epitaxial structure has been recorded at a Vds of + 5 V where a 2x50-25ID device design performs better than the other three. The sensor is developed on the 2x50-25ID design and tested in continuous running mode that is able to detect nM level of concentrations of mercury in water. The sensor exhibits a drain current change of 6.66% at a Vds of + 5 V when immersed into 1 nano-molar solution of the mercury with reference to the drain current obtained in normal DI water. The developed handheld system also shows a good response to the mercury contaminated water, and the the performance is reasonably close to the on chip detection. The packaged sensor and circuit is portable and can work stand alone for the detection of the mercury. Keywords GaN HEMT · Sensor · Mercury detection · Heavy metal · Handheld system

1 Introduction Mercury is an unavoidable heavy metal that occurs in water, ground, and air. Almost, all the human are somehow exposed to small amount of mercury throughout their life. A study presented by world health organization (WHO) demonstrated health problems associated with the mercury exposure. A small amount exposure of mercury is a threat to the development of the children in uterus and early in their life. We S. Mishra · P. Kachhawa · A. K. Jain · K. Kishore · N. Chaturvedi CSIR-Central Electronics Engineering Research Institute,Pilani, Rajasthan, India S. Mishra (B) · P. Kachhawa · K. Kishore · N. Chaturvedi Academy of Scientific and Innovative Research,Ghaziabad, Uttar Pradesh, India e-mail: [email protected]; [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_36

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are exposed to mercury due to its environmental presence in various mediums and have mercury in our body. However, in general, the amount is quite low at this level of exposure, and therefore, it does not show its toxic effects on human body [1, 2]. Mercury may have toxic effects on the nervous, digestive and immune system and on lungs, kidney, skin, and eyes [3, 4]. Considering all such associated problems Environmental Protection Agency (EPA) has set a regulation for mercury, known as maximum contaminant level (MCL), at 2 µml or 2 ppb. Therefore, to detect the mercury contamination in water, we develop a gallium nitride high-electronmobility transistor-based (GaN HEMT) sensor that can detect 0.27 ng/ml mercury in the water. The sensor enjoys the properties of GaN material and heterostructure which leads to very high sensitivity. Properties such as high electron mobility, high sheet carrier density [5, 6], high trans-conductance [7] and more importantly the chemical inertness of the material make this device more suitable for sensing applications [8– 10]. In this paper, we present the development of GaN HEMT as a platform device for the detection of nano-molar level of mercury in water.

2 Experimental Details The platform device, GaN HEMT, is fabricated on sapphire substrate with three different epitaxial structures for the detection of mercury in water. The epitaxial structure comprised of a 50 nm aluminum nitride as a nucleation layer followed by a thick 2.0 µm iron-doped gallium nitride (GaN) buffer layer. On the top of the GaN layer, a 22.0 nm thick aluminum gallium nitride (Al0.25 Ga0.75 N) has been further grown. Heterojuction is formed between the AlGaN and GaN layer that generates a sheet charge at the interface. The aforementioned layers are common in all the epitaxial structure. The epi layers are different on the top where the sensing plays an important role as the sensing is the surface phenomena in planner devices. For sensing applications, the quality of surface of the GaN HEMT plays crucial role. Thus, SiNx and GaN cap layers are used in three combinations that make three different epitaxial structures. Epitaxy-1 consists 5 and 2 nm of cap layers of GaN and SiNx on the top of AlGaN. Epitaxy-2 and epitaxy-3 have 5 nm thick GaN and 2 nm SiNx as a cap layer, respectively. Rest of details of the epitaxial structures is listed in Table 1. The sensor fabrication begins with formation of ohmic contacts, i.e., source and drain that are achieved by depositing a metal stack of Ti/Al/Ni/Au using an e-beam evaporator. To make the contact ohmic in nature, a rapid thermal annealing (RTA) has been used where the contacts are annealed at 830 ◦ C for 30 s in nitrogen environment. Transfer length method (TLM) has been used where the pads are separated by 2.0, 4.0, 8.0, and 16.0 µm. Current measurement has been obtained between each pad at a voltage range of −1 to +1 V. The devices are isolated by passivating the surface with silicon nitride, and then, ion implanting of the nitrogen atoms is performed. Highintensity nitrogen ions destroy the two-dimensional electron gas (2DEG) available at the interface of the AlGaN and GaN material that leads to inter-device isolation. A multi-stack of Ni/Ti/Au has been deposited to make Schottcky contact by defining

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Table 1 Details of the various epitaxial structures Structures Layers Epitaxy-1

Epitaxy-2

Epitaxy-3

Cap Cap Barrier Buffer Buffer Nucl. Cap Barrier Buffer Buffer Nucl. Barrier Buffer Buffer Nucl.

Sinx GaN:Si Al0.25 Ga0.75 N GaN GaN:Fe AlN GaN:Si Al0.25 Ga0.75 N GaN GaN:Fe AlN Al0.25 Ga0.75 N GaN GaN:Fe AlN

Thickness (nm) 2 5 22 800 1200 50 5 22 800 1200 50 22 800 1200 50

a gate trench in nitride layer using inductively coupled plasma reactive ion etching. For sensing purpose, Schottky contact is defined with various geometry keeping the gate length of 3 µm. Two designs of the gate are patterned using photo-lithography, wherein first, a rectangular gate is deposited with with the width of 100 µm, and in another, an inter-digital (ID) pattern has been used. Biasing pads are fabricated using a metal stack of Ti/Au. To avoid the cross-interaction of the test solution, the entire device is coated with a 50 nm thick silicon nitride layer. Finally, the silicon nitride layer is etched away from the gate area and biasing pads for sensing. The fabricated devices have two openings, one is on the gate area which is the sensing region, and another is the biasing pads that are used to bias the sensor, and rest of the device is protected with silicon nitride. In total, four different designs based on the gate structure (G and ID) and the distance of the source to drain (Lsd ) have been fabricated. In this study, these deisings are termed as 25G, 25ID, 50G, and 50ID where first two digits represent the distance between the source to drain and last alphabets tell about the type of geometry on the gate area. The inter-digital (ID) type device is shown in Fig. 1 where the inter-digital structure can be seen instead of a rectangular gate. In ID type structure, the fingers are connected at the end. Figure 1b, c shows the entire fabricated chip along with a single-diced device, respectively.

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Fig. 1 HEMT fabricated with various designs a inter-digital device, b 14 chips on 11 × 11 mm2 area, c single-diced device Fig. 2 Influence of design and epitaxial structures on the drain current of the GaN HEMTs measured at a Vds of +5V

3 Results Figure 2 compares the drain current response with respect to different device and epitaxy design at a Vds of + 5 V. Design of 2X50-25G shows the highest current but it is not as sensitive as 2X50-25ID. 2X50-25ID shows the strong effects of the epitaxial structures on the drain current which reflects the sensitivity for different epitaxial structure. For sensing application sensitivity is the most important parameter therefore 2X50-25ID is used for further testing. Figure 3 shows the running test of the sensor in which Vds is kept constant at 3.3 V and the drain current is measured in air, deionized (DI) water and nano-molar solution of mercury with 60 s gap in each measurement. The recorded current values of the sensor in air, deionized (DI) water, and nano-molar solutions are 10.49 mA, 14.11 mA, and 15.05 mA, respectively. The drain current for the DI water acts as a reference current for the 1 nM test solution of mercury in water, and from that level

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Fig. 3 Running test of the sensor for air, DI water, and nM mercury solution at Vds = 3.3 V

of the drain current for the DI water, the change in the drain current for 1 nM mercury in water is recorded as 6.7% (Fig. 3). We also developed the handheld electronic circuit and system for this mercury detector. Circuit consists of 3.7 V lithium polymer battery and AS1329 IC used for stepping up the voltage. It is having an instrumentation amplifier INA 114AP for gain, Arduino MKR1000 microcontroller, Nokia 5110 LCD for display. The developed circuit utilizes 3.7 V obtained from a 2000 mAH battery. A DC to DC converter and a voltage inverter have been used to convert the input supply to 5 V and ± 3.3 V, respectively. The sensor is connected to the positive input of the instrumentation amplifier (INA), and its negative input is used to cancel out the reference value of the drain current by using a digital to analog conversion (DAC). This cancellation of the reference values (drain current) ensures zero voltage at the output in dry condition of the sensor which changes to particular values while testing. Figure 2 shows the drain current response of the sensor with circuit integration. Similar steps are used in order to sense the nano-molar mercury in water. Base value of the sensor is 11.11 mA at 3.3 V, and del-I shows the change in current from its previous value. The del-I is zero due to the ADC as soon as the circuit is turned on. When the sensor is immersed in water, the del-I changes to 0.53mA and the corresponding voltage changes to 1.19 V. Subsequently, the sensor is immersed in a nanomolar mercury solution in water, del-I shows 0.71 mA and the corresponding voltage changes to 1.57 V. This response of the integrated system shows the successful development of handheld system for detecting the nano-molar mercury in water.

4 Conclusion The gallium nitride high-electron-mobility transistor-based sensor has been designed and fabricated for three different epitaxial structures and device designs. The perfor-

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Fig. 4 Measurement setup with fabricated sensor integrated with the readout circuit (above) and response of this integrated system for different mediums (below)

mance of the device based in the epitaxial structure and device design has been also compared. The fabricated device is used as a platform device that is used to test the presence of the mercury in water. The sensor exhibits a great sensitivity that leads to the detection of nM level of mercury contamination in the water. Transient test of the sensor has been demonstrated for air, DI wate,r and nM contaminated DI water at a Vds of + 5 V. A handheld readout circuitry has also been used to demonstrate a change in drain current which corresponds to nM mercury contamination. The sensor shows a change of 6.66% in drain current when it is immersed into 1 nano-molar mercury solution which is easily distinguishable. Acknowledgements Authors acknowledge the support of mission mode project (HCP0012). Authors are also grateful to the director of CSIR-CEERI, Pilani for his guidance and support.

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References 1. Kannan K, Smith R Jr, Lee R et al (1998) Distribution of total mercury and methyl mercury in water, sediment, and fish from South Florida estuaries. Arch Environ Contam Toxicol 34:109– 118 2. Jan AT, Murtaza I, Ali A et al (2009) Mercury pollution: an emerging problem and potential bacterial remediation strategies. World J Microbiol Biotechnol 25:1529–1537 3. Holmes P, James KAF, Levy LS (2009) Is low-level environmental mercury exposure of concern to human health? Sci Total Environ 408(2):171–182 4. Zahir F, Rizwi SJ, Haq SK, Khan RH (2005) Low dose mercury toxicity and human health. Environ Toxicol Pharmacol 20(2):351–360 5. Ueda T, Uemoto Y, Tanaka T, Ueda D (2009) GaN transistors for power switching and millimeter-wave applications. Int J High Speed Electron Syst 19(1):145–152 6. Herbecq N, Jeune IR, Linge A, Zegaoui M, Jeannin PO, Rouger N, Medjdoub F (2016) Above 2000 V breakdown voltage at 600 K GaN-on-silicon high electron mobility transistors. Phys Status Sol A 213(4):873–877 7. Sun H, Alt AR, Tirelli S, Marti D, Benedickter H, Piner E, Bolognesi CR (2011) Nanometric AlGaN/GaN HEMT performance with implant or mesa isolation. IEEE Electron Device Lett 32(8):1056–1058 8. Li B, Tang X, Wang J, Chen KJ (2016) Optoelectronic devices on AlGaN/GaN HEMT platform. Phys Status Sol A 213(5):1213–1221 9. Mishra UK, Shen L, Kazior TE, Wu Y-F (2008) GaN-based RF power devices and amplifiers. Proc IEEE 96(2):287–305 10. Ren F, Pearton SJ (2011) Recent advances in wide-bandgap semiconductor biological and gas sensors. In: Semiconductor device-based sensors for gas, chemical, and bio applications. CRC Press, Boca Raton, London, New York, pp 43–96

Design and Simulation Analysis of a Piezoresistive Cantilever Beam for Low-Pressure Detection M. Lakshmi Prasanna and V. R. Anitha

Abstract Many studies have shown that most MEMS devices use light beams whose deflection response is the main focus before choosing it for specific applications. This paper deals with the simulation of the MEMS-based cantilever beam for low-pressure detection. COMSOL 5.4 multiphysics FEM model is used to study the behavior of beam and compared with the conventional cantilever beam. Both are analyzed with two different materials SiO2 and SU-8. The change in the deflection has been analyzed with various pressure values applied on the cantilever beam. Through simulation and analysis results, it is observed that the deflection of the proposed beam is good at lower pressure values. Keywords Microcantilever · Deflection · Rectangular beam · FEM

1 Introduction In the past few decades, MEMS system attracts researchers due to its small size, quicker response, low power consumption, easy fabricating, low cost of production, and high sensitivity. Among many MEMS devices, microcantilevers have become more popular in the field of BioMEMS where low-mass load of biomolecules draws more attention on MEMS devices. Microcantilever sensors offer a wonderful means that to notice single cell or molecules within the atmosphere. Highly functionalized surface of the microcantilever absorbs specific targeted biomolecules and a surface stress has been induced, thereby leading to a deflection inflicting a downward bend at the free end. In addition to a single microcantilever beam structure, different microcantilever beam arrays can also be easily manufactured. Therefore, sensors M. Lakshmi Prasanna (B) Department of Electronics and Communication Engineering, JNTUA, Ananthapuramu, Andhra Pradesh, India e-mail: [email protected] V. R. Anitha Department of Electronics and Communication Engineering, BMS Institute of Technology and Management, Yelahanka, Bangalore, Karnataka 560064, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_37

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based on microcantilever beams have been potentially applied in various fields [1– 4]. Recently, research on cantilever beams used in chemical and biological sensors has developed rapidly in the medical, food, and agricultural industries. Therefore, the targeted range of the microcantilever expands with the passage of time, and an in-depth analysis of the microcantilever should be carried out. In the field of sensors, sensitivity is one of the most important factors of cantilever beam analysis. Geometry, shape, and resonance mode play a key role in the sensitivity of the cantilever sensor because these parameters greatly affect the resonance frequency, quality issues, and deflection of the cantilever [5, 6]. So far, various researchers have given different cantilever structures with microcantilever beams of different sizes to produce better deflection and sensitivity. Researchers have used different materials like SiO2 , SiN3 , and polymers like PDMS, SU-8, etc. [7, 8, 12]. Most of the researchers are interested to go with SU-8 material because of its improved Young’s modulus and yield strength [9]. Piezoresistive sensing is one of the major integrated technologies into microcantilever sensors which are compatible with external electronic devices [1]. A piezoresistor is placed at the one end of the cantilever beam with some doping concentration. When the target analyte is bonded to the cantilever surface, it encounters a surface stress, resulting in the change in resistance of the piezoresistor. Generally, piezoresistor is connected in the form of Wheatstone bridge format as shown in Fig. 1. Here, the change in resistance leads to a change in output voltage and is given by the equation  Vout

Fig. 1 Wheatstone bridge

 R2 R4 Vin − R1 + R2 R4 + R3

(1)

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2 Design Parameters and Proposed Design of a Cantilever This is considered low-pressure bimolecular detection for BioMEMS application. Figure 2 shows the schematic designs of conventional rectangular beam and our newly proposed high-sensitive cantilever beam design for low-pressure application, with identical piezoresistor at the fixed end of cantilever beam. The design of the proposed cantilever beam consists of four rectangular bar structures having dimensions 10 µm × 50 µm × 0.5 µm, with equally spaced at the flexible end of the cantilever beam. In this work, proposed cantilever beam is going to design with two different materials: SiO2 and SU-8 polymer. The specifications of the materials are listed in Table 1. The proposed cantilever sensor has a piezoresistor which is connected in the form of Wheatstone bridge setup. P-type polysilicon is used for the piezoresistor. The dimensions of piezoresistor are taken as 12 µm × 16 µm × 0.15 µm. A terminal voltage of 3 V is applied to the piezoresistor. The piezoresistive layer doping density is chosen as 10 G [1/m3 ].

Fig. 2 a Normal rectangular cantilever beam, b proposed cantilever beam both having thickness of 0.5 µm

362 Table 1 Material properties of SiO2 and SU-8

M. Lakshmi Prasanna and V. R. Anitha Material property Young’s modulus

Value SiO2 [10]

SU-8 [11]

70 GPa

4.02 GPa

Poisson’s ratio

0.17

0.26

Density

2200 kg/m3

1218 kg/m3

Fig. 3 Free tetrahedral mesh for the proposed cantilever

3 Simulation COMSOL 5.4 multiphysics has been used to design, simulate, and analyze proposed cantilever beam. The piezoresistivity domain current physics and stationary studies have been used for modeling. The cantilever beam is fixed at one end, and the boundary load is applied in the form of the target biomolecule concentration, defined as pressure, and applied in the z direction. Free tetrahedral meshes with ultra-fine element sizes are used for high-quality analysis. The mesh result is shown in Fig. 3. A parameter sweep has been defined for the specified pressure value and thickness value to analyze and compare the proposed cantilever beams for the materials SiO2 and SU-8.

4 Results and Discussion The proposed cantilever beam design has been simulated. When the beam is exposed to some pressure, it results in mass loading effect on the cantilever beam surface. Because of this pressure, cantilever will undergo some deflection, as shown in Fig. 4a.

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(a)

(b)

-110 Rectangular SU-8 Rectangular SiO2 Proposed beam SiO2 Proposed beam SU-8

-100 -90

Displacement (μm)

-80 -70 -60 -50 -40 -30 -20 -10 0 0

3

6

9

12

15 18 Pressure (Pa)

21

24

27

30

Fig. 4 a Sample of displacement for the proposed cantilever beam and b Comparison plot of displacement for the conventional rectangular beam and proposed cantilever beam

A comparison plot of deflection between normal rectangular beam and proposed beam with two materials is shown in Fig. 4b for different pressure values. The deflection the beam undergoes with mechanical stress. This mechanical stress results in change of resistance in piezoresistor which results in change in resistance,

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Resistance of Piezoresistor (PΩ)

65.640 65.560 65.480 65.400 65.320 65.240 65.160 65.080 65.000 0

5

10

15

20

25

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Pressure (Pa)

Fig. 5 Resistance change in piezoresistor for different pressure values

and the change in resistance is shown in Fig. 5. Deflection of beam has been measured with various thickness values by applying 10 Pa of pressure. It is plotted in Fig. 6.

5 Conclusions This study proposes a high-sensitivity MEMS piezoresistive micro-cantilever beam for studying low pressures in the field of BioMEMS which includes heavy metal detection, fungi detection, DNA detection, etc. The characteristics of the proposed cantilever beam are compared with a conventional rectangular microcantilever with the same piezoresistor. The result shows that the deflection of the proposed microcantilever beam is better than the traditional rectangular microcantilever beam. The mechanical stress is caused by the biomolecule absorption, the resistivity of the piezoresistive material is measured. The resistivity in the piezoresistor is noted in the order of PΩ, where for lower change in pressure values give good resistance change in the piezoresistor. It can be clearly seen from results that the proposed cantilever beam with both SiO2 and SU-8 material cantilevers provides better displacement. The linear relationship between the pressure and change in resistance of piezoresistor indicates that the proposed design of cantilever beam works well at lower pressure levels. Also, for optimum thickness levels, the results are good.

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-90 -80 Proposed beam SiO2

-70

Proposed beam SU -8

-60

Rect. beam SU -8

-50

Rect. Beam SiO2

-40 -30 -20 -10 0 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 Thickness (μm)

1

Fig. 6 Deflection of beam for different thickness values

Acknowledgements A Special thanks to the National MEMS Design Centre, Sree Vidyanikethan Engineering College, A. Rangampet, Tirupati, for providing the research facility.

References 1. Guo K, Jiang B, Liu B, Xingeng Li, Wu Y, Tian S, Gao Z, Zong L, Yao S, Zhao M, Mi C, Zhu G (2021) Study on the progress of piezoelectric microcantilever beam micromass sensor. IOP Conf Ser Earth Environ Sci 651:022091. https://doi.org/10.1088/1755-1315/651/2/022091 2. Ali S, Bhuvaneswari H, Kumar B (2020) Design and modeling of a large deflection microcantilever using rectangular SCR. AIP Conf Proc 2281:020037. https://doi.org/10.1063/5.002 7942 3. Rotake D, Darji A (2020) Design and reliability testing of microcantilever-based piezoresistive sensor for BioMEMS application. https://doi.org/10.13140/RG.2.2.25052.92803 4. Ashok A, Nighot R, Sahu N, Pal P, Pandey A (2019) Design and analysis of microcantilever beams based on arrow shape. Microsyst Technol 25:4379–4390. https://doi.org/10.1007/s00 542-019-04555-4 5. Passian A, Thundat T, Thanihaichelvan M (2017) Microcantilever sensors. https://doi.org/10. 1016/B978-0-12-803581-8.10525-9 6. Rotake D, Darji A, Singh J (2020) Ultrasensitive multi-arm-microcantilever-based piezoresistive sensor for BioMEMS application. https://doi.org/10.1109/VDAT50263.2020.9190249

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7. Gharge B, Upadhye V, Bodas D (2015) Design and simulation of microcantilevers for detection of pathogens. https://doi.org/10.1109/ISPTS.2015.7220122 8. Parsediya D (2016) Deflection and stresses of effective micro-cantilever beam designs under low mass loading:111–114. https://doi.org/10.1109/ICEPES.2016.7915915 9. Mathew R, Sankar R (2018) A review on surface stress-based miniaturized piezoresistive SU-8 polymeric cantilever sensors. Nano-Micro Lett 10:1–41. https://doi.org/10.1007/s40820-0180189-1 10. Gopinath PG (2014) Design and characterization of various shapes of microcantilever for human immunodeficiency virus detection. Int J Res Eng Technol 03:24–29. https://doi.org/10. 15623/ijret.2014.0310004 11. Schmid S (2009) Electrostatically actuated all-polymer microbeam resonators—characterization and application 12. Lamba M, Singh K, Chaudhary H (2020) Design analysis of polysilicon piezoresistors PDMS (polydimethylsiloxane) microcantilever based MEMS force sensor. Int J Mod Phys B 34:2050072.https://doi.org/10.1142/S0217979220500721

A Novel General Purpose Switched Capacitor/Varactor Design Concept in RF-MEMS Technology for Emerging 5G/6G and Super-IoT Applications Jacopo Iannacci, Girolamo Tagliapietra, Lakshmi Narayana Thalluri, and Koushik Guha Abstract The currently under-deployment 5G, as well as the future 6G and SuperIoT paradigms, is demanding and will go on demanding for high-performance, frequency agile, and reliable RF passive components, ranging from simple switches to articulated devices, phase shifters, impedance matching tuners, RF power step attenuators, filters, and so on, with pronounced characteristics of reconfigurability and/or tunability. RF-MEMS is one of the most suitable technologies able to meet these challenges, as its recent market absorption is demonstrating. In this paper, we discuss a novel design of switched capacitor/varactor entirely designed in RF-MEMS technology, optimized against a mitigation of the activation (pull-in) voltage, as well as an increase of the ON-state capacitance. In particular, multi-physical simulations are reported and discussed, after having validated the Finite Element Method (FEM) tools against experimental datasets. Moreover, physical samples are currently under fabrication and will be reported in the final paper. Keywords RF-MEMS · RF passive · Varactor · Switched capacitor · 5G · 6G · IoT · Super-IoT · Multi-physical simulation

1 Introduction Radio frequency (RF) microelectromechanical system (MEMS) passives, known with the acronym of RF-MEMS, have been discussed in literature for about 25 years, J. Iannacci (B) · G. Tagliapietra Center for Sensors and Devices (SD), Fondazione Bruno Kessler (FBK), 38123 Trento, Italy e-mail: [email protected] L. N. Thalluri Department of Electronics and Communication Engineering, Andhra Loyola Institute of Engineering and Technology, Vijayawada, A.P. 520008, India K. Guha Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam 788010, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_38

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starting from the first examples around the mid-1990s. Triggered by the achievable remarkable RF characteristics, like high isolation, low loss, wide reconfigurability, and frequency broadband operability [1–7], RF-MEMS technology used to be addressed since the beginning as a good candidate for mass-market applications [8, 9]. Despite such promising expectations, RF-MEMS technology did not gain significant room in the growing (at that time) market of first generations of mobile communications, in particular 2.5G and 3G. In fact, if on one hand MEMS-based RF passives were exhibiting additional issues at technical level, like poor reliability, need for proper packaging and encapsulation, and non-CMOS compatible voltages for switches driving, on the other side, the mentioned wireless standard did not have specific needs for the pronounced RF performance enabled by RF-MEMS technology [10]. The context changed quite radically with the 4G-LTE (Long Term Evolution) standard, and most of all with the spread of smartphones, that made necessary upgrading from the fixed to the adaptive matching of impedance between the Tx/Rx (Transmitting/Receiving) antenna and the active RFFE (RF Front End) [11]. Given such a technology demand, RF-MEMS impedance tuners were the first in line, and this marked the first commercial success of such a technology, starting from around the years 2013–2014. Beyond such a successful exploitation, the interest around high-performance RF passive components in MEMS technology is keeping on growing today, looking at future huge application scenarios, like the currently under-deployment 5G, the future 6G, the Internet of Things (IoT), and the Super-IoT [12–14]. Given such a frame of reference, the interest of research is currently getting back with strength to the manufacturing of highly reliable and high-performance RF-MEMS micro-switches, both ohmic and switched capacitors, as well as varactors (i.e., variable capacitors), as such basic components are crucial building blocks of more complex networks, like multiple-state reconfigurable impedance tuners, phase shifters, filters, and power attenuator. Stepping into more details, when looking at the future scenario of 6G, that is currently being shaped by relevant contributions delivered by eminent scholars, a rather scattered and diversified landscape has to be confronted. This happens because factual standardizations of the 6G do not exist, yet. To this end, a remarkable attempt to simplify such a hectic scenario is proposed by the recent review in [15]. The whole landscape is reconducted to four main Paradigm Shifts (PSs), within which the disruption that 6G will bring at various levels can be reconducted. The first PS has to do with the scattering of Artificial Intelligence (AI) in any part of the network, from the core to the edge, with the twofold target of supporting both the service end of the network, along with its operation, the latter one marking an unprecedented leap with respect to the previous generations [16–20]. The second PS deals with the 6G target of reaching global coverage, that is an extended and diversified infrastructure, featuring classical terrestrial radio towers, integrated with satellites and Unmanned Air Vehicles (UAVs), along with an innovative over-sea and under-sea infrastructure, realizing a space-air-ground-sea integrated network, ensuring the same quality and quantity of services, regardless of

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the particular location at stake, if a metropolitan, rather than rural or remote area [21, 22]. The third PS addresses the vision of an all-spectra allocation of 6G communications, starting from the classical sub-6 GHz frequency bands, ramping up to millimeter-Waves (mm-Waves) and sub-THz (30–300 GHz), again to THz and optical (including visible) frequencies [15]. Finally, the fourth PS addresses the increased issues in terms of security, trust, and privacy of data, that the massive communications triggered by 6G will bring [15]. Wrapping up the just listed PSs, and focusing in particular on the spectrum diversity, it is even more evident how critical will be having at hand RF passives with pronounced characteristics, in terms of frequency agility and reconfigurability. In light of the discussion developed above, this work focuses on a novel design concept of RF-MEMS switched capacitor/varactor, featuring some design solutions to reduce the activation (pull-in) voltage and increase the ON-state capacitance. The paper arrangement follows. After the introduction, Sect. 2 will report on the validation of the electromechanical and RF Finite Element Method (FEM) simulation tools and methodologies, based on the experimental results of a previously fabricated and tested similar design of RF-MEMS switch. Then, Sect. 3 will introduce and discuss the novel design concept, focus of this work, also reporting simulated results concerned to its pull-in characteristics and S-parameters (Scattering parameters) behavior. Finally, Sect. 4 will summarize some conclusive considerations.

2 Validation of the Modeling and Simulation Tools The target of this section is that of validating the Finite Element Method (FEM)-based software tools, utilized in order to predict the coupled electromechanical characteristics of RF-MEMS devices, with particular attention to the pull-in voltage, as well as to their RF performance, looking at the S-parameters (Scattering parameters). Once the validation phase is performed, the accuracy of the simulated results referred to the switched capacitor discussed in the next section will be strengthened in their truthfulness. The validation discussed here is based on an RF-MEMS ohmic micro-relay in series configuration, previously reported and discussed in literature [23]. The microfabrication technology platform, that is the same of the switched capacitor in the next section, capitalizes on a surface micromachining flow, performed on 6 in. silicon wafers and exploiting electroplated gold as MEMS structural material [24], available at the Center for Sensors and Devices (SD) of Fondazione Bruno Kessler (FBK), in Italy. The 3D profile of the target switch for validation purposes, as measured with a static optical profiling system, is shown in Fig. 1. The micro-relay is based on the classical clamped–clamped configuration, in which a central rectangular plate acts as electrostatic transducer, while four slender beams keep it suspended above the underlying fixed electrode and input/output contacts, also providing mechanical restoring force, when the switch is pulled-in.

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Fig. 1 3D rendering of the measured physical sample of the RF-MEMS switch used for validation purposes

Having said that, the electromechanical behavior is simulated within the Ansys Workbench environment, adopting lumped capacitor-like transducers to implement the electrostatic attraction force [25]. The simulation produces in output the vertical displacement of the MEMS membrane versus the applied voltage across the elevated structure and the fixed bottom electrode. Moreover, we characterized experimentally the I-V characteristic of a few physical samples, i.e., the input/output current vs. the applied biasing voltage. The comparison of simulations and experiments is reported in the plot in Fig. 2. Despite the vertical axes of the curves refer to different physical magnitudes, i.e., a mechanical displacement and an electric current, the pull-in transition is well visible in both cases, and the accuracy of the simulation in predicting the pull-in effect around 53 V is straightforward in the plot. Concerning the RF characteristics of the RF-MEMS ohmic switch in Fig. 1, FEM simulations were performed with the Ansys HFSS tool, both in the OPEN (switch OFF) and CLOSE (switch ON) device configurations. From the experimental side, S-parameters were acquired by a Vector Network Analyzer (VNA), connected to the RF-MEMS sample by means of Ground Signal Ground (GSG) micro-probes on a

Fig. 2 Comparison of the I-V measurement of the pull-in characteristic of the RF-MEMS physical sample with the simulated vertical displacement, against the applied biasing voltage

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(b)

Fig. 3 a Comparison of the measured and simulated (a) S11 (reflection) and S21 (isolation) parameters and b S11 (reflection) and S21 (transmission) parameters of the switch in Fig. 1, up to 40 GHz, in the OPEN (switch OFF) and CLOSE (switch ON) state, respectively

probe station [25]. The simulations and experimental measurements were carried out up to 40 GHz, and the comparison is reported in the plots in Fig. 3. Looking at the OPEN state, i.e., Fig. 3a, a good match of the simulated and measured S-parameters curves is visible, both for the reflection (S11) and isolation (S21). Concerning the CLOSE state, i.e., Fig. 3b, the measured traces are more noisy and the difference with respect to simulation is more evident. Anyway, the qualitative match is still satisfactory, both concerning reflection (S11) and transmission (S21). Given the results discussed in this section, the novel RF-MEMS switched capacitor/varactor design concept is now going to be introduced.

3 Novel RF-MEMS Switched Capacitor/Varactor Design Concept The design concept proposed here is still based on a clamped–clamped configuration, despite it features meandered flexible suspensions aimed at mitigating the activation (pull-in) voltage level [26, 27]. The layout of the device, fabricated in the same RF-MEMS technology previously mentioned and available at FBK, is reported in Fig. 4. The device is framed within a Coplanar Waveguide (CPW) structure and exploits a polycrystalline silicon high-resistivity layer, visible in red in Fig. 4, for realizing the DC biasing lines and the fixed electrodes for controlling the MEMS membrane. The RF line exploits the transition to the aluminum-based underpass layer, visible in blue, for realizing the counter electrode of the variable capacitor. The suspended MEMS plate, realizing the movable plate of the capacitor, has in-plane dimensions of 320 by 200 µm and thickness of 5 µm. Moreover, the meandered flexible suspensions are 15 µm wide and their thickness is 2 µm. The air gap, i.e., the clearance between the elevated MEMS structure from the underneath electrode, is about 2.7 µm. The electromechanical behavior of the discussed RF-MEMS design concept is investigated with the Ansys Workbench multi-physical FEM tool. In particular, the pull-in

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Fig. 4 Layout of the RF-MEMS switched capacitor/varactor design concept proposed in this work

behavior is observed by means of static structural simulations. Figure 5 shows the 3D deformed shape of the sole MEMS switch at pull-in, where all the surrounding CPW, pads, and feeding lines were not included in the model, as not relevant to determine the electromechanical behavior of the central membrane. The FEM model predicts the pull-in at 12.5 V, that is significantly lower than that of a traditional MEMS switch with straight suspending beam (see previous Fig. 2). This proves the viability of meandered suspensions instead of traditional anchoring design solutions. The next step consists in observing the RF characteristics of the design concept reported in Fig. 4. To this end, we built a full 3D model of the switch within the Ansys HFSS environment. We also parameterized the height of the MEMS membrane, in such a way to reproduce the OPEN (switch ON) and CLOSE (switch OFF) states. To this regard, it has to be noted that, since this device is a shunt (capacitive) one, its behavior is dual with respect to that of the series (ohmic) switch, previously reported in Sect. 2. The results of RF simulations are plotted in graph reported in Fig. 6. Looking at the OPEN configuration (Fig. 6a), the RF power is nearly entirely reflected starting from about 2–3 GHz and rising, as the S11 trace shows. Differently, isolation (S21) is always better than around − 15 dB, starting from 5 GHz, with the

Fig. 5 3D schematic of the pulled-in membrane in Ansys Workbench. The color scale indicates the extent of vertical displacement

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(b)

Fig. 6 Simulated S-parameters in the a OPEN (switch ON) state, where reflection (S11) and isolation (S21) are plotted, and in the b CLOSE (switch OFF) state, where reflection (S11) and transmission (S21) are plotted, up to 40 GHz

negative peak of around − 45 dB at 12.5 GHz. Concerning the CLOSE configuration (Fig. 6b), reflection (S11) is better than − 20 dB up to 30 GHz, while losses (S21) are below − 1 dB up to 30 GHz, that is a quite remarkable achievement in terms of performance.

4 Conclusion The emerging paradigms of the under-deployment 5G, along with future 6G, Internet of Things (IoT), and Super-IoT, are increasing the need of passives working in the radio frequency (RF) domain, with superior characteristics in terms of wideband operability, frequency agility and reliability. Given such a frame of reference, RFMEMS technology, i.e., microelectromechanical systems (MEMS) for RF applications, is emerging as a crucial asset to score these challenges. In this work, we reported a novel design of switched capacitor/varactor entirely designed in RFMEMS technology, optimized to mitigate the activation (pull-in) voltage and to increase the ON-state capacitance. Multi-physical simulations were reported and discussed, after having validated the Finite Element Method (FEM) tools against experimental datasets.

References 1. McGrath WR, Walker C, Yap M, Tai YC (1993) Silicon micromachined waveguides for millimeter-wave and submillimeter-wave frequencies. IEEE Microw Guid Wave Lett 3(3):61–63. https://doi.org/10.1109/75.205665 2. Katehi LPB, Rebeiz GM, Weller TM, Drayton RF, Cheng HJ, Whitaker JF (1993) Micromachined circuits for millimeter- and sub-millimeter-wave applications. IEEE Antennas Propag Mag 35(5):9–17. https://doi.org/10.1109/74.242171

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3. Weller TM, Katehi LPB (1995) Compact stubs for micromachined coplanar waveguide. In: 1995 25th European microwave conference, vol 2. https://doi.org/10.1109/EUMA.1995. 337029 4. Goldsmith CL, Yao Z, Eshelman S, Denniston D (1998) Performance of low-loss RF MEMS capacitive switches. IEEE Microw Guid Wave Lett 8(8):269–271. https://doi.org/10.1109/75. 704410 5. Feng ZFZ, Zhang WZW, Su BSB, Harsh KF, Gupta KC, Bright V, Lee YC (1999) Design and modeling of RF MEMS tunable capacitors using electro-thermal actuators. In: 1999 IEEE MTT-S international microwave symposium digest (Cat. No. 99CH36282), vol 4. https://doi. org/10.1109/MWSYM.1999.780240 6. Katehi LPB, Rebeiz GM, Nguyen CT-C (1998) MEMS and Si-micromachined components for low-power, high-frequency\ncommunications systems. In: 1998 IEEE MTT-S international microwave symposium digest (Cat. No. 98CH36192), vol 1, 6–8. https://doi.org/10. 1109/MWSYM.1998.689386 7. Malczewski A, Eshelman S, Pillans B, Ehmke J, Goldsmith CL (1999) X-band RF MEMS phase shifters for phased array applications. IEEE Microw Guided Wave Lett 9(12):517–519 8. Nguyen CTC (2001) Transceiver front-end architectures using vibrating micromechanical signal processors. Top Meet Silicon Monolith Integr Circuits RF Syst SiRF 2001(C):23–32. https://doi.org/10.1109/SMIC.2001.942335 9. Nguyen CT-C (1998) Microelectromechanical devices for wireless communications. In: Proceedings MEMS 98. IEEE. Eleventh annual international workshop on micro electro mechanical systems. An investigation of micro structures, sensors, actuators, machines and systems (Cat. No. 98CH36176), pp 1–7. https://doi.org/10.1109/MEMSYS.1998.659719 10. Iannacci J (2015) RF-MEMS: an enabling technology for modern wireless systems bearing a market potential still not fully displayed. Microsyst Technol 21(10). https://doi.org/10.1007/ s00542-015-2665-6 11. Iannacci J (2017) RF-MEMS technology for high-performance passives the challenge of 5G mobile applications. https://doi.org/10.1088/978-0-7503-1545-6 12. Iannacci J (2021) The WEAF mnecosystem (water, earth, air, fire micro/nano ecosystem): a perspective of micro/nanotechnologies as pillars of future 6G and tactile internet (with focus on MEMS). Microsyst Technol. https://doi.org/10.1007/s00542-020-05202-z 13. Iannacci J (2018) Internet of things (IoT); internet of everything (IoE); tactile internet; 5G—a (not so evanescent) unifying vision empowered by EH-MEMS (energy harvesting MEMS) and RF-MEMS (radio frequency MEMS). Sens Act A Phys 272:187–198. https://doi.org/10.1016/ j.sna.2018.01.038 14. Iannacci J (2018) Surfing the hype curve of RF-MEMS passive components: towards the 5th generation (5G) of mobile networks. Microsyst Technol. https://doi.org/10.1007/s00542-0183718-4 15. You X, Wang CX, Huang J et al (2021) Towards 6G wireless communication networks: vision, enabling technologies, and new paradigm shifts. Sci China Inf Sci 64(1). https://doi.org/10. 1007/s11432-020-2955-6 16. Morocho Cayamcela ME, Lim W (2018) Artificial intelligence in 5G technology: a survey. In: 9th international conference on information and communication technology convergence: ICT convergence powered by smart intelligence, ICTC 2018. https://doi.org/10.1109/ICTC.2018. 8539642 17. Kibria MG, Nguyen K, Villardi GP, Zhao O, Ishizu K, Kojima F (2018) Big data analytics, machine learning, and artificial intelligence in next-generation wireless networks. IEEE Access 6. https://doi.org/10.1109/ACCESS.2018.2837692 18. Li R, Zhao Z, Zhou X et al (2017) Intelligent 5G: when cellular networks meet artificial intelligence. IEEE Wirel Commun 24(5). https://doi.org/10.1109/MWC.2017.1600304WC 19. Han S, Chih-Lin I, Li G, Wang S, Sun Q (2017) Big data enabled mobile network design for 5G and beyond. IEEE Commun Mag 55(9). https://doi.org/10.1109/MCOM.2017.1600911 20. Chih-Lin I, Sun Q, Liu Z, Zhang S, Han S (2017) The big-data-driven intelligent wireless network: architecture, use cases, solutions, and future trends. IEEE Veh Technol Mag 12(4). https://doi.org/10.1109/MVT.2017.2752758

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Design and Analysis of MEMS Varactor for Ka Band Applications Anusmita Kakati, P. S. Ganaraj, Koushik Guha, and M. Kavicharan

Abstract A variable MEMS capacitor for Ka band frequency is designed having high capacitance ratio, less pull-in voltage, less stress misses, and better quality factor. MEMS varactor can be used as a tuning device to tune the frequency of a resonator. MEMS varactor is placed over the Substrate-Integrated Waveguide (SIW)-based resonator. The SIW resonator is designed over a single-layered Rogers RT/Duroid 6002 having dielectric constant εr = 2.94 and tanδ = 0.0012 whose substrate thickness is of 508 μm. The gap between SIW top layer and MEMS structure is 3 μm. MEMS varactor structures with holes and without holes are simulated. Meanders are used to support the membrane, which makes displacement more uniform. The serpentine-structured meanders are suitable as it decreases the pull-in voltage. Pullin voltage of 0.84 V is achieved. The RF behavior of the MEMS variable capacitor depends on UP and DOWN capacitance and air gap between the two plates. The UP capacitance of 3.69 pF and resonance frequency of 39.5 kHz were achieved. When DC voltage is applied to the bottom fixed plate, the DOWN capacitance increases to 166.59 pF. A high Capacitance ratio of 45.14 is achieved. RF analysis of the device is done at 1–40 GHz. Return loss is noted as − 12.21 dB at 27 GHz. The low insertion loss of − 1.97 dB at 27 GHz for the proposed MEMS varactor has made the design suitable for the Ka communication band. This device is first of its kind in the Ka band communication where a minor change in structural parameters will have a huge impact over the response. Keywords RF MEMS varactor · SIW · Pull-in voltage · Insertion loss

A. Kakati · P. S. Ganaraj (B) · K. Guha · M. Kavicharan National MEMS Design Centre, National Institute Technology Silchar, Silchar 788010, India e-mail: [email protected] P. S. Ganaraj School of Electronics Engineering, KIIT Deemed to be University, Bhubaneswar 751024, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_39

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1 Introduction Microelectromechanical systems (MEMS) have been in development since the 1970s, for pressure and temperature sensors, accelerometers, gas chromatographs, and other sensing devices [1]. The MEMS switch for low frequency applications was also shown in the early 1980s, but it has long been the curiosity of the laboratory. They are essentially miniature devices that use mechanical motion to create short circuits or open circuits in transmission lines. Low pull-in voltage and higher capacitance ratio are the main objectives to reach in making MEMS capacitive RF switches and varactors [2]. With the advent of the 5G, there is a surge in the demand of more reliable RF devices. RF MEMS would provide perfect platform where the features of MEMS devices can be harnessed. MEMS-based varactors can be used as a device that would help in tuning the filter designed over a Substrate-Integrated Waveguide Platform. Substrate-Integrated Waveguide structure can be used instead of planar structures stripline/microstrip structures when operated at Ka band (27–40 GHz), as SIWs alleviate the losses and improve the quality factor of the structure. The footprint of the SIW structures can be reduced by different topologies without much affecting the performance of the device [3]. The width of the HMSIW structure and the dimensions of Complementary Split Ring Resonator (CSRR) decide the resonant frequency of the filter [4]. The CSRRs have an equivalent circuit, which is the combination of L and C in parallel. MEMS variable capacitor placed over the CSRR-loaded HMSIW to tune the resonance frequency of the first order HMSIW filter. The MEMS varactor and the complimentary split ring resonator should be coupling directly [5]. In this work, MEMS varactor required at Ka band for tuning of the SIW filter is designed. The perforations are made on the MEMS bridge to reduce the mass of the bridge and residual stress, thereby reducing the pull-in voltage [6]. Four geometries for the bridge are considered, and the parameters like pull-in voltage, switching time, capacitance ratio, and stress on the bridge are measured. Comparative study is made and is found that rectangular structure with perforations is the most reliable design. With the addition of Meanders, reduction in the pull-in voltage was made possible. Serpentine structure meanders help in the reduction of pull-in voltage. CSRR-loaded HMSIW is placed under the movable plate. Switching time is calculated for the design as it gives the transition time between the ON state and OFF state of the switch. ON and OFF state capacitance is calculated to get the capacitance ratio. A better capacitance ratio is required to operate the switch in Ka band. By varying gap between the two plates, all parameters, viz. pull-in voltage, switching time, on and off capacitance, and capacitance ratio, are calculated. Stress analysis is also done by putting pressure on the MEMS bridge. Electromagnetic analysis includes return loss, insertion loss, and isolation loss.

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2 RF MEMS Varactor for Ka Band SIWs consists a substrate sand witched between two metal layers and metallic vials are placed in a straight line which form the wall of the waveguide as shown in Fig. 1a. Complementary Split Ring Resonator is etched over the SIW to form a filter, operating at Ka band. Over the SIW structure, MEMS structure is placed as shown in Fig. 1b. The air gap between these two plates, and it is denoted as d 0 . When a DC voltage is applied to the fixed plate, an electrostatic force will be generated due to which the top plate will move downwards to the SIW line giving off capacitance. The thickness of the MEMS movable beam is 3 μm. In Fig. 1, a HMSIW CSRR is shown. Where, a = b = c = e = 0.2 mm, d = 0.36 mm, p1 = p2 = 1 mm, W = 1.65 mm. First, the simulations are done for MEMS bridge structure which is not having meanders. Later perforations and meanders are added to the structure to reduce the pull-in voltage, improve the switching time, and reduce the residual stress. Both ends of the MEMS bridge are kept fixed.

2.1 Perforations The holes or perforations have a small area as the length of the square perforations can be from 3 to 8 μm. To enhance the switching speed of these MEMS devices or to decrease the squeeze film damping, perforations are done in the beam of the MEMS device. These hole areas should not be more than 65% of the total area of the MEMS device’s structure. By creating perforations, we can decrease the total mass of the beam [6]. As mass decrease, actuation voltage is also reduced so pull-in voltage is also reduced to pull beam in the force’s direction [7].

Fig. 1 a Top view of HMSIW with loaded CSRR. b Side view of the SIW and MEMS structure

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Fig. 2 Type 1 meander and type 2 meander

Table 1 Dimensions of the meanders

Parameters (μm)

Dimensions

w

100

L1

100

L2

900

L3 , L5

50

L4 , L6

450

b1

500

b2

200

b3

500

W2

10

2.2 Meanders By adding meanders to the structure, we can decrease the spring constant [8]. As a result, pull-in voltage and switching time decrease. There are different meandering techniques. In this work, two and four meandering techniques have been used and comparative analysis is made. Two types of meanders are used as shown in Fig. 2a, b. Table 1 shows the dimensions of the meanders in Fig. 3.

3 Theoretical Analysis 3.1 Spring Constant Meanders generally develop spring constant for the system. Whole mechanical behavior of the RF MEMS switch depends on the spring constant of the system.

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Fig. 3 Rectangular bridge with four and two meandering technique, respectively

Meanders help to reduce insertion and increase isolation loss. Meanders are of many types. But serpentine meanders are helpful in case of low pull-in voltage. They consist of rectangular blocks. Each block’s spring constant is determined by [6], k= E W t l

Ewt 3 l3

(1)

Young’s modulus of the metal. Width of the given block. thickness of the given block. length of the given block. As blocks are series with each other, we can write the effective spring constant

as, 1 1 1 1 = + ... keff k1 k2 Km

(2)

where m is the total number of blocks in each meanders. As in the proposed design, there are total four meanders, so total spring constant will be equal to, k = 4k eff . Different materials have different spring constants as their Young’s moduli are different.

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3.2 Pull-In Voltage When a DC voltage is applied to the diaphragm, it will move downwards because of electrostatic force. At a specific value of DC voltage, the diaphragm will come in contact with the SIW plate. This voltage is known as pull-in voltage. It is given as [6], Vpull in =

8K d 3 27ε0 Aeff

(3)

where K = Spring constant of the bridge, d = air gap between the diaphragm and SIW, ε0 = Permittivity of free space, Aeff = Effective area, which is total area of diaphragm (l × w) minus total area of the perforations.

3.3 Switching Time Analysis Switching time can be measured by [6], ts = 3.67

Vp Vs ω0

(4)

Vp = pull-in voltage, Vs = Supply voltage, ω0 = resonance frequency = 2π f 0 . 1 f0 = 2π

/

k m

(5)

m = mass of the diaphragm and k = spring constant.

3.4 Quality Factor and Damping Coefficient Quality factor is calculated by the formula [6], Q=

k 2π f 0 b

where b = damping factor, f 0 = operating frequency, k = spring constant. Damping coefficient is calculated as,

(6)

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b=

3μA2eff 2π d 3

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(7)

μ = viscosity of air, Aeff = Effective area, d = air gap between the diaphragm and SIW. Quality factor is plotted varying the beam thickness and air gap.

3.5 Capacitance Ratio When there is no voltage applied on the MEMS bridge, we get ON capacitance [9]. Con =

ε0 Aeff d + εtdr

(8)

td = Thickness of the SIW plate, εr = relative permittivity of the substrate used in SIW. Now as we apply DC voltage, the MEMS bridge will move down and capacitance increases. At the point when the gap between the two plates becomes zero, that capacitance is called as down state capacitance. Coff =

ε0 εr Aeff td

(9)

3.6 Electromagnetic Analysis When the MEMS switch is in on state, it will give insertion loss and return loss [10]. S11 = / S21 =

− jω0 cu Z 0 2 + j ωcu Z o 4 ω2 (cdown )2 (Z 0 )2

(10)

(11)

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4 Results and Discussion The simulations for finding the Pull-in voltage, switching time, ON and OFF capacitance, Capacitance ratio, Quality factor and Electromagnetic analysis are measured. The stress distribution is shown in Fig. 4 for the Non-meandered structures, and Fig. 5 shows for the meandered MEMS structures. The finite element analysis simulations are carried out using IntelliSuite MEMS tool.

4.1 Electromechanical Analysis Figure 4 shows the perforation effect over the pull-in voltage and switching time for non-meandered MEMS bridge. The results show that with inclusion of perforations we are able to decrease the pull-in voltage in Table 2. Figure 5 shows the displacement of MEMS structure with 4 and 2 meander structures. The 4-meander structure exhibits a low pull-in voltage of 0.84 V. Comparative

Fig. 4 Displacement of the beam with no perforations

Fig. 5 Rectangular MEMS bridge with four meanders and two meanders

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Table 2 Parameters comparison with no perforation and with perforations Parameter

No perforations

Pull-in voltage, V

2

Switching time, μs

13.925

With perforation 1.55 13.206

Table 3 Parameters comparison when meanders are added to the rectangular structure Meandering technique Meandering technique Pull-in voltage (V)

No meander

Two meanders

Four meanders

2.00

1.00

0.84

Switching time, μs

32.59

30.54

25.17

Quality factor (in 10–6)

52.08

8.12

6.76

Table 4 Parameters related to the 4-meander structure Parameter Up capacitance, pf Down capacitance, pf Capacitance ratio

Value 3.69 166.59 45.14

study toward pull-in voltage, switching time, and quality factor of the MEMS varactors with and without meander structure is calculated and tabulated in Table 3. The up capacitance and down capacitance and further, the Capacitance ratio are calculated and tabulated in Table 4.

4.2 Electromagnetic Analysis The device’s RF analysis is done at 1–40 GHz using Eqs. 10 and 11. The insertion loss less than − 10 dB can be said as a good design, and we found it as − 1.97 dB at 27 GHz and − 2.14 dB at 40 GHz. Figure 6 shows the variation of insertion loss for the frequency range 0–40 GHz. The reliability depends on return loss, and it should be better than − 10 dB and we have found it to be as − 12.21 dB at 27 GHz. Hence, the switch can be used between 0 and 40 GHz effectively and suitable for Ka band communication.

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Fig. 6 Insertion loss (a) and return loss (b) of MEMS varactor for range 0–40 GHz

5 Conclusion The RF behavior of this MEMS varactor will directly depend up and down capacitance and air gap between the two plates. Air gap between the SIW and MEMS bridges is taken as 3 μm. With no voltage applied, the varactor is in off state, thus giving rise to the UP capacitance of 3.69 pF and resonance frequency of 39.5 kHz. As we apply DC voltage, the MEMS bridge will move down and capacitance increases. At the point when the gap between the two plates becomes zero, that capacitance is called as DOWN state capacitance and we found it as 166.59 pF. Tuning range of the SIW filter can be increased with better capacitance ratio that has been achieved in this work. A high capacitance ratio of 45.14 has been achieved. The RF analysis is done for the frequency range 1–40 GHz. The insertion and return loss is found to be − 2.14 and − 12.21 dB at 40 GHz. The low insertion loss and low pull-in voltage has made the proposed MEMS varactor suitable for the 5G FR2 which is under the Ka communication Band. Further, miniaturization can be achieved by replacing the HMSIW topology with Quarter Mode SIW (QMSIW) topology without much effecting the response of the structure in terms of Insertion and Return losses.

References 1. Shekhar S, Vinoy KJ, Ananthasuresh GK (2018) Low-voltage high-reliability MEMS switch for millimeter wave 5G applications. Micromech Micro Eng 28(7):1, 15 2. Shah DR, Sharma R, Varshney HK (2017) Study of RF-MEMS capacitive shunt switch for microwave backhaul applications. J Electron Commun Eng 12(1):57–65 3. Shimada S, Ootomo I, Ishii S, Ohi K, Hirotani H (1970) Millimeter-wave directional filter. IEEE Trans Microw Theory Tech 18(1):61–62 4. Uysal S (1997) Microstrip loop directional filter. Electron Lett 33(6):475–476

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5. Wang Y, You C, Zhu X (2009) Half-mode substrate integrated waveguide (HMSIW) directional filter with complementary split ring resonator (CSRR). In: 2009 Asia specific microwave conference 6. Rebeiz GM (2003) RF MEMS theory, design and technology. Wiley. ISBN: 0-471-20169-3 7. Fang DM, Li XH, Yuan Q, Zhang HX (2010) Effect of etch holes on the capacitance and pull-in voltage in MEMS tunable capacitors. Int J Electron 1439–1448 8. Guha K, Parmer A, Kumar M, Baishya S (2014) Non uniform meander based low actuation voltage high capacitance ratio RF MEMS shunt capacitive switch 9. Muldavin JB, Rebeiz GM (2000) High-isolation CPW MEMS shunt switches—part 1: modeling. IEEE Trans Microw Theory Tech 48(6):1045–1052 10. Srinivasa Rao K, Thalluri LN, Guha K, Girija Sravani K (2018) Fabrication and characterization of capacitive RF MEMS perforated switch

Design and Simulation of Parallel Plate-Comb Type Mems Capacitive Accelerometer Using COMSOL C. S. Likhith , K. Asha , and Narayan Krishnaswamy

Abstract An overview on design of MEMS accelerometer involving parallel plate mechanical suspension is analysed. It is built using single-crystal isotropic silicon on the platform ‘COMSOL Multiphysics’. Stepwise analysis is performed to know the effect of structural parameters on Von Mises stress, displacement, eigenfrequency, change in capacitance and also frequency response bringing in the concept of finite element analysis (FEA) by considering g in the range of 0–500 m/s2 . All the relations between capacitance and acceleration are interpreted by plotting a graph considering various values, and its application can be well defined in detecting mechanical properties efficiently. Keywords MEMS accelerometers · Eigenfrequency · Perforated proof mass · Frequency response · Capacitance · COMSOL multiphysics

1 Introduction Accelerometer is an electro-mechanical device that can convert mechanical forces such as motion, vibration and shock into an electrical signal that can be measured and recorded. This paper mainly focuses on the development of parallel plate-comb type MEMS capacitive accelerometer [1]. The design is simulated using COMSOL Multiphysics Software. Capacitive sensing technique is used to design the accelerometer in this paper, designing an accelerometer with capacitive sensing method has many advantages like linear output, high sensitivity, etc. COMSOL Multiphysics is a tool by finite element analysis solver with Multiphysics simulation environment [2]. It is a unified workflow C. S. Likhith (B) · K. Asha (B) · N. Krishnaswamy (B) Department of Electronics and Communication Engineering, Sai Vidya Institute of Technology, Bangalore, VTU, Bangalore 560064, India e-mail: [email protected] K. Asha e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_40

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for electrical, fluid, mechanical, acoustics and chemical applications and also brings a user interface and experience. A square proof mass at the centre of the structure to which the force is applied in one direction, for transverse moment of proof mass the maximum displacement of proof mass should be less than the gap between the coupled finger [3]. The acceleration determination is based on change in capacitance between the fingers of the proof mass and fixed fingers, a series of fingers have been attached to detect the change in capacitance, when the force is being applied to the proof mass in one direction producing the displacement.

2 Literature Survey The design of mems accelerometer is still active research. Limited research simulations are done under COMSOL Multiphysics platform in order to analyse the relations between stress, displacement and frequencies, but none of them targeted on finding relationships between parameters considering a particular range of acceleration values, i.e. 0–500 g. So, this research paper gives a detailed analysis of designing a mems accelerometer and relation between parameters is found using COMSOL Multiphysics. The amplitude range of the accelerometer ranges from 0 to 500g. The production of MEMS accelerometers is based on trial and error method rather than explicit design principles. MEMS fabrication and testing are expensive, extensive modelling and simulation can be for evaluating the various designs, performing parametric analyses, and virtual prototyping each MEMS design is necessary [4]. To analyse the characteristics of the device, we have determined the following: an eigenfrequency, displacement, Von Mises stress, change in capacitance vs acceleration and displacement vs frequency. The results have matched the theoretical data, and the following observation table has been attached below.

3 Methodology Finite element analysis is adopted in which analytical modelling of mechanical suspension systems, and simulation is done using COMSOL Multiphysics. Finite element analysis (FEA) is commonly used to examine microstructures in the development of micro electro-mechanical systems. Stress, resonance, deformation, temperature distribution, EM (electromagnetic) interference and electrical properties are determined. This method allows for easy expansion of device performance while also decreasing the time and cost of MEMS fabrication [5].

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4 Modelling The MEMS accelerometer is designed under the study of solid mechanics on COMSOL Multiphysics platform. The material which is used to carry out the design is single-crystal isotropic silicon having Youngs modulus of 170 GPa and poisons ratio of 0.28, respectively [6]. Nine equally sized movable fingers are placed along with the equally sized fixed fingers attached to the vertical rod on either side between the parallelly placed beams [7]. The union of the design is subdivided into minute micro particles as per finite element analysis methodology utilizing the free tetrahedral meshing. In the later phase, perforations are created in order to increase the eigenfrequency to the expected frequency range as mass and frequency are inversely proportional [8]. A single axis resonating accelerometer with sensing element is discussed. Analogue feedback circuit is used in this work [9]. A temperature compensation method using tuning fork is developed for the capacitive accelerometer. Double ended tuning fork resonator is integrated into the device. A precise temperature sensing is possible with the help of two sensors [10]. A very high-resolution area change concept-based MEMS capacitive accelerometer proposed for tilt sensing acts as a transducer. It works on the concept of capacitive displacement. The fabrication steps include lift-off process, deep reactive ion etching (DRIE) process, electroplating and dicing and electric banding by using gold-tin material [11]. A gold proof mass accelerometer which has pillar shaped electrodes as MEMS capacitive accelerometers are suitable for capacitive sensitivity analysis [12]. In literature, out-of-plane (z-axis) accelerometer that employs two distinct MEMS capacitive electrode architectures in tandem to create a linear closed-loop system is available. The complexity of the sensing element’s design and fabrication stages is kept to a minimum throughout implementation. A capacitive MEMS sensing element produced with a 4-mask method is used in accelerometer [13]. Using a set of vertical and horizontal electrodes, this work describes an integrated multi-axis MEMS capacitive accelerometer. All detecting electrodes are positioned on a single silicon proof mass was used. A set of newly designed movable and fixed, vertical and horizontal comb electrodes of various lengths was used to detect 3-axis acceleration. The transduction mechanism based on capacitance used in the structure provides excellent reliability, low drift, low temperature sensitivity and low power consumption [14]. A variety of read out method such as CPC, CVC and sigma delta modulator concepts incorporated to find gravity of acceleration [15]. Simulation of parallel plate-comb type MEMS capacitive accelerometer is discussed in this article. The accelerometer without fingers and perforations modelling is shown in Fig. 1. The modified simulation of parallel plate-comb type MEMS capacitive accelerometer with fingers and without perforations modelling is given in Fig. 2. Figure 3 shows simulation of parallel plate-comb type MEMS capacitive accelerometer with fingers and with perforations modelling.

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Fig. 1 MEMS capacitive accelerometer without fingers and perforations modelling

Fig. 2 MEMS capacitive accelerometer with fingers and without perforations modelling

5 Analytical Values The analytical values used in the simulation are given below. I.

The mass (m in µkg) = S 2 . 1. 2.

CASE 1—m1—without perforations—m1 = 0.0257 µkg CASE 2—m2—with perforations—m2 = 0.020041 µkg

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Fig. 3 MEMS capacitive accelerometer with fingers and with perforations modelling

II. III. IV.

The force (F in µN) = ma. K(x)/K(y) ≥ 5000 Natural frequency (ω) ≥ 10,000

V.

For case g = 400: C1 = Nf * ε0 * A * (1/(g1 − y) + 1/(g2 + y)) = 3.47 nF. C2 = Nf * ε0 * A * (1/(g1 + y) + 1/(g2 − y)) = 3.35 nF. Material used—singe crystal isotropic silicon. The material property used in the simulation are listed in Table 1.

Table 1 Property of the material S. No.

Property

Symbol

Value

1

Density

Rho

2329 kg/m3

2

Young’s modulus

E

170 × 109 Pa

3

Poisson’s ratio

ν

0.28

4

Coefficient of thermal expansion

α ISO

2.6 × 10–6 [1/K]

5

Heat capacity at constant pressure

Cp

700 (J/kg*K)

6

Relative permittivity

∈r_iso

11.7

7

Thermal conductivity

k iso

130 [W/(m*K)]

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6 Results 6.1 Eigenfrequency The eigenfrequency for all the three sections that is, the modelling without fingers, with fingers and with perforations are studied individually and the results are tabulated. Eigenfrequency value is 10,000 Hz used in the simulation. Eigenfrequency of all three cases namely without fingers, with fingers and with perforation is given in Table 2. In the later phase, the eigenfrequency reduces as the fingers are attached to the proof mass. The frequency is thus enhanced further by creating perforations. The shape of the perforations can be of any shape, i.e. circle, square, rectangle, etc. The main aim of the creating perforations is to reduce the mass of the proof mass. Figure 4 shows the MEMS capacitive accelerometer without fingers for Eigenfrequency = 9647.2 Hz. Figure 5 shows the MEMS capacitive accelerometer with fingers eigenfrequency = 8844.4 Hz, and Figure 6 shows MEMS capacitive accelerometer with eigenfrequency = 9774.9 Hz. In Fig. 4, the eigenfrequency is maximum as mass of the model is the least as compared to the other two sections. Table 2 Eigenfrequency of all three cases

S. No.

Cases

Symbol

F in Hz

1

Case1

Without fingers

9647.2

2

Case2

With fingers

8844.4

3

Case3

With perforations

9774.9

Fig. 4 MEMS capacitive accelerometer without fingers—eigenfrequency = 9647.2 Hz

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Fig. 5 MEMS capacitive accelerometer with fingers eigenfrequency = 8844.4 Hz

Fig. 6 MEMS capacitive accelerometer with perforation—eigenfrequency = 9774.9 Hz

Subsequently in the further cases, the eigenfrequency varies with respect to the addition or deletion of certain amount of mass from the proof mass or onto it. There are various types of eigenfrequencies that are dealt under COMSOL Multiphysics, out of which the efficient and the most general one is used in analysis. The eigenfrequency is analysed in three different cases as shown in the figure above. The considered frequency for the research is 10,000 Hz, so initially without any fingers, the frequency is close to the optimum frequency value considered. When the fingers are added, the eigenfrequency is reduced to 8844.4 Hz. In order to increase

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this value to the optimum value again, perforations are created and then the eigenvalue is calculated. The result is found to be 9774.9 Hz.

6.2 Stress and Displacements A sample of ten values are taken for acceleration, and accordingly, the force is calculated using the formula (F = ma). I.

Section A—Without fingers

Von Mises stress and displacement for the MEMS capacitive accelerometer without fingers is shown in Figs. 7 and 8. The stress and displacements vary for all the different sections starting from that of a model with no fingers neither perforation to that of a complex model having both perforations and also fingers. The movements of the fingers and the proof mass is analysed by applying force on a single rectangular region shown in Fig. 7 having the other end fixed by usage of fixed constraints wherever necessary. II.

Section A—Without fingers

The above figures depict the stress and displacement in the design where in no fingers are attached. After the force is applied to one of the sides of the accelerometer, the

Fig. 7 Stress the MEMS capacitive accelerometer without fingers

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Fig. 8 Displacement the MEMS capacitive accelerometer without fingers

displacement is clearly shown with the reference strips and is found to be in the range of 1 µm. Table 3 shows the stress and displacement variation in the modelling with no fingers. Table 3 Stress and displacement variation in the modelling with no fingers S. No.

Acceleration (m/s2 ) (g)

Force (F1) (µm)

Stress (mega) N/m2

Displacement (µm)

Case1: with no fingers 1

0

0

0

0

2

50

12.447

1.2

0.124

3

100

24.895

2.4

0.2489

4

150

37.343

3.7

0.3734

5

200

49.790

4.9

0.4797

6

250

62.230

6.2

0.6223

7

300

74.686

7.4

0.7468

8

350

87.134

8.7

0.8713

9

400

99.581

9.9

0.9958

10

450

112.029

11.2

1.12

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With fingers and without perforations

Stress and displacement of the MEMS capacitive accelerometer with fingers is shown in Figs. 9 and 10, respectively. Stress and displacement variation in the modelling with fingers is shown in Table 4.

Fig. 9 Stress of the MEMS capacitive accelerometer with fingers

Fig. 10 Displacement of the MEMS capacitive accelerometer with fingers

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Table 4 Stress and displacement variation in the modelling with fingers S. No.

Acceleration (m/s2 ) (g)

Force (F1) (s2 )

Stress (mega) N/m2

Displacement (µm)

Case 2: with fingers 1

0

0

0

0

2

50

12.447

1.25

0.125

3

100

24.895

2.52

0.25

4

150

37.343

3.75

0.38

5

200

49.790

5.1

0.5

6

250

62.230

6.3

0.63

7

300

74.686

7.5

0.75

8

350

87.134

8.8

0.88

9

400

99.581

10

1.01

10

450

112.029

11.3

1.16

IV.

Section C—With fingers and with perforations

Von Mises stress and displacement of the MEMS capacitive accelerometer with perforations is shown in Figs. 11 and 12, respectively. Stress and displacement variation in the modelling with fingers is shown in Table 5. The above figures are simulated by creating perforations on the proof mass, and the displacement is clearly visible among the sections of movable fingers and also the proof mass. The Von Mises stress is calculated is a similar manner, and the values are noted by keeping the applied force on a single axis of the accelerometer constant.

Fig. 11 Stress of the MEMS capacitive accelerometer with perforations

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Fig. 12 Displacement of the MEMS capacitive accelerometer with perforations

Table 5 Stress and displacement change in the modelling with fingers and perforations S. No.

Acceleration (m/s2 ) (g)

Force (F1) (s2 )

Stress (mega) N/m2

Displacement (µm)

Case 3: perforations 1

0

0

0

0

2

50

9.82

0.98

0.09

3

100

19.64

1.9

0.19

4

150

29.46

2.9

0.29

5

200

39.28

3.9

0.39

6

250

49.1

4.9

0.49

7

300

58.92

5.9

0.59

8

350

68.74

6.9

0.69

9

400

78.56

7.9

0.79

10

450

88.38

8.9

0.89

6.3 Capacitance with Change in Capacitance See Table 6.

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Table 6 Change in capacitance S. No.

Acceleration (m/s2 ) (g)

Displacement (µm)

Capacitance C1 (nF)

Capacitance C1 (nF)

ΔC = |C2 − C1|

1

0

0

3.3999

3.3999

0

2

50

0.98

3.4089

3.3911

0.0178

3

100

0.19

3.4175

3.3831

0.0344

4

150

0.29

3.4272

3.3745

0.0527

5

200

0.39

3.437

3.3662

0.0708

6

250

0.49

3.4471

3.582

0.0889

7

300

0.59

3.4575

3.3503

0.1072

8

350

0.69

3.4681

3.3426

0.1255

9

400

0.79

3.4790

3.3352

0.14380

10

450

0.89

3.4901

3.3279

0.1622

6.4 Output Graphs 6.4.1

Frequency Response

A quantitative measure of the device output and its spectrum is in response to a stimulus that is used to describe the system dynamics. Here, total displacement and the frequency are compared and the final graph is generated whose peak value is almost equal to the assumed natural frequency of 10,000 Hz. The frequency response is shown in Fig. 13.

6.4.2

Acceleration Versus Displacement

A linear graph is obtained which shows they are directly proportional is shown in Fig. 14.

6.4.3

Capacitance Graph

Demonstrates individual capacitances and shows how they are related as in Fig. 15.

6.4.4

Change in Capacitance Versus Acceleration

The individual capacitances are subtracted to obtain the ΔC and is thus compared with acceleration to obtain a linear graph as shown in Fig. 16.

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Fig. 13 Frequency response

Fig. 14 Acceleration versus displacement curve

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Fig. 15 Acceleration versus capacitances curve

Fig. 16 ΔC versus acceleration

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7 Conclusion In this article, we have summarized the design of MEMS accelerometer and various parameters are compared with respect to acceleration and capacitance in accordance with the area of the proof mass. Linear relationships are obtained between parameters of displacement and acceleration and also between change in capacitance to that of acceleration, and these types of accelerometers can be used for mechanical property detection by setting the acceleration due to gravity between 0 and 500 m/s2 . Acknowledgements The authors like to thank SVIT, Bangalore and also thank Bhoomika C. S. (Project assistant, CENSE—IISc, Bangalore) for their expert advice and encouragement throughout this project.

References 1. Andrabi Z, Gupta KA (2018) Study and analysis of materials for design of MEMS capacitive accelerometer. In: 2018 3rd IEEE international conference on recent trends in electronics, information & communication technology (RTEICT), pp 2183–2187. https://doi.org/10.1109/ RTEICT42901.2018.9012505 2. Maj C, Napieralski A (2017) Mechanical simulation of 3-axis accelerometer using a single proof-mass. In: 2017 XIIIth international conference on perspective technologies and methods in MEMS design (MEMSTECH), pp 47–50. https://doi.org/10.1109/MEMSTECH.2017.793 7530 3. Maj C, Szermer M, Jankowski M (2019) Influence of fringing field on estimating of comb-drive accelerometer performance. In: 2019 IEEE XVth international conference on the perspective technologies and methods in MEMS design (MEMSTECH), pp 67–70. https://doi.org/10.1109/ MEMSTECH.2019.8817397 4. Szermer M, Nazdrowicz J, Zabierowski W (2017) FEM analysis of a 3D model of a capacitive surface micro machined accelerometer. In: 2017 14th international conference the experience of designing and 16 application of CAD systems in microelectronics (CADSM), pp 432–434. https://doi.org/10.1109/CADSM.2017.7916168 5. Trifunovic M, Vadiraj AM, van Driel WD (2012) MEMS accelerometers and their bioapplications. In: 2012 13th international thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems, pp 1/7–7/7. https://doi.org/10.1109/ ESimE.2012.6191749 6. Yusof N, Bais B, Soin N, Majlis BY (2021) Beam parameters optimization of MEMS piezoresistive accelerometer by using response surface method. IEEE Regional Symp Micro and Nanoelectron (RSM) 2021:161–164. https://doi.org/10.1109/RSM52397.2021.9511599 7. Bhalla N, Li S, Chung DW (2011) Finite element analysis of MEMS square piezoresistive accelerometer designs with low crosstalk. In: CAS 2011 proceedings (2011 international semiconductor conference), pp 353–356. https://doi.org/10.1109/SMICND.2011.6095815 8. Baldasarre L, Tocchio A, Urquia MA, Zerbini S (2013) Lattice structure for a critically damped high-G MEMS accelerometer. In: 2013 symposium on design, test, integration and packaging of MEMS/MOEMS (DTIP), pp 1–2 9. Kose T, Terzioglu Y, Azgin K, Akin T (2016) A single-mass self-resonating closed-loop capacitive MEMS accelerometer. IEEE Sens 2016:1–3. https://doi.org/10.1109/ICSENS.2016.780 8711

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10. Kose T, Azgin K, Akin T (2016) Temperature compensation of a capacitive MEMS accelerometer by using a MEMS oscillator. IEEE Int Symp Inertial Sens Syst 2016:33–36. https://doi. org/10.1109/ISISS.2016.7435538 11. Rao K et al (2020) A high-resolution area-change-based capacitive MEMS accelerometer for tilt sensing. IEEE Int Symp Inertial Sens Syst (Inertial) 2020:1–4. https://doi.org/10.1109/INE RTIAL48129.2020.9090016 12. Atsumi K et al (2019) Pillar-shaped electrodes for 3-axis gold-proof-mass MEMS capacitive accelerometers. In: 2019 symposium on design, test, integration & packaging of MEMS and MOEMS (DTIP), pp 1–4. https://doi.org/10.1109/DTIP.2019.8752744 13. Terzioglu Y, Kose T, Azgin K, Akin T (2015) A simple out-of-plane capacitive MEMS accelerometer utilizing lateral and vertical electrodes for differential sensing. IEEE Sens 2015:1–3. https://doi.org/10.1109/ICSENS.2015.7370306 14. Momen HG, Tavakoli H, Sani EA (2016) A 3-axis MEMS capacitive accelerometer free of cross axis sensitivity. In: 2016 24th Iranian conference on electrical engineering (ICEE), pp 1491–1494. https://doi.org/10.1109/IranianCEE.2016.7585757 15. Zhang H, Wei X, Jiang Z (2018) Comparison study of three readout methods for a capacitive MEMS accelerometer. IEEE Sens 2018:1–4. https://doi.org/10.1109/ICSENS.2018.8589648

Modulated Scattering Technique (MST) Devices Hybridized with RF-MEMS Micro-switches for Next Generation IoT and 5G Smart Sensors Massimo Donelli, Mohammedhusen Manekiya, and Jacopo Iannacci

Abstract Wireless sensor industry is driven by challenging paradigm of the Internet of things (IoT) devices and the 5th generation of wireless communications (5G). However, the near field devices have a lot of potential due to their low-power consumption, with the downside of covering a typically shorter range. This paper addresses the challenge of increasing the range by utilizing a modulated scattering technique (MST)-based wireless sensor integrated with a micro-switch realized in microelectromechanical systems (MEMS) technology for radio frequency (RF) applications. Our hybrid MST-RF-MEMS sensor prototype has been reviewed in real-time outdoor scenarios for environmental parameter sensing as well as for an indoor air quality monitoring system. The employed RF-MEMS switch is highly miniaturized and exhibits good performances and RF characteristics for frequencies up to 110 GHz. Numerically designed proposed MST-RF-MEMS prototype sensor has been fabricated and experimentally assessed. The achieved results are adequate and prove that the prototype RF-MEMS based sensor significantly increases the addressed communication range. The integration of the MST and RF-MEMS switch in the sensor system reveals its essential role for designing the next generation near field sensors in the millimetre and sub-millimetre frequency bands, where standard RF switches are unable to operate. Keywords Modulated scattering technique (MST) · Electromagnetic scattering · Wireless sensors · RF-MEMS · 5G · 6G · IoT

M. Donelli · M. Manekiya Department of Information Engineering and Computer Science, University of Trento, Trento, Italy J. Iannacci (B) Center for Sensors and Devices (SD), Fondazione Bruno Kessler (FBK), Trento, Italy e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_41

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1 Introduction The 5th generation of wireless communications (5G) and the Internet of things (IoT) has changed the paradigm of low-power devices and wearables. In parallel, new materials and computer-aided design methodologies enable innovative and low-cost RF and microwave components and systems. Emerging wireless technologies such as tablets, smartphones, smartwatches, ZigBee, and wireless sensor networks (WSNs) [1, 2] are massively driven by the 5G and IoT paradigms, urging for trends like miniaturization, energy efficiency, high-speed data transmission, and increased bandwidth. Semiconductor switches based on microelectromechanical systems (MEMS) or pin-diodes [3] or using a varactor diode [4] can accomplish the demand of current and new-generation devices(5G). Physical sensors such as temperature, pressure, and monitoring of gases are used extensively in home appliances and the automotive industries. Wireless sensors have a great demand in the biomedical field to manage real-time monitoring functionalities, such as intelligent sensor systems that can remotely analyze the heart rate, blood volume pulse [5], and respiration rate. An extensive survey like [6, 7] has highlighted the wireless sensor design challenges and requirement based on the application. More importantly, [7] presented a survey on the passive sensor, designed based on radio-frequencies (RF), acoustic waves, and microwave. In addition, some important RF sensor research work has been illustrated based on characteristics and applications, which needs to be considered for the environment to health and future industries. Despite the advancement of sensors stability, sensitivity, efficiency, and productivity, several commercial sensors are often costly and require proficient individuals for signal analysis. Modulated scattering technique (MST) provides an alternative solution for wireless sensor systems. RF-MEMS switches adopted with MST probe reported in [8] proclaim the stability and linearity of the MST system. Furthermore, the MEMS-based switch provides higher modulation efficiency (ME) and improves the MST system performance. In this paper, we have exploited the RF-MEMS switch with MST for an indoor-outdoor environmental sensor system. In the following section, MST system description with the mathematical formulation is discussed. Finally, experimentally accessed results are examined, and based on it, the concluding remarks have been made.

1.1 System Description and Mathematical Formulation The proposed MST-RF-MEMS-based sensor system comprises two sections such as (1) MST reader and (2) MST tag containing a MEMS switch. In Fig. 1, a photo of the detailed block diagram of a monostatic MST reader and MST-RF-MEMS tag is shown. The MST reader section structure is a standard monostatic one; it comprises a transceiver antenna, an X band direct digital synthesis (DDS) microwave signal generator USB-SA12A (signal hund), a ferrite circulator, and Gtx = 17 dBi gain horn antenna, as mentioned in [9]. The X band microwave signal generator has a power

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Fig. 1 Detailed block diagram of the proposed MEMS-based MST sensor system

of Ptx = 50 mW, and Gamp = 20 dB total gain of two low-frequency amplifiers. A USB-SA12A (signal hund) causes the prototype size to be more compact and robust. The ferrite circulator is paired with a homodyne receiver, where the receiver has an unequal splitter to feed by the reference signal to the integrated mixer (AKD12000). A low-pass filter of a seventh order equal ripple 0.5 dB has been used to filter the output of the mixer. The low-modulation signal from the backscattered wave was extracted using the coherent detector. The baseband signal has been amplified with two low-noise amplifiers, and at the receiver, detectable power is Prx = −120 dBm. The second block is the MST-RF-MEMS sensor tag has a Tx/Rx patch antenna, three loads Z 1 , Z 2 , and Z 3 RF-MEMS switch, a power splitter, a processing block, and a set of sensors. An incoming RF signal has been converted to DC via a power splitter. The following Friis radar equation [10, 11] provides the distance between the MST reader and tag for the far-field free space conditions with enhanced communication range d b : 1 dˆ = 2

(

Pt x · G t x · λ2 · Atag · G tag · M E (4π )2 · Pr x

) 41 (1)

where the power of an impinging electromagnetic wave is denoted as Ptx , the gain of reader antenna is Gtx , and tag is Gtag . Prx defines least detectable power of the homodyne receiver, and Atag is the aperture cross-section of tag antenna. The electromagnetic wave wavelength is expressed by λ. In Fig. 1, the sensor tag is installed with two electrochemical gas sensors to identify ammonia and other contamination in a placed environment. The temperature/humidity sensor has been installed with the tag to improve the calibration. The proposed RF-MEMS switch has significantly lower power consumption and a higher operative range with high efficiency; 8.3 × 3.6 mm2

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dimension of the tag with an RF-MEMS switch. Regarding returns loss (S11) and isolation, the RF-MEMS switch provides excellent performances for the 0 − 20 GHz frequency span. At MST reader, the backscattered signal’s electric characteristic has been calculated by following equations: ⎡

⎤ ⎡ ⎤ ⎡ ⎤ 1 Z 1 − ᴦ L1 εm + Z ant · ᴦ L0 Z 1 · ᴦ L1 ⎣ 1 Z 2 − ᴦ L2 ⎦ · ⎣ ⎦ = ⎣ Z 2 · ᴦ L2 ⎦ ᴦund 1 Z 3 − ᴦ L3 Z ant Z 3 · ᴦ L3

(3)

where Z Li ,i = 1, 2, 3, and Z ant are the three resistive loads and an antenna patch impedance, respectively. ᴦ Li ,i = 1, 2, 3 estimate backscattered wave amplitude. ᴦ und can be studied by the following equation: ᴦund = S11 +

Sscatt + Sstruct Pinc

(3)

where S struct is an antenna structural term, and it can be neglected. The generated power is Pinc , and return loss S 11 at the MST reader. The reflections of the environment are represented as S scatt . By inverting the Eq. (2), εm , the impedance of the surrounding media can be retrieved. The experimental results for the indoor and outdoor scenarios have been explained in the following section.

2 Results The developed prototype MST-RF-MEMS sensor tag is for the indoor air quality system and outdoor real-time environmental parameter measurement system by respecting the guidelines served in [12]. The proposed prototype’s central unit receives and sends the modulation signal to the modulation circuit. The total dimensions of unit structure are 50 × 35 × 45 mm3 . The dimension changes are due to the replacement of the sensor. In particular, we have utilized two electrochemical gas sensors for the indoor scenario that can detect CO2 , ammonia, hydrogen, smoke, n-butane, and other contamination of gas. An LM35DZ temperature sensor and an HR202 humidity sensor have been used for indoor and outdoor temperature and humidity sensing, respectively. In Genoa (Italy) at the EMC company, the sensors have been calibrated accurately in a climatic chamber (ANGELATONI DY1200) with a temperature and humidity extent of −40C < T < 180C and 10% < H < 98%. The prototype RF-MEMS switch offers an efficiency of ME = 3.2, close to theoretical value and miniaturized the size of the sensor tag. The measurement campaign was performed in regulated environment. When the transmitted sequence from the tag was received correctly, then the operative range r was considered valid. The received output data at the reader were post-processed on a laptop using post-processing algorithm. A three-month campaign was performed to evaluate the

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Fig. 2 a Recovered received signal at the reader. b Detection of signal when sensor tag is inactive

MST sensor’s real-time capability and monitor the humidity and temperature during the summer season. In Fig. 3, the reader can be seen placed outside of the laboratory window, whereas the RF-MEMS tag can be seen placed in front of the building exposed to the weather. The digital laser telemeter (BOSH PLR40C), with an accuracy of ±2 mm, measures the distance of RF-MEMS-tag form MST reader. The microcontroller placed in an MST reader was programmed to take a measurement every thirty-minutes consecutively. Figures 2 and 3 indicate the humidity and temperature values recorded in an indoor and outdoor scenarios, respectively. From the recovered data presented in Fig. 3, it can be noticed the maximum T max = 37 and minimum T min = 12 temperature values were recorded. The official meteorological reports were compared and authenticated the recovered data. These indoor and outdoor experimental results prove the significance of the MST-RF-MEMS system as wireless sensors for next generation IoT devices. Compared to the other considered IoT sensor systems present in the market [6], our proposed system can operate with a higher operative range and low-transmitting power.

3 Conclusion An experiment has numerically designed, fabricated, and tested an MST-RF-MEMS sensor system for indoor and outdoor. The proposed prototype is a monostatic system, the reader has a high gain antenna, and a rectangular patch antenna is connected to the MST-RF-MEMS sensor tag. The combination of MST sensor tag and RF-MEMS is crucial for wireless sensor and IoT system deployment; it results in system efficiency, increased communication range, and power consumption. The experimental results have indicated the significance and prominence of the proposed MST-RF-MEMS system for an appealing alternative to near field IoT systems.

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Fig. 3 a A photo of experimental setup b, c humidity and temperature three-month measurement campaign data. r = 15 m from the reader.

References 1. Viani F, Lizzi L, Donelli M, Pregnolato D, Oliveri G, Massa A (2010) Exploitation of parasitic smart antennas in wireless sensor networks. J Electromagn Waves Appl 993–1003 2. Bellofiore S, Balanis C, Foutz J, Spanias A (2002) Smart antenna systems for mobilecommunication networks. Part 1: overview and antenna design. IEEE Antennas Propagat Mag 145–154 3. Sanchez-Soriano MA, Gomez-Garcia R, Torregrosa-Penalva G, Bronchalo E (2012) Reconfigurable-bandwidth bandpass filter within 10–50%. IET Microwaves Antennas Propag 7(7):502–509 4. Hong JS (2009) Reconfigurable planar filter. IEEE Microwave Mag 73–83 5. Katertsidis NS, Katsis CD, Fotiadis DI (2009) INTREPID, a biosignal-based system for the monitoring of patients with anxiety disorders. In: 2009 9th international conference on information technology and applications in biomedicine, Larnaca, pp 1–6 6. Ehsan S, Hamdaoui B (2012) A survey on energy-efficient routing techniques with QoS assurances for wireless multimedia sensor networks. IEEE Commun Surv Tutor 14(2):265–278

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7. Hallil H et al (2021) Passive resonant sensors: trends and future prospects. IEEE Sensors J 21(11):12618–12632 8. Donelli M, Iannacci J (2019) Exploitation of RF-MEMS switches for the design of broadband modulated scattering technique wireless sensors. Antennas Wirel Propag Lett 18(1):44–48 9. Donelli M, Manekiya M, Iannacci J (2019) Broadband MST sensor probes based on a SP3T MEMs switch. In: 2019 IEEE international symposium on antennas and propagation and USNC-URSI radio science meeting, Atlanta, GA, pp 649–650 10. Picquenard A (1974) Radiowave propagation, MacMillan Bath UK 11. Skolnik MI (1990) Radar handbook. McGraw-Hill, New York 12. Donelli M (2014) Guidelines for the design and optimization of wireless sensors based on the modulated scattering technique. IEEE Trans Instrum Meas 63:1824–1833

Study of Metal-Porous GaN-Based 1D Photonic Crystal Tamm Plasmon Sensor for Detection of Fat Concentrations in Milk Abinash Panda

and Puspa Devi Pukhrambam

Abstract Nowadays, it has become indispensable to precisely detect the fat concentrations in milk to maintain a healthy life. To address this issue, we propose a biophotonics sensor, which works on Tamm plasmon polariton (TPP) technique. The proposed structure is comprised of metal (Ag) integrated 1D photonic crystal (PhC) structure, where the PhC is realized with an alternate arrangements of SiO2 and porous GaN. The numerical computations are performed employing the wellestablished transfer matrix method. Various parameters of the structure like number of period of the PhC, and thickness of the metal layer are sensibly selected in order to accomplish maximum sensing performance. The reflection spectrum is investigated for different fat concentrations in the range 0–33.3%. An optimum sensitivity of 214.28 nm RIU−1 and quality factor of 622.64 is reported, which can be considered as noteworthy performance in the present research scenario. Moreover, the simple structural analysis and cost-effective fabrication techniques make the suggested sensor an apt contender for developing bio-sensing devices. Keywords 1D PhC · TPP · TMM · Reflectance spectrum · Biosensor

1 Introduction Milk is an essential food in every household, which consists of most of the mandatory nutrients for maintaining a healthy life. In particular, milk is the major source of calcium, protein, vitamin A, D, etc., which helps in lowering the risk of bone fracture, diabetes, and blood pressure [1]. The American Heart Association (AHA) has specified that consuming foods containing more fats can boost the cholesterol level in the body and may ends up in heart diseases and stroke [2]. Therefore, it is quite important to retain the quality of milk and its various products. Since its discovery in 1987 by Yablonovitch and John, photonic crystal (PhC) structures have A. Panda (B) · P. D. Pukhrambam Electronics and Communication Engineering Department, National Institute of Technology, Silchar, Assam 788010, India e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_42

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seen a remarkable advancement in various optical domains [3, 4]. PhCs are periodically organized layered structures having different dielectric constants and refractive index in one/two/three dimensions [5]. 1D PhC structures are currently the burning research area owing to its simple structure and low-cost fabrication feasibility [6–8]. When electromagnetic (EM) signal intermingle with such structures, they exhibit a special property known as bandgap. The frequency components that reside within the bandgap are restricted to enter the structure. This property of PhC makes it convenient to realize numerous important applications such as sensors, lasers, Bragg reflectors, absorbers, filters, polarizers, and communication applications [9–12]. Besides, due to the flexibility in layer arrangements, the PhCs outperform distributed Bragg reflector (DBR) based configurations in development of highly sensitive sensors [13]. In the last decade, the concept of plasmonic has perceived a notable progress, and it has evolved as a significant field in the design of photonic biosensors and nonlinear optoelectronic devices. Nevertheless, surface plasmon polariton (SPP) mode supports such plasmonic applications, and they comprise some dispersion compensating components like prisms and gratings, which makes the overall structure more complex [14, 15]. On the other hand, this shortcoming of SPP modes can be overcome by Tamm plasmon polariton (TPP)-based configurations. TPP modes can be excited near the boundary of metal and DBR/1D PhC. Moreover, TPP modes are polarization independent [16, 17]. The TPP-based sensors exhibit a sharp resonance dip with a broad PBG. This resonance dip is highly sensitive to the geometrical parameters, which leads to realization of sensing, filtering, and switching applications [18–21]. The traditional methods to detect the food quality are relatively expensive and consume more time. In the recent years, researchers have explored the photonic sensors as a right alternative to conventional techniques. Abohassan et al. studied defective 1D PhC to measure the fat concentrations in milk [22]. Dias et al. reported a NIR photometer model to sense the amount of water in fresh milk [23]. Dave et al. investigated photonic sensing principle to estimate the water adulteration in milk [24]. Porous materials are the most suitable platform to envisage sensing applications. The pores refer to the small voids in the materials which can be infiltrated with the targeted gaseous or liquid analytes. The porous materials can be the integral part of the 1D PhC, where the % of porosity mainly controls the performance. Nevertheless, there exist various types of porous material like porous Si [25], porous Ta2 O5 [26], etc. to design 1D PhC. We have considered porous GaN owing to its unique optical properties. In this context, porous gallium nitride (GaN) has been proved to be a potential material, which can be easily integrated with numerous active devices compared to the porous dielectrics [27]. GaN offers a good refractive index (RI) contrast along with absolute lattice matching [28, 29]. Lheureux and his team carried out an experimental study by employing wet etching technique [28]. In this research, as per as the authors knowledge is concerned, for the first time, we have investigated a TPP mode characteristics at the interface of thin Ag layer and porous GaN-based 1D PhC structure. The thickness of the Ag layer and period of the PhC is judiciously optimized to obtain high sensing performance. The position

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and intensity of the TPP resonance mode are thoroughly studied for different fat concentrations of milk. Moreover, the porous GaN-based TPP modes can be easily integrated into the photonic technologies. On top of that, we derived a mathematical relation to evaluate the % of fat concentrations in milk with respect to change in the RI. So, the authors believe that the proposed sensor has high potential to be used in the food-processing industry.

2 Proposed Structure and Mathematical Formulation The graphical representation of the suggested sensor has been depicted in Fig. 1. The metal is selected as Ag, and the 1D multilayer structure is consisted of porous GaN and SiO2 alternating layers. The entire structure configuration is Ag/(porous GaN/SiO2 )N /substrate. The symbol N denotes the number of periods of the PhC. The pores are the tiny holes which are infiltrated with the milk containing different fat concentrations. The incident light is assumed to be transverse electric polarized, which strike on the said structure along the x-direction at an angle of 0◦ . The reference wavelength is set at 800 nm. The optimized thickness of Ag (M), porous GaN (A), and SiO2 (B) are chosen as dM = 40nm, dA = 255nm, and dB = 120nm, respectively. The number of period is selected as N = 6. The percentage of porosity of the GaN layer is considered as 53% because it was experimentally synthesized and various characteristics were measured at this level of porosity. The RI of different concentrations (%) of fat present in commercial milk is presented in Table 1 [22]. Milk holds mostly water particles, and the RI of water

Fig. 1 Structural representation of the proposed TPP sensor

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Table 1 RI of milk corresponding to different fat concentrations

Fat concentrations (%)

Refractive index

0

1.3452

1.5

1.3496

3.3

1.3517

6.6

1.3543

10

1.3564

33.3

1.3657

almost remains constant over a wide wavelength range. So, a very small change in RI is observed for different fat concentrations. The refractive index of the porous GaN is computed by utilizing volume average concept, which is expressed as [30], nporousGaN =

√

(1 − P)n1 2 + Pns 2

(1)

where n1 signifies the RI of GaN, ns denotes the RI of the infiltrated analyte, and P represents the ratio of porosity. The RI of GaN (n1 ) and SiO2 (nSiO2 ) can be evaluated by the following Sellmeier equations [31, 32], / n1 =

3.6 +

/ nSiO2 =

1+

λ2

4.1λ2 1.75λ2 + 2 λ2 − 17.862 λ2 − 0.256

Aλ2 Bλ2 Cλ2 + 2 + 2 2 2 − 0.06840 λ − 0.11624 λ − 9.896162

(2)

(3)

where A = 0.6961663, B = 0.4079426, and C = 0.8974794 are the Sellmeier coefficients. The RI of Ag is found using the Drude model [33], nAg =

√

/ εAg (λ) =

1−

λ2 λc λp (λc + iλ) 2

(4)

where λp and λc denote the plasma wavelength and collision wavelength, respectively. In the calculation of nAg , we have taken λp = 1.454 × 10−7 m and λc = 1.761 × 10−5 m. Using TMM, the characteristic matrix of any layer t is expressed as [34], (

[ Mt =

cosδt −i∅t sinδt

) ] − ∅i t sinδt cosδt

(5)

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In case of TE polarization mode, δt and ∅t can be expressed as, δt =

2π dt nt cosθt and ∅t = nt cosθt λ

(6)

where nt , dt , and θt imply the RI, thickness, and incident angle of tth layer. Further, the transfer matrix of the whole configuration can be written as [35], [ ] ( )N M (1, 1) M (1, 2) M = MAg MporousGaN MSiO2 = M (2, 1) M (2, 2)

(7)

Using the matrix elements of Eq. (7), the reflection coefficients are computed as below [35], r=

(M (1, 1) + M (1, 2)μsu )μ0 − (M (2, 1) + M (2, 2)μsu ) (M (1, 1) + M (1, 2)μsu )μ0 + (M (2, 1) + M (2, 2)μsu )

(8)

where μ0 and μsu are the parameters associated with the incident medium (air) and the last medium (substrate), respectively. Finally, the numerical expression of reflectance (R) is stated as, R = |r|2

(9)

3 Results and Interpretations Figure 2 demonstrates the reflectance spectrum of the designed structure with and without Ag layer. As shown in Fig. 2a, in the absence of Ag layer, the photonic bandgap is limited to 722.1–847.2 nm. Interestingly, the inclusion of Ag layer in the

Fig. 2 Reflectivity a (porous GaN/SiO2 )N /substrate. b Ag/(porous GaN/SiO2 )N /substrate

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structure leads to increase the bandgap over the whole spectrum and a resonance dip is observed at 790.6 nm as shown in Fig. 2b. The wavelength of the resonance dip is very sensitive to the geometrical parameters, which forms a suitable condition to realize sensing applications. We optimized the metal layer thickness (dM ) for realizing a proper TPP resonance mode with highest performance. Figure 3 shows the characteristics of the resonant mode (i.e. wavelength and intensity) under different values of dM . From this fig., it is apparent that at dM = 40nm, the resonance dip intensity is highest and the FWHM (full width half maximum) is lowest, which indicates high sensing performance like high-quality factor, high detection accuracy, etc. So, we selected optimized value of dM as 40 nm. Next, we optimized the number of periods (N) of the 1D PhC, which is delineated in Fig. 4. It can be noticed that for N = 2 and N = 4, the FWHM is very high, which is undesired from design point of view. On the other hand, for N = 8, although the FWHM is fine, the intensity of the resonant dip is 0.59, which is not acceptable. We found that the best value of N is 6, where the structure offers a notable intensity of resonance dip and FWHM. Figure 5 illustrates the shifting nature of the TPP mode wavelength when the structure is infiltrated with milk of different percentage of fat. It is observed that with increase in fat concentrations, the wavelength of the TPP mode is shifted toward higher wavelengths. The red-shifting of wavelength can be clearly noticed in the Fig. 3 Reflection spectrum for thickness of Ag layer

Fig. 4 Optimization of the number of period

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Fig. 5 The reflectance spectrum of the structure at optimized geometrical parameters for different values of fat concentrations in milk

expanded diagram which is inserted within Fig. 5. As the fat concentration changes from 0 to 33.3%, the resonant wavelength is shifted from 790.6 nm to 793.9%. The red-shifting nature of wavelength is due to the change in effective refractive index of the proposed structure with change in the fat concentrations in milk, which is described using standing wave condition [34], γ = pλres = neff τ

(10)

In Eq. (10), the optical and geometrical path differences are denoted by the symbol γ and τ , respectively. λres designates the TPP mode wavelength, and neff denotes the effective refractive index. The increase in the fat concentration will increase the neff . In order to keep γ constant, the resonance mode wavelength increases to higher value. From Fig. 6, it is perceived that the resonance wavelength increases almost linearly with rise in fat concentrations (F). This nature of variation can be described by linearly fitted equation, λres = 0.0865 × F + 791.36

(11)

Afterward, we evaluated various important sensing performance parameters such as sensitivity and quality factor. Sensitivity is computed as the ratio of shift in resonant mode wavelength to shift in RI of the infiltrated analyte. Quality factor is described as the sensor’s ability to efficiently detect the resonance wavelength. These parameters can be expressed as [36, 37], Sensitivity =

Δλres Δn

(12)

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Fig. 6 Variation in the resonant mode wavelength

Q=

Δλres FWHM

(13)

The variation of sensitivity and quality factors for different concentrations of fat is shown in Fig. 7. It is seen that both sensitivity and quality factors vary nonlinearly with increase in fat concentrations. A maximum sensitivity of 214.28 nm/RIU and quality factor of 622.64 are attained with the proposed sensor. With such optimum performance parameters, we believe that the proposed TPP sensor can be a strong contender for bio-sensing applications. Finally, we compared the performance of the designed sensor with some recently published works, which are presented in Table 2. From this table, it can be clearly observed that the proposed sensor bestows superior performance. Fig. 7 Analysis of sensitivity and quality factor

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Table 2 Comparative analysis References

Configuration

Sensitivity (nm/RIU)

Quality factor

[9]

1D PhC with central defect

74.5098

19.608

[8]

Defect-based 1D PhC

43

–

[20]

Au-TiO2 /MgF2 PhC

17

–

[21]

Ag/1D DBR

10

300

This work

Ag/Porous GaN 1D PhC

214.28

622.64

4 Conclusion In conclusion, the present work addresses a highly sensitive TPP sensor for precise detection of fat concentrations in commercial milk. With integration of Ag with porous GaN-based 1D PhC, a sharp resonance dip is formed in the refraction spectrum. The Ag layer is responsible for formation of a sharp resonance dip due to Tamm plasmon polariton effect. The cornerstone of this article is investigating the TPP resonant mode shift for various fat concentrations in milk. The optimized thickness of the Ag layer is taken as 40 nm, and period of the PhC is selected as 6 to maximize the sensor performance. The TPP sensor bestows a highest sensitivity of 214.28 nm/RIU and quality factor of 622.64, which can be considered as encouraging results. So, the authors claim that the proposed sensor can be a promising candidate for detection of fat concentrations in milk.

References 1. Da Silva Dias L et al (2018) A NIR photometer prototype with integrating sphere for the detection of added water in raw milk. IEEE Trans Instrum Meas 67:2812–2819 2. Saturated Fat (n.d.) American Heart Association. https://www.heart.org/en/healthy-living/hea lthy-eating/eatsmart/fats/saturatedfats 3. Yablonovitch E (1987) Inhibited spontaneous emission in solid-state physics and electronics. Phys Rev Lett 58:2059 4. John S (1987) Strong localization of photons in certain dielectric superlattices. Phys Rev Lett 58:2486 5. Abinash Panda PD, Pukhrambam (2020) Photonic crystal biosensor for refractive index based cancerous cell detection. Opt Fiber Technol 54:102123 6. Panda A, Pukhrambam PD, Keiser G (2020) Realization of sucrose sensor using 1D photonic crystal structure vis-à-vis band gap analysis. Microsyst Technol 27:833–842 7. Panda A, Pukhrambam PD (2021) Investigation of defect based 1D photonic crystal structure for real-time detection of waterborne bacteria. Physica B 607:412854 8. Ramanujam NR, Amiri I, Taya SA, Olyaee S, Udaiyakumar R, Pandian AP (2019) Enhanced sensitivity of cancer cell using one dimensional nano composite material coated photonic crystal. Microsyst Technol 25:189–196 9. Bijalwan A, Singh BK, Rastogi V (2021) Analysis of one-dimensional photonic crystal based sensor for detection of blood plasma and cancer cells. Optik 226(1):165994

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10. Panda A, Pukhrambam PD (2021) A theoretical proposal of high performance blood components biosensor based on defective 1D photonic crystal employing WS2, MoS2 and graphene. Opt Quantum Electron 53:357 11. Sarkar P, Panda A, Palai G (2019) Analysis of 90° bend photonic crystal waveguide: an application to optical interconnect. Indian J Phys 93(11):1495–1500 12. Zhang S et al (2019) Photonic-crystal-based broadband graphene saturable absorber. Opt Lett 44(19):4785–4788 13. Lova P et al (2020) Strategies for dielectric contrast enhancement in 1D planar polymeric photonic crystals. Appl Sci 10:4122 14. Panda A, Pukhrambam PD (2021) Modeling of high-performance SPR refractive index sensor employing novel 2D materials for detection of malaria pathogens. IEEE Trans Nanobiosci. https://doi.org/10.1109/TNB.2021.3115906 15. Panda A, Pukhrambam PD, Keiser G (2020) Performance analysis of graphene-based surface plasmon resonance biosensor for blood glucose and gas detection. Appl Phys A 126(3):153 16. Bikbaev RG, Vetrov S, Timofeev YIV (2020) Hyperbolic metamaterial for the Tamm plasmon polariton application. J Opt Soc Am B 37(8):2215–2220 17. Wang Z, Clark JK, Ho Y-L, Vilquin B, Daiguji H, Delaunay J-J (2018) Narrowband thermal emission realized through the coupling of cavity and Tamm plasmon resonances. ACS Photonics 5:2446–2452 18. Das R, Srivastava T, Jha R (2014) Tamm-plasmon and surface-plasmon hybrid-mode based refractometry in photonic bandgap structures. Opt Lett 39(4):896–899 19. Maji PS, Das R (2017) Hybrid-Tamm-plasmon-polariton based self-reference temperature sensor. J Lightwave Technol 35(14):2833–2839 20. Klimov VV et al (2017) Fano resonances in a photonic crystal covered with a perforated gold film and its application to bio-sensing. J Phys D Appl Phys 50:285101 21. Lheureux G et al (2020) Tamm plasmons in metal/nanoporous GaN distributed Bragg reflector cavities for active and passive optoelectronics. Opt Expr 28:17934–17943 22. Abohassan KM, Ashour HS, Abadla MM (2021) A 1D binary photonic crystal sensor for detecting fat concentrations in commercial milk. RSC Adv 11:12058–12065 23. Silva Dias L et al (2018) A NIR photometer prototype with integrating sphere for the detection of added water in raw milk. IEEE Trans Instrum Meas 67:2812–2819 24. Dave A, Banwari D, Srivastava S, Sadistap S (2016) Optical sensing system for detecting water adulteration in milk. In: IEEE global humanitarian technology conference (GHTC), pp 634–639 25. Gutierrez CF et al (2019) Design, fabrication, and optical characterization of one-dimensional photonic crystals based on porous silicon assisted by in-situ photoacoustics. Sci Rep 9:14732 26. Zaky ZA, Sharma A, Aly AH (2021) Tamm plasmon polariton as refractive index sensor excited by gyroid metals/porous Ta2O5 photonic crystal. Plasmonics. https://doi.org/10.1007/s11468021-01559-7 27. Wang Z et al (2007) 1D partially oxidized porous silicon photonic crystal reflector for midinfrared application. J Phys D-Appl Phys 40(15):4482 28. Lheureux G et al (2020) Tamm plasmons in metal/nanoporous GaN distributed Bragg reflector cavities for active and passive optoelectronics. Opt Expr 28(12):17934–17943 29. Yerino CD et al (2011) Shape transformation of nanoporous GaN by annealing: from buried cavities to nanomembranes. Appl Phys Lett 98(25):251910 30. Zhang C, Park SH, Chen D, Lin DW, Xiong W, Kuo HC, Lin CF, Cao H, Han J (2015) Mesoporous GaN for photonic engineering highly reflective GaN mirrors as an example. ACS Photonics 2(7):980–986 31. Bowman SR et al (2018) Optical dispersion and phase matching in gallium nitride and aluminum nitride. Opt Mat Express 8(4):1091–1099 32. Refractive index of SiO2 (Silicon dioxide, Silica, Quartz)—Malitson 33. Tabassum RD, Gupta BD (2015) Performance analysis of bimetallic layer with zinc oxide for SPR-based fiber optic sensor. J Lightw Technol 33(22):4565–4571

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34. Panda A, Pukhrambam PD, Wu F, Belhadj W (2021) Graphene-based 1D defective photonic crystal biosensor for real-time detection of cancer cells. Eur Phys J Plus 136:809 35. Panda A, Vigneswaran D, Pukhrambam PD, Ayyanar N, Nguyen TK (2021) Design and performance analysis of reconfigurable 1D photonic crystal biosensor employing Ge2Sb2Te2 (GST) for detection of women reproductive hormones. IEEE Trans NanoBiosc. https://doi.org/10. 1109/TNB.2021.3107592 36. Panda A, Pukhrambam PD (2021) Analysis of GaN-based 2D photonic crystal sensor for real-time detection of alcohols. Braz J Phys 51(3):481–492 37. Panda A, Pukhrambam PD, Ayyanar N, Nguyen TK (2021) Investigation of transmission properties in defective one dimensional superconductive photonic crystal for ultralow level bioethanol detection. Optik 245:167733

Reliability Analysis of Thermally Actuated MEMS Micromirror Vikram Maharshi and Ajay Agarwal

Abstract This paper presents a reliability analysis of thermally actuated MEMS micromirror devices. The various factors affecting the reliability of the MEMS micromirror device were analyzed and discussed. The reliability distribution function and lifetime of the MEMS micromirror were analyzed. The series and parallel model reliability model for MEMS micromirror were reported. The p-out-of-n redundancy model was considered to increase reliability for the MEMS micromirror device. This model gives more redundancy to it, and the failure of one or more devices does not affect the system performance. Keywords MEMS · Reliability · Micromirror · Bathtub curve · Fatigue · Actuator · Bimorph

1 Introduction MEMS micromirror is a mechanical device that is used to deflect the light from one point to another point utilized in a wide range of applications like optical endoscopy, project display, barcode scanners [1–4]. Using microfabrication technology, MEMS technology incorporates microsensors and microactuators [5–8]. The miniaturization and multiplicity of batch fabrication make MEMS technology more appealing to a wide range of applications. The microactuator is a driving force of MEMS devices. There is different actuation mechanism like electrothermal, electrostatic, electromagnetic, and piezoelectric actuation used for MEMS sensors. The large actuation displacement with low-applied voltage makes electrothermal actuation more appealing for different applications. The electrothermal actuator works on the joule heating mechanism and coefficient of thermal expansion. The Joule heat is generated V. Maharshi (B) Indian Institute of Technology, Delhi, India e-mail: [email protected] A. Agarwal Indian Institute of Technology, Jodhpur, Rajasthan, India © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_43

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since current is passing through the bimorph actuator, and due to a mismatch in the coefficient of thermal expansion, it leads to the actuator’s deflection. This actuation is transferred to the mirror plate. Higher current passes through the bimorph at lower voltage leads to burn out of the devices, fatigue in the material due to external humidity and temperature, and the failures of the suspended springs and electrodes under the external mechanical shocks lead to the unreliability of the device. Reliability is a device’s ability to perform its designed function without degradation in static and dynamic conditions for a specific time. The fixed electrodes, suspended structures, and selected materials are critical to defining a MEMS device’s function with reliability and accuracy. There is a need to analyze MEMS devices’ reliability since these devices are commercialized now. The reliability and yield of the devices are critical factors of MEMS technology. Nowadays, MEMS devices are embedded in a system on a chip to use in real-life applications. The MEMS sensors are more appealing to safety and alarming critical events. Use of MEMS sensor in applications like a rocket launcher and implantable pills or optical endoscopy. Failure of a MEMS device leads to a disaster and serious threat to human life. Several reports presented on the reliability of MEMS structures [8–11] where the qualitative model for MEMS sensors was presented. The operating condition and environmental effect lead to structural damage and material fatigue. It is critical to know about material fatigue, moisture, humidity, and external shock effects on device performance. To do reliability analysis, we need to examine the device’s packaging, open and short electrical circuit, corrosion, and material degradation due to environmental effects. The challenge for the reliability analysis of MEMS sensors is finding the exact failure mechanism and collecting the statistical data. The model needs to be created by using that statistical data. There were several models for reliability analysis of the micromirror reported previously. This study reports the reliability model of micromirror using a built-in self-repair model and a non-built self-repair model. This paper presented a reliable analysis of the thermally actuated MEMS micromirror. The behavior of the device under the external shock load was explained. The effects of humidity and temperature on the device were analyzed and presented. The life span of the device using the bathtub curve was analyzed.

1.1 Effects of Humidity and Temperature Single crystal silicon, silicon dioxide, and polysilicon are the primary structural materials for MEMS device fabrication. The properties of these materials are well known established there. The mechanical properties still depend on their fatigue and external environment. There were fixed as well as moving objects in the device. The fixed objects had a minimum influence on the external environment since they depended more on fabrication processes. It was observed that fatigue was induced in silicon and polysilicon materials due to a rise in external humidity and temperature. Single crystal silicon is stress-free material at room temperature. That is why siliconbased MEMS devices brought a revolution in this field. Now, we need to analyze the

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Fig. 1 Displacement of thermal bimorph actuator with external temperature

reliability of these devices. Several case studies on humidity and temperature affect silicon and polysilicon material are reported [10, 11]. The bimorph actuator was made of silicon and aluminum material. The aluminum surface will get oxidized in the higher temperature and humidity environment and make rust that behaves as an insulator leads to the device’s failure. The fatigue induced in the silicon material is due to subcritical oxidation and crack growth. The external temperature and humidity play a significant part in crack development. The expression for crack growth in relation to temperature and humidity is shown below. C = Fr f (Hm )e− RT Q

(1)

C denotes crack growth, F r is the frequency component, F (Hm) is the humidity factor, Q is the energy needed for activation, T is the temperature, and R is the constant. The crack growth is directly proportional to the humidity and frequency parameters. It also depends on the exponential function of temperature. The external temperature also directly affects the device performance since its works on the CTE principle. The undesired displacement of the bimorph actuator can be seen with the rise in external temperature, which is shown in Fig. 1.

1.2 Mechanical Shock Effects The external mechanical shock induced stress on the fixed and moveable microstructures. When the level of stress is higher than the material’s yield strength, it leads to the device’s failure. It is necessary to perform a survivability analysis of devices under several mechanical shocks [12, 13] for reliability analysis. To design a single crystal silicon MEMS device, we only consider intrinsic and residual stress. Material deposited or grown on a substrate; stress arises for the contacting surface (growth morphology, lattice misfit, phase transformation); this type of stress is called intrinsic stress and is strongly dependent on the material. Residual stresses are also induced

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Fig. 2 Von mises stress at bimorph actuator to the voltage at 500 g shock load

due to the high-temperature process of film deposition. Since our MEMS micromirror base material is single crystal silicon, induced stress from all the sources should be less than the yield strength of a material that 7 GPa gives, which can be shown in Fig. 2.

1.3 Droop in the Microstructures The MEMS devices are fabricated using a bulk and surface micromachining process. The etching of the sacrificial layer in surface micromachining or the wet release process in bulk micromachining leads to the microstructure’s droop. This droop is the surface tension force that is different at microstructure with air and wet chemical. Due to stiction force, van der wall force, and electrostatic force between microstructure and bottom surface, it is challenging to pull back the microstructure to its original position [14]. This droop of the movable microstructure leads to the device’s failure and increases the unreliability of the system. The initial curling of the mirror plate’s bimorph and droop leads to failure of the MEMS micromirror device. To overcome the droop in the microstructure, the displacement in the y-direction needs to be optimized and used in fabrication constraints.

1.4 Electrical Failures During the MEMS devices’ characterization, an open or short electric circuit in the device is a prominent factor to increase the system’s unreliability. This belongs to the packaging and characterization of the I.C. technology. The electrostatic discharge, dielectric coefficient degradation, ohmic contacts, and electromigration charge lead to failures of electric components. Electrostatic discharge can be induced from the human body and charge environmental effects that lead to the device’s failures. The dielectric degradation leads to the breakdown of the gate oxide or the device’s

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insulator, increasing the system’s unreliability. The degradation of dielectric material initiates the bimorph actuator’s failure, leading to the unreliability of MEMS micromirror design.

1.5 Burnout During the device’s characterization, electrothermal bimorph actuators work on the joule heating and principle of thermal expansion coefficient and require low-actuation voltage to get large displacement. The larger current at low-actuation voltage leads to burn out of the bimorph actuator, increasing the MEMS micromirror device’s failure rate.

1.6 Mechanical Instabilities MEMS device is the combination of the sensors and actuators. The mechanical elements of the devices also affect their device performances. The motion of the moveable electrode is critical for the reliability of the system. The bimorph actuator’s repeatable deformation is difficult due to van der wall force and electrostatic force with the bottom surface. Once the actuator touches the lower body, it is tough to take the original position due to adhesion force, stiction, and van der wall force, leading to increased instability of the device and unreliable MEMS device.

1.7 Corrosion Corrosion is an essential factor that degrades the reliability of the device. The aluminum layer of our bimorph actuator is degraded at external humidity and temperature environment. In aluminum surface-induced corrosion, cracks due to moisture and temperature also lead to instability in the device performance. Corrosion of MEMS micromirror device material leads to the unreliability of the device.

1.8 Reliability Model A device’s reliability is a probability function that a device or a structure behaves correctly for a finite duration of time without any performance degradation. The reliability function Rp (t) defined with a limited period can be expressed as 0 < Rp (t) < 1. The system’s unreliability or failure is the probability function that the device or system will not work correctly at a finite time with specific environmental conditions.

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Fig. 3 The bathtub curve

The failure function can be described as F p (t), so apparently, distribution can be described as Rp (t) + F p (t) = 1. If the probability of reliability function is high, the system will have more reliable and perform without degrading at specific periods. For larger failure functions, the device will not perform appropriately with external environment conditions at a certain period. The rate of failure is given by the total number of failures and duration of time of failure. All the MEMS devices follow the bathtub curve model. The bathtub curve model shown in Fig. 3 presents the reliability rate or the devices’ failure rate to the time. The presented model consists three subareas. First area where the devices’ performance failure rate was high till the time t inf because of the defects that changes the device characteristic. The second subarea is where devices have a stable response with minimum failure rate. The maximum reliability failure rate should be small. In the third stage, failure rate of the devices increases because of the device degradation. In this region, devices were at the end of their life span. The meaning full lifetime of the devices was given by t lifetime = t opr – t inf . The models for reliability distribution had been reported earlier [15, 16]. The distribution models only describe the single component; we also need to analyze the reliability model for a whole device or a system. This kind of model allows the analysis of the reliability of the entire system, sensitivity, and design alternatives of the devices. The different configurations like series, parallel, and p-out-of-n redundancy to use MEMS sensors are presented.

1.9 Series Reliability Model This model is preferable when all the connected component works without degradation in the external environment. The failure of a single component leads to the development of an unreliable system. The model can be seen in Fig. 4. The reliability probability function for a component is given by e−λt . Rp provides the reliability probability function for this series model is given by Rp (t) = R1 + R2 + R3 … Rn . The reliability function Rp (t) is given by e−nλt .

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Fig. 4 Representation of series scheme of reliability model

Fig. 5 Representation of parallel scheme of reliability model

1.9.1

Parallel Reliability Model

This model is preferable when any of the components work without degradation in the external environment. The system will be reliable until all the part degrades and does not behave correctly. The stable performance of a single component leads to develop a reliable system. The representation of the parallel reliability model is shown in Fig. 5. The failure rate of a component is given by λ(t). The reliability probability function for each component is given by e−λt . Rp gives the reliability probability function for this parallel model is given by Rp (t) = 1 – (R1 + R2 + R3 … Rn ). 1 − e−nλt provides reliability with function Rp (t).

1.9.2

Combination Reliability Model

This model is preferable instead of series and parallel models. For stability of this system, minimum p components need to work appropriately, or maximum n-p faulty devices are allowed without losing the system’s operation. The representation of the combination model is shown in Fig. 6. This system configuration provides more redundancy data to model, leading to improving the system’s reliability. The reliability probability function for this configuration is given by Rp(t) = Rn(t) + nRn-1(t) F(t) + · · · + (R(t)k) (F(t)n-k ). The MEMS micromirror design consists of four bimorph actuators that are fixed at one constraint and free to move in another one. The actuators are connected to the mirror plate by four suspended springs. The reliability model of the MEMS micromirror device is a series of combinations of all the components. All the components need to be fault free to function the model correctly.

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Fig. 6 Representation of p-out-of-n redundancy reliability model

Fig. 7 Block diagram of MEMS micromirror reliability model

The representation of the MEMS micromirror reliability model is shown in Fig. 7. The reliability probability function for MEMS micromirror device is given by Rp (t) = ea−4λat . eb−4λbt . es−4λst . em−λmt . To increase the device’s reliability, the p-out-of-n redundancy model was recommendable since it provides more redundancy data to it. For this configuration, n MEMS micromirror device needs to connect in parallel to each other. Only p micromirror device needs to fault free out of n devices to make the system reliable. The representation of the p-out-of-n redundancy model of MEMS micromirror devices is shown in Fig. 8.

2 Conclusion In the paper, we presented a reliability analysis of a thermally actuated MEMS micromirror device. Various factors like humidity, temperature, corrosion, electrical, and mechanical failures that were affecting the reliability of the device were discussed and analyzed. The lifetime of the MEMS micromirror was analyzed using a bathtub curve model. The different configuration reliability model was discussed. The reliability model of MEMS micromirror was presented, and p-out-of-n redundancy configuration model was considered for MEMS micromirror device due to more data redundancy.

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Fig. 8 Representation of combination reliability model of MEMS micromirror

References 1. Xie H, Pan Y, Fedder GK (2002) A SCS CMOS micromirror for optical coherence tomographic imaging. In: Micro electro mechanical systems, 2002. The fifteenth IEEE international conference on, IEEE, pp 495–498 2. Maharshi V, Mere V, Agarwal A (2018) Multi-layered thermal actuator realization using metal passivated TMAH micro-machining. IEEE Electron Dev Kolkata Conf (EDKCON) 2018:392– 395. https://doi.org/10.1109/EDKCON.2018.8770408 3. Maharshi V, Mere V, Agarwal A (2018) Design and fabrication of electro-thermal 1-D micromirror. IEEE Electron Dev Kolkata Conf (EDKCON) 2018:419–422. https://doi.org/10.1109/ EDKCON.2018.8770509 4. Jia K, Pal S, Xie H (2009) An electrothermal tip–tilt–piston micromirror based on folded dual S-shaped bimorphs. J Microelectromech Syst 18(5) 5. Maharshi V, Mere V, Agarwal A (2021) Modeling of electrothermal microactuator. In: Mukherjee S, Datta A, Manna S, Sahoo SK (eds) Computational mathematics, nanoelectronics, and astrophysics. CMNA 2018. Springer proceedings in mathematics & statistics, vol 342. Springer. https://doi.org/10.1007/978-981-15-9708-4_9 6. Maharshi V, Mere V, Agarwal A (2019) Multi-layered [Au/Si3N4/SiO2] thermal actuator realization using metal passivated TMAH micro-machining. Eng Res Express 1(1):015006 7. Todd ST Electrothermomechanical modelling of a 1-D electro thermal MEMS Micromirror 8. Mere V, Aditia VM, Agarwal A (2014) Thermally actuated MEMS micromirror: design aspects. Asian J Phys 23(4):00–001 9. Van Spengen WM (2003) MEMS reliability from a failure mechanisms perspective. Microelectron Reliab 43(7):1049–1060 10. Fonseca DJ, Sequera M (2011) On MEMS reliability and failure mechanisms. J Qual Reliab Eng 11. Lall P, Abrol A, Locker D (2017) Effects of sustained exposure to temperature and humidity on the reliability and performance of MEMS microphone. In: International electronic packaging technical conference and exhibition, vol 58097, pp V001T01A022. American Society of Mechanical Engineers

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12. Peng T, You Z (2021) Reliability of MEMS in shock environments: 2000–2020. Micromachines 12(11):1275 13. Srikar VT, Senturia SD (2002) The reliability of microelectromechanical systems (MEMS) in shock environments. J Microelectromech Syst 11(3):206–214 14. Spengen WMV, Puers R, Wolf ID (2003) On the physics of stiction and its impact on the reliability of microstructures. J Adhes Sci Technol 17(4):563–582 15. Neubeck K (2004) Practical reliability analysis, Pearson Prentice Hall, New Jersey 16. Smith RW, Dietrich DL (1994) The bathtub curve: an alternative explanation. In: Proceedings of annual reliability and maintainability symposium (RAMS). IEEE, pp 241–247

RF-MEMS Technology and Beamforming in 5G: Challenges and Opportunities for a Pair with a Still Untapped Potential Girolamo Tagliapietra and Jacopo Iannacci

Abstract The challenging characteristics addressed by the 5G standard rely on widespread coverage and services enabled by adaptive beamforming operated by cells and base stations. To this end, basic radio frequency (RF) components and systems are subjected to a constant push toward miniaturization, reconfigurability, frequency agility, and low-power consumption. In case of high-performance RF passives, these needs can be satisfied by RF-MEMS technology (i.e. RF-microelectro-mechanical-systems), and this will be the starting point of this paper. In this paper, an overview concerning the state of the art of RF-MEMS components and compounds involved in beamforming networks is provided, with a special attention toward hybrid architectures as key feature of realistic massive-multiple-inputmultiple-output (mMIMO) systems. In light of the current frontiers for RF-MEMS in the framework of hybrid architectures, switches, phase shifters, and an attenuator realized at Fondazione Bruno Kessler (FBK) are presented as suitable building blocks for future compact modules and beamforming architectures, in which RF-MEMS could play an effective and predominant role. Keywords RF-MEMS · 5G · mMIMO · mm-Wave · Beamforming · Phased arrays · Switches · Phase shifters · Attenuators · T/R modules · Transceivers

1 Introduction The evolving 5G scenario appears to be the first historical field of convergence between different communication systems and needs. Besides the more “classic” mobile telephony, the 5G network is expected to support multiple paradigms. Starting from extensive machine-to-machine (M2M) communications concerning house and G. Tagliapietra (B) · J. Iannacci Center for Sensors and Devices (SD), Fondazione Bruno Kessler (FBK), 38123 Trento, Italy e-mail: [email protected] J. Iannacci e-mail: [email protected] © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023 T. R. Lenka et al. (eds.), Micro and Nanoelectronics Devices, Circuits and Systems, Lecture Notes in Electrical Engineering 904, https://doi.org/10.1007/978-981-19-2308-1_44

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personal appliances, up to huge multimedia data flows for extended reality (XR), the concept of Internet of Things (IoT) is gradually shifting to the Internet of Everything (IoE). The final goal is to implement “smart” cities, factories, farming, and vehicles [1], in a fully interconnected and unifying framework, so that it is more reasonable to refer to it as the “5G Ecosystem”. An ecosystem able to support such complexity and variety of standards and devices must necessarily operate along a wide portion of the spectrum. In fact, according to the latest release of 5G standard by the 3rd Generation Partnership Project (3GPP) consortium, the Release 17, the interval of employed frequencies will be divided into two ranges: the Frequency Range 1 (FR1) in the 425–7125 MHz range, and the Frequency Range 2 (FR2) in the 24.25–52.6 GHz range [2]. The coverage of the different areas is provided by different kinds of cells, ranging from the more powerful base stations (i.e. metro cells) up to the more restrained femtocells, depending on the deployment environment and the expected number of users. In addition, while the FR1 is adopted by cells with a higher number of users, the cells devoted to interior deployment (e.g., homes and businesses) employ belonging to FR2. Differently from previous standards, such as 4G LTE, a native and key feature of 5G is the use of beamforming (BF). By means of BF, the radiation pattern of an antenna generally composed by multiple radiating elements is modified. The goal is to maximize the radiated power along a desired direction, and/or to suppress an interfering undesired signal coming from a known direction. Among the different advantages, in the framework of 5G the use of BF at cell and user equipment (UE) side is beneficial to energy efficiency and, above all, to spectral efficiency. In fact, focusing the radiated power toward the desired receiver’s location maximizes the signal-to-noise ratio (and thus the throughput), enabling the extraordinary data rates considered in the 5G standard (20 Gb/s peak download speed, 10 Gb/s peak upload). Such performances can be obtained by means of massive multiple-input-multipleoutput (mMIMO) antenna configurations at cell level, with antennas consisting of tens or hundreds of radiating elements simultaneously serving multiple users by focused radiation beams. The basic operation performed in BF consists in assigning a different attenuation level and phase shift to each signal transmitted or received by each radiating element of the array. The choice of a proper beamforming architecture is then crucial since it determines the achievable performances of the whole radiating antenna system, and its feasibility in the framework of mMIMO. Basically, adaptive BF can be implemented by analog, digital, or hybrid architectures, whose main features are visible in Fig. 1. The more “traditional” and simpler analog implementation is characterized by a single common RF chain and a phase shifter for each radiating element. On one hand, this arrangement guarantees low power consumption, a simplified hardware (reduced space occupancy) and a cost-effective solution. On the other hand, its limited flexibility in terms of generated beams, frequency agility, data rates, and the impossibility to support multiple simultaneous data streams, makes analog BF useless in mMIMO [3]. Digital BF guarantees the best achievable performances, by controlling both the amplitude and the phase of signals and by supporting multiple data streams to multiple users simultaneously. Its digital nature permits extensive use of

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Fig. 1 Block schemes of typical analog (a), digital (b), and hybrid (c) beamforming architectures

digital signal processing (DSP) techniques for calibration, direction of arrival (DOA) estimation, and suppression of interfering signals. Since the actual BF is performed in baseband, each radiating element must be provided with a dedicated RF chain (mixers, filters, and digital-to-analog-converters), which dramatically increases the space occupancy and complexity of the required hardware. The related and excessive power consumption and cost make the use of digital BF impractical in mMIMO [4]. Hybrid BF represents a viable trade-off, combining the reduced hardware complexity of the analog BF with the flexibility of digital one. In the hybrid approach, while the digital BF is performed at baseband for the different data streams, each RF chain serves a sub-array of radiating elements by means of an analog BF network. In the framework of large-scale mMIMO antenna systems this approach ranked as the reference one, providing near-optimal performance while maintaining a low-power consumption and a contained cost [5]. The internal architecture of the analog part of a hybrid BF network can be organized according to different topologies, depending on the desired trade-off between performances and complexity, and physical footprint and costs. As an example, in a fully-connected topology, every antenna is connected to every RF chain, while in a partially-connected topology, RF chains are connected to a subset of antennas, as in Fig. 2.

Fig. 2 a Detailed block schemes of common superheterodyne-based RF chains, comprising the transmit and the receive path, with multiple bandpass filters (BPF), amplifiers (AMP), mixers (MIX), and a local oscillator (LO). b Part of the analog BF network of the hybrid beamforming architecture reported in Fig. 1, comprising a SPMT switch and a variable attenuator, a variable phase shifter, multiple SPDT switches and amplifiers for every antenna element

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Due to the deployment scenario, the expected number of users, and the involved range of frequencies, mMIMO systems working at frequencies in the FR1 are mainly used for channel hardening [6] (i.e. to decrease the channel variability by averaging phenomena of small-scale fading [7]). The true potential of BF in mMIMO systems is unleashed in case of cells working in the FR2, where small wavelengths determine small radiating elements and the chance to house a significant number of elements (from 64 × 64 up to 256 × 256) in contained array dimensions. From a hardware-based point of view, besides the incessant pursue of improved performances regarding the specific devices, the trend of an increasing number of radiating elements in increasingly larger arrangements poses constant challenges in terms of miniaturization and power consumption. In fact, small radiating elements separated by half-wavelength spacing require a suitable miniaturization of both components and transmit/receive modules (TRM or transceivers) of RF front-ends. On the other side, given the multitude of devices serving each radiating element, the need of an overall contained power consumption becomes stringent. These issues can be successfully addressed by means of micro electro-mechanical systems for radio frequencies (RF-MEMS). RF-MEMS represent a type of lumped passive components whose basic working principle consists in the mechanical movement and deformation of a conductive membrane (typically metallic). Characterized by sub-millimeter arrangements, the movement of the membranes is operated by electro-based principles, such as electrostatic, piezoelectric, electrothermal, or electromagnetic actuation, with the electrostatic one being the most common [8]. Since their first appearances in the literature during the ‘90s, MEMS-based implementations of switching devices have proved to be a viable solution to achieve low losses, high isolation, commendable linearity, and high reconfigurability along wide frequency ranges. In addition, the use of electrostatic actuation mechanism guarantees an almost null power consumption. Over the years, an increasing amount of literature has provided valuable works regarding both traditional lumped components and more complex systems. Starting from variable capacitors (varactors) and inductors, Single-Pole-Multi-Throw (SPMT) switches and switching matrixes, RF-MEMS encompassed the RF chain by reconfigurable resonators, filters, phase shifters, and attenuators. Moreover, the radiating elements have been concerned as well, with reconfigurable antennas and matching networks, so that nowadays RF-MEMS may effectively replace “standard” semiconductor-based components in RF circuits. The maturity of such technology is proved by its surging presence in commercial devices (e.g. mobile phones [9]) and by its expected market growth [10]. The goal of this research work consists in giving an overview regarding the needs related to adaptive beamforming in mMIMO systems as 5G cells, and what the research on RF-MEMS has provided up to the present moment to beamforming networks. To this purpose, the current frontiers of RF-MEMS technology in such application will be highlighted, and a special attention will be paid to the fabrication technology at Fondazione Bruno Kessler (FBK) and recent devices based on such technology as useful tools to overcome the current limitations.

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This paper is organized as follows: while the state of the art of RF-MEMS components like switches, phase shifters, and attenuators will be considered in Sect. 2, the open challenge concerning adaptive beamforming and RF-MEMS will be discussed in Sect. 3. In Sect. 4, the FBK fabrication technology is presented, together with some devices, while final considerations are reported in conclusions.

2 State of the Art Except for a single forward-looking and unifying example, the literature regarding RF-MEMS generally stops at the development of single devices or simple compounds. Up to the present moment, the most futuristic and articulate vision concerning RF-MEMS in radio front-ends has been proposed by Nguyen since the beginning of 2000s. In many works, such as [11], Nguyen points out that highperformance RF-MEMS devices could lead to a replacement of their semiconductorbased counterparts, but they may also trigger a radical rethinking of the existing receivers and transmitters based on super-heterodyne scheme, leading to nearly allMEMS front-ends. Despite the validity of his vision and the effort he spent over the years in that direction, BF networks and architectures still were not a matter of concern at the time (to cellular communications), therefore, his investigation suffers from this obvious lack. Within the framework of adaptive BF, the set of RF-MEMS passive components playing the major role consists of switches, phase shifters, and attenuators. As visible in Fig. 2b, while switches (generally SPDT) are meant to switch between the transmit or receive amplification path (power amplifier (PA) or low-noise amplifier (LNA)), phase shifters, and attenuators will provide the complex weighting (in amplitude and phase) to each transmitted or received signal [12, 13]. Since up to the present moment, MEMS-based proposals for BF involve simple arrangements or compounds, the following state of the art will consider only the single passive components belonging to the analog part of a hybrid BF network. The achievements and the features of the discussed devices that researchers are currently trying to improve are enumerated in the recapitulatory Table 1 at the end of the present section.

2.1 Switches Switches represent the most investigated device in the field of RF-MEMS, them being the first developed components and the enabling tool for the reconfigurability of more complex devices (phase shifters, attenuators, etc.) or systems. For sake of classification, the structure of the membrane defines a “cantilever” or a “clamped– clamped” switch. When actuated at a specific voltage (called pull-in voltage), the movable membrane may put in touch the input signal line with ground or another output line, determining a “shunt” or “series” configuration. On the basis of the

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Table 1 Achievements and current challenges faced by researchers in the development of future switches, phase shifters, and attenuators-based on RF-MEMS Type of device

Commonly achievable features

Features to be improved

Switches (and movable membranes employed in the subsequent devices, more generally)

Wideband remarkable electrical performance, high linearity, good power handling, low losses, and power consumption

Limited reliability, high control voltage, packaging impairments, compatibility and integration with CMOS, and switching time

Phase shifters

High reconfigurability

Limited maximum shift range, non-negligible root-mean-square (RMS) shift error

Attenuators

High reconfigurability

Coarse distribution of attenuation steps, RMS attenuation error

type of established contact between the membrane and the target surface, the switch can be of “ohmic” or “capacitive” type. In ohmic switches, the metallic membrane directly touches the targeted surface, while a dielectric layer covers the target area in case of capacitive ones. In case of switches, important figures of merit are the return loss (RL), insertion loss (IL), and isolation (ISO), generally expressed in decibels [14]. While RL represents the amount of power that is reflected at the input port, IL represents the power flowing towards an “open” output port. ISO indicates the leaked power by a “closed” output port. Beside the improvement of the electrical performances of the devices, over the past few years researchers addressed different issues concerning switches, such as reliability (lifetime of the device in actuation cycles) [15], CMOS compatibility (in fabrication process and operational voltages) [16] and miniaturization [14, 17]. Although there are multiple strategies that can be employed to solve the different issues, a trade-off is necessary, since a single solution simultaneously addressing all the issues does not exist. As an example, [18] proposes a cantilever series ohmic switch provided with two additional lateral cantilevers to be actuated when the switch is OFF (series membrane not actuated, output port is closed) for a better power handling and ISO. Besides the remarkable electrical performance of the device in terms of ISO (up to −72.3 dB) and IL (