Long-Term Reliability of Nanometer VLSI Systems: Modeling, Analysis and Optimization [1st ed. 2019] 978-3-030-26171-9, 978-3-030-26172-6

Table of contents :
Front Matter ....Pages i-xli
Front Matter ....Pages 1-1
Introduction (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 3-12
Physics-Based EM Modeling (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 13-45
Fast EM Stress Evolution Analysis Using Krylov Subspace Method (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 47-66
Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 67-96
Dynamic EM Models for Transient Stress Evolution and Recovery (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 97-120
Compact EM Models for Multi-Segment Interconnect Wires (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 121-151
EM Assessment for Power Grid Networks (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 153-175
Resource-Based EM Modeling DRM for Multi-Core Microprocessors (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 177-194
DRM and Optimization for Real-Time Embedded Systems (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 195-215
Learning-Based DRM and Energy Optimization for Manycore Dark Silicon Processors (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 217-245
Recovery-Aware DRM for Near-Threshold Dark Silicon Processors (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 247-262
Cross-Layer DRM and Optimization for Datacenter Systems (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 263-275
Front Matter ....Pages 277-277
Introduction (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 279-304
Aging-Aware Timing Analysis (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 305-321
Aging-Aware Standard Cell Library Optimization Methods (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 323-342
Aging Effects in Sequential Elements (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 343-356
Aging Guardband Reduction Through Selective Flip-Flop Optimization (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 357-372
Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 373-399
Aging Relaxation at Microarchitecture Level Using Special NOPs (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 401-414
ExtraTime: Modeling and Analysis of Transistor Aging at Microarchitecture-Level (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 415-438
Reducing Processor Wearout by Exploiting the Timing Slack of Instructions (Sheldon Tan, Mehdi Tahoori, Taeyoung Kim, Shengcheng Wang, Zeyu Sun, Saman Kiamehr)....Pages 439-455
Back Matter ....Pages 457-460

Citation preview

Sheldon Tan · Mehdi Tahoori  Taeyoung Kim · Shengcheng Wang  Zeyu Sun · Saman Kiamehr

Long-Term Reliability of Nanometer VLSI Systems Modeling, Analysis and Optimization

Long-Term Reliability of Nanometer VLSI Systems

Sheldon Tan • Mehdi Tahoori • Taeyoung Kim Shengcheng Wang • Zeyu Sun • Saman Kiamehr

Long-Term Reliability of Nanometer VLSI Systems Modeling, Analysis and Optimization

123

Sheldon Tan Department of Computer Science and Engineering University of California Riverside, CA, USA Taeyoung Kim Department of Electrical & Computer Engineering University of California Riverside, CA, USA

Mehdi Tahoori Karlsruhe Institute of Technology Karlsruhe, Germany Shengcheng Wang Karlsruhe Institute of Technology Karlsruhe, Germany Saman Kiamehr Robert Bosch Starter Generator GmbH Stuttgart, Germany

Zeyu Sun Department of Electrical & Computer Engineering University of California Riverside, CA, USA

ISBN 978-3-030-26171-9 ISBN 978-3-030-26172-6 (eBook) https://doi.org/10.1007/978-3-030-26172-6 © Springer Nature Switzerland AG 2019 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, express or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG. The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

To our families

Foreword

The analysis and optimization of circuit reliability has become one of the most critical challenges for high-performance digital circuits. While the underlying phenomena—bias temperature instability (BTI), hot-carrier injection (HCI), timedependent dielectric breakdown (TDDB), and electromigration (EM)—have been known for many years, our understanding of the underlying physics has greatly improved over the past decade or so. Initially, such investigations were largely confined to device reliability researchers, but as these phenomena have begun to rear their heads in commercial designs and conventional models have fallen short, the scope of this research has expanded. There has been a greater focus in the design community on determining the impact of device-level reliability on system performance, built upon physics-based models. This book provides an excellent overview of some recent research in the area of interconnect and device reliability. The authors are widely recognized as leading researchers in this area, with scores of high-quality publications in this area. The first part of the book focuses on EM. This is a phenomenon that leads to circuit failures as voids are formed in interconnects. For many decades, EM modeling was based on empirical modeling techniques, and there is a growing realization that such models are limited today for interconnect systems with numerous branches, fabrication technologies based on copper that use barrier/capping layers that block the migration of metal atoms, and an environment where on-chip temperatures are an increasingly serious factor in accelerating EM. This book provides a detailed view into physics-based EM modeling, starting from Korhonen’s equation that models the kinetics associated with stress evolution with an interconnect due to the electron wind force and the opposing back-stress. This is followed by an exposition of more recent numerical methods applied to two-pin nets and multisegment interconnect trees. Fast solution methods under both static and dynamic stresses, as well as methods for determining wire immortality, are presented, and the impact at the full-chip level is analyzed. The second part focuses on device-level reliability degradation due to BTI, HCI, and TDDB and begins with first-principles approach to explaining modeling methods at the transistor level. Bridges are then built from the language of vii

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transistor-level modeling to that of digital circuit design, determining the impact of degradation on aging on circuit timing, from library characterization to circuit analysis. Finally, methods for assuring performance through circuit optimization and guard-banding are presented, focusing on both combinational and sequential elements at the circuit level and considerations at the microarchitecture/system level. In summary, I commend this book as an excellent source for anyone interested in learning about aging effects in CMOS circuits. The topics addressed herein range from modeling techniques for elemental transistors and wires to circuit analysis and optimization and proceed all the way up to architectural considerations. Department of ECE University of Minnesota Minneapolis, MN, USA

Sachin Sapatnekar

Preface

Reliability has become a more serious design challenge for current nanometer very large-scale integrated (VLSI) circuits especially as the technology has advanced into 7 nm. It was expected that the future chips would show sign of reliabilityinduced age much faster than the previous generations. Among many reliability effects, electromigration (EM) and bias temperature instability (BTI) reliability effects have become major design constraints. EM is a physical phenomenon of the oriented migration of metal (Cu) atoms due to the momentum exchange between atoms and the conducting electrons. It can cause wire resistance change and thus functional failure of the system. With aggressive technology scaling, EM sign-off is becoming more difficult than before using traditional EM analysis approaches. BTI is a long-term transistor degradation mechanism, which gradually degrades the voltage threshold of a transistor and by consequent the switching delay of the gate and further to that the circuit path delay. Therefore, the modeling and estimation of its effects on circuit performance degradation have become imperative. Moreover, the mitigation techniques for BTI are also becoming vital in order to ensure that circuits are robust over their lifetime. Part I focuses on the recent development of new physics-based EM models, chip-scale assessment techniques, and system-level EM-induced dynamic reliability management for many important computing systems. First, we go through the basic EM physics and the partial differential equation (Korhonen’s equation) for describing stress evolution in a confined wire. Then, we introduce recently proposed physics-based three-phase EM model, which consists of void nucleation, void incubation, and growth phases. The new model is more consistent with measured wire resistance changes over time for copper damascene wires than the two-phase EM model. We further present a fast EM numerical analysis method, FastEM, based on the finite difference time domain (FDTD) and the Krylov subspace method. Furthermore, we also introduce a fast EM immortality check for a general multisegment interconnects, which is the natural extension of Blech’s limit for a single segment. Multi-segment interconnect-based analysis method is then discussed to account for the interdependency between the branches in a tree wire. We also present a new physics-based dynamic compact EM model, which, for the first time, ix

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can predict the transient EM recovery effect in a confined metal wire. The new EM recovery-aware model can be further exploited to significantly extend the chip lifetime. We further present a novel IR-drop-based full-chip EM assessment method to analyze the EM-induced degradation in the power grid networks. This method is further integrated with full-chip thermal and residual stress analysis techniques so that the impact of cross-layout temperature and residual stress distributions can be taken into account. For the system-level EM-induced dynamic reliability management, we do the following. First, we develop system-level management for real-time embedded systems. We investigate a new lifetime optimization technique for real-time embedded processors considering the electromigration-induced reliability. The new approach is based on a recently proposed physics-based electromigration (EM) model for more accurate EM assessment of a power grid network at the chip level. Second, we develop a new energy and lifetime optimization techniques for emerging dark silicon manycore microprocessors considering both hard long-term reliability effects (hard errors) and transient soft errors. To optimize EM-induced lifetime, we apply the adaptive Q-learning-based method, which is suitable for dynamic runtime operation as it can provide cost-effective yet good solutions. Third, we develop a new dynamic reliability management (DRM) techniques at the system level for emerging lowpower dark silicon manycore microprocessors operating in near-threshold region. We mainly consider the electromigration (EM) recovery effects. To leverage the EM recovery effects, which was ignored in the past, at the system level, we present a new equivalent DC current model to consider recovery effects for general time-varying current waveforms so that existing compact EM model can be applied. Fourth, we develop a new approach for cross-layer electromigration (EM)-induced reliability modeling and optimization at physics, system, and data center levels. To speed up the online optimization for energy in a data center, we investigate a new combined data center power and reliability compact model using a learning-based approach in which a feed-forward neural network (FNN) is trained to predict energy and longterm reliability for each processor under data center scheduling and workloads. Part II focuses on various modeling and mitigation techniques for transistors aging at different levels of abstraction. First of all, we propose a framework to comprehensively investigate the stochastic behavior of negative bias temperature instability (NBTI), which is a key aging effect in transistors. By abstracting atomistic NBTI models to the circuit timing analysis flow, the combined effect of stochastic NBTI and process variation can be studied on the performance of the VLSI design at circuit level. Second, we introduce a technique to optimize the standard cells considering BTI effect in order to balance their rise and fall delays at the expected lifetime rather than the design time. Afterwards, we focus on the aging reliability of flip-flop (FF), which is an important element in a circuit. Specifically, we first present a comparative analysis of the impact of process and runtime variations on the performance of flip-flops. Process and runtime variations affect the functionality of nanoscale VLSI designs which leads to reduced manufacturing yield and increased runtime failures. Second, a method to mitigate the BTI-induced aging of flip-flops via transistor sizing optimization is introduced. The optimized

Preface

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flip-flops are more resilient against BTI stress compared to the original ones. Third, we take the running workload into account and present a runtime monitoring method to raise a flag when a timing-critical flip-flop experiences severe static BTI stress. In the following chapters, we consider the modeling and mitigation techniques for transistors aging at higher abstraction levels. First, a novel No Operation instruction assignment to minimize NBTI effect is present in order to maximize NBTI relaxation on the processors. Afterwards, hot-carrier injection (HCI), which is another critical aging effect, is taken into account with NBTI during the modeling and mitigation for transistor aging reliability. First, a novel microarchitectural aging analysis framework is presented, which can be used in early design phases when detailed transistor-level information is not yet available to model, analyze, and predict performance, power, and aging. Second, based on this framework, an aging mitigation technique at the micro-architecture level is introduced, in which the load and stress on various functional units are distributed based on their timing slack and aging criticality. Last but not least, our treatment on the selected topics does not mean to be comprehensive. The important research work not covered in this book will not diminish the contributions from the corresponding authors. The contents of the book come mainly from the recent publications of the authors. Many of those original publications can be found at www.ece.ucr.edu/~ stan/publication_list.pdf. Future errata and update about this book can be found at www.ece.ucr.edu/~stan/project/books/book18reliability.htm. Riverside, CA, USA Karlsruhe, Germany Riverside, CA, USA Karlsruhe, Germany Riverside, CA, USA Stuttgart, Germany

Sheldon Tan Mehdi Tahoori Taeyoung Kim Shengcheng Wang Zeyu Sun Saman Kiamehr

Acknowledgments

The authors would like to thank many graduate students from UC Riverside and Karlsruhe Institute of Technology for their great research contributions, which make this book possible. Sheldon Tan would like to thank both the National Science Foundation and the University of California, Riverside, for their financial supports for this book. He highly appreciates the consistent supports of Dr. Sankar Basu of the National Science Foundation over the past 10 years. Without those supports, many of the presented works would not be possible. Specifically, he would like to acknowledge the following grants: NSF grant under No. CCF-1255899, CCF-1527324, and recent CCF-1816361 grants. He also is indebted to Dr. Kerry Berstein of Microsystems Technology Office (MTO), Defense Advanced Research Projects Agency (DARPA), who managed the DARPA IRIS (Integrity and Reliability of Integrated Circuits) Phase III program, which provides financial supports for some of the works in this book through the grant HR0011-16-2-0009. He is grateful to the following people for their significant contributions to this book: Dr. Xin Huang for some of the earlier physics-based EM models in this book; Dr. Haibao Chen for his contributions in the EM models for multi-segment interconnect wires; Mr. Chase Cook, who is a Ph.D. student at VSCLAB, for his contributions to the fast Krylov subspace-based finite difference-based EM analysis tool, FastEM; and Mr. Liang Chen for verifying some of the analytical solutions to the Korhonen’s equation. Mehdi Tahoori is grateful for the support of the German Research Foundation (Deutsche Forschungsgemeinschaft—DFG) as well as the Karlsruhe Institute of Technology for the financial support for this book. In particular, Mehdi Tahoori would like to acknowledge the priority Program SPP1500 of DFG on “Dependable Embedded Systems.” He would also like to thank Semiconductor Research Corporation (SRC) and in particular Dr. William Joyner and Dr. David Yeh for their financial and technical support. In particular, he would like to acknowledge SRC tasks 2448, 2502, and 2503. He would also like to thank Dr. Sani Nassif of Radyalis and Prof. Krishnendu Chakrabarty of Duke University for their contributions and collaboration on the research work on transistor aging modeling and mitigation. He is also grateful to the following people for their significant contributions to xiii

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this book: Dr. Fabian Oboril for the architecture-level transistor aging modeling and mitigation work, Dr. Farshad Firouzi for his work on aging modeling and mitigation at RTL, Dr. Mojtaba Ebrahimi and Mr. Mohammad Saber Golanbari for their contributions to aging-aware design for sequential elements and processor microarchitecture, and Mr. Arun Vijayan for learning-based static aging mitigation. Taeyoung Kim would like to thank his former advisor, Dr. Sheldon Tan. Without his support and strong leadership, he undoubtedly could not have done this book. He is grateful to the following people for their system-level reliability contributions to this book: Dr. Haibao Chen for his contributions in the embedded system optimization formulation, Mr. Hengyang Zhao for his strong efforts in neural network modeling and training, and Dr. Daniel Wong for his great advice and collaboration in data center system modeling. Shengcheng Wang would like to thank his former advisor, Dr. Mehdi Tahoori, for his support and leadership. He is grateful to the following people for their contributions to this book: Dr. Fabian Oboril for his contributions in the transistor aging modeling and mitigation at the architecture level, Dr. Farshad Firouzi for his work on transistor aging modeling and mitigation at the RTL level, Dr. Mojtaba Ebrahimi and Mr. Mohammad Saber Golanbari for their efforts in aging-aware design for sequential elements and processor microarchitecture, and Mr. Arun Vijayan for his work on learning-based static aging mitigation. Last but not the least, Sheldon Tan would like to thank his wife, Yan Ye, and his three daughters for the understanding and supports during many hours it took to write this book. Mehdi Tahoori would like to thank his wife, Mana, and his two sons, Kian and Artin, for the patience and support while he was writing part of this monograph. Taeyoung Kim would like to express his gratitude to his family, Yunji, and his two sons for the love, support, and constant encouragement for the work of this book. Zeyu would like to thank his parents for their supports. Shengcheng would like to thanks his family for their understanding and supports. Saman would like to thank his family for their support during the time he was writing the book.

Contents

Part I New Physics-Based EM Analysis and System-Level Dynamic Reliability Management 1

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Why Electromigration Reliability? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Why System-Level EM-Reliability Management? . . . . . . . . . . . . . . . . . 1.3 Chapter Outlook in Part I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 3 6 7 11

2

Physics-Based EM Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Electromigration Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Stress-Based EM Modeling and Stress Diffusion Equations . . . . . . . 2.3.1 EM-Induced Material Transport Equation. . . . . . . . . . . . . . . . . 2.3.2 One-Dimensional Stress Evolution Model . . . . . . . . . . . . . . . . 2.4 Modeling for Transient EM Effects and Initial Stress Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Post-voiding Stress and Void Volume Evolution. . . . . . . . . . . . . . . . . . . . 2.6 Compact Physics-Based EM Model for a Single Wire . . . . . . . . . . . . . 2.6.1 Physics-Based Two-Phase EM Model . . . . . . . . . . . . . . . . . . . . . 2.6.2 Physics-Based Three-Phase EM Models . . . . . . . . . . . . . . . . . . 2.7 The Physics-Based Three-Phase Compact EM Model for Multi-Segment Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.8 The New Void Saturation Volume Estimation for General Multi-Segment Wire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.9 Some Other Relevant EM Models and Analysis Methods . . . . . . . . . 2.10 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13 13 13 17 17 18 21 24 25 25 27 33 34 40 42 42

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Contents

Fast EM Stress Evolution Analysis Using Krylov Subspace Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 The Linear Time-Invariant Ordinary Differential Equations for EM Stress Evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.1 Steady-State Analysis for Nucleation Phase . . . . . . . . . . . . . . 3.3 The Presented Krylov Fast EM Stress Analysis . . . . . . . . . . . . . . . . . . . . 3.3.1 Singularity Mitigation for EM ODE Matrices . . . . . . . . . . . . 3.3.2 Fast Krylov Subspace-Based Stress Analysis . . . . . . . . . . . . . 3.3.3 EM Simulation Under Time-Varying Temperature . . . . . . . 3.3.4 Scaling Schemes for Numerical Stability . . . . . . . . . . . . . . . . . 3.4 Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Accuracy Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.2 Eigenvalue Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Voltage-Based EM Stress Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.1 Steady-State EM-Induced Stress Modeling . . . . . . . . . . . . . . . 4.2.2 New Voltage-Based Analysis for Steady-State EM Stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.3 Relationship to the Blech Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.4 Steady-State Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.5 Study of Some Special Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2.6 Current Crowding Impact Analysis . . . . . . . . . . . . . . . . . . . . . . . . 4.2.7 Application to Mesh-Structured Interconnect Wires . . . . . . 4.2.8 Application to IBM Power Grids . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Numerical Validation Results and Discussions . . . . . . . . . . . . . . . . . . . . . 4.3.1 Results for Straight-Line Three-Terminal Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.2 Results for T-Shaped Four-Terminal Interconnect . . . . . . . . 4.3.3 Results for Comb-Structured Interconnects . . . . . . . . . . . . . . . 4.3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dynamic EM Models for Transient Stress Evolution and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Background and Review of Existing Works . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Existing Modeling Based on Effective Direct Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.2 EM Physics and Governing Equations . . . . . . . . . . . . . . . . . . . .

47 47 48 51 52 52 54 57 58 59 59 61 63 65 65 67 67 70 70 71 74 76 80 84 87 89 90 91 92 92 94 95 97 97 98 98 99

Contents

New Model for the EM-Induced Stress Evolution Caused by Time-Dependent Current Density and Temperature . . . . . . . . . . . . 5.3.1 Generalized Model with the Arbitrary Piecewise Constant Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.2 EM Modeling for Periodic Pulse Current . . . . . . . . . . . . . . . . . 5.4 Study of the EM Stress Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 EM Stress Recovery Effect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.2 Limitation of Using Effective DC Methods . . . . . . . . . . . . . . . 5.4.3 Resistance Degradation Caused by the Symmetrical Bidirectional Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Application for System Level Reliability Aware Computing . . . . . . 5.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xvii

5.3

6

7

Compact EM Models for Multi-Segment Interconnect Wires . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2.1 Analytical Model for Stress Evolution Process . . . . . . . . . . . 6.2.2 Considering Varying Current Density . . . . . . . . . . . . . . . . . . . . . 6.2.3 Considering Varying Segment Length . . . . . . . . . . . . . . . . . . . . . 6.3 Dynamic EM Modeling for Three-Terminal Interconnect Tree . . . . 6.3.1 Temperature Impacts on EM Effects . . . . . . . . . . . . . . . . . . . . . . 6.3.2 Dynamic EM Model Considering Varying Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.1 Different Current Density and Segment Length Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.2 Dynamic EM Stress Under Time-Varying Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4.3 Computational Accuracy and Convergence Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Dynamic EM Models for More General Interconnect Wires. . . . . . . 6.6 EM Modeling by Integral Transformation Method for Straight Multi-Segment Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.7 EM Modeling by Integral Transformation Method for More General Multi-Segment Wires . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.8 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EM Assessment for Power Grid Networks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 New Power Grid Reliability Analysis Method . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Power Grid Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Effective-EM Current Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 New Analysis Method Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

100 101 106 108 109 110 112 116 117 119 121 121 122 122 128 130 132 132 134 136 136 139 141 142 146 147 150 150 153 153 154 154 155 156

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7.3 7.4

Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross-Layout Temperature and Thermal Stress Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.1 Full-Chip Power Characterization . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Thermal Simulation Methodology . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.3 Thermal Stress Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Impact of Across-Layout Temperature and Thermal Stress on EM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.1 Full-Chip EM Analysis Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Experimental Results and Discussion . . . . . . . . . . . . . . . . . . . . . 7.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

9

Resource-Based EM Modeling DRM for Multi-Core Microprocessors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Problem Formulation and Reliability Modeling . . . . . . . . . . . . . . . . . . . . 8.3 System-Level EM Modeling and EM-Reliability Management Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.1 System Level EM-Reliability Resource Consumption Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.2 EM-Reliability Resource-Based Task Migration. . . . . . . . . . 8.3.3 EM-Reliability Resource-Based Low Performance State Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.4 The Spatial Temperature Variation Impacts on the Proposed Method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.3.5 Practical Application of the Proposed Resource-Based EM Models and Reliability Management Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.1 A Walk-Through Example for the Proposed Reliability Estimation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4.2 Evaluation of the Proposed Methods . . . . . . . . . . . . . . . . . . . . . . 8.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DRM and Optimization for Real-Time Embedded Systems . . . . . . . . . . . 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 System-Level EM-Induced Reliability Model . . . . . . . . . . . . . . . . . . . . . . 9.3 Real-Time Embedded System Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Proposed New Lifetime Optimization Method . . . . . . . . . . . . . . . . . . . . . 9.4.1 The New Lifetime Optimization Flow . . . . . . . . . . . . . . . . . . . . . 9.4.2 Formulation One: Continuous Constrained Nonlinear Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.3 Formulation Two: Mixed-Integer Linear Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

156 161 163 164 167 169 169 170 173 175 177 177 178 179 179 181 183 185

186 186 187 188 192 193 195 195 196 196 198 198 200 201

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9.5

205 206 206

Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.2 Evaluation of the Proposed Lifetime Optimization . . . . . . . 9.5.3 Core Utilization Effects and Trade-Off on Energy and Lifetime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5.4 Solution Quality Study and Analysis . . . . . . . . . . . . . . . . . . . . . . 9.5.5 Trade-Off Between Performance and Lifetime . . . . . . . . . . . 9.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Learning-Based DRM and Energy Optimization for Manycore Dark Silicon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Review of System-Level EM and Soft Error Reliability Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.1 System-Level EM Reliability Model . . . . . . . . . . . . . . . . . . . . . . 10.2.2 Soft Error Reliability Model Considering DVFS Impacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2.3 Impact of Process Technology on Soft Error Reliability Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3 New Dynamic Lifetime and Energy Optimization Methods for Dark Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.1 Q-Learning Based Formulation and Solution for Lifetime and Energy Optimizations . . . . . . . . . . . . . . . . . . . . . . . 10.3.2 MILP Based Formulation and Solution for Lifetime Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.3 Implementation of the Dark Silicon Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.4 Time Complexity Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.3.5 Practical Application of the Proposed DRM with Reliability Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4 Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.2 Evaluation of the Proposed Q-Learning Lifetime Optimization Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.3 Accuracy and Convergence Rate of the Proposed Q-Learning DRM Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.4 Hard and Soft Errors in Dark Silicon Manycore Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.4.5 Evaluation of the Proposed Q-Learning Based Energy Optimization Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

207 208 210 212 214 217 217 219 219 220 221 222 222 226 227 229 230 231 231 231 233 234 235 241 242

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11

12

Contents

Recovery-Aware DRM for Near-Threshold Dark Silicon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Recovery-Aware Electromigration Modeling at System Levels . . . 11.2.1 New Equivalent DC Current Based Modeling for EM Recovery Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2.2 EM Modeling for Varying Temperature Effects. . . . . . . . . . . 11.3 New Learning-Based Reliability Management for Near-Threshold Dark Silicon for EM Recovery Effects . . . . . . . . 11.3.1 Near-Threshold Dark Silicon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.2 Framework of Dark Silicon in Near-Threshold Computing Region. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3.3 SARSA-Based Learning Algorithm for DRM Considering Long-Term Recovery . . . . . . . . . . . . . . . . . . . . . . . . . 11.4 Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.1 Evaluation of the Lifetime Impacts Considering EM Recovery Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.2 Evaluation of the DRM for Near-Threshold Dark Silicon Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4.3 DRM Considering Recovery Effects . . . . . . . . . . . . . . . . . . . . . . 11.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cross-Layer DRM and Optimization for Datacenter Systems . . . . . . . . 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 EM-Induced Reliability Model for a Manycore Processor in Datacenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 EM-Induced Reliability-Aware Datacenter Model . . . . . . . . . . . . . . . . . 12.4 New Reliability-Constrained Energy Optimization for Datacenter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.1 Neural Networks for Datacenter Energy and Reliability Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4.2 Q-Learning Optimization for Datacenter . . . . . . . . . . . . . . . . . . 12.4.3 Proposed New Datacenter Framework for Energy and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 Numerical Results and Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.1 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 Evaluations of the Proposed New Modeling and Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

247 247 248 248 253 254 254 255 256 258 258 258 260 261 261 263 263 265 265 266 267 269 270 272 272 272 273 274

Contents

xxi

Part II Transistor Aging Effects and Reliability 13

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 Transistor Reliability in Advanced Technology Nodes . . . . . . . . . . . . . 13.2 Transistor Aging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 Bias Temperature Instability (BTI) . . . . . . . . . . . . . . . . . . . . . . . . 13.2.2 Hot Carrier Injection (HCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.3 Coupling Models for BTI and HCI Degradations . . . . . . . . . 13.2.4 Random Telegraph Noise (RTN). . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.5 Time Dependent Dielectric Breakdown (TDDB) . . . . . . . . . 13.3 Chapter Outlook in Part II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

279 279 281 281 291 292 293 296 298 300

14

Aging-Aware Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3 Circuit Level Simulation Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.1 Library Cell Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.3.2 Stochastic NBTI Parameter Extraction . . . . . . . . . . . . . . . . . . . . 14.3.3 Monte Carlo Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.1 Simulation Setup, Terms, and Definitions . . . . . . . . . . . . . . . . . 14.4.2 Atomistic NBTI Model vs Equivalent Normal NBTI Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.3 Effect of Process Variation vs Stochastic NBTI. . . . . . . . . . . 14.4.4 Effect of Balanced Paths in Complex Circuits . . . . . . . . . . . . 14.4.5 Effect of Workload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.4.6 Runtime of the Proposed Variation-Aware Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

305 305 306 307 308 308 308 309 309

15

Aging-Aware Standard Cell Library Optimization Methods . . . . . . . . . . 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.3 Aging-Aware Cell Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4 Cell Library Redesign and Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.1 Aging-Aware Cell Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.4.2 Technology Mapping Using Aging-Aware Standard Cell Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.1 Simulation Setup and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.2 Aging Mitigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.3 Library Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.5.4 Effect of Voltage and Temperature Variation . . . . . . . . . . . . . .

310 311 315 316 319 320 320 323 323 324 325 329 330 331 332 332 334 336 338

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Contents

15.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 16

Aging Effects in Sequential Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.1 Flip-Flop Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.2 Process Variation Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2.3 Voltage Droop Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 Robustness Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.1 Overall Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3.2 Results and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 Reliability-Aware Flip-Flop Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4.3 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

343 343 344 344 344 345 346 346 347 351 351 352 354 355 355

17

Aging Guardband Reduction Through Selective Flip-Flop Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.2 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3 Flip-Flops Under Static and Near-Static BTI Stress . . . . . . . . . . . . . . . . 17.3.1 Aging of Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.2 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.3.3 S-BTI Aware Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4 Proposed Optimization Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4.1 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.4.2 S-BTI Aware Optimization Flow . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5 Optimization Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.1 Detailed Optimization Results for C2MOS . . . . . . . . . . . . . . . 17.5.2 Optimization Results for Other FFs . . . . . . . . . . . . . . . . . . . . . . . 17.5.3 Delay-Leakage Trade-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.5.4 Circuit Level Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

357 357 358 359 359 361 362 363 363 365 366 366 368 369 369 371 371

Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical Flip-Flops. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Preliminaries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2.1 Static vs Dynamic Transistor Aging . . . . . . . . . . . . . . . . . . . . . . . 18.2.2 Related Prior Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Overview of Proposed Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

373 373 375 375 376 378

18

Contents

xxiii

18.4

Offline Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.4.1 Offline Characterization and Correlation Analysis. . . . . . . . 18.4.2 Offline Static Aging Mitigation Analysis. . . . . . . . . . . . . . . . . . 18.5 Online Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5.1 Online Monitoring of Static Aging . . . . . . . . . . . . . . . . . . . . . . . . 18.5.2 Online Mitigation of Static Aging . . . . . . . . . . . . . . . . . . . . . . . . . 18.6 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6.1 Representative Flip-Flop Selection . . . . . . . . . . . . . . . . . . . . . . . . 18.6.2 Mitigation Measures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6.3 Overheads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6.4 Lifetime Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.7 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

379 380 383 388 388 390 392 393 395 396 397 397 398

19

Aging Relaxation at Microarchitecture Level Using Special NOPs . . . 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.2 Preliminaries: The MIPS Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3 MAR NOP Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.1 NBTI Effect of Possible NOPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.3.2 Linear Programming Approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4 Applying MAR NOPs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.1 Software-Based Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.2 Hardware-Based Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 19.4.3 Comparing Hardware vs Software Implementations . . . . . 19.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

401 401 402 403 403 405 407 407 408 410 411 413 413

20

ExtraTime: Modeling and Analysis of Transistor Aging at Microarchitecture-Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3 ExtraTime Framework . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.1 Basic Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.2 Aging Models at Microarchitecture-Level . . . . . . . . . . . . . . . . 20.3.3 Accuracy Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.3.4 Advantages of ExtraTime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4 Aging Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.1 Clock Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.2 Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.4.3 Aging-Aware Scheduling Techniques . . . . . . . . . . . . . . . . . . . . . 20.5 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.1 Evaluation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.5.2 Effect of Clock/Power Gating Techniques . . . . . . . . . . . . . . . . 20.5.3 Effect of Aging-Aware Scheduling . . . . . . . . . . . . . . . . . . . . . . . . 20.5.4 Effect of different Power Gating Strategies . . . . . . . . . . . . . . .

415 415 416 417 417 418 421 423 424 425 425 426 426 426 428 430 431

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21

Contents

20.5.5 Combination of Clock/Power Gating and Scheduling . . . . 20.5.6 Application Dependencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.6 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

432 433 436 437

Reducing Processor Wearout by Exploiting the Timing Slack of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2 Special Aging Mitigation Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.1 Input Vector Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.2.2 Power Gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3 Aging-Aware Instruction Scheduling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.1 Instruction Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.2 Delay-Aware Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.3.3 Further Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4 Experimental Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.1 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.4.2 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21.5 Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

439 439 441 441 442 442 443 446 448 448 448 450 453 454

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

List of Figures

Fig. 1.1 Fig. 1.2 Fig. 2.1 Fig. 2.2 Fig. 2.3 Fig. 2.4 Fig. 2.5

Fig. 2.6 Fig. 2.7 Fig. 2.8 Fig. 2.9

Fig. 2.10 Fig. 2.11 Fig. 2.12

Fig. 2.13

The lifetime of interconnect wires versus technology nodes by ITRS 2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evolution of the required current density versus the JEM and Jmax from ITRS 2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The 3D view of the confined Cu damascene structure with barrier and capping layers [60] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The stress development and distribution in EM, [10] . . . . . . . . . . . . . Interconnect tree confined by diffusion barriers/liners [58] . . . . . . A two-terminal wire with the electron flow and current flow indicated by the arrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evolution of hydrostatic stress along the wire, (a), and at the cathode end, (b), over time stressed under different current densities and temperatures, in the case of zero initial stress [25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress evolution caused by actual currents and traditional effective DC current [32] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EM-stress distribution change over time in simple metal wire for void growth [14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The structure of a confined Cu damascene wire [60] . . . . . . . . . . . . . Side-view of void formation: (a) void in a via-above line (early failure mode); (b) void in a via-below line (later failure mode) [60] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Current exponent n fitting for Korhonen’s equation [60] . . . . . . . . . Compare tnuc in proposed model and COMSOL result [60] . . . . . . (a) The three-phase EM model and the resulting resistance change over time [60]. (b) Measured resistance change, Courtesy of [64] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The computed resistance change over time based on the proposed three-phase EM model [60] . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 5 14 15 16 18

20 22 24 26

27 27 29

30 32

xxv

xxvi

Fig. 2.14

Fig. 2.15 Fig. 2.16 Fig. 2.17 Fig. 2.18 Fig. 2.19 Fig. 2.20 Fig. 3.1 Fig. 3.2 Fig. 3.3 Fig. 3.4 Fig. 3.5 Fig. 3.6 Fig. 3.7 Fig. 3.8 Fig. 3.9 Fig. 3.10 Fig. 3.11 Fig. 4.1 Fig. 4.2

Fig. 4.3 Fig. 4.4

List of Figures

(a) The computed current exponent values from the 3 phase EM model [60]; (b) Measured current exponent values versus current densities, Courtesy of [18] . . . . . . . . . . . . . . . . . A T-shaped wire with main segment and two other segments . . . . The typical stress evolution on a 30 µm copper wire computed by finite element analysis [58] . . . . . . . . . . . . . . . . . . . . . . . . . . (a) A two-segment wire and the direction indicate electron flow; (b) Stress integration area of a two-segment wire . . . . . . . . . . Stress distribution for two-segment wire at steady state [58] . . . . . A T-shaped wire (arrows indicate electron flow) [58] . . . . . . . . . . . . (a) Stress on horizontal segment 0–2; (b) Stress on vertical segment 1–3 [58] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Discretization of the two-segment wire with length L and segment lengths L2 [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A two-terminal wire with the electron flow indicated by the arrow [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example piecewise constant current density j input as a function of time t [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cathode stress over time for multiple wire temperatures [6] . . . . . Two-segment copper damascene wire with steady-state stress due to EM migration [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Nucleation stage validation for two wire segments. FastEM solved using q = 7 with 0.0155% average error [6] . . . . . . . . . . . . . . Growth stage validation for two wire segments. FastEM solved using q = 7 with 0.0123% average error [6] . . . . . . . . . . . . . . Cathode stress comparison under piecewise constant current density input [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cathode stress under varying temperature T = 360, 370, 365, 390 K [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Eigenvalue plot with (a) showing all eigenvalues and (b) without the two largest values [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress near nucleation time for 174-segment tree with different numbers of computed poles [6] . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnect tree confined by diffusion barriers/liners [24] . . . . . . (a) Illustration of T-junction interconnect with directed graph inserted to indicate electron flow. (b) Stress at the cathode end increases linearly as the stub is placed further away from the cathode end [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A three-terminal wire, with the direction indicating electron flow [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Different discretization steps (sizes) lead to the same steady-state stress [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

32 33 35 36 38 39 40 48 51 54 57 59 60 60 61 61 62 63 68

69 72 78

List of Figures

Fig. 4.5

Fig. 4.6

Fig. 4.7 Fig. 4.8 Fig. 4.9 Fig. 4.10

Fig. Fig. Fig. Fig. Fig. Fig. Fig.

4.11 4.12 4.13 4.14 4.15 4.16 4.17

Fig. 4.18

Fig. 4.19

Fig. 5.1 Fig. 5.2

Fig. 5.3 Fig. 5.4 Fig. 5.5

xxvii

(a) A three-terminal wire with inactive (passive) sink, with the cathode at node 2. (b) The steady-state stress distribution of a three-terminal wire with inactive (passive) sink [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) 2-D stress distribution on wire at steady state for passive reservoir. (b) EM stress versus length at steady state [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) 2-D stress distribution on wire at steady state for passive sink. (b) EM stress versus length at steady state [24] . . . . Interconnect examples for EM analysis for T-shaped four-terminal wire [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comb-structured interconnect examples for EM analysis [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) EM stress validation for each comb-structured interconnect with changing LB . (b) EM stress validation for each comb-structured interconnect with changing LF [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . L-shaped wire structure with three nodes [24] . . . . . . . . . . . . . . . . . . . . L-shaped wire structure with current crowding effects [24] . . . . . . U-shaped wire structure with four nodes [24] . . . . . . . . . . . . . . . . . . . . . U-shaped wire structure with current crowding effects [24] . . . . . . A 4 × 4 mesh-structured wire [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A small portion of a typical power supply network [18] . . . . . . . . . . Steady-state EM stress comparisons for each straight-line three-terminal interconnect case (x: case number, y: EM stress at the node 0 (cathode node)) [24] . . . . . . . . . . . . . . . . . . . . . . . . . . EM stress validations for each T-shaped four-terminal interconnect case (x: case number, y: EM stress at the node 0 (cathode node)) [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EM stress validations for each comb-structured interconnect case (x: number of fingers, y: EM stress at the node 0 (cathode node)) [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress relaxation (EM recovery) when current is switched-off [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evolution of hydrostatic stress (a) along the wire and (b) at the cathode end over time stressed under different current densities and temperatures, in the case of zero initial stress [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A random time-dependent current density waveform where piecewise constant method can be applied [12] . . . . . . . . . . . . . . . . . . . Stress evolution under time-varying current load with constant temperature [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Original time-dependent temperature waveform and (b) constant temperature with equivalent time intervals [12] . . . . . . . . .

79

81 81 81 82

84 85 85 86 87 88 90

91

93

94 98

100 102 103 104

xxviii

Fig. 5.6 Fig. 5.7

Fig. 5.8

Fig. 5.9

Fig. 5.10

Fig. 5.11

Fig. 5.12

Fig. 5.13 Fig. 5.14

Fig. 6.1 Fig. 6.2

Fig. 6.3

List of Figures

Stress evolution under time-varying current and temperature stressing [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress evolution caused by (a) periodic, (b) unipolar, and (c) symmetrical bipolar pulse current densities at cathode end of the metal line [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Time-dependent current density and temperature waveform, (b) EM recovery considering different current density change magnitude at constant temperature, (c) stress relaxation when current is switched off at different temperatures, and (d) stress evolution caused by DC current at different temperatures [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Stress evolution at the cathode end of the metal line caused by the unipolar pulse current (UPC) with duty cycle = 30% and averaged DC current, (b) EM lifetimes for UPC load with various duty cycles compared with lifetimes caused by constant peak current load. Here, javg is fixed to 2.5 × 109 A/m2 so that (javg × L) < (j × L), T = 373 K [12] . . Stress evolution at the cathode end of the metal line caused by unipolar pulse (UPC) with duty cycle = 50% and symmetrical bipolar pulse current (BPC) loads at T = 400 K [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Short line resistance evolution caused by a random set of current densities, (b) relaxation of the resistance change accumulated during 2 × 104 s of j = 5 × 109 A/m2 stressing. T = 400 K for both cases [12] . . . . . . . . . . . . . . . . . . . . . . . . . . 1 MHz symmetrical BPC load with j+ = 5 × 109 A/m2 , j− = −5 × 109 A/m2 , t+ = t− = P /2, T+ = 450 K, T− = 400 K [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power trace in KnightShift server [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Two cases of the power trace for Xeon node and (b) the resulting hydrostatic stress evolution kinetics in the interconnect, where current density is assumed to be 4 × 109 A/m2 [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

105

107

110

111

113

115

116 117

118

Three-terminal interconnect tree with two wire segments [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Steady-state stress distribution for an active segment of length L2 = 20 µm with an inactive sink of length L1 = 6 µm [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 The EM stress development along segments 1 and 2 in the three-terminal interconnect tree: (a) j2 = − 23 j1 ; (b) j2 = − 13 j1 ; (c) j2 = 13 j1 ; (d) j2 = 23 j1 [4] . . . . . . . . . . . . . . . . . . . . . . . 129

List of Figures

Fig. 6.4

Fig. 6.5

Fig. 6.6

Fig. 6.7

Fig. 6.8 Fig. 6.9

Fig. 6.10

Fig. 6.11

Fig. 6.12

Fig. 6.13 Fig. 6.14 Fig. 7.1

Fig. 7.2

xxix

The EM stress development along segments 1 and 2 in the three-terminal interconnect tree: (a) L2 = 16 L1 ; (b) L2 = 26 L1 ; (c) L2 = 36 L1 ; (d) L2 = 46 L1 [4] . . . . . . . . . . . . . . . . . . . . . The temperature profiles for simulations during the EM lifetime for the three-terminal interconnect tree: (a) temperatures between 353 and 373 K; (b) temperatures between 383 and 473 K [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The EM stress development at the cathode end of the three-terminal interconnect tree: (a) under temperature profiles shown in Fig. 6.5a; (b) under temperature profiles shown in Fig. 6.5b [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The EM stress development along segments 1 and 2 in the three-terminal interconnect tree considering current density and segment length configurations: (a) case I; (b) case II; (c) case III; (d) case IV; (e) case V; (f) case VI [4] . . . . . . . The proposed analytical method compared against XSim results [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The EM stress development along segments 1 and 2 in the three-terminal interconnect tree considering time-varying temperature: (a) t = 8 × 104 s; (b) t = 2 × 106 s; (c) t = 5 × 106 s; (d) t = 4 × 107 s [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relative errors between the one-term and two-term approximations at different locations in the three-terminal interconnect tree: (a) constant temperature; (b) time-varying temperature [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison between the proposed analytical method and the eigenfunction method for calculating the EM stress development along the three-terminal interconnect tree [4] . . . . . . The direction of the current is indicated by the arrow: (a) single line wire (“I” shape); (b) three-terminal wire (“dotted I” shape); (c) four-terminal wire (“T” shape); (d) cross-shaped five-terminal wire (“+” shape) [17] . . . . . . . . . . . . . . . . . Example of a multi-segment wire [18] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress distribution over time on multi-segment wire calculated by integral transformation method [18] . . . . . . . . . . . . . . .

131

132

133

138 139

140

141

143

144 146 147

(a) Steady-state hydrostatic stress (Pa) distribution predicted by the initial current densities and (b) initial IR-drop (V) distribution, in the layer that directly connects to circuits (M3) of IBMPG2 [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Void distribution, (a), and the IR-drop (V) distribution in the layer that directly connects to circuits (M3), (b), of IBMPG2 at t = TTF. Void volume saturation is taken into account [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

xxx

List of Figures

Fig. 7.3

Fig. 7.4 Fig. 7.5 Fig. 7.6 Fig. 7.7

Fig. 7.8 Fig. 7.9 Fig. Fig. Fig. Fig.

7.10 7.11 7.12 7.13

Fig. 7.14

Fig. 7.15

Fig. 7.16

Fig. 8.1 Fig. 8.2 Fig. 8.3

Fig. 8.4 Fig. 8.5

Void distribution, (a), and the IR-drop (V) distribution in the layer that is directly connected to circuit (M3), (b), of IBMPG2 at t = TTF. Void volume saturation is not considered [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage drop of the first failed node and maximum IR drop in IBMPGNEW1 change over time [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Effect of temperature on TTF [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layout of 32 nm test-chip [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power consumption in device layer (0–6.91 mW), (a), and joule in M1 (0–0.06 mW), (b), M3 (0–0.33 mW), (c), and M6 (0–4.53 mW), (d), layers [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The die is divided into arrays of thermal cells with 6 thermal resistances in each cell (bin) [4] . . . . . . . . . . . . . . . . . . . . . . . . . . Effective thermal resistance of M2 layer in (a) x direction and (b) y direction [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature (K) variation across different layers [4] . . . . . . . . . . . . . Temperature (K) distribution in M1 layer [4] . . . . . . . . . . . . . . . . . . . . . Thermal stress (MPa) distribution in M1 layer [4] . . . . . . . . . . . . . . . . (a) Steady-state hydrostatic stress map of M1 layer predicted by initial current densities (the distribution of thermal stress is taken into account), (b) EM-induced IR drops change in the power net, and (c) the increase of the maximum IR drop and number of nucleated voids over time [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of predicted maximum IR drop increase between w/o and w/ temperature variation conditions. Uniformly distributed thermal stress is considered in both cases [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The branches with voids (blue color) at the time when simulation stops in two cases: (a) uniform averaged temperature and (b) with temperature variation. Uniform thermal stress distribution is considered in both cases [4] . . . . . . . . Comparison of the IR drop evolutions calculated w/o and w/ thermal variation assessments. Temperature variation is considered in both cases [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The proposed reliability resource-based task migration scheme [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low p-state mode compensation scheme (one core) [13] . . . . . . . . Low p-state mode compensation scheme for a 4-core system with (a) imbalanced TTF consumption (b) balanced TTF consumption [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The increase of IR drop in power grid over years [13] . . . . . . . . . . . . The different TTF values under different task loads [13] . . . . . . . . .

161 162 162 163

165 165 166 167 168 168

172

173

174

175 182 183

184 187 188

List of Figures

Fig. 8.6 Fig. 8.7

Fig. 8.8

Fig. 8.9 Fig. 9.1 Fig. 9.2 Fig. 9.3 Fig. 9.4 Fig. 9.5

Fig. 9.6

Fig. 9.7 Fig. 10.1 Fig. 10.2

Fig. 10.3

Fig. 10.4

Fig. 10.5

xxxi

TTF resource slack (represented by Sd ) under different task migration schemes [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTF resource slack (represented by Sd ) compensation using low power mode under different task migration schemes [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TTF resource slack (represented by Sd ) evaluations of the proposed method with different temperature-based task migration schemes, temperature-based and temperature threshold-based. For temperature threshold-based, Tthreshold is threshold temperature and Mcore,max is the maximum allowed number of migrations out of 32 cores [13] . . . . . . . . . . . . . . . TTF resource slack (represented by Sd ) with heavy tasks (2× scale-up power traces) [13] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single-rate (a) and multi-rate (b) task scheduling models [12] . . . Multi-rate preemption [12]. (a) Non-preemption and (b) preemption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Core utilization effect—energy savings [12] . . . . . . . . . . . . . . . . . . . . . . . Core utilization effect—lifetime improvement [12] . . . . . . . . . . . . . . . The comparisons of simulated annealing and mixed-integer linear programming methods for the lifetime optimization for single rate with 6, 12, and 24 tasks per one task set under different core utilizations (0.3–0.8 in x-axis) . . . . . . . . . . . . . . . The comparisons of simulated annealing and mixed-integer linear programming methods for the lifetime optimization for multi-rate with 6, 12, and 24 tasks per one task set under different core utilizations (0.3–0.8 in x-axis) . . . . . . . . . . . . . . . Trade-off between lifetime and performance (each triangle is different set of core utilization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q-Learning model with reliability-aware dark silicon framework [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) SPLASH2 benchmark 64 multi-threaded tasks power traces with 44 cores off. (b) Thermal (color:degree) and EM lifetime (number:years) analysis on 64 cores [31] . . . . . . . . . . . Lifetime improvements given power budget and performance deadline on 64-core dark silicon chip: (a) PARSEC small task set. (b) SPLASH-2 large task set [31] . . . . . . Q-learning result for performance deadline from (a, b) PARSEC tasks and light (c, d) SPLASH-2 tasks in 64-core dark silicon chip [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Q-learning result for power constraints from heavy 4 PARSEC tasks and light 64 SPLASH-2 tasks in 64-core dark silicon chip [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

189

190

191 192 198 200 211 211

212

212 213 223

228

232

233

234

xxxii

Fig. 10.6

Fig. 10.7

Fig. 10.8

Fig. 10.9

Fig. 10.10

Fig. 10.11 Fig. 10.12

Fig. 10.13

Fig. 11.1 Fig. 11.2 Fig. 11.3 Fig. 11.4 Fig. 11.5 Fig. 11.6 Fig. 11.7

List of Figures

Post-validation with MILP for Q-learning accuracy: (a) 4 heavy task PARSEC workloads. (b) 64 light tasks SPLASH-2 workloads [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison between EM-induced lifetime and system-level soft error rate at different powers (by different DVFS configurations) on (a) PARSEC small tasks and (b) SPLASH-2 tasks [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Impact of different process technologies on system-level soft error rate, from left bar, case (A) global DVFS, case (B) our proposed DRM with only EM constraint, our proposed DRMs with both EM and SER constraints of case (C) 45 nm, case (D) 32 nm, and case (E) 22 nm [31] . . . . . . . . . . . . . . Energy optimization results (global DVFS, proposed with EM, and with/without tight and loose soft error constraint from small task set on PARSEC benchmarks (different performance deadlines in (a) and (b))) [31] . . . . . . . . . . . . . . . . . . . . . . . Energy optimization results (global DVFS, proposed with EM, and with/without tight and loose soft error constraint from large task set on SPLASH-2 benchmarks (different power budgets in (a) and (b))) [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Constraint violation cases [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Convergence rate of the proposed DRM method with EM-induced lifetime constraint in 64-core dark silicon (SPLASH-2 Tasks) [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) The scalability analysis for our proposed DRM (case 1: two p-states with dark silicon, case 2: three p-states with dark silicon). (b) Total average iteration number for both the cases [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress evolution caused by periodical current density [10] . . . . . . . . Stress evolutions caused by actual currents and traditional effective DC current [10]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Original input driving current density. (b) Calculated EM DC equivalent current density with tnuc [10] . . . . . . . . . . . . . . . . . (a) Original input driving current density. (b) Calculated EM DC equivalent current density with two methods [10] . . . . . . . Comparing the nucleation time of two equivalent methods and original stress [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The DRM and NTC framework [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) two cases of power traces from the proposed framework and (b) and the resulting MTTF without/with recovery effects [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

235

236

236

237

238 239

240

240 249 250 251 252 253 256

259

List of Figures

xxxiii

Fig. 11.8

Performance, energy, and EM-induced lifetime from the proposed DRM considering recovery effects for three cases: (1) Recovery effects with Trecovery = 50 s (first column). (2) Recovery effects with Trecovery = 1000 s (the second column). (3) Only DRM without recovery effects (the third column) [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Fig. 12.1

(a) Total datacenter cost by primary causes of unplanned outage ($1000). (b) Power consumption breakdown for one server [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Feed-forward neural network structure and data configuration [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The evaluation platform for datacenter and energy and reliability management algorithms [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . Validating violations with constraint limits. (a) Average socket MTTF. (b) Average cluster power. (c) Tail latency [11] . . .

Fig. 12.2 Fig. 12.3 Fig. 12.4 Fig. 13.1 Fig. 13.2 Fig. 13.3 Fig. 13.4 Fig. 13.5

Fig. 13.6 Fig. 13.7 Fig. 13.8

Fig. 13.9 Fig. 13.10 Fig. 13.11 Fig. 13.12 Fig. 13.13 Fig. 14.1

Components of chip guard-band for the IBM Power7+ [58] . . . . . BTI mechanisms: (a) Reaction-Diffusion (R-D) mechanism. (b) Trapping-Detrapping (TD) mechanism . . . . . . . . . . Threshold voltage shift due to NBTI and PBTI for 40 nm technology node with voltage constraint 2.5 V at 125 ◦ C . . . . . . . . . (a) Static vs. dynamic NBTI and (b) the dependency of dynamic NBTI to duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) BTI effect in large devices, (b) stochastic behavior of BTI in deeply-scaled devices and (c) lifetime of devices for different technology nodes [34] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Parameters affecting BTI for three different devices. (b) BTI-induced Vth for the three devices [33] . . . . . . . . . . . . . . . . . . . . . (a) CET map, (b) occupancy probability map, and (c) CET-active map [68] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) η calculated using (13.2.22) for different FinFET technologies. (b) Average number of occupied traps as function of DF for different FinFET technologies calculated using (13.2.16), (13.2.17) and (13.2.18) . . . . . . . . . . . . . . . Hot Carrier Injection (HCI) physical mechanism . . . . . . . . . . . . . . . . . HCI-induced Vth over time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (a) Capture and emission of mobile carriers and (b) threshold voltage fluctuation due to RTN . . . . . . . . . . . . . . . . . . . . . . . . . Time dependent dielectric Breakdown (TTDB) phases [32] . . . . . Power-law SBD model: (a) voltage dependent current source and (b) voltage dependent resistance model [69] . . . . . . . . .

264 268 271 274 280 282 283 285

286 287 288

290 291 292 293 296 297

Flow of proposed stochastic NBTI and process variation-aware timing analysis framework [7] . . . . . . . . . . . . . . . . . . . 307

xxxiv

List of Figures

Fig. 14.2

(a) Probability density function of NBTI-induced D for atomistic NBTI (ANBTI) and normal NBTI (NNBTI). (b) QQ-plot of atomistic NBTI (ANBTI) [7]. (c) QQ-plot of normal NBTI (NNBTI) [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.3 D distribution of (a) c880 and (b) c1355 considering atomistic NBTI (ANBTI), PV and combined effects (ANBTI+PV) [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.4 Timing margin error due to separately consideration of process variation and stochastic NBTI compared to combined effect [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.5 Violin plot of NBTI and process variation-inducedD [7] . . . . . . Fig. 14.6 QQ-plot of different circuits with different number of levels and critical paths [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.7 Effect of workload on ANBTI-induced D distribution of the circuit [7]. (a) One inverter. (b) Chain of 10 inverters. (c) c880. (d) c499 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.8 Effect of workload on ANBTI-induced D distribution of c2670 circuit for (a) unbalanced and (b) balanced versions [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.9 Effect of workload on signal probability distribution of the nodes on critical paths for c2670 circuit for (a) unbalanced and (b) balanced versions [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.10 Number of critical paths for c2670 circuit for (a) unbalanced and (b) balanced versions [7] . . . . . . . . . . . . . . . . . . . . . . . . . Fig. 14.11 The mean value of the maximum of n random variables

311

313

314 314 315

317

317

318 318

n

(E[max Vi ]). The random variables have a mean value of i=1

1 and standard deviation of 0.1. The values of standard deviation and mean are set according to the maximum NBTI-induced delay degradation of a single path which is less than 10% [7] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Fig. 15.1

Fig. 15.2

Fig. 15.3

Fig. 15.4

Effect of Wp/W n optimization on NBTI-induced delay degradation of an inverter with input SP = 0.5. (a) Time-zero-balanced. (b) Lifetime-balanced . . . . . . . . . . . . . . . . . . . . . . . Effect of Wp/W n optimization on BTI-induced delay degradation of an inverter with input SP = 0.1 [14]. (a) Time-zero-balanced. (b) Lifetime-balanced . . . . . . . . . . . . . . . . . . . . . . . Optimized Wp/W n ratio increase for different signal probabilities normalized to the case that it is optimized for time = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A simple circuit to show the efficiency of aging-aware standard cell sizing: (a) time-zero-balanced vs lifetime-balanced mapping and (b) delay of lifetime-balanced vs time-zero-balanced [14] . . . . . . . . . . . . . . . . . . . . .

325

326

326

327

List of Figures

xxxv

Fig. 15.5 Fig. Fig. Fig.

Fig.

Fig.

Overall flow of proposed aging-aware standard cell library design [14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.6 The histogram of internal node SP distribution for ISCAS89 benchmark circuits (over all benchmarks) . . . . . . . . . . . . . 15.7 Overall flow to obtain simulation results [14] . . . . . . . . . . . . . . . . . . . . . 15.8 Histogram of the internal node SPs of different applications. (a) benchmark = CRC32, (b) benchmark = Bitcounts, (c) benchmark = Stringsearch, (d) benchmark = QSort . . . . . . . . . . . . . 15.9 Effect of different workload on the SP range of internal nodes when the number of SP ranges is equal to (a) 2, (b) 3, (c) 5, (d) the average for all cases. SP range shift is shown for [80% 100%] range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.10 Effect of (a) voltage and (b) temperature variation on the rise/fall delay ratio of a simple inverter with input SP of 0.1 after 3 years [14] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Fig. 16.1

Fig. 16.2 Fig. 16.3

Fig. 16.4

Fig. 16.5

Fig. 16.6

Fig. 17.1

Clk-to-q and data-to-q for HLFF. The optimum setup-time is the setup skew at the minimum of data-to-q (delay) plot, and the corresponding data-to-q is called the delay of the FF [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The simulation test bench with voltage droop [4] . . . . . . . . . . . . . . . . . (a) Normalized delay of SDFF at different input SPs. The delay increases by increasing the input SP (temperature = 25 ◦ C, voltage droop = 0%). (b) Mean average percentage error (MAPE) of separate consideration of different sources of variation compared to the combined effect calculated according to Eq. (16.3.1) [4] . . . . . . . . . . . . . . . . . . . . . Effect of temperature and voltage droop on SAFF, SDFF, DFF, and HLFF reliability after aging. The numbers represent the percentage of timing failures for ranges of temperatures and voltage droops. (22 nm) [4] . . . . . . . . . . . . . . . . . . . . . The increase in the FFs’ delays for different technology nodes. The sizes of the violins increase by increasing the temperature and voltage droop. (All values are normalized to the nominal value of the corresponding technology node when T = 25 ◦ C, Vdd = 100%) [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Histogram of worst-case delay for a C2MOS FF before optimization, after delay minimization (first phase), and after sensitivity minimization (second phase at 22 nm). The histogram is pushed to the left by delay minimization, and is made thinner after sensitivity minimization [4] . . . . . . . . . . . . . . . .

329 331 332

337

339

340

345 346

347

349

350

354

Different FF timing parameters. The correct functionality is guaranteed by considering the FF delay as illustrated [6] . . . . . . 359

xxxvi

Fig. 17.2

Fig. 17.3

Fig. 17.4

Fig. 17.5 Fig. 17.6

Fig. 17.7 Fig. 17.8

List of Figures

(a) Delay of LH/HL paths of an aged C2MOS FF (optimized for PDP in the fresh state) for different input SPs. (b) Separate LH (red)/HL (blue) paths of the FF [6] . . . . . . . . . Delay of a C2MOS FF which is aged under SP = 0 over 5 years for LH/HL transitions, compared to the FF optimized for SP = 0 showing how the unbalanced aging of LH/HL paths worsens the degradation in original FF [6] . . . . . . . . . . . . . . . . . The average FF SPs during the execution of some MiBench workloads on Leon3, and the corresponding delay degradation in 5 years [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Overall flow to find the optimum FF sizing for S-BTI stress at a specific working corner (voltage, temperature) [6] . . . . . . . . . . . Performance of the original FF vs. the FF optimized by the proposed method at SP0 and SP1, before and after aging (5 years) [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay and leakage trade-off for C2MOS FF. Delay improvement saturates as β increases [6] . . . . . . . . . . . . . . . . . . . . . . . . . Fresh vs. aged delay of critical paths (for basicmath workload). Replacing the original FFs under S-BTI (red) with the optimized FFs (green) suppresses the aging of the most critical paths [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Comparison of Vth due to D-BTI (duty cycle (α) = 0.5) and S-BTI [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.2 Overview of the proposed technique [30] . . . . . . . . . . . . . . . . . . . . . . . . . 18.3 Steps involved in the offline characterization phase [30] . . . . . . . . . 18.4 Correlation analysis of flip-flops based on the overlap of concurrent SAPs [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.5 Flow chart showing the steps involved in ATPG-based subroutine generation [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.6 Illustration of ATPG-based subroutine generation settings for mitigating static aging [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.7 Flow chart showing the steps involved in functionality-based subroutine generation [30] ....................................................................... 18.8 Illustration of the online static aging monitoring hardware [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.9 Illustration of switching event propagation from flip-flops under static aging to the logic gates under static aging in their forward fan-out cone [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18.10 Illustration of static aging relaxation of the internal transistors of a master-slave flip-flop on subsequent switching events [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

360

361

362 365

368 369

371

Fig. 18.1 Fig. Fig. Fig. Fig. Fig. Fig.

Fig. Fig.

Fig.

376 379 380 382 384 385

387 389

391

392

List of Figures

xxxvii

Fig. 18.11 Results demonstrating the variation in percentage of (a) union of critical flip-flops of all workloads (UCF), and (b) representative flip-flops (RFF), with the minimum duration of SAPs for Fabscalar and Leon3 processors [30] . . . . . . . . . . . . . . . . 395 Fig. 19.1 Fig. 19.2

Fig. 19.3 Fig. 19.4 Fig. Fig. Fig. Fig. Fig.

20.1 20.2 20.3 20.4 20.5

Fig. 20.6

Fig. 20.7

Fig. 21.1 Fig. 21.2 Fig. 21.3 Fig. 21.4

Overall flow of the proposed NBTI-aware NOP selection and evaluation [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The effect of different NOPs (opcode and operand values) on NBTI-induced delay degradation (the range shows the impact of operand values) [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hardware-based implementation of NOP in MIPS architecture [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Lifetime improvement for selected spec2000 application using NBTI-aware NOP assignment [4] . . . . . . . . . . . . . . . . . . . . . . . . . . .

404

405 409 412

Data/information flow in our ExtraTime framework [25] . . . . . . . . Time flow of power gating periods of an execution unit [25] . . . . Effects of clock gating (CG) and power gating (PG) [25] . . . . . . . . Effects of different scheduling policies (with CG/PG) [25] . . . . . . Effect of various power gating strategies (with clock gating) on performance, power, and aging [25] (a) Different tidle cycles. (b) Different tdur cycles . . . . . . . . . . . . . . . . . . . . Relative improvements (possible maximum = 100%) of the “preferred” configuration for different applications compared to the native solution (CQ1, no CG/PG) [25] . . . . . . . . . . Influence of various applications on NBTI- and HCI-induced transistor wearout (using the “preferred” configuration) [25]. (a) Worst rel d for NBTI and HCI for several workloads. (b) rel d for ALU and FPU (NBTI and HCI) for several workloads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

417 425 429 430

Illustration of TC and NTC instructions [21] . . . . . . . . . . . . . . . . . . . . . Worst-case delay distribution and occurrence rate of ALU instructions [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Classification of instructions into TC and NTC and its impact on MTTF [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assignment of instructions to functional units for balanced and aging-aware scheduling [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

440

431

434

435

443 445 447

List of Tables

Table 1.1

Table 1.2 Table 2.1 Table 2.2 Table 3.1 Table 3.2 Table 4.1 Table 4.2 Table Table Table Table

4.3 4.4 4.5 4.6

Table 4.7 Table 4.8

Technology parameters based on the ITRS 2014 [15, 18]; maximum current and current densities for copper at 105 ◦ C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High performance computing (HPC) reliability and power issues [9, 12]), MTTI means mean time to interrupt . . . . . . . . . . . . . . Parameters and typical values used [25] . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparison of void area of two methods (wire width = 1 µm) [58]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Scalability performance results comparing FDTD and FastEM using increasingly large n-segment trees . . . . . . . . . . . . . . . . . Scalability performance results comparing FDTD and FastEM using increasingly large n-segment trees . . . . . . . . . . . . . . . . . The computed poles for the three-terminal wire [24] . . . . . . . . . . . . . EM stress calculated with and without current crowding effects [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stress values at each node for the U-shaped structure [24] . . . . . . . Stress condition for mesh structure [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . Property of IBM benchmarks [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameters for each straight-line three-terminal interconnect case [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameters for each T-shaped four-terminal interconnect case (l = µm, w = µm, and j = MA/cm2 ) [24] . . . . . . . . . . . . . . . . EM stress validations for comb-structured interconnect cases [24] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 6 21 39 64 64 78 86 87 89 90 91 92 93

Table 5.1

Parameters and typical values [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Table 6.1

Current density and segment length configurations used for modeling and simulation [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

Table 7.1

Parameters used in the proposed model [4] . . . . . . . . . . . . . . . . . . . . . . . . 157 xxxix

xl

Table 7.2 Table 7.3 Table 9.1 Table 9.2 Table 9.3 Table 9.4 Table 9.5 Table 9.6

List of Tables

Comparison of power grid MTTF using Black’s equation and the proposed model [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Geometry of power grid interconnects (µm) [4] . . . . . . . . . . . . . . . . . . 163 A preliminary measurement for preemptive effect on lifetime (years) [12] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimization method evaluation for low core utilization single-rate task (SA and MILP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimization method evaluation for high core utilization single-rate task (SA and MILP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimization method evaluation for low core utilization multi-rate task (SA and MILP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optimization method evaluation for high core utilization multi-rate task (SA and MILP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Elapsed CPU time to solve the proposed simulated annealing and MILP problems (second per one task set, 80% core utilization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Table 10.1 Raw SEU rate per microprocessor on different technologies [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10.2 An example of control states for a 3-core processor [31] . . . . . . . . Table 10.3 Elapsed CPU time to solve the proposed Q-learning and MILP problems [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10.4 Large-scale experiments with five p-state on 128-core and 256-core [31] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

200 207 208 209 210

213 221 223 229 241

Table 11.1 Results for dynamic reliability management for 64-core near-threshold dark silicon [10] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Table 12.1 Accuracy analysis (RMSE) of the feed-forward neural network (FNN) model [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Table 12.2 Energy optimization for datacenter [11] . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Table 13.1 RD model of NBTI-induced Vth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Table 14.1 Information of the normalized D distribution for four different cases: (1) normal NBTI (NNBTI), (2) atomistic NBTI (ANBTI), (3) process variation (PV), and (4) combined effect of process variation and NBTI (ANBTI+PV) [7] 312 Table 14.2 Runtime of proposed variation-aware timing analysis [7] . . . . . . . . 319 Table 15.1 The efficiency of our technique compared to the normal standard cell library design in terms of lifetime improvement and area overhead . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 Table 16.1 FF optimization method summary [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 Table 16.2 FF characteristics before and after optimization. . . . . . . . . . . . . . . . . . . 355 Table 17.1 FF optimization method summary [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364

List of Tables

xli

Table 17.2 C2MOS FF characteristics when: (1) optimized FF for PDP in the fresh state, (2) optimized for PDP in post-aging, and (3) optimized by proposed method before/after aging at SP0 [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Table 17.3 Processor delay comparison when (1) using only original FFs, and (2) using proposed method [6] . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Table 18.1 Functionality based flip-flop switching [30] . . . . . . . . . . . . . . . . . . . . . . . 386 Table 18.2 Examples for subroutine generation [30] . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Table 18.3 Representative flip-flop (FF) selection for different workloads for Leon3 and Fabscalar with Tsad_min = 3 million cycles [30] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Table 19.1 LP compatible object functions for gate delays [4] . . . . . . . . . . . . . Table 19.2 LP constraints for basic logic operations [4] . . . . . . . . . . . . . . . . . . . . . . Table 19.3 NOP candidates of MIPS processor in the software-based implementation [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19.4 Register reservation overhead on IPC [4] . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19.5 Normalized overhead of hardware-based implementation of NOP to original MIPS [4] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.1 Temperature effect on aging-induced delay change for an ALU [25] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20.2 Difference between a detailed transistor-level model and our proposed microarchitectural models regarding the estimate delay for an ALU after 3 years due to NBTI [25] . . . . . . . Table 20.3 Scheduling policies and how they influence which execution unit (EU) executes which instruction (A, . . . ,E) . . . . . . . Table 20.4 Configuration details for the experiments [25] . . . . . . . . . . . . . . . . . . . . Table 20.5 Native solution (CQ1, no CG/PG) vs. “preferred” configuration (CQ3-109 , CG, PG: tdur = 0, tidle = 5000) [25] . . Table 21.1 Workloads and their instruction ratios (execution time = 0.5 s) [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21.2 Different scheduling techniques and combinations of ALUs (normal once and specialized once for TC instructions) [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21.3 Configuration details for the experiments [21] . . . . . . . . . . . . . . . . . . . . Table 21.4 MTTF in years for several SPEC2000 benchmarks (with power gating or input vector control) [21] . . . . . . . . . . . . . . . . . . . . . . . . . Table 21.5 Performance (IPC) evaluation of different scheduling techniques [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

406 407 408 412 413 422

423 427 428 432 444

447 449 451 452

Part I

New Physics-Based EM Analysis and System-Level Dynamic Reliability Management

Chapter 1

Introduction

Reliability has become a significant challenge for design of current nanometer integrated circuits (ICs). Reliability degradation caused by aging effects are becoming limiting constraints in emerging computing and communication platforms due to increased failure rates from the continuous transistor scaling, increasing process variations, and aggressive power reductions. The introduction of new materials, processes, and devices coupled with voltage scaling limitations and increasing power density will impose many new reliability challenges.

1.1 Why Electromigration Reliability? Among many reliability effects, electromigration (EM) is the primary failure source for VLSI interconnects. As technology advances into the sub-10nm regime with FinFET devices, it is expected that the future chips would show signs of EM-induced aging much faster than previous generations. Thanks to the shrinking interconnect geometries and high temperature around the fins in the FinFET transistors. The EM assessment and verification is critical in the development of VLSI circuits to guarantee the metal wires and vias that connect the various devices in the chip do not fail and cause functional failure of the chip over years of continuous use. Electromigration failure of interconnects has been a long-standing concern for the development of highly reliable VLSI systems. Despite intense efforts from both industry and academia following the first observation of EM-related failure of Al circuit interconnects by James Black in 1969 [3], it has proven impossible to find a robust process solution by material modification for either Al or the today’s Cu metal system. EM failure can only partially be mitigated with process and material solutions and ultimately needs to be controlled and managed at circuits and even system levels in a holistic fashion. The International Technology Roadmap for Semiconductors (ITRS 2014) predicts that the EM-induced lifetime of a single © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_1

3

4

1

t50/t50 (1.3x0.9)

Fig. 1.1 The lifetime of interconnect wires versus technology nodes by ITRS 2014

1 Introduction

Assumption: j is constant

Scaling curve 0.1

eliner

0.01

Void h

Cu

65 nm 45 nm 0.0

0.2

0.4

0.6

0.8

1.0

1.2

DLCr h (µm2)

interconnect wire in an upper stream structure will decrease by half for each new technological generation as shown in Fig. 1.1 [15]. The figure also shows the actual and predicted lifetime scaling versus interconnect geometry over several technological generations. It has been predicted that EM failure will become more significant for interconnects in FinFET based technologies at 10nm and it is urgent to address this “EM crisis” which has recently prompted intense efforts to develop more robust interconnect materials, structures, and design solutions [21, 22]. Table 1.1 shows some important parameters related to the EM reliability from the IRES 2014 [15, 18]. In this table, Jmax is the maximum current density allowed to ensure immortality of wires, which basically goes down as technology advances. JEM is the maximum current density allowed (even with EM failure), beyond which we do not have solutions so far to mitigate unmet lifetime target due to EM failure. On the other hand, as technology advances, the cross section of the wires scales much faster than the scaling of wire width, which will lead to higher current density if we still need to deliver even the same amount of currents. As a result, from the circuit performance perspective, we actually need higher current density to maintain the signal integrity of the wires as we move to more advanced nodes. As you can see, after 2024, this required current density will be larger than the maximum allowed current density JEM , which means existing copper based interconnect technique will fall to the ground if no novel interconnect solutions are invented. The three current density trends and potential EM crisis is also graphically illustrated in Fig. 1.2. Even for today’s technology, EM becomes a limiting factor in the chip design practice. For instance, to ensure the EM signoff, conservative design rules based on the worst cases (highest possible temperature and power consumption) and simple empirical EM models can lead to significant overdesign and 2× to 3× enlarged guard bands [2]. Such conservative and overdesign rules, however, will be no longer an option in current and future technologies because 3× guardband increase will significantly increase the buffer size and many other aspects of chips, which will lead to increasing currents, and hence, the power consumption and cost of the chips. One fundamental issue in today’s VLSI design flow is the lack of physics-based EM

1.1 Why Electromigration Reliability?

5

Table 1.1 Technology parameters based on the ITRS 2014 [15, 18]; maximum current and current densities for copper at 105 ◦ C Year Maximum tolerable current density (w\o EM degradation)—Jmax Maximum current density (beyond solutions are unknown)—JEM Required current density for driving four inverter gates

2016 3.0

2018 1.8

2020 1.1

2022 0.7

2024 0.4

2026 0.3

2028 0.2

15.4

9.3

5.6

3.4

2.1

1.2

0.7

2.29

2.59

2.94

3.76

4.50

5.35

1.81

EM to be expected

Solution unknown

Fig. 1.2 Evolution of the required current density versus the JEM and Jmax from ITRS 2014

models, which can link to many design and run time parameters so that EM can be drastically optimized at circuit, architecture, and system levels or in a cross-layer, holistic way, which will be an enable key to resolve the incoming EM crisis. Currently employed Blech limit [4] (for the out filtration of immortal segments) and Black’s equation [3] (for calculating MTTFs for segments characterized by known current densities and temperatures) are subjects of the hard criticism [13, 19]. Across-die variation of residual stress makes the Blech’s “critical product” to be layout-dependent variables rather than experimentally determined constants. The Black equation’s current density exponent and the EM activation energy are shown to be the functions of current density and temperature, making the widely accepted methodology of calculating the MTTF at use condition groundless. The reason is that conventionally, the value of activation energy and current density exponent at chip use condition are assumed to be the same as the value determined at the highly stressed (accelerated) conditions, characterized by high current densities and elevated temperatures. These conservative design rules are not suitable for future technology scaling since more design guardbands are required for chip timing accuracy, and thus such a worst-case design methodology results in inefficiency and considerable penalties in the area, performance, power, and reliability budgets. Therefore, during the design process, a balance must be found to ensure circuit performance without seriously impairing electromigration reliability. Achieving this

6

1 Introduction

balance requires a thorough fundamental understanding of EM physics kinetics and the dominant factors for the failure process.

1.2 Why System-Level EM-Reliability Management? In addition to looking at reliability issues at the physics and circuit levels, EMreliability issues also need to be addressed at the architecture and system levels. The Exascale Roadmap from United States Department of Energy (U.S. DOE) reported potential power increasing issues in the future high performance computing (HPC) as seen in Table 1.2 [9]. Moreover, failure rates of large-scale HPC will dramatically increase; thus, it is expected to be order of magnitude of hours in the future in Table 1.2 [12]. For the safety-critical real-time embedded systems (such as satellite and surveillance systems) where reliability is as important as energy efficiency, reliabilityaware energy management becomes a necessity. Some initial efforts have been carried out for system level reliability analysis for SoC (system-on-a-chip). RAMP [28] is the first architecture level tool for modeling the long-term processor reliability of microprocessors at the design stage. The follow-up work by the same authors proposed a dynamic reliability management (DRM) concept by dynamic voltage and frequency scaling (DVFS) [29]. These works showed that it was not sufficient to just manage the temperature or power from the reliability perspective. For real-time embedded systems, many existing works focus on minimizing energy consumption while meeting all the deadlines for various real-time task models. Existing works include power management schemes, which exploits the available static and/or dynamic slack in the systems [1, 5, 6, 23–25]. For the high-performance system, reducing power will implicitly improve the reliability of a processor. However, the two objectives, increasing lifetime and reducing power, are still not controlled by one knob. Some reliability-aware power management works have been proposed recently [20, 32] by using low power techniques such as DVFS. However, most of those existing works focus on the transient errors instead of long-term wearout failures. Recently a reliability-aware task allocation and scheduling method for multi-core embedded processors were proposed [14]. This work considers long-term failure mechanisms using general reliability models. However, such general models will not be accurate for specific failure mechanisms. Also, task allocation and scheduling are not best methods to

Table 1.2 High performance computing (HPC) reliability and power issues [9, 12]), MTTI means mean time to interrupt Year MTTI Power

2009 1–4 days 6 MW

2012 5–19 h ∼10 MW

2016 50–230 min ∼10 MW

2020 22–120 min ∼20 MW

1.3 Chapter Outlook in Part I

7

manage the long-term wearout failures as they will not significantly change the temperatures of the chip as our study shows. Low power techniques like DVFS are more desired. A method in [27] shows that the power/performance and reliability are intrinsically conflicting metrics and have strong interactions in SoC designs, and proposes a joint policy optimization method. Another dynamic reliability management method was proposed in [16], in which a simple PID based runtime control was applied to optimize the performance subject to the long-term reliability constraints. Recently, architecture researchers predicted that future manycore (100–1000 cores) silicon dies can only be powered up partially (the so-called dark silicon) as power constraints will not allow all the cores to be active at the same time. The consequence is the emergence of the so-called dark silicon manycore microprocessors, which mean only a percentage of cores can be powered on the chip due to the power and temperature limitations. Such manycore systems pose new challenges and opportunities for power/thermal and reliability management of those chips [8]. The reliability management methods for dark silicon manycore scaling have been studied [7, 10]. However, all of these works considered general reliability models, which will not be accurate for specific failure mechanisms. Recently, a new EM model has been used for energy optimization as a DRM but it only considered the EM model [17]. For dynamic power and thermal management, learning based methods have recently become popular. Many proposed methods applied Q-learning based method, which is a reinforcement machine learning method for the adaptive control [11, 26, 31, 33]. To further reduce powers for many applications, ultra-low power designs become necessary. Recent research has led to sub-threshold region where CMOS circuits are found to be capable of operating with a supply voltage of less than 200 mV. The theoretical lower limit of Vdd has been determined to be 36 mV [30]. But at such low voltages, a leakage power dissipation increases drastically making the reduction in dynamic power insignificant. Also the circuit delay increases rapidly as the supply voltage is scaled down, resulting in decreased operation frequency or performance of the circuits.

1.3 Chapter Outlook in Part I In this book, we review some of the recent advances in EM modeling and crosslayer EM-induced dynamic reliability management techniques. The review article does not intend to cover all the recent development for the EM topics. We remark that the topics not covered in this article does not diminish their contributions and values to the communities. In this part, we focus on the recent advances in the EM modeling, analysis, and dynamic EM-based reliability management for manycore microprocessors and other important computing platforms. Chapter 2 presents the physics-based EM modeling methods and assessment techniques developed recently. The chapter starts with reviews of the classic EM physics and existing EM failure models and discusses the limitations of those

8

1 Introduction

models. Then it reviews the mainstream stress-based modeling of EM failure kinetics and the important Korhonen’s equation for describing the hydrostatic stress kinetics in the confined metals with copper material blocking boundary conditions. The chapter further presents the physics-based EM models, which consist of void nucleation and growth phases based on the analytical solutions of the Korhonen’s equations. On top of this, we present recently proposed more accurate physics-based three-phase EM model for single wires and general multi-segment interconnect wires, which represents the state-of-the-art compact EM models. Chapter 3 presents a fast numerical solution to the Korhonen’s equation to find the stress evolution in the confined metal multi-segment interconnect wires. The new approach, which we call FastEM, is based on the finite difference method (FDM) which is used to first discretize the partial differential equations into linear timeinvariant ordinary differential equations (ODE). After discretization, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the size of the original system matrices so that they can be efficiently simulated in the time domain. FastEM can perform the simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently proposed voltage-based EM analysis method for EM immortality checks. Chapter 4 focuses on the novel and fast electromigration (EM) immortality check for general multi-segment interconnect wires. The chapter basically presents a new wire immortality criteria based on a so-called critical EM voltage, which is essentially the natural, but important, extension of the Blech limit concept, which describes the EM immortality condition for a single segment wire, to more general multi-segment interconnect wires. The VBEM stress estimation method is based on the fundamental steady-state stress equations. This approach avoids computationally intensive numerical methods and can be implemented in CAD tools very easily, as we demonstrate on real design examples. The new immortality check method agrees very well with numerical methods. We also present an extension of this method to consider the significant current crowding effects and the conditions that proposed immortality check still work. Chapter 5 describes a new physics-based dynamic compact EM model, which for the first time can accurately predict the transient hydrostatic stress recovery effect in a confined metal wire. As a result, the evolution of preexisting void volume and the corresponding metal line resistance change can be further derived based on the stress evolution. The new dynamic EM model is based on the direct analytical solution of one-dimensional Korhonen’s equation with load driven by any unipolar or bipolar current waveforms under varying temperature. We show that the EM recovery effect can be quite significant even under unidirectional current loads. This recovery/healing process is sensitive to temperature, and higher temperatures lead to faster and more complete recovery. Such effect can be further exploited to extend the lifetime of the interconnect wires if the chip current or power can be properly regulated and managed. As a result, the new dynamic EM model

1.3 Chapter Outlook in Part I

9

can be incorporated with existing dynamic thermal/power/reliability management and optimization approaches, devoted to reliability-aware optimization at multiple system levels (chip/server/rack/data centers). Chapter 6 focuses on compact EM modeling and analysis technique for multisegment interconnect trees, which reflects practical VLSI interconnect architectures and interconnect layout-design techniques. We present several important works for this problem. First we present a closed form stress evolution expression for a three-terminal wire in confined interconnect wires. The work is based on the Laplace transform technique, which can give an exact analytical solution to the stress evolution equation for the void nucleation phase. The effects of different current densities and segment lengths on stress evolution have been observed from the proposed analytical model. This new model can also consider time-varying temperature based on the obtained exact series solution at constant temperature, which reflects a more practical chip working conditions especially for multi-core and emerging 3D ICs. On top of this, a more general analytical expressions are derived for a more general star-like interconnect wires. Then we present another closed form expressions for stress evolutions based on the integral transform technique for a straight multi-segment wire and extension of this work for a more general two-dimensional multi-segment wires. Chapter 7 presents a novel approach and techniques for physics-based EM assessment in power delivery networks of VLSI systems, which is based on the developed physics-based EM models in Chap. 2 and the EM-induced IR-drop degradation criterion that replaces the traditional conservative weakest segment method. Since both the temperature, which affects atom diffusivity, and the residual stress existing in each metal line before applying the electrical load are responsible for both void nucleation and growth, their distribution should be considered for accurate chip-scale EM assessment. Thus in the improved approach, we characterize the cross-layout temperature and thermal stress distributions by compact modeling and consider their impact on EM through physics-based EM models. Chapter 8 presents a new approach for system-level reliability management for multi/many core microprocessors. The electromigration (EM) induced time to failure (TTF) at the system level is modeled as a reliability resource, which is abstracted, from a recently proposed physics-based EM model, at the chip level. In this model, a single core can spend the TTF resources at different rates specified by the temperature and the related power consumption. The new resource-based EM model allows more flexible EM-reliability management for multi/manycore systems. As an application of the new model, we present a novel task migration method to explicitly balance consumption of EM resources for all the cores. The new method aims at equalizing the probability of failure of each core, which will maximize the lifetime of the whole multi/many core system. Chapter 9 presents a new lifetime optimization techniques for real-time embedded processors considering the electromigration-induced reliability. This chapter aims at maximizing the EM-induced reliability of the embedded processor subject to the hard timing constraints. System-level EM reliability model will be introduced. To optimize at the system-level, dynamic voltage frequency scaling (DVFS) is

10

1 Introduction

applied. To solve the resulting problem, two problem formulations and the corresponding solutions will be explored. First, we formulate the optimization problem as the continuous constrained nonlinear optimization problem using task’s mean time to failure as the variables, which is solved by the simulated annealing (SA) method. In the second formulation, the linearized resulting problem is solved by the mixed-integer linear programming (MILP) method to find the optimal solutions with regard to the proposed EM-induced reliability model and assumptions. Chapter 10 develops a new energy and lifetime optimization techniques for emerging dark silicon manycore microprocessors considering both long-term reliability effects (hard errors) and transient single event upset errors (soft errors). We employ both dynamic voltage and frequency scaling (DVFS) and dark silicon core state using on/off switching action as two control knobs. We develop our method based on these two optimization techniques for improving lifetime and reducing energy. To optimize EM-induced lifetime, we first apply the adaptive Q-learning based method, which is suitable for dynamic runtime operation as it can provide cost-effective yet good solutions. The second lifetime optimization approach is the mixed-integer linear programming method, which typically yields better solutions but at higher computational costs. Chapter 11 presents a new dynamic reliability management (DRM) techniques at the system level for emerging low power dark silicon manycore microprocessors operating in near-threshold region. We mainly consider the electromigration (EM) failures with recovery effects. To leverage the EM recovery effects, which was ignored in the past, at the system-level, we develop a new equivalent DC current model to consider recovery effects for general time-varying current waveforms so that existing compact EM model can be applied. The new recovery EM model can allow EM-induced lifetime to be better managed at the system level. Chapter 12 presents a new approach for cross-layer EM-induced reliability modeling and optimization at physics, system, and datacenter levels. We consider a recently proposed physics-based EM reliability model to predict the EM reliability of full-chip power grid networks for long-term failures. We show how the new physics-based dynamic EM model at the physics level can be abstracted at the system level and even at the datacenter level. Our datacenter system-level power model is based on the BigHouse simulator. To speed up the online optimization for energy in a datacenter, we develop a new combined datacenter power and reliability compact model using a learning based approach in which a feed-forward neural network is trained to predict energy and long term reliability for each processor under datacenter scheduling and workloads. To optimize the energy and reliability of a datacenter, we apply the efficient adaptive Q-learning-based reinforcement learning method. Throughout the book, numerical examples are provided to shed light on the developed algorithms and recommended implementations. However, we expect that the covered subjects and technical achievements expounded in this book can provide guidance and insights to CAD developers and practitioners to develop more advanced reliability-aware EDA tools and methodologies for coming sub 10 nm technologies and beyond.

References

11

References 1. H. Aydin, R. Melhem, D. Mosse, P. Mejia-Alvarez, Power-aware scheduling for periodic realtime tasks. IEEE Trans. Comput. 53(5), 584–600 (2004) 2. B. Bailey, Thermally challenged, in Semiconductor Engineering (Sperling Media Group LLC, 2013), pp. 1–8 3. J.R. Black, Electromigration-a brief survey and some recent results. IEEE Trans. Electron Devices 16(4), 338–347 (1969) 4. I.A. Blech, Electromigration in thin aluminum films on titanium nitride. J. Appl. Phys. 47(4), 1203–1208 (1976) 5. J.-J. Chen, T.-W. Kuo, Multiprocessor energy-efficient scheduling for real-time tasks with different power characteristics, in International Conference on Parallel Processing, 2005, ICPP 2005 (IEEE, Piscataway, 2005), pp. 13–20 6. J.-J. Chen, T.-W. Kuo, Procrastination determination for periodic real-time tasks in leakageaware dynamic voltage scaling systems, in IEEE/ACM International Conference on ComputerAided Design, 2007. ICCAD 2007 (IEEE, Piscataway, 2007), pp. 289–294 7. A. Das, R.A. Shafik, G.V. Merrett, B.M. Al-Hashimi, A. Kumar, B. Veeravalli, Reinforcement learning-based inter- and intra-application thermal optimization for lifetime improvement of multicore systems, in Proceedings of the 51st Annual Design Automation Conference, DAC ’14 (ACM, New York, 2014), pp. 170:1–170:6. http://doi.acm.org/10.1145/2593069.2593199 8. H. Esmaeilzadeh, E. Blem, R. St. Amant, K. Sankaralingam, D. Burger, Dark silicon and the end of multicore scaling, in Proceedings of the 38th Annual International Symposium on Computer Architecture, ISCA ’11 (ACM, New York, 2011), pp. 365–376 9. Exascale computing initiative update, 2012 United States, Department of Energy, 2012, https:// science.energy.gov/~/media/ascr/ascac/pdf/meetings/aug12/2012-ECI-ASCAC-v4.pdf 10. S. Feng, S. Gupta, A. Ansari, S. Mahlke, Maestro: orchestrating lifetime reliability in chip multiprocessors, in Proceedings of the 5th International Conference on High Performance Embedded Architectures and Compilers, HiPEAC’10 (Springer, Berlin, 2010), pp. 186–200. http://dx.doi.org/10.1007/978-3-642-11515-8_15 11. Y. Ge, Q. Qiu, Dynamic thermal management for multimedia applications using machine learning, in Proceedings of the 48th Design Automation Conference, DAC ’11 (ACM, New York, 2011), pp. 95–100. http://doi.acm.org/10.1145/2024724.2024746 12. J.N. Glosli, D.F. Richards, K.J. Caspersen, R.E. Rudd, J.A. Gunnels, F.H. Streitz, Extending stability beyond CPU millennium: a micron-scale atomistic simulation of Kelvin-Helmholtz instability, in Proceedings of the 2007 ACM/IEEE Conference on Supercomputing, SC ’07 (IEEE, Piscataway, 2007), pp. 1–11 13. M. Hauschildt, C. Hennesthal, G. Talut, O. Aubel, M. Gall, K.B. Yeap, E. Zschech, Electromigration early failure void nucleation and growth phenomena in Cu And Cu(Mn) interconnects, in IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2013), pp. 2C.1.1–2C.1.6 14. L. Huang, F. Yuan, Q. Xu, On task allocation and scheduling for lifetime extension of platformbased MPSoC designs. IEEE Trans. Parallel Distrib. Syst. 22(12), 2088–2099 (2011) 15. International technology roadmap for semiconductors (ITRS), 2014 update, 2014. http://public. itrs.net 16. E. Karl, D. Blaauw, D. Sylvester, T. Mudge, Reliability modeling and management in dynamic microprocessor-based systems, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2006), pp. 1057–1060 17. T. Kim, X. Huang, V.S. H.-B. CHen, S.X.-D. Tan, Learning-based dynamic reliability management for dark silicon processor considering EM effects, in Proceedings Design, Automation and Test in Europe (DATE) (IEEE, Piscataway, 2016) 18. J. Lienig, M. Thiele, Fundamentals of Electromigration-Aware Integrated Circuit Design (Springer, Berlin, 2018)

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19. J.R. Lloyd, New models for interconnect failure in advanced IC technology, in International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (IEEE, Piscataway, 2008), pp. 297–302 20. R. Melhem, D. Mosse, E. Elnozahy, The interplay of power management and fault recovery in real-time systems. IEEE Trans. Comput. 53(2), 217–231 (2004) 21. A.S. Oates, Strategies to ensure electromigration reliability of Cu/low-k interconnects at 10 nm. ECS J. Solid State Sci. Technol. 4(1), N3168–N3176 (2014) 22. A.S. Oates, M.H. Lin, The scaling of electromigration lifetimes, in IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2012), pp. 1–7 23. P. Pillai, K.G. Shin, Real-time dynamic voltage scaling for low-power embedded operating systems, in Proceedings of the Eighteenth ACM Symposium on Operating Systems Principles, SOSP ’01 (ACM, New York, 2001), pp. 89–102. http://doi.acm.org/10.1145/502034.502044 24. S. Saewong, R. Rajkumar, Practical voltage-scaling for fixed-priority RT-systems, in Proceedings of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (IEEE, Piscataway, 2003), pp. 106–114 25. C. Scordino, G. Lipari, A resource reservation algorithm for power-aware scheduling of periodic and aperiodic real-time tasks. IEEE Trans. Comput. 55(12), 1509–1522 (2006) 26. H. Shen, J. Lu, Q. Qiu, Learning based DVFS for simultaneous temperature, performance and energy management, in 2012 13th International Symposium on Quality Electronic Design (ISQED) (IEEE, Piscataway, 2012), pp. 747–754 27. T. Simunic, K. Mihic, G. Micheli, Optimization of Reliability and Power Consumption in Systems on a Chip. Lecture Notes in Computer Science, vol. 3728 (Springer, Berlin, 2005) 28. J. Srinivasan, S. Adve, P. Bose, J. Rivers, Ramp: a model for reliability aware microprocessor design. IBM Research Report, 2003 29. J. Srinivasan, S.V. Adve, P. Bose, J.A. Rivers, The case for lifetime reliability-aware microprocessors, in Proceedings of the 31st Annual International Symposium on Computer Architecture (IEEE, Piscataway, 2004), pp. 276–287 30. R.M. Swanson, J.D. Meindl, Ion-implanted complementary MOS transistors in low-voltage circuits. IEEE J. Solid State Circuits 7(2), 146–153 (1972) 31. Y. Tan, W. Liu, Q. Qiu, Adaptive power management using reinforcement learning, in Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD ’09 (ACM, New York, 2009), pp. 461–467. http://doi.acm.org/10.1145/1687399.1687486 32. O. Unsal, I. Koren, C. Krishna, Towards energy-aware software-based fault tolerance in realtime systems, in Proceedings of the 2002 International Symposium on Low Power Electronics and Design, ISLPED ’02 (IEEE, Piscataway, 2002), pp. 124–129 33. R. Ye, Q. Xu, Learning-based power management for multi-core processors via idle period manipulation, in 2012 17th Asia and South Pacific Design Automation Conference (ASP-DAC) (IEEE, Piscataway, 2012), pp. 115–120

Chapter 2

Physics-Based EM Modeling

2.1 Introduction In the chapter, we review some of the recent advances in EM modeling and assessment techniques. Specifically, we first reviews the EM physics and existing EM failure models and discusses limitations of those models. Then we reviews the mainstream stress-based modeling of EM failure kinetics and the important Korhonen’s partial differential equation for void forming and void growth in the confined metal interconnect wires. We present the recently proposed compact two-phase EM models. We then show the limitations of such two-phase EM models. First, the proposed nucleation time formula does not predict correctly the current exponent, which should be around 2 based on experimentally observed results. To mitigate this problem, we present the three-phase EM models, which consists of “void nucleation phase,” “void incubation phase,” and “void growth phase.” We give a more accurate compact formula for nucleation time estimation and show the compact models for determining the nucleation, incubation time and failure time for the three phases. More importantly the three- phase EM model can predict the wire resistance change patterns, which is more consistent with the experimentally observed data. On top of this, we further show the extension of this work to the multi-segment interconnect wires and show the fast saturation volume estimation method for multi-segment interconnects, which is critical for the time to failure analysis of EM failure.

2.2 Electromigration Fundamentals Electromigration (EM) is a physical phenomenon of the oriented migration of metal (Cu) atoms along a direction of applied electrical field due to the momentum exchange between atoms and the conducting electrons. Atoms (either lattice atoms

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_2

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2 Physics-Based EM Modeling

Fig. 2.1 The 3D view of the confined Cu damascene structure with barrier and capping layers [60]

or impurities) migrate toward the anode end of the metal wire along the trajectory of conducting electrons. This oriented atomic flow results in metal density depletion at the cathode, and a corresponding metal accumulation at the anode end of the metal wire. This depletion and accumulation occur because atoms cannot easily escape the metal volume as the metal wires are confined by the so-called diffusion barriers. A Cu damascene interconnect wire typically is confined or embedded by metallic barriers such as Ta and capped with either a dielectric (such as SiN) or a metallic layer (CoWP) as shown in Fig. 2.1. As a result, the wire volume changes, which is induced by the atom depletion and accumulation due to migration leading to build-up of hydrostatic stresses across the conductor resulting in tension at the cathode end and compression at the anode end of the wire [35, 52, 53]. Over time, the continuous unidirectional current flow increases these stresses, as well as the stress gradient along the metal line. The stress gradient actually serves as the back-force to reduce the EM-induced metal migration flow. In some cases, usually when a wire is long or current is large, this stress can reach critical levels, resulting in a void nucleation at the cathode and/or hillock formation at the anode end of wire as shown in Fig. 2.2. Voids are typically formed when existing cohesive or inter-facial micro-cracks near, or at, the barrier/Cu interfaces develop into a void by action of the appropriate stresses. On the other hand, a hillock is formed by compression-induced extrusion of metal into the surrounding dielectric which can cause a shortage between neighboring metal wires. EM can degrade both global interconnects such as power grid networks and signal wires when the current densities are sufficiently high (about 1 MA/cm2 ). However, the power grid networks are more susceptible to EM effects due to the conduction of unidirectional currents. The currently employed method of predicting the time to failure is based on the approximate statistical Black’s equation [4]. MTTF = Aj −n exp{Ea /kB T }

(2.2.1)

2.2 Electromigration Fundamentals

15

Fig. 2.2 The stress development and distribution in EM, [10]

However, calculating the MTTF of individual branches characterized by known current densities and temperatures is the subject of growing criticism. Here, j is the current density, kB is the Boltzmann’s constant; T is the absolute temperature; Ea is the EM activation energy. The symbol A is a constant, which depends on a number of factors, including grain size, line structure and geometry, test conditions, current density, thermal history, etc. Here current exponent n was found to be 2 by James Black. Typically, the values n and Ea are obtained at the highly stressed testing condition, then we can use them to extrapolate the MTTF at the use condition by using the following equation:  MTTFuse = MTTFstress

jstress juse

n

 exp

Ea kB



1 Tuse

−

1 Tstress

 (2.2.2)

where MTTFstress and MTTFuse are MTTF for the testing stress and normal use conditions, respectively. However, it is today’s common understanding that n is actually not constant over different stressing conditions (different current densities and temperatures), and its value has been highly debated in the past [18, 37, 43, 59]. As a result, Black’s equation does not scale very well over a wide range of current densities. On the other hand, the Blech limit or Blech product [5] (j × L) ≤ (j × L)crit =

σcrit eZρ

(2.2.3)

is used for the filtering out of immortal branches, which can only be applied to a single wire branch. Here, L is the wire branch length,  is the atomic volume; e is the electron charge, eZ is the effective charge of the migrating atoms, ρ is the wire electrical resistivity, σcrit is the critical stress needed for void or hillock formation as a precursor to failure. The immortality condition of Eq. (2.2.3) means that the atomic flux, generated by stress gradient in the metal lines characterized

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2 Physics-Based EM Modeling

Fig. 2.3 Interconnect tree confined by diffusion barriers/liners [58]

by (j × L) ≤ (j × L)crit , compensates the atomic flux caused by electrical current density. It should be mentioned that the Blech limit is valid only for a single wire segment or branch within the diffusion blocking boundaries. It does not work for multi-segment interconnect trees, which are commonly used in practical VLSI layouts. An interconnect tree wire is defined as continuously connected metal (copper or aluminum) within one layer of metallization. These trees are terminated by diffusion barriers at vias and contacts and can have more than one terminating segment, as shown in Fig. 2.3. Existing EM modeling and analysis techniques mainly focus on the simple straight line interconnect with two line-end terminals. However, a practical integrated circuit layout often has interconnects such as clock and power grid networks containing many such interconnect tree wires. The EM effects in the segments of a wire are not independent and they have to be considered simultaneously. To mitigate those mentioned problems, some physics-based EM analysis methods for the TSV and power grid networks have been proposed recently based on solving the basic mass transport equations [44, 45, 47, 65]. However, the proposed method can have immediate resistance change for a wire once current is applied to the wire as the atomic or vacancy concentration will change right away. However, such EM modeling does not fully reflect the real EM physics as EM failure is mainly caused by the growing hydrostatic stresses. The resistance change will not occur right away until the stresses reach to a critical value (the critical stresses) to have the void nucleation (wire resistance start to change) and then start void growth phase. It also fails to predict the immortal wires when the current density or wire width is small as shown in Blech’s equation (2.2.3). Furthermore, since these proposed methods solve the basic mass transport equations using the finite element method, they can only solve for very small structures such as one TSV structure. As a result, a complicated look-up table has to be built for different TSVs and wire segments for full-chip power grid analysis at reduced accuracy. Alternatively, a number of physics-based EM compact models have been proposed recently where void nucleation and void evolution are explicitly characterized, which is responsible for time-dependent resistance degradation of interconnect wires, which mitigates the major flaws in the Black–Blech models [21, 54]. In the new approach, the EM process is characterized in two phases: void nucleation and a subsequent void growth. In the void nucleation phase, void nucleation time (tnuc ) is determined as an instant in time when stress at the cathode end of the line,

2.3 Stress-Based EM Modeling and Stress Diffusion Equations

17

characterized by the biggest tensile stress, reaches the critical stress [21]. In the void growth phase, the void starts to grow its volume at a velocity that is a function of temperature and its current density, which will lead to the resistance increase with time. In the following sections, we will give more detailed presentations for the proposed physics-based EM models.

2.3 Stress-Based EM Modeling and Stress Diffusion Equations In addition to the Black and Blech equations, which are semi-physics- based EM models supported by early experimental results, many more physics models of electromigration phenomenon have been developed for new interconnect wiring structures. In this section, we present the most well-developed stress evolutionbased EM models characterized by the Korhonen’s equation first. Then we will present recently developed physics-based EM models and the new three-phase EM model, which is more consistent with the measured results for Cu damascene interconnect wires.

2.3.1 EM-Induced Material Transport Equation Blech first observed in his experiments that the end of strips which carries current flow will drift with the following velocity, which is also the Nernst–Einstein equation [5, 59]: vd = Da

Fem eZρj = Da kB T kB T

(2.3.1)

where Fem can be viewed as the EM-induced force due to the electronic wind. Da   is the atomic diffusion coefficient, which is given by Da = D0 exp − kEBaT , where D0 is the diffusion coefficient and Ea is the EM activation energy. The flux of metal atoms during the EM mainly consists of two major forces, one is the electron windinduced force, Fem and the second one back-force due to the atomic concentration changes (or the stress gradients due to the depletion of atoms at the cathode end and the accumulation of the atoms at the anode end) [12, 51]. Since the atomic migration occurs via a vacancy exchange mechanism, the material transport can be described in terms of a vacancy flux as follows: [11] Jv = −Dv ∇ · Cv + Cv

eZρj kB T

  eZρj = −Dv ∇ · Cv − Cv kB T

(2.3.2)

18

2 Physics-Based EM Modeling

where Dv is the vacancy diffusivity, Cv is the vacancy concentration. We assume that Da = Dv . Note that we ignore the transient force in (2.3.2) due to temperature gradients as EM is a long-term effect and transient temperature has marginal impacts on it. When the divergence occurs in vacancy flux due to the different diffusivities around metal grain boundaries, or pre-existing micro-cracks near or at the barrier(capping)/Cu interfaces, vacancies or metal atoms will accumulate or vanish, and in some cases void or hillocks can be formed as well. The vacancy continuity equation can be written as [15] ∂Cv = −∇ · Jv + G ∂t

(2.3.3)

where G represents a generation and annihilation term. Equation (2.3.3) presents the fundamental EM-induced material diffusion equation.

2.3.2 One-Dimensional Stress Evolution Model To simplify our presentation, we only consider the one-dimensional case as shown in Fig. 2.4. We consider a single wire segment with length L, the electronic flux direction, and current density j (which is opposite to the electronic flux direction) as shown in Fig. 2.4 as well. As a result, the node 0 is the cathode node and node L is the anode node and the defined positive direction is the x direction. As a result, we notice that current density j is negative in this case. One important observation is that in today’s interconnect wires, such as Cu damascene structures, the metal wires are confined by barriers or capping layers, thus metal wire volume can’t be changed as a result of the atomic/vacancy concentration changes. It follows then, that hydrostatic stress/strain will be developed in the metal Fig. 2.4 A two-terminal wire with the electron flow and current flow indicated by the arrow

2.3 Stress-Based EM Modeling and Stress Diffusion Equations

19

wires. Instead of using the vacancy concentration, Cv , as the variables in (2.3.3), using the hydrostatic stress σ inside wires as the variables is more convenient as stress is directly related to the EM failure damage forming process (such as the critical stress concept). Korhonen et al. [34] developed the simplified stress diffusion-based EM models. Specifically, they show that the concentration of lattice sites (grain boundary dislocation) changes dCL /CL will lead to the stress increments due to Hooke’s law: dCL dσ =− CL B where B is applicable modulus. Notice that G = −

(2.3.4) ∂CL ∂t

in (2.3.3) [13], we have

∂Jv ∂Cv CL ∂σ = + ∂x ∂t B ∂t

(2.3.5)

Assume that vacancy concentration in equilibrium is related with the mechanical stress as follows [15],  Cv = Cv0 exp

σ kB T

 (2.3.6)

As a result, we have ∂Cv  ∂σ ∂Cv  ∂σ = Cv ; = Cv , ∂t kB T ∂t ∂x kB T ∂x

(2.3.7)

With (2.3.7), (2.3.5) becomes ∂Jv ∂σ − = ∂x ∂t



Cv  ∂σ CL + kB T ∂t B

 (2.3.8)

If we substitute Jv defined in (2.3.2) into (2.3.8) with information from (2.3.7), we have the following hydrostatic stress diffusion equation in partial differential form: ∂σ ∂t



Cv  CL + kB T B



    ∂σ eZρj ∂ − = D v Cv ∂x kB T ∂x kB T

(2.3.9)

Korhonen noticed that (CV /CL )(B/kB T )  1 and CL = 1/ and Da = Dv Cv /CL [15, 34], he obtained the Korhonen’s equation: ∂ ∂σ = ∂t ∂x =

∂ ∂x

 

Da B kB T Da B kB T







∂σ − eZρj ∂x



∂σ + eZρ|j | ∂x



(2.3.10)  (2.3.11)

20

2 Physics-Based EM Modeling

Notice that the value of current density j here is negative given the x-axis directions definition in Fig. 2.4. If we treat the current density j as an absolute value variable, then the sign of eZρj term will be positive, which is in consistent with the equation in the Korhonen’s original paper [34]. In the rest of this book, for the sake of presentation, we will treat the current density j as an absolute value variable without using |j |. Korhonen’s equation completely describes how the hydrostatic stress develops in confined metal wires with material flux blocked at the barrier terminals such as vias. It can be applied to a single wire in one-dimensional case as shown in Fig. 2.4 and multi-segment wires in two-dimensional cases, which will be discussed in the sequel soon. Figure 2.5 shows stress evolution for a single wire line over time obtained from the Korhonen’s equation. The steady state will be reached when the backward flux compensates the current-induced flux, and the stress will be linearly distributed along the wire. Figure 2.5a shows the stress evolution along the wire (with the left end as the cathode node and right as the anode node). This is a typical hydrostatic stress evolution pattern driven by DC current. Figure 2.5b shows the evolution of the electric current-induced hydrostatic stress at the cathode end of a metal wire (biggest tensile stress) under different DC densities and temperatures. It indicates that both the current density and the temperature affect the stress evolution rate. Table 2.1 shows the parameters used for the simulation from Fig. 2.5. For Korhonen’s equation, if we consider a simple line wire of length l with the blocking boundary conditions at the two blocked ends located at x = 0 and L and constant initial condition: 600

700 σcrit

200

600 500

t

stress (MPa)

stress (MPa)

400

0

t

-200

400 300 3×10 9A/m 2, 370K 4×10 9A/m 2, 370K 3×10 9A/m 2, 380K 4×10 9A/m 2, 380K

200

-400

100 -600

0

20

40 60 x (μm)

80

100

0

0

2

4

6 time (s)

(a)

8

10 ×10 4

(b)

Fig. 2.5 Evolution of hydrostatic stress along the wire, (a), and at the cathode end, (b), over time stressed under different current densities and temperatures, in the case of zero initial stress [25]

2.4 Modeling for Transient EM Effects and Initial Stress Conditions

21

Table 2.1 Parameters and typical values used [25] Parameter Ea Z σcrit L kB

PDE :

Value 0.86 eV 10 400 MPa 1 × 10−4 m 1.38 × 10−23 m2 kg s−2 K−1

Parameter B  ρ D0

Value 1 × 1011 Pa 1.66 × 10−29 m3 3 × 10−8  7.56 × 10−5 m2 /s

   ∂σ (x, t) ∂ ∂σ (x, t) = + G , 0 ≤ x ≤ L, t > 0 κ ∂t ∂x ∂x

∂σ (0, t) = −G, ∂x ∂σ (L, t) BC : = −G, ∂x

BC :

t >0

(2.3.12)

t >0

IC : σ (x, 0) = σT Here, “PDE” is for the “partial differential equation.” G is defined as G = eZρj  >0 for constant absolute value current density j , and κ = Da B/kT . Notice that the (0,t) (L,t) value of ∂σ∂x and ∂σ ∂x are all negative given the x-axis direction definition in Fig. 2.4. σT is the thermal stress developed in the metal line during cooling from the zero stress temperature TZS down to the temperature of use condition. Using the separation of variable method, the exact analytical solution of this initial-boundary value problem for the stress evolution in a finite wire segment can be found as ⎡ 1 x σ (t) = σT + GL ⎣ − − 4 2 L

n=0

(2n+1)π x L (2n + 1)2 π 2

∞ cos



⎤ e

−κ

(2n+1)2 π 2 t L2

⎦

(2.3.13)

Notice that the exact solution consists of infinite number of terms. Our study shows that only a few dominant terms are actually needed for practical problems. If we just keep the first item, then we can solve for the nucleation time when we know the so-called critical stress value as we show in the later sections.

2.4 Modeling for Transient EM Effects and Initial Stress Conditions For practical chip working environments, the current and temperatures are no longer constant and we have time-varying stressing current. Furthermore, the dual damascene copper wires may also have non-zero initial stress due to thermal

22

2 Physics-Based EM Modeling

Fig. 2.6 Stress evolution caused by actual currents and traditional effective DC current [32]

6

×108 Critical stress

Stress (Pa)

5 4 3 2

real stress traditional DC equvilent stress

1 0

0

2

4

6

8

10

Normalized Time

mechanical effects during the fabrication process. The EM failure effects (like other long-term reliability effects)have the so-called recovery effects when the wire is stressed with time- varying current densities, which was shown in Fig. 2.6. Analytical solution for 1-D Korhonen’s equation considering time-varying current: For a single wire case, if we treat the current density j (t) as the timevarying function, and assume that initial constant stress condition, i.e.    ∂σ (x, t) ∂ ∂σ (x, t) = + G(t) , 0 ≤ x ≤ L, t > 0 κ PDE : ∂t ∂x ∂x ∂σ (0, t) = −G(t), ∂x ∂σ (L, t) BC : = −G(t), ∂x BC :

IC : σ (x, 0) = σT

t >0

(2.4.1)

t >0

0≤x≤L

where G(t) is defined as G(t) =

eZρj (t) 

(2.4.2)

Using the Laplace transformation method, we have the following analytical solution for the stress in the single wire with time-varying current [25, 26, 55], 4 σ (x, t) = σT + κ L

 t ∞  (2n − 1)π x (2n−1)22 π 2 κ(τ −t) L cos e G(τ ) dτ L 0 n=1

(2.4.3)

2.4 Modeling for Transient EM Effects and Initial Stress Conditions

23

Notice that n starts from 1 here and we use 2n − 1 in the solution. Solution (2.4.3) is valid for any arbitrary time-varying current waveform j (t). It can be shown that (2.4.3) converts to the standard stress evolution kinetics (2.3.12) if the current density is constant (DC current). More importantly, as we can see, the time-varying current will lead the EM recovery effects when the current density decreases or even becomes zero, the stress will start to go down as well. The recovery effects will be explained in more detail in Chap. 5. Analytical solution for 1-D Korhonen’s equation considering both timevarying current and non-constant initial stress: For many dual damascene copper wires and through silicon vias (TSV), study shows that the thermo-mechanical stress can be quite significant [46], which means that we have the following non-constant initial condition to consider: σ (x, 0) = g(x). As a result, the initial stress is function of distance x in general. Then the Korhonen’s equation, the boundary conditions, and initial stress conditions of σ (x, t) can be expressed in the following partial differential equation (PDE) form: PDE :

   ∂σ (x, t) ∂σ (x, t) ∂ = + G(t) , 0 ≤ x ≤ L, t > 0 κ ∂t ∂x ∂x

∂σ (0, t) = −G(t), ∂x ∂σ (L, t) BC : = −G(t), ∂x BC :

IC : σ (x, 0) = g(x),

t >0

(2.4.4)

t >0 0≤x≤L

Using the Laplace transformation method, it can be shown that the resulting Korhonen’s equation can still be solved exactly as follows [61]: σ (x, t) = +

2 L

∞  L



cos

0

n=1

nπ x nπ ξ − n2 π2 2 κt cos e L g(ξ ) dξ L L

 ∞  (2n − 1)π x (2n−1)22 π 2 κ(τ −t) 4 t L cos e G(τ ) dτ +κ L 0 L

(2.4.5)

n=1

The first summation series stand for the response from the position-related initial condition, and the second summation series stand for the response from the boundary conditions. Since this function can take care arbitrary distributed initial stress and time- varying current density, it is suitable for more accurate EM analysis for nucleation phase considering the layout dependence.

24

2 Physics-Based EM Modeling

2.5 Post-voiding Stress and Void Volume Evolution In this subsection, we discuss the post-voiding stress and void volume evolution which is the initial boundary value problem (IBVP) of Eq. (2.3.10). We assume that the time is counted from the moment when the void was nucleated tnuc . Void is nucleated at the cathode edge of line: x = 0. Effective thickness of the void interface δ in introduced, which is infinitely small in comparison with all other involved length. It allows us to introduce a stress gradient between the zero stress void surface and the surrounding metal as ∇σ = σ (δ, t)/δ, where σ (δ, t) ≈ σ (0, t) is the time-dependent stress in the metal near the void surface. Thus, the considered IBVP can be written as [56]:    ⎧ ∂σ (x, t) ∂σ (x, t) ∂ ⎪ ⎪ PDE : = + G(t) ; 0 ≤ x ≤ L, t > 0 κ ⎪ ⎪ ∂t ∂x ∂x ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ σ (0, t) ∂σ ⎪ ⎪ (0, t) = ;t > 0 BC : ⎪ ⎪ ∂x δ ⎪ ⎪ ⎪ ⎪ ⎨ ∂σ BC : (L, t) = −G(t); t > 0 ∂x ⎪ ⎪ ⎪ ⎪ G L ⎪ ⎪ ⎪ IC : σ (x, 0) = σT − Gnuc x + nuc − ⎪ ⎪ 2 ⎪ ⎪ ⎪   ⎪ 2  ∞ (2n+1)π x ⎪ ⎪ √ cos (2n + 1)π ⎪ L ⎪ exp − κ t ⎪ ⎩ 4GL L π 2 (2n + 1)2

(2.5.1)

n=0

where κ = Da B/kB T , Gnuc = eZρjnuc / . We assume that the current density in the nucleation phase, jnuc is constant. Figure 2.7 shows stress evolution in the same wire for the growth phase. It was shown that if the current density in the growth phase or G(t) is constant, then the analytical solution can still be found [56]. In general, it is difficult to solve this equation analytically and numerical solutions such 5 0

Stress(in 100MPa)

Fig. 2.7 EM-stress distribution change over time in simple metal wire for void growth [14]

-5 -10 -15 time=0.0005 time=0.01 time=0.04 time=0.1 time=0.2 time=1

-20 -25 -30

0

0.2

0.4

0.6

Scaled Distance

0.8

1

2.6 Compact Physics-Based EM Model for a Single Wire

25

as finite element or finite difference methods are needed, which will be discussed in the later chapters. After a void is nucleated, the stress around the void becomes zero and a large stress gradient is generated in the vicinity as mentioned before. This gradient pushes the copper material flux to the anode so that a back-force due to stress gradient will be built until the stress reaches steady state (the void growth will saturate in this case) as shown in this figure.

2.6 Compact Physics-Based EM Model for a Single Wire In this section, we present the compact physics-based EM models and time to failure assessment methods for a single wire based on the stress-based EM modeling techniques developed in Sect. 2.3.

2.6.1 Physics-Based Two-Phase EM Model As mentioned earlier in Sect. 2.2, the EM failure process consists of two important phases: the void nucleation phase and void growth phase. When current is applied to a wire, stress starts to build up in the wire based on Korhonen’s equation. Void Nucleation Phase At the cathode end of line (where x = 0), the tensile stress will start to increase over time. When the tensile stress reaches the critical stress σcrit , the void will be nucleated. To determine the nucleation time tnuc , one can take the first term, which is assumed to be dominant term, to solve for tnuc (2.3.13) [21, 24] tnuc

 L2 k B T ln ≈ 2Da B σT +

eZρj L 2 eZρj L 2 − σcrit

 (2.6.1)

Void Growth Phase For the void growth phase, which follows the nucleation phase, voids are formed at tnuc and grow at t > tnuc . In this phase, the wire resistance may start to increase over the time. The void growth phase can also be described by the Korhonen’s equation with different boundary conditions. In the following, we present a simple void growth model. Since the drift velocity of the void edge relates to atomic flux as shown in (2.3.1). A confined Cu wire structure with the marked width and length and height is shown in Fig. 2.8, where the Cu wire is confined by the highly resistive barrier layer (such as Na/TaN) with a capping layer (such as SiN) (which is typically dielectric with very high resistance, so its resistance can be ignored) at the top.

26

2 Physics-Based EM Modeling

Fig. 2.8 The structure of a confined Cu damascene wire [60]

The wire resistance change can be approximately described as [22]:  r(t) = vd (t − tnuc )

ρTa ρCu − hTa (2H + W ) H W

(2.6.2)

Here, ρTa and ρCu are the resistivity of the barrier material (Ta/TaN) and copper, W is the line width, H is the copper thickness, and hTa is the barrier layer thickness. The evolution of void growth and wire resistance is a pretty complicated process due to many failure mechanisms. Actually, void nucleation is a necessary condition for wire resistance changes, not a sufficient condition, as the void growth may stop (saturate) before the void volume can lead to significant wire resistance change. During the void growth process, the stress gradient will produce a backflow atomic drift velocity, vb , so the total drift velocity, dt , is given by [17]   σ  Da vt = vd − vb = jρeZ − L kB T

(2.6.3)

where σ is the back-flow stress and L is the wire length. Once the wire-stress gradient balances the EM driving force (i.e. vt = 0), metal atom depletion will stop. Korhonen et al. derives the maximum void volume in the one-dimensional case, Vmax [34] as Vmax =

σT L jρeZL2 + B 2B

(2.6.4)

where σT is the initial thermal stress. In addition, EM failure due to void-induce damage, void nucleation locations is statistically correlated to the electronic flow direction. As a result, there is so-called EM early failure or EM late failure of the wire [3]. Early failure typically occurs in via-to-via structure as shown in Fig. 2.9a, when the void forms in a via-above line (the void is also called slit-voids) and reaches critical size [20, 64], which equals to via’s diameter, the via is blocked by the void and thus electronic connection to the upper layer is also blocked (capping layer is fabricated with dielectrics such as Si3 N4 which does not shunt current flow). Late failure typically occurs in the so-called via-below structure as shown in Fig. 2.9b, when the void typically forms in a via-below line (the void is also called trench voids) and reaches critical size, current can still go through the barrier layer (barrier layer is fabricated with Ta whose resistivity is much higher than Cu) and resistance will increase over time.

2.6 Compact Physics-Based EM Model for a Single Wire

27

Fig. 2.9 Side-view of void formation: (a) void in a via-above line (early failure mode); (b) void in a via-below line (later failure mode) [60] 2.3

2.2

n

2.1

2

1.9

1.8

0

1

2

3

j

4 ×1010

Fig. 2.10 Current exponent n fitting for Korhonen’s equation [60]

However, statistically early failure can occur in via-below structure and late failure can occur in via-up structure. Although the void can grow at these positions, the possibility is very low.

2.6.2 Physics-Based Three-Phase EM Models The proposed two-phase EM models mentioned earlier still cannot completely describe the many observed wire resistance change behaviors from EM failure processes. Furthermore, we show in the section that the current density impacts on the stress developments is not consistent with the Korhonen’s equation.

2.6.2.1

What the Current Exponent n Should Be?

First, we show that the current exponent n computed by the Korhonen [34] is actually closer to 2, which is consistent with the measured data. Figure 2.10 shows

28

2 Physics-Based EM Modeling

the current exponent n from the numerical analysis results using COMSOL under different current densities. We found that this shows n is actually around 2 for different current densities. On the other hand, the compact EM models predicted by (2.6.1) gives different n values over current densities as shown in Fig. 2.10. In the past, some theoretical studies have been done to obtain the current exponent for different proposed EM models. In the work [51], the author derived the formula from Clement’s equation [11]. In their model, they claim n equals 2 for semi-infinite lines. However, there exists no theoretical results for n based on Korhonen’s equation in short lines, with blocked atom flux boundary conditions at both ends, which is the problem we face here. We performed analysis on a simple confined wire for a number of simulations for different current densities by solving Korhonen’s equations using COMSOL which we then use to compute n, which is plotted in Fig. 2.10. We found that this shows n is actually around 2 for different current densities. That means the nucleation time model from the compact EM model [22] is not very scalable over different current densities. To mitigate this problem, we start with the original exact solution of Korhonen’s equation (2.3.13), which is repeated below: 

⎫ ⎧ ∞ cos (2n+1)π x (2n+1)2 π 2 ⎬ L x eZρj L ⎨ 1 −κ t L2 σ = σT + − −4 e ⎭  ⎩2 L (2n + 1)2 π 2

(2.6.5)

n=0

Now we take the first term from (2.6.5) and then solve for the time when the stress reaches the critical stress σcrit , we have tnuc

  eZρL L2 k B T 2 j ln ≈ 2Da B σT + eZρL 2 j − σcrit   L2 k B T 1 = ln 2Da B 1−α

(2.6.6)

L where α = σcritβ−σT and β = eZρj 2 and σT is the pre-existing thermal-induced residual stress. To mitigate this problem, one way is just to keep the second order terms for the current density related term, which can be obtained by performing the Taylor’s expansion on (2.6.1).  1  Now if we perform the Taylor expansion on the ln 1−α , we have

tnuc

  α3 α2 L2 k B T + + ··· α+ = 2Da B 2 3

(2.6.7)

 From this expression, we can see that since α(j ) ∼ f j1 , when current density is increasing, α(j ) goes smaller, the current exponent n will approach 1 as the linear

2.6 Compact Physics-Based EM Model for a Single Wire Fig. 2.11 Compare tnuc in proposed model and COMSOL result [60]

29

10 COMSOL Result Traditional model Proposed model

ln(M T T F )

9 8 7 6 5 4

0

1

2

j

3

4 ×1010

term α(j ) dominates. To mitigate this problem, we propose to keep only the α 2 term in (2.6.7), in this way, the current exponent n will be constant 2 between tnuc and current density j : tnuc ≈

L2 k B T 2Da B



γ α2 2

 =γ

kB T (σcrit − σT )2 Da B(eZρj )2

(2.6.8)

L where α = σcritβ−σT and β = eZρj 2 and γ is a fitting parameter, which can be obtained by fitting with measured or computed results. If we do not consider the initial stress, (2.6.8) will become:

tnuc ≈ γ

kB T (σcrit )2 Da B(eZρj )2

(2.6.9)

Figure 2.11 shows the compared result between our proposed model and the simulation result for one single wire. In our study, we found that γ is around 0.78. As can be seen, this model is much closer to Korhonen’s equation compared with the model in [22]. We remark that Korhonen actually showed that for a semi-infinite wire line with one end blocked, the nucleation time at the cathode node (with the largest tensile stress) is [34]: tnuc ≈

π kB T (σcrit )2 4 Da B(eZρj )2

(2.6.10)

As we can see, in this case, γ = π4 = 0.7853, which is almost the same value we obtained. This means that the semi-infinite wire nucleation model also works well for the finite-length wire blocked at both ends if the wire is sufficient long, which was also observed and studied in [40]. In this work, the authors showed that if wire

30

2 Physics-Based EM Modeling

length is larger than 100 µm, then solutions of the finite wire and semi-finite wires will closely match as far as the reasonable lifetime (such as 10 years) is concerned.

2.6.2.2

The New Three-Phase EM Model

As mentioned above, the EM failure process in general can be viewed as two phases: the nucleation phase, in which void is generated after critical stress is reached, and the growth phase, in which void starts to grow. Existing compact EM models are also versed in terms of the two phases, and each phase is described by time to failure as a function of current density and other parameters [23, 37]. However, such a simple EM model ignores the fact that when the void is nucleated or formed, it will not change the wire resistance immediately. It is observed experimentally that there exists the so-called critical void size [20, 64], which is typically the via size diameter or height or width of interconnect wires. Since the conductivity of Cu is much higher than the barrier layers, the resistance of wire does not change even there is a small void until the void grows into a point where its volume equals or becomes larger than the cross section of the via or wire. Then all the current will starts to flow over the very thin barrier layer, which will lead to very higher current density and the resulted joule heating. The joule heating in turn will lead to small resistance jump, which indicated end of such period. Figure 2.12b shows the experimentally measured resistance change over time. The small resistance jumps are obviously visible. Also, sometimes the barrier layers are not very stable due to the manufacturing process variations, causing the barrier layer to very quickly burn out completely once entire current flows through it. This will lead to an open circuit very quick as is shown in Fig. 2.12b [64]. As a result, we present more general physics-based three-phase EM model shown in Fig. 2.12a [61]. In this model, there are three phases: (1) nucleation phase from t = 0 to tnuc ; (2) the incubation phase from tnuc to the ti ; then (3) growth phase

Fig. 2.12 (a) The three-phase EM model and the resulting resistance change over time [60]. (b) Measured resistance change, Courtesy of [64]

2.6 Compact Physics-Based EM Model for a Single Wire

31

starting from ti to t50 , t50 indicates the time to failure in statistical term (50% samples fail). In the following, we give the description of each phase. 1. Nucleation phase: this is defined as time period from t = 0 (when the wire is stressed at t = 0) to tnuc . In this phase, a void is not formed until time tnuc . That means the resistance does not increase. The stress can be modeled by Korhonen’s equation, and the nucleation time can be estimated using the proposed new nucleation model in (2.6.8). 2. Incubation phase: this is defined as time period from tnuc to the ti . In this phase, the void is nucleated, but its size is not significant and the void does not cover the cross section of via or the wire. Hence the resistance will remain almost the same. To model the incubation phase, we notice, the void growth rate vd is given by the mobility (Da /kB T ) times the electromigration driving force, which Fe = eZE = eZρj , then we have [20] vd =

Da Da Fe = eZρj kB T kB T

(2.6.11)

Then the incubation time(ti − tnuc ) can be expressed as: ti − tnuc =

Lcrit vd

(2.6.12)

Here Lcrit is length of critical void size. It is noted that in this phase, since the approximated drift velocity v is proportional to current density j and the ti − tnuc is related to j −1 . We note that the incubation period defined in (2.6.12) better reflects the technology scaling impacts on EM, which predicts that lifetime of wires are reduced by half by each technology generation, characterized by the feature sizes, which is closely related to minimum via or wire sizes [19, 20, 27]. As a result, the new EM model is also scalable and predictable for technology scaling in addition to scalability in stressing current density. 3. Growth phase: this is defined as time period from ti to t50 . Aft the beginning of growth phase, the void reaches the critical void size and blocks the cross section above the via. Then the current starts to flow over the liner or barrier layers with much higher current density. As a result, the current density at the liner part can be much higher than other part of copper. Since resistivity of the liner is much larger than copper and this liner is very thin, current density and resistance on the linear can be very high. The high current density and higher resistance will lead to significant joule heating. It is observed that the temperature increase due to joule heating can be 5–15 ◦ C [50], which will also lead to the wire resistance jump at the beginning of this phase we discussed. After this jump, the resistance will increase linearly. For a combined Cu wire with liner such as Ta surrounding the three sides of the wire, using the same the drift velocity (vd ), the resistance change over time can be computed as [21] in Eq. (2.6.2)

32

2 Physics-Based EM Modeling

To illustrate the three-phase EM mode, we compute the resistance changes for the three phases over time. The results are shown in Fig. 2.13. As can be seen, after a period of time, the void is nucleated at 3800. At that time the resistance does not increase. When the void reaches the critical size, there is a resistance jump due to the joule heating at around 9800. Then the temperature increases 10 ◦ C and the resistance jump is 3.86%. When the cross section is blocked by void, the resistance begins to increase linearly. When the resistance is larger than 10% of the total resistance, the wire is considered failed. Another important observation is that the proposed three-phase EM model leads to more accurate time to failure prediction over different current densities compared with experimentally observed data. Figure 2.14a shows computed current density

Resistance increase(ΔR/R0 )

0.25

0.2 Time to failure

0.15

Resistance jump due to Joule Heating

0.1

Incubation time

0.05 Nucleation time

0

0

2000

4000

6000

8000

10000

12000

time

Fig. 2.13 The computed resistance change over time based on the proposed three-phase EM model [60]

10

t0 t50

n=1.21

9

ln(t)

8 n=2

7 6 5 4 22.5

23

23.5

24

24.5

ln(j)

(a) (b) Fig. 2.14 (a) The computed current exponent values from the 3 phase EM model [60]; (b) Measured current exponent values versus current densities, Courtesy of [18]

2.7 The Physics-Based Three-Phase Compact EM Model for Multi-Segment. . .

33

exponent n versus current density in log scale using proposed 3 phase EM model for the pre-void period (nucleation phase) and post-void period.

2.7 The Physics-Based Three-Phase Compact EM Model for Multi-Segment Wires The three-phase EM model discussed in the previous section only works for single wire [60]. It turns out that the three-phase EM model can also be extended to the multi-segment wires. For multi-segment interconnect wires in the nucleation phase, the stress evolution at the cathode node can be obtained by solving the Korhonen’s equation (2.3.10) directly under blocked boundary conditions at the terminals. Once the stress exceeds the given critical stress, then nucleation time, tnuc , can be determined. Chapters 3 and 6 will present some fast closed-form expressions and numerical solutions to the Korhonen’s equation. For a multi-segment tree in the incubation phase, all segments connected with the void can contribute to the void growth. Electron wind at each segment can accelerate or slow down the void growth based on their directions. So total atom flux can also be expressed as a combination of all the flux on the segments. For multi-segment wires, the effective atomic flux per unit length vd Wm is the void growth rate on the main segment which can be expressed as vd = Jm∗ = 

1 Da eZρ Ji Wi = ji Wi Wm kB T Wm i

(2.7.1)

i

Here ji and Wi are the current density and width of the ith segment. Wm is the width of the main segment where the void is formed and Jm is the total flux impact on the main segment. An example structure is shown in Fig. 2.15

Fig. 2.15 A T-shaped wire with main segment and two other segments

34

2 Physics-Based EM Modeling

Here, we use Jm∗ =

1 Wm

 i

Ji Wi to compute the effective atomic flux Jm on

the main segment. Note if we only have one segment, then vd = DakBeZρj as shown T in [20]. Finally, in the growth phase, defined by time period from ti to t50 , the void reaches its critical size and blocks the cross section above the via, forcing the current to flow through the liner or barrier layers. Since this liner is very thin, and its resistivity is much larger than copper, the current density and resistance on the linear will be very high. At this point, resistance of the wire will continue to increase over time after a small resistance jump due to joule heating [50]. Hence, given incubation time ti and vd in (2.7.1), the time and the resistance change can be expressed as [21]: R(t)

t − ti = vd

ρTa hTa (2H +Wm )

−

ρCu H Wm

!

(2.7.2)

where ρTa and ρCu are the resistivity of the (barrier) liner material (Ta for instance) and copper, respectively, Wm is the line width of the segment where void is formed (main segment), H is the copper thickness, and hTa is the liner layer thickness. One important aspect in both incubation and growth phases is that the void volume will saturate in steady state. If saturation occurs before critical void size is reached, the wire can still be rendered as immortal. As a result, determining the void saturation volume is critical. While there are methods of determining the saturation volume, they are limited to 2-segment wires, which is not practical for real interconnect structures.

2.8 The New Void Saturation Volume Estimation for General Multi-Segment Wire Saturation volume of single wire is discussed in Sect. 2.3. In this section, the recently proposed work for fast estimation of saturation void volume for multi-segment wire at steady state will be presented [58]. After a void is formed in a segment, the tensile (positive) stress around the void will gradually reduce to zero and the stress distribution will become compressive (negative) as shown in Fig. 2.16. From the physics perspective, once a void is formed, the void volume Vv (t) in a multi-segment wire will satisfy the following atom conservation equation [33].  Vv (t) = A L

σ (V , t) dV B

(2.8.1)

where L is the volume of the remaining interconnect wire and A is its cross-section area. For the one dimensional, single segment case with wire length L, the steady state saturation volume of the void becomes

2.8 The New Void Saturation Volume Estimation for General Multi-Segment. . .

35

Fig. 2.16 The typical stress evolution on a 30 µm copper wire computed by finite element analysis [58]



L

Vsat = A 0

σ (x) Aσmax L dx = B 2B

(2.8.2)

where σmax is the maximum stress in steady state. Note that Vsat represents the void volume per unit cross-section area. Since length of the void is much smaller than the length of the wire (smaller than 1% of the segment), total length L is used here instead of the length of the remaining interconnect. Going back to Korhonen’s equation, in the steady state, we have jρeZ ∗ ∂σ σmax = = ∂x L 2 ∗ V eZ ∗ L jρeZ L = σmax = 2 2

(2.8.3)

where V is the voltage between cathode and anode of the wire. Using (2.8.2) and (2.8.3), we get Vsat =

AV eZ ∗ L AjρeZ ∗ L2 = 2B 2B

(2.8.4)

36

2 Physics-Based EM Modeling

If we have the initial stress distribution, then Vinit =

Aσinit L B

(2.8.5)

Therefore, void saturation volume, Vsat , for a single wire can be expressed as  Vsat = A

σinit L jρeZ ∗ L2 + B 2B



 =A

σinit L V eZ ∗ L + B 2B

 (2.8.6)

which agrees exactly with [17]. However, this method only works for onedimensional single wires. In this paper, we propose a formula to estimate the saturation volume for general multi-segment interconnect wires where each wire segment may have different widths. For a single segment (such as L1 from Fig. 2.17a), the stress between cathode and anode can be expressed as σc − σa =

j LρeZ (Va − Vc )eZ =  

(2.8.7)

where σc and σa represent stress on cathode and anode, respectively, and Vc and Va represent voltages on cathode and anode, respectively. At the steady state , the stress is linearly distributed on the mental wire as shown by the shaded areas in Fig. 2.17b. Since we need to consider the width of each segment, the problem becomes a 2D Fig. 2.17 (a) A two-segment wire and the direction indicate electron flow; (b) Stress integration area of a two-segment wire

2.8 The New Void Saturation Volume Estimation for General Multi-Segment. . .

37

stress-area integration problem. The void volume, Asat,i , for a segment i, which is the void volume per unit height of the wire or the essentially saturation area of the void, can be computed by stress and area integration as: Li Wi Asat,i = ((−σc,i ) + (−σa,i )) × 2B   Li Wi Vi eZ × = −2σc,i +  2B   Li Wi ji Li ρeZ × = −2σc,i +  2B

(2.8.8)

where Vi ,ji ,Li ,Wi are the voltage difference between anode and cathode, current density, length, and width of the segment, respectively. σc,i is the steady state stress on the cathode of the segment i, which becomes 0 where the void is nucleated. Except for the segment with the void, steady-state stress on cathode of other segments are the same as the anode of the segment connected to them. With this, we have the following results: Proposition 2.1 For a general multi-segment wire, assume that a void is formed in the cathode node of one of the segments and all the initial stresses are zero. Here, the saturation volume of the void Vsat can be computed as Asat =



Asat,i =

i



−2σc,i

i

=

 i

−2σc,i



Li Wi 2B  Li Wi ji Li ρeZ × +  2B Vi eZ + 

×

(2.8.9)

where Asat,i , σc,i , ji , Li , and Wi represent the void area, stress at the cathode, current density, length, and width of the ith segment, respectively. If Asat is smaller than the area of via, resistance will never increase. The interconnect tree can be considered as immortal in this case. If a non-zero initial stress is considered, we can add the initial stress contributions as shown in (2.8.6).  In the following, we go through a few example to illustrate the new formula (2.8.9). The first example is a three-terminal wire shown in Fig. 2.17. Here, stress at node 1 and node 2 can be expressed as j1 L1 ρeZ (V1 − 0)eZ =−   (j1 L1 + j2 L2 )ρeZ (V2 − V1 )eZ =− σ2 = −σ1 −  

σ1 = 0 −

(2.8.10)

38

2 Physics-Based EM Modeling

0

×109 A1

-0.5

A2

Stress(Pa)

-1 -1.5 -2 -2.5 -3 -3.5

0

20

40

60

80

100

Length(um) Fig. 2.18 Stress distribution for two-segment wire at steady state [58]

Figure 2.18 shows calculated stress at steady state during growth phase. The stress estimation agrees with the results in Eq. (2.8.10). As a result the void saturation can be computed as: Asat,2seg =

−σ1 L1 W1 + (−σ1 − σ2 )W2 L2 2B

j1 L21 W1 ρeZ (2j1 L1 + j2 L2 )L2 W2 ρeZ + = 2B 2B

(2.8.11)

For a two-segment wire structure, the saturation void volume estimation was proposed in [6] where segment 2 is treated as a reservoir (j2 = 0). However, in this work, the problem is still considered as 1D where all wire segments are assumed to have the same width. The saturation void volume, Vmax , computed using this method is given below: ⎤ ⎡"  2 Kp B ⎣ 2L1 K +1 + − 1⎦ Vmax /wh = L1 + L2 − K B B

(2.8.12)

where K = eZρj/ . Note, Vmax /wh is actually the saturation length and Vmax /w is the saturation area. This work considers the void size formulated in the cathode of the L1 segment and its impacts on the stress distributions. However, our analysis shows that the void size can be small compared to the segment length and therefore negligible. Comparison of the void volume calculated using this method and the method that we propose is shown in Table 2.2. Where A1 is the saturation area calculated using [6] and A2 is the saturation area calculated using the proposed

2.8 The New Void Saturation Volume Estimation for General Multi-Segment. . . Table 2.2 Comparison of void area of two methods (wire width = 1 µm) [58].

L1 (µm) 10 20 10 10

L2 (µm) 10 10 20 10

j (A/m2 ) 1010 1010 1010 5 × 109

A1 (µm2 ) 0.0609 0.1616 0.1010 0.0306

39 A2 (µm2 ) 0.0614 0.1636 0.1023 0.0307

Fig. 2.19 A T-shaped wire (arrows indicate electron flow) [58]

method. Note, the difference of these two methods is very small. Among the four test cases in Table 2.2, the maximum difference is only 1.28%. In our future work, we will also consider the impact of our void volume calculation on the stress distributions. For the last example we will consider the T-intersection shown in Fig. 2.19. In this case a void will be formed at node 0, stress at other nodes can be calculated as: j1 L1 ρeZ V1 eZ =−   (j1 L1 + j2 L2 )ρeZ (V2 − V1 )eZ =− σ2 = σ1 −   (j1 L1 + j3 L3 )ρeZ (V3 − V1 )eZ =− σ3 = σ1 −  

σ1 = −

(2.8.13)

Figure 2.20 shows stress at steady state during the growth phase. Here, the saturation void area then can be calculated as Asat,3seg = =

−σ1 L1 W1 + (−σ1 − σ2 )L2 W2 + (−σ1 − σ3 )L3 W3 2B j1 L21 W1 ρeZ (2j1 L1 + j2 L2 )L2 W2 ρeZ + 2B 2B (2j1 L1 + j3 L3 )L3 W3 ρeZ + 2B

(2.8.14)

40

2 Physics-Based EM Modeling

0

×109

0

×109

A1 A2

Stress(Pa)

Stress(Pa)

-0.5 -1 -1.5

A3

-1

-2

-2 -2.5 0

50

Length(um)

(a)

100

-3 0

20

40

60

Length(um)

(b)

Fig. 2.20 (a) Stress on horizontal segment 0–2; (b) Stress on vertical segment 1–3 [58]

2.9 Some Other Relevant EM Models and Analysis Methods In addition to the discussed physics-based EM models in the previous sections, there are some other related EM models and assessment methods proposed recently. EM failure shows strong stochastic behaviors and EM impacts on the power grid and signal interconnects inside standard cells considering practical workloads, wire structure, and AC currents also need detailed studies and investigations [36, 59]. Several important works were proposed recently to address those problems. EM analysis considering both signal and power ground interconnect wires inside standard cells was studied in [48, 49]. The joule heating effects were considered based on the root mean square (RMS) current estimation of AC currents. A equivalent EM DC current formula was proposed to consider AC current effects and signal interconnect topologies inside a cell. It was also showed that the lifetimes of the output pins in different locations can be different, which can be exploited for lifetime optimization for standard cells. But this work still uses the traditional Black’s model. The more detailed AC EM analysis for signal interconnect was further proposed in [39]. The effective current densities with recovery effects were considered for both ends of a wire segment under AC currents. The EM impacts on the circuit performances were assessed by a Monte Carlo based analysis based on the proposed AC EM assessment method. The result also showed that EM-induced degradation can be comparable to (even larger than) major device aging mechanisms such as BTI (bias temperature instability) and HCI (hot carrier injection) in the advanced technology nodes (sub 10 nm). Work in [40] studied the solutions of the Korhonen’s equation for a single wire with a finite length and with a semi-finite length. The authors showed that the solution of the finite length wire is upper bounded by that of the semi-finite wire. As a result, a hierarchical EM mortality check algorithm was proposed to find out EMsusceptible wires efficiently by using three criteria sequentially stage by stage with increasing accuracy. The authors also pointed out that the existing method using one

2.9 Some Other Relevant EM Models and Analysis Methods

41

item in the solution of Korhonen’s equation proposed in [21] may not be accurate for very long wires, which was also discussed in Sect. 2.6.2. Furthermore, the EM statistical analysis of the meshed clock networks using the Monte Carlo method considering the redundant structure was studied in [29]. In addition, an framework for logic IP internal EM verification was proposed in [28, 30]. The authors tried to solve the various workload issues for designing a EM safe cells or IPs for specific lifetime targets. The lifetime surface response modeling was developed by parameterized the workload currents and temperature so that different lifetime goals can be targeted at design time. Recently, a finite difference method for solving Korhonen’s equation for power grid EM analysis was proposed in [7]. An effective filtering and predictor-based schemes were used to speed up the analysis. The proposed EM solver also considered the statistical impacts of the EM failures using the Monte Carlo method. Later on, a compact modeling of resulting discretized dynamic Korhonen’s equations by reduced order modeling was further proposed to speedup the analysis [8, 9]. An analytical approach to solving Korhonen’s equation based on an Eigenfunction method was proposed in [62]. This method can give the exact solution for the stress evolution for the finite locations over time for straight multi-segment wires and work for both nucleation and growth phases. This work then was extended to the two-dimensional case for general multi-segment interconnect wires [63]. Some of the proposed methods will be discussed in Sects. 6.6 and 6.7. A probabilistic EM analysis framework for power grids was further proposed in [38, 41]. This work considered the inherent variations from the metal microstructures and activation energy on the wire resistances of copper dual-damascene interconnects based on a physics-based EM model of semi-infinite wires. It also was demonstrated that the power grids have inherent resilience to EM failures. Another stochastic EM analysis for power grids was also proposed using the Hermite polynomial chaos based stochastic analysis considering leakage current variations and inherent EM uncertainties [31]. A kth failure statistical method was used to consider the EM resilience of the P/G networks. But this method is still based on the traditional Black’s model. Another work considering interplay of the thermomechanical stress and EM stress on the array of vias for copper wires was proposed in [42]. The work showed that a via in a via array has different lifetime due to layout dependency. Mont Carlo analysis was applied to estimate the time to failure distribution of the power grids with the via arrays. A method for checking the EM immortality of multi-segment interconnect tree was proposed in [1]. This method can compute the steady state for each branch (their terminal nodes) so that EM immortality is checked for each branch. Recently a voltage-based EM immortality check method was proposed in [2], which extended the voltage-based EM immortality check method [16, 57] (to be discussed in details in Chap. 4). This method can consider the temperature gradient impacts due to joule heating on the stress distributions of the wires.

42

2 Physics-Based EM Modeling

2.10 Summary In the chapter, we reviewed the latest development of physics-based electromigration models. We reviewed important “Korhonen equation,” which describe the stress evolution in the confined copper metal with blocking boundary conditions for void forming and void development, its exact solutions to the Korhonen’s equation in both cases. Then we presented the approximate solutions, which give the compact EM models during the two-phase EM failure process: the “void nucleation phase” and “void growth” phase. On top of this, we present recently developed three-phase EM models, which consists of “void nucleation phase,” “void incubation phase,” and “void growth phase.” We showed the compact models for determining the nucleation, incubation time, and failure time for the three phases. Furthermore, we showed the extension of this work to the multi-segment interconnect wires and showed the fast saturation volume estimation method for multi-segment interconnects, which is critical for the time to failure analysis of EM failure. Last not least, we also reviewed some related EM modeling and analysis work, which are not focused in this book, such as stochastic and variational effects of EM failures, EM failure analysis for signal interconnects considering practical workloads and AC currents.

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27. International technology roadmap for semiconductors (ITRS), 2015 edition, 2015. http:// public.itrs.net 28. P. Jain, S.S. Sapatnekar, J. Cortadella, A retargetable and accurate methodology for logic-IPinternal electromigration assessment, in The 20th Asia and South Pacific Design Automation Conference (IEEE, Piscataway, 2015), pp. 346–351 29. P. Jain, S.S. Sapatnekar, J. Cortadella, Stochastic and topologically aware electromigration analysis for clock skew, in 2015 IEEE International Reliability Physics Symposium (IEEE, Piscataway, 2015), pp. 3D.4.1–3D.4.6 30. P. Jain, J. Cortadella, S.S. Sapatnekar, A fast and retargetable framework for logic-IP-internal electromigration assessment comprehending advanced waveform effects. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(6), 2345–2358 (2016) 31. P. Jain, V. Mishra, S.S. Sapatnekar, Fast stochastic analysis of electromigration in power distribution networks. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(9), 2512–2524 (2017) 32. T. Kim, Z. Sun, C. Cook, J. Gaddipati, H. Wang, H. Chen, S.X.-D. Tan, Dynamic reliability management for near-threshold dark silicon processors, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2016), pp. 1–7 33. M.A. Korhonen, P. Borgesen, D.D. Brown, C.-Y. Li, Microstructure based statistical model of electromigration damage in confined line metallizations in the presence of thermally induced stresses. J. Appl. Phys. 74(8), 4995-11 (1993) 34. M.A. Korhonen, P. Børgesen, K.N. Tu, C.-Y. Li, Stress evolution due to electromigration in confined metal lines. J. Appl. Phys. 73(8), 3790–3799 (1993) 35. C.J.M. Lasance, Thermally driven reliability issues in microelectronic systems: status-quo and challenges. Microelectron. Reliab. 43(12), 1969–1974 (2003) 36. J. Lienig, M. Thiele, Fundamentals of Electromigration-Aware Integrated Circuit Design (Springer, Berlin, 2018) 37. J.R. Lloyd, New models for interconnect failure in advanced IC technology, in International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) (IEEE, Piscataway, 2008), pp. 297–302 38. V. Mishra, S.S. Sapatnekar, The impact of electromigration in copper interconnects on power grid integrity, in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2013), pp. 1–6 39. V. Mishra, S.S. Sapatnekar, Circuit delay variability due to wire resistance evolution under AC electromigration, in 2015 IEEE International Reliability Physics Symposium (IEEE, Piscataway, 2015), pp. 3D.3.1–3D.3.7 40. V. Mishra, S.S. Sapatnekar, Predicting electromigration mortality under temperature and product lifetime specifications, in 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2016), pp. 1–6 41. V. Mishra, S.S. Sapatnekar, Probabilistic wire resistance degradation due to electromigration in power grids. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(4), 628–640 (2017) 42. V. Mishra, P. Jain, S.K. Marella, S.S. Sapatnekar, Incorporating the role of stress on electromigration in power grids with via arrays, in 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2017), pp. 1–6 43. M. Ohring, Reliability and Failure of Electronic Materials and Devices (Academic, San Diego, 1998) 44. J.S. Pak, M. Pathak, S.K. Lim, D. Pan, Modeling of electromigration in through-silicon-via based 3D IC, in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (IEEE, Piscataway, 2011), pp. 1420–1427 45. J. Pak, S.K. Lim, D.Z. Pan, Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs, in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2013), pp. 379–386 46. D.Z. Pan, S.K. Lim, K. Athikulwongse, M. Jung, J. Mitra, J. Pak, M. Pathak, J.-S. Yang, Design for manufacturability and reliability for TSV-based 3D ICs, in Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC) (IEEE, Piscataway, 2012), pp. 750–755

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47. M. Pathak, J.S. Pak, D. Pan, S.K. Lim, Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs, in 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2011), pp. 555–562 48. G. Posser, V. Mishra, P. Jain, R. Reis, S.S. Sapatnekar, A systematic approach for analyzing and optimizing cell-internal signal electromigration, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2014), pp. 1–6 49. G. Posser, V. Mishra, P. Jain, R. Reis, S.S. Sapatnekar, Cell-internal electromigration: analysis and pin placement based optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(2), 220–231 (2016) 50. A. Roy, C.M. Tan, Very high current density package level electromigration test for copper interconnects. J. Appl. Phys. 103, 093707 (2008) 51. M. Shatzkes, J.R. Lloyd, A model for conductor failure considering diffusion concurrently with electromigration resulting in a current exponent of 2. J. Appl. Phys. 59(11), 3890–3895 (1986) 52. V. Sukharev, Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), 1326–1335 (2005) 53. V. Sukharev, E. Zschech, W.D. Nix, A model for electromigration-induced degradation mechanisms in dual-inlaid copper interconnects: effect of microstructure. J. Appl. Phys. 102(5), 053505 (2007) 54. V. Sukharev, X. Huang, H. Chen, S.X.-D. Tan, IR-drop based electromigration assessment: parametric failure chip-scale analysis, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2014) 55. V. Sukharev, X. Huang, S.X.-D. Tan, Electromigration induced stress evolution under alternate current and pulse current loads. J. Appl. Phys. 118, 034504 (2015) 56. V. Sukharev, A. Kteyan, X. Huang, Post-voiding stress evolution in confined metal lines. IEEE Trans. Device Mater. Reliab. 16(1), 50–60 (2016) 57. Z. Sun, E. Demircan, M.D. Shroff, T. Kim, X. Huang, S.X.-D. Tan, Voltage-based electromigration immortality check for general multi-branch interconnects, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2016), pp. 1–7 58. Z. Sun, S. Sadiqbatcha, H. Zhao, S.X.-D. Tan, Accelerating electromigration aging for fast failure detection for nanometer ICs, in Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC) (IEEE, Piscataway, 2018) 59. C. M. Tan, Electomigration in ULSI Interconnects. International Series on Advances in Solid State Electronics and Technology (Word Scientific, Singapore, 2010) 60. S.X.-D. Tan, H. Amrouch, T. Kim, Z. Sun, C. Cook, J. Henkel, Recent advances in EM and BTI induced reliability modeling, analysis and optimization. Integr. VLSI J. 60, 132–152 (2018) 61. S. Wang, Z. Sun, Y. Cheng, S.X.-D. Tan, M. Tahoori, Leveraging recovery effect to reduce electromigration degradation in power/ground TSV, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2017) 62. X. Wang, H. Wang, J. He, S.X.-D. Tan, Y. Cai, S. Yang, Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks, in Proceedings of Design, Automation and Test in Europe (DATE) (IEEE, Piscataway, 2017) 63. X. Wang, Y. Yan, J. He, S.X.-D. Tan, C. Cook, S. Yang, S.X.-D. Tan, Fast physicsbased electromigration analysis for multi-branch interconnect trees, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2017) 64. L. Zhang, Effects of scaling and grain structure on electromigration reliability of cu interconnects, Ph.D. dissertation, University of Texas at Austin, 2010 65. X. Zhao, Y. Wan, M. Scheuermann, S.K. Lim, Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs, in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2013), pp. 363–370

Chapter 3

Fast EM Stress Evolution Analysis Using Krylov Subspace Method

3.1 Introduction As mentioned in Chap. 2, the stress in the interconnect tree is not independent for multi-segment interconnect trees. More accurate EM modeling and analysis techniques are needed. Recently more accurate physics-based EM models and assessment techniques have been proposed [2, 4, 9, 10]. In [9, 10], a compact time to failure model based on the Korhonen’s equation [11], mentioned in Chap. 2 was proposed. Initially, this EM model worked for only a single wire segment but has been extended to deal with multi-segment interconnect trees based on the projected steady-state stress. However, it still cannot provide the time-dependent evolution of hydrostatic stress, which ultimately determines the failure times for multi-branch interconnect trees [8, 18]. Recent methods have attempted to develop analytical solutions of the stress diffusion equations [4, 20]. Approaches in [4] were proposed to address EM modeling in multi-branch interconnect trees. In this approach, analytical solutions for stress evolutions of the stress PDE were derived for a few specific interconnect structures, but still cannot be applied to general multisegment interconnect trees. In [20], an integral transformation-based method was proposed to obtain the analytical solution for multi-segment wires in a straight line. However, this method needs many terms (a few hundred) to obtain accurate results. Both methods also cannot accommodate time-varying stress current densities and temperatures. Recently, a more general finite difference time domain (FDTD) based numerical analysis method has been proposed to solve the stress PDE [2, 5]. However, this method is still computationally intensive for full-chip level analysis. In [2], a finite difference-based linear time-invariant (LTI) system was formulated and reduction of the resulting system matrices was performed to speed up the time domain simulation based on the matrix exponential method. However, this work only presented speed-up results of an overall implementation and did not present accuracy or performance results specifically for the reduction algorithm.

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_3

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48

3 Fast EM Stress Evolution Analysis Using Krylov Subspace Method

In this chapter, we present a novel fast numerical approach to solve the stress partial differential equations based on the Krylov subspace method [6]. The new approach, called FastEM, is based on the finite difference method for initial discretization of the partial differential equations (PDEs) into linear time-invariant ordinary differential equations (ODEs). Then, a modified Krylov subspace-based reduction technique is applied in the frequency domain to reduce the original system matrices for efficient time-domain solutions. FastEM can perform the Krylov subspace-based simulation process for both void nucleation and void growth phases under piecewise constant linear current density inputs and time-varying stressing temperatures. Furthermore, we show that the steady-state response of the stress diffusion equations can be obtained from the resulting ODE system in the frequency domain, which agrees with the recently presented voltage-based EM analysis method for EM immortality check [16].

3.2 The Linear Time-Invariant Ordinary Differential Equations for EM Stress Evolution In this section, we show how to perform the finite difference discretization for the given stress partial differential equation, also known as the Korhonen’s equation in (2.3.10), to create the LTI ODE system. A two-segment wire example is used throughout the section for demonstration with total length L and separate G values for each segment as shown in Fig. 3.1. The wire is discretized into five nodes: two edge boundary nodes at each end of the wire, one junction node at the middle of the wire, and two non-boundary nodes, each between the junction and an edge node. The finite difference method (FDM) is a method of finding a numerical solution to partial differential equations (PDEs) [15]. The PDE can be discretized using many different methods; in our implementation, a central difference method (3.2.1) is used to discretize the spatial variable x (and y in the two-dimensional case as shown later). We use the central difference method due to the low truncation error compared to other discretization methods, such as the forward and backward

Cathode Boundary Node

Ghost Point

Segment Junction Node

Dx

Anode Boundary Node

Discretization Ghost Point

Fig. 3.1 Discretization of the two-segment wire with length L and segment lengths

L 2

[6]

3.2 The Linear Time-Invariant Ordinary Differential Equations for EM Stress. . .

49

differences, at the cost of only adding one term to each equation. Note that this is different from the finite difference time domain (FDTD) method in [5], where time is also discretized. ∂σ Da B σi+1 − 2σi + σi−1 , κ= (x, t) = κ ∂t kT x 2

(3.2.1)

Boundary conditions are discretized depending on location (internal junctions or edges) and EM phase (nucleation or growth). Edge boundaries are introduced during the handling of ghost points in the discretization scheme. These ghost points are terms in the central difference scheme that do not correspond to physical points on the wire structures. Boundary conditions are discretized using the backward difference scheme shown in (3.2.2). ∂σ (0, t) = ∂x ∂σ (L, t) = ∂x ∂σ Growth : (0, t) = ∂x ∂σ (L, t) = ∂x

Nucleation :

σi − σi−1 x σi+1 − σi x σi − σi−1 x σi+1 − σi x

= −G = −G =

σ (0, t) δ

(3.2.2)

= −G

By isolating the ghost point term to one side of the equation, we can replace the ghost point in the original central difference equation (3.2.1) which allows us to eliminate the non-existent point while also introducing the boundary condition. Equation (3.2.3) demonstrates the new central difference equation when the ghost point is eliminated at the cathode. ∂σ κ (0, t) = (G1 x − σi + σi+1 ) ∂t x 2

(3.2.3)

Internal junctions require no ghost point replacement and instead use the fact that flux is continuous at wire junctions to introduce the boundary conditions as in (3.2.4). ∂σ ∂t



L ,t 2

 =

κ (σi−1 − 2σi + σi+1 + (G2 − G1 )) x 2

(3.2.4)

In (3.2.4), G1 and G2 belong to the two respective wire segments that meet at the junction. Additionally, L2 indicates that the example is a single wire with two segments where the junction boundary occurs at half the length of the whole wire. As previously mentioned, we preserve the continuity of the time domain term which allows us to rewrite these equations as an ODE and LTI dynamic system.

50

3 Fast EM Stress Evolution Analysis Using Krylov Subspace Method

Using the previously derived equations (3.2.1), (3.2.2), and (3.2.4) for boundary and internal nodes, we can rewrite these equations into the matrix format: ⎡

⎤ ⎡ ⎤ σ˙1 −1 1 0 0 0 ⎢ σ˙ ⎥ ⎢ 1 −2 1 0 0 ⎥ ⎢ 2⎥ ⎥ κ ⎢ ⎢ ⎥ ⎢ ⎥ ⎢ σ˙3 ⎥ = ⎢ 0 1 −2 1 0 ⎥ 2 ⎢ ⎥ x ⎢ ⎥ ⎣ σ˙4 ⎦ ⎣ 0 0 1 −2 1 ⎦ 0 0 0 1 −1 σ˙5 ⎡ ⎤ ⎡ κβρ ⎤ 0 σ1 x ⎢σ ⎥ ⎢ 0 0 ⎥ ⎢ 2⎥ ⎢ ⎥ ⎢ ⎥ ⎢ −2κ(βρ) 2κ(βρ) ⎥ j1 × ⎢ σ3 ⎥ + ⎢ x x ⎥ ⎢ ⎥ ⎢ ⎥ j2 ⎣ σ4 ⎦ ⎣ 0 0 ⎦ σ5 0 − κβρ x

(3.2.5)

where β = eZ . For the growth phase, the void is nucleated at the cathode node. Then, the resulting LTI system for the two-segment wire case becomes: ⎡

⎤ ⎡ ⎤ σ˙1 (− x δ − 1) 1 0 0 0 ⎢ σ˙ ⎥ ⎢ 1 −2 1 0 0 ⎥ ⎢ 2⎥ ⎥ κ ⎢ ⎢ ⎥ ⎢ ⎥ 0 1 −2 1 0 ⎢ σ˙3 ⎥ = ⎢ ⎥ ⎢ ⎥ x 2 ⎢ ⎥ ⎣ σ˙4 ⎦ ⎣ 0 0 1 −2 1 ⎦ σ˙5 0 0 0 1 −1 ⎡ ⎤ ⎡ ⎤ 0 0 σ1 ⎢σ ⎥ ⎢ 0 0 ⎥ ⎢ 2⎥ ⎢ ⎥ ⎢ ⎥ ⎢ 2κ(βρ) 2κ(βρ) ⎥ j1 × ⎢ σ3 ⎥ + ⎢ − x x ⎥ ⎢ ⎥ ⎢ ⎥ j2 ⎣ σ4 ⎦ ⎣ 0 0 ⎦ σ5 0 − κβρ x

(3.2.6)

As a result, in both the void nucleation and growth phases, we can write the LTI ODE for stress evolution in the following general form: Cσ˙ (t) = Aσ (t) + Bj(t),

(3.2.7)

σ (0) = [σ1 (0), σ2 (0), . . . , σn (0)] In the case of (3.2.5), A is the 5 × 5 coefficient matrix, C is the 5 × 5 identity matrix, B is the 5 × 2 input matrix, and j(t) is the 2 × 1 column vector containing the current density of each wire segment for the respective time t.

3.2 The Linear Time-Invariant Ordinary Differential Equations for EM Stress. . .

51

We note that the presented example only requires equations for the onedimensional case. However, to handle more general cases, these equations can simply be extended to the two-dimensional domain as shown in (3.2.8). σi,j +1 − 2σi,j + σi,j −1 σi+1,j − 2σi,j + σi−1,j ∂σ +κ (x, y, t) = κ 2 ∂t x y 2

(3.2.8)

3.2.1 Steady-State Analysis for Nucleation Phase In this subsection, we show that the ODE for the nucleation phase which we derived from Korhonen’s equation shown in (3.2.5) has the same steady-state stress result as the recently proposed voltage-based EM method in [16]. We demonstrate this using one simple example, a two-terminal wire as shown in Fig. 3.2. We let the total length be L. We then use this wire segment length as the spatial step size and use the backward difference method shown in (3.2.2) for boundary derivation. The resulting system of equations for the two-terminal case is presented in Eq. (3.2.9). 

σ˙0 σ˙1



κ = 2 L



  κG −1 1 σ L × 0 + σ1 − κG 1 −1 L

(3.2.9)

We then rewrite these equations into the following format: σ˙ (t) = Aσ (t) + B y(t) = Eσ (t)

(3.2.10)

In (3.2.10), E = (1, 0), meaning we select node 0, the cathode, as the output node for which we are obtaining the steady-state stress. Then, a Laplace transform can be applied and the resulting transfer function becomes F(s) = E(sI − A)−1 B

(3.2.11)

Then we go back to (3.2.9), the resulting transfer function for the single wire case becomes: F (s) =

Fig. 3.2 A two-terminal wire with the electron flow indicated by the arrow [6]

κGL (sL2 + 2κ)

(3.2.12)

52

3 Fast EM Stress Evolution Analysis Using Krylov Subspace Method

Under step response, which is 1/s in frequency domain, we can then use the final value theorem to obtain the stress at t = ∞, which is the steady-state result of the system under step response as: σsteady = lim f (t) = lim sF (s) t→∞

s→0

GL 1 = s 2

(3.2.13)

We then can compute the steady-state stress based on the voltage-based method [16]: σsteady = VE

j LρeZ GL eZ = =  2 2

(3.2.14)

where VE = j Lρ/2 is the EM voltage at the cathode node (node 0) [16]. As we can see, the results from the two methods are identical. In general, this is the case for general multi-segment interconnects and the steady-state EM stress can be computed by either method. Furthermore, the voltagebased EM method [16] can provide an important relationship for stress values at different nodes as shown in (3.3.1) in the next section.

3.3 The Presented Krylov Fast EM Stress Analysis In this section, we will present our new Krylov subspace-based fast EM stress analysis method. The following section contains several steps necessary for explanation of the presented method and is outlined below: • We first show that the linear time-invariant system describing the dynamic stress evolution must be pre-processed to handle the inherent singularity of the A matrix. • We then compare the steady-state response of the LTI system with a recently presented steady-state method for EM stress evolution using frequency domain methods. • Next, we show the presented Krylov-based model reduction technique using a modified Arnoldi process. • The temperature dependence of the EM effect and our method for handling timevarying temperatures is presented. • Lastly, we outline our method for normalization of the results to maintain numeric stability during model reduction and simulation.

3.3.1 Singularity Mitigation for EM ODE Matrices Before we introduce our Krylov subspace-based method, we notice that the EM matrix A in (3.2.5) or in (3.2.8) in general is singular for our case. We notice that

3.3 The Presented Krylov Fast EM Stress Analysis

53

this is typically true for the nucleation phase; however, this will cause problems for the Krylov subspace-based method, which requires computing the inverse of A to obtain the Krylov subspace. The reason is that the stress variables for the wire nodes are not independent as there is no “ground” stress node. As a result, one more independent equation is required to make this matrix non-singular and we will show the mitigation method below. We note that this singularity issue has also been observed in [2]. To mitigate this problem, we need to introduce one more independent equation (to replace one dependent equation) into the stress LTI system (3.2.8). It turns out that such an independent stress equation can be found in the dynamic and steady-state stress of the LTI system (3.2.8) as a result of mass conservation and stress–strain relationship, and it has been shown in [7, 16] that

ak σk = 0

(3.3.1)

k

where ak is the total area of branches connected to the node k. This equation represents the conservation in the stress kinetics. Equation (3.3.1) is independent of any rows in the A matrix. As an example, for the two-segment wire in Fig. 3.1 with same width for all the segments, we have σ1 + 2σ2 + 2σ3 + 2σ4 + σ5 = 0

(3.3.2)

Therefore, we can use this equation to replace a dependent row (for example, the middle row of the A matrix). With the new row, the A matrix becomes an invertible matrix. As an example, the modified equation (3.3.3), where the second equation or row is replaced, is shown below: ⎡

1 ⎢0 ⎢ ⎢ ⎢0 ⎢ ⎣0 0

0 0 0 0 0

0 0 1 0 0

0 0 0 1 0

⎤⎡ ⎤ ⎤ ⎡ σ˙1 0 −1 1 0 0 0 ⎢ ⎥ ⎢ 1 2 2 2 1 ⎥ 0⎥ ⎥ ⎢ σ˙2 ⎥ ⎥ κ ⎢ ⎥⎢ ⎥ ⎥ ⎢ 0 ⎥ ⎢ σ˙3 ⎥ = 0 1 −2 1 0 ⎥ ⎢ ⎥ ⎢ ⎥ x 2 ⎢ ⎥ ⎣ 0 0 1 −2 1 ⎦ 0 ⎦ ⎣ σ˙4 ⎦ 1 0 0 0 1 −1 σ˙5 ⎡ ⎤ ⎡ κβρ ⎤ 0 σ1 x ⎢σ ⎥ ⎢ 0 0 ⎥ ⎢ 2⎥ ⎢ ⎥ ⎢ ⎥ ⎢ 2κ(βρ) 2κ(βρ) ⎥ j1 × ⎢ σ3 ⎥ + ⎢ − x x ⎥ ⎢ ⎥ ⎢ ⎥ j2 ⎣ σ4 ⎦ ⎣ 0 0 ⎦ σ5 0 − κβρ x

(3.3.3)

We notice that the A for the growth phase is not singular any more and no mitigation is required for growth phase analysis.

54

3 Fast EM Stress Evolution Analysis Using Krylov Subspace Method

3.3.2 Fast Krylov Subspace-Based Stress Analysis In this subsection we present our Krylov subspace-based complexity reduction and simulation method, which is based on the similar principles in the traditional model order reduction methods [14, 17]. After the stress evolution PDE has been discretized into the ODE as shown in (3.2.1)–(3.2.3), it can be written into the following linear time-invariant (LTI) dynamic system: Cx(t) ˙ = Ax(t) + Bj(t),

(3.3.4)

x(0) = [x1 (0), x2 (0), . . . , xn (0)] where the stress vector is represented by x(t), x(0) is the initial stress at t = 0 due to thermal–mechanical interaction. C, A are the n × n matrices and B is the b × p input matrix, where p is the number of inputs or the size of driving current density sources, j(t), which can be time-varying and is represented by the piecewise constant linear waveform as shown in Fig. 3.3. The piecewise constant linear input current density j(t) can be represented by u(t) = u1 (t) + u2 (t − t1 ) + u3 (t − t2 ) + · · · + uN (t − tN −1 )

(3.3.5)

We transform the problem domain into the frequency domain using the Laplace transformation of the state equation (3.3.5), which can be rewritten as 1 sCX(s) − Cx(0) = AX(s) + BJ1 s

(3.3.6)

where the Laplace transformation of j(t) is computed as & %N 1 1 ti−1 J (s) = ui e = J1 s s i=1

J1 =

%N i=1

Fig. 3.3 Example piecewise constant current density j input as a function of time t [6]

ui e

(3.3.7)

& ti−1

(3.3.8)

3.3 The Presented Krylov Fast EM Stress Analysis

55

It may be noted that in contrast to traditional model order reduction of the LTI systems, where the inputs are the impulse function and we perform reduction on the transfer functions [1], here the input is piecewise constant linear (or any arbitrary waveform represented by the piecewise linear function1 ). As a result, we have to consider the input signal subspace during the reduction process. Essentially the reduction process is no longer the traditional model order reduction, but is just the reduction step for a given signal input and is the pre-process step of the whole simulation. Notice that the extended Krylov subspace (EKS) method has been previously presented for fast power grid network analysis [19]. In this paper, we follow a similar idea, but we use a simple Arnoldi-like orthonormalization process to compute the Krylov subspace of the response space instead of using the more ˜ complicated EKS method. Specifically, let X(s) = sX(s), then the above equation becomes: ˜ sCX(s) − sCx(0) = AX(s) + BJ1

(3.3.9)

˜ We then expand the X(s) using Taylor’s series at s = 0, to get: sC(m0 + m1 s + m2 s 2 + · · · ) − sCX(0) = A(m0 + m1 s + m2 s 2 + · · · ) + BJ1

(3.3.10)

We then obtain the recursive response moment computation formula as follows: m0 = −A−1 BJ1 m1 = A−1 C(m0 − x(0)) m2 = A−1 Cm1 .. .

(3.3.11)

mq−1 = A−1 Cmq−2 For the Krylov subspace method, instead of computing the raw moments as shown in (3.3.11), a modified Arnoldi process is used to compute the orthonormalized response moment space. We let G = A−1 C and b = −A−1 BJ1 , and the modified Arnoldi process is shown in Algorithm 1. We call this a modified Arnoldi process, as the computed space Vq is not strictly a Krylov subspace which is defined as: Kq (G, b) = span(b, Gb, Gb2 , . . . , Gq−1 b)

(3.3.12)

1 For the EM-induced stress analysis, piecewise constant linear current density input is sufficient as

most of the power models of a real chip can be modeled as a piecewise constant linear waveform.

56

3 Fast EM Stress Evolution Analysis Using Krylov Subspace Method

Algorithm 1 Modified Arnoldi method for orthonormalization of moment space 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 11: 12: 13: 14: 15: 16: 17: 18: 19: 20: 21:

Modified Arnoldi process () input: (G, b, x(0), q) output: (Vq , Hq ) v1 = b/||b||2 for (j = 1; j

(4.2.17)

k=g

We want to remark that as far as immortality/mortality is concerned, we are only interested in whether or not there exists at least one void formed in a given wire. If no void is formed, the wire is immortal, else the wire is mortal. Hence, we only need to look at the node with lowest voltage, the ground node or cathode node of the whole tree, as a result, (4.2.17) can be simplified to 1 > ak Vk 2A N

VCrit,EM

(4.2.18)

k=g

If (4.2.18) fails, then transient EM analysis will be carried out to find the void location and the nucleation time.

4.2.3 Relationship to the Blech Limit In this subsection, we show how our VBEM analysis and Critical EM Voltage, VCrit,EM are related to the existing Blech limit. We first show that the Blech product essentially is the voltage-based EM assessment for just one wire segment. The

4.2 Voltage-Based EM Stress Estimation

75

proposed VBEM method can actually be viewed as the general extension of this technique to multi-branch interconnect wires. Specifically, let L be the length of a single wire and j the current density of the wire. Starting with the steady-state condition of EM stress shown in (4.2.3), which is also called the Blech condition, if we integrate (4.2.3) along the line, we obtain σ (x) = σinit +

eZρj x 

(4.2.19)

where σinit is the residual stress. The maximum tensile stress can be achieved at the cathode end of the wire (x = L). If the critical stress that the wire can withstand is σcrit , we can define the critical product for EM failure as (j L)crit =

(σcrit − σinit ) eZρ

(4.2.20)

which is called the Blech limit or Blech product [5]. A wire is immortal for EM if it satisfies j L < (j L)crit . As a result, the Blech product can help identify all the immortal wires efficiently. Notice that if ρ is the resistivity, ρLj is actually the voltage across the wire, then (4.2.20) becomes b (j L)crit ∗ ρ = Vcrit =

(σcrit − σinit ) . eZ

(4.2.21)

b is actually the critical voltage for this single wire. As we can see, this where Vcrit equation is the same as (4.2.14) for the single wire case. However, we want to stress that the new Critical EM Voltage, VCrit,EM is more general than the Blech limit due to the following reasons: first, the failure criterion is no longer associated with current density and length of a specific wire segment. In other words, the existing Blech product, j L, does not work any more in this case as the j L of individual branch not only depends on the critical stress, but also depends on the wire structures as the stresses in each wire segment are not independent as they affect each other. However, the proposed VCrit,EM concept can be applied to general interconnect trees with multi-segment wires as one single EM immortality criterion. Second, VCrit,EM still retains the benefits of the Blech limit as the voltage values can be measured directly based on the pass/fail determination of wires from experiments. Third, it agrees with the Blech limit for the single-wire segment case, which essentially validates the proposed method. It has the potential be used as a new design rule parameter between the foundry and design teams to replace or extend the current Blech limit parameter.

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

4.2.4 Steady-State Analysis In this subsection, we first show that the presented VBEM analysis agrees with the results from the steady-state results computed from the finite difference method. Then we show that it agrees with a published closed-form expression for a special case. We demonstrate this using one example, a three-terminal wire as depicted in Fig. 4.3. We first compare with the finite difference method. Let the total length be L. The segment lengths la and lb in the three-terminal wire are equal to L2 . We then use this wire segment length as the spatial step size and use the backward difference method for boundary derivation as shown in [8]. We remark that the matrix derived by the 1D finite difference method actually is singular. The reason is that the atomic conservation in the stress kinetics is not observed in this case. In order to resolve this problem, Eq. (4.2.7) is introduced to replace one row in the matrix. The resulting system of the equations for the three-terminal wire case is presented as below: ⎤⎡ ⎤ ⎤ ⎡ ⎤ ⎡ σ˙0 100 σ0 −1 1 0 κ ⎣ ⎣ 0 0 0 ⎦ ⎣ σ˙1 ⎦ = ⎦ × ⎣ σ1 ⎦ 1 2 1 (L/2)2 001 0 1 −1 σ˙2 σ2 ⎡ 2κGa ⎤ ⎡

+⎣

L

0

(4.2.22)

⎦

b − 2κG L

Here, Ga and Gb are the EM driving forces corresponding to segments a and b, respectively. We then rewrite these equations into the following format: Cσ˙ (t) = Aσ (t) + B y(t) = Eσ (t)

(4.2.23)

In Eq. (4.2.23), E = (1, 0, 0), which means we are looking at the steady state of node 0 which is the cathode node. Then, a Laplace transform can be applied and the transfer function can be obtained as: F (s) = E(sC − A)−1 B

(4.2.24)

Under step input, which is 1s in frequency domain, the final value theorem can be used to obtain the stress at steady state. If limt→∞ f (t) has a finite limit under a step input, the final value theorem for a function under the step input can be expressed as: lim f (t) = lim sF (s)

t→∞

s→0

1 = F (s)|s=0 = −EA−1 B s

(4.2.25)

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77

We notice that (−A)−1 is (−A)−1

⎤ ⎡ 3 −1 −1 L2 1⎣ = × −1 −1 −1 ⎦ 4κ 4 −1 −1 3

Then, we can obtain the steady-state result of the system:   1 2κGb L2 3 2κGa × + × σsteady = F (s)|s=0 = 4 L 4 L 4κ (3Ga + Gb )L = 8

(4.2.26)

(4.2.27)

On the other hand, we can compute steady-state stress at the cathode node (node 0) based on the voltage-based method as: A1 V1 + A2 V2 ×β 2A (3Ga + Gb )L ja Lρ + ja Lρ/2 + jb Lρ/2 ×β = = 4 8

σsteady = VE × β =

(4.2.28)

+A2 V2 where VE = A1 V12A is the EM voltage at the cathode node and β = eZ  . As we can see, the results from the two methods are identical. This example gives another theoretical validation of the presented VBEM analysis method, which agrees with the steady-state results from the finite difference method. Now we show that the discretization schemes (by using different discretization sizes) will not change the steady-state results. Figure 4.4 shows stress analysis using the simplified FDM method comparing COMSOL result of Korhonen’s equation. It can be observed that the steady-state results under different discretization sizes are same although their transient behaviors are different. In other words, discretization errors will not affect the final steady-state results from FDM. In addition to analyzing the FDM steady state results considering different discretization schemes, we further show some pole information from the FDM analysis of Korhonen’s equation. We use the same three-terminal wire shown in Fig. 4.3 as an example. In this case, we discretize the two segments into 21 nodes (so we have 21 poles) instead of just the three boundary nodes presented in (4.2.22). As we can see from Table 4.1, all the poles are real poles and the EM system is stable. The EM-induced stress basically is progressing monotonically for a given step current input. Such a monotonic nature of EM-induced stress is important to ensure the steady state is sufficient for the EM immortality check. Our study shows that this is the case for all the examples we analyzed. We also remark that although there is still a possibility of overshoots for a system with negative poles, for our case, it is rarely observed since they are only theoretically possible. Practically, it does not seem necessary to worry about the oscillating behaviors in the stress evolution process.

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

Fig. 4.4 Different discretization steps (sizes) lead to the same steady-state stress [24] Table 4.1 The computed poles for the three-terminal wire [24] Poles values (×103 ) −1.7541 −1.4319 −0.8161 −0.2354 −0.0000

−1.7248 −1.3230 −0.6857 −0.1533 −

−1.6767 −1.2042 −0.5598 −0.0873 −

−1.6107 −1.0783 −0.4410 −0.0392 −

−1.5286 −0.9479 −0.3321 −0.0099 −

Furthermore, we notice that recent work in [17] gives the closed-form expression (which is consistent with the measured experimental results) of steady-state stress for a special three-terminal wire case with an inactive (passive) segment (Fig. 4.5a) and the stress profile (Fig. 4.5b). In this case, the segment Ls has zero current (so it is inactive or passive), while the active segment L has current flow j . The cathode is located at node 2. It was shown in [17] that the steady-state stress at any location x in the active segment σ (x) is given by: σ (x) =

eρZj (x − Ls ) + σ1 

(4.2.29)

where σ1 is the stress in the inactive sink as shown in Fig. 4.5b, which is given by σ1 = −

eρZj L2 2(L + Ls )

(4.2.30)

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79

Fig. 4.5 (a) A three-terminal wire with inactive (passive) sink, with the cathode at node 2. (b) The steady-state stress distribution of a three-terminal wire with inactive (passive) sink [24]

As a result, the stress at the cathode node (x = Ls + L) will become eρZj L2 eρZj L −  2(L + Ls )  L2 eρZj L− =  2(L + Ls )

σ (L + Ls ) =

(4.2.31)

On the other hand, based on the VBEM method, we have V0 = V1 = j Lρ (as there is no current in Ls and A0 = Ls w and A1 = Lw + Ls w, where w is the width of the two segments (assuming two segments have the same width). Then, the stress at the cathode node, σ (L + Ls ), can be computed by A0 V0 + A1 V1 σ (L + Ls ) = β × VE (L + Ls ) = β × 2A  j Lρ(Ls w + Lw) + j LρLs w =β× 2(Lw + Ls w)  j LρLs j Lρ + =β× 2 2(L + Ls )  L2 eρZj L− =  2(L + Ls )

(4.2.32)

Comparing (4.2.31) and (4.2.32), we can see again that the VBEM method agrees exactly with the closed-form expression for this particular case given by Lin and Oates [17].

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

4.2.5 Study of Some Special Cases In this subsection, we study three multi-branch interconnect structures to illustrate the proposed method. The three structures consist of a straight-line three-terminal wire in Fig. 4.3, a T-shaped four-terminal wire in Fig. 4.8, and a comb structure wire in Fig. 4.9. We stress that the proposed method can be applied to any multi-branch tree-structured interconnects.

4.2.5.1

The Straight-Line Three-Terminal Wire

The straight-line three-terminal wire is shown in Fig. 4.3. In this wire, the node 0 is treated as the ground node. Note that current densities in the two segments are ja and jb , which are determined by the rest of the circuit and may not be the same. Then, the EM stress equation becomes: V0 = 0,

A0 = la wa ,

σ0 = βVE

V1 = ja la ρ,

A1 = la wa + lb wb ,

σ1 = β(VE − V1 )

V2 = jb lb ρ + ja la ρ,

A2 = lb wb ,

σ2 = β(VE − V2 )

A = A0 + A1 + A2 where VE =

V1 A1 + V2 A2 V0 A0 + V1 A1 + V2 A2 = 2A 2A

where β = eZ . Passive sink and passive reservoir configurations, described in [17], are typical elements in the general interconnect tree. They are used as test cases in this subsection. Figures 4.6 and 4.7 show the steady-state stress for the cases with passive reservoir (segment a with ja = 0) and passive sink (segment b with jb = 0). Here we define “passive” and “active” as representing zero current density and non-zero current density, respectively. The analysis will focus on mitigating the EM effect in the active segment. It can be observed from Fig. 4.6 that the passive reservoir (segment a) is characterized with higher stress compared with the active sink (segment b). Thus, the void will first nucleate in the reservoir which can relax the EM effect in the sink. On the contrary, as shown in Fig. 4.7, the existence of passive sink (segment b) will lead to higher stress in the active reservoir (segment a), which accelerates the void formation, thus leading to EM failure in the reservoir. A comparison of the steady-state stress predicted by VBEM with the finite element analysis (COMSOL) simulation in both cases has demonstrated an excellent agreement.

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81

Fig. 4.6 (a) 2-D stress distribution on wire at steady state for passive reservoir. (b) EM stress versus length at steady state [24]

Fig. 4.7 (a) 2-D stress distribution on wire at steady state for passive sink. (b) EM stress versus length at steady state [24] Fig. 4.8 Interconnect examples for EM analysis for T-shaped four-terminal wire [24]

4.2.5.2

T-Shaped Four-Terminal Wire with Stub

The structure of the T-shaped four-terminal wire is shown in Fig. 4.8. In this case, we have three segments which connect through the middle node 1. Current densities are ja , jb , and jc on the three branches. In this case, if we make the branch c (the vertical branch), the stub (its current density is set to zero, jc = 0), then the EM stress can also be obtained: V0 = 0,

A0 = la wa

V1 = ja la ρ,

A1 = la wa + lb wb + lc wc

V2 = jb lb ρ + ja la ρ,

A2 = lb wb

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

V3 = ja la ρ + jc lc ρ,

A3 = lc wc

σ0 = βVE ,

σ1 = β(VE − V1 )

σ2 = β(VE − V2 ),

σ3 = β(VE − V3 )

A = A0 + A1 + A2 + A3 where VE =

V1 A1 + V2 A2 + V3 A3 2A

The stub acts as a sink when it is close to an anode and serves as a source when it is close to a cathode. The distance between the stub and the cathode and the length of the stub can be important factors related to EM stress. As shown in Fig. 4.2b, when the stub is moved away from the cathode node (node 0), it allows more atoms to migrate to the stub and thus creates more tensile stress at the cathode node. This is a commonly seen structure in interconnect circuit design. We will discuss the effects of the distance between the stub and the cathode as well as the length of the stub on EM stress. Thus, by adjusting the stub location and length, we can adjust the stress at the cathode node to fix potential EM failures in the physical design.

4.2.5.3

Interconnect Wires with Comb Structure

Now, we study a more complicated interconnect structure, which is the comb or ladder structure as shown in Fig. 4.9. In this comb-structured interconnect, we have N fingers, in which each finger structure is assumed to be the same. Rsh is the sheet resistance of the metal and I

Fig. 4.9 Comb-structured interconnect examples for EM analysis [24]

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83

is the current along each finger. We assume that node 0 is still the ground node. LB and WB are the length and width, respectively, for the body structures, LF and WF are the length and width, respectively, for the fingers. i refers to ith node on the body and i  is the node on the ith finger. The total area connected to node k, except node N , is Ak and total area connected to node k  is Ak  , total area connected to node N is AN , and the total area of the whole comb structures, A, can be expressed as: Ak = 2WB LB + WF LF , Ak  = WF LF , AN = WB LB + WF LF , A = N(WB LB + WF LF ) Note that since the N th node is only connected to one part of the body structure, the total area connected with node N is different from other nodes. Current flows in the same direction (which is opposite to the arrows in Fig. 4.9), the highest EM tensile stress will be generated at node 0 because it has the lowest potential. Hence, in this case, we only need to check VE against the critical potential. The potential at each node for Vk and Vk  can be obtained as:  LB k(k − 1) Vk = Nk − ×I × Rsh , 2 WB Vk  = Vk + I ×

LF Rsh WF

Finally, the EM stress of the comb structure can be obtained as:  (N + 1)(4N − 1)LB 2 I Rsh × VE = 12 WB LB + WF LF  2(N + 1)(2N + 1)LB LF WF /WB + 6LF 2 + , WB LB + WF LF

(4.2.33)

σ0 = βVE As shown in the above equation, three factors, N , LF , and LB have a strong influence on stress. Figure 4.10 shows how the EM-induced stresses at the node 0 change with LF and LB . As we can see, LB has a much larger impact on the stress than LF , which can be used for EM optimization. Both LF and LB have nonlinear impacts on the stress, and this nonlinear trend is more clear for LF . Other trends of stress change will be analyzed and discussed in the numerical results section.

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires 4120

8000 6000 4000 2000 Incresing length of LB 0

0

50

100

150

Nomalized Stress

Nomalized Stress

10000

4100 4080 4060 4040 4020 4000 3980 3960

increasing length of LF 0

Length(um)

(a)

50

100

150

Length(um)

(b)

Fig. 4.10 (a) EM stress validation for each comb-structured interconnect with changing LB . (b) EM stress validation for each comb-structured interconnect with changing LF [24]

4.2.6 Current Crowding Impact Analysis In this subsection, we study the impact of the current density distributions on the presented VBEM analysis method. The VBEM method assumes that current density is evenly distributed. However, this is not always the case since for real interconnect wires, the current density may vary and become larger around the corner areas (the current crowding effect). We observe that if the width is not much smaller than the segment length, the current crowding effect can be quite significant. In this case, the calculated nodal voltage will be less accurate for stress calculations. To consider the current crowding effects, instead of using (4.2.11) to compute the EM voltage, we need to perform the area integration of voltage using (4.2.12) to compute the final steady-state stress after current and voltage distributions are computed. As we will show in this subsection, this will lead to more accurate results compared to the results using (4.2.11), and that the presented method can be extended to consider current crowding effects. The area used for the integration is the total areas of the wires in 2D case (although we show 3D structures of the wires) since (4.2.12) is for 2D integration. In principle, the integration can be done over the 3D volume. It does not have to be restricted to 2D integration. We also remark that the VBEM method will be more expensive for the numerical 2D integration operation. This is due to the nature of the current crowding modeling problem. One has to compute the detailed current and voltage distributions first using expensive numerical methods such as the finite element method, to account for the effects of current crowding on EM risks. In the following, we study two wire structures to assess the impact of current crowding effects. In Fig. 4.11, an L-shaped wire with three nodes is used as the first test structure. Here, la and lb are not much larger than the width of wire w. A voltage is applied on node 1 and node 0 is the ground node. Node 2 is connected with node 1 through a stub with a current density of 0.

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85

Fig. 4.11 L-shaped wire structure with three nodes [24]

Fig. 4.12 L-shaped wire structure with current crowding effects [24]

In this case, the current density distribution around node 1 is not uniform, as shown in Fig. 4.12. COMSOL simulation is used to obtain non-uniform current density distribution as well as voltage distribution. At node 1, the current density is smaller than the current density on the other part of the branch. This means that if the nodal voltage is used to calculate the stress, it will be smaller than the actual condition. On the other hand, if the branch is longer (compared to the width of the wire), the current crowding has a smaller effect on the final steady-state stress. Table 4.2 summarizes the results for two cases for the stress values at the cathode node. In case 1, la = 10, lb = 2, and j = 3 MA/cm2 with voltage difference 0.03 V between node 0 and 1. In case 2, la = 4, lb = 2, and j = 3 MA/cm2 with voltage difference 0.012 V between node 0 and 1. Column Crowding indicates that the current crowding effect is considered by using (4.2.12) and Err1 is the relative error

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

Table 4.2 EM stress calculated with and without current crowding effects [24] Cases 1 2

COMSOL 286 MPa 97.7 MPa

Crowding 284 MPa 96.1 MPa

Err1 0.94% 1.60%

NoCrowding 282 MPa 90.4 MPa

Err2 1.53% 7.72%

Fig. 4.13 U-shaped wire structure with four nodes [24]

of considering the crowding effect compared to COMSOL. Column noCrowding indicates that no current crowding effect is computed using (4.2.11) and Err2 is the error without considering the crowding effect. As we can see from Table 4.2, for the long branch (case 1), the error for the method without considering current crowding is 1.53% and the error increases to 7.72% for the shorter branch (case 2), which is quite significant. However, if the current crowding effect is considered (as shown in Crowding column), the errors become smaller (less than 2%). The second structure we study is the U-shaped wire shown in Fig. 4.13. Its segment length is not significantly larger than the width in this case, and current density distribution can be seen in Fig. 4.14, with the current crowding effect being very visible at nodes 2 and 3. For the U-shaped structure, we apply 0.05 V to node 1 and 0 V voltage to node 4. The result is shown in Table 4.3 for the stress values at the four nodes. Row Crowding indicates that the current crowding effect is considered and row noCrowding indicates that the crowding effect is not considered. As we can see, for nodes 1 and 4, even when current crowding is not considered, the error is only 1.74%, which is close to the errors of cases considering current crowding. However, for nodes 2 and 3 if current crowding is not considered, the errors increase to 23.16%. On the other hand, the error reduces to 1.95% when current crowding is considered. Thus, in both cases, if the wire segment is long

4.2 Voltage-Based EM Stress Estimation

87

Fig. 4.14 U-shaped wire structure with current crowding effects [24]

Table 4.3 Stress values at each node for the U-shaped structure [24] Cases/Nodes COMSOL Crowding Error No crowding Error

1 345.5 MPa 339.0 MPa 1.74% 339 MPa 1.74%

2 104.2 MPa 102.2 MPa 1.95% 135.6 MPa 23.16%

3 −104.2 MPa −102.2 MPa 1.95% −135.6 MPa 23.16%

4 −345.5 MPa −339.0 MPa 1.74% −339 MPa 1.74%

enough (more than ten times of wire width), the current crowding impact on stress values by the VBEM method is not significant.

4.2.7 Application to Mesh-Structured Interconnect Wires In this section, we study if the proposed VBEM analysis method can be applied to mesh-structured interconnect wires, which can be used at the cell-level layout design and can be vulnerable to EM failure as well. Figure 4.15 shows a 4 × 4 mesh structure with 16 nodes. In order to calculate the VE , nodal voltages and areas connected with each node are required. A voltage is applied on node 4 and node 13 is set to be ground node. The voltage of each node can be measured or analyzed by SPICE. Areas connected to each node are different at different locations. For the nodes at corners (1,4,13,16), the area connected with them is 2W L, where W is the width of the wire and L is the distance between adjacent nodes.

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

Fig. 4.15 A 4 × 4 mesh-structured wire [24]

For the nodes at the boundaries (2,3,5,8,9,12,14,15), the area connected with them is 3W L. For the nodes in the middle (6,7,10,11), the area connected with them is 4W L. The total area is the area summation of each branch, which is 48W L. Then the VE can be obtained as: VE = (2W L(V1 + V4 + V1 3 + V1 6) + 3W L(V2 + V3 + V5 + V8 + V9 + V1 2 + V1 4 + V1 5) + 4W L(V6 + V7 + V1 0 + V1 1))/48W L σmax = σ13 = βVE In our stressing set up, we apply 0.005 V to node 4 and 0 V (ground) to node 13. The length of each branch is 10 µm and width is 0.1 µm. Table 4.4 shows the result of the test case. As we can see, for all the cases, the VBEM method leads to less than 0.17% error compared to COMSOL, which shows that the proposed VBEM method can be directly applied to mesh-structured wires.

4.2 Voltage-Based EM Stress Estimation

89

Table 4.4 Stress condition for mesh structure [24] Nodes Voltage COMSOL VBEM Error

1 2.498e−3 V 0.2441 MPa 0.2439 MPa 0.0771%

2 2.880e−3 V −51.61 MPa −51.53 MPa 0.1549%

3 3.656e−3 V −157.0 MPa −156.8 MPa 0.1572%

4 5e−3 V −339.5 MPa 52.07 MPa 0.1609%

Nodes Voltage COMSOL VBEM Error

5 2.116e−3 V 52.15 MPa 52.07 MPa 0.1543%

6 2.498e−3 V 0.2118 MPa 0.2116 MPa 0.095%

7 3.079e−3 V −78.62 MPa −78.50 MPa 0.1547%

8 3.652e−3 V −156.6 MPa −156.3 MPa 0.1572%

Nodes Voltage COMSOL VBEM Error

9 1.347e−3 V 156.8 MPa 156.3 MPa 0.1571%

10 1.921e−3 V 78.62 MPa 78.50 MPa 0.1545%

11 2.502e−3 V −0.2114 MPa −2.110 MPa 0.1529%

12 2.884e−3 V −52.15 MPa −52.07 MPa 0.1545%

Nodes Voltage COMSOL VBEM Error

13 0 338.5 MPa 339.8 MPa 0.1543%

14 1.344e−3 V 157.0 MPa 156.8 MPa 0.095%

15 2.120e−3 V 51.61 MPa 51.53 MPa 0.1547%

16 0.250e−3 V −0.2441 MPa −0.2438 MPa 0.1572%

4.2.8 Application to IBM Power Grids Besides small interconnect structures, we also validate the proposed method on a large practical IBM power grid benchmark [18]. A portion of the power grid network is shown in Fig. 4.16. Details of the benchmark are shown in Table 4.5. In this experiment, critical stress is 500 MPa [11]. The critical voltage is 3.694 × 10−3 V. For the IBM power grid networks, COMSOL based FEM analysis method is too slow. Instead, we use a recently proposed eigenfunction-based stress analysis method for multi-segment interconnect trees [26] as the baseline for comparison. The proposed VBEM and baseline methods were both implemented with C/C++ for comparison. The comparison works were carried out on a workstation with 2 Intel Xeon E5-2698 CPUs and 128 GB memory. We can see that the VBEM method has significant acceleration compared to the baseline method. For ibmpg1, VBEM takes only 0.69 s to simulate all 689 trees, which translates to a 1319× speed-up over the baseline method. All the trees in ibmpg1 are small trees with the maximum number of branches in a tree being 30. With larger trees, the acceleration rate decreases, but one still sees 30.86×

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4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

Fig. 4.16 A small portion of a typical power supply network [18] Table 4.5 Property of IBM benchmarks [24]

Name #node #branch #max branch #trees #failed trees VBEM(s) Baseline(s) Acceleration

ibmpg1 11,572 5580 30 689 249 0.69 910.56 1319×

ibmpg2 61,797 61,143 192 462 91 29.63 973.65 30.86×

ibmpg3 407,279 399,201 965 7388 1585 3999.97 17720.97 4.43×

ibmpg4 474,836 384,709 571 9358 0 4565.27 22456.13 4.91×

acceleration for ibmpg2, 4.43× acceleration for ibmpg3, and 4.91× acceleration for ibmpg4. Note that the lengths of branches are not the same. As can be seen in ibmpg4, although it has trees with many branches, the lengths of branches are small so all trees are immortal in this case. We note that the baseline method is a transient EM analysis while the VBEM method is a steady-state method. Another saving brought by the VBEM method is the percentage of the immortal tree count over the total tree count, as the immortal trees will not need the costly transient EM analysis. The immortal tree number can be significant compared to the total tree count (ranging from 63.8% in ibmpg1 to 100% in ibmpg4 case. Hence, the percentage of savings from the proposed VBEM method is problem-specific and can be very significant.

4.3 Numerical Validation Results and Discussions In this section, we validate the presented voltage-based EM (VBEM) check tool against numerical analysis results. We validate the VBEM method against the results by a finite element analysis (FEA) tool, COMSOL [9], based on the dynamic stress evolution described by Korhonen’s equation (2.3.10). In the following, we list the results for the three structures we have discussed.

4.3 Numerical Validation Results and Discussions

91

4.3.1 Results for Straight-Line Three-Terminal Interconnects The parameters used for the validation cases are summarized in Table 4.6, and the results for the three-terminal wire are shown in Fig. 4.17, which shows the largest tensile stress at node 0. We compare our results against COMSOL and another published EM numerical simulator, XSim [27], which has been validated by measured results [13, 27]. As demonstrated in Fig. 4.17, the results of the presented method agree well with COMSOL results. To further validate the new method, we compared our Table 4.6 Parameters for each straight-line three-terminal interconnect case [24]

Branch a l w Case (µm) (µm) 1 25 1 2 25 1 3 25 1 4 25 1 5 25 1 6 10 0.1 7 10 0.2 8 10 0.3 9 10 0.4 10 10 0.5

Branch b l w (µm) (µm) 0 1 175 1 175 1 175 1 175 1 25 1.25 25 1.25 25 1.25 25 1.25 25 1.25

j (MA/cm2 ) 1.25 1.25 1.25 1.25 1.25 10 5 3.3 2.5 2

j (MA/cm2 ) 0 0 0.125 0.625 1.25 1.25 1.25 1.25 1.25 1.25

140 VBEM COMSOL Xsim

Normalized Stress

120 100 80 60 40 20 0

1

2

3

4

5

6

7

8

9

10

Case Number Fig. 4.17 Steady-state EM stress comparisons for each straight-line three-terminal interconnect case (x: case number, y: EM stress at the node 0 (cathode node)) [24]

92

4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

Table 4.7 Parameters for each T-shaped four-terminal interconnect case (l = µm, w = µm, and j = MA/cm2 ) [24] Branch a

b

c

Case l w j l w j l w j

1 6 0.14 7.142 4 0.14 7.142 5 0.28 0

2 10 0.14 7.142 0 0.14 7.142 5 0.28 0

3 11 0.14 7.142 9 0.14 7.142 10 0.14 0

4 20 0.14 7.142 0 0.14 7.142 10 0.14 0

5 20 0.28 3.571 0 0.28 3.571 5 0.14 0

6 20 0.28 3.571 0 0.28 3.571 10 0.14 0

results against the EM simulator XSim for steady-state results. As we can see, the VBEM method also agrees very well with XSim, which further validates the presented method. With the increase in length and current density in the branch b, the EM stress increases. If the current density in branch a decreases, EM stress also decreases.

4.3.2 Results for T-Shaped Four-Terminal Interconnect We next validate the VBEM method on the T-shaped four-terminal interconnect case. Again, we list the parameters used for the validation cases in Table 4.7, and the results of three-terminal wires are shown in Fig. 4.18, which shows the largest tensile stress at the node 0. During the analysis of the T-shaped interconnect, forward and reverse currents are provided in branches a and b. Again, we observe that the obtained results are also very close to COMSOL results and the average error rate is 0.56% while the maximum error is 1.42% in case 2 reverse. Also, it can be seen if the total length of branches a and b increases, the stress increases. Furthermore, the location and current density of the stub can have a significant impact on the stress at the stub (branch c). With zero current density, the stub can decrease the stress if it is closer to the cathode, or if its length is decreased. Also, if the stub is placed further away from the cathode and its length is longer, the stress increases.

4.3.3 Results for Comb-Structured Interconnects Now, we further validate the presented VBEM method on the comb-structured interconnect. We list the parameters used for different test cases and the predicted stress and error rate in Table 4.8. Figure 4.19 shows the impact of the number of

4.3 Numerical Validation Results and Discussions

93

Fig. 4.18 EM stress validations for each T-shaped four-terminal interconnect case (x: case number, y: EM stress at the node 0 (cathode node)) [24] Table 4.8 EM stress validations for comb-structured interconnect cases [24] Comb case Case 1—WB = 1, WF = 1, LB = 10, LF = 10

Case 2—WB = 1, WF = 1, LB = 20, LF = 10

Case 3—WB = 1, WF = 1, LB = 10, LF = 20

Method Proposed EM

Number of fingers 1 2 4 10 23.75 71.25

6 145.42

8 246.25

10 373.75

COMSOL Error Proposed EM

10 0.00% 15

23.78 0.08% 41.67

71.33 0.11% 135

146.50 0.74% 281.67

245.10 0.47% 481.67

375.88 0.57% 735

COMSOL Error Proposed EM

15 0.00% 15

41.59 0.18% 29.17

136.28 0.94% 77.5

279.80 0.67% 152.5

486.41 0.98% 254.17

738.12 0.42% 382.5

COMSOL Error

15 0.00%

29.42 0.85%

77.19 0.41%

152.07 0.28%

257.51 1.30%

385.73 0.84%

fingers, N , on the stress at the node 0 for these three cases or configurations. As we can see, with an increase in N , the EM stress increases super-linearly. Besides, we can observe from Fig. 4.10 that, increasing LB and LF increases EM-induced stress at node 0. However, the increase in LF only has a small effect on EM stress as compared to the increase in LB . Furthermore, the results of the VBEM approach

4 Fast EM Immortality Analysis for Multi-Segment Copper Interconnect Wires

Fig. 4.19 EM stress validations for each comb-structured interconnect case (x: number of fingers, y: EM stress at the node 0 (cathode node)) [24]

800 Normalized Stress

94

600 400

VBEM for case1 COMSOL for case1 VBEM for case2 COMSOL for case2 VBEM for case3 COMSOL for case3

200 0 0

5 Number of fingers

10

show good agreement with the results obtained from COMSOL. The average error is 0.49% and maximum error is 1.3% in case 3 at N = 8.

4.3.4 Summary In this chapter, we have presented a novel and fast EM immortality check for general multi-branch interconnect trees. The new method estimates the EM-induced steady-state stress in general multi-segment copper interconnect wires based on a novel parameter, Critical EM Voltage, VCrit,EM . We have shown that the VCrit,EM essentially is the natural, but important extension of the Blech product or Blech limit concept, which describes the EM immortality condition for a single-segment wire, to more general multi-segment interconnect wires. Furthermore, the new VBEM analysis method is very amenable for EM violation fixing as it brings new design knobs and capabilities into the physical design flow. The resulting EM risk assessment method can be much easier to integrate with physical design tools and flows. The new voltage-based EM stress estimation method is based on the exact solution of fundamental steady-state stress equations. We have shown that the presented VBEM analysis method agrees with the results from the finite difference method in the steady-state through one example and also agrees with one published closed-form expression of steady-state stress for a special three-terminal wire case, which further validates the presented method. Furthermore, we compared VBEM against the COMSOL finite element analysis tool and another published EM numerical simulator XSim and it was shown that the VBEM approach agrees with both of them very well in terms of accuracy. We also studied the impact of the current crowding of practical interconnect wires on the estimated steady-state stress and showed that the effect is not significant if the length of the wire length is much greater than its width. An extension of the VBEM method to consider the significant current crowding effects was given and additionally, we analyzed mesh-structured interconnect wires and demonstrated that the presented VBEM method is correct and accurate on these structures as well. The results showed that the VBEM method

References

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leads to less than 0.17% error compared to COMSOL for all the cases, which shows that the presented VBEM method can be directly applied to mesh-structured wires.

References 1. A. Abbasinasab, M. Marek-Sadowska, Blech effect in interconnects: applications and design guidelines, in Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD ’15 (ACM, New York, 2015), pp. 111–118 2. A. Abbasinasab, M. Marek-Sadowska, Rain: a tool for reliability assessment of interconnect networks—physics to software, in Proceedings of the Conference on Design Automation, DAC’18 (ACM, New York, 2018), pp. 133:1–133:6. http://doi.acm.org/10.1145/3195970. 3196099 3. B. Bailey, Thermally challenged, in Semiconductor Engineering (2013), pp. 1–8 4. J.R. Black, Electromigration-a brief survey and some recent results. IEEE Trans. Electron Devices 16(4), 338–347 (1969) 5. I.A. Blech, Electromigration in thin aluminum films on titanium nitride. J. Appl. Phys. 47(4), 1203–1208 (1976) 6. S. Chatterjee, V. Sukharev, F.N. Najm, Power grid electromigration checking using physicsbased models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7), 1317–1330 (2018) 7. H. Chen, S.X.-D. Tan, V. Sukharev, X. Huang, T. Kim, Interconnect reliability modeling and analysis for multi-branch interconnect trees, in Proceedings of the Design Automation Conference (DAC) (IEEE, Piscataway, 2015) 8. C. Cook, Z. Sun, T. Kim, S.X.-D. Tan, Finite difference method for electromigration analysis of multi-branch interconnects, in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD’16) (IEEE, Piscataway, 2016), pp. 1–4 9. Comsol multiphysics. https://www.comsol.com/ [Oct. 16, 2013] 10. E. Demircan, M.D.Shroff, Model based method for electro-migration stress determination in interconnects, in 2014 IEEE International Reliability Physics Symposium (IEEE, Piscataway, 2014), pp. IT.5.1–IT.5.6 11. R. Gleixner, W. Nix, A physically based model of electromigration and stress-induced void formation in microelectronic interconnects. J. Appl. Phys. 86(4), 1932–1944 (1999) 12. S. Hau-Riege, New methodologies for interconnect reliability assessments of integrated circuits, Ph.D. dissertation, Massachusetts Institute of Technology, 2000 13. C.S. Hau-Riege, A.P. Marathe, Z.S. Choi, The effect of current direction on the electromigration in short-lines with reservoirs, in IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2008), pp. 381–384 14. X. Huang, T. Yu, V. Sukharev, S.X.-D. Tan, Physics-based electromigration assessment for power grid networks, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2014) 15. M.A. Korhonen, P. Bo/rgesen, K.N. Tu, C.-Y. Li, Stress evolution due to electromigration in confined metal lines. J. Appl. Phys. 73(8), 3790–3799 (1993) 16. A. Kteyan, V. Sukharev, M.A. Meyer, E. Zschech, W.D. Nix, Microstructure effect on EMinduced degradations in dual-inlaid copper interconnects, in Proceedings of AIP Conference, vol. 945 (IEEE, Piscataway, 2007), pp. 42–55 17. M. Lin, A. Oates, An electromigration failure distribution model for short-length conductors incorporating passive sinks/reservoirs. IEEE Trans. Device Mater. Reliab. 13(1), 322–326 (2013) 18. S.R. Nassif, Power grid analysis benchmarks, in Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC) (IEEE, Piscataway, 2008), pp. 376–381

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19. J.S. Pak, M. Pathak, S.K. Lim, D. Pan, Modeling of electromigration in through-silicon-via based 3D IC, in 2011 IEEE 61st Electronic Components and Technology Conference (ECTC) (IEEE, Piscataway, 2011), pp. 1420–1427 20. J. Pak, S.K. Lim, D.Z. Pan, Electromigration study for multi-scale power/ground vias in TSV-based 3D ICs, in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2013), pp. 379–386 21. M. Pathak, J.S. Pak, D. Pan, S.K. Lim, Electromigration modeling and full-chip reliability analysis for BEOL interconnect in TSV-based 3D ICs, in 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2011), pp. 555–562 22. V. Sukharev, Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), 1326–1335 (2005) 23. Z. Sun, E. Demircan, M.D. Shroff, T. Kim, X. Huang, S.X.-D. Tan, Voltage-based electromigration immortality check for general multi-branch interconnects, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2016), pp. 1–7 24. Z. Sun, E. Demircan, M.D. Shroff, C. Cook, S.X.-D. Tan, Fast electromigration immortality analysis for multi-segment copper interconnect wires. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12), 3137–3150 (2018) 25. C.V. Thompson, S.P. Hau-Riege, V.K. Andleigh, Modeling and experimental characterization of electromigration in interconnect trees, in AIP Conference Proceedings, vol. 491 (AIP, 1999), pp. 62–73 26. X. Wang, H. Wang, J. He, S.X.-D. Tan, Y. Cai, S. Yang, Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks, in Proceedings of Design, Automation and Test In Europe (DATE) (IEEE, Piscataway, 2017) 27. F.L. Wei, C.L. Gan, T.L. Tan, C.S. Hau-Riege, A.P. Marathe, J.J. Vlassak, C.V. Thompson, Electromigration-induced extrusion failures in Cu/low-k interconnects. J. Appl. Phys. 104, 023529 (2008) 28. X. Zhao, Y. Wan, M. Scheuermann, S.K. Lim, Transient modeling of TSV-wire electromigration and lifetime analysis of power distribution network for 3D ICs, in 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD) (IEEE, Piscataway, 2013), pp. 363–370

Chapter 5

Dynamic EM Models for Transient Stress Evolution and Recovery

5.1 Introduction EM induced degradation of electric resistance in a variety of test structures is traditionally monitored by applying the DC stressing. A majority of proposed physical models describing the EM phenomenon have also assumed the DC load. At the same time all semiconductor integrated circuit (IC) chips operate with timedependent, for example, AC or pulse, electric currents. Today’s multi/manycore microprocessors are working on different performance states and are the subject for dynamic power/thermal management schemes. At the server and rack and even datacenter levels, many low power techniques such as the KnightShift architecture for scaling energy proportionality scheme using hybrid performance servers [26] and the big LITTLE technology from ARM at the chip level can create dynamic power, and, hence, across-die temperature profiles [1]. Such dynamic power/energy scheduling and provisioning could result in large variations in current density and temperature, which can have huge impacts on the EM-induced stress evolution in interconnect wires and, thus, affect the failure development. One important transient behavior in EM stress evolution is the recovery effect shown in Fig. 5.1. It refers to the stress relaxation or decreasing in the metal line, which occurs when the current is switched-off. It can be considered as the healing process extending the lifetime of interconnects. Manifestation of the recovery of EM-induced stress buildup has been observed and reported in many papers [10, 15, 17, 21]. This phenomenon is very visible when the wire is stressed by symmetric bidirectional (bipolar) pulse current waveforms. It becomes less obvious when the current waveforms are unidirectional (unipolar) characterized by the high frequencies (larger than kHz) [15, 17]. However, a lot of experimental works have found that when the frequencies of current waveforms are small enough (its period is about 100 s or longer), we can still see significant EM recovery, which extends the lifetime of the stressed wire [10]. Such low frequency power/temperature patterns

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_5

97

98

5 Dynamic EM Models for Transient Stress Evolution and Recovery

Fig. 5.1 Stress relaxation (EM recovery) when current is switched-off [12]

stress

ON

ON OFF

time

are typical today due to the proposed low power techniques at chip/server/rack levels, which can be operated at the time scale of minutes and hours. Emerging dark silicon also requires to keep cores at low power status for sufficient period of time [7]. However the lack of the solid EM transient models hinders the development of optimization techniques for such kind of effects. In this chapter, we propose a new physics-based dynamic compact EM model, which for the first time can accurately predict the transient hydrostatic stress recovery effect in a confined metal wire [12]. The transient recovery effect in the EM-induced stress evolution kinetics has never been modeled properly in all the existing analytical EM models, which assume the wire is stressed under constant current density and temperature. The new model is developed by the analytical solution of the one-dimensional Korhonen’s equation with the timevarying electric current and temperature loads [23]. The model can explain many of the experimentally observed transient stress recovery effects caused by various current waveform patterns [10, 15, 17]. More significantly, the new EM model opens new opportunities to manage EM reliability at the circuit, system, and even server/rack/datacenter levels without additional design costs.

5.2 Background and Review of Existing Works 5.2.1 Existing Modeling Based on Effective Direct Current Existing EM models such as the semi-empirical Black’s equation, which is widely used in industry, are based on the DC load of a single confined metal wire keeping at the constant temperature [2]. In order to consider the stress buildup caused by the transient current waveforms in a typical VLSI chip, which can be unipolar, such as in the power grid networks, or bipolar, such as in the signal nets, the timedependent current density waveforms are converted to the so-called EM effective DC current, Eq. (7.2.3). However, using the effective current formula in Eq. (7.2.3)

5.2 Background and Review of Existing Works

99

will create several problems [15]. First, the recovery factor depends on the specific current waveforms and is not constant. Second, it ignores important transient effects. For instance, we may have the driving current waveform, which makes the peak stress exceed the critical stress, while the average current never leads to void nucleation (wire is immortal). To mitigate this problem, a number of dynamic EM models, which consider the time-dependent current waveforms, have been presented [13, 16, 18]. However, the EM model in [18] is still based on traditional semi-empirical Black’s equation, where the current density exponent is not a constant but a function of residual stress and current density. Especially, the recovery effect is not properly considered and the weighted average current is still used. Recently, a new dynamic EM model was presented [5]. However, this model is based on Korhonen’s continuity equation with constant current density. It fails to predict stress recovery effect as we show in this work and inappropriately predicts increasing/constant stress when current changes are significant: reducing to a much smaller value or turning off.

5.2.2 EM Physics and Governing Equations EM is a physical phenomenon caused by current-induced atom diffusion in the direction of the electron flow due to momentum exchange between lattice atoms and charge carriers. This oriented atomic flow results in metal density depletion and accumulation at the ends of the wire, where the atomic migration is blocked by diffusion barriers. When the hydrostatic stress develops, the stress gradient along the wire would lead to the drift of lattice atoms in the direction opposite the direction of the electric current. As shown in Fig. 5.2, the steady state will be reached when the backward flux compensates the current-induced flux, and the stress will be linearly distributed along the wire. Figure 5.2a shows the stress evolution along the wire (with the left end as the cathode node and right as the anode node). This is a typical hydrostatic stress evolution pattern driven by DC current. But if the driving current is timevarying, the stress might not be monotonically increasing with time. For instance, if the current density is reduced at some instance in time, then the current-induced flux can be smaller than the stress gradient induced atomic backflow, and the atom migration direction can even be reversed leading to a reduction of the hydrostatic stress as shown in Fig. 5.1. Such transient recovery can make the stress evolution take longer time to reach to the critical stress for void nucleation. As a result, it can help extend the lifetime of the wires. Figure 5.2b shows the evolution of the electric current induced hydrostatic stress at the cathode end of a metal wire (biggest tensile stress) under different DC densities and temperatures. It indicates that both the current density and the temperature affect the stress evolution rate.

100

5 Dynamic EM Models for Transient Stress Evolution and Recovery

600 σcrit

stress (MPa)

400 200

t

0

t

-200 -400 -600

0

20

40 60 x (μm)

80

100

(a) 700 600 stress (MPa)

500 400 300 3×10 9A/m 2, 370K 4×10 9A/m 2, 370K 3×10 9A/m 2, 380K 4×10 9A/m 2, 380K

200 100 0

0

2

4

6 time (s)

8

10 4 ×10

(b) Fig. 5.2 Evolution of hydrostatic stress (a) along the wire and (b) at the cathode end over time stressed under different current densities and temperatures, in the case of zero initial stress [12]

5.3 New Model for the EM-Induced Stress Evolution Caused by Time-Dependent Current Density and Temperature In this section, we present the new dynamic EM model considering the timevarying current density and temperature. This model was originally derived from the analytical solution of the continuity equation (Eq. (2.3.10)) for a metal wire loaded by the time-varying electric current. We further extended the model to take into account the time-varying temperature. The resulting model can analyze the stress evolution kinetics caused by any time-varying currents and temperatures.

5.3 New Model for the EM-Induced Stress Evolution Caused by. . . Table 5.1 Parameters and typical values [12]

Parameter Ea Z σcrit l

Value 0.86 eV 10 400 MPa 1 × 10−4 m

Parameter B  ρ D0

101 Value 1 × 1011 Pa 1.66 × 10−29 m3 3 × 10−8  7.56 × 10−5 m2 /s

To validate the proposed model, detailed numerical simulation of the continuity equation (Eq. (2.3.10)) should be employed. Here, we do numerical simulation using the FEA tool COMSOL. Before we proceed, we list values of all employed parameter in Table 5.1. Also, to simplify our numerical analysis, we keep the thermal (residual) stress (σT ) equal to zero.

5.3.1 Generalized Model with the Arbitrary Piecewise Constant Current We first present the governing stress evolution equation with time-varying current waveforms. The stress evolution takes place in an initially void-less interconnect line. To simplify the analysis, we first assume that only the current density changes over time, i.e., the temperature is constant. Later on, we extend the derived stress evolution expression to consider time-varying temperature.

5.3.1.1

Dynamic EM Model Considering Arbitrary Time-Varying Currents

In the case of time-dependent current density, one-dimensional continuity equation (Eq. (2.3.10)) can be converted into the following nonhomogeneous form [23]:  ∂ σ+

eZρj   x

−

L 2



− σT

∂t   L ∂j eZρ x− =  2 ∂t



∂2 −κ 2 ∂x

    eZρj L σ+ x− − σT  2 (5.3.1)

eZρj with the boundary condition: ∂σ ∂t |x=0,L = −  and the initial condition: σ (x, t = 0) = σT . Here, κ = DB/kB T , where D = D0 exp(−Ea/kB T ) is the atomic diffusivity which depends on temperature. As it was shown in [23], Eq. (5.3.1) can be solved analytically. The analytical solution for stress evolution kinetics takes the form:

102

5 Dynamic EM Models for Transient Stress Evolution and Recovery ∞

σ (x, t) = σT +

4eZρ (2n + 1)π x − (2n+1)22 π 2 κ(τ −t) L κ e cos dτ L L n=0 ∞

= σT +

4eZρ (2n + 1)π x − (2n+1)22 π 2 κt L cos κ e L L n=0



t

×

j (t)e

(2n+1)2 π 2 κτ L2

(5.3.2)

dτ

0

Solution Eq. (5.3.2) is valid for any arbitrary time-varying current waveform j (t). It is not difficult to show that Eq. (5.3.2) converts to the standard stress evolution kinetics Eq. (2.3.10) if the current density is constant (DC current). In practical application, the current or power inputs of a chip are better modeled as time-varying piecewise constant as the chip may be in different stable performance/power states for a period of time instead of changing all the time. In this work, we divide a given time period [0, t] into i intervals and in each interval ti , we have constant temperature and current density. The time interval can be decided based on the computational complexity and precision requirement. A large interval is chosen at low frequency. Assume that we have computed the stress at ti−1 and want to predict the stress at ti = ti−1 + ti as shown in Fig. 5.3. Then we have the following iterative stress computation formula: σ (x, ti ) = σT +

∞ 4eZρ (2n + 1)π x φ(ti ) cos L L

(5.3.3)

n=0

where φ(ti ) = e

− (2n+1)2

2π2

L

κti

  κ 0

Fig. 5.3 A random time-dependent current density waveform where piecewise constant method can be applied [12]

ti

ji e

(2n+1)2 π 2 κτ L2

dτ + φ(ti−1 )

(5.3.4)

5.3 New Model for the EM-Induced Stress Evolution Caused by. . . Fig. 5.4 Stress evolution under time-varying current load with constant temperature [12]

j (A/m2)

6 ×10

103

9

4 2 T=373K

0

σ (MPa)

600 400 200 MODEL COMSOL

0

0

2

4

6

8

t (s)

10 4 ×10

and φ(t1 ) = e

− (2n+1)2 L

2π2

κt1

 κ

t1

j1 e

(2n+1)2 π 2 κτ L2

dτ

(5.3.5)

0

constant current density value during the time interval [ti−1 , ti ]. Here, ji is the ∞ (2n+1)π x Note that 4eZρ φ(ti−1 ) presents EM stress at ti−1 , which is caused 0 cos L L by the driving current j (t) from the very beginning (t = 0) to the time instant t = ti−1 . So the accumulated hydrostatic stress at the instant in time t = ti can be easily calculated based on Eq. (5.3.3) if φ(ti−1 ) is provided. Figure 5.4 shows an example of the stress evolution at the cathode end of the metal wire under time-varying current and constant temperature loads. The solution obtained from Eq. (5.3.3) agrees well with the result of numerical solution of Eq. (2.3.10).

5.3.1.2

Dynamic EM Model Considering Both Time-Varying Current and Temperature

Temperature affects atomic diffusivity and is reported to have huge (exponential) impacts on the lifetime of the wire due to EM effects [8, 11]. The on-chip temperature changes along with the change of chip workloads (power dissipation). Thus it is necessary to consider the effect of time-varying temperature in EM modeling. In this work, we employ the equivalent time scheme to account for the dynamic temperature effect, which uses expressions for stress buildup under constant temperature to describe the stress evolution under time-varying conditions [5, 18].

104

5 Dynamic EM Models for Transient Stress Evolution and Recovery

κ(T (t)) is the term that is affected by temperature: κ(T (t)) =

D0 exp(−Ea/kB T (t))B kB T (t)

(5.3.6)

It has been observed that, if the atomic diffusivity is assumed to be independent of the stress, the temperature impact on the stress σ (T , t) through κ(T (t)) can be translated to the time period change for a metal wire. In other words, as demonstrated in Fig. 5.5, the stress developed on the wire over time interval ti κ(Ti ) under temperature Ti is equal to the stress developed over time interval κ(T ti 1) under temperature T1 . As a result, the problem of analyzing stress evolution considering both time-varying current density and temperature becomes estimating stress evolution under dynamic current stress, while temperature is constant (T = T1 ), which has been discussed in Sect. 5.3.1.1. Thus we replace the time intervals κ(Ti ) ti in Eqs. (5.3.4) and (5.3.5) with new time intervals ti∗ = κ(T ti and apply 1) constant temperature T = T1 . The stress at ti considering time-varying current density and temperature can be calculated as: σ (x, ti ) = σT +

∞ 4eZρ (2n + 1)π x φ(ti ) cos L L n=0

Fig. 5.5 (a) Original time-dependent temperature waveform and (b) constant temperature with equivalent time intervals [12]

(5.3.7)

5.3 New Model for the EM-Induced Stress Evolution Caused by. . .

105

where φ(ti ) =e

− (2n+1)2

2π2

L



κ(T ) 1

κ(T1 ) κ(T i ) ti



κ(Ti ) κ(T1 ) ti

× κ(T1 )

ji e

(2n+1)2 π 2 κ(T1 )τ L2

 dτ + φ(ti−1 )

0

=e

− (2n+1)2

2π2

L

κ(Ti )ti

  × κ(T1 )

ti

ji e

κ(T ) (2n+1)2 π 2 κ(T1 ) κ(T i ) τ L2 1

0

=e

− (2n+1)2

2π2

L

κ(Ti ) dτ + φ(ti−1 ) κ(T1 )



(5.3.8)

κ(Ti )ti

  × κ(Ti )

ti

ji e

(2n+1)2 π 2 κ(Ti )τ L2

dτ + φ(ti−1 )

0

and φ(t1 ) = e

− (2n+1)2

2π2

L

κ(T1 )t1



t1

κ(T1 )

j1 e

(2n+1)2 π 2 κ(T1 )τ L2

(5.3.9)

dτ

0

Now we are able to predict the EM-induced stress evolution under time-varying current load with time-varying temperature based on Eq. (5.3.7). Figure 5.6 shows an example of the stress evolution at the cathode end of the metal wire caused

T

T1

4

T

2

j (A/m )

9 6 ×10

2

T

T 3

5

4

T

6

2

0

T= [370, 340, 350, 355, 365, 345] (K)

600

stress (MPa)

500 400 300 200 100 0

MODEL COMSOL

0

2

4

6 time (s)

8

10 ×104

Fig. 5.6 Stress evolution under time-varying current and temperature stressing [12]

106

5 Dynamic EM Models for Transient Stress Evolution and Recovery

by dynamic current load, which refers, for instance, to a core working in different power states. Since the time scale for each state is much longer than thermal time constant, we assume each state corresponds to a constant temperature value. We have compared the obtained analytical solution with the result of numerical solution of Eq. (2.3.10) with the known j (t) and T (t) and have gotten an excellent agreement as shown in Fig. 5.6. It can be observed from Eq. (5.3.8) that, different from the expressions in [5, 18] which need to translate the actual time intervals ti to the equivalent time intervals κ(Ti ) κ(T1 ) ti during the stress computation, the final expression of our proposed stress evolution model includes only the actual time-interval ti and the actual temperature Ti during the time interval ti . Besides, Eq. (5.3.8) differs from Eq. (5.3.4) only in that it uses a time-dependent temperature Ti instead of a constant temperature. Thus the proposed model naturally considers the temperature change. It also should be noted that the derived general discretization formula Eq. (5.3.7) can be applied to any time-varying current densities and temperature waveforms, and at the same time correctly predicts stress recovery effect, which is ignored in all existing ad-hoc methods [5, 18].

5.3.2 EM Modeling for Periodic Pulse Current Another interesting case is the driving currents are periodic pulse waveforms, which can be found in the typical clock networks and in some signal networks as well. In this case, the computation of the stress evolution can be simplified. Let’s consider, for instance, the current density profiles shown in Fig. 5.7, which are good approximations for real power traces in the practical situations. Specifically, we assume that the current density j (t) has the following form:  j (t) =

j1 , mP ≤ t < mP + t1 , j2 , mP + t1 ≤ t < (m + 1)P

(5.3.10)

We note that j1 and j2 can be in the same phase or in opposite phases of the pulse, P is the period of the current waveform. For large time scales, which is longer than thermal time constant, we can assume the temperature profile has similar form:  T (t) =

T1 , mP ≤ t < mP + t1 , T2 , mP + t1 ≤ t < (m + 1)P

(5.3.11)

5.3 New Model for the EM-Induced Stress Evolution Caused by. . . 9

6 ×10

×109 P

j1, T1

2

j (A/m )

4

T1 = 373K, T2 = 363K

t1 t2

2

j2, T2

2 0

T2 (343K)

600

500

500

400 300 200 MODEL COMSOL

100 0

400 300 200

1

2

3

4

5 ×104

time (s)

MODEL COMSOL

100 0

0

T1 (373K)

4

0 600

stress (MPa)

stress (MPa)

2

j (A/m )

6

107

0

1

2

3 time (s)

(a)

4

5 ×10

4

(b) ×10

9

2

j (A/m )

5 0 -5

T = 373K

stress (MPa)

400 200 0 -200 -400

MODEL COMSOL

0

1

2

3 time (s)

4

5 ×104

(c) Fig. 5.7 Stress evolution caused by (a) periodic, (b) unipolar, and (c) symmetrical bipolar pulse current densities at cathode end of the metal line [12]

In this case, the stress evolution expression considering periodic pulsed current waveform can be derived based on Eq. (5.3.7): • If mP ≤ t < mP + t1 (τ = t − mP ): ∞ 4eZρ (2n + 1)π x − (2n+1)22 π 2 κ1 τ L e cos σ (x, t) = σT + L L n=0    τ (2n+1)2 π 2 κ1 τ˜ × κ1 j1 e L2 d τ˜ + MφP 0

(5.3.12)

108

5 Dynamic EM Models for Transient Stress Evolution and Recovery

where φP = e

− (2n+1)2

2π2

L

+e

− (2n+1)2

(κ1 t1 +κ2 t2 )

2π2

L

κ2 t 2



t1

κ1

j1 e

(2n+1)2 π 2 κ1 τ˜ L2

d τ˜

0



t2

κ2

j2 e

(2n+1)2 π 2 κ2 τ˜ L2

d τ˜

0

• If mP + t1 ≤ t < (m + 1)P (τ = t − mP − t1 ): ∞ 4eZρ (2n + 1)π x − (2n+1)22 π 2 κ2 τ L e cos L L n=0    τ (2n+1)2 π 2 κ2 τ˜ × κ2 j2 e L2 d τ˜ + φ1 + MφP

σ (x, t) = σT +

(5.3.13)

0

where φ1 = e

− (2n+1)2

2π2

L

κ1 t 1



t1

κ1

j1 e

(2n+1)2 π 2 κ1 τ˜ L2

d τ˜

0

φP = e

− (2n+1)2 L

2π2

(κ1 t1 +κ2 t2 )

  × φ1 + κ2

t2

j2 e

(2n+1)2 π 2 κ2 τ˜ L2

 d τ˜

0

In both cases, we have

t2 = P − t 1

M=

1−e

−(2n+1)2 π 2 m(κ1 t1 +κ2 t2 ) L2

1−e κ1 =

D0 e

− k EaT

B 1

k B T1

B

−(2n+1)2 π 2 (κ1 t1 +κ2 t2 ) L2

κ2 =

D0 e

− k EaT

B 2

B

k B T2

The proposed model for periodic pulse current has been validated by results of numerical simulations as shown in Fig. 5.7. Figure 5.7a and b corresponds to unipolar pulsed current density waveforms, where the former one has two nonzero magnitudes, while Fig. 5.7c is the case of symmetrical bipolar pulsed current density. Significant stress variation caused by dynamical current loads is observed. We will discuss this phenomenon in the next section.

5.4 Study of the EM Stress Recovery EM process is composed of the void nucleation phase followed by the void growth. As it was mentioned above, the void is generated from the preexisting flaw existing in the metal when the EM-induced hydrostatic tensile stress exceeds the critical one.

5.4 Study of the EM Stress Recovery

109

We now analyze the EM stress recovery process focusing on the first phase where the void has not been nucleated. The recovery effect of hydrostatic stress, which is described in this subsection, is based on the proposed new dynamic EM model.

5.4.1 EM Stress Recovery Effect As shown in the previous sections, EM recovery will take place when the current density goes down temporarily. In Fig. 5.7, the hydrostatic stress is reduced when the current density jumps from j1 to a much smaller value j2 . As a result, it takes longer time for the stress to reach the critical value, thus results in a longer lifetime. The EM recovery effect is mainly caused by the net atomic backflow, which relaxes the stress. This phenomenon can be easily understood when atoms change their migration direction in the opposing phase of bipolar stressing. On the other hand, even when j1 and j2 are in the same direction, it is still possible that the net atom flow can change their direction. The reason is that when current is decreasing, the atomic backward flux caused by an accumulated stress gradient will prevail the electronic current-induced flux and we will have a temporal reduction in the stress. Figure 5.8 shows the analysis of the stress recovery for a single pulse current case. Figure 5.8a refers to the schematics for current density and temperature. To further study the recovery effects, we first fix the temperature and investigate EM recovery under different magnitudes of current density change as shown in Fig. 5.8b. Then we investigate the impact of temperature on stress evolution considering different current loads. Figure 5.8c describes the stress recovery when current is switched off, while Fig. 5.8d corresponds to constant current stressing. The observations are summarized as follows: • There could be no stress recovery when current density difference is small, for example, the j2 /j1 = 0.95 curve in Fig. 5.8b. This is because the electron flow induced forward flux can be still larger than the stress gradient induced backward flux when current density reduces from j1 to j2 . Thus the atoms keep diffusing from the cathode end to the anode end along the metal line, resulting in continuous accumulation of the stress. The backward atomic flux caused by stress gradient could be larger than the current-induced forward flux if the current density difference is significant, where an extreme case is the current is switched off at an instant in time t = t ∗ . This atomic backflow will be gradually reducing over time and finally the system will reach a new equilibrium state corresponding to the new current density. • As shown in Fig. 5.8c, the accumulated stress starts to relax when current is turned off. This process is described by an exponential decay with the time (2n+1) constants τ0 = l 2 /κπ 2 (2n + 1)2 = τ0 /(2n + 1)2 , determined by the atomic diffusivity. We observe that higher temperature can speed up atom diffusion toward the cathode end and lead to more recovery. This is contrary to the non-recovery case, for instance, the metal wire stressed by constant current

110

5 Dynamic EM Models for Transient Stress Evolution and Recovery 0.2 0.4 0.6 0.8 0.95 1

500 stress (MPa)

j 2 / j 1:

400

T 1 = T 2 = 373K

300 200 100 0

0

2

4

6

8

10 ×104

time (s)

(a) 350

500

j = 3×10 9A/m 2, j = 0 1

300

T1 = 373K

250

2

T = 373K

400

2

T = 343K 2

stress (MPa)

stress (MPa)

(b)

200 150 100

300 200 9

j 1 = j2 = 3×10 A/m

100

50

T1 = 373K

0

0

2

4 6 time (s)

8

10 4 ×10

0

0

2

(c)

4 6 time (s)

2

T2 = 373K T2 = 343K

8

10 ×10 4

(d)

Fig. 5.8 (a) Time-dependent current density and temperature waveform, (b) EM recovery considering different current density change magnitude at constant temperature, (c) stress relaxation when current is switched off at different temperatures, and (d) stress evolution caused by DC current at different temperatures [12]

as demonstrated in Fig. 5.8d, where higher temperature results in faster stress accumulation, thus a shorter lifetime.

5.4.2 Limitation of Using Effective DC Methods For unidirectional current, the time-averaged or other weighted averaged currents have been used as the effective DC in existing EM analysis. However, we show in this subsection that using the effective DC for failure predication and immortal wire detection can lead sometime to wrong results. It is well known that the Blech rule has been employed for the out filtration of immortal wire segments with diffusion blocking boundaries [3]. The interconnect will not fail if the product of (j × L) is smaller than the critical value, as shown

5.4 Study of the EM Stress Recovery

500 σcrit

400 stress (MPa)

Fig. 5.9 (a) Stress evolution at the cathode end of the metal line caused by the unipolar pulse current (UPC) with duty cycle = 30% and averaged DC current, (b) EM lifetimes for UPC load with various duty cycles compared with lifetimes caused by constant peak current load. Here, javg is fixed to 2.5 × 109 A/m2 so that (javg × L) < (j × L), T = 373 K [12]

111

300 200 100 0

UPC, duty cycle = 30% 9 2 javg = 2.5× 10 A/m

0

2

4

6 time (s)

8

10 ×104

(a)

10

×10

tf (s)

8

4

UPC , j = 2.5× 109A/m2 avg j peak

6 4 2 0 0.001

0.01

0.1

1

duty cycle (b)

in Eq. (2.2.3). Now let’s look at one particular case. Assuming at a constant temperature, we set the average current density (javg ) to 2.5 × 109 A/m2 so that (javg × l) < (j × l)crit , which means that the metal line is EM immortal under the average current model using the Blech rule. However, based on the proposed dynamic model, which is also the actual numerical analysis results as shown in Fig. 5.9a, we find that stress can go above the critical stress σcrit , indicating that the void will be nucleated in this case. Note that the kinetics of stress evolution is caused by unipolar pulse current of 30% duty cycle in Fig. 5.9a. Figure 5.9b further shows the lifetimes of a wire caused by UPC under different duty cycles (duty cycle = 1 means DC current) with the same average current density using the proposed EM model. We also show the lifetime of a wire caused by the peak current of the UPC. From the figure, we can observe that the wire would fail by

112

5 Dynamic EM Models for Transient Stress Evolution and Recovery

UPC stressing when duty cycle ≤40% (when the curve starts to appear in the figure). However, if we use the average current density for the calculation, as shown in the previous figure, the wire will never fail by EM. So the effective DC method can lead to optimistic EM estimation, which can be dangerous for practical EM signoff. On the other hand, simply applying worst-case current density would lead to too conservative results, limiting the design space for reliability-performance trade-off. Traditionally, the EM failure for a single confined metal line is considered as, for example, 10% line resistance increase. So far, we have discussed a phenomenon of the void nucleation, which by itself cannot increase the line resistance. Void growth following its nucleation is responsible for this increase. As it was shown in [11], it is pretty straightforward to account the void volume growth for the accurate estimation of the line lifetime. But, taking into consideration the noticeable redundancy existing in on-chip interconnects, we can conclude that the failure of an individual line of the power/ground grids cannot result in the interconnect failure. New criterion for the EM-induced chip failure was proposed in a number of works, see, for example, [4, 11]. To be more specific, EM-induced voltage drop degradation above the spec should be considered as the failure criteria for the full-chip EM assessment [11]. All above results were obtained for the low frequency currents with time intervals comparable to time constant τ0 , which is close to minutes or hours. Time-varying current or power profiles in those cases are more likely to be caused by power/energy management at server/rack/datacenter levels, where the currents under analysis are mainly carried by the power/ground nets. However, the chip level power management and scheduling may operate at millisecond level and chip clocks may operate in the MHz and GHz ranges. Figure 5.10 analyzes the stress evolution in a metal line caused by UPC and symmetrical BPC at 1 MHz frequency, which corresponds to the signal lines in the circuit. We can observe from the figure that, at high frequencies, the averaged DC currents can be good estimations of the unipolar and bipolar pulsed currents. In this case, the time-dependent current induced stress fluctuates (∼0.01 MPa) around the curve, which describes the stress evolution generated by the effective DC current. This is because at high frequencies, the time intervals are much shorter than τ0 so that the system cannot reach a new equilibrium state corresponding to the new applied current by means of atom diffusion. In Fig. 5.10b, stress fluctuates around zero for symmetrical bipolar pulse current. It indicates complete EM recovery during current reversal, and has been experimentally observed in [17]. Thus high frequency symmetrical bipolar current will not cause EM failure in interconnects.

5.4.3 Resistance Degradation Caused by the Symmetrical Bidirectional Current The results, that were obtained above, indicate that even long metal lines loaded with the symmetrical bipolar pulse or AC currents will never fail since the EM-

5.4 Study of the EM Stress Recovery 0.04 UPC, duty cycle = 50% javg

0.035 0.03 stress (MPa)

Fig. 5.10 Stress evolution at the cathode end of the metal line caused by unipolar pulse (UPC) with duty cycle = 50% and symmetrical bipolar pulse current (BPC) loads at T = 400 K [12]

113

0.025 0.02 0.015 0.01 0.005 0

0

0.5

1

1.5 time (s)

2

2.5 3 -5 ×10

2

2.5 3 -5 ×10

(a) 0.05 symmetric BPC

stress (MPa)

0.03 0.01 -0.01 -0.03 -0.05

0

0.5

1

1.5 time (s)

(b)

induced accumulation of the critical stress required for voiding or hillock formation is never happened. Nevertheless there are a good number of papers providing the experimental proof of failures generated by this type of stressing [9, 15, 16, 25]. One of the possible answers for this paradox can be found in the paper of Moning et al. [20], where the identical defects were found in all three lines located in a close proximity to each other in the test structure with two outer lines loaded with the sinusoidal voltages and the middle line was not carrying any current. The temperature oscillations generated by the outer lines have resulted in the identical defects in all three lines. The authors have concluded that the thermal fatigue controlled by diffusive mechanism and interface properties was responsible for these defects. A difference between these fatigue-based defects and the EM-induced voids is a mobility of the latter under the action of electric current, which can be observed, for example, by SEM studies [19]. Another possible mechanism of failure caused by symmetrical bidirectional currents is the growth of a void, which was formed in the line as the result of thermal stress relaxation. Very short metal lines with preexisting thermal voids, loaded with

114

5 Dynamic EM Models for Transient Stress Evolution and Recovery

such bidirectional currents, can demonstrate a notable resistance increase when a specific temperature oscillation is generated. In order to prove the existence of this mechanism, we need to develop a formalism describing an evolution of the metal line resistance caused by the current induced evolution of the void volume. As it was discussed in [24], a metal line embedded in the rigid confinement and cooled from the zero stress temperature down to the test temperature can reach two different states of equilibrium. One of them is the state with a uniformly distributed tensile stress, which was generated in the line due to a difference in the coefficients of thermal expansion of the metal and surrounding. Another one is characterized by the presence of a void, whose volume is determined by the relaxation of the preexisting tensile strain, and by zero stress everywhere else in the metal. It should be mentioned that generated thermal stress should exceed the critical stress, which is required for void nucleation. The latter state is the only stable equilibrium state for the metal line with the large tensile stress. When an electrical stressing is applied to this line, a void, if it is located at the line end, starts changing its volume. In the case of DC stressing, a void located at the cathode end of line will be growing by means of migration of the void surface atoms to the metal bulk. In the case of time-dependent current densities loaded to the line with the preexisting void, a calculation of the stress evolution is done in the way very similar to that was used for the calculation of stress evolution in the void-less case, considered in Sect. 5.3. Conversion of the stress distribution obtained from the solution of Eq. (5.3.1), with the zero stress and zero flux BC at the void edge and the anode end of line correspondingly, to the void volume evolution through +L V (t) = − 0 σ (x,t) B dx, and, then, to the kinetics of the resistance change, provides the following results: for the general case time-dependent current density j (t): (global time is t)  ρTaN ρCu − HTa (W + 2H ) W H  t ∞ 2 2 (−1)n κ (2+1)2 π τ 4L j (t)e dτ × 2 2 −κ (2+1)2 π n=1 (2n + 1)e 4L t 0

4eZρDa R = − π kB T



(5.4.1)

and for resistance relaxation after switching off the electric current at t+ : (global time is t ≥ t+ )  ρTaN ρCu − HTa (W + 2H ) W H  t+ ∞ 2 2 (−1)n κ (2+1)2 π τ 4L j (t)e dτ × 2 2 −κ (2+1)2 π n=1 (2n + 1)e 4L t 0

R = −

4eZρDa π kB T



(5.4.2)

Figure 5.11 shows the kinetics of line resistance change caused by a random timedependent current, Fig. 5.11a, and by switching off the applied current, Fig. 5.11b.

5.4 Study of the EM Stress Recovery

115

2

6 ×10 5 4 3 2 1 0 0

9

2

4

6

8

10 4

×10

Δ R (Ω)

0.2 0.15 0.1 0.05 0

0

2

4

6

8

10 4

×10

(a) 0.18 0.16 0.14 0.12

Δ R (Ω)

Fig. 5.11 (a) Short line resistance evolution caused by a random set of current densities, (b) relaxation of the resistance change accumulated during 2 × 104 s of j = 5 × 109 A/m2 stressing. T = 400 K for both cases [12]

j (A/m )

Figure 5.12 shows the resistance increase caused by the high frequency symmetrical BPC, which is synchronized with a specific temperature oscillation: the positive pulse of the current occurs at higher temperature than the negative pulse. It destroys the symmetry of the bidirectional change of the void volume caused by a transfer of atoms between the void surface and metal bulk. The resistance increase shown in Fig. 5.12 is happened when the current positive pulses forcing atoms to move from the void surface into the metal in the direction toward the anode end of line occur at T = 450 K, while the negative pulses pushing atoms back on the void surface take place at lower temperature of T = 400 K. We use this ideal but unrealistic synchronized current-temperature dynamics just to illustrate a possible mechanism of resistance degradation in short metal lines loaded with the

0.1 0.08 0.06 0.04 0.02 0

0

1

2

3

t (s)

(b)

4

5 4 ×10

5 Dynamic EM Models for Transient Stress Evolution and Recovery 0.16 0.14 0.12 0.1

6

0.08

Δ R (Ω)

Fig. 5.12 1 MHz symmetrical BPC load with j+ = 5 × 109 A/m2 , j− = −5 × 109 A/m2 , t+ = t− = P /2, T+ = 450 K, T− = 400 K [12]

Δ R (Ω)

116

0.06

×10

-9

4 2

0.04 0

0.02

0

0.5

t (s) 0

0

500

1000

1500 t (s)

2000

1

×10

2500

-5

3000

symmetrical BPC. In reality, we can expect a variety of temperature oscillations inside on-chip interconnect due to a sporadic character of switching off many millions of transistors, whose locations are distributed through the chip layout. Such irregular temperature oscillations can cause asymmetry in the void shrinkingadvancing and, in some cases, can be responsible for void growth above the critical size, corresponding to the threshold increase of the line resistance.

5.5 Application for System Level Reliability Aware Computing Now we present a potential application of the proposed EM model for reliabilityaware energy-efficient computing at the server level. We look at the KnightShift architecture [26], which is a server-level heterogeneous server architecture that introduces an active low power mode using the additional computing node called the Knight. KnightShift enables two energy-efficient operating regions from two different CPUs. Figure 5.13 [26] shows the power trace a KnightShift architecture will generate, where the Knight is a node with a 1.8 GHz Intel Atom D525, which operates from 15 to 16.7 W, and the CPU and memory consumes 9 W at idle, while the primary node corresponds to dual 2.13 GHz 4-code Intel Xeon L5630 that consumes from 156 to 205 W at active mode. The main benefit of the KnightShift architecture is that the primary node can be powered off to save energy during the light demands and Knight can still operate to take the light loads. If the both power-on and shut-down time can be properly managed and controlled such that performance can still be maintained, then we can significantly extend the server reliability by leveraging the EM recovery effects, predicted by the proposed model. Note that KnightShift can also place the primary server in suspend mode quicker than shutting down, but at the cost of higher idle

5.6 Summary

117

system power consumption

KnightShift Architecture Power Trace

Xeon Active Mode

Xeon Active Mode

Xeon turned-off Knight-Mode on

2.13GHz 4-core Intel Xeon L5630 1.8GHz Intel Atom D525

time

Fig. 5.13 Power trace in KnightShift server [12]

power. For the sake of illustration, we only consider the shut-down situation in this work. Specifically, we present two different power traces for the Xeon CPU based on [6] for our analysis. As demonstrated in Fig. 5.14a, the two traces are different in that the Xeon CPU is working during ta and tb in case 1 and is turned off in case 2. The temperature is assumed to be 363 K when Xeon node is active and 340 K when it is off [22]. During this period (ta and tb ), the task loads could be taken over by the Knight node when the demand is light or by other primary node in a server cluster for heavy demands. Such power-off period not only leads to energy saving, it also can be served as the recovery period for EM effect to extend the lifetime of the chip. Indeed, by using the proposed EM model, we find that the interconnect lifetime in case 2 can be extended to be 42% longer than that of case 1 due to EM recovery during ta and tb as shown Fig. 5.14b. For each CPU, if we can extend the poweroff periods even longer or reduce the power-on periods while still maintaining the performance requirement, we can achieve both energy saving and much longer lifetime (even immortal EM-induced life). As a result, the new EM recovery model can lead to more opportunities for system level reliability optimization or combined energy and reliability management and optimization.

5.6 Summary In this chapter, we proposed the new model for EM-induced degradation, which for the first time accounts for the transient stress recovery effect. Nowadays the recovery effect becomes more significant and relevant due to available low power and energy optimization and management techniques at multiple system levels. The

5 Dynamic EM Models for Transient Stress Evolution and Recovery

core power consumption (W)

118 150

case 1

case 2

100

ta

t

b

50

0

0

500

1000

1500

2000

2500

3000

time (scaled)

(a) 1.5 tf2

tf1

stress (scaled)

42%t f1

σ crit

1

0.5

case 1 case 2

0

0

500

1000

1500

2000

2500

3000

time (scaled)

(b) Fig. 5.14 (a) Two cases of the power trace for Xeon node and (b) the resulting hydrostatic stress evolution kinetics in the interconnect, where current density is assumed to be 4 × 109 A/m2 [12]

new dynamic model is based on the direct analytical solution of the Korhonen’s equation with arbitrary unipolar or bipolar current loads at varying temperatures. We demonstrated that the recovery effect can be quite significant even under time-dependent unidirectional current loads. Large difference in current densities and high temperature during the healing process will lead to a more complete recovery. Such effect can be further leveraged to extend the lifetime of the onchip interconnect if the driving powers will be properly controlled and managed at the runtime. Our numerical results showed that the results generated by the proposed analytical model agree well with the numerical analysis results under any time-varying current densities and temperature profiles. Potential applications of the proposed model were demonstrated.

References

119

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21. Y.-J. Park, K.-D. Lee, W.R. Hunter, A variable current exponent model for electromigration lifetime relaxation in short Cu interconnects, in International Electron Devices Meeting (IEDM’06) (2006), pp. 1–4 22. D. Shin, J. Kim, N. Chang, J. Choi, S.W. Chung, E.-Y. Chung, Energy-optimal dynamic thermal management for green computing, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2009), pp. 652–657 23. V. Sukharev, X. Huang, S.X.-D. Tan, Electromigration induced stress evolution under alternate current and pulse current loads. J. Appl. Phys. 118, 034504 (2015) 24. Z. Suo, Reliability of Interconnect Structures. Comprehensive Structural Integrity, vol. 8 (Elsevier, Amsterdam, 2003) 25. J. Tao, N. Cheung, C. Hu, Metal electromigration damage healing under bidirectional current stress. Appl. Phys. Lett. 14(12), 554–556 (1993) 26. D. Wong, M. Annavaram, KnightShift: scaling the energy proportionality wall through server-level heterogeneity, in 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) (IEEE, Piscataway, 2012), pp. 119–130

Chapter 6

Compact EM Models for Multi-Segment Interconnect Wires

6.1 Introduction Many researches have been devoting to derive exact and approximate mathematical models for the electromigration nucleation process for a single, straight-line structure investigated in reliability analysis. However, obtaining analytical solutions for electromigration-induced stress evolution in general interconnect structure is extremely difficult (if not impossible). Korhonen, for example, developed an analytical model for straight-line interconnects under the assumptions of constant temperature and current density [10]. For more complex VLSI interconnect trees such as circuit-like interconnects with multi-segments [12, 13, 16], conservative analytical models are needed to analyze mechanical stress evolution during electromigration. Also, a new technique for EM assessment in power delivery networks of VLSI systems has been reported in [8, 9]. However, it did not give an accurate analytical form to model a multi-segment interconnect tree. Analytical model for describing stress evolution process of multi-branch interconnect tree has been studied in [2, 3], but this new analytical model needs to assume that each wire segment in the interconnect tree has the same length. Analytical model for multi-branch tree with different lengths of wire segments is still an unsolved problem. In [2, 3], a Laplace transform based method has been presented for analytical modeling and analysis of the straight-line three-terminal wires, the T-shaped four-terminal wires, and the cross-shaped five-terminal wires, which assumes that each wire segment in the interconnect tree has the same length. The EM behavior of three-terminal Cu interconnect trees was described in [1, 6] and the effects of different current density and segment length in a three-terminal interconnect were experimentally studied. But they did not provide accurate analytical modeling and analysis techniques for three-terminal interconnect trees in which the wire segments had various finite lengths and did not consider the effects of time-varying temperatures on the calculation of stress evolution by electromigration. © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_6

121

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In this chapter, we present the analytical model for stress evolutions of interconnect tree wires with varying wire segment lengths under time-varying temperature stressing conditions. This new method first solves the stress evolution equation (Korhonen’s equation) considering different current density and varying segment length in three-terminal interconnect tree by decoupling the individual segments through the boundary conditions. The resulting equations are then solved with the Laplace transformation technique and the analytical solution can be represented by a set of auxiliary basis functions using the known complementary error function. The evolutions of tensile and compressive stresses are simulated for several cases with different current densities and segment lengths. Furthermore, we present the new model to consider time-varying temperature stressing condition and initial non-zero residual stress [4]. On top of this, we further present analytical EM model for void nucleation phase for more general multi-segment star-liked interconnect trees including the straightline three-terminal wires, the T-shaped four-terminal wires, and the cross-shaped five-terminal wires. The proposed closed-form expression can be used to calculate the hydrostatic stress evolution with time-varying temperature [17]. We further present another closed-form EM stress solution based on integral transform technique, which could efficiently calculate the hydrostatic stress evolution over time for straight-line multi-segment metal wires stressed with different current densities. The new method can also naturally consider the preexisting residual stresses coming from the thermal or other stress sources [20]. The method was also extended to consider more general two-dimensional interconnect wire trees and can consider non-uniform temperature distributions in the wires [23].

6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree In this section, we will develop an exact analytical model that can be applied to study the electromigration-induced reliability of three-terminal interconnect tree with various wire segment lengths during the void nucleation phase. The effects of current density and segment length configurations on stress evolution at the void nucleation phase will be considered for this type of interconnect tree by the present analytical model.

6.2.1 Analytical Model for Stress Evolution Process We now develop an exact closed-form solution for the EM-induced stress analysis of a three-terminal interconnect tree with two wire segments with different segment lengths as showed in Fig. 6.1. The two segments which are interacted by the

6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree

123

Fig. 6.1 Three-terminal interconnect tree with two wire segments [4]

rest of the circuit may not have the same current density. For this three-terminal interconnect tree with two wire segments, the following two partial differential equations based on Korhonen model [10] can be used to describe the stress evolution process in the two wire segments:    ∂σ1 (x, t) ∂ ∂σ1 (x, t) = + G1 , −L1 < x < 0, t > 0, κ1 ∂t ∂x ∂x    ∂σ2 (x, t) ∂σ2 (x, t) ∂ κ2 = + G2 , 0 < x < L2 , t > 0 ∂t ∂x ∂x

(6.2.1)

Equations (6.2.1) are formally very similar to the familiar partial differential equation for diffusion with the diffusivities κ1 and κ2 replacing the conventional diffusion coefficients. For the sake of simplicity, we need to assume that each segment in the three-terminal interconnect tree has the same diffusivity, that is, κ1 = κ2 = κ. In order to ensure that this assumption is met, the temperature for each segment should be kept the same due to the fact that the diffusion coefficient in metal (Cu) lines depends on the temperature. For the void nucleation phase, we need to consider the case of the three-terminal Da  ∂σ (x,t) interconnect tree where the atom flux is blocked at both ends, that is, kT ∂x +  G |x=−L1 ,L2 = 0. The stresses in the two wire segments will interfere with each other, which can be reflected in the stress value at the intersection “o.” The BC of the equations (6.2.1) for the void nucleation phase are then found to be  κ1

∂σ1 (x, t) + G1 ∂x

 = 0, at x = −L1 , t > 0,

σ1 (x, t) = σ2 (x, t), at x = 0, t > 0,     ∂σ1 (x, t) ∂σ2 (x, t) + G1 = κ2 + G2 , at x = 0, t > 0, κ1 ∂x ∂x   ∂σ2 (x, t) κ2 + G2 = 0, at x = L2 , t > 0 ∂x

(6.2.2)

The first and fourth equations in (6.2.2) imply that blocking boundary conditions for the void nucleation phase are required, such that the atom fluxes are zero at both the ends. The second equation in (6.2.2) ensures that stresses at the intersection point of the two wire segments are continuous. The third equation in (6.2.2) means that the atomic fluxes are also continuous at the intersection. To obtain the analytical

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6 Compact EM Models for Multi-Segment Interconnect Wires

solution of (6.2.2), we assume that the initial conditions (IC) are given by: σ1 (x, 0) = 0, −L1 < x < 0,

(6.2.3)

σ2 (x, 0) = 0, 0 < x < L2

which means that there is no stress everywhere in each line segment at t = 0. The IC for stress evolution is that there is no driving force for the sink or source reactions when electromigration in the void nucleation phase starts. With the BC (6.2.2) and the IC (6.2.3), we consider the exact time-dependent solutions for the equations (6.2.1) by the Laplace transform technique. For t ≥ 0, the Laplace + +∞transform of the function σi (x, t) (i = 1, 2) is defined by σˆ i (x, s) = 0 e−st σi (x, t)dt. Instead of solving directly for σi (x, t), we derive new equations for σˆ i (x, s). Once we find σˆ i (x, s), we use inverse transform to determine σi (x, t). The first step is to take the Laplace transform of both sides of the original partial differential equations (6.2.1) with the IC (6.2.3). Hence, we obtain the ordinary differential equations d 2 σˆ 1 (x, s) s = σˆ 1 (x, s), −L1 < x < 0, κ1 dx 2 d 2 σˆ 2 (x, s) s = σˆ 2 (x, s), 0 < x < L2 κ2 dx 2

(6.2.4)

The particular solutions can be determined using variation of parameters or the method of undetermined coefficients. Solving for σˆ i (x, s) in (6.2.4), we have ,

σˆ 1 (x, s) = A1 e ,

σˆ 2 (x, s) = A2 e

s κ1 x s κ2 x

+ B1 e + B2 e

, − κs x 1

,

, − κs x

(6.2.5)

2

where the coefficients A1 , A2 , B1 , and B2 are determined by the BC (6.2.2). In order to obtain the undetermined coefficients, we need to take the Laplace transform for the BC (6.2.2): d σˆ 1 (x, s) G1 + = 0, at x = −L1 , dx s σˆ 1 (x, s) = σˆ 2 (x, s), at x = 0,     d σˆ 1 (x, s) G1 d σˆ 2 (x, s) G2 + + = κ2 , at x = 0, κ1 dx s dx s d σˆ 2 (x, s) G2 − = 0, at x = L2 dx s

(6.2.6)

6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree

125

Substituting the expressions σˆ 1 (x, s) and σˆ 2 (x, s) from (6.2.5) into (6.2.6), we obtain the following linear system: ⎡

−ad1 ⎢ ⎢0 0 ⎢ ⎣ a −a 1 1 a d1

0 ad2 −a −1

0 − da2 a −1

⎤⎡

⎤ ⎡ ⎤ A1 −c1 ⎥⎢ ⎥ ⎢ ⎥ ⎢ B1 ⎥ ⎢ −c2 ⎥ ⎥ ⎥⎣ ⎦ = ⎣ c2 − c1 ⎦ ⎦ A2 B2 0

(6.2.7)

, √s Gi s κ Li (i = 1, 2). Solution of the linear where a = κ , ci = s , and di = e system (6.2.7) yields these coefficients: A1 = B1 = A2 = B2 =

−2c1 d1−1 d2−2 + (c1 − c2 )d2−2 + 2c2 d2−1 + (c1 − c2 ) −2a(1 − d1−2 d2−2 )

,

(c1 − c2 )d1−2 d2−2 + 2c2 d1−2 d2−1 + (c1 − c2 )d1−2 − 2c1 d1−1 −2a(1 − d1−2 d2−2 )

(c1 − c2 )d1−2 d2−2 − 2c1 d1−1 d2−2 + (c1 − c2 )d2−2 + 2c2 d2−1 −2a(1 − d1−2 d2−2 )

, (6.2.8) ,

2c2 d1−2 d2−1 + (c1 − c2 )d1−2 − 2c1 d1−1 + (c1 − c2 ) −2a(1 − d1−2 d2−2 )

An analytical method based on the Laplace transform technique has been developed for the EM-induced stress evolution problem of the three-terminal interconnect tree, when the IC (6.2.3) are given and the BC (6.2.2) are known at the three terminals. On the basis of these known coefficients Ai and Bi , the closedform solution can be determined from (6.2.5) for each segment by using the inverse Laplace transform technique. In order to derive the analytical solutions σ1 (x, t) and σ2 (x, t), we will start by introducing the notations: ξ1 (x, n) = (2n + 1)L1 + (2n + 2)L2 − x, ξ2 (x, n) = (2n)L1 + (2n + 2)L2 − x, ξ3 (x, n) = (2n)L1 + (2n + 1)L2 − x, ξ4 (x, n) = (2n)L1 + (2n)L2 − x, ξ5 (x, n) = (2n + 2)L1 + (2n + 2)L2 + x, ξ6 (x, n) = (2n + 2)L1 + (2n + 1)L2 + x, ξ7 (x, n) = (2n + 2)L1 + (2n)L2 + x, ξ8 (x, n) = (2n + 1)L1 + (2n)L2 + x, η1 (x, n) = (2n + 2)L1 + (2n + 2)L2 − x,

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6 Compact EM Models for Multi-Segment Interconnect Wires

η2 (x, n) = ξ1 (x, n), η3 (x, n) = ξ2 (x, n), η4 (x, n) = ξ3 (x, n), η5 (x, n) = ξ6 (x, n), η6 (x, n) = ξ7 (x, n), η7 (x, n) = ξ8 (x, n),

(6.2.9)

η8 (x, n) = (2n)L1 + (2n)L2 + x where x is a location in the three-terminal interconnect tree and n is a nonnegative integer. These functions ξi and ηi (i = 1, 2, . . . , 8) are previously determined from the location x and the nonnegative integer n. Also we need to introduce the + +∞ 2 complementary error function which is defined as erf c{x} = √2π x e−t dt. In mathematics, the complementary error function is a special function that can be used in probability, statistics, and partial differential equations describing diffusion. Based on the complementary error function, we construct the following basis function:   κt − x 2 x 4κt (6.2.10) g(x, t) = 2 e − x × erf c √ π 2 κt It would be necessary to say why the basis function shown in (6.2.10) is adopted instead of a trigonometric function in terms of location and time for calculating the analytical solution for each segment in the three-terminal interconnect tree. The reason is that a general solution for the stress evolution equation for this tree type is provided in a functional form of g(x, t). By using these functions ξi (x, n), ηi (x, n), and g(x, t), we can obtain the exact analytical solutions for the stress evolution in both segments: +∞

σ1 (x, t) = −

1 {−2G1 g(ξ1 , t) + (G1 − G2 )g(ξ2 , t) 2 n=0

+ 2G2 g(ξ3 , t) + (G1 − G2 )g(ξ4 , t)} +∞

1 − {(G1 − G2 )g(ξ5 , t) + 2G2 g(ξ6 , t) 2

(6.2.11)

n=0

+ (G1 − G2 )g(ξ7 , t) − 2G1 g(ξ8 , t)}, +∞

1 σ2 (x, t) = − {(G1 − G2 )g(η1 , t) − 2G1 g(η2 , t) 2 n=0

+ (G1 − G2 )g(η3 , t) + 2G2 g(η4 , t)} +∞

1 {2G2 g(η5 , t) + (G1 − G2 )g(η6 , t) − 2 n=0

− 2G1 g(η7 , t) + (G1 − G2 )g(η8 , t)}

(6.2.12)

6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree

127

It should be mentioned that the closed-form expressions σ1 (x, t) in (6.2.11) and σ2 (x, t) in (6.2.12) are obtained by assuming that the preexisting residual stress σT is zero. If we consider the effect of the residual stress σT preexisting in the interconnect line, by a direct derivation we can easily calculate the total stress σi,total (x, t)(i = 1, 2) experienced by electromigration as the summation of the two stresses σi (x, t) and σT , i.e., σ1,total (x, t) = σ1 (x, t) + σ1,T , σ2,total (x, t) = σ2 (x, t) + σ2,T

(6.2.13)

where σ1,T and σ2,T are the residual stresses preexisting in the left and right segments, respectively. Obviously, the closed-form expressions (6.2.11) and (6.2.12) show exact series solutions of stress evolution equations for the two wire segments. When the tensile stress at the cathode end of an interconnect wire exceeds the critical stress σcrit necessary for void nucleation, the value of the void nucleation time tnuc can be extracted from the general expressions (6.2.11) and (6.2.12). Once a void starts to nucleate, it can grow to larger volume even spanning the whole interconnect line. On the other hand, an approximate value of tnuc can be derived from the approximate solution of the one-dimensional diffusion-like equation by using the first dominant term (n = 0) approximation for each segment 1 σ1 (x, t) ≈ − {−2G1 g(ξ1 (x, 0), t) + (G1 − G2 )g(ξ2 (x, 0), t) 2 + 2G2 g(ξ3 (x, 0), t) + (G1 − G2 )g(ξ4 (x, 0), t)} 1 − {(G1 − G2 )g(ξ5 (x, 0), t) + 2G2 g(ξ6 (x, 0), t) 2

(6.2.14)

+ (G1 − G2 )g(ξ7 (x, 0), t) − 2G1 g(ξ8 (x, 0), t)}, 1 σ2 (x, t) ≈ − {(G1 − G2 )g(η1 (x, 0), t) − 2G1 g(η2 (x, 0), t) 2 + (G1 − G2 )g(η3 (x, 0), t) + 2G2 g(η4 (x, 0), t)} 1 − {2G2 g(η5 (x, 0), t) + (G1 − G2 )g(η6 (x, 0), t) 2

(6.2.15)

− 2G1 g(η7 (x, 0), t) + (G1 − G2 )g(η8 (x, 0), t)} Similar to the single wire case, the void nucleation time can be obtained by solving the equations σ1 (x, tnuc,1 ) = σcrit , σ2 (x, tnuc,2 ) = σcrit

(6.2.16)

where the critical stress σcrit is known. It can be seen from (6.2.14) to (6.2.16) that the void nucleation time depends on the critical tensile stress and hence is related

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6 Compact EM Models for Multi-Segment Interconnect Wires

Fig. 6.2 Steady-state stress distribution for an active segment of length L2 = 20 µm with an inactive sink of length L1 = 6 µm [4]

8

4

x 10

Stress (Pa)

2

Proposed method, t=1x108s Method in Ref. [37]

0 −2 −4 −1

0

1 Length (m)

2 x

10−5

to the critical current density which is not included in the Black’s equation (2.2.1). Also, we can see from (6.2.14) and (6.2.15) that the lifetime is also affected by the segment length configuration information which has not been fully reflected in the Black’s equation (2.2.1). The MTTF estimated by the Black’s equation becomes invalid for this type of circuit-like interconnects with multi-segments [12, 13, 16]. It should be noted that because of the nonlinearity properties of the functions σ1 (x, tnuc,1 ) and σ2 (x, tnuc,2 ), iterative methods can be used to calculate the void nucleation time. It should also be noted that the one-term approximation (6.2.14)–(6.2.15) can be used to calculate the steady-state stress distribution along three-terminal interconnect tree. Theoretically the stresses σi,steady (i = 1, 2) at steady state can be given by σi,steady = σi (x, +∞). In order to verify the accuracy of computing the steady-state stress distribution using (6.2.14) and (6.2.15), we consider a threeterminal interconnect tree with active and inactive segments like the interconnect structure as shown in [11]. For practical simulation in our work, the lengths of inactive and active segments are set to be L1 = 6 µm and L2 = 20 µm, respectively, and the corresponding current density values are assumed to be j1 = 0 A/m2 and j2 = 5 × 109 A/m2 . It can be seen from Fig. 6.2 that the steady-state stress distribution, obtained by the proposed method, is consistent with the previously published method in [11].

6.2.2 Considering Varying Current Density To simplify the discussion of the effects of current density configurations on the void nucleation phase for the three-terminal interconnect tree and the EM-induced stress evolution in this type of tree, we will in this section assume that the two segments

6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree

129

in this tree have the same length L1 = L2 = 20 µm. We will simulate the effects of electromigration using our closed-form expression presented in Sect. 6.2. The proposed analytical solver is based on a one-dimensional Korhonen model which has been modified to account for a wide range of EM effects, including the impacts on the junction of the two wire segments. By the closed-form expressions, the stress evolution process can be modeled through initial prestress distribution to steadystate stress distribution. We can also model the associated void nucleation time using the proposed exact series solution when the tensile stress at the cathode end reaches the critical stress value. Figure 6.3 shows the four different current configurations that were used in tests of the three-terminal interconnect structure. A constant current density of j1 = 6×1010 A/m2 was applied in the left line segment, while a current density with varying direction and magnitude, j2 , was used to stress the right line segment. For

4

x 109

5

t=1x106s 7 t=1x10 s t=1x108s

3

3

Stress (Pa)

Stress (Pa)

0 −1

2 1 0 −1

−2 −3 −2

t=1x106s 7 t=1x10 s t=1x108s

4

2 1

x 109

−2

−1.5

−1

−0.5

0

0.5

1

1.5

Length (m)

−3 −2

2 x 10−5

−1.5

−1

−0.5

(a) 6

0.5

1

1.5

2 x 10−5

(b)

x 109

6

t=1x106s t=1x107s t=1x108s

5 4

x 109

t=1x106s t=1x107s t=1x108s

4

3

2

Stress (Pa)

Stress (Pa)

0

Length (m)

2 1 0

0

−2

−1 −2

−4

−3 −4 −2

−1.5

−1

−0.5

0

Length (m)

(c)

0.5

1

1.5

2 x 10−5

−6 −2

−1.5

−1

−0.5

0

Length (m)

0.5

1

1.5

2 x 10−5

(d)

Fig. 6.3 The EM stress development along segments 1 and 2 in the three-terminal interconnect tree: (a) j2 = − 23 j1 ; (b) j2 = − 31 j1 ; (c) j2 = 13 j1 ; (d) j2 = 23 j1 [4]

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6 Compact EM Models for Multi-Segment Interconnect Wires

cases (a) and (b), the currents have different directions that can lead to tensile stress at both ends of the two line segments. Voids can nucleate at the ends “a” and “b” of this interconnect tree when the tensile stresses exceed the critical stress necessary for void nucleation. It can be seen from Fig. 6.3a, b that the time to failure of the left line segment decreases as the current density in the right line segment decreases. However, the lifetime of the right line segment increases with the decrease of its current density. For cases (c) and (d), the two segments have the same current direction. As a result, a tensile stress, which can cause voiding, develops at the cathode end “a” in the left line segment. Correspondingly, a compressive stress, which can cause metal extrusion, develops at the anode end “b” of the test structure. We can see from Fig. 6.3c, d that the compressive stress at the anode end increases as the current density of the right line segment increases for a fixed current density j1 in the left line segment. The effect of current density on stress evolution is obvious in numerical simulation results obtained from the proposed analytical model, which fits well with the experimental work in [11].

6.2.3 Considering Varying Segment Length In this section, the effects of segment length on lifetime at the void nucleation phase will be considered for the three-terminal interconnect tree. For simplicity (without loss of generality), we assume that the current densities j1 and j2 in the left and right segments are set to be 2 × 1010 A/m2 and −2 × 1010 A/m2 , respectively. Under this assumption, the directions of the currents in the two segments are opposite to each, which may cause tensile stress at both ends “a” and “b” under some given segment length configurations. The effect of electromigration on stress evolution will be simulated by using the presented analytical model. Stress evolution, as presented in Sect. 6.2.2, will be simulated through initial prestress distribution to a steady-state stress distribution. Also, the void nucleation time can be calculated for different segment length configurations by using the presented closed-form expression. The stress of a three-terminal interconnect tree as a function of its segment length configurations has been shown in (6.2.11) and (6.2.12). When this analytical model is applied to compute the lifetime of a three-terminal interconnect tree, it is obvious that the lifetime is changed as there is an increase or decrease in the segment length. The effect of segment length on lifetime has been demonstrated by experimental characterization with metallization technology [19]. However, it did not give a closed-form expression to model the three-terminal interconnect tree in which the neighboring segments interact with each other. In order to simulate the effect of segment length under the fixed current condition, we assume that the length of the left segment is 20 µm, and we will observe the change of stress by setting different current densities for the right segment. At the fixed current density configuration, it can be seen from Fig. 6.4 that the stress of the right segment decreases as the decrease of the length, which leads to the increase of the lifetime of the interconnect tree. This is due to the fact that the compressive stress developed

6.2 Accurate Analytical Model for Three-Terminal Interconnect Tree 9

1.5

x 10

t=1x10 s 7 t=1x10 s t=1x108s

x 10

9

t=1x106s 7 t=1x10 s t=1x108s

1

Stress (Pa)

1

Stress (Pa)

1.5

6

0.5 0

−0.5

0.5 0

−0.5

−1 −20

−15

−10

−5

0

−1 −2

5

Length (m)

x 10

−1.5

−6

(a) 1.5

t=1x106s t=1x107s t=1x108s

0

0.5

1 −5

x 10

x 10

9

t=1x106s 7

t=1x10 s

1

Stress (Pa)

1

Stress (Pa)

−0.5

(b)

x 10

0.5 0

−0.5 −1 −2

−1

Length (m)

9

1.5

131

t=1x108s

0.5 0

−0.5

−1.5

−1

−0.5

Length (m)

(c)

0

0.5

1 x 10

−5

−1 −2 −1.5 −1 −0.5

0

Length (m)

0.5

1

1.5 −5

x 10

(d)

Fig. 6.4 The EM stress development along segments 1 and 2 in the three-terminal interconnect tree: (a) L2 = 16 L1 ; (b) L2 = 26 L1 ; (c) L2 = 36 L1 ; (d) L2 = 46 L1 [4]

at the node “o” of the test structure can interact with, and thus slow down the rate of tensile stress increase at the node “b.” It was observed from Fig. 6.4a, b that a compressive hydrostatic stress can build up in the right segment when the length of this segment is small enough. They demonstrate that the decreasing of the length of one of the segments taking place under the fixed electric current load results in a progressive development of the compressive stress in this segment. This is caused by a continuously increasing back stress gradient in the short segment due to a continuous supply of atoms from the long segment to the segment border. On the other hand, as seen in Fig. 6.4c, d, a tensile stress can also build up in the right segment if we increase the length of this segment. With the increase of the length of the right segment, a void can form at the node “b” of this segment where the tensile stress is the largest, resulting in simultaneous failure of the right segment. As a result, voids do not necessarily always form in the longest segment of an interconnect tree.

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6 Compact EM Models for Multi-Segment Interconnect Wires

6.3 Dynamic EM Modeling for Three-Terminal Interconnect Tree The thermal effects have become a key factor in reliability-aware design under lifetime constraints. In this section, we will present a dynamic EM-induced stress model for three-terminal interconnect tree with various wire segment lengths, which can be used to calculate the stress values under any time-varying temperature profile for the EM-induced reliability.

6.3.1 Temperature Impacts on EM Effects Black’s model (2.2.1) needs to assume a constant temperature when applied to system-level thermal reliability analysis and design. This assumption eliminates the need for the thermal analysis on the interconnect lifetime prediction [14, 15]. When the interconnect trees have very high current densities (j > 109 A/m2 ), thermal effects are becoming a limiting factor in high performance IC design due to the strong temperature dependence of reliability. Further, using average temperature isnever a good practice for EM evaluation due to its Arrhenius nature Ea Da = D0 exp − kT . If a constant temperature is considered in the stress evolution equation (6.2.1) for three-terminal interconnect tree, it may result in pessimistic lifetime estimations in restricted design spaces. As an example, we consider time-periodic responses of the interconnect temperature as shown in Fig. 6.5a, b, where P is the period. The current densities j1 and j2 in the left and right wire segments are set to be 1 × 1010 A/m2 and 2 × 1010 A/m2 , respectively. Using the data from Fig. 6.5a, the maximum and minimum temperatures in this three-terminal interconnect tree are assumed to be

Temperature (K)

Temperature (K)

373

473 Average

363

Average

428

383

353 P

2P

(a)

Time

P

2P

Time

(b)

Fig. 6.5 The temperature profiles for simulations during the EM lifetime for the three-terminal interconnect tree: (a) temperatures between 353 and 373 K; (b) temperatures between 383 and 473 K [4]

6.3 Dynamic EM Modeling for Three-Terminal Interconnect Tree

12

x 108

10

Stress (Pa)

Fig. 6.6 The EM stress development at the cathode end of the three-terminal interconnect tree: (a) under temperature profiles shown in Fig. 6.5a; (b) under temperature profiles shown in Fig. 6.5b [4]

133

8 6 4 Min Temperature, 353K Actual Temperature Average Temperature,363K Max Temperature, 373K

2 0

0

1

2

3

4 x 107

Time (s) (a) 7

x 107 Min Temperature, 383K Actual Temperature Average Temperature, 428K Max Temperature, 473K

6

Stress (Pa)

5 4 3 2 1 0

0

2

4

6 Time (s)

8

10 x 104

(b)

373 K and 353 K, respectively. Hence, the corresponding average temperature used for the simulation of stress evolution process is 363 K. Using these configurations, we can compare the values of stress obtained from the actual temperatures with those of the average, maximum, and minimum temperatures, and finally compare the time to the void nucleation by (6.2.16). A similar treatment can be required for the temperature profiles shown in Fig. 6.5b. Our simulation results are reported in Fig. 6.6 which shows four different cases where the temperatures profile affects the stress evolution process in the interconnect. In general, if the temperature change is within 10 K and the current density is relatively small, using the average temperature for estimating interconnect lifetime is still a good approximation to the IC circuit designers. It can be observed

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6 Compact EM Models for Multi-Segment Interconnect Wires

from Fig. 6.6 that while the interconnect temperature variation increases (e.g., beyond 20 K), these differences become obvious by comparison between the actual and average temperatures. On the other hand, it can be seen from Fig. 6.6a that using the minimal temperature will make a big difference for stress calculations and it will lead to larger errors for interconnect lifetime prediction. Also, if we take the maximum temperature during the total simulation time, we can see from Fig. 6.6b that there is a serious difference between the actual and maximum stress profile calculations. Thus, the interconnect could be seriously underestimated, resulting in excessive design margin. Therefore, as the temperature variation increases, we can no longer use minimal/average/maximum temperature to estimate the interconnect reliability. In view of the fact that the variation magnitude seriously affects the estimation of interconnect lifetime under EM constraints, we will develop an exact dynamic EMinduced stress model for three-interconnect tree with various wire segment lengths in the next section. This dynamic model can be used for calculation of interconnect lifetime for any time-dependent temperature profile.

6.3.2 Dynamic EM Model Considering Varying Temperature We now present dynamic EM modeling considering time-varying temperature for three-terminal interconnect trees with varying segment length. We start with the stress evolution equation as shown in (6.2.1) and assume that the two segments in the three-terminal interconnect tree have the same diffusivity. Considering that the temperature is time-dependent, we can rewrite the diffusivities κ1 and κ2 as κ1 (t) = κ2 (t) = κ(t) =



a D0 exp − kTE(t) B kT (t)

(6.3.1)

We still assume that the current density for each segment does not change over time. Therefore, the terms G1 = E1 q and G2 = E2 q are both constant. We are now ready to derive the analytical solution of the stress evolution equation (6.2.1) with the time-varying temperature. Although we were able to use the Laplace transformation technique to obtain the series solution of stress evolution equation of three-terminal interconnect tree with various segment length and constant temperature, the stress evolution equation with time-varying temperature cannot be solved in a similar way. But fortunately, we have the following observations: Theorem 6.1 Let σi (x, t, κ1 ) and σi (x, t, κ2 ) (i = 1, 2) be the solutions to the stress evolution equation (6.2.1) with the diffusivities κ1 and κ2 for the same initial and boundary conditions, respectively, then we have   κ2 σi (x, t, κ2 ) = σi x, t, κ1 κ1

6.3 Dynamic EM Modeling for Three-Terminal Interconnect Tree

135

Proof This can be proved

using the  same technique as for the analogous result in [14]. Let σ˜ i (x, t) = σi x, κκ21 t, κ1 , then we just need to verify that σ˜ i (x, t) is equal to σi (x, t, κ2 ). If we take the derivative of the partial derivative of σ˜ i (x, t) with respect to t, then we can extract a partial differential equation (PDE), namely

 κ2 x, ∂σ t, κ i 1 κ1 ∂ σ˜ i (x, t) κ2 − =0 ∂t κ1 ∂t Since σi (x, t, κ1 ) is the solution of Eq. (6.2.1)

with the  diffusivity κ1 for certain  κ

∂σi x, κ2 t,κ1 ∂σi x, κ2 t,κ1 κ ∂ 1 1 = ∂x κ1 + initial and boundary conditions, we have ∂t ∂x ! = 0. Substituting this expression into the above PDE, and noting that Gi ∂ σ˜ i (x,t) ∂t

=

 κ ∂σi x, κ2 t,κ1 1

∂t

, we have

   ∂ σ˜ i (x, t) κ2 ∂ ∂ σ˜ i (x, t) =0 − + Gi κ1 ∂t κ1 ∂x ∂x which implies that σ˜ i (x, t) is the solution of the stress evolution equation (6.2.1) with the diffusivity κ2 under the same initial and boundary conditions. This completes the proof of the theorem.  It can be seen from Theorem 6.1 that the stress evolution processes in the three-terminal interconnect tree are independent of the diffusivity in (6.2.1) which only affects the stress evolution speedup. This will lead to a time-shift invariant representation of the solution of the stress evolution equation with time-varying temperature based on the series solution (6.2.11) and (6.2.12) in the case of constant temperature. On the other hand, if we look at the complete analytical solution (6.2.11) and (6.2.12), only the term g(x, t) is affected by the temperature T (t). From (6.2.10) we can see that as long as κ(T (t))t is constant, the basis function g(x, t) will be the same. As a result, the temperature impact on the stress σi (x, t, κ) through κ(T (t)) can be translated to the time period change for a three-terminal interconnect tree. In other words, a three-terminal interconnect tree whose stress development over a period t2 under the temperature T2 will be equal to the stress 2) development for a three-terminal interconnect tree over a period κ(T κ(T1 ) t2 under the temperature T1 . Without loss of generality, we assume that the time period can be partitioned into n small segments: ⎧ κ1 , t ∈ [0, t1 ], ⎪ ⎪ ⎪ ⎪ ⎪ ⎪ κ , t ∈ (t1 , t1 + t2 ], ⎪ ⎪ 2 ⎨ κ(T (t)) = . . . , ⎪ ⎪ %n−1  ⎪ i ⎪ ⎪ ⎪ ⎪ ⎪ tl , tl , n = 2, 3, . . . . ⎩ κn , t ∈ l=1

l=1

(6.3.2)

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6 Compact EM Models for Multi-Segment Interconnect Wires

Inside each time segment we assume that the temperature is constant, which leads to an invariant diffusivity for the stress evolution processes. As a result, the temperature-varying stress computation problem can be converted into the constant temperature problem. Now we denote the dynamic stress with time-varying temperature by σi,th (x, t, κ) for each metal wire. At the end of the first time segment [0, t1 ], we have σi,th (x, t1 , κ1 ) = σi (x, t1 , κ1 ), where σi (x, t1 , κ1 ) is calculated by i  (6.2.11) and (6.2.12). Then at the current time ti = tl , we have l=1

% σi,th x,

n l=1

& tl , κn

% = σi

n κl tl , κ1 x, κ1

& (6.3.3)

l=1

where n = 1, 2, . . ., and σi (x, t, κ) is given by (6.2.11) and (6.2.12). When the tensile stress (we ignore thermal residual σT for time being for the sake of better presentation) reaches the critical stress σcrit , a void will nucleate at the cathode end of a metal wire. If σcrit is greater than the steady state tensile stress at the cathode end, no void will form and the wire is immortal. If the dynamic reachesa  stress n nuc κl critical threshold at the inuc -th time segment, we have σcrit = σi x, κ1 tl , κ1 . Then the time to nucleation can be computed by tnuc =

n nuc

l=1

tl .

l=1

6.4 Numerical Results and Discussions The present dynamic EM model and the method of analysis of three-terminal interconnect tree with various wire segment lengths have been implemented in MATLAB and compared with the finite element analysis tool COMSOL [5] and the electromigration simulator XSim [24] and the recently proposed eigenfunction method [22], which is considered as a “golden” tool in our work.

6.4.1 Different Current Density and Segment Length Configurations For the purpose of simulation, the metal wire structure used in our experiment has been shown in Fig. 6.1. The current density and segment length configurations used in our numerical simulations are shown in Table 6.1 from which we can see that the left segment length for each case is set to be shorter than the right one. Also, the current magnitude of the left segment is set to be larger than that of the right

6.4 Numerical Results and Discussions Table 6.1 Current density and segment length configurations used for modeling and simulation [4]

Case I II III IV V VI

137 j1 1 × 1010 A/m2 1 × 1010 A/m2 1 × 1010 A/m2 1 × 1010 A/m2 1 × 1010 A/m2 1 × 1010 A/m2

j2 5 × 109 A/m2 1 × 109 A/m2 0 A/m2 −5 × 109 A/m2 −1 × 109 A/m2 0 A/m2

L1 10 µm 10 µm 10 µm 6 µm 6 µm 6 µm

L2 20 µm 20 µm 20 µm 20 µm 20 µm 20 µm

segment for each case. The stress profiles for different times shown in Fig. 6.7a–f are obtained from the five-term approximation of the proposed series solution (6.2.11) and the COMSOL simulations. It can be seen from Fig. 6.7a–f that the analytical solution obtained with the proposed method fits well to the results of the numerical simulations by COMSOL at every time instance. We now discuss all the cases, in which different current density and segment length configurations are set in the two line segments. In cases I and II, the left and right segments have the same current direction. It was observed from Fig. 6.7a, b that a tensile stress will be developed over time along the left segment and a compressive stress will be developed along the right segment. The tensile stress at the cathode node “a” in the left segment decreases as the current density of the right segment decreases for a fixed current density in the left segment. Generally, the left segment in the two cases is called reservoir as it has tensile stress and the right segment is called sink [11]. Figure 6.7b shows that voids can only take place in the reservoir when the current magnitude in the sink is zero or small. However, voids can be also nucleated when the sink becomes active. This can be easily seen from Fig. 6.7d for the case when the current magnitude in the right segment is with no zero and the current direction is opposite to the left segment. In cases III and VI, voids can be only nucleated in the left segment since the current density in the right segment is zero. The tensile stress at the node “a” increases with the length of the left segment for a fixed length of the right segment. In cases IV and V, tensile stresses can build up at both ends “a” and “b” since the currents in the two segments are opposite in direction. Figure 6.7d shows that voids can first form at the end “b” of the longer segment (right). On the other hand, it can be seen from Fig. 6.7e that void can also be nucleated at the end “a” of the shorter segment (left) if we decrease the current magnitude of the right segment. To further verify the accuracy of the proposed method, we compare the proposed analytical solution with the results published in the literature on very similar structures [7, 24] in which the EM-based stress evolution in a short three-contact interconnect tree was calculated by the electromigration simulator XSim [24]. XSim is widely used to calculate the hydrostatic stress evolution in an interconnect which is assumed to be confined within diffusion barriers. In this simulation, the lengths of the left and right segments in the interconnect line are set to be 1 × 10−5 m and 4 × 10−5 m, respectively. The width and the thickness in the interconnect tree used in XSim are set to be 0.2×10−6 m and 0.38×10−6 m, respectively. The temperature

138

6 Compact EM Models for Multi-Segment Interconnect Wires

8

x 10

8

8

5

x 10

6

6

Proposed,t=1x10 s

Proposed,t=1x10 s

6

COMSOL,t=1x10 s

6

6

COMSOL,t=1x10 s

4

7

Proposed,t=1x10 s

7

Proposed,t=1x10 s

4

7

Stress (Pa)

Stress (Pa)

7

COMSOL,t=1x10 s 8

Proposed,t=1x10 s 8

COMSOL,t=1x10 s

2 0 −2 −4

COMSOL,t=1x10 s

3

8

Proposed,t=1x10 s COMSOL,t=1x108s

2 1 0 −1

−6 −1.5

−1

−0.5

0

0.5

1

1.5

−2 −1.5

2

−5

−1

−0.5

x 10

Length (m) (a) 5

x 10

0

0.5

1

1.5

2

−5

x 10

Length (m) (b)

8

8

3

x 10

Proposed,t=1x106s COMSOL,t=1x106s

4

2

Proposed,t=1x107s

Stress (Pa)

Stress (Pa)

7

COMSOL,t=1x10 s

3

8

Proposed,t=1x10 s COMSOL,t=1x108s

2 1 0

1 0 Proposed,t=1x106s 6

COMSOL,t=1x10 s

−1

Proposed,t=1x107s COMSOL,t=1x107s

−1

−2

−2 −1.5

−3 −1

Proposed,t=1x108s COMSOL,t=1x108s

−1

−0.5

0

0.5

1

1.5

2

−5

−0.5

0

x 10

Length (m) (c)

1

2.5 −5 x 10

3

x 10

Proposed,t=1x106s

Proposed,t=1x106s

6

6

2.5

COMSOL,t=1x10 s

2

COMSOL,t=1x10 s

7

7

Proposed,t=1x10 s

Proposed,t=1x10 s

COMSOL,t=1x10 s

1.5

8

Proposed,t=1x10 s 8

COMSOL,t=1x10 s

1 0.5 0 −0.5

Stress (Pa)

7

Stress (Pa)

2

8

x 10

−1 −1

1.5

(d)

8

2.5

0.5

Length (m)

7

2

COMSOL,t=1x10 s 8

Proposed,t=1x10 s 8

1.5

COMSOL,t=1x10 s

1 0.5 0 −0.5

−0.5

0

0.5

1

Length (m) (e)

1.5

2

2.5 −5 x 10

−1 −1

−0.5

0

0.5

1

Length (m)

1.5

2

2.5 −5 x 10

(f)

Fig. 6.7 The EM stress development along segments 1 and 2 in the three-terminal interconnect tree considering current density and segment length configurations: (a) case I; (b) case II; (c) case III; (d) case IV; (e) case V; (f) case VI [4]

6.4 Numerical Results and Discussions

2

139

x 108

Stress (Pa)

1 0 Proposed, t=100s XSim, t=100s Proposed, t=1000s XSim, t=1000s Proposed, t=10000s XSim, t=10000s

−1 −2 −3

0

1

2 3 Position (m)

4

5 −5

x 10

Fig. 6.8 The proposed analytical method compared against XSim results [4]

is set to be 350 ◦ C and the current densities in the left and right segments are −2×109 A/m2 and 2×109 A/m2 , respectively. Figure 6.8 shows the stress evolution calculated by XSim and using the first dominant term approximation (6.2.14) and (6.2.15) along this interconnect line at various time. We can see from Fig. 6.8 that XSim and the one-term approximation provide results of similar accuracy which shows the effectiveness of the proposed analytical method.

6.4.2 Dynamic EM Stress Under Time-Varying Temperature To verify the accuracy of the new dynamic EM model, let us consider the threeterminal interconnect tree shown in Fig. 6.1 in which the lengths of the left and right segments are set to be 6 × 10−6 m and 2 × 10−5 m, respectively. For our simulation, we assume that the current densities j1 and j2 in the left and right segments are 1 × 1010 A/m2 and 2 × 1010 A/m2 , respectively, and we create the periodic change temperature profiles over time which can be shown in Fig. 6.5a. For this case the corresponding analytical solution to the stress evolution equation (6.2.1) with time-varying temperature can be represented by (6.3.3). For comparison with the proposed dynamic EM model, we will also apply COMSOL to compute an accurate numerical solution of (6.2.1). To illustrate the effect of time-varying temperature, we use the one-term approximation (n = 0) of the proposed series solution (6.2.11) and the FEA tool COMSOL to calculate the stress values during the void nucleation process. Figure 6.9 shows the stress distributions under time-varying temperature along the whole length of

140

6 Compact EM Models for Multi-Segment Interconnect Wires 7

5

8

x 10

4

x 10

Stress (Pa)

Stress (Pa)

2 0

−5

Proposed COMSOL −10 −1

0

0 −2

Proposed COMSOL

−4

1

Position (m)

−6 −1

2

0

1

Position (m)

−5

x 10

(a)

(b)

8

6

9

x 10

1.5

2 0 −2 −4

−8 −1

x 10

1

Stress (Pa)

Stress (Pa)

4

−6

2 x 10−5

Proposed COMSOL 0

0 −0.5 −1

1

Position (m) (c)

0.5

2 x 10−5

−1.5 −1

Proposed COMSOL 0

1

Position (m)

2 x 10−5

(d)

Fig. 6.9 The EM stress development along segments 1 and 2 in the three-terminal interconnect tree considering time-varying temperature: (a) t = 8 × 104 s; (b) t = 2 × 106 s; (c) t = 5 × 106 s; (d) t = 4 × 107 s [4]

this three-terminal interconnect tree. It can be seen from Fig. 6.9 that the stresses calculated by the proposed one-term approximation are in good agreement with those obtained from COMSOL. It should be noted that electrons flow from the left segment to the right segment and out of the anode end of the right segment. The slope of the stress profile will be unchanged in the interconnect tree when the stress gradually increases to a steady-state level, but it can be observed from Fig. 6.9 that the maximum tensile stress will be higher and will still occur at the end “a” (the cathode end) of the left segment.

6.4 Numerical Results and Discussions

141

6.4.3 Computational Accuracy and Convergence Characteristics We now study the convergence behavior of the aforementioned method using the series solution (6.2.11) and we illustrate the discussion by analyzing the convergence observed in actual computations. In general, we need to compare the (m + l)-term approximation with the m-term approximation for arbitrary fixed nonnegative integers m and l. As we can see, Fig. 6.9 has shown that the dominant term of the expression (6.2.11) can match well with the COMSOL simulation results for a given current density and temperature profile for the three-terminal interconnect tree with various lengths. Therefore, we just need to compare the accuracies of the EM models employing the one-term (n = 0) and two-term (n = 1) approximations of the original series solution. This comparison can be seen clearly from the numerical simulation results or the stress evolution process. Figure 6.10 shows the comparison results between the one-

−4

x 10

Relative Error

2

−6

1.5

Position: −6x10 m Position: 0x10−6m Position: 1x10−5m

1

Position: 2x10−5m

0.5

0

0

1

2

3

Time (s)

4 7

x 10

(a) −3

2

x 10

Position: −6x10−6m

1.5

Relative Error

Fig. 6.10 Relative errors between the one-term and two-term approximations at different locations in the three-terminal interconnect tree: (a) constant temperature; (b) time-varying temperature [4]

−6

Position: 0x10 m Position: 1x10−5m −5

1

Position: 2x10 m

0.5

0

0

1

2

Time (s) (b)

3

4 7

x 10

142

6 Compact EM Models for Multi-Segment Interconnect Wires

term and two-term approximations for this three-terminal interconnect tree. It can be seen that the relative errors between the one-term and two-term approximations are less than 0.2% for both the constant and time-varying temperatures. Figure 6.10a shows that using the constant temperature can lead to smaller relative errors (e.g., within 0.02%). By using more terms, the accuracy of the proposed EM model simulation results will not be significantly increased, which means that the dominant one-term approximation can achieve sufficient accuracy for practical EM analysis. To further illustrate that the analytical series solution (6.2.11) and (6.2.12) has fast convergence, we compare the proposed method with results reported in [22] for an interconnect with similar structures. In [22], the integral transform technique was used to calculate the transient hydrostatic stress represented in the form of an infinite series of eigenfunctions. The accuracy of this algorithm depends on the number of eigenfunctions used in the series solution. As discussed above, the accuracy of the proposed analytical method by using the one-term approximation is validated by numerical experiments. However, Fig. 6.11a shows that a significant error can be produced if the one-term approximation of the infinite series solution of eigenfunctions is used to calculate the stress evolution along the interconnect line. The accuracy will be improved if more eigenfunctions are used for simulation. It can be seen from Fig. 6.11b that the 50-term approximation of the eigenfunction method can achieve the same accuracy with the one-term approximation of the series solution (6.2.11) and (6.2.12). That is to say, the analytical method proposed in this paper has faster convergence compared with the eigenfunction method reported in [22]. Simulation results show that the proposed method can achieve improved performance compared with the eigenfunction method for calculating the stress evolution by electromigration of three-terminal interconnect tree.

6.5 Dynamic EM Models for More General Interconnect Wires In this section, we look at more general multi-segment interconnect wires as shown in Fig. 6.12 and establish a unified equation for describing the stress evolution process during the void nucleation. The multi-segments in these trees are connected through the center node “0.” Each port and branch is identified by a number. The current densities in each segment may not be same, which is determined by the rest of the circuit. Then, based on the port 0, we establish rectangular coordinates indicating the location of each branch to induce further solution. The continuity at the joints (port 0) of connected wire segments will be preserved. Without loss of generality, we assume that the interconnect tree has m segments which have the same length L. In order to derive a unified equation describing the stress evolution for each segment, the rectangular coordinate system centered at the node “0” can be used for indicating the location of each branch. Thus, a unified equation describing stress evolution during the void nucleation phase for these multi-branch interconnect trees can be established as follows:

6.5 Dynamic EM Models for More General Interconnect Wires 8

3

x 10

Proposed, 1 term, t=1x106s

2.5

Ref. [31], 1 term, t=1x106s 7

2

Proposed, 1 term, t=1x10 s 7

Stress (Pa)

Fig. 6.11 Comparison between the proposed analytical method and the eigenfunction method for calculating the EM stress development along the three-terminal interconnect tree [4]

143

Ref. [31], 1 term, t=1x10 s

1.5

8 Proposed, 1 term, t=1x10 s 8

1

Ref. [31], 1 term, t=1x10 s

0.5 0 −0.5 −1

0

0.5

1 1.5 Position (m)

2

2.5 −5

x 10

(a) 8

3

x 10

6

Proposed, 1 term, t=1x10 s 2.5

Ref. [31], 50 terms, t=1x106s 7 Proposed, 1 term, t=1x10 s

Stress (Pa)

2

Ref. [31], 50 terms, t=1x107s

1.5

8

Proposed, 1 term, t=1x10 s 8

Ref. [31], 50 terms, t=1x10 s

1 0.5 0 −0.5 −1

0

0.5

1 1.5 Position (m)

2

2.5 −5

x 10

(b)    ∂σ2a+1 (x, t) ∂ ∂σ2a+1 (x, t) = + G2a+1 Dt,2a+1 ∂t ∂x ∂x in − L < x < 0, t > 0,    ∂σ2b+2 (x, t) ∂ ∂σ2b+2 (x, t) = + G2b+2 Dt,2b+2 ∂t ∂x ∂x in 0 < x < L, t > 0

(6.5.1)

144

6 Compact EM Models for Multi-Segment Interconnect Wires

Fig. 6.12 The direction of the current is indicated by the arrow: (a) single line wire (“I” shape); (b) three-terminal wire (“dotted I” shape); (c) four-terminal wire (“T” shape); (d) cross-shaped five-terminal wire (“+” shape) [17]

where a = 0, 1, . . . , (m − 1)/2 and b = 0, 1, . . . , m/2 − 1. It should be noted that the atom flux and the stress value must be continuous at the joint point “0,” which can be reflected by the following boundary conditions: 

 ∂σ2a+1 (x, t) + G2a+1 = 0, at x = −L, t > 0, ∂x   ∂σ2b+2 (x, t) + G2b+2 = 0, at x = L, t > 0, Dt,2b+2 ∂x Dt,2a+1

σ2a+1 (x, t) = σ2b+2 (x, t), at x = 0, t > 0 (m−1)/2

 Dt,2a+1

a=0

=

m/2−1 b=0

 ∂σ2a+1 (x, t) + G2a+1 , ∂x

 Dt,2b+2

(6.5.2)

 ∂σ2b+2 (x, t) + G2b+2 , x = 0, t > 0 ∂x

We assume that there is no stress anywhere in the whole tree at the initial time t = 0. For the sake of simplicity, we also assume that each branch has , the same diffusivity, i.e., Dt1 = Dt2 = · · · = D and β1 = β2 = · · · = β = Ds . In order to obtain the analytical solution σi (x, t) by using the Laplace transform technique, we need to introduce the following notations: ξ0 (x, q) = 4qL − x,

η0 (x, q) = 4qL + x,

ξ1 (x, q) = (1 + 4q)L − x, η1 (x, q) = (1 + 4q)L + x, ξ2 (x, q) = (2 + 4q)L − x, η2 (x, q) = (2 + 4q)L + x,

(6.5.3)

6.5 Dynamic EM Models for More General Interconnect Wires

ξ3 (x, q) = (3 + 4q)L − x, η3 (x, q) = (3 + 4q)L + x, ξ4 (x, q) = (4 + 4q)L − x, η4 (x, q) = (4 + 4q)L + x

145

(6.5.4)

where n is a nonnegative integer. Also, we need to construct the following basic function:   κt − x 2 x 4κt (6.5.5) e − x × erf c √ g(x, t) = 2 π 2 κt + +∞ 2 where erf c{x} = √2π x e−t dt is the complementary error function. We omit the details here due to space limit. Using the notations mentioned above, we can get the exact analytical solution of the stress evolution equation for each segment: +∞

σ2a+1 =

1 {2(Gsum − G2a+1 )g(ξ1 , t) + mG2a+1 g(ξ3 , t) m q=0

− (m − 2)G2a+1 g(ξ1 , t) − Gsum (g(ξ0 , t) + g(ξ2 , t))} +∞

1 + {2(Gsum − G2a+1 )g(η3 , t) + mG2a+1 g(η1 , t) m

(6.5.6)

q=0

− (m − 2)G2a+1 g(η3 , t) − Gsum (g(η2 , t) + g(η4 , t))}, +∞

σ2b+2 =

1 {2(Gsum + G2b+2 )g(ξ3 , t) − mG2b+2 g(ξ1 , t) m q=0

+ (m − 2)G2b+2 g(ξ3 , t) − Gsum (g(ξ2 , t) + g(ξ4 , t))} +∞

1 + {2(Gsum + G2b+2 )g(η1 , t) − mG2b+2 g(η3 , t) m

(6.5.7)

q=0

+ (m − 2)G2b+2 g(η1 , t) − Gsum (g(η0 , t) + g(η2 , t))} (m−1)/2 m/2−1 where Gsum = a=0 G2a+1 − b=0 G2b+2 . It should be noted that the dominant one-term approximation can achieve sufficient accuracy for practical EM analysis, which will be addressed later in experimental section.

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6 Compact EM Models for Multi-Segment Interconnect Wires

6.6 EM Modeling by Integral Transformation Method for Straight Multi-Segment Wires Recently, another closed form analytical solution was developed for straight multisegment wires as shown in Fig. 6.13 using the so-called integral transformation method, which is essentially the Green’s function based method [21]. The method can compute the stress evolution over time for that kind of wires. Korhonen’s equation (2.3.10) is discretized using this method and stress can be expressed as: σ (x, t) =

∞ ψm (x) σ¯ (λm , t) N (λm )

(6.6.1)

m=1

where the norm of eigenfunctions N(λm ) is  N(λm ) =

L

χ =0

[ψm (χ )]2 dχ

(6.6.2)

and σ¯ (λm , t) is transformed solution of stress which is 1 2 2 σ¯ (λm , t) =F¯ (λm )e−κλm t + 2 (1 − eκλm t ) λm ·

n k=1



xk xk−1 mπ − cos mπ k · cos L L

(6.6.3)

where F is F¯ (λm ) =



L χ =0

ψm (χ ) · σ0 (χ )dχ

(6.6.4)

λm and ψ(x) are the eigenvalues and eigenfunctions which are the solutions of the Sturm–Liouville problem corresponding to the diffusion equation (2.3.10) and the boundary conditions λm =

mπ x , ψm (x) = cos mπ L L

Fig. 6.13 Example of a multi-segment wire [18]

(6.6.5)

6.7 EM Modeling by Integral Transformation Method for More General. . .

147

Fig. 6.14 Stress distribution over time on multi-segment wire calculated by integral transformation method [18]

where m = 1, 2, . . . , ∞. k is k =

eZρ jk , k = 0, 1, . . . , n 

(6.6.6)

With (6.6.1), when the stress σ (x, t) equals to the given critical stress σcrit , then the nucleation time tnuc is obtained. This method is efficient and overcomes the difficulty for numerical solution of partial differential equations. The tnuc estimated using this method is very close to original Korhonen’s equation. An example is shown in Fig. 6.14. As can be seen, the stress can be calculated correctly for multibranch wires. This work uses the integral transformation method to develop a closed-form expression of Korhonen’s equation for EM analysis. Different current densities on multi-branches can be considered and stress analyzed with this method is very accurate. However, this method is limited to one-dimensional wires and cannot handle two-dimensional structures such as the T-shape or cross-shape.

6.7 EM Modeling by Integral Transformation Method for More General Multi-Segment Wires In contrast to the previous works [3, 22] in Sects. 6.2 and 6.6, this section presents a new method not only for special cases of interconnect trees, but also for general multi-branch interconnect trees with varying wire sizing and non-uniform

148

6 Compact EM Models for Multi-Segment Interconnect Wires

temperature distribution. For the nucleation phase, hydrostatic stress is calculated in five steps. First, Eq. (2.3.10) is transformed to homogeneous problem and solved by “separation of variables” technique. Then eigenvalues and eigenfunctions are computed numerically and the coefficients of eigenfunctions are determined by initial conditions. In the end, the transient hydrostatic stress is calculated as a linear combination of eigenfunctions. With the help of transformation equation and the zero atom flux equation for steady state, it could be proven that the Korhonen’s equation (2.3.10) is transformed to homogeneous problem, which is described by governing equations (6.7.1) and boundary conditions (6.7.2), (6.7.3). ∂ σˆ ij (x, t) ∂ 2 σˆ ij (x, t) = κij ∂t ∂x 2

(6.7.1)

σˆ ij1 (x = xi , t) = σˆ ij2 (x = xi , t) . ∂ σˆ ij (x, t) .. wij · κij · ni = 0 . ∂x x=xi

(6.7.2)

i

κj 

. ∂ σˆ j  (x, t) .. =0 . ∂x x=x

(6.7.3)

where ni is the “normal direction” of boundary i on branch ij , which is +1 for right end and −1 for left end of branch. Meanwhile, the initial conditions are transformed as Eq. (6.7.4). σˆ (x, 0) = σ (x, ∞) − σ (x, 0) = σ (x, ∞) − σT

(6.7.4)

After the origin problem transformed to homogeneous equations, the initial boundary value problem (6.7.1), (6.7.3), (6.7.2) is ready for separation of variables. The general solution to problem (6.7.1) σˆ ij (x, t) is shown by Eq. (6.7.5). σˆ ij (x, t) =

∞

Cm e−λm t ψij,m (x) 2

(6.7.5)

m=1

where the eigenvalues λm and coefficients Cm are to be determined by boundary conditions and initial conditions. Finally the original transient hydrostatic stress σ (x, t) is obtained as σ (x, t) = σ (x, ∞) − σˆ (x, t). In order to solve Eq. (6.7.5) the eigenvalues λm and eigenfunctions ψij,m (x) are essential. Eigenvalues λm are of the top priority because they are the key parameters in both the transient part (x) and eigenfunctions ψij,m (x) for the solution.

6.7 EM Modeling by Integral Transformation Method for More General. . .

149

By substituting the so-called “edge equations” to the BCs (6.7.2), (6.7.3), the boundary conditions then lead to constraints of the eigenfunction values on ends of branches, which are represented by Eq. (6.7.6). K(λm ) · ψ ∗ = 0

(6.7.6)

where matrix K(λm ) consists of combinations of coefficients of edge equations, which depend on eigenvalues λm , and ψ ∗ = [ψ1,m , ψ2,m , . . . , ψn,m ]T is the vector of eigenfunction values on nodes of interconnect tree. Also Eq. (6.7.7) needs to be satisfied. det (K(λm )) = 0

(6.7.7)

After the eigenvalues λm are determined, the linear equations (6.7.6) are solved for eigenfunctions. Because det (K(λm )) = 0, the eigenfunction values ψ ∗ could only be uniquely determined with respect to some given elements ψi,m . In the numerical computation, we prescribe some element to 1 and then the ψ ∗ is solved by LU solver. Once the ψ ∗ is solved, eigenfunctions can also be solved. Once the eigenvalues λm and eigenfunctions ψij,m (x) are determined, the coefficients of the linear combination Cm would be solved by setting the solution (6.7.5) to satisfy the initial conditions, as shown by Eq. (6.7.8). σˆ 0 (x) = σˆ (x, t = 0) =

∞

Cm ψij,m (x)

(6.7.8)

m=1

Cm could be obtained by calculating the inner product of each eigenfunctions ψm (x) to the initial conditions σˆ 0 (x), as shown by Eq. (6.7.9). ψm (x) · σˆ 0 (x) = Cm = ψm (x) · ψm (x)



wij 

ij

ij

+ xj

ψij,m (x) · σˆ 0 (x)dx + xj 2 wij xi ψij,m (x)dx xi

(6.7.9)

With eigenvalues λm eigenfunctions ψij,m (x) and coefficient Cm , Eq. (6.7.5) can be solved and hydrostatic stress can be calculated. The same technique that used in void nucleation phase could be applied to transform growth phase to homogeneous problem. The transformed stress σˆ (x, t) will satisfy the BC (6.7.10) for growth phase. . ∂ σˆ (x, t) .. σˆ (x , t) = . ∂x δ x=x

(6.7.10)

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6 Compact EM Models for Multi-Segment Interconnect Wires

New boundary condition (6.7.10) has to be taken into consideration when building the K matrix for determination of eigenvalues and eigenfunctions. To satisfy the BC (6.7.10), the following equation (6.7.11) is used when building the K matrix: ωj,m csc(ωj,m lj )ψj,m − ωj,m cot(ωj,m lj )ψ,m = ψ,m /δ

(6.7.11)

where j is a branch with one end  at void nucleation. The rest of steps to solve for the transient stress σ (x, t) in void growth phase is the same as those in void nucleation phase, described in previous part.

6.8 Summary In this chapter, we have presented a modeling and analysis technique for EM reliability analysis in multi-segment interconnect tree with wire segment lengths, which reflects practical VLSI interconnect architectures and interconnect layoutdesign techniques. We have presented several compact models in this chapter. We start with the compact models for three-terminal wires by using the Laplace transformation technique. We have derived an exact analytical solution to the stress evolution equation for the void nucleation phase during EM of this type of interconnect tree. Then we presented the extension of this models to consider the time-varying temperature conditions. On top of this, we further presented analytical EM model for void nucleation phase for more general multi-segment star-liked using Laplace transformation technique. Finally, we further presented another closed-form EM stress solution based on integral transform technique, which could efficiently calculate the hydrostatic stress evolution over time for straight-line multi-segment metal wires stressed with different current densities and for general two-dimensional multi-segment interconnect wires as well.

References 1. C.W. Chang, Z.-S. Choi, C.V. Thompson, C.L. Gan, K.L. Pey, W.K. Choi, N. Hwang, Electromigration resistance in a short three-contact interconnect tree. J. Appl. Phys. 99(9), 094505 (2006) 2. H. Chen, S.X.-D. Tan, V. Sukharev, X. Huang, T. Kim, Interconnect reliability modeling and analysis for multi-branch interconnect trees, in Proceedings of the Design Automation Conference (DAC) (IEEE, Piscataway, 2015) 3. H. Chen, S.X.-D. Tan, X. Huang, T. Kim, V. Sukharev, Analytical modeling and characterization of electromigration effects for multibranch interconnect trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11), 1811–1824 (2016) 4. C. Chen, S.X.-D. Tan, J. Peng, T. Kim, J. Chen, Analytical modeling of electromigration failure for VLSI interconnect tree considering temperature and segment length effects. IEEE Trans. Device Mater. Reliab. 17(4), 653–666 (2017) 5. Comsol multiphysics. https://www.comsol.com/ [Oct. 16, 2013]

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6. C.L. Gan, C.V. Thompson, K.L. Pey, W.K. Choi, Experimental characterization and modeling of the reliability of three-terminal dual damascene CU interconnect trees. J. Appl. Phys. 94(2), 1222–1228 (2003) 7. C.S. Hau-Riege, A.P. Marathe, Z.S. Choi, The effect of current direction on the electromigration in short-lines with reservoirs, in IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2008), pp. 381–384 8. X. Huang, T. Yu, V. Sukharev, S.X.-D. Tan, Physics-based electromigration assessment for power grid networks, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2014) 9. X. Huang, A. Kteyan, S.X.-D. Tan, V. Sukharev, Physics-based electromigration models and full-chip assessment for power grid networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11), 1848–1861 (2016) 10. M.A. Korhonen, P. Bo/rgesen, K.N. Tu, C.-Y. Li, Stress evolution due to electromigration in confined metal lines. J. Appl. Phys. 73(8), 3790–3799 (1993) 11. M. Lin, A. Oates, An electromigration failure distribution model for short-length conductors incorporating passive sinks/reservoirs. IEEE Trans. Device Mater. Reliab. 13(1), 322–326 (2013) 12. M.H. Lin, A.S. Oates, Electromigration failure of circuit interconnects, in 2016 IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2016), pp. 5B-2-1– 5B-2-8 13. M.H. Lin, A.S. Oates, Electromigration failure time model of general circuit-like interconnects. IEEE Trans. Device Mater. Reliab. 17(2), 381–398 (2017) 14. Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron, Interconnect lifetime prediction under dynamic stress for reliability-aware design, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2004), pp. 327–334 15. Z. Lu, J. Lach, M.R. Stan, K. Skadron, Improved thermal management with reliability banking. IEEE Micro 25(6), 40–49 (2005) 16. A.S. Oates, M.H. Lin, Electromigration failure of circuit—like interconnects: short length failure time distributions with active sinks and reservoirs, in 2014 IEEE International Reliability Physics Symposium (IEEE, Piscataway, 2014), pp. 5A.2.1–5A.2.7 17. J. Peng, H.B. Chen, H. Zhao, Z. Sun, S.X.D. Tan, Dynamic temperature-aware reliability modeling for multi-branch interconnect trees, in 2017 IEEE 12th International Conference on ASIC (ASICON) (IEEE, Piscataway, 2017), pp. 92–95 18. S.X.-D. Tan, H. Amrouch, T. Kim, Z. Sun, C. Cook, J. Henkel, Recent advances in EM and BTI induced reliability modeling, analysis and optimization. Integr. VLSI J. 60, 132–152 (2018) 19. C.V. Thompson, S.P. Hau-Riege, V.K. Andleigh, Modeling and experimental characterization of electromigration in interconnect trees, in AIP Conference Proceedings, vol. 491 (AIP, 1999), pp. 62–73 20. S. Wang, H. Zhao, S.X.-D. Tan, M.B. Tahoori, Recovery-aware proactive TSV repair for electromigration in 3D ICs, in Proceedings of Design, Automation and Test In Europe (DATE) (IEEE, Piscataway, 2017), pp. 220–225 21. X. Wang, H. Wang, J. He, S.X.-D. Tan, Y. Cai, S. Yang, Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks, in Proceedings of Design, Automation and Test In Europe (DATE) (IEEE, Piscataway, 2017) 22. X. Wang, H. Wang, J. He, S.X.D. Tan, Y. Cai, S. Yang, Physics-based electromigration modeling and assessment for multi-segment interconnects in power grid networks, in Design, Automation Test in Europe Conference Exhibition (DATE) (IEEE, Piscataway, 2017), pp. 1727– 1732 23. X. Wang, Y. Yan, J. He, S.X.-D. Tan, C. Cook, S. Yang, S.X.-D. Tan, Fast physicsbased electromigration analysis for multi-branch interconnect trees, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2017) 24. F.L. Wei, C.L. Gan, T.L. Tan, C.S. Hau-Riege, A.P. Marathe, J.J. Vlassak, C.V. Thompson, Electromigration-induced extrusion failures in Cu/low-k interconnects. J. Appl. Phys. 104, 023529 (2008)

Chapter 7

EM Assessment for Power Grid Networks

7.1 Introduction Continuous increase in the die size accompanied by reduction of the metal line cross sections and, hence by increase of the current densities governed by a technology scaling, results in an increasingly difficult EM signoff when the traditional EM checking approaches are employed. In these approaches, the EM-induced failure rates of the individual interconnect lines are considered as a measure of EM-induced reliability and, in the extreme end, a mean time to failure (MTTF) of the weakest segment is accepted as a measure for the whole chip lifetime. It results in a very conservative design rules for the current densities that can be used in the chip design for a particular technology node in order to avoid EM failure. A very different way to EM assessment can be proposed from the positions of interconnect functionality, when the failure means its inability to function properly. There are two major functions of the chip interconnect: providing a connectivity between different parts of design for a signal propagating, and supplying a voltage. EM can degrade both these functions by degrading the conductivity of the individual segments of the interconnect circuits. The difference is in the types of electrical currents employed in these two cases. Indeed, the signal lines carrying bidirectional or pulsed currents are characterized by very long times to the EM-induced failure. It is caused by a repetitive increase and decrease of the mechanical stress at the line ends, caused by the excessive atom accumulation and depletion governed by the electron wind force and stress gradient. In contrast, power lines carrying unidirectional currents can fail in much shorter times due to continuous stress buildup under the EM effects. Thus, we can conclude that EM-induced chip failure occurs often when the degrading P/G network leads to a severe IR drop problem. It means that loss of performance, which is a parametric failure, should be considered as the practical criterion of the EM-induced failure. It is clear that a structure of the power grid, which is characterized by high level of redundancy, can affect the kinetics of failure development. Indeed, due to redundancy, the failures of some of © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_7

153

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7 EM Assessment for Power Grid Networks

interconnect segments do not necessarily result in a critical IR drop on the P/G grid causing an electrical malfunction [1, 7]. Thus, more accurate and less pessimistic full-chip EM assessment requires new methods dealing with the grid structure and redundancy. An ideal EM assessment assumes a calculability of transient current densities and temperatures in each tree across interconnect. A complexity of extraction of these distributions is acerbated by an uncertainty in workload taking place in modern chips. Its complex multi-modal behavior results in a dependency of the power dissipated by different blocks on the modes of operation. It means that current densities and temperatures in different interconnect trees should be estimated for different workloads and should be used for prediction of MTTF occurring in different scenarios including worst-case conditions for voltage drop [1]. In this chapter, we present a novel approach and techniques for physics-based EM assessment in power delivery networks of VLSI systems [4], which is based on the developed physics-based EM models in Chap. 2 and the EM-induced IRdrop degradation criterion that replaces the traditional conservative weakest segment method.

7.2 New Power Grid Reliability Analysis Method In this section, we present the proposed new power grid reliability analysis method using the nucleation and growth concepts and physics-based EM models we discussed in the previous sections.

7.2.1 Power Grid Models Because of the concern with the long-term average effects of the current, in EM related work a DC model of the power grid is generally assumed [1]. As a result, we need to consider only the EM-induced kinetics of the power grid network resistances. As the current sources is transient, we will show how to compute the effective-EM current and EM current sources later. In our problem formulation, each mortal wire, which is the subject to the EM impact, will start to change its resistance value upon achieving the nucleation time. As a result, we end up with the power grid systems, which is a linear, time-varying, and driven by the DC effective currents. For a power grid network with n nodes, G(t) × v(t) = I (t)

(7.2.1)

7.2 New Power Grid Reliability Analysis Method

155

where G(t) is a n × n time-varying conductance matrix; I (t) is the transient current source vector; v(t) is the corresponding vector of nodal voltages. In our problem, the time scale is the EM time scale, which can be months or years.

7.2.2 Effective-EM Current Density EM is a long-term cumulative failure phenomenon. In reality the P/G nets are characterized by the time-dependent current densities. Small background DC currents distributed across the grid are perturbed with the unipolar pulses generated by switching cells. An intensity of these perturbations depends on the activity factors of standard cells, which are different for different workloads. In general, total current passing between the neighbor power vias is a unidirectional pulsed current. Unidirectional current and the long length of the power net segments can provide the conditions for σcrit accumulation. In this case, the criterion for determination of the effective DC current should be established [10]. The effective-EM currents will give the same lifetime as the transient waveforms. It can be understood from the following. Equation (7.2.2) provides the kinetics of the hydrostatic stress in the interconnect line caused by applied current. A simple integration provides: σ (t, x) − σ0 =



∂ ∂x

t

κ 0

eZρ ∂σ dt + κ ∂x 





t

(7.2.2)

j dt 0

It means that under assumptions made for derivation of Eq. (2.3.10) in [5], the stress distribution at any particular instant in time is governed by the time integral of the applied current density. This can be used as a justification of replacing the current density waveforms with the time averaged DC current density. For most general cases of both unidirectional and bidirectional current densities, we have the following effective-EM current density [6, 10]: jtrans,EM,eff =

1 P

 0

P

j + (t)dt − R



P

|j − (t)|dt

(7.2.3)

0

where j + (t) and j − (t) are the current densities of the positive and negative phases of the bipolar current, R is the EM recovery factor determined by experiments, P is the period of the current density waveform. When the current density is unidirectional, the effective-EM current density jtrans,EM,eff is the time averaged current density. Furthermore, if the current sources are time dependent, we can compute the effective-EM current sources in a similar way, which will generate the same effective current densities in each interconnect tree so that only one DC analysis is required for EM analysis at each EM time point.

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7 EM Assessment for Power Grid Networks

7.2.3 New Analysis Method Flow Now we present the new EM-induced reliability analysis algorithm and flow for P/G networks. In our formulation of the dynamic P/G networks, the wire resistance begins to change (increase) starting with the nucleation time (tnuc ). After this, their resistance changes will be computed by Eq. (2.6.2). First we compute initial current densities j0,mn for each branch of every tree. Then, by using the proposed treebased EM analysis method, we obtain the stresses for all branches in all trees. Next, we identify the trees, which are the subjects for void nucleation: hydrostatic stress at any of the tree nodes is larger than σcrit . Then, we compute the set of i tnuc for all suspicious branches. Branch characterized by the largest stress and smallest tnuc among others sets up the initial (starting) time t0 , which is indicated i } in step 4 in the algorithm, and the branch will be included in the by t0 = min{tnuc growth phase pool. After this, we move to next step t1 = t0 + t. The chosen timestep t should be small enough to detect approximately an instant in time when the critical stress is developed in any branch of any interconnect tree. We update power grid conductance matrix G due to resistance change in the wire in the growth phase, re-compute current densities j for each wire of each tree again, and then repeat the previous steps: stress calculation, identification of the branches satisfying σ > σcrit , putting the most vulnerable branch into growth phase pool if it reaches its tnuc , and moving to the next step: t2 = t1 + t. We continue this process until the IR drops at one or more nodes reach the given threshold such as 10% of the supply voltage. We identify this instant in time as the TTF of the whole P/G network. It is worth noting that, in step 7 in the algorithm, we consider the generation of the void saturated volume when updating the branch resistance. For each branch in the growth phase, we first obtain its void volume saturation time tVS . Then we compare tVS with last instant in time ti−1 . Only the branches in the growth phase pool with tVS > ti−1 have resistance increase during [ti−1 , tVS ].

7.3 Numerical Results and Discussions The proposed EM assessment method is implemented in C++ on a 2.3 GHz Linux server with 132 GB memory and validated by the IBM power grid benchmark circuits [8], which has both power networks and ground networks. The power networks are used to test our method and their source current values are modified to ensure that the initial IR drop of any node is smaller than the threshold value. In this work, we assume the interconnect material as copper and the power grid circuit fails when the largest IR drop exceeds 10%Vdd . Parameters used in our model are listed in Table 7.1. Table 7.2 shows the power grid lifetime obtained from both Black’s equation and our proposed approach. In Black’s equation based analysis, Eq. (2.2.2) is used to estimate the MTTF of single metal line, where Tstress = 600 K, jstress = 3 MA/cm2 ,

7.3 Numerical Results and Discussions

157

Algorithm 1 New power grid EM-induced reliability analysis algorithm Input: power grid networks with current inputs, time step, and technology parameters Output: The time reaching the threshold IR-drop and failed branches. 1: Compute the initial effective EM current density. 2: Divide the power grids into interconnect trees with a number of connected branches. 3: Compute the steady state distributions of hydrostatic stress inside each interconnect tree. 4: Conclude all suspicious branches  i whose tensile stress is larger than critical stress. Calculate the nucleation time t0 = min tnuc for the most vulnerable branch (with the largest stress). 5: Start the analysis from time t = t0 . Branch with nucleation time t0 enters into the growth phase. 6: while the largest IR-drop ≤ threshold do 7: Move to next instant in time t := t + t, update the wire resistances for wires with void volume increase. 8: Perform the DC analysis of the power grids. Recompute the current densities of each branch. 9: Compute the steady state distributions of hydrostatic stress inside each branch based on the updated EM current densities. 10: For each  i tree,  identify new branches with the stresses exceeding the critical value.  Calculate i the min tnuc for suspicious branches in the nucleation phase. If min tnuc ≤ t, the corresponding branch steps into the growth phase. 11: end while 12: Output t and the failed branch

Table 7.1 Parameters used in the proposed model [4]

Parameter EV EVD TZS B

Value 0.75 eV 0.65 eV 623 K 1 × 1011 Pa

Parameter T σT Z σcrit

Value 373 K 400 MPa 10 500 MPa

Table 7.2 Comparison of power grid MTTF using Black’s equation and the proposed model [4] Power grid Name IBMPG2 IBMPG3 IBMPG4 IBMPG5 IBMPG6 IBMPGNEW1 IBMPGNEW2

Nodes 61,797 407,279 474,836 497,658 807,825 715,022 715,022

Time to failure (years) Black’s equation Proposed model Series Mesh No void sat With void sat 6.17 12.83 16.85 18.78 12.79 17.90 23.56 31.97 13.23 22.27 26.97 33.41 4.41 12.34 19.13 25.16 8.44 10.89 14.62 19.85 12.85 13.96 18.84 25.97 12.73 13.84 15.60 21.79

Runtime 6.36 min 5.83 h 14.71 h 40.64 min 1.75 h 16.78 h 15.32 h

Ea = 0.86 eV, and MTTFstress is obtained from Eq. (2.6.1) under stressed condition (used condition characteristics are the same as characteristics used in our predictive work). The current density exponent n is taken as two when failure is nucleation dominated and is taken as one when failure is nucleation dominated. Two different Black’s equation based models are used to compare with the proposed method.

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One is series model, under which the circuit is considered to have failed as soon as any branch fails. The other is mesh model that takes redundancy into account, defining the circuit fails when it cannot deliver required amount of voltage. From the experimental results, we can observe that the Black’s equation based series model would lead to a too pessimistic prediction. The TTF estimated by Black’s equation based mesh model is more conservative than our model because it assumes infinite resistance after the predicted TTF of each branch, while actually the metal line continues to conduct voltage after TTF with increasing resistance. Figure 7.1a, b shows the steady-state hydrostatic stress distribution predicted by the initial current density, and the initial IR-drop distribution in the metal layer that directly connects to the underlying logic blocks, respectively. The locations of voids nucleated during the lifetime of the circuit are demonstrated in Fig. 7.2a. We can observe from Figs. 7.1a and 7.2b that with uniformly distributed temperature, the failure is most likely to occur at the place where the hydrostatic stress predicted by the initial current density is large. It is due to the fact that the branches with larger stress are more likely to nucleate void and, since the void growth rate is almost independent on stress, and a larger stress would result in a larger void saturated volume, which means larger resistance change, the IR drops at these places will more likely to exceed the threshold value. We also implemented the assessment method, which assumes that the void keeps growing once it is nucleated. Figure 7.3a, b are the experimental results obtained from the model in which the void volume saturation is not considered. The distribution of the voids in the P/G net and the distribution of IR drops in the first metal layer at the instant in time the circuit fails are depicted, respectively. It is observed that when the void saturated volume is taken into account, the more voids are distributed in the circuit when compared to the distribution where the voids keep growing upon nucleation. Table 7.2 summarizes the comparison between TTF obtained when considering and neglecting void volume saturation. We can conclude that for the same circuit, introducing void volume saturation would result in a larger number of nucleated voids, thus a larger number of branches in the circuit whose resistance has changed due to EM effect, but a longer TTF. It is due to the fact that when the void volume saturation has been considered, a void would stop growing when its volume reaches the saturation state. It starts growing again only when the current passing this branch increases due to voids generated in neighbor branches/trees. Thus the overall change of branch resistance is slower than in the case of neglected void volume saturation, more time and more voids will be needed for the circuit to meet the same failure criteria. So accounting for the void volume saturation in the EM analysis is necessary in order to get precise circuit lifetime. Node voltage keeps changing with time after creation of the first void in the network and its value can be tracked as shown in Fig. 7.4. Effect of different

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Fig. 7.1 (a) Steady-state hydrostatic stress (Pa) distribution predicted by the initial current densities and (b) initial IR-drop (V) distribution, in the layer that directly connects to circuits (M3) of IBMPG2 [4]

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Fig. 7.2 Void distribution, (a), and the IR-drop (V) distribution in the layer that directly connects to circuits (M3), (b), of IBMPG2 at t = TTF. Void volume saturation is taken into account [4]

average chip temperatures on P/G network’s TTF is investigated. From Fig. 7.5, the experimental result reveals that TTF obtained from our proposed method obeys the same functional dependencies as the Black’s equation, which is the Arrhenius dependence on temperature. So reducing the temperature can efficiently suppress the EM effect.

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Fig. 7.3 Void distribution, (a), and the IR-drop (V) distribution in the layer that is directly connected to circuit (M3), (b), of IBMPG2 at t = TTF. Void volume saturation is not considered [4]

7.4 Cross-Layout Temperature and Thermal Stress Characterization This section describes the estimation of within-die temperature and thermal stress distribution. We demonstrate the characterization of power dissipation in the devices and the joule heating in interconnects, then, we detail the temperature simulation

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methodology, which builds a thermal netlist with the effective thermal properties. Further, the thermal stress variation across the layout will be obtained based on the temperature distribution. A 32 nm test-chip is used as the case example to present the flow. Standard cells are used in this design along with seven metal (copper) layers. Figure 7.6 shows the layout of this design with dimension 184 µm × 184 µm. There are 16 layers in total (the Si-layer is divided into a thin Si-device layer that includes power dissipation and a thick Si-substrate layer for thermal analysis purpose). The BEOL (back-end-of-line) geometry information is described in Table 7.3.

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Fig. 7.6 Layout of 32 nm test-chip [4] Table 7.3 Geometry of power grid interconnects (µm) [4]

Layer Contact M1 V1 M2 V2 M3 V3 M4 V4 M5 V5 M6 V6 M7

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Layer 1: Si-substrate; Layer 2: device layer

7.4.1 Full-Chip Power Characterization Power estimation is a challenging task since the result is highly dependent on the workload or typical usage of a chip. We consider both the power dissipation in the devices and joule heating in interconnects. The chip power consists of static

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and dynamic components. Equation (7.4.1) is the power model for each individual primitive block, where a block is considered to be a primitive if it cannot be further decomposed into smaller blocks based on a user settings. The dynamic power comes from the gate switching, in which the block dissipates power by charging the load capacitances of wires and gates and dissipates power during a very short period of time when a conduction path exists between the power and ground voltage connections. Thus, more active block is characterized by the higher dynamic power. In contrast, the static power is due to static current, including the leakage current and presents regardless of a block’s activity level. Pblock = Pstatic + αswitching × Pdynamic

(7.4.1)

Here, Pstatic and Pdynamic are the static and dynamic powers of a block, αswitching is the switching estimate for signals that describes the switching activity of the block. For time-varying currents, the time scale is on the order of picosecond, which is too fine for the thermal time scale. As a result, power averaging is further applied to obtain the power consumption in the device layer. The current flowing through interconnects generates joule heating. Similar to Eq. (7.4.1), we estimate the joule heating in a wire by evaluating both static and dynamic components of generated heat. Figure 7.7a is the power map for the device layer. We selectively show the joule heating in M1, M3, and M6 layers in Fig. 7.7b–d.

7.4.2 Thermal Simulation Methodology Since the temperature affects atom diffusivity, the EM assessment requires accurate local temperature estimation at each interconnect layer in order to adequately account for the temperature-sensitive void nucleation and growth kinetics. In this section, we describe a thermal analysis flow that efficiently estimates the crossdie temperature variation by employing a compact thermal model that represents a die as arrays of cuboidal thermal cells with effective local thermal properties. The methodology includes three steps: (1) extract effective thermal properties of a thermal cell in a layer, (2) generate thermal netlist of the whole chip, and (3) calculate temperature at each thermal node by a circuit solver, see, for example, [3, 9]. As shown in Fig. 7.8, all the considered composite layers are divided into a set of thermal cells defined by a layer thickness and a square window of size L which is chosen based on the simulation accuracy: the finer partitioning provides more accurate results at the expense of the runtime. Each cell contains 6 thermal resistors representing heat propagation in the lateral and vertical directions; a thermal capacitance can be included for transient thermal analysis. The effective thermal conductivities are functions of metal density and routing direction of wires in each metal layer based on the theory of effective thermal properties of anisotropic composite materials [2]. Based on the standard procedure [3, 9], with the extracted thermal resistances, e.g., Fig. 7.9, estimated power

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Fig. 7.7 Power consumption in device layer (0–6.91 mW), (a), and joule in M1 (0–0.06 mW), (b), M3 (0–0.33 mW), (c), and M6 (0–4.53 mW), (d), layers [4]

Fig. 7.8 The die is divided into arrays of thermal cells with 6 thermal resistances in each cell (bin) [4]

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sources, as well as the thermal boundary conditions, the chip can be represented as a thermal netlist, in which the nodal temperatures correspond to the nodal voltages and the powers correspond to the currents. The electric circuit solver can then obtain temperature for each thermal node. In the thermal simulation, performed in the analyzed design, a window size L = 5 µm was chosen for computational efficiency while keeping reasonable temperature resolution. The top surface of the die was kept at T = 330 K, while all other sides were insulated. As shown in Fig. 7.10, the temperature varies across different layers. The temperature distribution in M1 interconnects is shown in Fig. 7.11.

7.4.3 Thermal Stress Estimation Since the residual stress existing in each metal line before the electrical load is applied is responsible for both void nucleation and growth, its distribution should be considered for accurate chip-scale EM assessment. This work focuses on the thermal stress, which is a major source of the residual stress. In the case of metal line embedded into the rigid confinement, which, in the analyzed case of the on-chip interconnect, is comprised by refractive metal and dielectric diffusion barriers and ILD/IMD dielectrics, the initial stress is generated during the system cooling from the stress-free annealing temperature TZS down to the use temperature T . A primary source of this thermal stress is the difference in the coefficients of thermal expansion of the metal αM and confinement αconf , which is mainly determined by the silicon substrate:

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Fig. 7.11 Temperature (K) distribution in M1 layer [4]

Fig. 7.12 Thermal stress (MPa) distribution in M1 layer [4]

σT = B(αM − αconf )(TZS − T )

(7.4.2)

The thermal stress distribution in the M1 layer is demonstrated in Fig. 7.12. Since a lower thermal stress corresponds to a higher layout temperature due to the smaller temperature gap T = TZS − T , the regions with the highest T , Fig. 7.11, are characterized by the smallest σT , Fig. 7.12. Note that more accurate thermal stress estimation should consider the elastic portion of the stress generated by interaction with confinement. This is reserved for the future analysis. Nevertheless,

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the calculated inelastic fraction of the thermal stress demonstrates well the trend caused by the thermal stress variation and its relation to the temperature distribution.

7.5 Impact of Across-Layout Temperature and Thermal Stress on EM 7.5.1 Full-Chip EM Analysis Flow Now we present the new EM-induced reliability analysis flow for P/G networks of the 32 nm test-chip, which accounts for the impacts of within-die temperature and thermal stress variations. The new Algorithm 2 is similar to Algorithm 1 stated in Sect. 7.2. But it first performs thermal analysis and mapped the temperature and thermal stress values to the P/G network interconnects before performing the EM assessment. Thus, different from the uniformly distributed temperature case, the minimum tnuc here is determined by both the hydrostatic stress and the local temperature instead of the maximum hydrostatic stress only. The full-chip EM assessment is achieved through the following steps: • IP block modeling and power grid network extraction: Model IP block’s interaction with the P/G nets through pre-defined connections (pin locations) under various conditions (e.g., input slew and output loading capacitance): run circuit simulations of the transistor netlist annotated with the layout parasitic information; estimate block’s activity based on realistic circuit behaviors, such as the percentage of design switching within a clock cycle. Assuming that each standard cell used in this design has a power (VDD ) pin and a ground (VSS ) pin associated with the power grids, we extract the P/G networks as parasitic circuits with each P/G pin modeled as a DC current source: IDC = Ileakage +αswitching ION . • Cross-layout temperature and thermal stress characterization: First, we characterize power dissipation in devices and joule heating in interconnects by Eq. (7.4.1). Then, upon dividing each layer into multi-thermal cells the local effective thermal properties are computed. The die is further modeled as an equivalent thermal circuit, where the power is represented as current and the temperature is denoted by voltage. We solve the thermal net and get the temperature distribution across the die. Further, the thermal stress distribution can be obtained based on Eq. (7.4.2). Finally, we map the temperatures and the thermal stresses into the layout. • Full-chip EM analysis considering within-die temperature and thermal stress distributions: Each of the interconnect branches is now assigned a local temperature and a local thermal stress, replacing the average values used in the traditional EM analysis. In the formulation of the dynamic P/G networks, the hydrostatic stress is analyzed in interconnect trees; the wire resistance begins to change (increase) starting with the nucleation time (tnuc ), calculated by Eq. (2.6.1), and later their resistance changes are estimated by Eq. (2.6.2). The generation of void saturated volume should be checked before updating

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Algorithm 2 New power grid EM-induced reliability analysis algorithm considering cross-layout temperature and thermal stress variations Input: layout design files, required chip LT (LTREQ ), chip failure criteria, time step (t) Output: TTF and failed segment (if T T F < LTREQ ), largest IR drop, void locations 1: IP block power modeling and P/G network extraction. 2: Chip power consumption and interconnect Joule heating estimation. 3: Thermal analysis: obtain within-die temperature and thermal stress distribution. Apply results in following full-chip EM assessment. 4: Divide the P/G nets into a set of interconnect trees. 5: Calculate the initial effective EM current density for each branch and compute the steady state distributions of hydrostatic stress inside each interconnect tree. 6: Find all suspicious branches with the tensile stress larger than the critical value. Find i }). nucleation time for the first void (t0 = min{tnuc 7: Start the analysis from time t = t0 . Branch with the first nucleated void enters the growth phase. 8: while the largest IR drop ≤ threshold or t < LTREQ do 9: Move to next instant in time t := t +t: For branches in the growth phase, update resistance for branches with non-saturated voids. 10: Perform the DC analysis of the P/G nets. Re-compute the hydrostatic stress distribution inside each tree. i ) for all suspicious branches 11: For each tree, find the minimum void nucleation time (min{tnuc i } ≤ t, the corresponding branches steps into the growth in the nucleation phase. If min{tnuc phase. 12: end while 13: Output t, IR drop map and locations of voids

the resistance. As indicated in step 7 in Algorithm 1, the P/G network starts to i }, which is characterized degrade after the first void has nucleated at t = min{tnuc by both hydrostatic stress and temperature. Then at each instant in time t := t + t, we update resistance of all branches with non-saturated voids; recalculate current density and hydrostatic stress; and check if there are any new voids nucleated during the previous time increment t. The chosen time-step t should be small enough to detect approximately an instant in time when the critical stress is developed in any branch of any tree. We continue the process until the IR drops at one or more nodes reach the given threshold, for example, 10%VDD or when the time instant has reached the required lifetime (LTREQ ).

7.5.2 Experimental Results and Discussion The proposed full-chip thermal variation aware-EM assessment method is implemented by C++ code on a 2.4 GHz Linux server and tested on the 32 nm standard cell IC design. We use Calibre tools for layout extraction and circuit analysis. The EM analysis results can be mapped into the BEOL layout and displayed in Calibre RVE tool. The power net and ground net are symmetrical and independent on each other since the standard cells are modeled as effective DC current sources. In this

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work, the thermal analysis targets the whole chip and the EM analysis focuses on the power net. We assume the chip fails when the maximum IR drop exceeds 10%VDD . Figure 7.13b demonstrates the EM-induced IR drop increase in the power net. The results show that the most significant IR drop change takes place in the M1 layer, which is the closest layer to devices. Comparing it with the initial steadystate hydrostatic stress shown in Fig. 7.13a, which includes the thermal stress and the steady-state EM stress computed by the initial current densities, and with the temperature distribution shown in Fig. 7.11, we can get the conclusion that the EMinduced IR-drop degradation is more likely to occur at the locations with both high hydrostatic stress and high local temperature. Figure 7.13c plots the change of the largest IR drop in the power net over time, caused by the increasing number of nucleated voids. It shows that the worst IR drop is smaller than 10%VDD (VDD = 1.1 V) when the simulation stops, which means this chip has a longer lifetime than the requirement.

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Effect of Cross-Layout Temperature Variation

To evaluate the impact of within-die temperature variation, we performed EM assessment under assumption of uniform temperature (T = 367.4 K, averaged temperature across the chip) and with the calculated non-uniform temperature distribution. Uniform average thermal stress σT = 434.55 MPa was assumed in both cases. The evolution of IR-drop degradation and the locations of branches with voids when the simulation stops are shown in Figs. 7.14 and 7.15, respectively. We have several interesting observations: First, the accelerated voltage degradation caused by high local temperatures at lower layers was observed in the case of non-uniform temperature distribution during the earlier time. Second, as time goes by, the drastic IR drop increase is found under the average temperature assumption. At this time these two assumptions result in totally different analysis results (the average temperature case causes a false-alarm chip failure). This is mainly due to the incorrect prediction of voids nucleated in the top layers where the actual local temperature is much lower than the average value, which can be viewed by comparing Fig. 7.15a, b.

7.5.2.2

Effect of Spatial Thermal Stress Variation

Next, we have investigated the impact of thermal stress on EM effects by comparing the IR drop evolution in two cases characterized by non-uniform and uniform (σT = 434. 55 MPa) thermal stress distributions. Figure 7.16 shows the IR drop evolution taking place in these two cases. Contrary to the impacts of spatial temperature variation, the retarded voltage degradation has been observed when the thermal stress variation was taken into account. The failure prefers to occur at places where both the hydrostatic stress and local temperature are high. Since a higher temperature corresponds to a lower thermal stress, when spatial thermal

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7.6 Summary In this chapter, we proposed and implemented a new EM assessment method for power delivery networks of VLSI circuits. In the proposed approach, an increase in the IR drop above the threshold level, caused by EM-induced increase in resistances of the individual interconnect branches, was considered as a failure criterion. It replaced a currently employed conservative weakest branch criterion, which does not account an essential redundancy for current propagation existing in the P/G networks. EM-induced increase in the resistance of the individual grid branches was described in the approximation of our developed physics-based formalism for void nucleation and growth discussed in Chap. 2. We implemented the treebased analysis approach to calculate the void nucleation times in the group of branches comprising the interconnect tree. As a result, P/G networks became timevarying linear networks. A developed technique for calculating the hydrostatic stress evolution inside a multi-branch interconnect tree allows to avoid over optimistic prediction of the TTF made with the Blech–Black analysis of individual branches of interconnect tree. Experimental results obtained on a number of IBM benchmark circuits show that the proposed method will lead to less conservative estimation of the lifetime than the existing Black–Blech based methods. It also revealed that the EM-induced failure was more likely to occur at the place where the hydrostatic stress predicted by the initial current density was large and was more likely to occur at longer times when the saturated void volume effect was taken into account.

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Fig. 7.15 The branches with voids (blue color) at the time when simulation stops in two cases: (a) uniform averaged temperature and (b) with temperature variation. Uniform thermal stress distribution is considered in both cases [4]

We next improved the full-chip EM assessment methodology by integrating it with temperature and thermal stress assessment methods, where the temperature simulation is realized by characterizing the power dissipation in devices and joule heating in interconnects, and by building the thermal netlist with the effective thermal properties. Then, the thermal stress variation across the layout was obtained

References 9

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Fig. 7.16 Comparison of the IR drop evolutions calculated w/o and w/ thermal variation assessments. Temperature variation is considered in both cases [4]

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based on the temperature distribution. Experimental results obtained on a 32/28 nm test-chip show that traditional assumption of the uniform average temperature led to inaccurate predictions of the time to failure. Furthermore, the consideration of thermal stress variation resulted in a retarded EM-induced degradation.

References 1. S. Chatterjee, M.B. Fawaz, F.N. Najm, Redundancy-aware electromigration checking for mesh power grids, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2013), pp. 540–547 2. R.M. Christensen, Mechanics of Composite Materials—Richard M. Christensen—Google Books (Dover Publication, New York, 2005) 3. W. Huang, M.R. Stan, K. Skadron, Parameterized physical compact thermal modeling. IEEE Trans. Compon. Packag. Technol. 28(4), 615–622 (2005) 4. X. Huang, A. Kteyan, S.X.-D. Tan, V. Sukharev, Physics-based electromigration models and full-chip assessment for power grid networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11), 1848–1861 (2016) 5. M.A. Korhonen, P. Bo/rgesen, K.N. Tu, C.-Y. Li, Stress evolution due to electromigration in confined metal lines. J. Appl. Phys. 73(8), 3790–3799 (1993) 6. K.-D. Lee, Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current, in IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2012), pp. 6B.3.1–6B.3.4 7. V. Mishra, S.S. Sapatnekar, The impact of electromigration in copper interconnects on power grid integrity, in 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC) (IEEE, Piscataway, 2013), pp. 1–6 8. S.R. Nassif, Power grid analysis benchmarks, in Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC) (IEEE, Piscataway, 2008), pp. 376–381 9. A. Sridhar, A. Vincenzi, M. Ruggiero, T. Brunschwiler, D.A. Alonso, 3D-ICE: fast compact transient thermal modeling for 3D-ICs with inter-tier liquid cooling, in Proceedings International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2010), pp. 463–470 10. V. Sukharev, X. Huang, S.X.-D. Tan, Electromigration induced stress evolution under alternate current and pulse current loads. J. Appl. Phys. 118, 034504 (2015)

Chapter 8

Resource-Based EM Modeling DRM for Multi-Core Microprocessors

8.1 Introduction In this chapter, a new approach for system-level reliability management for multi/manycore microprocessors is introduced [13]. Early works mainly focus on dynamic thermal management (DTM) techniques, which have been proposed in the past to keep the temperature to stay below a limit to avoid the temperature-sensitive long-term reliability problems [2, 8, 21]. Those techniques, which typically consist of dynamic voltage and frequency scaling (DVFS), task throttling and clock gating, were first developed for single core microprocessors. Recently, these techniques have been extended for multi-core architectures and multiprocessor system-ona-chips. They include frequency-control method [30], the combined DVFS and task migration methods [6, 16], the predictive control method [28, 29], and task migration based methods [4, 7, 14, 18, 19, 28]. However, all of those techniques fail to explicitly consider the reliability and lifetime directly. As we will show in the work, the thermal-only DVFS can lead to much shorter lifetime for the many-core processors than reliability-aware DVFS methods. The new resource-based EM models allow more flexible EM-reliability management for multi/many-core systems. As an application for the new resource based reliability model, we present a new run-time reliability management technique. It consists of two optimization knobs. The first one is a new task migration method, which explicitly balances consumption of EM resources for all the cores. The new method aims at the equal chance of failure of these cores, which will maximize the lifetime of the whole multi-/manycore system. To more efficiently regulate the lifetime of the multi-/manycore system, DVFS technique (by using different performance states (p-states), which can represent different operating voltages and frequencies) can be employed to reduce power of the systems to meet lifetime requirement of the cores. In this way, it allows compensation of the excessively consumed life time of all the cores when the chip is loaded with heavy tasks for a

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certain period of time and the new method essentially can have more flexibility to handle heavy task assignment on demand. We remark that the proposed system-level resource-based reliability models and the online management methods can also be applied to other long-term reliability effects such as TDDB (time dependent dielectric breakdown), NBTI (negative bias temperature instability), and hot carriers, etc. as these reliability effects can also be modeled as consumable resources and their consumption rates are also very sensitive to temperature (thus power). As a result, those long-term effects can be considered at the same time if they all can be modeled as resources, which then can be easily managed and optimized at the system level. But in this paper, we only focus on the reliability management for EM effects as an application of the proposed resource models. The electromigration (EM)-induced time to failure (TTF) at the system level is modeled as a resource, which is abstracted, from a recently proposed physicsbased EM model, at the chip level. In this model, a single core can spend the TTF resources at different rates specified by the temperature and the related power consumption. The new resource-based EM model allows more flexible EMreliability management for multi/many-core systems. As an application of the new model, we present a novel task migration method to explicitly balance consumption of EM resources for all the cores. The new method aims at equalizing the probability of failure of each core, which will maximize the lifetime of the whole multi/manycore system.

8.2 Problem Formulation and Reliability Modeling As long-term reliabilities and performance are intrinsically conflicting factors, one has to consider them jointly at system-level optimization as shown in the existing works [11, 20, 23]. To consider and model the reliability effects due to various failure mechanisms, many existing works use the so-called sum of failure rate model (SOFT) [17] to compute MTTF of a whole system from its components. SOFR model consists of the competing risk model which estimates the failure rate of each component and the series model which estimates the failure rate of the system based on failure rates of each component. Such SOFR models only work when the following conditions are met: first, each failure mechanism proceeds independently (they do not affect each other). Second, the whole system fails when the first of its component fails. For EM-related reliability on a practical power grid network neither conditions are met. In this work, we try to mitigate those problems by using a new physics-based EM model and redundancy-aware analysis techniques to compute the TTF of a power grid for given current sources, supply voltages, and temperatures. For multi-core microprocessors, the optimization could be achieved through proper reliability management of resources and tasks. In this work, we treat MTTF as a reliability resource that could be consumed and controlled during task

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executions. For optimization purposes, instead of dealing with the difficult tradeoff between performance and reliability in a given period, in this work, we target a methodology allowing to compensate the lifetime excessively consumed during a certain period when the processor is loaded with heavy tasks.

8.3 System-Level EM Modeling and EM-Reliability Management Method In this section, we first introduce the novel system-level resource-based EM models and then we present the new dynamic EM-induced reliability management method for many-core systems.

8.3.1 System Level EM-Reliability Resource Consumption Model Given the new physics-based EM model, we now introduce our system level EMreliability resource consumption model. Based on the EM model discussed in the previous section, instead of using the EM-induced stress and resistance values, we can view the interconnect time to failure (TTF) as the resource. TTF occurs when the interconnect tree resistance has significant change due to the EM process so that the resulting voltage drops in the power grid network exceed 10% (or other predefined value). Once electrical current starts to flow through the wire, the EM process starts to spend the resource at a rate, which is a function of the temperature and current density. We notice that treating the EM as a resource was first introduced in [15]. But this work is still based on the traditional Black’s equation. Specifically, the reliability of a component is a probability function R(t), defined on the interval [0, inf], that the component (system) operates correctly with no repair up to time t. The failure rate of a component, λf , is the conditional probability that the component (or system) fails in the interval [t, t + t] while assuming correct operation up to time t. The mean time +to failure MTTF is the expected time at which a component fails, i.e., MTTF = R(t)dt. If the failure rate λf is constant with time, then MTTF is λ1f and the reliability is R(t) = e−λf t . In general, failure rates are time dependent. In the following, the TTF is still used instead of MTTF as explained before. In order to explain a system-level reliability on a multi-core processor, we use one processor lifetime as the shortest lifetime among the cores. This methodology is widely used because if one core fails in a short time, then more stress to the rest of cores to deliver the same performance until all the cores fail or the processor cannot meet the performance requirement.

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As a result, all the cores with the similar lifetime (which is close to the smallest lifetime) will be better off. We can illustrate this with a simple example: suppose that we have two cores. The performance requires both cores to be active (even in the low power models). In this case, if one core fails much faster, its failure time will be the whole system (two-core processor) failure time. While if we can keep both core live as much longer as possible by using them evenly so that their lifetime is similar, the system will obviously live longer than the first case. On the other hand, recently, one study used performability as the ratio of number of nonfailure cores over total number of cores [22] to explain chip multiprocessor (CMP). But the specific mechanism has not introduced and is too abstract, so we use the shortest lifetime in this paper as this method has been shown in many published works [5, 12, 25]. Let’s assume that we have a set of different time intervals pk characterized by different workloads in terms of current n density jk and temperature Tk for a processor or a core. It means that P = k=1 pk is the total execution time. Each kth workload, if it lasts till imaginary failure, provides time to failure TTFk . Thus the failure rate at the kth workload which last pk is λk = 1/TTFk . Then the average failure rate for the considered set of workloads is λavg =

n k=1

pk pk n λk λk = P j =1 pj n

(8.3.1)

k=1

As a result, the expected time to failure or average lifetime of the whole processor, TTF is [15], TTF =

1 =  n λavg

k=1

1 1 pk TTF k



(8.3.2) /P

Based on the (8.3.2), we can treat the lifetime of the processor specified by TTF as a resource that could be consumed as the core works. We first define the specified TTF as a nominal value, denoted as TTFN , which is the intended or required life of the core under a typical temperature and power setting for a core or system. For example, a processor has nominal TTF of 10 years under temperature of 70 ◦ C and working power of 20 W as a specification. However, in reality, TTF varies under different temperature and power settings. For the kth workload, its time to failure is TTFk and the overall time to failure for the whole set of workloads is given in (8.3.2). In reality, depending on different workload settings, the consumption rate could be either higher or lower than its nominal rate, and we define consumption rate for workload k as crk =

TTFN TTFk

(8.3.3)

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in which the lifetime in real case (TTFk under the kth workload) could be estimated by the new proposed reliability model in the previous subsections. In the nominal case, the core is working under its specified temperature and power setting, and it has lifetime given by TTFN . Hence, the amount of lifetime consumed by the core in each second is 1 EM second, that is to say, the nominal average consumption rate is crN = 1. If TTFk > TTFN , then crk < crN , which indicates that the core is consuming its nominal lifetime at a lower rate, and thus the real lifetime is longer than the nominal one. Conversely, if TTFk < TTFN , then crk > crN , which indicates that the core is consuming its nominal lifetime at higher rate, and thus the real lifetime is shorter than the nominal one. Hence, instead of saying TTF changes, we perceive TTF as a constant resource, which is given by TTFN , and (8.3.3) is the consumption rate (crk ) of TTF that determines the real lifetime of the core. If the summation of EM slacks over a period is zero, then the lifetime or TTF of the core during that period will the TTFN as predicted by (8.3.2).

8.3.2 EM-Reliability Resource-Based Task Migration First, we present the new task migration method to balance the EM-reliability resources, which is different from the conventional task migration method that targets improvement of on-chip temperature profile. According to the definition of average TTF consumption rate defined by (8.3.3), if crk > crN persistently, it will introduce excessive consumption of TTF, which would possibly lead to early failure of the core if no compensation is made. In real application, it is common that crk > crN during the period when heavy tasks are assigned to the core, and the lifetime is excessively consumed during this period, while on the other hand, when light tasks are assigned to the core, crk < crN , and less lifetime is consumed during this period. We define TTF resource slack (Sd ) as the accumulative TTF consumption difference between real case and nominal case over all different task execution periods, which is calculated through Sd =

(crN − crk )pk

(8.3.4)

k=1

 TTFk − TTFN  pk = TTFk k=1  TTF(t) − TTFN d(t) = TTF(t)

(8.3.5)

(8.3.6)

where crk is the average consumption rate during the kth execution cycle, crN is the nominal average consumption rate, in the continuous time, and TTF(t) is TTF at time t based on the temperature and current densities at t. In the sequel, we assume that all the execution cycles are same, i.e., pk = ECT is a constant for easy presentation and the time period is defined as Execution Cycle

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Time (ECT). This restriction can be easily removed as the proposed method can trivially be applied to various execution times. Given (8.3.4), we consider the following scenarios: • If Sd = 0, it indicates the overall consumption of the core would lead to its intended TTF. It is easy to verify lifetime = TTFN by using (8.3.2) in this case. • If Sd < 0, it indicates that the lifetime is excessively consumed for the past execution periods, and it requires compensations in future to avoid early failure. • If Sd > 0, it indicates that the lifetime is consumed less than its nominal rate for the past execution periods, and it allows increased consumptions in future without causing early failure. In a multi-core system, for each core i, we could calculate TTF resource slack for core i at the end of each task execution cycle, and denote it as Sd (i). We could also characterize the average power of the tasks in the coming execution cycle for each core. Assuming that the multi-core processor has N cores with no process variation, and the average power of the tasks on each core are denoted as P1 ,P2 , . . . , PN , and the TTF resource slack for each core are denoted as Sd (1), Sd (2), . . . , Sd (N ). To balance the EM-reliability of all the cores, we sort out the order of power consumptions and that of the TTF resource slack, assign the highest power to the core with the highest value of Sd , assign the second highest power to the core with the second highest value of Sd , and so on. The overall task migration scheme is shown in Fig. 8.1, in which Sd is calculated based on (8.3.4) and (8.3.3), using the estimated TTFk through our proposed reliability model.

Fig. 8.1 The proposed reliability resource-based task migration scheme [13]

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In Fig. 8.1, each tasks power, Px , Py , Pz , . . . , Pn can be assigned to each core Corei , Corej , Corek , . . . , Corem . Here, Px is the highest power task, so this task can be assigned into the highest value of Sd , which is Corej . Whereas, Pn is the lowest power task, so it is assigned to Corem , which is the lowest value of Sd , which means this core’s resource Corem has been mostly consumed before the task migration. In this way, the TTF consumption of different cores could be balanced, which means that all the cores will be targeting at the similar length of lifetime, avoiding early failure of some cores due to continued heavy load assignment.

8.3.3 EM-Reliability Resource-Based Low Performance State Mode With the proposed task migration scheme, the TTF consumption of different cores is balanced so that all the cores would have the comparable lifetime. However, task migration would not be able to compensate the excessively consumed TTF if all the cores are loaded with heavy tasks. Hence, a low performance state (p-state) mode for dynamic voltage and frequency scaling (DVFS) setting needs to be enabled to compensate the overly consumed TTF later on, so that the core could maintain its intended lifetime. With TTF consumption getting balanced across all the cores, low p-state mode (low operating voltage and frequency setting) could effectively balance the lifetime of the cores as will be discussed later in this subsection. Here, we employ different p-state settings to compensate the excessively consumed TTF of a single core as illustrated in Fig. 8.2. From this Fig. 8.2 and (8.3.4), it is clear that Sd will start negative accumulation when crk > crN , which indicates faster consumption of TTF comparing with

Fig. 8.2 Low p-state mode compensation scheme (one core) [13]

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Fig. 8.3 Low p-state mode compensation scheme for a 4-core system with (a) imbalanced TTF consumption (b) balanced TTF consumption [13]

nominal case. However, once the core switches to low p-state mode with crk < crN , the excessively consumed TTF starts to get compensated, and eventually, the consumed TTF gets compensated to the nominal consumption of TTF when Sd = 0 over time. Since the task migration scheme has succeeded to balance the TTF consumption of all the cores, low p-state mode in this case could effectively compensate the excessively consumed lifetime of all the cores. Figure 8.3 shows the examples of a 4-core system to illustrate the importance of balancing TTF consumption of all cores before low p-state mode could be used to effectively compensate the excessively consumed TTF of the multi-core systems. Figure 8.3a shows a 4-core system with imbalanced TTF consumption in which some of the cores are excessively consuming TTF while other cores are not. In this case, the low p-state mode would not be able to compensate the consumption of all the cores. But on the other hand, in Fig. 8.3b, the low p-state mode with crk < crN could effectively compensate all the excessively consumed TTF, and make the TTF resource slack to be zero (Sd = 0), which regulates the TTF of all the cores at its nominal value. Since the TTF consumption could be compensated by low p-state mode with the proposed task migration scheme, it clearly implies the following: • Excessive lifetime consumption is not necessarily causing early failure as long as it could be compensated.

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• The processor could “borrow” some lifetime from the future and use it to fulfill the completion of heavy task assignment in a certain period. Hence, in terms of TTF resource compensation, we propose the following scheme to trade-off heavy task execution and TTF requirement. • When working in high p-state mode, the multi-core processor continues to keep this mode for N cycles after over 80% of cores have Sd < 0, or the highest temperature among cores reaches to the maximum allowed temperature, max(Tk ) > Tmax , and then switch to low p-state mode starting from the N + 1 cycles. • When working under low p-state mode, the multi-core processor continues to keep this mode for M cycles after over 80% of cores have Sd > 0, and the highest temperature among cores is below the maximum allowed temperature, max(Tk ) < Tmax , and then switch to high p-state mode starting from the M + 1 cycles. In reality, the number N and M could be specified by the user based on the needs of handling heavy load and compensating lifetime. We used low p-state mode as 80% as a certain threshold, which can be changed due to the process design. In this way, the required TTF of all the cores could be maintained through low p-state mode compensation, while the processor has the flexibility to handle heavy task assignment when needed.

8.3.4 The Spatial Temperature Variation Impacts on the Proposed Method The new dynamic reliability optimization technique will be less impacted by the spatial temperature effects (than the dynamic thermal management (DTM)). The reason is as follows: unlike temperature or power, reliability or lifetime hot spots due to spatial temperature differences and power distributions do not have hard threshold lifetime or (time to failure) value, which cannot be exceeded as EM failure is a longterm accumulated effect. We can have very short lifetime for a chip under very high temperature or power for executing very heavy loads. But we can still meet the overall time to failure goal of the chip over long term as we showed in this paper. The aging effects will have average effects as long as the HotSpots will be stressed all the time, which will not be the case given different workload. Our resource-based model is exactly considering this transient and long-term effects. On the other hand, temperature (or power) HotSpot and spatial gradient are more severe and harmful as very high local temperature can lead to permanent damage of PN junctions or MOS gates and even thermal runaway in the worst case. As a result, using one or a few temperature sensor information for EM lifetime estimation will lead to less accuracy loss and less harmful effects over a long-term period.

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8.3.5 Practical Application of the Proposed Resource-Based EM Models and Reliability Management Method Currently, it is very hard to build on-chip EM sensor to directly measure time to failure of a core for its current temperature and power consumption. As a result, EM-induced time to failure (TTF) assessment technique at circuit level discussed in this paper (which was proposed in [9, 10, 24]) has to be used for each core. For practical application of proposed reliability management method for a real chip, such EM assessment technique needs to know the details of the power grid networks and power consumptions of gates or function modules for some real workloads. As a result, it can be built when the chip was designed and then look-up table or other behavior models can be constructed for time to failure as the function of temperature and power inputs, which can be measured or estimated accurately. The performance of the EM assessment to the real silicon data needs to be improved by calibrating in the accelerated aging testing with the real chip under practical workloads, which goes beyond the scope of this works and can be future research work. We further stress the on-chip temperature and the powers, which actually can be measured or accurately predicted. For instance, Intel’s multi-core CPU has one thermal sensor per core [1]. The power or functional block of the cores can be measured or estimated accurately using the performance counters [26]. Then the resource-based EM models proposed in this work can be applied to core-level reliability management.

8.4 Numerical Results and Discussions The proposed reliability model is implemented in C++, and the task migration and low performance state (p-state) mode control framework is built in Matlab environment. We applied the recently proposed physics-based EM model and analysis method for our EM analysis [9]. For the architecture model, we used SimpleScalar Alpha AXP (EV6) model with SPEC2000 benchmarks to simulate the core. HotSpot [21] is used to build the thermal model based on the configuration of a 36 core processor, and Wattch [3] is used as the architecture level power simulation tool. We measure one on-chip temperature per each core, which is based on a practical temperature sensor placement shown in [1]. In this work, we extend its functionality to calculate power under different supply voltage and working frequency. We assume that each core can have its own voltage (voltage island) and frequency settings and DVFS can be done locally for each core. We use a simple mesh-structured power grid for each core, and each core has its power island with the its power regulator. We assume that power grids for each core are same and are less coupled as far as EM effects are concerned. The dynamic workloads from SPEC2000 benchmark set are used as tasks to simulate power traces for every ECT. We select the temperature at core level not at intra-core level. For

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187

workload distribution, the dynamic 36 workloads from SPEC2000 benchmark sets are evenly distributed to run on each core within one Execution Cycle Time (ECT). Specifically, we first generate 36 tasks (2× ammp, 2× apsi, 2× bzip2, 2× equake, 2× galgel, 2× gcc, 2× lucas, 2× mesa, 2× parser, 2× twolf, 2× vpr, 2× applu, 2× art, 2× crafty, 2× fma3d, 2× gap, 1× gzip, 1× mcf, 2× mgrid) and then assign each task into each core for every ECT. Here 2× bzip2 means that task bzip2 is assigned twice to two different cores.

8.4.1 A Walk-Through Example for the Proposed Reliability Estimation In this section, we walk through an example to illustrate the proposed method. We first set the supply voltage to be 2.65 V and operation frequency to be 950 MHZ for a single core processor under test. The task “ammp” is used to generate power and thermal traces. The supply voltage of this single core processor chip, average power, and temperature of each function unit over the transient simulation period could be obtained and used as the input of the proposed reliability model. The new reliability model estimates that the nucleation time (the time when the first void is formed in power grid networks) to be 11.22 years and the TTF (the time when the chip fails) to be 19.31 years. The degradation of the IR drop is shown in Fig. 8.4. The supply voltage of the function units maintains to be 2.65 V as the value of its initial setup with the IR drop remaining to be zero before nucleation time when the first void is formed. Once it reaches the nucleation time, the formation of the void increases the resistance of the interconnect, resulting in increased IR drop in the power delivery networks. The IR drop continues to increase as the number of voids in power grids

Fig. 8.4 The increase of IR drop in power grid over years [13]

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8 Resource-Based EM Modeling DRM for Multi-Core Microprocessors

Fig. 8.5 The different TTF values under different task loads [13]

increases over years, which eventually leads to the failure of the chip. TTF is the time when the IR drop increases to 10% of the original supply voltage (0.265 V in this case). In fact, the TTF really depends on the executing tasks, that is heavier tasks lead to shorter lifetime and lighter tasks lead to longer lifetime. As an example, the estimated values of TTF under different task executions are plotted in Fig. 8.5, in which TTF shows significantly different values from one task to another.

8.4.2 Evaluation of the Proposed Methods In this part, we will be testing how the TTF of the cores gets accumulatively consumed during the task executions. In our testing environment, we keep each time-step to be 30 µ s for power simulation and thermal simulation, and specify each task execution interval to be 362 time-steps. The nominal TTF for each core is set to 15 years, and 36 task loads from benchmarks and the 36 core processors are used as our testing framework. In our framework, our processor has two different p-states for, one is high p-state mode, with 1 G of frequency and 1.4 V of supply voltage; and the other is low p-state mode, with 800 M of frequency and 1.12 V of supply voltage. First, we use the high p-state and use the proposed task migration method to balance the reliability across all the cores. The experimental results of the TTF resource slack as reflected by Sd is shown in Fig. 8.6, in which the unit of Sd is normalized to ECT (the execution cycle time as defined by pk in (8.3.4)), and the unit of time is measured by task execution cycles. We could clearly see that TTF consumption is balanced across all the cores, and thus, the TTF is consumed in the similar rate, which indicates that all the cores are regulated to have the similar lifetime. The balanced processor lifetime is about 6.66 years and unbalanced

8.4 Numerical Results and Discussions

189

Fig. 8.6 TTF resource slack (represented by Sd ) under different task migration schemes [13]

processor lifetime is 3.15 years. Our method can achieve 2.1× lifetime improvement in the proposed resource-based model. In addition, as a comparison, we also implement temperature-based task migration scheme that migrates the heaviest tasks to the cores with the lowest temperature and testify its performance in terms of TTF resource slack. As demonstrated by Fig. 8.6, the temperature oriented task migration could not balance TTF consumption, and we could clearly observe that some of the cores are consuming significantly more TTF than others, leading to imbalanced TTF consumption. Since the result in Fig. 8.6 has confirmed that the proposed task migration scheme can balance the TTF consumption across all the cores, making the cores target to similar lifetime, the low p-state mode could now effectively compensate the TTF consumption by switching the processor to low operating voltage and frequency. In this part of experiment, the low p-state mode is set up as follows: In the high p-state mode, if over 80% of the cores have Sd < 0 for over 10 task execution cycles (N = 10), the processor switches to low p-state mode. In the low p-state mode, if over 80% of cores have Sd > 0 for over 1 cycle (M = 1), the processor switches back to high p-state state. As Fig. 8.7 shows, the processor starts with high p-state mode, in which the TTF is excessively consumed for all the cores, and Sd of all the cores are decreasing simultaneously. After 10 task execution cycles and after 80% of the cores have Sd < 0, the processor switches to low p-state mode. Once the processor switches to low p-state mode, values of Sd start to accumulate in positive direction because all the cores are now consuming TTF at lower rate than the nominal rate, and we could clearly observe that Sd values calculated from different cores get effectively compensated to around 0 as the tasks run under the proposed task migration scheme, which indicates that the overall TTF consumption is close to the nominal case and the cores are targeting at achieving their required TTF (15 years lifetime). The calculated standard deviation of TTF resource slack by the end of the 40 execution cycle is 2.27 ECT, which is converged and would not keep increasing as more tasks get executed. In the low p-state mode, there is average 25% of performance loss for each task execution. In Fig. 8.7, our proposed

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8 Resource-Based EM Modeling DRM for Multi-Core Microprocessors

Fig. 8.7 TTF resource slack (represented by Sd ) compensation using low power mode under different task migration schemes [13]

algorithm with using low p-state mode can achieve 2.25× lifetime improvement with 20.3% of performance loss than the method without low p-state mode. On the other hand, if we use temperature-based migration, low power mode could not be used to compensate the TTF consumption as seen in Fig. 8.7, because the TTF consumption for different cores is completely different, and the values of Sd diverge as task runs, which indicates the lifetime of different cores diverges, and some cores would likely to have an early failure if tasks are executed under this scheme. The calculated standard deviation of the TTF resource slack by the end of the 40 execution cycle is 41.08 ECT, which is around 18 times larger than that of the standard deviation using the proposed method. Moreover, this standard deviation will increase as more tasks are executed. The result from Fig. 8.7 also suggests that, the processor could be assigned with heavy load for a certain period under the proposed migration scheme. Because, as long as the cores could be balanced to have comparable TTF, their lifetime consumption could be effectively compensated by low p-state mode. In order to show that our proposed method can be more suitable for EMinduced dynamic reliability management, we compare ours with one more different temperature-based task migration method. In addition to one simple temperaturebased method in Figs. 8.6 and 8.7, we added temperature threshold-based method, which tasks can be migrated from hot cores to cool cores only after core temperature reaches the certain temperature threshold shown in the recent publications [4, 19, 27]. Figure 8.8 summarizes the comparison results for our proposed methods with temperature-based and temperature threshold-based methods. For the temperature threshold-based method, we showed the results with two different temperature thresholds (60 and 65 ◦ C, which can be considered as the absolute maximum for long periods) and two different maximum number of task migrations at once (12 and 24) because adjustments of threshold and migration number are important in the temperature threshold-based method [19]. The temperature threshold-based method can less diverge than simple temperature-based method, but it also leads to

8.4 Numerical Results and Discussions proposed method

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high imbalanced TTF consumption across all the cores compared to our proposed method with all the different set of thresholds and migration numbers. We note that temperature-based methods cannot be a suitable solution for EM-induced reliability management as EM effect is not only function of temperature but also more function of power, power-grid geometry, and resistance change itself as shown in our EM model. Moreover, in order to see our proposed method with more heavier tasks, we injected uniformly 2× scale-up power consumption tasks with adjusted nominal TTF and lower p-state mode set (80–60%) for higher power traces. As seen in Fig. 8.9, our proposed method with heavier tasks can still well balance TTF consumption across as same as seen in normal task case in Fig. 8.7.

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8 Resource-Based EM Modeling DRM for Multi-Core Microprocessors proposed method

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8.5 Summary In this chapter, we proposed a new EM-induced reliability management method to balance and control the lifetime of multi-core processor chips due to EM process. The new approach applied a recently proposed physics-based EM model for more accurate prediction of the TTF without using empirical solutions. The proposed reliability management treated the TTF as a resource to consume during task execution, and used task migration to balance the TTF consumption across different cores, which leads to comparable lifetime among different cores to maximize the lifetime of the whole system. By using different performance states (p-states) for DVFS, we further ensured that the TTF of a whole system met the target even if some cores were executing some heavy task loads for a period of time. As a result, the reliability management method gave the processor the flexibility to handle heavy load when needed as the excessively consumed TTF could be compensated for later on. The experimental results showed that comparing with the proposed approach, the existing temperature-based task migration methods can still lead very unbalanced TTF of cores, and the low p-state mode could not effectively compensate the lifetime of all the cores, whereas our proposed reliability-based task migration approach can balance TTF consumption effectively.

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References 1. M. Berktold, T. Tian, CPU monitoring with DTS/PECI, 2010. http://www.intel.com/content/ www/us/en/embedded/testing-and-validation/cpu-monitoring-dts-peci-paper.html 2. D. Brooks, M. Martonosi, Dynamic thermal management for high-performance microprocessors, in Proceedings of International Symposium on High-Performance Computer Architecture (IEEE, Piscataway, 2001), pp. 171–182 3. D. Brooks, V. Tiwari, M. Martonosi, Wattch: a framework for architectural-level power analysis and optimizations, in Proceedings of the International Symposium on Computer Architecture (ISCA) (IEEE, Piscataway, 2000), pp. 83–94 4. A.K. Coskun, T.S. Rosing, K.C. Gross, Proactive temperature management in MPSoCs, in 2008 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) (IEEE, Piscataway, 2008), pp. 165–170 5. A. Das, A. Kumar, B. Veeravalli, Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems, in Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’13 (EDA Consortium, San Jose, 2013), pp. 689–694. http://dl.acm.org/citation.cfm?id=2485288.2485457 6. J. Donald, M. Martonosi, Techniques for multicore thermal management: classification and new exploration, in Proceedings of the 33rd Annual International Symposium on Computer Architecture, ISCA ’06 (IEEE Computer Society, Washington, 2006), pp. 78–88. http://dx.doi. org/10.1109/ISCA.2006.39 7. Y. Ge, P. Malani, Q. Qiu, Distributed task migration for thermal management in many-core systems, in Proceedings of Design Automation Conference (DAC) (IEEE, Piscataway, 2010), pp. 579–584 8. S. Gunther, F. Binns, D. Carmean, J. Hall, Managing the impact of increasing microprocessor power consumption. Intel Technol. J. 5, 37–45 (2001) 9. X. Huang, T. Yu, V. Sukharev, S.X.-D. Tan, Physics-based electromigration assessment for power grid networks, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2014) 10. X. Huang, A. Kteyan, S.X.-D. Tan, V. Sukharev, Physics-based electromigration models and full-chip assessment for power grid networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(11), 1848–1861 (2016) 11. E. Karl, D. Blaauw, D. Sylvester, T. Mudge, Reliability modeling and management in dynamic microprocessor-based systems, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2006), pp. 1057–1060 12. T. Kim, Z. Sun, H.-B. Chen, H. Wang, S.X.-D. Tan, Energy and lifetime optimizations for dark silicon manycore microprocessor considering both hard and soft errors. IEEE Trans. Very Large Scale Integr. VLSI Syst. 25(9), 2561–2574 (2017) 13. T. Kim, Z. Liu, S.X.-D. Tan, Dynamic reliability management based on resource-based em modeling for multi-core microprocessors. Microchem. J. 74, 106–115 (2018) 14. G. Liu, M. Fan, G. Quan, Neighbor-aware dynamic thermal management for multi-core platform, in Proceedings of the European Design and Test Conference (DATE) (IEEE, Piscataway, 2012), pp. 187–192 15. Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron, Interconnect lifetime prediction under dynamic stress for reliability-aware design, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2004), pp. 327–334 16. F. Mulas, D. Atienza, A. Acquaviva, S. Carta, Thermal balancing policy for multiprocessor stream computing platforms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(12), 1870–1882 (2009) 17. NIST, Assessing Product Reliability. NIST/SEMATECH e-Handbook of Statistical Methods, 2012, ch. Chapter 8. http://www.itl.nist.gov/div898/handbook/

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18. M. Powell, M. Gomaa, T.N. Vijaykumar, Heat-and-run: leveraging smt and CMP to manage power density through the operating systems, in ACM Sigplan Notices, vol. 39 (2004), pp. 260–270 19. B. Salami, M. Baharani, H. Noori, Proactive task migration with a self-adjusting migration threshold for dynamic thermal management of multi-core processors. J. Supercomput. 68(3), 1068–1087 (2014). https://doi.org/10.1007/s11227-014-1140-y 20. T. Simunic, K. Mihic, G. Micheli, Optimization of Reliability and Power Consumption in Systems on a Chip. Lecture Notes in Computer Science, vol. 3728 (Springer, Berlin, 2005) 21. K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, Temperatureaware microarchitecture, in International Symposium on Computer Architecture (IEEE, Piscataway, 2003), pp. 2–13 22. W. Song, S. Mukhopadhyay, S. Yalamanchili, Architectural reliability: lifetime reliability characterization and management of many-core processors. Comput. Archit. Lett. 14(2), 103– 106 (2014) 23. J. Srinivasan, S. Adve, P. Bose, J. Rivers, Ramp: a model for reliability aware microprocessor design. IBM Research Report, 2003 24. S.X.-D. Tan, H. Amrouch, T. Kim, Z. Sun, C. Cook, J. Henkel, Recent advances in EM and BTI induced reliability modeling, analysis and optimization. Integr. VLSI J. 60, 132–152 (2018) 25. S. Wang, J.-J. Chen, Thermal-aware lifetime reliability in multicore systems, in 2010 11th International Symposium on Quality Electronic Design (ISQED) (IEEE, Piscataway, 2010), pp. 399–405 26. W. Wu, L. Jin, J. Yang, P. Liu, S.X.-D. Tan, A systematic method for functional unit power estimation in microprocessors, in Proceedings of Design Automation Conference (DAC) (IEEE, Piscataway, 2006), pp. 554–557 27. I. Yeo, E.J. Kim, Temperature-aware scheduler based on thermal behavior grouping in multicore systems, in Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’09 (European Design and Automation Association, Leuven, 2009), pp. 946– 951. http://dl.acm.org/citation.cfm?id=1874620.1874852 28. I. Yeo, C.C. Liu, E.J. Kim, Predictive dynamic thermal management for multicore systems, in Proceedings of Design Automation Conference (DAC) (ACM, New York, 2008), pp. 734–739. http://doi.acm.org/10.1145/1391469.1391658 29. F. Zanini, D. Atienza, L. Benini, G. De Micheli, Multicore thermal management with model predictive control, in Proceedings of the 19th European Conference on Cicuit Theory and Design (IEEE Press, Piscataway, 2009), pp. 90–95 30. F. Zanini, D. Atienza, G. De Micheli, A control theory approach for thermal balancing of MPSoC, in Proceedings of the Asia South Pacific Design Automation Conference (ASPDAC) 2009), pp. 37–42

Chapter 9

DRM and Optimization for Real-Time Embedded Systems

9.1 Introduction This chapter presents a new lifetime optimization techniques for real-time embedded processors considering the electromigration-induced reliability [12]. For real-time embedded systems, many existing works focus on minimizing energy consumption while meeting all the deadlines for various real-time task models. Existing works include power management schemes, which exploits the available static and/or dynamic slack in the systems [1, 3, 4, 18, 19, 21]. For long-term reliability effects, reducing power will implicitly improve the reliability of a processor. However, the two objectives, increasing lifetime and reducing power, are still not the same. Some reliability-aware power management works have been proposed recently [16, 24] by using low power techniques such as DVFS. However, most of those existing works focus on the transient errors instead of long-term wearout failures. Recently a reliability-aware task allocation and scheduling method for multi-core embedded processors were proposed [7]. This work considers longterm failure mechanisms using general reliability models. However, such general models will not be accurate for specific failure mechanisms. Also, task allocation and scheduling are not best methods to manage the long-term wearout failures as they will not significantly change the temperatures of the chip as our study shows. Low power techniques like DVFS are more desired. This chapter aims at maximizing the EM-induced reliability of the embedded processor subject to the hard timing constraints. System-level EM reliability model will be introduced. To optimize at the system-level, dynamic voltage frequency scaling (DVFS) is applied. To solve the resulting problem, two problem formulations and the corresponding solutions will be explored. First, we formulate the optimization problem as the continuous constrained nonlinear optimization problem using task’s mean time to failure as the variables, which is solved by the simulated annealing (SA) method. In the second formulation, the linearized resulting problem is solved by the mixed-integer linear programming (MILP) method to find the © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_9

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optimal solutions with regard to the proposed EM-induced reliability model and assumptions.

9.2 System-Level EM-Induced Reliability Model At the system level, the embedded system will run on different tasks under different p-states. Let’s assume that we have a set of different time intervals pk characterized by different workloads or p-state in terms of current ndensity jk and temperature Tk for a processor or a core. It means that P = k=1 pk is the total execution time. Each kth workload, if it lasts till imaginary failure, provides time to failure TTFk . Thus the failure rate at the kth workload which last pk is λk = 1/TTFk . Then the average failure rate for the considered set of workloads is λavg =

n k=1

pk pk n λk λk = P j =1 pj n

(9.2.1)

k=1

As a result, the expected time to failure or average lifetime of the whole processor, TTF is [14] MTTF =

1 λavg

1

 1 p /P k k=1 MTTFR,k

=  n

(9.2.2)

where MTTFR,k is the actual MTTF under the kth power and temperature settings the chip works through n different power and temperature for pk period, assuming  settings and P = nk=1 pk . Each MTTFR,k will be computed based on the EM models discussed in the previous section.

9.3 Real-Time Embedded System Models In this section, we review the real-time task models considered in this work. Most of the embedded systems are real-time systems, where tasks are activated periodically, so timing and deadline should be carefully considered. We mainly consider two kinds of models for real-time systems: (1) single-rate system, where all tasks in the system have the same activation period and deadline, and (2) multirate system, where each task can have its own activation period and deadline. A task set is represented as T = {τ1 , τ2 , τ3 , . . . , τn }, where all tasks in the system are independent of each other. All tasks are scheduled on a single core processor. For single-rate system, every task has the same activation period T . For multi-rate

9.3 Real-Time Embedded System Models

197

system, every task has its period and we use Ti to denote the period of task τi . In this work, we consider the deadline of each task as its activation period, where every task must finish the execution before its next activation, or missing deadline may have detrimental impacts on the whole system. In single-rate system, every task has the same period and deadline, so the worst case for timing is that one task has to wait for all the other tasks to finish execution. As long as the sum of all task execution times is no greater than deadline T , the system is schedulable. We use ti to represent the execution time of each task, so the timing constraints for single-rate system is expressed as i ti ≤ T . In multi-rate system, the task scheduling is repeated at a hyper-period that is the LCM (least common multiple) of all periods, so we just need to consider the p-state selection for tasks within a hyper-period for multi-rate system. Thus, we assume that for every activation the task uses the same p-state in the hyper-period. We apply a fixed-priority scheduling method, in which higher priority tasks can preempt lower priority tasks, so the order of tasks is obtained from the priority. This scheduling method is widely used and is supported by standards like OSEK [2]. Task response time is an important metric to analyze timing in multi-rate system. It represents the time between the task is ready to execute and it finishes the execution. In fixed-priority scheduling, higher priority tasks can preempt lower priority tasks, so the response time of one task contains the time it is preempted by higher priority tasks besides its execution time. We use ri to represent the response time of task τi and it is expressed as (9.3.1), where hp(τi ) denotes the task set containing higher priority tasks than task τi . The first term of (9.3.1) represents the execution time of task τi and the second term denotes the preemption time of higher priority tasks. ri = ti +

τk ∈hp(τi )

/

0 ri tk Tk

(9.3.1)

The timing constraints for multi-rate system is that the response time of any task should be no greater than its period: ∀i : ri ≤ Ti . Every task must finish its execution before its next activation. In our real-time system model, we use rate monotonic scheduling, which is a common preemptive fixed-priority scheduling method. As an illustration, a real-time system model for single- and multi-rate is shown in Fig. 9.1 where task 2 has the highest priority due to its smallest period and task 3 has been preempted two times by task 2 within its response time. Further, we use core utilization to measure the percentage of total execution time in the processor, which has significant impacts on the lifetime improvement by the different slack  ti time from DVFS. The core utilization u is expressed as u = i , where ti is Ti the execution time for task i and Ti is the period of the task.

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One period Task 2 Task Execution

Task 1

Task Preempted

Task 3 (a)

Multi periods

Task 2 Task 1 Task 3 (b)

Hyper Period

Fig. 9.1 Single-rate (a) and multi-rate (b) task scheduling models [12]

9.4 Proposed New Lifetime Optimization Method In this section, we introduce the proposed lifetime optimization method for realtime embedded systems considering EM effects. The goal is to optimize the EM-based lifetime of the embedded system subject to the timing and performance constraints. To effectively manage the lifetime of the chips due to EM effect, we still apply the dynamic voltage and frequency scaling (DVFS), which is implemented by performance-state (p-state) selections for a processor [6]. We assume that a task scheduling for an embedded system has been finished already with rate monotonic as described in Sect. 9.3. First, we formulate continuous nonlinear objective function and use a heuristic optimization solution; thus, we can find a feasible solution. However, due to the limitation of heuristic global optimization solution, which can hardly find the optimal solutions, we show a linearization of the formulation to solve with linear solution easily. We build continuous nonlinear and discrete linear objective functions and use simulated annealing (SA) and mixed-integer linear programming (MILP), respectively. To solve the resulting optimization problem, we first formulate the problem as continuous constrained nonlinear programming problem and solve it by the simulated annealing method. However, due to the limitation of SA, global optimality is not guaranteed. Second, we re-formulate the same problem into a mixed-integer linear programming (MILP) problem and find the optimal solutions with regard to the same assumptions of the above nonlinear programming problem. We also compare the two solving solutions.

9.4.1 The New Lifetime Optimization Flow In this subsection, we first explain the new optimization flow and its major steps. The whole algorithm flow is shown in Algorithm 1. First, we start with a single- or multi-

9.4 Proposed New Lifetime Optimization Method

199

Algorithm 1 EM-induced lifetime optimization algorithm flow [12] Lifetime optimization for real-time embedded systems Input: A task set with execution time (ti ), power, and available p-states (pj ) Output: Optimized p-state selection for a task set (Two methods, P1 with the objective function (9.4.1) and P2 with the objective function (9.4.20)) Compute scaling voltage and frequency for each task with every p-state Compute a period Ti or hyper-period Thyper for single- or multi-rate system. Compute scaled power and measured temperature for each task with every p-state pj With given power and temperature, MTTFi = MTTF(pj ) can be calculated for each p-state pj Calculate the task execution time ti and MTTF (lifetime) for each task for every p-state if Simulated Annealing (P1) then (P1) Build continuous function of ti (MTTFi ) for each task i. (P1) Perform the MTTF optimization as shown in (9.4.1) with timing constraint to find best p-state for each task. (P1) Output each selected p-state for each task as the first solution. end else if MILP (P2) then (P2) Linearize the continuous function in (9.4.1) with timing constraint. (P2) Perform Pstate optimization as shown in (9.4.20) with linearized timing constraints to find best p-state for each task. (P2) Output each selected p-state for each task as the second solution. end

rate task set in either single-rate or multi-rate model. The tasks have non-optimized initial p-state, which has a pair of highest operating frequency and voltage. The temperature values from the profiled power and execution time can be measured by running HotSpot [22] with respect to every possible p-state selection for each task. Once we have all the power and temperature information, we compute the MTTF for each p-state for the task based on the after-mentioned EM simulator discussed in the previous section. As a result, for each p-state pj of a task i, the execution time ti is the function of its MTTFi = MTTF(pj ) under the pstate pj . We then build a continuous function of ti (MTTFi ) using the response surface methodology (RSM) [17]. We may use up to 3rd order polynomials for our RSM method to handle the nonlinearity. The function is important for the lifetime optimization as shown later. Then, we solve a constrained nonlinear optimization problem to find the best p-state for each task. To show the quality of this original solution (P1 in Algorithm 1), we use an alternative method (P2 in Algorithm 1). We linearize the objective and the constraints of the nonlinear problem as a MILP problem. We solve a discrete linear optimization problem. Then, we compare two solutions in the experiment. For a multi-rate system, one important problem is that preemption can lead to interruption of a task execution. Figure 9.2 shows an example of the mechanism of preemption in which task 1 has been preempted by task 2. Since each task has its power (thus temperature profile), does such re-ordered task execution will affect the EM-induced reliability? It turns out that such task re-ordering or task preemption has marginal impacts on the EM-induced reliability. Table 9.1 shows the results for the MTTF of two executions: one for non-preemption and one for preemption. As we can see that the MTTFs for both cases are almost the same. The reason is that the temperature of the each task execution is mainly determined by its

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9 DRM and Optimization for Real-Time Embedded Systems

Task 2

Task 2

Task 1

Task 1

(a)

Task Execution Task Preempted

(b)

Fig. 9.2 Multi-rate preemption [12]. (a) Non-preemption and (b) preemption Table 9.1 A preliminary measurement for preemptive effect on lifetime (years) [12]

Non-preemption MTTFi Preemption MTTFi

Task1 0.47 Task1 (Divided) 0.47,0.47

Task2 83 Task2 84.3

Lifetime 0.71 Lifetime 0.71

power, its transient thermal effects between task transition are not significant. Thus, the lifetime formulation in (9.2.2) remains the same for multi-rate system.

9.4.2 Formulation One: Continuous Constrained Nonlinear Optimization In this subsection, we first show the resulting problem formulation for continuous constrained nonlinear optimization. Specifically, the whole optimization can be formulated in (9.4.1). Max Lif etime(m) =  i=1 n

Subject to: ri = ti +

1 1 ti MTTF i

Thyper Ti

 /Thyper

/ ri 0 tk ≤ Ti Tk

k∈hp(i)

MTTFi,l ≤ MTTFi ≤ MTTFi,u (9.4.1) where m = [MTTF1 , MTTF2 , . . . , MTTFn ]T , which is the variable vector, i is the task id, ti is the execution time for task i, n is the total number of task, MTTFi is the segment MTTF for task i, ri is the response time of task i, hp(i) is the task set containing the higher priority tasks than the current task i. Ti is the period of task i, which is a deadline. Thyper is the hyper-period for all tasks. At the single rate Thyper is equal to Ti . Ttotal is the total execution time of all tasks. MTTFi,l is the minimum bound of MTTF for task i and MTTFi,u is the maximum bound of MTTF for task i.

9.4 Proposed New Lifetime Optimization Method

201

We note that each frequency in the DVFS settings is tighten to each p-state. For instance, we used five p-sate pj = {(1.6 GHz, 1.484 V),(1.4 GHz, 1.409 V), (1.22 GHz, 1.339 V), (1.07 GHz, 1.272 V), (930 MHz, 1.208 V)} which were chosen from ACPI standard and Enhanced Intel Speedstep Technology [6, 11]. As a result, once we know the MTTFi for a task, its p-state and the associated frequency and execution time can be determined by finding the p-state giving the closest MTTF to the MTTFi . To solve the constrained nonlinear optimization problem, the simulated annealing method (SA) is applied. We use the MATLAB’s global optimization toolbox, which provides the SA function code based on adaptive simulated annealing (ASA) [10]. The simulated annealing begins with an initial MTTFi obtained by a median of MTTFi,l and MTTFi,u for each task i. The algorithm allows a large number of moves to gradually improve MTTF. The step length equals to the current temperature, and the moving direction is uniformly random. The problem type is set as bound constrained with a set of bounds, which are MTTFi,l and MTTFi,u for each task i. The regression coefficients in our RSM model can be parameterized by the variables (MTTFi ) of our objective function and act as constants during the optimization. The temperature will be lowered by 0.95k at each iteration, where k is the annealing parameter, which is the same as the iteration number before the annealing. The stopping criterion is set to 10−6 , where the iteration stops when the average lifetime variation in the objective function is smaller than this tolerance. The maximum number of evaluation is set to 3000. Once a solution m is found, the corresponding p-state pj for each MTTFi for each task is calculated by finding the shortest-distance between MTTFi (pj ) and computed MTTFi .

9.4.3 Formulation Two: Mixed-Integer Linear Programming Since global optimality is not guaranteed in the first problem formulation, a better solution is desired. In this subsection, we try to solve the same optimization problem using an alternative method. The idea is to linearize the nonlinear objective function in (9.4.1). The resulting problem becomes a constrained linear optimization problem and can be solved by the mixed-integer linear programming (MILP) method, which can lead to the optimal solutions with regard to the proposed EM-induced reliability model and assumptions. However, MILP will be more expensive to solve for largescale problem. Nevertheless, it can be used to show the quality of the solutions obtained from the previous constrained nonlinear optimization method. Multi-rate System We first calculate the task execution time and MTTF for each task under every p-state, and store the results in the corresponding look-up table. tτi ,pk represents the execution time of task τi under p-state pk . MTTFτi ,pk represents the MTTF of task τi under p-state pk . The output p-state selection can be denoted by the Boolean variable aτi ,pk , which equals to 1 if p-state pk is selected for task τi and 0 otherwise. Since one task can only choose one p-state, τi ,

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9 DRM and Optimization for Real-Time Embedded Systems



k aτi ,pk = 1 for each task. With the Boolean variable, the execution time cτi of task τi can be formulated as (9.4.2) and the MTTF mτi of task τi can be formulated as (9.4.3).

cτi =



aτi ,pk · tτi ,pk

(9.4.2)

aτi ,pk · MTTFτi ,pk

(9.4.3)

k

mτi =

k

Then, the lifetime in (9.4.1) can be re-formulated as follows: max: lifetime(mτ ) =

Thyper 1 =  cτi 1  cτi Thyper τi ∈T mτi Tτi τi ∈T mτi Tτi

(9.4.4)

The optimal solution remains the same if we minimize the inverse of lifetime (lif etime−1 ), and we will prove lif etime−1 can be further linearized into (9.4.5). The intuition is that both cτi and mτi are decided by the same variable aτi ,pk . min: lifetime−1 (aτ,p ) =

τi ∈T

aτi ,pk

k

tτi ,pk MTTFτi ,pk · Tτi

tτi ,pk cτi = aτi ,pk mτi MTTFτi ,pk

(9.4.5) (9.4.6)

k

To show that such a linearization is valid, we need to prove that (9.4.6) is true.  Proof As we discussed, aτi ,pk is the Boolean variable and k aτi ,pk = 1, so τi has only one p-state. If pγ is the possible p-state, aτi ,pγ is 1, all other a for task τi is 0. So,  aτ ,p · tτi ,pk cτi = k i k LHS = mτi a k τi ,pk · MTTFτi ,pk = RHS =

aτi ,pγ tτi ,pγ aτi ,pγ MTTFτi ,pγ k

=

aτi ,pk

=

tτi ,pγ MTTFτi ,pγ

(9.4.7)

tτi ,pγ tτi ,pk = aτi ,pγ MTTFτi ,pk MTTFτi ,pγ

tτi ,pγ MTTFτi ,pγ

Thus, LHS equals to RHS, and we proved that (9.4.6) was true.

(9.4.8) 

9.4 Proposed New Lifetime Optimization Method

203

Therefore, if we plug Eq. (9.4.6) into Eq. (9.4.4), we can obtain lifetime−1 as follows: lifetime−1 (aτ,p ) =

cτ 1 tτi ,pk i = aτi ,pk mτi Tτi MTTFτi ,pk · Tτi

τi ∈T

τi ∈T

(9.4.9)

k

Equation (9.4.5) is proved. Therefore, the resulting optimizing problem is shown below. The constraint (9.4.11) ensures that every task chooses only one p-state. We treat the deadline of each task as its period and this leads to constraint (9.4.12). min: lifetime−1 (aτ,p ) =

τi ∈T

aτi ,pk

k

tτi ,pk MTTFτi ,pk · Tτi

(9.4.10)

subject to: ∀i:

k

∀i: rτi = cτi +

aτi ,pk = 1





τj ∈hp(τi )

rτi cτj ≤ Tτi Tτj

(9.4.11) (9.4.12)

However, the constraint (9.4.12) is still not linear. We first plug in Eq. (9.4.2), and the constraint becomes 1 2 rτ i ∀i: rτi = aτi ,pk tτi ,pk + (9.4.13) aτj ,pk tτj ,pk ≤ Tτi Tτj τj ∈hp(τi ) k

k

We can observe the nonlinearity comes from the ceiling function. Therefore, we use integer variable xτi ,τj to represent the ceiling function rτi /Tτj  with a newly added constraint ∀i, j : 0 ≤ xτi ,τj − rτi /Tτj < 1. Constraint (9.4.12) further becomes ∀i: rτi =

k

aτi ,pk tτi ,pk +





xτi ,τj aτj ,pk tτj ,pk ≤ Tτi

(9.4.14)

τj ∈hp(τi ) k

However, the nonlinearity still exists as an integer variable is multiplied by a binary variable xτi ,τj ∗ aτj ,pk . We introduce a nonnegative integer variable δτi ,τj ,pk to represent xτi ,τj ∗ aτj ,pk and use “big M method” to linearize the multiplication of an integer variable and a binary variable as follows: ∀i, j, k: xτi ,τj − M ∗ (1 − aτj ,pk ) ≤ δτi ,τj ,pk

(9.4.15)

∀i, j, k: δτi ,τj ,pk ≤ xτi ,τj

(9.4.16)

∀i, j, k: 0 ≤ δτi ,τj ,pk ≤ M ∗ aτj ,pk

(9.4.17)

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9 DRM and Optimization for Real-Time Embedded Systems

The “big M” is a large integer M in a set of linear inequalities to represent the equation δτi ,τj ,pk = xτi ,τj ∗ aτj ,pk . Simply put, we want to guarantee that if aτj ,pk = 1, δτi ,τj ,pk = xτi ,τj , and if aτj ,pk = 0, δτi ,τj ,pk = 0. In inequality (9.4.15), if aτj ,pk = 1, xτi ,τj ≤ δτi ,τj ,pk . Combined with (9.4.16) xτi ,τj ≥ δτi ,τj ,pk , we can guarantee δτi ,τj ,pk = xτi ,τj . In inequality (9.4.15), if aτj ,pk = 0, xτi ,τj − M ≤ δτi ,τj ,pk . Combined with constraints (9.4.17) 0 ≤ δτi ,τj ,pk ≤ M∗0, we can guarantee that δτi ,τj ,pk = 0. Therefore, constraints (9.4.15)–(9.4.17) are equivalent to equation δτi ,τj ,pk = xτi ,τj ∗ aτj ,pk , and thus constraint (9.4.12) can be further written as ∀i: rτi =





aτi ,pk tτi ,pk +



δτi ,τj ,pk tτj ,pk ≤ Tτi

(9.4.18)

τj ∈hp(τi ) k

k

with constraints (9.4.15)–(9.4.17) added. One last thing is to represent the set of higher priority tasks. Constant Pτi ,τj represents the priority between task τi and τj . Constant Pτi ,τj equals to 1 if τj has higher priority than τi and 0 otherwise. Finally, constraint (9.4.12) becomes a linear equation with the above constraints added. ∀i: rτi =



aτi ,pk tτi ,pk +

τj ∈T

k

δτi ,τj ,pk Pτi ,τj tτj ,pk ≤ Tτi

(9.4.19)

k

After all these linearization steps, we have the following linear objective function with linear timing constraints, which can be solved by the mixed-integer linear programming (MILP) method: minimize: lifetime−1 (aτ,p ) =

τi ∈T

aτi ,pk

k

tτi ,pk MTTFτi ,pk · Tτi

(9.4.20)

subject to: ∀i:

∀i: rτi =





k aτi ,pk

=1

(9.4.21)

∀i, j : 0 ≤ xτi ,τj − rτi /Tτj < 1

(9.4.22)

∀i, j, k: xτi ,τj − M ∗ (1 − aτj ,pk ) ≤ δτi ,τj ,pk

(9.4.23)

∀i, j, k: δτi ,τj ,pk ≤ xτi ,τj

(9.4.24)

k aτi ,pk

∀i, j, k: 0 ≤ δτi ,τj ,pk ≤ M ∗ aτj ,pk (9.4.25)   ∗ tτi ,pk + τj ∈T k δτi ,τj ,pk ∗ Pτi ,τj ∗ tτj ,pk ≤ Tτi (9.4.26)

Note that the linearization techniques in this work do not change optimality as shown above and no approximation is conducted during the derivation. Therefore, we can guarantee our solution is exactly optimal with regard to our lifetime model.

9.5 Numerical Results and Discussions

205

Single-Rate System  As discussed in Sect. 9.3, the timing constraints of single-rate system is simply i tτi < T . So, there is no ceiling function for linearization, and the optimization is much simpler. For single-rate system, we can simplify the problem as follows to make the execution much faster:

minimize: lifetime−1 (aτ,p ) =

τi ∈T

aτi ,pk

k

tτi ,pk MTTFτi ,pk · Tτi

(9.4.27)

subject to: 

τi ∈T

∀i: 



k aτi ,pk

k aτi ,pk

=1

∗ tτi ,pk ≤ T

(9.4.28) (9.4.29)

We note that in this work, we only consider the EM effects reliability. But there are many other reliability effects for back end of the lines such as TDDB (time dependent dielectric breakdown) and TC (thermal cycling). We want to stress that the proposed optimization method is orthogonal to other reliability effects as long as they can be modeled properly in terms of system-level parameters such as temperature and p-state. Our work can be viewed as a demonstration of considering long-term reliability and performance for embedded systems and it can be easily extended to deal with other reliability effects. Actually considering TDDB effect is a√trivial as TDDB induced time to failure based on TDDB models such as 1/E and E models. [15] shows similar trend with respect to the power/temperature with respect to the temperature. We should expect to see the similar trade-off between lifetime and the performance. For thermal cycling, the effects may contradict the EM effects as number of cycling and temperature ranges will make differences as shown in [5]. On the other hand, these effects are more significant for package and die interface (solder joints). Experiments show that very large thermal cycles (more than 140 ◦ C) are required to cause any damage to the silicon substrate and interconnects [23]. As a result, it seems less concern for normal chip working conditions as we assumed in this work.

9.5 Numerical Results and Discussions We first show the experimental setups for evaluating the proposed optimization algorithms. Then we show the reliability and performance results on a number of real-time embedded systems. Finally, we study the results from the two optimization methods to analyze the solution quality of the two proposed methods. We also provide some insight into the resulting trade-off between performance and lifetime.

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9.5.1 Experimental Setup The proposed new lifetime task optimization method has been implemented in MATLAB and C++. We applied the recently proposed physics-based EM model and analysis method for our EM analysis [8]. We use simple mesh-structured power grid for embedded processor. We used the interconnect material as copper and the power grid fails when the largest voltage drop exceeds 10% of Vdd . HotSpot [22] is used for the temperature modeling. We used 60 different task sets and each task set has a different number of tasks per one task set (6 tasks, 12 tasks, and 24 tasks). To generate task sets, we implement a random real-time task generator based on the core utilization factor (different ratio from 0.3 to 0.8). The core utilization is defined as the percentage of total execution time in the processor for the tasks in the real-time system for single- and multi-rate. The core utilization is not considered as a explicit constraint but treated implicitly as it is a function of the task execution times and its given deadlines which are considered as constraints. For single-rate task sets, the period is set to be 100 ms. For multi-rate task sets, we randomly choose task period among 100, 50, 20, and 10 ms. The hyper-period for both cases is 100 ms. Based on the period, we randomly generate task execution time between 0 to its period considering target core utilization. All tasks are independent with each other. All benchmarks and MATLAB environment are running on a 4core 3.0 GHz Xeon server with 16 GB RAM running Linux. Five p-states pj = {(1.6 GHz, 1.484 V),(1.4 GHz, 1.409 V), (1.22 GHz, 1.339 V), (1.07 GHz, 1.272 V), (930 MHz, 1.208 V)} are chosen from ACPI standard and Enhanced Intel Speedstep Technology [6, 11]. Lastly, IBM ILOG CPLEX optimizer [9] is used for mixedinteger linear programming.

9.5.2 Evaluation of the Proposed Lifetime Optimization First, we evaluate our lifetime optimization method (see Sect. 9.4) by comparing its lifetime and energy with non-optimized p-state tasks to the optimized p-state tasks. Here, we use 6 tasks per one task set and 36 task sets. In the evaluation of our lifetime optimization (SA method), we consider four different task sets (low and high core utilization, and single and multi-rates) for comparison. Tables 9.2 and 9.3 summarize the results for 40% and 80% core utilization of single-rate real-time tasks. As we can see, for the low core utilization tasks, the optimization method finds the lowest-energy p-state solution for each task and total energy consumption decreases about 67% as each task p-state is selected as five, which is the lowestenergy DVFS for each task execution. With SA optimization method, the lifetime is improved to 66.97 years from 1.19 years. However, for the high utilization case, lifetime improvement will be limited as shown in the 80% utilization case. In this case, the most of the p-states are moved to the middle range (3 in this case). However, there is still 85% energy saving and 3× lifetime improvement achieved by the

9.5 Numerical Results and Discussions Table 9.2 Optimization method evaluation for low core utilization single-rate task (SA and MILP)

207 6 Tasks at 40% core utilization at single rate

Non-optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTF (year) Energy (Wh) Total energy SA optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTFi (year) Energyi (Wh) Total energy MILP optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTFi (year) Energyi (Wh) Total energy

1 1 3.70 50 0.47 0.11 0.59

2 1 5.82 50 0.47 0.17

3 1 2.43 50 0.46 0.07 Lifetime

4 1 5.10 50 0.47 0.15 1.19

5 1 0.92 50 0.47 0.02

6 1 1.99 50 0.47 0.05

1 5 6.32 50 44.8 0.07 0.40

2 5 9.93 50 44.7 0.11

3 5 4.15 50 48 0.04 Lifetime

4 5 8.69 50 44.7 0.10 66.97

5 5 1.57 50 50 0.01

6 5 3.40 50 48 0.04

1 5 6.32 50 44.8 0.07 0.40

2 5 9.93 50 44.7 0.11

3 5 4.15 50 48 0.04 Lifetime

4 5 8.69 50 44.7 0.10 66.97

5 5 1.57 50 50 0.01

6 5 3.40 50 48 0.04

proposed lifetime optimization method. This indicates the significant improvement can be made for both energy and reliability from the simple task scheduling. In addition to single-rate task sets, we also show results for multi-rate task sets summarized in Tables 9.4 and 9.5. Again, depending on the core utilization, the energy and lifetime can be both improved and the improvement can be significant.

9.5.3 Core Utilization Effects and Trade-Off on Energy and Lifetime As we can see, the core utilization factor can have significant impacts on the final results. Figures 9.3 and 9.4 show the core utilization versus energy and lifetime for the SA method. The experiments are simulated with single-rate tasks at 50, 20, and 10 ms periods, and three random multi-rate tasks at 100 ms hyper-period. In the low core utilization, the system can run the task under higher p-state as the core utilization is the ratio of the task execution time and its period. In the

208

9 DRM and Optimization for Real-Time Embedded Systems

Table 9.3 Optimization method evaluation for high core utilization single-rate task (SA and MILP) 6 Tasks at 80% core utilization at single rate [12] Non-optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTFi (year) Energyi (Wh) Total energy SA optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTFi (year) Energyi (Wh) Total energy MILP optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTFi (year) Energyi (Wh) Total energy

1 1 6.81 50 0.47 0.20 1.19

2 1 5.49 50 0.47 0.16

3 1 8.37 50 0.46 0.25 Lifetime

4 1 5.25 50 0.47 0.15 0.59

5 1 7.45 50 0.47 0.22

6 1 6.51 50 0.47 0.19

1 2 7.79 50 0.95 0.18 1.027

2 3 7.18 50 3.06 0.13

3 3 10.93 50 3.06 0.20 Lifetime

4 3 6.86 50 3.06 0.13 1.78

5 2 8.52 50 0.95 0.20

6 3 8.50 50 3.06 0.16

1 2 7.79 50 0.95 0.18 1.025

2 3 7.18 50 3.06 0.13

3 3 10.93 50 3.06 0.20 Lifetime

4 3 6.86 50 3.06 0.13 1.83

5 3 9.74 50 3.06 0.18

6 2 7.44 50 0.954 0.17

higher utilization, energy saving and lifetime improvements decrease as the higher utilization leads to less number of p-state selection.

9.5.4 Solution Quality Study and Analysis In this subsection, we compare both the optimization algorithms on a number of examples. The results are shown in Figs. 9.5 and 9.6, which show lifetime improvement for both single- and multi-rate real-time embedded systems under different core utilization with different task sets solved by the MILP method and simulated annealing method, respectively. To show the scalability of our proposed algorithm, we used different task sets with 6 tasks per one task set (36 task sets), 12 tasks per one (12 task sets), and 24 tasks per one (12 task sets). MILP formulation can deliver the optimal results but at high computational costs for large-scale optimization. For the lower utilization cases, both results from both MILP and

9.5 Numerical Results and Discussions Table 9.4 Optimization method evaluation for low core utilization multi-rate task (SA and MILP)

209 6 Tasks at 40% core utilization at multi-rate

Non-optimized task id i Pk (p-state) ti (ms) P eriodi (ms) MTTFi (year) Energyi (Wh) Total energy SA optimized task id i Pk (p-state) ti (ms) MTTFi (year) Energyi (Wh) Total energy MILP optimized task id i Pk (p-state) ti (ms) MTTFi (year) Energyi (Wh) Total energy

1 1 6.93 100 0.47 0.20 1.20

2 1 4.02 100 0.47 0.12

3 1 4.19 50 0.46 0.25 Lifetime

4 1 1.91 20 0.47 0.28 1.18

5 1 1.64 20 0.47 0.24

6 1 3.03 100 0.47 0.09

1 5 11.8 44.7 0.14 0.82

2 5 6.58 44.8 0.08

3 5 7.15 44.8 0.17 Lifetime

4 5 3.27 48.2 0.19 68.02

5 5 2.79 49 0.16

6 5 5.18 48 0.06

1 5 11.8 44.7 0.14 0.82

2 5 6.58 44.8 0.08

3 5 7.15 44.8 0.17 Lifetime

4 5 3.27 48.2 0.19 68.02

5 5 2.79 49 0.16

6 5 5.18 48 0.06

continuous simulated annealing are almost same. But, for the higher utilization and higher task set cases, MILP shows better results as expected as the optimization becomes more difficult to reach optimal solutions. These results indicate that the proposed constrained optimization can lead to near-optimal results in general. We remark that it is rather difficult to fairly compare CPU times for these two optimization methods as the simulated annealing method was running on MATLAB Toolbox, whereas the MILP was running on commercial CPLEX Optimizer. For the large case, however, MILP will be very expensive as it basically uses the branchand-bound algorithm, which involves constructions of a search tree as seen in Table 9.6. It shows MILP is more expensive with larger scale tasks and its running time was 6003.98 s with 24 tasks, whereas the simulated annealing method can only take 15.19 s to solve the large scale tasks. Due to the exponential growth in the size of the search trees, MILP method would quickly become computationally expensive [13]. Moreover, due to the nature of the search tree usage, it results in excessive memory usage [13]. Thus, MILP does not scale very well for large problem sizes.

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9 DRM and Optimization for Real-Time Embedded Systems

Table 9.5 Optimization method evaluation for high core utilization multi-rate task (SA and MILP) 6 Tasks at 80% core utilization at multi-rate Non-optimized i (task id) Pk (p-state) ti (ms) P eriodi (ms) MTTF (year) Energy (Wh) Total energy SA optimized i (task id) Pk (p-state) ti (ms) MTTF (year) Energy (Wh) Total energy MILP optimized i (task id) Pk (p-state) ti (ms) MTTF (year) Energy (Wh) Total energy

1 1 9.33 100 0.47 0.27 2.42

2 1 7.25 50 0.47 0.43

3 1 16.38 100 0.46 0.49 Lifetime

4 1 13.94 100 0.47 0.41 0.58

5 1 10.05 100 0.47 0.30

6 1 3.30 20 0.47 0.49

1 3 12.18 3.06 0.23 2.10

2 4 10.82 15.2 0.16

3 3 21.39 3.06 0.40 Lifetime

4 1 13.94 0.47 0.41 1.36

5 2 11.49 0.95 0.27

6 2 3.77 0.95 0.09

1 2 10.66 0.95 0.25 2.09

2 2 8.28 0.95 0.19

3 3 21.39 3.06 0.40 Lifetime

4 3 18.21 3.06 0.34 1.65

5 2 11.49 0.95 0.27

6 3 4.31 3.06 0.08

9.5.5 Trade-Off Between Performance and Lifetime Finally, we show the Pareto-like trade-off between the performance (core utilization) and lifetime obtained from the proposed lifetime optimization as shown in Fig. 9.7. We assume that the higher utilization implies more tasks can be scheduled and executed in the given time; thus, it can be considered as higher performance in Fig. 9.7. For long-term reliability, such as electromigration effects, high performance will always lead to the shorter lifetime and vice versa. But, this is not true for soft error short term reliability, in which low performance/power leads to much worse reliability [20]. With low utilization, we can have more room for such performance/power and reliability trade-off. The proposed method can lead to the best (Pareto-like) trade-off.

9.5 Numerical Results and Discussions

211 Energy

1

0.95

Single Rate = 50ms Single Rate = 20ms Single Rate = 10ms Multi Rate = 100ms Multi Rate = 100ms Multi Rate = 100ms

Energy Saving Ratio

0.9

0.85

0.8

0.75

0.7

0.65

0.6 0.3

0.4

0.5

0.6

0.7

0.8

0.6

0.7

0.8

Core Utilization

Fig. 9.3 Core utilization effect—energy savings [12] Lifetime

70

Lifetime Improvement (Times)

60

50

40

30

20

10

0 0.3

Single Rate = 50ms Single Rate = 20ms Single Rate = 10ms Multi Rate = 100ms Multi Rate = 100ms Multi Rate = 100ms

0.4

0.5

Core Utilization

Fig. 9.4 Core utilization effect—lifetime improvement [12]

Average Lifetime Improvement (Times)

212

9 DRM and Optimization for Real-Time Embedded Systems

60

60 MILP SA

50

60 MILP SA

50

50

40

40

40

30

30

30

20

20

20

10

10

10

0 0.3

0.4

0.5

0.6

0.7

0.8

0 0.3

0.4

Tasks = 6

0.5

0.6

0.7

0.8

MILP SA

0 0.3

0.4

Tasks = 12

0.5

0.6

0.7

0.8

Tasks = 24

Average Lifetime Improvement (Times)

Fig. 9.5 The comparisons of simulated annealing and mixed-integer linear programming methods for the lifetime optimization for single rate with 6, 12, and 24 tasks per one task set under different core utilizations (0.3–0.8 in x-axis) 60

70 MILP SA

50

70 MILP SA

60

MILP SA

60

50

50

40

40

30

30

20

20

10

10

40 30 20 10 0 0.3

0.4

0.5

0.6

Tasks = 6

0.7

0.8

0 0.3

0.4

0.5

0.6

Tasks = 12

0.7

0.8

0 0.3

0.4

0.5

0.6

0.7

0.8

Tasks = 24

Fig. 9.6 The comparisons of simulated annealing and mixed-integer linear programming methods for the lifetime optimization for multi-rate with 6, 12, and 24 tasks per one task set under different core utilizations (0.3–0.8 in x-axis)

9.6 Summary In this chapter, we have developed new lifetime task optimization techniques for real-time embedded processors considering the electromigration-induced reliability. The new approach was based on a recently proposed physics-based electromigration (EM) model for more accurate EM assessment of a power grid network at the chip level. We applied the dynamic voltage and frequency scaling (DVFS) (by selecting the performance states or p-states of the tasks to manage the power) and thus the

9.6 Summary

213

Table 9.6 Elapsed CPU time to solve the proposed simulated annealing and MILP problems (second per one task set, 80% core utilization) Multi-rate task case 6 tasks per one task set 12 tasks per one task set 24 tasks per one task set

Simulated annealing (P1) 3.29 s 6.18 s 15.19 s

MILP (P2) 1.54 s 155.40 s 6003.98 s

Trade-off between Performance and Lifetime

45 40

Lifetime Improvement

35 30 25 20 15 10 5 0 0.55

0.6

0.65

0.7

0.75

0.8

0.85

Performance (Core Utilization)

Fig. 9.7 Trade-off between lifetime and performance (each triangle is different set of core utilization)

lifetime of the processor running different tasks over their periods. We considered both single-rate and multi-rate embedded systems with preemption. We explored problem formulations and found the corresponding solutions with different solution qualities and computational costs. Experimental results have shown that for low utilization systems, significant reliability improvement can be achieved with even smaller power consumption than existing reliability-ignore scheduling method. We also compared the results from the two formulations and showed that the solutions given by the constrained nonlinear optimization method was close to the ones given by the MILP-based method, which was considered to be an optimal solution with regard to the proposed EM-induced reliability model and assumptions.

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References 1. H. Aydin, R. Melhem, D. Mosse, P. Mejia-Alvarez, Power-aware scheduling for periodic realtime tasks. IEEE Trans. Comput. 53(5), 584–600 (2004) 2. G. Buttazzo, Hard Real-Time Computing Systems: Predictable Scheduling Algorithms and Applications, 2nd edn. (Springer, Berlin, 2010) 3. J.-J. Chen, T.-W. Kuo, Multiprocessor energy-efficient scheduling for real-time tasks with different power characteristics, in International Conference on Parallel Processing, 2005, ICPP 2005 (IEEE, Piscataway, 2005), pp. 13–20 4. J.-J. Chen, T.-W. Kuo, Procrastination determination for periodic real-time tasks in leakageaware dynamic voltage scaling systems, in IEEE/ACM International Conference on ComputerAided Design, 2007. ICCAD 2007 (IEEE, Piscataway, 2007), pp. 289–294 5. A.K. Coskun, R. Strong, D.M. Tullsen, T. Simunic Rosing, Evaluating the impact of job scheduling and power management on processor lifetime for chip multiprocessors, in Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems, SIGMETRICS ’09 (ACM, New York, 2009), pp. 169–180. http://doi.acm. org/10.1145/1555349.1555369 6. Hewlett-Packard, Intel, Microsoft, Phoenix, and Toshiba, Advanced configuration and power interface specification 5.0a, 2013. http://www.acpi.info 7. L. Huang, F. Yuan, Q. Xu, On task allocation and scheduling for lifetime extension of platformbased MPSoC designs. IEEE Trans. Parallel Distrib. Syst. 22(12), 2088–2099 (2011) 8. X. Huang, T. Yu, V. Sukharev, S.X.-D. Tan, Physics-based electromigration assessment for power grid networks, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2014) 9. IBM, ILOG CPLEX optimizer, 2015. http://www-01.ibm.com/software/commerce/ optimization/cplex-optimizer 10. L. Ingber, Adaptive simulated annealing (ASA): lessons learned. Control. Cybern. 25, 33–54 (1996) 11. Intel, Enhanced Intel Speedstep Technology for the Intel Pentium M Processor (Intel, Santa Clara, 2004). http://download.intel.com/design/network/papers/30117401.pdf 12. T. Kim, B. Zheng, H. Chen, Q. Zhu, V. Sukharev, S.X.-D. Tan, Lifetime optimization for real-time embedded systems considering electromigration effects, in Proceedings of the International Conference Computer Aided Design (ICCAD) (IEEE, Piscataway, 2014) 13. E. Klotz, A.M. Newman, Practical guidelines for solving difficult mixed integer linear programs. Surv. Oper. Res. Manag. Sci. 18(1), 18–32 (2013) 14. Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron, Interconnect lifetime prediction under dynamic stress for reliability-aware design, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2004), pp. 327–334 15. J.W. McPherson, Time dependent dielectric breakdown physics—models revisited. Microelectron. Reliab. 52(9), 1753–1760 (2012) 16. R. Melhem, D. Mosse, E. Elnozahy, The interplay of power management and fault recovery in real-time systems. IEEE Trans. Comput. 53(2), 217–231 (2004) 17. R.H. Myers, D.C. Montgomery, Response Surface Methodology: Process and Product Optimization Using Designed Experiments (Wiley, London 2002) 18. P. Pillai, K.G. Shin, Real-time dynamic voltage scaling for low-power embedded operating systems, in Proceedings of the Eighteenth ACM Symposium on Operating Systems Principles, SOSP ’01 (ACM, New York, 2001), pp. 89–102. http://doi.acm.org/10.1145/502034.502044 19. S. Saewong, R. Rajkumar, Practical voltage-scaling for fixed-priority RT-systems, in Proceedings of the 9th IEEE Real-Time and Embedded Technology and Applications Symposium (IEEE, Piscataway, 2003), pp. 106–114 20. M. Salehi, M.K. Tavana, S. Rehman, F. Kriebel, M. Shafique, A. Ejlali, J. Henkel, DRVS: power-efficient reliability management through dynamic redundancy and voltage scaling under variations, in Proceedings of the 2005 International Symposium on Low Power Electronics and Design (ACM, New York, 2015)

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Chapter 10

Learning-Based DRM and Energy Optimization for Manycore Dark Silicon Processors

10.1 Introduction For the last several decades, technology scaling has led to the continuous integration of devices, and microprocessors will have more cores integrated in the future. However, due to the failure of Dennard’s scaling [13], chip power density is increasing on technology nodes since transistor and voltage scaling is no longer linear. The consequence is the emergence of the so-called dark silicon manycore microprocessors, which mean only a percentage of cores can be powered on the chip due to the power and temperature limitations. Recently, architecture researchers predicted that future manycore (100–1000 cores) silicon dies can only be powered up partially (the so-called dark silicon) as power constraints will not allow all the cores to be active at the same time. Such manycore systems pose new challenges and opportunities for power/thermal and reliability management of those chips [16]. Existing works for dark silicon research mainly have been focused on the core organization, optimal number of cores, task allocation, migration, and scheduling [8, 10, 16, 23]. Moreover, those existing works focus on performance latency, bandwidth, and energy efficiency for dark silicon chips. Recently, the reliability management methods for dark silicon manycore scaling have been studied [12, 18]. However, all of these works considered general reliability models, which will not be accurate for specific failure mechanisms. Recently, a new EM model has been used for energy optimization as a DRM but it only considered the EM model [30]. For dynamic power and thermal management, learning based methods have recently become popular. Many proposed methods applied Q-learning based method, which is a reinforcement machine learning method for the adaptive control [19, 39, 44, 51]. Energy-efficient or green computing is important for sustainability and environmental responsibility. This is also true for dark silicon manycore microprocessors as they may power many IT equipment and datacenters in the near future. Power,

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_10

217

218

10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

performance, and temperature limitations are traditional dominant factors for energy-efficient high-performance and mobile computing. As technology advances, reliability starts to become another limiting factor in high-performance nanometer microprocessors due to the high failure rates in deep submicron and nanoscale devices. It is expected that future chips will show signs of reliability-induced aging much sooner than the previous generations based on the prediction of ITRS 2014 [27]. Among many reliability effects, we consider electromigration (EM) and soft error-induced reliability effects as they have become major concerns for designers due to aggressive transistor scaling and increasing power density. EM effect is the dominant interconnect failure mechanism in the 22 nm and below technology due to the shrinking wire width and thermal elevation due to FinFET devices [38], which will have immediate impacts on the metals above the FinFET devices. We want to stress that there exist many other long-term reliability effects such as NBTI (negative bias temperature instability), hot carrier injection (HCI), TDDB (time dependent dielectric breakdown) for devices and stress migration and thermal migration for interconnects. However, in this work, we only consider EM reliability for the demonstration of the proposed reliability management techniques. The proposed techniques are orthogonal to other long-term reliability managements as those longterm reliability effects generally behave similarly or in a similar trend under their stressing conditions in terms of voltage, current, and temperature [2]. On the other hand, soft error related reliability has quite different impacts on VLSI chips (from the long-term reliability). This is especially true for chips operating in the very low voltage or even near threshold voltage regions. For practical chips, we have to consider both reliability effects at the same time. Although there are many soft error mitigation techniques ranging from redundancy based design to software-based methods, it is important to study their impacts in the context of long-term reliability optimization techniques such as DVFS and on/off switching of cores from dark silicons. In this chapter, we develop a new energy and lifetime optimization techniques for emerging dark silicon manycore microprocessors considering both long-term reliability effects (hard errors) and transient single event upset errors (soft errors) [31]. We employ both dynamic voltage and frequency scaling (DVFS) and dark silicon core state using on/off switching action as two control knobs. We develop two optimization techniques for improving lifetime and reducing energy. To optimize EM-induced lifetime, we first apply the adaptive Q-learning based method, which is suitable for dynamic runtime operation as it can provide cost-effective yet good solutions. The second lifetime optimization approach is the mixed-integer linear programming method, which typically yields better solutions but at higher computational costs.

10.2 Review of System-Level EM and Soft Error Reliability Models

219

10.2 Review of System-Level EM and Soft Error Reliability Models 10.2.1 System-Level EM Reliability Model At the system-level EM reliability, the manycore system will run on different tasks under different p-states. Let’s assume that we have a set of different time intervals pk characterized by different workloads or p-state in terms of current density jk  and temperature Tk for a processor or a core. It means that P = nk=1 pk is the total execution time. Each kth workload, if it lasts till imaginary failure, provides time to failure T T Fk . Thus the failure rate at the kth workload which last pk is λk = 1/T T Fk . Then the average failure rate for the considered set of workloads is λavg =

n k=1

pk pk n λk λk = P j =1 pj n

(10.2.1)

k=1

As a result, the expected time to failure or average lifetime of the whole processor, T T F is [35] MTTF =

1 =  n λavg

k=1

1 1 pk MTTF R,k



(10.2.2) /P

where MTTFR,k is the actual MTTF under the kth power and temperature settings for pk period, assuming the chip works through n different power and temperature  settings and P = nk=1 pk . Each MTTFR,k will be computed based on the EM models in Chap. 7. To consider a system-level EM reliability on a manycore dark silicon processor, we use the shortest lifetime among all the cores as the lifetime for all manycore processors [11]. We want to stress that the proposed techniques are orthogonal to other long-term reliability effects (such as NBTI, HCI, TDDB for devices and stress and thermal migration for interconnects). The proposed techniques are orthogonal to other long-term reliability managements as those long-term reliability effects generally behave similarly or in a similar trend under their stressing conditions in terms of voltage, current and temperature [2]. Specifically, the power and temperature typically have the same impacts on the NBTI, HCI, and TDDB as those failure effects follow the Arrhenius equation for the relationship between the failure rate and temperature (which is a function of powers or energy) [17], as a result, those long-term reliability effects will become worse when temperature increases. As a result, DVFS based optimization will lead to similar trade-off between longterm reliability and soft errors.

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

10.2.2 Soft Error Reliability Model Considering DVFS Impacts Soft errors, or single event upset, are defined as the transient faults inside the logic or memory on a chip, and result in an incorrect system output. The soft errors can be caused by cosmic radiation, alpha particle decay, and thermal neutrons. Soft error rate (SER) is the rate in which a chip or system encounters soft errors and typically can be expressed as the number of failures in the given time. Although there is still a lack of consensus on the exact soft error rate (SER) of specific chips and systems, it is obvious that the SER per chip is practically increasing due to the increasing number of components or cores on a chip. Recently it has been reported that the dynamic voltage frequency scaling (DVFS) method, used for energy saving, negatively affects the system reliability because the transient fault rate increases and the critical charge decreases by lowering the voltage and frequency. As a result, new exponential soft error models have been introduced to account for those effects [45, 53]. For our problem, we employ an existing exponential model considering DVFS effects on soft error rate, which assumes that the radiation-induced failure follows a Poisson distribution, so the average soft error rate can be expressed as terms of operating frequency f , supply voltage Vdd , where SER0 is the average failure rate at the maximum frequency fmax and voltage Vmax (so, fmin < f < fmax , Vmin < V < Vmax ) in (10.2.3) [53]. d(fmax −f )

SER(f, Vdd ) = SER0 e (fmax −fmin )

(10.2.3)

where d is an architecture dependent constant, which is the sensitivity of failure rate with DVFS. We also employ the previous work to model the relationship between operating frequency and supply voltage to further simplify (10.2.3) from [52]. f =β

(Vdd − Vth )2 Vdd

(10.2.4)

where β is a technology-related constant, and Vth is the threshold voltage. By substituting (10.2.4) into (10.2.3), DVFS-aware SER equation can be derived as the function of supply voltage Vdd [45]:

SER(Vdd ) = SER0 e

10.2.2.1

% & V2 d fmax −βVdd −2Vth + V th dd fmax −fmin

(10.2.5)

System-Level Soft Error Model for Dark Silicon Manycore Processor

To estimate system-level soft error reliability, the sum of failure rate (SOFT) with architecture vulnerability factor (AVF) method has been widely accepted in the

10.2 Review of System-Level EM and Soft Error Reliability Models

221

semiconductor industry [33, 42] for combining soft error rates from each core to estimate whole system-level soft error. The AVF is used to express the probability that a visible soft error will occur with a given raw error event in a core [37]. The previous study shows the SOFR model can be used to show the whole system soft error rate (SERSY S ) [33]: SERsys = SOFR =

m

AVFi × SERi (Vdd )

(10.2.6)

i=0

where m is the total number of cores in a processor and SERi (Vdd ) is the soft error rate for given voltage setting (Vdd ) and AVFi is architecture vulnerability factor for ith core.

10.2.3 Impact of Process Technology on Soft Error Reliability Model In the past, soft errors in microprocessor logic have not been greatly concerned as the number of flops/latches in a microprocessor is much fewer than the number of SRAM cells and microprocessor single event upset (SEU) rates were lower than SRAM SEU rates. After 90 nm technology, however, microprocessor SEU rates are larger than SRAM SEU rates because flop protection mechanisms (machine encoding and invariant checking) are more difficult to implement than simple memory protection mechanisms (parity, error correction code) [15]. Thus, the SEU in microprocessor will be the dominant factor to system soft error rate as technology scales to smaller feature size. Table 10.1 shows the normalized SEU rate in microprocessor reported from the real silicon data [26]. As technology scales to smaller feature size, SEU rates keep increasing for different technologies. To assess technology scaling impacts, we used different raw SER values and other parameters (different threshold voltage (Vth ) and supply voltage (Vdd )) in (10.2.5) based on the experimental data from [6, 26]. The technology scaling impact on our proposed dynamic reliability management method will be discussed in Sect. 10.4.4. Table 10.1 Raw SEU rate per microprocessor on different technologies [31]

Technology 45 nm 32 nm 22 nm

Normalized SEU rate 1× 1.38× 1.59×

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

10.3 New Dynamic Lifetime and Energy Optimization Methods for Dark Silicon In this section, we formulate our dynamic reliability management (DRM) problem as maximizing the (EM-induced) lifetime of dark silicon manycore processors by controlling the number of active cores and the suitable performance state (p-state) subject to the performance and temperature constraints. To improve EM-induced lifetime, we first present the Q-learning based solution to this problem. Then we re-formulate the same problem as mixed-integer linear programming (MILP) problem. Moreover, for energy saving, we re-formulate our dynamic reliability management (DRM) problem with a Q-learning method as the minimizing energy consumption considering EM-induced lifetime and soft errorinduced lifetime of dark silicon manycore processors by controlling number of active cores and the suitable performance state (p-state) subject to the performance and temperature constraints.

10.3.1 Q-Learning Based Formulation and Solution for Lifetime and Energy Optimizations 10.3.1.1

State and Action Determination

Q-learning [47], a reinforcement learning method, performs the control by maximizing expected long-term rewards [43]. Q-learning can handle problems with stochastic transition without any adaptation and is a method to be able to converge close to the optimal solution of a state–action function for an arbitrary policy [28]. In our problem, the state (s) consists of the configurations of DVFS and active status (power on/off) for each core. DVFS uses performance state (p-state) which can represent operating voltage and frequency. Action (a) is defined as a state transition from one state to the another state. An action updates the learning agent’s Q-value with the reward/penalty calculation in the Q-table, also known as the state–action table. Transiting an action in a state makes the agent with a reward (negative penalty) scoring that is calculated with the quantity of state–action combination (Q). Q can be defined as a set of states (S) and a set of action (A) table, S × A, which is Q-table. Q-table can be updated by a Q-value function which is a long-term penalty function with state and action. Figure 10.1 shows the proposed learning-based (Q-learning) reliability-aware lifetime/energy optimization framework (both lifetime and energy optimizations use Q-learning method). The framework consists of an environment containing the dark silicon manycore microprocessor, and the learning agent which is the Q-learning algorithm. The learning agent obtains the environment state, calculates the penalty function, and finally decides the next action.

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Fig. 10.1 Q-Learning model with reliability-aware dark silicon framework [31] Table 10.2 An example of control states for a 3-core processor [31]

State 0 2 4 6 8

p-state 0, 0, 1 0, 1, 1 0, 2, 2 1, 1, 2 2, 2, 2

Active core off, off, on off, on, on off, on, on on, on, on on, on, on

State 1 3 5 7

p-state 0, 0, 2 0, 1, 2 1, 1, 1 1, 2, 2

Active core off, off, on off, on, on on, on, on on, on, on

Table 10.2 illustrates an example of state, p-state, and active core for small 3core dark silicon chip. In p-state, 1 is low power mode, 2 is full power mode, and 0 means the core is turned off. Clearly, state 0 is the state with a minimum number of active cores, which are in the lowest power modes and state 8 is the state with a maximum number of active core, which are in the highest power modes.

10.3.1.2

Q-Value Function and Q-Learning Process

In the Q-learning process, one critical issue is to define the Q-value function with penalty term. Specifically, let’s formally define State i: si = {P Si , CSi ). P Si is the set of p-state (DVFS) statuses for all the cores. CSi is the set of core

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

status for all cores. Each state si will determine the total power of the whole chip P ower(si ), worse case performances of all cores P erfmax (si ), the maximum temperature incurred T empmax (si ), total core energy consumption in the whole chip E( si ), and the minimum lifetime among cores EMmin (si ), which is defined as the EM-induced lifetime of the chip. SERmin (Si ) is defined as system-level soft error rate (SERsys ) of the chip. The total core energy consumption can be obtained from  k Ek (si ) which is kth core’s core energy, each core’s energy can be calculated by P owerk (si ) × P erfk (si ), where P owerk (si ) is average kth core’s power and P erfk (si ) is each kth core’s performance. An action ai,j can be viewed as the transition from state i to state j . Then the penalty function Q determines a penalty and a new state which is related to the previous state and selected action. Q-value is updated at every step t. Qt+1 (s(t), a(t)) = Qt (s(t), a(t)) 

+ α(t) × P T (t + 1) + γ min(∀Qt (s(t + 1), a)) a

(10.3.1)

− α(t) × Qt (s(t), a(t)) where α(t) is the learning rate between 0 and 1 which determines how much newly calculated Q-value will be applied. For instance, setting α to 0, then Qvalues are not updated, so nothing is learned. Setting it to 1 means that Q-values are considering the most recent state-action. In practice, the constant learning rate is used (α(t) = 0.1, ∀t) as the algorithm needs to converge, so it requires a learning rate close to zero [43]. s(t + 1) is determined by action a(t), so Qt (s(t + 1), a) are all possible actions’ Q-values from future state. So the discount factor γ (between 0 and 1) affects the importance of future penalty. A small discount factor gives more penalties in the near future penalty, and high discount factor accounts more for the far future penalty. This parameter needs to be tuned experimentally. min(∀Qt s(t + 1), a) can be viewed as the estimate of the optimal future value. The difference between old Q-value (Qt ) and learned value (P T (t + 1) + γ min(∀Qt (s(t + 1), a))) updates the new Q-value (Qt+1 ) with the learning a rate. The penalty term, (P T (t + 1)) in (10.3.1) at t + 1 time, is the penalty obtained after performing action a(t) in state s(t) on the dark silicon manycore processor. In our problem, we have three main constraints: total core power, performance deadline of all the tasks, and temperature upper limit. EM-induced lifetime is what we want to maximize. As a result, we define the penalty function P T in [30, 39] to consider multiple constraints. We can build a penalty term (P T ) as shown in (10.3.2) for each EM-induced and energy optimization. P TE is a penalty term for total core energy, P TEM is a penalty term for EM-induced lifetime, P TSER is a penalty term for systemlevel soft error rate, P Tpower for power, P Ttemp for temperature, and P Tperf for performance deadline of all tasks. Each penalty term (P Tx ) is normalized in (10.3.2). We use the feature scaling method to bring all values between 0 and 1.

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225

For instance, P TE = E(t+1)−E(t) EMax −EMin for energy related penalty, where E(t) is the total energy consumption in the previous time t and E(t + 1) is the energy of the system at current t + 1. For the EM lifetime, P TEM = MTTF(t)−MTTF(t+1) MTTFMax −MTTFMin for EM related penalty, where MTTF(t) is the MTTF of the system for EM-induced in the previous time t and MTTF(t + 1) is the MTTF of system at current t + 1. Similarly, for the soft errors, P TSER = SER(t+1)−SER(t) SERMax −SERMin for soft error related penalty, where SER(t) is the soft error rate of the system in the previous time t and SER(t + 1) is the soft error rate of system at current t + 1. Energy and EM terms can be interchangeable, so both energy and life optimizations can be achieved with similar penalty term as seen in (10.3.2). P T =P TE + C



δx P T x

x={EM,SER,power,temp,perf }

for energy optimization P T =P TEM + C

δx P T x

x={E,power,temp,perf }

(10.3.2)

for EM-induced lifetime optimization  0 if P Tx ≤ Bx + x δx = 1 if P Tx > Bx + x where δx is a binary function to active (δx = 1) or inactive (δx = 0) of user defined or given constraint bounds, Bpower , Bperf , and Btemp in the penalty term. They are also normalized power, performance, temperature bounds, respectively. Each x is the difference between each bound and average penalty (P T ) for power, performance, and temperature. x is negative if the system violates the given constraint; otherwise, it is positive and the system is bounded and performs well. Therefore, if the system violated the user constraints in the past, then the penalty can be quite significant (due to large value for constant C in (10.3.2)). Our learning-based lifetime/energy optimization algorithm steps can be explained as follows: the input is an initial state set for each core with p-state and core status and output is the selected p-state and core states. First, all the Q-values in the Q-table are initialized to zero. The current state, denoted as s(t), finds an action a(t) with the lowest Qt in (10.3.1) and switches to next state with corresponding p-states and active cores. For every step, EM lifetime, soft error rate, performance, temperature, and power are evaluated, and thus, the whole environment can be updated. Then, it calculates the new corresponding penalty P T (t + 1) in (10.3.2) and Qt+1 can be updated (learning process). After the update, the current state is discarded in exchange for a new action and subsequent iterations yield more updates with new states. Finally, when all the Q-values changes are less than a certain threshold, the best policy will be chosen.

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

10.3.2 MILP Based Formulation and Solution for Lifetime Optimization The second approach for lifetime optimization that we apply is the mixed-integer linear programming (MILP) method. MILP formulation of the performed constrained lifetime optimization method is more straightforward than the Q-learning based method. MILP also delivers better results than Q-learning based method as shown in this work. However, in general, MILP has higher computation costs than the Q-learning method. Also, MILP solver is very heavier, so it is not suitable for online management method. Hence we can use MILP solution to measure the solution quality of the Q-learning based method. We know that the MTTF of a core (or lifetime) stressed by different periods with different temperature can be approximated by formula (10.2.2). For the manycore processor, we assume that the MTTF of the overall chip is determined by the minimum MTTF of all cores [11]. Let’s define the lifetime of a core k for a given state si as L(k, si ), which will be built as a look-up first. Then the lifetime optimization problem for dark silicon manycore processor can be formulated as the following MILP problem: max i

min k

subject to

i

∀i:





bi ck L(k, si )

k

bi = 1,

∀k:

i

P owerk ≤ Bpower



ck = 1,

k

(10.3.3)

k

T empmax ≤ Btemp P erfmax ≤ Bperf where P owerk is the kth normalized core power, T empmax is the maximum normalized temperature among cores, and P erfmax is the maximum normalized performance deadlines among cores (or all the tasks). Bconst , Bconst , and Bconst are normalized performance, temperature, and power bounds allowed. Note that a selection for a chip lifetime can be denoted by a Boolean variable bk , which equals to 1 if the kth core’s lifetime is selected and 0 otherwise. Similarly, a state selection for a core is also denoted by a Boolean variable ci , which equals to 1 if state si is selected for the chip and 0 otherwise.

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227

10.3.3 Implementation of the Dark Silicon Evaluation Platform To evaluate the proposed DRM algorithms, we implement a simulation-based platform for dark silicon processor. The platform is shown in Fig. 10.1. We first describe the major component models of the framework such as microarchitecture, power estimation, thermal and reliability models. Our proposed framework uses Sniper as a microarchitecture model, which is an accurate and fast application-level interval-based microarchitecture simulation [7]. The interval simulation is a recently proposed multi/manycore simulation framework at a higher level of abstraction which is faster than cycle-accurate full-system simulation. The interval simulation uses mechanistic analytical model, which is constructed from the mechanism of a superscalar processor core. The cycle-accurate full-system simulator, such as gem5 (full-system mode) [5], GEMS [36], MARSSx86 [20], and SimFlex [48], can run both application and operating system (OS). These frameworks have the merit of having an accurate evaluation of I/O activities and OS extensive kernel function. However, these full-time simulations are extremely slow and not very suitable for our framework because they rely on the existing OS systems, which currently do not support manycore and dark silicon architectures in their simulators [1]. Thus, to support dark silicon and manycore processor, we choose applicationlevel Sniper simulator. This Sniper interval-based model is accurately matching well with the Intel x86 multi-core architecture [7]. PARSEC [4] and SPLASH2 [49] benchmarks are used for our platform workloads. PARSEC benchmark, recently released multithreaded benchmarks, provides an up-to-date collection of modern workloads for multi/manycore systems, and SPLASH-2 has been used many multi/manycore research for a long time. We use both workloads to evaluate our proposed framework and algorithm in Sect. 10.4. For the power estimation, we use McPAT (multi-core power, area, and timing), which is a recently proposed full integration modeling framework. McPAT can provide dynamic and static, even short-circuit power dissipation and provides multithreaded and multi-core processor models. For the thermal model, we use HotSpot to accurately characterize the thermal traces from the given multi-threaded task run in each core [40]. To enable the dark silicon feature, the floor plan and power trace are dynamically controlled by the dark silicon DRM module in Fig. 10.1. As shown in Fig. 10.1, once the cycle per instruction (CPI) stacks and power/energy traces are achieved in the microarchitecture model with the power model, the thermal model can generate thermal traces for given task run. With each core’s power trace, thermal trace, core voltage, core frequency, and active cores, we can perform EM and soft error reliability effects analysis and the system-level assessment for microprocessor lifetime based on the reliability models. Figure 10.2a and b show the results from the proposed framework, which are the power traces, thermal measurement, and EM lifetime on a 64-core dark silicon chip. Figure 10.2 shows the example thermal and EM analysis under 64-cores dark silicon chip (20 cores on and 44 cores off). 64 multi-threaded tasks (16× CHOLESKYs, 16×

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

Fig. 10.2 (a) SPLASH2 benchmark 64 multi-threaded tasks power traces with 44 cores off. (b) Thermal (color:degree) and EM lifetime (number:years) analysis on 64 cores [31]

10.3 New Dynamic Lifetime and Energy Optimization Methods for Dark Silicon

229

RADIXs, 16× RAYTRACEs, 16× VOLRENDs) are running under normal DVFS settings (2.0 GHz, 1.2 V). Power budgeting is not applied here. We remark that the soft error affects the short term hardware functionality and it has a different way to impact the reliability of the circuits than the long-term reliability. However, both effects hurt the reliability of a chip and we think it is necessary to consider both as the power/energy and performance have contradicting impacts on them. The trade-off has to be found among the robustness, costs, and performance of the manycore processor systems to mitigate both the soft and hard reliability effects. In our formulation, both soft errors and EM-induced reliability are modeled in terms of system soft error rates (SER) and mean time to failure (MTTF), respectively, and parameterized by the chip and system parameters such as Vdd /frequency, temperature, p-state, etc. As shown in (10.3.1) and (10.3.2), the SER and MTTF will contribute to the constraints of the optimization in terms of penalty terms. As seen in Fig. 10.1, our framework implemented two reliability models, such as EM [24] for long-term reliability and DVFS-aware soft error effects [33, 45, 53] for short-term reliability. Each reliability has been assessed for DRM module to provide constraints in our Q-learning. We also stress that DVFS and task scheduling may not be the most effective way to mitigate the soft errors and other techniques are required when the soft errors are high due to the conflicting requirement from hard reliability.

10.3.4 Time Complexity Analysis It has been proved that MILP problems are NP hard. Though branch and bound techniques can be used to solve the problem, the time complexity is not easy to analyze as we use commercial CPLEX as the solver. For the Q-learning, each value iteration can be performed in O(|A||S|2 ) steps, or faster if there is sparsity in the transition function (where A is a number of actions and S is a number of states). In practice, policy iteration converges in fewer iterations than value iteration, and there is no known tight worst-case bound available [34]. As a result, we report the running CPU times of Q-learning and MILP in our experiments with more p-states in Table 10.3 in Sect. 10.4 to compare the time complexities of the two methods. We further remark that it is rather difficult to fairly compare CPU times for these two optimization methods as the Q-learning was running on Python, whereas the MILP was running on commercial CPLEX Optimizer. Nevertheless, the numerical results still show that MILP has much higher computation cost than the Q-learning method. Table 10.3 Elapsed CPU time to solve the proposed Q-learning and MILP problems [31]

64 tasks in 64-core dark silicon (total states) Case 1—2 p-states (150 states) Case 2—3 p-states (192 states)

Q-learning time (s) 0.172 0.183

MILP time (s) 9.1 88.08

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

10.3.5 Practical Application of the Proposed DRM with Reliability Models Currently, it is very hard to build on-chip EM sensor to directly measure time to EM failure of a core for its current temperature and power consumption (although we have made some early efforts on on-chip EM sensors recently [21]). But at the fullchip level, as far as power grid is concerned, EM can be measured by the voltage drops in power grids as we discussed in Chap. 7. In our manycore dark silicon simulation framework, the EM-induced time to failure (TTF) assessment technique at circuit level discussed in this chapter (which was proposed in [24, 25]) was used for each core. For practical application of the proposed reliability management method for a real chip, such EM and SER assessment techniques need to know the details of the power grid networks and power consumptions of gates or function modules for some real workloads. As a result, it can be built when the chip was designed and then power grid voltage drop sensors (for EM measurement) or look-up table/other behavior models can be constructed for time to failure as the function of temperature and power inputs, which can be measured or estimated accurately. The accuracy of the reliability assessments with respect to the real silicon data needs to be calibrated in the accelerated testing conditions for real chip under practical workloads, which will go beyond the scope of this work and can be future research. We further stress that the on-chip temperature and the powers are practically measured or estimated. For instance, Intel’s multi-core CPU has one thermal sensor per core [3]. The power or functional block of the cores can be measured or estimated accurately using the performance counters [50]. Then our models proposed in this work can be applied to core-level reliability management. We notice that the learning-based DVFS managements have been used before to deal with difficulty of controlling the dynamics of the multi/manycore processors [14, 29]. Recently, reinforcement learning has been successfully applied for DVFS management of multi/manycore systems [9, 12, 44]. These approaches employ a simple type of reinforcement learning (Q-learning) because this method has a relatively low overhead in terms of execution time and memory foot print. In this work, we assume the similar light scheduling overheads or time costs by the Q-learning methods. We have added the execution time for the proposed Q-learning method in Sect. 10.4.5. Furthermore, as the state space of manycore systems becomes large, we can explore overhead-aware scheduling method [9], the discrete look-up table method [41, 46], or pre-training based method [12] during the Q-learning to avoid expensive Q-value updating operations. In our work, we use look-up table based method.

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231

10.4 Numerical Results and Discussions 10.4.1 Experimental Setup The proposed new energy optimization algorithm in the dark silicon framework has been implemented in Python 2.7.9 with the numerical libraries (NumPy 1.9.2 and SciPy 0.15.1). For dark silicon framework, we modified the architectural simulator (Sniper 6.1), power estimator (McPAT 1.0.32), and thermal simulator (HotSpot 5.02 [40]) to estimate EM-induced lifetime and system-level soft error rate on top of the new physics-based EM model [24] and DVFS-aware soft error model [33, 45, 53]. In the proposed framework as shown in Fig 10.1, each simulator module is connected with a plug-in connector, so that one simulator’s result can dynamically feed the other’s inputs. The learning agent and Q-learning method have been implemented in Python 2.7.9 with extensive solutions from Python NumPy Extension. Our energy optimization method is validated with a 64-core processor on the PARSEC and SPLASH-2 multi-threaded benchmarks. A small number of tasks with PARSEC (1 BLACKSCHOLES, 1 CANNEAL, 1 FREQMINE, and 1 VIPS) and for a large number of tasks with SPLASH-2 (16 CHOLESKYs, 16 RADIXs, 16 RAYTRACEs, 16 VOLRENDs) are used with the same 64 threads. We chose two performance states (p-state) with the clustered DVFS [32], which have been employed to reduce the simulation time with small solution quality degradation due to the large number of cores in our experiment. To show that our method can find the lowest possible energy optimization, we compare our results with the global DVFS method, in which all active cores have the same p-state. The full power mode (2.0 GHz, 1.2 V) and the low power mode (1.0 GHz, 0.9 V) have been set for our framework. For the soft error model, we use system-level soft error rates, the architecture constant (β = 1.5 × 1010 and d = 2), AVF ( a constant = 0.5) for each core, and the threshold voltage (Vth = 0.9) have been obtained from [33] and Enhanced Intel Speedstep Technology [22] with 45 nm technology.

10.4.2 Evaluation of the Proposed Q-Learning Lifetime Optimization Method First, we evaluate our learning-based DRM method (see Sect. 10.3) by showing lifetime improvements with different sets of power budgets and performance deadline. Figure 10.3 shows the lifetime improvements given power budget and performance deadline for a small and large task set on 64-core dark silicon chip. As we can see in Fig. 10.3a, for the small task set case our method finds relatively high lifetime improvement (87.9 years) as the task loads are small and more cores can be in low power mode or turned off (dark silicon) with the given power budget and performance deadline. In small performance deadline (42 ms), there is still chance to

10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

Fig. 10.3 Lifetime improvements given power budget and performance deadline on 64-core dark silicon chip: (a) PARSEC small task set. (b) SPLASH-2 large task set [31]

Lifetime Improvement

232

150

100

Performance Performance Performance Performance

deadline deadline deadline deadline

= = = =

32ms 42ms 53ms 107ms

50

0 100

150

200

250

300

350

Total Core Power Budget (W) (a)

Lifetime Improvement

15

10

Performance Performance Performance Perofrmance

deadline deadline deadline deadline

= = = =

16ms 40ms 80ms 160ms

5

0 100

150

200

250

300

350

Total Core Power Budget (W) (b)

improve lifetime (11.2 years) in the high power budgets (200–350 W). However, for the large task set case, lifetime improvement will be limited as shown in Fig. 10.3b. The highest lifetime improvement is 28 years with highest power budget, and there are still 10.5 years lifetime improvement in the middle range of power budget and performance deadline (40–80 ms). This indicates significant improvement can be made for both small and large tasks with given power budget and performance deadline. Figures 10.4 and 10.5 show the power consumptions and performances from our proposed DRM method and it indicates all the results can meet the given power budgets and performance deadline. Furthermore, no violations were found in either small or large task set results.

10.4 Numerical Results and Discussions

Performance (ms)

(a) 36 34 32 29 27 25 23 21

Deadline = 32.0ms (4 heavy tasks)

Deadline = 42.7ms (4 heavy tasks)

(b)

43.2

Performance Constraint

Performance Constraint

42.7 42.3 41.9

200

(c)

233

250

300

350

Deadline = 40.2ms (64 light tasks)

48.2

200

250

300

350

Deadline = 80.4ms (64 light tasks)

(d) 96.5

Performance Constraint

40.2

80.4

32.1

64.3

24.1

48.2

16.0

32.1

8.0

16

0

Performance Constraint

0 250

300

350

200

250

300

350

Power Budget (W) Fig. 10.4 Q-learning result for performance deadline from (a, b) PARSEC tasks and light (c, d) SPLASH-2 tasks in 64-core dark silicon chip [31]

10.4.3 Accuracy and Convergence Rate of the Proposed Q-Learning DRM Method Now we show some results from our second method for lifetime optimization method, MILP solver. To see the accuracy, we use MILP formulation (10.3.3) with the given solver, which is limited to post-validation as MILP method is very expensive to solve for large-scale problem. Nevertheless, it can be used to show the quality of the solution obtained from the learning-based DRM method. A comparison of the Q-learning DRM method and the MILP method shows lifetime improvement for both small and large cases with results shown in Fig. 10.6. MILP method can deliver better results but with higher computational costs for large-scale optimization. To see the accuracy comparison, 100 iterative tests are carried out for each case. For small and large cases in Fig. 10.6, our proposed Q-learning DRM method can achieve relatively high accuracy, 95% and 94%, respectively. It also shows that system violation can be effectively prevented by our proposed penalty function (10.3.2).

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10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

Power Budget = 150W 4 heavy tasks

Total Core Power Conosumption

150

Power Budget = 200W 4 heavy tasks

Power Constraint

Power Constraint

200 150

100

100 50

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10.4.4 Hard and Soft Errors in Dark Silicon Manycore Processor For both the reliability effects, we show the different impacts that power consumption has on both EM and soft error related reliability effects. We try to observe two reliability effects (EM-induced lifetime and system-level soft error rate) on the 64core dark silicon manycore processor with the different task sets. Figure 10.7 shows how two failure rates (1/MTTFEM and SERsys ) change over power determined by different DVFS settings when 12 cores are turned on with a 64 thread multi-threaded benchmarks. As we can see, for long-term hard reliability (electromigration effect), high power leads to short lifetime. However, for short-term/transient soft errors, low power will lead to much worse reliability issues. As a result, the system level optimization subject to both reliability constraints is no longer a simple trade-off between performance/power versus reliability effects. Figure 10.8 shows that our DRM method in the different process technologies can affect our soft error reliability model. Also, as we discussed in Sect. 10.2.3, technology scaling can be impacted on soft error rate and its constraint. Smaller technology has higher soft error rate. As we seen in Fig. 10.8, with smaller

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technology nodes, our DRM method under loose EM (5 years) and loose SER (0.6) constraints finds less energy saving as smaller technology can affect higher soft error rate for 32 nm and 22 nm cases (cases D and E) than 45 nm cases (case C). However, our method still can find better energy saving point.

10.4.5 Evaluation of the Proposed Q-Learning Based Energy Optimization Method To evaluate the proposed Q-learning based energy optimization method in Sect. 10.3, we show the total energy consumption with the different sets of EMinduced lifetime constraint, system-level soft error rate constraint, power budgets, and performance deadlines. Energy optimization results for a small task set and a large task set cases are shown in Figs. 10.9 and 10.10, respectively. Each figure

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Fig. 10.8 Impact of different process technologies on system-level soft error rate, from left bar, case (A) global DVFS, case (B) our proposed DRM with only EM constraint, our proposed DRMs with both EM and SER constraints of case (C) 45 nm, case (D) 32 nm, and case (E) 22 nm [31]

includes two groups with loose and tight EM, where the left 4 bars are loose EM constraints and the right 4 bars are tight EM constraints. In each group, the third bar is tight soft error constraints and the fourth bar is loose soft error constraints. As we can see, if we consider only EM constraints for the different EM lifetimes, power budgets, and performance deadlines for small task set case, the proposed method finds relatively high energy saving with both large and small performance deadlines (see Fig. 10.9a and b) than the global DVFS method because more cores can be in low power mode or turned off (dark silicon constraint) with the given power budgets and performance deadlines. When the loose soft error constraint is further considered (SERsys = 0.6), our proposed method can still find good energy

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savings (similar or slightly higher than the method considering only EM constraint as shown in Figs. 10.9 and 10.10). However, for the tight soft error constraint (SERsys = 0.15) with tight EM constraint cases, our method violates the given EM constraints because soft errors and EM constraints have a contradictory relationship as seen in Fig. 10.7. For the large task set case in Fig. 10.10, more violations and less energy savings are observed. Those violations are caused by the higher task utilization of active cores, tight EM lifetime constraints, and power budget. However, our method can still find relatively good energy savings with the loose soft error constraints and tight EM constraints even at the large task sets. Thus, with exception to the violation cases

10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

Fig. 10.10 Energy optimization results (global DVFS, proposed with EM, and with/without tight and loose soft error constraint from large task set on SPLASH-2 benchmarks (different power budgets in (a) and (b))) [31]

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(where both EM and soft error constraints are tight), our proposed method can find decent energy savings satisfying both EM and soft errors reliability constraints. In Fig. 10.11, we further show the EM (a) and soft error (b) constraint violation cases under different EM and soft error constraints and power constraints (cases 1, 2, 3, 4 for small task sets, 5, 6, 7, 8 for large task sets). In all the cases (1–8), the soft error constraints are all tight. For cases 2, 4, 8, the EM constraints are tight. First, as we can see, both EMs and soft errors are violated in cases 6 and 8 due to the tight soft error constraint with large task sets. For cases 2 and 4, only EMs are violated due to both tight EM and soft error constraints with small task sets. More interesting is in case 5 where EM is violated even the EM constraint is not tight. The

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reason is that we have very small power budget (tight power constraint). For case 7, which is large case, the soft error is very tight. As a result, soft error constraint is still violated even with large power budget. Therefore, as we can see, for energyefficient computing on manycore systems with power constraints (dark silicon), and competing hard and soft error constraints, the results are no longer a simple tradeoff among different factors, and instead, depend on those factors in a complicated way. In other words, under tightened power and performance constraints, we cannot satisfy both hard and soft errors at the same time and some other soft error mitigation techniques become necessary in this case. The proposed Q-learning method converges around 8% of explorations out of all possible state–action solution space as shown in Fig. 10.12. It also shows that system violation can be effectively prevented by our proposed penalty function (10.3.2). To show the scalability of our proposed algorithm, we have added one more performance state on 64-core dark silicon chip with 64 tasks SPLASH-2 multithreaded benchmark. The full power mode (2.0 GHz, 1.2 V), the low power mode (1.0 GHz, 0.9 V), and very low power mode (800 MHz, 0.7 V) have been set for our framework. We compare two different numbers of p-states, case 1 has two p-states (full power and low power) and dark silicon states, and case 2 has three pstates (full power, low power, very low power) and dark silicon states. Due to very low power mode, we choose relatively loose constraints (deadline = 12 ms, power budget = 350 W, EM = 5 years, SER = 0.6). As seen in Fig. 10.13a, our proposed

10 Learning-Based DRM and Energy Optimization for Manycore Dark Silicon. . .

Fig. 10.12 Convergence rate of the proposed DRM method with EM-induced lifetime constraint in 64-core dark silicon (SPLASH-2 Tasks) [31]

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algorithm can find low energy consumption with lower p-state cases. We chose three performance states (p-state) with the clustered DVFS [32], which have been employed to reduce the simulation time with small solution quality degradation due to a large number of cores in our experiment, so, case 1 is 150 states, and case 3 is 192 states. As seen in Fig. 10.13b, case 3 has 28% more states, but the iteration requires only 6.58% more steps. Table 10.3 showed elapsed CPU time to solve the proposed Q-learning and MILP problem for each case. Q-learning elapsed CPU time was obtained on iPython 5.1.0 with using only single core of Intel Xeon E5 system (clock 2.3 GHz) platform. Moreover, in order to show more higher scalability of the proposed algorithm, we increase p-states to five different ones for two large cases (128-core and 256-core), and their voltage and frequency (V ,f ) sets are (2.0 GHz, 1.2 V), (1.6 GHz, 1.1 V), (1.2 GHz, 1.0 V), (1.0 GHz, 0.9 V), and (800 MHz, 0.7 V) on 64 tasks SPLASH-2 multi-threaded benchmark. We used 16-core as one cluster for the clustered DVFS. Also, we use 32core as one cluster for dark silicon states in 128-core case and 64-core in 256-core case, which have been employed for a very large number of cores in our experiment. Table 10.4 shows the elapsed CPU time results for solving the proposed Q-learning result and energy savings over global DVFS. 128-core with 5 p-states (case 3) has 775 different states, which is 516% more states than case 1, but the iteration requires only 406% more steps. 256-core with 5 p-states (case 4) has 7160 states, which is 4773% more states than case 1, but only 4081% more steps are required. Thus, our proposed DRM can be a scalable solution for large number of cores and higher pstates cases since iteration steps and CPU times are close to increase linearly with respect to the total number of states. Both large cases also can find decent energy savings. Due to extremely high cost of MILP method for large case (128-core and 256-core with 5 p-states), the elapsed CPU times of Q-learning method have been only shown in Table 10.4.

10.5 Summary In this chapter, we developed a new energy and lifetime optimization technique for emerging dark silicon manycore microprocessors considering hard and soft errors. The new approach was based on a newly proposed physics-based electromigration (EM) reliability model to predict the EM reliability of full-chip power grid networks for hard error. DVFS-aware soft error rate (SER) model and the sum of the failure rates (SOFR) method were employed for system-level soft error model, which has been widely used to estimate microprocessor level soft errors. We employed both

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dynamic voltage and frequency scaling (DVFS) and dark silicon core state using on/off pulsing action as the two control knobs. The impact on DVFS for hard and soft errors was investigated. We focused on two optimization techniques for improving lifetime and reducing energy. To optimize lifetime, we first applied the adaptive Q-learning based method, which was suitable for dynamic runtime operation as it was able to provide costeffective yet good solutions. The second lifetime optimization approach was the mixed-integer linear programming (MILP) method, which typically yields better solutions but at higher computational costs. To optimize the energy of a dark silicon chip, we applied the Q-learning reinforcement learning method, which was suitable for our reliability management for the energy optimization considering hard and soft errors. Experimental results on a 64-core dark silicon chip showed that the proposed methods work well for performance and lifetime optimizations considering both the soft and hard reliability constraints.

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Chapter 11

Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

11.1 Introduction To further reduce powers for many applications, ultra-low power designs become necessary. Recent research has led to sub-threshold region where CMOS circuits are found to be capable of operating with a supply voltage of less than 200 mV. The theoretical lower limit of Vdd has been determined to be 36 mV [20]. But at such low voltages, a leakage power dissipation increases drastically making the reduction in dynamic power insignificant. Also the circuit delay increases rapidly as the supply voltage is scaled down, resulting in decreased operation frequency or performance of the circuits. For dark silicon manycore processors operating in near-threshold voltage, reliability becomes quite significant for the long-term reliability such as electromigration. To address the increasing reliability issues, a system-level and runtime approach becomes more appealing. There are some existing works on dynamic reliability managements for dark silicon in the past [9, 16]. These works have been proposed to leverage the dark silicon manycore processors in order to save energy while maintaining performance considering reliability. Runtime management of the heterogeneous dark silicon processors and optimal policy of core status have been addressed. Dynamic voltage frequency scaling method has been employed as energy saving techniques in those works. However, dynamic reliability management for near-threshold dark silicon processors has not been studied. This chapter presents a new dynamic reliability management (DRM) techniques at the system level for emerging low power dark silicon manycore microprocessors operating in near-threshold region [10]. We mainly consider the electromigration (EM) failures considering recovery effects. To leverage the EM recovery effects, which was ignored in the past, at the system level, we develop a new equivalent DC current model to consider recovery effects for general time-varying current waveforms so that existing compact EM model can be applied. The new recovery EM model can allow EM-induced lifetime to be better managed at the system level. © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_11

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11.2 Recovery-Aware Electromigration Modeling at System Levels 11.2.1 New Equivalent DC Current Based Modeling for EM Recovery Effects For EM failures, one of the important phenomenon is that the EM-induced stress can go down when the stressing current becomes small. This effect is called “EM recovery effect” as it represents important transient effects due to time-varying currents. Figure 11.1 shows the EM-induced stress changes over time over a periodic current pulse. As we can see the stress can go down significantly. The net effect for such recovery effect is that the lifetime of wire due to EM can be extended significantly as it will take longer time for the stress to reach to the critical stress over time. However, EM recovery effects were ignored completely in the existing EM models as most of those models assume constant current or current density. To mitigate this problem, a physics-based EM recovery model was proposed recently [7, 19] by obtaining an analytical solution of the Korhonen’s equation describing the stress evolution kinetics of EM effects. Although the accuracy of this model is high, it is still too complicated for practical use. For practical chip design, EM assessment and signoff still uses simple EM models like Black’s model [1] or the recently proposed, more accurate EM model in (2.6.1), which takes constant current and temperature as inputs. In order to consider practical no-DC currents, a simple time-varying equivalent DC current is computed as following, jtrans,EM,eff =

1 P

 0

P

 j+ (t)dt − γ

P 0

 |j− |(t)dt

(11.2.1)

where j+ (t) and j− (t) are the current densities of the positive and negative phases of the bipolar current, γ is the EM recovery factor, P is the period of the current waveform. When the current density is unidirectional, jtrans,EM,eff is essentially the time averaged current density. However, using the effective current formula in (11.2.1) will create a number of problems [11]. First of all, the recovery factor depends on the specific current waveforms which is not constant. Also, it ignores important transient effects such as the recovery and peak stress effects. Figure 11.2 shows the stress evolutions over time driven by two current waveforms, the actual one and the time-varying equivalent DC current. As we can see, the peak stress due to the actual current waveform can exceed the critical stress, while the average current never leads to void nucleation (wire is immortal). In order to solve the problems of these models, we propose a new and novel equivalent DC current method to consider the transient EM recovery effects. The new model is based on first-principle based numerical analysis of EM effects. Here we use nucleation phase to compute the time to failure of a wire as a demonstration

11.2 Recovery-Aware Electromigration Modeling at System Levels

Current Density (A/m2 )

6

249

×109

5 4 3 2 1 0 -1

0

2

4

6

8

10

8

10

Normalized Time (a) 6

×10

8

Stress (Pa)

5 4 3 2 1 0

0

2

4

6

Normalized Time (b) Fig. 11.1 Stress evolution caused by periodical current density [10]

of this proposed method. The idea is that for a given EM model, the DC equivalent current will lead to the same time to failure (TTF) computed from the detailed numerical EM analysis of stress diffusion equation. This is better illustrated in Fig. 11.3b in which the periodic current density and a DC current give the same nucleation time tnuc . Unlike the traditional method which could ignore the case that the peak stress exceeds the critical stress but the equivalent current density never

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11 Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

Fig. 11.2 Stress evolutions caused by actual currents and traditional effective DC current [10]

6

×108 Critical stress

Stress (Pa)

5 4 3 2

real stress traditional DC equvilent stress

1 0

0

2

4

6

8

10

Normalized Time

leads to void nucleation, so the transient effects are explicitly taken into account in this method. That model works well for standard periodic square waveforms with one high current density (j1 ) and one low current density (j2 ). As shown in Fig. 11.3a, j1 , j2 , period (P ), and duty cycle(D) are used as the variables in the model. Also we find that the temperature (T ) is one of the dominant parameters for the equivalent EM DC equivalent current density (jem ). To further derive the parameterized equivalent DC current in terms of two currents, period and duty cycle and temperature, response surface methodology (RSM) [14] is carried out over many different waveforms from measured or detailed numerical analysis information. (11.2.2) is the fitted model to obtain equivalent DC current in terms of the five parameters. jem =4.988 ∗ 109 − 0.0663 ∗ 109 ∗ X12 − 1.114 ∗ 109 ∗ X1 ∗ X2 − 0.9981 ∗ 109 ∗ X1 ∗ X3 − 0.1390 ∗ 109 ∗ X1 ∗ X4 − 0.3485 ∗ 109 ∗ X1 ∗ X5 − 0.0315 ∗ 109 ∗ X22 − 0.1728 ∗ 109 ∗ X32 − 0.3461 ∗ 109 ∗ X3 ∗ X4 + 0.0181 ∗ 109 ∗ X42 + 0.0934 ∗ 109 ∗ X52 where X1 =

j1 − 7.5 ∗ 109 (A/m2 ) 2.5 ∗ 109 (A/m2 )

X2 =

j2 − 1.75 ∗ 109 (A/m2 ) 2.75 ∗ 109 (A/m2 )

X3 =

D − 70% 25%

X4 =

P − 5.5 ∗ 103 (s) 4.5 ∗ 103 (s)

X5 =

T − 380(K) 20(K)

(11.2.2)

Current Density (A/m2)

11.2 Recovery-Aware Electromigration Modeling at System Levels

6

×109

5

j1

251

4 3 2 1

j2

0

Period

-1 0

2

4

6

8

10

Normalized Time (a) 6

×10

8

t

Stress (Pa)

5

nuc

4 3 2

real stress DC equivalent stress

1 0

0

2

4

6

Normalized Time

8

10 ×107

(b) Fig. 11.3 (a) Original input driving current density. (b) Calculated EM DC equivalent current density with tnuc [10]

However, this model can only handle regular square waveforms, but for practical cases, the current waveforms are arbitrary. To mitigate this problem, one of the ideas is to convert the arbitrary current waveform to an equivalent square waveform before we apply the after-mentioned parameterized equivalent DC current modeling. In this conversion process, we make sure that the stresses derived by the square waveform

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11 Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

and the actual current waveform will match at both the highest peak stress and the final stress (end of period or time) as shown in Fig. 11.4b. By matching the two stress points, we can find the two currents j1 for highest stress point and j2 for the end of period stress as shown in Fig. 11.4. During this conversion process, we assume that the given current waveform will repeat itself over time so that it becomes a periodic waveform. This assumption is reasonable as the future current or power of a chip cannot be predicted precisely in general and the recurrent assumption is a good guess.

×109

Current Density (A/m2 )

15 T1=373K T2=383K T3=393K T4=370K T5=380K T6=375K

T4

T1

10

5 T2

T5 T3

T6

0 0

200

400

600

800

1000

1200

Normalized Time (a)

250

stress(MPa)

200

150

100

original waveform equivalent square waveform equivalent DC

50

0 0

200

400

600

800

1000

1200

time(s) (b)

Fig. 11.4 (a) Original input driving current density. (b) Calculated EM DC equivalent current density with two methods [10]

11.2 Recovery-Aware Electromigration Modeling at System Levels 600 critical stress

stress(MPa)

Fig. 11.5 Comparing the nucleation time of two equivalent methods and original stress [10]

253

400

200

0

original waveform equivalent square waveform equivalent DC

0

5000

10000

15000

time(s)

The other idea is to convert the arbitrary current waveform directly to a DC equivalent current so that the stresses from two waveforms match at the end of period time as shown in Fig. 11.4b. But this approach may lead to large errors for time to failure estimation as it ignores the peak stress, which can be significant to determine the time reaching the critical stress (time to failure). To study the accuracy of the two modeling methods, the two-step method (square waveform modeling and RSM fitting and the direct equivalent DC current method) is proposed. We compare stress generated by two-step method and the stress given by direct equivalent DC current method against the stress generated by the original current waveform. The results are shown in Fig. 11.5. As we can see, equivalent square DC current density (two-step method) has smaller error compared to the direct DC equivalent method in terms of time to failure estimation. As a result, we will use the two-step method to compute the parameterized equivalent DC current.

11.2.2 EM Modeling for Varying Temperature Effects At the system-level EM reliability, the manycore system will run on different tasks under different voltages and frequencies. As a result, its temperature and current densities will change with time. However existing EM models including the new physics-based model can only take a constant temperature. The previous study shows that whole system MTTF or lifetime under different temperature can be approximated by [13]: MTTFEM =  n m=1

1 1 tm MTTF m



(11.2.3) /T

where MTTFm is the actual MTTF (mean time to failure) under the mth power and temperature settings for tm period, assumingthe chip works through n different n power and temperature settings and T = m=1 tm . Each MTTFm will be computed based on the EM models discussed in the previous section. To consider

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11 Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

a system-level EM reliability on a manycore dark silicon processor, we use the shortest lifetime among all the cores as the lifetime for all manycore processors [3].

11.3 New Learning-Based Reliability Management for Near-Threshold Dark Silicon for EM Recovery Effects 11.3.1 Near-Threshold Dark Silicon Near-threshold computing (NTC) has been proposed as a viable solution to overcome the limit of energy efficient computing by using optimal near-threshold voltage between super-threshold and sub-threshold region. NTC cores are operated at or near their threshold voltage Vth . By reducing supply voltage Vdd from nominal 1.1 V to 500 mV, a 10× energy efficiency gain can be achieved at the expense of 10× performance degradation [4]. Compared to the sub-threshold region where 20× energy efficiency can be achieved, but the 50× performance degradation due to increased circuit delay is too big a factor to ignore for large-scale applications. Applications with significant standby times benefit greatly from NTC. Memories have to retain their contents even though digital logic is to be powered off. Thus supply voltage scaling results in a significant reduction in leakage power. On the other hand, NTC is also a promising technique to mitigate the effects of dark silicon as cores can reduce power and temperature under a given power budget, thus, allowing a larger number of cores to be turned on simultaneously at costs of allowed performance losses. Recently, instead of operating the entire cores at either nominal voltage or near-threshold voltage (NTV), voltage islands have been defined such that only partial cores are operated at NTV and the rest is operating at a nominal voltage for more flexible trade-off between power and performance [17]. Supply voltage is proportional to the threshold voltage of the transistors in the core. The core with the highest threshold can determine supply voltage for the voltage island. However, the different types of parallel workloads can lead to performance degradation and energy waste. Efficient dynamic management and scheduling to find suitable NTC regions are needed. In addition to energy and performance, NTC has an effect on reliabilities. NTC may exhibit better long-term EM reliability, as a lower voltage can lead to lower temperature, current density, and residual stresses, which are the major factors of EM effects [6]. The NTV, which is a lower supply voltage, can improve EMinduced lifetime of dark silicon processors. However, using NTV for manycore can make significant performance issue since NTV still uses some cores operated at the nominal voltage and a manycore system’s reliability can be highly affected by those core’s reliability [3].

11.3 New Learning-Based Reliability Management for Near-Threshold Dark. . .

255

11.3.2 Framework of Dark Silicon in Near-Threshold Computing Region We present the framework for dynamic reliability management (DRM) at NTC region in dark silicon. The DRM framework employs several simulator models (microarchitecture, power, thermal), a policy optimization module, all in conjunction with EM recovery model. Additionally, the DRM has policy optimizer that cores can choose the best NTC policy to maximize energy efficiency while meeting performance limit and power budgets. This work uses a 45 nm-based 64-core dark silicon simulation framework with the threshold voltage of Vth = 0.20 V, core on/off knobs, and capabilities. The DRM module sets the voltage and frequency policy for the chip. Each core (k) can be assigned a voltage (Vk ), nominal (Vknom = 1.0 V) or near threshold (Vknt ) which is defined as 0.40V ≤ Vknt < Vknom . Additionally, the DRM can turn a core off nom/nt ). The DRM makes these decisions off (Vk ) and then turn a core back on(Vk based on an online policy optimization module that employs the SARSA algorithm which is explained later. In the framework, the DRM receives the new policy from the optimization module. It then sets each Vk or turns the core off. Additionally, each core operating frequency (fk ) is affected by Vk , because of this we use 11.3.1 as a relation to calculate fk based on its respective Vk . This ensures that the performance degradation from NTV is reflected in the simulation framework. This policy is then propagated to the architecture, thermal, and power simulators as well as the EM recovery model, and optimizer. fk ∝

(Vk − Vth )2 Vth

(11.3.1)

The framework uses the Sniper architecture simulator [2] to generate system performance for given workloads on a specified architecture. Parameters (chip floorplan, number of cores, frequency, and cache design) describing the architecture are passed to Sniper. Benchmarks representing the desired workloads are also used as inputs to sniper to simulate the system’s functionality. Sniper then outputs system performance, such as performance characteristics, instruction per cycle, of the chip for each given benchmark run. This is repeated in our experimental setup for several different set of workloads. The DRM framework for near-threshold dark silicon is illustrated in Fig. 11.6. Once the performance information is estimated from microarchitecture simulator, all the information is transferred to the physical simulators HotSpot [5] and MCPAT [12]. Based on the architecture of the chip, its system performance from Sniper, and the voltage scheduling from the DRM, MCPAT (Multi-Core Power Area and Timing simulator) will generate a power trace for each chip component including each core Pk . HotSpot then uses the chip floorplan in conjunction with the power trace generated by MCPAT, to produce a thermal trace for each chip component and core Tk .

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11 Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

Fig. 11.6 The DRM and NTC framework [10]

After the power/thermal/voltage characteristics have been generated by the various simulators, the EM recovery model can use these parameters (Pk , Tk , and Vk ) to estimate the chip’s time to failure considering any recovery effects the chip off may experience, from Vknt and Vk for that given policy. Lastly, all the information generated, in addition to the current policy enacted by the DRM, are passed to the policy optimizer which will generate a new policy. This new policy will find the best voltage schedule for the various cores to optimize the energy of the chip while meeting MTTF, performance, and power budgets.

11.3.3 SARSA-Based Learning Algorithm for DRM Considering Long-Term Recovery We can model our DRM problem as a Markov decision process (MDP) with states s(t) and actions a(t), where states are the parameters of the framework for the timestep t, e.g., fk(t) , Tk(t) , MTTF(t), Pk(t) , and Vk(t) . Actions are defined as changes to these parameters which in our case is the tuning of Vk(t) . In our case, our goal is to achieve the best policy that minimizes energy E while meeting all constraints and budgets.

11.3 New Learning-Based Reliability Management for Near-Threshold Dark. . .

257

The reinforcement learning algorithm used to optimize the DRM policy is the State–Action–Reward–State–Action algorithm, or SARSA, first presented in [15]. SARSA is a combination of Q-learning and the traditional temporal difference method (TD) [15]. This algorithm exchanges the greedy updates of Q-learning with a policy driven update that is closer to the TD method. The result is an onpolicy reinforcement learning algorithm with faster convergence when compared to Q-learning [15]. The major difference with traditional Q-learning is that the maximum reward (minimum penalty) for the next state is not used for updating the Q-values. Instead, a new action is selected using the same policy that determined the original action. The SARSA algorithm works first by populating a Q-table Q(s(t), a(t)), where s(t) is a state and a(t) is an action for time-step t. It then selects an action from the states using some policy. This action is taken and the penalty P T (t + 1) (negative reward) and new state s(t + 1) are generated. From this new state, another action a(t + 1) is selected from s(t + 1). The Q-table is then updated using a penalty function shown below. Qt+1 ((s(t), a(t)) = Qt (s(t), a(t))+ α(t) × (P T (t + 1) + γ Q(s(t + 1), a(t + 1)) − Q(s(t), a(t)))

(11.3.2)

Here, α is the learning rate and γ is the discount factor. In our DRM, we employ multiple-constrained penalty function (P T (t + 1), [9]) and modify to accommodate each value (EM, power, temperature, and performance) and to also incorporate the power budgets, performance/thermal limits assigned as constraints. In order to provide long-term shut-off time for leveraging EM recovery effects, our DRM has a recovery selection scheduler. It is a periodic scheduler on the top of SARSA for long-term recovery cycle (Trecovery ), which is the required time for recovery effects. The selected cores need to be turned off to enable the long-term recovery effects as seen in Sect. 11.2.1. For every Trecovery cycle, we use greedybased selection algorithm by EM-induced lifetime evaluation and find the worst lifetime core set below the certain lifetime threshold (EMthreshold ), then SARSA will work only for the cores except recovering cores for Trecovery . After each long-term cycle, we find new long-term recovery core set. The proposed new energy optimization algorithm in the near-threshold dark silicon framework has been implemented in Python 2.7.9 with the numerical libraries (NumPy 1.9.2 and SciPy 0.15.1). For near-threshold dark silicon framework, we used the architectural simulator (Sniper 6.1), power estimator (McPAT 1.0.32), and thermal simulator (HotSpot 5.02 [18]) to estimate recovery-considered EMinduced lifetime on top of the new physics-based EM model [6]. In the proposed framework as shown in Fig. 11.6, each simulator module is connected with a plugin connector, so that one simulator’s result can dynamically provide the other’s inputs. The learning-based SARSA method and recovery selection scheduler have been implemented for our dynamic reliability management (DRM).

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11 Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

The DRM module assigns each core as the near-threshold or nominal voltage, and calculates its frequency from 11.3.1. The near-threshold voltages as 0.45 V and a nominal voltage of 1.2 V are defined [8]. Additionally, each core can be turned off completely or turned back on for dark silicon. Once the simulation runs, the optimization module can then send a new policy to the DRM which it will use to schedule the core voltages. Our energy optimization method is validated with a near-threshold 64-core processor on the SPLASH-2 multi-threaded benchmarks.

11.4 Numerical Results and Discussions 11.4.1 Evaluation of the Lifetime Impacts Considering EM Recovery Effects In order to evaluate system-level EM-induced lifetime considering recovery effects, a single core long-term task example case from our framework is shown here. Our proposed framework, shown in Fig. 11.6, can properly manage and control for both power-on and shut-down of each core, so we can significantly extend the systemlevel reliability by leveraging the EM recovery effects introduced in Sect. 11.2.1. We present two different simple power traces and calculate EM-induced MTTF (mean time to failure) in Fig. 11.7. In this example, the time period is 1000 s and switch off for 500 s that can be recognized as a sufficient period for recovery effect. The original power traces (5.72 W) are converted to an equivalent power, which equals to 2.122 W using our recovery model. Our duty cycle for turning-off is 50% in the recovery case. As a result, it leads to 50% performance degradation. On the other hand, the EM-induced lifetime considering recovery effect is 9.16× higher than that of the original case without recovery effect case, which is quite significant.

11.4.2 Evaluation of the DRM for Near-Threshold Dark Silicon Processors To evaluate the proposed learning-based energy optimization method in Sect. 11.3, we show the comparison results of performance, EM-induced lifetime, energy consumption on processing 64 multi-threaded tasks on a 64-core near-threshold dark silicon processor. Our experiment uses performance and energy metrics as s/tasks and J /tasks, which are total execution time and energy consumption for selected 64 multi-threaded tasks (16 CHOLESKYs, 16 RADIXs, 16 RAYTRACEs, 16 VOLRENDs) on our framework. The results are shown in Table 11.1. We compare our DRM case (without recovery effects) with all-NTV cores (64 cores are near-threshold voltages(NTV)), half-NTV/half-dark (32 cores are NTV and 32 cores are turned off), and half-nominal/half-dark (32 cores are nominal and 32 cores are turned off) cases. The optimization results show the energy consumption

11.4 Numerical Results and Discussions

259

Fig. 11.7 (a) two cases of power traces from the proposed framework and (b) and the resulting MTTF without/with recovery effects [10]

(a) 250

MTTF (year)

200 150 100 50 0

without

with

Recovery Effects

(b)

Table 11.1 Results for dynamic reliability management for 64-core near-threshold dark silicon [10] 64-Core Performance (s/tasks) EM lifetime (year) Energy (Joule/tasks)

DRM no recovery 0.014 9.03 0.942

All NTV cores 0.23 221 14.54

Half-NTV /Half-dark 0.48 221 29.05

Half-nominal /Half-dark 0.03 7.1 2.07

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11 Recovery-Aware DRM for Near-Threshold Dark Silicon Processors

improvements for the given budget constraints (power budget is 250 W, performance limit 5 s per given tasks, and EM-induced lifetime limit is more than 5 years). For all-NTV and half NTV/dark cases, EM lifetimes are significantly improved, but their performance results are 16× and 35× slower than the DRM baseline result. On the other hand, for only half-nominal/half-dark case, energy and performance are quite improved but EM lifetime is relatively short. Therefore, our DRM result effectively finds better EM lifetime (9.03 years) with significantly high performance with the lowest energy.

11.4.3 DRM Considering Recovery Effects

Energy (J/tasks) Lifetime (year)Performance (s/tasks)

Finally, we evaluate our proposed DRM method considering the EM recovery effects. As seen in Fig. 11.8, we evaluate two different recovery cycles (Trecovery = 50 s and 1000 s), so all the cores’ MTTFs are periodically evaluated for every Trecovery to determine which core needs to be turned off for the whole period when the core is below the certain lifetime threshold, EMthreshold . For our experiment, we set 8 years as the EMthreshold in the recovery selection scheduler. As we can see, both DRM cases with recovery effects can significantly improve our EM-induced lifetime (8.6× longer compared to the baseline results, which are shown in the third column in Fig. 11.8). However, the costs are the 2.0× more energy consumption (1.9 J/tasks vs 0.94 J/tasks) and 3.3× performance degradations (0.05 s/tasks vs 0.014 s/tasks).

0.1 0.05 0 100 50 0 2 1 0 With Recovery (50s)

With Recovery (1000s)

No Recovery

Fig. 11.8 Performance, energy, and EM-induced lifetime from the proposed DRM considering recovery effects for three cases: (1) Recovery effects with Trecovery = 50 s (first column). (2) Recovery effects with Trecovery = 1000 s (the second column). (3) Only DRM without recovery effects (the third column) [10]

References

261

But this is still a better trade-off for the higher EM lifetime (64.7 years and 78.1 years for Trecovery = 50 s and 1000 s, respectively) compared with the baseline case in Fig. 11.8.

11.5 Summary In this chapter, we developed a new dynamic reliability management (DRM) techniques for emerging near-threshold dark silicon manycore microprocessors considering electromigration (EM) reliability. To leverage the EM recovery effects, which was ignored in the past, at the system level, we developed a new equivalent DC current model to consider recovery effects for general time-varying current waveforms so that existing compact EM model can be applied. The new EM current model allows EM recovery effects to be effectively considered at the system level for the first time. To leverage the EM recovery effects, we considered the energy optimization problem for dark silicon manycore processors with near-threshold voltage (NTV) capabilities considering EM reliability. We showed that the on-chip power consumptions have different impact on reliability. The optimization problem can be formulized into State–Action–Reward–State–Action (SARSA) reinforcement learning algorithm to optimize the near-threshold dark silicon cores’ voltage policy, thus it minimizes energy considering reliability. Experimental results on a 64core near-threshold dark silicon processor showed that the new equivalent EM DC currents model was able to fully exhibit the recovery effects at the system level so that trade-off between EM lifetime and energy/performance was easily made. We further showed that the proposed learning-based energy optimization can effectively manage and optimize energy subject to reliability, given power budget and performance limits.

References 1. J.R. Black, Electromigration-a brief survey and some recent results. IEEE Trans. Electron Devices 16(4), 338–347 (1969) 2. T.E. Carlson, W. Heirman, L. Eeckhout, Sniper: exploring the level of abstraction for scalable and accurate parallel multi-core simulations, in International Conference for High Performance Computing, Networking, Storage and Analysis (SC) (IEEE, Piscataway, 2011), pp. 52:1–52:12 3. A. Das, A. Kumar, B. Veeravalli, Reliability-driven task mapping for lifetime extension of networks-on-chip based multiprocessor systems, in Proceedings of the Conference on Design, Automation and Test in Europe, DATE ’13 (EDA Consortium, San Jose, 2013), pp. 689–694. http://dl.acm.org/citation.cfm?id=2485288.2485457 4. R.G. Dreslinski, M. Wieckowski, D. Blaauw, D. Sylvester, T. Mudge, Near-threshold computing: reclaiming Moore’s law through energy efficient integrated circuits. Proc. IEEE 98(2), 253–266 (2010)

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5. W. Huang, S. Ghosh, S. Velusamy, K. Sankaranarayanan, K. Skadron, M.R. Stan, HotSpot: a compact thermal modeling methodology for early-stage VLSI design. IEEE Trans. Very Large Scale Integr. VLSI Syst. 14(5), 501–513 (2006) 6. X. Huang, T. Yu, V. Sukharev, S.X.-D. Tan, Physics-based electromigration assessment for power grid networks, in Proceedings Design Automation Conference (DAC) (IEEE, Piscataway, 2014) 7. X. Huang, V. Sukharev, T. Kim, S.X.-D. Tan, Electromigration recovery modeling and analysis under time-dependent current and temperature stressing, in Proceedings of Asia South Pacific Design Automation Conference (ASPDAC) (IEEE, Piscataway, 2016), pp. 244–249 8. H. Kaul, M. Anders, S. Hsu, A. Agarwal, R. Krishnamurthy, S. Borkar, Near-threshold voltage (NTV) design: opportunities and challenges, in Proceedings of the 49th Annual Design Automation Conference, DAC ’12 (ACM, New York, 2012), pp. 1153–1158. http://doi.acm. org/10.1145/2228360.2228572 9. T. Kim, X. Huang, V.S. H.-B. CHen, S.X.-D. Tan, Learning-based dynamic reliability management for dark silicon processor considering EM effects, in Proceedings Design, Automation and Test In Europe (DATE) (IEEE, Piscataway, 2016) 10. T. Kim, Z. Sun, C. Cook, J. Gaddipati, H. Wang, H. Chen, S.X.-D. Tan, Dynamic reliability management for near-threshold dark silicon processors, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2016), pp. 1–7 11. K.-D. Lee, Electromigration recovery and short lead effect under bipolar- and unipolar-pulse current, in IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2012), pp. 6B.3.1–6B.3.4 12. S. Li, J.H. Ahn, R.D. Strong, J.B, Brockman, D.M. Tullsen, N.P. Jouppi, McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures, in Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture (ACM, New York, 2009), pp. 469–480 13. Z. Lu, W. Huang, J. Lach, M. Stan, K. Skadron, Interconnect lifetime prediction under dynamic stress for reliability-aware design, in Proceedings of the International Conference on Computer Aided Design (ICCAD) (IEEE, Piscataway, 2004), pp. 327–334 14. R.H. Myers, D.C. Montgomery, Response Surface Methodology: Process and Product Optimization Using Designed Experiments (Wiley, London 2002) 15. G.A. Rummery, M. Niranjan, On-Line Q-Learning Using Connectionist Systems (University of Cambridge, Department of Engineering, 1994) 16. M. Shafique, S. Garg, T. Mitra, S. Parameswaran, J. Henkel, Dark silicon as a challenge for hardware/software co-design: invited special session paper, in Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, CODES ’14 (ACM, New York, 2014), pp. 13:1–13:10. http://doi.acm.org/10.1145/2656075.2661645 17. C. Silvano, G. Palermo, S. Xydis, I. Stamelakos, Voltage island management in near threshold manycore architectures to mitigate dark silicon, in 2014 Design, Automation Test in Europe Conference Exhibition (DATE) (IEEE, Piscataway, 2014), pp. 1–6 18. K. Skadron, M.R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan, Temperatureaware microarchitecture, in International Symposium on Computer Architecture (IEEE, Piscataway, 2003), pp. 2–13 19. V. Sukharev, X. Huang, S.X.-D. Tan, Electromigration induced stress evolution under alternate current and pulse current loads. J. Appl. Phys. 118, 034504 (2015) 20. R.M. Swanson, J.D. Meindl, Ion-implanted complementary MOS transistors in low-voltage circuits. IEEE J. Solid State Circuits 7(2), 146–153 (1972)

Chapter 12

Cross-Layer DRM and Optimization for Datacenter Systems

12.1 Introduction Datacenter downtime has become a major concern as every minute equates to money lost. An unplanned outage can easily cost a datacenter $8000 per minute of downtime and can even reach costs of $16,000 per minute of downtime. The main root causes of unplanned failures are largely attributed to power system failure and human error. Hardware failures, such as server failures, only account for about 4–5% of unplanned downtime. However, these types of failures are often much more difficult and costly to recover from. As a result, unplanned datacenter outages caused by server failures are responsible for the highest incurred costs, compared to downtimes attributed to other root causes, despite their low rate of occurrence as seen in Fig. 12.1a [1]. This presents much of the motivation behind the work in this paper as we develop a framework for reducing this hardware failure subject to performance constraints. Although the servers consist of multiple components, existing works for datacenter hardware failure research have been mainly focused on the large-scale studies in a hard disk [16] and memory failures [17]. However, in a typical server, the processor accounts for the majority of the power consumption at nearly 40% compared to other component such as memory and peripherals [4] in Fig. 12.1b. Furthermore, a recent study found that processors are the leading cause of single node hardware failure in high performance computing clusters [13]. This trend is expected to become increasingly common as processor reliability is becoming a limiting constraint in high-performance processor designs due to high failure rates in deep submicron and nanoscale devices. Technology scaling has led to the continuous integration of devices, and processors will have more cores integrated. This growing trend for large-scale manycore devices was brought upon by the increase in transistor density and the subsequent breakdown of Dennard’s scaling. The result of which is the loss of power distribution scaling with transistor sizes, leading to increased chip temperatures, and the movement from utilization of a © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_12

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Fig. 12.1 (a) Total datacenter cost by primary causes of unplanned outage ($1000). (b) Power consumption breakdown for one server [11]

single powerful machine to a large cluster of machines which can help distribute workloads. However, large cluster system generates reliability concerns as we no longer can consider the reliability of just a single device or chip. This is especially true as each node in the datacenter begins to utilize highly integrated processors with their own reliability concerns. It is increasingly obvious that single server, or even chip level, reliability needs to be a large factor in how we address the reliability of numerous devices employed on a larger scale. In order to address these concerns, the relationship between datacenter and processor reliability should be examined. The reliability issue for datacenter presents the challenge of correlating processor and datacenter cluster reliability. We examine reliability effects of processors under practical datacenter workloads and model the effects that the operating parameters of the servers have on the processor reliability. This chapter presents a new approach for cross-layer EM-induced reliability modeling and optimization at physics, system, and datacenter levels [11]. We consider a recently proposed physics-based EM reliability model to predict the EM reliability of full-chip power grid networks for long-term failures. We show how the new physics-based dynamic EM model at the physics level can be abstracted at the system level and even at the datacenter level. Our datacenter system-level power model is based on the BigHouse simulator. To speed up the online optimization for energy in a datacenter, we develop a new combined datacenter power and reliability compact model using a learning-based approach in which a feed-forward neural network is trained to predict energy and long-term reliability for each processor under datacenter scheduling and workloads. To optimize the energy and reliability of a datacenter, we apply the efficient adaptive Q-learning-based reinforcement learning method.

12.3 EM-Induced Reliability-Aware Datacenter Model

265

12.2 EM-Induced Reliability Model for a Manycore Processor in Datacenter An existing EM model, including the new physics-based model, can only take a constant temperature. The previous study shows that system-level time to failure (TTF) or lifetime under different temperature can be approximated by [12]: EM reliability model for individual core can be expressed as follows: TTFi-core =  n k=1

1 ti,k TTF1 i,k



(12.2.1) /T

where TTFi,k is the actual TTF under the kth power and temperature settings for tk period, assuming ith core works through n different power and temperature settings  and T = nk=1 ti,k . Each TTFi,k will be computed based on the recently proposed physics-based EM model and assessment techniques [9]. A manycore processor lifetime can be defined as the shortest lifetime among the cores [3, 19]. The individual core lifetime can be obtained from (12.2.1). Recently, one study used performability as the ratio of number of non-failure cores over total number of cores [18] to explain chip multiprocessor (CMP). But the specific mechanism was not introduced and is too abstract, so we use the shortest lifetime in this chapter; however, our framework easily extends to support performability later.

12.3 EM-Induced Reliability-Aware Datacenter Model To evaluate datacenter-level EM-induced reliability, we use the BigHouse simulator [15], a simulation infrastructure for datacenter. BigHouse is based on stochastic queueing simulation, a validated methodology for simulating the power/performance behavior of datacenter workloads. The BigHouse simulator is widely used in academia, as well as in Google datacenter research [14, 15, 20]. BigHouse uses synthetic arrival/service traces that are generated through empirical interarrival and interservice distributions collected from real systems [14, 15]. We evaluate two major workloads, Domain Name Service (DNS) and Apache World Web Service (WWW), provided with the BigHouse simulator. These workloads are modeled by workloads distribution, which represents the average, standard deviation (σ ), and coefficient of variation (Cv ) for the interarrival and service time distributions of the workloads. The interarrival distribution is used to drive the queueing model, while the service time distribution is used for the service nodes. These synthetic arrival/service traces are fed into a discrete-event simulation of a G/G/k queueing system that models active and idle low power modes through statedependent service rates.

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During simulation time, measures of interest, such as power consumption and 99th percentile latency, are obtained by sampling the output of the simulation until each measurement reaches a normalized half-width 95% confidence interval of 5%. The simulation ends when the sample statistics are considered converged, that is, once the observed sample size is sufficient to achieve the desired confidence interval of 95%. The sample size required to achieve a certain confidence is given by: Nm =

2 ∗ σ2 Z1−α/2

2

(12.3.1)

where σ is the standard deviation of the samples,  is the half-width of the desired confidence interval, and Z1−α is the value of the standard normal distribution at the (1 − α/2)th quantile. For 95% confidence, this value is 1.96. To explore the EM effect on datacenter-level reliability, we integrate the EM model into BigHouse simulator. Additionally, we added thermal modeling into BigHouse, and drive the EM model using power, voltage, and temperature measurements. The thermal modeling is achieved using the HotSpot thermal model [8]. This thermal model offers a compact solution with relatively good accuracy and speed. HotSpot is integrated into BigHouse and fed a power trace of each simulated core using the method described above. Each core is then modeled and simulated to produce a thermal trace. It is this thermal trace that is used as the temperature measurements for the EM model. To explain server-level reliability on datacenters, we use average socket lifetime (mean time to failure, MTTF). One socket lifetime can be defined as the shortest lifetime among the processors in one server. We use tail latency as most important service latency for the datacenter since the tail flow completion time (FCT), 99th or 99.9th percentile FCT, can be more than 10× larger than the mean FCT. So tail latency is a very crucial performance metric for datacenter as the service response needs to wait for the slowest flow/workload to complete [2].

12.4 New Reliability-Constrained Energy Optimization for Datacenter In this section, we introduce new reliability-constrained energy optimization for datacenter. To speed up the online optimization for datacenter energy and reliability, we use feed-forward neural network (FNN), which is trained to predict energy and long-term reliability for each processor under datacenter scheduling and workloads. To further optimize energy and reliability of a datacenter model, we formulate a learning-based optimization method, Q-learning, as minimizing datacenter energy subject to reliability, given power budget and performance.

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12.4.1 Neural Networks for Datacenter Energy and Reliability Models 12.4.1.1

Review of Feed-Forward Neural Network

To build a compact energy and reliability model for datacenter systems, learningbased techniques such as neural network, which is composed of multiple processing layers, can learn representations of data with multiple levels of abstraction. Processor power consumption and EM-induced lifetime can be considered as supervised learning in neural networks. One advantage of neural networks is its wide applications for nonlinear systems. The universal approximation capability of feed-forward neural network (FNN) has been proved to show that any Borel measurable function can be approximated with any arbitrary accuracy by an FNN using squashing activation functions [7]. If we have an input vector u = {u1 , u2 , . . . , up } and an output vector y = {y1 , y2 , . . . , yq }, then the layer-wise structured FNN without bias node has the form a 1 = f 1 (uW (IN,1) ),

a 2 = f 2 (a 1 W (1,2) ),

a i = f i (a i W (i−1,i) ),

...,

...,

y = a k W (k,OUT)

(12.4.1)

where the activation function f is element-wise squashing operator such as a sigmoid or a hyperbolic tangent function; vector a i is the intermediate activation result of each layer; W (·,·) is the weighting matrix connecting adjacent layers. FNN with bias node requires each activation result vector a i to be appended with a fixed unit value before it is fed into next level of calculation, and the dimensions of W (·,·) also need to be adjusted accordingly. 12.4.1.2

Neural Network Training for Datacenter Reliability-Aware Energy Model

As seen in (12.4.1), in theoretical aspect, training a neural network is equivalent to the optimization problem to minimize cost function (without bias node or connections, without regulation terms): m

 3 3 3y j − yˆ j 3 J W (IN,1) , W (1,2) , . . . , W (k,OUT) =

(12.4.2)

j =1

where yˆ i is a neural network output which can be explicitly written in a nested activation form yˆ =f k (f k−1 (f k−2 (. . . f 2 (f 1 (uW (IN,1) )W (1,2) )W (2,3) . . .) W (k−2,k−1) )W (k−1,k) )W (k,OUT)

(12.4.3)

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Therefore, the training problem of neural networks can be solved by applying existing optimization methods such as gradient descent, Broyden–Fletcher–Goldfarb– Shanno (BFGS) algorithm [5], and the Quasi-Newton method with the cost function J . In practice, an algorithm with lower computational cost, Back-propagation, has been widely used for solving the training problem [6].

12.4.1.3

Neural Network Structure and Data Configuration

As shown in Fig. 12.2, the feed-forward neural network (FNN) can be constructed to predict energy and long-term reliability for each processor under datacenter scheduling and workloads. We separately construct and train networks for each individual workloads. The inputs to the neural networks are average load rate, power mode (quantified), and a number of servers in the datacenter. With these inputs, the neural networks can estimate average cluster power, average processor temperature, tail latency, and average socket MTTF. To train the neural networks more efficiently with less numerical stability issues, the scaling of the inputs is required. Otherwise, it can have a large effect on the quality of the final solution. As shown in Fig. 12.2, the number of servers is normalized. The average load rate can be used without scaling since it already has a good distribution. In the same way, the output data set can be scaled and converted into logarithmic scale since they are served as a part of the training input set in the back-propagation algorithm [6]. We use three hidden layers with sigmoid activation functions, with all layers having 15 nodes, respectively. The input and output layer sizes are 3 and 5, respectively.

Fig. 12.2 Feed-forward neural network structure and data configuration [11]

12.4 New Reliability-Constrained Energy Optimization for Datacenter

269

12.4.2 Q-Learning Optimization for Datacenter 12.4.2.1

State and Action Determination

Q-learning is a reinforcement learning method used as a controller to maximize long-term rewards. It can converge close to the optimal result of a state–action function for arbitrary policies while handling problems with stochastic transition [10]. In this case, state(s) used in this work consists of workload model, average load rate, power model, and a number of servers. Action (a) is used to describe transitions between two states. Executing an action in a certain state provides a learning agent contained in the model whose goal is to minimize penalty with updated Q-value by penalty calculation in the Q-table, also known as the state–action table. The environment part is reliability-aware BigHouse model, whose learning agent is Qlearning algorithm. The learning agent can obtain the environment state, calculate penalty function, and finally, decide the next action.

12.4.2.2

Q-Value Function and Q-Learning Process

In the Q-learning process, one critical issue is to define the Q-value function with penalty term. Each state si will determine average cluster power P ower(si ), tail latency of datacenter latency(si ), the average processor temperature, T emp(si ). EMmin (si ) is defined as average socket MTTF in datacenter. E(si ) is energy per request in datacenter. An action, say ai,j , can be viewed as the transition from state i to state j . The penalty function Q determines a penalty and a new state which is related to the previous state and selected action. Q-value is updated at every step t. Qt+1 (s(t), a(t)) = Qt (s(t), a(t)) 

+ α(t) × P T (t + 1) + γ min(∀Qt (s(t + 1), a)) − Qt (s(t), a(t)) a

(12.4.4) where α(t) is the learning rate between 0 and 1 which determines the percentage of newly calculated Q-value applied. s(t + 1) is determined by action a(t), and Qt (s(t + 1), a) are all possible action’s Q-values from future state. The discount factor γ (between 0 and 1) determines the importance of future penalty. min(∀Qt s(t + 1), a) is considered to be the estimated optimal future value. The difference between old Q-value (Qt ) and learned value (P T (t + 1) + γ min(∀Qt (s(t + a

1), a))) updates the new Q-value (Qt+1 ) with the learning rate. A penalty term (P T ) is shown in (12.4.5). P TE is a penalty term for total datacenter energy, P TEM is a penalty term for average socket MTTF, P Tpower for average cluster power, P Ttemp for average processor temperature, and P Tlatency is tail latency of datacenter. Each penalty term (P Tx ) is normalized in (12.4.5). For instance, P TE = E(t+1)−E(t) EMax −EMin is for energy related penalty, where E(t) is the energy per request in the previous time

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12 Cross-Layer DRM and Optimization for Datacenter Systems

t and E(t + 1) is energy per request of the datacenter at current time t + 1. For the EM MTTF, P TEM = MTTF(t)−MTTF(t+1) MTTFMax −MTTFMin is for EM related Penalty, where MTTF(t) is the average socket MTTF of the datacenter for EM-induced in the previous time t and MTTF(t + 1) is the average socket MTTF of the datacenter at current time t + 1. P T = P TE + C δx P T x x={EM,power,temp,latency}

 0 if P Tx ≤ Bx + x δx = 1 if P Tx > Bx + x

(12.4.5)

where δx is a binary function to active (δx = 1) or inactive (δx = 0) of user defined or given constraint bounds, Bpower , Blatency , and Btemp in the penalty term. They are also normalized average cluster power, tail latency, average processor temperature bounds, respectively. Each x is the difference between each bound and average penalty (P T ) for the power, latency, and temperature. x is positive if the whole datacenter violated the given constraint; otherwise, it is negative which means the system is bounded and working in acceptable condition. If the datacenter violated user’s constraints in the past, penalty would be significant due to large value for constant C in (12.4.5). The proposed learning-based energy optimization algorithm goes with the following flow: first, all the Q-values in the Q-table are initialized to zero. Current state s(t) finds an action a(t) with the lowest Qt in (12.4.4) and switches to next state corresponding to input values. For every step, average socket MTTF, latency, average processor temperature, average cluster power, and energy per request are evaluated and thus, all environments can be updated. Then, new corresponding penalty P T (t + 1) would be calculated in (12.4.5) and Qt+1 would be updated (learning process). After the update, the current state could be replaced by a new action and it would iterate with a newly updated state. Finally, when all the Q-value changes are less than a certain threshold, the best policy will be chosen based on the result.

12.4.3 Proposed New Datacenter Framework for Energy and Reliability To evaluate the proposed new reliability-constrained energy optimization for datacenter, we use BigHouse model, which can provide cluster power and performance models with different datacenter scheduling and workloads, such as average load rate, power model (low, mid, and high), a number of active servers in datacenter. Once BigHouse model generates the performance and power traces of each core in the server of datacenter, HotSpot can generate each core’s temperature from the power traces. For the EM-induced reliability, we use the power traces, the

12.4 New Reliability-Constrained Energy Optimization for Datacenter

271

thermal traces, and the core’s voltage as input to generate the individual core EM-induced lifetime of a manycore processor. As explained in Sect. 12.2, systemlevel (a processor) EM-induced lifetime can be calculated. For the datacenter level lifetime, we use average processor MTTF. The training data can be obtained from BigHouse simulator with all the possible datacenter scheduling and workloads to train the neural network to speed up online optimization for datacenter power and reliability model. With the trained network, Q-learning method can find the optimal policies for datacenter scheduling and workloads to achieve minimizing energy subject to given reliability, power performance constraints as seen in Fig. 12.3.

Fig. 12.3 The evaluation platform for datacenter and energy and reliability management algorithms [11]

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12 Cross-Layer DRM and Optimization for Datacenter Systems

12.5 Numerical Results and Discussions 12.5.1 Experimental Setup The proposed new compact model (FNN-based) and optimization (Q-Learning) for the datacenter framework have been implemented in Python 2.7.9 with the numerical libraries (NumPy 1.9.2 and SciPy 0.15.1). Thermal model (HotSpot 6.0 [8]) to estimate EM-induced lifetime. BigHouse utilizes a simple system-level power model, as shown in Fig. 12.3, which takes in a server utilization and outputs the power consumption of each server. Two major workloads (DNS and WWW) have been used to evaluate our proposed models. The server power model is based on a highly energy proportional server (Huawei XH320) derived from reported SPECpower benchmark results [21]. Our EM model requires per core energy. In order to extract per core energy, we instrumented a high energy proportional server to measure per-component power, with component breakdown as shown in Fig. 12.3. We instrumented each individual component by intercepting the power rails and measuring the current with LTS 25-NP current sensors. The outputs of the current sensors are sampled at 1 kHz using a DAQ and logged using LabView. To measure CPU power, we inserted a current sensor in series with the 4-pin ATX power connector. To measure memory power, we inserted a current sensor in series with pins 10 and 12 of the 24-pin ATX power connector which supplies power to the motherboard. To measure the power of the hard drive, we inserted a current sensor in series with the hard drive backplane power connector. We use the per-component power breakdown to derive the per core power from the server.

12.5.2 Evaluations of the Proposed New Modeling and Optimization First we evaluate our learning-based datacenter modeling (see Sect. 12.3). We get normalized ,  root mean square error (RMSE) by calculating 1 1 (yest − yref )2 , where yref and yest are obtained from the max(yref )−min(yref ) n reliability-aware BigHouse model (reference) and FNN-based model (estimated), respectively. Table 12.1 shows each training error and validation error of the proposed compact model. In validation phase, both estimations have good accuracy on DNS and Web datacenter workloads, where RMSEs are lower than 10%. Second, we evaluate our learning-based optimization method (see Sect. 12.4.2) by optimizing for energy savings with different sets of average processor MTTF, average cluster power, and tail latency. Table 12.2 and Fig. 12.4 show the energy savings given constraint for average processor MTTF, average cluster power, and tail latency, with DNS and WWW workload on the proposed datacenter framework.

12.6 Summary

273

Table 12.1 Accuracy analysis (RMSE) of the feed-forward neural network (FNN) model [11] Metric Tail latency Avg. cluster power Avg. proc. temp. Avg. proc. MTTF Energy per request

Training error DNS (%) 3.97 2.64 0.549 5.59 0.671

WWW (%) 6.53 2.45 2.91 6.78 0.738

Validation error DNS (%) 2.83 3.02 0.497 5.70 1.57

WWW (%) 9.37 3.50 2.92 7.40 1.20

Table 12.2 Energy optimization for datacenter [11] Max state (DNS) Case 1 (DNS) Case 2 (DNS) Case 3 (DNS) Max state (WWW) Case 4 (WWW) Case 5 (WWW) Case 6 (WWW)

Energy per request (J) 67.63 18.76 24.08 35.04 23.71 8.44 8.44 12.25

Energy saving (%) 72.25 64.39 48.18 64.37 64.37 49.30

As we can see, energy savings for the different constraints have been evaluated in Fig. 12.4, cases 1–3 are DNS workload and cases 4–6 are WWW workload with tight MTTF constraints (cases 1 and 4) and loose MTTF constraints (cases 3 and 6). In Table 12.2, our method finds relatively high energy savings for each case.

12.6 Summary In this chapter, we developed a novel cross-layer approach to optimizing the energy of a datacenter subject to long-term reliability and performance constraints. We considered a recently proposed physics-based EM reliability model to predict the EM reliability of full-chip power grid networks for long-term failures. We showed how the new physics-based dynamic EM model at the physics level can be abstracted at the system level and even at the datacenter level. To speed up the online optimization for energy for datacenter, we developed a new combined datacenter power and reliability model using a learning-based approach in which a feed-forward neural network (FNN) was trained to predict energy and longterm reliability for each processor under datacenter scheduling and workloads. To optimize the energy and reliability of a datacenter model, we applied the Qlearning-based reinforcement learning method. Experimental results showed that the proposed compact models for the datacenter system trained with different

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12 Cross-Layer DRM and Optimization for Datacenter Systems

Avg socket MTTF(yrs)

Average cluster power (W)

60

3000

40

2000

MTTF Constrain

Average Power Constrain

Avg Processor MTTF

Average Cluster Power

20

1000

0 1

2

3 4 (a)

5

0

6

1

2

3 4 (b)

5

6

Tail latency 1.5 1 0.5

Tail Latency Constrain Tail Latency

0 1

2

3 4 (c)

5

6

Fig. 12.4 Validating violations with constraint limits. (a) Average socket MTTF. (b) Average cluster power. (c) Tail latency [11]

workloads under different cluster power modes and scheduling policies were able to build accurate energy and lifetime.

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Part II

Transistor Aging Effects and Reliability

Chapter 13

Introduction

The first part of this book focused on interconnect aging effects. In this part we focus on aging effects in active components and in particular transistors. This chapter introduces an overview of transistor aging provoked by different wearout physical effects such as bias temperature instability (BTI), hot carrier injection (HCI), random telegraph noise (RTN), and time dependent dielectric breakdown (TDDB). We discuss how this transistor aging effect is affected by various process and runtime variation effects and the impact of technology down-scaling on transistor aging reliability.

13.1 Transistor Reliability in Advanced Technology Nodes With aggressive down-scaling of CMOS technology into deep nanometer, reliability has become a major issue [31]. In this section, the general sources of transistor reliability issues in current technology nodes are briefly explained. The sources of unreliability in current technology nodes can be categorized into three different categories: (1) variability issues, (2) transient faults and soft errors, (3) permanent faults, all of them closely related to the fabrication process and to actual economical and physical difficulties to further improve the fabrication process [14], to the stochastical fluctuations of dopants in transistor channel and the thin oxide thickness [4], and to the intrinsic mechanisms of transistor and interconnect aging [28]. Due to variability, the devices/gates/circuits characteristics are different from the intended designed ones. The variability could be due to “time-zero” variation (process variation) or runtime variation such as voltage and temperature variations [50]. Process variation is a natural device parameter variation which makes the properties of fabricated devices different from that of designed ones. In other words, due to process variation different similarly designed transistors/gates will perform © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_13

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13 Introduction

(operate) with parametric differences after fabrication. Due to runtime variation, the transistors/gates properties will change (degrade) during the chip operational lifetime. Runtime variations are routed in different sources such as voltage variation and temperature variation. The voltage and temperature variations are temporal or spatial according to the place of the transistor/gate and they depend on the workload, frequency, and time of operation. Therefore, they cause variation on the properties of different transistors/gates at different locations of the circuit and at different time points during the chip operational lifetime. Transistor aging is a source of runtime variations caused by different wearout effects such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), and soft Time Dependent Dielectric Breakdown (soft TDDB), which in turn are dependent on process and runtime variations. All these effects cause the threshold voltage of the transistors to increase and hence the switching delay of the gates that containing these transistors increases which can eventually lead to parametric timing failures if the delay of the circuit does not meet the timing constraints [25]. In order to deal with these sources of variation, traditional approaches consist in improving the technology process as much as possible, or to add guard-banding as a common approach at the design level. The guard-banding approach, a timing margin is added to the designed clock cycle in order to guarantee the correct operation of the circuit during the operational lifetime. A pessimistic guard-banding leads to a performance loss, and an optimistic guard-banding results in a low reliability of the chip. Therefore, the required timing margin needs to be accurately predicted. Figure 13.1 shows the components of the required timing margin for IBM Power7+ processor [58]. As shown in this figure, the main components of the timing margin are uncertainty (e.g. global and local process variation), wearout (transistor aging), and voltage and thermal variations. Time dependent dielectric breakdown (TDDB) is also a major reliability issue which can lead to permanent fault [2]. The material of transistor gate oxide is degraded when a sufficiently high electric field is applied across the gate oxide which leads to an increase of its conductance. In case of a long-term application of electric field a conductive path may be formed through the gate oxide leading to an abrupt increase of gate leakage current. This issue is called hard TDDB and Fig. 13.1 Components of chip guard-band for the IBM Power7+ [58]

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it becomes more severe as the gate oxide thickness becomes thinner due to the technology scaling. In the following sections, some of the reliability issues which are targeted in this chapter will be explained in more details.

13.2 Transistor Aging Transistor aging is one of the major sources of reliability issues in current technologies [52]. The transistor switching delay is degraded over time due to the transistor aging which can eventually cause the circuit to fail if the timing constraint is not met. In this chapter, the focus is on the two major sources of transistor aging which are Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) [53]. The physical mechanism and modeling of these two effects will be described in more details in the following sections.

13.2.1 Bias Temperature Instability (BTI) BTI is a wearout phenomenon, which gradually degrades the voltage threshold of a transistor. Consequently, the switching delay of the gate will be degraded and further to the circuit path delay. This degradation is monotonous over time. BTI consists of two similar phenomena: (1) Negative BTI (NBTI) affecting PMOS transistors and (2) Positive BTI (PBTI) affecting NMOS transistors. NBTI was considered as an important reliability issue for a long time, and PBTI was neglected due to its small effect on NMOS transistors, however, by the introduction of high-κ metalgate technologies, PBTI becomes comparable to NBTI [55, 74]. NBTI degradation manifest as a degradation of all electrical parameters of a MOS transistor, under a negative VGS (for PMOS transistor) at relatively high temperatures. It is a static degradation phenomena, as there is no current in the channel (VDS = 0 V). This degradation gets worse when increasing the temperature, but depends on the type of oxide (SiO2, SiON, HfO2, HfSiON) and its thickness [12, 27]. It is usual to quantify this degradation as an important increase of the threshold voltage and a direct current reduction. In general, there are two main models describing this phenomenon: (1) reactiondiffusion (RD) model [3, 44, 66] and (2) trapping-detrapping (TD) model [26, 33]. According to both models, BTI consists of two phases: • Stress phase The transistor is under NBTI (PBTI) stress if the gate-source of the PMOS (NMOS) transistor is negatively (positively) biased at relatively high temperature. In other words, the transistor is under stress if it is ON. According to the RD model, in this phase, some of the Si–H bonds at the interface of the channel and the gate oxide are broken leading to the generation of interface traps

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13 Introduction

Fig. 13.2 BTI mechanisms: (a) Reaction-Diffusion (R-D) mechanism. (b) Trapping-Detrapping (TD) mechanism

(Reaction). This reaction is triggered by the carriers in the channel (electrons in NMOS and holes in PMOS). The reaction-generated species (hydrogen atoms or molecules) diffuse inside the gate oxide (diffusion) leading to the generation of traps inside the gate oxide. The generation of these traps at the interface of the channel/gate oxide and inside the gate oxide leads to an increase in the threshold voltage of the transistor. The RD mechanism is shown in Fig. 13.2a. On the other hand, based on the TD model, during the stress phase some pre-existent traps inside the gate oxide captures the charge which leads to an increase in the threshold voltage of the transistor (see Fig. 13.2b). • Recovery phase The transistor is in recovery phase if the gate-source bias is removed, i.e. when the transistor is OFF. In this phase, according to the RD model, some of the generated traps are removed since some of the generated hydrogen atoms and molecules diffuse back especially for thin oxide thickness structures where the gate tunnel current is important. According to the TD model, during this phase, some of the traps which captured the charge re-emit their charge. In general, the threshold voltage of the transistor decreases during the recovery phase, however, it cannot completely compensate the threshold voltage shift due to the stress phase. Similar behavior occurs for NMOS transistor, and we call this phenomena PBTI. In this case the carriers injected in the gate oxide under a positive VGS are the electrons. PBTI degradation is lower than NBTI, even for most advanced nodes [36, 67] . Next figure shows the evolution of the Vth with the time for NMOS and PMOS transistors for 40 nm technology node, for the same input voltage constraint 2.5 V at 125 ◦ C [49] (Fig. 13.3). The difference of behavior between NBTI and PBTI is explained by the fact that holes are more efficient to generate defects inside the oxide and at the oxide interface than electrons that are injected in the channel by the date tunnel current that occupy pre-existing defects in the dielectric.

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Fig. 13.3 Threshold voltage shift due to NBTI and PBTI for 40 nm technology node with voltage constraint 2.5 V at 125 ◦ C

There is still a debate about the model which explains the BTI effect better (TD or RD) [35]. According to the literature, although the RD model is suitable to accurately predict the stress phase, it fails to cover the recovery phase [26]. It is observed that even after long time stress (1000 s), threshold voltage drops significantly after 1 s recovery (a very fast recovery) [54]. This fast recovery cannot be explained well by the RD model and it is well explained by TD model [24], however, the RD model is suitable to predict the long-term effect of BTI [26]. In previous technology nodes, the BTI effect on transistors was fairly deterministic for a particular workload condition (e.g. temperature and stress) [47]. However, by further down-scaling of the transistor dimensions into deca-nanometer range, the number of defects per device decreases leading to a drastic increase in the time dependent variability of BTI [68]. Thus, it is important to model the stochastic behavior of BTI in advanced technology nodes. In the following we will explain two BTI models which are used in this thesis in more details. One is a deterministic RD model, and the other one is a stochastic atomistic trap-based model.

13.2.1.1

Deterministic RD Model

For the deterministic RD model we exploit the model proposed in [3, 66]. The model is proposed for NBTI effect, but since the mechanisms of NBTI and PBTI are the same, we have used similar model to address the PBTI effect. NBTI can be modeled for two different cases: (1) Static NBTI: in which the transistor is under constant stress and (2) Dynamic NBTI: in which the transistor alternatively goes to stress (ON) and recovery (OFF) phases. The static NBTI is more severe compared to the dynamic one since the transistor has no time for

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13 Introduction

recovery in the static NBTI (see Fig. 13.4a). The threshold voltage shift (Vth ) due to the static NBTI effect can be expressed by: 2n

4 static Vth = A (1 + δ)tox + C(t − t0 "   2   qtox 3 2 Eox A= K Cox (VGS − Vth ) exp ox E0

(13.2.1) (13.2.2)

where q is the electron charge, Eox is the electric field of the gate oxide, Cox is the oxide capacitance per area, and n is a technology dependent factor which is either equal to 1/4 or 1/6. The other constants and coefficients are summarized in Table 13.1. Table 13.1 RD model of NBTI-induced Vth NBTI-induced Vth Static Dynamic

2n  √ A (1 + δ)tox + C(t − t0  2n √ Stress Kv (t − t0 )1 /2 + 2n Vth0

 √ Recovery Vth0 1 − 2ξ1 te + ξ2√C(t−t0 ) 2tox + Ct %4 &2n Long-term Kv2 αTclk 1/2n

1 − βt Constants and coefficients A Kv Eox C te

Ea (eV) E0 (V/nm) δ K(s−0.25 C−0.5 nm−2 ) ξ1 ξ2 To

"   Eox 2 qtox 3 2 K Cox (VGS − Vth ) exp( ) ox E0     √ qtox 3 2 2Eox K Cox (VGS − Vth ) C exp ox E0 VGS − Vth tox To−1 · exp(−Ea /kT ) if t − t0 > t1 tox otherwise t − t0 ξ2 C(t − t0 ) tox − t1 2ξ1 0.49 0.335 0.5 8 × 104 0.9 0.5 10−8 

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For dynamic NBTI, the Vth shift of each stress and recovery phases can be separately expressed by the following equations: 2n

4 Stress : Vth = Kv (t − t0 )1 /2 + 2n Vth0 √   2ξ1 te + ξ2 C(t − t0 ) Recovery : Vth = Vth0 1 − √ 2tox + Ct

(13.2.3) (13.2.4)

where the constants and coefficients are described in Table 13.1. Equations (13.2.3) and (13.2.4) can be exploit to obtain the long-term dynamic NBTI-induced Vth shift when transistor undergoes alternate stress and recovery phases: %4 dynamic Vth

βt = 1 −

=

2ξ1 te +

√

Kv2 αTclk

&2n

1/2n

1 − βt

ξ2 C(1 − α)Tclk √ 2tox + Ct

(13.2.5)

(13.2.6)

where Tclk is the clock cycle. α in this equation is the Duty cycle and defined as the ratio of the time in which transistor is under stress to the total time. NBTI-induced Vth is a strong function of the duty cycle as shown in Fig. 13.4b. The dependence Fig. 13.4 (a) Static vs. dynamic NBTI and (b) the dependency of dynamic NBTI to duty cycle

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13 Introduction

Fig. 13.5 (a) BTI effect in large devices, (b) stochastic behavior of BTI in deeply-scaled devices and (c) lifetime of devices for different technology nodes [34]

of duty cycle has been confirmed by many measurements performed by different industry teams, on different technology processes [38]. All the equations and related coefficients and constants are summarized in Table 13.1.

13.2.1.2

Stochastic Atomistic Trap-Based Model

It is shown that a large portion of the BTI degradation and relaxation during the stress and the recovery phases is due to the charging and discharging of pre-existent gate oxide defects [22]. In previous technology nodes, the BTI effect on transistors was fairly deterministic for a particular workload condition (e.g. temperature and stress) due to the large number of defects in the device (see Fig. 13.5a) . However, by further down-scaling of the transistor dimensions into deca-nanometer range, the number of defects per device decreases leading to a drastic increase in the time dependent variability of BTI [68] (see Fig. 13.5b). As a result, the lifetime of the device becomes also a stochastic value. Figure 13.5c shows the lifetime of the device for different technology nodes. As shown in this figure, the lifetime spread of smaller devices with lower number of defects is larger. Therefore it is important to model the intrinsic variation of BTI. In this chapter, we consider the model proposed in [33, 34] for stochastic behavior of BTI. In this model, each device is characterized by three different factors [33] (see Fig. 13.6): • Number of defects (n) • Defects capture time (τc ): it is defined as the time needed to charge a gate oxide defect during the stress phase. • Defects emission time (τe ): it is defined as the time needed for the defect to reemit its charge during the recovery phase. By knowing these parameters for each device, the total BTI-induced Vth of each transistor can be calculated according to Fig. 13.6b. In this model the total number of defects is obtained from a Poisson distribution:

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Fig. 13.6 (a) Parameters affecting BTI for three different devices. (b) BTI-induced Vth for the three devices [33]

n = Poiss(NT )

(13.2.7)

NT ∝ (L · W )

(13.2.8)

where NT is the mean number of charged (occupied) defects (traps). L and W are the length and width of the transistor. The effect of each occupied trap is obtained from an exponential distribution: V thi = exp(η)

(13.2.9)

η ∝ 1/(L · W )

(13.2.10)

where η is the average impact of individual defect on threshold voltage (∝1/device area). An analytical description has been derived [33] for the total BTI V th cumulative distribution function as: Hη,NT (V th) =

∞ −NT n  e N T

n=0

n!

  n V th 1 −  n, n! η

(13.2.11)

This formulation allows for an elegant parameterization of the distribution using the average number of defect NT and the average impact per defect η which further describes the mean and the variance: μV th = V th = NT η

(13.2.12)

2 2 σV th = 2NT η

(13.2.13)

The average impact per defect η can be extracted from experiments [16]. The average number of defect NT can be calculated using capture/emission time (CET) maps. CET map describes the probability density function of a broadly distributed defect capture and emission times and it is obtained from experimental data [23, 48] (see Fig. 13.7a). To build the complete CET-map, an analytical 2-component bivariate log-normal mixture distribution is used with a probability density of fCET (τc , τe ). By integrating the CET map over the entire time domain, the total

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13 Introduction

Fig. 13.7 (a) CET map, (b) occupancy probability map, and (c) CET-active map [68]

defect density (nT ) and the mean number of available traps in each device (NTavv ) can be calculated as follows:   fCET (τc , τe )dτc dτe (13.2.14) nT = NTavv = W · L · nT

(13.2.15)

All of these available traps do not contribute on the total BTI-induced Vth shift but those which are charged (occupied). The occupancy probability of each trap (Pocc ) depends on the applied stress waveform (see Fig. 13.7b) and can be extracted by the following equation: α % &⎞ ⎛ α 1−α + −t f τ stress c 1−e ⎜ ⎟ τc τe % & 1−e = ⎠ 1 α 1−α ⎝ + − τe 1 − e f τc −

Pocc

(13.2.16)

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289

where α is the duty cycle (the ratio between the stress time to the total time), f is the frequency, and tstress is the total time. Using this occupancy probability (Pocc ), the CET-active map can be obtained which shows the distribution of active traps (charged defects) according to the corresponding stress waveform (see Fig. 13.7c). By integrating the CET-active map over the entire time domain, the average number of defects (NT ) can be obtained by the following equations: ++ ρ=

fCET (τc , τe )Pocc (τc , τe , α, tstress , f )dτc dτe ++ fCET (τc , τe )dτc dτe

NT = ρ · NTavv

(13.2.17) (13.2.18)

where NT is the average number of defects as a result of the applied stress waveform. This parameter is used in Eq. (13.2.11) to obtain the CDF of BTI-induced Vth .

13.2.1.3

Process Variation and Stochastic BTI: Are they Correlated?

Since both process variation and stochastic BTI can affect the threshold voltage of a transistor, it is important to consider the correlation of these two effects for the calculation of the total threshold voltage shift of the transistor considering both effects. According to [1, 34], there is no correlation between BTI-induced threshold voltage shift and process variation. However, there is a strong correlation between the standard deviation quantities of threshold voltage shift of these two variation sources since identical sources are responsible for process variation and stochastic BTI variability [63]. From measurements, independently of the technology [63], the correlation has been found to follow the empirical relation: μV th 2 σV thPV B B = 100 mV

2 σV th (t) =

(13.2.19) (13.2.20)

where B is a technology specific parameter. It is important to note that the variances are correlated here, the V th and initial V th are assumed not to be [1, 34]. Assessing the impact of degradation induced time dependent variability of the V th will be a difficult task in future technologies because of the uncertainty on the BTI critical parameters η and NT .The correlation between process variation and stochastic BTI however gives a powerful predictive method for evaluating existing and future technologies. Combining (13.2.12) and (13.2.13) with (13.2.19), η can be directly derived from the initial process variation: η=

1 2 σ 2B V thPV

(13.2.21)

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13 Introduction

or combining with Pelgrom’s mismatch law: η=

AV th √ 2B W L

(13.2.22)

Thus, for simulating future technologies, η is derived directly from the expected Pelgrom’s mismatch parameter AV th [40, 64, 73] and NT will be calculated using (13.2.16), (13.2.17), and (13.2.18) with a CET map measured on polysilicon oxynitride (SiON) process technology. The scaling of oxide thickness TOX and stress voltage is incorporated by using a power-law extrapolation for the overdrive electric field EOX (calculated as VOV /TI N V .) [10]. Here the V th degradation is proportional to (EOX )γ , where γ is the voltage acceleration which has a typical value of 3 [17]. Assuming there are no changes in the oxide or oxide quality the extrapolation towards more scaled nodes is done using the following relationship V thref  V thsim  = (EOX,ref )γ (EOX,sim )γ

(13.2.23)

As shown in Fig. 13.8, values for η and NT can be readily obtained when using the methodology described above. Fig. 13.8 (a) η calculated using (13.2.22) for different FinFET technologies. (b) Average number of occupied traps as function of DF for different FinFET technologies calculated using (13.2.16), (13.2.17) and (13.2.18)

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291

13.2.2 Hot Carrier Injection (HCI) “Hot” carriers are referred to carriers which have a temperature much higher than the lattice temperature [15]. When the transistor is in saturation mode, some of the carriers become “hot” due to the high lateral field and they gain enough energy to overcome channel/gate oxide potential barrier (channel hot carriers) [8]. These channel hot carriers may collide with the silicon atoms in the pinch-off region and generate electron-hole pairs due to the impact ionization. Some of the generated carriers may become “hot” and overcome channel/gate oxide potential barriers [8]. The second type of hot carriers are called avalanche hot carriers. Both channel and avalanche hot carriers may be injected in the gate oxide. Damaging the hot carriers can generate traps inside the gate oxide or charge existing oxide traps. The gate oxide damage degrades the device characteristic such as the drain current and specially the threshold voltage of the transistor. This phenomenon is called hot carrier injection (HCI) or channel hot carrier (CHC) which is an important transistor aging issue in nanometer-technology nodes. The physical mechanism of HCI effect is depicted in Fig. 13.9. HCI describes degradation of the electrical parameters of a MOS transistor under a dynamic stress mode, as it occurs over the whole VDS /VGS range (note that BTI was present only under vertical electrical field with null VDS biasing). We can easily assume that HCI physical phenomena is worst during the rise and fall bias of the transistors in a given gate. HCI issue is observed as a critical issue in Eighties [8] due to the high lateral electric filed in the technologies used in these period of time. However, from the mid-Nineties, the supply voltage started to decrease by the technology scaling to decrease the power consumption issue [5]. As a result the lateral electric field decreased and hence the HCI effect became less by technology scaling. This trend has stopped in recent technology nodes, due to the fact that the supply voltage scaling is slowing down or stopping due to various reasons such as non-scalability of the threshold voltage and the sub-threshold slope, signal-to-noise margin issue and process variation. Therefore, the lateral electric field started to increase and hence HCI again has become an important transistor aging issue [5]. HCI mainly affects NMOS transistors, and its effect is negligible in PMOS transistors [62] since in the PMOS transistors fewer hot-carriers are generated. The reason of this is twofold: (1) shorter mean free path of the holes and (2) higher oxide barriers for holes. Fig. 13.9 Hot Carrier Injection (HCI) physical mechanism

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13 Introduction

Fig. 13.10 HCI-induced Vth over time

13.2.2.1

HCI Model

In this section, we explain the HCI model that is used in the literature. As mentioned previously, the device characteristics such as threshold voltage and sub-threshold slope are degraded due to the HCI effect. Here, the model of transistor Vth shift as the main effect of HCI is explained (see Fig. 13.10). Hot carriers are generated during logic transition and hence the HCI-induced Vth degradation is a function of switching frequency of the input signal [56, 62]: Vth = AHCI × SW × f × e Eox =

Eox E1

× t 0.5

VGS − Vth tox

(13.2.24) (13.2.25)

where AHCI is a technology dependent constant, SW is the switching activity factor, and f is the clock frequency. Vth and VGS are the threshold voltage and the gatesource voltage of the transistor, respectively. tox is the oxide thickness, E1 is a constant equal to 0.8 V/nm [45], and t is the total time. Moreover, it is shown that HCI effect depends on the temperature [5, 72]. Therefore, the HCI model of Eq. (13.2.24) is modified as follows: Vth = AHCI × SW × f × e

−Ea kT

×e

Eox E1

× t 0.5

(13.2.26)

where k is the Boltzmann constant and Ea the activation energy for the charge injection into the gate oxide.

13.2.3 Coupling Models for BTI and HCI Degradations NBTI and HCI degradation are usually assessed independently one from the other. Their respective degradations are assumed to be additive. However, in [6] it is shown that these two phenomena are interacting and their contributions should be

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293

correlated. In fact, as the degradation rate is depending on the damage provoked by carriers, defects created during the two mechanisms are the same, only their respective localizations differ. It is shown through experiments, that the average total (BTI+HCI) degradation is largely overestimated up to a factor of 2 if a simple additive model is used. Thus correlated BTI and HCI models should be used during the evaluation of the degradation for a better accuracy.

13.2.4 Random Telegraph Noise (RTN) Random telegraph noise (RTN) is an important source of runtime variation which is manifested as a low-frequency noise phenomenon and causes a temporal and random fluctuation of transistor electrical parameters, e.g. threshold voltage and drain current [9, 42]. It is shown that RTN is a serious reliability issue for image sensors [65], SRAM [71], and flash memories [18]. Variation due to RTN is increasing with the device down-scaling and its effect exceeds process variation in 22 nm technology nodes [59, 61]. Therefore, RTN recently has become a reliability issue also for logic circuits specially for the ones performing under low supply voltage/low power applications [29, 41]. RTN is caused by the stochastic capture/trapping and emission/detrapping of mobile charged carriers into gate dielectric and therefore it shares some common mechanisms with BTI [20, 37, 42]. RTN mechanism and its effect on threshold voltage of transistor are shown in Fig. 13.11. A carrier in the channel might be Fig. 13.11 (a) Capture and emission of mobile carriers and (b) threshold voltage fluctuation due to RTN

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13 Introduction

captured by a trap in the oxide which leads to an increase in the threshold voltage value of the transistor. The captured carrier will be emitted back after a period of the time and thus the threshold voltage value decreases towards its original value. The capture/emission is a stochastic process and can be described by a two-state Markov chain [9, 30]. The power spectral density of the individual capture/emission process is Lorentzian power spectrum (slope = 1/f 2 ), however, the overall RTN effect is the superposition of many capture/emission events which leads to a 1/f noise in the frequency domain [7, 42].

13.2.4.1

RTN Model

RTN has a stochastic behavior and it is shown that its effect on the circuit leads to a long tail delay distribution [9]. Therefore, it is important to characterize and model the statistical behavior of RTN. There have been many different models proposed in literature, however, here we briefly describe a compact statistical model of the effect of RTN on the threshold voltage of transistor proposed in [46]. In this model, the statistics of number of traps (NT ) and the impact of each single trap on the threshold ST ) are modeled separately. Then, these two models are voltage of transistor (Vth combined to obtain a complex model of overall impact of RTN on the threshold voltage of transistor. This model is described in more details in the following. Number of Traps (NT ) It is shown that the number of traps in the transistor follows a Poisson probability distribution [46]: fT (NT ; λ) =

λNT e−λ NT !

(13.2.27)

where λ is the average number of traps which is a strong function of transistor dimensions and obtained from experimental measurements. ST ) Single-trap effect on the Single-Trap Effect on Threshold Voltage (Vth ST threshold voltage (Vth ) has a long tail distribution and therefore it can be modeled by either an exponential distribution [21, 57] or a log-normal distribution [46, 60]. According to [46], a log-normal distribution leads to a better fit to the measured data:

ST fl (Vth ; Vth0 , σl ) =

e

−

Vth0 = eμ

2 ST −ln V ln Vth th0 2 2σl

ST σl Vth

√

2π

(13.2.28) (13.2.29)

where σl is the log-normal shape parameter and λ is the mean of the distribution of ST ). ln(Vth

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295

Overall Effect of RTN on Threshold Voltage (Vth ) In order to obtain the overall ST have effect of RTN on threshold voltage (Vth ), the statistics of NT and Vth to be combined into one comprehensive statistical model. For this purpose, it is assumed that the effects of individual traps on threshold voltage are independent which means that a simple superposition can be used to obtain the overall effects of all traps. Using superposition, the probability distribution function (PDF) of a system with n traps can be expressed as  fl,n (Vth ; Vth0 , σl , n) =

∞ −∞

fl,n (Vth − u; Vth0 , σl , n − 1) × fl (u; Vth0 , σl )du (13.2.30)

Then Eq. (13.2.27) can be used to obtain the contribution of the system with n traps into the total RTN effect as an = P (NT = n) =

λn e−λ n!

(13.2.31)

Equations (13.2.30) and (13.2.31) can be combined to obtain the PDF of overall RTN effect as fc (Vth ; Vth0 , σl , λ) = a0 δ0 (Vth ) +

∞

ai fl,n (Vth ; Vth0 , σl , i)

(13.2.32)

i=1

and cumulative distribution function (CDF) of Vth can be expressed as 

Vth

Fc (Vth ; Vth0 , σl , λ) =

fc (x; Vth0 , σl , λ)dx

(13.2.33)

0

Concerning RTN, it is worth to note the following issues: • Physically based 3D TCAD combined with Monte Carlo statistical simulation together with detailed experimental measures and circuit simulation is the present method to better and accurately understand the mechanisms leading to device degradation and the impact on circuit and gates degradations • RTN is highly correlated with local process variation, such as the random dopant fluctuation (RDF), line edge roughness (LER), and metal gate granularity (MGG). Gerrer et al.[19] shows that the impact on Vth fluctuation is mostly due to RDF and MGG local variations. • BTI degradation and impact on Vth were compared with RTN impact and it was demonstrated a lack of correlation between these two effects [19]. • RTN has a serious impact on voltage sense amplifiers used for memory designs as the random fluctuation of PMOS drain currents can lead to read errors of stored data [39].

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• FDSOI technology, alternatively used for very advanced geometries, shows less local process random variation than bulk technologies, similar RTN-induced variations of current amplitudes and threshold voltages were found [75]. This suggests that in future process nodes operating at lower voltages, RTN will be a major reliability issue.

13.2.5 Time Dependent Dielectric Breakdown (TDDB) Time dependent dielectric breakdown (TDDB) is an important transistor reliability concern where the quality of gate oxide is degraded over time in presence of high electric fields and it can eventually leads to severe failure in the gate oxide of transistor and a huge leakage current. By technology down-scaling, the gate oxide is scaled down, however, the supply voltage does not scale with the same trend. Therefore, the electric field over gate oxide increases and TDDB becomes more of a concern [11]. Generally, there are two types of TDDB called soft breakdown (SBD) and hard breakdown (HBD) based on the severity of the problem. In the presence of high electric fields, the channel carriers are trapped inside the oxide dielectric. By increasing the number of traps, they may form a resistive conduction path from gate to channel. In the beginning, the device is still functional; however, this leads to variations in the characteristics of transistors such as threshold voltage and current which is called SBD. The increase in the number of traps will cause the conduction path to become longer which eventually could lead to a catastrophic failure called HBD. When HBD occurs, the device is not functional any more since a huge current is drawn from the gate to drain/source of the transistor. Figure 13.12 shows different phases of oxide breakdown and its impact on leakage path current of transistor [32]. The key factor of causing oxide degradation and eventually breakdown is trap generation. There are different models to explain the trap generation causing TDDB, and a correct model is still debatable [2]. Three general models which is well Fig. 13.12 Time dependent dielectric Breakdown (TTDB) phases [32]

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297

Fig. 13.13 Power-law SBD model: (a) voltage dependent current source and (b) voltage dependent resistance model [69]

discussed in literature are (1) anode hole injection (AHI) model known also as 1/E model [51], (2) thermo-chemical model known also as E model [43], and (3) anode hydrogen release (AHR) model [13].

13.2.5.1

SBD Model

As discussed before, due to SBD the leakage current of transistor increases which might impact the circuit characteristics such as delay and energy. By technology scaling, the electric field over gate oxide increases which makes the SBD more pronounced [11]. Therefore, it is very crucial to model the impact of SBD on the circuit characteristics. A very well-known model for SBD is voltage-dependent power-law gate oxide degradation model [69]. In this model, SBD-induced leakage current increase is modeled by a voltage dependent current source or a voltagedependent resistance between the gate and drain/source (see Fig. 13.13). The voltage-dependent resistance is obtained by the following equation [11]: RBD (V ) = V (1−p) /K

(13.2.34)

where p represents the level oxide degradation and K reflects size of breakdown spot. These two parameters increase over time since the oxide degradation level increases. Extracting the values of K and p is very complicated since the device behavior after SBD depends on many factors such as technology node, transistor type, oxide area, etc.

13.2.5.2

HBD Model

Since after HBD the device is not functional any more, HBD normally modeled with a statistical parameter called time-to-breakdown (tBD ). Generally, tBD is modeled either with Weibull distribution [2] or log-normal distribution [70]. Here, we briefly

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explain the Weibull distribution model. The cumulative distribution function of tBD can be described by:     t β F (t) = 1 − exp − η

(13.2.35)

where β is the shape factor of the distribution and η is the scale factor. Normally, Eq. (13.2.35) is rewritten as: ln [−ln(1 − F (t))] = βln(t) − βln(η)

(13.2.36)

In which ln [−ln(1 − F (t))] can be depicted as a linear function of ln(t) with a slope of β and a y-intercept equal to −βln(η).

13.3 Chapter Outlook in Part II The remaining chapters in this part of the book focus on various modeling and mitigation techniques for transistor aging at various levels of abstraction. While transistor aging is affected by technology, design and runtime (workload) parameters, the modeling and mitigation techniques addressing these effects can be done at various abstraction levels. In addition, for more comprehensive and costeffective modeling and mitigation, a cross-layer approach is also necessary. Chapter 14 presents a framework to comprehensively investigate the combined effect of stochastic NBTI and process variation on the performance of the VLSI design at circuit level, by abstracting atomistic NBTI models (for the stochastic behavior) to the circuit timing analysis flow. Our simulation results show that the stochastic behavior of NBTI can result in a significant increase of the guard-band. Moreover, our analysis reveals that stochastic NBTI and process variation should be considered together, otherwise it can lead to a major overestimation of the mean value of the delay degradation. Chapter 15 proposes a technique to optimize the standard cells considering both NBTI and PBTI effects. The main idea is to optimize the library cells in order to balance their rise and fall delays at the expected lifetime rather than the design time. In our technique, we consider uneven BTI-induced degradation by taking the duty cycle of each transistor into account. This is achieved by replicating and redesigning library cells for different ranges of input signal probabilities. In order to keep a reasonable trade-off between library size and lifetime improvement (i.e., BTI-induced timing margin reduction), we investigate the optimal sampling ranges for input signal probabilities. We also provide the flow for library extension as well as technology mapping to this aging-aware library. Chapter 16 presents a comparative analysis of the impact of process and runtime variations, including transistor aging, on the performance of flip-flops. Process and runtime variations affect the functionality of nanoscale VLSI designs which leads to

13.3 Chapter Outlook in Part II

299

reduced manufacturing yield and increased runtime failures. Our analysis shows that independent consideration of the effect of different sources of variations may result in significant inaccuracy compared to the combined effect analysis, and leads to sub-optimal designs. In particular, our analysis reveals that the particular FF designs which are resilient to the process variation are not the best choices for the combined effects of process and runtime variations. Furthermore, a framework is developed to design and optimize resilient flip-flops against process and runtime variations, in particular transistor aging. Chapter 17 presents a method to mitigate the BTI-induced aging of flip-flops via transistor sizing optimization. BTI affects both timing and functionality of flipflops. In a typical processor, a considerable portion of flip-flops always operate under severe BTI stress independent of the running workload. This leads to a serious timing degradation in these flip-flops, and to avoid timing violations in field, they mandate a large aging guardband (timing margin). The optimized flip-flops are more resilient against BTI stress compared to the original ones. The imposed overall leakage is negligible, and the area of the optimized flip-flops is similar to the original ones in order to facilitate the replacement of the original flip-flops with optimized alternatives in the circuit layout. Simulation results show that incorporating the optimized flip-flops in a processor can reduce the timing guardband of the processor by significantly compared to the original design, which translates into prolonged lifetime and more reliability. Chapter 18 presents a runtime monitoring method to raise a flag when a timingcritical flip-flop experiences severe static-BTI stress. The worst-case effects of BTI occur during specific workload phases in which flip-flops on a critical path do not switch their logic values for a long duration. These inactive flip-flops in the circuit experience accelerated workload-dependent static-BTI stress. The aging effect of static BTI for a few hours has been shown to be equivalent to 1 year of aging due to dynamic BTI, which can eventually cause circuit failure. The techniques available to mitigate static-BTI stress during standby mode of circuits are pessimistic, thereby limiting the performance of the circuit. To address this problem, the proposed technique selects a small representative set of flip-flops offline based on workloadaware correlation analysis, and these selected flip-flops are monitored online for static aging phases. A low-overhead mitigated scheme is also presented to relax critical flip-flops by executing a software subroutine that is designed to exercise critical flip-flops. Chapter 19 presents a novel No Operation instruction assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. As a major source of transistor aging in scaled CMOS, NBTI is strongly dependent on the input vectors. Moreover, a considerable fraction of execution time of an application is spent to execute No Operation instructions. Therefore, NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as No Operation. On top of this, we also proposed two methods, software-based and hardware-based, to replace the original No Operation with this maximum aging reduction No Operation.

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Chapter 20 presents “ExtraTime”, which is novel microarchitectural aging analysis framework. With shrinking feature sizes, transistor aging due to NBTI and HCI becomes a major reliability challenge for microprocessors. These processes lead to increased gate delays, more failures during runtime and eventually reduced operational lifetime. Currently, to ensure correct functionality for a certain operational lifetime, additional timing margins are added to the design. However, this approach implies a significant performance loss and may fail to meet reliability requirements. Therefore, aging-aware microarchitecture design is inevitable. This proposed framework can be used in early design phases when detailed transistorlevel information is not yet available to model, analyze, and predict performance, power, and aging. Furthermore, we show a comprehensive investigation using ExtraTime of various clock and power gating strategies as well as aging-aware instruction scheduling policies as a case study to show the impact of the architecture on aging. Chapter 21 presents an aging mitigation technique at the microarchitecture level based on the analysis framework which was presented in Chap. 20. The main idea is to distribute the load and stress on various functional units based on their timing slack and aging criticality. To achieve this, the instructions are classified depending on their worst-case delay into critical (i.e. the instructions whose delay is close to the cycle boundary) and non-critical instructions (i.e. those instruction with larger timing slack). Each of these classes uses its own (specialized) functional unit(s). It has been shown that this non-uniform load distribution is far more effective in aging mitigation than conventional wear leveling.

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Chapter 14

Aging-Aware Timing Analysis

14.1 Introduction In previous technology nodes, the NBTI effect on transistors was fairly deterministic for a particular workload condition (e.g. temperature and stress), and it was effectively mitigated by adding timing guardband to the design by “predicting” worst-case workload and stress conditions in the field [13]. However, by further down-scaling of transistor dimensions into deca-nanometer range, the number of defects per device decreases leading to a drastic increase in the time dependent variability of NBTI [15]. As a result, the delay degradation due to this nondeterministic NBTI effect becomes also stochastic, and the timing guardband needs to be obtained according to the far tail of the distribution (e.g. μ + 3σ ) to guarantee reliable operation in the field. Accurate stochastic timing analysis of the circuit becomes very important in this case since over and under margining can lead to significant performance or yield loss (timing failure), respectively. The matter is aggravated when it is combined with process variation, adding another degree of non-determinism. Thus, it is important to analyze the stochastic behavior of NBTI combined with process variation affecting the VLSI circuits performance. In this chapter, we present a framework for analyzing the combined effect of stochastic NBTI together with process variation during circuit timing analysis. Using the framework, a comprehensive analysis is performed to obtain the contribution of process variation, stochastic NBTI, and their combined effect on the total variation of the circuit delay during its operational lifetime. The proposed timing analysis is performed on a set of ISCAS85 benchmark circuits (http://web.eecs.umich.edu/~jhayes/iscas.restore/) with a 7 nm FinFET technology library [12]. The simulation results show: • Stochastic NBTI effect leads to an asymmetric (non-normal) distribution of circuit delay degradation.

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_14

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• The effect of process variation on the mean of the delay degradation is less than that of stochastic NBTI while it leads to more variability on the distribution. • The stochastic behavior of NBTI can result in a significant increase of the guardband compared to a deterministic case. • Considering these sources of variation separately leads to a considerable overestimation of the delay degradation mean value. In this chapter, NBTI is only considered since for deeply scaled FinFET devices NBTI is expected to dominate over PBTI. For recent FinFET technologies metal gate work function tuning and using a fully depleted body has successfully reduced the electric field in the high-k layer and has been shown to be an effective mitigation approach for PBTI. Nonetheless, similar models and statistical flow can be leveraged to obtain the effect of stochastic PBTI as well.

14.2 Related Work There have been some studies to analyze the stochastic behavior of NBTI effect. In [10], the authors proposed a statistical analysis framework to obtain the combined effect of process variation and NBTI on the delay distribution. For this purpose, the mean and standard deviation of the gate delays are propagated to obtain the mean and standard deviation of the circuit delay as a normal distribution. However, we will later show that the distribution of circuit delay considering the combined effect of NBTI and process variation is not a normal distribution. In their framework, NBTI is considered as a random process because the NBTI effect is a function of the transistor initial threshold voltage as well as oxide thickness [2], and these two process parameters have variation due to process variation. In order to model this, they used a deterministic NBTI model proposed in [2] and by considering stochastic behavior of the oxide thickness and the threshold voltage, the NBTI effect can also be expressed as a stochastic parameter. However, it is shown that the NBTI effect has an intrinsic variation [15]. This means that even two identical transistors with the same oxide thickness, initial threshold voltage, and stress condition may have different NBTI effect. This intrinsic variability of NBTI which is not considered in [10] can be modeled by statistical atomistic models. Since the existing atomistic models are complex, they can be used at device level [3, 8, 11] up to gate/cell level [6] including memory cells such as SRAM [15]. However, implementing the stochastic behavior of NBTI into circuit level timing analysis poses severe restrictions on circuit size and/or simulation time [15]. Moreover, as shown later in the results section, normal distribution models for stochastic NBTI (as an attempt to abstract out atomistic models) are fairly inaccurate. There have been few studies of stochastic NBTI at circuit level and due to the aforementioned challenges at this level, they either consider a simple chain of inverters [5] or only a single critical path [4]. However, the analysis of single path does not properly reflect the statistical NBTI-induced distribution of

14.3 Circuit Level Simulation Flow

307

circuit delay since the interaction of several critical paths in well-balanced circuits are neglected. Authors in [9] studied NBTI-induced performance degradation of 32bit adders. However, the analysis is only performed at the +3σ corner. Moreover, none of the existing work considers the combined effect of process variation and stochastic NBTI, as our analysis shows they cannot be considered separately.

14.3 Circuit Level Simulation Flow Figure 14.1 shows the flow of the proposed stochastic NBTI and process variationaware timing analysis. As shown in this figure, the first step is to characterize the standard cells for different values of their internal transistor threshold voltage shift. Then, the corresponding delay/transition time look-up tables (LUTs) are stored in an extended library. The extended library is used later by timing analysis tool to obtain the timing information of the gates. Besides, a logic simulator is used to calculate the internal signal probabilities (the probability that the signal is equal to binary value of “one”) and the NBTI parameters of transistors accordingly. Finally, a Monte Carlo (MC) simulation is performed to obtain the distribution of NBTI and process variation-induced delay degradation. For this purpose, for each MC iteration, V th samples are calculated for transistors according to their NBTImodel parameters. Then, the gates timing information is updated in the library, and a static timing analysis (STA) is performed to calculate the circuit delay. Fig. 14.1 Flow of proposed stochastic NBTI and process variation-aware timing analysis framework [7]

308

14 Aging-Aware Timing Analysis

14.3.1 Library Cell Characterization In the standard cell library, the timing information of a cell (e.g. rise/fall delays and transition times) is stored for different input transition times and load capacitances as 2-dimensional LUTs for the nominal threshold voltage value (V th). These LUTs are used in STA tools to obtain the circuit delay. However, the V th of the internal transistors of the cell may change due to process/runtime variations. In order to be capable of performing the STA considering process and runtime variations, we need to characterize the cells for different combination of V th of their transistors and store the timing information LUTs in an extended library. For example, instead of having only one LUT in the library for INVX1 cell, we will have different LUTs for different INVX1V thnV thp instances where V thn and V thp are the corresponding threshold voltage shift values of NMOS and PMOS transistors, respectively. However, it is not possible to characterize the cells for all combinations of V ths (the library size goes to infinity). Therefore, V ths range is discretized and the library is extended for different combination of V ths according to the discretization. In this chapter, the minimum, maximum, and discretization step values of V th are −60 mV, 120 mV, and 10 mV, respectively.

14.3.2 Stochastic NBTI Parameter Extraction For a given circuit netlist, a logic simulator is used to obtain the internal node signal probabilities. Next, the duty cycle of all internal transistors is calculated according to the internal node signal probabilities. Then, for each transistor, based on its duty cycle and feature size, the parameters of the atomistic NBTI model (η and n) are obtained using the model introduced in Sect. 13.2.1.2. These parameters are used in the MC simulation to obtain the samples of NBTI-induced V th for each iteration.

14.3.3 Monte Carlo Simulation 14.3.3.1

Vth Sampling

The first step of the MC simulation is to obtain samples for V th of all internal transistors due to the stochastic NBTI effect and process variation. For sampling the NBTI-induced V th, for each iteration (i) and for each transistor Tj , we get a sample (ni,Tj ) from a Poisson distribution with a mean of NTj , where NTj is the mean number of transistor defects obtained from Eqs. (13.2.17) and (13.2.18). This sample (ni,Tj ) represents the number of defects in the transistor Tj for iteration i of MC. Then, the total NBTI-induced V th is obtained by:

14.4 Results and Discussion

309 ni,Tj

V thNBTI i,Tj

=



V thk

(14.3.1)

k=1

where V thk is the threshold voltage shift for each defect obtained by sampling from an exponential distribution with a mean of η (the mean threshold voltage shift due to each defect) obtained from Eqs. (13.2.21) and (13.2.22). Afterwards, the process variation-induced threshold voltage shift sample (V thPV i,Tj ) is obtained from a normal distribution with a mean equal zero and standard deviation obtained from Pelgrom’s mismatch law, and the total threshold voltage shift of each iteration for each transistor is calculated with: PV V thi,Tj = V thNBTI i,Tj + V thi,Tj

(14.3.2)

Here a simple superposition is performed to obtain the total threshold voltage shift. This is due to the fact that according to [1, 5], there is no correlation between NBTIinduced threshold voltage shift and process variation.

14.3.3.2

Stochastic NBTI and Process Variation Aware STA

After obtaining the V ths of all transistors for each iteration, the delay and transition time LUTs of each gate in the netlist are calculated by interpolating the LUTs of the extended library according to V th values and a new library is built according to these LUTs. Finally, a STA tool is used to obtain the circuit delay using the updated timing LUTs of the gates. By performing such a STA during each iteration of MC, the delay degradation distribution of the circuit is calculated.

14.4 Results and Discussion 14.4.1 Simulation Setup, Terms, and Definitions In this section the results of the proposed stochastic NBTI and process variation aware STA are presented for ISCAS85 benchmark circuits (http://web.eecs.umich. edu/~jhayes/iscas.restore/) as well as three inverter chains with 1 (chain1), 9 (chain9), and 39 (chain39) inverters, respectively. A 7 nm FinFET technology node library [12] is used. Cadence Altos Liberate (http://www.altos-da.com/) is exploited for characterization to obtain the extended library, and Synopsys PrimeTime (http:// www.synopsys.com) is used for STA. All the results are presented as normalized D in percentage calculated from:

310

14 Aging-Aware Timing Analysis

normalized D =

D − D0 D0

(14.4.1)

where D is the delay of the circuit considering process/aging variations and D0 is the nominal delay at time zero. There are some terms used later in the results discussion which are defined as follows: • Number of critical paths: it shows the number of critical paths contributing in the post-aging delay distribution of the circuit. • Skewness: it is a measure of the asymmetry of the probability distribution of a random variable. It is equal to zero for a random variable with a normal distribution. • Kurtosis: it is a measure of the tails weight of a distribution. Kurtosis value of a variable with normal distribution is equal to 3. Higher kurtosis means that the weight of infrequent extreme deviations on the variance is more compared to that of frequent modestly sized deviations.

14.4.2 Atomistic NBTI Model vs Equivalent Normal NBTI Model Figure 14.2a shows the probability density function (PDF) of NBTI-induced D distribution of the c432 benchmark circuit for two different stochastic NBTI models: (1) atomistic NBTI (ANBTI) model and (2) equivalent normal NBTI (NNBTI) model using mean and standard deviation according to Eqs. (13.2.12) and (13.2.13), respectively. As shown in this figure, the shapes of the distributions are different specially in the tails. This is also shown in QQ-plots of the D distribution (see Fig. 14.2b, c). According to these figures, the NBTI-induced D distribution using the atomistic model is not a normal distribution specially in the tails while a normal model for NBTI leads to a distribution of delay degradation which is very similar to a normal distribution. Table 14.1 also summarizes the information of D distribution for these two models of stochastic NBTI behavior. According to the table, the mean and standard deviation of the D distributions are almost similar for these two models, however, the difference between the skewness metric is significant, for instance as large as 3× for c880 benchmark circuit. Moreover, according to the table, the required timing margin for guard-banding is 30% larger on average for the case of stochastic NBTI (μ + 3σ of delay degradation) compared to that of a deterministic analysis (μ of delay degradation) which shows the importance of the stochastic NBTI analysis at circuit level.

14.4 Results and Discussion

311

Fig. 14.2 (a) Probability density function of NBTI-induced D for atomistic NBTI (ANBTI) and normal NBTI (NNBTI). (b) QQ-plot of atomistic NBTI (ANBTI) [7]. (c) QQ-plot of normal NBTI (NNBTI) [7]

14.4.3 Effect of Process Variation vs Stochastic NBTI Figure 14.3 shows the PDF of the D distribution for three cases considering (1) only NBTI, (2) only process variation, and (3) combined effect, for c880 and c1355 benchmark circuits. As shown in this figure, the mean of D is larger for NBTI effect while the distribution of process variation is wider (more variability due to process variation). Moreover, the mean and standard deviation of combined effect is larger than those of both cases when they are considered separately.

6

24

c2670 (balanced)

185

c1908 (balanced)

c2670 (unbalanced)

4

35

c499

c1908 (unbalance)

15

c432

2

1

c17

54

1

chain39

c1355

1

chain9

c880

1

NNBTI

31

6

234

4

84

3

35

17

1

1

1

1

ANBTI

5

94

25

3

1

1

1

7

610

5

103

30

3

1

1

1

ANBTI+PV

74

9

84

9

1065 1106

7

635

PV

# of critical paths

chain1

Benchmark ANBTI

PV

ANBTI+PV

4.63

3.71

3.38 3.31

4.26 4.15

3.61 3.52

3.38 3.28

3.8

4.16 4.07

3.57 3.49

3.88 3.79

2.82 2.71

4.7

4.67 4.6

1.52 4.21

1.04 4.45

2.01 4.59

0.67 3.35

1.69 4.5

0.72 4.13

1.32 4.09

1.26 4.48

1.73 3.88

0.28 4.15

0.27 4.15

4.32 4.23 −0.21 3.56

NNBTI

Mean PV

ANBTI+PV

1.75 3.86 4.23

ANBTI

2.82

0.32 0.68 0.73

0.32 0.58 0.62

0.37 0.4

0.72 0.74

0.39 0.42 0.94 1.04

0.28 0.31 0.56 0.57

0.3

0.3

0.36 0.37 0.74 0.8

0.34 0.36 0.66 0.69

0.36 0.41 0.79 0.86

1.27 1.33 2.6

0.43 0.44 0.73 0.82

0.87 0.89 1.51 1.7

1.7

NNBTI

Standard deviation ANBTI

PV

ANBTI+PV

ANBTI

PV

ANBTI+PV

0.25 0.36

0.05

0.3

0.38 0.28

0.11 0.26 0.11

0.36 0.43 0.23

0.11 0.2

0.25 0.26 0.27

0.07 0.21 0.07

0.2

0.11 0.33 0.2

0.3

0.09

0.22

0.02

0.14

0.07

0.32

0.13

2.94

3.09 2.96 3.09 3.15 3.34 3.13 3.14

2.9

3.25 3.38 3.13 3.05

2.94 2.99 2.98 3.05

3.02 3.04 3.16 3.08

2.97 3.24 3.08 2.98

2.91 3.06 3.29 3

3.02 3.25 3.1

2.69 3.42 2.83 2.86

3.07 2.98 2.89 2.93

0.24 0.64 0.21

0.12

2.96 3.04 3.09 2.88

0

0.27 0.09 −0.03

2.72 3.41 2.44 2.8

NNBTI

Kurtosis

−0.03 0.14 0.01 −0.02

0.04 0.51 0.14 −0.09

NNBTI

Skewness

Table 14.1 Information of the normalized D distribution for four different cases: (1) normal NBTI (NNBTI), (2) atomistic NBTI (ANBTI), (3) process variation (PV), and (4) combined effect of process variation and NBTI (ANBTI+PV) [7]

312 14 Aging-Aware Timing Analysis

14.4 Results and Discussion

313

0.25

0.25

0.15

0.15

0.1

0.1

0.05

0.05

ANBTI PV 0.2 ANBTI+PV

ANBTI PV 0.2 ANBTI+PV

0

0 -4

-2

0

2

4

6

8

-4

-2

0

2

ΔD (%)

ΔD (%)

(a)

(b)

4

6

8

Fig. 14.3 D distribution of (a) c880 and (b) c1355 considering atomistic NBTI (ANBTI), PV and combined effects (ANBTI+PV) [7]

Since the threshold voltage shift due to NBTI and process variation for transistors are uncorrelated [1, 5], the mean and sigma of the overall effect on the threshold voltage shift of the transistor can be estimated by the following equations: μANBTI+PV = μANBTI + μPV 2 2 2 σANBTI+PV = σANBTI + σPV

If process variation and stochastic NBTI are considered separately, the same set of equations shall be used to obtain the mean and sigma of the D distribution at circuit level. However, according to the results of the ISCAS85 benchmark circuits (see Table 14.1), the following inequalities are valid at the circuit level when the combined effect is considered: μPV < μANBTI < μANBTI+PV < μANBTI + μPV 2 2 2 σANBTI < σPV < σANBTI+PV 2 2 2 σANBTI+PV = σANBTI + σPV

which means that considering these two sources of variation separately always leads to an overestimation of the mean value of the D distribution (17% on average) and an error (for some circuits it leads to an underestimation and for others an overestimation) in the estimation of standard deviation (4% error in average).

14 Aging-Aware Timing Analysis

Margin Estimation Error (%)

314

16 14 12 10 8 6 4 2 0

c43 c49 c88 c13 c19 c26 ave 2 9 0 55 08 70 rag e Benchmark Circuit

Fig. 14.4 Timing margin error due to separately consideration of process variation and stochastic NBTI compared to combined effect [7]

Fig. 14.5 Violin plot of NBTI and process variation-inducedD [7]

Figure 14.4 shows the error in the timing margin estimation if these sources of variation are considered separately and the error is calculated according to the following equations: , 2 2 ) + σPV marginseparated = μANBTI + μPV + 3 (σANBTI margincombined = μANBTI+PV + 3σANBTI+PV Error =

marginseparated − margincombined margincombined

According to Fig. 14.4, considering these two sources of variation separately lead to an overestimation of the timing margin for guard-banding by 13% on average. Figure 14.5 shows the violin plot of the D distributions for different benchmark circuits. According to this figure, NBTI and process variation lead to different

14.4 Results and Discussion

315

amount of variation on the circuit delay for different benchmark circuits. The combined effect of NBTI and process variation can lead to a worst-case delay degradation ranging between 6–8%.

14.4.4 Effect of Balanced Paths in Complex Circuits According to Table 14.1, when the number of cells in the inverter chain increases, the D distribution becomes closer to a normal distribution (see skewness and Kurtosis of chain1, chain9, and chain39 in the table). In other words, for the longer paths, D distribution becomes closer to a normal distribution which is consistent with central limit theorem (see Fig. 14.6a–c).

Fig. 14.6 QQ-plot of different circuits with different number of levels and critical paths [7]

316

14 Aging-Aware Timing Analysis

However, more than one path contribute to the D distribution of the circuit (see # of CP in the table) in a typical circuit. Therefore, reporting only the D distribution of one path [4] may reduce the accuracy of the timing analysis. This is because the delay of the circuit is obtained by a maximum operation across the delay of all the critical paths. Since the maximum operation is not a linear function, the maximum of two normal distributions is not necessarily a normal distribution. According to the table, for more balanced circuits (the ones with more critical paths) the skewness of NBTI-PV-induced D distribution is larger (see Fig. 14.6d). To show the effect of balanced paths more clearly, we synthesized c1908 and c2670 circuits in two different ways (1) unbalanced, by putting a loose timing constraint for synthesis and (2) balanced, by putting a very tight timing constraint for synthesis. According to the table, the skewness of the D distribution in balanced circuit is 10× and 3× larger than that of unbalanced one for c1908 and c2670, respectively.

14.4.5 Effect of Workload Figure 14.7 illustrates the effect of workload on the amount of ANBTI-induced delay degradation. For this purpose, the signal probabilities of all internal inputs are swept from 0.0 to 1.0 with a step of 0.25. Figure 14.7a shows the results for a simple inverter. As shown in this figure, by increasing the signal probability (decreasing equivalent duty cycle), the mean and standard deviation of delay distribution decrease. This is consistent with Fig. 13.8 in which the number of traps increases as the duty cycle increases. However, as shown in Fig. 14.7b, the workload has negligible effect on the distribution of ANBTI-induced delay degradation of a chain of inverter with 10 inverters in a row. This is due to the structure of inverter chain circuit in which the average duty cycle of internal transistor is approximately equal to 0.5 for all values of input signal probability and as a result, the input signal probability has negligible effect on the distribution delay degradation. Figure 14.7c, d shows the results for two different benchmark circuits of c880 (with a balanced structure) and c499 (with an unbalanced structure). According to these figures, the effect of input signal probability on the delay degradation distribution is a strong function of circuit structure. To further investigate the effect of the circuit structure, the effect of the workload on the amount of ANBTI-induced delay degradation for two versions (balanced and unbalanced) of a similar benchmark circuit (c2670) is obtained and the results are illustrated in Fig. 14.8. According to the figure, the sensitivity of the NBTI-induced delay degradation to the input signal probability for the unbalanced version of the circuit is larger compared to that of balanced one. In order to explain this observation, first, we obtained the signal probability distribution of the internal nodes, placed on the most critical paths, for these two versions of the circuit. The results are illustrated in Fig. 14.9. According to the figure, the mean and the shape of the signal probability distributions are very similar for both versions of the circuit and hence the difference between the sensitivity of

14.4 Results and Discussion

(a)

(c)

317

(b)

(d)

Fig. 14.7 Effect of workload on ANBTI-induced D distribution of the circuit [7]. (a) One inverter. (b) Chain of 10 inverters. (c) c880. (d) c499

(a)

(b)

Fig. 14.8 Effect of workload on ANBTI-induced D distribution of c2670 circuit for (a) unbalanced and (b) balanced versions [7]

318

14 Aging-Aware Timing Analysis

(a)

(b)

Fig. 14.9 Effect of workload on signal probability distribution of the nodes on critical paths for c2670 circuit for (a) unbalanced and (b) balanced versions [7]

(a)

(b)

Fig. 14.10 Number of critical paths for c2670 circuit for (a) unbalanced and (b) balanced versions [7]

the NBTI-induced delay degradation to the input signal probability is not related to this factor. We also obtained the number of “aging” critical paths, contributing in the postaging delay distribution of the circuit. As depicted in Fig. 14.10, the number of aging critical paths is different for various workloads (input signal probabilities). Moreover, the number of aging critical paths is much larger in balanced version of the circuit compared to that of unbalanced one. Since the delay of the circuit is obtained by a maximum operation across the delay of all the aging critical paths, the circuit delay distribution is affected by the number of aging critical paths. Figure 14.11 shows the dependency of the mean value of the maximum of n random n variables (E[max Vi ]) for different values of n. Based on the figure, by increasing i=1

n the mean value of the maximum increases, however, the mean value saturates for large amount of variables (n > 10). Therefore, for balanced version of the circuit, the

14.4 Results and Discussion

319

Fig. 14.11 The mean value of the maximum of n random n variables (E[max Vi ]). The i=1

random variables have a mean value of 1 and standard deviation of 0.1. The values of standard deviation and mean are set according to the maximum NBTI-induced delay degradation of a single path which is less than 10% [7]

Table 14.2 Runtime of proposed variation-aware timing analysis [7]

Benchmark c17 c432 c499 c880 c1355 c1908 c2670

# of gates 6 220 539 566 585 610 1101

Runtime (s) 3450 15,508 32,600 29,240 38,202 34,952 57,192

sensitivity of the post-aging delay distribution to the number of aging critical paths, and hence to input signal probability, is much less compared to that of unbalanced one. It should be noted that, the number of near critical paths (the paths with slack less than 5% of the circuit delay) at design time of the balanced version of c2670 is more than 800, but since the NBTI effect asymmetrically impacts the circuit, the number of post-aging critical paths is reduced to less than 30 paths for this version of the circuit. For the unbalanced version, these numbers are 56 and 6, respectively. This means that even for very large circuits, if the design of the circuit is not wellbalanced, the number of post-aging critical path might become very small, leading to a high sensitivity of NBTI-induced delay degradation to the executed workload.

14.4.6 Runtime of the Proposed Variation-Aware Timing Analysis Table 14.2 shows the runtime of the proposed variation-aware timing analysis for 10,000 MC samples. As shown in this table, the runtime of the technique increases linearly with the size of the circuit. It should be noted that this framework is not optimized for runtime but it enables us to perform a comprehensive analysis of stochastic NBTI and process variation at circuit level with a high accuracy

320

14 Aging-Aware Timing Analysis

by abstracting detailed device-level atomistic models to logic-level circuit timing analysis. The results of this analysis can be used as a baseline for faster (but less accurate) timing analysis at higher level of abstraction or better scalability for larger circuits. Moreover, there are multiple ways to improve the existing flow. One way is to decrease the number of MC iterations by leveraging smart approaches such as importance sampling or quasi MC simulation [14]. The other opportunity is to decrease the runtime of each MC simulation (iteration). For this purpose, the actual gate delay can be updated for each MC iteration according to the values of V th samples (e.g., using standard delay file (SDF)) instead of updating the entire gates delay LUTs and performing STA for each case.

14.5 Summary By further down-scaling, the NBTI effect becomes stochastic which has a significant impact on guard-banding for aging. This chapter presented a framework to analyze the effect process variation and stochastic NBTI on the timing of logic-level circuits. Simulation results show that the stochastic behavior of NBTI can result in a significant increase in the guardband up to 30% compared to the deterministic case. Moreover, results reveal that the effect of process variation on the mean of the delay degradation is less than that of stochastic NBTI while it leads to a more variability on the distribution. In general, the analysis reveals that there is a need to consider the stochasticity as a part of the standard timing analysis flow and the stochastic nature of NBTI mandates a more complex guard-banding in contrast to existing static guard-banding solutions.

References 1. D. Angot, V. Huard, L. Rahhal, A. Cros, X. Federspiel, A. Bajolet, Y. Carminati, M. Saliva, E. Pion, F. Cacho et al., BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset, in Proceedings of the IEEE International Electron Devices Meeting (IEDM), (IEEE, Piscataway, 2013), pp. 15–4 2. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, Predictive modeling of the NBTI effect for reliable design, in IEEE Custom Integrated Circuits Conference (IEEE, Piscataway, 2006), pp. 189–192 3. J. Bhaskarr Velamala, K.B. Sutaria, H. Shimizu, H. Awano, T. Sato, G. Wirth, Y. Cao, Compact modeling of statistical BTI under trapping/detrapping. IEEE Trans. Electron Devices 60(11), 3645–3654 (2013) 4. V.V. Camargo, B. Kaczer, G. Wirth, T. Grasser, G. Groeseneken, Use of SSTA tools for evaluating BTI impact on combinational circuits. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(2), 280–285 (2014) 5. B. Kaczer, S. Mahato, V. V. de Almeida Camargo, M. Toledano-Luque, P.J. Roussel, T. Grasser, F. Catthoor, P. Dobrovolny, P. Zuber, G. Wirth et al., Atomistic approach to variability of bias-

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temperature instability in circuit simulations, in 2011 IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2011), pp. XT–3 6. S. Khan, S. Hamdioui, H. Kukner, P. Raghavan, F. Catthoor, BTI impact on logical gates in nano-scale CMOS technology, in International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) (IEEE, Piscataway, 2012) 7. S. Kiamehr, P. Weckx, M. Tahoori, B. Kaczer, H. Kukner, P. Raghavan, G. Groeseneken, F. Catthoor, The impact of process variation and stochastic aging in nanoscale VLSI, in 2016 IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2016), pp. CR–1 8. H. Kukner, S. Khan, P. Weckx, P. Raghavan, S. Hamdioui, B. Kaczer, F. Catthoor, L. Van der Perre, R. Lauwereins, G. Groeseneken, Comparison of reaction-diffusion and atomistic trapbased BTI models for logic gates. IEEE Trans. Device Mater. Reliab. 14(1), 182–193 (2014) 9. H. Kukner, P. Weckx, S. Morrison, P. Raghavan, B. Kaczer, F. Catthoor, L.V.d. Perre, R. Lauwereins, G. Groeseneken, NBTI aging on 32-bit adders in the downscaling planar FET technology nodes, in 2014 17th Euromicro Conference on Digital System Design (DSD) (IEEE, Piscataway, 2014), pp. 98–107 10. Y. Lu, L. Shang, H. Zhou, H. Zhu, F. Yang, X. Zeng, Statistical reliability analysis under process variation and aging effects, in Proceedings of the 46th Annual Design Automation Conference (ACM, New York, 2009), pp. 514–519 11. T. Naphade, N. Goel, P. Nair, S. Mahapatra, Investigation of stochastic implementation of reaction diffusion (RD) models for NBTI related interface trap generation, in 2013 IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2013), pp. XT-5 12. Predictive Technology Model. http://www.eas.asu.edu/~ptm/ 13. V. Reddy, J.M. Carulli, A.T. Krishnan, W. Bosch, B. Burgess, Impact of negative bias temperature instability on product parametric drift, in International Test Conference (ITC) (IEEE, Piscataway, 2004), pp. 148–155 14. V. Veetil, D. Sylvester, D. Blaauw, Efficient Monte Carlo based incremental statistical timing analysis, in 45th ACM/IEEE Design Automation Conference, DAC 2008 (IEEE, Piscataway, 2008), pp. 676–681 15. P. Weckx, B. Kaczer, M. Toledano-Luque, T. Grasser, P.J. Roussel, H. Kukner, P. Raghavan, F. Catthoor, G. Groeseneken, Defect-based methodology for workload-dependent circuit lifetime projections-application to SRAM, in 2013 IEEE International Reliability Physics Symposium (IRPS) (IEEE, Piscataway, 2013), p. 3A-4

Chapter 15

Aging-Aware Standard Cell Library Optimization Methods

15.1 Introduction While the focus of the previous chapters was the modeling of reliability, the focus of the following chapters is to design reliable cells and circuits in order to mitigate the aging effect. Typically, standard cells in the library are optimized according to the design time delay, however, due to the asymmetric effect of BTI, the rise and fall delays might become significantly imbalanced over the lifetime. In this chapter, a method is proposed to mitigate the BTI effect by balancing the rise and fall delays of the standard cells at the excepted lifetime. We find an optimal tradeoff between the increase in the size of the library and the lifetime improvement (timing margin reduction) by non-uniform extension of the library cells for various ranges of the input signal probabilities. The simulation results reveal that our technique can prolong the circuit lifetime by around 150% with a negligible area overhead. Moreover, we investigate the effect of different realistic workloads on the distribution of internal node signal probabilities. This is done to obtain the sensitivity of our static (design time) approach to different workloads during system lifetime. The results show that our proposed approach is still efficient if the workload changes during the runtime. The rest of the chapter is organized as follows. Related work is discussed in Sect. 15.2. The proposed BTI-aware cell sizing idea is explained in Sect. 15.3. Afterwards, the proposed methodology is described in Sect. 15.4. Simulation results are presented in Sect. 15.5, and finally, Sect. 15.6 concludes the chapter.

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_15

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15.2 Related Work In order to mitigate BTI, there are two main categories of techniques: (1) sense and adapt (at runtime) and (2) model, predict, and margin (at design time). In the former approach, the circuit behavior has to be monitored at runtime and according to the feedback of monitors an adaptive technique is applied to compensate the degradation due to aging. Body biasing [15, 16, 21], clock and power gating [6, 7, 19], and dynamic voltage and frequency scaling (DVFS) [2, 28] are some of the well-known methods in this category [10]. In the later approach, the proper operation of the circuit at the expected lifetime is guaranteed by a guard-banding method [23], i.e. adding additional timing margin. For effective guard-banding, the timing margin has to be accurately predicted. The guard-banding method can be combined with aging mitigation techniques at design and runtime such as gate sizing [8, 18, 20, 24, 27] and input vector control [1, 5, 11, 25, 26] in order to improve lifetime or reduce the amount of required timing margin. Input vector control is a design time technique in which a suitable input vector is applied during standby mode of the circuit to maximize the recovery phase of aging critical gates. Gate sizing is another design time technique to mitigate the aging effect. In this approach, the gates placed in aging critical paths are upsized in order to prevent timing failures due to aging. For this purpose, the larger gates, which are available in the standard cell library, are used. However, since the aging effect is not considered in the standard cell library design, the area and/or power overhead of upsizing is high. Therefore, there is need to redesign/extend the standard cell library in order to reduce the overheads of gate sizing method. In the standard cell library design, the transistors in each gate are sized in a way that the rise and fall delays become equal for a typical load capacitance and transition time [22]. However, BTI asymmetrically affects the rise and fall delays of the gates according to their transistors duty cycle (which in turn is a function of its input sp [4]). In other words, the rise and fall delays of a cell become significantly imbalanced during operational time. To address this issue, one approach is to size the transistors in an efficient way to reduce aging effect. A transistor level sizing approach based on Lagrangian relaxation technique is proposed in [13]. However, it is not based on standard cell library design and it gives different sizing for each gate inside the circuit which makes it infeasible for standard cell-based design. In [3], an NBTI/process variation aware standard cell design method is presented. However, the effect of input SP is neglected and a constant SP of 50% is assumed for NBTI-induced V th shift calculation. An NBTI-aware basic cell design is also proposed in [9]. However, no proper methodology to consider the effect of input SPs (uneven BTI-induced degradation) is provided. As will be shown in our simulation results, neglecting the effect of SP impacts the efficiency of such method especially in advanced technology nodes where both NBTI and PBTI matter.

15.3 Aging-Aware Cell Sizing

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15.3 Aging-Aware Cell Sizing

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In the typical library cell design, the optimal ratio of Wp (width of the PMOS transistor) to W n (width of the NMOS transistor) is adjusted in order to balance the rise and fall delays of the gate [22]. However, due to BTI effect, the threshold voltage of transistors degrades unevenly leading to unequal rise and fall delays of the gates at the end of the expected lifetime. Figure 15.1a shows the rise and fall delays of a simple inverter over the time for a duty cycle equal to 0.5 considering only NBTI effect. As shown in this figure, although the rise and fall delays are equal at design time (time = 0), they diverge after 3 years. This is due to the fact that NBTI effect leads to an increase in the threshold voltage of PMOS transistor leading to an increase in the rise delay and a decrease in the fall delay of the gate. Our objective is to design the cell (by changing the Wp/W n ratio), in a way that its rise and fall delays become equal at the end of the expected lifetime (see Fig. 15.1b). As shown in this figure, by optimizing Wp/W n ratio to balance rise and fall delays at expected lifetime, at the expense of upsizing only PMOS transistor in the gate, a better post-aging delay is achieved. Figure 15.2 shows similar results but considering BTI (NBTI and PBTI) effect for an inverter with input SP of 0.1. Since the duty cycle (DC) of the PMOS transistor (DCNBTI = 1 − SPin = 0.9) is higher than that of the NMOS transistor (DCPBTI = SPin = 0.1), the rise delay degradation is higher than the fall delay degradation. As a result, the Wp/W n ratio has to increase compared to the typical mode in order to have the same rise and fall delays at the expected lifetime. Since BTI effect is a function of DC (see Fig. 13.4b), the optimized BTI-aware Wp/W n ratio for each cell is a function of input duty cycle (and hence SP). Figure 15.3 shows the optimized NBTI-aware Wp/W n ratio for different input SPs normalized to the case that aging effects are not considered. Since for the NBTI case DCNBTI = 1 − SPin , for smaller SPs the NBTI effect is larger and, as a result, the PMOS transistor in the pull-up network has to be designed larger to compensate NBTI effect.

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15 Aging-Aware Standard Cell Library Optimization Methods

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Fig. 15.3 Optimized Wp/W n ratio increase for different signal probabilities normalized to the case that it is optimized for time = 0

Figure 15.3 also shows BTI-aware Wp/W n ratio but for the case where both NBTI and PBTI effects are considered. As shown in this figure, the optimized Wp/W n ratio is more sensitive to SP compared to the case in which only NBTI effect is considered. Another observation is that, for the case of BTI effect, if SP = 0.5 the Wp/W n ratio is almost equal to the case that aging effect is neglected. In fact, when SP = 0.5, both NMOS and PMOS transistors are almost under the same stress and as a result both transistors degrade at almost the same pace. Therefore, their ratio in this case is almost equal to the typical case. Moreover, for the larger SPs the Wp/W n ratio is less than the typical case. Since we consider a constant W n and for larger SPs (SP > 0.5) the NMOS transistor degrades more than PMOS transistor, the fall delay becomes larger than the rise delay and hence we can decrease Wp to make the rise and fall delays equal in order to save area and power. It should be noted that, in this case we only gain area/power, however, BTI is not mitigated.

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The efficiency of this approach is demonstrated in the following by the example circuit given in Fig. 15.4. The circuit is an inverter chain with the primary input SP of 0.1. Figure 15.4a shows the rise and fall delays when the time-zero-balanced (typical) library cells are used. As shown in this figure, although the rise and fall delays of the path are the same at design time, they diverge significantly throughout the lifetime. There are two reasons for this significant imbalance during operational time:

Fig. 15.4 A simple circuit to show the efficiency of aging-aware standard cell sizing: (a) time-zero-balanced vs lifetime-balanced mapping and (b) delay of lifetime-balanced vs time-zerobalanced [14]

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1. The rise delays of inverter 1 and 3 become larger than their fall delay during operational time (Dr(inv1) > Df (inv1) & Dr(inv3) > Df (inv3) at time = 3 years) as these inverters suffer more from NBTI effect rather than PBTI. 2. The situation for inverters 2 and 4 is the opposite since their fall delays increase over the lifetime as they are mostly under PBTI stress. (Df (inv2) > Dr(inv2) & Df (inv4) > Dr(inv4) at time = 3 years). Therefore, the total rise and fall delays of the path which can be obtained by Eq. (15.3.1) become significantly imbalanced. Drise = Df (inv1) + Dr (inv2) + Df (inv3) + Dr (inv4)

(15.3.1)

Df all = Dr (inv1) + Df (inv2) + Dr (inv3) + Df (inv4) Figure 15.4a also shows the rise and fall delays when the lifetime-balanced library cells are used. As shown for this case, the rise and fall delays of the path become similar at the end of the operational lifetime of the circuit, and the overall delay (100.6 ps) is less than the case in which the time-zero-balanced library cells are used (104 ps). Dlifetime-balanced (100.6 ps) < Dtime-zero-balanced (104 ps)

(15.3.2)

This is obtained by the upsizing of PMOS transistors for the inverters under NBTI stress (higher Wp/W n ratio for inverters 1 and 3 with smaller SPs according to Fig. 15.3). On the other side, this upsizing is compensated (in terms of power and area) by downsizing the PMOS transistors of the other inverters (inverters 2 and 4) which are more under PBTI stress (lower Wp/W n ratio for larger SPs according to Fig. 15.3). Due to the downsizing, the sum of transistors width (which is a representative for area and power) for the lifetime-balanced library cells is equal to that of time-zero-balanced scenario while it has better delay after 3 years. Based on the observation above, in order to reduce aging effect, we can optimize the Wp/W n ratio of different gates (i.e. library cell redesign) according to their input SPs, in order to make their rise and fall delays equal at their expected lifetime. In order to address different types of variability (e.g. transistor aging), a safety margin (guardband) is added to the design to guarantee the reliable operation of the designed circuit. Therefore, the overall clock cycle is obtained by the following equation: T clk = D0 + GB

(15.3.3)

where D0 is the time-zero delay, GB is the guardband, and T clk is the clock period. According to Fig. 15.4b, although the delay of the circuit at time zero may even become larger, it becomes smaller at the expected lifetime:

15.4 Cell Library Redesign and Mapping

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D0LT B > D0T ZB GB LT B < GB T ZB D0LT B + GB LT B < D0T ZB + GB T ZB ⇒ T clk LT B < T clk T ZB

(15.3.4)

where LT B and T ZB are the abbreviations for lifetime-balanced and time-zerobalanced, respectively. Therefore, with the reduction in the amount of aging-induced timing margin, the clock period is reduced in overall.

15.4 Cell Library Redesign and Mapping Figure 15.5 shows the overall flow of the proposed methodology. It consists of two phases: (1) aging-aware standard cell library redesign and (2) circuit library mapping using the new library cells. The first phase is the aging-aware standard cell library redesign in which the library cells are optimized for different SPs considering BTI effect. This step is done only once for each technology in order

Fig. 15.5 Overall flow of proposed aging-aware standard cell library design [14]

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to build the aging-aware library. The second phase is circuit library mapping using the new library cells. The gate-level netlist is given to a logic simulator to obtain the SPs of all internal nodes. According to internal node SPs, the gates are replaced with optimized aging-aware designed library cells. The details of each phase are explained next.

15.4.1 Aging-Aware Cell Library We propose aging-aware standard cell library redesign, in which the library cells are optimized for different SPs considering the BTI effect. According to Fig. 15.3, the optimized Wp/W n ratio is a function of the SPs of cell inputs. However, it is not possible to extend the library for all combinations of SPs. For this purpose, the SP range ([0.0, 1.0]) is discretized and for each combination of these SP values a new library cell is added and optimized by finding a suitable Wp/W n ratio for that range using SPICE simulations. In order to obtain the optimized Wp/W n ratio, first the BTI-induced V th for all internal transistors of the cell is calculated according to the particular SP value. Then, the Wp/W n ratio of the cell is swept using a binary search to obtain the best ratio leading to equal rise and fall delays. For example, if we discretize the SP range to {[0.0 0.2), [0.2 0.4), [0.4 0.6), [0.6 0.8), [0.8 1.0]}, then for a simple inverter (I N V X1) we need to extend the library with five additional cells: {I N V X1_0.1, I N V X1_0.3, I N V X1_0.5, I N V X1_0.7, I N V X1_0.9} and for each cell the Wp/W n are obtained to have equal rise and fall delays at the expected lifetime. Here, {0.1, 0.3, 0.5, 0.7, 0.9} are the representative SPs for each range and the library cell for each range is optimized according to its representative SP value. In order to build the library, each cell is characterized to obtain the delay and leakage Look-up tables (LUTs). By increasing the library size, the characterization time/effort increases accordingly, however, it should be noted that the aging-aware library cell design and characterization are done only once for each technology. Library Size Increase and Non-uniform SP Sampling If the SP range ([0.0 1.0]) is discretized to m intervals, for each cell with n inputs, mn cells are added to the library. In other words, the number of new library cells increases exponentially with m. More sampling points for the input SP range may increase the efficiency of this approach in terms of delay balancing, however, it leads to a very large size of the library. This makes the approach infeasible for industrial-scale libraries which contain more than 1000 cells. Moreover, a high resolution of SP sampling makes the technique very sensitive to process variations. This implies that a suitable discretization resolution has to be considered for a reasonable trade-off between the efficiency of the method and the library size. For this purpose, two important parameters have to be considered:

15.4 Cell Library Redesign and Mapping 7000 6000 Number of nodes

Fig. 15.6 The histogram of internal node SP distribution for ISCAS89 benchmark circuits (over all benchmarks)

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1. The sensitivity of BTI-induced Vth shift to SP: As shown in Fig. 13.4b, the BTIinduced Vth shift has different sensitivities to the SP (duty cycle) in different range of SPs. Therefore, more samples (at least one sample) has to be considered for more sensitive ranges (e.g. [0.0 0.1] range in Fig. 13.4b). 2. Distribution of the SPs of internal nodes in typical circuits: The SPs of the internal nodes in typical circuits are not uniformly distributed over the entire range ([0.0 1.0]). Figure 15.6 shows the histogram of SP distribution for internal nodes of ISCAS89 benchmark circuits. As shown in this figure, SP values around 0.0, 0.5, and 1.0 are more frequent. Therefore, in a non-uniform sampling, more samples have to be chosen in ranges where the probability of occurrence in the typical circuits is higher. Considering these two factors, a non-uniform discretization and sampling can be used in order to keep the sampling points as few as possible, while maintaining a high efficiency for this technique in terms of aging mitigation.

15.4.2 Technology Mapping Using Aging-Aware Standard Cell Library Once the aging-aware cell library is constructed, it can be used for the technology mapping phase for different circuits. In order to obtain suitable standard cells for each circuit, we start from a netlist mapped into the original aging-unaware library. Then, the gate-level netlist is given to a logic simulator to obtain the internal SPs. According to the input SPs of each gate, a new cell with the closest set of input SPs from the new library is chosen to replace the initial cell. For example, if we have a two-input NAND gate with the SPs of 0.15 and 0.73 for its inputs, according to the discretization example of previous subsection, this NAND gate will be replaced with the N AN D_0.1_0.7 aging-aware cell. In order to minimize the area/power

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overhead, this remapping is done only for the critical gates (gates which are in the critical/near-critical paths) since the others have no contribution to the delay of the circuit.

15.5 Simulation Results In this section, we show the efficiency of our proposed method by comparing it to the time-zero-balanced library cell design as well as scenarios in which a representative SP is considered for all gates. We also investigate the trade-off between library size increase and aging mitigation by considering various sample sizes and strategies. The impact of different workloads is also discussed.

15.5.1 Simulation Setup and Flow Figure 15.7 shows the details of our flow to obtain the simulation results. The gatelevel netlist is obtained by synthesizing the ISCAS89 benchmark circuits using Nangate 45 nm library [17] containing 42 cells (INVERTER, BUFFER and two inputs AND, OR, NAND, NOR, XOR, and XNOR gates). The worst-case BTIinduced delay degradation is assumed to be 10% in 3 years, and the parameters of the BTI model are set accordingly using the deterministic model explained in Sect. 13.2.1.1.

Fig. 15.7 Overall flow to obtain simulation results [14]

15.5 Simulation Results

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The first step is to conduct the aging-aware library cell design as proposed in Sect. 15.4.1. Here, we consider four different scenarios for the discretization of the SP range: Uniform Sampling with 5 Points (U5) In this scenario, the SP range is discretized uniformly to 5 ranges: {[0.0 0.2), [0.2 0.4), [0.4 0.6), [0.6 0.8), [0.8 1.0]} with representative sampling points of 0.1, 0.3, 0.5, 0.7, 0.9. The number of logical standard cells (AND, OR, BUFFER, NAND, NOR, INVERTER, XOR, and XNOR) is increased by around 50× (from 42 to 2010 cells). Such an increase in the library size makes it infeasible to be used for industrial applications. Non-uniform Sampling with 3 Points (NU3) Another option for SP discretization is to use a non-uniform sampling. For this purpose we put more SP samples in the range that BTI is more sensitive to SP changes (for example, the range [0.0 0.1] according to Fig. 13.4b). Another important factor which has to be considered is the SP distribution for different logic gates of a typical circuit. For this scenario, based on Fig. 15.6, we only consider 3 samples for SP ({0.1, 0.5, 0.9}) for three ranges of {[0.0 0.2), [0.2 0.8), [0.8 1.0]} in order to decrease the library size in comparison with the previous scenario. In this case, the library size consists of 522 cells which is almost 4 times smaller than that of the previous scenario. Non-uniform Sampling with 2 Points (NU2) For this case we only consider 2 samples of SP ({0.1, 0.9}) for two ranges {[0.0 0.5), [0.5 1.0]} in order to further decrease the library size. In this case, the aging-aware library consists of 192 cells (more than 10 times reduction compared to the first scenario). Non-uniform Worst-Case Sampling with 2 Points (NU2W) For this case we also consider 2 samples of SP ({0.1, 0.5}) for two ranges {[0.0 0.5), [0.5 1.0]}. The library size is equal to previous case, however, in this case all the gates with input SP larger than 0.5 are mapped to cell with SP = 0.5 in order to upsize the PMOS transistors (according to Fig. 15.3) to further reduce BTI-degradation compared to NU2. In order to obtain the results for the case in which the effect of SP is neglected in library cell design (e.g. the method in [9]), we considered two cases. In the first case, we assumed that all cells are optimized with input SP of 0.5. For the second case, we considered a worst-case approach. For this purpose, according to Fig. 15.3, we consider very small SP of 0.1 in order to upsize the PMOS transistors to mitigate BTI. We used accurate SPICE simulations in order to optimize the standard cells by finding the best Wp/W n ratio for all scenarios. After obtaining the new agingaware cells, each cell is characterized to obtain delay LUTs for different load capacitances, transition times, and V th. This means that for each standard cell we have generated nT + 2 dimensional LUTs, where nT is the number of transistors inside that gate, and the two other dimensions are related to the load capacitance and the transition time. Since the SP range ([0.0 1.0]) is discretized and for each range of SPs a suitable standard cell is added to library, the characterization step has to be done only once in order to obtain the delay LUTs for each standard cell.

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Besides, the benchmark circuit is synthesized to obtain the gate-level netlist. In the mapping phase, only the critical gates in the gate-level netlist are replaced with the new cells, as described in Sect. 15.4.2, to obtain the aging-aware gate-level netlist. Here, the critical/near critical paths which have the delay more than 90% of circuit delay are selected in order to find the critical gates. Next, the netlist mapped into the original library and the one mapped into the aging-aware library are given to a logic simulator to obtain the SPs of internal nodes. Then the BTI-induced V th of all the transistors are obtained according to the model proposed in [4]. Finally, the gate-level netlists, V th values, and the delay LUTs are given to an aging-aware static timing analysis (STA) tool, similar to the one proposed in [12], to obtain the fresh and aged circuit delays. For the aging-aware STA, a method similar to the one proposed in [12] is employed.

15.5.2 Aging Mitigation The simulation results are shown in Table 15.1. The area is approximated by the summation of all transistor widths inside the circuit. Therefore, it is not only a representative for the area, but also shows the trend of the power consumption. As shown in this table, uniform sampling with 5 points (U5) and non-uniform sampling with 3 points (NU3) scenarios lead to 26.7% and 25.4% timing margin reduction (167% and 155% lifetime improvement), respectively. This implies that while NU3 needs much smaller library size compared to U5, their efficiencies in terms of lifetime improvement and timing margin reduction are comparable. This shows that the lifetime improvement saturates when the number of SP samples exceeds a particular limit. Both scenarios have negligible area overhead. There are two reasons for that: (1) the aging-aware technology mapping is only performed for critical gates and (2) for the gates with large input SPs, the PMOS transistors are down-sized in order to save area/power overhead (according to Fig. 15.3) . The results for NU2 scenario show that with a much smaller library size, 14% timing margin reduction (85% lifetime improvement) is obtained. However, NU2W gives better results compared to NU2 in terms of timing margin (lifetime improvement) with the same library size at the expense of a small area/power overhead (0.3%). This shows the importance of the proper SP sampling for aging-aware cell library design. Compared to other alternative (in which the SP distribution of internal node is neglected [9]), considering a fixed SP of 0.5 leads to even worse lifetime compared to the original library cell design, although it might be beneficial only when NBTI effect is considered. For the other scenario (fixed SP of 0.1), the lifetime improvement is much less than all the four scenarios above. Moreover, for this worst-case scenario, the area/power overhead is higher (0.6%).

Lifetime improvement U5 NU3 NU2 NU2W (%) (%) (%) (%) 239.3 211.4 183.4 162.3 275.0 271.0 235.1 162.0 94.4 68.3 12.2 49.4 178.6 224.3 165.3 88.4 98.2 65.9 3.7 64.2 147.2 139.0 52.6 94.1 255.0 274.3 200.6 109.7 132.0 121.9 57.5 104.8 201.8 221.5 147.9 124.8 438.5 244.3 150.1 155.9 136.1 114.3 89.4 73.4 207.5 181.2 124.2 110.8 244.1 265.5 174.2 174.4 45.4 180.7 106.9 106.7 120.7 133.8 36.5 66.8 153.8 106.0 71.5 94.5 167.2 155.3 85.5 97.1 SP = 0.5 (%) −13.2 −13.7 −14.5 −8.1 −11.9 −12.6 −11.7 −13.3 −15.9 −13.8 −2.8 −11.3 −13.4 −10.6 −8.4 −12.5 −11.8

SP = 0.1 (%) 79.6 82.4 23.7 33.6 36.0 39.6 78.2 61.2 93.8 127.4 31.8 71.2 135.6 56.9 36.6 52.6 56.8

Area overhead U5 NU3 NU2 (%) (%) (%) 0.1 −0.1 0.1 0.2 −0.1 −0.3 0.0 −0.1 0.0 0.2 0.1 0.0 0.0 0.0 0.0 0.0 0.0 0.1 0.0 0.0 0.0 0.0 0.0 0.0 0.0 −0.1 −0.1 0.1 0.0 0.0 0.0 0.0 0.0 0.0 −0.1 0.0 0.0 0.0 0.0 0.3 0.1 0.0 0.0 0.0 0.0 0.0 0.0 0.0 0.1 0.0 0.0 NU2W (%) 0.4 0.3 0.5 0.3 0.2 0.2 0.1 0.4 0.3 0.1 0.2 0.3 0.1 0.2 0.3 0.0 0.3

SP = 0.5 (%) −0.1 −0.1 −0.1 −0.1 −0.1 0.0 0.0 −0.1 −0.1 0.0 0.0 −0.1 0.0 0.0 −0.1 0.0 −0.1

SP = 0.1 (%) 0.8 0.9 0.9 0.6 0.5 0.4 0.3 1.0 0.7 0.3 0.3 0.6 0.2 0.5 0.6 0.0 0.6

U5 Uniform sampling with 5 points ({0.1, 0.3, 0.5, 0.7, 0.9}), NU3 Non-uniform sampling with 3 points ({0.1, 0.5, 0.9}), NU2 Non-uniform sampling with 3 points ({0.1, 0.9}), NU2W Non-uniform worst-case sampling with 2 points ({0.1, 0.5})

# of gates

Timing margin reduction U5 NU3 NU2 NU2W (%) (%) (%) (%) s400 228 35.7 32.8 29.7 27.3 s444 249 39.2 38.8 35.3 27.2 s420 280 18.1 13.9 2.9 10.6 s526 330 29.2 34.2 27.6 17.2 s510 373 18.7 13.5 0.9 13.2 s832 584 25.4 24.3 11.1 18.0 s953 683 37.3 39.1 31.7 20.3 s1196 797 23.4 22.1 12.0 19.6 s1423 824 31.8 33.9 25.5 22.4 s1238 881 52.3 36.2 25.8 26.5 s1488 902 24.0 21.0 17.3 14.8 s9234 1725 32.4 29.5 22.4 20.5 s5378 2926 36.2 38.3 28.7 28.7 s13207 4074 9.8 29.4 19.9 19.9 s15850 5244 21.9 23.7 8.1 13.6 s38584 18,142 26.2 19.8 14.4 18.1 Average (%) 26.7 25.4 14.2 18.0

Benchmark circuit

Table 15.1 The efficiency of our technique compared to the normal standard cell library design in terms of lifetime improvement and area overhead

15.5 Simulation Results 335

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To account for wearout mechanisms, the clock frequency has to be set according to delay of the circuit at the expected lifetime (not at t = 0), by adding aginginduced timing margins. This means that the circuit performance is determined by the post-aging delay. Although our proposed method may even lead to a higher circuit delay at t = 0 (up to 2%), it provides an overall performance improvement by reducing the post-aging delay and its associated timing margin, as shown in Table 15.1. For the case where the performance is fixed, the proposed technique results in an improvement in the circuit lifetime.

15.5.3 Library Size According to the results, using more sampling points results in better lifetime improvement at the expense of library size explosion. However, the non-uniform sampling with fewer points (e.g. NU3) provides comparable improvement with much reduced library size. For further reduction of library size, we found that NU2W is a good trade-off which provides 97% improvement in the lifetime with around 4× increase of library size. Another alternative solution for SP sampling is a hybrid non-uniform sampling. In this scenario, the cells with more inputs (e.g. more than 2 inputs) will have fewer sampling points (e.g. 2 sampling points), while the cells with fewer inputs (e.g. 1 or 2 inputs) use more sampling points (e.g. 3 nonuniform sampling points) in order to balance library size and lifetime improvement. Effect of the Workload For the simulation results presented in Table 15.1, we assumed that the primary input SPs are 0.5 for both the gate mapping phase and the SP calculation of internal nodes (with which BTI-induced V th values are obtained accordingly). However, different workloads result in different primary input SPs, and internal SPs accordingly, observed by the circuit during its operational lifetime. To account for this on the efficiency of our methodology, we performed two sets of experiments. In the first experiment, the gates are mapped (optimized) according to the primary input SP of 0.5 but the internal nodes SPs (and BTI-induced V th shifts) are calculated for the primary input SP of 0.2. In the second experiment, the primary input SPs used for the mapping phase and the internal SP (and degradation) calculation were chosen as 0.2 and 0.5, respectively, i.e. the reverse situation as in the first experiment. The results show that the efficiency of U5 decreases by around 25% (from 167% lifetime improvement to 127%) when different primary input SPs are used for the mapping phase and the delay degradation calculation. However, this has negligible effect on the efficiency of the methods with the fewer SP samples (less than 1% decrease in the lifetime improvement of NU2W). Therefore, while the optimization is done at “design time” using a particular assumption over the primary input SPs, the method still remains effective as the workload changes during runtime.

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Effect of Workloads in a Real System As a case study of applying proposed approach to a real system, we extracted the SP distribution for different workloads running on OR1200 processor. The idea is to show whether a design time decision which maps the gates to different cells based on a “typical” SP distribution known at design time is still valid when real workloads exhibit changes for SPs and the system switches to different workloads during its lifetime. OR1200 is an in-order processor with five stages pipeline which implements Harvard architecture, i.e. has separate instruction and data cache. This processor is synthesized with Design Compiler using Nangate 45 nm standard cell library. The final netlist has 30,986 gates and 2693 flip-flops. During the post-synthesis simulation, several benchmarks from MiBench benchmark suite are executed on this processor and the activity of all signals is dumped in VCD format. By analyzing the corresponding VCD file of each workload, we extracted the SP of all signals during the execution of that workload. Figure 15.8 shows the histogram of SP of all signals for different workloads running on this processor. As shown in

Fig. 15.8 Histogram of the internal node SPs of different applications. (a) benchmark = CRC32, (b) benchmark = Bitcounts, (c) benchmark = Stringsearch, (d) benchmark = QSort

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this figure, SP values around [0.0, 0.1] and [0.9, 0.1] are more frequent which needs to be considered in the SP sampling of our proposed approach. Moreover, as shown in the flow of proposed approach, the gate mapping phase is done according to the SP of the internal nodes. However, the SP of internal nodes might change from one workload to another. This means that for different workloads we need to have different mapping which is not possible since the gate mapping has to be done only once at design time. Therefore, we propose to perform the gate mapping phase according to the average of internal node SPs over all workloads. However, the efficiency of our approach, for a particular workload, strongly depends on the internal node SP distribution of that workload compared to that of average case. In other words, if there is a huge difference between the SP distribution of one workload compared to average case, the efficiency of our approach would be very limited. To investigate this issue, we perform a set of simulations to compare the internal node SP distribution of different workloads and the average case. For this purpose, we obtain the SP range of the internal nodes for the average case and each particular workload to check whether the internal node SP remains in the same range or it is shifted to other ranges. This is done for all discretization scenarios introduced in Sect. 15.5.1. Figure 15.9a shows the results for the case in which we have only two SP ranges (NU2 and NU2W). As shown in this figure, for all workloads more than 95% of the internal nodes remain in the same SP bucket compared to the average case. Figure 15.9b, c show similar results for the case in which the entire SP range is divided to 3 and 5 buckets (NU3 and U5), respectively. Figure 15.9d compares the results for U5, NU3, NU2 (NU2W) scenarios. As shown in this figure, while in NU2 scenario, more than 95% of the internal nodes remain in the same SP bucket compared to the average case, this percentage is around 85% for U5 scenario. This means that when the SP range is discretized to more buckets, there will be more shifts across different buckets when considering different workloads. However, the efficiency of our approach will be less affected in NU2 and NU2W scenarios for different workloads compared to the U5 scenario. As also shown in Sect. 15.5.3, less discretization of the SP range, using NU2 and NU2W methods, results in a better trade-off between library size and lifetime improvement, which is also supported by this analysis.

15.5.4 Effect of Voltage and Temperature Variation As discussed previously, the main idea of this chapter is to balance the rise and fall delays of standard cells at the end of their expected lifetime rather than the design time according to the input SP of the cell. However, the BTI effect is not only dependent of input SP, but also the supply voltage and the temperature. Since

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different circuits (and hence cells inside the circuits) may have different working temperatures and supply voltages, the efficiency of our proposed approach may be affected. To investigate this issue, the rise to fall delay ratio of a simple inverter is obtained for different corners of temperature and supply voltage values for two cases of proposed lifetime-balanced cell and time-zero-balanced cell. It should be noted that the optimization is done for the nominal corner of supply voltage (Vdd = 1 V) and room temperature (25 ◦ C). As shown in Fig. 15.10, although the cell becomes less balanced for higher temperature and lower Vdd values, still our approach provides more balanced rise and fall delay values (the ratio is more close to 1). This is due to the fact that the temperature and voltage variations affect both pull-up and pull-down network and their aging rate with almost the same rate. Therefore, making the cell more balances at one corner (nominal corner of supply voltage and room temperature) is helpful for other corners as well. This confirms that our proposed approach is still useful in the different corners of temperature and supply voltage variations.

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15.6 Summary In this chapter, we proposed a BTI-aware library cell design to mitigate the BTI effect. The main idea is to balance the rise and fall delays of a cell by considering the target lifetime delay degradations instead of time-zero delays. We also presented a technology mapping technique in which the critical gates in the circuit are mapped to suitable cells within this aging-aware library based on their input signal probabilities. The simulation results show that our technique can improve the lifetime by approximately 150% with negligible area/power overheads. Our experiments also show that the proposed approach remains effective even when the system workload changes during the operational lifetime.

References 1. J. Abella, X. Vera, A. Gonzalez, Penelope: the NBTI-aware processor, in International Symposium on Microarchitecture (IEEE, Piscataway, 2007), pp. 85–96 2. M. Basoglu, M. Orshansky, M. Erez, NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime, in Proceedings of the 16th ACM/IEEE International Symposium on Low Power Electronics and Design (ACM, New York, 2010), pp. 253–258 3. S. Basu, R. Vemuri, Process variation and NBTI tolerant standard cells to improve parametric yield and lifetime of ICS, in IEEE Computer Society Annual Symposium on VLSI. (IEEE, Piscataway, 2007), pp. 291–298 4. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, Predictive modeling of the NBTI effect for reliable design, in IEEE Custom Integrated Circuits Conference (IEEE, Piscataway, 2006), pp. 189–192 5. D. Bild, R. Dick, G. Bok, Static NBTI reduction using internal node control. ACM Trans. Des. Autom. Electron. Syst. 17(4), 45 (2012)

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6. A. Calimera, E. Macii, M. Poncino, NBTI-aware power gating for concurrent leakage and aging optimization, in Proceedings of the International Symposium on Low Power Electronics and Design (ACM, New York, 2009), pp. 127–132 7. A. Calimera, E. Macii, M. Poncino, NBTI-aware clustered power gating. ACM Trans. Des. Autom. Electron. Syst. 16(1), 3 (2010) 8. J. Chen, S. Wang, M. Tehranipoor, Efficient selection and analysis of critical-reliability paths and gates, in Proceedings of the ACM Great Lakes symposium on VLSI (GLSVLSI) (ACM, New York, 2012), pp. 45–50 9. M.B. da Silva, V.V. Camargo, L. Brusamarello, G.I. Wirth, R. da Silva, NBTI-aware technique for transistor sizing of high-performance CMOS gates, in IEEE Latin-American Test Workshop (LATW) (IEEE, Piscataway, 2009), pp. 1–5 10. J. Fang, S. Gupta, S.V. Kumar, S.K. Marella, V. Mishra, P. Zhou, S.S. Sapatnekar, Circuit reliability: from physics to architectures, in Proceedings of the International Conference on Computer-Aided Design (ACM, New York, 2012), pp. 243–246 11. F. Firouzi, S. Kiamehr, M.B. Tahoori, NBTI mitigation by optimized NOP assignment and insertion, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2012), pp. 218–223 12. F. Firouzi, S. Kiamehr, M. Tahoori, S. Nassif, Incorporating the impacts of workload-dependent runtime variations into timing analysis, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2013), pp. 1022–1025 13. K. Kang, H. Kufluoglu, M. Alain, K. Roy, Efficient transistor-level sizing technique under temporal performance degradation due to NBTI, in International Conference on Computer Design (ICCD) (IEEE, Piscataway, 2007), pp. 216–221 14. S. Kiamehr, M. Ebrahimi, F. Firouzi, M.B. Tahoori, Extending standard cell library for aging mitigation. IET Comput. Digit. Tech. 9(4), 206–212 (2015) 15. S.V. Kumar, C.H. Kim, S.S. Sapatnekar, Adaptive techniques for overcoming performance degradation due to aging in cmos circuits. IEEE Trans. Very Large Scale Integr. VLSI Syst. 19(4), 603–614 (2011) 16. H. Mostafa, M. Anis, M. Elmasry, Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Trans. Circuits Syst. Regul. Pap. 58(12), 2859– 2871 (2011) 17. Nangate open cell library. http://www.nangate.com/ 18. F. Oboril, M. Tahoori, MTTF-Balanced pipeline design, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2013), pp. 1–6 19. F. Oboril, M.B. Tahoori, ExtraTime: modeling and analysis of wearout due to transistor aging at microarchitecture-level, in 2012 42nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN) (IEEE, Piscataway, 2012), pp. 1–12 20. B. Paul, K. Kang, H. Kufluoglu, M.A. Alam, K. Roy, Negative bias temperature instability: estimation and design for improved reliability of nanoscale circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4), 743–751 (2007) 21. Z. Qi, M.R. Stan, NBTI resilient circuits using adaptive body biasing, in Proceedings of the 18th ACM Great Lakes symposium on VLSI (ACM, New York, 2008), pp. 285–290 22. J.M. Rabaey, A.P. Chandrakasan, B. Nikolic, Digital Integrated Circuits, vol. 2 (Prentice Hall, Englewood Cliffs 2002) 23. V. Reddy, J.M. Carulli, A.T. Krishnan, W. Bosch, B. Burgess, Impact of negative bias temperature instability on product parametric drift, in International Test Conference (ITC) (IEEE, Piscataway, 2004), pp. 148–155 24. W. Wang, Z. Wei, S. Yang, Y. Cao, An efficient method to identify critical gates under circuit aging, in International Conference on Computer-Aided Design (IEEE, Piscataway, 2007), pp. 735–740 25. Y. Wang, H. Luo, K. He, R. Luo, H. Yang, Y. Xie, Temperature-aware NBTI modeling and the impact of input vector control on performance degradation, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2007), pp. 1–6

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Chapter 16

Aging Effects in Sequential Elements

16.1 Introduction The effects of process and runtime variations on memories and combinational circuits are vastly studied [3, 18]. However, there are few studies targeting the sequential elements of the circuit. Flip-flops (FFs) and latches play a crucial role in digital circuits since they are responsible for storing the system states and advancement of operations synchronized by the system clock in different circuit stages. Therefore, the reliability of the entire design is heavily dependent on the resilience of FFs. There are few analyses which evaluate the resiliency of representative FF designs under the impact of process or runtime variations [10, 12, 14]. Additionally, several techniques have been proposed to enhance the yield and the tolerability of FFs against process or runtime variations [1, 6, 14]. However, FFs are affected by both process and runtime variations, and we show that due to the interdependencies among different sources of variabilities, the combined effect on circuit delay is not merely a sum of these effects considered independently. Moreover, due to the intertwined impact of process and runtime variations on the performance of FFs, the need to methods which consider the effect of several variability sources while improving the yield and reliability of FFs is advocated. In this chapter, we analyze the functionality of different FF designs considering all significant sources of the process and runtime variations. More importantly, we present an optimization method to improve the resiliency of FFs under process and runtime variations. This work is different from related work in these aspects: • The effects of voltage droop, temperature, and input signal probability on the aging of FFs are taken into consideration. • We consider both runtime and process variations and their interdependence in a unified analysis and optimization framework.

© Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_16

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• We show that the impact of process and runtime variations on the reliability of FFs needs to be carefully considered in the design. Furthermore, we propose an optimization method to make FFs resilient against the combined effects of process and runtime variations. The rest of this chapter is organized as follows. Section 16.2 provides the related background. In Sect. 16.3, the methodology used to perform FF timing analysis and the analysis results are presented. In Sect. 16.4 a reliability optimization framework for FFs is presented and finally Sect. 16.5 concludes the chapter.

16.2 Background In this section, we provide the background information regarding the typical timing metrics of FFs. Afterwards, we describe the models which are employed in this chapter for the aging, process variation, and voltage droop.

16.2.1 Flip-Flop Timing Analysis FFs have several timing characteristics. Setup skew is the amount of time between the arrival of the data at the input and the triggering clock edge. Similarly the amount of time between the triggering clock edge and the appearance of data at the output is clk-to-q. Hold time is defined as the minimum time that the input signal should be kept unchanged after the triggering clock edge. The duration between data arrival at the input and appearance of data at the output is called data-to-q which is the sum of setup skew and clk-to-q. Since the value of data-to-q expresses the effective portion of the clock period which is taken by the FF to transfer the signal from the FF input to the FF output, it is usually considered as the delay of the FF for a given setup skew [16]. Figure 16.1 shows the extracted clk-to-q plot and the related data-to-q for a hybrid latch FF (HLFF). Similar behavior is observed in all our analyzed FFs. As shown in this figure, the data-to-q plot has a minimum point. The setup skew corresponding to this minimum is called optimum setup-time and its corresponding data-to-q value is the smallest delay of the FF. From this point on, any reference to flip-flop delay refers to the minimum data-to-q. In this chapter, we evaluate the performance of FFs based on their delays.

16.2.2 Process Variation Model There are numerous sources of process variation such as RDF, LER, and oxide thickness fluctuation which are aggravated with technology scaling. Simulational

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and experimental results have shown that the standard deviation of the threshold voltage (σ Vth ) due to process variation is related to the size of the transistor channel as [9]: 1 σVth ∝ √ Leff Weff

(16.2.1)

where Leff and Weff are the effective channel length and width of the transistor. In this chapter, we assume a normal distribution for the Vth of all transistors.

16.2.3 Voltage Droop Model A large number of simultaneously charging and discharging transistors in a circuit result in a bounce in power and ground voltage levels. This phenomenon, which is called voltage droop, reduces the actual supply voltage that is feeding the circuit, thus reduces the speed of the circuit and may result in reliability issues [5]. A large portion of the current drawn from the circuit is drawn by FFs and a major voltage droop occurs during the time that FFs are changing states. Therefore, the voltage droop here is modeled by connecting the FF with a resistor to supply voltage as shown in Fig. 16.2.

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Fig. 16.2 The simulation test bench with voltage droop [4]

16.3 Robustness Analysis In this section, the methodology for analyzing FFs in the presence of process and runtime variabilities is presented. We consider different FFs and latch topologies which are commonly used in high-performance and low power designs for our analysis [16], namely hybrid-latch FF (HLFF), semi-dynamic FF (SDFF), sense amplifier FF (SAFF), digital DFF, dynamic/static single transistor clocked latches (DSTC/SSTC), and modified C2MOS latch. The simulations are performed using SPICE simulator for three different technology nodes 45 nm, 32 nm, and 22 nm using predictive technology models [13]. We followed an iterative multivariate optimization method to find the best sizing of each FF for the optimum power-delay product (PDP).

16.3.1 Overall Flow First, the BTI-induced threshold voltage (Vth ) of each transistor is obtained according to their input signal probabilities and temperature using the model proposed in [2]. The worst-case BTI-induced delay degradation is assumed to be 10% over 3 years for a simple inverter and the parameters of the BTI model are set accordingly for each technology node. The next step is to perform a Monte Carlo (MC) timing analysis. For each MC sample the process variation is applied by generating a set of Vth for all the FF transistors based on their sizes according to the model proposed in [9]. The simulation parameters are configured so that the σ/μ (the ratio between the standard deviation to the mean) of the Vth for a minimum size transistor at 45 nm, 32 nm, and 22 nm nodes becomes equal to 10%, 14%, and 20%, respectively [8]. Vth for each transistor is the sum of Vth for BTI and process variation.

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The voltage droop impact is also applied by connecting the FF with a resistor to supply voltage. For this purpose, the resistor value is adjusted according to the assumption of maximum voltage droop value of FF (here up to 10% [11]). Then a SPICE netlist is generated and finally timing analysis is performed to find the optimum setup-time and the delay of each FF. We perform the complete flow for all FFs considering aging effect while sweeping other sources of runtime variation such as signal probability, temperature, and voltage droop in order to consider all variabilities simultaneously. In order to consider the effects of all variability sources, we obtain the timing failure of the FF; a timing failure occurs if the delay of a FF affected by all variability sources exceeds (1+X) times of the delay of the FF at the design time working at nominal temperature and supply voltage. Parameter X is calculated according to the average variation of FF delays considering only the process variation for each technology node. For instance, X is equal to 40% for 22 nm technology node.

16.3.2 Results and Analysis Effect of FF Input Signal Probability Figure 16.3a shows how the delay of SDFF changes considering: (1) only the BTI, (2) only the process variation (PV), and (3) combined effect. As shown in this figure, the BTI-induced delay degradation ranging up to 25% depends on the input signal probability (SP), i.e., the probability of FF input signal being equal to logic level “1.” Furthermore, based on the internal structure of a FF, increasing or decreasing the input SP of the FF may

Fig. 16.3 (a) Normalized delay of SDFF at different input SPs. The delay increases by increasing the input SP (temperature = 25 ◦ C, voltage droop = 0%). (b) Mean average percentage error (MAPE) of separate consideration of different sources of variation compared to the combined effect calculated according to Eq. (16.3.1) [4]

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aggravate the delay degradation. For example, in SDFF, the delay degradation is intensified by increasing the input SP as shown in Fig. 16.3a. In addition, according to Fig. 16.3a, the process variation by itself has a small impact on the mean of the delay degradation but when combined with the BTI, the standard deviation of the delay degradation is pronounced. This happens when Vth of a critical transistor does not linearly affect the delay degradation; hence, an additional change in the Vth amplifies the impact on the FF delay. Later we will show that increasing the temperature and voltage droop will induce more variations to the delay. Since we need to consider the worst case for the guard-banding, the highest delay degradation of a particular FF design should be considered. Although the input SP of 0.0 and 1.0 has the highest impact on the delay degradation due to static BTI condition, it barely happens that the input SP of a FF becomes exactly equal to 0.0 or 1.0 due to large probability of signal transition in combinational logics. Therefore, to avoid overly pessimistic scenario, for this analysis we consider the maximum of the delay degradation when input SP is equal to 0.1 and 0.9 as the practical worst BTI corner. Moreover, the worst-case condition is μ + 3σ at this corner for the rest of the analysis in this section. Combined vs Separate Analysis of the Impact of Variation Sources Figure 16.3b shows the error of separate consideration of different sources of variations compared to the combined analysis at the worst case. The actual delay is extracted when the combined effect of BTI and PV is considered, while the predicted delay is calculated by simply adding the delay due to only BTI and delay due to only process variation (PV). Therefore, the error is defined as the mean absolute percentage error (MAPE) of the predicted and reference values for all MC samples: delayactual,i = delayPV+BTI,i

(16.3.1)

delaypredicted,i = delayBTI,i + delayPV,i ei =

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i=1

According to this figure, the error of isolated analysis compared to the combined analysis could be more than 20%. As previously discussed, this is due to the nonlinearity of the effect of the Vth of the critical transistors on the FF delay, which results in an intensified delay degradation. This figure emphasizes that the effect of runtime and process variations on the timing of FFs needs to be considered simultaneously. All the results that appear from this point are calculated considering the combined effect of all variation sources.

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Effect of Temperature and Voltage Droop The percentages of timing failure of FFs obtained for different values of temperature and voltage droop and results are shown in Fig. 16.4. As shown in this figure, regardless of FF design, the timing failure probability increases by increasing temperature and voltage droop. However, the sensitivities of the FFs to these runtime variations are not similar. Lowering the supply voltage slows down the circuit causing more delay degradation which means higher timing failure rates. On the other hand, higher temperature leads to smaller Vth and mobility of transistors. While a reduction in Vth results in a faster device, the decrease of mobility makes the device slower. Moreover, the BTIinduced degradation is larger at higher temperature ranges. Hence, the overall timing failure increases at higher temperature ranges. Effect of Technology Scaling The violin graphs presented in Fig. 16.5 show the increase in the FFs’ delays with technology scaling. These graphs also provide an insight into the probability density function (PDF) of the delay variation. The cross signs in the graphs show the mean values of the delays for each FF and technology node. According to the results, the amount of delay increase is significantly different

Fig. 16.5 The increase in the FFs’ delays for different technology nodes. The sizes of the violins increase by increasing the temperature and voltage droop. (All values are normalized to the nominal value of the corresponding technology node when T = 25 ◦ C, Vdd = 100%) [4]

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for FF designs ranging from around 35% for DSTC and SSTC to more than 60% for SDFF for 45 nm technology node. This is due to the fact that different FFs have different sensitivities to the Vth shift of their internal transistors. Therefore, they have different delay variations which need to be considered in the calculation of their corresponding timing margins for guard-banding. While SDFF is very sensitive to the technology scaling, C2MOS latch and SAFF show the lowest sensitivity.

16.4 Reliability-Aware Flip-Flop Design The analysis in the previous section shows that process and runtime variations can have a huge effect on the reliability of FFs. Thus, these sources of variation need to be considered for FF design. In this section, an optimization technique is introduced which increases the reliability of a given FF under runtime and process variations by altering the sizes of transistors. For this purpose, a two-phase optimization flow is developed as shown in Table 16.1. We first minimize the post-aging delay of the FF with limited area and power budget in order to compensate the delay increase due to runtime variations. Afterwards, we minimize the sensitivity of the FF with respect to process variation. At the end by presenting the optimization results for some representative FFs, we show the effectiveness of this two-phase approach.

16.4.1 Definitions The FF delay is defined as the sum of the largest setup-time and the largest clkto-q of all probable input signal probabilities and voltage droops. This is because two adjacent FFs, with some combinational logic in between, might operate with different input signal probabilities and voltage droop. Therefore we need to consider the maximum portion of each clock period used by FF as the representative delay.

Table 16.1 FF optimization method summary [4] Parameters Initial guess Constraints

Phase 1: delay minimizer Phase 2: sensitivity minimizer

W = (w1 , . . . , wn ) W 0 = optimized W for power-delay product wi ≥ wmin n 1 wi ≤ areamax power(W ) ≤ powermax Target: f (W ) Additional constraint: s(W ) ≤ s(W 0) Target: s(W ) Additional constraint: f (W ) ≤ f (W 1), W 1: optimized W from delay minimizer

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The delay is a function of many parameters such as the widths of the transistors, temperature, supply voltage, load, and the shift in threshold voltages of transistors which is related to process and runtime variations. Since the optimization is done for a specific operating condition (temperature and voltage droop), the delay can be presented as a function of transistors’ widths and threshold voltages for that specific condition. delay = f (W, Vth ),

(16.4.1)

W = [wi ], Vth = [vth,i ] [wi ], [vth,i ] are two vectors and wi , vth,i are the width and the threshold voltage shift of transistor i, respectively. When W is constant, the delay is a function of the threshold voltages of FF transistors (Vth ). Moreover, in order to minimize the effect of process variation in the second phase of the optimization, a sensitivity metric is used. For this purpose, the sensitivity of the delay function is defined using the partial derivatives of the delay function with respect to the threshold voltage of transistors. Although the partial derivatives reflect the sensitivity of the delay function to vth,i , we also need to consider the width of each transistor because the threshold voltage shift due to RDF is inversely proportional to the root square of the area of the transistor [9]. Therefore we define the total sensitivity of the delay function as: . . . ∂f 1 .. . s(W ) = . √ ∂V thi wi .

(16.4.2)

The total sensitivity is an estimation of the severity of the impact of process variation on the FF. In this chapter all derivatives are numerically approximated. For example, in order to calculate the partial derivative of f with respect to V thi we change the threshold voltage of transistor i by a fixed value (δv) and characterize the delay of the resulting FF. The delay variation is then divided by δv to find an approximation of the partial derivative.

16.4.2 Methodology In the first phase of optimization which is post-aging delay minimization, the delay function is minimized with the help of a sequential quadratic programming (SQP) method which is a nonlinear programming solver [7]. The reason to use such method is the nonlinearity and complexity of the delay function. The constraints of the problem are the area and the leakage power of the FF cell. Since the optimizer can take area from some transistors and add to other transistors, there is a possibility that the sensitivity to threshold voltage variation increases during this optimization phase. Therefore one additional constraint should

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353

be added which sets the upper limit of the total sensitivity to a value equal to the total sensitivity of the FF before optimization. Table 16.1 presents the complete definition of the problem in this phase. The initial guess W 0 is equal to the optimum W for PDP, and W 1 is the optimum solution after the first phase. wmin is the minimum possible size for each transistor, and areamax puts a limit to the sum of transistors’ widths. power(W ) function is the power consumption of the FF with the size W which is calculated through cell characterization and powermax sets an upper limit for the FF power. As previously defined, s(W 0) is the total sensitivity of the FF before optimization which limits the impact of process variation on FF. As it is shown, the variables of this phase are the widths of transistors W . Given the set of equality and inequality constraints, the underlying optimization method solves quadratic sub-problems to generate δW steps. For a simplified problem of minimizing delay function f (W ) with only one constraint b(W ) ≥ 0, the overall flow of the solver is as follows: 1. Define the Lagrangian of the delay function by mixing the target function and the constraints: L(W, λ) = f (W ) − λT .b(W ). 2. Define and solve the quadratic programming sub-problem to find the step value d: Use the quadratic approximation of the original target function (here f (W )) as the target function of the sub-problem, and use the linear approximation of the constraints as the constraints of the sub-problem. All derivatives of the target function and constraints are numerically extracted as explained before: (a) The target function is then to minimize the quadratic approximation: f (Wk ) + ∇f (Wk )T .d + 12 d T ∇ 2 L(Wk , λk ).d (b) The constraint is: b(Wk ) + ∇b(Wk )T .d ≥ 0. 3. Calculate the widths for the next step: Wk+1 = Wk + d. 4. Evaluate f (Wk+1 ). 5. If the precision |f (Wk+1 ) − f (Wk )| is enough, then the solution is Wk+1 , otherwise go to step 1. As it is shown the method finds the next best step in each iteration by using the gradient of the target function and the constraints. The method first uses the steps as large as the gradient vector of the delay function, and gradually improves the steps with the help of the gradient vectors of the constraints in order to confine the solution to constraints. For more detailed information, please refer to [7]. The first phase reduces the total aging-induced delay degradation of the FF with respect to the constraints. However, if the process variation is considered, the FF may become unstable (due to sensitivity to the variations). Please note that the constraint on maximum sensitivity does not directly reduce σdelay , but tries to limit the maximum variation in delay due to process variation. Hence the resulting σdelay after optimization might be a little higher than before. The second phase of the optimization is performed in order to reduce the effect of process variation. For this purpose, we minimize the sensitivity of the FF to threshold voltage shift due to process variation. In this regard, the target function is the sensitivity function. For

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16 Aging Effects in Sequential Elements

this phase, also the same solver is used with the same area and power constraints as those used for the delay minimization. The only difference is that instead of FF sensitivity, here a limit on the upper bound of FF delay is set (f (W 1)) to prevent any increase in the delay at the end of the second phase. Therefore, after the second optimization phase, FF has less sensitivity to process variation but with the same delay compared to the FF obtained from the first phase. Table 16.1 summarizes the two-phase optimization approach.

16.4.3 Results

# occurrences

We use Cadence Virtuoso Liberate [17] to characterize the timing and power of FFs, and SciPy [15] as the optimizer tool. The optimization is carried out for a specific temperature corner (125 ◦ C) and worst case for voltage droop (10%) and worst case input signal probabilities of 0.1 and 0.9. It should be pointed out that the optimization flow is independent of these conditions and the FF can be optimized for any corner using our approach. Figure 16.6 shows the histogram of a C2MOS FF delay for three cases: (1) before optimization, in which the optimized FF sizing for PDP is used, (2) after the first phase in which the post-aging delay is minimized, and (3) after the second phase which also reduces the sensitivity. It is clearly shown that in the first phase the histogram is pushed to the left, but in the second phase the deviation of the distribution is reduced. We applied the presented method to all six aforementioned FFs but we present the results for SDFF, C2MOS, and SAFF as the representatives. The results of other FFs also show similar improvements. The results are shown in Table 16.2. The area

180 160 140 120 100 80 60 40 20 0

delay minimized original sensitivity minimized

C2MOS FF (22NM) T = 125°C VDD = 90% 150

200

250

300

350

400

450

500

d-q (ps) Fig. 16.6 Histogram of worst-case delay for a C2MOS FF before optimization, after delay minimization (first phase), and after sensitivity minimization (second phase at 22 nm). The histogram is pushed to the left by delay minimization, and is made thinner after sensitivity minimization [4]

References

355

Table 16.2 FF characteristics before and after optimization Parameter Leakage power (nW) Delay (ps) μdelay (ps) σdelay (ps) Timing failure

SDFF C2MOS FF SAFF Before After Before After Before After 418.3 516.4 (+23.5%) 181.1 224.0 (+23.7%) 321.5 408.5 (+26.9%) 29.2 26.3 (−9.9%) 154.5 55.7 46.0 (−17.5%) 291.2 9.0 9.3 (+3.2%) 59.6 97.4% 53.5% 95.9%

92.8 (−39.9%) 53.1 36.4 (−31.4%) 175.5 (−39.7%) 97.0 62.1 (−36%) 19.2 (−67.7%) 7.9 4.0 (−49.4%) 2.5% 100% 0.5%

Leakage power and delay values are extracted without considering any variation. μdelay , σdelay , and timing failures are extracted considering all variations [4]

overhead is set to 20%. As shown in this table, the mean and standard deviation of the FF delay (and as a result timing failure) can be significantly reduced at the expense of less than 30% leakage power overhead. The entire optimization of a C2MOS FF with 24 transistors (which is indeed a big FF) could take up to 3 h, because in each step it needs to characterize the FF and extract the delay and total sensitivity of the FF for different working conditions.

16.5 Summary In this chapter, we performed a comparative analysis of flip-flops under various sources of process and runtime variations. This analysis shows that FFs have different sensitivities to the sources of variations and it reveals the corners where a particular flip-flop design is very vulnerable. With the help of this framework, we are able to optimize FF design under process and runtime variations. With the cost of 20% area and up to 30% power consumption overhead, we are able to reduce the timing failures of FFs at least by 43.9% in SDFF and up to 99.5% in SAFF.

References 1. H. Abrishami, S. Hatami, M. Pedram, Design and multicorner optimization of the energy-delay product of CMOS flip-flops under the negative bias temperature instability effect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6), 869–881 (2013) 2. S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, Predictive modeling of the NBTI effect for reliable design, in IEEE Custom Integrated Circuits Conference (IEEE, Piscataway, 2006), pp. 189–192 3. F. Firouzi, S. Kiamehr, M. Tahoori, S. Nassif, Incorporating the impacts of workload-dependent runtime variations into timing analysis, in Design, Automation & Test in Europe Conference & Exhibition (DATE) (IEEE, Piscataway, 2013), pp. 1022–1025

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4. M.S. Golanbari, S. Kiamehr, M.B. Tahoori, S. Nassif, Analysis and optimization of flipflops under process and runtime variations, in 2015 16th International Symposium on Quality Electronic Design (ISQED) (IEEE, Piscataway, 2015), pp. 191–196 5. Y.-M. Jiang, K.-T. Cheng, Analysis of performance impact caused by power supply noise in deep submicron devices, in Proceedings 1999 Design Automation Conference, DAC (IEEE, Piscataway, 1999), pp. 760–765 6. W. Kim, Y.H. Kim, Improving the process variation tolerability of flip-flops for UDSM circuit design, in 2010 11th International Symposium on Quality Electronic Design (ISQED) (IEEE, Piscataway, 2010), pp. 812–817 7. D. Kraft, A Software Package for Sequential Quadratic Programming. Deutsche Forschungsund Versuchsanstalt für Luft- und Raumfahrt Köln: Forschungsbericht (Berichtswesen d. DFVLR, Wiss 1988) 8. K.J. Kuhn, Reducing Variation in advanced logic technologies: approaches to process and design for manufacturability of nanoscale CMOS, in 2007 IEEE International Electron Devices Meeting, IEDM (IEEE, Piscataway, 2007), pp. 471–474 9. K.J. Kuhn, M.D. Giles, D. Becher, P. Kolar, A. Kornfeld, R. Kotlyar, S.T. Ma, A. Maheshwari, S. Mudanai, Process technology variation. IEEE Trans. Electron Devices 58(8), 2197–2208 (2011) 10. M. Lanuzza, R.D. Rose, F. Frustaci, S. Perri, P. Corsonello, Comparative analysis of yield optimized pulsed flip-flops. Microelectron. Reliab. 52(8), 1679–1689 (2012) 11. S. Nassif, K. Bernstein, D.J. Frank, A. Gattiker, W. Haensch, B. L. Ji, E. Nowak, D. Pearson, N.J. Rohrer, High Performance CMOS variability in the 65 nm regime and beyond, in IEDM (2007), pp. 569–571 12. C. Nunes, P.F. Butzen, A.I. Reis, R.P. Ribas, BTI, HCI and TDDB aging impact in flip-flops. Microelectron. Reliab. 53(9), 1355–1359 (2013) 13. Predictive Technology Model. http://www.eas.asu.edu/~ptm/ 14. V. Rao, H. Mahmoodi, Analysis of reliability of flip-flops under transistor aging effects in nanoscale CMOS technology, in 2011 IEEE 29th International Conference on Computer Design (ICCD) (IEEE, Piscataway, 2011), pp. 439–440 15. SciPy: Open source scientific tools for Python. http://www.scipy.org 16. V. Stojanovic and V. Oklobdzija, Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. IEEE J. Solid State Circuits 34(4), 536–548 (1999) 17. Virtuoso liberate characterization solution. http://www.cadence.com/products/cic/liberate 18. W. Wang, S. Yang, S. Bhardwaj, S. Vrudhula, F. Liu, Y. Cao, The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis. IEEE Trans. Very Large Scale Integr. VLSI Syst. 18(2), 173–183 (2010)

Chapter 17

Aging Guardband Reduction Through Selective Flip-Flop Optimization

17.1 Introduction Modern VLSI circuits are influenced by several sources of process and runtime variabilities, including transistor aging [7]. Therefore, it is necessary to employ techniques to consider and control the gradual degradations and mismatches during design time, e.g. by adding appropriate timing margins (aging guardband) and incorporating mitigation techniques [10, 15]. Accordingly, the degradation of FFs and latches, as the sequential elements of the circuits responsible for storing and transferring the state of the circuit with clock ticks, needs to be addressed and mitigated. Particular aspects of FFs e.g. internal feedback structure, can lead to serious timing degradation or even functional failure (inability to capture the input disregard of its timing) [13]. In this regard, there are some studies on the impact of BTI on FFs [1, 5, 11, 14]. For example, [1] proposes a method to improve FF reliability for a set of corners with different working conditions such as temperatures and voltages by altering the sizing of transistors. These studies mostly optimize FFs for dynamic BTI stress condition. However, the FFs operating under static BTI stress as well as near-static BTI stress condition (i.e., when the FF input SP is near 0.0 or 1.0), which experience large timing degradation, are mostly overlooked. As we will show later in this chapter, the traditional optimization techniques such as optimization for the PowerDelay Product (PDP) cannot effectively reduce the delay increase of FFs under such stress. Furthermore, in a typical digital design such as a microprocessor, based on the functionality of different components, some FFs operate under static or near-static BTI stress, irrespective of the workload. Since the synthesis tool balances most path delays to achieve the best performance, area, and power, the timing of almost all FFs are critical. Being subject to severe BTI stress, the aforementioned FFs degrade faster, enforcing a large aging guardband to the entire circuit. Therefore, by treating such FFs differently, i.e., optimizing them under severe BTI stress, the overall aging guardband for the entire circuit can be reduced at minimal cost. © Springer Nature Switzerland AG 2019 S. Tan et al., Long-Term Reliability of Nanometer VLSI Systems, https://doi.org/10.1007/978-3-030-26172-6_17

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In this chapter, we present a technique to improve the reliability of FFs suffering from severe BTI stress. The idea is to selectively re-optimize the design of FFs under severe BTI stress by appropriately sizing their transistors. This is done by adding aging-resilient versions of FF cells in the library, optimized for different aging corners, and only replacing the instances in the design under severe BTI stress with such resilient FF cells. This aging resilience comes at the cost of a considerable leakage overhead per FF. However, since the aging hardening is done selectively only for those FFs under severe BTI stress, and they constitute a very small percentage of total FFs in the circuit, the impact on the overall circuit power is minimal. So overall, this approach can drastically reduce the aging guardband with minimal overheads. Also, the overall FF area is kept untouched, by which the aspect ratio can also be kept the same, such that the FFs can be easily replaced in the circuit layout, even in the final design stages. This makes the method viable in the existing design flow without the need to do the place and route again. Optimization results show that the FFs optimized with the proposed method exhibit much less delay degradation, while imposing less than 0.81% overhead to the total leakage of a processor. According to the results, the timing guardband of a processor using the proposed method is saved by 22.8% compared to the original processor, which means longer lifetime and better reliability. The rest of the chapter is organized as follows. Section 17.2 explains the required background. In Sect. 17.3, the motivation for the work presented in this chapter is presented. Section 17.4 describes the methodology to perform the optimization, and in Sect. 17.5 the results of the optimization method will be shown. Finally, Sect. 17.6 concludes the chapter.

17.2 Background FF timing metrics such as setup-time (U ), hold-time (H ), clock-to-q (DCQ ), and data-to-q(DDQ ) are well discussed in [16]. When the setup-time is large enough, the clock-to-q value is almost constant, but further reduction of the setup-time will increase the clock-to-q value monotonously until a value after which the FF is unable to capture and latch the input [16]. Based on this, the optimum setup-time is defined as the setup-time value which causes the clock-to-q value to increase by 10% from its minimum value [17]. Moreover, each FF has two internal paths; one for transferring the input state “zero” to the output, i.e., High-to-Low (HL) input transition, and the other for transferring the input state “one” to the output, i.e., Low-to-High (LH) input transition. Basically, the timing parameters for these two paths can be different [13] as shown in Fig. 17.1, meaning that there are two sets of timing parameters for LH and HL paths: {ULH , DCQLH , DDQLH } for LH transition, and {UHL , DCQHL , DDQHL } for HL transition. FF delay should be defined such that the correct functionality of the FF will be guaranteed, disregard of the transition. Therefore, we define the FF delay as the summation of the worst setup-time and the worst clock-to-q of both transitions as shown in Fig. 17.1. The worst setup-time

17.3 Flip-Flops Under Static and Near-Static BTI Stress

359

Fig. 17.1 Different FF timing parameters. The correct functionality is guaranteed by considering the FF delay as illustrated [6]

guarantees that the input signal is captured in both transitions, and the worst clockto-q assures that the output signal is propagated to the FF output.

17.3 Flip-Flops Under Static and Near-Static BTI Stress In this section, first, we present an overview on FF aging due to static and near-static BTI stress (to which we refer to as S-BTI from now on). Afterward, we motivate our work by demonstrating that a considerable number of FFs in a processor operate under S-BTI. Then we will discuss the overall approach to reduce the delay degradation of the circuit by optimizing FFs operating under S-BTI.

17.3.1 Aging of Flip-Flops While parameters such as temperature and voltage affect the entire FF similarly, the impact of the input SP is different for FF transistors. This may lead to an asymmetric aging of FF transistors according to their duty cycles. As a result, the delay degradation of LH and HL paths of the aged FF depends on the input SP [13]. Figure 17.2a illustrates the delay of LH and HL transitions of an aged C2MOS FF [16] for different input SPs. As shown in this figure, the worst delay degradation happens for both HL and LH transitions when input SP is 0.0 (SP0) and 1.0 (SP1), respectively. The reason is that in both cases some transistors are under S-BTI, which results in a high degradation. Moreover, in these conditions, BTI alters the threshold voltages asymmetrically which leads to unbalanced aging of LH and HL paths of FF. As depicted in Fig. 17.2b, LH and HL paths consist

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17 Aging Guardband Reduction Through Selective Flip-Flop Optimization

Fig. 17.2 (a) Delay of LH/HL paths of an aged C2MOS FF (optimized for PDP in the fresh state) for different input SPs. (b) Separate LH (red)/HL (blue) paths of the FF [6]

of two separate groups of transistors, which makes the aging of these two paths independent according to their SP values. The unbalanced aging of HL and LH paths is clearly shown in Fig. 17.3 for the same FF for a period of 5 years. When the FF is aged under SP0, the delay of LH path slightly increases while the delay of HL path significantly increases. In this case (the delays of LH and HL paths are similar), the path with higher degradation rate eventually becomes dominant and determines the total delay of the FF. On the other hand, if the path with higher degradation rate, is initially faster than the path with lower degradation rate, the dominant path would be the slower one, and hence the higher degradation rate of the faster path is masked. Therefore, the overall aging of the FF would be rather small. The optimized FF shown in Fig. 17.3 exhibits such characteristics. At the end, the delay of this FF would increase by ∼10 ps, which is much lower than the delay increase of the original FF (which is ∼40 ps).

17.3 Flip-Flops Under Static and Near-Static BTI Stress

160

FF data-to-q (ps)

150 140

LH DDQ HL DDQ LH DDQ HL DDQ

361

(ORIGINAL) (ORIGINAL) (OPTIMIZED) (OPTIMIZED)

130 120 110 100 90 10−8

10−7

10−6

10−5

10−4

10−3

10−2

10−1

100

101

time (year) Fig. 17.3 Delay of a C2MOS FF which is aged under SP = 0 over 5 years for LH/HL transitions, compared to the FF optimized for SP = 0 showing how the unbalanced aging of LH/HL paths worsens the degradation in original FF [6]

17.3.2 Problem Statement As mentioned in the previous subsection, a FF experiences higher aging rate when it is under S-BTI. In order to investigate the likelihood of having such a scenario in a typical digital design, we extracted the distribution of the signal probability of FFs in Leon3 processor executing six MiBench workloads namely stringsearch, qsort, basicmath, bitcount, fft, and crc32. In this regard, the processor is first synthesized with respect to a standard cell library and then each workload is executed during post-synthesis simulation. The signal probabilities of FFs are extracted from the simulation outputs. In order to be fair, we excluded the FFs belonging to the parts which are not exercised by the employed workloads including interrupt handler, timers, UART controller, etc. The synthesized netlist of the Leon3 processor has 2352 FFs, but the results demonstrated in this section are only for 1686 FFs belonging to the parts which are exercised by all employed workloads. Figure 17.4 demonstrates the signal probability distribution of the aforementioned 1686 flip-flops. The results shows that the input SP value of 181 FFs is always 0, while the SP value of the remaining 29 FFs is always 1. Our analysis shows that the FFs with such behavior typically belong to either the error checking and exception handling registers or higher bits of address registers which are constant due to temporal and spatial locality of executed instructions. Besides, the SP of a considerable number of FFs is very close to either 0 or 1. Please note that the results reported in Fig. 17.4 is the average of six employed workloads and hence, the FFs with SP of 0 or 1 have such SP across all workloads. Similar experiment has been carried out in [8] to study the impact of workload in real systems, which shows that some FFs are always under S-BTI across different workloads.

17 Aging Guardband Reduction Through Selective Flip-Flop Optimization

# of Flip-flops

600

38 delay increase

500

36 34

400

32

300

30

200

28

100

26

0

24

SP

=0

0