Laboratory manual for pulse-width modulated DC-DC power converters [Second edition] 9781119009597, 1119009596, 9781119052753, 1119052750, 9781119009542

Table of contents :
Content: Preface ix Acknowledgments xiii List of Symbols xv Part I OPEN-LOOP PULSE-WIDTH MODULATED DC DC CONVERTERS STEADY-STATE AND PERFORMANCE ANALYSIS AND SIMULATION OF CONVERTER TOPOLOGIES 1 Boost DC DC Converter in CCM Steady-State Simulation 3 2 Efficiency and DC Voltage Transfer Function of PWM Boost DC DC Converter in CCM 7 3 Boost DC DC Converter in DCM Steady-State Simulation 11 4 Efficiency and DC Voltage Transfer Function of PWM Boost DC DC Converter in DCM 15 5 Open-Loop Boost AC DC Power Factor Corrector Steady-State Simulation 19 6 Buck DC DC Converter in CCM Steady-State Simulation 23 7 Efficiency and DC Voltage Transfer Function of PWM Buck DC DC Converter in CCM 27 8 Buck DC DC Converter in DCM Steady-State Simulation 31 9 Efficiency and DC Voltage Transfer Function of PWM Buck DC DC Converter in DCM 35 10 High-Side Gate-Drive Circuit for Buck DC DC Converter 39 11 Quadratic Buck DC DC Converter in CCM Steady-State Simulation 41 12 Buck Boost DC DC Converter in CCM Steady-State Simulation 45 13 Efficiency and DC Voltage Transfer Function of PWM Buck Boost DC DC Converter in CCM 49 14 Buck Boost DC DC Converter in DCM Steady-State Simulation 53 15 Efficiency and DC Voltage Transfer Function of PWM Buck Boost DC DC Converter in DCM 57 16 Flyback DC DC Converter in CCM Steady-State Simulation 61 17 Efficiency and DC Voltage Transfer Function of PWM Flyback DC DC Converters in CCM 65 18 Multiple-Output Flyback DC DC Converter in CCM 69 19 Flyback DC DC Converter in DCM Steady-State Simulation 73 20 Efficiency and DC Voltage Transfer Function of PWM Flyback DC DC Converter in DCM 77 21 Forward DC DC Converter in CCM Steady-State Simulation 81 22 Efficiency and DC Voltage Transfer Function of PWM Forward DC DC Converter in CCM 85 23 Forward DC DC Converter in DCM Steady-State Simulation 89 24 Efficiency and DC Voltage Transfer Function of PWM Forward DC DC Converter in DCM 93 25 Half-Bridge DC DC Converter in CCM Steady-State Simulation 97 26 Efficiency and DC Voltage Transfer Function of PWM Half-Bridge DC DC Converter in CCM 101 27 Full-Bridge DC DC Converter in CCM Steady-State Simulation 105 28 Efficiency and DC Voltage Transfer Function of PWM Full-Bridge DC DC Converters in CCM 109 Part II CLOSED-LOOP PULSE-WIDTH MODULATED DC DC CONVERTERS TRANSIENT ANALYSIS, SMALL-SIGNAL MODELING, AND CONTROL 29 Design of the Pulse-Width Modulator and the PWM Boost DC DC Converter in CCM 115 30 Dynamic Analysis of the Open-Loop PWM Boost DC DC Converter in CCM for Step Change in the Input Voltage, Load Resistance, and Duty Cycle 119 31 Open-Loop Control-to-Output Voltage Transfer Function of the Boost Converter in CCM 123 32 Root Locus and 3D Plot of the Control-to-Output Voltage Transfer Function 129 33 Open-Loop Input-to-Output Voltage Transfer Function of the Boost Converter in CCM 133 34 Open-Loop Small-Signal Input and Output Impedances of the Boost Converter in CCM 137 35 Feedforward Control of the Boost DC DC Converter in CCM 141 36 P, PI, and PID Controller Design 145 37 P, PI, and PID Controllers: Bode and Transient Analysis 149 38 Transfer Functions of the Pulse-Width Modulator, Boost Converter Power Stage, and Feedback Network 153 39 Closed-Loop Control-to-Output Voltage Transfer Function with Unity-Gain Control 157 40 Simulation of the Closed-Loop Boost Converter with Proportional Control 161 41 Voltage-Mode Control of Boost DC DC Converter with Integral-Double-Lead Controller 165 42 Control-to-Output Voltage Transfer Function of the Open-Loop Buck DC DC Converter 169 43 Voltage-Mode Control of Buck DC DC Converter 173 44 Feedforward Control of the Buck DC DC Converter in CCM 179 Part III SEMICONDUCTOR MATERIALS AND POWER DEVICES 45 Temperature Dependence of Si and SiC Semiconductor Materials 187 46 Dynamic Characteristics of the PN Junction Diode 191 47 Characteristics of the Silicon and Silicon-Carbide PN Junction Diodes 195 48 Analysis of the Output and Switching Characteristics of Power MOSFETs 199 49 Short-Channel Effects in MOSFETs 201 50 Gallium-Nitride Semiconductor: Material Properties 205 APPENDICES 209 A Design Equations for Continuous-Conduction Mode 211 B Design Equations for Discontinuous-Conduction Mode 215 C Simulation Tools 219 D MOSFET Parameters 231 E Diode Parameters 233 F Selected MOSFETs Spice Models 235 G Selected Diodes Spice Models 237 H Physical Constants 239 I Format of Lab Report 241 Index 245

Citation preview

Pulse-Width Modulated DC–DC Power Converters Second Edition

MARIAN K. KAZIMIERCZUK Wright State University, Dayton, Ohio, USA

This edition first published 2016 © 2016 John Wiley & Sons, Ltd Registered office John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom For details of our global editorial offices, for customer services and for information about how to apply for permission to reuse the copyright material in this book please see our website at www.wiley.com. The right of the author to be identified as the author of this work has been asserted in accordance with the Copyright, Designs and Patents Act 1988. All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by the UK Copyright, Designs and Patents Act 1988, without the prior permission of the publisher. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic books. Designations used by companies to distinguish their products are often claimed as trademarks. All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners. The publisher is not associated with any product or vendor mentioned in this book. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. It is sold on the understanding that the publisher is not engaged in rendering professional services and neither the publisher nor the author shall be liable for damages arising herefrom. If professional advice or other expert assistance is required, the services of a competent professional should be sought Library of Congress Cataloging-in-Publication Data Kazimierczuk, Marian K.  Pulse-width modulated DC–DC power converters / Marian K. Kazimierczuk. – Second edition.    pages cm  Includes bibliographical references and index.  ISBN 978-1-119-00954-2 (cloth)  1. DC-to-DC converters. 2. Pulse circuits. 3. PWM power converters. I. Title.  TK7872.C8K387 2015  621.381′044–dc23 2015018212 A catalogue record for this book is available from the British Library. ISBN: 9781119009542

To my wife Alicja

CONTENTS About the Author Preface Nomenclature 1: Introduction 1.1 Classification of Power Supplies 1.2 Basic Functions of Voltage Regulators 1.3 Power Relationships in DC–DC Converters 1.4 DC Transfer Functions of DC–DC Converters 1.5 Static Characteristics of DC Voltage Regulators 1.6 Dynamic Characteristics of DC Voltage Regulators 1.7 Linear Voltage Regulators 1.8 Topologies of PWM DC–DC Converters 1.9 Relationships Among Current, Voltage, Energy, and Power 1.10 Summary References Review Questions Problems 2: Buck PWM DC–DC Converter 2.1 Introduction 2.2 DC Analysis of PWM Buck Converter for CCM 2.3 DC Analysis of PWM Buck Converter for DCM 2.4 Buck Converter with Input Filter 2.5 Buck Converter with Synchronous Rectifier 2.6 Buck Converter with Positive Common Rail 2.7 Quadratic Buck Converter 2.8 Tapped-Inductor Buck Converters 2.9 Multiphase Buck Converter 2.10 Switched-Inductor Buck Converter 2.11 Layout 2.12 Summary References

Review Questions Problems 3: Boost PWM DC–DC Converter 3.1 Introduction 3.2 DC Analysis of PWM Boost Converter for CCM 3.3 DC Analysis of PWM Boost Converter for DCM 3.4 Bidirectional Buck and Boost Converters 3.5 Synchronous Boost Converter 3.6 Tapped-Inductor Boost Converters 3.7 Duality 3.8 Power Factor Correction 3.9 Summary References Review Questions Problems 4: Buck–Boost PWM DC–DC Converter 4.1 Introduction 4.2 DC Analysis of PWM Buck–Boost Converter for CCM 4.3 DC Analysis of PWM Buck–Boost Converter for DCM 4.4 Bidirectional Buck–Boost Converter 4.5 Synthesis of Buck–Boost Converter 4.6 Synthesis of Boost–Buck (Ćuk) Converter 4.7 Noninverting Buck–Boost Converters 4.8 Tapped-Inductor Buck–Boost Converters 4.9 Summary References Review Questions Problems 5: Flyback PWM DC–DC Converter 5.1 Introduction 5.2 Transformers 5.3 DC Analysis of PWM Flyback Converter for CCM 5.4 DC Analysis of PWM Flyback Converter for DCM 5.5 Multiple-Output Flyback Converter

5.6 Bidirectional Flyback Converter 5.7 Ringing in Flyback Converter 5.8 Flyback Converter with Passive Dissipative Snubber 5.9 Flyback Converter with Zener Diode Voltage Clamp 5.10 Flyback Converter with Active Clamping 5.11 Two-Transistor Flyback Converter 5.12 Summary References Review Questions Problems 6: Forward PWM DC–DC Converter 6.1 Introduction 6.2 DC Analysis of PWM Forward Converter for CCM 6.3 DC Analysis of PWM Forward Converter for DCM 6.4 Multiple-Output Forward Converter 6.5 Forward Converter with Synchronous Rectifier 6.6 Forward Converters with Active Clamping 6.7 Two-Switch Forward Converter 6.8 Forward–Flyback Converter 6.9 Summary References Review Questions Problems 7: Half-Bridge PWM DC–DC Converter 7.1 Introduction 7.2 DC Analysis of PWM Half-Bridge Converter for CCM 7.3 DC Analysis of PWM Half-Bridge Converter for DCM 7.4 Summary References Review Questions Problems 8: Full-Bridge PWM DC–DC Converter 8.1 Introduction 8.2 DC Analysis of PWM Full-Bridge Converter for CCM

8.3 DC Analysis of PWM Full-Bridge Converter for DCM 8.4 Phase-Controlled Full-Bridge Converter 8.5 Summary References Review Questions Problems 9: Small-Signal Models of PWM Converters for CCM and DCM 9.1 Introduction 9.2 Assumptions 9.3 Averaged Model of Ideal Switching Network for CCM 9.4 Averaged Values of Switched Resistances 9.5 Model Reduction 9.6 Large-Signal Averaged Model for CCM 9.7 DC and Small-Signal Circuit Linear Models of Switching Network for CCM 9.8 Block Diagram of Small-signal Model of PWM DC–DC Converters 9.9 Family of PWM Converter Models for CCM 9.10 PWM Small-Signal Switch Model for CCM 9.11 Modeling of Ideal Switching Network for DCM 9.12 Averaged Parasitic Resistances for DCM 9.13 Summary References Review Questions Problems 10: Small-Signal Characteristics of Buck Converter for CCM 10.1 Introduction 10.2 Small-Signal Model of the PWM Buck Converter 10.3 Open-Loop Transfer Functions 10.4 Open-Loop Step Responses 10.5 Open-Loop DC Transfer Functions 10.6 Summary References Review Questions Problems 11: Small-Signal Characteristics of Boost Converter for CCM

11.1 Introduction 11.2 DC Characteristics 11.3 Open-Loop Control-to-Output Transfer Function 11.4 Delay in Open-Loop Control-to-Output Transfer Function 11.5 Open-Loop Audio Susceptibility 11.6 Open-Loop Input Impedance 11.7 Open-Loop Output Impedance 11.8 Open-Loop Step Responses 11.9 Summary References Review Questions Problems 12: Voltage-Mode Control of PWM Buck Converter 12.1 Introduction 12.2 Properties of Negative Feedback 12.3 Stability 12.4 Single-Loop Control of PWM Buck Converter 12.5 Closed-Loop Small-Signal Model of Buck Converter 12.6 Pulse-Width Modulator 12.7 Feedback Network 12.8 Transfer Function of Buck Converter with Modulator and Feedback Network 12.9 Control Circuits 12.10 Closed-Loop Step Responses 12.11 Summary References Review Questions Problems 13: Voltage-Mode Control of Boost Converter 13.1 Introduction 13.2 Circuit of Boost Converter with Voltage-Mode Control 13.3 Transfer Function of Modulator, Boost Converter Power Stage, and Feedback Network 13.4 Integral-Double-Lead Controller 13.5 Design of Integral-Double-Lead Controller

13.6 Loop Gain 13.7 Closed-Loop Control-to-Output Voltage Transfer Function 13.8 Closed-Loop Audio Susceptibility 13.9 Closed-Loop Input Impedance 13.10 Closed-Loop Output Impedance 13.11 Closed-Loop Step Responses 13.12 Closed-Loop DC Transfer Functions 13.13 Summary References Review Questions Problems 14: Current-Mode Control 14.1 Introduction 14.2 Principle of Operation of PWM Converters with Peak CMC 14.3 Relationship Between Duty Cycle and Inductor-Current Slopes 14.4 Instability of Closed-Current Loop 14.5 Slope Compensation 14.6 Sample-and-Hold Effect on Current Loop 14.7 Closed-Loop Control Voltage-to-Inductor Current Transfer Function in s-Domain 14.8 Loop Gain of Current Loop 14.9 Gain-Crossover Frequency of Inner Loop 14.10 Phase Margin of Inner Loop 14.11 Maximum Duty Cycle for Converters Without Slope Compensation 14.12 Maximum Duty Cycle for Converters with Slope Compensation 14.13 Minimum Slope Compensation for Buck and Buck–Boost Converter 14.14 Minimum Slope Compensation for Boost Converter 14.15 Error Voltage-to-Duty Cycle Transfer Function 14.16 Closed-Loop Control Voltage-to-Duty Cycle Transfer Function of Current Loop 14.17 Alternative Representation of Current Loop 14.18 Current Loop with Disturbances 14.19 Voltage Loop of PWM Converters with Current-Mode Control 14.20 Feedforward Gains in PWM Converters with Current-Mode Control without Slope Compensation 14.21 Feedforward Gains in PWM Converters with Current-Mode Control and Slope

Compensation 14.22 Control-to-Output Voltage Transfer Function of Inner Loop with Feedforward Gains 14.23 Audio-Susceptibility of Inner Loop with Feedforward Gains 14.24 Closed-Loop Transfer Functions with Feedforward Gains 14.25 Slope Compensation by Adding a Ramp to Inductor Current Waveform 14.26 Relationships for Constant-Frequency Current-Mode On-Time Control 14.27 Summary References Review Questions Problems 14.28 Appendix: Sample-and-Hold Modeling 15: Current-Mode Control of Boost Converter 15.1 Introduction 15.2 Open-Loop Small-Signal Transfer Functions 15.3 Open-Loop Step Responses of Inductor Current 15.4 Closed-Current-Loop Transfer Functions 15.5 Closed-Voltage-Loop Transfer Functions 15.6 Closed-Loop Step Responses 15.7 Closed-Loop DC Transfer Functions 15.8 Summary References Review Questions Problems 16: Open-Loop Small-Signal Characteristics of PWM Boost Converter for DCM 16.1 Introduction 16.2 Small-Signal Model of Boost Converter for DCM 16.3 Open-Loop Control-to-Output Transfer Function 16.4 Open-Loop Input-to-Output Voltage Transfer Function 16.5 Open-Loop Input Impedance 16.6 Open-Loop Output Impedance 16.7 Step Responses of Output Voltage of Boost Converter for DCM 16.8 Open-Loop Duty Cycle-to-Inductor Current Transfer Function 16.9 Open-Loop Input Voltage-to-Inductor Current Transfer Function

16.10 Open-Loop Output Current-to-Inductor Current Transfer Function 16.11 Step Responses of Inductor Current of Boost Converter for DCM 16.12 DC Characteristics of Boost Converter for DCM 16.13 Summary References Review Questions Problems 17: Silicon and Silicon-Carbide Power Diodes 17.1 Introduction 17.2 Electronic Power Switches 17.3 Atom 17.4 Electron and Hole Effective Mass 17.5 Semiconductors 17.6 Intrinsic Semiconductors 17.7 Extrinsic Semiconductors 17.8 Wide Band Gap Semiconductors 17.9 Physical Structure of Junction Diodes 17.10 Static I–V Diode Characteristic 17.11 Breakdown Voltage of Junction Diodes 17.12 Capacitances of Junction Diodes 17.13 Reverse Recovery of pn Junction Diodes 17.14 Schottky Diodes 17.15 Solar Cells 17.16 Light-Emitting Diodes 17.17 SPICE Model of Diodes 17.18 Summary References Review Questions Problems Note 18: Silicon and Silicon-Carbide Power MOSFETs 18.1 Introduction 18.2 Integrated MOSFETs 18.3 Physical Structure of Power MOSFETs

18.4 Principle of Operation of Power MOSFETs 18.5 Derivation of Power MOSFET Characteristics 18.6 Power MOSFET Characteristics 18.7 Mobility of Charge Carriers 18.8 Short-Channel Effects 18.9 Aspect Ratio of Power MOSFETs 18.10 Breakdown Voltage of Power MOSFETs 18.11 Gate Oxide Breakdown Voltage of Power MOSFETs 18.12 Specific On-Resistance 18.13 Figures-of-Merit of Semiconductors 18.14 On-Resistance of Power MOSFETs 18.15 Capacitances of Power MOSFETs 18.16 Switching Waveforms 18.17 SPICE Model of Power MOSFETs 18.18 IGBTs 18.19 Heat Sinks 18.20 Summary References Review Questions Problems 19: Electromagnetic Compatibility 19.1 Introduction 19.2 Definition of EMI 19.3 Definition of EMC 19.4 EMI Immunity 19.5 EMI Susceptibility 19.6 Classification of EMI 19.7 Sources of EMI 19.8 Safety Standards 19.9 EMC Standards 19.10 Near Field and Far Field 19.11 Techniques of EMI Reduction 19.12 Insertion Loss 19.13 EMI Filters

19.14 Feed-Through Capacitors 19.15 EMI Shielding 19.16 Interconnections 19.17 Summary References Review Questions Problem Appendices A: Introduction to SPICE B: Introduction to MATLAB® C: Physical Constants Answers to Problems Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 Chapter 7 Chapter 8 Chapter 9 Chapter 10 Chapter 11 Chapter 12 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Chapter 18 Index EULA

List of Tables

Chapter 9 Table 9.1 Chapter 17 Table 17.1 Table 17.2 Table 17.3 Table 17.4 Chapter 18 Table 18.1 Appendix C Table A.1

List of Illustrations Chapter 1 Figure 1.1 Classification of power supply technologies. Figure 1.2 Block diagrams of ac–dc power supplies. (a) With a linear regulator. (b) With a switching-mode voltage regulator. Figure 1.3 Zener diode voltage regulator. Figure 1.4 Block diagram of a voltage regulator with negative feedback. Figure 1.5 A dc model of a dc–dc converter. Figure 1.6 Output voltage Vo versus input voltage VI for voltage regulators illustrating line regulation. Figure 1.7 Output voltage VO versus output current IO for voltage regulators illustrating load regulation. Figure 1.8 DC model of voltage source with an output resistance. Figure 1.9 Circuit for testing the line transient response of voltage regulators. Figure 1.10 Waveforms illustrating line transient response of voltage regulators. (a) Waveform of the input voltage vI. (b) Waveform of the output voltage vO. Figure 1.11 Circuit for testing the transient response to a sudden electrical load change using an active current sink. Figure 1.12 Waveforms illustrating load transient response of voltage regulators. (a)

Waveform of the load current iO. (b) Waveform of the output voltage vO. Figure 1.13 Circuit for testing the load transient response with a switched load resistance from R1 to R1||R2 using a MOSFET. Figure 1.14 Voltage–current characteristic of a constant power source. Figure 1.15 Basic circuits of linear voltage regulators. (a) Series voltage regulator. (b) Shunt voltage regulator. Figure 1.16 Typical low drop-out (LDO) voltage regulator topology. Figure 1.17 Single-ended PWM dc–;dc nonisolated and isolated converters. Figure 1.18 Multiple-switch isolated PWM dc–dc converters. Chapter 2 Figure 2.1 PWM buck converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. Figure 2.2 Idealized current and voltage waveforms in the PWM buck converter for CCM. Figure 2.3 Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax. Figure 2.4 Normalized load current IOB/(VO/2fsL) at the boundary between CCM and DCM as a function of the duty cycle D for buck converter. Figure 2.5 Normalized load resistance RLB/(2fsL) at the boundary between CCM and DCM as a function of the duty cycle D for buck converter. Figure 2.6 Magnitude of the capacitor impedance. Figure 2.7 Phase of the capacitor impedance. Figure 2.8 Model of the output circuit of the buck converter for frequencies lower than the self-resonant frequency of the filter capacitor. Figure 2.9 Waveforms illustrating the ripple voltage in the PWM buck converter. Figure 2.10 Waveforms of vc, vrc, and vo at three values of the filter capacitor for CCM. (a) C < Cmin. (b) C = Cmin. (c) C > Cmin. Figure 2.11 Equivalent circuit of the buck converter with parasitic resistances and the diode offset voltage. Figure 2.12 Efficiency η of the designed buck converter as a function of dc input voltage VI for CCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. Figure 2.13 Duty cycle D of the designed buck converter as a function of dc input

voltage VI for CCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. Figure 2.14 Efficiency η of the designed buck converter as a function of load current IO for CCM at VI = 24 V, 28 V, and 32 V. Figure 2.15 Duty cycle D of the designed buck converter as a function of load current IO for CCM at VI = 24 V, 28 V, and 32 V. Figure 2.16 Efficiency η of the designed buck converter as a function of load resistance RL for CCM at VI = 24 V, 28 V, and 32 V. Figure 2.17 Duty cycle D of the designed buck converter as a function of load resistance RL for CCM at VI = 24 V, 28 V, and 32 V. Figure 2.18 PWM buck converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF. Figure 2.19 Idealized current and voltage waveforms in the PWM buck converter for DCM. Figure 2.20 Duty cycle D as a function of the normalized load current IO/(VO/2fsL) at various values of MV DC for the lossless buck converter. Figure 2.21 Duty cycle D as a function of the normalized load resistance RL/(2fsL) at various values of MV DC for the lossless buck converter. Figure 2.22 DC voltage transfer function MV DC as a function of the normalized load current IO/(VO/2fsL) at fixed values of D for the lossless buck converter. Figure 2.23 DC voltage transfer function MV DC as a function of the normalized load resistance RL/(2fsL) at fixed values of D for the lossless buck converter. Figure 2.24 Waveforms of the inductor current at the boundary between DCM and CCM for VI = VImin and VI = VImax. Figure 2.25 Efficiency η as a function of the DC input voltage VI for the buck converter given in the design example for DCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. Figure 2.26 Duty cycle D as a function of the dc input voltage VI for the buck converter given in the design example for DCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω. Figure 2.27 Efficiency η of the buck converter as a function of the load current IO for DCM at VI = 24 V, 28 V, and 32 V. Figure 2.28 Duty cycle D of the buck converter as a function of the load current IO for

DCM at VI = 24 V, 28 V, and 32 V. Figure 2.29 Efficiency η of the buck converter as a function of load resistance RL for DCM at VI = 24 V, 28 V, and 32 V. Figure 2.30 Duty cycle D of the buck converter as a function of load resistance RL for DCM at VI = 24 V, 28 V, and 32 V. Figure 2.31 Buck converter with an input L1-C1 low-pass filter. Figure 2.32 Buck converter with a synchronous rectifier. (a) With two n-channel MOSFETs. (b) CMOS buck converter. Figure 2.33 Synchronous buck converter with a transformer driver. Figure 2.34 Synchronous buck converter with a voltage mirror driver. Figure 2.35 Efficiency η of the buck converter with synchronous rectifier as a function of the load current IO at VI = 28 V and VO = 12 V. Figure 2.36 Efficiency η of the buck converter with synchronous rectifier as a function of the load resistance RL at VI = 28 V and VO = 12 V. Figure 2.37 Efficiency η of the buck converter with synchronous rectifier as a function of the output power PO at VI = 28 V and VO = 12 V. Figure 2.38 Efficiency η of the buck converter with synchronous rectifier as a function of duty cycle D at fixed RL = 1.2 Ω and VI = 28 V. Figure 2.39 DC voltage transfer function MV DC of the buck converter with synchronous rectifier as a function of duty cycle D at fixed RL = 1.2 Ω and VI = 28 V. Figure 2.40 Derivation of the buck converter topology with the positive common rail. (a) Classical buck converter with a negative common rail. (b) Buck converter with the MOSFET and the inductor moved to the negative branch, resulting in the positive common rail. (c) Buck converter with a positive common rail. Figure 2.41 Topology of the buck converter with the gate referenced to ground and floating output voltage. Figure 2.42 Topology of the buck converter in which both the MOSFET source and the converter output are grounded, but this topology requires a floating power supply. Figure 2.43 Quadratic buck converter. Figure 2.44 Tapped-inductor buck converters. (a) Tapped-inductor common-diode buck converter. (b) Tapped-inductor common-switch buck converter. (c) Watkins– Johnson (common-source) converter. Figure 2.45 DC voltage transfer function of common-diode tapped-inductor buck converter for CCM.

Figure 2.46 DC voltage transfer function of tapped-inductor common-switch buck converter for CCM. Figure 2.47 DC voltage transfer function of Watkins–Johnson (common-source) tappedinductor buck converter for CCM. Figure 2.48 Two-phase buck converter. Figure 2.49 Waveforms in two-phase buck converter. Figure 2.50 Two-phase buck converter with two input capacitors. Figure 2.51 Switched-inductor buck converter. Figure 2.52 DC voltage transfer function of switched-inductor buck converter MV DC as a function of the duty cycle D. Chapter 3 Figure 3.1 PWM boost converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. Figure 3.2 Idealized current and voltage waveforms in the PWM boost converter for CCM. Figure 3.3 Waveform of the inductor current at the boundary between CCM and DCM for the boost converter. Figure 3.4 Normalized load current IOB/(VO/2fsL) at the boundary between CCM and DCM as a function of D for boost converter. Figure 3.5 Normalized load resistance RLB/(2fsL) at the boundary between CCM and DCM as a function of D for boost converter. Figure 3.6 Equivalent circuit of the output part of the boost converter. Figure 3.7 Waveforms illustrating the ripple voltage in the PWM boost converter. Figure 3.8 Equivalent circuit of the boost converter with parasitic resistances and the diode offset voltage. Figure 3.9 Efficiency of the boost converter η versus D for VO = 28 V, rDS = 0.5 Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. Figure 3.10 DC voltage transfer function MVDC of the lossy boost converter as a function of D for CCM at VO = 28 V, rDS = 0.5Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. Figure 3.11 Efficiency η of the designed boost converter as a function of VI at fixed values of RL for CCM.

Figure 3.12 Duty cycle D of the boost converter designed as a function of VI at fixed values of RL for CCM. Figure 3.13 Efficiency η of the designed boost converter as a function of load current IO at fixed values of VI for CCM. Figure 3.14 Duty cycle D of the designed boost converter as a function of load current IO at fixed values of VI for CCM. Figure 3.15 Efficiency η of the designed boost converter as a function of load resistance RL at fixed values of VI for CCM. Figure 3.16 Duty cycle D of the designed boost converter as a function of load resistance RL at fixed values of VI for CCM. Figure 3.17 PWM boost converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF. Figure 3.18 Idealized current and voltage waveforms in the PWM boost converter for DCM. Figure 3.19 Duty cycle D as a function of normalized load current IO/(VO/2fsL) at various values of MVDC for the lossless boost converter. Figure 3.20 Duty cycle D as a function of normalized load resistance RL/(2fsL) at various values of MVDC for the lossless boost converter. Figure 3.21 DC voltage transfer function MVDC as a function of normalized load current IO/(VO/2fsL) at various values of D for the lossless boost converter. Figure 3.22 DC voltage transfer function MVDC as a function of normalized load resistance RL/(2fsL) at various values of D for the lossless boost converter. Figure 3.23 Efficiency η as a function of VI at fixed values of RL for the boost converter in DCM. Figure 3.24 Duty cycle D as a function of VI at fixed values of RL for the boost converter in DCM. Figure 3.25 Efficiency η as a function of IO at fixed values of VI for the designed boost converter in DCM. Figure 3.26 Duty cycle D as a function of IO at fixed values of VI for the boost converter in DCM. Figure 3.27 Efficiency η as a function of RL at fixed values of VI of the designed boost

converter in DCM. Figure 3.28 Duty cycle D as a function of RL at fixed values of VI for DCM at fixed values of VI. Figure 3.29 Derivation of the boost converter topology with a positive common rail. (a) Boost converter with a negative common rail. (b) Boost converter with the inductor and diode moved to the negative rail. (c) Boost converter with a positive common rail at the bottom. Figure 3.30 Bidirectional buck and boost PWM converters. Figure 3.31 Isolated boost PWM converter. Figure 3.32 Synchronous boost PWM converter. Figure 3.33 Tapped-inductor boost converters. (a) Tapped-inductor common-transistor boost converter. (b) Tapped-inductor common-diode boost converter. (c) Tappedinductor common-load boost converter. Figure 3.34 DC voltage transfer function of tapped-inductor common-transistor boost converter for CCM. Figure 3.35 DC voltage transfer function of tapped-inductor common-diode boost converter for CCM. Figure 3.36 DC voltage transfer function of tapped-inductor common-load (IWJ) boost converter for CCM. Figure 3.37 Derivation of the boost converter from the buck converter, or vice versa, using the duality principles. Figure 3.38 Full-wave peak rectifier. Figure 3.39 Line voltage and current loaded by a full-wave peak rectifier. Figure 3.40 Distortion factor FDF as a function of THD. Figure 3.41 Full-wave rectifier without filter capacitor. Figure 3.42 Boost power factor corrector. Figure 3.43 Boost power factor corrector. Figure 3.44 Waveforms in the boost power factor corrector for a cycle of the line frequency. (a) Waveforms of the rectified line voltage |vs|, output voltage VO, and inductor current iL. (b) Waveform of the line voltage vs and line current is. Figure 3.45 Waveforms of the duty cycle D(t) in the boost power factor corrector at VO = 400 V for a half of a cycle of the line frequency at Vrms = 90 V and Vrms = 264 V. Figure 3.46 Electronic ballast with boost active power factor corrector for fluorescent lamps [16].

Chapter 4 Figure 4.1 PWM buck–boost converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. Figure 4.2 Idealized current and voltage waveforms for the PWM buck–boost converter for CCM. Figure 4.3 Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax. Figure 4.4 Normalized load current IOB/(VO/2fsL) as a function of D at the boundary between CCM and DCM for buck–boost converter. Figure 4.5 Normalized load resistance RLB/(2fsL) as a function of D at the boundary between CCM and DCM for buck–boost converter. Figure 4.6 Output circuit of the buck–boost converter for deriving the output voltage ripple. Figure 4.7 Waveforms associated with the ripple voltage for the PWM buck–boost converter for CCM. Figure 4.8 Equivalent circuit of the buck–boost converter with parasitic resistances and the diode offset voltage to determine power losses. Figure 4.9 Efficiency of the buck–boost converter η versus duty cycle D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. Figure 4.10 The dc voltage transfer function MVDC of the lossy buck–boost converter for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. Figure 4.11 Efficiency η as a function of the dc input voltage VI at fixed load resistances RL for the buck–boost converter in CCM. Figure 4.12 Duty cycle D as a function of the dc input voltage VI at fixed load resistances RL for the buck–boost converters in CCM. Figure 4.13 Efficiency η as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM. Figure 4.14 Duty cycle D as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM. Figure 4.15 Efficiency η as a function of the load resistance RL at VImin = 24 V, VInom =

28 V, and VImax = 32 V for the buck–boost converter in CCM. Figure 4.16 Duty cycle D as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM. Figure 4.17 PWM buck–boost converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF. Figure 4.18 Waveforms for the PWM buck–boost converter operating in DCM. Figure 4.19 Duty cycle D as a function of the normalized load current IO/(VO/2fsL) at fixed values of MVDC for the lossless buck–boost converter. Figure 4.20 Duty cycle D as a function of the normalized load resistance RL/(2fsL) at fixed values of MVDC for the lossless buck–boost converter. Figure 4.21 DC voltage transfer function MVDC versus normalized load current IO/(VO/2fsL) at fixed values of duty cycle D for the lossless buck–boost converter. Figure 4.22 DC voltage transfer function MVDC versus normalized load resistance RL/(2fsL) at fixed values of duty cycle D for the lossless buck–boost converter. Figure 4.23 Efficiency η as a function of the dc input voltage VI at fixed load resistances for the buck–boost converter in DCM. Figure 4.24 Duty cycle D as a function of the dc input voltage VI at various load resistances for the buck–boost converter in DCM. Figure 4.25 Efficiency η as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. Figure 4.26 Duty cycle D as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. Figure 4.27 Efficiency η as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. Figure 4.28 Duty cycle D as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM. Figure 4.29 Bidirectional buck–boost converter. Figure 4.30 Block diagram of the buck–boost converter. Figure 4.31 Transformation of the boost converter. (a) Boost converter with a positive input voltage. (b) Boost converter with inductor and diode moved to the bottom

common rail. (c) Boost converter with a negative input voltage. Figure 4.32 Derivation of the buck–boost converter. (a) Buck and modified boost converters connected by a unity-gain inverter. (b) Filter capacitor is removed from the circuit and two inductors are combined into one inductor. (c) Simplified circuit. (d) Conductor is removed. (e) Redundant components S2 and D1 are removed. Figure 4.33 Derivation of the Ćuk (boost–buck) converter. (a) Cascaded boost converter, inverting unity-gain stage, and buck converter with negative input voltage. (b) Simplified circuit to reveal redundant components. (c) Ćuk (boost–buck) converter. Figure 4.34 Noninverting cascaded buck–boost and boost–buck converters. (a) Noninverting buck–boost converter. (b) Noninverting boost–buck converter. Figure 4.35 Noninverting cascaded synchronous CMOS boost–buck converter. Figure 4.36 Four-transistor CMOS noninverting buck–boost converter. (a) Circuit. (b) Buck converter. (c) Boost converter. Figure 4.37 Four-transistor noninverting buck–boost converter with nMOS transistors. (a) Circuit. (b) Buck converter. (c) Boost converter. Figure 4.38 Four-transistor noninverting buck–boost converter. (a) Circuit. (b) For time interval when the inductor is charged. (c) For time interval when the inductor is discharged. Figure 4.39 Switching-inductor inverting buck–boost converter. Figure 4.40 Tapped-inductor buck–boost converters. (a) Tapped-inductor commondiode buck–boost converter. (b) Tapped-inductor common-tansistor buck–boost converter. (c) Tapped-inductor common-load buck–boost converter. Figure 4.41 DC voltage transfer function of tapped-inductor common-diode buck–boost converter for CCM. Figure 4.42 DC voltage transfer function of tapped-inductor common-transistor buck– boost converter for CCM. Figure 4.43 DC voltage transfer function of tapped-inductor common-load buck–boost converter for CCM. Figure 4.44 Tapped-inductor common-source buck–boost converter. Figure 4.45 DC voltage transfer function of tapped-inductor common-source buck– boost converter for CCM. Chapter 5 Figure 5.1 Transformer. (a) Ideal noninverting transformer. (b) Ideal inverting transformer. (c) Model of a transformer consisting of an ideal noninverting transformer and a magnetizing inductance Lm.

Figure 5.2 Derivation of the PWM flyback converter from the PWM buck–boost converter. (a) Buck–boost converter. (b) Flyback inverting converter. (c) Flyback inverting converter with the gate driven with respect to ground. (d) Flyback noninverting converter with the gate driven with respect to ground. Figure 5.3 Power supply consisting of a rectifier and a PWM flyback converter. Figure 5.4 Equivalent circuits of the noninverting PWM flyback converter for CCM. (a) Equivalent circuit when the switch is ON and the diode is OFF. (b) Equivalent circuit when the switch is OFF and the diode is ON. Figure 5.5 Idealized current and voltage waveforms in the PWM inverting flyback converter for CCM. Figure 5.6 Waveform of the current through the magnetizing inductance Lm at the boundary between CCM and DCM for the flyback converter. Figure 5.7 Normalized load current IOB/(n2VO/2fsLm) at the boundary between CCM and DCM as functions of D for the flyback converter. Figure 5.8 Normalized load resistance RLB/(2fsLm/n2) at the boundary between CCM and DCM as functions of D for the flyback converter. Figure 5.9 Output circuit of the flyback converter. Figure 5.10 Waveforms illustrating the ripple voltage in the PWM flyback converter. Figure 5.11 Equivalent circuit of the flyback converter with parasitic resistances and the diode offset voltage. Figure 5.12 Efficiency η versus dc input voltage VI at various load resistances RL for the flyback converter in CCM. Figure 5.13 Duty cycle D versus dc input voltage VI at fixed load resistances RL for the flyback converter in CCM. Figure 5.14 Efficiency η versus dc load current IO at fixed values of dc input voltage VI for the flyback converter in CCM. Figure 5.15 Duty cycle D versus dc load current IO at fixed values of dc input voltage VI for the flyback converter in CCM. Figure 5.16 Efficiency η versus load resistance RL at dc fixed values of input voltage VI for the flyback converter in CCM. Figure 5.17 Duty cycle D versus load resistance RL at dc fixed values of input voltage VI for the flyback converter in CCM. Figure 5.18 Equivalent circuits of the PWM flyback converter for DCM. (a) Equivalent circuit when the switch is ON and the diode is OFF. (b) Equivalent circuit when the

switch is OFF and the diode is ON. (c) Equivalent circuit when both the switch and the diode are OFF. Figure 5.19 Idealized current and voltage waveforms in the PWM flyback converter for DCM. Figure 5.20 Duty cycle D as a function of normalized load current IO/(VO/2fsLms) at fixed values of MV DC for the lossless flyback converter in CCM and DCM. Figure 5.21 Duty cycle D as a function of load resistance RL/(2fsLms) at fixed values of MV DC for the lossless flyback converter in CCM and DCM. Figure 5.22 DC voltage transfer function MV DC as a function of normalized load current IO/(VO/2fsLms) at fixed values of D for the lossless flyback converter. Figure 5.23 DC voltage transfer function MV DC as a function of normalized load resistance RL/(2fsLms) at fixed values of D for the lossless flyback converter. Figure 5.24 Efficiency η as a function of dc input voltage VI at fixed load resistances for the flyback converter in DCM. Figure 5.25 Duty cycle D as a function of dc input voltage VI at fixed load resistances for the flyback converter in DCM. Figure 5.26 Efficiency η as a function of dc load current IO at fixed load resistances for the flyback converter in DCM. Figure 5.27 Duty cycle D as a function of dc load current IO at fixed load resistances for the flyback converter in DCM. Figure 5.28 Efficiency η as a function of load resistance RL at fixed dc input voltages for the flyback converter in DCM. Figure 5.29 Duty cycle D as a function of load resistance RL at fixed dc input voltages for the flyback converter in DCM. Figure 5.30 Multiple-output flyback converter. Figure 5.31 Equivalent circuit of multiple-output flyback converter. Figure 5.32 Derivation of a bidirectional flyback converter. (a) Unidirectional noninverting flyback converter. (b) Unidirectional noninverting flyback converter with the cathode of the diode connected to ground. (c) Bidirectional flyback converter. Figure 5.33 Equivalent circuit of flyback converter when the transistor is OFF. Figure 5.34 Flyback converter with dissipative RCD snubber. Figure 5.35 Flyback converter with a Zener diode voltage clamp across the transformer primary winding.

Figure 5.36 Flyback converter with clamp circuits to avoid ringing. (a) High-end nchannel active clamp. (b) Low-end n-channel active clamp. (c) Low-end p-channel active clamp. Figure 5.37 Two-switch flyback converter that eliminates ringing. Chapter 6 Figure 6.1 Derivation of the forward PWM converter. (a) Buck converter. (b) An inductor Lm, diode D1, an additional winding, and diode D3 are added to the buck converter. (c) Forward converter with the MOSFET gate driven with respect to a “hot point.” (d) Forward converter with the MOSFET gate driven with respect to ground. Figure 6.2 Equivalent circuits for different time intervals for the forward PWM converter operating in CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ DT + tm. (c) For DT + tm < t ≤ T. Figure 6.3 Waveforms in the PWM forward converter for CCM. Figure 6.4 Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax. Figure 6.5 Normalized load current IOB/(VO/2fsL) at the boundary between CCM and DCM as a function of duty cycle D for the forward converter at DMAX = 0.5 and η = 1. Figure 6.6 Normalized load Resistance RLB/(2fsL) at the boundary between CCM and DCM as a function of duty cycle D for the forward converter at DMAX = 0.5 and η = 1. Figure 6.7 Equivalent circuit of the forward converter with parasitic resistances to determine component losses (the branch with diode D3 is neglected). Figure 6.8 Efficiency η as a function of the dc input voltage VI at RL = 0.25 Ω, 0.5 Ω, and 2.5 Ω for the forward converter in CCM. Figure 6.9 Duty cycle D as a function of the dc input voltage VI for the forward converter at fixed load resistances RL in CCM. Figure 6.10 Efficiency η as a function of the dc load current IO at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. Figure 6.11 Duty cycle D as a function of the dc load current IO at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. Figure 6.12 Efficiency η as a function of the load resistance RL at VI = 127 V, 156 V, and 187 V for the forward converter in CCM. Figure 6.13 Duty cycle D as a function of the load resistance RL at VI = 127 V, 156 V, and 187 V for the forward converter in CCM.

Figure 6.14 Equivalent circuits for different time intervals for the forward PWM converter operating in DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ DT + tm. (c) For DT + tm < t ≤ (D + D1)T. (d) For (D + D1)T < t ≤ T. Figure 6.15 Waveforms in the PWM forward converter for DCM. Figure 6.16 Duty cycle D as a function of IO/(VO/2fsL) at constant values of n1MV DC and n3 = n1 for the lossless forward converter. Figure 6.17 Duty cycle D as a function of RL/(2fsL) at constant values of n1MV DC and n3 = n1 for the lossless forward converter. Figure 6.18 n1MV DC as a function of RL/(2fsL) at constant values of D for the lossless forward converter for n3 = n1. Figure 6.19 n1MV DC as a function of RL/(2fsL) at constant values of D for the lossless forward converter for n3 = n1. Figure 6.20 Waveforms of the inductor current at the boundary between DCM and CCM for VImin and VImax. Figure 6.21 Efficiency η as a function of the dc input voltage VI at various load resistances RL for the forward converter in DCM. Figure 6.22 Duty cycle D as a function of the dc input voltage VI at various load resistances RL for the forward converter in DCM. Figure 6.23 Efficiency η as a function of the dc load current IO at various dc input voltages VI for the forward converter in DCM. Figure 6.24 Duty cycle D as a function of the dc load current IO at various dc input voltages VI for the forward converter in DCM. Figure 6.25 Efficiency η as a function of the load current IO at various dc input voltages VI for the forward converter in DCM. Figure 6.26 Duty cycle D as a function of the load resistance RL at various dc input voltages VI for the forward converter in DCM. Figure 6.27 Multiple-output forward converter. Figure 6.28 Forward converters with synchronous rectifier. (a) With self-driven MOSFETs. (b) With IC driver of all MOSFETs. Figure 6.29 Forward converters with active clamping. (a) High-end n-channel active clamping. (b) Low-end n-channel active clamping. (c) Low-end p-channel active clamping.

Figure 6.30 Two-transistor forward converter. Figure 6.31 Single-transistor forward–flyback converter. Figure 6.32 Two-transistor forward–flyback converter [19]. Chapter 7 Figure 7.1 Half-bridge converter with two blocking capacitors. (a) With a transformer center-tapped rectifier. (b) With a full-bridge rectifier. (c) With a half-wave rectifier. Figure 7.2 Half-bridge converter with a single coupling capacitor Cc. (a) With a transformer center-tapped rectifier. (b) With a bridge rectifier. (c) With a half-wave rectifier. Figure 7.3 Equivalent circuit of the half-bridge converter with a transformer centertapped rectifier for CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ T/2. (c) For T/2 < t ≤ T/2 + DT. (d) For T/2 + DT < t ≤ T. Figure 7.4 Waveforms in the half-bridge converter with a transformer center-tapped rectifier for CCM. Figure 7.5 Waveforms of the inductor current in the half-bridge converter at the boundary between CCM and DCM. Figure 7.6 Normalized load current IOB/(VO/2fsL) = (0.5 − D) as a function of duty cycle D at the boundary between CCM and DCM for the half-bridge converter. Figure 7.7 Normalized load resistance RLB/(2fsL) as a function of duty cycle D at the boundary between CCM and DCM for the half-bridge converter. Figure 7.8 Equivalent circuit of the half-bridge converter with parasitic resistances to determine component losses. Figure 7.9 Efficiency η as a function of dc input voltage VI at fixed load resistances RL for the half-bridge converter in CCM. Figure 7.10 Duty cycle D as a function of dc input voltage VI at fixed load resistances for the half-bridge converter in CCM. Figure 7.11 Efficiency η as a function of dc load current IO at fixed dc input voltages VI for the half-bridge converter in CCM. Figure 7.12 Duty cycle D as a function of dc load current IO at fixed dc input voltages VI for the half-bridge converter in CCM. Figure 7.13 Efficiency η as a function of load resistance RL at fixed dc input voltages VI for the half-bridge converter in CCM. Figure 7.14 Duty cycle D as a function of load resistance RL at fixed dc input voltages VI for the half-bridge converter in CCM.

Figure 7.15 Equivalent circuit of the half-bridge converter with a transformer centertapped rectifier for DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ (D + D1)T. (c) For (D + D1)T < t ≤ T/2. (d) For T/2 < t ≤ T/2 + DT. (e) For T/2 + DT < t ≤ T/2 + (D + D1)T. Figure 7.16 Waveforms in the half-bridge converter with a transformer center-tapped rectifier for DCM. Figure 7.17 Duty cycle D versus normalized load current IO/(VO/2fsL) at fixed values of nMVDC for CCM and DCM for the lossless half-bridge converter. Figure 7.18 Duty cycle D versus normalized load resistance RL/(2fsL) at fixed values of nMVDC for CCM and DCM for the lossless half-bridge converter. Figure 7.19 DC voltage transfer function nMVDC versus normalized load current IO/(VO/2fsL) at fixed values of D for CCM and DCM for the lossless half-bridge converter. Figure 7.20 DC voltage transfer function nMVDC versus normalized load resistance RL/(2fsL) at fixed values of D for CCM and DCM for the lossless half-bridge converter. Figure 7.21 Waveforms of the inductor current at the boundary between CCM and DCM in the half-bridge converter for VImin and VImax. Chapter 8 Figure 8.1 Full-bridge converter. (a) With a transformer center-tapped rectifier. (b) With a full-bridge rectifier. (c) With a half-wave rectifier. Figure 8.2 Equivalent circuits of the full-bridge converter with a transformer centertapped rectifier for CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ T/2. (c) For T/2 < t ≤ T/2 + DT. (d) For T/2 + DT < t ≤ T. Figure 8.3 Waveforms of the full-bridge converter with a transformer center-tapped rectifier for CCM. Figure 8.4 Waveforms of the inductor current in the full-bridge converter at the boundary between CCM and DCM. Figure 8.5 Normalized load current IOB/(VO/2fsL) as function of duty cycle D at the boundary between CCM and DCM for the full-bridge converter. Figure 8.6 Normalized load resistance RLB/(2fsL) as function of duty cycle D at the boundary between CCM and DCM for the full-bridge converter. Figure 8.7 Equivalent circuit of the full-bridge converter with parasitic resistances to determine component losses. Figure 8.8 Efficiency η as a function of the dc input voltage VI at fixed load resistances

RL for the full-bridge converter in CCM. Figure 8.9 Duty cycle D as a function of the dc input voltage VI at fixed load resistances RL for the full-bridge converter in CCM. Figure 8.10 Efficiency η as a function of the dc load current IO at fixed dc input voltages VI for the full-bridge converter in CCM. Figure 8.11 Duty cycle D as a function of the dc load current IO at fixed input voltages VI for the full-bridge converter in CCM. Figure 8.12 Efficiency η as a function of the load resistance IO at fixed input voltages VI for the full-bridge converter in CCM. Figure 8.13 Duty cycle D as a function of the load resistance IO at fixed input voltages VI for the full-bridge converter in CCM. Figure 8.14 Equivalent circuits of the full-bridge converter with a transformer centertapped rectifier for DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ (D + D1T)T. (c) For (D + D1)T < t ≤ T/2. (d) For T/2 < t ≤ T/2 + DT. (e) For T/2 + DT < t ≤ (D + D1)T. Figure 8.15 Waveforms in the full-bridge converter with a transformer center-tapped rectifier for DCM. Figure 8.16 Duty cycle D as a function of the normalized load current IO/(VO/2fsL) at fixed values of nMVDC for the lossless full-bridge converter. Figure 8.17 Duty cycle D as a function of normalized load resistance RL/(2fsL) at fixed values of nMVDC for the lossless full-bridge converter. Figure 8.18 DC voltage transfer function nMVDC as a function of the normalized load current IO/(VO/2fsL) at fixed values of D for the lossless full-bridge converter. Figure 8.19 DC voltage transfer function nMVDC as a function of normalized load resistance RL/(2fsL) at fixed values of D for the lossless full-bridge converter. Figure 8.20 Waveform of the inductor current in the full-bridge converter at the boundary between CCM and DCM for VImin and VImax. Figure 8.21 Full-bridge converter with phase-shift control. Figure 8.22 Equivalent circuits in full-bridge converter with phase-shift control. Figure 8.23 Waveforms in full-bridge converter with phase-shift control. Chapter 9 Figure 9.1 Single-ended transformerless two-switch PWM converters. (a) Buck converter. (b) Boost converter. (c) Buck–boost converter. (d) Ćuk converter.

Figure 9.2 Switching network and equivalent circuit of single-ended transformerless two-switch PWM converters. (a) Switching network. (b) Equivalent circuit. Figure 9.3 Steady-state waveforms in the ideal switching network for CCM. Figure 9.4 Averaged model of ideal switch, ideal diode, and ideal switching network for the dc components in steady state for CCM. (a) Averaged model of an ideal switch. (b) Averaged model of an ideal diode. (c) Averaged model of an ideal switching network of two-switch PWM converters. Figure 9.5 Averaged models of the actual MOSFET and the actual diode in steady state for CCM. (a) Averaged model of the actual MOSFET. (b) Averaged model of the actual diode. Figure 9.6 Modeling of the actual switching network under steady-state conditions for two-switch PWM converters operating in CCM. (a) Actual switching network. (b) Averaged dc model of the actual switching network. (c) Simplified averaged dc model of the actual switching network with the averaged resistances moved to the inductor branch. Figure 9.7 Large-signal averaged models of the actual switching network for twoswitch PWM converters for CCM. (a) Actual switching network. (b) Large-signal averaged model of the actual switching network. (c) Simplified large-signal averaged model of the actual switching network with the averaged resistances moved to the inductor branch. Figure 9.8 Large-signal low-frequency model of the buck PWM converter with parasitic components for CCM. (a) Large-signal model with the dependent sources in the original branches. (b) Large-signal model with the dependent current source split into two sources. (c) Simplified large-signal model. Figure 9.9 Normalized output voltage vO/(DVI) as a response to a step change in the dc input voltage at ξ = 0.3, neglecting the switching-frequency component. Figure 9.10 Waveforms of the input voltage and the inductor current under sinusoidal low-frequency small-signal perturbations for CCM. (a) Waveform of the input voltage. (b) Waveform of the high-frequency inductor current. (c) Waveform of the averaged low-frequency inductor current. Figure 9.11 Averaged low-frequency large-signal and bilinear models of the actual switching network for two-switch PWM converters for CCM. (a) Averaged lowfrequency large-signal nonlinear model. (b) Averaged low-frequency bilinear model. (c) Averaged dc and low-frequency small-signal model. Figure 9.12 Small-signal low-frequency and dc linear circuit models of the actual switching network for two-switch PWM converters for CCM. (a) Linear lowfrequency small-signal circuit model of the actual switching network. (b) DC model of the actual switching network.

Figure 9.13 Small-signal low-frequency model of the buck PWM converter with parasitic components for CCM. (a) Circuit of the physical buck PWM converter. (b) Small-signal model of the buck converter. (c) Small-signal model of the buck converter with two sets of the dependent current sources. (d) Simplified small-signal model of the buck converter. Figure 9.14 Small-signal low-frequency model of the boost PWM converter with parasitic components for CCM. (a) Circuit of the physical boost PWM converter. (b) Alternative representation of the circuit of the physical boost PWM converter. (c) Small-signal model of the boost converter. (d) Simplified small-signal model of the boost converter. Figure 9.15 Small-signal low-frequency model of the buck–boost PWM converter with parasitic components for CCM. (a) Circuit of the physical buck-boost PWM converter. (b) Small-signal model of the buck–boost converter. Figure 9.16 Block diagram of a small-signal model of PWM dc–dc converters. Figure 9.17 Family of averaged large-signal circuit models of the ideal switching network for basic two-switch PWM converters in CCM. Figure 9.18 A PWM small-signal switch model of the nonlinear switching network for basic two-switch PWM converters operating in CCM. Figure 9.19 Voltage waveforms in PWM converters for DCM. Figure 9.20 Current waveforms in PWM converters for DCM. Figure 9.21 Models of PWM converters for DCM. (a) DC and small-signal model. (b) Small-signal model. (c) DC model. Figure 9.22 Small-signal model of PWM buck converter for DCM. (a) Buck converter. (b) Small-signal model for DCM. Figure 9.23 Small-signal model of PWM boost converter for DCM. (a) Boost converter. (b) Small-signal model for DCM. (c) Small-signal model for boost converter with some components moved to the upper branches. Figure 9.24 Small-signal model of PWM buck-boost converter for DCM. (a) Buck– boost converter. (b) Small-signal model for DCM. Chapter 10 Figure 10.1 Circuit and small-signal model of the open-loop PWM buck converter for CCM. (a) Circuit of the PWM buck converter. (b) Small-signal circuit model of the open-loop PWM buck converter for CCM. Figure 10.2 Block diagram of the open-loop small-signal model of the PWM converter. Figure 10.3 Small-signal model of the PWM converter for the derivation of the openloop control-to-output transfer function Tp.

Figure 10.4 Idealized Bode plots of the control-to-output transfer function Tp for the buck converter (without the delay). (a) Tp versus f. (b)

versus f.

Figure 10.5 The magnitude of the control-to-output transfer function Tp for the buck converter without the delay. Figure 10.6 The phase of the control-to-output transfer function Tp without the delay. Figure 10.7 Magnitude of the delay function Td for td/Ts = 0.1 and fs = 100 kHz. Figure 10.8 Phase of the delay function Td for td/Ts = 0.1 and fs = 100 kHz. Figure 10.9 Bode plot of the magnitude of Tp without and with the delay for td = 1 μs and fs = 100 kHz, that is, for td/Ts = 0.1. Figure 10.10 Bode plot of the phase of Tp without and with the delay for td = 1 μs and fs = 100 kHz, that is, for td/Ts = 0.1. Figure 10.11 Small-signal model of the PWM converter for the derivation of the openloop input-to-output transfer function Mv and the open-loop input impedance Zi. Figure 10.12 Idealized Bode plots of the input-to-output transfer function Mv. (a) |Mv| versus f. (b) versus f. Figure 10.13 Bode plot of the magnitude of the input-to-output transfer function Mv for the buck converter. Figure 10.14 Bode plot of the phase of the input-to-output transfer function Mv for the buck converter. Figure 10.15 The magnitude of the open-loop input impedance Zi of the buck converter loaded by the load resistance RL. Figure 10.16 The phase of the open-loop input impedance Zi of the buck converter loaded by the load resistance RL. Figure 10.17 Small-signal model of the PWM converter for the derivation of the openloop output impedance Zo. Figure 10.18 The magnitude of the open-loop output impedance Zo of the buck converter. Figure 10.19 The phase of the open-loop output impedance Zo of the buck converter. Figure 10.20 Maximum percent overshoot as a function of fz/f0 at fixed values of ξ. Figure 10.21 Step response of vO to a step change in vI from 28 to 29 V for the buck converter without feedback for Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω,

r = 0.16 Ω, and rC = 0.391 Ω. Figure 10.22 Step response of vO to a step change in the duty cycle dT from 0.555 to 0.655 for the buck converter without feedback for VInom = 28 V, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Figure 10.23 Step response of vO to a step change in the load current IO from 1.4 to 1.5 A for the buck converter without feedback for VInom = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Figure 10.24 DC model of the PWM buck converter. Chapter 11 Figure 11.1 DC model of the PWM boost converter. Figure 11.2 DC voltage transfer function MV DC as a function of the duty cycle D at RL = 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω. Figure 11.3 Efficiency η as a function of the duty cycle D at RL= 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω. Figure 11.4 Small-signal model and block diagram of the PWM boost converter for CCM. (a) Small-signal model. (b) Block diagram. Figure 11.5 Small-signal model of the PWM boost converter for determining the control-to-output transfer function Tp. Figure 11.6 Total parasitic resistance r as a function of D for rDS = 0.18 Ω, RF = 0.072 Ω, and rL = 0.19 Ω. Figure 11.7 Frequency of the RHP zero fzp as a function of D for the boost converter at VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω for RL = 40 Ω. Figure 11.8 Corner frequency f0 as a function of D for the boost converter at VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω for RL = 40 Ω. Figure 11.9 Damping ratio ξ as a function of D for RL = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Figure 11.10 Idealized Bode plots of the open-loop control-to-output transfer function Tp for the boost converter (without the delay). (a) |Tp| versus f. (b) ϕTp versus f. Figure 11.11 Exact and approximated delay phase ϕTd. Figure 11.12 Bode plot of the magnitude of the open-loop control-to-output transfer

function Tp without and with the delay td = 1 μs for the boost converter. Figure 11.13 Bode plot of the phase of the open-loop control-to-output transfer function Tp for the boost converter without and with the delay td = 1 μs. Figure 11.14 Small-signal model of the PWM boost converter for determining the input-to-output transfer function Mv. Figure 11.15 Idealized Bode plots of the open-loop input-to-output transfer function Mv for the boost converter in CCM. (a) |Mv| versus f. (b) ϕMv versus f. Figure 11.16 Bode plot of the magnitude of the open-loop input-to-output transfer function |Mv| versus frequency for the boost converter. Figure 11.17 Bode plot of the phase of the open-loop input-to-output transfer function |Mv| versus frequency for the boost converter. Figure 11.18 The magnitude of the open-loop input impedance Zi for the boost converter. Figure 11.19 The phase of the open-loop input impedance Zi for the boost converter. Figure 11.20 Small-signal model of the PWM boost converter for determining the output impedance Zo. Figure 11.21 The magnitude of the open-loop output impedance Zo for the boost converter. Figure 11.22 The phase of the open-loop output impedance Zo for the boost converter. Figure 11.23 Response of the output voltage vO to a step change in vI from 12 to 13 V for the boost converter without feedback for Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Figure 11.24 Response of the output voltage vO to a step change in the duty cycle dT from 0.5 to 0.6 for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Figure 11.25 Step response of vO to a step change in the load current IO from 0.5 to 0.6 A for the boost converter without feedback for VInom = 12 V, D = 0.5, L = 156 μH, C = 68 μF, RLmin = 40 Ω, r = 0.316 Ω, and rC = 0.111 Ω. Chapter 12 Figure 12.1 Block diagram of a single-loop negative feedback configuration. Figure 12.2 Closed-loop gain Af as a function of the open-loop gain A and the transfer function of the feedback network β. (a) Af versus A at a fixed β. (b) Af versus β at a

fixed A. Figure 12.3 Circuit of closed-loop voltage-mode-controlled buck PWM converter. Figure 12.4 Closed-loop voltage-mode-controlled buck PWM converter with a feedback network β represented by the h-parameters, where h21 = 0. Figure 12.5 Closed-loop voltage-mode-controlled buck PWM converter with resistances h11 and 1/h22 included in the A-network. Figure 12.6 Waveforms in the closed-loop voltage-mode-control PWM buck converter with a negative feedback loop. Figure 12.7 Closed-loop small-signal low-frequency representations of the buck PWM converter. (a) Small-signal model. (b) Block diagram. (c) Simplified block diagram. Figure 12.8 Pulse-width modulator. (a) Circuit. (b) DC block diagram. (c) AC smallsignal block diagram. Figure 12.9 Waveforms in the pulse-width modulator. (a) Waveforms of the sawtooth voltage vt and the control voltage vC. (b) Waveforms of the gate-to-source voltage vGS. Figure 12.10 Waveforms in the pulse-width modulator for a sinusoidal ac component of the control voltage. Figure 12.11 Block diagram and equivalent circuit of a linear two-port network represented by the h-parameters. (a) Block diagram of a general two-port network. (b) A two-port representation using the hybrid h-parameters. Figure 12.12 Feedback network and its h-parameter equivalent circuit. (a) Feedback network. (b) Equivalent circuit of the feedback network represented by its hparameters. (c) Equivalent circuit of the feedback network represented by h-parameters with h21 = 0. Figure 12.13 Bode plot of the magnitude of Tmp. Figure 12.14 Bode plot of the phase of Tmp. Figure 12.15 Bode plot of the magnitude of Tk . Figure 12.16 Bode plot of the phase of Tk . Figure 12.17 General circuit and control block diagram of an error amplifier. (a) General circuit. (b) Control block diagram. Figure 12.18 Proportional controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. Figure 12.19 Bode plots of the ac voltage transfer function Tc of proportional controller. (a) Magnitude |Tc|. (b) Phase .

Figure 12.20 Integral controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. Figure 12.21 Bode plots of the ac voltage transfer function Tc of integral controller. (a) Magnitude |Tc|. (b) Phase . Figure 12.22 Proportional-integral (PI) controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. Figure 12.23 Bode plots of the ac voltage transfer function Tc of proportional-integral (PI) controller. (a) Magnitude |Tc|. (b) Phase . Figure 12.24 Bode plot of the magnitude |Tc| of the ac voltage transfer function Tc of proportional-integral (PI) controller at KP = 10 and fz = 1 kHz. Figure 12.25 Bode plot of the phase ϕTc of the ac voltage transfer function Tc of proportional-integral (PI) controller at KP = 10 and fz = 1 kHz. Figure 12.26 Integral-single-lead controller (type II controller). (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. Figure 12.27 Idealized Bode plots for the integral-lead controller (type II controller). Figure 12.28 Plot of phase ϕm versus K for the integral-lead controller (type II controller). Figure 12.29 Bode plot of the magnitude of Tc for fzc = 310.82 kHz, fzp = 205.9 kHz, and B = 35.57 × 106 rad/s. Figure 12.30 Bode plot of the phase of Tc for fzc = 310.82 kHz, fzp = 205.9 kHz, and B = 35.57 × 106 rad/s. Figure 12.31 Bode plot of the magnitude of loop gain T. Figure 12.32 Bode plot of the phase of loop gain T. Figure 12.33 Bode plot of the magnitude of closed-loop transfer function Tcl. Figure 12.34 Bode plot of the phase of closed-loop transfer function Tcl. Figure 12.35 Bode plot of the magnitude of the closed-loop input-to-output transfer function Mvcl. Figure 12.36 Bode plot of the phase of the closed-loop input-to-output transfer function Mvcl. Figure 12.37 Magnitude of the closed-loop input impedance Zicl. Figure 12.38 Phase of the closed-loop input impedance Zicl.

Figure 12.39 Magnitude of Zocl. Figure 12.40 Phase of Zocl. Figure 12.41 Step response of vO to a step change in vI from 28 to 29 V for the buck converter with negative feedback. Figure 12.42 Step response of vO to a step change in vR from 5 to 6 V for the buck converter with negative feedback. Figure 12.43 Step response of vO to a step change in the load current IO from 1.4 to 1.5 A for the buck converter with negative feedback. Figure 12.44 Closed-loop dc model of the PWM buck converter. Chapter 13 Figure 13.1 Boost PWM converter with voltage-mode control. Figure 13.2 Closed-loop boost PWM converter with a feedback network β represented by h-parameters. Figure 13.3 Closed-loop boost PWM converter with resistances h11 and 1/h22 moved to the A-network. Figure 13.4 Closed-loop small-signal low-frequency model of the boost converter. (a) Small-signal model. (b) Block diagram. (c) Simplified block diagram. Figure 13.5 Bode plot of the magnitude of the modulator and the control-to-output transfer function Tmp = TmTp for the boost converter. Figure 13.6 Bode plot of the phase of the modulator and the control-to-output transfer function Tmp = TmTp for the boost converter. Figure 13.7 Bode plot of the magnitude of the modulator, the control-to-output transfer function, and the feedback network Tk = βTmp = βTmTp for the boost converter. Figure 13.8 Bode plot of the magnitude of the modulator, the control-to-output transfer function, and the feedback network Tk = βTmp = βTmTp for the boost converter. Figure 13.9 Third-order integral-double-lead controller with two zero–pole pairs (type III controller). (a) Circuit. (b) Equivalent circuit for the ac component. Figure 13.10 Maximum phase boost ϕm versus K for the integral-double-lead controller with two zero–pole pairs (type III controller). Figure 13.11 Bode plot of the magnitude of the voltage transfer function Tc for the designed integral-double-lead controller with two zero–pole pairs (type III converter). Figure 13.12 Bode plot of the phase of the voltage transfer function Tc for the designed integral-double-lead controller with two zero–pole pairs (Type III).

Figure 13.13 Bode plot of the magnitude of the loop gain T for the boost converter. Figure 13.14 Bode plot of the phase of the loop gain T for the boost converter. Figure 13.15 Bode plot of the magnitude of the closed-loop control-to-output transfer function Tcl for the boost converter. Figure 13.16 Bode plot of the phase of the closed-loop control-to-output transfer function Tcl for the boost converter. Figure 13.17 Bode plot of the magnitude of the closed-loop input-to-output transfer function Mvcl for the boost converter. Figure 13.18 Bode plot of the phase of the closed-loop input-to-output transfer function Mvcl for the boost converter. Figure 13.19 The magnitude of the closed-loop input impedance Zicl versus frequency for the boost converter. Figure 13.20 The phase of the closed-loop input impedance Zicl versus frequency for the boost converter. Figure 13.21 The input resistance of the closed-loop input impedance Zicl = Ricl + jXicl versus frequency for the boost converter. Figure 13.22 The input reactance of the closed-loop input impedance Zicl = Ricl + jXicl versus frequency for the boost converter. Figure 13.23 Plot of the magnitude of the closed-loop output impedance Zocl versus frequency for the boost converter. Figure 13.24 Plot of the magnitude of the closed-loop output impedance Zocl versus frequency for the boost converter. Figure 13.25 Response of vO to a step change in input voltage vI from 12 to 13 V for the boost converter with negative feedback. Figure 13.26 Response of vO to a step change in reference voltage vR from 2.5 to 3 V for the boost converter with negative feedback. Figure 13.27 Response of vO to a step change in load current iO from 0.5 to 0.6 A for the boost converter with negative feedback. Chapter 14 Figure 14.1 Circuit of a PWM buck converter with peak-current-mode control. Figure 14.2 Circuit of a PWM boost converter with peak-current-mode control. Figure 14.3 Circuit of a PWM buck–boost converter with peak-current-mode control.

Figure 14.4 Waveforms of PWM converters with constant-frequency, trailing-edge modulation, peak-current-mode control. Figure 14.5 Steady-state waveforms of the inductor voltage and current in PWM converters for CCM. Figure 14.6 Steady-state and perturbed (transient) waveforms of inductor current in PWM converters with current-mode control in CCM. Figure 14.7 Steady-state (solid line) and perturbed (dashed line) waveforms of inductor current iL for PWM converters with current-mode control. (a) For a stable current loop (D < 0.5). (b) For a marginally stable current loop (D = 0.5). (c) For an unstable current loop (D > 0.5). Figure 14.8 Small-signal inductor current waveforms il for PWM converters with current-mode control. (a) For a stable current loop (D < 0.5). (b) For a marginally stable current loop (D = 0.5). (c) For an unstable current loop (D > 0.5). Figure 14.9 Implementation of slope compensation, using a differential amplifier. Figure 14.10 Steady-state waveforms of the inductor current iL, the control current iC, an artificial ramp current iA, and iC–iA illustrating slope compensation by subtracting a ramp current iA from the control current iC in PWM converters with current-mode control for CCM. Figure 14.11 Waveforms of the inductor current iL, the control current iC, and iC–iA used to derive the stability condition for the current loop with slope compensation. Figure 14.12 Plot of M3/M1 as a function of D. Figure 14.13 Plot of M3/M2 as a function of D. Figure 14.14 Elimination of perturbation in the inductor current waveform in closedinner loop during one cycle at M3 = M2 (dead-beat control). Figure 14.15 Normalized critical slope compensation M3cr/(VO/L) as a function of the maximum duty cycle Dmax for the buck and buck–boost converters. This plot forms a boundary between stable and unstable regions. Figure 14.16 Normalized critical slope compensation M3cr/(VO/L) as a function of the maximum duty cycle Dmax for the boost converter. This plot constitutes a boundary between stable and unstable regions. Figure 14.17 Waveforms in the inner-current loop. Figure 14.18 Natural response (zero-input response or source-free response) of the inductor current in the closed-current loop. The zero-input response is obtained when all the inputs are identically zero. The zero-input response is zero if all initial conditions are zero. Waveforms of the inductor current in the inner-current loop after a

small perturbation in the inductor current iL introduced at time t = kTs. (a) Waveforms of steady-state control voltage vC, steady-state normalized inductor current RsiL (solid line), and perturbed (transient) normalized inductor current Rs(iL + il) (dashed line). (b) Exact waveform of the difference between the steady-state and perturbed waveforms, resulting in a small-signal inductor current il. (c) Approximate waveform of the smallsignal inductor current il. Figure 14.19 Enlarged waveforms of natural response depicted in Figure 14.18(a). Figure 14.20 Forced response of the inductor current in the closed-current loop. Waveforms of the control voltage and the inductor current in the inner-current loop after a step change in the control voltage vC from VC to VC + vc at time t = kTs, causing a perturbation of the inductor current iL. (a) Waveforms of control voltage vC = VC + vc, steady-state inductor current RsiL (solid line), and perturbed normalized inductor current Rs(iL + il) (dashed line). (b) Exact waveform of the difference between the steady-state and perturbed waveforms, resulting in a small-signal inductor current il. (c) Approximate waveform of the small-signal inductor current il. Figure 14.21 Enlarged waveforms of the forced response shown in Figure 14.20(a). Figure 14.22 Step response of the inductor current to a step change in the control voltage ΔVC = vc = 0.1 V at a = 0.7. Figure 14.23 Locations of the pole p = −a of the discrete-time control voltage-toinductor current transfer function Hicl(z) of the closed-current loop in the complex plane and sequence of samples. (a) For −1 < p < 0, the current loop is stable. (b) For p = −1, the current loop is marginally stable. (b) For − ∞ < p < −1, the current loop is unstable. Figure 14.24 Margin of stability of discrete systems. Figure 14.25 Block diagram for converting the closed-loop control voltage-to-inductor current transfer function from z-domain into s-domain. Figure 14.26 Magnitude of closed-current loop |H*icl| as a functions of f/fs for a = 0.1712 for a wide frequency range. Figure 14.27 Phase of closed-current loop Hicl as a functions of f/fs for a = 0.1712 for a wide frequency range. Figure 14.28 Exact and approximate plots of the magnitude of closed-current loop Hicl as a functions of f/fs for a = 0.1712 for a wide frequency range, using the second-order Padé and modified Padé approximations. Figure 14.29 Exact and approximate plots of the phase of closed-current loop Hicl as a functions of f/fs for a = 0.1712 for a wide frequency range, using the second-order Padé

and modified Padé approximations. Figure 14.30 Exact and approximate plots of the magnitude of Hicl as a functions of f/fs for a = 0.1712. Figure 14.31 Exact and approximate plots of the phase of Hicl as a functions of f/fs for a = 0.1712. Figure 14.32 Exact and approximate plots of the magnitude of Hicl as a functions of f/fs for a = 0.1712. Figure 14.33 Exact and approximate plots of the phase of Hicl as a functions of f/fs for a = 0.1712. Figure 14.34 Damping factor ξi as a function of a. Figure 14.35 Root locus of the closed-current-loop transfer function Hicl(s) at fs = 100 kHz for variations of a from 0 to 10. Figure 14.36 Bode plot of the magnitude of Hicl for selected values of a. Figure 14.37 Bode plot of the phase of Hicl for selected values of a. Figure 14.38 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 0.7. Figure 14.39 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 1. Figure 14.40 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 1.2. Figure 14.41 Block diagram of the inner loop. Figure 14.42 Bode plot of the magnitude of the inner loop gain Ti at a = 0.1712. Figure 14.43 Bode plot of the phase of the inner loop gain Ti at a = 0.1712. Figure 14.44 Enlarged Bode plot of the magnitude of the inner loop gain Ti at a = 0.1712. Figure 14.45 Enlarged Bode plot of the phase of the inner loop gain at a = 0.1712. Figure 14.46 Bode plot of the magnitude of the current-loop gain Ti for selected values of a. Figure 14.47 Bode plot of the phase of the current-loop gain Ti for selected values of a. Figure 14.48 Nyquist plot of the loop gain of current loop Ti(jω) at fs = 100 kHz for selected values of a.

Figure 14.49 Plot of fci/fs as a function of a. Figure 14.50 Perturbation ratio a as a function of phase margin PM for the innercurrent loop. Figure 14.51 Belt margins at the phase margins PM = 0, PM = 45°, and PM = 60°. Figure 14.52 Normalized crossover frequency fci/fs a function of phase margin PM for the current loop. Figure 14.53 The maximum duty cycle Dmax as a function of a without slope compensation. Figure 14.54 The maximum duty cycle Dmax as a function of phase margin PM without slope compensation. Figure 14.55 The maximum duty cycle Dmax as a function of a at selected values of M3/M1. Figure 14.56 The maximum duty cycle Dmax as a function of M3/M1 at selected values of a. Figure 14.57 The maximum duty cycle Dmax as a function of M3/M1 at selected values of phase margin PM. Figure 14.58 The maximum duty cycle Dmax as a function of PM at selected values of M3/M1. Figure 14.59 The required slope compensation M3/M1 as a function of the maximum duty cycle Dmax at selected values of phase margin PM. Figure 14.60 Normalized crossover frequency fci/fs as a function of the normalized slope compensation M3/M1 at selected values of the maximum duty cycle Dmax. Figure 14.61 Normalized slope compensation M3min/(VO/L) as a function of the maximum duty cycle Dmax at selected values of the phase margin PM for the buck and buck–boost converters. Figure 14.62 Normalized slope compensation M3min/(VO/L) as a function of the maximum duty cycle Dmax at selected values of the phase margin PM for the boost converter. Figure 14.63 Block diagram of the closed-current loop showing the transfer function from the control voltage-to-the inductor current il, used for determining Tms = d/vei. No disturbances are present, that is, vi = 0 and io = 0. (a) Without slope compensation. (b) With slope compensation. Figure 14.64 Block diagram of the closed-current loop showing the transfer function

from control voltage to the duty cycle d, as in actual converters. The disturbances are zero (i.e., vi = 0 and io = 0.) (a) Without slope compensation. (b) With slope compensation. Figure 14.65 Waveforms of d(t) and d0(t) as responses to a step change in the duty cycle from 0.55 to 0.65. Figure 14.66 Bode plot of the magnitude of the error voltage-to-duty cycle transfer function Tms for selected values of a. Figure 14.67 Bode plot of the phase of the error voltage-to-duty cycle transfer function Tms for selected values of a. Figure 14.68 Bode plot of the magnitude of the closed-current loop Ticl(s) for the buck PWM converter at 0.1712. Figure 14.69 Bode plot of the phase of the closed-current loop Ticl(s) for the buck PWM converter at a = 0.1712. Figure 14.70 Bode plot of the magnitude of the closed-current loop Ticl(s) for the buck converter at a = 0.1712. Figure 14.71 Bode plot of the phase of the closed-current loop Ticl(s) for the buck converter at a = 0.1712. Figure 14.72 Bode plot of the magnitude of the closed-current loop Ticl(s) for selected values of a. Figure 14.73 Bode plot of the phase of the closed-current loop Ticl(s) for selected values of a. Figure 14.74 Block diagram for the alternative representation of Ticl. Figure 14.75 Block diagram of current loop with disturbances. Figure 14.76 Block diagram for determining the input voltage-to-duty cycle transfer function Mvd for the closed-current loop. Figure 14.77 Block diagram for determining the load-current-to-duty cycle transfer function Aid for the closed-current loop. Figure 14.78 Crossover frequencies fci/fs and fcim/fs as functions of a. Figure 14.79 a as a function of phase margin PM for the Padé approximation and for modified approximation. Figure 14.80 Location of the pole for phase margin PM = 0, PM = 45°, and PM = 60° using the Padé approximation. Figure 14.81 Maximum duty cycle Dmax as a function M3/M1 at selected values of

phase margin PM. Figure 14.82 M3/M1 as a function of maximum duty cycle Dmax at selected values of phase margin PM. Figure 14.83 Block diagram for determining the control-to-output transfer function Tco for the buck converter. (a) Block diagram. (b) Simplified block diagram. Figure 14.84 Magnitude of the control-to-output transfer function Tco for the buck converter. Figure 14.85 Phase of the control-to-output transfer function Tco for the buck converter. Figure 14.86 Block diagram of the power stage of PWM converters. Figure 14.87 Current-mode control block diagram of PWM converters without feedforward gains. Figure 14.88 Block diagram for the critical path of closed-loop PWM converters with current-mode control at vi = 0 and io = 0. Figure 14.89 Block diagram of PWM converters with current-mode control for determining the closed-loop audio susceptibility. Figure 14.90 Block diagram of PWM converters with current-mode control for determining the closed-loop output impedance. Figure 14.91 Waveforms of the inductor current with steady-state slope M1 and with perturbed slope M1 + m1 at fixed control voltage VC in PWM converter with currentmode control and without slope compensation. (a) Waveforms of the inductor and control currents. (b) Waveform of the gate-to-source voltage. Figure 14.92 Block diagram of the current modulator that includes feedforward gains. Figure 14.93 Block diagram of current loop with disturbances and feedforward gains. Figure 14.94 Waveforms of the inductor current with steady-state slope M1 and with perturbed slope M1 + m1 for fixed control voltage VC and compensating slope M3 in PWM converter with current-mode control and with slope compensation. Figure 14.95 Control block diagram of a PWM converter with current-mode control, where the feedforward gains are included. Figure 14.96 Slope compensation by adding an external periodic ramp current iA to the inductor current waveform iL. Figure 14.97 Sampler. (a) Circuit. (b) Model. Figure 14.98 Spectrum of a sine wave. (a) Before sampling. (b) After sampling for f < fs/2.

Figure 14.99 Magnitude of the zero-order hold transfer function |HZOH| as a function of frequency. Figure 14.100 Phase of the zero-order hold transfer function ϕZOH as a function of frequency. Figure 14.101 Magnitude of sample-and-hold transfer function |Hsh|. Figure 14.102 Phase of sample-and-hold transfer function ϕHsh. Figure 14.103 Plots of the exact, first-order, second-order, and third-order Padé approximations of the phase of as functions of f/fs in semi-log scale. Figure 14.104 Plots of the phase of the exact function (14.377) and the first-order, second-order, and third-order Padé approximations of the phase of as functions of f/fs in linear scale. Chapter 15 Figure 15.1 Small-signal model and block diagram of the PWM boost converter for CCM. (a) Small-signal model. (b) Block diagram. Figure 15.2 Small-signal model of the PWM boost converter used to derive the duty cycle-to-inductor current transfer function Tpi. Figure 15.3 Idealized Bode plots of the open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter (without the delay). (a) |Tpi| versus f. (b) ϕTpi versus f. Figure 15.4 Bode plot of the magnitude of the open-loop duty cycle-to-inductor current transfer function. Figure 15.5 Bode plot of the phase of the open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter without and with the delay time td = 1 μs. Figure 15.6 High-frequency small-signal model of the PWM boost converter used to derive the duty cycle-to-inductor current transfer function Tpi. Figure 15.7 Bode plots of the magnitude of the high-frequency and exact open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter without the delay. Figure 15.8 Bode plots of the phase of the high-frequency and exact open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter without the delay time. Figure 15.9 Small-signal model of the PWM boost converter for deriving the input voltage-to-inductor current transfer function Mvi. Figure 15.10 Idealized Bode plots of the open-loop input voltage-to-inductor current

transfer function Mvi for the boost converter. (a) |Mvi| versus f. (b) ϕMvi versus f. Figure 15.11 Bode plot of the magnitude of the open-loop input voltage-to-inductor current transfer function Mvi versus frequency for the boost converter. Figure 15.12 Bode plot of the phase of the open-loop input voltage-to-inductor current transfer function Mvi versus frequency for the boost converter. Figure 15.13 Small-signal model of the PWM boost converter for deriving the inductor-to-output current transfer function Ai. Figure 15.14 Idealized Bode plots of the open-loop input voltage-to-inductor current transfer function Ai for the boost converter. (a) |Ai| versus f. (b) ϕAi versus f. Figure 15.15 Bode plot of the magnitude of the open-loop inductor-to-output current transfer function Ai versus frequency for the boost converter. Figure 15.16 Bode plot of the phase of the open-loop inductor-to-output current transfer function Ai versus frequency for the boost converter. Figure 15.17 Response of the transient component of the inductor current iL to a step change of vI from 12 to 13 V for the boost converter without feedback for Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. Figure 15.18 Response of the transient component of the inductor current iL to a step change of the duty cycle dT from 0.5 to 0.6 for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. Figure 15.19 Response of the transient component of the inductor current iL to a step change of the load current ΔIO from 0.5 to 0.6 A for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Figure 15.20 Bode plot of the magnitude of Tms for the boost converter. Figure 15.21 Bode plot of the phase of Tms for the boost converter. Figure 15.22 Bode plot of the magnitude of the current loop gain Ti for the boost converter. Figure 15.23 Bode plot of the phase of the current loop gain Ti for the boost converter. Figure 15.24 Bode plot of the magnitude of the closed-loop gain of the current loop Ticl for the boost converter.

Figure 15.25 Bode plot of the phase of the closed-loop gain of the current loop Ticl for the boost converter. Figure 15.26 Response of the duty cycle dT to a step change in the control voltage vc = 0.01 V in the boost converter at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, rC = 0.111 Ω, f0 = 783.66 Hz, fzi1 = 116.379 Hz, and ξ = 0.261. Figure 15.27 Bode plot of the magnitude of the closed-loop gain of the current loop Hicl for the boost converter. Figure 15.28 Bode plot of the magnitude of the closed-loop gain of the current loop Hicl for the boost converter. Figure 15.29 Response of the inductor current iL to a step change in the control voltage vc = 0.01 V in the boost converter at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, rC = 0.111 Ω, f0 = 783.66 Hz, fzi1 = 116.38 Hz, and ξ = 0.261. Figure 15.30 Bode plot of the magnitude of inductor current-to-output voltage transfer function |Tio| for the boost converter. Figure 15.31 Bode plot of the phase of inductor current-to-output voltage transfer function for the boost converter. Figure 15.32 Bode plot of the magnitude of control-to-output transfer function |Tco| for the boost converter. Figure 15.33 Bode plot of the phase of control-to-output transfer function boost converter.

for the

Figure 15.34 Block diagram for deriving the input voltage-to-duty cycle transfer function. Figure 15.35 Bode plot of the magnitude of Mvd for the boost converter without feedforward gain Ki. Figure 15.36 Bode plot of the phase of Mvd for the boost converter without feedforward gain Ki. Figure 15.37 Response of dT to a step change ΔVI = 1 V from 12 to 13 V for the boost converter without feedforward gain Ki = 0.04167. Figure 15.38 Block diagram for deriving the input voltage-to-duty cycle transfer function Mvdf with feedforward gain Ki. Figure 15.39 Bode plot of the magnitude of Mvdf for the boost converter with

feedforward gain Ki = −0.04167. Figure 15.40 Bode plot of the phase of Mvdf for the boost converter with feedforward gain Ki = −0.04167. Figure 15.41 Response of dT to a step change ΔVI = 1 V from 12 to 13 V for the boost converter with feedforward gain Ki = −0.04167. Figure 15.42 Block diagram for deriving the load current-to-duty cycle transfer function Aid. Figure 15.43 Bode plot of the magnitude of Aid for the boost converter. Figure 15.44 Bode plot of the phase of Aid for the boost converter. Figure 15.45 Response of dT to a step change ΔIO = 0.1 A due to Aid for the boost converter with the closed current loop. Figure 15.46 Block diagram for deriving the output impedance Zoi of the closed-current loop. Figure 15.47 Magnitude of the output impedance Zoi of the closed-current loop for the boost converter. Figure 15.48 Phase of the output impedance ϕZoi of the closed-current loop for the boost converter. Figure 15.49 Response of vo to a step change ΔIO = 0.1 A due to Zoi with the closed current loop for the boost converter. Figure 15.50 Bode plot of the magnitude of the control to output transfer function Tco for the boost converter. Figure 15.51 Bode plot of the phase of the control-to-output transfer function Tco for the boost converter. Figure 15.52 Bode plot of the magnitude of Tk for the boost converter. Figure 15.53 Bode plot of the phase of Tk for the boost converter. Figure 15.54 Bode plot of the magnitude of the third-order integral-lead controller (type III) voltage transfer function Tc. Figure 15.55 Bode plot of the phase of the third-order integral-lead controller (type III) voltage transfer function Tc. Figure 15.56 Bode plot of the magnitude of the loop gain of the voltage loop T for the boost converter with an integral-lead controller (type III). Figure 15.57 Bode plot of the magnitude of the loop gain of the voltage loop T for the

boost converter with an integral-lead controller (type III). Figure 15.58 Bode plot of the magnitude of the closed-loop gain of the voltage loop Tcl for the boost converter with an integral-lead controller. Figure 15.59 Bode plot of the phase of the closed-loop gain of the voltage loop Tcl for the boost converter with an integral-lead controller. Figure 15.60 Bode plot of the magnitude of Tv for the boost converter with an integral lead. Figure 15.61 Bode plot of the phase of Tv for the boost converter with an integral-lead. Figure 15.62 Bode plot of the magnitude of the closed-loop audio susceptibility Mvcl for the boost converter with an integral-lead controller. Figure 15.63 Bode plot of the phase of the closed-loop audio susceptibility Mvcl for the boost converter with an integral-lead controller. Figure 15.64 The magnitude of the closed-loop output impedance Zocl for the boost converter with an integral-lead controller. Figure 15.65 The phase of the closed-loop output impedance Zocl for the boost converter with an integral-lead controller. Figure 15.66 Closed-loop response of vO to a step change of the input voltage vI from 12 to 13 V for the boost converter with an integral-lead controller at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.38 Hz, f0 = 783.66 Hz, ξ = 0.261, and β = 0.25 for Dnom = 0.5. Figure 15.67 Closed-loop response of vO to a step change of the load current ΔIO = 0.25 A from 1 to 1.25 A for the boost converter with an integral-lead controller at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.38 Hz, f0 = 783.66 Hz, ξ = 0.261, and β = 0.25 for Dnom = 0.5. Figure 15.68 Closed-loop response of vO to a step change of the reference voltage VR from 5 to 6 V for the boost converter with an integral-lead controller at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.38 Hz, f0 = 873.66 Hz, ξ = 0.261, and β = 0.25 for Dnom = 0.5. Chapter 16 Figure 16.1 Small-signal model of the PWM boost converter for DCM. (a) Circuit of the boost converter. (b) Small-signal model of the boost converter. (c) Modified small-

signal model of the boost converter. Figure 16.2 Small-signal model of the PWM boost converter for DCM for deriving the control-to-output transfer function Tp. Figure 16.3 Bode plot of the magnitude of Tp for the boost converter operated in DCM. Figure 16.4 Bode plot of the phase of Tp for the boost converter operated in DCM. Figure 16.5 Small-signal model of the PWM boost converter for DCM for deriving the input-to-output voltage transfer function Mv. Figure 16.6 Bode plot of the magnitude of Mv for the boost converter operated in DCM. Figure 16.7 Bode plot of the phase of Mv for the boost converter operated in DCM. Figure 16.8 Plot of the magnitude of Zi for the boost converter operated in DCM. Figure 16.9 Plot of the magnitude of Zi for the boost converter operated in DCM. Figure 16.10 Small-signal model of the PWM boost converter for DCM for deriving the output impedance Zo. Figure 16.11 Plot of the magnitude of Zo for the boost converter operated in DCM. Figure 16.12 Plot of the magnitude of Zo for the boost converter operated in DCM. Figure 16.13 Response of the output voltage vO to the step change of the input voltage ΔVI = 1 V from 10 to 11 V for the boost converter operated in DCM. Figure 16.14 Response of the output voltage vO to the step change of the duty cycle dT = 0.1 from 0.4 to 0.5 for the boost converter operated in DCM. Figure 16.15 Response of the output voltage vO to a step change of the load current ΔIO = 0.1 A from 2 to 2.5 A for the boost converter operated in DCM. Figure 16.16 Bode plot of the magnitude of Tpi for the boost converter operated in DCM. Figure 16.17 Bode plot of the magnitude of Tpi for the boost converter operated in DCM. Figure 16.18 Bode plot of the magnitude of Mvi for the boost converter operated in DCM. Figure 16.19 Bode plot of the phase of Mvi for the boost converter operated in DCM. Figure 16.20 Small-signal model of the PWM boost converter for DCM for deriving the output current-to-inductor current transfer function Ai. Figure 16.21 Bode plot of the magnitude of Ai for the boost converter operated in

DCM. Figure 16.22 Bode plot of the magnitude of Ai for the boost converter operated in DCM. Figure 16.23 Response of the inductor current iL to the step change of the input voltage ΔVI = 1 V from 10 to 11 V for the boost converter operated in DCM. Figure 16.24 Response of the inductor current iL to the step change of the duty cycle ΔdT = 0.1 from 0.4 to 0.5 for the boost converter operated in DCM. Figure 16.25 Response of the inductor current iL to the step change of the load current ΔIO = 0.1 A from 2 to 2.1 for the boost converter operated in DCM. Figure 16.26 DC model of the boost converter operated for DCM. Chapter 17 Figure 17.1 Shell structure of silicon atom. Figure 17.2 Energy band gap EG in a semiconductor. Figure 17.3 Intrinsic carrier concentrations ni as functions of temperature T for silicon and silicon carbide. Figure 17.4 Intrinsic carrier concentrations ni as functions of temperature 1000/T for silicon and silicon carbide. Figure 17.5 Energy levels in semiconductors. Figure 17.6 Donor in an n-type semiconductor. Figure 17.7 Donor concentration ND, intrinsic carrier concentration ni, majority electron concentration nn, and minority hole concentration pn as functions of temperature T for n-type silicon with ND = 1015 cm− 3. Figure 17.8 Acceptor in a p-type semiconductor. Figure 17.9 Donor concentration ND, intrinsic carrier concentration of silicon ni(Si), electron concentration for silicon nn(Si), hole concentration for silicon pn(Si), intrinsic carrier concentration of silicon-carbide ni(SiC), electron concentration for siliconcarbide nn(SiC), and hole concentration for silicon-carbide pn(SiC) as functions of temperature T for n-type semiconductors with ND = 1015 cm− 3. Figure 17.10 Shell structure of carbon atom. Figure 17.11 Cross section of pn junction diodes. (a) Cross section. (b) Symbol. Figure 17.12 Physical structure of p+ n step junction diodes, doping concentration profile, space-charge density ρ, electric field intensity E, and electrostatic potential

V(x). Figure 17.13 Silicon static diode characteristics at three temperatures T. Figure 17.14 Silicon-carbide static diode characteristics at three temperatures T. Figure 17.15 The effect of the voltage drop RSID across the neutral regions and the metal–semiconductor contacts on the diode characteristic at high currents. Figure 17.16 Piecewise-linear large-signal model of a diode. Figure 17.17 Depletion region width W as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3. Figure 17.18 Maximum electric field intensity Em as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3. Figure 17.19 Breakdown voltage VBD as a function of doping concentration ND at NA = 1017 cm− 3 for silicon and silicon-carbide diodes. Figure 17.20 Electric field intensity distribution for two levels of doping concentration ND. Figure 17.21 Electric field intensity distribution in pn junction, illustrating punchthrough breakdown voltage when xn = ln. Figure 17.22 Electric field distribution in the pn junction without and with guard ring. (a) Electric field concentration at the corner. (b) More evenly distributed electric field in the diode with guard ring. Figure 17.23 Depletion region profile in the pn junction diode with multiple guard ring termination. Figure 17.24 Changes in the charge stored in the depletion region and the depletion region width due to the diode voltage change ΔvD (usually for the reverse bias). The changes in the stored charge ΔQJn and the depletion region width on n-side Δxn results in the junction capacitance CJ. Figure 17.25 Charge QJn, junction capacitance CJ, and energy stored in the junction capacitance WCJ as functions of diode voltage vD. (a) Charge stored in the depletion region on the n-side. (b) Junction capacitance CJ. (c) Energy stored in the junction capacitance WCJ. Figure 17.26 Junction capacitance CJ as a function of diode voltage vD for Vbi = 0.75 V, ND = 1015 cm− 3, and AJ = 4 mm2. Figure 17.27 1/C2J as a function of diode voltage vD for Vbi = 0.75 V, ND = 1015 cm− 3, and AJ = 4 mm2.

Figure 17.28 Change in minority carrier charge stored in the bulk regions due to a diode voltage change around the dc quiescent diode voltage VDQ. The change in the excess carrier minority charge results in the diffusion capacitance CD. Figure 17.29 Large-signal model of a pn junction diode. Figure 17.30 Small-signal model of a pn junction diode. Figure 17.31 Change in minority carrier charge stored in the bulk regions during the turn-off transition. This charge must be removed when the diode is turned-off from forward to reverse bias. Figure 17.32 Hole distribution in the n-region as a function of time during the turn-off transition. Figure 17.33 Circuit for studying the on-to-off and off-to-on transitions in diodes. Figure 17.34 Waveforms for on-to-off and off-to-on transitions in junction diodes. Figure 17.35 Dynamic iD-vD diode characteristic during the turn-off transition in resistive circuit with square wave driving voltage. Figure 17.36 Waveforms for pn junction diode during the turn-on transition. Figure 17.37 Waveforms for pn junction diode during the storage time ts. Figure 17.38 Waveform of the excess minority charge Qp for pn junction diode during the storage time ts. Figure 17.39 Waveforms for pn junction diode during the transient time tt. Figure 17.40 Idealized current and voltage waveforms of a pn junction diode illustrating the reverse recovery in inductive circuits. Figure 17.41 Dynamic iD-vD diode characteristic during the turn-off transition in inductive circuits. Figure 17.42 Dependence of the peak reverse recovery diode current IR on the slope |diF/dt| during the turn-off transition in inductive circuits. Figure 17.43 Physical structure of Schottky diodes. Figure 17.44 Cross section of silicon-carbide Schottky diodes. Figure 17.45 Waveforms of Schottky diodes illustrating the turn-off and turn-on transitions. Figure 17.46 Waveform of the current through the junction capacitance CJ during the turn-off transition for the Cree CSD10060 SiC Schottky diode at CJ0 = 381 pF, Vbi = 9.99 V, R = 500 Ω, Vm = 9 V, f = 200 kHz, and T = 300 K.

Figure 17.47 Waveforms for Schottky diodes during turn-off transition. Figure 17.48 Waveforms for Schottky diodes during turn-on transition. Figure 17.49 Solar cell and dark current characteristics of pn junction at ISC = 0.5 A and IS = 10− 10 A. Figure 17.50 Power delivered by a solar cell at ISC = 0.5 A and IS = 10− 10 A. Figure 17.51 SPICE large-signal model for diodes. Chapter 18 Figure 18.1 Physical structure of IC MOSFET. Figure 18.2 Physical structure of n-channel power MOSFET (NMOS). Figure 18.3 Three-dimensional structure of power MOSFETs. Figure 18.4 Commonly used patterns of power MOSFET cells. (a) Squares on a square grid. (b) Hexagons on a hexagonal grid. Figure 18.5 Square pattern of n-channel power MOSFET. Figure 18.6 Physical structure of p-channel power MOSFET (PMOS). Figure 18.7 Complete and simplified circuit symbols for enhancement power MOSFETs. (a) For n-channel power MOSFET (NMOS). (b) For p-channel power MOSFET (PMOS). Figure 18.8 Channel structure in the linear region when vDS increases at vGS > Vt. Figure 18.9 Channel structure in the saturation region when vDS increases. at vGS > Vt. Figure 18.10 Voltages in the MOSFET structure in the linear region. (a) For vDS = 0. (b) For 0 < vDS < vDSsat. Figure 18.11 Voltages in the MOSFET structure in the saturation region. (a) The channel is pinched off at the drain. (b) The channel is pinched off between the drain and the source. Figure 18.12 Channel profile in the saturation (pinch-off) region. Figure 18.13 Input and output characteristics of n-channel MOSFET. Figure 18.14 Low-field electron mobility μn and hole mobility μp as functions of doping concentration N at T = 300 K for silicon. Figure 18.15 Low-field resistivities ρn and ρp as functions of doping concentration N at T = 300 K for silicon. Figure 18.16 Low-field electron mobility μn and hole mobility μp as functions of doping concentration N at T = 300 K for silicon carbide.

Figure 18.17 Low-field resistivities ρn and ρp as functions of doping concentration N at T = 300 K for silicon carbide. Figure 18.18 Low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon. Figure 18.19 Low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon. Figure 18.20 Low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon carbide. Figure 18.21 Resistivities ρn and ρp as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon. Figure 18.22 Average electron drift velocity vn as a function of electric field intensity E for μn0 = 1360 cm2/V • s, vsat = 8 × 106 cm/s, and T = 300 K for silicon. Figure 18.23 Electron mobility μn as a function of electric field intensity E for μn0 = 1360 cm2/V • s, vsat = 8 × 106 cm/s, and T = 300 K for silicon. Figure 18.24 Electron mobility μn as a function of electric field intensity E and temperature T for μn0 = 1360 cm2/V • s, vsat = 8 × 106 cm/s for silicon. Figure 18.25 Resistivities of ρn and ρp as functions of electric field intensity E for μn0 = 1360 cm2/V • s, μp0 = 480 cm2/V • s, vsat = 8 × 106 cm/s, N = 1015 cm− 3, and T = 300 K for silicon. Figure 18.26 Average electron drift velocity vn as a function of electric field intensity E for silicon carbide. Figure 18.27 Electron mobility μn as a function of electric field intensity E for silicon carbide. Figure 18.28 Electron saturation drift velocity vn(sat) and hole saturation drift velocity vp(sat) as functions of temperature T for silicon. Figure 18.29 MOSFET iD–vGS characteristics described by square law, linear law, and exact equation for Vt = 1 V, μn0 = 600 cm2/(V • s), mF/m2, W/L = 105, vsat = 8 × 106 cm/s, and λ = 0. Exact plot: L = 2 μm and θ = 1.51/V. Linear law: L = 0.5 μm and W = 0.5 × 105 μm. Figure 18.30 MOSFET iD–vDS characteristics described by square law, linear law, and exact equation at a fixed gate-to-source voltage vGS0 for Vt = 1 V, μn0 = 600 cm2/(V • s),

mF/m2, W/L = 105, vsat = 8 × 106 cm/s, and λ = 0. Exact plot: L = 2 μm and

θ = 0.375. Linear law: L = 0.5 μm and W = 0.5 × 105 μm. Figure 18.31 Specific drift resistance ARDR as a function of breakdown voltage VBD for silicon and silicon carbide. Figure 18.32 Components of on-resistance rDS for power MOSFETs. Figure 18.33 Long-channel resistance RCh and short-channel resistance RCh(sc) as functions of voltage vGS − Vt at μn = 600 cm2/V • s, Cox = 34.5 nF/cm2, W/L = 1.4 × 106, Vt = 3.5 V, θ = 0.2 V− 1 for power MOSFET. Figure 18.34 Top view of accumulation region. Figure 18.35 Piecewise-linear model of the MOSFET operated as a switch in the linear and cutoff regions with the voltage-controlled on-resistance rDS. Figure 18.36 Capacitances of power MOSFET. Figure 18.37 Top view of the MOSFET gate used to determine capacitance Cgm. Figure 18.38 Components of gate-to-drain capacitance Cgd of power MOSFET for 2xn < dpp, when vDS is moderate. Figure 18.39 Top view of the gate-oxide-accumulation region capacitance Cga of power MOSFET for vDS(ON) < vDS < vDS(cr) and xn > 0. Figure 18.40 Components of gate-to-drain capacitance Cgd of power MOSFET for 2xn = dpp, when vDS is high. Figure 18.41 Power MOSFET capacitances as functions of transistor voltages. Figure 18.42 Drain-to-source capacitance Cds as a function of the drain-to-source voltage vDS. Figure 18.43 Capacitance CDn as a function of the drain-to-source voltage vDS. Figure 18.44 Neck area An as a function of the drain-to-source voltage vDS for 2xn < dpp, when vDS is moderate (0 ≤ vDS ≤ vDS(cr)). Figure 18.45 Capacitances Cga1 and Cga2 as functions of the drain-to-source voltage vDS for 2xn < dpp, when vDS is moderate (0 ≤ vDS ≤ vDS(cr)). Figure 18.46 Gate-to-drain capacitance Cgd as a function of the drain-to-source voltage vDS for 2xn < dpp, when vDS is moderate (0 ≤ vDS ≤ vDS(cr)). Figure 18.47 Capacitance CJn as a function of the drain-to-source voltage vDS for 2xn = dpp, when vDS is high (vDS(cr) ≤ vDS ≤ VDSS). Figure 18.48 Gate-to-drain capacitance Cgd as a function of the drain-to-source voltage

vDS for 2xn = dpp, when vDS is high (vDS(cr) ≤ vDS ≤ VDSS). Figure 18.49 Gate-to-drain capacitance Cgd as a function of the drain-to-source voltage vDS. Figure 18.50 Capacitances Ciss, Crss, and Coss as functions of the drain-to-source voltage vDS. Figure 18.51 Capacitances Ciss, Crss, and Coss as functions of the drain-to-source voltage vDS. Figure 18.52 MOSFET waveforms during the turn-on and turn-off transitions. Figure 18.53 SPICE large-signal model for n-channel MOSFET (NMOS). The body B is short-circuited to the source S for power MOSFETs. Figure 18.54 Cross section of the n-channel IGBT. Figure 18.55 IGBT. (a) Equivalent circuit of n-channel IGBT, a composite device that consists of an n-channel MOSFET and a pnp BJT. (b) Symbols. Figure 18.56 Heat transfer by conduction. (a) Layer conducting heat. (b) Temperature distribution in a layer of heat conductor. Figure 18.57 Heat transfer by convection. (a) Air flow along a hot surface. (b) Temperature distribution. (c) Air velocity distribution. Figure 18.58 Electrical equivalent circuits for heat transfer in semiconductor devices. (a) Thermal model for steady-state operation. (b) Thermal model for transients. Figure 18.59 The maximum power dissipation PDmax as a function of the case temperature TC. Chapter 19 Figure 19.1 Equivalent circuits for conducted noise. (a) Equivalent circuit for the common-mode noise. (b) Equivalent circuit for the differential-mode noise. Figure 19.2 Common-mode EMI filter. Figure 19.3 Currents in common-mode EMI filter. (a) Common currents and magnetic flux. (b) Differential currents and magnetic flux.

About the Author Marian K. Kazimierczuk is Frederick A. White Distinguished Professor of Electrical Engineering at Wright State University, Dayton, Ohio, USA. He received the M.S., Ph.D., and D.Sc. degrees from Warsaw University of Technology, Department of Electronics, Warsaw, Poland. He is the author of six books, over 180 archival refereed journal papers, over 210 conference papers, and seven patents. His research interests are in power electronics, including RF high-efficiency power amplifiers and oscillators, PWM dc–dc power converters, resonant dc–dc power converters, modeling and controls of power converter, high-frequency magnetic devices, electronic ballasts, active power factor correctors, semiconductor power devices, wireless charging systems, renewable energy sources, energy harvesting, green energy, and evanescent microwave microscopy. Professor Kazimierczuk is a Fellow of the IEEE. He served as Chair of the Technical Committee of Power Systems and Power Electronics Circuits, IEEE Circuits and Systems Society. He served on the Technical Program Committees of the IEEE International Symposium on Circuits and Systems (ISCAS) and the IEEE Midwest Symposium on Circuits and Systems. He also served as Associate Editor of the IEEE Transactions on Circuits and Systems, Part I, Regular Papers, IEEE Transactions on Industrial Electronics, International Journal of Circuit Theory and Applications, and Journal of Circuits, Systems, and Computers, and as Guest Editor of the IEEE Transactions on Power Electronics. He was an IEEE Distinguished Lecturer. Professor Kazimierczuk received the Presidential Award for Outstanding Faculty Member at Wright State University in 1995. He was Brage Golding Distinguished Professor of Research at Wright State University in 1996–2000. He received the Trustees’ Award from Wright State University for Faculty Excellence in 2004. He received the Outstanding Teaching Award from the American Society for Engineering Education (ASEE) in 2008. He was also honored with the Excellence in Research Award, Excellence in Teaching Awards, and Excellence in Professional Service Award in the College of Engineering and Computer Science, Wright State University. He is listed in Top Authors in Engineering and Top Authors in Electrical & Electronic Engineering. Professor Kazimierczuk is the author or co-author of six books: Resonant Power Converters, 2nd Ed., Wiley, Pulse-Width Modulated DC–DC Power Converters, IEEE Press/Wiley, HighFrequency Magnetic Components, 2nd Ed. (translated in Chinese), Wiley, RF Power Amplifiers, 2nd Ed. (translated in Chinese), Wiley, Electronic Devices, A Design Approach, Pearson/Prentice Hall, and Laboratory Manual to Accompany Electronic Devices, A Design Approach, 2nd Ed., Pearson/Prentice Hall.

Preface This book is about switching-mode dc–dc power converters with pulse-width modulation (PWM) control. It is intended as a power electronics textbook at the senior and graduate levels for students majoring in electrical engineering, as well as a reference for practicing engineers in the area of power electronics. The purpose of the book is to provide foundations for semiconductor power devices, topologies of PWM switching-mode dc–dc power converters, modeling, dynamics, and controls of PWM converters. The book is devoted to energy conversion. The first part of the book covers topologies of transformerless and isolated PWM converters, such as buck, boost, and buck–boost, flyback, forward, half-bridge, and full-bridge converters. The second part covers small-signal circuit models of PWM converters, transfer functions of PWM converter power stages, voltage-mode control, and current-mode control of PWM converters. The third part presents silicon and silicon carbide power devices. The textbook assumes that the student is familiar with general circuit analysis techniques and electronic circuits. Complete solutions for all problems are included in the Solutions Manual, which is available from the publisher for those instructors who adopt the book for their courses. I am pleased to express my gratitude to Dr. Nisha Kondrath and Agasthya Ayachit for MATLAB® figures, proofreading, suggestions, and critical evaluation of the manuscript. Throughout the entire course of this project, the support provided by John Wiley & Sons was excellent. I wish to express my sincere thanks to Ella Mitchell, Associate Commissioning Editor, Electrical Engineering; Peter Mitchell, Publisher, Engineering Technology; and Richard Davis, Senior Project Editor. It has been a real pleasure working with them. Last but not least, I wish to thank my family for the support. The author would welcome and greatly appreciate suggestions and corrections from the readers, for the improvements in the technical content as well as the presentation style. Marian K. Kazimierczuk

Nomenclature A Ai

Transfer function of forward path in negative feedback system Inductor-to-load current transfer function

AJ

Cross-sectional area of junction

BW

Bandwidth

C Cb

Filter capacitance Blocking capacitance

Cc

Coupling capacitance

Cds

Drain–source capacitance of MOSFET

Cgd

Gate–drain capacitance of MOSFET

Cgs

Gate–source capacitance of MOSFET

Ciss

MOSFET input capacitance at VDS = 0, Ciss = Cgs + Cgd

Cmin

Minimum value of filter capacitance C

Co

Transistor output capacitance

Coss

MOSFET output capacitance at VGD = 0, Coss = Cgs + Cds

Cox

Oxide capacitance per unit area

Crss

MOSFET transfer capacitance, Crss = Cgd

c D d dm

Speed of light DC component of on-duty cycle of switch AC component of on-duty cycle of switch Amplitude of small-signal component of on-duty cycle of switch

dT

Total on-duty cycle of switch

ESR fc

Equivalent series resistance of capacitors and inductors Gain-crossover frequency

fz

Frequency of zero of transfer function

f0

Corner frequency

fp

Frequency of pole of transfer function

fs

Switching frequency

f− 180

Phase-crossover frequency

Hsh

Transfer function of sampler and zero-order hold

ICrms

rms value of capacitor current iC

Ipk

Magnitude of cross-conduction current

Irms

rms value of current i

ID

Average diode current

IDM

Peak diode current

IDrms

rms value of diode current

II

DC input current of converter

IL

Average current through inductor L

ILB

Average current through inductor L at CCM/DCM boundary

IO

DC output current of converter

IOmax

Maximum value of dc load current IO

IOmin

Minimum value of dc load current IO

IOB

DC output current at the boundary between CCM and DCM

ISM

Peak switch current

ISrms

rms value of switch current iS

ii

AC component of input current

i0i(t)

Zero-order-hold AC component of input current

io

AC component of load current

iC

Current through filter capacitor C

iD

Diode current

iL

Current through inductor L

iO

Total load current

iS

Switch current

Ki

Input feedforward gain

Ko

Output feedforward gain

k L

Boltzmann constant Inductance, Channel length

Le

Effective channel length

Ln

Electron diffusion length

Lp

Hole diffusion length

Lm

Magnetizing inductance of transformer

Lmax

Maximum inductance L for DCM operation

Lmin

Minimum inductance L for CCM operation

LNR LOR MIDC

Line regulation Load regulation DC current transfer function of converter

MVDC DC voltage transfer function of converter Mv

Open-loop input-to-output voltage function of converter

Mvcl

Closed-loop input-to-output voltage function of converter

Mvi

Open-loop input voltage-to-inductor current transfer function

Mvo

Open-loop input-to-output voltage function of converter at f = 0

me

Mass of free electron

me*

Effective mass of electron

mh

Mass of hole

mh*

Effective mass of hole

NA

Concentration of acceptors

ND

Concentration of donors

Np

Number of turns of primary winding

Ns

Number of turns of secondary winding

n

Transformer turns ratio, electron concentration density

n+ ni

Electron concentration of heavily doped semiconductor by donors Intrinsic carrier concentration

nn

Majority electron concentration

np

Minority electron concentration

np0

Thermal equilibrium minority electron concentration

pn

Minority hole concentration

pn0

Thermal equilibrium minority hole concentration

pp

Majority hole concentration

PM Pton

Phase margin Turn-on switching losses

PD

Total diode conduction loss

PFET

Overall power dissipation in MOSFET (excluding gate-drive power)

PG

Gate-drive power

PI

DC input power of converter

PLS

Overall power dissipation of converter

PM PO

Phase margin DC output power of converter

PRF

Conduction loss in diode forward resistance RF

PrC

Conduction loss in filter capacitor ESR

PVF

Conduction loss in diode offset voltage VF

p

Hole concentration

p+ Q Qg

Hole concentration of heavily doped semiconductor by acceptors Quality factor Gate charge

QF

Forward stored charge

Qrr

Reverse recovery charge

q RDR

Magnitude of electron charge Resistance of drift region

RF

Diode forward resistance

RL

DC load resistance

RLB

DC load resistance at CCM/DCM boundary

RLmax

Maximum value of load resistance RL

RLmin

Minimum value of load resistance RL

rC

Equivalent series resistance (ESR) of filter capacitor

rDS

On-resistance of MOSFET

q S

Electron charge Specific resistance of drift region

Smax

Maximum percentage overshoot

SR

Slew rate of op-amps

T TA

Switching period, Loop gain Ambient temperature

Tc

Voltage transfer function of controller

Tcl

Closed-loop control-to-output transfer function

Ti

Loop gain of current loop

TJ

Junction temperature

Tm

Transfer function of pulse-width modulator

Tp

Open-loop control-to-output transfer function

Tpi

Open-loop duty cycle-to-inductor current transfer function

Tpo

Open-loop control-to-output transfer function at f = 0

THD tf

Total harmonic distortion Fall time

tr

Rise time

trr

Reverse recovery time

Vbi

Built-in potential

VC

DC component of control voltage

Vcm

Amplitude of small-signal component of control voltage

VCpp

Peak-to-peak ripple voltage of the filter capacitance

VE

DC component of error voltage

Vt

Gate-to-source threshold voltage

VBD

Breakdown voltage

VBR

Reverse blocking (breakdown) voltage

VDM

Reverse peak voltage of diode

VDS

Drain–source dc voltage of MOSFET

VDSS

Drain–source breakdown voltage of MOSFETs

VF

Diode offset voltage, dc component of feedback voltage

VGD

Gate-to-drain voltage of MOSFET

VGSpp Peak-to-peak gate-to-source voltage VI

DC component of input voltage of converter

VO

DC output voltage of converter

VR

DC reference voltage

Vr

Peak-to-peak value of output ripple voltage

Vrcpp

Peak-to-peak ripple voltage across ESR

VSM

Peak switch voltage

VT

Thermal voltage

VTm

Peak ramp voltage of pulse-width modulator

vC

Total control voltage

vc

AC component of control voltage

v*c(t)

Sampled AC component of control voltage

v*c(jω) Spectrum of sampled AC component of control voltage vDS

Drain–source voltage of MOSFET

vE

Total error voltage

vF

Total feedback voltage

ve

AC component of error voltage

vd

Average drift velocity

vf

AC component of feedback voltage

vL

Voltage across inductance L

vi

AC component of converter input voltage

vo

AC component of converter output voltage

vsat

Saturation velocity of carriers

vr

AC component of reference voltage

vrc

Voltage across ESR of filter capacitor

vth

Thermal velocity of electron

vsat

Saturated average drift velocity

W WC

Channel width Energy stored in capacitor

WL

Energy stored in inductor

Zi

Open-loop input impedance of converter

Zicl

Closed-loop input impedance of converter

Zo

Open-loop output impedance of converter

Zocl

Closed-loop output impedance of converter

β ΔiL

Transfer function of feedback network Peak-to-peak of inductor ripple current

η θ μ μp

Efficiency of converter Thermal resistance Carrier mobility Mobility of holes

μn

Mobility of electrons

ξ ρ σ τ τn

Damping ratio Resistivity Conductivity, Damping factor Minority carrier lifetime, Time constant Electron lifetime

τp

Hole lifetime

ϕ ψ ω ωc

Phase of transfer function, Magnetic flux Initial phase Angular frequency Unity-gain angular crossover frequency

ωd

Damped angular resonant frequency

ω0

Corner angular frequency

ωp

Angular frequency of simple pole

ωz

Angular frequency of simple zero

1 Introduction 1.1 Classification of Power Supplies Power supply technology is an enabling technology that allows us to build and operate electronic circuits and systems [1–28]. All active electronic circuits, both digital and analog, require power supplies. Many electronic systems require several dc supply voltages. Power supplies are widely used in computers, telecommunications, instrumentation equipment, aerospace, medical, and defense electronics. A dc supply voltage is usually derived from a battery or an ac utility line using a transformer, rectifier, and a filter. The resultant raw dc voltage is not constant enough and contains a high ac ripple that is not appropriate for most applications. Voltage regulators are used to make the dc voltage more constant and to attenuate the ac ripple. A power supply is a constant voltage source with a maximum current capability. There are two general classes of power supplies: regulated and unregulated. The output voltage of a regulated power supply is automatically maintained within a narrow range, e.g., 1 or 2% of the desired nominal value, in spite of line voltage, load current, and temperature variations. Regulated dc power supplies are called dc voltage regulators. There are also dc current regulators, such as battery chargers. Figure 1.1 shows a classification of regulated power supply technologies. Two of the most popular categories of voltage regulators are linear regulators and switching-mode power supplies (SMPS). There are two basic linear regulator topologies: the series voltage regulator and the shunt voltage regulator. The switching-mode voltage regulators are divided into three categories: pulse-width modulated (PWM) dc–dc converters, resonant dc–dc converters, and switched-capacitor (also called charge-pump) voltage regulators. In linear voltage regulators, transistors are operated in the active region as dependent current sources with relatively high voltage drops at high currents, dissipating a large amount of power and resulting in low efficiency. Linear regulators are heavy and large, but they exhibit low noise level and are suitable for audio applications.

Figure 1.1 Classification of power supply technologies. In switching-mode converters, transistors are operated as switches, which inherently dissipate much less power than transistors operated as dependent current sources. The voltage drop across the transistors is very low when they conduct high current and the transistors conduct a nearly zero current when the voltage drop across them is high. Therefore, the conduction losses are low and the efficiency of switching-mode converters is high, usually above 80% or 90%. However, switching losses reduce the efficiency at high frequencies. Switching losses increase proportionally to switching frequency. Linear and switched-capacitor regulator circuits (except for large capacitors) can be fully integrated and are used in low-power and low-voltage applications, usually below several watts and 50 V. PWM and resonant regulators are used at high power and voltage levels. They are small in size, light in weight, and have high conversion efficiency. Figure 1.2 shows block diagrams of two typical ac–dc power supplies that convert the widely available ac power to dc power. The power supply of Figure 1.2(a) contains a dc linear voltage regulator, whereas the power supply of Figure 1.2(b) contains a switching-mode voltage regulator. The power supply shown in Figure 1.2(a) consists of a low-frequency stepdown power line transformer, a front-end rectifier, a low-pass filter, a linear voltage regulator, and a load. The nominal voltage of the ac utility power line is 110 Vrms in the United States and 230 Vrms in Europe. However, the actual line voltage varies within a range of about ± 20% of the nominal voltage. The frequency of the ac line voltage is very low (50 Hz in Europe, 60 Hz in United States, 400 Hz in aircraft applications, and 20 kHz in space applications). The line transformer provides dc isolation from the ac power line and reduces a relatively high line voltage to a lower voltage (ranging usually from 5 to 28 Vrms). Since the frequency of the ac line voltage is very low, the line transformer is heavy and bulky. The output voltage of the front-end rectifier/filter is unregulated and it varies because the peak voltage of the ac line

varies. Therefore, a voltage regulator is required between the rectifier/filter and the load. There still exists a need for universal power supplies that can accept any utility line voltage in the world, ranging from 85 to 264 Vrms.

Figure 1.2 Block diagrams of ac–dc power supplies. (a) With a linear regulator. (b) With a switching-mode voltage regulator. The power supply shown in Figure 1.2(b) consists of a front-end rectifier, a low-pass filter, an isolated dc–dc switching-mode voltage regulator, and a load. It is run directly from the ac line. The ac voltage is rectified directly from the ac power line, which does not require a bulky low-frequency line transformer. Hence, such a circuit is called an off-line power supply (plug into the wall). The switching-mode voltage regulator contains a high-frequency transformer to obtain dc isolation for the entire power supply. Since the switching frequency is much higher than that of the ac line frequency, the size and weight of a high-frequency transformer as well as inductors and capacitors is reduced. The switching frequency usually ranges from 25 to 500 kHz. To avoid audio noise, the switching frequency should be above 20 kHz. A PWM switching-mode voltage regulator generates a high-frequency rectangular voltage wave, which is rectified and filtered. The duty cycle (or the pulse width) of the rectangular wave is varied to control the dc output voltage. Therefore, these voltage regulators are called PWM dc–dc converters. Power converters are required to convert one form of electric energy to another. A dc–dc converter is a power supply that converts a dc input voltage into a desired regulated dc output voltage. The dc input may be an unregulated or regulated voltage. Often, the input of a dc–dc converter is a battery or a rectified ac line voltage. A voltage regulator should provide a constant voltage to the load, even if line voltage, load current, and temperature vary. Unlike in linear voltage regulators, the output voltage in PWM dc–dc converters may be either lower or higher than the input voltage and are called either step-down or step-up converters. In a step-

down converter, the output voltage is lower than the input voltage. In a step-up converter, the output voltage is higher than the input voltage. Some converters may act as both step-down and step-up converters. The output voltage source may be of the same polarity (noninverting) or opposite polarity (inverting) to that of the polarity of the input voltage. The dc–dc converters may have common negative or common positive input and output terminals. Converters may have a single output or multiple outputs. In addition, there are fixed or adjustable output voltage power supplies. Fixed output voltage supplies (e.g., 1.8 V) are used for power electronic circuits that require a specific supply voltage. Power supplies with adjustable output voltage (e.g., from 0 to 30 V) are convenient for laboratory tests. In some applications, programmable power supplies with digitally selected output voltages are required. Power supplies may be nonisolated or isolated. Transformers can be used to obtain dc isolation between the input and output and between the different outputs. Common requirements of most power supplies are: high efficiency, high power density, high reliability, and low cost.

1.2 Basic Functions of Voltage Regulators The simplest voltage regulator is a Zener diode regulator, shown in Figure 1.3. It is a shunt regulator. However, the performance of the Zener diode regulator is not satisfactory for most applications. Therefore, negative feedback techniques are usually used in voltage regulators to improve the performance. A block diagram of a voltage regulator with negative feedback is shown in Figure 1.4. It consists of a power stage (a dc–dc converter), a feedback network, a reference voltage Vref , and a control circuit (also called an error amplifier). The feedback network monitors the output voltage and reduces the error signal. The control circuit compares the feedback voltage with the reference voltage, generates an error voltage, amplifies it, and adjusts the transistor base current to keep the output voltage VO constant.

Figure 1.3 Zener diode voltage regulator.

Figure 1.4 Block diagram of a voltage regulator with negative feedback. The load current IO may vary over a very wide range: IOmin ≤ IO ≤ IOmax. Consequently, the load resistance RL = VO/IO also varies over a wide range: RLmin ≤ RL ≤ RLmax, where RLmin = VO/IOmax and RLmax = VO/IOmin. Most regulated power supplies have a short-circuit or currentoverload protection circuit, which limits the output current to a safe level to protect the power supply and/or the load. The input voltage of a voltage regulator is usually unregulated and can vary over a wide range: VImin ≤ VI ≤ VImax. For example, the dc input voltage in telecommunication power supplies is 36 ≤ VI ≤ 72 V with a nominal input voltage VInom = 48 V. The input voltage source may be a battery, a rectified single-phase or three-phase ac line voltage. The output voltage of a battery decreases when the battery is discharged. The peak voltage of a utility line varies as much as 10% or 20%, causing the rectified dc voltage to vary. The operating temperature of semiconductor and passive devices may also change from Tmin to Tmax, affecting the performance of power supplies. The basic functions of a dc–dc converter are as follows: 1. to provide conversion of a dc input voltage VI to the desired dc output voltage within a tolerance range, for example, VO = 1.2 V±1%; 2. to regulate the output voltage VO against variations in the input voltage VI, the load current IO (or the load resistance RL), and the temperature; 3. to reduce the output ripple voltage below the specified level; 4. to ensure fast response to rapid changes in the input voltage and load current (or load

resistance); 5. to provide dc isolation; 6. to provide multiple outputs; 7. to minimize the electromagnetic interference (EMI) below levels specified by EMI standards.

1.3 Power Relationships in DC–DC Converters The input current iI of many switching-mode dc–dc converters is pulsating. The dc component of the converter input current is given by (1.1) Hence, the dc input power of a dc–dc converter is (1.2) The ac components of the output voltage and current are assumed to be very small and can be neglected. Therefore, dc output power of a dc–dc converter is (1.3) and the power loss in the converter is (1.4) The efficiency of the dc–dc converter is (1.5) from which (1.6) The normalized power loss PLS/PO decreases as the converter efficiency increases. For example, for η = 25%, PLS/PO = 300%, but for η = 95%, PLS/PO = 5.26%.

1.4 DC Transfer Functions of DC–DC Converters The dc voltage transfer function (also called the dc voltage conversion ratio or the dc voltage

gain) of a dc–dc converter is (1.7) and the dc current transfer function of a dc–dc converter is (1.8) Hence, the efficiency of a dc–dc converter is (1.9) From (1.7), (1.8), and (1.9), (1.10) and (1.11) These equations can be represented by the dc circuit model of a dc–dc converter shown in Figure 1.5.

Figure 1.5 A dc model of a dc–dc converter.

1.5 Static Characteristics of DC Voltage Regulators The quality of a power supply can be described by three parameters: line regulation, load regulation, and thermal regulation. The output voltage VO of most voltage regulators increases as the input voltage VI increases, as shown in Figure 1.6. Therefore, one figure-of-merit of

voltage regulators for steady-state operation is line regulation, which is a measure of the regulator’s ability to maintain the predescribed nominal output voltage VOnom under slowly varying input voltage conditions.

Figure 1.6 Output voltage Vo versus input voltage VI for voltage regulators illustrating line regulation. The line regulation is the ratio of the output voltage change ΔVO to a corresponding change in the input voltage (1.12) where TA is the ambient temperature. For example, for a linear voltage regulator LM140, ΔVO = 10 mV at IO = 0.5 A, TA = 25°C, and 7.5 V≤ VI ≤ 20 V. Hence, LNR = 10/(20 − 7.5) = 0.8 mV/V. The percentage line regulation (PLNR) is defined as the ratio of the percentage change in the output voltage to a corresponding change in the input voltage

(1.13)

where TA is the ambient temperature. Ideally, the line regulation should be zero, in which case the output voltage is independent of the input voltage. In practice, the line regulation (LNR) should be less than 0.1%. For example, for a linear voltage regulator LM317, the typical value of the line regulation is PLNR = 0.01%/V at IO = 20 mA, TA = 25°C, and 3 V ≤ (VI − VO) ≤ 40 V. The output voltage VO of voltage regulators decreases as the load current IO increases due to a varying load resistance, as shown in Figure 1.7. Hence, the second figure-of-merit of voltage regulators for steady-state operation is load regulation, which is a measure of the regulator’s ability to maintain a constant output voltage VOnom under slowly varying load conditions over a certain range of load current, usually from zero load current to a maximum load current IOmax.

Figure 1.7 Output voltage VO versus output current IO for voltage regulators illustrating load regulation. The load regulation is given by

(1.14)

The load regulation LOR should be less than 1%. The percentage load regulation for voltage regulators that have no minimum load requirement is defined as (1.15) where VO(NL) is the no-load (open-circuit) output voltage and VO(FL) is the full-load output voltage, which corresponds to a maximum load current IOmax. In some voltage regulators, such as PWM converters operated in the continuous conduction mode, the minimum load current IOmin is not zero. The output voltage at the minimum load current is VO(minL). In this case, the load regulation is defined as (1.16) For an ideal voltage regulator, the load regulation is zero. For example, for a linear voltage regulator LM117, PLOR2 = 0.3% for 5 mA≤ IO ≤ 100 mA and TA = 25°C. The line regulation and the load regulation can be combined into a line/load regulation (1.17)

Sometimes power supply manufacturers specify the equivalent dc output resistance Ro. A dc model of a real voltage source consists of an ideal voltage source V and an output resistance Ro, as shown in Figure 1.8. The output voltage is given by (1.18) from which (1.19) Hence, the incremental or dynamic output resistance is defined as the ratio of change in the output voltage to the corresponding change in the load current (1.20)

When IOmin = 0, the dc output resistance is given by (1.21) The output resistance of a voltage regulator should be as low as possible so that a change in the output current ΔIO will result only in a small change in the output voltage ΔVO = −RoΔIO. Ideally, Ro should be zero, resulting in the output voltage that is independent of the load current. At high frequencies (or for fast changes in the load current), the output resistance has a complex output impedance. From Figure 1.8, the output voltage at the full load resistance RFL = RLmin is (1.22) Hence, the percentage load regulation when the voltage regulator operates from full load to noload can be expressed as (1.23)

Figure 1.8 DC model of voltage source with an output resistance. A very low output resistance can be obtained by using negative feedback with shunt connection of the power stage and the feedback network at the output. The relationship between the openloop output resistance Ro and the closed-loop output resistance Rof is (1.24) where A is the dc (or low-frequency) voltage gain of the forward path and β is the transfer function of the feedback network.

A third figure-of-merit of voltage regulators is the thermal regulation defined as (1.25)

where ΔPD is the change in power dissipation. For example, for a linear voltage regulator LM317, THR = 0.04%/W. The static or dc input resistance of a dc voltage regulator at a given operating point Q is (1.26) Since (1.27) and (1.28) the converter efficiency can be expressed as (1.29)

Hence, one obtains the dc input resistance of dc voltage regulators as a function of load resistance RL and the dc–dc voltage transfer function (1.30)

1.6 Dynamic Characteristics of DC Voltage Regulators Voltage regulators should minimize the amount of ripple voltage at the output. The parameter that describes this feature is called the ripple rejection ratio defined as (1.31) where Vr is the output ripple resulting from an input ripple Vri. For example, for a linear

voltage regulator LM317, RRR = 80 dB = 104 at f = 120 Hz. If the input ripple Vri = 1 V, then the output ripple is Vr = Vri/RRR = 1/104 = 0.1 mV. Dynamic transient performance of voltage regulators is described by line transient response and load transient response. In general, transient response is the shape of a signal as it moves between two steady-state points. Figure 1.9 shows a circuit for testing line transient response of voltage regulators. A test is made at a fixed load current IO, usually 50% of its rated fullload current IOmax. The input voltage vI contains step changes of magnitude ΔvI superimposed on its dc component VI, as shown in Figure 1.10(a). As a result, the output voltage vO contains transients just after the step changes in the input voltage, as shown in Figure 1.10(b). When the input voltage vI abruptly increases, the output voltage vO also increases initially and then returns to a steady-state value. On the other hand, when the input voltage vI abruptly decreases, the output voltage also decreases initially and then returns to a steady-state value. The abrupt change in the input voltage may cause an oscillatory (or underdamped) response characterized by overshoot and undershoot through the limits of a static regulation band. The response may be overdamped or critically damped. A closed-loop step response should be nonoscillatory. An oscillatory step response of a closed-loop circuit indicates that the margins of stability are too low or the circuit is unstable. The settling time ts and the transient component Vpk should be below the specified levels.

Figure 1.9 Circuit for testing the line transient response of voltage regulators.

Figure 1.10 Waveforms illustrating line transient response of voltage regulators. (a) Waveform of the input voltage vI. (b) Waveform of the output voltage vO. Figure 1.11 shows a circuit for testing a transient response to a sudden electrical load changes. The input voltage VI is held constant, usually at the nominal value VInom. Step changes in the load current are obtained using an active load that acts like a current sink. Its waveform is a square wave with a dc offset, as shown in Figure 1.12(a). The step changes in the load current cause a transient response in the converter output voltage. When the load current is abruptly decreased, the output voltage initially increases and then returns to its steady-state value. The two parameters of output voltage are the peak transient voltage Vpk and the settling time ts. The settling time ts should be less than 200–500 ms and Vpk should be below a specified value. Usually, nonoscillatory response is expected in closed-loop power supplies to ensure sufficient stability margins.

Figure 1.11 Circuit for testing the transient response to a sudden electrical load change using an active current sink.

Figure 1.12 Waveforms illustrating load transient response of voltage regulators. (a) Waveform of the load current iO. (b) Waveform of the output voltage vO. Another circuit for testing the load transient response is shown in Figure 1.13. The input voltage VI is held constant, usually at the nominal value VInom. A step change in the load current may be obtained by switching the load resistance RL. A resistor R1 is connected in parallel with a series combination of a resistor R2 and a fast switch, for example, a power metal-oxide-semiconductor-field-effect transistor (MOSFET). If the switch is OFF, the load resistance is high, equal to RL1 = R1, and the steady-state load current is low, equal to IO1 = VO/RL1. If the switch is ON, the load resistance is low, equal to RL2 = R1R2/(R1 + R2), and the steady-state load current is high, equal to IO2 = VO/RL2. Therefore, when the load resistance is switched from RL1 to RL2 and vice versa, the load current iO experiences step changes in magnitude ΔIO superimposed on the dc load current IO, for example, from 0.1IOmax to 0.9IOmax. This causes the output voltage to change just after the step change in the load current, as shown in Figure 1.12(b). When the load current iO abruptly increases, the output voltage vO

initially decreases and then returns to a steady-state value and vice versa. In general, the response may be underdamped (or oscillatory), critically damped, or overdamped, but a nonoscillatory response is normally required.

Figure 1.13 Circuit for testing the load transient response with a switched load resistance from R1 to R1||R2 using a MOSFET. Many voltage regulators are operated with a constant load resistance RL (or a constant load current IO) for relatively long time intervals. In addition, these regulators have a negative feedback controller, which maintains a constant output voltage VO. Therefore, the dc output power PO = V2O/RL is also constant. Such operating conditions are called constant power load. If the output power PO and the efficiency η are constant, the input power PI = PO/η = VIII is also constant. The dc input voltage of a dc voltage regulator can be expressed by (1.32) Figure 1.14 shows a plot of the input voltage VI as a function of the dc input current II at a constant output power PO. If the input voltage VI is increased, the input current II = PI/VI decreases under constant power load conditions. Therefore, the slope of the II–VI characteristic is negative at any operating point Q. The dynamic input resistance (also called the ac or incremental input resistance) of the voltage regulator with a constant input power PI for slow changes of the input voltage and current at a given operating point Q (i.e., for low frequencies) is given by (1.33) Note that for a constant input power, the dynamic input resistance is just the negative of the static input resistance. The dynamic input resistance of a voltage regulator with a constant output power PO and a constant efficiency η is

(1.34) From (1.9), one obtains (1.35) Substitution of (1.35) into (1.34) produces (1.36) It can be seen that the dynamic input resistance of a dc voltage regulator with a constant power load is negative and directly proportional to the load resistance RL. The dynamic input resistance is a negative reflected load resistance.

Figure 1.14 Voltage–current characteristic of a constant power source.

1.7 Linear Voltage Regulators There are two basic topologies of linear voltage regulators: the series voltage regulator and the shunt voltage regulator. These topologies are shown in Figure 1.15. A band gap reference voltage source Vref is applied to the noninverting input of the op-amp. The input voltage of the

op-amp is the difference between the noninverting input voltage V+ and the inverting input voltage V− given by Vi(op − amp) = V+ − V−. Since the input voltage of an op-amp with negative feedback is almost zero, the voltage across the resistor R2 is controlled by the reference voltage source Vref . Thus, (1.37) Rearrangement of this equation gives the output voltage for both linear voltage regulators (1.38) The range of the output current of linear voltage regulators is from 0 to a maximum value IOmax, usually determined by a current limiting circuit.

Figure 1.15 Basic circuits of linear voltage regulators. (a) Series voltage regulator. (b) Shunt voltage regulator.

1.7.1 Series Voltage Regulator The series voltage regulator is shown in Figure 1.15(a). It employs a pass transistor whose collector-to-emitter voltage VCE is controlled to compensate for varying the input voltage. Referring to Figure 1.15(a), (1.39) Since VO is constant, (1.40) Thus, a change in the input voltage will result in the same change in the voltage drop across the pass transistor. The pass transistor behaves like a variable resistor Rv. The series voltage regulator can be represented as a voltage divider composed of the variable resistor Rv and the

load resistor RL. When the output voltage VO decreases, the variable resistance also decreases, causing the output voltage across the load resistance to increase, and vice versa. The voltage drop across Rv can be expressed as (1.41) At a fixed load current IO, a change in the input voltage is given by (1.42) When the input voltage is changed by ΔVI, the resistance is changed by ΔRv = ΔVI/IO. The efficiency of a series voltage regulator can be derived by observing that IO ≈ II (1.43) It can be seen that the efficiency of a series voltage regulator is equal to the dc voltage transfer function MVDC. If the input voltage VI is much higher than the output voltage VO, the efficiency is very low. For example, if VI = 20 V and VO = 5 V, then η = 5/20 = 25%. This is a very low efficiency. However, if VI = 8 V and VO = 5 V, then η = 5/8 = 62.5%. The power loss in the pass transistor is expressed by (1.44) Thus, the power loss increases with increasing load current IO and the voltage drop across the pass transistor ΔV = VI − VO. The series voltage regulator will work properly as long as VI does not drop too low, which causes the op-amp to saturate. The op-amp must be in the linear region to function properly as a control circuit. The minimum voltage difference between the unregulated input voltage and the regulated output voltage VDO = VImin − VO at which the circuit ceases to regulate against further reduction in the input voltage is called the drop-out voltage. For most series voltage regulators, this voltage is about 2 V, but in some voltage regulators VDO can be as low as 0.1 V. Voltage regulators with a low drop-out (LDO) voltage are called LDO regulators. In these regulators, a pnp or an NMOS transistor is used as a pass component, as shown in Figure 1.16. The series voltage regulator is quiet because its transistor always operates in the pinch-off region as a dependent current source and does not generate a lot of noise like that in switchingmode power supplies. In addition, a series voltage regulator is simple to design and build.

Figure 1.16 Typical low drop-out (LDO) voltage regulator topology.

1.7.2 Shunt Voltage Regulator The shunt voltage regulator is shown in Figure 1.15(b). It employs a shunt transistor, in which the current is controlled to compensate for the change in the input voltage or the load current. The output voltage is held constant by varying the collector current IC of the shunt transistor. The shunt transistor acts like a variable resistor. When the output voltage VO decreases, the opamp output voltage also decreases, the shunt transistor conducts less heavily, and the variable resistance increases. Thus, less current is diverted from the load, causing an increase in the load current and the output voltage. Using Kirchhoff’s current law (KCL), (1.45) When the load current IO is changed at a fixed input voltage VI, the input current II = (VI − VO)/Rs is constant and therefore (1.46) Equation (1.45) can be rewritten as (1.47) When the input voltage changes at a fixed load current IO, (1.48)

from which (1.49) Thus, the output voltage VO is held constant by varying the voltage drop across the series resistor Rs, which in turn is controlled by varying the collector current IC of the shunt transistor. The shunt regulator is inherently short-circuit proof. The output current under short-circuit conditions is given by (1.50) The power loss in resistor Rs is (1.51) The power loss in the shunt transistor is (1.52) and the efficiency is defined as (1.53) Thus, the shunt voltage regulator is less efficient than the series voltage regulator due to the power loss in both series resistor Rs and shunt transistor. However, the line transient response of the shunt regulator is better than that of the series regulator. The shunt voltage regulator must be protected against input overvoltage conditions. The major characteristics of IC linear voltage regulators are as follows: 1. Simple circuit 2. Very small size and low weight 3. Cost effective 4. Low noise level 5. Wide bandwidth and fast step response to load and line changes 6. Low input and output voltages, usually below 40 V 7. Low output current, usually below 3 A 8. Low output power, usually below 25 W 9. Low efficiency (especially for VI VO), usually between 20% and 60%

10. Only step-down linear voltage regulators are possible 11. Only noninverting linear voltage regulators are possible 12. Large low-frequency (50 or 60 Hz) transformers are required in AC–DC power supplies with linear voltage regulators.

1.8 Topologies of PWM DC–DC Converters Switched-mode technology employs a wide variety of topologies. Figure 1.17 shows a family of single-ended PWM dc–dc converters, such as buck, boost, buck–boost, flyback, forward, Ćuk (boost–buck), SEPIC (single-ended primary input converter), and dual-SEPIC [7] (also called zeta or inverse-SEPIC) converters. The SEPIC converter is noninverting stepdown/step-up converter. Its voltage ratio is MVDC = VO/VI = D/(1 − D).

Figure 1.17 Single-ended PWM dc–;dc nonisolated and isolated converters. The flyback converter is a transformer version of the buck–boost converter, and the forward

converter is a transformer version of the buck converter. The flyback and dual-SEPIC converters are identical on the primary side of the transformer. Also, the Ćuk and SEPIC converters are identical on the primary side of the transformer. The flyback and SEPIC converters are identical on the secondary side of the transformer. Also, the Ćuk and dualSEPIC converters are identical on the secondary side of the transformer. Figure 1.18 depicts the multiple-switch PWM dc–dc converters: half-bridge, full-bridge, and push–pull converters. Switched-mode converters use duty-cycle control of a switching element to block the flow of energy from the input to the output and thus achieve voltage regulation. The advantages of these converters include significant reduction of a transformer and energy storage components. Since switched-mode converters can operate at high frequencies, a small transformer with a ferrite core can be used. The reduced size is very important in many applications, such as aerospace, computers, and wireless technologies. However, there is a penalty paid due to the increased noise, which is present at both input and output of the supply due to the switching action of semiconductor devices. In addition, the control circuit is much more complicated than that used in linear regulators.

Figure 1.18 Multiple-switch isolated PWM dc–dc converters. Power MOSFETs are often used as controllable switches. In 1979, International Rectifier patented the first commercially viable power MOSFET, called the HEXFET. Fast recovery diodes, ultrafast recovery [28], and hyperfast recovery pn junction diodes, or Schottky diodes are used in switching dc–dc power converters. In 1976 , Silicon General introduced the industry’s first PWM controller IC, the SG1524.

1.9 Relationships Among Current, Voltage, Energy, and Power The average value of current i(t) is given by (1.54) and the rms value of the current is

(1.55) Likewise, the average value of voltage v(t) is expressed by (1.56) and the rms value of the voltage is given by (1.57) The instantaneous power is (1.58) The energy dissipated in a component or delivered by a source over a time interval t1 is (1.59) For periodic waveforms in steady state, the average real power absorbed by a component or delivered by a source is the time average value of the instantaneous power over a period T of the operating frequency (1.60) For periodic waveforms in steady state, the average charge stored in a capacitor over one period is zero (1.61) This is called the principle of capacitor charge balance or capacitor ampere-second balance. Thus, the average current through a capacitor for steady-state operation is zero (1.62) For periodic waveforms in steady state, the average magnetic flux linkage of an inductor over one period is zero (1.63)

This is called the principle of inductor flux linkage balance or inductor volt-second balance. Hence, the average voltage across an inductor in steady state is zero (1.64) The instantaneous energy stored in a capacitor is (1.65) and in an inductor is (1.66)

1.10 Summary The main function of voltage regulators is the regulation of the dc output voltage against changes in the load current, the input voltage, and the temperature. Additional functions of voltage regulators are the dc isolation, ripple voltage reduction, and fast transient response to rapid changes in the load current and the input voltage. Voltage regulators can be categorized into linear voltage regulators, switching-mode dc–dc converters, and switched-capacitor voltage regulators. Linear voltage regulators have simple circuit, low power levels, low noise (EMI), low output ripple voltage, excellent load and line regulation, wide bandwidth and fast transient response to load and line changes, but have low efficiency and are only step-down regulators. There are series and shunt linear voltage regulators. In linear voltage regulators, transistors are operated as dependent current sources. In PWM dc–dc converters, transistors are operated as switches. Therefore, the voltage is low when the current is high, and the current is zero when the voltage is high, yielding low conduction loss and high efficiency. PWM converters are sources of EMI because of the hard switching action of transistors and diodes. Switching voltage regulators have high efficiency, high power density, and high power levels. They can be step-down or step-up converters and can have multiple-output voltages, but they have slow response to load and line changes, produce high level of EMI, and have high output ripple voltage. Flyback converters are used at power levels in the range 0–50 W. Forward converters are used in the range 50–500 W. Half-bridge converters are used in the range 100–1000 W.

Full-bridge converters are used for power level above 500 W. Power converters are sources of EMI/RFI noise. EMI noise can be conducted and radiated. The conducted noise is in the range from 9 kHz to 30 MHz. The radiated noise is in the range from 30 MHz to 1 GHz. EMI noise can be differential-mode noise and common-mode noise.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York, NY: Van Nostrand, 1981. 3. K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. 4. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984. 5. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 6. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 7. J. Jóźwik and M. K. Kazimierczuk, “Dual SEPIC PWM switching-mode dc/dc converter,” IEEE Transactions on Industrial Electronics, vol. IE-36, pp. 64–70, February 1989. 8. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 9. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. 10. M. K. Kazimierczuk and D. Czarkowski, Resonant Power Converters, 2nd Ed. New York: John Wiley & Sons, 2011. 11. D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. 12. A. M. Trzynadlowski, Introduction to Modern Power Electronics. New York: John Wiley & Sons, 1998. 13. P. T. Krein, Elements to Power Electronics. New York: Oxford University Press, 1998. 14. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd Ed. Norwall, MA: Kluwer Academic Publisher, 2001.

15. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 16. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. 17. W. Shepherd and L. Zhang, Power Converter Circuits. New York: Marcel Dekker, 2004. 18. S. Ang and A. Oliva, Power-Switching Converters, 2nd Ed. Boca Raton, FL: CRC/Taylor & Francis, 2004. 19. A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. 20. I. Batarseh, Power Electronics Circuits. New York: John Wiley & Sons, 2004. 21. M. H. Rashid, Editor, Power Electronics Handbook. New York: Academic Press, 2006. 22. M. H. Rashid and H. M. Rashid, SPICE for Power Electronics and Electric Power, 2nd Ed. Boca Raton, FL: CRC/Taylor & Francis, 2006. 23. C. P. Basso, Switch-Mode Power Supply. New York: McGraw-Hill, 2008. 24. M. K. Kazimierczuk, RF Power Amplifiers. Chichester, UK: John Wiley & Sons, 2014. 25. M. K. Kazimierczuk, High-Frequency Magnetic Components, 2nd Ed. Chichester, UK: John Wiley & Sons, 2014. 26. S. Buso and P. Mattavelli, Digital Control in Power Electronics. Morgan & Claypool Publishers, 2006. 27. S. Maniktala, Switching Power Supply Design and Optimization. New York: McGrawHill, 2005. 28. M. K. Kazimierczuk, “Reverse recovery power pn junction diodes,” International Journal of Circuits, Systems, and Computers, vol. 5, no. 4, pp. 747–755, December 1995.

Review Questions 1. List the main functions of dc–dc converters. 2. Give a classification of power supplies. 3. Define line regulation of voltage regulators. 4. Define load regulation of voltage regulators. 5. Define thermal regulation of voltage regulators. 6. Define the dc input resistance of voltage regulators.

7. Define the dynamic input resistance of voltage regulators. 8. Define the ripple rejection ratio of voltage regulators. 9. What is the line transient response of voltage regulators? 10. What is the load transient response of voltage regulators? 11. How are transistors operated in linear voltage regulators? 12. What are the basic topologies of linear voltage regulators? 13. Give the expression for the efficiency of the series voltage regulator. 14. What is the range of efficiency for linear voltage regulators? 15. What is the range of output power for linear voltage regulators? 16. Can you build a step-up linear voltage regulator? 17. What is the size and weight of a transformer in power supplies with linear voltage regulators? 18. What is the noise level in linear voltage regulators? 19. What are LDO voltage regulators? 20. How are transistors and diodes operated in switching-mode dc–dc power converters? 21. How is the dc isolation achieved in switching-mode power supplies? 22. Compare the efficiency of linear and PWM switching-mode voltage regulators.

Problems 1. A voltage regulator experiences a 100 mV change in the output voltage, when its input voltage changes by 10 V at IO = 0.2 A and TA = 25°C. The nominal output voltage is VOnom = 3.3 V. Determine the line regulation and the percentage line regulation. 2. A voltage regulator is rated for an output current IO = 0–50 mA. Under the no-load condition, the output voltage is 5 V. Under the full-load condition, the output voltage 4.99 V. Find load regulation, the percentage load regulation, the dc output resistance, and load/line regulation. 3. A series linear voltage regulator is operated under the following conditions: VI = 6–15 V, VO = 3.3V, and IO = 0–0.4 A. Find the minimum and maximum efficiency of the voltage regulator at full load. 4. A voltage regulator has RL = 10 Ω, VI = 10 V, VO = 5 V, and η = 90%. Find the dc input resistance. 5. A boost PWM converter operating in CCM is rated for an output current of 0.5–1 A. The

output voltage at minimum load current is 20 V and at full load current is 19.95 V. Find the load regulation in (mV/A), the percentage load regulation in (%), and the dc output resistance (Ω).

2 Buck PWM DC–DC Converter 2.1 Introduction This chapter studies the PWM buck switching-mode converter, often referred to as a “chopper” [1–30]. Analysis is given for both continuous conduction mode (CCM) and discontinuous conduction mode (DCM). Current and voltage waveforms for all the components of the converter are derived. The dc voltage function is derived for both the modes. Voltage and current stresses of the components are found. The boundary between CCM and DCM is determined. An expression for the output voltage ripple is derived. The power losses in all the components and the transistor gate-drive power are estimated. The overall efficiency of the converter is determined. Design examples are also given.

2.2 DC Analysis of PWM Buck Converter for CCM 2.2.1 Circuit Description In general, a basic PWM converter, such as buck, boost, and buck–boost converter, contains a single-pole, double-throw switch, which controls the energy flow from the source to the load. A circuit of the PWM buck dc–dc converter is depicted in Figure 2.1(a). It consists of four components: a power MOSFET used as a controllable switch S, a rectifying diode D1, an inductor L, a filter capacitor C. Resistor RL represents a dc load. Power MOSFETs are the most commonly used controllable switches in dc–dc converters because of their high speeds. In 1979, International Rectifier patented the first commercially viable power MOSFET, the HEXFET. Other power switches such as bipolar junction transistors (BJTs), isolated gate bipolar transistors (IGBTs), or MOS-controlled thyristors (MCTs) may also be used. The diode D1 is called a freewheeling diode, a flywheel diode, or a catch diode.

Figure 2.1 PWM buck converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. The transistor and the diode form a single-pole, double-throw switch, which controls the energy flow from the source to the load. The task for the capacitor and the inductor is energy storage and transfer. The switching network, composed of the transistor and the diode, “chops” the dc input voltage VI, and therefore the converter is often called a “chopper,” which produces a reduced average voltage. The switch S is controlled by a pulse-width modulator and is turned on and off at the switching frequency fs = 1/T. The duty cycle D is defined as (2.1) where ton is the time interval when the switch S is closed and toff is the time interval when the switch S is open. Since the duty cycle D of the drive voltage vGS is varied, so does the duty ratio of other waveforms. This permits the regulation of the dc output voltage against changes

in the dc input voltage VI and the load resistance RL (or the load current IO). The circuit L-CRL acts like a second-order low-pass filter whose corner frequency is . The output voltage VO of the buck converter is always lower than the input voltage VI. Therefore, it is a step-down converter. The buck converter “bucks” the voltage to a lower level. Because the gate of the MOSFET is not referenced to ground, it is difficult to drive the transistor. The converter requires a floating gate drive. With the input current of the converter being discontinuous, a smoothing LC filter may be required at the input. The buck converter can operate in a CCM or in a DCM, depending on the waveform of the inductor current. In CCM, the inductor current flows for the entire cycle, whereas in DCM, the inductor current flows only for a part of the cycle. In DCM, it falls to zero, remains at zero for some time interval, and then starts to increase. Operation at the boundary between CCM and DCM is called the critical mode (CRM). Let us consider the buck converter operation in the CCM. Figures 2.1(b) and (c) shows the equivalent circuits of the buck converter for CCM when the switch S is ON and the diode D1 is OFF, and when the switch is OFF and the diode is ON, respectively. The principle of the converter operation is explained by the idealized current and voltage waveforms depicted in Figure 2.2. At time t = 0, the switch is turned on by the driver. Consequently, the voltage across the diode is vD = −VI, causing the diode to be reverse biased. The voltage across the inductor L is vL = VI − VO and therefore the inductor current increases linearly with a slope of (VI − VO)/L. For CCM, iL(0) > 0. The inductor current iL flows through the switch, resulting in iS = iL when the switch is ON. During this time interval, the energy is transferred from the dc input voltage source VI to the inductor, capacitor, and the load. At time t = DT, the switch is turned off by the driver.

Figure 2.2 Idealized current and voltage waveforms in the PWM buck converter for CCM. The inductor has a nonzero current when the switch is turned off. Because the inductor current waveform is a continuous function of time, the inductor current continues to flow in the same direction after the switch turns off. Therefore, the inductor L acts as a current source, which forces the diode to turn on. The voltage across the switch is VI and the voltage across the inductor is − VO. Hence, the inductor current decreases linearly with a slope of − VO/L. During this time interval, the input source VI is disconnected from the circuit and does not deliver energy to the load and the LC circuit. The inductor L and capacitor C form an energy reservoir that maintains the load voltage and current when the switch is OFF. At time t = T, the switch is turned on again, the inductor current increases and hence energy increases. PWM converters are operated at hard switching because the switch voltage waveform is rectangular and the transistor is turned on at a high voltage. The power switch S and the diode D1 convert the dc input voltage VI into a square wave at the input of the L-C-RL circuit. In other words, the dc input voltage VI is chopped by the transistor–

diode switching network. The L-C-RL circuit acts as a second-order low-pass filter and converts the square wave into a low-ripple dc output voltage. Since the average voltage across the inductor L is zero for steady state, the average output voltage VO is equal to the average voltage of the square wave. The width of the square wave is equal to the on-time of the switch S and can be controlled by varying the duty cycle D of the MOSFET gate-drive voltage. Thus, the square wave is a pulse-width modulated (PWM) voltage waveform. The average value of the PWM voltage waveform is VO = DVI, which depends on the duty cycle D and is almost independent of the load for CCM operation. Theoretically, the duty cycle D may be varied from 0% to 100%. This means that the output VO ranges from 0 to VI. Thus, the buck circuit is a step-down converter. In practice, the dc input voltage VI varies over a specified range while the output voltage VO should be held at a fixed value. If the dc voltage VI is increased, the duty cycle D is reduced so that the product DVI being the average value of the PWM voltage remains constant. On the other hand, if the input voltage VI is reduced, the duty cycle D is increased so that the average value of the PWM signal is constant. Therefore, the amount of energy delivered from the input voltage source VI to the load can be controlled by varying the switch on-duty cycle D. If the output voltage VO and the load resistance RL (or the load current IO) are constant, the output power is also constant. When the input voltage VI increases, the switch on-time is reduced to transfer the same amount of energy. The practical range of D is usually from 5% to 95% due to resolution. The duty cycle D is controlled by a control circuit. The inductor current contains an ac component which is independent of the dc load current in CCM and a dc component which is equal to the dc load current IO. As the dc output current IO flows through the inductor L, only one-half of the B–H curve of the inductor ferrite core is exploited. Therefore, the inductor L should be designed such that the core will not saturate. To avoid core saturation, a core with an air gap and sufficiently large volume may be required.

2.2.2 Assumptions The analysis of the buck PWM converter of Figure 2.1(a) begins with the following assumptions: 1. The power MOSFET and the diode are ideal switches. 2. The transistor output capacitance, the diode capacitance, and the lead inductances are zero and thereby switching losses are neglected. 3. Passive components are linear, time invariant, and frequency independent. 4. The output impedance of the input voltage source VI is zero for both dc and ac components. 5. The converter operates in steady state. 6. The switching period T = 1/fs is much shorter than the time constants of reactive components.

7. The dc output voltage VO is constant, but the dc input voltage VI and the load resistance RL are variable.

2.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch S is ON and the diode D1 is OFF. An ideal equivalent circuit for this time interval is shown in Figure 2.1(b). When the switch is ON, the voltage across the diode vD is approximately equal to − VI, causing the diode to be reverse biased. The voltage across the switch vS and the diode current are zero. The voltage across the inductor L is given by (2.2) Hence, the current through the inductor L and the switch S is (2.3) where iL(0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes (2.4) and the peak-to-peak ripple current of the inductor L is (2.5) The diode voltage is (2.6) Thus, the peak value of the diode reverse voltage is (2.7) The average value of the inductor current is equal to the dc output current IO. Hence, the peak value of the switch current is (2.8) The instantaneous energy stored in the magnetic field in the inductor is

(2.9) The increase in the magnetic energy stored in the inductor L during the time interval 0 to DT is given by (2.10) The time interval 0 to DT is terminated when the switch is turned off by the gate driver.

2.2.4 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch S is OFF and the diode D1 is ON. Figure 2.1(c) shows an ideal equivalent circuit for this time interval. Since iL(DT) is nonzero at that instant, the switch turns off and the fact that the inductor current iL is a continuous function of time, the inductor acts as a current source and turns the diode on. The switch current iS and the diode voltage vD are zero and the voltage across the inductor L is (2.11) The current through the inductor L and the diode can be found as (2.12)

where iL(DT) is the initial condition of the inductor L at t = DT. The peak-to-peak ripple current of the inductor L is (2.13) Note that the peak-to-peak value of the inductor current ripple ΔiL is independent of the load current IO in CCM and depends only on the dc input voltage VI and thereby on the duty cycle D. For a fixed output voltage VO, the maximum value of the peak-to-peak inductor ripple current occurs at the maximum input voltage VImax, which corresponds to the minimum duty cycle Dmin. It is given by (2.14) The switch voltage vS and the peak switch voltage VSM are given by

The diode and switch peak currents are given by

(2.15) (2.16)

This time interval ends at t = T when the switch is turned on by the driver. The decrease in the magnetic energy stored in the inductor L during time interval DT < t ≤ T is given by (2.17) For steady-state operation, the increase in the magnetic energy ΔWL(in) is equal to the decrease in the magnetic energy ΔWL(out). The transient and steady-state waveforms in converters with commercial components can be obtained from computer simulations using SPICE model.

2.2.5 Device Stresses for CCM The maximum voltage and current stresses of the switch and the diode in CCM for steady-state operation are (2.18) and (2.19)

2.2.6 DC Voltage Transfer Function for CCM The voltage and current across a linear inductor are related by Faraday’s law in its differential form (2.20) For steady-state operation, the following boundary condition is satisfied (2.21) Rearranging (2.20), (2.22) and integrating both sides yields

(2.23) The integral form of Faraday’s law for an inductor under steady-state conditions is (2.24) The average value of the voltage across an inductor for steady state is zero. Thus, (2.25) This equation is also called a volt-second balance for an inductor, which means that “voltsecond” stored is equal to “volt-second” released. The inductor average voltage for PWM converters operating in CCM is (2.26) from which (2.27) This means that the area encircled by the positive part of the inductor voltage waveform A+ is equal to the area encircled by the negative part of the inductor voltage waveform A−, that is, (2.28) where (2.29) and (2.30) Referring to Figure 2.2, (2.31) which simplifies to the form

(2.32) For a lossless converter, VIII = VOIO. Hence, from (2.32), the dc voltage transfer function (or the voltage conversion ratio) of the lossless buck converter is given by (2.33) The range of MV DC is (2.34) Note that the output voltage VO is independent of the load resistance RL. It depends only on the dc input voltage VI and the duty cycle D. The sensitivity of the output voltage with respect to the duty cycle is (2.35) In most practical situations, VO = DVI is constant which means that if VI is increased, D should be decreased by a control circuit to keep VO constant, and vice versa. The dc current transfer function is given by (2.36) and its value decreases from ∞ to 1 as D is increased from 0 to 1. From (2.8), (2.15), and (2.33), the switch and the diode utilization in the buck converter is characterized by the output-power capability (2.37) As D is increased from 0 to 1, so does cp.

2.2.7 Boundary Between CCM and DCM Figure 2.3 depicts the inductor current waveform at the boundary between the CCM and the DCM, where iL(0) = 0. This waveform can be described by (2.38) resulting in the peak inductor current

(2.39) where VI = VO/MV DC = VO/D for a lossless buck converter. Hence, one obtains a dc load current at the boundary (2.40) and the load resistance at the boundary (2.41) Figures 2.4 and 2.5 show the normalized load current IOB/(VO/2fsL) = 1 − D and the load resistance RLB/(2fsL) = 1/(1 − D) at the boundary between CCM and DCM as functions of the duty cycle D, respectively. The plots can be obtained using MATLAB®, described in Appendix B.

Figure 2.3 Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax.

Figure 2.4 Normalized load current IOB/(VO/2fsL) at the boundary between CCM and DCM as a function of the duty cycle D for buck converter.

Figure 2.5 Normalized load resistance RLB/(2fsL) at the boundary between CCM and DCM as a function of the duty cycle D for buck converter. For the worst case, (2.42) Hence, the minimum inductance required to maintain the CCM operation for the duty cycle ranging from Dmin to Dmax is (2.43) As the switching frequency fs increases, the minimum inductance Lmin decreases. Therefore, high switching frequencies are desirable to reduce the size of the inductor. In some applications, the inductance L can be much higher than Lmin in order to reduce the ripple

current through the inductor and the filter capacitor. Therefore, it is easier to reduce the output voltage ripple, to avoid the core saturation, and to reduce the winding and core losses. In a real converter, the efficiency η < 1, and therefore MV DC = VO/VI = ηD. Since VI = VO/(ηD), (2.44)

(2.45)

(2.46)

and (2.47)

where Dmin = MV DCmin/η = VO/(ηVImax). A gapped ferrite core should be used to make the inductor because the inductor current contains a dc component, and therefore the core may saturate. The inductance is given by (2.48)

where N is the number of turns, Ac is the core cross-sectional area, lc is the magnetic path length (MPL), and lg is the air-gap length. If the dc output current IO and the dc input voltage VI are fixed, the peak-to-peak inductor current ΔiL = 2IO can be made very large while maintaining the converter operation in CCM. In this case, the ripple current of the inductor should be limited, for example, ΔiL/(2IO) ≤ 10%.

2.2.8 Capacitors Capacitors are classified according to dielectric material used between the conductors. The following types of capacitors are used in switching-mode power supplies: wet aluminum electrolytic capacitors wet tantalum electrolytic capacitors

solid electrolytic capacitors ceramic capacitors. Wet electrolytic capacitors can be built using aluminum or tantalum. They are made of two aluminum foils. A paper spacer soaked in wet electrolyte separates the two aluminum foils. One of the aluminum foils is coated with an insulating aluminum oxide layer, which forms the capacitor dielectric material. The aluminum foil coated in aluminum oxide is the anode of the capacitor. The liquid electrolyte and the second aluminum foil act as a cathode of the capacitor. The two aluminum foils with attached leads are rolled together with the electrolyte soaked paper in a cylindrical aluminum case to form a wet aluminum electrolyte capacitor. Wet electrolyte tantalum capacitors are formed in a similar manner as wet aluminum electrolyte capacitors except that the dielectric material is tantalum oxide. Solid electrolytic capacitors are constructed similarly to wet electrolytic capacitors except that a solid dielectric material is used in place of a wet dielectric material These capacitors have moderate capacitances and a higher ripple current rating. Electrolytic capacitors are the most commonly used in power electronics because of a high ratio of capacitance per unit volume and low cost. Ceramic capacitors use ceramic dielectric to separate two conductive plates. The ceramic dielectric material is composed of titanium dioxide (Class I) or barium titanate (Class II). Ceramic capacitors can be disc capacitors or multilayer ceramic (MLC) capacitors. Disc capacitors have low capacitance per unit volume. Conductive material is placed on the ceramic dielectric material forming interlace fingers. Ceramic capacitors have lower capacitances than electrolytic capacitors. The capacitances of ceramic capacitors are usually below 1 μF. Ceramic capacitors have very low values of ESR. This property reduces voltage ripple and power loss. Important parameters of capacitors are the capacitance C, the equivalent series resistance (ESR) rC, and the series equivalent inductance (ESL) Ls, the self-resonant frequncy fr, and the breakdown voltage VBD. The capacitance is (2.49) where A is the area of each conductor, d is the thickness of the dielectric, εr is the relative permittivity of the dielectric, and ε0 = 8.85 × 10− 12 F/m is the permittivity of free space. The ESR is the sum of the resistances of leads, the resistances of the contacts, and the resistance of the plate conductors. The ESL is the inductance of the leads. The self-resonant frequency is (2.50) The dissipation factor of a capacitor is

(2.51) The quality factor of a capacitor at a frequency f = ω/(2π) is (2.52) For the buck converter, the ESL is connected in series with the filter inductance L and does not present a problem. However, the ESL can have a negative effect in boost converter. Capacitors are rated for the breakdown voltage and the maximum rms value of the ripple current. The maximum rms ripple current is the limit of ac current and is dependent of the temperature and frequency of the current conducted by a capacitor. The ripple current flowing through the ESR causes power loss PC = rCI2ac(rms), which generates heat within the capacitor. Electrolytic tantalum capacitors have the highest values of ESR, and ceramic capacitors have the lowest ESR. The performance of electrolytic capacitors is highly affected by operating conditions, such as frequency, ac current, dc voltage, and temperature. The ESR is frequency dependent. As the frequency increases, the ESR first decreases, usually reaches a minimum value at the selfresonant frequency, and then increases. For electrolytic capacitors, the ESR decreases as the dc voltage increases. It also decreases as the peak-to-peak ac ripple voltage increases. The ESR is often measured by manufacturers at the capacitor self-resonant frequency. The ESR of capacitors controls the peak-to-peak value of the output ripple voltage. Also, the higher the ESR of the capacitor, the greater the heat generated due to the continuous flow of current through the ESR. This reduces the converter efficiency and life expectancy of the power supply. During aging process, the electrolytic liquid inside the capacitor gradually evaporates, causing an increase in ESR. When a voltage is applied between the conductors and across the dielectric of a capacitor, an electric field is induced in the dielectric. The electric energy is stored in the electric field. The dielectric has a maximum value of the electric field strength EBD = VBD/d, resulting in a capacitor breakdown voltage VBD.

2.2.9 Ripple Voltage in Buck Converter for CCM A model of the filter capacitor consists of capacitance C, equivalent series resistance rC, and equivalent series inductance LESL The impedance of the capacitor model is (2.53) where the self-resonant frequency of the filter capacitor is (2.54)

and the quality factor of the capacitor at its self-resonant frequency is (2.55) Figures 2.6 and 2.7 show plots of the magnitude |ZC| and phase ϕZC of the capacitor for C = 1 μF, rC = 50 mΩ, and LESL = 15 nH. The filter capacitor impedance is capacitive below the self-resonant frequency and inductive above the self-resonant frequency.

Figure 2.6 Magnitude of the capacitor impedance.

Figure 2.7 Phase of the capacitor impedance. The input voltage of the second-order low-pass LCR output filter is rectangular with a maximum value VI and a duty cycle D. This voltage can be expanded into a Fourier series (2.56)

The components of this series are transmitted through the output filter to the load. It is difficult to determine the peak-to-peak output voltage ripple Vr using the Fourier series of the output voltage. Therefore, a different approach will be taken for deriving an expression for Vr. A simpler derivation [24] is given below. A model of the output part of the buck converter for frequencies lower than the capacitor self-resonant frequency (i.e., f ≤ fr) is shown in Figure 2.8. The filter capacitor in this figure is modeled by its capacitance C and its equivalent series resistance (ESR) designated by rC. Figure 2.9 depicts current and voltage waveforms in the

converter output circuit. The dc component of the inductor current flows through the load resistor RL while the ac component is divided between the capacitor C and the load resistor RL. In practice, the filter capacitor is designed so that the impedance of the capacitive branch is much less than the load resistance RL. Consequently, the load ripple current is very small and can be neglected. Thus, the current through the capacitor is approximately equal to the ac component of the inductor current, that is, iC ≈ iL − IO.

Figure 2.8 Model of the output circuit of the buck converter for frequencies lower than the self-resonant frequency of the filter capacitor.

Figure 2.9 Waveforms illustrating the ripple voltage in the PWM buck converter. For the interval 0 < t ≤ DT, when the switch is ON and the diode is OFF, the capacitor current is given by (2.57) resulting in the ac component of the voltage across the ESR (2.58) The voltage across the filter capacitance vC consists of the dc voltage VC and the ac voltage vc, that is, vC = VC + vc. Only the ac component vc may contribute to the output ripple voltage. The ac component of the voltage across the filter capacitance is found as

(2.59) For steady state, vc(DT) = vc(0). The waveform of the voltage across capacitance C is a parabolic function. The ac component of the output voltage is the sum of voltage across the filter capacitor ESR rC and the filter capacitance C (2.60) Let us consider the minimum value of the voltage vo. The derivative of the voltage vo with respect to time is (2.61) Setting this derivative to zero, the time at which the minimum value of vo occurs is given by (2.62) The minimum value of vo is equal to the minimum value of vrc if tmin = 0. This occurs at a minimum capacitance, which is given by (2.63) Consider the time interval DT < t ≤ T when the switch S is OFF and the diode D1 is ON. Referring to Figure 2.9, the current through the capacitor is (2.64) resulting in the voltage across the ESR (2.65) and the voltage across the capacitor (2.66)

Adding (2.65) and (2.66) yields the ac component of the output voltage

(2.67) The derivative of vo with respect to time is (2.68) Setting the derivative to zero, the time at which the maximum value of vo occurs is expressed by (2.69) The maximum value of vo is equal to the maximum value of vrc if tmax = DT. This occurs at a minimum capacitance, which is given by (2.70) The peak-to-peak ripple voltage is independent of the voltage across the filter capacitance C and is determined only by the ripple voltage across the ESR if (2.71) Hence, (2.72) and (2.73) For the worst case, Dmin = 0 or Dmax = 1. Thus, the above condition is satisfied at any value of D if (2.74) If condition (2.71) is satisfied, the peak-to-peak ripple voltage of the buck converter is (2.75) For steady-state operation, the average value of the ac component of the capacitor voltage vc is

zero, that is, (2.76) resulting in (2.77) Waveforms of vrc, vc, and vo are depicted in Figure 2.10 for three values of the filter capacitance C. In Figure 2.10(a), the peak-to-peak value of vo is higher than the peak-to-peak value of vrc because C < Cmin. Figures 2.10(b) and (c) shows the waveforms for C = Cmin and C > Cmin, respectively. For both these cases, the peak-to-peak voltages of vo and vrc are the same. For aluminum electrolytic capacitors, τ = rCC ≈ 65 × 10− 6 s.

Figure 2.10 Waveforms of vc, vrc, and vo at three values of the filter capacitor for CCM. (a) C < Cmin. (b) C = Cmin. (c) C > Cmin. If condition (2.71) is not satisfied, both the voltage drop across the filter capacitor C and the voltage drop across the ESR contribute to the ripple output voltage. The ac component of the voltage across the filter capacitor increases when the ac component of the charge stored in capacitor is positive. The positive charge is equal to the area under the capacitor current waveform for iC > 0. The capacitor current is positive during time interval T/2. The maximum increase of the charge stored in the filter capacitor in every cycle T is (2.78) Hence, using (2.39), the voltage ripple across the capacitance C is

(2.79) where is the corner frequency of the output filter. The minimum filter capacitance required to reduce its peak-to-peak ripple voltage below a specified level VCpp is (2.80) Thus, Cmin is inversely proportional to f2s. Therefore, high switching frequencies are desirable to reduce the size of the filter capacitor. Using (2.39), the peak-to-peak voltage ripple across the ESR is (2.81) Hence, the conservative estimation of the total voltage ripple is (2.82)

2.2.10 Switching Losses with Linear MOSFET Output Capacitance Let us assume that the MOSFET output capacitance Co is linear. First, we shall consider the transistor turn-off transition. During this time interval, the transistor is OFF, the drain-tosource voltage vDS increases from nearly zero to VI, and the transistor output capacitance is charged. Because dQ = CodvDS, the charge transferred from the input voltage source VI to the transistor output capacitance Co during the turn-off transition is (2.83) yielding the energy transferred from the input voltage source VI to the converter during the turnoff transition as (2.84) An alternative method for deriving an expression for the energy delivered from a dc source VI to a series R-Co circuit after turning on VI is as follows. The input current is (2.85)

where τ = RCo is the time constant. Hence, (2.86) Using dWs = QdvDS/2, the energy stored in the transistor output capacitance Co at the end of the transistor turn-off transition, when vDS = VI, is given by (2.87) Thus, the energy lost in the parasitic resistance of the capacitor charging path is the turn-off switching energy loss described by (2.88) which results in the turn-off switching power loss in the resistance of the charging path (2.89) After turn-off, the transistor remains in the off-state for some time interval and the charge Ws is stored in the output capacitance Co. The efficiency of charging a linear capacitance from a dc voltage source is 50%. Now consider the transistor turn-on transition. When the transistor is turned on, its output capacitance Co is shorted out through the transistor on-resistance rDS, the charge stored in Co decreases, and the drain-to-source voltage decreases from VI to nearly zero. As a result, all the energy stored in the transistor output capacitance is dissipated as heat in the transistor onresistance rDS. Therefore, the turn-on switching energy loss is (2.90) resulting in the turn-on switching power loss in the MOSFET (2.91) The turn-on loss is independent of the transistor on-resistance rDS as long as the transistor output capacitance is fully discharged before the turn-off transition begins. The total switching energy loss in every cycle of the switching frequency during the process of first charging and then discharging of the output capacitance is given by (2.92)

and the total switching loss in the converter is (2.93) For a linear capacitance, one-half of the switching power is lost in the MOSFET and the other half is lost in the resistance of the charging path of the transistor output capacitance, that is, Pturn-on = Pturn-off = Psw/2. The behavior of a diode is different from that of a transistor because a diode cannot discharge its parallel capacitance through its forward resistance. This is because a diode does not turn on until its voltage drops to the threshold voltage. However, the junction diodes suffer from the reverse recovery at turn-off.

2.2.11 Switching Losses with Nonlinear MOSFET Output Capacitance The MOSFET drain-to-source capacitance Cds is a nonlinear capacitance of the pn stepjunction body-diode, which depends on the drain-to-source voltage vDS. This capacitance is given by (2.94)

where CJ0 is the zero-bias junction capacitance and VB is the built-in potential barrier and it is in the range 0.55–0.9 V. From (2.94), (2.95) Manufacturers of power MOSFETs usually specify the capacitances Crss = Cgd, Ciss = Cgs + Cgd, and Coss = Cds + Cgd at f = 1 MHz. The capacitances Crss and Coss are measured at VDS = 25 V and VGS = 0 V. Hence, Cds25 = Coss − Crss. The output capacitance at vDS = VI is (2.96)

Since dQ = CdsdvDS, the charge transferred from the dc input voltage source VI to the drain-tosource junction capacitance Cds during the turn-off transition is given by

(2.97)

Hence, (2.98) The energy transferred from the input dc voltage source VI to the converter during the turn-off transition is given by (2.99) Because dWs = QdvDS/2, the energy stored in the drain-to-source capacitance Cds at vDS is (2.100)

Hence, one obtains the energy stored in Cds at VI (2.101) Therefore, the energy lost in the resistance of the charging path of the MOSFET output capacitance is given by (2.102) Hence, the switching power loss dissipated in the resistance r of the path of charging the transistor output capacitance is (2.103) The transistor equivalent linear output capacitance that causes the same switching power loss in the charging path resistance r during the turn-off transition as the linear one is derived as (2.104) producing (2.105)

During the turn-on transition, all the energy stored in the transistor output capacitance is lost in the MOSFET on-resistance rDS (2.106) Thus, the MOSFET turn-on switching loss is (2.107) The transistor equivalent linear output capacitance that causes the same switching power loss in the MOSFET on-resistance during the turn-on transition as the linear one can be obtained as (2.108) resulting in (2.109) The total switching energy loss in each cycle of the switching frequency is (2.110) and the total switching loss in the converter is (2.111) The transistor equivalent linear output capacitance Ceq(sw) that produces the same amount of the switching loss as the nonlinear one at a given VI can be derived as (2.112) yielding (2.113) The turn-off switching power loss is twice as high as the turn-on switching power loss for the MOSFET with a nonlinear output capacitance. The ratio of these losses is (2.114)

Example 2.1 A power MOSFET IRF510 with VB = 0.774158 V, Crss = 25 pF, and Coss = 100 pF is operated in the buck PWM converter at VI = 100 V and fs = 100 kHz. Find: Cds25, CJ0, Cds(VI), Q(VI), Wsw, Psw, Ceq(sw), Wturn-on, Psw(FET), Ceq(FET), Wturn-off , Pturn-off , and Ceq(r). Solution: The transistor drain-to-source capacitance at VDS = 25 V is (2.115) The zero-bias drain-to-source capacitance is (2.116) The drain-to-source capacitance at VI = 100 V is (2.117)

The charge transferred from the dc input source to Cds during the turn-off transition is (2.118) The switching energy is (2.119) The switching loss is (2.120) The equivalent linear switching capacitance is (2.121) The energy lost during the turn-on transition is equal to the energy stored in Cds at the end of the turn-off transition when vDS = VI. This energy is (2.122) The switching power loss in the MOSFET is (2.123)

The equivalent linear turn-on capacitance is (2.124) The energy lost in the resistance of the charging path of Cds during the turn-off transition is (2.125) The turn-off switching loss is (2.126) The turn-off equivalent linear capacitance is (2.127)

2.2.12 Power Losses and Efficiency of Buck Converter for CCM An equivalent circuit of the buck converter with parasitic resistances is shown in Figure 2.11. In this figure, rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The slope of the ID–VDS curves in the ohmic region is equal to the inverse of the MOSFET on-resistance 1/rDS. The MOSFET on-resistance rDS increases with temperature because the mobility of electrons μn ≈ K1/T2.5 decreases with temperature T in the range from 100 to 400°C, where K1 is a constant. Typically, rDS doubles as the temperature rises by 100°C.

Figure 2.11 Equivalent circuit of the buck converter with parasitic resistances and the diode offset voltage. The large-signal model of a diode consists of a battery VF in series with a forward resistance RF. The voltage across the conducting diode is VD = VF + RFID. If a line is drawn along the linear high-current portion of the ID–VD curve (or log(ID)–VD) extending to the VD-axis, the intercept on the VD-axis is VF and the slope is 1/RF. The threshold voltage VF is typically 0.7 V for silicon (Si) pn junction diodes, and VF = 2.8 V for silicon carbide (SiC) pn junction diodes. The threshold voltage VF = 0.3–0.4 V for silicon Schottky diodes and VF = 2 V for silicon carbide Schottky diodes. The threshold voltage VF of silicon diodes decreases with temperature at the rate of 2 mV/°C. The series resistance RF of pn junction diodes decreases with temperature, while resistance RF of Schottky diodes increases with temperature. The conduction losses will be evaluated assuming that the inductor current iL is ripple free and is equal to the dc output current IO. Hence, the switch current can be approximated by (2.128) which results in its rms value (2.129) and the MOSFET conduction loss (2.130)

The transistor conduction loss PrDS is proportional to the duty cycle D at a fixed load current IO. At D = 0, the switch is OFF for the entire cycle and therefore the conduction loss is zero. At D = 1, the switch is ON for the entire cycle, resulting in a maximum conduction loss. Assuming that Dmax = VO/VImin as for the lossless converter, the maximum MOSFET conduction power is (2.131) Assuming that the transistor output capacitance Co is linear, the switching loss is expressed by (2.132) The maximum switching loss is (2.133) Excluding the MOSFET gate-drive power, the total power dissipation in the MOSFET is (2.134) Similarly, the diode current can be approximated by (2.135) yielding its rms value (2.136) and the power loss in RF (2.137) The average value of the diode current is (2.138) which gives the power loss associated with the voltage VF

(2.139) Thus, the overall diode conduction loss is (2.140) The diode conduction loss PD decreases, when the duty cycle D increases at a fixed load current IO. At D = 0, the diode is ON for the entire cycle, resulting in a maximum conduction loss. At D = 1, the diode is OFF for the entire cycle and therefore the conduction loss is zero. The maximum diode conduction loss is (2.141) Typically, the power loss in the inductor core can be ignored and only the copper loss in the inductor winding should be considered. The inductor current can be approximated by (2.142) leading to its rms value (2.143) and the inductor conduction loss (2.144) The maximum power loss in the inductor is (2.145) Using (2.13), (2.57), and (2.64), the rms current through the filter capacitor is found to be (2.146)

and the power loss in the filter capacitor (2.147) The maximum power loss in the capacitor is

(2.148)

The overall power loss is given by (2.149)

Thus, the converter efficiency is (2.150)

For D = 0, the switch is OFF and the diode is ON, yielding the converter efficiency (2.151) For D = 1, the switch is ON and the diode is OFF, resulting in the converter efficiency (2.152) If the inductor peak-to-peak current ripple ΔiL = VO(1 − D)/(fsL) = D(1 − D)VI/(fsL) is taken into account, the rms value of the switch current is given by (2.153) where ISmin = IO − ΔiL/2 and ISmax = IO + ΔiL/2. Similarly, the rms value of the diode current is (2.154) where IDmin = IO − ΔiL/2 and IDmax = IO + ΔiL/2. The rms value of the inductor current is (2.155)

For example, for ΔiL/IO = 0.1, ILrms = 1.0017IO, and for ΔiL/IO = 0.5, ILrms = 1.0408IO. Assuming that the resistances rL, rDS, and RF are constant and frequency independent, the conduction power loss in the MOSFET is given by (2.156) The conduction power loss in the diode forward resistance is (2.157) Assuming that the inductor resistance rL is independent of frequency, the power loss in the inductor winding is given by (2.158) The overall power loss is (2.159)

Hence, the converter efficiency is (2.160)

For example, for ΔiL/IO = 0.1, (2.161) For ΔiL/IO = 0.2, (2.162) In the buck converter, part of the dc input power is transferred directly to the output and is

converted to ac power, which is then converted back to dc power. It can be shown that the amount of power which is converted to ac power is (2.163) and the amount of the dc power that directly flows to the output is (2.164)

2.2.13 DC Voltage Transfer Function of Lossy Converter for CCM The dc component of the input current is (2.165) leading to the dc current transfer function of the buck converter (2.166) This equation holds true for both lossless and lossy converters. The converter efficiency can be expressed as (2.167) from which the voltage transfer function of the lossy buck converter is (2.168)

For D = 1, MV DC = η < 1. From (2.168), the on-duty cycle is (2.169) The duty cycle D at a given dc voltage transfer function is higher for the lossy converter than that of a lossless converter. This is because the switch S must be closed for a longer period of time for the lossy converter to transfer enough energy to supply both the required output energy and the converter losses. Substitution of (2.169) into (2.150) gives the converter efficiency

(2.170) where (2.171)

and (2.172)

2.2.14 MOSFET Gate-Drive Power When the transistor is driven by a square-wave voltage source, the MOSFET gate-drive power is associated with charging the transistor input capacitance, when the gate-to-source voltage increases, and discharging this capacitance when the gate-to-source voltage decreases. Unfortunately, the input capacitance of power MOSFETs is highly nonlinear and therefore it is difficult to determine the gate-drive power, using the transistor input capacitance. In data sheets, a total gate charge Qg stored in the gate-to-source capacitance and the gate-to-drain capacitance is given at a specified gate-to-source voltage VGS (usually, VGS = 10 V) and a specified drain-to-source voltage VDS (usually, VDS = 0.8 of the maximum rating). Using a square-wave voltage source to drive the MOSFET gate, the energy transferred from the gatedrive source to the transistor is (2.173) This energy is lost during one cycle T of the switching frequency fs = 1/T for charging and discharging the MOSFET input capacitance. Thus, the MOSFET gate-drive power is (2.174) The gate-drive power PG is proportional to the switching frequency fs. The power gain is defined by (2.175) The power-added efficiency (PAE) incorporates the gate-drive power PG by subtracting it from the output power PO and is defined by

(2.176) If the power gain kp is high, ηPAE ≈ η. If the power gain kp < 1, ηPAE < 0. The total efficiency is defined by (2.177) The average efficiency is defined by (2.178) In order to determine this efficiency, the probability-density functions of the average input and output powers are required.

2.2.15 Gate Driver Both the gate and the source of the MOSFET in the buck converter are connected to two hot points. Therefore, it is difficult to drive the transistor. The driver is usually an integrated circuit, which requires a power supply and one end terminal of the power supply should be connected to ground. One option is to connect the driver between the gate and ground. In this case, KVL is (2.179) yielding (2.180) When the MOSFET is ON, vDS ≈ 0, resulting in (2.181) If the gate-to-source voltage vGS in the ON state is 5–10 V, the on-gate voltage is (2.182) For example, if VI = 5 V, vG(ON) = 5 + 5 = 10 V to vG(ON) = 5 + 10 = 15 V. However, if VI = 100 V, vG(ON) = 100 + 5 = 105 V to 100 + 10 = 110 V. When the MOSFET is OFF, the diode is ON, vD ≈ 0, and vG(OFF) − vGS(OFF) = 0. If vG(OFF) = VI, vGS(OFF) = vG(OFF) = VI = 100 V. This high voltage will break the SiO2 dielectric in the gate.

2.2.16 Design of Buck Converter for CCM

Design a PWM buck converter operating in CCM to meet the following specifications: VI = 28 ± 4 V, VO = 12 V, IOmin = 1 A, IOmax = 10 A, fs = 100 kHz, and Vr/VO ≤ 1%. Solution: The minimum, nominal, and maximum values of the input voltage VImin = 24 V, VInom = 28 V, and VImax = 32 V. The maximum and minimum values of the dc output power are (2.183) and (2.184) The minimum and maximum values of the load resistance are (2.185) and (2.186) The minimum, nominal, and maximum values of the dc voltage transfer function are (2.187) (2.188) and (2.189) Assume the converter efficiency η = 85%. The minimum, nominal, and maximum values of the duty cycle are (2.190) (2.191) and (2.192)

Assuming the switching frequency fs = 100 kHz, the minimum inductance that is required to maintain the converter in CCM is (2.193)

Let us use a standard value of the inductane L = 50 μH/rL = 0.05 Ω. The maximum inductor ripple current is (2.194) The ripple voltage is (2.195) If the filter capacitance is large enough, Vr = rCmaxΔiLmax and the maximum ESR of the filter capacitor is (2.196) Let rC = 50 mΩ. The minimum value of the filter capacitance at which the ripple voltage is determined by the ripple voltage across the ESR is (2.197) Pick C = 100 μF/25 V/50 mΩ. The corner frequency of the output low-pass filter is (2.198) Thus, fs/fo = 100/2.25 = 44.4. The bandwidth of the converter is approximately equal to the corner frequency. The voltage and current stresses of power MOSFET and diode are (2.199) and (2.200)

An International Rectifier IRF150 power MOSFET is selected, which has VDSS = 100 V, ISM = 40 A, rDS = 55 mΩ, Co = 100 pF, and Qg = 63 nC. Also, an MBR1060 Schottky barrier diode is chosen, which has IDM = 20 A, VDM = 60 V, VF = 0.4 V, and RF = 25 mΩ. The power losses and the efficiency will be calculated at the minimum load resistance RLmin = 1.2 Ω and the maximum dc input voltage VImax = 32 V, which correspond to the minimum duty cycle Dmin = 0.441. The conduction power loss in the MOSFET is (2.201) and the switching loss is (2.202) Hence, the total power loss in the MOSFET is (2.203) However, the maximum conduction power loss in the MOSFET occurs at the minimum dc input voltage VImin = 24 V, RLmin = 1.2 Ω, and Dmax = 0.588. Thus, PrDSmax = DmaxrDSI2Omax = 0.588 × 0.055 × 102 = 3.234 W. The diode loss due to VF is (2.204) the diode loss due to RF is (2.205) and the total diode conduction loss is (2.206) The power loss in the inductor dc ESR rL = 50 mΩ is (2.207) The power loss in the capacitor ESR is (2.208) The total power loss is (2.209)

and the efficiency of the converter at full load is (2.210) If the assumed efficiency is much different than the calculated one in (2.210), a next iteration step is needed with a new assumed converter efficiency. Note that the maximum conduction power loss in the MOSFET occurs at VImin = 24 V and RLmin = 1.2 Ω and is given by (2.211) Assuming that the peak-to-peak gate-to-source voltage is VGSpp = 16 V, the MOSFET gatedrive power is (2.212) The efficiency η of the designed buck converter was computed from (2.170) through (2.172) over the entire range of the specified operating conditions. Next, the duty cycle D was computed from (2.169), using the calculated efficiency η. The plots of η and D as functions of VI, IO, and RL are shown in Figures 2.12 through 2.17 for rDS = 55 mΩ, RF = 25 mΩ, VF = 0.4 V, rL = 50 mΩ, rC = 50 mΩ, L = 40 μH, Co = 100 pF, and fs = 100 kHz. The converter efficiency η decreases as the load current IO increases (or the load resistance RL decreases). The minimum efficiency ηmin occurs at the maximum load current IOmax and the maximum dc input voltage VImax. The duty cycle D decreases when VI increases, and D increases when IO increases (or RL decreases).

Figure 2.12 Efficiency η of the designed buck converter as a function of dc input voltage VI for CCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω.

Figure 2.13 Duty cycle D of the designed buck converter as a function of dc input voltage VI for CCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω.

Figure 2.14 Efficiency η of the designed buck converter as a function of load current IO for CCM at VI = 24 V, 28 V, and 32 V.

Figure 2.15 Duty cycle D of the designed buck converter as a function of load current IO for CCM at VI = 24 V, 28 V, and 32 V.

Figure 2.16 Efficiency η of the designed buck converter as a function of load resistance RL for CCM at VI = 24 V, 28 V, and 32 V.

Figure 2.17 Duty cycle D of the designed buck converter as a function of load resistance RL for CCM at VI = 24 V, 28 V, and 32 V.

2.3 DC Analysis of PWM Buck Converter for DCM Equivalent circuits for the PWM buck converter operating in the DCM are depicted in Figure 2.18. Idealized current and voltage waveforms are shown in Figure 2.19. At time t = 0 when the switch is turned on, the inductor current is zero. For the time interval 0 < t ≤ DT, the switch is ON and the diode is OFF as depicted in Figure 2.18(b). The voltage across the diode is − VI. The voltage across the inductor is VI − VO, which causes the inductor current to increase linearly from zero. At time t = DT, the switch is turned off and the inductor current is diverted from the switch to the freewheeling diode. The equivalent circuit is shown in Figure 2.18(c) for time interval DT < t ≤ (D + D1)T. The voltage across the switch is VI. The voltage across the inductor is − VO, causing the inductor current to decrease linearly. This current flows through the diode. At time t = (D + D1)T, the diode current reaches zero and the diode begins

to turn off. Since the diode cannot conduct negative current (neglecting the reverse-recovery current), the inductor current remains zero until the switch is turned on at time t = T. Figure 2.18(d) shows the equivalent circuit for time interval (D + D1)T < t ≤ T. The voltage across the inductor is zero because its current is constant and equals zero. At time t = T, the switch is turned on and the inductor current increases from zero.

Figure 2.18 PWM buck converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF.

Figure 2.19 Idealized current and voltage waveforms in the PWM buck converter for DCM.

2.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is ON and the diode is OFF. The equivalent circuit is shown in Figure 2.18(b). The switch voltage vS and the diode current iD are zero. The voltage across the inductor L is (2.213) Hence, the current through the inductor and switch is (2.214) Thus, the peak current through the switch and inductor is

(2.215) The voltage across the diode is (2.216) The end of this time interval occurs when the switch is turned off by the driver.

2.3.2 Time Interval: DT < t ≤ (D + D1)T The equivalent circuit for this time interval is shown in Figure 2.18(c). The switch is OFF and the diode is ON. Hence, iS = 0 and vD = 0. The voltage across the inductor L is (2.217) and the inductor and diode currents are obtained using (2.215) (2.218)

These currents can also be derived as (2.219)

Hence, the diode and inductor peak currents are found as (2.220) or (2.221) The peak voltage across the switch is (2.222) This time interval ends when the diode current reaches zero.

2.3.3 Time Interval: (D + D1)T < t ≤ T

During this time interval, both the switch and the diode are OFF. The equivalent circuit is shown in Figure 2.18(d). The inductor current iL, the inductor voltage vL, the switch current iS, and the diode current iD are zero. The voltage across the switch is (2.223) and the voltage across the diode is (2.224) This time interval ends when the switch is turned on by the driver.

2.3.4 Device Stresses for DCM Using (2.7) and (2.15), one obtains the voltage stress of the switch and the diode in DCM for steady-state operation (2.225) From (2.215), the current stress of the switch and the diode in DCM for steady-state operation is (2.226)

2.3.5 DC Voltage Transfer Function for DCM Referring to Figure 2.19 and using the volt-second balance principle, A+ = A−. Hence, (2.227) which leads to (2.228) From (2.215) and (2.228), the peak-to-peak value of the inductor current is (2.229) The dc output current is equal to the average value of the inductor current (2.230) Substitution of (2.228) into (2.230) yields

(2.231) which can be rearranged to the form (2.232) Thus, the duty cycle D increases with increasing IO when VO and MV DC (or VI) are held constant. The inductance required to obtain a desired dc voltage transfer function at given values of D, RL, and fs is (2.233) At the boundary between CCM and DCM, (2.234) as in CCM. Substitution of this into (2.232) yields the duty cycle DB at the boundary (2.235) As the normalized load current IO/(VO/2fsL) is increased from 0 to 1, the boundary duty cycle DB decreases from 1 to 0. At D close to 1, the converter operates in CCM practically at any load. At D close to zero, there is a large load range in which the converter operates in DCM. Figures 2.20 and 2.21 show plots of D versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of MV DC for both CCM and DCM for the lossless buck converter, respectively.

Figure 2.20 Duty cycle D as a function of the normalized load current IO/(VO/2fsL) at various values of MV DC for the lossless buck converter.

Figure 2.21 Duty cycle D as a function of the normalized load resistance RL/(2fsL) at various values of MV DC for the lossless buck converter. Rearranging (2.232), one obtains (2.236) Solving this equation for MV DC gives (2.237)

The dc voltage transfer function depends on the load resistance RL for DCM. Figures 2.22 and 2.23 display MV DC versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of D for both CCM and DCM for the lossless buck

converter, respectively.

Figure 2.22 DC voltage transfer function MV DC as a function of the normalized load current IO/(VO/2fsL) at fixed values of D for the lossless buck converter.

Figure 2.23 DC voltage transfer function MV DC as a function of the normalized load resistance RL/(2fsL) at fixed values of D for the lossless buck converter. Using (2.228) and (2.237), D1 can be expressed in terms of D, RL, fs, and L as (2.238) It can be seen that D1 depends on D, RL, L, and fs.

2.3.6 Maximum Inductance for DCM Figure 2.24 shows the waveforms of the inductor current at the boundary between DCM and CCM for VI = VImin and VI = VImax. Using (2.39), the minimum value of the inductor peak current at the boundary between DCM and CCM is

Figure 2.24 Waveforms of the inductor current at the boundary between DCM and CCM for VI = VImin and VI = VImax. (2.239) Therefore, the dc output current at the boundary can be expressed as (2.240) which yields (2.241) where DBmax is the maximum duty cycle at the boundary between the CCM and DCM modes for the lossy buck converter and is given by (2.242) The dwell-duty cycle is (2.243)

Hence, the maximum inductance for a given dwell-duty cycle is

(2.244) For example, for RLmin = 1.2 Ω, MV DCmax = 0.5, fs = 100 kHz, η = 0.9, and Dw = 0.05, we get Lmax = 2.4368 μH. The filter capacitor can be designed using the same approach as that for CCM. The maximum ripple voltage occurs at full power, for which the inductor waveform is close to that of the boundary between the DCM and CCM.

2.3.7 Power Losses and Efficiency of Buck Converter for DCM Substitution of (2.228) into (2.229) yields the inductor, switch, and diode peak current (2.245) Using this expression, one obtains the rms value of the switch current (2.246)

and the conduction loss in the MOSFET (2.247) The switching loss is (2.248) The total power loss in the MOSFET is (2.249)

Using (2.238) and (2.245), one arrives at the rms value of the diode current (2.250)

which gives the diode conduction loss due to RF

(2.251) Using (2.218), (2.230), (2.238), and (2.245), one obtains the average diode current (2.252) resulting in the diode conduction loss due to VF (2.253) Hence, the overall diode conduction loss is (2.254)

Using (2.238) and (2.245), one obtains the rms value of the inductor current (2.255)

which leads to the power loss in the inductor ESR (2.256) Neglecting the power loss in the ESR of the filter capacitor, the total converter power loss is given by (2.257)

The efficiency of the buck converter in DCM is defined as (2.258) which gives

(2.259)

The dc input current of the converter is described by (2.260) yielding the dc input power (2.261)

The dc output power is (2.262) Hence, the efficiency of the buck converter operating in DCM is given by (2.263) The duty cycle (2.264) and the dc voltage transfer function of the lossy buck converter for DCM (2.265)

At the boundary between DCM and CCM, D = D1 = 0.5, and ΔiL/IO = 2. Hence, the power loss in the inductor winding is given by (2.266)

2.3.8 Design of Buck Converter for DCM

Design a PWM buck converter to meet the following specifications: POmin = 0, POmax = 120 W, VO = 12 V, VImin = 24 V, VInom = 28 V, VImax = 32 V, fs = 100 kHz, and Vr/VO ≤ 6%. The maximum load current is (2.267) and the minimum load resistance is (2.268) The dc voltage transfer functions are (2.269) (2.270) and (2.271) Let us assume η = 0.9. The maximum duty cycle at the boundary between CCM and DCM at full load RLmin = 1.2 Ω occurs at VImin = 24 V (2.272) resulting in the maximum inductance required for DCM operation (2.273) Pick L = 2.4 μH. The maximum duty cycle at RLmin = 1.2 Ω, VImin = 24 V, and L = 2.4 μH is (2.274)

(2.275) and

(2.276) The nominal duty cycle at RLmin = 1.2 Ω and VInom = 28 V is (2.277)

(2.278) and (2.279) The minimum duty cycle at RLmin = 1.2 Ω and VImax = 32 V is (2.280)

(2.281) and (2.282) The maximum peak switch, diode, and inductor current occurs at RLmin = 1.2 Ω and VImax = 32 V and is found as (2.283) The maximum switch and diode voltage stress is (2.284) Let us choose an IRF150 power MOSFET with VDSS = 100 V, ISM = 40 A, rDS = 0.055 Ω, Co = 100 pF, and Qg = 63 nC. In addition, we select an MBR4040 Schottky diode with VDM = 40 V, IDM = 40 A, VF = 0.4 V, and RF = 25 mΩ. The ripple voltage is (2.285) The minimum filter capacitor ESR is

(2.286) Pick rC = 25 mΩ. The minimum filter capacitance is (2.287) Pick C = 220 μF/25 V/25 mΩ. Let us estimate the power losses in various components at RLmin = 1.2 Ω and VImin = 24 V. The conduction power loss in the MOSFET is (2.288)

The switching loss is (2.289) Hence, the total power loss in the MOSFET is (2.290) The diode conduction loss due to RF is (2.291)

The power loss in the diode due to VF is (2.292) Hence, the overall diode conduction loss is (2.293) Assuming rL = 0.05 Ω, the power loss in the inductor ESR is (2.294)

The total power loss is

(2.295) resulting in the converter efficiency (2.296) Assuming the gate-to-source peak-to-peak voltage VGSm = 8 V, the MOSFET gate-drive power is (2.297) The converter efficiency η can be computed from (2.258) and the duty cycle D from (2.264). Figures 2.25 and 2.26 depict plots of the converter efficiency η and the duty cycle D as functions of the DC input voltage VI at fixed load resistances RL, respectively, at rDS = 55 mΩ, RF = 25 mΩ, VF = 0.4 V, rL = 50 mΩ, rC = 25 mΩ, L = 2.4 μH, Co = 100 pF, and fs = 100 kHz. It can be seen that the efficiency η decreases as the input voltage VI increases. Figures 2.27 through 2.30 show plots of the converter efficiency η and duty cycle D versus the load current IO and the load resistance RL for DCM at fixed values of the dc input voltage VI. The efficiency decreases with respect to IO and increases with respect to RL.

Figure 2.25 Efficiency η as a function of the DC input voltage VI for the buck converter given in the design example for DCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω.

Figure 2.26 Duty cycle D as a function of the dc input voltage VI for the buck converter given in the design example for DCM at RL = 1.2 Ω, 2.4 Ω, and 12 Ω.

Figure 2.27 Efficiency η of the buck converter as a function of the load current IO for DCM at VI = 24 V, 28 V, and 32 V.

Figure 2.28 Duty cycle D of the buck converter as a function of the load current IO for DCM at VI = 24 V, 28 V, and 32 V.

Figure 2.29 Efficiency η of the buck converter as a function of load resistance RL for DCM at VI = 24 V, 28 V, and 32 V.

Figure 2.30 Duty cycle D of the buck converter as a function of load resistance RL for DCM at VI = 24 V, 28 V, and 32 V.

2.4 Buck Converter with Input Filter The disadvantage of the buck converter topology shown in Figure 2.1(a) is discontinuous and pulsating input current waveform because the switch is connected in series with the input voltage source. The input current flows when the switch is closed and is abruptly interrupted when the switch is opened. In order to obtain a continuous input current, a second-order L1-C1 low-pass filter can be added at the input of the converter, as depicted in Figure 2.31.

Figure 2.31 Buck converter with an input L1-C1 low-pass filter.

2.5 Buck Converter with Synchronous Rectifier A buck converter topology with a synchronous rectifier is shown in Figure 2.32(a). This circuit is obtained by replacing the diode with an n-channel MOSFET. In general, diodes have an offset voltage VF and may be comparable to the output voltage in low-voltage applications. In contrast, MOSFETs do not have an offset voltage. If the on-resistance of a MOSFET is low, the forward voltage drop across the MOSFET is very low, reducing the conduction loss and yielding high efficiency. Some low-breakdown voltage MOSFETs have the on-resistance rDS as low as 6 mΩ. In addition, operation in DCM can be avoided because the channel of the transistor can conduct current in both directions. The synchronous buck converter operates in CCM from no load to full load.

Figure 2.32 Buck converter with a synchronous rectifier. (a) With two n-channel MOSFETs. (b) CMOS buck converter. The two MOSFETs are driven in a complimentary manner. The low side n-channel MOSFET replaces a Schottky diode and operates in the third quadrant because the current normally flows from source to drain. When both the transistors are n-channel MOSFETs, it is difficult to drive the upper MOSFET because both the gate and the source are connected to “hot” points. One solution is to use a transformer with one primary winding and two secondary windings. The primary winding is connected to a driver, for example, an integrated circuit (IC) driver. One transformer output is noninverting and the other transformer output is inverting. The synchronous buck converter suffers from cross-conduction (or shoot-through) effect, resulting in high current spikes in both transistors. This produces high losses and reduces the efficiency. A nonoverlapping driver can produce a dead time and reduce the cross-conduction loss. During the dead time periods, the inductor current flows through the lower MOSFET body diode. This body diode has a very slow reverse recovery characteristic that can adversely affect the converter efficiency. An external Schottky diode can be connected in parallel with the low-side MOSFET to shunt the body diode and to prevent it from affecting the converter

performance. The added Schottky diode can have a much lower current rating than the diode in the conventional nonsynchronous buck converter because it only conducts during the small dead time when both MOSFETs are OFF. If the upper MOSFET is a PMOS and the lower MOSFET is an NMOS, then the circuit is similar to a digital CMOS inverter, as shown in Figure 2.32(b). In this case, both transistors can be driven by the same gate-to-source voltage. The peak-to-peak gate-to-source voltage should be equal or close to the dc input voltage VI. Therefore, the CMOS buck synchronous converter is a good topology for applications with a low dc voltage VI. The whole converter can be integrated, except for the filter capacitor C. The PMOS transistor has larger capacitances because it must have larger area due to lower mobility of holes. At a high voltage VI, the peak-to-peak gate-to-source voltage is high and may break the MOSFET gate. The same gate-to-drive voltage may cause cross-conduction of both transistors, generating high spikes and drastically reducing the converter efficiency. A dead time will reduce the current spikes, but this requires two nonoverlapping gate-to-source voltages to drive the MOSFETs. The synchronous buck converter is especially attractive in power supplies with a very low output voltage (e.g., VO = 3.3 V or VO = 1 V) and/or a wide load range, including operation from no-load to full-load. Its main advantage is higher efficiency than that of the conventional buck converter. The synchronous buck converter may be used as a bidirectional converter. Figure 2.33 shows a synchronous buck converter with a transformer driver. If both MOSFETs are n-channel devices, then the upper output of the transformer should be noninverting and the other should be inverting. If the upper transistor is a PMOS and the bottom transistor is an NMOS, then both transformer outputs should be noninverting or inverting.

Figure 2.33 Synchronous buck converter with a transformer driver. Figure 2.34 shows a synchronous buck converter with a voltage mirror driver. The voltage mirror driver acts as a voltage shifter for the ac voltage waveform so that the gate-to-source voltage of the n-channel MOSFET is the same as the source-to-gate voltage of the p-channel MOSFET. Unlike in the CMOS synchronous buck converter, the peak-to-peak voltage of the gate-to-source voltage can be lower than the dc input voltage VI. Therefore, this driver is good for applications with high values of VI.

Figure 2.34 Synchronous buck converter with a voltage mirror driver. The minimum inductance for the synchronous converter is limited only by the inductor current. For CCM, the maximum inductor current ripple is (2.298) Hence, the minimum inductance is given by (2.299) The choice between synchronous rectification and Schottky diode rectification is as follows. Synchronous rectifiers should be used for VO ≤ 2 V, fs ≤ 300 kHz, and 10 A ≤ IO ≤ 100 A. Schottky diodes should be used for VO > 5 V and fs > 1 MHz, IO < 10 A, and IO > 100 A. The efficiency of the buck converter with synchronous rectifier is (2.300)

where ΔiL = VO(1 − D)/(fsL) = D(1 − D)VI/(fsL) and ΔiL/IO = RL(1 − D)/(fsL) = RL(1 − VO/VI)/fsL = (1 − VO/VI)VO/(fsLIO). If rDS1 = rDS2, the converter efficiency becomes

(2.301)

Figures 2.35, 2.36, and 2.37 show the efficiency η of the buck converter with synchronous rectifier as functions of the load current IO, the load resistance RL, and the output power PO, respectively, at VO = 12 V, VI = 28 V, rDS = 55 mΩ, rL = rC = 50 mΩ, D = 0.506, MV DC = 0.43, fs = 100 kHz, and Co = 100 pF. The inductor current ripple is ΔiL = VO(1 − D)/(fsL) = 12 × (1 − 0.506)/(105 × 40 × 10− 6) = 1.482 A. It can be observed that the converter efficiency η decreases for low values of load current IO ≤ 0.2 A, which corresponds to large values of load resistance RL ≥ 60 Ω and low values of output power PO ≤ 24 mW.

Figure 2.35 Efficiency η of the buck converter with synchronous rectifier as a function of the load current IO at VI = 28 V and VO = 12 V.

Figure 2.36 Efficiency η of the buck converter with synchronous rectifier as a function of the load resistance RL at VI = 28 V and VO = 12 V.

Figure 2.37 Efficiency η of the buck converter with synchronous rectifier as a function of the output power PO at VI = 28 V and VO = 12 V. The dc voltage transfer function is (2.302)

Figures 2.38 and 2.39 show the efficiency η of the buck converter with synchronous rectifier and the voltage transfer function MV DC as functions of the duty cycle D at the load resistance RL = 1.2 Ω, respectively, at VI = 28 V, rDS = 55 mΩ, rL = rC = 50 mΩ, fs = 100 kHz, and Co = 100 pF.

Figure 2.38 Efficiency η of the buck converter with synchronous rectifier as a function of duty cycle D at fixed RL = 1.2 Ω and VI = 28 V.

Figure 2.39 DC voltage transfer function MV DC of the buck converter with synchronous rectifier as a function of duty cycle D at fixed RL = 1.2 Ω and VI = 28 V.

2.6 Buck Converter with Positive Common Rail Figure 2.40 shows the derivation of a buck converter topology, in which the positive potential of both the input and output voltages is common and can be connected to the ground. The classical buck converter with a negative common rail is depicted in Figure 2.40(a). Figure 2.40(b) shows the converter circuit with the MOSFET and the inductor moved to the common rail of Figure 2.40(a). The resulting positive bus is now the common rail. Figure 2.40(c) shows the circuit of Figure 2.40(b) flipped so that the positive rail is at the bottom.

Figure 2.40 Derivation of the buck converter topology with the positive common rail. (a) Classical buck converter with a negative common rail. (b) Buck converter with the MOSFET and the inductor moved to the negative branch, resulting in the positive common rail. (c) Buck converter with a positive common rail. Gate-Drive with Respect to Ground. One of the disadvantages of the buck converter shown in Figure 2.1(a) is the difficulty of driving the transistor because neither the gate nor the source is connected to the ground. Figure 2.41 shows a topology of the buck converter, in which the gate is referenced to ground, but the output of the converter is not grounded. This topology may be useful in some preliminary laboratory tests of the converter because a simple driver may be used. It can also be used in applications, where the load is not connected to ground, for example, a bulb or an LED with variable brightness.

Figure 2.41 Topology of the buck converter with the gate referenced to ground and floating output voltage. Figure 2.42 shows a topology of the buck converter, in which both the source of the MOSFET and the output of the converter are connected to ground, but it requires a floating power supply.

Figure 2.42 Topology of the buck converter in which both the MOSFET source and the converter output are grounded, but this topology requires a floating power supply.

2.7 Quadratic Buck Converter In order to increase the range of the conversion ratio, two buck converters can be cascaded. However, this circuit requires twice as many components as a single-stage buck converter, which increases the size, weight, and cost. A quadratic buck converter [25–28] is shown in Figure 2.43. The dc voltage transfer function of this converter is (2.303) The quadratic buck converter contains only one transistor.

Figure 2.43 Quadratic buck converter.

2.8 Tapped-Inductor Buck Converters

The simplest method of extending the range of the dc voltage transfer function MV DC is by replacing the inductor L with a tapped inductor in the basic dc–dc converters. The turns ratio n of the tapped inductor is present in MV DC. It permits to adjust the duty cycle value to achieve high efficiency. Very low and very high values of the duty cycle can be avoided. Also, the utilization of the switching devices cp and passive devices can be improved. Tapped-inductor buck converters are shown in Figure 2.44. These circuits are high step-down converters. The tapped inductor acts as a transformer and its magnetizing inductance acts as an output filter inductor. A magnetic core with an air gap can be used to build the tapped inductor. The tapped inductor may store magnetic energy.

Figure 2.44 Tapped-inductor buck converters. (a) Tapped-inductor common-diode buck converter. (b) Tapped-inductor common-switch buck converter. (c) Watkins–Johnson (common-source) converter.

2.8.1 Tapped-Inductor Common-Diode Buck Converter

Consider the common-diode (CD) tapped-inductor buck converter shown in Figure 2.44(a). The voltage transfer function of the tapped inductor is (2.304) When the MOSFET is ON and the diode is OFF, (2.305) producing the voltage across the Ns winding (2.306) When the MOSFET is OFF and the diode is ON, (2.307) Using the volt-second balance for the Ns winding, we obtain the dc voltage transfer function for the common-diode converter operating in CCM (2.308) The dc voltage transfer function MV DC versus D for CCM is illustrated in Figure 2.45. The current and voltage stresses are

Figure 2.45 DC voltage transfer function of common-diode tapped-inductor buck converter for CCM. (2.309)

(2.310)

(2.311) The magnetizing inductance on the terminals of winding Ns is (2.312)

where L = Lp + Ls is the total winding inductance. The circuit has several advantages, such as high voltage conversion ratio, low switch current stress, and low diode voltage stress. The main disadvantage of the tapped-inductor buck converter is the effect of the leakage inductance of winding Np. When the upper transistor is turned off, the leakage inductance forms a resonant circuit with the drain-to-source capacitance of that transistor, causing ringing. This increases the transistor peak voltage and switching loss. A higher voltage transistor is required, which will have a higher on-resistance, resulting in a higher conduction loss. MOSFET on-resistance rapidly increases with rated breakdown voltage. An active-clamp technique may be used to reduce the switch peak voltage.

2.8.2 Tapped-Inductor Common-Transistor Buck Converter Consider the tapped-inductor common-transistor (CT) buck converter shown in Figure 2.44(b). When the MOSFET is ON and the diode is OFF, (2.313) When the MOSFET is OFF and the diode is ON, (2.314) resulting in (2.315) Applying the volt-second balance, we arrive at the dc voltage transfer function for the common-switch converter operating in CCM (2.316) Figure 2.46 shows plots of MV DC as function of D for CCM.

Figure 2.46 DC voltage transfer function of tapped-inductor common-switch buck converter for CCM.

2.8.3 Watkins–Johnson Converter Now, we will analyze the Watkins–Johnson (WJ) converter, which is a tapped-inductor common-source (CS) converter. The converter was named after its inventors, Watkins–Johnson Company. It has been used to power traveling wave tubes that exhibit a negative input resistance and are used in satellite communications. The circuit has two poles and a single LHP zero. When the MOSFET is ON and the diode is OFF, (2.317) yielding (2.318) When the MOSFET is OFF and the diode is ON,

(2.319) resulting in (2.320) Applying the volt-second balance, (2.321) we get the dc voltage transfer function of the Watkins–Johnson converter for CCM (2.322) This function is illustrated in Figure 2.47. A multiple-output Watkins–Johnson converter can be built, for example, VO1 = 3.3 V and VO2 = 14 V [23].

Figure 2.47 DC voltage transfer function of Watkins–Johnson (common-source) tappedinductor buck converter for CCM.

2.9 Multiphase Buck Converter So far, we have studied a single-phase buck converter. This circuit requires a relatively large filter capacitor to reduce the output voltage ripple. Microprocessors are supplied with a very low voltage and a very high current, for example, VO = 1.1 V and IO = 100 A. In these applications, there is a stringent requirement on the output voltage tolerance. The output voltage must remain within the required range under dynamic load variations. This imposes restrictions on the values of the filter inductance and the filter capacitance. A very wide bandwidth is required in AM modulators used in RF transmitters. Multiphase buck converter has a smaller filter capacitor and therefore a wider bandwidth. In a polyphase or multiphase buck converter, two or more single-phase converters are operated in parallel and feed the same filter capacitor and load resistance, resulting in ripple cancellation. A two-phase buck converter is shown in Figure 2.48. Usually, synchronous

rectifiers are used as diodes. Current and voltage waveforms are shown in Figure 2.49 for the two-phase buck converter. In the two-phase buck converter, the drive signals vGS1 and vGS2 are shifted by 180°. When the individual phases of the converter are switched complimentarily, the output voltage ripple reduces considerably due to the ripple cancellation. In a two-phase buck converter, iL1 + iL2 is constant at D = 0.5, yielding a zero ac component. Therefore, the ac component of the current through the filter capacitor is also zero, resulting in zero ripple voltage. Partial ripple cancellation occurs at D ≠ 0.5.

Figure 2.48 Two-phase buck converter.

Figure 2.49 Waveforms in two-phase buck converter. If n individual phases are operated in parallel, the frequency of the ripple in the output voltage is n times the switching frequency of each single-phase converter, that is, fr = nfs. The ripple cancellation occurs at D = 1/n. Due to the reduced magnitude and increased frequency of the output voltage ripple, the required filter capacitance is reduced significantly. This improves the transient response of the power supply. Figure 2.50 shows a two-phase buck converter, with two large capacitors C1 and C2 at the input. The voltage stresses of the switches in this converter are reduced. The dc voltage transfer function is

Figure 2.50 Two-phase buck converter with two input capacitors. (2.323)

2.10 Switched-Inductor Buck Converter Figure 2.51 shows a circuit of a swithed-inductor buck converter. The dc voltage transfer function of this converter for CCM is given by

Figure 2.51 Switched-inductor buck converter. (2.324) Figure 2.52 shows a plot of a dc voltage transfer function MV DC as a function of duty cycle D.

Figure 2.52 DC voltage transfer function of switched-inductor buck converter MV DC as a function of the duty cycle D.

2.11 Layout The layout of the converter components is very important from EMI and power loss point of view. The dc current in each loop distributes to minimize the dc voltage drop around the loop, thus minimizing the dc conduction loss. The ac currents distribute to minimize energy stored in magnetic field for each current harmonic. Thus, the ac current flows through the path of the lowest inductance.

2.12 Summary The PWM buck converter is a step-down converter (VO < VI). The buck converter is a transformerless converter. It does not provide dc isolation.

It can operate in two modes: CCM or DCM. The dc voltage transfer function of the buck converter is MV DC = VO/VI = D for CCM if the losses are neglected. It is independent of the load resistance RL (or the load current IO) and depends only on the switch on-duty cycle D. Therefore, the output voltage VO = DVI is independent of the load resistance RL and depends only on the dc input voltage VI and the duty cycle D. The converter has conduction losses and switching losses. The duty cycle D of the lossy converter is greater than that of the lossless converter at the same dc voltage transfer function. The peak-to-peak value of the inductor ripple current ΔiL is independent of the dc load current for CCM. The peak-to-peak value of the current through the filter capacitor C is relatively low and is equal to the peak-to-peak inductor ripple current ΔiL. If the capacitance of the filter capacitor is sufficiently high, the output ripple voltage is determined only by the ESR of the filter capacitor and is independent of the capacitance of the filter capacitor. In order to reduce the output ripple voltage, it is necessary to chose a filter capacitor with a low ESR. The minimum value of the inductor is determined by the boundary between CCM and DCM, ripple voltage, or ac losses in the inductor and the filter capacitor. A disadvantage of the buck converter is that the input current is pulsating. However, an LC filter can be placed at the converter input to obtain a nonpulsating input current waveform. The corner frequency of the output filter resistance.

is independent of the load

It is relatively difficult to drive the transistor because neither the source nor the gate is referenced to ground. Therefore, a transformer or an optical coupler is required in the driver circuit. For CCM, the maximum conduction loss in the transistor occurs at the maximum load current IOmax and at the minimum input voltage VImin (i.e., at Dmax). For CCM, the maximum conduction loss in the diode occurs at the maximum load current IOmax and at the maximum input voltage VImax (i.e., at Dmin). The dc voltage transfer function MV DC is independent of the inductance L for CCM, whereas MV DC depends on L for DCM. The minimum efficiency occurs at the full load IOmax (or RLmin) and at VImin for the buck converter operated in both CCM and DCM.

The peak currents, rms currents, and conduction losses in the switch, diode, and filter capacitor are higher in DCM than those in CCM at the same values of the dc input and output currents and output power. The device current stresses in DCM are higher than those in CCM by a factor of two or more. The ESR of the inductor in DCM is usually lower than that in CCM because the inductance is lower. A filter capacitor with a very low ESR is required for the buck converter to achieve a low ripple voltage. The efficiency of the converter in CCM is higher than that in DCM at the same dc input and output currents and the same switching frequency. Only one-half of the B–H curve of the inductor core is utilized in the buck converter because the dc current flows through the inductor L.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. 3. K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. 4. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984. 5. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 6. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 7. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 8. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. 9. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 10. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. 11. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 12. B. M. Bird, K. G. King, and D. A. G. Pedder, An Introduction to Power Electronics. New

York, NY: John Wiley & Sons, 1993. 13. D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. 14. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 15. I. Batarseh, Power Electronic Circuits. New York, NY: John Wiley & Sons, 2004. 16. A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. 17. A. Reatti, “Steady-state analysis including parasitic components and switching losses of buck and boost dc-dc converter,” International Journal of Electronics, vol. 77, no. 5, pp. 679–702, November 1994. 18. M. K. Kazimierczuk, “Reverse recovery of power pn junction diodes,” International Journal of Circuits, Systems, and Computers, vol. 5, no. 4, pp. 747–755, December 1995. 19. D. A. Grant and Y. Darraman, “Watkins-Johnson converter completes tapped inductor converter matrix,” Electronic Letters, vol. 39, no. 3, pp. 271–272, February 6, 2003. 20. T. H. Kim, J. H. Park, and B. H. Cho, “Small-signal modeling of the tapped-inductor converter under variable frequency control,” IEEE Power Electronics Specialists Conference, 2004, pp. 1648–1652. 21. K. Yao, M. Ye, M. Xu, and F. C. Lee, “Tapped-inductor buck converter for high-step-down dc-dc conversion,” IEEE Transactions on Power Electronics, vol. 20, no. 4, pp. 775–780, July 2005. 22. B. Axelord, Y. Berbovich, and A. Ioinovici, “Switched-capacitor/switched-inductor structure for getting transformerless hybrid dc-dc PWM converters,” IEEE Transactions on Circuits and Systems, vol. 55, no. 2, pp. 687–696, March 2008. 23. Y. Darroman and A. Ferré, “42-V/3-V Watkins-Johnson converter for automotive use,” IEEE Transactions on Power Electronics, vol. 21, no. 3, pp. 592–602, May 2006. 24. D. Czarkowski and M. K. Kazimierczuk, “Static- and dynamic-circuit models of PWM buck-derived converters,” IEE Proceedings Part G Devices Circuits and Systems, vol. 139, no. 6, pp. 669–679, December 1992. 25. D. Maksimović and S. Ćuk, “Switching converters with wide dc conversion range,” IEEE Transactions on Power Electronics, vol. 6, no. 1, pp. 151–157, January 1991. 26. A. Ayachit and M. K. Kazimierczuk, “Steady-state analysis of PWM quadratic buck converter in CCM,” IEEE Midwest Symposium on Circuits and Systems, Columbus, OH, August 3–7, 2013, pp. 49–52.

27. A. Ayachit and M. K. Kazimierczuk, “Power losses and efficiency analysis of PWM quadratic buck converter in CCM,” IEEE Midwest Symposium on Circuits and Systems, College Station, TX, August 4–8, 2014. 28. A. Ayachit and M. K. Kazimierczuk, “Open-loop transfer functions of PWM quadratic buck converter in CCM,” IEEE Industrial Electronics Society, Dallas, TX, November 2014, pp. 1643–1649. 29. L. Balogh, “Design and application guide for high speed MOSFET gate drive circuits.” Texas Instrument Publication. 30. P.-J. Liu, W.-S. Shan, J.-N. Tai, H.-S. Chen, J.-H. Chen, Y.-J. E. Chen, “A high-efficiency CMOS dc-dc converter with 9-μs transient recovery time,” IEEE Transactions on Circuits and Systems-I: Regular Papers, vol. 59, no. 3, pp. 575–583, March 2012. pp. 687–696, March 2008.

Review Questions 1. Define the converter operation in the CCM and the DCM. 2. Does the buck converter have a transformer version? 3. Is the input current of the basic buck converter pulsating? 4. How can the buck circuit be modified to obtain a nonpulsating input current? 5. Is the transistor driven with respect to ground in the buck converter? 6. How is the dc voltage transfer function MV DC related to the duty cycle D for the lossless buck converter operated in CCM? 7. Is the duty cycle D of the lossy buck converter lower or greater than that of the lossless converter at a given value of MV DC for CCM? 8. Does the dc voltage transfer function of the buck converter depend on the load resistance? 9. What determines the ripple voltage in the buck converter in CCM? 10. Compare the voltage and current stresses for the transistor and the diode in the buck converter for CCM and DCM. 11. Is the corner frequency of the output filter dependent on the load resistance in the buck converter? 12. Is the efficiency high at heavy or light loads for the buck converter operated in CCM? 13. Are both halves of the B–H curve of the inductor core utilized in the buck converter?

Problems

1. Derive an expression for the dc voltage transfer function of the lossless buck converter operating in CCM using the diode voltage waveform. 2. A buck converter has VI = 22–32 V, VO = 14 V, IO = 0.2–2 A, and fs = 40 kHz. Find the minimum inductance L required to maintain the converter operation in the continuous conduction mode. 3. For the converter given in Problem 2.2, find the voltage and current stresses of the transistor and diode. 4. A buck PWM converter has VI = 10–14 V, VO = 5 V, IO = 0.2–1 A, fs = 200 kHz, L = 100 μH, C = 100 μF, and rC = 20 mΩ. Find the ripple voltage Vr and (Vr/VO) × 100%. Also, calculate the ripple voltage across the filter capacitance and the corner frequency of the output filter. 5. For the converter given in Problem 2.4, the filter capacitance has been reduced to 47 μF. Find the ripple voltage. 6. A PWM converter operates in CCM at VI = 10 V and VO = 5 V. Find the duty cycle D if (a) the converter efficiency η = 100% and (b) the converter efficiency η = 80%. 7. A buck converter operating in CCM has a MOSFET whose rDS = 0.025 Ω. The load current is IO = 10 A. Determine the MOSFET conduction loss at D = 0.1 and 0.9. 8. A buck converter operating in CCM has a diode whose RF = 0.025 Ω and VF = 0.3 V. The load current is IO = 10 A. Determine the diode conduction loss at D = 0.1 and 0.9. 9. A power MOSFET has VB = 0.75 V, Crss = 30 pF, and Coss = 130 pF at VDS = 25 V. It is used in a buck PWM converter with VI = 400 V and fs = 1 MHz. Find CJ0, Cds(VI), Q(VI), Psw, Pturn-off and Psw(FET). 10. A buck converter has VI = 22–32 V, VO = 14 V, IO = 0–2 A, and fs = 40 kHz. Find the maximum inductance L required to maintain the converter operation in the discontinuous conduction mode. Assume η = 90%. 11. Design a buck PWM converter to meet the following specifications: VI = 12 V± 4 V, VO = 5 V, IO = 1–10 A, Vr/VO ≤ 1%, fs = 100 kHz, rL(dc) = 50 mΩ, rDS = 10 mΩ, Co = 200 pF, VF = 0.3 V, and RF = 20 mΩ. 12. Design a universal buck PWM converter to meet the following specifications: V, V, VO = 48 V, IO = 0.2 to 2 A, Vr/VO ≤ 1%, fs = 200 kHz, rL = 1 Ω, rDS = 1 Ω, Co = 100 pF, VF = 0.7 V, and RF = 25 mΩ. 13. A buck converter has the following specifications: VI = 4–6 V, VO = 3 V, IO = 0–5 A, fs = 250 kHz, and Vr/VO ≤ 2%. Assume η = 0.9. Find L, C, and rC. 14. A buck PWM converter has VI = 270 V ± 5%, VO = 28 V, IO = 0–15 A, Vr/VO ≤ 5%, rL(dc)

= 0.05 Ω, rC = 0.037 Ω, rDS = 0.3 Ω, Co = 150 pF, VF = 0.8 V, RF = 17.1 mΩ, and fs = 100 kHz. Find L, C, and rC. Assume the initial efficiency η = 90% at full power. 15. A buck PWM converter has VI = 5 V ± 20%, VO = 1.8 V, IO = 1–10 A, Vr/VO ≤ 3%, rL(dc) = 0.02 Ω, rDS = 0.01 Ω, Co = 150 pF, VF = 0.3 V, RF = 18 mΩ, and fs = 500 kHz. Find L, C, rCmax, ISMmax, and VSMmax. Estimate PLS and η at IOmax and VImin. Assume the initial efficiency η = 80% at full power. 16. Design a buck converter to meet the following specifications: VI = 5 ± 1 V, VO = 3.3 V, IO = 0–5 A, Vr/VO ≤ 1%, fs = 500 kHz, rDS = 8 mΩ, RF = 20 mΩ, VF = 0.3 V, rL = 50 mΩ, and Qg = 50 nC. 17. Design a buck PWM converter to meet the following specifications: VI = 3.3 V ± 0.3 V, VO = 1.8 V, IO = 0.3–1.5 A, Vr ≤ 10 mV, and fs = 200 kHz.

3 Boost PWM DC–DC Converter 3.1 Introduction This chapter is devoted to the PWM boost dc–dc switching-mode converter [1–21]. The converter is analyzed for both CCM and DCM. Voltage and current waveforms are derived. The dc voltage transfer function is determined. The voltage and current stresses of the converter components are given. Expressions for the inductance and the capacitance are derived. Power losses are estimated. Design examples are given.

3.2 DC Analysis of PWM Boost Converter for CCM 3.2.1 Circuit Description The circuit of the PWM boost dc–dc converter is shown in Figure 3.1(a). Its output voltage VO is always higher than the input voltage VI for steady-state operation. It “boosts” the voltage to a higher level. The converter consists of an inductor L, a power MOSFET, a diode D1, a filter capacitor C, and a load resistor RL. The switch S is turned on and off at the switching frequency fs = 1/T with the ON duty ratio D = ton/T, where ton is the time interval when the switch S is ON.

Figure 3.1 PWM boost converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. The boost converter can operate in one of the two modes: a continuous conduction mode (CCM) or a discontinuous conduction mode (DCM), depending on the waveform of the inductor current. The boost converter in DCM cannot operate at RL = ∞ because the filter capacitor has no path to discharge. The CCM will be considered first. Figures 3.1(b) and (c) show equivalent circuits of the boost converter for CCM when the switch S is ON and the diode is OFF, and when the switch is OFF and the diode is ON, respectively. Idealized waveforms of the currents and voltages that explain the principle of operation of the boost converter are depicted in Figure 3.2. For the time interval 0 < t ≤ DT, the switch is ON. Therefore, the voltage across the diode is vD = −VO, causing the diode to be reverse biased. The voltage across the inductor is vL = VI. As a result, the inductor current increases linearly with a slope of VI/L. Consequently, the magnetic energy also increases. The switch current is equal to the inductor current. At t = DT, the switch is turned off by the gate-to-source voltage.

The inductor acts as a current source and turns the diode on. The voltage across the inductor is vL = VI − VO < 0. Hence, the inductor current decreases with a slope of (VI − VO)/L. The diode current is equal to the inductor current. During this time interval, the energy is transferred from the inductor L to the filter capacitor C and the load resistance RL. At time t = T, the switch is turned on again, terminating the cycle.

Figure 3.2 Idealized current and voltage waveforms in the PWM boost converter for CCM. The boost converter has poor ability to prevent hazardous transients and failures. If a high positive voltage surge appears at the converter input, the input voltage exceeds the output voltage and the diode D1 is on for many cycles due to cycle skip. This generates a large current spike through the diode, which may destroy the diode. A similar problem exists at the initial turn-on of the converter when the input voltage is high and the output voltage is initially zero and while the output voltage is lower than the input voltage until steady-state conditions are approached. One way to protect the converter is to add a diode whose anode is connected to the input source VI and the cathode is connected to the output filter capacitor C. When the output voltage is lower than the input voltage, the additional diode and the filter capacitor form

a peak rectifier and the energy flows from the input to the output of the converter through the additional diode. When the output voltage becomes higher than the input voltage, the additional diode is reverse biased and turns off and the boost converter begins normal operation. The output power level of the boost converter is usually between 20 and 400 W. This converter is commonly used as an active power factor corrector.

3.2.2 Assumptions The analysis of the boost PWM converter of Figure 3.1(a) begins with the following assumptions: 1. The power MOSFET and the diode are ideal switches. 2. The transistor output capacitance, the diode capacitance, and lead inductances (and thereby switching losses) are zero. 3. Passive components are linear, time invariant, and frequency independent. 4. The output impedance of the input voltage source VI is zero for both dc and ac components.

3.2.3 Time Interval: 0 < t ≤ DT The switch S is ON and the diode is OFF during the time interval 0 < t ≤ DT. An ideal equivalent circuit for this time interval is shown in Figure 3.1(b). When the switch is ON, the voltage across the diode vD is approximately equal to − VO and therefore the diode is reverse biased. The voltage across the switch vS and the diode current are zero. The voltage across the inductor L is (3.1) and the inductor current iL and the switch current iS is (3.2) where iL(0) is the initial inductor current at time t = 0. From (3.2), the peak inductor current is obtained (3.3) It will be shown shortly that the dc voltage transfer function is MVDC = VO/VI = II/IO = 1/(1 − D). Hence, the peak-to-peak value of the inductor ripple current is expressed as (3.4)

For fixed values of VO, fs, and L, (3.5) Setting this derivative to zero, one can show that the maximum value of ΔiL occurs at D = 0.5 and is given by (3.6)

As the duty cycle D is increased from 0 to 1, the peak-to-peak inductor ripple current ΔiL increases from zero, reaches its maximum at D = 0.5, and then decreases to zero. The diode voltage is (3.7) Therefore, the diode is OFF. The average value of the inductor current IL is equal to the dc input current II. Hence, one arrives at the peak value of the switch current (3.8) This time interval is terminated at t = DT when the switch is turned off by the driver. The inductor current iL flows continuously for CCM. Since iL(DT) is nonzero when the switch is turned off, it acts almost as a current source and turns the diode on. The waveform of the magnetic energy stored in the inductor is (3.9) The increase in the inductor magnetic energy is (3.10)

3.2.4 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch is OFF and the diode is ON. Figure 3.1(c) shows an ideal equivalent circuit of the lossless converter for this time interval. The switch current iS and the diode voltage vD are zero. The inductor discharges during this time interval. The voltage across the inductor L is

(3.11) which indicates that VO > VI. The current through the inductor and the diode can be found as (3.12) where iL(DT) is the initial inductor current iL at t = DT. The peak-to-peak value of the inductor ripple current is (3.13) where VI = VO(1 − D). The voltage across the switch S is given by (3.14) The peak diode current and the peak switch current are given by (3.15) For the worst case, this expression becomes (3.16) This time interval ends at t = T when the switch is turned on by the driver. The decrease in the magnetic energy stored in the inductor L during the time interval DT < t ≤ T is (3.17) For steady state, the increase in the magnetic energy stored in the inductor during the time interval 0 < t ≤ DT is equal to the decrease in the magnetic energy stored in the inductor during the time interval DT < t ≤ T.

3.2.5 DC Voltage Transfer Function for CCM The average value of the voltage across the inductor for steady state is (3.18) Referring to Figure 3.2,

(3.19) which gives (3.20) and results in the dc voltage transfer function for the lossless boost converter (3.21) The range of MVDC for the lossless converter is (3.22) It will be shown shortly that the maximum value of MVDC is limited by losses. Rearrangement of (3.21) gives (3.23) The sensitivity of VO with respect to D is (3.24) The dc current transfer function of the boost converter is (3.25) As D is increased from 0 to 1, MIDC decreases from 1 to 0. Using (3.21) and (3.25), the outputpower capability of the boost converter is (3.26) As D is increased from 0 to 1, cp decreases from 1 to 0.

3.2.6 Boundary Between CCM and DCM Figure 3.3 shows the inductor current waveform at the boundary between the CCM and the DCM. This waveform is given by (3.27) from which

(3.28) The dc input current at the boundary between CCM and DCM is (3.29) whose maximum value occurs at D = 0.5. From (3.21) and (3.29), the dc output current at the boundary between CCM and DCM is (3.30) and the load resistance at the boundary is (3.31) Figures 3.4 and 3.5 show the plots of IOB/(VO/2fsL) = D(1 − D)2 and RLB/(2fsL) = 1/[D(1 − D)2] as functions of D. To find the maximum value of IOB, its derivative can be found as (3.32) Thus, the maximum value of IOB occurs at (3.33) which corresponds to MVDC = 1.5. Substitution of (3.33) into (3.30) gives the maximum value of the load current at the boundary (3.34) and the minimum value of the load resistance at the boundary (3.35) Hence, using IOBmax = IOmin = VO/RLmax, one arrives at the minimum value of the inductance L which ensures the operation in CCM at any value of D (3.36)

Figure 3.3 Waveform of the inductor current at the boundary between CCM and DCM for the boost converter.

Figure 3.4 Normalized load current IOB/(VO/2fsL) at the boundary between CCM and DCM as a function of D for boost converter.

Figure 3.5 Normalized load resistance RLB/(2fsL) at the boundary between CCM and DCM as a function of D for boost converter. If Dmax < 1/3 or Dmin > 1/3, a less conservative approach can be taken. Using (3.30), the following expressions can be derived (3.37)

and

(3.38)

3.2.7 Ripple Voltage in Boost Converter for CCM The output part of the boost converter is shown in Figure 3.6. The filter capacitor in this figure is modeled by its capacitance C and its equivalent series resistance (ESR) rC. Figure 3.7 shows current and voltage waveforms in the converter output circuit. The dc component of the diode current flows through the load resistor RL. The ac component of the diode current is divided between the capacitor branch and the load resistance branch. In practice, the filter capacitor is designed in such a way that the impedance of the capacitor branch is much less than the load resistance RL. Consequently, the current through the capacitor is approximately equal to the ac component of the diode current.

Figure 3.6 Equivalent circuit of the output part of the boost converter.

Figure 3.7 Waveforms illustrating the ripple voltage in the PWM boost converter. The maximum peak-to-peak value of the capacitor current is (3.39) resulting in the peak-to-peak value of the voltage across rC (3.40) The peak-to-peak value of the output ripple voltage Vr is usually specified. Hence, the maximum peak-to-peak value of the ac component of the voltage across the capacitance C is found as (3.41)

On the other hand, this voltage is approximately given by (3.42) where ΔQmax is the charge decrease during the time interval from zero to DT. Rearrangement of (3.42) gives the minimum filter capacitance (3.43)

3.2.8 Power Losses and Efficiency of Boost Converter for CCM An equivalent circuit of the boost converter with parasitic resistances is shown in Figure 3.8, where rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be evaluated assuming that the inductor current iL is ripple free and equals the dc input current II. Hence, the switch current can be approximated by (3.44) resulting in its rms value (3.45) and the MOSFET conduction loss (3.46) Note that the transistor conduction loss increases rapidly with increasing duty cycle D at a fixed load current IO.

Figure 3.8 Equivalent circuit of the boost converter with parasitic resistances and the diode offset voltage. Assuming that the transistor output capacitance Co is linear, the switching loss is expressed by (3.47) Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) (3.48) Likewise, the diode current can be approximated by (3.49) yielding its rms value (3.50)

and the power loss in RF (3.51) The diode power loss due to RF increases rapidly with increasing duty cycle D at fixed load current IO.

The average value of the diode current is (3.52) which gives the power loss associated with the voltage VF (3.53) Thus, the overall diode conduction loss is (3.54) The inductor current is (3.55) leading to its rms value (3.56) and the inductor loss (3.57) The inductor loss increases rapidly with increasing duty cycle D at fixed load current IO. The current through the capacitor C is approximately given by (3.58) Hence, one obtains the rms current through the filter capacitor (3.59) and the power loss in the filter capacitor (3.60)

The overall power loss of the boost converter is (3.61) yielding the converter efficiency (3.62) Figure 3.9 shows the efficiency of the boost converter η as a function of the duty cycle D for VO = 28 V, rDS = 0.5 Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. It can be seen that the efficiency η decreases with increasing D and it is higher for higher load resistances RL.

Figure 3.9 Efficiency of the boost converter η versus D for VO = 28 V, rDS = 0.5 Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF.

3.2.9 DC Voltage Transfer Function of Lossy Boost Converter for CCM The dc component of the output current is (3.63) leading to the dc current transfer function of the boost converter (3.64) This equation holds true for both lossless and lossy converters. The efficiency of the converter can be expressed as (3.65) from which the voltage transfer function of the lossy boost converter is (3.66) Figure 3.10 depicts MVDC as a function of D. The duty cycle of the lossy boost converter is (3.67) Thus, the duty cycle D increases as the efficiency decreases at a fixed value of MVDC.

Figure 3.10 DC voltage transfer function MVDC of the lossy boost converter as a function of D for CCM at VO = 28 V, rDS = 0.5Ω, VF = 0.7 V, RF = 25 m Ω, rL = 0.3 Ω, rC = 40 m Ω, fs = 100 kHz, and Co = 100 pF. Substitution of (3.67) into (3.62) yields the converter efficiency (3.68) where (3.69)

and

(3.70)

3.2.10 Design of Boost Converter for CCM Design a PWM boost converter to meet the following specifications: VI is the US single-phase rectified utility line voltage, VO = 400 V, IOmax = 0.225 A, IOmin = 5% of IOmax, and Vr/VO < 1%. Solution: Assume that the converter is operated in CCM. The rms voltage of the US utility line changes from 90 V (low line) to 132 V (high line) for normal operation. Hence, the minimum, nominal, and maximum values of the dc voltages at the output of a full-bridge front-end rectifier are (3.71) (3.72) and (3.73) The minimum load current is (3.74) The maximum and minimum values of the output power are (3.75) and (3.76) The minimum and the maximum load resistances are (3.77) and (3.78) The minimum, nominal, and maximum values of the dc voltage transfer function are

(3.79) (3.80) and (3.81) Assume that the efficiency η of the converter is 90%. Hence, the minimum, nominal, and maximum values of the duty cycle are (3.82) (3.83) and (3.84) Let us assume the switching frequency fs = 100 kHz. The minimum inductance that ensures CCM operation at any duty cycle D is (3.85) Since Dmin = 0.58 > 1/3, the minimum inductance required for CCM operation can be calculated as (3.86) Pick L = 20 mH. One can design this inductor so that its dc ESR is rL(dc) = 2.1 Ω. For D > 0.5, the maximum inductor peak-to-peak current of the ac component occurs at Dmin. Hence, (3.87) The current and voltage stresses of the MOSFET and the diode are

(3.88)

and (3.89) One can select an MTP4N50 power MOSFET with VDSS = 500 V, ISM = 4 A, rDS = 1 Ω, Qg = 27 nC, and Co = 100 pF. An ultrafast recovery diode MUR1560 is also chosen, which has VDM = 600 V, IDM = 15 A, VF = 0.7 V, and RF = 17.1 m Ω. The ripple voltage is (3.90) Let us assume that the ripple voltage is equally divided between the capacitance and the ESR. Thus (3.91) Hence, the maximum ESR is (3.92) and the minimum filter capacitance is (3.93) Pick a metallized polyester capacitor with C = 1 μ F/630 V/1 Ω. The minimum corner frequency of the output filter is (3.94) and the maximum corner frequency of the output filter is (3.95) The rms values of the inductor current is (3.96) resulting in the inductor power loss

(3.97) The rms values of the switch current is (3.98) which leads to the MOSFET conduction loss (3.99) The output capacitance of the MOSFET is Co = 100 pF. Hence, the switching loss is (3.100) The total power loss in the MOSFET is (3.101) The diode power loss due to the diode offset voltage VF is (3.102) The diode rms current is (3.103) resulting in the power loss due to the diode forward resistance RF (3.104) Thus, the diode conduction loss is (3.105) The capacitor rms current is (3.106) Assuming the ESR of the filter capacitor rC = 1 Ω, the power loss in the capacitor is (3.107) The total power loss is

(3.108) and the converter efficiency at full load is (3.109) Assuming the magnitude of the gate-to-source voltage VGSm = 7 V, the gate-drive power is calculated as (3.110) Using (3.68) through (3.70), the efficiency η of the designed boost converter can be computed over the entire range of VI and IO (or RL) for CCM. Using the calculated efficiency η, the duty cycle D can be calculated from (3.67). Figures 3.11 and 3.12 depict the efficiency η and the duty cycle D of the designed boost converter versus the dc input voltage VI at fixed load resistances RL. Plots of the efficiency η and the duty cycle D as functions of IO at fixed values of VI are shown in Figures 3.13 and 3.14. Figures 3.15 and 3.16 show the efficiency η and the duty cycle D of the designed converter as functions of RL at fixed values of VI. The efficiency η increases as IO increases (or RL decreases). The maximum efficiency ηmax occurs at the maximum load current IOmax, and the minimum efficiency ηmin occurs at the minimum load IOmin, which is an advantage of the boost converter. The duty cycle D increases as VI and IO decrease.

Figure 3.11 Efficiency η of the designed boost converter as a function of VI at fixed values of RL for CCM.

Figure 3.12 Duty cycle D of the boost converter designed as a function of VI at fixed values of RL for CCM.

Figure 3.13 Efficiency η of the designed boost converter as a function of load current IO at fixed values of VI for CCM.

Figure 3.14 Duty cycle D of the designed boost converter as a function of load current IO at fixed values of VI for CCM.

Figure 3.15 Efficiency η of the designed boost converter as a function of load resistance RL at fixed values of VI for CCM.

Figure 3.16 Duty cycle D of the designed boost converter as a function of load resistance RL at fixed values of VI for CCM.

3.3 DC Analysis of PWM Boost Converter for DCM Equivalent circuits for the PWM boost converter operating in the DCM are depicted in Figure 3.17. Idealized current and voltage waveforms are shown in Figure 3.18. For the time interval 0 < t ≤ DT, the switch is ON and therefore the diode is OFF. The voltage across the inductor is VI and the inductor current increases linearly from zero. For the time interval DT < t ≤ (D + D1)T, the switch is OFF and the diode is ON. At time t = (D + D1)T, the inductor and diode current reaches zero, turning the diode off. For the time interval (D + D1)T < t ≤ T, both the switch and the diode are off. Since the current through the inductor is constant (equal to zero), the voltage across the inductor is zero. At time t = T, the switch is turned on and the inductor current starts to increase from zero.

Figure 3.17 PWM boost converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF.

Figure 3.18 Idealized current and voltage waveforms in the PWM boost converter for DCM.

3.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is ON and the diode is OFF. The equivalent circuit is shown in Figure 3.17(b). The switch voltage vS and the diode current iD are zero. The voltage across the inductor L is (3.111) and the inductor and switch current is (3.112) Hence, the peak switch and inductor current is

(3.113) The voltage across the diode is (3.114) Therefore, the diode is OFF. The energy stored in the magnetic field of the inductor is (3.115) This time interval ends when the switch is turned off by the driver.

3.3.2 Time Interval: DT < t ≤ (D + D1)T The equivalent circuit for this time interval is shown in Figure 3.17(c). The switch is OFF and the diode is ON. Hence, iS = 0 and vD = 0. The voltage across the inductor L is given by (3.116) Using (3.113), the diode and inductor current is (3.117)

The peak diode and inductor current is obtained as (3.118) The voltage across the switch is (3.119) The energy stored in the magnetic field of the inductor is (3.120) When the diode current reaches zero, this time interval ends.

3.3.3 Time Interval: (D + D1)T < t ≤ T During this time interval, both the switch and the diode are OFF. The equivalent circuit is

shown in Figure 3.17(d). The inductor current iL, the inductor voltage vL, the switch current iS, and the diode current iD are zero. The voltage across the switch is (3.121) and the voltage across the diode is (3.122) This time ends when the switch is turned on by the driver.

3.3.4 Device Stresses for DCM The maximum switch and diode voltage stresses for steady state are (3.123) The maximum steady-state switch and diode current stresses occur at full power and they are (3.124)

3.3.5 DC Voltage Transfer Function for DCM Referring to Figure 3.18 and using the volt-second balance, (3.125) leading to (3.126) From (3.113) and (3.126), the peak-to-peak inductor current is (3.127) Using (3.126) and (3.127), the dc input current is obtained as an average value of the inductor current (3.128) from which (3.129)

Hence, (3.130) At the boundary between CCM and DCM, MVDCB = 1/(1 − DB) as in CCM. Therefore, the boundary occurs at (3.131) As the normalized load current is increased from zero to 4fsLIO/(27VO), the boundary duty cycle DB increases from zero to 1/3 and then decreases to zero. Figures 3.19 and 3.20 show plots of the duty cycle D versus the normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of MVDC for both CCM and DCM.

Figure 3.19 Duty cycle D as a function of normalized load current IO/(VO/2fsL) at various values of MVDC for the lossless boost converter.

Figure 3.20 Duty cycle D as a function of normalized load resistance RL/(2fsL) at various values of MVDC for the lossless boost converter. From (3.130), one obtains (3.132) which produces the dc voltage transfer function of the boost converter for DCM (3.133)

It can be seen that MVDC depends on D, RL, L, and fs. Figures 3.21 and 3.22 depict plots of

MVDC versus IO/(VO/2fsL) and RL/(2fsL) at fixed values of D.

Figure 3.21 DC voltage transfer function MVDC as a function of normalized load current IO/(VO/2fsL) at various values of D for the lossless boost converter.

Figure 3.22 DC voltage transfer function MVDC as a function of normalized load resistance RL/(2fsL) at various values of D for the lossless boost converter. Rearrangement of (3.130) produces the inductance required for given values of MVDC, D, RL, and fs (3.134) From (3.126) and (3.130), one obtains D1 in terms of D, RL, L, and fs (3.135)

3.3.6 Maximum Inductance for DCM The dc output current at the boundary between DCM and CCM occurs at D = DBmin for D < 1/3 and at D = DBmax for D > 1/3. Therefore, (3.136)

and (3.137)

If DBmin < 1/3 and DBmax > 1/3, (3.138) The dwell-duty cycle is (3.139) yielding (3.140) Substitution of (3.130) for D gives (3.141) producing the maximum inductance for a given dwell-duty cycle (3.142)

3.3.7 Power Losses and Efficiency of Boost Converter for DCM

Substitution of (3.133) into (3.127) yields (3.143)

The rms value of the switch current is (3.144)

resulting in the MOSFET conduction loss (3.145)

The switching loss in the converter is (3.146) Likewise, the rms value of the diode current is (3.147)

which gives the diode conduction loss associated with RF

(3.148)

The average current through the diode is ID = IO, yielding the diode conduction loss associated with VF (3.149) Therefore, the total diode conduction loss is (3.150)

The rms value of the inductor current is (3.151)

resulting in the conduction loss in the inductor ESR (3.152) The total power loss is

(3.153)

and the efficiency can be found to be (3.154)

Using (3.128), the dc input power is (3.155) the dc output power is (3.156) and the converter efficiency is (3.157) Hence, the duty cycle for the lossy boost converter in DCM is (3.158)

and the dc voltage transfer function for the lossy boost converter in DCM is (3.159)

3.3.8 Design of Boost Converter for DCM Example 3.1 Solution: A boost converter has the following parameters: VI = 8–18 V, VO = 24 V, POmax = 48 W, POmin = 0, rL = 0.05 Ω, rC = 0.01 Ω, rDS = 0.055 Ω, Co = 100 pF, RF = 0.025 Ω, VF = 0.3 V, fs = 100 kHz, and Vr/VO ≤ 1%. Find component values, component stresses, and the efficiency at full power. At full power, the maximum load current is (3.160) and the minimum load resistance is (3.161) The minimum and maximum values of the dc voltage transfer function are (3.162) and (3.163) Hence, the minimum and maximum values of the duty cycle at the CCM/DCM boundary are (3.164) and (3.165) The maximum inductances required for DCM operation at DBmax and DBmin are

(3.166)

and (3.167) resulting in the maximum inductance required for DCM operation under any operating conditions (3.168) Assuming the dwell-duty cycle Dw = 0.1, we get the maximum inductance (3.169) Let L = 3.3 μ H < Lmax. Assuming η = 0.9, the maximum duty cycle at RLmin = 12 Ω and VI = VImin = 8 V is (3.170) and (3.171) yielding (3.172) and (3.173) The maximum peak switch, diode, and inductor current is (3.174) The minimum duty cycle at RLmin at RLmin = 12 Ω and V = VImax = 18 V is

(3.175)

and (3.176) producing (3.177) and (3.178) The maximum peak switch, diode, and inductor current is (3.179) The maximum switch and diode voltage stress is (3.180) The ripple voltage on the output voltage is (3.181) The peak-to-peak ripple voltage across rC = 0.01 Ω is (3.182) Thus, the ripple voltage across the filter capacitance C is (3.183) Hence, the minimum capacitance is (3.184) Pick C = 150 μF/36 V/ 0.01 Ω. The component power losses will be calculated at VImin = 8 V, RLmin = 12 Ω, POmax = 48 W, and IOmax = 2 A. The conduction loss in the power MOSFET is

(3.185)

The switching loss is (3.186) The power loss in the diode forward resistance is (3.187)

and the power loss in the diode offset voltage source VF is (3.188) resulting in the diode conduction loss (3.189) The power loss in the inductor is (3.190)

The overall power loss is (3.191) The efficiency of the converter boost for DCM is (3.192) Assuming the gate charge Qg = 50 nC and VDSpp = 8 V, the MOSFET gate-drive power is (3.193) Figures 3.23 and 3.28 depict the efficiency η and the duty cycle D of the designed boost converter as functions of VI at fixed load resistances RL for DCM. Figures 3.25 and 3.26 show the efficiency η and the duty cycle D and of the designed converter as functions of IO and RL at fixed values of VI. Figures 3.28 and 3.27 depict the efficiency η and the duty cycle D of the designed boost converter as functions of RL at fixed values of VI. The duty cycle D decreases

as VI increases and IO decreases (or RL increases). The efficiency η increases as VI increases and η decreases as IO increases (or RL decreases).

Figure 3.23 Efficiency η as a function of VI at fixed values of RL for the boost converter in DCM.

Figure 3.24 Duty cycle D as a function of VI at fixed values of RL for the boost converter in DCM.

Figure 3.25 Efficiency η as a function of IO at fixed values of VI for the designed boost converter in DCM.

Figure 3.26 Duty cycle D as a function of IO at fixed values of VI for the boost converter in DCM.

Figure 3.27 Efficiency η as a function of RL at fixed values of VI of the designed boost converter in DCM.

Figure 3.28 Duty cycle D as a function of RL at fixed values of VI for DCM at fixed values of VI. Example 3.2 A boost converter has the following parameters: VI = 10 V, VO = 20 V, POmax = 40 W, POmin = 0, rL = 0.1 Ω, rC = 0.1 Ω, rDS = 0.055 Ω, Co = 100 pF, RF = 0.025 Ω, VF = 0.3 V, fs = 50 kHz, and Vr/VO ≤ 5.5%. Find component values, component stresses, and the efficiency at full power. Solution: At full power, the maximum load current is (3.194) and the minimum load resistance is

(3.195) The dc voltage transfer function is (3.196) Hence, the duty cycle at the CCM/DCM boundary for MVDC = 2 is (3.197) The maximum inductance required for DCM operation at DB is (3.198) Assuming Dmax = 0.4 at full power, one obtains (3.199) (3.200) and (3.201) Thus, L < Lmax. The maximum peak switch, diode, and inductor current is (3.202) The maximum switch and diode voltage stress is (3.203) The peak-to-peak ripple voltage across rC = 0.1 Ω is (3.204) The ripple voltage on the output voltage is (3.205)

Thus, the ripple voltage across the filter capacitance C is (3.206) Hence, the minimum capacitance is (3.207) Pick C = 220 μF/36 V/0.1 Ω. The component power losses will be calculated at VI = 10 V, RLmin = 10 Ω, POmax = 40 W, and IOmax = 2 A. The conduction loss in the power MOSFET is (3.208)

The switching loss is (3.209) The power loss in the diode forward resistance is (3.210)

and the power loss in the diode offset voltage source VF is (3.211) resulting in the diode conduction loss (3.212) The power loss in the inductor is (3.213)

The overall power loss is (3.214) The efficiency of the converter is

(3.215)

3.4 Bidirectional Buck and Boost Converters Figure 3.29(a) shows the classical boost converter topology with a negative common rail. In the converter of Figure 3.29(b), the inductor and the diode are moved to the negative rail, resulting in the boost converter topology with a positive common rail. Figure 3.29(c) shows the boost converter topology of Figure 3.29(b) flipped so that the positive common rail is at the bottom.

Figure 3.29 Derivation of the boost converter topology with a positive common rail. (a) Boost converter with a negative common rail. (b) Boost converter with the inductor and diode moved to the negative rail. (c) Boost converter with a positive common rail at the bottom. A bidirectional buck and boost PWM converter [21] is shown in Figure 3.30. In this circuit, both switches are composed of a transistor and an antiparallel diode. They can conduct current

in both directions, but can support the voltage in only one direction. In other words, the switches are bidirectional for the current and unidirectional for the voltage. These are twoquadrant switches, which permit energy flow in both directions, from left to right, and vice versa.

Figure 3.30 Bidirectional buck and boost PWM converters. If a dc voltage source V1 is connected in parallel with the capacitor C1 and a load is connected in parallel with the capacitor C2, the buck converter is obtained. In this case, the energy flows from left to right. The horizontal MOSFET channel is used as a controllable switch and its antiparallel diode is permanently OFF, whereas the vertical diode is used as a passive (naturally commutated) switch. The channel of the vertical MOSFET can be held permanently OFF or it can be turned on by a driver, when the vertical diode is ON. In contrast, if a dc voltage source V2 is connected in parallel with the capacitor C2 and a load is connected in parallel with the capacitor C1, the boost converter is obtained. Then, the energy flows from right to left. The channel of the vertical MOSFET is used as a controllable switch and its antiparallel diode is always OFF, whereas the horizontal diode is used as a passive switch. The channel of the horizontal MOSFET can be kept in the off-state during the whole cycle or it can be turned on, when the horizontal diode is ON. Figure 3.31 shows an isolated boost converter. It consists of inductor L, full-bridge inverter, high-frequency transformer, bridge rectifier, and a filter capacitor. The circuit can operate as either a noninverting or inverting converter and it is suitable for high-power applications.

Figure 3.31 Isolated boost PWM converter.

3.5 Synchronous Boost Converter Figure 3.32 shows a synchronous boost converter. In this circuit, the diode is replaced by a MOSFET. Assuming that both transistors have the same on-resistance rDS, the efficiency of the synchronous converter is (3.216)

The dc voltage transfer function of this converter is (3.217)

Figure 3.32 Synchronous boost PWM converter.

3.6 Tapped-Inductor Boost Converters A tapped-inductor common-transistor (CT) boost converter [13] is shown in Figure 3.33(a). It is a high step-up converter. The voltage transfer function of the tapped inductor is (3.218) When the MOSFET is ON and the diode is OFF, (3.219) When the MOSFET is OFF and the diode is ON, (3.220) resulting in (3.221) Using the volt-second balance for the Np winding across which the voltage is vS, (3.222) Hence, the dc voltage transfer function of the tapped-inductor common-transistor configuration operating in CCM is given by (3.223) Plots of MVDC as a function of D for CCM are shown in Figure 3.34. The magnetizing inductance Lm on the terminals of the winding Np is given by (3.224) where L is the total inductance of winding Lp + Ls.

Figure 3.33 Tapped-inductor boost converters. (a) Tapped-inductor common-transistor boost converter. (b) Tapped-inductor common-diode boost converter. (c) Tapped-inductor commonload boost converter.

Figure 3.34 DC voltage transfer function of tapped-inductor common-transistor boost converter for CCM.

3.6.1 Tapped-Inductor Common-Diode Boost Converter A tapped-inductor common-diode (CD) boost converter is shown in Figure 3.33(b). When the MOSFET is OFF and the diode is ON, (3.225) resulting in (3.226) When the MOSFET is OFF and the diode is ON, (3.227)

Using the volt-second balance for the inductance Lp across which the voltage is vp, (3.228) we obtain the dc voltage transfer function of the tapped-inductor common-diode in CCM (3.229) Figure 3.35 shows plots of MVDC as a function of D for CCM.

Figure 3.35 DC voltage transfer function of tapped-inductor common-diode boost converter for CCM.

3.6.2 Tapped-Inductor Common-Load Boost Converter A tapped-inductor common-load (CL) boost converter is shown in Figure 3.33(c). It is an

inverse Watkins–Johnson (IWJ) converter [21]. When the MOSFET is ON and the diode is OFF, (3.230) resulting in (3.231) When the MOSFET is OFF and the diode is ON, (3.232) producing (3.233) Applying the volt-second balance, (3.234) Hence, we obtain the dc voltage transfer function of the tapped-inductor common-load boost converter (3.235) Plots of MVDC as a function of D for the tapped-inductor common-diode boost converter operating in CCM are shown in Figure 3.36.

Figure 3.36 DC voltage transfer function of tapped-inductor common-load (IWJ) boost converter for CCM.

3.7 Duality In order to use the duality principles for dc–dc converters, it is useful to introduce the following simplifications: 1. An inductor in series with a parallel combination of filter capacitor and a load resistance (or the inductor in series with a load resistance) can be replaced by a dc current sink. 2. A filter capacitor in parallel with a resistor can be replaced by a voltage source. 3. A dc source in series with an inductor can be replaced by a dc current source. The duality principles in dc–dc converter are as follows: 1. Replace a dc voltage source by a dc current source.

2. Replace a series switch by a parallel switch, and vice versa. 3. Replace a parallel diode by a series diode, and vice versa. 4. Replace a dc current sink by a dc voltage source. 5. Replace a dc voltage sink by a dc current source. 6. Replace the on-duty cycle D by the off-duty cycle

.

Figure 3.37 shows the derivation of the boost converter from the buck converter, or vice versa, using the duality principles.

Figure 3.37 Derivation of the boost converter from the buck converter, or vice versa, using the duality principles.

3.8 Power Factor Correction 3.8.1 Power Factor

The power factor describes the effectiveness of energy transmission from a source to a load. It indicates the power utilization efficiency. The loads can be resistive or reactive, and linear or nonlinear. Nonlinear loads generate current harmonics, which are injected into the utility power system, degrading it. Reactive components of the load impedance cause a phase shift between load current and voltage. If the power factor PF is low, the energy transmission loss is higher and the power station must produce more power to satisfy the needs of various loads. Thus, green energy requires a high-quality energy with a high power factor PF. Universal ac–dc power supplies of electronic systems should be designed to accept any level of utility voltage used in the world, which are in the range from 92 to 264 Vrms. A low utility line voltage in the United States is 92 Vrms and a high utility line voltage in Europe is 264 Vrms. Universal power supplies must satisfy IEC 61000-3-2 Class C regulation, IEC555-2 line harmonic standard, and VDE 0871B conducted emission standard. Information technology equipment must comply with EMI standards, such as CISPR-22, which determines the limits of the EMI noise generated in the frequency range from 150 kHz to 300 MHz. Conventional peak rectifiers contain a full-wave bridge rectifier followed by a large storage and filter capacitor, as shown in Figure 3.38. The diodes in these rectifiers conduct current for a very short portion of a cycle. The conduction angle of the diode current is very small because the filter capacitor remains charged at or near the peak ac voltage during each cycle. As a result, the rectifier diodes are reverse biased most of the time and no current flows. The unidirectional diode currents are reflected to the input of the front-end rectifier and form the line current waveform is composed of very narrow positive and negative pulses, as shown in Figure 3.39. Therefore, the input current waveform of peak rectifiers with capacitive filters consists of half-sine wave pulses and contains a lot of odd harmonics, up to the 25th harmonic. In addition, the phase shift ϕ between the fundamental components of the utility voltage and current gives cos ϕ = 0.6–0.8. Usually, THD > 130%, resulting in a very low power factor, usually, PF < 0.6. Power supplies must comply with power quality regulations, such as IEC 61000-3-2 Class C.

Figure 3.38 Full-wave peak rectifier.

Figure 3.39 Line voltage and current loaded by a full-wave peak rectifier. The power factor is defined as ratio of the real power to the apparent power (3.236)

where the real power, called the average power or the time-average power, is given by (3.237) the apparent power is (3.238)

p = vi is the instantaneous power, and S = VI* = |S|eϕ is the complex power. Only the real power produces real work. Let us assume that the utility line voltage is purely sinusoidal (3.239) In general, the utility line current waveform is periodic and nonsinusoidal, which can be represented by a Fourier series (3.240) The rms value of the line ac current is (3.241) The total harmonic distortion is defined by (3.242)

The power factor for a sinusoidal voltage and a nonsinusoidal current is defined as (3.243)

where the distortion factor or the current distortion factor is (3.244) and the displacement angle or the displacement factor is (3.245) The distortion factor FDF as function of THD is shown in Figure 3.40. Usually, for line rectifiers, ϕ1 = 0 and the power factor becomes (3.246)

The range of PF is from 0 to 1. For perfect energy transmission from a source to a load, a unity

power factor (PF = 1) is required. In this case, the load presented by an electric circuit to the utility line behaves like a linear resistance. When the rms values of current harmonics are zero, THD = 0 and PF = 1 (at cos ϕ1 = 1). The total harmonic distortion (THD) in terms of the power factor PF is (3.247) The rms value of input current of an ac–dc power converter with the output power PO and efficiency η is (3.248)

Figure 3.40 Distortion factor FDF as a function of THD. As off-line ac–dc converters deliver increasing amounts of power, power factor correction (PFC) becomes of great interest to both manufacturers and users. The line current, although in

phase with the ac line voltage, is often nonsinusoidal with high peak values, placing high stress on circuit breakers, fuses, wall sockets, installation wires, and transformers. Since wall sockets are being pushed to their limit, safety becomes an important issue. In the United States, a typical office has a 15 A/110 V wall plug, which cannot be run at more than 80% of its rating according to the UL regulation. The maximum current drawn from the line is 12 Arms. Line voltages sag and become distorted. Also, there is an increased power loss in the transmission line resistance because a larger rms current is required for a given real power P at PF < 1. Since power companies want to minimize the power loss in the transmission lines, they want the customers to have a power factor as close to 1 as possible. For this reason, they will provide penalties or price incentives to encourage the users to reduce the cost of energy transmission. A typical value of the power factor for single-phase 110/220 Vrms lines is 0.65, but it can go as low as 0.49, depending on the front-end rectifier and the line impedance, which is in the range from 0.1 to 1.5 Ω. The apparent power becomes much larger than the real power when the power factor is poor. Rising power quality requirements and the proliferation of electronic equipment are demanding that off-line converters incorporate PFC. There are passive and active power factor correctors. Passive PFCs use a large input choke. If a choke inductance is large enough, a PFC of 0.9 is possible. However, such chokes tend to be very large and heavy, reducing the power density. A full-wave rectifier without a large filter capacitor shown in Figure 3.41 has a sinusoidal line current, but its output voltage is not constant. This fact can be used for designing PFCs.

Figure 3.41 Full-wave rectifier without filter capacitor.

3.8.2 Boost Power Factor Corrector The circuit of a single-phase boost power factor corrector is depicted in Figure 3.42. It consists of a front-end rectifier and a boost PWM dc–dc converter. The rectifier does not contain a large filter capacitor to reduce the line-frequency voltage ripple. It usually contains a small filter capacitor at the output to reduced a switching-frequency current component generated by the boost converter. Current and voltage waveforms in the boost power factor corrector are shown in Figure 3.44. The rectifier output voltage |vs| is a full-wave rectified sinusoid. The minimum value of the peak rectified voltage for the low US utility line is

V and the maximum value of the peak rectified voltage for the high European utility line is V. The time-dependent rectified voltage |vs| is converted into a dc voltage VO. A control circuit forces the inductor current iL of the boost converter to follow a full-wave rectified sinusoidal reference voltage |vs|. Since the boost converter is a step-up converter, the output voltage VO must be higher than the maximum value of the voltage |vs|, that is, VO > 373 V. Various dc voltages are derived from the dc voltage VO, using dc–dc converters. Figure 3.44 shows a complete ac-to-dc converter. It consists of an EMI filter, full-wave rectifier, and a boost power-factor corrector.

Figure 3.42 Boost power factor corrector.

Figure 3.43 Boost power factor corrector.

Figure 3.44 Waveforms in the boost power factor corrector for a cycle of the line frequency. (a) Waveforms of the rectified line voltage |vs|, output voltage VO, and inductor current iL. (b) Waveform of the line voltage vs and line current is. The line voltage is sinusoidal and is given by (3.249) The voltage at the output of the front-end full-wave rectifier is (3.250) The voltage transfer function is (3.251) resulting in the duty cycle

(3.252) Figure 3.45 shows the waveforms of the duty cycle D(t) in the boost power factor corrector at VO = 400 V for a half of a cycle of the line frequency at Vrms = 90 V and Vrms = 264 V. The maximum value of the duty cycle is 1 and occurs at ωt = 0, π, and 2π. The minimum value of the duty cycle is Dmin = 1 − Vsm/VO and occurs at ωt = π/2 and 3π/2. For Vrms = 90 V, and for Vrms = 264 V,

.

Figure 3.45 Waveforms of the duty cycle D(t) in the boost power factor corrector at VO = 400 V for a half of a cycle of the line frequency at Vrms = 90 V and Vrms = 264 V. The inductor current is shaped to have a full-wave rectified waveform (3.253) The input current of the rectifier is

(3.254) Thus, the boost converter represents a resistive load to the utility line, yielding THD = 0 and FDF = 1. The line current is in phase with the line voltage, yielding FDA = cos ϕ1 = 1. Thus, PF = 1. The diode current waveform is (3.255) Since (3.256) we obtain (3.257) The dc component of the diode current ID flows through the load and nearly all of the second harmonic of the diode current id flows through the output filter capacitor C. The ac component of the voltage across the filter capacitor is (3.258)

where amplitude of the second harmonic of the output voltage is (3.259) Hence, the filter capacitance is (3.260) where the maximum power drawn from the line is (3.261)

3.8.3 Electronic Ballasts for Fluorescent Lamps Figure 3.46 shows an application of the boost active power factor corrector in an electronic ballast for fluorescent lamps [16]. The dc output voltage of the boost PFC supplies a Class-D

half-bridge dc-to-ac high-frequency resonant inverter. When the voltage at the input of the front-end rectifier is turned-on, the plasma in the fluorescent lamp OFF, the lamp resistance is infinity, and the voltage across the lamp increases until the plasma is ignited. Then the lamp resistance decreases and the voltage across the lamp also decreases. The lamp remains ON until the switch of the utility voltage is turned-off, producing a healthy light, free of flickering. This instant-start ballast. The efficiency of fluorescent lamps is about 5–6 times higher than that of the incandescent lamps. Active power factor correctors are widely used in power supplies.

Figure 3.46 Electronic ballast with boost active power factor corrector for fluorescent lamps [16].

3.9 Summary The boost converter is a step-up circuit. It has only a transformerless version. It can be operated either in CCM or DCM. Its advantage is that the input current has a continuous (nonpulsating) waveform. It is easy to drive the MOSFET in the boost converter because the gate is referenced to ground. If losses are neglected, the dc voltage transfer function for CCM is MVDC = VO/VI = 1/(1 − D). It increases from 1 to ∞ as D is increased from 0 to 1. The dc voltage transfer function of the lossy converter is lower than that of the lossless converter at the same duty cycle D. The difference is especially significant at the duty cycle D close to 1. As D is increased from 0 to 1, the dc voltage transfer function of the lossy boost converter initially increases, reaches its maximum value, and then decreases back to 0. The converter should not be used at D close to 1 because of its poor efficiency.

The peak-to-peak current through the filter capacitor is very high; it is equal to the peak-topeak value of the diode current IDM. It is easy to drive the MOSFET because the gate is referenced to ground. The dc voltage transfer function MVDC depends on the inductance L for DCM, and it is independent of L for CCM. For the boost converter operating in CCM, the maximum efficiency occurs at full load IOmax (or RLmin) and at the maximum dc input voltage VImmax. For the boost converter operating in CCM, the minimum efficiency occurs at full load IOmax (or RLmin) and at the minimum dc input voltage VImin.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. 3. K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. 4. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984. 5. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York, NY: Van Nostrand, 1985. 6. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 7. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Upper Saddle River, NJ: Prentice Hall, 2004. 8. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 9. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 10. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. 11. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 12. B. M. Bird, K. G. King, and D. A. G. Pedder, An Introduction to Power Electronics. New York: John Wiley & Sons, 1993.

13. R. D. Middlebrook, “A continuous model for tapped-inductor boost converter,” Proceedings of the IEEE Power Electronics Specialists Conference, Culver City, CA, June 9–11, 1975, pp. 63–79. 14. S. Ćuk and R. D. Middlebrook, “Coupled-inductor and other extensions of a new optimum topology switching dc-dc converter,” IEEE IAS Conference, 1977, pp. 1110–1126. 15. B. W. Dishner, “Boost/buck dc/dc converter,” US Patent 4,801,859, January 31, 1989. 16. M. K. Kazimierczuk and W. Szaraniec, “Electronic ballast for fluorescent lamps,” IEEE Transactions on Power Electronics, vol. 8, pp. 386–395, October 1993. 17. D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. 18. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 19. I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. 20. A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. 21. D. A. Grant and Y. Darroman, “Inverse Watkins-Johnson converter − analysis reveals its merits,” Electronics Letters, vol. 39, no. 18, pp. 1342–1343, September 4, 2003.

Review Questions 1. What is the range of the dc voltage transfer function for the lossless and lossy boost PWM converter? 2. How does the efficiency of the boost converter depend on the duty cycle? 3. Is it easy to obtain a low ripple voltage in the boost PWM converter? 4. Is the current flowing into the filter capacitor and the load continuous in the boost PWM converter? 5. Is the input current of the boost PWM converter pulsating? 6. Are both halves of the B–H curve of the inductor core used in the boost PWM converter? 7. Is the corner frequency fo dependent on the load resistance RL in the boost converter? 8. Is the efficiency high at heavy or light loads for the boost converter? 9. Does the maximum power loss in each component of the boost converter occur at the minimum or the maximum duty cycle? 10. What is the complex power?

11. What is the apparent power? 12. What is the power factor? 13. What is the total harmonic distortion? 14. Draw the circuit of the boost power factor corrector and explain its principle of operation.

Problems 1. Derive an expression for the dc voltage transfer function MVDC of a lossless boost converter using the steady-state condition for the inductor current. 2. A boost PWM converter has the following data: VI = 125–350 V, VO = 380 V, PO = 6.8–68 W, and fs = 50 kHz. Compute the voltage and current stresses of the transistor and the diode. 3. A boost PWM converter has the following data: VI = 8–16 V, VO = 24 V, IO = 0.2–2 A, and fs = 200 kHz. Calculate the minimum inductance required for the converter operation in CCM. Assume η = 90%. 4. A boost PWM converter has the following data: VI = 8–12 V, VO = 24 V, IO = 0.2–2 A, and fs = 200 kHz. Calculate the minimum inductance required for the converter operation in CCM. Assume η = 90%. 5. A boost PWM converter is operated in CCM at VI = 14 V and VO = 28 V. Find the required duty cycle D for the converter efficiency (a) η = 100% and (b) η = 80%. 6. A boost PWM converter employs a power MOSFET with an on-resistance rDS = 0.02 Ω. The load current is IO = 10 A. Calculate the transistor conduction loss at D = 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9. 7. A boost PWM converter employs a diode with a forward resistance RF = 0.02 Ω. The load current is IO = 10 A. Calculate the diode conduction loss due to the forward resistance RF at D = 0.1, 0.2, 0.5, 0.8, and 0.9. 8. A boost PWM converter employs an inductor with a dc resistance rL = 0.02 Ω. The load current is IO = 10 A. Calculate the inductor loss at D = 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9. 9. For the boost converter with VI = 8–16 V, VO = 24 V, IO = 0.2–2 A, and fs = 200 kHz, find the maximum inductance required to maintain the converter in DCM. 10. Design a boost PWM converter with the following specifications: VImin =

V, VImax =

V, VO = 400 V, IO = 0.2–2 A, Vr/VO ≤ 1%, rL = 2.5 Ω, rDS = 1 Ω, Co = 100 pF, RF = 25 m Ω, VF = 0.7 V, rC = 50 m Ω, and fs = 50 kHz. Find L, C, and η.

11. Design a boost PWM converter to meet the following specifications: VImin = 25 V, VInom = 28 V, VImax = 31 V, VO = 270 V, RLmin = 462 Ω, RLmax = 518 Ω, fs = 25 kHz, Vr/VO ≤ 1%, VF = 1.5 V, RF = 0.188 Ω, rDS = 0.3 Ω, Co = 400 pF, rL = 0.21 Ω, and rC = 0.1 Ω. Find L, C, ISM, VSM, and η. 12. Design a boost converter to meet the following specifications: VI = 24±4 V, VO = 48 V, IO = 0.2 to 2 A, Vr/VO ≤ 1%, fs = 100 kHz, rDS = 0.2 Ω, rL(dc) = 0.25 Ω, RF = rC = 25 m Ω, VF = 0.8 V, and Co = 250 pF. Find L, C, ISM, VSM, and η. 13. Design a boost converter to meet the following specifications: VI = 10–24 V, VO = 28 V, IO = 0.5–1 A, Vr/VO ≤ 1%, fs = 100 kHz, rDS = 0.2 Ω, rL(dc) = 0.11 Ω, rC = 25 m Ω, RF = 25 m Ω, VF = 0.3 V, and Co = 150 pF. Find L, C, ISM, VSM, and η. 14. Design a boost converter to meet the following specifications: VI is the US single-phase rectified utility line, VO = 400 V, IO = 0–0.225 A, Vr/VO ≤ 1%, fs = 100 kHz, rDS = 1 Ω, Co = 150 pF, Qg = 27 nC, rL = 2.1 Ω, rC = 0.25Ω, RF = 17.1 m Ω, and VF = 0.7 V, and Co = 150 pF. Find L, C, ISM, VSM, and η. 15. Design a boost converter for photovoltaic applications to meet the specifications: VI = 1.5 ± 0.5 V, VO = 5 V, IO = 0.2–4 A, Vr/VO ≤ 2%, and fs = 250 kHz.

4 Buck–Boost PWM DC–DC Converter 4.1 Introduction This chapter covers the buck–boost PWM switching-mode converter [1–21]. The circuit of the converter is described. The current and voltage waveforms for various components are derived. The device stresses are found. The dc voltage transfer function is determined. An expression for the minimum inductance is derived from the condition for the boundary between CCM and DCM. A design equation for the filter capacitor is developed from the ripple voltage requirement. Power losses in all devices and the overall efficiency are estimated. Illustrative design examples are given for both CCM and DCM. Finally, the buck–boost converter is derived from the buck and boost converters.

4.2 DC Analysis of PWM Buck–Boost Converter for CCM 4.2.1 Circuit Description The circuit of the PWM buck–boost dc–dc converter [1–21] is shown in Figure 4.1(a). It consists of a power MOSFET used as a controllable switch, an inductor L, a diode, a filter capacitor C, and a load resistor RL. The switch is turned on and off at the switching frequency fs = 1/T with the ON duty ratio D = ton/T, where ton is the time interval when the switch is ON. It is difficult to drive the transistor because source is not connected to ground. Therefore, the driver is floating as neither end is connected to ground.

Figure 4.1 PWM buck–boost converter and its ideal equivalent circuits for CCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. Two modes of operation exist: CCM and DCM. Figures 4.1(b) and (c) show equivalent circuits of the buck–boost converter for CCM when the switch is ON and the diode is OFF, and when the switch is OFF and the diode is ON, respectively. The principle of operation of the buck–boost converter is explained by the idealized waveforms of the currents and voltages shown in Figure 4.2. During the time interval 0 < t ≤ DT, the switch is ON and the diode is OFF as indicated in Figure 4.1(b). The voltage across the diode is − (VI + VO) and maintains the diode in the off-state. The voltage across the inductor is VI and gives rise to a linear increase in the inductor current with a slope of VI/L. During time interval DT < t ≤ T, the switch is OFF and the diode is ON as shown in Figure 4.1(c). The voltage across the inductor is − VO and causes the inductor current to decrease linearly with a slope of − VO/L. The voltage across the switch is VI + VO. At time t = T, the switch is turned on again and the next cycle begins.

Figure 4.2 Idealized current and voltage waveforms for the PWM buck–boost converter for CCM.

4.2.2 Assumptions The analysis of the buck–boost PWM converter of Figure 4.1(a) is based on the following assumptions: 1. The power MOSFET and the diode are ideal switches. 2. The transistor output capacitance and the diode capacitance as well as lead inductances (and thereby switching losses) are zero. 3. Passive components are linear, time invariant, and frequency independent. 4. The output impedance of the input voltage source VI is zero for both dc and ac components.

4.2.3 Time Interval: 0 < t ≤ DT

During the time interval 0 < t ≤ DT, the switch is ON and the diode is OFF. An ideal equivalent circuit for this time interval is shown in Figure 4.1(b). When the switch is ON, the voltage across the diode vD is approximately equal to − (VI + VO), causing the diode to be reverse biased. The voltage across the switch vS and the diode current iD are zero. The voltage across the inductor L is given by (4.1) Hence, one obtains the current through the inductor L and the switch (4.2) where iL(0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes (4.3) and the peak-to-peak value of the ripple current through the inductor L is (4.4) It will be shown shortly that the dc voltage transfer function is MVDC = VO/VI = II/IO = D/(1 − D). Hence, we can find the diode voltage (4.5) The average value of the inductor current IL is equal to the sum of the dc input current II and the dc output current IO. Hence, one arrives at the peak value of the switch current ISM (4.6) An increase of the magnetic energy in the inductor L is (4.7) This time interval is terminated at t = DT when the switch is turned off by an external driver. The inductor current iL is a continuous function of time. Since iL(DT) is nonzero when the switch turns on, the inductor acts as a current source, thus turning the diode on.

4.2.4 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch is OFF and the diode is ON. Figure 4.1(c) shows an ideal equivalent circuit for this time interval. The switch current iS and the diode voltage vD are zero. The voltage across the inductor L is (4.8) Hence, one obtains the current through the inductor L and the diode (4.9)

where iL(DT) is the initial current of the inductor L at t = DT. The peak-to-peak value of the ripple current through the inductor L is (4.10) Since VO/VI = D/(1 − D), the voltage across the switch is given by (4.11) resulting in a maximum value of the peak voltage across the switch and the diode (4.12) The peak diode and switch currents are (4.13) The maximum values of the peak currents are (4.14) Note that the maximum dc input current occurs at Dmax, whereas the maximum peak-to-peak ripple current of the inductor occurs at Dmin. The “off” time interval ends at t = T when the switch is turned on by an external driver. The decrease in the magnetic energy stored in inductor L during interval DT < t ≤ T is

(4.15) For steady-state operation, the increase in the magnetic energy stored in the inductor ΔEL(in) is equal to the decrease in the stored magnetic energy in the inductor ΔEL(out).

4.2.5 DC Voltage Transfer Function for CCM Referring to Figure 4.2 and using a volt-second balance, A+ = A−, we can write (4.16) which can be rearranged to the form (4.17) resulting in the dc voltage transfer function of the lossless converter (4.18) The range of MVDC for the lossless buck–boost converter is (4.19) For the lossless buck–boost converter, MVDC increased from 0 to ∞ as D increased from 0 to 1. It follows from (4.17) that the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI. It will be shown shortly that MVDC is significantly altered by losses, especially when the values of D is close to 1. From (4.18), (4.20) The sensitivity of the output voltage with respect to the duty cycle is (4.21) In practice, VO should be held constant. If VI increases, D should be decreased by a control circuit so that VO remains constant, and vice versa. The dc current transfer function is (4.22) and its value decreases from ∞ to zero as D is increased from 0 to 1. Using (4.11),

(4.23) and using (4.22), (4.24) Thus, the switch and the diode utilization in the buck–boost converter is characterized by the output-power capability (4.25) As D is increased from 0 to 1, cp increases from 0, reaches a maximum equal to 0.25 at D = 0.5, and then decreases back to zero.

4.2.6 Device Stresses for CCM The dc input power is PI = IIVI and the dc output power is PO = IOVO. Neglecting power losses, PO = PI, that is, VOIO = VIII. Hence, (4.26) Therefore, (4.27) The maximum switch and diode peak voltages for steady state in CCM are (4.28) The maximum inductor current ripple is given by (4.29) From (4.26), the dc component of the input current is (4.30) The maximum value of the dc input current occurs at IOmax and VImin, that is, at MVDCmax and Dmax. Hence,

(4.31) The average inductor current IL is equal to the sum of the average switch current IS and the average diode current ID. In turn, the average switch current IS is equal to the average input current II and the average diode current ID is equal to the average output current IO. Thus, (4.32) Hence, the maximum switch and diode peak currents for steady state in CCM are (4.33) Note that ΔiL = ΔiLmin when II = IImax.

4.2.7 Boundary Between CCM and DCM Figure 4.3 depicts the inductor current waveform at the boundary between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM). This waveform can be described by (4.34) From (4.18), VI = VO(1 − D)/D. Therefore, (4.35) The dc inductor current at the boundary between CCM and DCM is (4.36) From (4.32), (4.37) which results in the dc output current at the boundary (4.38) The load resistance at the boundary is

(4.39) Hence, the minimum value of the inductance L is found as (4.40) Figures 4.4 and 4.5 show the normalized load current IOB/(VO/2fsL) = (1 − D)2 and load resistance RLB/(2fsL) = 1/(1 − D)2 as functions of D at the boundary between CCM and DCM.

Figure 4.3 Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax.

Figure 4.4 Normalized load current IOB/(VO/2fsL) as a function of D at the boundary between CCM and DCM for buck–boost converter.

Figure 4.5 Normalized load resistance RLB/(2fsL) as a function of D at the boundary between CCM and DCM for buck–boost converter.

4.2.8 Ripple Voltage in Buck–Boost Converter for CCM The output part of the buck–boost converter is shown in Figure 4.6, where the filter capacitor is modeled by its capacitance C and its ESR denoted by rC. Figure 4.7 displays current and voltage waveforms for the converter output circuit. The dc component of the inductor current equals the dc load current IO. The ac component of the inductor current flows through the capacitor C and the load resistance RL. In most practical applications, the current through the capacitor is approximately equal to the ac component of the inductor current.

Figure 4.6 Output circuit of the buck–boost converter for deriving the output voltage ripple.

Figure 4.7 Waveforms associated with the ripple voltage for the PWM buck–boost converter for CCM. The peak-to-peak value of the capacitor current may be written as (4.41) resulting in the peak-to-peak value of the voltage across rC (4.42) The peak-to-peak value of the output ripple voltage Vr is usually given. Hence, the maximum peak-to-peak value of the ac component of the voltage across the capacitance C is found as (4.43)

On the other hand, this voltage is approximately given by (4.44) where ΔQmax is the maximum decrease in charge during the time interval from zero to DT. Rearrangement of (4.44) gives (4.45)

4.2.9 Power Losses and Efficiency of the Buck–Boost Converter for CCM An equivalent circuit of the buck–boost converter with parasitic resistances is shown in Figure 4.8. In this figure, rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be evaluated assuming that the inductor current iL is ripple free and equals the dc current II + IO. Hence, the switch current can be approximated by (4.46) resulting in its rms value (4.47) and the MOSFET conduction loss (4.48) Assuming that the transistor output capacitance Co is linear, the switching loss is expressed as (4.49)

Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power)

(4.50)

Similarly, the diode current may be approximated by (4.51) which yields its rms value (4.52)

and the power loss in RF (4.53) The average value of the diode current is (4.54) which gives the power loss associated with the voltage VF (4.55) Thus, the overall diode conduction loss is (4.56) The inductor current is (4.57) leading to its rms value (4.58) and the inductor conduction loss

(4.59) The current through the filter capacitor is (4.60) and the rms current through the filter capacitor is found as (4.61) and the power loss in the filter capacitor (4.62) The overall power loss is given by (4.63)

Thus, the converter efficiency is (4.64)

Figure 4.9 shows the efficiency of the buck–boost converter η as a function of the duty cycle D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. At the duty cycle D close to zero, the conduction losses are low, but the switching loss is high because VI is high at a fixed value of VO. Hence, the efficiency decreases to zero. At the duty cycle D close to 1, the conduction losses are high, reducing the efficiency to zero. Therefore, the operation at very low and high values of D should be avoided.

Figure 4.8 Equivalent circuit of the buck–boost converter with parasitic resistances and the diode offset voltage to determine power losses.

Figure 4.9 Efficiency of the buck–boost converter η versus duty cycle D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF.

4.2.10 DC Voltage Transfer Function of Lossy Buck–Boost Converter for CCM The dc component of the input current is (4.65) where IL = II + IO. Similarly, the dc component of the output current is (4.66)

Hence, one obtains the dc current transfer function of the buck–boost converter (4.67) This equation holds true for both lossless and lossy converter. The converter efficiency can be expressed as (4.68) from which the voltage transfer function of the lossy buck–boost converter is (4.69)

Figure 4.10 portrays MVDC as a function of D at various load resistances for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. It can be seen that MVDC first increases with D, reaches the maximum value, and then decreases to zero. This is because the efficiency is very low at D close to 1. From (4.69), the on-duty cycle is (4.70)

Notice that the duty cycle D at a given dc voltage transfer function is greater for the lossy converter than that for the lossless converter. The switch must be closed for a greater portion of the cycle in the lossy converter to transfer energy equal to the output energy and the losses.

Figure 4.10 The dc voltage transfer function MVDC of the lossy buck–boost converter for VO = 12 V, rDS = 0.11 Ω, VF = 0.7 V, RF = 20 mΩ, rL = 0.05 Ω, rC = 6 mΩ, fs = 100 kHz, and Co = 100 pF. Substitution of (4.70) into (4.64) gives the efficiency of the buck–boost converter (4.71) where (4.72)

and (4.73)

4.2.11 Design of Buck–Boost Converter for CCM Design a PWM buck–boost converter that meets the following specifications: VI = 28 V ± 4 V, VO = 12 V, IO = 1–10 A, and Vr/VO ≤ 1%. Solution: The maximum and minimum values of the output power are (4.74) and (4.75) The minimum and maximum values of the load resistance are (4.76) and (4.77) The minimum, nominal, and maximum values of the dc voltage transfer function are (4.78) (4.79) and (4.80) Assume the converter efficiency η = 85%. The minimum, nominal, and maximum values of the duty cycle are (4.81)

(4.82) and (4.83) Selecting the switching frequency fs = 100 kHz, the minimum inductance is (4.84) Pick L = 30 μH. The peak-to-peak value of the ac component of the inductor current is (4.85) The maximum dc input current occurs at VImin = 24 V, which corresponds to the maximum dc voltage transfer function MVDCmax = 0.5. This current is given by (4.86) The current and voltage stresses of the semiconductor devices are (4.87) and (4.88) Let us select an International Rectifier IRF142 power MOSFET whose VDSS = 100 V, ISM = 24 A, rDS = 0.11 Ω, Qg = 38 nC, and Co = 100 pF. Choose also an MUR2510 ultrafast recovery diode whose IF(AV) = 25 A, VDM = 100 V, VF = 0.7 V, and RF = 20 mΩ. The ripple voltage is (4.89) Assume that Vrcpp = 100 mV. Hence, one obtains the maximum value of the ESR of the filter capacitor (4.90)

The ripple voltage across the filter capacitance is (4.91) and the filter capacitance is (4.92) Pick C = 2.2 mF/25 V/6 mΩ. The power losses and the efficiency will be calculated for full load IOmax = 10 A and minimum dc input voltage VImin = 24 V, corresponding to Dmax = 0.37. The rms value of the inductor current is (4.93) Assuming the dc ESR of the inductor rL = 50 mΩ, one arrives at the loss in the ESR of the inductor (4.94) The switch rms current is (4.95) which gives the MOSFET conduction loss (4.96) The switching loss is (4.97) The total power loss in the MOSFET (without the gate drive power) is (4.98) The rms diode current is (4.99) Thus, the power loss due to RF is

(4.100) and the power loss due to VF is (4.101) resulting in the diode conduction loss (4.102) The rms current of the filter capacitor is (4.103) Hence, the power loss in the ESR of the filter capacitor is (4.104) The total power loss is (4.105) Hence, the converter efficiency is (4.106) Assuming that the peak-to-peak gate-to-source voltage is VGSpp = 14 V, the gate-drive power is (4.107) Using (4.71) through (4.73), the efficiency η of the designed buck–boost converter can be computed for the specified range of VI and IO for CCM. Using the computed efficiency η, the duty cycle D can be calculated from (4.70). The plots of the efficiency η and the duty cycle D versus VI at fixed load resistances RL are depicted in Figures 4.11 and 4.12, respectively. Figures 4.13 and 4.14 show the plots of the efficiency η and the duty cycle D versus the load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V. Plots of the efficiency η and the duty cycle D versus RL at fixed values of VI are shown in Figures 4.15 and 4.16. The efficiency η decreases as IO increases (or RL decreases). The duty cycle D increases as VI decreases and IO increases (or RL decreases).

Figure 4.11 Efficiency η as a function of the dc input voltage VI at fixed load resistances RL for the buck–boost converter in CCM.

Figure 4.12 Duty cycle D as a function of the dc input voltage VI at fixed load resistances RL for the buck–boost converters in CCM.

Figure 4.13 Efficiency η as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM.

Figure 4.14 Duty cycle D as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM.

Figure 4.15 Efficiency η as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in CCM.

Figure 4.16 Duty cycle D as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converters in CCM.

4.3 DC Analysis of PWM Buck–Boost Converter for DCM Equivalent circuits for the PWM buck–boost converter operating in the DCM are depicted in Figure 4.17. Idealized current and voltage waveforms are shown in Figure 4.18. Prior to time t = 0, the inductor current is zero. At time t = 0, the switch is turned on, causing the diode to turn off. The voltage across the inductor is VI and the inductor current increases linearly from zero. At time t = DT, the switch is turned off and the diode turns on. The voltage across the inductor is − VO. Therefore, the inductor current decreases linearly. This current flows through the diode. Once the diode current reaches zero, the diode begins to turn off. Since both the transistor and the diode are OFF, the inductor current is zero until the switch is turned on.

Figure 4.17 PWM buck–boost converter and its ideal equivalent circuits for DCM. (a) Circuit. (b) Equivalent circuit when the switch is ON and the diode is OFF. (c) Equivalent circuit when the switch is OFF and the diode is ON. (d) Equivalent circuit when both the switch and the diode are OFF.

Figure 4.18 Waveforms for the PWM buck–boost converter operating in DCM.

4.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is ON and the diode is OFF. The equivalent circuit is shown in Figure 4.17(b). The switch voltage vS and the diode current iD are zero. The voltage across the inductor L is (4.108) and the inductor and switch current is (4.109) Hence, one obtains the peak switch and inductor current

(4.110) The voltage across the diode is (4.111) This time interval ends when the switch is turned off by the driver.

4.3.2 Time Interval: DT < t ≤ (D + D1)T The equivalent circuit for this time interval is shown in Figure 4.17(c). The switch is OFF and the diode is ON. Hence, iS = 0 and vD = 0. The voltage across the inductor L is (4.112) and, using (4.110), the inductor and diode current is obtained as (4.113)

The peak diode and inductor current is found to be (4.114) The peak voltage across the switch is (4.115) This time interval ends when the diode current reaches zero.

4.3.3 Time Interval: (D + D1)T < t ≤ T During this time interval, both the switch and the diode are OFF. The equivalent circuit is shown in Figure 4.17(d). The inductor current iL, the inductor voltage vL, the switch current iS, and the diode current iD are zero. The voltage across the switch is (4.116) and the voltage across the diode is (4.117) This time interval ends when the switch is turned on by the driver.

4.3.4 Device Stresses of the Buck–Boost Converter in DCM From (4.111) and (4.115), the voltage stress of the transistor and the diode is (4.118) and, from (4.110) and (4.114), the current stress of the transistor and the diode is (4.119)

4.3.5 DC Voltage Transfer Function of the Buck–Boost Converter for DCM Referring to Figure 4.18 and using the volt-second balance principle, (4.120) which leads to (4.121) Using (4.110), the dc output current is found as (4.122) Thus, (4.123) Equating the right-hand sides of (4.121) and (4.123) produces (4.124) Substitution of this into (4.121) yields the dc voltage transfer function of the buck–boost converter for DCM (4.125) It follows from this equation that MVDC depends on D, RL, L, and fs. From (4.125),

(4.126) At the boundary between the DCM and CCM modes, (4.127) Hence, from (4.126), one obtains the boundary duty cycle (4.128) Figures 4.19 and 4.20 show plots of the duty cycle D versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of MVDC for both CCM and DCM.

Figure 4.19 Duty cycle D as a function of the normalized load current IO/(VO/2fsL) at fixed values of MVDC for the lossless buck–boost converter.

Figure 4.20 Duty cycle D as a function of the normalized load resistance RL/(2fsL) at fixed values of MVDC for the lossless buck–boost converter. Substitution of (4.126) into (4.128) produces the dc voltage transfer function of the buck–boost converter at the boundary (4.129) Plots of MVDC as a function of normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at fixed values of D are depicted in Figures 4.21 and 4.22, respectively.

Figure 4.21 DC voltage transfer function MVDC versus normalized load current IO/(VO/2fsL) at fixed values of duty cycle D for the lossless buck–boost converter.

Figure 4.22 DC voltage transfer function MVDC versus normalized load resistance RL/(2fsL) at fixed values of duty cycle D for the lossless buck–boost converter.

4.3.6 Maximum Inductance for DCM Referring to Figure 4.2, the minimum value of the inductor peak current at the boundary between DCM and CCM is (4.130) The dc inductor current at the boundary between CCM and DCM is (4.131) Using (4.22),

(4.132) from which the dc output current at the boundary is obtained (4.133) The load resistance at the boundary is (4.134) Therefore, the maximum inductance L required for operation in DCM is (4.135)

4.3.7 Power Losses and Efficiency of the Buck–Boost Converter in DCM Using (4.125), the peak inductor, switch, and diode current is (4.136) The rms value of the switch current is (4.137) Therefore, the MOSFET conduction loss is (4.138) From (4.115) and (4.125), the switching loss is (4.139)

The rms value of the diode current is

(4.140)

Hence, the power loss in the diode associated with RF is (4.141) The average diode current is ID = IO, resulting in the diode loss associated with VF (4.142) Thus the overall diode conduction loss is (4.143) Using (4.124) and (4.126), the rms value of the current through the inductor L is (4.144)

The power loss in the inductor ESR is therefore given by (4.145)

The total power loss in the converter is (4.146)

This leads to the efficiency of the buck–boost converter in DCM (4.147)

The dc input current is (4.148) yielding the dc input power (4.149) The dc output power is (4.150) The dc input power, dc output power, and the efficiency are related by (4.151) producing (4.152) Hence, the dc voltage transfer function of lossy converter is

(4.153)

Thus, (4.154)

4.3.8 Design of Buck–Boost Converter for DCM Design a PWM buck–boost converter that meets the following specifications: VI = 28 V ± 4 V, VO = 12 V, IO = 0–10 A, and Vr/VO ≤ 1%. Solution: The maximum and minimum values of the output power are (4.155) and (4.156) The minimum and maximum values of the load resistance are (4.157) and (4.158) The minimum, nominal, and maximum values of the dc voltage transfer function are (4.159) (4.160)

and (4.161) Assume the converter efficiency η = 85%. The minimum, nominal, and maximum values of the duty cycle are (4.162) (4.163) and (4.164) Assuming the switching frequency fs = 100 kHz, the maximum inductance required for DCM operation is (4.165) Pick L = 2.2 μH. At full load RL = RLmin, (4.166)

(4.167)

(4.168) and (4.169) Hence,

(4.170) The current and voltage stresses of the semiconductor devices are (4.171) and (4.172) Select an International Rectifier IRF142 power MOSFET whose VDSS = 100 V, ISM = 24 A, rDS = 0.11 Ω, Qg = 38 nC, and Co = 100 pF. Also, select an MUR2510 ultrafast recovery diode whose IF(AV) = 25 A, VDM = 100 V, VF = 0.7 V, and RF = 20 mΩ. The ripple voltage is (4.173) Assume that Vrcpp = 100 mV. Hence, one obtains the maximum value of the ESR of the filter capacitor (4.174) The ripple voltage across the filter capacitance is (4.175) and the filter capacitance is (4.176) Pick C = 1.8 mF/25 V/2.5 mΩ. Power losses and efficiency will be calculated at full power and VImin = 24 V at which D = Dmax = 0.328. The maximum conduction power loss in the MOSFET occurs at full load RLmin = 1.2 Ω and Dmax = 0.328 and is given by (4.177) The transistor output capacitance is Co = 100 pF. The switching loss occurs at VImin = 24 V and is given by (4.178)

The power loss in the MOSFET is (4.179) The diode conduction power loss due to RF is (4.180) and the diode conduction power loss due to VF is (4.181) Hence, the total diode conduction power loss is (4.182) Assuming the ESR of the inductor rL = 10 mΩ, the power loss in the inductor winding is (4.183)

Neglecting the power loss in the filter capacitor, the total power loss in the converter is (4.184) The converter efficiency is (4.185) Assuming that the peak-to-peak gate-to-source voltage is VGSpp = 14 V, the gate-drive power is (4.186) The converter efficiency η can be computed from (4.147) and the duty cycle D from (4.154). The plots of the efficiency η versus VI at fixed load resistances are depicted in Figure 4.23. Figure 4.24 shows the plot of D as VI increases from 24 to 32 V for the buck–boost converter in CCM given in the design example. Figure 4.25 shows the plots of the efficiency η versus the load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V. Figure 4.26 depicts plots of the duty cycle D as a function of the dc load current IO for DCM at VImin = 24 V, VInom = 28 V, and VImax = 32 V. Plots of the efficiency η versus RL at fixed values of VI are shown in Figure 4.27. Figure 4.28

exhibits the plots of the duty cycle D as a function of the load resistance RL for DCM at VImin = 24 V, VInom = 28 V, and VImax = 32 V.

Figure 4.23 Efficiency η as a function of the dc input voltage VI at fixed load resistances for the buck–boost converter in DCM.

Figure 4.24 Duty cycle D as a function of the dc input voltage VI at various load resistances for the buck–boost converter in DCM.

Figure 4.25 Efficiency η as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM.

Figure 4.26 Duty cycle D as a function of the dc load current IO at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM.

Figure 4.27 Efficiency η as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM.

Figure 4.28 Duty cycle D as a function of the load resistance RL at VImin = 24 V, VInom = 28 V, and VImax = 32 V for the buck–boost converter in DCM.

4.4 Bidirectional Buck–Boost Converter A bidirectional buck–boost converter is shown in Figure 4.29. It is derived from a conventional unidirectional buck–boost converter of Figure 4.1(a) by replacing a diode with a MOSFET. If a dc voltage source is connected in parallel with the capacitor C1 and a load is connected in parallel with the capacitor C2, the energy flows from left to right. On the other hand, if a dc voltage source is connected in parallel with the capacitor C2 and a load is connected in parallel with the capacitor C1, the energy flows from right to left.

Figure 4.29 Bidirectional buck–boost converter.

4.5 Synthesis of Buck–Boost Converter The buck–boost converter can be derived from the buck and boost converters [15]. The dc-todc voltage transfer function of the buck–boost converter for CCM can be represented as follows: (4.187) Hence, a block diagram of the buck–boost converter can be presented, as shown in Figure 4.30, where VO < 0. It consists of a converter with the dc-to-dc voltage transfer function equal to D such as the buck converter, an inverting unity-gain block with a voltage transfer function equal to − 1, and a converter with the dc-to-dc voltage transfer function equal to 1/(1 − D) such as the boost converter.

Figure 4.30 Block diagram of the buck–boost converter. Due the presence of the inverting unity-gain block, the polarity of the boost converter input voltage should be opposite to that of the buck converter output voltage. Figure 4.31 shows the transformation of the boost converter from the circuit accepting a positive input voltage to the circuit accepting a negative input voltage. A conventional boost converter with a positive input

voltage is depicted in Figure 4.31(a). In Figure 4.31(b), the inductor and the diode are moved to the common rail. In Figure 4.31(c), the converter is flipped over to obtain a circuit that accepts a negative input voltage.

Figure 4.31 Transformation of the boost converter. (a) Boost converter with a positive input voltage. (b) Boost converter with inductor and diode moved to the bottom common rail. (c) Boost converter with a negative input voltage. Figure 4.32(a) shows the buck and modified boost converters connected by the unity-gain inverter, where the transistors in both the converters are synchronized to the same switching frequency fs and have the same duty cycle D. The inductors in the buck and boost converters ideally act as current sources and the dc current through the filter capacitor of the buck converter is zero for steady-state operation. Therefore, the filter capacitor can be removed from the circuit and the two inductors can be combined into one inductor, as shown in Figure 4.32(b). A simplified circuit is depicted in Figure 4.32(c). It can be seen that the current in the conductor is zero and therefore this conductor can be removed from the circuit. When both transistors are OFF and both diodes are ON, the conductor is connected to an open circuit

between the two transistors and conducts zero current. When both transistors are ON and both diodes are OFF, the conductor is connected to an open circuit between points B and and conducts no current. Therefore, this conductor can be removed from the circuit, as shown in Figure 4.32(d). Finally, the redundant components S2 and D1 can be removed to obtain the inverting buck–boost converter, as depicted in Figure 4.32(e).

Figure 4.32 Derivation of the buck–boost converter. (a) Buck and modified boost converters connected by a unity-gain inverter. (b) Filter capacitor is removed from the circuit and two inductors are combined into one inductor. (c) Simplified circuit. (d) Conductor is removed. (e) Redundant components S2 and D1 are removed.

4.6 Synthesis of Boost–Buck (Ćuk) Converter A derivation of the boost–buck converter [16], known as the Ćuk converter, is shown in Figure 4.33. The dc-to-dc voltage transfer function of the boost–buck converter for CCM can be written as

(4.188) This equation represents the product of the dc voltage transfer functions of boost converter, inverting unity-gain stage, and buck converter with negative input voltage, as shown in Figure 4.33(a). The circuit is redrawn in Figure 4.33(b) and it reveals a redundant MOSFET and a redundant diode. Removing the redundant components, we obtain the boost–buck (Ćuk) converter, shown in Figure 4.33(c). If we replace the horizontal capacitor by a series combination of two capacitors, a transformer can be inserted between the two capacitors and ground to obtain an isolated Ćuk converter.

Figure 4.33 Derivation of the Ćuk (boost–buck) converter. (a) Cascaded boost converter, inverting unity-gain stage, and buck converter with negative input voltage. (b) Simplified circuit to reveal redundant components. (c) Ćuk (boost–buck) converter.

4.7 Noninverting Buck–Boost Converters

4.7.1 Cascaded Noninverting Buck–Boost Converters There is a great demand for a noninverting step-down/step-up dc–dc converter, especially for battery powered portable electronics applications. For example, the voltage of the lithium-ion battery changes from 4.2 to 2.8 V and the supply voltage of an electronic circuit is 3.3 V. A noninverting step-down/step-up converter can be obtained by cascading the buck and boost converters. The output filter capacitor of the buck converter can be removed and the buck output filter inductor and the boost input filter inductor can be combined to obtain a noninverting buck–boost converter shown in Figure 4.34(a). A noninverting boost–buck converter is shown in Figure 4.34(b). A noninverting synchronous boost–buck converter is shown in Figure 4.35.

Figure 4.34 Noninverting cascaded buck–boost and boost–buck converters. (a) Noninverting buck–boost converter. (b) Noninverting boost–buck converter.

Figure 4.35 Noninverting cascaded synchronous CMOS boost–buck converter.

4.7.2 Four-Transistor Noninverting Buck–Boost Converters A four-transistor CMOS noninverting buck–boost converter [18] is shown in Figure 4.36(a). It consists of four switches, an inductor L, and a filter capacitor C. Each pair of the transistors is a CMOS inverter that consists of an NMOS and a PMOS. Synchronous rectification is employed to increase efficiency. This is a reconfigurable converter topology. If the transistor Q3 is ON and the transistor Q4 is OFF, a synchronous buck converter is obtained, as shown in Figure 4.36(b). The transistors Q1 and Q2 are used to control the duty cycle. If the transistor Q1 is ON and the transistor Q2 is OFF, a synchronous boost converter is obtained, as shown in Figure 4.36(c). The transistors Q3 and Q4 are used to control the duty cycle. The input voltage VI is compared to a reference voltage to reconfigure the converter structure to the buck or boost converter. The smooth transition between the two converters may create a problem because it is difficult to achieve the duty cycle close to 0 in the boost converter and the duty cycle close to 1 in the buck converter for VI ≈ VO. A four-transistor noninverting buck–boost converter with four NMOS transistors is shown in Figure 4.37.

Figure 4.36 Four-transistor CMOS noninverting buck–boost converter. (a) Circuit. (b) Buck converter. (c) Boost converter.

Figure 4.37 Four-transistor noninverting buck–boost converter with nMOS transistors. (a) Circuit. (b) Buck converter. (c) Boost converter. The four-transistor noninverting buck–boost converter shown in Figure 4.38(a) can be operated in such a way that all transistors are switched in every cycle. When transistors Q1 and Q4 are ON and transistors Q2 and Q3 are OFF in every cycle, the inductor L is charged as shown Figure 4.38(b). When transistors Q2 and Q3 are ON and transistors Q1 and Q4 are OFF in every cycle, the inductor L is discharged into the capacitor C and the load resistor RL as shown in Figure 4.38(c). The efficiency of the converter in this mode of operation is reduced because all four switches turn on and off every cycle, increasing switching losses. Figure 4.39 shows a circuit of a switching inductor buck–boost PWM converter. The dc voltage transfer function of this circuit is (4.189)

Figure 4.38 Four-transistor noninverting buck–boost converter. (a) Circuit. (b) For time interval when the inductor is charged. (c) For time interval when the inductor is discharged.

Figure 4.39 Switching-inductor inverting buck–boost converter.

4.8 Tapped-Inductor Buck–Boost Converters 4.8.1 Tapped-Inductor Common-Diode Buck–Boost Converter Tapped-inductor buck–boost converters are shown in Figure 4.40. The turns ratio of the tapped inductor is defined as (4.190)

Figure 4.40 Tapped-inductor buck–boost converters. (a) Tapped-inductor common-diode buck–boost converter. (b) Tapped-inductor common-tansistor buck–boost converter. (c) Tapped-inductor common-load buck–boost converter. The tapped-inductor common-diode buck–boost converter is shown in Figure 4.40(a). When the MOSFET is ON, (4.191) When the MOSFET is OFF, (4.192) Hence, (4.193) Thus, the dc voltage transfer function for CCM for the tapped-inductor common-diode buck–

boost converter is (4.194) Figure 4.41 shows MVDC as a function of D for the tapped-inductor common-diode converter operating in CCM.

Figure 4.41 DC voltage transfer function of tapped-inductor common-diode buck–boost converter for CCM.

4.8.2 Tapped-Inductor Common-Transistor Buck–Boost Converter The tapped-inductor common-transistor buck–boost converter is shown in Figure 4.40(b). When the MOSFET is ON, (4.195)

When the MOSFET is OFF, (4.196) Hence, (4.197) The dc voltage transfer function of the tapped-inductor common-transistor buck–boost converter for CCM is (4.198) This transfer function is identical to the dc voltage transfer function of the flyback converter. Figure 4.42 shows plots of MVDC as a function of D for the tapped-inductor common-transistor converter operating in CCM.

Figure 4.42 DC voltage transfer function of tapped-inductor common-transistor buck–boost converter for CCM.

4.8.3 Tapped-Inductor Common-Load Buck–Boost Converter The tapped-inductor common-load buck-boost converter is shown in Figure 4.40(b). When the MOSFET is ON, (4.199) When the MOSFET is OFF, (4.200) Hence, (4.201)

The dc voltage transfer function of the tapped-inductor common-load buck–boost converter for CCM is (4.202) Figure 4.43 shows plots of MVDC as a function of D for the tapped-inductor common-load buck–boost converter operating in CCM.

Figure 4.43 DC voltage transfer function of tapped-inductor common-load buck–boost converter for CCM.

4.8.4 Tapped-Inductor Common-Source Buck–Boost Converter A tapped-inductor common-source buck–boost converter is shown in Figure 4.44 [21]. When the switch is ON, (4.203)

When the switch is OFF, (4.204) which gives (4.205) Hence, (4.206) The dc voltage transfer function of the tapped-inductor common-source buck–boost converter operating in for CCM is given by (4.207) Figure 4.45 shows plots of the dc voltage transfer function MVDC of tapped-inductor commonsource buck–boost converter for CCM.

Figure 4.44 Tapped-inductor common-source buck–boost converter.

Figure 4.45 DC voltage transfer function of tapped-inductor common-source buck–boost converter for CCM. A noninverting flyback converter with two transformer terminals connected together also belongs to the inductor-tapped buck-boost converter family.

4.9 Summary The buck–boost converter can be derived from the buck and boost converters. The buck–boost converter can be used either as a step-down or a step-up converter. It is an inverting converter. The inductor in the buck–boost converter can be replaced by a transformer, resulting in a flyback converter. For the lossless buck–boost converter, the dc voltage transfer function is MVDC = D/(1 − D) for CCM.

For the lossy buck–boost converter, the dc voltage transfer has lower values than those for the lossless converter, especially when the duty cycle D is close to 1. For this reason, the maximum value of the dc voltage transfer function is limited. The converter should not be used at D close to 1 because its efficiency is poor for D > 0.85. Therefore, D is usually below 85%. The peak-to-peak value of the current through the filter capacitor is very high, equal to the diode peak current IDM. The input current is pulsating. It is relatively difficult to drive the transistor in the buck–boost converter because both the source and the gate of the transistor are connected to “hot” points. Therefore, the driver is floating because neither end is connected to ground. Usually, a transformer or optical coupling is required. The inductance L for DCM is much lower than that for CCM. In DCM, D1 is independent of D. The MOSFET and diode peak current for DCM is higher than that for CCM, approximately by a factor of 2. In DCM, the diode power loss is independent of the duty cycle, that is, VI.

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9. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 10. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. 11. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 12. B. M. Bird, K. G. King, and D. A. G. Pedder, An Introduction to Power Electronics. New York: John Wiley & Sons, 1993. 13. D. W. Hart, Introduction to Power Electronics. Upper Saddle River, NJ: Prentice Hall, 1997. 14. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 15. B. Bryant and M. K. Kazimierczuk, “Derivation of PWM dc-dc buck-boost converter topology,” IEEE International Symposium on Circuits and Systems, Scottsdale, AZ, May 26–29, 2002, Paper V-841, pp. 443–446. 16. B. Bryant and M. K. Kazimierczuk, “Derivation of the Ćuk PWM dc-dc converter circuit topology,” IEEE International Symposium on Circuits and Systems, Bangkok, Thailand, May 25–28, 2003, Vol. III, pp. 841–844. 17. I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. 18. M. Gaboriault and A. Notman, “A high efficiency, noninverting buck-boost dc-dc converter,” IEEE Applied Power Electronics Conference, 2004, vol. 3, pp. 1411–1415. 19. A. Aminian and M. K. Kazimierczuk, Electronic Devices: A Design Approach. Upper Saddle River, NJ: Prentice Hall, 2004. 20. M. Asano, D. Abe, and H. Koizumi, “A common grounded Z-source buck-boost converter,” IEEE International Symposium on Circuits and Systems, 2011, pp. 490–493. 21. D. A. Grant and Y. Darroman, “Extending the tapped-inductor dc-to-dc converter family,” Electronic Letters, vol. 37, no. 3, pp. 145–146, 2001.

Review Questions 1. What is the range of the dc voltage transfer function for the lossless and lossy buck–boost converter? 2. How does the efficiency of the buck–boost converter change with the duty cycle? 3. Is it difficult to drive the transistor in the buck–boost converter?

4. Is the input current of the buck–boost converter pulsating? 5. Is the current through the filter capacitor continuous in the buck–boost converter? What is the peak-to-peak value of the capacitor current? 6. Is only one-half of the B–H curve of the inductor core utilized in the buck–boost converter? 7. Is the buck–boost converter an attractive type of converter? If so, explain why. 8. Is the corner frequency of the output filter dependent on the load resistance in the buck– boost converter? 9. Explain why the obtained circuit cannot function as a dc–dc converter, when the polarity of the diode is reversed in the buck–boost converter.

Problems 1. A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 1–2 A, η = 100%, and fs = 50 kHz. Find the minimum inductance required for CCM operation. 2. A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 1–2 A, η = 85%, and fs = 50 kHz. Find the minimum inductance required for CCM operation. 3. A buck–boost PWM converter (given in Problem 4.1) has VI = 127–187 V, VO = 48 V, IO = 1–2 A, L = 420 μH, and fs = 50 kHz. Find the voltage and current stresses of the transistor and the diode. 4. A buck–boost PWM converter (given in Problem 4.2) has VI = 127–187 V, VO = 48 V, IO = 1–2 A, L = 420 μH, and fs = 50 kHz. Find the filter capacitance and the ESR so that Vr/VO ≤ 1%. 5. A buck–boost PWM converter employs a filter capacitor with an ESR rC = 10 mΩ. The load current is IO = 10 A and the converter operates in CCM. Calculate the power loss in the filter capacitor at D = 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, and 0.9. 6. A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 0–2 A, η = 100%, and fs = 50 kHz. Find the maximum inductance required for DCM operation. 7. A buck–boost PWM converter has VI = 127–187 V, VO = 48 V, IO = 0–2 A, η = 85%, and fs = 50 kHz. Find the maximum inductance required for DCM operation. 8. Derive an expression for the dc voltage transfer function of the lossless and lossy buck– boost PWM converter operated in DCM using the principle of energy conservation. 9. A buck–boost PWM converter has VI = 42–60 V, VO = 28 V, IO = 0.2–2 A, Vr/VO ≤ 1%, rDS = 0.1 Ω, RF = 35 mΩ, VF = 0.7 V, rL = 12 mΩ, Co = 200 pF, and fs = 100 kHz. Find the converter efficiency.

10. A buck–boost converter has VI = 42–60 V, VO = 28 V, IO = 0.2–2 A, rDS = 0.2 Ω, RF = 20 mΩ, VF = 0.7 V, rL = 0.15 Ω, rC = 25 mΩ, Co = 200 pF, Vr/VO ≤ 1%, and fs = 100 kHz. Find L, C, ISM, VSM, and η. 11. Design a buck–boost PWM converter to meet the following specifications: VImin = 42 V, VInom = 48 V, VImax = 60 V, VO = 28 V, IO = 0.2–2 A, Vr/VO ≤ 1.5%, fs = 100 kHz, rL = 0.32 Ω, rC = 33 mΩ, rDS = 0.4 Ω, RF = 20 mΩ, VF = 0.7 V, and Co = 100 pF. 12. In a buck–boost converter, VI = 48 ± 6 V, VO = 12 V, IO = 0.4–4 A, Vr/VO ≤ 1%, and fs = 200 kHz. Find L, C, and rCmax.

5 Flyback PWM DC–DC Converter 5.1 Introduction A PWM flyback dc–dc converter [1–20] is a transformer (or isolated) version of the buck– boost converter. A transformer is used to eliminate any direct (dc) electrical connection between the input and the output of the converter power stage. This safety feature is required in many applications, especially in medical equipment. For example, 1.5 kV dc isolation is typical for worldwide compliance. The safety standard in the United States is regulated by the Underwriters Laboratory (UL) in the United States of America. For most worldwide system applications, power supplies should satisfy the following safety agency standards: UL1950, VDE0805(EN60950, IEC950), and CSA C22.2, No. 950-95. In addition, the transformer allows the converters to achieve much higher or lower values of the dc voltage transfer function than their transformerless counterparts. This transformer is also called coupled inductor. Since the operating frequency of PWM converters is much higher than 50–60 Hz line frequency, the transformer, inductors, and capacitors are much smaller than those operated at line frequencies. The transformer performs several functions in the flyback converter: 1. It provides dc isolation. 2. It stores the magnetic energy. 3. It changes the voltage levels. 4. The output voltages can be either positive or negative. 5. Additional secondary transformer windings and rectifiers may be added to provide more than one output voltage of any polarity. A multiple-output transformer allows one switching-mode power supply to provide all the voltages required by most product designs, for example, 5 V, − 5 V, 12 V, and − 12 V. The flyback converter is used in low-power applications, typically from 20 to 200 W. It has a low parts count. The magnetizing inductance of the transformer is used to store magnetic energy, and therefore, an inductor is not required. However, a large transformer core is needed for higher power levels. An air gap is normally used to avoid core saturation. The voltage stress of the switch is high. The flyback converter is widely used in computers, TV sets, and other electronic equipment.

5.2 Transformers Let us consider an ideal noninverting transformer shown in Figure 5.1(a). In an ideal transformer, both coils share precisely the same magnetic flux ϕ = ϕ21 = ϕ12 and have the

coupling coefficient k = 1. The voltages of the transformer are given by (5.1) and (5.2) where N1 is the number of turns of the primary winding and N2 is the number of turns of the secondary winding. The ratio of the two voltages is (5.3)

where n is the transformer turns ratio.

Figure 5.1 Transformer. (a) Ideal noninverting transformer. (b) Ideal inverting transformer. (c) Model of a transformer consisting of an ideal noninverting transformer and a magnetizing inductance Lm. The instantaneous input power of the transformer is Pi = i1v1 and the instantaneous output power of the transformer is Po = i2v2. Assuming that the efficiency of the transformer η = Po/Pi = 1, one obtains (5.4) from which the ratio of the voltages and currents is given by (5.5) From (5.3) and (5.5), one obtains the relationship among voltages, currents, and turns ratio for the ideal noninverting transformer

(5.6) Figure 5.1(b) shows an ideal inverting transformer. The input voltage is given by (5.1) and the output voltage is (5.7) Equations (5.4) and (5.5) hold true. Therefore, the relationship for the ideal inverting transformer is given by (5.8) Thus, v2 is out of phase by 180° with respect to v1 and i2 is out of phase by 180° with respect to i1. A complete model of an actual transformer contains a number of components such as magnetizing inductance, core resistance, resistances of the windings, leakage inductances, and stray capacitances. A simple transformer model, shown in Figure 5.1(c), is usually used for analysis of PWM converters. It consists of an ideal transformer and a magnetizing inductance Lm. This model reflects the transformer capability to store magnetic energy in Lm and to transform the ac current and voltage levels.

5.3 DC Analysis of PWM Flyback Converter for CCM 5.3.1 Derivation of PWM Flyback Converter Figure 5.2 shows the derivation of the PWM flyback converter. The PWM buck–boost converter is shown in Figure 5.2(a). It is an inverting dc–dc converter. Its disadvantage is that the gate is driven with respect to a “hot” point. The inductor may be replaced by a noninverting transformer in the buck–boost converter, resulting in an inverting flyback PWM converter. The transformer magnetizing inductance Lm can be used to store the magnetic energy. Gapped cores are usually used to obtain a low magnetizing inductance Lm. The converter of Figure 5.2(b) has a gate driven with respect to a “hot” point as the buck–boost converter. This circuit can be redrawn so that the gate is driven with respect to ground, as depicted in Figure 5.2(c), because the switch and the primary of the transformer are connected in series. If the direction of the diode and the filter capacitor (if it is an electrolytic capacitor) is reversed, and the polarity of the transformer is reversed, a noninverting flyback PWM converter is obtained as shown in Figure 5.2(d). To accomplish dc isolation between the input and the output, a control circuit must also have dc isolation. Optocouplers or transformers are used to provide dc isolation in a control circuit. The transformer can have many secondary windings, and therefore a flyback converter can have multiple outputs. Some of them can have positive voltages and others negative voltages, depending upon the polarity of secondary outputs. Figure 5.3 shows a power

supply, which consists of a front-end rectifier and a PWM flyback converter.

Figure 5.2 Derivation of the PWM flyback converter from the PWM buck–boost converter. (a) Buck–boost converter. (b) Flyback inverting converter. (c) Flyback inverting converter with the gate driven with respect to ground. (d) Flyback noninverting converter with the gate driven with respect to ground.

Figure 5.3 Power supply consisting of a rectifier and a PWM flyback converter.

5.3.2 Circuit Description An equivalent circuit of the noninverting PWM flyback dc–dc converter is depicted in Figure 5.4. It consists of a power MOSFET operated as a switch, a transformer, a diode, and a filter capacitor C. The transformer performs two functions: it provides dc isolation and stores the magnetic energy. It is the simplest transformer-isolated converter. The power level for the flyback converter is usually between 20 to 200 W. There are two modes of operation: CCM and DCM. Figures 5.4(a) and (b) show equivalent circuits of the noninverting flyback converter of Figure 5.2(d) for CCM when the switch is ON and the diode is OFF, and when the switch is OFF and the diode is ON, respectively. The transformer is modeled by an ideal transformer and its magnetizing inductance Lm. The principle of operation of the flyback converter is explained by the idealized waveforms of the currents and voltages shown in Figure 5.5. During the time interval 0 < t ≤ DT, the switch is ON and the diode is OFF as indicated in Figure 5.4(a). The voltage across the diode is − (VI/n + VO), which maintains the diode in the off-state. The voltage across the magnetizing inductance Lm is VI and gives rise to a linear increase of the magnetizing inductance current with a slope of VI/Lm. During the time interval DT < t ≤ T, the switch is OFF and the diode is ON as shown in Figure 5.4(b). The voltage across the magnetizing inductance Lm is − nVO, which causes the magnetizing inductance current to decrease linearly with a slope of − nVO/Lm. The voltage across the switch is VI + nVO. At time t = T, the switch is turned on again and the next cycle begins.

Figure 5.4 Equivalent circuits of the noninverting PWM flyback converter for CCM. (a) Equivalent circuit when the switch is ON and the diode is OFF. (b) Equivalent circuit when the switch is OFF and the diode is ON.

5.3.3 Assumptions The analysis of the flyback PWM converter of Figure 5.4(a) is based on the following assumptions: 1. The power MOSFET and the diode are ideal switches. 2. The transistor output capacitance, the diode capacitance, and lead inductances (and thereby switching losses) are zero. 3. The transformer leakage inductances and the stray capacitances are neglected. 4. Passive components are linear, time invariant, and frequency independent. 5. The output impedance of the input voltage source VI is zero for both dc and ac components.

Figure 5.5 Idealized current and voltage waveforms in the PWM inverting flyback converter for CCM.

5.3.4 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch is ON and the diode OFF. An ideal equivalent circuit for this time interval is shown in Figure 5.4(a). When the switch is ON, the voltage across the diode vD is approximately equal to − (VI/n + VO), causing the diode to be reverse biased. The voltage across the switch vS and the diode current are zero. Because (5.9) (5.10) The voltage across the magnetizing inductance Lm is given by

(5.11) Hence, one obtains the current through the magnetizing inductance Lm and the switch (5.12) where iLm(0) is the initial current in the magnetizing inductance Lm at time t = 0. The peak current of the magnetizing inductance is (5.13) and the peak-to-peak value of the ripple current through the magnetizing inductance Lm is (5.14) It will be shown shortly that the dc voltage transfer function of the flyback converter is MVDC = VO/VI = II/IO = D/[n(1 − D)]. Hence, we can find the peak value of the diode reverse voltage (5.15) from which (5.16) The peak value of the switch current ISM is (5.17) which gives (5.18) An increase of the magnetic energy in the magnetizing inductance Lm is (5.19) This time interval is terminated at t = DT when the switch is turned off by an external driver. The current through the magnetizing inductance iLm is a continuous function of time and because

iLm(DT) is nonzero at the switch turn-off, it acts as a current source, thus turning on the diode.

5.3.5 Time Interval: DT < t ≤ T During the time interval DT < t ≤ T, the switch is OFF and the diode is ON. Figure 5.4(b) shows an ideal equivalent circuit for this time interval. The switch current iS and the diode voltage vD are zero. The voltage across the secondary of the transformer is (5.20) resulting in the voltage across the primary of the transformer (5.21) Therefore, the voltage across the magnetizing inductance Lm is (5.22) The current through the magnetizing inductance Lm can be found as (5.23)

where iLm(DT) is the initial current of the magnetizing inductance Lm at t = DT. The peak-topeak value of the ripple current through the magnetizing inductance Lm is (5.24) The current of the primary of the ideal transformer is (5.25) which leads to the secondary and the diode current (5.26) Because VO/VI = D/n(1 − D), the peak voltage across the switch S is given by (5.27) resulting in a maximum value of the peak voltage across the switch

(5.28) The peak diode current is (5.29) which for the worst case becomes (5.30) This time interval ends at t = T when the switch is turned on by a external driver. A decrease of the magnetic energy stored in the magnetizing inductance Lm during the interval DT < t ≤ T is (5.31) For steady-state operation, the increase in the stored magnetic energy in the magnetizing inductance ΔWLm(in) is equal to the decrease in the stored magnetic energy in the inductance ΔWLm(out).

5.3.6 DC Voltage Transfer Function for CCM Referring to Figure 5.5 and using a volt-second balance, A+ = A−, we can write (5.32) which can be rearranged to the form (5.33) resulting in the dc voltage transfer function of the lossless converter (5.34) The range of MV DC for the lossless flyback converter for 0 ≤ D ≤ 1 is (5.35) Notice that the plot of nMV DC = D/(1 − D) is the same as that of the dc voltage transfer function MV DC = D/(1 − D) for the buck–boost converter given in Chapter 4. It follows from (5.33) that the output voltage VO is independent of the load resistance RL and depends only on

the dc input voltage VI. It will be shown shortly that MV DC is significantly altered by losses, especially at values of D close to 1. From (5.34), (5.36) The sensitivity of the output voltage with respect to the duty cycle is (5.37) In practice, VO should be held constant. If VI increases, D should be decreased by a control circuit so that VO remains constant, and vice versa. The dc current transfer function is (5.38) and its value decreases from ∞ to zero as D is increased from 0 to 1. Using (5.34), (5.39) and using (5.38), (5.40) Thus, the switch and the diode utilization in the flyback converter is characterized by the output-power capability (5.41) As D is increased from 0 to 1, cp increases from 0, reaches a maximum equal to 0.25 at D = 0.5, and then decreases back to zero.

5.3.7 Boundary Between CCM and DCM Figure 5.6 depicts the current waveform of the magnetizing inductance at the boundary between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) for the flyback converter. This waveform can be described by (5.42)

Using (5.34), VI = nVO(1 − D)/D. Hence, (5.43) resulting in (5.44) The dc current through the magnetizing inductance at the boundary between CCM and DCM is (5.45) The energy transferred from the input dc voltage source VI to the magnetizing inductance during one cycle for the boundary case is (5.46) which produces the dc output power at the boundary (5.47) On the other hand, the dc power transferred from the converter to the load at the CCM/DCM boundary can be expressed as (5.48) where RLB = RLmax = VO/IOmin. Hence, the minimum value of the magnetizing inductance Lm is (5.49) The load resistance RLB at the boundary between the CCM and DCM modes is (5.50) and the load current at the boundary is (5.51)

Figures 5.7 and 5.8 show the normalized load current IOB/(n2VO/2fsLm) = (1 − D)2 and load resistance RLB/(2fsLm/n2) = 1/(1 − D)2 at the boundary between CCM and DCM as functions of D. Ferrite material should be used for the transformer. When the relative permeability of the core magnetic material is high, the magnetic energy stored in the transformer is low. The magnetic core should contain an air gap to avoid saturation and store a large amount of magnetic energy in the air gap.

Figure 5.6 Waveform of the current through the magnetizing inductance Lm at the boundary between CCM and DCM for the flyback converter.

Figure 5.7 Normalized load current IOB/(n2VO/2fsLm) at the boundary between CCM and DCM as functions of D for the flyback converter.

Figure 5.8 Normalized load resistance RLB/(2fsLm/n2) at the boundary between CCM and DCM as functions of D for the flyback converter.

5.3.8 Ripple Voltage in Flyback Converter for CCM The output part of the flyback converter is shown in Figure 5.9, where the filter capacitor is modeled by its capacitance C and its ESR denoted by rC. Figure 5.10 displays current and voltage waveforms in the converter output circuit. The dc component of the diode current equals the dc load current IO. The ac component of the diode current flows approximately through the filter capacitor Cf . The peak-to-peak value of the capacitor current may be written as (5.52) resulting in the peak-to-peak value of the voltage across rC

(5.53) The peak-to-peak value of the output ripple voltage Vr is usually specified. Hence, the maximum peak-to-peak value of the ac component of the voltage across the capacitance C is found as (5.54) On the other hand, this voltage is approximately given by (5.55) where ΔQmax is the charge decrease during the time interval from zero to DT. Rearrangement of (5.55) gives (5.56)

Figure 5.9 Output circuit of the flyback converter.

Figure 5.10 Waveforms illustrating the ripple voltage in the PWM flyback converter.

5.3.9 Power Losses and Efficiency of Flyback Converter for CCM An equivalent circuit of the flyback converter with parasitic resistances is shown in Figure 5.11. In this figure, rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the magnetizing inductance Lm representing core losses, and rC is the ESR of the filter capacitor C. The conduction losses will be found assuming that the magnetizing inductance current iLm is ripple free. Hence, the switch current can be approximated by (5.57)

resulting in its rms value

(5.58) resulting in the conduction loss in the MOSFET and in the primary winding of the transformer (5.59) and the primary winding of the transformer (5.60)

Figure 5.11 Equivalent circuit of the flyback converter with parasitic resistances and the diode offset voltage. Assuming that the transistor output capacitance Co is linear, the switching loss is expressed as (5.61)

Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) (5.62)

Similarly, the diode current may be approximated by

(5.63) which yields its rms value (5.64)

leading to the power loss in the diode forward resistance RF (5.65) and the resistance in the secondary winding of the transformer (5.66) The average value of the diode current is (5.67) which gives the power loss associated with the voltage VF (5.68) Thus, the overall diode conduction loss is (5.69) The current through the magnetizing inductance is (5.70) leading to its rms value (5.71) and the conduction loss in rL

(5.72) The current through the filter capacitor is (5.73) and the rms current through the filter capacitor is found as (5.74) and the power loss in the filter capacitor (5.75) The overall power loss is given by (5.76)

Thus, the converter efficiency is (5.77)

5.3.10 DC Voltage Transfer Function of Lossy Converter for CCM The dc component of the input current is (5.78) Hence, one obtains the dc current transfer function of the flyback converter (5.79) This equation holds true for both lossless and lossy converter. The converter efficiency can be expressed as

(5.80) from which the voltage transfer function of the lossy flyback converter is (5.81) Hence, the duty cycle for the lossy converter is given by (5.82) Notice that the duty cycle D at a given dc voltage transfer function is greater for the lossy converter than that for the lossless converter. Substitution of (5.82) into (5.77) yields the efficiency of the flyback converter for CCM (5.83) where (5.84)

and (5.85)

5.3.11 Design of Flyback Converter for CCM Design a universal power supply that accepts a single-phase utility line voltage from 85 to 264 Vrms at frequencies 50, 60, and 400 Hz, VO = 5 V, IO = 1–10 A, and Vr/VO ≤ 1%. Solution: The maximum and minimum output powers are (5.86) and

The minimum and maximum load resistances are

(5.87) (5.88)

and (5.89) The minimum and maximum dc input voltages are (5.90) and (5.91) Hence, the minimum and maximum values of the dc voltage transfer function are (5.92) and (5.93) Assume the converter efficiency η = 80% and Dmax = 0.36. Hence, the transformer turns ratio is (5.94) Let n = 11. The minimum and maximum duty cycle is (5.95) and (5.96) Assuming the switching frequency fs = 100 kHz, the minimum magnetizing inductance is

(5.97) Pick Lm = 2.5 mH. The peak-to-peak value of the ac component of the current through the magnetizing inductance is (5.98) The maximum dc input current occurs at VImin = 120.21 V, which corresponds to the maximum dc voltage transfer function MV DCmax = 0.04159. This current is given by (5.99) The current and voltage stresses of the semiconductor devices are (5.100) (5.101) (5.102) and (5.103) Let us select an International Rectifier IRF840 power MOSFET whose VDSS = 500 V, ISM = 8 A, rDS = 0.85 Ω, Qg = 42 nC, and Co = 100 pF, and an MBR2540 Schottky barrier diode whose IDM = 25 A, VDM = 40 V, VF = 0.3 V, and RF = 10 mΩ. The ripple voltage is (5.104) Let us assume Vrcpp = 40 mV and VCpp = 10 mV. Hence, one obtains the maximum value of the ESR of the filter capacitor (5.105) and the filter capacitance

(5.106) Pick C = 4 mF/25 V/2.5 mΩ. The power losses and the converter efficiency will be calculated at the maximum load current IOmax = 10 A and the maximum input voltage VImax = 373.35 V. The rms value of the current through the magnetizing inductance is (5.107) Assuming the dc value of rL = 350 mΩ, one obtains (5.108) The switch rms current is (5.109) which gives the MOSFET conduction loss (5.110) Assuming the resistance of the primary winding of the transformer rT1 = 0.9 Ω, the conduction loss in rT1 is (5.111) The switching loss is (5.112) Hence, (5.113) The rms diode current is (5.114) Thus, the power loss due to RF is

(5.115) and the power loss due to VF is (5.116) resulting in the diode conduction loss (5.117) Assuming the resistance of the secondary winding of the transformer rT2 = 20 mΩ, the power loss in rT2 is (5.118) The rms current of the filter capacitor is (5.119) Hence, the power loss in the ESR of the filter capacitor is (5.120) The total power loss is (5.121) Hence, the converter efficiency at full power is (5.122) A rectangular positive gate-to-source voltage of magnitude VGSm = 8 V is used to drive the MOSFET. Therefore, the gate-drive power is (5.123) Using (5.83) through (5.85), one can calculate the efficiency η as a function of the dc input voltage VI at fixed load resistances RL for the designed flyback converter in CCM; the plots are depicted in Figure 5.12. Knowing the efficiency η, the duty cycle D can be computed from (5.82). Figure 5.13 shows the duty cycle D as a function of dc input voltage VI for the flyback converter designed for CCM. Figures 5.14 and 5.15 show the efficiency η as a function of the dc output current IO at fixed dc input voltages VI, respectively. Plots of the efficiency η and the duty cycle D versus the load resistance RL at fixed dc input voltages VI are depicted in Figures

5.16 and 5.17. The duty cycle D decreases as VI increases.

Figure 5.12 Efficiency η versus dc input voltage VI at various load resistances RL for the flyback converter in CCM.

Figure 5.13 Duty cycle D versus dc input voltage VI at fixed load resistances RL for the flyback converter in CCM.

Figure 5.14 Efficiency η versus dc load current IO at fixed values of dc input voltage VI for the flyback converter in CCM.

Figure 5.15 Duty cycle D versus dc load current IO at fixed values of dc input voltage VI for the flyback converter in CCM.

Figure 5.16 Efficiency η versus load resistance RL at dc fixed values of input voltage VI for the flyback converter in CCM.

Figure 5.17 Duty cycle D versus load resistance RL at dc fixed values of input voltage VI for the flyback converter in CCM.

5.4 DC Analysis of PWM Flyback Converter for DCM Equivalent circuits for the PWM flyback converter operating in the DCM are depicted in Figure 5.18. Idealized current and voltage waveforms are shown in Figure 5.19. Prior to time t = 0, the current through the magnetizing inductance Lm is zero. At time t = 0, the switch is turned on. The diode remains off. The voltage across the magnetizing inductance is VI and the current through this inductance increases linearly from zero. At time t = DT, the switch is turned off and the diode turns on. The voltage across the magnetizing inductance is − VO. Therefore, the current through the magnetizing inductance decreases linearly. This current is reflected to the secondary of the transformer and flows through the diode. Once the diode current reaches zero, the diode begins to turn off. The current through the magnetizing inductance is zero until the switch is turned on.

Figure 5.18 Equivalent circuits of the PWM flyback converter for DCM. (a) Equivalent circuit when the switch is ON and the diode is OFF. (b) Equivalent circuit when the switch is OFF and the diode is ON. (c) Equivalent circuit when both the switch and the diode are OFF.

Figure 5.19 Idealized current and voltage waveforms in the PWM flyback converter for DCM.

5.4.1 Time Interval: 0 < t ≤ DT During this time interval, the switch is ON and the diode is OFF. The equivalent circuit is shown in Figure 5.18(a). The current through the diode and the secondary is iD = i2 = 0, resulting in the current through the primary i1 = −i2/n = 0. The voltage across the primary and the magnetizing inductance Lm is (5.124) and the magnetizing inductance and switch current is (5.125) Hence, one obtains the peak value of the switch current and the magnetizing inductance current

(5.126) The voltage across the secondary winding is (5.127) resulting in the voltage across the diode (5.128) from which (5.129) This time interval ends when the switch is turned off by the driver.

5.4.2 Time Interval: DT < t ≤ (D + D1)T The equivalent circuit for this time interval is shown in Figure 5.18(b). The switch is OFF and the diode is ON. Hence, iS = 0 and vD = 0. Since (5.130) the voltage across the magnetizing inductance Lm and the primary of the transformer is (5.131) From (5.126), the current through the magnetizing inductance is (5.132)

Since (5.133) the peak value of this current is

(5.134) Using (5.132), one arrives at the current through the primary of the transformer (5.135) and the current through the diode and the secondary of the transformer (5.136) Thus, from (5.126), the peak value of the diode current is (5.137) Because (5.138) the peak voltage across the switch is (5.139) which produces (5.140) This time interval ends when the diode current reaches zero.

5.4.3 Time Interval: (D + D1)T < t ≤ T During this time interval, both the switch and the diode are OFF. The equivalent circuit is shown in Figure 5.18(c). For this circuit, (5.141) resulting in (5.142) Also, (5.143) Because both iS and i1 = 0, (5.144)

Hence, (5.145) resulting in (5.146) The voltage across the switch is (5.147) and the voltage across the diode is (5.148) This time interval ends when the switch is turned on by the driver.

5.4.4 DC Voltage Transfer Function for DCM Method I: Referring to Figure 5.19 and using the volt-second balance for vLm, (5.149) which leads to (5.150) Using (5.126), the dc output current is found as (5.151) resulting in (5.152) Equating the right-hand sides of (5.150) and (5.152) produces (5.153) and substitution of this into (5.150) yields

(5.154) Hence, (5.155) Since the magnetizing inductance reflected to the transformer secondary is given by (5.156) one obtains (5.157) and (5.158) At the boundary between DCM and CCM, (5.159) Hence, one obtains the duty cycle at the boundary (5.160) Using (5.155) and (5.160), the dc voltage transfer function at the boundary is obtained as (5.161)

Figures 5.20 and 5.21 depict plots of D versus IO/(VO/2fsLms) and RL/(2fsLms) at various values of nMV DC for both CCM and DCM, respectively. Plots of nMV DC versus IO/(VO/2fsLms) and RL/(2fsLms) at various values of D are shown in Figures 5.22 and 5.23.

Figure 5.20 Duty cycle D as a function of normalized load current IO/(VO/2fsLms) at fixed values of MV DC for the lossless flyback converter in CCM and DCM.

Figure 5.21 Duty cycle D as a function of load resistance RL/(2fsLms) at fixed values of MV DC for the lossless flyback converter in CCM and DCM.

Figure 5.22 DC voltage transfer function MV DC as a function of normalized load current IO/(VO/2fsLms) at fixed values of D for the lossless flyback converter.

Figure 5.23 DC voltage transfer function MV DC as a function of normalized load resistance RL/(2fsLms) at fixed values of D for the lossless flyback converter. Method II: The dc component of the input current equals the dc component of the switch current (5.162) Therefore, the dc input power is (5.163) The dc output power is

(5.164) Equating right-hand sides of (5.163) and (5.164), one obtains (5.154).

5.4.5 Maximum Magnetizing Inductance for DCM The minimum value of the magnetizing inductance peak current at the boundary between the DCM and CCM occurs at D = DBmax. From (5.43), (5.165) The dc current through the magnetizing inductance at the boundary between CCM and DCM is (5.166) The energy transferred from the input dc voltage source VI to the magnetizing inductance during one cycle for the boundary case is (5.167) which results in the dc output power at the boundary (5.168)

The dc power transferred from the converter to the load at the boundary can be expressed as (5.169) Hence, the maximum value of the magnetizing inductance Lm is (5.170) Another method for deriving an expression for Lm is as follows. The dwell-duty ratio at full power is (5.171)

resulting in (5.172)

5.4.6 Ripple Voltage in Flyback Converter for DCM The peak-to-peak value of the capacitor current is (5.173) resulting in the peak-to-peak value of the voltage across rC (5.174) The voltage drop across the capacitor (5.175) The voltage across the capacitance is (5.176) where ΔQmax is the charge decrease during the time interval from zero to DT. Rearrangement of (5.55) gives (5.177)

5.4.7 Power Losses and Efficiency of Flyback Converter for DCM The peak current through the magnetizing inductance and the switch is (5.178) The rms value of the switch current is (5.179) Therefore, the MOSFET conduction loss is

(5.180) and the conduction loss in the primary winding resistance rT1 is (5.181) The maximum conduction loss in rDS and rT1 occurs at a full-load resistance RLmin and a low input voltage VImin. At low input voltage VImin, the duty cycle takes on a maximum value Dmax. At a full-load resistance RLmin, a large current is drawn from the line. Both these effects result in a maximum value of the switch rms current ISrms. The switching loss is given by (5.182)

The maximum switching loss occurs at the maximum switch voltage VSMmax = VImax + nVO and is independent of the load. The peak diode current is (5.183) and the rms value of the diode current is (5.184)

Hence, the power loss in the diode due to RF is (5.185) and the conduction loss in the secondary winding resistance rT2 is (5.186) The average diode current is ID = IO, resulting in the diode loss associated with VF

(5.187) Thus the overall diode conduction loss is (5.188) Using (5.153), (5.155), and (5.178), the rms value of the current through the magnetizing inductance is (5.189)

The power loss in rL is therefore given by (5.190)

The total power loss in the converter is (5.191)

This leads to the converter efficiency (5.192)

The dc input current is given by

(5.193) producing the dc input power (5.194) The dc output power is PO = V2O/RL. Since PO = ηPI, the dc voltage transfer function of the lossy flyback converter is (5.195)

Hence, (5.196)

5.4.8 Design of Flyback Converter for DCM Design a universal dc–dc converter for laptop computers that accepts a rectified single-phase utility line voltage from 85 to 264 Vrms, VO = 15 V, IO = 0–2 A, and Vr/VO ≤ 1%. Solution: The maximum output power is (5.197) and the minimum output power is zero. The minimum load resistance is (5.198) and the maximum load resistance is infinity. The minimum and maximum values of the dc input voltage are (5.199) and (5.200) Thus, the minimum and maximum dc voltage transfer functions are

(5.201) and (5.202) Assume that the duty cycle at the CCM/DCM boundary is DBmax = 0.4 and the converter efficiency is η = 0.85. Hence, one obtains the transformer turns ratio (5.203) Pick n = 5. Assume that the switching frequency is fs = 100 kHz. From (5.170), the maximum magnetizing inductance required to maintain the converter in DCM is found as (5.204) Pick Lm = 300 μH. From (5.195), the minimum duty cycle occurs at VImax = 373.35 V (5.205) and the maximum duty cycle occurs at VImin = 120.21 V (5.206) The maximum duty cycle of the diode at any input voltage VI is (5.207) At VImin = 120.21 V, (5.208) and at VImax = 373.35 V, (5.209) Assuming the dwell-duty ratio Dw = 0.05, we get

(5.210)

From (5.126) and (5.137), one obtains the maximum peak switch current (5.211) and the maximum peak diode current (5.212) Using (5.129) and (5.140), one can find the maximum value of the diode voltage (5.213) and the maximum value of the switch voltage (5.214) The maximum ripple voltage is (5.215) Assuming that the ESR of the filter capacitor is rC = 10 mΩ, the voltage drop across rC is found as (5.216) Hence, the maximum voltage across the filter capacitance is (5.217) Therefore, the minimum filter capacitance is (5.218) Let C = 120 μF/25 V/10 mΩ. Choose an International Rectifier IRF840 power MOSFET with rDS = 0.85 Ω, VDSS = VSM = 500 V, ISM = 8 A, Qg = 42 nC, and Co = 100 pF. Also, select an MBR10100 Schottky diode with VDM = 100 V, IDM = IF(AV) = 10 A, VF = 0.35 V at 25°C, VF = 0.24 V at 100°C, and RF = 30 mΩ. The maximum conduction loss in the MOSFET occurs at full load RLmin = 7.5 Ω and at D =

Dmax = 0.383, which corresponds to the low line VI = VImin = 120.21 V. This power is given by (5.219) The conduction loss in the MOSFET at D = Dmin = 0.123, which corresponds to the high line VI = VImax = 373.35 V, is (5.220) The transistor output capacitance is Co = 100 pF. Hence, the switching loss at VImin = 120.21 V is (5.221) and the switching loss at VImax = 373.35 V is (5.222) The power loss in the MOSFET at VImin = 120.21 V is (5.223) and the power loss in the MOSFET at VImax = 373.35 V is (5.224) The conduction power loss in the diode due to RF at any input voltage VI is (5.225) and the diode conduction loss due to VF at any input voltage VI is (5.226) which gives the total diode conduction loss at any input voltage VI (5.227) Let rT1 = 1 Ω and rT2 = 0.03 Ω. Hence, one obtains the conduction loss in the primary winding at VImin = 120.21 V as

(5.228) and at VImax = 373.35 V (5.229) and the conduction loss in the secondary winding at any input voltage VI (5.230) Assume that the series resistance of the magnetic core is rL = 0.5 Ω. Thus, the power loss in rL at VImin is (5.231)

and at VImax is (5.232)

The total power loss and the converter efficiency at VImin = 120.21 V and RLmin = 7.5 Ω are (5.233) and (5.234) The total power loss and the converter efficiency at VImax and RLmin are (5.235) and

(5.236) Assuming that the rectangular gate-to-source voltage changes from 0 to VGSpp = 7 V, the gatedrive power is (5.237) The efficiency η can be calculated from (5.192) and the duty cycle D from (5.196). Figures 5.24 through 5.29 show the efficiency η and the duty cycle D versus the dc input voltage VI, load current IO, and load resistance RL for the flyback converter designed in the above example for DCM.

5.5 Multiple-Output Flyback Converter In many applications such as computers, power supplies are required to provide several outputs at different voltages, which can be both positive and negative, and may be required to be isolated from each other. Multiple outputs can be obtained by adding additional secondary windings to the transformer, each with its own rectifier and output low-pass filter. Figure 5.30 shows an example of a two-output flyback converter. However, only one of the outputs can be regulated with a negative feedback loop by controlling the duty cycle D of the transistor, and other outputs are not regulated. Normally, the output with the highest output power is regulated. Other outputs will follow according to the duty cycle determined by the control loop of the main output. If the input voltage VI increases, the duty cycle D is reduced for all outputs. If other outputs are required to be regulated, a linear regulator or a magamp post regulator may be added on each low-power output. Figure 5.31 shows an equivalent circuit of multiple-output flyback converter. The turns ratios of the transformer are (5.238)

Figure 5.24 Efficiency η as a function of dc input voltage VI at fixed load resistances for the flyback converter in DCM.

Figure 5.25 Duty cycle D as a function of dc input voltage VI at fixed load resistances for the flyback converter in DCM.

Figure 5.26 Efficiency η as a function of dc load current IO at fixed load resistances for the flyback converter in DCM.

Figure 5.27 Duty cycle D as a function of dc load current IO at fixed load resistances for the flyback converter in DCM.

Figure 5.28 Efficiency η as a function of load resistance RL at fixed dc input voltages for the flyback converter in DCM.

Figure 5.29 Duty cycle D as a function of load resistance RL at fixed dc input voltages for the flyback converter in DCM.

Figure 5.30 Multiple-output flyback converter.

Figure 5.31 Equivalent circuit of multiple-output flyback converter. and (5.239) The dc voltage transfer functions of the flyback converter are [20] (5.240) and (5.241) yielding (5.242)

and (5.243) Consider the minimum magnetizing inductance Lm(min) required for CCM operation. The boundary between CCM and DCM on the CCM side occurs at VImax, which corresponds to Dmin. At the boundary between CCM and DCM, the peak current through the magnetizing inductor is (5.244) and the magnetic energy stored in the magnetizing inductance is (5.245) All this energy is transferred to both output loads. Thus, the output power delivered to both outputs is (5.246)

Thus, (5.247) Hence, the minimum magnetizing inductance required for CCM operation of the flyback converter with two outputs is (5.248)

Similarly, (5.249) yielding the minimum magnetizing inductance required for CCM operation

(5.250)

For n1 = n2, we get (5.251) The minimum magnetizing inductance for the flyback converter with n outputs required for CCM operation is given by (5.252)

The boundary between CCM and DCM on the DCM side occurs at VImin, which corresponds to Dmax. The maximum magnetizing inductance required for DCM operation of the flyback converter with two outputs is (5.253)

The maximum magnetizing inductance required for DCM operation of the flyback converter with n outputs is (5.254)

The magnetizing inductance of multiple-output flyback converter for CCM and DCM is the same as that of the single-output flyback converter with the same maximum total output power.

5.6 Bidirectional Flyback Converter A derivation of a bidirectional flyback converter is shown in Figure 5.32. A unidirectional noninverting flyback converter is depicted in Figure 5.32(a). Figure 5.32(b) shows the same converter with the cathode of the diode connected to ground. If the diode in this circuit is replaced by a MOSFET, a bidirectional flyback converter is obtained as depicted in Figure 5.32(c).

Figure 5.32 Derivation of a bidirectional flyback converter. (a) Unidirectional noninverting flyback converter. (b) Unidirectional noninverting flyback converter with the cathode of the diode connected to ground. (c) Bidirectional flyback converter.

5.7 Ringing in Flyback Converter The leakage inductance of transformers of all isolated dc–dc converters may lead to ringing, increased voltage stresses, and increased power loss, resulting in a significant degradation of circuit performance. The ringing is caused by parasitic oscillations between the transformer leakage inductance and the transistor output capacitance. The leakage inductance on the primary side of the transformer is given by (5.255) where Lp is the inductance of the primary winding and k is the coupling coefficient of the transformer primary and secondary windings. Typical values of k are in the range 0.98–0.99.

For example, for Lp = 2.5 mH and k = 0.98, we obtain Ll = (1 − 0.98) × 2.5 × 10− 3 = 50 μH. In a single-transistor flyback converter, a voltage spike and ringing is developed at the leading edge of the switch voltage vS at each transistor turn-off due to the transformer leakage inductance Ll. A high voltage spike and ringing are superimposed on the steady-state transistor voltage VSM = VI + nVO. When the transistor is turned off, the transformer leakage inductance Ll, the transistor output capacitance Co = Coss = Cds + Cgd, and the transformer stray input capacitance Cp form a resonant circuit, as shown in Figure 5.33. The current through the leakage inductance Ll is (5.256) the voltage across the leakage inductance is (5.257) and the voltage across the switch is (5.258) where is the current in the leakage inductance Ll just before the switch turns off, Rp is the primary winding resistance, , the frequency of ringing is (5.259) the characteristic impedance of the resonant circuit is (5.260) Hence, the peak voltage across the switch is (5.261)

Figure 5.33 Equivalent circuit of flyback converter when the transistor is OFF. The energy stored in the leakage inductance just before the transistor turn off is (5.262) resulting in the power loss due to ringing (5.263) Example 5.1 A flyback converter (designed for CCM) has Ll = 50 μH, Co = 470 pF, Cp = 30 pF, ISMmax = 1.418 A, VSMmax = 373 V, n = 11, VO = 5 V, and fs = 100 kHz. Find the ringing frequency, the maximum switch voltage, and the power loss due to ringing. Solutions: The ringing frequency is (5.264) the characteristic impedance is (5.265)

the peak value of the voltage across the leakage inductance is

(5.266) the maximum value of the voltage across the switch is (5.267) and the power loss due to ringing is (5.268) The switch conduction loss also increased because a transistor with a much higher breakdown voltage VDSS and a much higher on-resistance rDS must be used.

5.8 Flyback Converter with Passive Dissipative Snubber One way to reduce the magnitude of ringing is to use a passive dissipative RCD snubber, as shown in Figure 5.34. A large capacitance acts as a voltage source whose average voltage is nVO. When the ringing voltage increases the diode turns on and a constant voltage is dropped across the transformer primary winding and a transistor. The maximum peak voltage of the transistor is (5.269) Most of the energy stored in the leakage inductance is dissipated in the snubber resistor R and the snubber diode, reducing the converter efficiency.

Figure 5.34 Flyback converter with dissipative RCD snubber.

5.9 Flyback Converter with Zener Diode Voltage Clamp In order to reduce the magnitude of the ringing, a voltage limiter (or voltage clamp) in the form of a Zener diode in series with a diode connected back-to-back may be added across the

transformer winding as shown in Figure 5.35. This is also a dissipative voltage clamp. When the transistor is turned off, the voltage across the primary winding reverses, and the diodes conduct. The voltage across the magnetizing inductance is vLm = nVO. The Zener diode behaves like a dc voltage source with its voltage Vz. The voltage across the leakage inductance after the switch is turned off and the Zener diode turns on is V. The voltage across the switch after it is turned off is given by (5.270) The current through the leakage inductance and the diodes decreases linearly. When the diode current reaches zero, the diodes turns off, and the voltage across the switch is expressed by (5.271) The Zener diode voltage clamp is used in low voltage converters, where Vz ≤ 50 V. It is not used in universal-input, off-line flyback converters.

Figure 5.35 Flyback converter with a Zener diode voltage clamp across the transformer primary winding.

5.10 Flyback Converter with Active Clamping Figure 5.36 shows three nearly lossless active clamp circuits. These circuits may also provide zero-voltage switching (ZVS), reducing switching losses, reducing EMI, and increasing the efficiency. The clamping circuit consists of transistor Q2 and the coupling capacitor Cc. In the converter depicted in Figure 5.36(a), the clamping circuit is connected across the primary. This circuit is called the high-end n-channel active clamp. The main transistor Q1 is driven with the duty cycle D and the clamp transistor is driven with the duty cycle 1 − D. The voltage across the clamp capacitor is

(5.272) where VLl is the voltage across the leakage inductance, which can be up to 0.4nVO. the converter shown in Figure 5.36(b), the clamping circuit is connected across the main switch. It is called the low-end n-channel active clamp. The voltage across the clamping capacitor Cc is (5.273) In the converter shown in Figure 5.36(c), the clamping circuit contains a p-channel MOSFET. This circuit is called the low-end p-channel active clamp.

Figure 5.36 Flyback converter with clamp circuits to avoid ringing. (a) High-end n-channel active clamp. (b) Low-end n-channel active clamp. (c) Low-end p-channel active clamp.

5.11 Two-Transistor Flyback Converter A two-switch flyback converter with two fast diodes is shown in Figure 5.37. Both transistors are ON and OFF simultaneously. When the transistors are turned off, the two clamping diodes

D2 and D3 are forced to turn on by the current of the magnetizing inductance Lm and clamp the voltage across the transistors and the primary winding to VSMmax = VImax. Therefore, steadystate voltage across each switch is reduced over that of a single-switch flyback converter, which is VSM = VI + nVO. The peak value of the single-switch flyback converter is VSM = VI + nVO + Vpk(ring), where Vpk(ring) is the magnitude of the voltage ringing superimposed on the steady-state transistor voltage. The conduction loss in the single-switch converter PDS1 = rDS1I2srms. The conduction loss in each transistor is the two-switch converter PDS2 = rDS2I2srms. The ratio of the conduction loss in the transistor of the single-switch flyback converter to the conduction loss in both the transistors in the two-switch flyback converter is (5.274)

where VBD1 is the breakdown voltage of the MOSFET in the single-switch flyback converter and VBD2 is the breakdown voltage of the MOSFETs in the two-switch flyback converter. The maximum overshoot of the second-order system causing ringing can be as high as 100%, resulting in Vpk(ring) ≈ VImax. Thus, the conduction loss in the two transistors of the two-switch flyback converter is lower than that of the single-switch flyback converter.

Figure 5.37 Two-switch flyback converter that eliminates ringing. The current of the magnetizing inductance flows through the clamping diodes D2 and D3, and

also through the rectifier diode D1. The current of the two clamping diodes decreases gradually to zero with slope VI/Lm. When the current of the clamping diodes reaches zero, the diodes turn off at zero current and do not suffer from the reverse recovery problems. The converter is used in both CCm and DCM, especially at high dc input voltages VI. The dc voltage transfer function of the two-transistor flyback converter is identical to that of the single-transistor flyback converter. For CCM, the dc voltage transfer function is (5.275) The advantage of the two-switch flyback converter over its single-switch counterpart is the reduced voltage stress of the switch. This voltage is well determined. In addition, there is no need for a snubber across the primary winding to dissipate the energy stored in the leakage inductance of the primary winding. The disadvantage of the two-transistor flyback converter is the floating gate driver of the high side transistor.

5.12 Summary The flyback converter is the lowest cost regulator because it has the lowest parts count and the output filter inductor is not required. It consists of only four components. The transformer provides dc isolations and its magnetizing inductance stores the energy and no extra inductor is required. The flyback converter can be derived from the buck–boost converter by replacing the inductor with a transformer. The equations for the flyback converter are similar to those of the buck–boost converter. To obtain the equations for the flyback converters from the buck–boost converter, MV DC should be replaced by nMV DC, VI reflected to the secondary side of the transformer should be replaced by VI/n, and the load current IO reflected to the primary side of the transformer should be replaced by IO/n. The flyback converter can be used either as a step-down or a step-up converter. It can be either inverting or noninverting converter, depending on the polarity of the transformer, the rectifier diode, and the filter capacitor. The flyback converter may be used to build multiple-output power supplies. The voltage and current stresses are high in the flyback converter. The typical power range of the flyback converter is from 20 to 2000 W. For the lossless flyback converter, the dc voltage transfer function is MV DC = D/n(1 − D) for CCM. For the lossy converter, the dc voltage transfer has lower values than those for the lossless

converter, especially for the duty cycle D close to 1. For this reason, the maximum value of the dc voltage transfer function is limited. The converter should not be used at D close to 1 because its efficiency is poor for D from 0.9 to 1. The peak-to-peak value of the current through the filter capacitor is large, equal to the peak-to-peak value of the diode current IDM. The input current is pulsating. The corner frequency of the output filter fo = 1/(2πCRL) depends on the load resistance RL. It is very easy to drive the transistor in the flyback converter because the source is connected to ground. In the flyback converter, only one-half of the B–H curve of the transformer core is utilized. Therefore, a core with an air gap and a relatively large volume is normally required to avoid saturation. The two-switch flyback converter has a reduced voltage stress of the switch from VSMmax = VImax + nVO + Vpk(ring) and the energy stored in the leakage inductance of the primary winding is returned to the dc input voltage source, thus eliminating the need for a snubber across the primary winding.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984. 3. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 4. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 5. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood, NJ: Prentice-Hall, 2004. 6. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 7. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 8. J. G. Kassakian, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991.

9. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 10. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 11. R. Watson, F. C. Lee, and G. C. Hua, “Utilization of an active-clamp circuit to achieve soft switching in flyback converter,” IEEE Transactions on Power Electronics, vol. 11, no. 1, pp. 162–169, January 1996. 12. H. Chung, S. Y. Hui, and W. H. Wang, “An isolated ZVS/ZCS flyback converter using the leakage inductance of the coupled inductor,” IEEE Transactions on Industrial Electronics, vol. 45, no. 4, pp. 679–682, August 1998. 13. H. Chung, S. Y. Hui, and W. H. Wang, “A zero-current switching PWM flyback converter with a simple auxiliary switch,” IEEE Transactions on Power Electronics, vol. 14, no. 2, pp. 329–342, March 1999. 14. I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. 15. D. Murthy-Bellur and M. K. Kazimierczuk, “Two-switch flyback dc-dc converter in continous-conduction mode,” International Journal of Circuit Theory and Applications, vol. 39, no. 8, pp. 849–864, August 2011. 16. D. Murthy-Bellur and M. K. Kazimierczuk, “Two-switch flyback dc-dc converter in discontinous-conduction mode,” International Journal of Circuit Theory and Applications, vol. 39, no. 11, pp. 1145–1160, November 2011. 17. D. Murthy-Bellur and M. K. Kazimierczuk, “Isolated two-switch zeta converter with reduced transistor voltage stress,” IEEE Transactions on Circuits and Systems, Part II, Express Brief, vol. 58, no. 1, pp. 41–45, January 2011. 18. D. Murthy-Bellur and M. K. Kazimierczuk, “Zero-current transition two-switch flyback pulse-width modulated dc-dc converter,” IET Power Electronics, vol. 4, no. 3, pp. 288– 295, 2011. 19. D. Murthy-Bellur and M. K. Kazimierczuk, “Active clamp ZVS two-switch flyback dc-dc converter,” IEEE International Symposium on Circuits and Systems, Rio de Janeiro, Brazil, May 15–18, 2011, pp. 241–244. 20. N. Kondrath, A. Ayachit, and M. K. Kazimierczuk, “Minimum required magnetizing inductance for multiple-output flyback dc-dc converter in CCM,” IET Electronic Letters, vol. 51, no. 12, pp. 930–931, June 11, 2015.

Review Questions 1. What are the roles of the transformer in the flyback PWM converter?

2. Is the flyback converter a step-down or a step-up converter? 3. What is the useful range of the duty cycle for the flyback converter? 4. What is the useful range of the dc voltage transfer function for the flyback converter? 5. Is the transformer required to store energy in the flyback converter? 6. Is it difficult to drive the transistor in the flyback converter? 7. Is the peak-to-peak value of the current through the filter capacitor large in the flyback converter? 8. Is the flyback converter a complicated converter? 9. What is the typical range of the output power of the flyback converter? 10. Is the flyback converter an inverting or a noninverting converter? 11. Can the flyback converter be used in multiple-output power supplies? Draw an example circuit of such a converter? 12. Is the switch voltage stress low in the flyback converter? 13. Is the size of the magnetic core small in the flyback converter? 14. Is it useful to use a core with an air gap in the flyback converter?

Problems 1. The dc input voltage of a flyback PWM converter operating in CCM is the US single-phase rectified voltage and the dc output voltage is VO = 800 V. Find the transformer turns ratio n. 2. The dc input voltage of a flyback PWM converter is the US single-phase rectified voltage, the dc output voltage is VO = 800 V, and the transformer turns ratio is n = 1/3. Find the voltage stresses of the switch and the diode. 3. The dc input voltage of a flyback PWM converter is the US single-phase rectified voltage, the dc output voltage is VO = 800 V, the minimum load current is IOmin = 0.2 A, the maximum input voltage VImax = 187 V, the switching frequency is fs = 50 kHz, the efficiency is η = 0.95, and the transformer turns ratio is n = 1/3. Find the minimum magnetizing inductance of the transformer to maintain the operation in CCM. 4. A flyback PWM converter is supplied by the US single-phase rectified line voltage, VO = 800 V, IO = 0.2–0.5 A, the minimum input voltage VImin = 127 V, the minimum duty cycle Dmin = 0.6, n = 1/3, Lm = 2 mH, and fs = 50 kHz. Find the current stresses of the switch and the diode. 5. A flyback PWM converter is supplied by the US single-phase rectified line voltage, VO = 800 V, IO = 0.2–0.5 A, n = 1/3, the maximum dc input current is IImax = 3.15 A, MV DCmin =

6.229, fs = 50 kHz, and Vr/VO ≤ 1%. Find the filter capacitance. 6. Design a flyback PWM converter to meet the following specifications: VI = 270 Vdc ± 10%, VO = 28 V, IO = 0.2–2 A, and Vr/VO ≤ 1%. Find n, Lm, C, and η. 7. The dc input voltage of a flyback PWM converter is the US single-phase rectified voltage, the dc output voltage is VO = 800 V, the minimum load current is IOmin = 0 A, the maximum load current is IOmax = 0.5 A, the switching frequency is fs = 50 kHz, the efficiency is η = 0.95, and the transformer turns ratio is n = 1/3. Find the maximum magnetizing inductance of the transformer to maintain the operation in DCM. 8. Design a flyback converter to meet the following specifications: VI = 240 to 300 Vdc, VO = 28 V, IO = 0.2–2 A, fs = 200 kHz, Vr/VO ≤ 1%, rL = 2 Ω, rDS = 0.5 Ω, rT1 = 50 mΩ, rT2 = 10 mΩ, rC = 50 mΩ, VF = 0.7 V, RF = 25 mΩ, and Co = 100 pF. Find n, Dmin, Dmax, L, C, and η. 9. Design a flyback converter whose VI is the US rectified line voltage 92–132 Vrms, VO = 800 V, IO = 50–500 mA, Vr/VO ≤ 1%. Find Lm, C, rC, ISM, VSM, and n. 10. Design a universal power supply that accepts a single-phase line voltage from 85 to 264 Vrms at f = 50–440 Hz, VO = 5 V, IO = 0–10 A, and Vr/VO ≤ 1%. Assume rDS = 0.85 Ω, RF = 10 mΩ, VF = 0.3 V, rC = 2.5 mΩ, rL = 0.35 Ω, rT1 = 0.9 Ω, rT2 = 0.02 Ω, fs = 100 kHz, Co = 100 pF, and the initial efficiency η = 80%. 11. Draw a circuit of a multiple-output flyback converter with VO1 = 5 V, VO2 = 12 V, and VO3 = 12 V.

6 Forward PWM DC–DC Converter 6.1 Introduction The PWM forward converter [1–18] is one of the most widely used converters. It is a singleended isolated (i.e., transformer) converter and can be derived from the buck converter. Therefore, it belongs to the family of the buck-derived converters. A core reset circuit is required in this converter. The transformer is not required to store magnetic energy. The switch must withstand high voltage stress. The forward converter is suitable for low and medium power applications, usually from 30 to 500 W. It is used in either single output or multipleoutput power supplies. This chapter presents a steady-state analysis of the PWM forward converter for both CCM and DCM. Design examples are given for both modes.

6.2 DC Analysis of PWM Forward Converter for CCM 6.2.1 Derivation of Forward PWM Converter The forward converter can be derived from the buck converter by adding the transformer and diode D1 between the switch and the diode D2. Therefore, the forward converter is one of the buck-derived converters. Figure 6.1 shows the derivation of the forward converter. The buck converter is depicted in Figure 6.1(a). It is a transformerless converter. Its disadvantage is that the gate of the MOSFET is driven with respect to a “hot point.” In Figure 6.1(b), an inductor Lm and a diode D1 are added between the switch and the freewheeling diode D2. Notice that the inductor Lm cannot be connected directly in parallel with the diode D2 because the average steady-state voltage across the inductor is zero, whereas the average voltage across the diode is negative. To remove this contradiction, the diode D1 is added between the inductor Lm and the diode D2. The average voltage across the diode D2 is equal to the average voltage across the diode D1. The switch and the diode D1 are either ON or OFF during the same time intervals. In contrast, the diode D2 is in the opposite state to both the switch and the diode D1 for CCM. When the switch is ON, the voltage across the inductor Lm is equal to VI and therefore the inductor current increases linearly. When the switch is turned off, the diode D1 also turns off, making an open circuit for the inductor Lm. The current and the energy stored in the inductor Lm at this time is nonzero. Therefore, some provision must be added to demagnetize the inductor Lm. One way is to add an extra winding coupled to the inductor Lm and a diode D3, as shown in Figure 6.1(b). The polarity of the extra winding must be such that the voltage across Lm is negative in order to cause the current through Lm to decrease. In addition, the switch must be held off long enough to allow the inductor current to decrease to

zero. The energy stored in the inductor Lm at the time the switch is turned off is returned to the dc input source VI. The inductor Lm can be replaced by a transformer, resulting in the forward converter shown in Figure 6.1(c). Because the MOSFET is connected in series with the primary of the transformer, it can be shifted so that the gate is driven with respect to ground, as shown in Figure 6.1(d). The transformer core reset is obtained by adding a tertiary winding to the transformer (also called a clamp winding) in series with a diode D3. It generally has the same number of turns as the primary in most applications and is usually bifilar wound. It clamps the voltage across the switch at twice the line voltage VI if the number of turns of the primary and the tertiary are the same. Its main function is to return energy stored in the magnetizing inductance to the input voltage source VI and therefore reset the core after each cycle of operation. The duty cycle of the switch is limited to allow the core to reset. Its maximum value is 50% if the number of turns of the primary and the tertiary are the same. There are other core reset circuits, but most of them are lossy circuits.

Figure 6.1 Derivation of the forward PWM converter. (a) Buck converter. (b) An inductor Lm, diode D1, an additional winding, and diode D3 are added to the buck converter. (c) Forward converter with the MOSFET gate driven with respect to a “hot point.” (d) Forward converter with the MOSFET gate driven with respect to ground. A negative output voltage can be obtained by reversing the secondary and diodes D1 and D2. A multiple-output converter can be obtained by adding extra secondary windings, diodes D1 and D2, and an inductor L, and a filter capacitor C. The magnetizing inductance in the forward converter is not required to store energy. The transformer employs only one-half of the B–H curve of the magnetic core. Therefore, the core usually requires an air gap and may be bulky. The input current waveform is pulsating, but an LC input filter can be added to obtain a nonpulsating input current. The forward converter is usually suitable for applications where the power level is between 30 and 500 W. The analysis of the forward PWM converter of Figure 6.1(d) is based on the following assumptions:

1. The power MOSFET and the diode are ideal switches. 2. The transistor output capacitance and the diode capacitance, as well as lead inductances are zero, which implies zero switching losses. 3. The transformer leakage inductances and stray capacitances are neglected. 4. Passive components are linear, time invariant, and frequency independent. 5. The output impedance of the input voltage source VI is zero for both dc and ac components.

6.2.2 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch and the diode D1 are ON, and the diodes D2 and D3 are OFF. An ideal equivalent circuit for this time interval is shown in Figure 6.2(a). The actual transformer is modeled by an ideal transformer and the magnetizing inductance Lm. The relationship among the transformer voltages and the transformer turns ratio is (6.1) where N1, N2, and N3 are the numbers of turns of the primary, secondary, and tertiary, respectively. The voltage ratio can also be expressed as (6.2) from which (6.3) where n1 = N1/N2 and n3 = N3/N2. The power balance for the ideal transformer is i1v1 = i2v2 + i3v3, where i3 = iD3.

Figure 6.2 Equivalent circuits for different time intervals for the forward PWM converter operating in CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ DT + tm. (c) For DT + tm < t ≤ T. When the switch is ON, the voltage across the primary of the ideal transformer and the magnetizing inductance Lm is (6.4) The boundary condition of the magnetizing inductance is iLm(0) = 0 as shown later. Hence, one obtains the current through the magnetizing inductance Lm (6.5) The peak value of the magnetizing current is given by

(6.6) whose maximum value occurs at VImax and Dmin or at VImin and Dmax (6.7) Thus, the minimum magnetizing inductance is (6.8) where ΔiLm(max) is usually 5–10% of the maximum peak current of the ideal transformer primary I1max. The voltage across the secondary of the transformer is found as (6.9) Thus, the voltage across inductance L is (6.10) This leads to the current through the secondary, diode D1, and inductance L (6.11) resulting in (6.12)

and (6.13)

The current through the primary of the transformer is (6.14)

and the current through the switch (6.15)

The voltage across the diode D2 is (6.16) Using (6.4), one obtains the voltage across the tertiary winding (6.17) and the voltage across the diode D3 (6.18) The waveforms in the forward converter for CCM are shown in Figure 6.3.

Figure 6.3 Waveforms in the PWM forward converter for CCM.

6.2.3 Time Interval: DT < t ≤ DT + tm Figure 6.2(b) shows an ideal equivalent circuit for the forward converter during the time interval DT < t ≤ DT + tm. During this time interval, the switch and diode D1 are OFF, and the diodes D2 and D3 are ON. The voltage across the inductor L is (6.19) Hence, the current through the inductor L and the diode D2 can be found as (6.20) where iL(DT) is the initial condition of the inductor L at t = DT. The peak-to-peak value of the

current ripple through the inductor L is (6.21) Referring to Figure 6.2(b), the voltage across the tertiary is (6.22) Hence, the voltage across the primary and the magnetizing inductance Lm is (6.23) Hence, (6.24)

(6.25) and (6.26) The peak current of the diode D3 occurs at t = DT and is given by (6.27) The voltages across the secondary and the diode D1 are (6.28) and the voltage across the switch is (6.29) At time t = DT + tm, the current through the magnetizing inductance iLm and the diode current iD3 reach zero, terminating this time interval. Since iLm(DT + tm) = 0,

(6.30) from which (6.31) For n3 = n1, tm = DT and tm(max) = DmaxT. The magnetizing inductance is given by (6.32)

where N1 is the number of turns in the primary winding, Ac is the core cross-sectional area, lc is the core length, lg the air gap length, and μr is the core relative permeability. The maximum magnetic flux density is (6.33)

where Bs is the core saturation flux density.

6.2.4 Time Interval: DT + tm < t ≤ T An equivalent circuit of the forward converter for the time interval DT + tm < t ≤ T is shown in Figure 6.2(c). During this time interval, the switch, the diode D1, and the diode D3 are OFF and the diode D2 is ON. The voltages across the transformer windings and the diode D2 are v1 = v2 = v3 = vLm = 0. The voltage across the switch is (6.34) and the voltage across the diode D3 is (6.35) The voltage across the inductor L and the current through the diode D2 and inductor L are given by (6.19) and (6.20), respectively.

6.2.5 Maximum Duty Cycle To ensure the transformer core reset, the current through the magnetizing inductance Lm must decrease to zero in every cycle for the steady-state operation. Otherwise, the current and the energy stored in the magnetizing inductance Lm at the end of each cycle would be greater than

that at the end of the previous cycle. This would lead to a catastrophic failure of the converter. Therefore, the duty cycle for the forward converter has its maximum permissible value DMAX. The transformer core reset condition can be expressed as (6.36) or (6.37) For the worst case, this condition is (6.38) or (6.39) The voltage across the magnetizing inductance vLm is VI for 0 < t ≤ DT and − (n1/n3)VI for DT < t ≤ DT + tm. Using the volt-second balance, (6.40) Rearranging this equation yields (6.41)

As the ratio n3/n1 increases from 0.25 to 4, DMAX decreases from 0.8 to 0.2. For n3 = n1, DMAX = 0.5. From (6.41), (6.42) Hence, from (6.29), the peak switch voltage becomes (6.43) As n3/n1 increases from 0.25 to 4, VSM increases from 1.25VI to 5VI. For n3 = n1, VSM = 2VI. The peak switch voltage VSM increases with increasing DMAX (i.e., with increasing ratio n1/n3) and becomes very high at DMAX close to 1. Therefore, one should avoid DMAX > 0.8. In many applications, n3 = n1 is used.

6.2.6 Device Stresses

The maximum value of the peak switch voltage and current through the switch are (6.44) and (6.45) The maximum value of the peak voltage across the diode D1 is (6.46) the maximum value of the peak voltage across the diode D2 is (6.47) and the peak values of the currents through the diodes D1 and D2 are (6.48) The maximum value of the peak voltage across the diode D3 is (6.49) and the peak value of the current through diode D3 is (6.50) As n3/n1 increases from 0.25 to 4, VD3M increases from 1.25VI to 5VI. For n3 = n1, VD3M = 2VI.

6.2.7 DC Voltage Transfer Function for CCM From Figure 6.3, the voltage across the inductor L is vL = VI/n1 − VO for 0 < t ≤ DT and vL = −VO for DT < t ≤ T. Applying the volt-second balance, (6.51) from which the dc voltage transfer function of the lossless converter is obtained

(6.52) The output voltage VO is independent of the load resistance RL. It depends only on the dc input voltage VI. In most practical situations, VO = DVI/n1 is constant. If VI is increased, D should be decreased by a control circuit to keep VO constant, and vice versa. The dc current transfer function is given by (6.53) From (6.44), (6.45), and (6.52), the switch and the diode utilization in the forward converter is characterized by the output-power capability (6.54) As D is increased from 0 to 1, so does cp.

6.2.8 Boundary Between CCM and DCM Figure 6.4 shows the inductor current waveform iL at the boundary between CCM and DCM. The inductor current waveform is (6.55) yielding (6.56)

Taking into account the converter efficiency η, we get (6.57) from which (6.58) (6.59)

and (6.60)

Figure 6.4 Waveforms of the inductor current at the boundary between CCM and DCM at VImin and VImax. The dc output current at the boundary between CCM and DCM is (6.61)

The load resistance at the CCM/DCM boundary is (6.62) Hence, the minimum value of the inductance L is found to be (6.63)

where Dmin = n1MV DCmin/η = n1VO/(ηVImax). Equation (6.63) is the same as that for the buck converter. Figures 6.5 and 6.6 show the normalized load current IOB/(VO/2fsL) = 1 − D and load resistance RLB/(2fsL) = 1/(1 − D) at the boundary between CCM and DCM as functions of the duty cycle D for DMAX = 0.5 and η = 1, respectively.

Figure 6.5 Normalized load current IOB/(VO/2fsL) at the boundary between CCM and DCM as a function of duty cycle D for the forward converter at DMAX = 0.5 and η = 1.

Figure 6.6 Normalized load Resistance RLB/(2fsL) at the boundary between CCM and DCM as a function of duty cycle D for the forward converter at DMAX = 0.5 and η = 1.

6.2.9 Ripple Voltage in Forward Converter for CCM The ripple voltage for the forward converter can be found in the same way as for the buck converter. The peak-to-peak ripple on the output voltage is independent of the voltage across the filter capacitance and is determined only by the ripple voltage across the ESR if the following condition is satisfied (6.64) In the worst case, Dmin = 0. Thus, the above condition is satisfied at any value of D if (6.65)

If condition (6.64) is satisfied, the peak-to-peak ripple voltage of the forward converter is (6.66) If condition (6.64) is not met, the voltages across the filter capacitance and the ESR contribute to the total output voltage ripple. The maximum increase in the charge stored in the filter capacitor is (6.67) Using (6.60) and (6.67), the peak-to-peak ripple voltage across the filter capacitance C is (6.68) where capacitance is

is the corner frequency of the output low-pass filter. The minimum

(6.69) The peak-to-peak ripple voltage across the ESR is (6.70) The total ripple of the output voltage is approximately given by (6.71)

6.2.10 Power Losses and Efficiency of Forward Converter for CCM Figure 6.7 depicts an equivalent circuit of the forward converter with parasitic resistances, rDS is the MOSFET on-resistance, rT1 is the winding resistance of the primary, rT2 is the winding resistance of the secondary, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. Neglecting the ripple of the inductor current, the switch current can be approximated by (6.72) which results in its rms value

(6.73)

and the conduction loss in the power MOSFET (6.74) Assuming that the transistor output capacitance Co is linear, the switching loss is (6.75) Hence, one obtains the total power dissipation in the MOSFET (excluding the drive power) (6.76)

Figure 6.7 Equivalent circuit of the forward converter with parasitic resistances to determine component losses (the branch with diode D3 is neglected). The conduction loss in the winding of the primary is (6.77) Let us assume that the diodes D1 and D2 are identical. The current through the diode D1 and the secondary winding of the transformer can be approximated by

(6.78) producing its rms value (6.79) and the power losses in RF (6.80) The average value of the current through the diode D1 is (6.81) which gives the power loss associated with the voltage VF of diode D1 (6.82) Thus, the total conduction loss in diode D1 is given by (6.83) The power loss in rT2 is (6.84) The power loss in both the primary and secondary winding is (6.85) The current of diode D2 can be approximated by (6.86) yielding its rms value

(6.87) and the power loss in RF (6.88) The average value of the current through the diode D2 is found as (6.89) from which the power loss associated with the voltage VF of diode D2 is obtained as (6.90) Thus, the overall conduction loss in diode D2 is (6.91) The power losses in the diode D3 and the tertiary winding as well as the power transferred back from the magnetizing inductance to the input voltage source VI are neglected. The inductor current is (6.92) leading to its rms value (6.93) and the inductor conduction loss (6.94) The current through the filter capacitor can be expressed as (6.95)

Using (6.21) and (6.95) the rms current through the filter capacitor is found to be

(6.96)

and the power loss in the filter capacitor is (6.97) Neglecting the power loss in the transformer core reset circuit, the overall power loss is given by (6.98)

Thus, the converter efficiency is (6.99)

6.2.11 DC Voltage Transfer Function of Lossy Converter for CCM The dc component of the input current is (6.100) yielding the dc current transfer function of the forward converter (6.101) This transfer function is the same for both lossless and lossy converters. The converter efficiency can be expressed as (6.102) from which the dc voltage transfer function of the lossy forward converter is (6.103)

From (6.103), the on-duty cycle is

(6.104) The duty cycle D is greater for the lossy converter than that for the lossless converter at a given dc voltage transfer function. Substituting (6.104) into (6.99), one obtains the efficiency for the forward converter in CCM (6.105) where (6.106)

and (6.107)

6.2.12 Design of Forward Converter for CCM Design a PWM forward converter operating in CCM to meet the following specifications: VO = 5 V, IOmin = 2 A, IOmax = 20 A, Vr/VO ≤ 1%, and the input voltage is the US single-phase utility line rectified voltage. Solution: The minimum, nominal, and maximum values of the input voltage are (6.108) (6.109) and (6.110) The minimum, nominal, and maximum values of the dc voltage transfer function are (6.111)

(6.112) and (6.113) The maximum and minimum values of the dc output power are (6.114) and (6.115) The minimum and maximum values of the load resistance are (6.116) and (6.117) Let us assume the switching frequency fs = 100 kHz, the converter efficiency η = 80%, and Dmax ≈ 0.4. The transformer turns ratio is (6.118) Pick n1 = n3 = 8. The minimum, nominal, and maximum values of the duty cycle are (6.119) (6.120) and (6.121) Hence, tm(max)/T = Dmax = 0.3937. The maximum permissible duty cycle is

(6.122) Thus, Dmax < DMAX. The minimum inductance is (6.123) Let L = 20 μH. The maximum peak-to-peak value of the inductor ripple current is (6.124) The ripple voltage is (6.125) The maximum ESR of the filter capacitor is (6.126) Let rC = 25 mΩ. Thus, the filter capacitance is (6.127)

Pick C = 200 μF/16 V/25 mΩ. The corner frequency of the low-pass output filter is (6.128) Hence, fs/fo = 100/2.516 = 39.75. The voltage stresses of the rectifier diodes are (6.129) (6.130)

and the current stresses of these diodes are (6.131) The maximum peak current through the primary of the ideal transformer is (6.132) Assume that the maximum peak current through the magnetizing inductance is less than 10% of the maximum peak current through the primary of the ideal transformer. Thus, (6.133) The minimum magnetizing inductance is then (6.134) Pick Lm = 2 mH. The stresses of the diode D3 are (6.135) and (6.136) The voltage and current stresses of the switch are (6.137) and (6.138) An International Rectifier IRF740 power MOSFET is selected, which has VDSS = 400 V, ISM = 10 A, rDS = 0.55 Ω, Qg(typ) = 41 nC, Qgmax = 60 nC, and Co = 100 pF. Two MBR2540 Schottky barrier diodes are chosen, which has IDM = 25 A, VDM = 40 V, VF = 0.3 V, and RF = 16 mΩ. A fast recovery MR826 diode is selected with VDM = 600 V and IDM(AV) = 5 A. We will calculate power losses for POmax = 100 W and VImin = 127 V. The conduction power loss in the MOSFET is

(6.139) the switching loss is (6.140) Assuming rT1 = 50 mΩ, (6.141) The power loss due to RF in diode D1 is (6.142) the power loss due to VF in diode D1 is (6.143) resulting in the conduction loss in diode D1 (6.144) Assuming rT2 = 10 mΩ, (6.145) Hence, the power loss in both primary and secondary windings is (6.146) The power loss due to RF in diode D2 is (6.147) the power loss due to VF in diode D2 is (6.148) the conduction loss in diode D2 is (6.149) Assuming that the dc ESR of the inductor is rL = 15 mΩ, one obtains the power loss in the inductor ESR

(6.150) the power loss in the capacitor ESR (6.151) the total power loss (6.152) and the efficiency of the converter (6.153) If the magnitude of the gate-to-source voltage is VGSm = 7 V, then the gate-drive power is (6.154) The efficiency η can be calculated from (6.105) through (6.107). Once the efficiency is known, the duty cycle D can be computed from (6.104). Figures 6.8 through 6.13 show the characteristics of the designed forward converter. It can be seen that the efficiency η decreases as IO increases (or RL decreases). The minimum efficiency ηmin occurs at IOmax. The duty cycle D increases as VI decreases and IO increases (or RL decreases). The plots are similar to those of the buck converter.

Figure 6.8 Efficiency η as a function of the dc input voltage VI at RL = 0.25 Ω, 0.5 Ω, and 2.5 Ω for the forward converter in CCM.

Figure 6.9 Duty cycle D as a function of the dc input voltage VI for the forward converter at fixed load resistances RL in CCM.

Figure 6.10 Efficiency η as a function of the dc load current IO at VI = 127 V, 156 V, and 187 V for the forward converter in CCM.

Figure 6.11 Duty cycle D as a function of the dc load current IO at VI = 127 V, 156 V, and 187 V for the forward converter in CCM.

Figure 6.12 Efficiency η as a function of the load resistance RL at VI = 127 V, 156 V, and 187 V for the forward converter in CCM.

Figure 6.13 Duty cycle D as a function of the load resistance RL at VI = 127 V, 156 V, and 187 V for the forward converter in CCM.

6.3 DC Analysis of PWM Forward Converter for DCM Figure 6.14 shows equivalent circuits for the PWM forward converter operating in DCM. Idealized current and voltage waveforms are depicted in Figure 6.15. At time t = 0 when the switch is turned on, the inductor current is zero. For the time interval 0 < t ≤ DT, the switch and the diode D1 are ON, and the diodes D2 and D3 are OFF as shown in Figure 6.14(a). The voltage across the primary is VI and across the secondary is VI/n1. The voltage across the inductor is VI/n1 − VO, causing the inductor current to increase linearly from zero.

Figure 6.14 Equivalent circuits for different time intervals for the forward PWM converter operating in DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ DT + tm. (c) For DT + tm < t ≤ (D + D1)T. (d) For (D + D1)T < t ≤ T. At time t = DT, the switch is turned off, turning the diode D1 off and the diodes D2 and D3 on. The equivalent circuit is shown in Figure 6.14(b) for time interval DT < t ≤ DT + tm. The voltage across the switch is VI. The voltage across the inductor is − VO, causing the inductor current to decrease linearly. The voltage across the magnetizing inductance is vLm = −(n1/n3)VI. Therefore, the current through the magnetizing inductance and the diode D3 decreases linearly. At time t = DT + tm, these two currents reach zero and the diode D3 turns off. The equivalent circuit for the time interval DT + tm < t ≤ (D + D1)T is shown in Figure 6.14(c). The voltage across the inductance L is − VO and therefore the current through this inductance and the diode D2 decreases linearly. At time t = (D + D1)T, the current through the inductor L and the diode D2 reaches zero and the diode D3 turns off. The inductor current remains zero

until the switch is turned on at time t = T. Figure 6.14(d) displays the equivalent circuit for the time interval (D + D1)T < t ≤ T. The voltage across the inductor is zero because its current is zero. At time t = T, the switch is turned on and the inductor current commences to increase from zero.

6.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch and the diode D1 are ON, and the diodes D2 and D3 are OFF. The equivalent circuit is shown in Figure 6.14(a). The switch voltage vS and the diode currents iD2 and iD3 are zero. The voltage across the primary and the magnetizing inductance Lm is (6.155) resulting in the current through the magnetizing inductance (6.156) and the peak current of the magnetizing inductance (6.157) The voltage across the tertiary winding is (6.158) which gives the voltage across the diode D3 (6.159) Since the voltage vD3 is negative, the diode D3 is OFF. The voltage across the secondary is (6.160) and the voltage across the diode D2 is (6.161)

which maintains diode D2 in the OFF state. The voltage across the inductor L is (6.162) and the inductor and switch current is (6.163) resulting in the peak inductor current (6.164)

The current through the primary is (6.165) yielding the current through the switch (6.166)

6.3.2 Time Interval: DT < t ≤ DT + tm The equivalent circuit for this time interval is shown in Figure 6.14(b). The switch and the diode D1 are OFF, and the diodes D2 and D3 are ON. The voltage across the inductor L is (6.167) resulting in the current through the inductor L and diode D2 (6.168)

The peak inductor current is found as

(6.169) The voltage across the tertiary winding is (6.170) which gives the voltage across primary and the magnetizing inductance (6.171) the current through the magnetizing inductance (6.172) the current through the primary (6.173) and the current through the diode D3 (6.174) The voltage across the secondary is (6.175) and the voltage across the diode D1 is (6.176) and the voltage across the switch is (6.177) This time interval ends when the current through the magnetizing inductance and therefore through the diode D3 reaches zero.

6.3.3 Time Interval: DT + tm < t ≤ (D + D1)T

It is assumed that tm < D1T. During this time interval, the switch and the diodes D1 and D3 are OFF, and the diode D2 is ON. The equivalent circuit is shown in Figure 6.14(c). The voltages across the transformer windings and diodes D1 and D2 are vLm = v1 = v2 = v3 = vD1 = vD2 = 0, the currents are iLm = i1 = i2 = iD1 = i3 = iD3 = 0, the voltage across the diode D3 is (6.178) and the voltage across the switch is (6.179) The inductor voltage and current waveforms are given by (6.167) and (6.168). This time interval is terminated when the current through the diode D2 reaches zero.

6.3.4 Time Interval: (D + D1)T < t ≤ T During this time interval, the switch and all the diodes are OFF. The equivalent circuit is shown in Figure 6.14(d). The inductor current iL, the inductor voltage vL, the switch current iS, and the diode currents iD1, iD2, and iD3 are zero. The voltage across the switch is (6.180) the voltages across the diodes D1 and D2 are (6.181) and the voltage across the diode D3 is (6.182) This time interval ends when the switch is turned on by the driver.

6.3.5 DC Voltage Transfer Function for DCM Referring to the inductor voltage waveform in Figure 6.15 and using the volt-second balance, (6.183) which gives the dc-to-dc voltage transfer function (6.184) From (6.164) and (6.184), the peak inductor current is

(6.185)

The dc output current is equal to the average value of the inductor current and from (6.184) and (6.185) can be expressed as (6.186) Using (6.184) and (6.185), (6.187) Solving for D gives (6.188) At the boundary between CCM and DCM, (6.189) as in CCM. Substitution of this into (6.188) yields the duty cycle DB at the boundary (6.190) Figures 6.16 and 6.17 show plots of D versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of n1MV DC and n3 = n1 for the lossless forward converter, respectively.

Figure 6.15 Waveforms in the PWM forward converter for DCM.

Figure 6.16 Duty cycle D as a function of IO/(VO/2fsL) at constant values of n1MV DC and n3 = n1 for the lossless forward converter.

Figure 6.17 Duty cycle D as a function of RL/(2fsL) at constant values of n1MV DC and n3 = n1 for the lossless forward converter. From (6.188), (6.191) which yields the dc-to-dc voltage transfer function of the forward converter for DCM (6.192)

It can be seen that MV DC depends on D, RL, L, and fs for DCM. Figures 6.18 and 6.19 show plots of n1MV DC versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of D and n3 = n1 (i.e., DMAX = 0.5) for the lossless forward

converter, respectively.

Figure 6.18 n1MV DC as a function of RL/(2fsL) at constant values of D for the lossless forward converter for n3 = n1.

Figure 6.19 n1MV DC as a function of RL/(2fsL) at constant values of D for the lossless forward converter for n3 = n1. From (6.184) and (6.192), (6.193) Neglecting the current through the magnetizing inductance iLm, that is, iLm i1, the converter input current iI is equal to the current through the primary i1 for 0 < t ≤ DT (6.194) yielding the average value of the converter input current

(6.195)

and the dc input power (6.196)

The dc output power is (6.197) The converter efficiency is (6.198) Rearrangement of this equation gives the duty cycle of the lossy forward converter for DCM (6.199) and the voltage transfer function (6.200)

6.3.6 Maximum Inductance for DCM The waveforms of the inductor current iL at the boundary between the DCM and CCM at the minimum input voltage VImin and at the maximum input voltage VImax are depicted in Figure 6.20. The minimum value of the inductor peak current at the boundary between CCM and DCM occurs at DB = DBmax and can be obtained from (6.21) as (6.201) The dc output current at the boundary between the CCM and DCM IOB is equal to the maximum load current IOmax and is given by

(6.202) Thus, the maximum inductance required to maintain the converter operation in DCM is (6.203) where (6.204)

Figure 6.20 Waveforms of the inductor current at the boundary between DCM and CCM for VImin and VImax.

6.3.7 Power Losses and Efficiency of Forward Converter for DCM The peak inductor current is (6.205) The rms switch current is (6.206)

resulting in MOSFET conduction power loss

(6.207)

The switching loss is (6.208) The power loss in the MOSFET is (6.209)

The power loss in the winding resistance of the primary is (6.210)

The rms value of the current through diode D1 is (6.211)

yielding the power loss in the forward resistance of D1 (6.212) The average current through diode D1 is (6.213) resulting in the power loss in VF of D1 (6.214) Hence, the power loss in diode D1 is

(6.215)

The power loss in the winding resistance of the secondary is (6.216) The winding power loss in both primary and secondary is given by (6.217)

The rms value of the current through the diode D2 is (6.218)

yielding the power loss in RF of D2 (6.219) The average current through diode D2 is (6.220) which leads to the power loss in VF of diode D2 (6.221) Hence, the conduction power loss in diode D2 is (6.222)

The rms value of the inductor current is

(6.223)

yielding the power loss in the inductor winding (6.224) The total converter power loss is (6.225)

The efficiency of the forward converter for DCM is given by (6.226)

6.3.8 Design of Forward Converter for DCM Design a universal PWM forward converter operating in DCM to meet the following specifications: VO = 5 V, IOmin = 0 A, IOmax = 20 A, Vr/VO ≤ 10%, and the input voltage is the single-phase utility line rectified voltage anywhere in the world whose rms voltage is in the range from 85 to 264 Vrms. Solution: The minimum and maximum values of the dc input voltage are (6.227) and (6.228) The minimum and maximum values of the dc voltage transfer function are (6.229)

and (6.230) The maximum value of the dc output power is (6.231) The minimum load resistance is (6.232) Let us assume the switching frequency fs = 100 kHz, the converter efficiency η = 80%, and Dmax ≈ 0.4. In this case, the transformer turns ratio is (6.233) Pick n1 = n3 = 8. The maximum permissible duty cycle is (6.234) Thus, Dmax < DMAX. The minimum and maximum values of the duty cycle at the CCM/DCM boundary are (6.235) and (6.236) The maximum inductance is (6.237) Pick a standard inductance L = 0.56 μH. The maximum duty cycle at VI = VImin = 120 V and RLmin is

(6.238)

resulting in (6.239) and hence (6.240) The minimum inductor current is (6.241)

The minimum duty cycle at VI = VImax = 373 V and RLmin is (6.242)

which gives (6.243) producing (6.244) The maximum inductor current is (6.245)

The ripple voltage is (6.246) The maximum ESR of the filter capacitor is (6.247) Let rC = 7 mΩ. Thus, the filter capacitance is

(6.248)

Pick C = 1 mF/16 V/7 mΩ. The current and voltage stresses of the rectifier diodes are (6.249) (6.250) and (6.251) The maximum peak current through the primary of the ideal transformer (6.252) and the maximum peak current through the magnetizing inductance is (6.253) producing the minimum magnetizing inductance (6.254) The current and voltage stresses of the switch are (6.255) and (6.256) The current and voltage stresses of diode D3 are (6.257) and

(6.258) A Cree SiC CMF20120D power MOSFET is selected, which has VDSS = 1200 V, ISM = 42 A, rDS = 80 mΩ, TJmax = 125°C, junction-to-case thermal resistance θJC = 0.51 K/W, and TO2473 package. Two MBR2540 Schottky barrier diodes are also chosen for D1 and D2, which has IDM = 25 A, VDM = 40 V, VF = 0.3 V, and RF = 16 mΩ. A Cree C2d05120a SiC Schottky diode is selected for D3, which has VDM = 1.2 kV and IDM = 5 A. The power losses will be calculated for full load RLmin = 0.25 Ω and the maximum input voltage VImax = 373 V. The MOSFET conduction power loss is (6.259)

The switching loss is (6.260) The power loss in the MOSFET is (6.261) Assuming rT1 = 0.05 Ω, the power loss in the winding resistance of the primary is given by (6.262)

The power loss in the forward resistance of diode D1 is (6.263)

and the power loss in VF of diode D1 is (6.264) resulting the conduction loss in diode D1

(6.265) Assuming rT2 = 0.01 Ω, the power loss in the winding resistance of the secondary is (6.266)

The winding power loss in both primary and secondary is given by (6.267) The power loss in the forward resistance RF of D2 is (6.268)

The power loss in VF of diode D2 is (6.269) Hence, the conduction power loss in diode D2 is (6.270) Assuming rL = 0.015 Ω, the power loss in the inductor winding resistance is (6.271)

The total converter power loss is (6.272) The efficiency of the forward converter is (6.273) Figures 6.21 through 6.26 show the characteristics of the designed forward converter for DCM. The lowest efficiency η occurs at IOmax and VImax. The duty cycle D decreases as VI increases and IO decreases (or RL increases).

Figure 6.21 Efficiency η as a function of the dc input voltage VI at various load resistances RL for the forward converter in DCM.

Figure 6.22 Duty cycle D as a function of the dc input voltage VI at various load resistances RL for the forward converter in DCM.

Figure 6.23 Efficiency η as a function of the dc load current IO at various dc input voltages VI for the forward converter in DCM.

Figure 6.24 Duty cycle D as a function of the dc load current IO at various dc input voltages VI for the forward converter in DCM.

Figure 6.25 Efficiency η as a function of the load current IO at various dc input voltages VI for the forward converter in DCM.

Figure 6.26 Duty cycle D as a function of the load resistance RL at various dc input voltages VI for the forward converter in DCM.

Figure 6.27 Multiple-output forward converter.

6.4 Multiple-Output Forward Converter Figure 6.27 shows a two-output forward converter. In order to obtain the second output, the transformer has an extra secondary winding, which drives an additional rectifier composed of two diodes, an inductor, and a filter capacitor. More outputs can be obtained by adding more secondaries, rectifiers, and low-pass filters. Usually, only one output is controlled and other outputs are not regulated. If the dc input voltage VI is increased, the duty cycle D is decreased by the feedback network of the controlled output. Nearly the same decrease in D is also required by the unregulated outputs, maintaining the output voltages close to the required values. However, the load resistances may change in the direction opposite to that of the regulated output, causing variations of the output voltages. This is especially true for DCM operation, in which the output voltage is heavily dependent on the load resistance. Interactions between multiple outputs is called cross-regulation.

6.5 Forward Converter with Synchronous Rectifier Synchronous rectifiers are attractive in low output voltage applications (e.g., 1.8 or 3.3 V),

where Schottky diodes may be replaced by low on-resistance MOSFETs, as shown in Figure 6.28. In the self-driven architecture shown in Figure 6.28(a), the MOSFETs are driven by the transformer output voltage. The transistor gates are connected to the opposite ends of the secondary winding, and the gate of each device is connected to the drain of another device. The rectifier MOSFETs are automatically synchronized to the main switch. The benefits of this topology are simplicity and low parts count. In the circuit of Figure 6.28(b), the MOSFETs are driven by an IC driver, which is normally a part of an IC control circuit. The transformer in the driver and the transformer in the power stage ensure dc isolation between the converter input and the output. Unlike diodes, MOSFETs do not have offset voltages. Low-voltage MOSFETs exhibit very low on-resistances, for example, 5 mΩ, yielding low conduction loss and high efficiency. Since MOSFETs can conduct current in both directions, the transformer reset circuit is not needed. A converter with a synchronous rectifier may operate only in CCM.

Figure 6.28 Forward converters with synchronous rectifier. (a) With self-driven MOSFETs. (b) With IC driver of all MOSFETs.

6.6 Forward Converters with Active Clamping A forward converter with three active clamping and core reset circuits is shown in Figure 6.29 [17]. The clamping circuit of Figure 6.29(a) is connected across the transformer primary. The main transistor Q1 is driven with the duty cycle D and the clamp transistor is driven with the duty cycle 1 − D. This circuit is called the high-end n-channel active clamp. The MOSFET Q2 carries only the transformer magnetizing current, which has a small peak value compared to the reflected load current. Therefore, Q2 may have a much lower current rating than that of Q1. A dead time is required between the time Q1 is turning off and the time Q2 is turning on. During the dead time, the primary current flows through the body diode of either MOSFET. This is a resonant time interval in which zero-voltage switching (ZVS) occurs. Neglecting the voltage drop across the leakage inductance, the voltage across the clamping capacitor Cc is (6.274) Therefore, it is also called the boost type clamp. The voltage across the main switch Q1 is given by (6.275) The clamping circuit of Figure 6.29(b) is connected in parallel with the main switch. It is called the low-end n-channel active clamp. Neglecting the voltage drop across the leakage inductance, the voltage across the clamping capacitor Cc is (6.276) Therefore, it is also called the buck–boost type clamp. The voltage across the main switch Q1 is given by (6.275). The clamping circuit of Figure 6.29(c) is called the low-end p-channel active clamp. It uses a p-channel MOSFET. There is no need for the transformer reset circuit in all three circuits.

Figure 6.29 Forward converters with active clamping. (a) High-end n-channel active clamping. (b) Low-end n-channel active clamping. (c) Low-end p-channel active clamping.

6.7 Two-Switch Forward Converter A two-transistor forward converter is shown Figure 6.30. Both transistors are ON simultaneously during the time interval 0 < t ≤ DT and are OFF during the reminder of the cycle. During the interval 0 < t ≤ DT, the voltage across the primary winding is VI, the current through the magnetizing inductance Lm flows through both transistors, and it increases with slope VI/Lm. After the transistors are turned off, the magnetizing inductance is demagnetized by diodes D1 and D2, the voltage across the primary winding is − VI, the current of the magnetizing inductance Lm decreases to zero at time t = DT + tm with slope − VI/Lm, and the energy stored in the magnetizing inductance Lm is returned to the input voltage source VI. The magnetizing current is reset to zero before the beginning of the next cycle. The condition of a complete demagnetization of the core is tm ≤ 1 − D. When the magnetizing current decrease

gradually and reaches zero, both demagnetization diodes turn off at zero current. Therefore, the duty cycle must be held in the range 0 < D < 0.5. There is no need for a core reset circuit, which usually consists of a separate winding and a diode. The rectifier circuit on the secondary side of the transformer is identical to that of the single-transistor forward converter. The horizontal rectifier diode conducts when both transistors are ON, and the freewheeling diode conducts when both transistors are OFF. The dc voltage transfer function for CCM is (6.277) The two-switch forward converter has reduced ringing. The peak voltage across the switches is VSM = VI, which is much lower than that of a single-switch forward converter. The voltage rating of the switch in a single-switch forward converter is VSM = VI(1 + n1/n3). However, the circuit requires a floating gate drive for the high side transistor.

Figure 6.30 Two-transistor forward converter.

6.8 Forward–Flyback Converter In a conventional forward converter, the diode D3 in the core flux reset circuit is connected to the dc input voltage source VI, as shown in Figure 6.1(d). In this circuit, the energy stored in the magnetic field of the transformer is transferred to the input dc source VI. Figure 6.31 shows a forward converter, in which the diode D3 of the core reset circuit is connected to the output filter capacitor C and the load resistor RL [13]. Therefore, the energy stored in the magnetic

field of the transformer is transferred to the filter capacitor and the load. The maximum value of the magnetic filed density is (6.278) Figure 6.32 depicts a two-switch forward–flyback converter [19]. In this circuit, the voltage stress across the switches is reduced. It is VSMmax = VImax.

Figure 6.31 Single-transistor forward–flyback converter.

Figure 6.32 Two-transistor forward–flyback converter [19].

6.9 Summary The PWM forward converter can be derived from the buck converter by adding a transformer, a diode, and a transformer core reset circuit. Therefore, it belongs to the family of buck-derived converters. The PWM forward converter provides dc isolation between the input and the output. The transformer allows the forward converter to obtain much lower and much higher values of the dc voltage transfer function than those of the buck converter. The forward converter is a step-down or a step-up converter. If the number of turns of the primary and tertiary is the same, the voltage stress on the transistor is twice the dc input voltage and the duty cycle D must be less than 0.5 in the forward converter. The typical power level of the forward converter is from 30 to 500 W. The transistor is driven with respect to ground in the forward converter. The magnetizing inductance of the transformer is not required to store energy. The forward converter requires a transformer core reset circuit. The maximum duty cycle in the forward converter is less than 100% to allow for core reset. The magnetic core utilization is poor in the forward converter because a dc current flows through the primary.

The forward converter can operate in two modes: CCM or DCM. The dc voltage transfer function of the lossless forward converter is MV DC = D/n1. The duty cycle D of the lossy converter is greater than that of the lossless converter at the same dc voltage transfer function. The peak-to-peak value of the inductor current ripple ΔiL is independent of the dc load current for CCM. The peak-to-peak value of the current through the filter capacitor C is equal to the peak-topeak inductor current ripple ΔiL. The peak-to-peak ripple current through the filter capacitor decreases as the inductance L increases. If the capacitance of the filter capacitor is sufficiently high, the output ripple voltage is determined only by the ESR of the filter capacitor and is independent of the capacitance of the filter capacitor. The minimum value of the inductance L is determined by the boundary between CCM and DCM, ripple of the output voltage, or ac losses in the inductor and/or the filter capacitor. A disadvantage of the forward converter is that the input current is pulsating. However, a nonpulsating input current waveform can be obtained by inserting an input LC filter between the input dc source and the transistor. The corner frequency of the output filter resistance.

is independent of the load

For the forward converter operating in CCM and DCM, the minimum efficiency occurs at the maximum load current IOmax (or RLmin) and a high efficiency occurs at light loads. The two-switch forward converter has a reduced voltage stress of the MOSFETs and does not require a separate core reset circuit.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. 3. K. K. Sum, Switching Power Conversion. New York: Marcel Dekker, 1984. 4. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984.

5. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 6. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 7. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood Cliffs, NJ: Prentice Hall, 2004. 8. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 9. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 10. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. 11. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 12. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 13. J. N. Park and T. R. Zaloun, “A dual mode forward flyback converter,” IEEE PESC, 1982, pp. 3–13. 14. J. Sebastian, J. Uceda, M. Rico, M. A. Pérez, and F. Aldana, “A complete study of the double forward-flyback converter,” IEEE Power Electronics Specialists Conference, 1988, pp. 142–149. 15. H. E. Tacca, “Single-switch two-output flyback-forward converter operation,” IEEE Transactions on Power Electronics, vol. 13, no. 5, pp. 903–911, September 1998. 16. Y.-M. Liu and L.-K. Chabg, “Single-stage soft-switching AC-DC converter with inputcurrent shaping for universal line applications,” IEEE Transactions on Industrial Electronics, vol. 56, no. 2, pp. 467–479, February 2009. 17. B. Carsten, “Design techniques for transformer active reset circuits and high frequencies at power levels,” Proceedings of the High Frequency Power Conversion, 1990, pp. 235–246. 18. I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004. 19. D. Murthy-Bellur and M. K. Kazimierczuk, “Two-switch flyback-forward PWM dc-dc converter with reduced switch voltage stress,” Proceedings of the IEEE International Symposium on Circuits and Systems, Paris, France, May 31–June 2, 2010, pp. 3705–3707.

Review Questions 1. Does the forward PWM converter provide dc isolation between the input and the output?

2. Does the forward converter require a transformer core reset circuit? Explain its operation. 3. What is the range of the duty cycle in the forward converter? 4. Is the forward converter a step-down or a step-up converter? 5. Is the transformer required to store energy in the forward converter? 6. Is the input current of the basic forward converter pulsating? 7. How can the forward converter circuit be modified to obtain a nonpulsating input current? 8. Is the transistor drive circuit floating with respect to ground in the forward converter? 9. How is the dc voltage transfer function MV DC related to the duty cycle D of the lossless forward converter for CCM? 10. Is the duty cycle D of the lossy forward converter lower or greater than that of the lossless converter at a given value of MV DC for CCM? 11. Is the corner frequency of the output filter dependent on the load resistance in the forward converter? 12. Is it possible to obtain a negative output voltage in the forward converter? If so, draw a circuit of such a converter. 13. Is it possible to obtain multiple-output forward converter? If so, draw the circuit of such a converter. 14. Is it possible to control all the outputs in the forward converter? 15. What is the typical output power range of the forward converter? 16. Is the efficiency high at heavy or light loads for the forward converter?

Problems 1. For the forward PWM converter, find the maximum duty cycle DMAX. (a) For n3 = 0.5n1. (b) For n3 = 2n1. (c) For n3 = 4n1. 2. For the forward PWM converter, find the switch peak voltage in terms of the dc input voltage VI. (a) For n3 = 0.5n1. (b) For n3 = 2n1. (c) For n3 = 4n1. 3. For the forward PWM converter, find the peak voltage of the diode D3 connected in series with the tertiary in terms of the dc input voltage VI. (a) For n3 = 0.5n1. (b) For n3 = 2n1. (c) For n3 = 4n1. 4. A forward PWM converter is supplied by a European single-phase rectified utility line voltage and VO = 12 V. Find the primary-to-secondary transformer turns ratio n1. 5. A forward PWM converter is supplied by a European single-phase rectified utility line

voltage, VO = 12 V, and n1 = 8. Find the maximum permissible duty cycle DMAX. 6. A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VO = 12 V, and n1 = n3 = 8. Find the minimum, nominal, and maximum duty cycle. 7. A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VImax = 342 V, VO = 12 V, and n1 = n3 = 8. Find the voltage stresses of the semiconductor devices. 8. A forward PWM converter has VO = 12 V, IO = 4–40 A, n1 = n3 = 8, VImax = 342 V, η = 90%, and fs = 75 kHz. Find the minimum inductance required for the CCM operation. 9. A forward PWM converter has VO = 12 V, IO = 4–40 A, the duty cycle Dmin = 0.3119, L = 20 μH, Dmin = 0.3119, fs = 75 kHz, and Vr/VO ≤ 1%. Find the filter capacitance and the corner frequency of the output filter. 10. A forward PWM converter has VO = 12 V, IO = 4–40 A, L = 20 μH, Dmin = 0.3119, and fs = 75 kHz. Find the current stresses of the rectifier diodes. 11. A forward PWM converter has VO = 12 V, IO = 4–40 A, n1 = n3 = 8, L = 20 μH, VImax = 342 V, Dmin = 0.3119, and fs = 75 kHz. Find the magnetizing inductance such that its peak current is less than 12% of the maximum peak current of the primary of the ideal transformer. 12. A forward PWM converter is supplied by a European single-phase rectified utility line voltage, VO = 12 V, IO = 4–40 A, n1 = n3 = 8, L = 20 μH, and fs = 75 kHz. Find the current stress of the switch. 13. For a forward PWM converter supplied by a European single-phase rectified utility line voltage, determine the maximum inductance required for DCM operation, if VO = 12 V, IO = 0–4 A, n1 = n3 = 8, and fs = 75 kHz. 14. Design a PWM forward converter that will meet the following specifications: the CCM, VI is the European single-phase rectified line voltage with Vrms = 220 V± 10%, VO = 14 V, IOmin = 2 A, IOmax = 20 A, and Vr/VO ≤ 1%. Assume rDS = 1 Ω, VF = 0.56 V, RF = 25 mΩ, rL(dc) = 20 mΩ, rT1 = 100 mΩ, rT2 = 25 mΩ, Co = 100 pF, Lm = 5 mH, and fs = 100 kHz. Find component values, component stresses, and converter efficiency. 15. Design a PWM forward converter with VI = 48±6 V, VO = 5 V, IO = 2–20 A, fs = 50 kHz, Vr/VO ≤ 1%, and ΔiLm(max)/I1max ≤ 10%. Find L, Lm, C, rC, n1, n3, Dmin, Dmax, DMAX, VSMmax, ISMmax, VD1Mmax, ID1Mmax, VD2Mmax, ID2Mmax, VD3Mmax, ID3Mmax, and η. Assume the CCM, rDS = 0.18 Ω, VF = 0.4 V, RF = 20 mΩ, rL(dc) = 20 mΩ, rT1 = 50 mΩ, rT2 = 15 mΩ, and Co = 200 pF. 16. A PWM forward converter has VI = 24–32 V, IO = 2–20 A, VO = 18 V, and fs = 150 kHz.

Find L, C, n1, n3, Dmin, Dmax, DMAX, VSMmax, ISMmax, ID1Mmax, VD1Mmax, and VD3Mmax. 17. Draw a circuit of a multiple-output dc–dc forward converter with VO1 = 3.3 V, VO2 = 12 V, and VO3 = −12 V.

7 Half-Bridge PWM DC–DC Converter 7.1 Introduction The half-bridge PWM dc–dc converter [1–12] contains two transistors, a transformer, and a rectifier. Its main advantage is that the voltage stresses of the transistors are low and equal to the maximum dc input voltage of the converter. It can handle the rectified dc voltage of the European 220 Vrms + 10% utility single-phase line, which usually ranges from 280 to 340 V. Power transistors with a 400-to-500 V voltage rating are readily available and may be used in this converter; therefore, the half-bridge converter is used in off-line power supplies. Another advantage is that the core saturation problems are minimized because the dc component of the current through the primary is zero due to the coupling or blocking capacitors in series with the primary. Since the primary is driven in both directions, the core is utilized more effectively. The disadvantages are the requirement of an additional power transistor and an isolated driver for the upper transistor. Typically, the converter is suitable for medium and high power applications ranging from 150 W to 1 kW and is widely used in telecommunication power supplies. It belongs to the family of buck-derived converters. The purpose of this chapter is to present an analysis and a design procedure for the half-bridge PWM converter.

7.2 DC Analysis of PWM Half-Bridge Converter for CCM 7.2.1 Circuit Description A circuit of the PWM half-bridge dc–dc converter is depicted in Figure 7.1(a). The converter consists of a PWM inverter and a PWM rectifier. The inverter consists of two power MOSFETs used as controllable switches S1 and S2, a transformer, and two blocking capacitors Cb. The isolation transformer does not have to store energy. Its magnetizing inductance should be large enough to reduce the current through this inductance and the switches. Because of the blocking capacitors, the dc current through the primary of the transformer is zero, resulting in excellent core utilization. In addition, the core is operated in a bipolar mode because the primary winding is driven in both directions from VI/2 to − VI/2; therefore, the core is utilized more effectively. The core is half the size of equivalent transformers in single-transistor converters, in which magnetic cores are operated in unipolar mode. Therefore, the half-bridge converter provides a cost advantage over its single-transistor counterparts.

Figure 7.1 Half-bridge converter with two blocking capacitors. (a) With a transformer centertapped rectifier. (b) With a full-bridge rectifier. (c) With a half-wave rectifier. The transistors are driven by nonoverlapping voltages that are out of phase by 180°. The maximum duty cycle of gate-to-source voltages is slightly less than 50% to avoid the situation, when both transistors are conducting at the same time. In this case, the dc input voltage VI is connected to the ground through two on-resistances of the MOSFETs, generating a very large current spike and destroying the transistors. For example, if dc input voltage is VI = 340 V and the MOSFET on-resistance is rDS = 1 Ω, then the peak current through the MOSFETs is Ipk = VI/(2rDS) = 340/2 = 170 A. The phenomenon when both transistors are conducting at the same time is called a cross conduction, and the current through the transistors is called a shootthrough current. The switching network of the inverter has two transistors in series (a totem pole arrangement), resulting in difficulty in driving the high-end (upper) transistor because its gate is not referenced to ground. A small wide bandwidth (pulse) transformer is normally used to drive the upper transistor to achieve a square-wave gate-to-source voltage. A second pulse transformer is usually added to drive the bottom transistor. This driver provides dc isolation in

the control path. DC isolation is required in the power stage and the control circuit to accomplish a dc isolation between the input and the output of a dc–dc converter. Pulse transformers also provide protection of a control circuit against high-voltage breakdown. The transistor may be broken in such a way that there is a short circuit between the transistor drain and gate, and a high voltage VI appears at the transistor gate. If the control circuit is directly coupled to the gate, a high voltage is applied across the control circuit output, destroying the control circuit. However, if a control circuit is coupled to the gate through a pulse transformer, the control circuit will not be damaged by a high voltage at the transistor gate. Assuming that both blocking capacitors Cb are identical, the voltage drop across each of them is VI/2. These are usually large electrolytic capacitors with very large tolerances, for example, –20% and +100%; therefore, the voltage drops across them may be different from VI/2. To make these voltages closer to each other, large balance resistors Rb of the order of 100 kΩ to 1 MΩ may be connected in parallel with the blocking capacitors. If the front-end rectifier is a voltage doubler, its filter capacitors can be used as the blocking capacitors Cb. The dc current through the primary of the transformer is zero because of the blocking capacitors Cb. However, this property is lost if resistors are connected in parallel with the blocking capacitors Cb. The half-bridge converter may employ the following rectifiers: a transformer center-tapped rectifier shown in Figure 7.1(a), a bridge rectifier depicted in Figure 7.1(b), or a half-wave rectifier with a freewheeling diode shown in Figure 7.1(c). Full-wave rectifiers (i.e., centertapped and bridge rectifiers) are more suitable because the voltage across the primary winding changes in both directions, from VI/2 to − VI/2. The transformer center-tapped rectifier consists of two diodes D1 and D2, an inductor L, a filter capacitor C, and a load resistor RL. It is most suitable for low-voltage applications because only one diode conducts while it carries the entire inductor current. Schottky diodes or low on-resistance power MOSFETs can be used as rectifying devices. The voltage stress of the diodes is high, equal to VI/n, and makes the centertapped rectifier unsuitable for high-voltage applications. In contrast, the bridge rectifier is suitable for high-voltage applications because the voltage stress of the diodes is low, equal to VI/(2n), which is half of that in the center-taped rectifier. This rectifier is not suitable for low-voltage applications because two diodes conduct at the same time and the total forward voltage across the two diodes becomes comparable with the output voltage. As a result, the efficiency is poor at a low output voltage VO. To eliminate the dc current through the primary winding, a nonelectrolytic coupling capacitor Cc (2–10 μF) may be connected in series with the primary winding, as shown in Figure 7.2. The voltage across Cc is the average voltage across the bottom switch which is equal to VI/2. For the ac component, the dc input source VI in the converter of Figure 7.1(a) behaves similar to a short circuit and the two blocking capacitors are connected in parallel, resulting in the converter circuit shown in Figure 7.2(a), where Cc = 2Cb.

Figure 7.2 Half-bridge converter with a single coupling capacitor Cc. (a) With a transformer center-tapped rectifier. (b) With a bridge rectifier. (c) With a half-wave rectifier.

7.2.2 Assumptions Analysis of the half-bridge PWM converter with a transformer center-tapped rectifier, shown in Figure 7.1(a), is based on the following assumptions: 1. The power MOSFETs and the diodes are ideal switches. 2. Capacitances and lead inductances of the transistors and the diodes are zero. 3. The transformer is modeled by an ideal transformer and its magnetizing inductance Lm. Leakage inductances and stray capacitances are neglected. 4. Passive components are linear, time invariant, and frequency independent. 5. The output impedance of the input voltage source VI is zero for both dc and ac components.

7.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switch S1 and the diode D1 are ON and the switch S2 and the diode D2 are OFF. An ideal equivalent circuit for this time interval is shown in Figure 7.3(a). The voltage across the switch S2 is (7.1) The voltage across the primary and the magnetizing inductance Lm is (7.2) Hence, the current through the magnetizing inductance Lm is (7.3) where iLm(0) is the initial current through the magnetizing inductance Lm at t = 0; this current is negative. The peak-to-peak ripple current through Lm is (7.4) Consequently, (7.5)

(7.6) and (7.7) From (7.4), (7.8) from which (7.9)

Note that DVI = DminVImax = DmaxVImin is constant if the output voltage VO is held constant.

Figure 7.3 Equivalent circuit of the half-bridge converter with a transformer center-tapped rectifier for CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ T/2. (c) For T/2 < t ≤ T/2 + DT. (d) For T/2 + DT < t ≤ T. The output voltages of the transformer are (7.10) The voltage across the diode D2 is (7.11) The negative diode voltage keeps the diode reverse biased, as originally assumed. The voltage across the inductor L is given by

(7.12) Hence, one obtains the current through the inductor L (7.13) where iL(0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes (7.14) and the peak-to-peak value of the current ripple through the inductor L is (7.15)

where VI = nVO/D as will be shown shortly. The current through the primary of the transformer is (7.16) and the current through the switch is (7.17) Current and voltage waveforms in the half-bridge converter for CCM are depicted in Figure 7.4.

Figure 7.4 Waveforms in the half-bridge converter with a transformer center-tapped rectifier for CCM.

7.2.4 Time Interval: DT < t ≤ T/2 Figure 7.3(b) shows an equivalent circuit of the converter for the time interval DT < t ≤ T/2, during which both switches are OFF and both diodes are ON. Assuming that the off-resistances of the switches are the same, the voltages across both switches are (7.18) As a result, the voltage across the primary winding and the magnetizing inductance Lm is (7.19) resulting in the current through the magnetizing inductance

(7.20) and the current through the primary (7.21) The currents through both secondary windings are equal in magnitude, but flow in the opposite direction, resulting in zero magnetic flux; therefore, the voltages across the transformer secondary windings are (7.22) Hence, both rectifier diodes are on. The voltage across the inductor L is (7.23) and the inductor current is (7.24) Assuming that the rectifier circuit is symmetrical, the inductor current is divided equally between the diodes (7.25)

7.2.5 Time Interval: T/2 < t ≤ T/2 + DT Figure 7.3(c) shows an equivalent circuit of the converter for the time interval T/2 < t ≤ T/2 + DT, during which the switch S1 and the diode D1 are OFF and the switch S2 and the diode D2 are ON. The voltage across the switch S1 is (7.26) The voltage across the primary and the magnetizing inductance Lm is (7.27) and the current through the magnetizing inductance is (7.28)

The voltages at the transformer secondaries are (7.29) The voltage across the diode D1 is (7.30) The voltage across the inductor L is (7.31) Hence, the current through the bottom transformer winding, the diode D2, and the inductor L is obtained as (7.32) Hence, the current through the primary is (7.33) The current through the switch S2 is (7.34)

7.2.6 Time Interval: T/2 + DT < t ≤ T An equivalent circuit of the converter for the time interval T/2 + DT < t ≤ T is shown in Figure 7.3(d). Both switches are OFF and both diodes are ON during this time interval. The equivalent circuit for this time interval is the same as that of Figure 7.3(b). Therefore, the analysis of the converter is the same as that given in Section 7.2.4.

7.2.7 Device Stresses The maximum value of the voltage of each switch is (7.35) and the maximum peak current of each switch is

(7.36) The maximum peak value of the voltage across each diode in the transformer center-tapped rectifier is (7.37) and in the full-bridge rectifier is (7.38) The average value of the inductor current is equal to the dc output current IO. Hence, one arrives at the peak current of each diode (7.39)

7.2.8 DC Voltage Transfer Function of Lossless Half-Bridge Converter for CCM Referring to Figure 7.4, (7.40) resulting in the dc voltage transfer function of the lossless converter (7.41) The range of MVDC is (7.42) For the lossless converter, the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI. Rearrangement of (7.41) gives VI = nVO/D. Hence, from (7.15), (7.43) The sensitivity of the output voltage with respect to the duty cycle is

(7.44) The dc current transfer function is (7.45) As D is increased from 0 to 0.5, MIDC decreases from ∞ to 2n. From (7.35), (7.36), and (7.41), the switch and the diode utilization in the half-bridge converter is characterized by the output-power capability (7.46) As D is increased from 0 to 0.5, cp increases from 0 to 0.5.

7.2.9 Boundary Between CCM and DCM The waveform of the inductor current at the boundary between the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) is shown in Figure 7.5 and is given by (7.47) from which (7.48) This gives the maximum peak value of the inductor current at the CCM/DCM boundary (7.49)

The dc output current at the boundary between CCM and DCM is (7.50)

Hence, the load resistance at the CCM/DCM boundary is (7.51) Thus, one obtains at the minimum value of the inductance L

(7.52)

Figures 7.6 and 7.7 show the normalized load current IOB/(VO/2fsL) = (0.5 − D) and the normalized load resistance RLB/(2fsL) = 1/(0.5 − D) as functions of duty cycle D at the boundary between CCM and DCM for the half-bridge converter, respectively.

Figure 7.5 Waveforms of the inductor current in the half-bridge converter at the boundary between CCM and DCM.

Figure 7.6 Normalized load current IOB/(VO/2fsL) = (0.5 − D) as a function of duty cycle D at the boundary between CCM and DCM for the half-bridge converter.

Figure 7.7 Normalized load resistance RLB/(2fsL) as a function of duty cycle D at the boundary between CCM and DCM for the half-bridge converter.

7.2.10 Ripple Voltage in Half-Bridge Converter for CCM The analysis of the ripple voltage for the half-bridge converter is similar to that of the buck converter. It can be shown that the ripple output voltage is equal to the ripple voltage across the ESR if (7.53) where Dmax ≤ 0.5. If condition (7.53) is satisfied, the peak-to-peak ripple output voltage Vr is expressed by (7.54)

Setting Dmax = 0.5 or Dmin = 0, one obtains the worst case condition for the capacitance at which the ripple is determined by the ESR of the filter capacitor for any value of D (7.55) If condition (7.53) is not met, the peak-to-peak ripple output voltage Vr depends on the voltage across both the filter capacitance and the ESR. The maximum increase of the capacitor charge during each half of the cycle T is (7.56) resulting in the ripple voltage across the capacitance C (7.57) where

is the corner frequency of the output low-pass filter. Hence, (7.58)

The peak-to-peak ripple voltage across the ESR is (7.59) The total ripple output voltage can be approximated by (7.60)

7.2.11 Power Losses and Efficiency of Half-Bridge Converter for CCM Figure 7.8 depicts an equivalent circuit of the half-bridge converter with parasitic components, where rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be determined assuming that the ripple of the inductor current is zero. Therefore, the inductor current can be approximated as (7.61) The current through the switch S1 can be expressed by

(7.62) The rms value of the switch S1 current is (7.63) and the conduction loss in the upper MOSFET is (7.64) If the on-resistances of both the MOSFETs are identical, that is, rDS1 = rDS2 = rDS, the conduction losses in both the MOSFETs are the same, that is, PrDS1 = PrDS2 = PrDS.

Figure 7.8 Equivalent circuit of the half-bridge converter with parasitic resistances to determine component losses. Assuming that the transistor output capacitance Co is linear, the switching loss per transistor is (7.65) Hence, one obtains the total power dissipation in each MOSFET (excluding the drive power) (7.66)

The current through the bottom blocking capacitors is

(7.67)

Hence, the rms value of each blocking capacitor current is (7.68)

The power loss in the ESR rCb of each blocking capacitor is (7.69) The rms value of the current through the primary winding is (7.70)

and the conduction loss in the primary winding resistance is (7.71) The current through the diode D1 can be approximated by (7.72)

leading to its rms value (7.73)

and the power loss in RF

(7.74) The average value of the diode current is (7.75) which gives the power loss associated with the voltage VF (7.76) Thus, the overall diode conduction loss is (7.77) The power loss in the secondary winding resistance rT2 is (7.78) If both secondary winding resistances rT2 and rT3 are equal, then the conduction losses in both output windings are the same, that is, PrT2 = PrT3 = PrT. The rms value of the inductor current is (7.79) and the inductor conduction loss (7.80) The current through the filter capacitor is (7.81)

Hence, using (7.43), one arrives at the rms value of the capacitor current (7.82)

and the power loss in the ESR of the filter capacitor (7.83)

The overall power loss is given by (7.84)

Thus, the converter efficiency is (7.85)

7.2.12 DC Voltage Transfer Function of Lossy Converter for CCM Using (7.62), the dc component of the input current can be found as (7.86) This produces the dc current transfer function of the half-bridge converter (7.87) This equation is valid for both lossless and lossy converters. The converter efficiency can be expressed as (7.88) from which the voltage transfer function of the lossy half-bridge converter is

(7.89)

Hence, one arrives at the on-duty cycle (7.90) The duty cycle D, at a given dc voltage transfer function, is greater for the lossy converter than for the lossless converter. The switches must be closed for a longer portion of the lossy converter period in order to transfer enough energy to be equal to the required output energy and the converter losses. Substitution of (7.90) into (7.85) gives the efficiency of the half-bridge converter (7.91) where (7.92)

and (7.93)

7.2.13 Design of Half-Bridge Converter for CCM Design a PWM half-bridge converter operating in CCM to meet the following specifications: 110 = 156 V, 90 = 127 V, 132 = 187 V, VO = 5 V, IOmin = 4 A, IOmax = 40 A, and Vr/VO ≤ 1%. Solution: A half-bridge converter with a transformer center-tapped rectifier is selected for the design because the output voltage is low. The maximum and minimum values of the dc output power are

and

(7.94) (7.95)

The minimum and maximum values of the load resistance are (7.96) and (7.97) The minimum, nominal, and maximum values of the dc voltage transfer function are (7.98) (7.99) and (7.100) Assume the converter efficiency η = 75% and the maximum duty cycle is Dmax ≈ 0.4. Hence, the transformer turns ratio is (7.101) Pick n = 7. The minimum, nominal, and maximum values of the duty cycle are (7.102) (7.103) and (7.104) Assume the switching frequency fs = 100 kHz. The minimum inductance required to maintain the converter in CCM is

(7.105)

Let L = 20 μH. An inductance L much larger than Lmin was selected in order to reduce the ripple current through the inductor and thereby the filter capacitance. The maximum ripple of the inductor current is (7.106)

The ripple voltage is (7.107) If the filter capacitance is large enough, Vr = rCmaxΔiLmax and the maximum ESR of the filter capacitor is (7.108) Pick rC = 50 mΩ. The minimum value of the filter capacitance at which the ripple voltage is determined by the ripple voltage across the ESR is (7.109)

Pick C = 47 μF/50 mΩ/16 V. The voltage and current stresses of the diodes are (7.110) and (7.111) The maximum peak value of the current through the ideal transformer primary is (7.112) The maximum peak-to-peak current through the magnetizing inductance should be limited to, say, 10% of I1max, which gives

(7.113) From (7.9), the minimum magnetizing inductance is (7.114) The voltage and current stresses of the power MOSFETs are (7.115) and (7.116) International Rectifier IRF640 power MOSFETs are chosen, which have VDSS = 200 V, ISM = 18 A, rDS = 180 mΩ, Co = 100 pF, and Qg = 43 nF. MBR2545CT Schottky barrier diodes are selected, which have ID(AV)max = 30 A, IFSM = 300 A, VDM = 45 V, VF = 0.27 V, and RF = 13.25 mΩ. The conduction power loss in each MOSFET is (7.117) the switching loss per transistor is (7.118) Assuming that the winding resistance of the primary is rT1 = 20 mΩ and the winding resistances of the transformer on the secondaries are rT2 = rT3 = 5 mΩ, the conduction power losses are (7.119) and (7.120) Assuming that rCb = 50 mΩ, the power loss in the ESR of each blocking capacitor is

(7.121) The diode loss due to RF is (7.122) the diode loss due to VF is (7.123) and the conduction loss in each diode is (7.124) Assuming that the ESR of the inductor is rL = 10 mΩ, (7.125) and the power loss in the ESR of the capacitor is (7.126) Neglecting the MOSFET gate-drive power, the total power loss is (7.127) and the efficiency of the converter is (7.128) If the peak-to-peak gate-to-source voltage is VGSpp = 14 V, the gate drive power per transistor is (7.129) Figures 7.9 and 7.10 depict the efficiency η and the duty cycle D versus the dc input voltage VI at fixed load resistances RL. Plots of the efficiency η and the duty cycle D versus the dc load current IO at various dc input voltages VI are shown in Figures 7.11 and 7.12. Figures 7.13 and 7.14 illustrate the efficiency η and the duty cycle D as functions of the dc load resistance RL at fixed dc input voltages VI. The efficiency η decreases as IO increases (or RL decreases). The minimum efficiency ηmin occurs at IOmax and VImin. The duty cycle D increases as VI decreases

and IO increases (or RL decreases).

Figure 7.9 Efficiency η as a function of dc input voltage VI at fixed load resistances RL for the half-bridge converter in CCM.

Figure 7.10 Duty cycle D as a function of dc input voltage VI at fixed load resistances for the half-bridge converter in CCM.

Figure 7.11 Efficiency η as a function of dc load current IO at fixed dc input voltages VI for the half-bridge converter in CCM.

Figure 7.12 Duty cycle D as a function of dc load current IO at fixed dc input voltages VI for the half-bridge converter in CCM.

Figure 7.13 Efficiency η as a function of load resistance RL at fixed dc input voltages VI for the half-bridge converter in CCM.

Figure 7.14 Duty cycle D as a function of load resistance RL at fixed dc input voltages VI for the half-bridge converter in CCM.

7.3 DC Analysis of PWM Half-Bridge Converter for DCM 7.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switch S1 and the diode D1 are ON and the switch S2 and the diode D2 are OFF. The equivalent circuit is shown in Figure 7.15(a). The switch voltage vS1 and the diode current iD2 are zero. The voltage across the switch S2 is (7.130) The voltage across the primary and the magnetizing inductance is (7.131)

resulting in the current through the magnetizing inductance (7.132) Hence, (7.133)

(7.134)

(7.135) and (7.136)

Figure 7.15 Equivalent circuit of the half-bridge converter with a transformer center-tapped rectifier for DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ (D + D1)T. (c) For (D + D1)T < t ≤ T/2. (d) For T/2 < t ≤ T/2 + DT. (e) For T/2 + DT < t ≤ T/2 + (D + D1)T. The voltages at the output of the transformer are (7.137) which gives the voltage across the diode D2 (7.138) The voltage across the inductor L is (7.139)

and the inductor and switch current is (7.140) Hence, the peak inductor current is (7.141)

The primary current is (7.142) and the current through the upper switch is (7.143) The waveforms in the half-bridge converter for DCM are depicted in Figure 7.16.

Figure 7.16 Waveforms in the half-bridge converter with a transformer center-tapped rectifier for DCM.

7.3.2 Time Interval: DT < t ≤ (D + D1)T The equivalent circuit for this time interval is shown in Figure 7.15(b). Both switches are OFF and both diodes are ON. The voltages across the switches are (7.144) resulting in the transformer voltages (7.145) the voltage across the primary and the magnetizing inductance

(7.146) the current through the magnetizing inductance (7.147) and the current through the primary of the ideal transformer (7.148) The voltage across the inductor L is (7.149) and the inductor current is obtained using (7.141) (7.150)

Therefore, the peak inductor current is found as (7.151) The currents through the diodes are (7.152) This time interval ends when the diode currents iD1 and iD2 reach zero.

7.3.3 Time Interval: (D + D1)T < t ≤ T/2 During this time interval, both switches S1 and S2 and both diodes D1 and D2 are OFF. The equivalent circuit is shown in Figure 7.15(c). The inductor current iL, the inductor voltage vL, the switch currents iS1, iS2 and the diode currents iD1, iD2 are zero. The voltages across the switches are (7.153) the voltages across the transformer windings are

(7.154) and the voltages across the diodes are (7.155) The voltage across the primary and the magnetizing inductance is (7.156) the current through the magnetizing inductance is (7.157) and the current through the primary of the ideal transformer is (7.158) This time ends when the switch S1 is turned on by the driver. The second half of the period is similar to the first one.

7.3.4 DC Voltage Transfer Function for DCM Referring to Figure 7.16 and using the volt-second balance, (7.159) which yields (7.160) From (7.141) and (7.160), the peak-to-peak inductor current is (7.161)

Using (7.160) and (7.161), (7.162) From (7.160), D + D1 = D/(2nMVDC). Substituting this into (7.162), one obtains

(7.163) which gives (7.164) At the boundary between CCM and DCM, the dc voltage transfer function is the same as that in CCM and is given by (7.165) Substitution of this into (7.164) yields the duty cycle DB at the boundary (7.166) Figures 7.17 and 7.18 show plots of D versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of nMVDC for both CCM and DCM for the lossless half-bridge converter.

Figure 7.17 Duty cycle D versus normalized load current IO/(VO/2fsL) at fixed values of nMVDC for CCM and DCM for the lossless half-bridge converter.

Figure 7.18 Duty cycle D versus normalized load resistance RL/(2fsL) at fixed values of nMVDC for CCM and DCM for the lossless half-bridge converter. Rearrangement of (7.164) leads to (7.167) which yields (7.168)

Notice that nMVDC strongly depends on D, RL, L, and fs for DCM. Figures 7.19 and 7.20 display nMVDC versus normalized load current IO/(VO/2fsL) and normalized load resistance

RL/(2fsL) at various values of D for both CCM and DCM for the lossless half-bridge converter.

Figure 7.19 DC voltage transfer function nMVDC versus normalized load current IO/(VO/2fsL) at fixed values of D for CCM and DCM for the lossless half-bridge converter.

Figure 7.20 DC voltage transfer function nMVDC versus normalized load resistance RL/(2fsL) at fixed values of D for CCM and DCM for the lossless half-bridge converter. From (7.160) and (7.168), (7.169)

The dc input current is (7.170)

Hence, the dc input power is

(7.171)

The output power is (7.172) Thus, the converter efficiency is (7.173) Hence, one obtains the duty cycle for the lossy half-bridge converter in DCM (7.174) and the voltage transfer function for the lossy half-bridge converter in DCM (7.175)

7.3.5 Maximum Inductance for DCM Figure 7.21 shows the waveforms of the inductor current at the boundary between CCM and DCM for VImin and VImax. The minimum peak value of the inductor current at the boundary occurs for VI = VImin, which corresponds to D = DBmax, and is described by (7.176)

The dc output current at the boundary is equal to the maximum output current given by (7.177)

which yields (7.178)

Figure 7.21 Waveforms of the inductor current at the boundary between CCM and DCM in the half-bridge converter for VImin and VImax.

7.4 Summary The PWM half-bridge converter is a step-down or a step-up converter. The dc voltage transfer function of the lossless converter is MVDC = D/n. The voltage transfer function of the half-bridge converter is proportional to the duty cycle like in the buck converter; therefore, the converter belongs to the family of buck-derived converters. The maximum value of the duty cycle in the half-bridge converter is theoretically 50%. However, there must be a mandatory dead time when neither transistor conducts to avoid cross conduction. This implies that the duty cycle of the gate-to-source voltages should be slightly lower than 50%. The transformer is not required to store energy in the half-bridge converter. The transformer core utilization is excellent in the half-bridge converter because the dc current through the primary winding is zero and the primary is driven in both directions. The voltage stress of the switches is low, equal to VImax; therefore, the converter is used in off-line power supplies. The voltage stresses of the diodes are VImax/n for the transformer center-tapped rectifier

and the half-wave rectifier, and VImax/(2n) for the bridge rectifier. The frequency of the waveforms in the output filter is twice the frequency of the MOSFET drivers. The duty cycle D of the lossy converter is greater than that of the lossless converter at the same value of the dc voltage transfer function. The peak-to-peak value of the inductor current ripple ΔiL is independent of the dc load current for CCM. The peak-to-peak value of the current through the filter capacitor C is relatively low; it is equal to the peak-to-peak inductor current ripple ΔiL. If the capacitance of the filter capacitor is sufficiently large, the output ripple voltage is determined only by the filter capacitor ESR and is independent of the filter capacitance. The minimum value of the inductor is determined by the boundary between CCM and DCM, ripple voltage, or ac losses in the inductor and/or the filter capacitor. The input current is pulsating. However, an input LC filter can be added at the converter input to obtain a nonpulsating input current waveform. The corner frequency of the output filter resistance.

is independent of the load

It is relatively difficult to drive the upper transistor because the gate is not referenced to ground. Therefore, a transformer or an optocoupler is required to drive the circuit.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. 3. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984. 4. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 5. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 6. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood Cliffs, N J: Prentice Hall, 2004. 7. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters,

Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 8. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 9. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, Mass.: Addison-Wesley, 1991. 10. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 11. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 12. I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004.

Review Questions 1. Give an expression for the dc voltage transfer function of the lossless half-bridge converter. 2. What is the maximum value of the duty cycle of the half-bridge converter? 3. What happens when the duty cycle is too large in the half-bridge converter? 4. What is cross conduction? How would you prevent it? 5. Is the transformer required to store energy in the half-bridge converter? 6. What is the dc component of the current through the primary of the transformer in the halfbridge converter? 7. What is the total dc magnetic flux caused by the dc components of the diode currents in center-tapped, bridge, and half-wave rectifiers? 8. Is the input current of the basic half-bridge converter pulsating? 9. What are the voltage stresses of the switches in the half-bridge converter? 10. What are the voltage stresses of the diodes in the center-tapped, bridge, and half-wave rectifiers? 11. How can the circuit be changed to obtain a nonpulsating input current in the half-bridge converter? 12. Is the upper transistor driven with respect to ground in the half-bridge converter? 13. How is the dc voltage transfer function MVDC related to the duty cycle D of the lossless half-bridge converter for CCM? 14. Is the duty cycle D of the lossy half-bridge converter less than or greater than that of the lossless converter at a given value of MVDC for CCM? 15. Is the corner frequency of the output filter dependent on the load resistance?

16. How can the circuit of the half-bridge converter be modified to eliminate one blocking capacitor? 17. What are the best applications for a half-bridge converter with a transformer center-tapped rectifier? 18. What are the best applications for a half-bridge converter with a bridge rectifier? 19. Why is dead time required in the gate drive voltages of the half-bridge converter? 20. Is transformer core utilization good in the half-bridge converter? 21. Is the half-bridge converter a good candidate for applications in off-line power supplies? 22. Sketch the voltage waveform across the primary winding in the half-bridge converter.

Problems 1. Derive an expression for the voltage stress of the diodes in the half-bridge PWM converter with a bridge rectifier. 2. The input voltage of a half-bridge PWM converter operating in CCM is the European single-phase rectified line voltage 220 Vrms ± 10% and VO = 12 V. Find the transformer turns ratio n, the minimum duty cycle Dmin, and the maximum duty cycle Dmax. 3. A half-bridge converter operating in CCM has VImax = 342 V and n = 9. Find the voltage stresses of the switches and the diodes. 4. A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 1–20 A, fs = 50 kHz and Dmin = 0.3424. Find the minimum inductance required to maintain the converter operation in CCM. 5. A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 1–20 A, L = 25 μH, n = 9, Dmin = 0.3424, Dmax = 0.4193, fs = 50 kHz, and Vr/VO < 2%. Find the minimum filter capacitance and the corner frequency of the output filter. 6. A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 1–20 A, L = 25 μH, n = 9, ΔiLmax = 1.513, and fs = 50 kHz. Determine the minimum magnetizing inductance at which its peak-to-peak current is less than 10% of the maximum peak current of the ideal transformer primary. 7. A half-bridge converter has VImin = 280 V, VImax = 342 V, VO = 12 V, IO = 0–20 A, n = 9, fs = 50 kHz, and Dmin = 0.3424. Find the maximum inductance required to maintain the converter operation in DCM. 8. Design a half-bridge converter operating in CCM to meet the following specifications: VI is the single-phase rectified European line voltage with Vrms is 220 V ± 10%, VO = 5 V,

IOmin = 2 A, IOmax = 20 A, and Vr/VO ≤1%. Assume rDS = 1 Ω, rT1 = 150 mΩ, rT2 = rT3 = 40 mΩ, rL = 9 mΩ, rC = 35 mΩ, rCb = 350 mΩ, RF = 10 mΩ, VF = 0.3 V, and Co = 80 pF. Assume initially the converter efficiency η = 85%. 9. Design a half-bridge converter whose VI is the single-phase rectified voltage 220 Vrms ± 10%, VO = 5 V, IO = 1–10 A, and Vr/VO ≤ 1%. Find L, C, Lm, rC, n, ISMmax, VSMmax, IDMmax, and VSMmax.

8 Full-Bridge PWM DC–DC Converter 8.1 Introduction The full-bridge PWM converter [1–12] contains two switching legs. Therefore, it draws two current pulses from the input voltage source per cycle of the transistor switching frequency and is capable of delivering more output power than the half-bridge converter. The voltage stresses of the switches are low and equal to the dc input voltage VI. For this reason, the full-bridge converter is used in off-line high-power supplies. This topology of the converter offers the highest power levels, from 500 W to 5 kW. The core is excited in both directions and is relatively small. Applications of the full-bridge converter include telecommunications and aerospace power supplies. The converter belongs to the family of buck-derived converters. This chapter describes, analyzes, and gives a design example of the full-bridge converter.

8.2 DC Analysis of PWM Full-Bridge Converter for CCM 8.2.1 Circuit Description A circuit of the PWM full-bridge dc–dc converter is depicted in Figure 8.1(a). It is composed of a PWM inverter and a PWM rectifier. The inverter consists of a transformer and four power MOSFETs used as controllable switches S1, S2, S3, and S4. The transistors in each switching leg are driven by nonoverlapping voltages that are out of phase by 180°. The maximum duty cycle of the gate-to-source voltages is slightly less than 50%. The waveforms of the gate-tosource voltages should be nonoverlapping to avoid the cross conduction. The switching part of the converter has a totem pole arrangement. Therefore, it is not easy to drive the upper transistors because their gates are not driven with respect to ground. Pulse transformers can be used to drive the upper transistors. The bottom transistors can also be driven by pulse transformers. Pulse transformers driving transistors S1 and S3 may be connected to one output of a control circuit. Similarly, pulse transformers driving transistors S2 and S4 may be connected to the second output of a control circuit. The two outputs of a control circuit provide nonoverlapping voltages, which are out of phase by 180°. The isolation transformer is not required to store energy. Its magnetizing inductance Lm should be large enough to reduce the current through this inductance. On the other hand, if the magnetizing inductance is too large, it requires a large number of turns and is physically large. Ideally, the dc component of the current through the magnetizing inductance is zero. A coupling capacitor may be added in series with the primary winding to achieve zero dc component of the current through the magnetizing inductance and thereby removing an imbalance of the magnetic core. The fullbridge converter is well suited for high-power applications, usually from 0.5 kW to several

kilowatts. It offers the highest power levels among all converters. In very high-power applications, insulated-gate bipolar transistors (IGBTs), thyristors, or MOSFET-controlled thyristors (MCTs) are used as switching devices. In addition, two or more power switching devices may be connected in parallel to increase current capability of every switch and output power levels.

Figure 8.1 Full-bridge converter. (a) With a transformer center-tapped rectifier. (b) With a full-bridge rectifier. (c) With a half-wave rectifier. Three topologies can be used for the full-bridge converter: with a transformer center-tapped rectifier, with a full-bridge rectifier, or with a half-wave rectifier. The transformer centertapped rectifier consists of two diodes D1 and D2, an inductor L, a filter capacitor C, and a load resistor RL. IGBTs or MCTs can also be used. This rectifier is most suitable for low output voltage applications because only one diode conducts, when two switches are ON. Schottky diodes or low on-resistance power MOSFETs can be used as rectifying devices. The voltage stress of the diodes is 2VI/n, which is higher than that in the bridge rectifier. Therefore, the transformer center-tapped rectifier is not suitable for high-voltage applications.

The bridge rectifier is suitable for high output voltage applications because the voltage stress of the diodes is VI/n, which is half of the transformer center-tapped rectifier. This rectifier is not suitable for low-voltage applications because the two diodes conduct when the two switches are ON, and the total forward voltage across the two diodes may become comparable with the output voltage, resulting in low efficiency.

8.2.2 Assumptions The analysis of the full-bridge PWM converter with a transformer center-tapped rectifier shown in Figure 8.1(a) is based upon the following assumptions: 1. The power MOSFETs and the diodes are ideal switches. 2. Transistor and diode capacitances as well as lead inductances are zero. 3. The transformer is modeled by an ideal transformer and its magnetizing inductance Lm. Leakage inductances and stray capacitances are neglected. 4. Passive components are linear, time invariant, and frequency independent. 5. The output impedance of the input voltage source VI is zero for both dc and ac components.

8.2.3 Time Interval: 0 < t ≤ DT During the time interval 0 < t ≤ DT, the switches S1 and S3 as well as the diode D1 are ON, whereas the switches S2 and S4 as well as the diode D2 are OFF. An ideal equivalent circuit for this time interval is shown in Figure 8.2(a). The voltages across the switches S2 and S4 are (8.1) The voltage across the primary winding and the magnetizing inductance Lm is (8.2) Hence, the current through the magnetizing inductance Lm is (8.3) where iLm(0) is the initial current through the magnetizing inductance Lm at t = 0. This current is negative. The peak-to-peak ripple current of the magnetizing inductance is (8.4) the current through the magnetizing inductance at t = 0 is

(8.5) and the current through the magnetizing inductance at t = DT is (8.6) The maximum value of the peak-to-peak ripple current of the magnetizing inductance is (8.7) which gives the minimum magnetizing inductance (8.8)

Figure 8.2 Equivalent circuits of the full-bridge converter with a transformer center-tapped rectifier for CCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ T/2. (c) For T/2 < t ≤ T/2 + DT. (d) For T/2 + DT < t ≤ T. The voltages across the transformer secondary windings are (8.9) The voltage across the diode D2 is (8.10) Since vD2 < 0, the diode D2 is OFF. The voltage across the inductor L is given by (8.11)

resulting in the current through the inductor L (8.12) where iL(0) is the initial current in the inductor L at time t = 0. The peak inductor current becomes (8.13) and the peak-to-peak value of the ripple current through the inductor L is (8.14)

where VI = nVO/(2D) as will be shown shortly. The maximum value of the peak-to-peak ripple current through the inductor L is (8.15) The current through the primary winding of the ideal transformer is (8.16) and the current through the switch is (8.17) Figure 8.3 shows current and voltage waveforms in the full-bridge converter with a transformer center-tapped rectifier for CCM.

Figure 8.3 Waveforms of the full-bridge converter with a transformer center-tapped rectifier for CCM.

8.2.4 Time Interval: DT < t ≤ T/2 Figure 8.2(b) shows an equivalent circuit of the converter for the time interval DT < t ≤ T/2, during which all four switches are OFF and both diodes are ON. Assuming that the offresistances of the switches are same, the voltages across all the switches are (8.18) Therefore, the voltage across the primary winding and the magnetizing inductance Lm is (8.19) which gives the current through the magnetizing inductance

(8.20) and the current through the primary winding of the ideal transformer (8.21) The voltages at the transformer outputs are (8.22) The voltage across the inductor L is (8.23) and the inductor current is (8.24) Assuming that the rectifier circuit is symmetrical, the inductor current is divided equally between the diodes (8.25)

8.2.5 Time Interval: T/2 < t ≤ T/2 + DT Figure 8.2(c) shows an equivalent circuit of the converter for the time interval T/2 < t ≤ T/2 + DT, during which the switches S1 and S3 as well as the diode D1 are OFF, and the switches S2 and S4 as well as diode D2 are ON. The voltages across the switches S1 and S3 are (8.26) and the voltage across the primary winding and the magnetizing inductance Lm is (8.27) The current through the magnetizing inductance is (8.28) and the voltages at the output of the transformer are

(8.29) The voltage across the diode D1 is (8.30) The voltage across the inductor is expressed by (8.31) Hence, the current through the bottom transformer winding, the diode D2, and the inductor L is (8.32) Hence, the current through the primary winding is (8.33) The current through the switches S2 and S4 is (8.34)

8.2.6 Time Interval: T/2 + DT < t ≤ T An equivalent circuit of the converter for the time interval T/2 + DT < t ≤ T is shown in Figure 8.2(d). All switches are OFF and both diodes are ON during this time interval. The equivalent circuit of Figure 8.2(d) is the same as that of Figure 8.2(b). Consequently, the analysis of the converter is the same as that in Section 8.2.4.

8.2.7 Device Stresses The maximum peak value of the voltage across each switch is (8.35) and the maximum peak value of the current through each switch is

(8.36) The maximum peak value of the voltage across each diode of the transformer center-tapped rectifier is (8.37) and the maximum peak value of the voltage across each diode of the full-bridge rectifier is (8.38) The average value of the inductor current is equal to the dc output current IO. Hence, the maximum peak value of each diode is given by (8.39)

8.2.8 DC Voltage Transfer Function of Lossless Full-Wave Converter for CCM Referring to Figure 8.3, (8.40) resulting in the dc voltage transfer function of the lossless converter (8.41) The range of MVDC is (8.42) For the lossless converter, the output voltage VO is independent of the load resistance RL and depends only on the dc input voltage VI. The sensitivity of the output voltage with respect to the duty cycle is (8.43) The dc current transfer function is

(8.44) As D is increased from 0 to 0.5, MIDC decreases from ∞ to n. From (8.41), one obtains VI = nVO/(2D). Substitution of VI into (8.14) gives (8.45) From (8.35), (8.36), and (8.41), IO/ISM ≈ n and VO/VSM = VO/VI = 2D/n. Hence, the switch utilization in the full-bridge converter, characterized by the output-power capability, is given by (8.46) As D is increased from 0 to 0.5, cp increases from 0 to 1.

8.2.9 Boundary Between CCM and DCM The waveform of the inductor current at the boundary between CCM and DCM is shown in Figure 8.4 and is given by (8.47) which produces (8.48) Hence, one obtains the maximum peak value of the inductor current at the CCM/DCM boundary (8.49)

The dc output current at the boundary between CCM and DCM is (8.50)

Hence, the load resistance at the boundary between CCM and DCM is

(8.51) The minimum value of the inductance L required to maintain the converter operation in CCM is then expressed by (8.52)

Figures 8.5 and 8.6 show the normalized load current IOB/(VO/2fsL) = 0.5 − D and the load resistance RLB/(2fsL) = 1/(0.5 − D) at the boundary between CCM and DCM as functions of the duty cycle D, respectively.

Figure 8.4 Waveforms of the inductor current in the full-bridge converter at the boundary between CCM and DCM.

Figure 8.5 Normalized load current IOB/(VO/2fsL) as function of duty cycle D at the boundary between CCM and DCM for the full-bridge converter.

Figure 8.6 Normalized load resistance RLB/(2fsL) as function of duty cycle D at the boundary between CCM and DCM for the full-bridge converter.

8.2.10 Ripple Voltage in Full-Bridge Converter for CCM An analysis similar to that of the buck converter reveals that the peak-to-peak output ripple voltage is equal to the peak-to-peak ripple voltage across the ESR if (8.53) where Dmax ≤ 0.5. This condition is satisfied at any duty cycle D ≤ 0.5 if (8.54) If condition (8.53) is met, the peak-to-peak output ripple voltage Vr is independent of the filter capacitance C and is determined by the ripple voltage across the ESR. Thus,

(8.55) If condition (8.53) is not met, the peak-to-peak output ripple voltage is determined by both the voltage across the capacitance and the ESR. The maximum change of charge stored in the capacitor is (8.56) Hence, (8.57) which gives (8.58) The ripple voltage across the ESR is (8.59) The output ripple voltage is approximately equal to (8.60)

8.2.11 Power Losses and Efficiency of Full-Bridge Converter for CCM Figure 8.7 depicts an equivalent circuit of the full-bridge converter with parasitic resistances, where rDS is the MOSFET on-resistance, RF is the diode forward resistance, VF is the diode threshold voltage, rL is the ESR of the inductor L, and rC is the ESR of the filter capacitor C. The conduction losses will be determined by assuming that the ripple of the inductor current is zero. Therefore, the inductor current can be approximated as (8.61) In the full-bridge converter, the duty cycle D must be less than 0.5. Assume that the peak value of the magnetizing current iLm is much lower than the peak value of the switch current. The current through the switches S1 and S3 can be expressed by

(8.62) The rms value of the switches S1 and S3 is (8.63) Similarly, the current through the switches S2 and S4 can be approximated by (8.64)

The rms value of the switches S2 and S4 is (8.65) The conduction power loss in each MOSFET is (8.66)

Figure 8.7 Equivalent circuit of the full-bridge converter with parasitic resistances to determine component losses. Assuming that the transistor output capacitance Co is linear, the switching loss per transistor is

(8.67) The total power dissipation in each MOSFET (excluding the MOSFET drive power) is given by (8.68)

The current through the primary winding resistance rT1 is (8.69)

Hence, the rms value of the current through the primary winding resistance is (8.70)

Thus, the conduction loss in the primary winding resistance rT1 is (8.71) The conduction loss in the coupling capacitance resistance is (8.72) The current of the diode D1 can be approximated by (8.73)

leading to its rms value

(8.74)

and the power loss in RF in each diode (8.75) The average value of the diode current is (8.76) which gives the power loss associated with the voltage VF in each diode (8.77) Thus, the overall conduction loss in each diode is (8.78) Ideally, the current through the diode D2 is equal to the current through the diode D1. Assuming that the diode D2 is the same as the diode D1, the power loss in the diode D2 is the same as that in the diode D1. The current through the upper secondary winding is equal to that through the diode D1. Consequently, the power loss in the upper secondary winding resistance rT2 is (8.79) The power loss in the bottom secondary winding resistance is PrT3 = PrT2. The rms value of the inductor current is approximately equal to (8.80) which gives the inductor conduction loss (8.81) The current through the filter capacitor is

(8.82)

Hence, using (8.45), one obtains the rms value of the capacitor current (8.83)

and the power loss in the filter capacitor (8.84) The overall power loss is given by (8.85)

Thus, the converter efficiency is (8.86)

8.2.12 DC Voltage Transfer Function of Lossy Converter for CCM Neglecting the magnetizing current iLm, the input current of the converter can be approximated by (8.87)

Hence, the dc component of the input current is

(8.88) leading to the dc current transfer function of the full-bridge converter (8.89) This equation is valid for both lossless and lossy converters. The converter efficiency can be expressed as (8.90) from which the voltage transfer function of the lossy full-bridge converter is (8.91)

From (8.91), the on-duty cycle is (8.92) The duty cycle D at a given dc voltage transfer function is greater for the lossy converter than that for the lossless converter. Substitution of (8.92) to (8.86) yields the efficiency of the full-bridge converter (8.93) where (8.94)

and

(8.95)

8.2.13 Design of Full-Bridge Converter for CCM Design a PWM full-bridge converter operating in CCM to meet the following specifications: V, V, V, VO = 48 V, IOmin = 2.5 A, IOmax = 25 A, and Vr/VO ≤ 1%. Solution: A full-bridge converter with a transformer center-tapped rectifier is selected for the design because the output voltage is low. The maximum and minimum values of the dc output power are (8.96) and (8.97) The minimum and maximum values of the load resistance are (8.98) and (8.99) The minimum, nominal, and maximum values of the dc voltage transfer function are (8.100) (8.101) and (8.102) Let us assume the converter efficiency η = 85% and the maximum duty cycle Dmax ≈ 0.4 < 0.5. Hence, the transformer turns ratio is (8.103)

Let n = 4. The minimum, nominal, and maximum values of the duty cycle are (8.104) (8.105) and (8.106) Assume the switching frequency fs = 50 kHz. The minimum inductance required to maintain the converter operation in CCM is (8.107)

Pick L = 40 μH. The maximum ripple of the inductor current is (8.108)

The ripple voltage is (8.109) If the filter capacitance is large enough, Vr = rCmaxΔiLmax. Hence, the maximum ESR of the filter capacitor is (8.110) Pick a capacitor with rC = 100 mΩ. The minimum value of the filter capacitance at which the ripple voltage is determined by the ripple voltage across the ESR is (8.111)

Pick C = 50 μF/100 V/100 mΩ.

The corner frequency is (8.112) Since i1 = iD1/n, the maximum peak current through the ideal transformer primary winding is (8.113) Let us assume that the maximum peak-to-peak value of the magnetizing current is less than 10% of I1max. Thus, the maximum peak of the magnetizing inductance current is (8.114) Hence, the minimum magnetizing inductance is (8.115) Pick Lm = 3.5 mH. The voltage and current stresses of the power MOSFETs are (8.116) and (8.117)

The voltage stress of the diodes in the transformer center-tapped rectifier is (8.118) and the current stress of the diodes is (8.119) MTM15N40 power MOSFETs are selected, which have VDSS = 400 V, ISM = 15 A of continuous current, rDS = 300 mΩ, Qg = 110 nC, and Co = 100 pF. MR866 fast recovery diodes are selected, which have ID(AV)max = 40 A, IFSM = 350 A, VDM = 600 V, VF = 0.7 V, and RF = 12.5 mΩ. The power losses and the efficiency will be calculated at the maximum load current IOmax = 25

A and the minimum dc input voltage VImin = 283 V. The conduction power loss in each MOSFET is (8.120) The switching power loss per transistor is (8.121) Hence, the total power loss in each transistor is (8.122) Assume that the winding resistance of the primary winding is rT1 = 25 mΩ and the winding resistances of the transformer on the secondary side are rT2 = rT3 = 10 mΩ, the conduction power losses in these resistances are (8.123)

(8.124) and (8.125) The diode loss due to RF is (8.126) The diode power loss due to VF is (8.127) and the conduction power loss in each diode is (8.128) Assuming that the dc inductor ESR is rL(dc) = 10 mΩ, the conduction power loss in the inductor ESR is

(8.129) and the power loss in the capacitor ESR is (8.130) The total power loss is (8.131) and the efficiency of the converter is (8.132) The peak-to-peak gate–source voltage is VGSpp = 14 V. Hence, one arrives at the gate-drive power per transistor (8.133) Figures 8.8 through 8.13 show the plots of the efficiency η and the duty cycle D as functions of VI, IO and RL for the designed full-bridge converter for CCM. The efficiency η was computed from (8.93) through (8.95) and the duty cycle D was calculated from (8.92). The efficiency η first increases and then decreases as IO increases. The duty cycle D decreases as VI increases.

Figure 8.8 Efficiency η as a function of the dc input voltage VI at fixed load resistances RL for the full-bridge converter in CCM.

Figure 8.9 Duty cycle D as a function of the dc input voltage VI at fixed load resistances RL for the full-bridge converter in CCM.

Figure 8.10 Efficiency η as a function of the dc load current IO at fixed dc input voltages VI for the full-bridge converter in CCM.

Figure 8.11 Duty cycle D as a function of the dc load current IO at fixed input voltages VI for the full-bridge converter in CCM.

Figure 8.12 Efficiency η as a function of the load resistance IO at fixed input voltages VI for the full-bridge converter in CCM.

Figure 8.13 Duty cycle D as a function of the load resistance IO at fixed input voltages VI for the full-bridge converter in CCM.

8.3 DC Analysis of PWM Full-Bridge Converter for DCM 8.3.1 Time Interval: 0 < t ≤ DT During this time interval, the switches S1 and S3 and the diode D1 are ON and the switches S2 and S4 and the diode D2 are OFF. The equivalent circuit is shown in Figure 8.14(a). The voltages across the switches S2 and S4 are (8.134) the voltage across the primary winding is (8.135)

the voltages across the transformer secondary are (8.136) and the voltage across the diode D2 is (8.137)

Figure 8.14 Equivalent circuits of the full-bridge converter with a transformer center-tapped rectifier for DCM. (a) For 0 < t ≤ DT. (b) For DT < t ≤ (D + D1T)T. (c) For (D + D1)T < t ≤ T/2. (d) For T/2 < t ≤ T/2 + DT. (e) For T/2 + DT < t ≤ (D + D1)T. The voltage across the inductor L is (8.138)

and the inductor and switch current is (8.139) Hence, the peak inductor current is (8.140)

The voltage across the magnetizing inductance is (8.141) which yields the current through the magnetizing inductance (8.142) and (8.143) Hence, (8.144)

(8.145) and (8.146) The current through the primary winding of the ideal transformer is (8.147) and the current through the switches S1 and S3 is

(8.148) Figure 8.15 shows idealized current and voltage waveforms of the full-bridge converter with center-tapped rectifier for DCM.

8.3.2 Time Interval: DT < t ≤ (D + D1)T The equivalent circuit for this time interval is shown in Figure 8.14(b). During this time interval, all the switches are OFF and both diodes are ON. The voltages across the switches are (8.149) and the voltages across the primary winding and the secondary winding are (8.150) The voltage across the inductor L is (8.151) and the inductor and diode current is obtained using (8.140) (8.152)

The peak inductor current is found as (8.153) The currents of the diodes are (8.154) The voltage across the magnetizing inductance is (8.155) the current through the magnetizing inductance is

(8.156) and the current through the primary winding of the ideal transformer is (8.157) This time interval ends when the diode currents reaches zero.

8.3.3 Time Interval: (D + D1)T < t ≤ T/2 During this time interval, all switches and both diodes are OFF. The equivalent circuit is shown in Figure 8.14(c). The voltages across the switches are (8.158) the voltages across the primary and secondary windings are (8.159) and the voltages across the diodes are (8.160) The inductor current iL, the inductor voltage vL, the switch currents, and the diode currents are zero. The voltage across the magnetizing inductance is (8.161) the current through the magnetizing inductance is (8.162) and the current through the primary winding of the ideal transformer is (8.163) This time ends when the switches S2 and S4 are turned on by the driver.

8.3.4 DC Voltage Transfer Function for DCM Referring to Figure 8.15 and using the volt-second balance,

(8.164) which leads to (8.165) From (8.140) and (8.165), the peak-to-peak inductor current is (8.166)

The dc output current is equal to the average value of the inductor current. Using (8.165) and (8.166), (8.167)

Hence, (8.168) At the boundary between CCM and DCM, (8.169) as in CCM. Substitution of this into (8.168) yields the duty cycle DB at the boundary between CCM and DCM (8.170) Figures 8.16 and 8.17 depict plots of D versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of nMVDC for both CCM and DCM for the lossless full-bridge converter.

Figure 8.15 Waveforms in the full-bridge converter with a transformer center-tapped rectifier for DCM.

Figure 8.16 Duty cycle D as a function of the normalized load current IO/(VO/2fsL) at fixed values of nMVDC for the lossless full-bridge converter.

Figure 8.17 Duty cycle D as a function of normalized load resistance RL/(2fsL) at fixed values of nMVDC for the lossless full-bridge converter. From (8.168), (8.171) Solving this equation for MVDC gives (8.172)

Figures 8.18 and 8.19 show nMVDC versus normalized load current IO/(VO/2fsL) and normalized load resistance RL/(2fsL) at various values of D for both CCM and DCM for the

lossless full-bridge converter. Notice that MVDC depends strongly on D, RL, L, and fs for DCM.

Figure 8.18 DC voltage transfer function nMVDC as a function of the normalized load current IO/(VO/2fsL) at fixed values of D for the lossless full-bridge converter.

Figure 8.19 DC voltage transfer function nMVDC as a function of normalized load resistance RL/(2fsL) at fixed values of D for the lossless full-bridge converter. Using (8.165) and (8.172), (8.173)

The dc input current is (8.174) resulting in the dc input current

(8.175)

and the dc input power (8.176)

The dc output power is (8.177) The efficiency of the converter is (8.178) which gives the duty cycle of the lossy full-bridge converter in DCM (8.179) Rearrangement of this yields (8.180)

8.3.5 Maximum Inductance for DCM The inductor current waveforms at the boundary between CCM and DCM for VImin and VImax are shown in Figure 8.20. The maximum output current at boundary between DCM and CCM is (8.181) which gives the maximum inductance required to maintain the converter operation in DCM is (8.182)

Figure 8.20 Waveform of the inductor current in the full-bridge converter at the boundary between CCM and DCM for VImin and VImax.

8.4 Phase-Controlled Full-Bridge Converter A full-bridge converter with phase-shift control is shown in Figure 8.21. The phase of the gateto-source voltages in the right switching leg are shifted by the phase Δϕ with respect to the gate-to-source voltages in the left switching leg. Figure 8.22 depicts the equivalent circuits for the phase-controlled full-bridge converter. Waveforms for this circuit are shown in Figure 8.23. It can be seen that the duty cycle D of the voltage across the rectifier can be controlled by varying the phase shift Δϕ. The duty cycle D is given by (8.183) As the phase shift Δϕ increases from 0 to π, the duty cycle of the upper pulse and the bottom pulse decreases from 0.5 to 0.

Figure 8.21 Full-bridge converter with phase-shift control.

Figure 8.22 Equivalent circuits in full-bridge converter with phase-shift control.

Figure 8.23 Waveforms in full-bridge converter with phase-shift control.

8.5 Summary The PWM full-bridge converter is either a step-up or a step-down converter. The dc voltage transfer function of the lossless converter is MVDC = 2D/n. The duty cycle must be less than 50%. The transformer is not required to store energy in the full-bridge converter. The magnetic core utilization is excellent because the flux can vary between ± Bs, where Bs is the saturation flux density. The converter has conduction losses and switching losses. The duty cycle D of the lossy converter is greater than that of the lossless converter at the same value of the dc voltage transfer function.

The peak-to-peak value of the inductor ripple current ΔiL is independent of the dc load current for CCM. The peak-to-peak value of the current through the filter capacitor C is relatively low and is equal to the peak-to-peak inductor ripple current ΔiL. If the capacitance of the filter capacitor is sufficiently high, the output ripple voltage is determined only by the ESR of the filter capacitor and is independent of the capacitance of the filter capacitor. The minimum value of the inductor is determined by the boundary between CCM and DCM, output ripple voltage, core saturation, or ac losses in the inductor and/or the filter capacitor. The input current is pulsating. However, an LC filter can be added at the input of the converter to obtain a nonpulsating input current waveform. The corner frequency of the output filter resistance.

is independent of the load

The output inductor can be made smaller because the ripple frequency is twice that of the single-ended converters. It is relatively difficult to drive the upper transistors because the gates are not referenced to ground.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I, II, and III. Pasadena, CA: TESLAco, 1981. 2. E. R. Hnatek, Design of Solid-State Power Supplies, 2nd Ed. New York: Van Nostrand, 1981. 3. G. Chryssis, High-Frequency Power Supplies: Theory and Design. New York: McGrawHill, 1984. 4. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985. 5. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 6. M. H. Rashid, Power Electronics, Circuits, Devices, and Applications, 3rd Ed. Englewood Cliffs, N J: Prentice Hall, 2004. 7. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004.

8. K. Billings, Switchmode Power Supply Handbook. New York: McGraw-Hill, 1989. 9. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, Mass.: Addison-Wesley, 1991. 10. A. I. Pressman, Switching Power Supply Design. New York: McGraw-Hill, 1991. 11. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics. Norwell, MA: Kluwer Academic Publisher, 2001. 12. I. Batarseh, Power Electronic Circuits. New York: John Wiley & Sons, 2004.

Review Questions 1. Give the expression for the dc voltage transfer function of the lossless full-bridge converter. 2. What is the maximum value of the duty cycle for the full-bridge converter? 3. What happens when the duty cycle is too large? 4. How to prevent cross conduction in the full-bridge converter? 5. Is the transformer required to store energy in the full-bridge converter? 6. What is the dc component of the current through the primary winding of the transformer in the full-bridge converter? 7. Is the magnetic core utilization good in the full-bridge converter? 8. Is the input current of the basic full-bridge converter pulsating? 9. How can the circuit be modified to obtain a nonpulsating input current in the full-bridge converter? 10. Are the upper transistors driven with respect to ground in the full-bridge converter? 11. What is the correct value of the magnetizing inductance Lm of the transformer? 12. Do the losses increases or decrease the duty cycle D of the full-bridge converter at a given value of MVDC for CCM? 13. Is the corner frequency of the output filter dependent on the load resistance? 14. Compare the frequency of the output ripple voltage with the frequency of the gate-to-source voltages of the power transistors.

Problems 1. Derive an expression for the voltage stress of the diodes in the full-bridge converter with

the full-bridge rectifier. 2. A full-bridge PWM converter has the input voltage as the US single-phase rectified line, VO = 48 V, PO = 1–2.5 kW, and fs = 35 kHz. Find the transformer turns ratio n, the minimum duty cycle Dmin, and the maximum duty cycle Dmax. 3. A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1– 2.5 kW, and fs = 35 kHz. Find the voltage stresses of the transistors and the diodes. 4. A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1– 2.5 kW, Dmin = 0.27, and fs = 35 kHz. Find the minimum inductance required to maintain the converter operation in CCM. Calculate the maximum value of peak-to-peak inductor ripple current and ΔiLmax/IOmax. 5. A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1– 2.5 kW, Dmin = 0.27, and fs = 35 kHz. Find the minimum inductance at which the ratio of the peak-to-peak inductor ripple current to the maximum load current is less than 10%. 6. A full-bridge PWM converter has the input voltage as the US single-phase rectified line, VO = 48 V, PO = 1–2.5 kW, L = 70 μH, and fs = 35 kHz, and Vr/VO ≤ 1%. Find the filter capacitance and the corner frequency of the output filter. 7. A full-bridge PWM converter has the input voltage as the US single-phase rectified line, VO = 48 V, PO = 1–2.5 kW, fs = 35 kHz, and Vr/VO ≤ 1%. Find the minimum magnetizing inductance Lm(min) at which its maximum peak-to-peak current is less than 10% of the maximum peak current of the ideal transformer primary winding. 8. A full-bridge PWM converter has VImin = 127 V, VImax = 187 V, n = 2, VO = 48 V, PO = 1– 2.5 kW, and fs = 35 kHz. Find the current stresses of the transistors and the diodes. 9. A full-bridge dc–dc converter accepts a US single-phase rectified line and deliver VO = 1 kV. Find the transformer turns ratio n, the minimum duty cycle Dmin, and the maximum duty cycle Dmax. 10. A full-bridge dc–dc converter with a bridge rectifier accepts the US single-phase rectified line and has VO = 1 kV and n = 1/10. Find the voltage stresses of the switches and the diodes. 11. A full-bridge dc–dc converter accepts the US single-phase rectified line and has VO = 1 kV, n = 1/10, PO = 100 W to 1 kW, Dmin = 0.2815, and fs = 50 kHz. Find the minimum inductance for CCM operation. 12. A full-bridge dc–dc converter accepts the US single-phase rectified line and has VO = 1 kV, n = 1/10, PO = 100 W to 1 kW, Dmin = 0.2814, Dmax = 0.4144, L = 25 mH, Vr/VO ≤ 1%, and fs = 50 kHz. Find the minimum filter capacitance and its minimum ESR.

13. A full-bridge dc–dc converter should accept the US three-phase rectified line and delivers VO = 1 kV. Find the transformer turns ratio n. 14. Design a full-bridge PWM converter suitable for telecommunication applications with V± 10%), VO = 48 V, IO = 5–50 A, fs = 35 kHz, and Vr/VO ≤ 1%. Assume rDS = 0.3 Ω, Co = 100 pF, Qg = 110 nF, VF = 0.7 V, RF = 12.5 mΩ, rT1 = 25 mΩ, rT2 = 10 mΩ, and rL(dc) = 10 mΩ. Assume initially the converter efficiency η = 96%. 15. Design a full-bridge PWM converter for aerospace applications with VI = 270 V± 10%, VO = 28 V, IO = 10–100 A, and Vr/VO ≤ 1%. 16. Design a full-bridge converter to meet the following specifications: VI = 48 ± 6 V, VO = 5 V, IO = 5–50 A, and Vr/VO ≤ 1%. Assume rDS = 0.18 Ω, Co = 100 pF, Qg = 110 nF, VF = 0.3 V, RF = 10 mΩ, rT1 = 10 mΩ, rT2 = 3 mΩ, rL(dc) = 4 mΩ, and fs = 50 kHz. Assume initially the converter efficiency η = 75%. 17. Design a universal off-line full-bridge converter operating in CCM to meet the following specifications: the input voltage is from a single-phase utility line anywhere in world with the rms voltage V = 90–240 Vrms, f = 50/60 Hz, VO = 48 V, IO = 5–50 A, fs = 100 kHz, and Vr/VO ≤ 1%.

9 Small-Signal Models of PWM Converters for CCM and DCM 9.1 Introduction Power stages of PWM converters are highly nonlinear systems because they contain at least one transistor and at least one diode, which are operated as switches. PWM converters are periodic variable structure systems. The converters normally require control circuits to regulate the dc output voltage against load and line variations. Typical control aspects of interest are frequency response, transient response, and stability. Linear control theory is well developed and it may offer valuable tools for studying the small-signal dynamic performance of PWM converters. However, in order to apply this theory, nonlinear power stages of PWM converters should be averaged and linearized [1–51]. There are two averaging methods for PWM converters: state-space averaging method [1–43] circuit-averaging method [9–33]. The state-space averaging method [1–43] is based on analytical averaging of state-space equations describing linear equivalent circuits for different states of a converter determined by the on–off status of the transistor(s) and the diode(s). The state-space equations are weighed according to the fraction of the switching cycle, during which the converter remains in a given state. However, the state-space averaging method requires a considerable amount of matrix algebra manipulations and is sometimes tedious, especially when the converter circuit contains a large number of passive elements or parasitic components. Moreover, it provides little insight into the converter behavior. On the other hand, in many power electronic circuits, the average values of voltages and currents of switching components rather than their instantaneous values are of the greatest interests. The circuit-averaging method involves the following steps: 1. Averaging of current and voltage waveforms of switching components over one switching period, 2. Replacement of switching components with nonlinear dc dependent current and voltage sources, 3. Averaging the parasitic components of the switching devices over one switching period, such as transistor on-resistance, diode forward resistance, and diode offset voltage, 4. Perturbation of the averaged current, voltage, and duty ratio waveforms to obtain largesignal time-dependent waveforms,

5. Replacement of dc dependent sources by nonlinear large-signal dependent current and voltage sources, 6. Splitting the large-signal current, voltage, and duty cycle waveforms into the dc and ac components, 7. Linearization of nonlinear dependent current and voltage sources, 8. Separation of dc and small-signal variables, 9. Representation of the dc variables by a dc circuit model and representation of the smallsignal ac variables by a small-signal linear ac circuit model. The circuit-averaging method leads to linear time-invariant (LTI) circuit models [9–33]. These models are relatively simple, provide good physical and intuitive insight into the converter behavior, can be used for deriving various transfer functions and step responses, and are compatible with general purpose electronic circuit simulators. In addition, control loops for PWM converters can be designed by applying well-known linear control techniques. Some nonlinear control methods have been proposed in [34–36]. In this chapter, the averaged nonlinear large-signal, dc, and ac small-signal LTI circuit models of the discrete switching network of PWM converters are developed for CCM and DCM, using current and voltage dependent sources and the law of conservation of energy [23–44]. The current- and voltage-dependent sources are used to model the ideal switching network and the law of conservation of energy is used to model parasitic components of switching devices, such as the transistor on-resistance, the diode forward resistance, and the diode offset voltage. The ideal switching network of single-ended transformerless PWM converters consists of two ideal switches. This network can be modeled for the dc components in steady state by two ideal dc dependent sources. The switched forward resistances of the switch and the diode are averaged, using the law of conservation of energy. The currents, voltages, and duty cycle are then perturbed in the average dc model. Hence, the dc dependent sources in the model are replaced by large-signal time-varying dependent sources. Consequently, large-signal currents, voltages, and duty cycle contain both dc and ac components. Therefore, the large-signal sources can be replaced by the dc dependent sources and the ac small-signal dependent sources. If the magnitudes of the small-signal components are low enough, the model can be linearized by neglecting products of the ac components. This leads to a linear circuit model, containing both dc- and ac-dependent sources. Since the model is linear, it can be split into a small-signal low-frequency ac circuit model and a dc circuit model. If the switching network in a PWM converter is replaced by its small-signal model, a small-signal model of the entire power stage is obtained. This model may be used to derive and simulate small-signal transfer functions and step responses of that converter. A good model should reproduce the characteristics of a real circuit.

9.2 Assumptions The models are derived under the following assumptions:

1. The transistor output capacitance and the diode capacitance are neglected; therefore, switching losses are neglected. 2. The transistor on-resistance rDS is linear and the transistor off-resistance is infinite. 3. The diode in the on-state is modeled by a linear battery VF and a linear forward resistance RF. In the off-state, the diode is modeled by an infinite resistance. 4. Passive components are linear, time invariant, and frequency independent. 5. Storage-time modulation of bipolar transistors is neglected.

9.3 Averaged Model of Ideal Switching Network for CCM A PWM converter consists of a nonlinear discrete part and a linear analog part. The nonlinear part consists of nonlinear semiconductor devices such as a transistor(s) and a diode(s) operated as switches, that is, as discrete components. The linear part consists of linear components, such as capacitors and inductors with their equivalent series resistances. The nonlinear part may be replaced by an average circuit model, which emulates its average lowfrequency behavior. In the average circuit model, the average low-frequency voltages across the model terminals and the average low-frequency currents into its terminals are identical to those of the original switching network. The waveforms of the average current and voltage do not contain high-frequency components. The high-frequency components can be regarded as carriers. The average model is nonlinear and may be linearized for small ac signals. The linear part of a converter does not require averaging and linearization. The modeling strategy of PWM converters is similar to transistor modeling and is based on the following principles: 1. Replacement of the switching network (or components) by an analog (continuous) circuit model. 2. Leaving the analog part composed of linear components unchanged. Figure 9.1 shows four basic single-ended transformerless two-switch PWM converters: buck, boost, buck–boost, and Ćuk converters. All these converters have a common subcircuit that consists of two switching devices: a power MOSFET and a diode. This subcircuit is highly nonlinear and is referred to as a switching network. Figure 9.2(a) shows the switching network of single-ended transformerless two-switch PWM converters, and Figure 9.2(b) shows an equivalent circuit of the switching network. The ideal part of the switching network consists of two ideal switches. One ideal switch represents an ideal MOSFET whose onresistance is zero, and the other ideal switch represents an ideal diode whose forward resistance and offset voltage are zero. The actual switching network consists of an ideal switching network and parasitic components. The MOSFET is represented by an ideal switch and a linear on-resistance rDS, and the diode is represented by an ideal switch, a linear

forward resistance RF, and an offset voltage VF.

Figure 9.1 Single-ended transformerless two-switch PWM converters. (a) Buck converter. (b) Boost converter. (c) Buck–boost converter. (d) Ćuk converter.

Figure 9.2 Switching network and equivalent circuit of single-ended transformerless twoswitch PWM converters. (a) Switching network. (b) Equivalent circuit. Figure 9.3 shows the steady-state current and voltage waveforms in the ideal switching network for CCM. In this case, all ac external excitations, disturbances, and uncertainties are zero. There is no startup, shutdown, or sudden change in the input voltage and load resistance. Since the steady-state waveforms are periodic, all the current and voltage waveforms, their dc components, and the duty cycle D are the same in every cycle of the switching frequency fs = 1/T. In general, the average value of any periodic waveform of any quantity x(t) in steady state over one cycle T is given by (9.1)

Figure 9.3 Steady-state waveforms in the ideal switching network for CCM. The waveforms of the inductor current iL and the voltage across the combination of the switch and the diode vSD are continuous, whereas the waveforms of the switch current iS and the diode reverse voltage vLD are pulsating. Averaging the high-frequency instantaneous values of converter waveforms is simply extracting the corresponding dc components over one cycle of the switching frequency fs. Note that averaging the steady-state waveforms (with zero ac excitations) over many cycles gives the same result. Let us neglect the parasitic components in the PWM converters shown in Figure 9.1. For the buck converter, VSD = VI, VSL = VI − VO, and VLD = VO. For the boost converter, VSD = VO, VSL = VI, and VLD = VO − VI. For the buck–boost converter, VSD = VI − VO = VI + |VO|, VSL = VI, and VLD = VO. For the Ćuk converter, VSD = VI − VO = VI + |VO|, VSL = VI, and VLD = VO. According to Figure 9.3, the steady-state waveform of the switch current can be approximated by

(9.2) Hence, the dc component of the switch current is (9.3) This expression describes an ideal dc current-controlled current source (CCCS) or currentdependent current source controlled by the dc component IL of the inductor current iL. An equivalent circuit representing this expression is an averaged model of an ideal switch and is shown in Figure 9.4(a).

Figure 9.4 Averaged model of ideal switch, ideal diode, and ideal switching network for the dc components in steady state for CCM. (a) Averaged model of an ideal switch. (b) Averaged model of an ideal diode. (c) Averaged model of an ideal switching network of two-switch PWM converters.

Referring to Figure 9.3, the steady-state waveform of the voltage across the ideal diode is given by (9.4) yielding its dc component (9.5) This expression describes an ideal dc voltage-controlled voltage source (VCVS) or voltagedependent voltage source controlled by the dc component VSD of the switch–diode voltage vSD. Figure 9.4(b) shows an equivalent circuit representing an averaged model of an ideal diode. Using the averaged models of an ideal switch and an ideal diode, an averaged model of an ideal switching network of two-switch PWM converters is obtained, as depicted in Figure 9.4(c). This model describes the performance of an ideal switching network for the dc components under steady-state conditions. It does not contain information about the inductor ripple current as well as the pulsating nature of the switch and diode current and voltage waveforms. The model of the switching network for the dc components under steady-state operating conditions is referred to as the “dc model.”

9.4 Averaged Values of Switched Resistances The transistor on-resistance rDS and the diode forward resistance RF are in series with the ideal switches in the switching network of Figure 9.2(b). These resistances should be averaged. Other resistances of a converter, such as the ESR of the inductor and the ESR of the filter capacitor, need not be averaged because they are not connected in series with the switches. The law of conservation of energy is used to determine the average values of the switched resistances. The diode current can be approximated by (9.6) Thus, the dc component of the diode current is (9.7) From (9.3) and (9.7),

(9.8) Using (9.2) and (9.3), the rms value of the switch current is obtained as (9.9)

The power loss in the MOSFET on-resistance rDS is (9.10) On the other hand, the power loss in the averaged MOSFET on-resistance rDSAV(S) in the switch branch is (9.11) Using the law of conservation of energy, the energy dissipated in the switched MOSFET onresistance rDS is the same as that in the averaged switch resistance rDSAV(S). Hence, the equivalent averaged resistance (EAR) of rDS in the switch branch is (9.12) as shown in Figure 9.5(a).

Figure 9.5 Averaged models of the actual MOSFET and the actual diode in steady state for CCM. (a) Averaged model of the actual MOSFET. (b) Averaged model of the actual diode. The switch resistance may be also averaged by averaging the switch conductance over the period of the switching frequency T = 1/fs. The switch conductance is approximated by (9.13) The average switch conductance in the switch branch is (9.14) yielding the average switch resistance in the switch branch

(9.15) Using (9.6), the rms value of the diode current is obtained as (9.16)

resulting in the power loss in the diode forward resistance RF (9.17) The power dissipated in the equivalent averaged diode forward resistance RFAV(D) in the diode branch is (9.18) Consequently, the EAR of RF in the diode branch is obtained as (9.19) as shown in Figure 9.5(b). The diode forward resistance may be averaged by averaging the diode forward conductance over the period of the switching frequency. The diode forward resistance conductance can be approximated by (9.20) The average diode forward conductance in the diode branch is (9.21) producing the average diode forward resistance in the diode branch (9.22) The power dissipated in the diode offset voltage source VF is (9.23) and the power dissipated in the equivalent averaged voltage VFAV(D) of the offset voltage

source in the diode branch is (9.24) Equating the right-hand sides of (9.23) and (9.24), one obtains the averaged diode offset voltage in the diode branch (9.25) as shown in Figure 9.5(b). Figures 9.6(a) and (b) depicts the actual switching network and its averaged dc model, respectively. If a bipolar junction transistor (BJT) or an insulated gate bipolar transistor (IGBT) is used as a switch, the offset voltage source can be averaged in a similar manner. The inductance L is not a part of the switching network model.

Figure 9.6 Modeling of the actual switching network under steady-state conditions for twoswitch PWM converters operating in CCM. (a) Actual switching network. (b) Averaged dc model of the actual switching network. (c) Simplified averaged dc model of the actual switching network with the averaged resistances moved to the inductor branch.

9.5 Model Reduction The averaged model of the actual switching network shown in Figure 9.6(b) contains two resistors. This does not cause any problem if the model is used for converter simulation purposes, such as PSPICE. However, a simpler form of the model is desirable, if it is used to derive various transfer functions and impedances. Reflection rules are used to derive a simplified model of the actual switching network. Substitution of (9.8) into (9.10) yields (9.26)

Hence, the averaged MOSFET resistance in the MOSFET branch is (9.27) the averaged MOSFET resistance in the inductor branch is (9.28) and the averaged MOSFET resistance in the diode branch is (9.29) The ratios of these resistances are (9.30)

(9.31) and (9.32) Thus, the relationship among the averaged MOSFET resistances in the different branches is (9.33) Substituting (9.8) into (9.17), one obtains (9.34) which results in the averaged diode resistance in the diode branch (9.35) the averaged diode resistance in the inductor branch (9.36) and the averaged diode resistance in the MOSFET branch (9.37)

The ratios of these resistances are (9.38)

(9.39) and (9.40) Hence, the relationship among the averaged diode forward resistances in the different branches is (9.41) Substitution of (9.8) into (9.23) gives (9.42) This leads to the averaged offset diode voltage in the diode branch (9.43) the averaged offset diode voltage in the inductor branch (9.44) and the averaged offset diode voltage in the MOSFET branch (9.45) The ratios of these averaged voltages are (9.46)

(9.47) and

(9.48) Finally, the relationship among the averaged diode offset voltages in the various branches is (9.49) Using (9.12), (9.19), and (9.26)–(9.48), the general reflection rules are as follows: (9.50) (9.51) where rl, rs, and rd are the EARs in inductor branch, switch branch, and diode branch, respectively, and Vl, Vs, and Vd are the equivalent averaged voltage sources in the inductor branch, the switch branch, and the diode branch, respectively. The equivalent resistance of the inductor branch is given by (9.52) A simplified averaged dc model of the actual switching network is shown in Figure 9.6(c). The reflection rules can be applied to move the parasitic components from one branch to another, yielding an averaged model, which is equivalent to that of Figure 9.6(b).

Figure 9.7 Large-signal averaged models of the actual switching network for two-switch PWM converters for CCM. (a) Actual switching network. (b) Large-signal averaged model of the actual switching network. (c) Simplified large-signal averaged model of the actual switching network with the averaged resistances moved to the inductor branch.

9.6 Large-Signal Averaged Model for CCM The actual switching network is shown in Figure 9.7(a). The dc quantities such as dc inductor current IL, dc voltage VSD, and constant duty cycle D in the averaged models shown in Figures 9.6(b) and (c) can be replaced by slowly varying, time-dependent, large-signal quantities such as the current iL, voltage vSD, and duty cycle dT. Relationships among the low-frequency largesignal variables can be approximated using the dc relationships (9.3) and (9.5) for the dc variables (9.53)

and (9.54) A large-signal, low-frequency, averaged model representing these equations is shown in Figures 9.7(b) and (c). It assumed that the relationships between the dc components and the large-signal time-dependent components remain the same. This assumption is satisfied when the time rate of change of the average values of all variables is sufficiently low. In particular, it assumed that the capacitive effects can be neglected. Example 9.1 Draw a large-signal low-frequency averaged model of the buck PWM converter with parasitic components. Simplify this model using a current source splitting theorem. Solution: Figure 9.8(a) shows a large-signal low-frequency averaged model of the buck converter. This model can be obtained by replacing the actual switching network with the large-signal model shown in Figure 9.7(c) in the buck converter. Note that vSD = vI for the buck converter. Using the current splitting theorem, the dependent current source can be split into two current sources, as shown in Figure 9.8(b). In general, the parallel combination of a current source and a voltage source is equivalent to the voltage source. Therefore, the model may be simplified by neglecting the dependent current source in parallel with the dependent voltage source, as depicted in Figure 9.8(c).

Figure 9.8 Large-signal low-frequency model of the buck PWM converter with parasitic components for CCM. (a) Large-signal model with the dependent sources in the original branches. (b) Large-signal model with the dependent current source split into two sources. (c) Simplified large-signal model. Example 9.2 In the buck PWM converter, the duty cycle dT = D is held at a fixed value and the initial boundary conditions of the inductor L and the filter capacitor C are zero. The inductance L is high enough to operate the converter in CCM for steady state. At time t = 0, the dc input voltage source VI is turned on. Find the waveform of the output voltage vO without the switching-frequency component and its harmonics for ξ = 0.3. Neglect parasitic elements. Solution: The large-signal low-frequency averaged model shown in Figure 9.8(c) with no parasitic elements may be used to find the output voltage. This voltage is a response to a step change of the input voltage, without the switching-frequency component. This model is linear when dT = D. The step change of the input voltage in the time domain is (9.55)

Therefore, the average voltage at the input of the LCRL circuit is also a step change given by (9.56) which in the s-domain is (9.57) The voltage transfer function of the LCRL circuit is (9.58)

The undamped resonant frequency (or the natural frequency) is (9.59) and the damping factor is (9.60) Hence, (9.61) The output voltage in the s-domain is (9.62) resulting in the output voltage in the time domain (9.63) where (9.64) Figure 9.9 shows the normalized output voltage waveform vO/(DVI) without the switching-

frequency component. The output voltage is the response of the second-order low-pass filter to a step change in the dc input voltage from zero to VI.

Figure 9.9 Normalized output voltage vO/(DVI) as a response to a step change in the dc input voltage at ξ = 0.3, neglecting the switching-frequency component.

9.7 DC and Small-Signal Circuit Linear Models of Switching Network for CCM 9.7.1 Large-Signal Circuit Model of Switching Network for CCM Consider the operation of a PWM converter under the external low-frequency excitation (also called a low-frequency perturbation) superimposed on the dc component. Each of the waveforms in a PWM converter under the low-frequency excitation contains three components: 1. a dc component,

2. a low-frequency component of the frequency f = ω/(2π) and its harmonics, and 3. a high-frequency component of the switching frequency fs and its harmonics. Only the dc components and the low-frequency components are of interest to study control aspects of PWM converters. This is because the control signals of the closed-loop PWM converters normally consist of the dc and low-frequency components. Consequently, the lowfrequency components are used to characterize the dynamics of PWM systems. The purpose of the averaged low-frequency dynamic models is to emulate the average behavior (in particular, dynamics) of the open- and closed-loop PWM converters in the low-frequency range. In the simplest case, the low-frequency perturbation signals can be sinusoidal. They are especially useful for test purposes to study the frequency response of a PWM system. As an illustrative example, Figure 9.10 shows the waveforms of the input voltage and the inductor current under a sinusoidal low-frequency perturbation. Figure 9.10(a) shows the ac lowfrequency sinusoidal component of the input voltage (9.65) superimposed on the dc component of the input voltage VI, resulting in the large-signal input voltage (9.66) The high-frequency waveform of the inductor current is depicted in Figure 9.10(b). Figure 9.10(c) shows the averaged low-frequency sinusoidal component of the inductor current (9.67) superimposed on the dc component IL, and the averaged low-frequency large-signal inductor current (9.68) The procedure for extracting the averaged dc and low-frequency components of the inductor current consists of two steps. First, the average values of the instantaneous high-frequency inductor current for every cycle of the switching frequency fs = 1/T (also called local average values) are found as (9.69) as shown in Figure 9.10(b) by the dashed lines. Second, the averaged low-frequency component of Figure 9.10(c) is obtained by connecting the average values in Figure 9.10(b), for example, in the middle or at the beginning of every cycle of the switching frequency fs = 1/T.

Figure 9.10 Waveforms of the input voltage and the inductor current under sinusoidal lowfrequency small-signal perturbations for CCM. (a) Waveform of the input voltage. (b) Waveform of the high-frequency inductor current. (c) Waveform of the averaged low-frequency inductor current. In reality, the low-frequency perturbation signal may be more complex. An example of such a signal is a ripple voltage of a frequency of 100 or 120 Hz on the rectified voltage obtained from a single-phase front-end bridge rectifier. According to Shannon’s sampling theorem, the frequency f of the perturbation signal must be less than or equal to one-half of the switching frequency fs, called the Nyquist frequency. As a result, the low-frequency dynamic models of PWM converters are valid only in the frequency range: 0 ≤ f ≤ fs/2. If the dc independent external variables, such as the dc input voltage VI and/or the duty cycle D, are perturbed in a converter circuit at a low frequency f < fs/2, all other variables will vary around their corresponding dc levels at a low frequency f. As a result, the averaged voltages,

currents, and duty cycle can be expressed as the sums of dc components and ac low-frequency components as follows: (9.70) (9.71) (9.72) (9.73) (9.74) (9.75) and (9.76) The large-signal model shown in Figure 9.11(a) is nonlinear. Linearization of the large-signal averaged model at a given operating point can be performed by (1) expanding the large-signal nonlinear equations into a Taylor series about the operating point and (2) neglecting the higherorder terms. A linear small-signal model can be obtained by assuming small-signal perturbations, which allow us to take into account only the first-order terms. The assumption of the small-signal perturbation implies that the magnitudes of the ac low-frequency components are much lower than those of the corresponding dc components.

Figure 9.11 Averaged low-frequency large-signal and bilinear models of the actual switching network for two-switch PWM converters for CCM. (a) Averaged low-frequency large-signal nonlinear model. (b) Averaged low-frequency bilinear model. (c) Averaged dc and lowfrequency small-signal model. Substituting (9.71), (9.73), and (9.76) into (9.54), one obtains a nonlinear equation (9.77) The first term is the dc (or quiescent) component of the switch current IS, the second term is the time-varying switch current that is linearly related to the ac component of the inductor current il, and the third term is equal to the product of small-signal component of inductor current il and the small-signal component of the duty cycle d. The third term is a nonlinear term that produces nonlinear distortion,that is, harmonics of the switch current. For example, assume that il = Ilmsin ωt and d = dmsin ωt. Hence, . The operation given in (9.77) is equivalent to expanding (9.54) into a two-dimensional Taylor series around the dc

operating point Q(D, IL) and neglecting higher-order terms. Similarly, substitution of (9.70), (9.72), and (9.76) into (9.53) yields a nonlinear equation (9.78) The first term is the dc (or quiescent) component of the voltage across the diode VLD, the second term is the time-varying diode voltage that is linearly related to the ac component of the diode voltage vsd, and the third term is equal to the product of small-signal component of voltage vsd and the small-signal component of the duty cycle d. The last term is a nonlinear term that produces nonlinear distortion. Equations (9.77) and (9.78) can be represented by a circuit model of the actual switching network, shown in Figure 9.11(b). This model is nonlinear and is known as a bilinear model.

9.7.2 Linearization of Switching Network Model for CCM To linearize the nonlinear model of the converter switching network of Figure 9.11(b), let us assume that (9.79) (9.80) (9.81) and (9.82) Simplifying these inequalities, one obtains the small-signality conditions (9.83) (9.84) and (9.85) Neglecting the products of the small-signal components ild and vsdd in (9.77) and (9.78), one obtains a set of linear equations (9.86) and (9.87)

This set of linear equations can be represented by a linear circuit model of the actual switching network for both dc and small-signal ac components depicted in Figure 9.11(c). Since this model is linear, the principle of superposition can be used to split the model of Figure 9.11(c) into a small-signal circuit model and a dc circuit model of the actual switching network, as shown in Figures 9.12(a) and (b), respectively.

Figure 9.12 Small-signal low-frequency and dc linear circuit models of the actual switching network for two-switch PWM converters for CCM. (a) Linear low-frequency small-signal circuit model of the actual switching network. (b) DC model of the actual switching network. A circuit of the buck PWM converter is depicted in Figure 9.13(a). Figure 9.13(b) shows a small-signal low-frequency model of the buck converter with parasitic components. This model can be obtained by replacing the actual switching network in the buck converter with the small-signal low-frequency model shown in Figure 9.12(a). For the buck converter, VSD = VI and vsd = vi. The dependent current sources can be split into two sets of current sources: one set in parallel with the input voltage source vi and the other set in parallel with the series combination of the dependent voltage sources, as shown in Figure 9.13(c). The parallel

combination of the current sources and the voltage sources is equivalent to the voltage sources; therefore, the model may be simplified by neglecting the parallel dependent current sources, as shown in Figure 9.13(d). Figures 9.14 and 9.15 show small-signal models of the boost and buck–boost converters, respectively. For the boost converter, VSD = VO and vsd = vo. For the buck–boost converter, VSD = VI − VO and vsd = vi − vo, where VO < 0.

Figure 9.13 Small-signal low-frequency model of the buck PWM converter with parasitic components for CCM. (a) Circuit of the physical buck PWM converter. (b) Small-signal model of the buck converter. (c) Small-signal model of the buck converter with two sets of the dependent current sources. (d) Simplified small-signal model of the buck converter.

Figure 9.14 Small-signal low-frequency model of the boost PWM converter with parasitic components for CCM. (a) Circuit of the physical boost PWM converter. (b) Alternative representation of the circuit of the physical boost PWM converter. (c) Small-signal model of the boost converter. (d) Simplified small-signal model of the boost converter.

Figure 9.15 Small-signal low-frequency model of the buck–boost PWM converter with parasitic components for CCM. (a) Circuit of the physical buck-boost PWM converter. (b) Small-signal model of the buck–boost converter.

Figure 9.16 Block diagram of a small-signal model of PWM dc–dc converters.

9.8 Block Diagram of Small-signal Model of PWM DC– DC Converters Figure 9.16 shows a block diagram of small-signal models for power stages of PWM dc–dc converters. There are three small-signal inputs d, vi, and io, where vi and io are disturbances and d is the control parameter used to control a converter against these disturbances. There are also two small-signal outputs vo and il. The small-signal model may be described by six transfer functions: Tp = v′o/d, Mv = v″ o/vi, Zo = −v‴o/io, Tpi = i′l/d, Mvi = i″ l/vi, and Ai = i‴l/io. These transfer functions will be studied in subsequent chapters.

9.9 Family of PWM Converter Models for CCM The relationships among the averaged large-signal variables for the single-ended

transformerless PWM converters operated in CCM are given by (9.88) and (9.89) These relationships lead to six topologies of the averaged large-signal models of the ideal switching network for CCM, shown in Figure 9.17. Each topology contains one ideal currentdependent current source and one ideal voltage-dependent voltage source. Each currentdependent current source can be controlled by the current through one of the remaining branches. Similarly, each voltage-dependent voltage source can be controlled by one of the remaining interterminal voltages. Therefore, there are 24 pairs of descriptive combinations for the current and voltage dependent sources. These combinations are given in Table 9.1, and there are 24 averaged large-signal models of the ideal switching network. Only six of them are shown in Figure 9.17. The averaged resistances and the averaged offset voltage source can be added to each model to obtain an averaged large-signal model of the actual switching network. In each model, the large-signal quantities can be replaced by the dc component and the ac component. Any of these models can be linearized to obtain an averaged small-signal model and a dc model in a similar manner to that shown in this chapter for the model of Figure 9.17(a).

Figure 9.17 Family of averaged large-signal circuit models of the ideal switching network for basic two-switch PWM converters in CCM.

Table 9.1 Descriptions of dependent sources in large-signal models of Figure 9.16 for CCM

The same technique may also be used to derive models for transformer PWM converters (e.g., flyback or forward converters), multiple-switch converters (e.g., half-bridge, full-bridge, or push–pull converters), and for converters operating in the discontinuous conduction mode.

9.10 PWM Small-Signal Switch Model for CCM Figure 9.18 shows a PWM small-signal switch model for the switching network of all twoswitch PWM converters [6, 18]. The symbols a, p, and c denote the “active,” “passive,” and “common” terminals, respectively. In this model, D is the steady-state dc component of the onduty cycle, Vap is the steady-state dc component of the voltage across the series combination of the active switch (a transistor) and the passive switch (a diode), that is, Vap = VSD, and IC is the steady-state dc component of the current flowing out of the common node, that is, the steady-state dc component of the inductor current IL. For a given operating point, Vap, D, and IC are constant quantities. The quantities d and ic are the small-signal duty cycle and the small-

signal inductor current, respectively. As the frequency approaches zero, the transformer becomes a dc transformer, which is not a circuit-theory component. Substitution of the nonlinear switching network (a transistor and a diode) by its PWM small-signal model of Figure 9.18 gives the small-signal model of the entire power stage of a two-switch PWM converter. The small-signal model shown in Figure 9.18 and proposed in [18] has a different topology than that shown in Figure 9.12(a) and developed in [23, 24], even if the transformer in Figure 9.18 is replaced by dependent sources.

Figure 9.18 A PWM small-signal switch model of the nonlinear switching network for basic two-switch PWM converters operating in CCM.

9.11 Modeling of Ideal Switching Network for DCM 9.11.1 Relationships Among DC Components for DCM Circuit models of PWM converters operated in DCM [19, 44] will be derived below. Let us consider the ideal switching network shown in Figure 9.2(b). Figure 9.19 shows the steadystate voltage waveforms in PWM converters for DCM. From Figure 9.1, the dc components of the terminal voltages (i.e., the average voltages) of the switching network can be expressed in terms of the converter dc input and output voltages VI and VO as follows: VSD = VI, VSL = VI −

VO, and VLD = VO for the buck converter, VSD = VO, VSL = VI, VLD = VO − VI for the boost converter, and VSD = VI − VO = VI + |VO|, VSL = VI, VLD = −VO for the buck–boost and Ćuk converters.

Figure 9.19 Voltage waveforms in PWM converters for DCM. Referring to Figures 9.1 and 9.2, and neglecting the parasitic components rDS, RF, and VF, one can note that voltages and contain only dc components and , respectively, that is, (9.90) and (9.91) Since the average inductor voltage VL(AV) = 0, the dc component of the voltage across the series combination of the switch and the inductor is equal to the dc component of the switch

voltage VSL (9.92) The dc component of the voltage across the series combination of the diode and the inductor is equal to the dc component of the diode voltage VLD (9.93) By Kirchhoff’s voltage law (KVL), the inductor voltage can be expressed as (9.94) or (9.95) For 0 < t ≤ DT, the switch is ON, vSL = 0, and (9.96) For DT < t ≤ (D + D1)T, the diode is ON, vLD = 0, and (9.97) For (D + D1)T < t ≤ T, iL = 0, and therefore vL = 0. Hence, the voltage across the inductor can be summarized as follows: (9.98)

resulting in the inductor current (9.99) from which the peak inductor current is found as (9.100) Similarly, (9.101) The peak inductor current can also be calculated as follows:

(9.102) Thus, (9.103) Figure 9.20 shows the steady-state current waveforms for DCM. The inductor current waveform is given by (9.104)

yielding the dc component of the inductor current (9.105)

Figure 9.20 Current waveforms in PWM converters for DCM. The waveform of the switch current is described by (9.106) which gives the dc component of the switch current (9.107) Substitution of (9.100) into (9.107) yields (9.108) Similarly, the diode current waveform is given by

(9.109)

resulting in the dc component of the diode current (9.110) Dividing (9.110) by (9.107), (9.111) Substituting (9.100) into (9.110), one obtains (9.112) Hence, using (9.103), one obtains (9.113) From (9.103) and (9.111), (9.114) The voltage vSD across the series combination of the switch and the diode is not pulsating and is equal to its dc component VSD. Hence, the voltage across the switch is (9.115)

where VSL is the dc component of the voltage across the switch, and VSD is the dc component of the voltage across both the switch and the diode. This leads to the dc component of the voltage across the switch (9.116) The voltage across the diode is

(9.117)

where VLD is the dc component of the voltage across the diode. The dc component of the diode voltage is (9.118) Dividing (9.118) by (9.116), one obtains (9.119)

9.11.2 Small-Signal Model of Ideal Switching Network for DCM Using relationship (9.108) for the dc components, one can write the identical relationship among the large-signal, slowly varying components (9.120) where each large-signal component may be expressed as a sum of a dc component and an ac component (9.121) (9.122) and (9.123) Substituting (9.121), (9.122), and (9.123) into (9.120), one obtains the switch current (9.124) For d2 D2, this equation can be approximated by (9.125) Neglecting the product of the small-signal component vsld, one arrives at

(9.126) from which, one obtains the dc component of the switch current (9.127) and the ac small-signal component of the switch current (9.128) where (9.129)

(9.130) and (9.131) Note that Ri = ri. Using (9.113), the relationship among the large-signal, slowly varying quantities is given by (9.132) where each large-signal component can be expressed as a sum of a dc component and an ac component (9.133) (9.134) (9.135) (9.136) Substitution of (9.133), (9.134), (9.135), and (9.136) into (9.132) yields

(9.137)

Next, the following approximation can be made (9.138) Hence, for vsl VSL and d D, the terms d2 and v2sl can be neglected and relationship (9.137) can be approximated by (9.139)

Neglecting the small-signal component product vsld, (9.140) Neglecting the terms containing the products of small-signal components vslvld and vldd, one obtains (9.141)

from which (9.142) and (9.143) where (9.144)

(9.145) and (9.146) The combination of the dc and small-signal models of PWM converters for DCM described by (9.126) and (9.141) is shown in Figure 9.21(a). Figure 9.21(b) depicts a small-signal model of the PWM converters for DCM described by (9.128) and (9.143). Figure 9.21(c) shows a dc model of the PWM converters for DCM described by (9.127) and (9.142).

Figure 9.21 Models of PWM converters for DCM. (a) DC and small-signal model. (b) Smallsignal model. (c) DC model.

9.12 Averaged Parasitic Resistances for DCM

Using (9.105), the rms values of the inductor, switch, and diode currents are (9.147)

(9.148)

and (9.149)

From (9.105) and (9.147), the power loss in the inductor resistance rL is (9.150) The power loss in the inductor resistance rL may also be described in terms of the inductor average current IL and the averaged inductor resistance in the inductor branch rrLAV(L) (9.151) Hence, using the law of conservation of energy, one arrives at the averaged inductor resistance connected in series with the inductor L (9.152) The power loss in the switch ON-resistance rDS is (9.153) This power loss can also be expressed in terms of the dc inductor current IL as (9.154) Thus, the switch averaged resistance in the inductor branch is (9.155) The power loss in the diode forward resistance RF is

(9.156) The power loss in the diode forward resistance can also be expressed in terms of the dc inductor current as (9.157) Thus, the diode averaged resistance in the inductor branch is (9.158) From (9.152), (9.155), and (9.158), one obtains the total averaged resistance connected in series with the inductor L (9.159)

The power loss in the diode offset voltage is (9.160) On the other hand, this power may be written as (9.161) Hence, the averaged diode offset voltage connected in series with the inductor L is (9.162) Figures 9.22–9.24 depict small-signal models for buck, boost, and buck–boost converters for DCM operation, respectively. Figure 9.16 shows a block diagram of a small-signal model for a power stage of PWM dc–dc converters.

Figure 9.22 Small-signal model of PWM buck converter for DCM. (a) Buck converter. (b) Small-signal model for DCM.

Figure 9.23 Small-signal model of PWM boost converter for DCM. (a) Boost converter. (b) Small-signal model for DCM. (c) Small-signal model for boost converter with some components moved to the upper branches.

Figure 9.24 Small-signal model of PWM buck-boost converter for DCM. (a) Buck–boost converter. (b) Small-signal model for DCM.

9.13 Summary PWM converters are variable structure periodic systems. The ideal switches can be replaced by dependent current or voltage sources. The strength of the dependent sources is determined by the dc components of the terminal currents, voltages, and duty cycle. An ideal MOSFET can be modeled for dc components using an ideal dc current-dependent current source. An ideal diode can be modeled for dc components using an ideal dc voltage-dependent voltage source. An ideal switching network can be modeled for dc components using an ideal dc currentdependent current source and an ideal dc voltage-dependent voltage source.

The MOSFET on-resistance rDS and the diode forward resistance RF can be averaged using the law of conservation of energy. The MOSFET on-resistance rDS and the diode forward resistance RF can be also averaged by averaging the MOSFET on-conductance gDS = 1/rDS and the diode forward conductance GF = 1/RF. Large signal can be replaced by the dc and ac components. The averaged transistor and diode resistances as well as the averaged offset voltage source can be moved to different branches using the reflection rules. The averaged model of the actual switching network for the dc components can be transformed to a large-signal model by making all dc variables time dependent. The large-signal model can be transformed into a bilinear model for both dc and smallsignal ac components by neglecting nonlinear terms. The bilinear model can be simplified to a linear model for both dc and small-signal ac components. Since this model is linear, it can be split into a linear small-signal circuit model and a linear dc circuit model. The small-signal model of PWM dc–dc converters is valid only at low frequencies ranging from dc to the Nyquist frequency fs/2. The dc circuit model can be used to predict the open-loop and closed-loop converter behavior at dc. The small-signal circuit model can be used to predict the open-loop and closed-loop small-signal dynamic performance and stability of a PWM dc–dc converter. The dc and small-signal circuit models can be used in the design and simulation of PWM dc–dc power converters.

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Review Questions 1. Draw an ideal switching network of single-ended PWM converters. 2. Draw an actual switching network of single-ended PWM converters. 3. Draw an averaged large-signal model of an ideal switch for CCM. 4. Draw an averaged large-signal model of an ideal diode for CCM. 5. Draw an averaged large-signal model of an ideal switching network for CCM. 6. Draw an averaged large-signal model of an actual switch for CCM. 7. Draw an averaged large-signal model of an actual diode for CCM. 8. Draw an averaged large-signal model of an actual switching network with all the components in original branches for CCM. 9. Draw a simplified averaged large-signal model of an actual switching network for CCM. 10. Draw a nonlinear (bilinear) model of an actual switching network for CCM. 11. Draw a small-signal model of an actual switching network for CCM. 12. Draw a dc model of an actual switching network for CCM. 13. What is the frequency range in which the averaged small-signal model of the switching network is valid? 14. Draw a PWM small-signal switch model for CCM. 15. Draw a dc model of the actual switching network for DCM. 16. Draw a small-signal model of the actual switching network for DCM.

Problems 1. A single-ended transformerless PWM converter is operated under steady-state conditions in CCM. The duty cycle is D = 0.4. Find the components of an averaged model of the ideal switching network. 2. The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the original branches. 3. The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the inductor branch. 4. The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the switch branch. 5. The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and the duty cycle is D = 0.4. Find the values of the averaged parasitic components in the diode branch. 6. The parasitic components of a single-ended transformerless PWM converter operated under steady-state conditions in CCM are rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, rL = 0.2 Ω, and the duty cycle is D = 0.4. Find the total averaged parasitic resistance in the inductor branch. 7. The duty cycle of a single-ended transformerless PWM converter operated under steadystate conditions in CCM is D = 0.4 and the ESR of the inductor is rL = 0.2 Ω. Find the resistance of the inductor ESR in (a) the switch branch and (b) the diode branch. 8. A single-ended transformerless PWM converter operated under steady-state conditions in CCM has D = 0.4, VSD = 24 V, IL = 1.8 A, rDS = 1 Ω, RF = 24 mΩ, VF = 0.7 V, and rL = 0.2 Ω. Find the components of the small-signal model of the actual switching network with all parasitic elements in the inductor branch. 9. In the buck PWM converter with no parasitic components, the dc input voltage is turned on at t = 0. The inductance is high enough to operate the converter in CCM for steady state. Find the transient waveform of the inductor current without the switching-frequency component and its harmonics.

10 Small-Signal Characteristics of Buck Converter for CCM 10.1 Introduction In this chapter, small-signal characteristics are given for a power stage of the PWM buck converter operated in CCM [1–16]. A small-signal circuit model of the buck converter is developed using the small-signal model of the switching network. Subsequently, this model is used to derive a control law and open-loop transfer functions for the power stage of the buck converter, such as the control-to-output transfer function, the input-to-output transfer function, the input impedance, and the output impedance. In addition, the responses of the output voltage to step changes in the input voltage and the duty cycle are given. A dc circuit model is derived and is used to find the dc transfer functions and efficiency of the converter. All the converter performance characteristics are illustrated by examples.

10.2 Small-Signal Model of the PWM Buck Converter A circuit and a small-signal circuit model of the PWM buck converter for CCM operation are shown in Figure 10.1. This model can be obtained by (1) replacing the switching network in the complete circuit of the buck converter by the small-signal model and (2) reducing the dc components of the input voltage VI and the duty cycle D to zero. Notice that vsd = vi in the small-signal model of the switching network for the buck converter.

Figure 10.1 Circuit and small-signal model of the open-loop PWM buck converter for CCM. (a) Circuit of the PWM buck converter. (b) Small-signal circuit model of the open-loop PWM buck converter for CCM. From Figure 10.1, vo = 0 when VId + Dvi = 0; therefore, the control law is (10.1) or d/D = −vi/VI. Thus, the required relative change in the duty cycle d/D is equal in magnitude and opposite in sign to the relative change in the input voltage vi/VI.

10.3 Open-Loop Transfer Functions Figure 10.2 depicts a block diagram of the open-loop small-signal model of the PWM buck converter shown in Figure 10.1. It can be seen that both the small-signal model and the block diagram have three input variables d, vi, and io, and one output variable vo. Therefore, the

converter is a multi-input single output (MISO) system. The small-signal duty cycle d is a control variable, whereas small-signal input voltage vi and the small-signal load current io are disturbances. The two transfer functions can be defined as the control-to-output transfer function Tp and the input-to-output transfer function Mv, respectively. In addition, two impedances can be defined: the input impedance Zi and the output impedance Zo.

Figure 10.2 Block diagram of the open-loop small-signal model of the PWM converter. The output voltage can be found using the principle of superposition. The responses from many excitations can be computed as the sum of the responses resulting from each excitation acting alone. Thus, (10.2) Assuming a sinusoidal small-signal component of the duty cycle (10.3) the output voltage is (10.4) Likewise, assuming a sinusoidal small-signal component of the input voltage (10.5) the output voltage is

(10.6) Assuming a sinusoidal small-signal component of the load current (10.7) the output voltage is (10.8) Hence, the overall small-signal component of the output voltage is (10.9) The magnitudes |Tp(f)|, |Mv(f)|, and |Zo(f)| and the phases ϕTp(f), ϕMv(f), and ϕZo(f) are dependent on frequency. These magnitudes and phases are found in the subsequent analysis.

10.3.1 Open-Loop Control-to-Output Transfer Function Reducing the ac input voltage vi and the ac load current sink io to zero in the complete smallsignal model of the buck converter of Figure 10.1, one obtains a small-signal model shown in Figure 10.3. This model is a single-input single-output (SISO) system and can be described by a control-to-output transfer function, also called a duty ratio-to-output voltage transfer function. The output voltage is (10.10) where (10.11) and (10.12)

Hence, one obtains the control-to-outputtransfer function of the PWM buck converter in the sdomain

(10.13)

where (10.14) The low-frequency value of Tp is (10.15) The angular natural frequency, also called the angular undamped frequency or the angular corner frequency, is (10.16)

The time constants are (10.17) and (10.18) The damping ratio is (10.19) The quality factor is (10.20)

The ESR zero is (10.21) The angular frequency of the ESR zero is (10.22) The poles are (10.23) The damping factor is (10.24) The angular damped frequency is (10.25)

Figure 10.3 Small-signal model of the PWM converter for the derivation of the open-loop control-to-output transfer function Tp. The converter model of Figure 10.3 is a low-pass filter. The time constants can be determined using the open-circuit time-constant method. Setting d = 0 and L = ∞ (i.e., an open circuit), one

obtains an equivalent circuit comprised of the series combination of C, rC, and RL, whose time constant is τC = C(RL + rC). Similarly, setting d = 0 and C = 0 (i.e., an open circuit) produces an equivalent circuit composed of a series combination of L, r, and RL, whose time constant is τL = L/(RL + r). It can be seen that Tp is a second-order transfer function with two poles and one finite zero, all of which lie in the left-half of s-plane (LHP). The zero is real. The poles are real for ξ ≥ 1 (i.e., for

) or complex conjugates for ξ < 1 (i.e., for

). Both poles are the same for ξ

= 1 (i.e., for ). The damping ratio ξ decreases with increasing load resistance RL and increases with increasing parasitic resistances r and rC. The frequency of the zero fz is inversely proportional to rC. For rC = 0, fz = ∞. The frequency response can be found by setting σ = 0. In this case, s = jω and (10.13) becomes (10.26)

where (10.27)

and (10.28)

or (10.29)

Note that ϕTp(0) = 0. For fz f0, the peak of Tp is obtained by setting the derivative of the quantity under the square-root sign to zero. This peak occurs at

(10.30) and is equal to (10.31)

At f = f0 for fz f0, (10.32) The frequency response does not exhibit a peak for or at fz f0. Figure 10.4 shows idealized Bode plots of Tp. The decreasing slope of ϕTpi due to the second-order term with two complex conjugate poles in the denominator is ( − 90°/ξ)/decade. The increasing slope of ϕTpi due to the first-order term in the nominator (i.e., a zero) is 45°/decade.

Figure 10.4 Idealized Bode plots of the control-to-output transfer function Tp for the buck converter (without the delay). (a) Tp versus f. (b)

versus f.

Using expressions for L and C given in Chapter 2, we have for C = Cmin(on) (10.33)

(10.34) (10.35)

(10.36)

The maximum frequency of the zero is (10.37) For C = Cmin(off), (10.38) and (10.39)

Thus, the corner frequency f0 is directly proportional to the switching frequency fs. Typical values of f0 are in the range from 0.01fs to 0.02fs. The maximum frequency of the zero is (10.40) Thus, fz is directly proportional to the switching frequency fs. Typical values of fz are in the range from 0.06fs to 0.08fs. Example 10.1 A buck converter has the following specifications: continuous conduction mode (CCM), nominal input voltage VInom = 28 V, minimum input voltage VImin = 24 V, maximum input voltage VImax = 32 V, output voltage VO = 14 V, minimum output current IOmin = 0.14 A, maximum output current IOmax = 1.4 A, switching frequency fs = 100 kHz, converter efficiency at full power η = 90%, and the maximum peak-to-peak value of the ripple voltage on the dc output voltage to be Vr/VO ≤ 1%. Calculate r, Tpx, Tpo, fz, f0, ξ, Q, |Tp(pk)|, |Tp(f0)|, p1, p2, and fd at VInom, Dnom, and RLmin. Draw Bode plots of the control-to-output transfer function Tp. Solution: The calculated values of the minimum and the maximum load resistance are RLmin = 10 Ω and RLmax = 100 Ω. The calculated maximum, minimum, and nominal duty cycles are Dmax = 0.6481, Dmin = 0.4861, and Dnom = 0.555. For CCM, the minimum value of the inductor is Lmin = 256.95 μH. The inductor was made using a Phillips ferrite pot core 2616 PA A00

3C8 and using 15 turns of Belden solid copper magnet wire with AWG 26. The measured inductance was L = 301 μH and the measured dc ESR of the inductor was rL = 0.05 Ω. The maximum value of the ESR is rCmax = 0.5857 Ω. Pick rC = 0.4 Ω. The minimum calculated filter capacitance is Cmin = 8.1 μF. The standard value of 47 μF was chosen as the filter capacitance, and the measured capacitance was 51.2 μF with the ESR of rC = 0.391 Ω. The switching components used were an International Rectifier power MOSFET IRF 530 (200V/9A) with on-resistance rDS = 0.18 Ω and a Motorola power diode MUR 820 (200V/8A) with RF = 0.022 Ω and VF = 0.7 V. For Dnom = 0.555, rDS = 0.18 Ω, RF = 22 mΩ, and rL = 0.05 Ω, the equivalent resistance in series with inductor is (10.41) For VInom = 28 V, L = 301μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, Dnom = 0.555, and rC = 0.391 Ω, one obtains (10.42) (10.43) (10.44) (10.45) (10.46)

(10.47) (10.48)

(10.49) (10.50)

(10.51)

(10.52)

(10.53)

and (10.54) Figures 10.5 and 10.6 show the Bode plots of the magnitude Tp and the phase shift ϕ Tp of the control-to-output transfer function Tp for VInom = 28 V, Dnom = 0.555, L = 301μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. At low frequencies, the magnitude Tp is equal to 28.8 dB, next it increases to reach 35.8 dB at the frequency f = 1.23 kHz, and then it decreases at approximately − 40 dB per decade up to fz = 7.95 kHz and at approximately − 20 dB per decade for frequencies above fz. The magnitude Tp crosses 0 dB at f = 7.95 kHz. The phase shift ϕTp initially decreases from zero to reach a minimum value of − 145.95° at f = 3.18 kHz and then increases to − 90°. The − 3dB bandwidth is BW = 1.8 kHz. The corner frequency f0 is almost independent of the load resistance RL. In contrast, the damping ratio ξ and the quality factor Q strongly depend on the load resistance RL. The damping ratio ξ decreases with increasing load resistance RL. At RLmax = 100 Ω, f0 = 1.2812 kHz, ξ = 0.12553, and Q = 3.9831. The parasitic resistances rC and r slightly affect the value of f0. At rC = 0 and r = 0, kHz at any load resistance RL. Conversely, the damping ratio ξ is significantly affected by the presence of the parasitic resistances. At rC = 0 and r = 0, and Q = 4.1254 at RLmin = 10 Ω and ξ = 0.01212 and Q = 41.254 at RLmax = 100 Ω. At RLmin, ξactual/ξapprox = 0.2298/0.1212 = 1.896. Therefore, the parasitic resistances cannot be neglected for calculating ξ and Q.

Figure 10.5 The magnitude of the control-to-output transfer function Tp for the buck converter without the delay.

Figure 10.6 The phase of the control-to-output transfer function Tp without the delay.

10.3.2 Delay in Control-to-Output Transfer Function There is a delay td caused by power MOSFET, MOSFET driver, and pulse-width modulator. The delay can be represented by the function , which is not a rational function. It can be approximated by a first-order Padé function in the frequency range from dc to fs/2 (10.55)

where (10.56) and

(10.57) For s = jω, (10.58)

where (10.59)

and (10.60) The magnitude of the delay transfer function is equal to 1 at all frequencies. The phase of this transfer function is zero at low frequencies, starts to decrease at fpd/10, crosses − 90° at fpd, reaches − 180° at 10fpd, and then is equal to − 180°. For example, for td/Ts = tdfs = 0.1, fpd = 10fs/π ≈ 3.18fs and the phase of Td starts to decrease at fpd/10 = fs/π ≈ 0.318fs. Figures 10.7 and 10.8 depict Bode plots of Td given by the first-order Padé approximation versus f for td/Ts = 0.1 and fs = 100 kHz.

Figure 10.7 Magnitude of the delay function Td for td/Ts = 0.1 and fs = 100 kHz.

Figure 10.8 Phase of the delay function Td for td/Ts = 0.1 and fs = 100 kHz. The control-to-output transfer function that takes into account the delay is given by (10.61)

Figures 10.9 and 10.10 show Bode plots of Tp without and with the delay td = 1 μs. The phase of this transfer function has more negative values at high frequencies f > 0.1fpd as compared to that without the delay.

Figure 10.9 Bode plot of the magnitude of Tp without and with the delay for td = 1 μs and fs = 100 kHz, that is, for td/Ts = 0.1.

Figure 10.10 Bode plot of the phase of Tp without and with the delay for td = 1 μs and fs = 100 kHz, that is, for td/Ts = 0.1.

10.3.3 Open-Loop Input-to-Output Transfer Function Setting d = 0 and io = 0 in the complete small-signal model of the buck converter of Figure 10.1, one obtains a small-signal model shown in Figure 10.11. It is a single-input single-output (SISO) system and can be used to derive an input-to-output transfer function, also called a line-to-output voltage transfer function, or an audio susceptibility. Physically, this transfer function describes the input-to-output noise transmission. From Figure 10.11, the output voltage is (10.62) Hence, using (10.13), the input-to-output transfer function is derived as

(10.63)

where (10.64) and (10.65) Notice that Mv is a second-order transfer function with two poles and one zero in the LHP. The magnitude |Mv| is independent of VI and increases with increasing D; therefore, the worst case occurs at the maximum value of D. Physically, this observation is obvious because the longer the switch is ON, the larger the amount of noise is transmitted from the line to the converter output. Figure 10.12 shows idealized Bode plots of Mv.

Figure 10.11 Small-signal model of the PWM converter for the derivation of the open-loop input-to-output transfer function Mv and the open-loop input impedance Zi.

Figure 10.12 Idealized Bode plots of the input-to-output transfer function Mv. (a) |Mv| versus f. (b) versus f. Example 10.2 For the buck converter specified in Example 10.1, calculate Mvo at VInom, Dnom, and RLmin. Also, draw Bode plots of Mv. Solution. At f = 0, (10.66) Bode plots of Mv are shown in Figures 10.13 and 10.14 for VInom = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The − 3dB bandwidth is BW = 1.8 kHz.

Figure 10.13 Bode plot of the magnitude of the input-to-output transfer function Mv for the buck converter.

Figure 10.14 Bode plot of the phase of the input-to-output transfer function Mv the buck converter.

for

10.3.4 Open-Loop Input Impedance The open-loop input impedance of the converter can be derived using the model of Figure 10.11. The current through the inductor is (10.67) resulting in the input current (10.68) where Z = Z1 + Z2. Hence, using (10.11) and (10.12), one obtains the open-loop input impedance of the buck converter

(10.69)

where (10.70) and (10.71) Example 10.3 For the converter specified in Example 10.1, calculate fcr and Zi(0) at VInom, Dnom, and RLmin. Draw the plots of Zi versus frequency. Solution: Using (10.71), (10.72) At f = 0, (10.73) Figures 10.15 and 10.16 show plots of Zi for VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RL = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Notice that the equivalent circuit for the input impedance shown in Figure 10.11 contains a series resonant circuit. For this reason, the plots of the input impedance of the buck converter shown in Figure 10.15 are similar to those of the impedance for the series resonant circuit. At high frequencies, the input impedance is approximately equal to the reactance of the inductance, which increases with frequency.

Figure 10.15 The magnitude of the open-loop input impedance Zi of the buck converter loaded by the load resistance RL.

Figure 10.16 The phase of the open-loop input impedance Zi of the buck converter loaded by the load resistance RL.

10.3.5 Open-Loop Output Impedance Figure 10.17 shows a small-signal model for the derivation of the open-loop output impedance of the buck converter including the load resistance RL. This model is obtained by setting vi = 0, d = 0, and io = 0 in the complete small-signal model of the buck converter of Figure 10.1. To find the output impedance, one can apply a test voltage source vt across the load resistance RL and determine the current it forced by the test voltage source. The ratio of the voltage vt to the current it is equal to the output impedance Zo. Thus, using (10.11) and (10.12), one arrives at the open-loop output impedance of the buck converter loaded by the load resistance RL

(10.74)

where (10.75) and (10.76) For s = 0, (10.77)

Figure 10.17 Small-signal model of the PWM converter for the derivation of the open-loop output impedance Zo. At high frequencies, (10.78) Since vt = vo and it = −io, the output impedance is (10.79) Example 10.4 For the buck converter specified in Example 10.1, calculate frl and Zo(0) at VInom, Dnom, and RLmin. Also, draw the plots of Zo versus frequency. Solution: From (10.76), (10.80) At f = 0, (10.81) Figures 10.18 and 10.19 show plots of Zo for VInom = 28 V, Dnom = 0.555, L = 301 μH, C =

51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The maximum value of the open-loop output impedance Zo occurs at frequency f0 = 1.2677 kHz and is equal to Zo = 5.2 Ω. At f = 100 Hz, Zo = 264 mΩ. It can be seen in Figure 10.17 that the output impedance is formed by a parallel resonant circuit. This is consistent with the plots shown in Figure 10.18.

Figure 10.18 The magnitude of the open-loop output impedance Zo of the buck converter.

Figure 10.19 The phase of the open-loop output impedance Zo of the buck converter.

10.4 Open-Loop Step Responses 10.4.1 Open-Loop Response of Output Voltage to Step Change in Input Voltage Suppose that there is a step change in the input voltage of magnitude ΔVI at time t = 0 for fixed duty cycle D and load resistance RL. The total input voltage is described by (10.82) where u(t) is the unit step function and VI(0−) is the steady-state input voltage before the step change. The step change of the input voltage in the time domain is given by (10.83) The step change of the input voltage in the s-domain is

(10.84) Using (10.63) and (10.84), one obtains the transient component of the output voltage of the open-loop buck converter in the s-domain (10.85) The pole of vo(s) at s = 0 produces a constant term and the two complex-conjugate poles produce a sinusoidal term in vo(t); therefore, vo(t) is composed of a constant and a sinusoid. The inverse Laplace transform of (10.85) gives the transient component of the output voltage of the open-loop buck converter in the time domain (10.86)

where (10.87)

and (10.88)

For f0 fz, the step response is critically damped for ζ = 1. The total output voltage is (10.89) where VO(0−) is the output voltage at time t = 0−, that is, just before the step change in the input voltage. Taking the derivative of (10.86) with respect to ω0t and setting the result to zero, one obtains (10.90)

(10.91) (10.92) (10.93) where (10.94) From (10.93), the maxima and minima of vo occur at (10.95) where n is an integer. Since (10.96)

or (10.97)

(10.95) becomes (10.98)

or (10.99)

The first maximum of vo is the highest one and occurs for n = 2. Thus,

(10.100)

or (10.101)

Substitution of (10.100) or (10.101) into (10.86) gives (10.102) and yields the highest maximum of vo (10.103)

resulting in the maximum overshoot of the transient component of the output voltage vo (10.104) where vo(∞) = ΔVIMvo is the final steady-state value of the transient small-signal component of the output voltage vo after the transition. Figure 10.20 shows the percent maximum overshoot as a function of fz/f0 at fixed values of ξ. For fz/f0 > 3, Smax is nearly independent of fz/f0. However, for fz/f0 ≤ 3, Smax increases as fz/f0 decreases.

Figure 10.20 Maximum percent overshoot as a function of fz/f0 at fixed values of ξ. For fz/f0 ξ, the poles are dominant, (10.105)

and (10.98) can be approximated by (10.106) This approximation usually holds true for Tp and Mv of a buck converter. The highest maximum of vo occurs for n = 2 at

(10.107) Substitution of (10.107) into (10.103) produces the maximum output voltage (10.108)

yielding the maximum overshoot (10.109)

This expression can be approximated by (10.110) The maximum relative transient ripple of the total output voltage is defined as (10.111) where vO(∞) = VO(0−) + vo(∞) = VO(0−) + MvoΔVI is the final steady-state value of the total output voltage after the transition. The ± 5% settling time is (10.112) The delay time is (10.113) and the rise time is (10.114) Example 10.5 For the open-loop buck converter specified in Example 10.1, draw the waveform of the output voltage vO that is a response to the step change in the input voltage vI from 28 to 29 V. Calculate (a) the maximum overshoot of the transient component of the output voltage, (b) the steady-state values of the transient component and the total output voltage, and (c) the maximum relative transient ripple of the total output voltage.

Solution: Figure 10.21 shows a step response of the output voltage vO to a step change in the input voltage vI from 28 to 29 V, which corresponds to a step change of vi from 0 to 1 V, for the buck converter without feedback at Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The output voltage increases from 14 to 14.8 V and reaches its final steady-state value of vO(∞) = 14.55 V after approximately 3 ms. From Example 10.1, ξ = 0.2298, fz = 7.95 kHz, and f0 = 1.2677 kHz. Because fz/f0 = 6.27 ξ = 0.2298, (10.115) yielding tm = 3.228/(2πf0) = 3.228/(2π × 1262.7) = 0.4053 ms. For the same reason, equation (10.109) can be used to calculate the maximum overshoot of the transient component of the output voltage vo (10.116)

Using (10.66), one obtains the steady-state value of the transient component of the output voltage (10.117) The maximum value of the transient component of the output voltage is (10.118) The steady-state value of the total output voltage is (10.119) Hence, the maximum relative transient ripple of the output voltage is (10.120) The ± 5% settling time is (10.121) The delay time is

(10.122) and the rise time is (10.123)

Figure 10.21 Step response of vO to a step change in vI from 28 to 29 V for the buck converter without feedback for Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω.

10.4.2 Open-Loop Response of Output Voltage to Step Change in Duty Cycle Let us assume that there is a step change in the duty cycle ΔdT at time t = 0 for fixed input voltage VI and load resistance RL. The total duty cycle is

(10.124) The step change in the duty cycle in the time domain is given by (10.125) which results in (10.126) Hence, using (10.13), the transient component of the output voltage of the open-loop buck converter in the s-domain is (10.127) The inverse Laplace transform gives the output voltage of the open-loop buck converter in the time domain (10.128)

where ϕ is given by (10.87). The total output voltage vO can be found from (10.89). The maximum overshoot of vo is given by (10.104) or (10.109). Example 10.6 For the open-loop buck converter specified in Example 10.1, draw the waveform of the output voltage vO that is a response to the step change in the duty cycle dT from 0.555 to 0.655. Solution: Figure 10.22 shows a step response of the output voltage vO to a step change in the control input dT from 0.555 to 0.655, for d = 0.1 for the buck converter without feedback at VI = 28 V, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The output voltage vO increases from 14 V to a peak value of 18.05 V and then reaches a final steady-state value of approximately 16.75 V after 3 ms. Since Tpo = 27.559 V, the final steady-state value of the transient component of the output voltage is (10.129) The first maximum occurs at tm = 0.4053 ms. The maximum overshoot is given by (10.116) and is Smax = 0.4647. Therefore, the maximum value of the transient component of the output voltage is

(10.130) The final total output voltage is (10.131) Thus, the maximum relative transient ripple of the output voltage is (10.132)

Figure 10.22 Step response of vO to a step change in the duty cycle dT from 0.555 to 0.655 for the buck converter without feedback for VInom = 28 V, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω.

10.4.3 Open-Loop Response of Output Voltage to Step Change in Load Current Consider a step change in the load current ΔIO at time t = 0 for fixed input voltage VI and duty

cycle D. The total load current is described by (10.133) Hence, the step change in the load current in the time domain is (10.134) and in the s-domain is (10.135) This results in the transient component of the output voltage in the s-domain (10.136) and in the time domain (10.137) The total output voltage vO(t) can be found from (10.89). Example 10.7 For the open-loop buck converter given in Example 10.1, draw the waveform of the output voltage vO that is a response to the step change in the load current IO from 1.4 to 1.5 A. Calculate the output voltage for steady state after the transition and the maximum relative transient ripple. Solution: Figure 10.23 shows a step response of the output voltage vO to a step change in the load current iO from 1.4 to 1.5 A for the buck converter without feedback at VI = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. The output voltage vO decreases from 14 V to a minimum value of 12.82 V and then reaches a final steady-state value of approximately 13.98 V after 3 ms. The dc output resistance is Zo(0) = Ro(0) = RLminr/(RLmin + r) = 0.157 Ω. The change in the steady-state output voltage is (10.138) yielding the output voltage after the transition (10.139) The step change of vo at t = 0 is (10.140) From Figure 10.23, vomin = 190 mV, yielding the maximum undershoot of the output voltage

(10.141) and the maximum relative transient ripple of the output voltage (10.142)

Figure 10.23 Step response of vO to a step change in the load current IO from 1.4 to 1.5 A for the buck converter without feedback for VInom = 28 V, D = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω.

10.5 Open-Loop DC Transfer Functions Figure 10.24 shows a dc model of the buck converter, which is obtained by replacing the switching network in the complete buck converter circuit by a dc model, replacing the inductance L with a short circuit, and replacing the filter capacitor branch with an open circuit. Notice that VSD = VI. From Figure 10.24, the dc output voltage is

(10.143)

which gives the dc input-to-output voltage transfer function of the lossy buck converter at fixed value of VI is (10.144) Hence, MVDC = 0 at (10.145) For D = 1, (10.146)

Figure 10.24 DC model of the PWM buck converter. Substituting VI = VO/MVDC into (10.144), one obtains the dc voltage transfer function at a fixed value of the output voltage VO (10.147) Since the dc input current is II = DIL and the output current is IO = IL, the dc current transfer function is obtained as

(10.148) This function is independent of r and VF. Using (10.147) and (10.148), the converter efficiency is obtained as (10.149) For D = 0, r = RF + rL and the efficiency is given by (10.150) As D approaches 1, r = rDS + rL and the efficiency becomes (10.151) Equations (10.147) and (10.149) show that the dc voltage transfer function is (10.152) The dc duty cycle-to-output voltage transfer function is (10.153) Switching losses are neglected in the above equations.

10.6 Summary A small-signal model of the PWM buck converter can be derived by replacing its switching network by a small-signal model, and reducing the dc component of the input voltage source VI and the dc component of the duty cycle D to zero. A dc model of the PWM buck converter can be derived by replacing its switching network by a dc model, and reducing the ac component of the input voltage source vi and the ac component of the duty cycle d to zero. The small-signal model has three inputs (the duty cycle d, the input voltage vi, and the load current io) and one output (the output voltage vo). A small-signal model of the buck converter can be simplified to obtain appropriate models to derive open-loop transfer functions and impedances. The control-to-output transfer function of the PWM buck converter is a second-order low-

pass function with two poles and one zero located in the left half of the s-plane. The poles are real for ξ ≥ 1 (i.e., Q ≤ 0.5), and the poles are complex conjugate for ξ ≤ 1 (i.e., Q > 0.5). At ξ = 1 (i.e., Q = 0.5), the poles are real and equal. The magnitudes of the transfer functions |Tp| and |Mv| exhibit peaking for

(i.e.,

). The maximum overshoot of step responses to step changes of d and vi is zero for ξ ≥ 1 (i.e., Q ≤ 0.5). The step responses exhibit ringing for ξ < 1/4 (i.e., Q > 2).

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched–Mode Power Conversion, vols. I and II. Pasadena, CA: TESLAco, 1981. 2. R. D. Middlebrook and S. Ćuk, “A general unified approach to modeling switching– converter power stages,” IEEE Power Electronics Specialists Conference Record, 1976, pp. 18–34. 3. W. M. Polivka, P. R. K. Chetty, and R. D. Middlebrook, “State–space average modeling of converters with parasitics and storage time modulation,” IEEE Power Electronics Specialists Conference Record, 1980, pp. 119–143. 4. R. P. Severns and G. Bloom, Modern DC–to–DC Switchmode Power Converter Circuits. New York: Van Nostrand, 1985, pp. 30–42 and 130–135. 5. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw–Hill, 1988, pp. 74– 76. 6. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, ch. 10, 2nd Ed. New York: John Wiley and Sons, pp. 301–353. 7. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading: Addison–Wesley, 1991, pp. 251–402. 8. V. Vorpérian, “Simplified analysis of PWM converters using the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES–26, pp. 497–505, May 1990. 9. D. Czarkowski and M. K. Kazimierczuk, “Circuit models of PWM dc-dc converters,” Proceedings of the IEEE National Aerospace and Electronics Conference (NEACON’92), Dayton, OH, May 8–22, 1992, pp. 407–413. 10. D. Czarkowski and M. K. Kazimierczuk, “Linear circuit models of PWM flyback and

buck/boost converters,” IEEE Transactions on Circuits and Systems, Part I, Fundamental Theory and Applications, vol. CAS-39, pp. 688-693 August 1992. 11. D. Czarkowski and M. K. Kazimierczuk, “A new and systematic method of modeling PWM dc-dc converters,” Proceedings of the International Conference on Systems Engineering, Kobe, Japan, September 17–19, 1992, pp. 628–631. 12. D. Czarkowski and M. K. Kazimierczuk, “Static- and dynamic-circuit models of PWM buck-derived dc-dc converters,” IEE Proceedings Part G: Circuits, Devices and Systems, vol. 139, no. 6, pp. 669–679 December 1992. 13. D. Czarkowski and M. K. Kazimierczuk, “Energy-conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-29, pp. 1059-1063 July 1993. 14. M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” Proceedings of the 2nd IEEE Conference on Control Applications, Vancouver, Canada, September 13–16, 1993, pp. 291–296. 15. M. K. Kazimierczuk, N. Sathappan, and D. Czarkowski, “A voltage-mode-control PWM buck dc-dc converter with a proportional controller,” Proceedings of the IEEE National Aerospace and Electronic Conference (NAECON’93), Dayton, OH, May 24–28, 1993, vol. 2, pp. 639–644. 16. A. Ayachit and M. K. Kazimierczuk, “Open-loop small-signal transfer functions of the quadratic buck PWM dc-dc converter in CCM,” 40th Annual Conference of the IEEE Industrial Electronics Society (IECON14), October 29-November 1, 2014, Dallas, TX, pp. 1643–1649.

Review Questions 1. Draw a small-signal model of the PWM buck converter. 2. Draw a dc model of the PWM buck converter. 3. Derive a control law for the PWM buck converter. 4. Draw a small-signal model for the PWM buck converter for deriving the open-loop control-to-output transfer function. 5. Derive an open-loop small-signal control-to-output transfer function for the buck converter. 6. What is the order of the open-loop control-to-output transfer function? 7. What is the location of the poles and the zero of the open-loop control-to-output transfer function in the s-plane? 8. Draw a small-signal model of the PWM buck converter for deriving the open-loop inputto-output transfer function.

9. Derive an open-loop small-signal input-to-input transfer function for the buck converter. 10. What is the physical meaning of the input-to-output transfer function. 11. Draw a small-signal model of the PWM buck converter for deriving the open-loop input impedance. 12. Derive the open-loop input impedance for the buck converter. 13. Explain the behavior of the input impedance versus frequency. 14. Draw a small-signal model of the PWM buck converter for deriving the open-loop output impedance. 15. Derive the open-loop output impedance for the buck converter. 16. Explain the behavior of the output impedance versus frequency.

Problems 1. An open-loop buck converter has VInom = 28 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 mΩ, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine z, fz, f0, ξ, Q, p1, p2, and fd. 2. An open-loop buck converter has VImin = 24 V, VInom = 28 V, VImax = 32 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine Tpo. 3. An open-loop buck converter has VImin = 24 V, VInom = 28 V, VImax = 32 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine fpk and |Tp(pk)|. 4. An open-loop buck converter has VImin = 24 V, VInom = 28 V, VImax = 32 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine Mvo, fpk , and |Mv(pk)|. 5. An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine fcr and Zi(0). 6. An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmin = 1.2 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine frl, Zo(0), and Zo(∞). 7. An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmax = 12 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine the approximate values of f0, ξ, and Q. Find also the ratio of the actual to approximate values of ξ.

8. An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmax = 12 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine the values of f0, ξ, Q, p1, p2, and fd. 9. An open-loop buck converter has Dnom = 0.5, rDS = 55 mΩ, RF = 25 Ω, VO = 12 V, RLmax = 12 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine the approximate values of ξ and Q. Calculate also the ratio of the actual to approximate values of ξ. 10. An open-loop buck converter has VInom = 28 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 mΩ, VO = 12 V, RLmin = 100 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. Determine Tpo, z, fz, f0, ξ, Q, p1, p2, and fd. 11. An open-loop buck converter has VInom = 28 V, Dnom = 0.5, rDS = 55 mΩ, VF = 0.4 V, RF = 25 mΩ, VO = 12 V, RLmin = 100 Ω, L = 40 μH, rL = 100 mΩ, C = 100 μF, and rC = 50 mΩ. There is a step change of the input voltage from 28 to 29 V. Determine Smax, vo(∞), vOmax, and δmax.

11 Small-Signal Characteristics of Boost Converter for CCM 11.1 Introduction The aims of this chapter are: (1) to introduce dc and small-signal linear circuit models of the PWM boost dc–dc converter, taking into account parasitic resistances of reactive components and power switches and also the offset voltage of the power diode; (2) to derive and illustrate the dc voltage transfer function and efficiency using the dc model; and (3) to derive and illustrate the small-signal open-loop control-to-output transfer function, input-to-output transfer function, input impedance, and output impedance using the small-signal model. Responses of the output voltage to step changes in the duty cycle, input voltage, and load current are also given. The dynamics of the PWM boost converter has been studied in [1–14].

11.2 DC Characteristics A dc model of the boost converter is shown in Figure 11.1. This model can be derived by replacing switching devices in the boost converter with the dc model of the actual switching network, the inductance L with a short circuit, and the capacitance C with an open circuit. The equivalent resistance in the inductor branch is (11.1) Since the battery representing the diode offset voltage VF is moved to the inductor branch, (11.2) In addition, (11.3) Using the KCL, (11.4) which gives the dc current transfer function (11.5) Since IO = VO/RL,

(11.6)

Figure 11.1 DC model of the PWM boost converter. Using the KVL, (11.7) which yields (11.8)

Hence, one obtains the dc input-to-output voltage transfer function (11.9) and the dc control-to-output transfer function (11.10)

From (11.5) and (11.9), the efficiency of the converter is (11.11) Switching losses are neglected in this equation. Figures 11.2 and 11.3 show the dc voltage transfer function MV DC and the efficiency η as a function of D at RL = 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω.

Figure 11.2 DC voltage transfer function MV DC as a function of the duty cycle D at RL = 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω.

Figure 11.3 Efficiency η as a function of the duty cycle D at RL= 40 Ω, VO = 20 V, rDS = 0.18 Ω, VF = 0.3 V, RF = 72 mΩ, and rL = 0.19 Ω.

11.3 Open-Loop Control-to-Output Transfer Function A small-signal model of the PWM boost converter for CCM operation is shown in Figure 11.4(a). This model is obtained by replacing the switching network in the boost converter with a small-signal model. Figure 11.4(b) shows a block diagram of the open-loop boost converter. Setting vi = 0 and io = 0 in Figure 11.4(a), one obtains a small-signal model of the boost converter for determining the control-to-output transfer function shown in Figure 11.5. Note that (11.12) The current through the parallel combination of the load resistance and the filter capacitance is

(11.13) and the current through the inductor is (11.14) which, from (11.6), produces (11.15)

Figure 11.4 Small-signal model and block diagram of the PWM boost converter for CCM. (a) Small-signal model. (b) Block diagram.

Figure 11.5 Small-signal model of the PWM boost converter for determining the control-tooutput transfer function Tp. Using the KVL, (11.16) Substituting (11.15) into (11.16) yields (11.17) which becomes (11.18) Hence, using (11.6), one obtains the control-to-output transfer function (11.19)

The impedances Z1 and Z2 are (11.20) and

(11.21)

Substitution of (11.20) and (11.21) into (11.19) gives the control-to-output transfer function (or the duty ratio-to-output transfer function) in the s-domain (11.22)

where the magnitude of Tp at high frequencies (11.23) the magnitude of Tp at f = 0 is (11.24) the angular corner frequency or the angular natural undamped frequency is (11.25)

the time constants are (11.26) (11.27) the damping ratio is

(11.28) the quality factor is (11.29) the damping factor (11.30) the angular damped frequency (11.31) the ESR zero, which is a left-half plane (LHP) or negative zero, is given by (11.32) the angular frequency of the ESR zero is (11.33) the right-half plane (RHP) or positive zero and its angular frequency are (11.34) and the poles are (11.35) The control-to-output transfer function Tp is a second-order low-pass function, which has two LHP poles, one LHP zero, and one RHP zero. The boost converter is a non-minimum phase system because it has RHP zero. The LHP zero zn is independent of D, whereas the poles and the RHP zero depend on D. As D is increased from 0 to 1, the RHP zero zp decreases from a maximum value of (RL − r)/L, crosses zero when r = RL(1 − D)2, becomes negative, and reaches a minimum value of − r/L. In other words, zp is moving from a location in the righthand plane to the origin, and then enters the left-hand plane at D = 1. When D is increased from 0 to 1, the corner frequency f0 decreases and the damping factor ξ increases. The maximum value of zp occurs at RLmax and VImax, whereas the minimum value of zp occurs at RLmin and

VImin. For D = 0, r = RF + rL and (11.36) and for D = 1, r = rDS + rL and (11.37) Hence, (11.38) Using the reflection rule, the resistance r can be moved from the inductor branch to the diode branch. This equivalent resistance is given by (11.39) As D is increased from 0 to 1, re increases from rL + RF to ∞. The equivalent inductance connected in series with the C-rC-RL circuit is (11.40) Another method for deriving the equivalent inductance Le is based on the principle of energy conservation. The average inductor and diode currents are related by (11.41) The energy stored in the inductance L located in its original branch is (11.42) and the energy stored in the equivalent inductance Le located in the diode branch is (11.43) Hence, Le = L/(1 − D)2.

Example 11.1 A boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Calculate r, zn, fzn, zp, fzp, f0, ξ, Q, p1, p2, and fd at RLmin = 40 Ω. Plot r, fzp, f0, and ξ versus D. Solution: The total parasitic resistance in series with the inductor at Dnom = 0.5 is (11.44) Figure 11.6 shows a plot of r versus D for rDS = 0.18 Ω, RF = 72 mΩ, and rL = 0.19 Ω. The LHP zero is (11.45) and the frequency of the LHP zero is (11.46) The RHP zero is (11.47) and the frequency of the RHP zero is (11.48) Figure 11.7 shows a plot of f0 versus D for rDS = 0.18 Ω, RF = 72 mΩ, rL = 0.19 Ω, rC = 111 mΩ, and RL = 40 Ω. The corner frequency is (11.49)

Figure 11.8 shows a plot of fzp versus D for rDS = 0.18 Ω, RF = 72 mΩ, rL = 0.19 Ω, rC = 111 mΩ, and RL = 40 Ω. The damping ratio is

(11.50)

and the quality factor is (11.51) Figure 11.9 shows a plot of ξ versus D for rDS = 0.18 Ω, RF = 72 mΩ, rL = 0.19 Ω, rC = 111 mΩ, and RL = 40 Ω. The poles are (11.52) and the damped frequency is (11.53) At r = rC = 0, the approximate equations give fzp ≈ RLmin(1 − Dnom)2/(2πL) = 20.4 kHz, Hz, , Q = 1/2ξ ≈ 13.2, rad/s, and fd ≈ 771.49 Hz. Note that ξlossy/ξlossless = 0.261/0.03787 = 6.89. Therefore, the parasitic components cannot be neglected.

Figure 11.6 Total parasitic resistance r as a function of D for rDS = 0.18 Ω, RF = 0.072 Ω, and rL = 0.19 Ω.

Figure 11.7 Frequency of the RHP zero fzp as a function of D for the boost converter at VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω for RL = 40 Ω.

Figure 11.8 Corner frequency f0 as a function of D for the boost converter at VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω for RL = 40 Ω.

Figure 11.9 Damping ratio ξ as a function of D for RL = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. Substitution of s = jω into (11.22) yields (11.54)

where (11.55)

and (11.56)

or (11.57)

Figure 11.10 shows idealized Bode plots of the open-loop control-to-output transfer function Tp for the boost converter.

Figure 11.10 Idealized Bode plots of the open-loop control-to-output transfer function Tp for the boost converter (without the delay). (a) |Tp| versus f. (b) ϕTp versus f.

11.4 Delay in Open-Loop Control-to-Output Transfer Function The delay time td introduced by the power transistor, the power transistor driver, and the pulse-width modulator can be described by the function or . Hence, |Td| = 1 and the phase due to the delay time is (11.58) The delay function Td(s) can be approximated by a first-order Padé rational function for frequencies from dc to fs/2

(11.59)

where ωzd = ωpd = 2/td. For s = jω, (11.60)

where |Td| = 1 and (11.61) Figure 11.11 shows the exact and approximate plots of the delay phase ϕTp using the first-order Padé rational function. The difference between the first-order approximation and the exact plot is within 5° for f/fpd ≤ 0.5.

Figure 11.11 Exact and approximated delay phase ϕTd. The control-to-output transfer function with the delay is (11.62) If the ac component of the duty cycle is given by d = dmcos ωt, the ac component of the output voltage is given by (11.63) Example 11.2 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, calculate Tpo and Tp(∞) at RLmin = 40 Ω. Draw the Bode plots of Tp for D = 0.5 at td = 0 and td = 1 μs. Solution: From (11.24),

(11.64)

The approximate equation gives Tpo ≈ VO/(1 − Dnom) = 20/(1 − 0.5) = 40 V = 32 dBV. From (11.23), (11.65) which gives |Tpx| = |Tp(∞)| = −19 dBV. Figures 11.12 and 11.13 show Bode plots of Tp for the boost converter with and without the delay. The − 3 dB bandwidth at D = 0.5 is BW = 1 kHz.

Figure 11.12 Bode plot of the magnitude of the open-loop control-to-output transfer function Tp without and with the delay td = 1 μs for the boost converter.

Figure 11.13 Bode plot of the phase of the open-loop control-to-output transfer function Tp for the boost converter without and with the delay td = 1 μs.

11.5 Open-Loop Audio Susceptibility Setting d = 0 and io = 0 in the small-signal model of the boost converter of Figure 11.4 gives a small-signal model shown in Figure 11.14 that can be used for deriving the input-to-output voltage transfer function Mv. From the KCL, (11.66) which can be rearranged to the form (11.67) From the KVL,

(11.68) Substitution of (11.67) into (11.68) produces (11.69) Thus, the open-loop input-to-output transfer function is obtained (11.70)

Substituting (11.20) and (11.21) into (11.70), one obtains the input-to-output voltage transfer function (also called the line-to-output voltage transfer function or the audio susceptibility) (11.71)

Hence, (11.72)

(11.73) and (11.74) Notice that Mvo ≈ 1/(1 − D) for r/(1 − D)2 RL and is the same as the dc voltage transfer function MV DC for the lossless boost converter.

Figure 11.14 Small-signal model of the PWM boost converter for determining the input-tooutput transfer function Mv. For s = jω, (11.75)

which gives (11.76)

Figure 11.15 shows idealized Bode plots of the open-loop input-to-output transfer function Mv for the boost converter. The slope of the phase is ( − 90°/ξ)/decade Example 11.3 The boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, Calculate Mvo at RLmin = 40 Ω and draw the Bode plot of |Mv| at D = 0.5.

Solution: From (11.72), (11.77) Figures 11.16 and 11.17 show the Bode plots of Mv. It can be seen that Mvo increases with increasing duty cycle D. In addition, |Mv| decreases with increasing frequency above f0 = 784 Hz at a rate of − 40 dB/decade and above fzn = 21.09 kHz at a rate of − 20 dB/decade. The − 3 dB bandwidth is BW = 1 kHz at D = 0.5.

Figure 11.15 Idealized Bode plots of the open-loop input-to-output transfer function Mv for the boost converter in CCM. (a) |Mv| versus f. (b) ϕMv versus f.

Figure 11.16 Bode plot of the magnitude of the open-loop input-to-output transfer function |Mv| versus frequency for the boost converter.

Figure 11.17 Bode plot of the phase of the open-loop input-to-output transfer function |Mv| versus frequency for the boost converter.

11.6 Open-Loop Input Impedance The equivalent circuit of Figure 11.14 can be used to derive the open-loop small-signal input impedance of the boost converter. Note that ii = il and iZ2 = vo/Z2. Hence, using KCL, (11.78) Hence, the output voltage is (11.79) Using KVL, (11.80)

Substitution of (11.79) into (11.80) yields (11.81) Hence, the open-loop input impedance is (11.82)

(11.83)

where (11.84) From (11.83), (11.85) and (11.86) Example 11.4 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, calculate frc and Ri(0) at RLmin = 40 Ω. Draw the plots of Zi at D = 0.5. Solution: Using (11.84), (11.87) From (11.85), (11.88) Figures 11.18 and 11.19 show the plots of Zi versus frequency. These plots are similar to those of a series resonant circuit. It can be seen that |Zi| decreases with increasing D and rapidly increases with frequency above 1 kHz.

Figure 11.18 The magnitude of the open-loop input impedance Zi for the boost converter.

Figure 11.19 The phase of the open-loop input impedance Zi for the boost converter.

11.7 Open-Loop Output Impedance A small-signal model of the boost converter for deriving the open-loop output impedance is shown in Figure 11.20. This model is obtained by reducing d, vi, and io to zero and applying an independent voltage source vt at the output of the model. The voltage source vt will force a current it. The open-loop output impedance is equal to the ratio of the voltage vt and the current it. From the KVL, (11.89) which gives (11.90)

From the KCL, (11.91) and (11.92) Hence, the open-loop output impedance (including the load resistance RL) is (11.93)

Thus, (11.94)

where (11.95) From (11.94), (11.96) and (11.97) Example 11.5 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω, calculate frl, Zo(0), and Z(∞) at RLmin = 40 Ω. Draw the plots of Zo at Dnom = 0.5. Solution: From (11.95), (11.98) From (11.96),

(11.99) The output impedance at high frequencies is (11.100) Figures 11.21 and 11.22 show the plots of the output impedance Zo versus frequency. The plots of Zo are similar to those of a parallel resonant circuit. It can be seen that the dc output impedance is R(0) = 1.225 Ω. The magnitude of output impedance |Zo| is nearly constant for frequencies from 0 to frl = 322.55 Hz, then increases with increasing f, reaches a maximum value of about 6.2 Ω at f0 = 784 Hz, and finally decreases to rC||RLmin with increasing f. The magnitude |Zo| increases with D at low frequencies because r/(1 − D)2 increases with D.

Figure 11.20 Small-signal model of the PWM boost converter for determining the output impedance Zo.

Figure 11.21 The magnitude of the open-loop output impedance Zo for the boost converter.

Figure 11.22 The phase of the open-loop output impedance Zo for the boost converter.

11.8 Open-Loop Step Responses 11.8.1 Open-Loop Response of Output Voltage to Step Change in Input Voltage Let us consider a step change in the input voltage of magnitude ΔVI at time t = 0. The total input voltage is given by (11.101) (0−) is the steady-state input voltage before the step

where u(t) is the unit step function and VI change. The step change of the input voltage in the time domain is expressed by

(11.102) which gives the step change of the input voltage in the s-domain

(11.103) Hence, from (11.71) and (11.103), the transient component of the output voltage of the openloop boost converter in the s-domain is obtained as (11.104) This produces the transient component of the output voltage of the open-loop boost converter in the time domain (11.105)

where (11.106)

or (11.107)

The final steady-state value of the small-signal output voltage after the transient is (11.108) The total output voltage is (11.109) where VO(0−) is the output voltage at time t = 0−. Setting the derivative of (11.105) to zero, one obtains the time instants at which the maximum and minimum values of vo occur (11.110) where n is an integer. The first maximum value of vo is the highest one and occurs for n = 1. Letting n = 1,

(11.111) The highest maximum value of vo is given by (11.112)

resulting in the maximum overshoot of the transient component of the output voltage vo (11.113)

where vo(∞) = ΔVIMvo is the final steady-state value of the transient component of the output voltage vo after the transition. For ξ ≥ 1, the step response does not exhibit any overshoot, that is, vo(t) ≤ vo(∞). The maximum relative transient ripple of the total output voltage is defined as (11.114) where vO(∞) = VO(0−) + vo(∞) = VO(0−) + MvoΔVI is the final steady-state value of the total output voltage after the transition. The 5% settling time is (11.115) The delay time is (11.116) The rise time is (11.117) Example 11.6 For the open-loop boost converter specified in Example 11.1, draw the waveform of the output voltage vO that is a response to the step change in the input voltage from 12 to 13 V. Calculate (a) the maximum overshoot of the transient component of the output voltage, (b) the final steady-state values of the transient component and the total output voltage,

(c) the maximum relative transient ripple of the total output voltage. Solution: Figure 11.23 shows a step response of the transient component of the output voltage vo to a step change in the input voltage vI from 12 to 13 V, which corresponds to a step change in vi from 0 to 1 V, for the boost converter without feedback at Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. The output voltage waveform vO obtained from the MATLAB® simulation shown in Figure 11.23 shows that the output voltage increases from 20 V to its peak value of 22.738 V and then reaches its final steady-state value of vO = 21.939 V after approximately 3 ms. From Examples 11.1 and 11.3, ξ = 0.261, fzn = 21.09 kHz, f0 = 784 Hz, and Mvo = 1.939. The final steady-state value of the transient component of the output voltage is (11.118) Using (11.113), one can compute the maximum overshoot of the transient component of the output voltage vo (11.119)

Hence, the maximum value of the transient component of the output voltage is (11.120) The final steady-state value of the total output voltage after the transient is (11.121) Thus, the maximum relative transient ripple of the output voltage is (11.122) The 5% settling time is (11.123) The delay time is (11.124) The rise time is

(11.125)

Figure 11.23 Response of the output voltage vO to a step change in vI from 12 to 13 V for the boost converter without feedback for Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω.

11.8.2 Open-Loop Response of Output Voltage to Step Change in Duty Cycle Assume a step change in the duty cycle ΔdT at time t = 0. The total duty cycle is (11.126) The step change in the duty cycle in the time domain is given by (11.127) which results in

(11.128) Hence, using (11.22), the transient component of the output voltage of the open-loop boost converter in the s-domain is (11.129) The ac component of the output voltage is given by (11.130) The inverse Laplace transform of the output voltage of the open-loop boost converter in the time domain can be found using MATLAB®. The total output voltage is (11.131) Example 11.7 For the open-loop boost converter specified in Example 11.1, draw the waveform of the output voltage vO that is a response to the step change in the duty cycle dT from 0.5 to 0.6. Calculate the output voltage for steady state after the transition and the maximum relative transient ripple. Solution: Figure 11.24 shows a response of the transient component of the output voltage vo to a step change in the control input dT from 0.5 to 0.6 for d = 0.1 for the boost converter without feedback at VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω. The output voltage vO increases from 20 V to a peak value of 25.35 V and then reaches a final steady-state value of approximately 23.755 V after 3 ms. From Example 11.2, the transient component of the output voltage is (11.132) Referring to Figure 11.24, vomax = 5.35 V and the maximum overshoot is (11.133) The total output voltage is (11.134) Hence, the maximum relative transient ripple of the output voltage is (11.135)

Figure 11.24 Response of the output voltage vO to a step change in the duty cycle dT from 0.5 to 0.6 for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω.

11.8.3 Open-Loop Response of Output Voltage to Step Change in Load Current Let us assume a step change in the load current ΔIO at time t = 0 for fixed input voltage VI and duty cycle D. The total load current is given by (11.136) resulting in the step change in the load current in the time domain (11.137) and in the s-domain

(11.138) This leads to the transient component of the output voltage in the s-domain (11.139) and in the time domain (11.140) The total output voltage is vO(t) = VO(0−) + vo(t). Example 11.8 For the open-loop boost converter given in Example 11.1, draw the waveform of the output voltage vO that is a response to the step change in the load current iO from 0.5 to 0.6 A. Find the output voltage for steady state after the transition and the maximum relative transient ripple. Solution: Figure 11.25 shows a step response of the output voltage vO to a step change in the load current iO from 0.5 to 0.6 A for the boost converter without feedback at VI = 28 V, D = 0.5, L = 156 μH, C = 68 μF, RLmin = 40 Ω, r = 0.316 Ω, and rC = 0.111 Ω. The output voltage vO decreases from 20 V to a minimum value of 19.69 V and then reaches a final steady-state value of approximately 19.9 V after 3 ms. The dc output resistance is Zo(0) = Ro(0) = RLminr/[(1 − Dnom)2RLmin + r] = 1.225 Ω. The change in the steady-state output voltage is (11.141) Hence, the output voltage after the transition is (11.142) From Figure 11.25, vomin = −0.3051 V, yielding the maximum undershoot of the output voltage (11.143) and the maximum relative transient ripple of the output voltage (11.144)

Figure 11.25 Step response of vO to a step change in the load current IO from 0.5 to 0.6 A for the boost converter without feedback for VInom = 12 V, D = 0.5, L = 156 μH, C = 68 μF, RLmin = 40 Ω, r = 0.316 Ω, and rC = 0.111 Ω.

11.9 Summary The small-signal model of the boost converter has two inputs: the small-signal duty cycle d and the small-signal input voltage vi. The small-signal duty cycle d is a control variable and the small-signal input voltage vi is a disturbance. The small-signal model of the boost converter has one output, which is the small-signal component of the output voltage vo. The open-loop control-to-output transfer function of the boost converter is a second-order low-pass function with two poles and two zeros. The two poles and one zero are located in the LHP and one zero is located in the RHP for most values of the dc duty cycle D. As D is increased from 0 to 1, the zero moves from the

RHP to the origin and enters the LHP as D approaches 1. The open-loop input-to-output transfer function of the boost converter is a second-order low-pass transfer function. The open-loop input-to-output transfer function of the boost converter has two simple or complex poles and one simple zero. Both the poles and the zero of the open-loop input-to-output transfer function of the boost converter are located in the LHP. The plots of the open-loop input impedance of the boost converter are similar to those of the series resonant circuit composed of a series combination of L/(1 − D)2 and r/(1 − D)2 in series with the C-rC-RL circuit. The plots of the open-loop output impedance of the boost converter are similar to those of the parallel resonant circuit composed of a series combination of L/(1 − D)2 and r/(1 − D)2 in parallel with the C-rC-RL circuit. The magnitude of the output impedance |Zo| increases with increasing D at low frequencies.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I and II. Pasadena, CA: TESLAco, 1981, pp. 73–89. 2. D. M. Mitchell, Switching Regulator Analysis. New York: McGraw-Hill, 1988. 3. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, ch. 11.4. Reading, MA: Addison-Wesley, 1991, pp. 274–280. 4. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed, New York: John Wiley and Sons, 2003. 5. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd Ed. Norwell, MA: Kluwer, 2001. 6. V. Vorpérian, “Simplified analysis of PWM converters using the model of the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-26, pp. 497–505, May 1990. 7. D. Czarkowski and M. K. Kazimierczuk, “Circuit models of PWM dc-dc converters,” Proceedings of the IEEE National Aerospace Conf. (NAECON’92), Dayton, OH, May 18– 22, 1992, pp. 407–413. 8. D. Czarkowski and M. K. Kazimierczuk, “Static- and dynamic-circuit models of PWM buck-derived dc-dc converters,” IEEE Proc., Pt. G, Circuits, Devices and Systems, vol. 139, pp. 669–679, December 1992.

9. D. Czarkowski and M. K. Kazimierczuk, “Energy-conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-29, pp. 1059–1063, July 1993. 10. M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” 2nd IEEE Conference on Control Applications, Vancouver, BC, Canada, September 13–16, 1993, pp. 291–296. 11. M. K. Kazimierczuk and R. Cravens, II, “Closed-loop input impedance of a voltage-modecontrolled PWM boost dc-dc converter for CCM,” IEEE 37th Midwest Symposium on Circuits and Systems, Lafayette, LA, August 3–5, 1994, pp. 1253–1256. 12. M. K. Kazimierczuk and R. Cravens, II, “Closed-loop characteristics of voltage-modecontrolled PWM boost dc-dc converter with an integral-lead controller,” Journal of Circuits, Systems, and Computers, vol. 4, no. 4, pp. 429–458, December 1994. 13. M. K. Kazimierczuk and R. Cravens, II, “Input impedance of closed-loop PWM boost dcdc converter for CCM,” IEEE International Conference on Circuits and Systems, Seattle, WA, April 30–May 3, 1995, pp. 2047–2050. 14. B. Bryant and M. K. Kazimierczuk, “Voltage-loop power-stage transfer functions with MOSFET delay for boost PWM converter operating in CCM,” IEEE Transactions on Industrial Electronics, vol. 54, pp. 347–353, February 2007.

Review Questions 1. Draw a dc model for a boost converter for CCM. 2. Draw a small-signal model for a boost converter for CCM. 3. Draw a small-signal model for deriving the control-to-output transfer function of a boost converter for CCM. 4. What is the order of the control-to-output transfer function of the boost converter? 5. Where are the poles and zeros of the control-to-output transfer function of the boost converter located in the s-plane? 6. How does the location of the poles and zeros of the control-to-output transfer function change with increasing dc duty cycle D? 7. What is a non-minimal phase system? 8. Is the control-to-output transfer function of the boost converter minimal or non-minimal phase? 9. Sketch Bode plots for the control-to-output transfer function of the boost converter? 10. Draw a small-signal model for deriving the input-to-output transfer function of a boost

converter. 11. Sketch the magnitude of the input-to-output transfer function for the boost converter. 12. Where are the poles and the zero of the input-to-output transfer function of the boost converter located in the s-plane? 13. Draw a small-signal model for deriving the input impedance of a boost converter. 14. Sketch the magnitude and the phase of the input impedance for the boost converter. 15. Draw a small-signal model for deriving the output impedance of a boost converter. 16. Sketch the magnitude and the phase of the output impedance for the boost converter.

Problems 1. The boost converter designed in Chapter 3 has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, VF = 1.4 V, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, and rC = 1 Ω. Determine MV DC and η. 2. The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Calculate zn, fzn, zp, fzp, f0, ξ, Q, p1, p2, and fd. 3. The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Tpo and Tp(∞). 4. The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Mvo. 5. The boost converter has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 μH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Zi(0). 6. The boost converter has VInom = 28 V, VO = −12 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Zo(0) and Zo(∞). 7. The boost converter has RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC = 1 Ω. Determine Zo(0) for D = 0.1, 0.5, 0.8, and 0.9. 8. The boost converter has ξlossy = 0.162, VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, r = 2.756 Ω, and rC

= 1 Ω. Determine ξ and Q at all parasitic resistances equal to zero. Calculate the ratio of the actual to approximate values of ξ. 9. A boost PWM dc–dc converter has VImin = 1 V, VImax = 8 V, VO = 20 V, RL = 40 Ω, rDS = 120 mΩ, RF = 80 mΩ, L = 156 μH, rL = 50 mΩ, C = 68 μF, rC = 50 mΩ, and fs = 100 kHz. Find values of the zero and its frequency at VImin and VImax. Draw the location of the zero zp (root locus) of the zero in the s-plane for VImin and VImax. Find the value of D at which zp = 0. 10. A boost PWM dc–dc converter has VI = 10 V, VO = 20 V, RLmin = 40 Ω, RLmax = 200 Ω, rDS = 120 mΩ, RF = 80 mΩ, L = 156 μH, rL = 50 mΩ, C = 68 μF, rC = 50 mΩ, and fs = 100 kHz. Find values of the zero and its frequency at VImin and VImax. Draw the location of the zero zp (root locus) of the zero in the s-plane for VImin and VImax. Find the value of RL at which zp = 0. 11. A boost PWM dc–dc converter has VImin = 1 V, VImax = 8 V, VO = 20 V, RL = 40 Ω, rDS = 120 mΩ, RF = 80 mΩ, L = 156 μH, rL = 50 mΩ, C = 68 μF, rC = 50 mΩ, and fs = 100 kHz. (a) Find the values of the RHP zero zp and its frequencies at VImin and VImax. (b) Find the value of D at which zp = 0. (c) Draw the location of zp in the s-plane at VImin and VImax. (d) Sketch the Bode plots for zp only for VImin and VImax.

12 Voltage-Mode Control of PWM Buck Converter 12.1 Introduction Voltage-mode control of the PWM buck converter is explored in this chapter [1–4]. The control circuit of a power switch must decide when to turn the switch on and off. The basic blocks of the voltage-mode control system are described. One technique is known as voltagemode control (or programming) or duty-cycle control because the output voltage is proportional to the duty cycle D. It is a single-loop control scheme. The transfer function of the pulse-width modulator is derived. The feedback network is represented by the two-port network hybrid h-parameters. The loading effect of the A-network by the β-network is considered. The criteria of the relative stability are discussed and the loop compensation procedure is explained. An integral-lead control circuit is analyzed and its design procedure is given. The loop gain is determined. The following closed-loop transfer functions and impedances of the buck converter are derived: the control-to-output transfer function, the inputto-output transfer function, the input impedance, and the output impedance. The responses of the output voltage to step changes in the input voltage and the duty cycle are also given. A physical power converter is unable to perform exactly according to the design in view of several practical considerations such as tolerance of circuit elements, environmental effects (temperature fluctuations, humidity, radiation, interference, etc.), and aging. One of the design objectives is to minimize the effect of parameter variations. Dc–dc power converters normally require a control circuit for the following reasons: To obtain a good dc voltage source. To regulate the output voltage against line voltage and load current (or load resistance) variations. To reduce the dc error. To reduce the sensitivity of the closed-loop voltage transfer function Tcl ≈ 1/β to the component values in the forward path A over a wide range of operating conditions, such as temperature range and frequency range. To reduce the closed-loop output impedance Zocl = Zo/(1 + T). To reduce the magnitude of the audio susceptibility Mvcl = Mv/(1 + T), especially to reduce the 100 or 120-Hz voltage ripple and other line disturbances such as transients. The relative stability is a measure of how far the system is from instability. To achieve a sufficient degree of relative stability, that is, a sufficient gain margin GM (usually, GM > 6–12 dB) and a sufficient phase margin PM (usually, PM > 45–60°).

To increase the closed-loop bandwidth and thereby the speed of the transient responses to sudden changes in the input voltage and load current (or resistance).

12.2 Properties of Negative Feedback An open-loop circuit has the disadvantage of being subject to aging of components, drift of circuit parameters with temperature, time, etc. A block diagram of a single-loop negative feedback control circuit is shown in Figure 12.1. It consists of an A-network and a β-network. The A-network delivers an output signal xo = Axe to an external load. The feedback network β produces a feedback signal xf = βxo that is subtracted from the reference signal xr to form an error signal xe = xr − xf . From Figure 12.1, (12.1) Hence, the closed-loop gain is given by (12.2) where A = xo/xe is the open-loop gain, β = xf /xo is the transfer function of the feedback network, T = xf /xe = βA is the loop gain or the loop transmission, D = 1 + βA is the amount of feedback, and T/(1 + T) = 1/(1 + 1/T) is the correction factor. Let us assume initially that A and β are frequency-independent real quantities. Pure negative feedback takes place for βA > 0 and pure positive feedback occurs for βA < 0. It follows from (12.2) that |Af | < |A| for negative feedback.

Figure 12.1 Block diagram of a single-loop negative feedback configuration. From (12.2), (12.3)

Figure 12.2 shows a plot of Af as a function of A at a fixed value of β. It can be seen that Af approaches 1/β as A increases to ∞. Therefore, the gain of negative feedback systems Af is practically independent of A and is almost entirely determined by the feedback network if the loop gain βA 1.

Figure 12.2 Closed-loop gain Af as a function of the open-loop gain A and the transfer function of the feedback network β. (a) Af versus A at a fixed β. (b) Af versus β at a fixed A. Assuming that β is constant and taking the derivative dAf /dA of (12.2), one obtains (12.4) Dividing (12.4) by (12.2) gives the relationship between the relative change in the closed-loop gain dAf /Af and the relative change in the open-loop gain dA/A

(12.5) Thus, the fractional change in Af is (1 + βA) times lower than the fractional change in A. If βA 1, the negative feedback makes the closed-loop gain Af almost insensitive to variations in the A-network parameters. This is one of the key advantages of negative feedback. The openloop gain A is a function of many parameters, some of which have large tolerances and uncertainties. The A-network contains active semiconductor devices whose parameters have a very wide range of tolerances (up to 100%) and depend on temperature, power supply voltages, etc. Passive elements have parasitic components that depend on frequency and temperature, and the range of their values is very wide, for example, for the ESR of filter capacitors. Figure 12.2(b) shows a plot of Af versus β at a fixed value of A. Taking the derivative dAf /dβ of (12.2) results in (12.6) Dividing (12.6) by (12.2) yields the relationship between the relative changes in the closedloop gain dAf /Af and the feedback network transfer function dβ/β (12.7) Thus, the fractional change in Af is almost equal in magnitude and opposite in sign to the fractional change in β. To achieve predictable and accurate closed-loop gain, the feedback network should be built of precision passive components, such as resistors with low tolerances, usually less then or equal to 1%. The fractional change on Af in terms of fractional changes in A and β is (12.8) The feedback signal is given by (12.9) and the error signal is (12.10) If |βA| 1, xe xr and xf xr.

The magnitude of the open-loop gain |A| usually decreases with increasing frequency. Therefore, the magnitude of the loop gain |βA| also decreases with frequency. Consequently, the desired condition |βA| 1 is no longer satisfied at high frequencies. When the loop gain |β A| becomes low, the advantages of negative feedback are significantly reduced. Example 12.1 A single-loop negative-feedback system has nominal values of A = 990 and β = 0.1. The reference signal is xr = 1 V. It is known that dA/A = 10% and dβ/β = 10%. Calculate the nominal values of T, Af , xf , and xe. Find also dAf /Af at dβ = 0, and dAf /Af at dA = 0. Solution: For the nominal values of A and β, one obtains the loop gain (12.11) the amount of feedback (12.12) and the closed-loop gain (12.13) The approximate value of the closed-loop gain is (12.14) The fractional change in the closed-loop gain due to the fractional change in the open-loop gain is (12.15) and the fractional change in the closed-loop gain due to the fractional change in the transfer function of the feedback network is (12.16) The total fractional change in the closed-loop gain is (12.17) The output signal is (12.18) and the error signal is

(12.19)

12.3 Stability The loop gain in the s-domain is (12.20) The closed-loop gain in the s-domain is given by (12.21) For s = jω, the closed-loop gain is given by (12.22) The condition for oscillation is (12.23) yielding (12.24) In this case, the circuit is marginally stable and produces sustained steady-state oscillations with a fixed amplitude of the output voltage. Equation (12.23) can be rewritten as (12.25) Hence, the amplitude condition for oscillation is (12.26) and the phase condition for oscillation is (12.27) where f− 180 is the phase crossover frequency at which ϕT = −180° and f0 dB is the gain crossover frequency at which |T| = 1 = 0 dB. If these two conditions are satisfied simultaneously at the same frequency fo = f0 dB = f− 180, termed the oscillation frequency fo, the circuit oscillates at a fixed amplitude of the output signal.

In order to achieve a stable circuit, either both conditions or one of the conditions for oscillations should not be satisfied. In addition, a sufficient degree of stability should be achieved. The relative stability is determined by the gain margin GM and the phase margin PM. The gain margin is defined as (12.28) The phase margin is defined as (12.29) For example, if |T(f− 180)| = 0.5 and ϕT(f0 dB) = −120°, then GM = 1/0.5 = 2 = 6 dB and PM = 180° + ( − 120°) = 60°. In general, a circuit is unstable when (12.30) and (12.31) In this case, the circuit produces initially growing oscillations. The stability margin is defined as the shortest distance from the Nyquist plot Re{T(f)} vs. Im{T(f)} to the point (−1,0) (12.32) The point (−1,0) is not encircled by the Nyquist plot.

12.4 Single-Loop Control of PWM Buck Converter A buck PWM converter with negative feedback is shown in Figure 12.3. This control scheme is called voltage-mode control because the duty cycle is proportional to the control voltage. It is a single-loop control circuit, in which the converter output voltage is sensed by a feedback network and used to develop an error voltage at the input of a control circuit. The output voltage of a control circuit controls the duty cycle. It is a series-shunt topology (also called a voltage-series topology) of negative feedback because the two-port networks are connected in series at the input and in parallel at the output. This topology reduces the output impedance, which is a desirable property of a good voltage source (i.e., a power supply). The magnitude of the output impedance is reduced because the A-network and the feedback network β are connected in parallel at the converter output. The series connection of the two-port networks at the input compares the reference voltage VR and the feedback voltage vF and generates the error voltage vE = VR − vF. Figures 12.4 and 12.5 show the buck converter with

rearrangements of the feedback network, using the h-parameters.

Figure 12.3 Circuit of closed-loop voltage-mode-controlled buck PWM converter.

Figure 12.4 Closed-loop voltage-mode-controlled buck PWM converter with a feedback network β represented by the h-parameters, where h21 = 0.

Figure 12.5 Closed-loop voltage-mode-controlled buck PWM converter with resistances h11 and 1/h22 included in the A-network. The waveforms in the control circuit are depicted in Figure 12.6. The output voltage vO = VO + vo is reduced by a feedback network β comprised of a resistive voltage divider RA and RB to generate a feedback voltage vF = VF + vf . The feedback voltage is compared to a reference voltage VR to develop an error voltage vE = VE + ve = VR − vF = VR − VF − vf , where VE = VR − VF is a dc error voltage and ve = −vf is an ac error voltage. The error voltage is applied to the input of a controller, which is a linear error amplifier in the form of an inverting closed-loop op amp. The controller produces a control voltage vC = VC + vc. The next stage is a pulsewidth modulator, which is an inverting comparator. The control voltage vC is applied to the non-inverting input of the comparator and a sawtooth voltage vt of magnitude VTm and frequency fs is applied to the inverting input of the comparator. In most applications, the frequency of vt is constant, but it may also vary. The converter switching frequency fs is determined by the sawtooth generator frequency. In the comparator, v+ = vC and v− = vt. When vC < vt, (i.e., v+ < v−), the output voltage of the comparator goes low. When vC > vt, (i.e., v+ > v −), the output voltage of the comparator goes high. The output voltage v of the pulse-width AB modulator is a rectangular wave whose duty cycle dT depends on the value of the control voltage vC. The gate-to-source voltage of the power MOSFET vGS is of the same phase as the output voltage of the pulse-width modulator.

Figure 12.6 Waveforms in the closed-loop voltage-mode-control PWM buck converter with a negative feedback loop. Suppose the input voltage of the converter vI is increased as shown in Figure 12.6. Consequently, the output voltage vO increases, causing the feedback voltage vF to increase. Hence, the error voltage vE decreases and the control voltage vC also decreases. Therefore, the duty cycle dT of the comparator output voltage vAB decreases, causing the output voltage vO = dTvI to decrease. The switching frequency of the converter is equal to the frequency of the ramp voltage. Normally, the frequency of vt is constant. It is easier to reduce the electromagnetic interference (EMI) noise at a fixed frequency. Since VO ≈ (1/β)VR = (1 + RB/RA)VR, the tolerance of the resistors RA and RB in the feedback network should be low, for example, 1%.

12.5 Closed-Loop Small-Signal Model of Buck Converter

A small-signal low-frequency model of the voltage-mode-controlled PWM buck converter is depicted in Figure 12.7(a). Figure 12.7(b) shows a block diagram of a closed-loop buck converter for small-signal operation. In this figure, Tp = v′o/d represents the small-signal openloop control-to-output transfer function of the power stage of the buck converter, Mv = v′′o/vi is the open-loop input-to-output transfer function, Zo = −v′′′o/io is the open-loop output impedance which includes the load resistance RL, Tm = d/vc is the transfer function of the pulse-width modulator, Tc = vc/ve represents the voltage transfer function of the controller, β = vf /vo is the voltage transfer function of the feedback network (or the feedback-path voltage transfer function), A = v′o/ve = TcTmTp is the forward-path voltage transfer function, T = vf /ve = βA = βTcTmTp is the loop gain, vc is the output voltage of the controller, ve is the ac component of the error voltage, and vr is the ac component of the reference voltage. The PWM regulator of Figure 12.7(a) is a multivariable system with three inputs, d, vi, and io, and a single output vo. The block diagram of Figure 12.7(b) can be simplified to the form shown in Figure 12.7(c). Applying superposition, one obtains the ac component of the output voltage (12.33)

Negative feedback reduces the magnitudes of the closed-loop audio susceptibility |Mvcl| and the closed-loop output impedance |Zocl| by a factor of (1 + |T|). However, |T| decreases with frequency and (1 + |T|) ≈ 1 at high frequencies, where negative feedback is no longer effective in improving the closed-loop converter performance.

Figure 12.7 Closed-loop small-signal low-frequency representations of the buck PWM converter. (a) Small-signal model. (b) Block diagram. (c) Simplified block diagram.

12.6 Pulse-Width Modulator A circuit of a pulse-width modulator is shown in Figure 12.8(a). It is an inverting comparator based on an open-loop op amp. The control voltage is applied to the non-inverting input, and the ramp voltage vt is applied to the inverting input. Waveforms of the control voltage vC and the ramp voltage vt in the pulse-width modulator are shown in Figure 12.9. As the control voltage is increased from VC to VC + vc, the duty cycle is increased from D to D + d, causing an increase in the converter output voltage. From Figure 12.9, the slope of the ramp voltage waveform vt can be expressed in terms of the dc components of the control voltage VC and the duty cycle D

(12.34) Hence, the dc control voltage-to-duty cycle transfer function of the pulse-width modulator is (12.35)

Figure 12.8 Pulse-width modulator. (a) Circuit. (b) DC block diagram. (c) AC small-signal block diagram.

Figure 12.9 Waveforms in the pulse-width modulator. (a) Waveforms of the sawtooth voltage vt and the control voltage vC. (b) Waveforms of the gate-to-source voltage vGS. Using Figure 12.9(a), the slope of the ramp voltage vt can be described in terms of the smallsignal components of the control voltage vc and the duty cycle d (12.36) Rearrangement of this equation leads to the ac control voltage-to-duty cycle transfer function of the pulse-width modulator (12.37) Note that Tm(dc) = Tm(ac) = Tm. Another method for deriving Tm(ac) is given below. It follows from Figure 12.9(a) and

trigonometric considerations that the slope of the ramp voltage vt can be expressed in terms of the large-signal control voltage vC = VC + vc and the duty cycle dT = D + d (12.38) which produces (12.39) Hence, the small-signal control voltage-to-duty cycle transfer function of the pulse-width modulator can be derived as (12.40) Let us now assume that the control voltage vC contains a sinusoidal ac component as shown in Figure 12.10 (12.41) The total control voltage is then given by (12.42) Therefore, the total duty cycle is (12.43) Since VE VR, VF ≈ VR. It will be shown shortly that VC ≈ VR. Hence, one obtains the dc component of the duty cycle (12.44) resulting in the dc transfer function of the pulse-width modulator (12.45)

Figure 12.10 Waveforms in the pulse-width modulator for a sinusoidal ac component of the control voltage. The ac component of the duty cycle is (12.46) where the amplitude of the ac component of the duty cycle is (12.47) The ac control voltage-to-duty cycle transfer function of the pulse-width modulator is (12.48) Notice that the dc and ac transfer functions of the pulse-width modulator are equal

(12.49) The ac transfer function of the pulse-width modulator may exhibit a pure delay ϕTm = −ωto and is expressed by (12.50) In subsequent analyses, the pure delay of the pulse-width modulator ϕTm = −ωto will be neglected or combined with the delay of the power MOSFET. The op amp used as a comparator in the pulse-width modulator is required to have high enough slew rate SR. Assuming that the rise time tr and the fall time tf of the gate-to-source voltage are less than 5% of the period Ts = 1/fs, the maximum rise and fall times are (12.51) and the minimum slew rate of the op amp is (12.52) Example 12.2 A PWM buck converter has a dc reference voltage VR = 5 V and the nominal value of the dc component of the duty cycle Dnom = 0.555. Find the peak value of the ramp voltage at the input of the pulse-width modulator and the transfer function of the pulse-width modulator. Also calculate the minimum slew rate of the op amp used in the pulse-width modulator. Solution: The dc component of the control voltage VC is approximately equal to the reference voltage VR. From (12.35), (12.53) Pick VTm = 10 V. Hence, the voltage transfer function of the pulse-width modulator is (12.54) The period of the switching frequency is (12.55) and the maximum rise time is

(12.56) Assuming that ΔVGS = 10 V, the minimum slew rate is (12.57)

12.7 Feedback Network The feedback network is not an ideal voltage-controlled voltage source. It is a passive resistive voltage divider and therefore will load the A-network at the input and the output. Consequently, the gain, the input impedance, and the output impedance of the A-network are altered by the feedback network. In order to take into account the loading effect of the Anetwork by the feedback network, the feedback network can be represented by its hparameters. This hybrid representation is compatible with the series-shunt topology of negative feedback because it contains a series network at the input and a parallel network at the output. Figure 12.11(a) shows a block diagram of a feedback network represented by a general twoport network excited by a current source I1 at the input and by a voltage source V2 at the output. Let us assume that the two-port network is time-invariant, linear, and does not contain independent sources. The two dependent variables (i.e., responses), the input voltage V1 and the output current I2, can be expressed in terms of the independent variables (i.e., inputs) I1 and V2 and the hybrid h-parameters (12.58) (12.59) Figure 12.11(b) shows an equivalent circuit, which represents these equations.

Figure 12.11 Block diagram and equivalent circuit of a linear two-port network represented by the h-parameters. (a) Block diagram of a general two-port network. (b) A two-port representation using the hybrid h-parameters. The feedback network used in the control circuit of Figure 12.7(a) is depicted in Figure 12.12(a). Its h-parameters are (12.60)

(12.61)

(12.62)

(12.63) The h-parameter equivalent circuit of the feedback network is shown in Figure 12.12(b). Note that h11 is the short-circuit input impedance, h12 is the open-circuit reverse voltage gain, h21 is the short-circuit forward current gain, and h22 is the open-circuit output admittance. Since the feedback network is passive, its forward transmission h21 is usually small and therefore can be neglected, as shown in Figure 12.12(c).

Figure 12.12 Feedback network and its h-parameter equivalent circuit. (a) Feedback network. (b) Equivalent circuit of the feedback network represented by its h-parameters. (c) Equivalent circuit of the feedback network represented by h-parameters with h21 = 0. In Figure 12.4, the feedback network is replaced by its h-parameter representation of Figure 12.12(c). The resistances h11 and 1/h22 can be moved from the feedback network to the Anetwork, as shown in Figure 12.5. In this case, the feedback network is an ideal voltage-

controlled voltage source. Observe that the error voltage vE is produced by two ideal voltage sources, VR and vF = βvO. Example 12.3 A closed-loop PWM buck converter has a dc reference voltage VR = 5 V and a dc output voltage VO = 14 V. Design a feedback network. The load resistance of the converter RL ranges from 10 to 100 Ω. The required input resistance of the control circuit is R1 = 6.8 kΩ. How significant is the loading effect of the A-network by the feedback network? Solution: Assuming that T(0) = βA(0) 1, the dc error voltage VE is much less than the reference voltage VR and the dc feedback voltage VF. Therefore, the dc component of the feedback voltage VF is approximately equal to the reference voltage VR. The voltage transfer function of the feedback network is (12.64) Let RB = 5.1 kΩ/0.25 W/1%. Hence, (12.65) Pick RA = 9.1 kΩ/0.25 W/1%. Thus, (12.66) and (12.67) Since 1/h22 = 14.2 kΩ RLmax = 100 Ω, the equivalent load resistance of the A-network remains approximately equal to RL and the loading effect of the A-network by the feedback network at the output is negligible.

12.8 Transfer Function of Buck Converter with Modulator and Feedback Network From Figure 12.7(a), the control-to-output transfer function of the PWM buck converter and the pulse-width modulator (usually called a plant) is given by (12.68)

where (12.69) It can be seen from (12.69) that if the ratio VI/VTm is constant, the control-to-output transfer function of the converter and modulator is independent of the input voltage VI. A constant value of this ratio can be accomplished by means of a feed-forward loop. The feed-forward loop may be obtained in such a way that the supply voltage terminal of the sawtooth generator is connected to the converter dc input voltage VI using a resistive voltage divider. In this arrangement, VTm is directly proportional to VI, resulting in a constant ratio VI/VTm. Example 12.4 A PWM buck converter, studied in Chapter 11, has VR = 5 V, VTm = 10 V, VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, and rC = 0.391 Ω. Draw Bode plots of the product of the transfer function of the pulse-width modulator and the control-to-output transfer function Tmp. Calculate Tmpo. Solution: From (12.54), the transfer function of the pulse-width modulator is Tm = 0.1 = −20 dB. Bode plots of Tmp are depicted in Figures 12.13 and 12.14. The magnitude |Tmp| crosses 0 dB at a frequency of 2.457 kHz. The minimum value of the phase ϕTmp occurs at f = 3.18 kHz and is equal to − 145.95°. From (12.69), (12.70)

Figure 12.13 Bode plot of the magnitude of Tmp.

Figure 12.14 Bode plot of the phase of Tmp. The transfer function of the buck converter, the pulse-width modulator, and the feedback network is (12.71)

where (12.72) Setting s = jω,

(12.73)

and (12.74)

or (12.75)

Example 12.5 A PWM buck converter of Example 12.4 has VInom = 28 V, Dnom = 0.555, L = 301 μH, C = 51.2 μF, RLmin = 10 Ω, r = 0.16 Ω, rC = 0.391 Ω, VR = 5 V, and VTm = 10 V, β = 0.3571, and VO = 14 V. Draw Bode plots of the transfer function of the PWM back converter along with the pulse-width modulator and the feedback network Tk . Find the frequency at which |Tk | crosses zero and the frequency at which the phase has a minimum value. Calculate Tko. Solution: Figures 12.15 and 12.16 show Bode plots of the magnitude |Tk | as a function of frequency. The magnitude |Tk | crosses 0 dB at f = 1.7 kHz. The minimum value of the phase occurs at fmin = 3.18 kHz. At f = 0, (12.76)

Figure 12.15 Bode plot of the magnitude of Tk .

Figure 12.16 Bode plot of the phase of Tk .

12.9 Control Circuits 12.9.1 Error Amplifier A general circuit of an error amplifier and its control block diagram are shown in Figure 12.17(a) and (b), respectively. The error amplifier is also called a controller or a compensator. The feedback voltage consists of a dc component and an ac component (12.77) Hence, the error voltage is given by (12.78) where the dc component of the error voltage is (12.79)

and the ac component of the error voltage is (12.80)

Figure 12.17 General circuit and control block diagram of an error amplifier. (a) General circuit. (b) Control block diagram. The current through the impedances Zi and Zf is (12.81) Rearrangement of this equation gives the total control voltage (12.82) where the dc component of the control voltage is

(12.83) and the ac component of the control voltage is (12.84) Substitution of (12.80) into (12.84) yields (12.85) which gives the ac voltage transfer function of the controller (12.86) The ac voltage gain of the op amp error amplifier is (12.87)

12.9.2 Proportional Controller Figure 12.18 shows a circuit of a proportional controller and its ac equivalent circuit. Assuming an ideal op-amp, The voltage transfer function of an ideal op-amp amplifier is given by (12.88) The ac voltage transfer function of the ideal proportional controller is (12.89) Figure 12.19 shows Bode plots of the proportional controller. The control voltage vc is proportional to the error voltage ve. The proportional control increases the magnitude of the loop gain T and therefore reduces the error voltage. For most systems, there is an upper limit of the controller gain |Tc| in order to achieve a well-damped, stable response.

Figure 12.18 Proportional controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component.

Figure 12.19 Bode plots of the ac voltage transfer function Tc of proportional controller. (a) Magnitude |Tc|. (b) Phase . In reality, a compensated op-amp is a first-order system. Therefore, the voltage transfer function of a practical op-amp proportional control circuit is (12.90) where f1 = |Avo|fH is the unity-gain frequency of an op-amp and fH is the upper 3-dB corner frequency. The controller magnitude is approximately constant for f < fH and decreases with f for f > fH at the rate of 10 dB/dec. The controller phase ϕTc ≈ 0° for f ≤ fH/10, decreases with f at the rate of − 45°/dec for fH/10 < f < 10fH, and ϕc ≈ −90° for f ≥ 10fH.

12.9.3 Integral Controller

Figure 12.20 show a circuit of an integral controller and its ac equivalent circuit. The voltage transfer function is (12.91)

where (12.92) The ac voltage transfer function of the integral controller is (12.93) where KI = 1/(R1 + h11)C1. Figure 12.21 shows Bode plots of the integral controller. The integral control provides a finite value of the control voltage vc with no error voltage ve. It is no longer necessary for the error signal ve to be finite to produce a finite control voltage vc. Ideally, an integral controller reduces or eliminates the steady-state error. This benefit typically comes at the cost of reduced stability because the integral controller introduces a phase shift equal to − 90° at all frequencies. The dc voltage gain of an op-amp is limited by the open-loop dc gain AOL. In addition, an op-amp may saturate when the gain is very large. Therefore, a band resistor Rb is usually connected in parallel with the capacitor C1. This reduces the low-frequency controller voltage gain to Tco = Rb/(Rb + R1 + h11).

Figure 12.20 Integral controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component.

Figure 12.21 Bode plots of the ac voltage transfer function Tc of integral controller. (a) Magnitude |Tc|. (b) Phase . In reality, an op-amp is a first-order system. Therefore, the voltage transfer function of the integral control circuit is (12.94)

Therefore, KI/2π should be much lower than the unity gain frequency of op-amp f1. The highfrequency phase of the real integral control circuit is − 180°.

12.9.4 Proportional-Integral Controller Figure 12.22 shows a circuit of a proportional-integral (PI) controller and its ac equivalent circuit. The ac voltage transfer function of the amplifier shown in Figure 12.22(b) is given by

(12.95)

where (12.96) and (12.97) The ac voltage transfer function of the PI controller is (12.98)

where (12.99) and (12.100) Figure 12.23 shows Bode plots of the ac voltage transfer function Tc of the PI controller. Figures 12.24 and 12.25 show Bode plots of Tc for KP = 10 and fz = 10 Hz. The PI controller is a low-pass filter and reduces switching noise. However, it also reduces the bandwidth, increases the rise time, and increases the setting time.

Figure 12.22 Proportional-integral (PI) controller. (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component.

Figure 12.23 Bode plots of the ac voltage transfer function Tc of proportional-integral (PI) controller. (a) Magnitude |Tc|. (b) Phase .

Figure 12.24 Bode plot of the magnitude |Tc| of the ac voltage transfer function Tc of proportional-integral (PI) controller at KP = 10 and fz = 1 kHz.

Figure 12.25 Bode plot of the phase ϕTc of the ac voltage transfer function Tc of proportionalintegral (PI) controller at KP = 10 and fz = 1 kHz. A design procedure of the PI controller is as follows. At the gain-crossover frequency fc, the magnitude of the loop gain is (12.101) where Tk is the uncompensated loop gain. Hence, the gain of the proportional part of the controller is (12.102) If fz ≤ fc/10, the phase lag of the PI controller has a negligible effect on the phase of the compensated loop gain near the gain-crossover frequency fc. The corner frequency fz should not be too low because the bandwidth BW will be narrow, increasing the rise time and the settling time. The frequency of the controller zero fz should be at least one decade lower than

the gain-crossover frequency fc. Thus, the coefficient of the integral part of the controller is (12.103) producing (12.104) Assuming a standard value of capacitance C1, we obtain (12.105) and (12.106)

12.9.5 Integral-Single-Lead Controller To avoid excessive oscillations in closed-loop converters when load and input voltage change, integral, proportional, or PI controllers are used. Derivative controllers are not used to avoid the differentiation of the switching actions. When integral controllers are used, a low dc error is achieved by sacrificing the speed of the transient response because of a narrow bandwidth. On the other hand, when proportional controllers are used, a fast transient response is achieved by sacrificing the dc steady-state error because the dc gain is low. When proportional-integral (PI) controllers are used with the proportional gain set to a low level, the dc error will be reduced, the oscillations can be avoided, and a comparatively slower system will result. An integral-single lead (or type II) controller, also called the type II controller [4], is shown in Figure 12.26(a). The circuit has a pole at the origin and a single pole–zero pair. The pole at the origin forms the integral part of the controller and the pole–zero pair forms the lead part of the controller. Since the magnitude of the controller transfer function has two slopes, the circuit is called the type II controller. An integral circuit is called the type I controller. The controller is an inverting op amp with a dc reference voltage source VR. Setting the dc reference voltage VR to zero, one obtains an equivalent circuit for the ac component, as depicted in Figure 12.26(b). The controller is used to obtain a low steady-state (dc) error and fast transient responses. The primary reason for using an integral controller is to obtain very high values of the gain at low frequencies and therefore reduce the dc error, but this benefit typically comes at the expense of reduced stability. This is because the integral controller introduces a phase lag of − 90° at all frequencies. The phase lag can partially be compensated (reduced) by means of a lead controller. The task for the lead controller is to reduce the phase lag and therefore achieve a high crossover frequency fc, while maintaining a specified phase margin PM. The crossover frequency fc is defined as the frequency at which the magnitude of the loop gain |T| crosses 1 or

0 dB. A high crossover frequency fc normally results in a wide bandwidth of the closed-loop system, yielding a fast response. The crossover frequency is usually equal to fs/5. The capacitor C2 and the resistance R1 + h11 form the integral part of the controller, which ideally introduces a pole at the origin. The capacitor C1 and the resistor R2 introduce a zero. The resistor R2 and the series combination of C1 and C2 introduce a pole. The capacitance C1 is usually much higher than the capacitance C2, and therefore the frequency of the pole fpc is much higher than the frequency of the zero fzc.

Figure 12.26 Integral-single-lead controller (type II controller). (a) Circuit for both the dc and ac components. (b) Equivalent circuit for the ac component. Let us assume that the operational amplifier is ideal, that is, its open-loop dc gain and bandwidth are infinite. The voltage transfer function of the amplifier shown in Figure 12.26(a) is given by

(12.107)

Since ve = vr − vf = −vf at vr = 0, the voltage transfer function of the integral-lead controller is (12.108)

where (12.109) (12.110) (12.111) and (12.112)

It can be seen from (12.108) that the integral-lead controller introduces a pole at the origin in addition to a pole–zero pair. The pole at the origin provides a very high gain at low frequencies like an integral controller and the zero–pole pair provides a constant gain and a reduced phase shift between the zero frequency fzc and the pole frequency fpc like a lead controller. Therefore, the controller provides a very high gain at low frequencies as an integral controller and a reduced phase lag between the zero and pole frequencies. Substitution of s = jω into (12.108) yields the frequency response of the integral-lead controller (12.113)

where

(12.114)

and (12.115)

The integral part of |Tc| occurs for f fzc, which can be approximated by (12.116) This means that |Tc| for an integral-lead controller is K2 times lower than that for a standard integral controller at f < fzc. Figure 12.27 shows the idealized Bode plots for the voltage transfer function of the integral-lead controller. The magnitude |Tc| decreases with frequency at a rate of − 20 dB/dec at low frequencies like for an integral controller, it is constant and equal to |Tcm| = R2/(h11 + R1) at mid-frequencies like for a proportional controller, and decreases with frequency again at a rate of − 20 dB/dec at high frequency like for an integral controller. This last part of |Tc| is useful in switching power supply applications because it reduces the magnitudes of the switching frequency and its harmonics. The phase shift starts from − 90° at low frequencies like for an integral controller, reaches its maximum value at frequency fm like for a lead controller, and decreases back to − 90° at high frequencies like for an integral controller.

Figure 12.27 Idealized Bode plots for the integral-lead controller (type II controller). Setting the derivative of the term in the parenthesis of (12.115) to zero and using (12.112), one obtains the frequency at which the phase shift ϕTc reaches a maximum value (12.117) Thus, the maximum value of the phase ϕTc(max) = ϕTc(fm) occurs at the geometrical mean value of the zero and pole frequencies. Substitution of (12.117) into (12.115) gives (12.118)

Hence, the maximum amount of the phase shift reduction, also called a phase boost, is (12.119) from which (12.120) Hence, (12.121) Figure 12.28 illustrates the relationship between ϕm and K. It can be seen that the phase boost ϕm increases from 0 to 90° as K is increased from 0 to ∞. The required amount of phase boost ϕm can be achieved by adjusting the spread of the zero and pole frequencies K2 = fpc/fzc.

Figure 12.28 Plot of phase ϕm versus K for the integral-lead controller (type II controller). Substitution (12.117) into (12.114) yields the magnitude of the controller voltage transfer function at the frequency fm (12.122) Substituting (12.109) into (12.122) and using (12.111) and (12.117) produces (12.123) The crossover frequency fc is the frequency at which the loop-gain magnitude |T| is equal to unity (12.124) It indicates the frequency range, in which negative feedback is effective in attenuating audio

susceptibility and output impedance. Relative stability of closed-loop linear systems is measured by two criteria: the gain margin GM and the phase margin PM. The gain margin GM is defined as the reciprocal of the loopgain magnitude at the frequency f− 180 at which the loop-gain phase angle reaches − 180° (12.125) It indicates how many times the loop-gain magnitude can be increased before the system becomes unstable. Typical gain margins range from 6 to 12 dB. The phase margin PM is defined as the amount of the loop-gain phase lag at the crossover frequency fc that is required to bring the system to the verge of instability (12.126) Typical phase margins range from 45° to 75°. A lower phase margin gives faster transient response and shorter settling time, but more peaking in the closed-loop transfer function and higher ringing and overshoot in transient responses. The integral-lead controller is usually designed in such a way that the gain crossover frequency fc is equal to the frequency fm. The magnitude of the loop gain at the crossover frequency fc is (12.127) Hence, using (12.123), one obtains the required value of the controller transfer function magnitude at the crossover frequency fc (12.128) Using (12.119), the phase of the loop gain at the crossover frequency fc is given by (12.129) Hence, the phase margin can be expressed as (12.130) which leads to the required phase boost (12.131) Example 12.6 Design an integral-lead controller for the buck converter given in Example 12.5 with |Tko| = 0.998, h11 = 3.2683 kΩ, ξ = 0.2298, f0 = 1.2677 kHz, and fz = 7.95 kHz. The required phase margin is PM = 45°. Draw Bode plots of the controller transfer function Tc.

Solution: Let us assume that fc = fm = 8 kHz. Substitution of f0 = 1.2677 kHz, fz = 7.95 kHz, and ξ = 0.2298 into (12.75) yields (12.132)

Since the required phase margin is PM = 45°, (12.133) Hence, (12.134) From (12.73) and (12.76), (12.135)

The magnitude of the voltage transfer function of the controller at the crossover frequency fc is (12.136) Using (12.122) and (12.117), (12.137) (12.138) and (12.139) Bode plots of Tc of the designed controller are shown in Figure 12.29. Assuming R1 = 1 k/0.25 W/1%Ω and using (12.128),

(12.140) Pick C2 = 6.8 pF/12 V. Using (12.112), (12.141) Pick C1 = 4.7 nF/24 V. From (12.117), (12.142) Pick R2 = 110 kΩ/0.25 W/1%. Bode plots of Tc of the designed controller are shown in Figures 12.29 and 12.30. At low frequencies, the controller behaves like an integrator. As the frequency f is increased from zero, the magnitude Tc decreases with a slope of − 20 dB/decade, then remains almost constant between fzc and fpc, and finally decreases again with a slope of − 20 dB/decade. A high gain Tc at f = 0 enables the converter to achieve a low dc error. As the frequency is increased, the phase shift ϕTc is − 90° for f < fzc/10, reaches its maximum value at a frequency fm, and is − 90° for f > 10fpc. The controller behaves like a lead controller for frequencies ranging from fzc to fpc.

Figure 12.29 Bode plot of the magnitude of Tc for fzc = 310.82 kHz, fzp = 205.9 kHz, and B = 35.57 × 106 rad/s.

Figure 12.30 Bode plot of the phase of Tc for fzc = 310.82 kHz, fzp = 205.9 kHz, and B = 35.57 × 106 rad/s. In reality, the pure integral control concept cannot be implemented because of a finite dc openloop voltage gain of op-amps, voltage and current offsets of op-amps, and noise level. The maximum achievable magnitude of the controller dc gain without a bound resistor is (12.143) where AOL is the dc open-loop gain of op-amps. For example, AOL = 200, 000 for a 741 opamp. Furthermore, the dc voltage gain of the controller should be made lower than AOL because of voltage and current offsets of an op-amp and noise level. If the dc gain is not limited, the dc offset voltage would be integrated and eventually saturate the operation amplifier. The dc gain of the op-amp can be reduced by connecting a resistor Rb (called a bound resistor) in parallel with the capacitor C2. The dc gain of the controller in this case is (12.144)

Usually, Tco is limited to the range from 1000 to 3000. For example, to obtain Tco = 1000, Rb = Tco(R1 + h11) = 1000(1 + 3.2683) = 4.2368 MΩ. Pick Rb = 4.3 MΩ/0.25 W/1%.

12.9.6 Loop Gain Using (12.71) and (12.108), one obtains the loop gain (12.145)

where (12.146) Note that if R1 = 0, then βB = 1/(C2RA). Example 12.7 Draw Bode plots of the loop gain T for the buck converter of Example 12.5 with the controller of Example 12.6. What is the gain crossover frequency fc and the phase margin PM? Find the dc loop gain To = T(0) if Tc(0) = AOL = 200, 000. Solution: Plots of T are shown in Figures 12.31 and 12.32. The gain crossover frequency fc is 8 kHz, and the phase margin is approximately 45°. Hence, fs/fc = 100/8 = 12.5. The dc loop gain is (12.147)

Figure 12.31 Bode plot of the magnitude of loop gain T.

Figure 12.32 Bode plot of the phase of loop gain T.

12.9.7 Closed-Loop Control-to-Output Voltage Transfer Function The closed-loop control-to-output transfer function is given by (12.148)

Example 12.8 Draw Bode plots of the closed-loop control-to-output transfer function Tcl for the converter of Example 12.7. What is the 3-dB bandwidth of the closed-loop converter? Find the dc closed-loop voltage control-to-output voltage transfer function. Solution: Figures 12.33 and 12.34 show Bode plots of Tcl. The 3-dB bandwidth of the closedloop converter BW is approximately 10 kHz. The dc closed-loop voltage control-to-output transfer function is

(12.149)

Figure 12.33 Bode plot of the magnitude of closed-loop transfer function Tcl.

Figure 12.34 Bode plot of the phase of closed-loop transfer function Tcl.

12.9.8 Closed-Loop Input-to-Output Transfer Function The closed-loop input-to-output voltage transfer function is (12.150)

Example 12.9 Draw Bode plots of the closed-loop input-to-output transfer function Mvcl for the converter of Example 12.8. Find the dc closed-loop input-to-output transfer function if Mvo = Mv(0) = 0.5463 and To = 199, 600. Find a change in the output voltage if the dc change in the input voltage is ΔVI = 1 V. Solution: Figures 12.35 and 12.36 show Bode plots of Mvcl. The dc closed-loop input-tooutput transfer function is

(12.151) The change in the dc output voltage is (12.152)

Figure 12.35 Bode plot of the magnitude of the closed-loop input-to-output transfer function Mvcl.

Figure 12.36 Bode plot of the phase of the closed-loop input-to-output transfer function Mvcl.

12.9.9 Closed-Loop Input Impedance Referring to the block diagram shown in Figure 12.7(b) and setting vr = 0, (12.153) and (12.154) from which (12.155) From the small-signal analysis,

(12.156) and therefore (12.155) becomes (12.157) From the dc model of the buck converter of Figure 10.24, (12.158) Referring to Figure 12.7(a) and using the relationship Zi = (Z1 + Z2)/D2, the current through the inductor is (12.159) Using (12.157), (12.158), and (12.159), one arrives at the closed-loop input admittance (12.160)

Hence, the closed-loop input impedance is (12.161)

For s = 0, |T| 1, yielding 1/(1 + T) ≈ 0 and T/(1 + T) ≈ 1. Hence, the closed-loop input resistance is negative at dc and low frequencies (12.162) For f fc, |T| 1 and therefore the closed-loop input impedance at high frequencies can be approximated by (12.163) Example 12.10 Calculate the closed-loop input impedance Zicl at f = 0, RLmin = 10 Ω, r = 0.16 Ω, and Dnom = 0.555. Draw Bode plots of the closed-loop input impedance Zicl for the converter of Example 12.8. Solution: The closed-loop input impedance is

(12.164) Figures 12.37 and 12.38 depict plots of Zicl. The phase ϕZicl is − 180° at low frequencies. Thus, the input resistance is negative in this frequency range. This may cause instability leading to oscillations.

Figure 12.37 Magnitude of the closed-loop input impedance Zicl.

Figure 12.38 Phase of the closed-loop input impedance Zicl.

12.9.10 Closed-Loop Output Impedance The closed-loop output impedance is (12.165) where vt is a test voltage applied at the output of the converter and it is a current developed by the voltage vt. The closed-loop output impedance excluding the load resistance RL is (12.166) Since Zocl

RL, Z′ocl ≈ Zocl.

Example 12.11 Draw Bode plots of the closed-loop output impedance Zocl for the converter of

Example 12.8. Find the dc output resistance if Ro = 0.157 Ω and To = 199, 600. Solution: Plots of Zocl are displayed in Figures 12.39 and 12.40. It can be seen that negative feedback considerably reduces the output impedance magnitude of the converter at low frequencies, where |T| 1. For example, the closed-loop output impedance | Zocl| = 1.9 mΩ at frequency f = 100 Hz. The maximum value of the magnitude of the closed-loop output impedance |Zocl| occurs at frequency f = 7.2 kHz and is equal to 0.74 Ω. Note that the output impedance of an ideal voltage-source power supply should be zero at all frequencies. The dc output resistance is (12.167)

Figure 12.39 Magnitude of Zocl.

Figure 12.40 Phase of Zocl.

12.10 Closed-Loop Step Responses 12.10.1 Response to Step Change in Input Voltage If there is a step change in the input voltage ΔVI at time t = 0 and the steady-state input voltage before the step change is VI(0−), the total input voltage is given by (12.168) resulting in a step change in the input voltage (12.169) and

(12.170) The transient component of the output voltage is (12.171) Taking the inverse Laplace transform, one obtains the transient component of the output voltage (12.172) and the total output voltage (12.173) Example 12.12 Draw the total output voltage vO(t) of the closed-loop buck converter of Example 12.8 as a response to the step change in the input voltage from 28 to 29 V. Find the maximum transient ripple of the total output voltage vO. Solution: Figure 12.41 shows a step response of the output voltage vO to a step change in the input voltage vI from 28 to 29 V for the buck converter with negative feedback. The output voltage increases from 14 to 14.02451 V and then returns to VO = 14 V after 3 ms. The maximum relative transient ripple of the output voltage is (12.174)

Figure 12.41 Step response of vO to a step change in vI from 28 to 29 V for the buck converter with negative feedback.

12.10.2 Response to Step Change in Reference Voltage Let us now consider a step change in the reference voltage ΔVR starting at VR(0−) at time t = 0. The total reference voltage can be described by (12.175) from which (12.176) and (12.177) The transient component of the output voltage is given by

(12.178) Taking the inverse Laplace transform, one obtains the transient component of the output voltage (12.179) and the total output voltage (12.180) Example 12.13 Draw the total output voltage vO(t) of the closed-loop buck converter of Example 12.8 as a response to the step change in the reference voltage from 5 to 6 V. Find the maximum overshoot and the maximum transient ripple. Calculate also an increase in the steady-state output voltage. Solution: Figure 12.42 shows the step response of the output voltage vO to a step change in the reference voltage vR from 5 to 6 V, which corresponds to a step change in the ac component of the reference voltage vr from 0 to 1 V, for the buck converter with negative feedback. The total output voltage vO increase from 14 to 17.74 V and reaches a steady-state value of 16.8 V after 0.3 ms. The maximum overshoot is (12.181) The maximum transient ripple is (12.182) When the reference voltage is VR = 5 V and the output voltage is VO = 14 V, the dc closed-loop voltage transfer function is (12.183) The increase of the reference voltage VR from 5 to 6 V causes the output voltage VO to increase to (12.184) or (12.185)

Thus, the increase in the steady-state output voltage is (12.186) Consequently, the output voltage vO increases from 14 V to approximately 16.8 V.

Figure 12.42 Step response of vO to a step change in vR from 5 to 6 V for the buck converter with negative feedback.

12.10.3 Closed-Loop Response to Step Change in Load Current The load current with a step change ΔIO at t = 0 can be expressed by (12.187) Therefore, the step change in the load current in the time domain is (12.188) and the s-domain is

(12.189) Hence, using (12.165), one obtains the transient component of the output voltage in the sdomain (12.190) The inverse Laplace transform of vo(s) gives the transient component of the output voltage vo(t), which leads to the total output voltage vO(t) = VO(0−) + vo(t). Example 12.14 Draw the total output voltage vO(t) of the closed-loop buck converter of Example 12.8 as a response to the step change in the load current IO from 1.4 to 1.5 A. Find the maximum transient ripple. Solution: Figure 12.43 shows the step response of the output voltage vO to a step change in the load current IO from 1.4 to 1.5 A, which corresponds to a step change in the ac component of the load current io from 0 to 0.1 A, for the buck converter with negative feedback. The total output voltage vO decreases from 14 to 13.96 V and reaches a steady-state value of 14 V after 0.4 ms. The maximum transient zero-to-peak ripple of the output voltage is (12.191) The step change in the output voltage at t = 0 is ΔVO = rC||RLΔIO ≈ −rCΔIO = −0.391 × 0.1 = −39.1 mV. The value of the filter capacitor ESR rC has a significant influence on the output voltage response to a step change in the load current.

Figure 12.43 Step response of vO to a step change in the load current IO from 1.4 to 1.5 A for the buck converter with negative feedback.

12.10.4 Closed-Loop DC Transfer Functions Figure 12.44 shows a closed-loop model and control block diagrams. The dc forward-path voltage transfer function is (12.192) The dc loop gain is (12.193) The dc closed-loop control-to-output gain is (12.194) The dc closed-loop output impedance is

(12.195) The dc closed-loop input-to-output gain is (12.196)

Figure 12.44 Closed-loop dc model of the PWM buck converter. Example 12.15 For the buck converter given in Example 12.8 with VInom = 28 V and VO = 14 V, calculate Tclo, VO, VE, and Roclo if Tco = 1000, Tpo = 27.559 V, β = 5/14, VR = 5 V, and Ro = 0.157 Ω. Solution: The dc forward-path voltage transfer function is (12.197)

The dc loop gain is (12.198) The dc closed-loop control-to-output voltage transfer function is (12.199) The dc output voltage is (12.200) the dc error voltage is (12.201) the dc feedback voltage is (12.202) and the dc control voltage is (12.203) If the reference voltage has a step change from 5 to 6 V, then ΔVR = 1 V. The change in the dc output voltage is (12.204) Hence, the dc output voltage is (12.205) The dc closed-loop input-to-output gain is (12.206) If the dc input voltage has a step change from 28 to 30 V, then ΔVI = 2 V. The change in the dc output voltage is (12.207) Thus, the dc output voltage is (12.208)

The line regulation is (12.209) The percentage line regulation is (12.210) The dc closed-loop output resistance is (12.211) If the load current has step change ΔIO = 0.2 A, then the change in the dc output voltage is (12.212) The dc output voltage is (12.213) The load regulation is (12.214) The dc output-to-reference voltage transfer function is (12.215)

12.11 Summary The percentage change in the closed-loop transfer function Af is (1 + βA) times lower than that of the A-network. Therefore, if the loop gain T = βA 1, the closed-loop transfer function Af is almost independent of the A-network parameters. The percentage change of the closed-loop transfer function Af is almost equal in magnitude and is of the opposite sign to the percentage change in the transfer function of the feedback network.

If the loop gain T = βA 1, the closed-loop transfer function Af is almost entirely determined by the feedback network transfer function β. The feedback network should be made up of precision resistors to achieve an accurate output voltage VO. The closed-loop buck converter has three inputs (dc reference voltage VR, input voltage vI, and load current iO) and one output (the output voltage vO). A series-shunt topology of negative feedback is used in the voltage-mode-controlled PWM buck converter. This topology of negative feedback stabilizes the voltage transfer function and reduces the output impedance of the closed-loop converter. There is a loading effect of the forward A-network by the feedback network, which may change the transfer function of the controller. The hybrid h-parameters can be used to describe the series-shunt feedback network. Negative feedback reduces the magnitude of the audio susceptibility by a factor |1 + T|. Negative feedback reduces the magnitude of the output impedance by a factor |1 + T|. Negative feedback is effective at low frequencies, where |T| 1. Negative feedback is not effective at high frequencies, where |T| 1. The voltage-mode control circuit of the buck converter consists of a control circuit, PWM modulator, power stage of the buck converter, and feedback network. The pulse-width modulator is made of an open-loop op-amp with a ramp voltage applied to the inverting input and the control voltage applied to the non-inverting input. The op-amp used for the pulse-width modulator should have a high slew rate. The integral controller is attractive because its gain at low frequencies is high. However, it introduces a phase lag of − 90° at all frequencies, which may cause instability. The lead controller is attractive because its phase lag is reduced in some frequency range. The integral-single-lead controller provides the phase lag reduction theoretically between 0 and 90° and practically between 0 and 80°. The magnitude of the audio susceptibility |Mvcl| is lower than the magnitude of the openloop audio susceptibility |Mv| by a factor of |1 + T|. The closed-loop input resistance of the buck converter is negative at low frequencies. The magnitude of the closed-loop output impedance |Zocl| is lower than the magnitude of the open-loop output impedance |Zo| by a factor of |1 + T|.

References

1. M. K. Kazimierczuk, N. Sathappan, and D. Czarkowski, “A voltage-mode-control PWM buck dc-dc converter with a proportional controller,” Proceedings of the IEEE National Aerospace and Electronic Conference (NAECON’93), Dayton, OH, May 24–28, 1993, vol. 2, pp. 639–644. 2. M. K. Kazimierczuk, R. C. Cravens, II, and A. Reatti, “Closed-loop input impedance of the PWM buck converter,” Proceedings of the IEEE International Symposium on Circuits and Systems, London, UK, May 30–June 3, 1994, pp. 61–64. 3. R. D. Midddlebrook, “The general feedback theorem: a final solution for feedback system,” IEEE Microwave Magazine, pp. 50–61, April 2006. 4. H. D. Venable, “The K factor: a new mathematical tool for stability analysis and synthesis,” Proceedings of the Powercon 10, 1983, H-1, pp. 1–12.

Review Questions 1. Draw the circuit of the voltage-mode-controlled PWM buck converter. 2. Draw a block diagram of the closed-loop PWM buck converter for small-signal operation. 3. Draw a simplified block diagram of the closed-loop PWM buck converter for small-signal operation. 4. Derive an expression for the loop gain for the buck converter. 5. Derive an expression for the closed-loop small-signal control-to-input transfer function Tcl for the buck converter with an integral-single-lead controller. 6. What is the order of the closed-loop control-to-output transfer function Tcl? 7. What is the location of the poles and the zero of the closed-loop control-to-output transfer function Tcl in the s-plane? 8. Draw a small-signal model of the PWM buck converter for deriving the closed-loop inputto-output transfer function Mvcl. 9. Derive a closed-loop small-signal input-to-input transfer function Mvcl for the buck converter. 10. What is the physical meaning of the input-to-output transfer function Mvcl? 11. Draw a small-signal model of the PWM buck converter for deriving the closed-loop input impedance Zicl. 12. Derive an expression for the closed-loop input impedance Zicl for the buck converter. 13. Draw a small-signal model of the PWM buck converter for deriving the closed-loop output impedance Zocl.

14. Derive an expression for the closed-loop output impedance Zocl for the buck converter. 15. Explain the behavior of the closed-loop susceptibility Mvcl versus frequency. 16. Explain the behavior of the closed-loop output impedance Zocl versus frequency.

Problems 1. Determine the transfer function of the pulse-width modulator if VTm = 5 V. 2. Determine the reference voltage if Dnom = 0.5 and VTm = 5 V. 3. A buck converter has VO = 12 V and VR = 5 V. Design a feedback network. 4. A buck converter has Tpo = 25 V, Tm = 0.4 1/V, β = 0.2, ξ = 0.3549, fz = 31.8 kHz, and f0 = 2.6 kHz. Design a control circuit such that PM ≥ 60°. 5. At f = 120 Hz, |Mv| = 0.5, |T| = 34 dB, and the ripple input voltage is Vr(in) = 1 V. Find the output ripple voltage.

13 Voltage-Mode Control of Boost Converter 13.1 Introduction The objective of this chapter is to present a small-signal analysis of a closed-loop voltagemode-controlled PWM boost dc–dc converter with an integral-lead controller, also called an integral-double-lead (IDL) controller [1–13]. The circuit of the controller is analyzed. Its design procedure is developed. Loop gain, closed-loop transfer functions, and closed-loop input and output impedances are found. In addition, step responses of the closed-loop circuit are computed for changes in the input voltage and the reference voltage. A design example is given.

13.2 Circuit of Boost Converter with Voltage-Mode Control A boost converter with a single-loop control circuit is shown in Figure 13.1. This circuit has a series-shunt negative feedback topology. The duty cycle is directly controlled by the voltage derived from the reference voltage VR and the feedback voltage vF. This method of control is called voltage-mode control.

Figure 13.1 Boost PWM converter with voltage-mode control. The feedback network can be represented by h-parameters as shown in Figure 13.2. The resistances h11 = RARB/(RA + RB) and 1/h22 = RA + RB can be moved from the feedback network to the A-circuit [13] as shown in Figure 13.3. Since usually 1/h22 RL, it can be neglected.

Figure 13.2 Closed-loop boost PWM converter with a feedback network β represented by hparameters.

Figure 13.3 Closed-loop boost PWM converter with resistances h11 and 1/h22 moved to the Anetwork. Figure 13.4(a) shows a small-signal model of the boost converter and various stages related to the control of the output voltage. A block diagram of a closed-loop boost converter with voltage-mode-control is shown in Figure 13.4(b). In this figure, Tp is the small-signal controlto-output transfer function of the power stage of the boost converter, Mv is the input-to-output voltage transfer function, Zo is the open-loop output impedance, Tm is the transfer function of the pulse-width modulator, Tc is the voltage transfer function of the controller, β is the transfer function of the feedback network, vf is the ac component of the feedback voltage, vc is the ac component of the output voltage of the controller, ve is the ac component of the error voltage, and vr is the ac component of the reference voltage. The control block diagram is a three-input and a single-output system driven by three independent sources, vr, vi, and io. The ac component of the input voltage vi can be viewed as a disturbance caused by a low-frequency ripple voltage and/or variations of the line voltage. For a constant dc output voltage, vr = 0. The voltage gain of the forward path for the ac components is (13.1) and the loop gain is

(13.2) The ac component of the output voltage is given by (13.3) where vd = v′′o − v′′′o is the total disturbance voltage. Using this equation, the block diagram of Figure 13.4(b) can be simplified to the form shown in Figure 13.4(c).

Figure 13.4 Closed-loop small-signal low-frequency model of the boost converter. (a) Smallsignal model. (b) Block diagram. (c) Simplified block diagram.

13.3 Transfer Function of Modulator, Boost Converter Power Stage, and Feedback Network

The transfer function of the pulse-width modulator and the boost converter power stage is (13.4)

where (13.5) Example 13.1 A boost converter has VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and VTm = 5 V. Calculate Tmpo and draw Bode plots of Tmp for D = 0.5. Solution: The transfer function of the pulse-width modulator is (13.6) The frequency of the LHP zero is fzn = 21.09 kHz. At RLmin, Tpo = 37.55 V, ξ = 0.261, f0 = 784 Hz, and fzp = 9.88 kHz. The transfer function of the pulse-width modulator and the boost converter at f = 0 is (13.7) Figures 13.5 and 13.6 show Bode plots of Tmp = TmTp.

Figure 13.5 Bode plot of the magnitude of the modulator and the control-to-output transfer function Tmp = TmTp for the boost converter.

Figure 13.6 Bode plot of the phase of the modulator and the control-to-output transfer function Tmp = TmTp for the boost converter. Since VC ≈ VR and D = VC/VTm ≈ VR/VTm, the reference voltage can be found as (13.8) The voltage transfer function of the feedback network is (13.9) The transfer function of the pulse-width modulator, the boost converter, and the feedback network (i.e., the transfer function of the uncompensated loop) is

(13.10)

where (13.11) Substituting s = jω, we get the transfer function of the uncompensated loop (13.12)

where (13.13)

and (13.14)

or (13.15)

Example 13.2 A boost converter has VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, Tmpo = 7.51, and β = 0.125. Calculate Tko. Draw Bode plots of Tk for D = 0.5. Solution: The dc reference voltage is (13.16)

The voltage transfer function of the feedback network is (13.17) Thus, (13.18) Figures 13.7 and 13.8 show Bode plots of Tk . The phases of Tmp and Tk are the same as the phase of Tp.

Figure 13.7 Bode plot of the magnitude of the modulator, the control-to-output transfer function, and the feedback network Tk = βTmp = βTmTp for the boost converter.

Figure 13.8 Bode plot of the magnitude of the modulator, the control-to-output transfer function, and the feedback network Tk = βTmp = βTmTp for the boost converter. Figure 12.20 shows a circuit of an integral controller and its KP = 10 and fz = 10 Hz.

13.4 Integral-Double-Lead Controller An IDL compensator, also called a third-order integral-lead controller or the type III controller [4], is shown in Figure 13.9(a). The circuit is loaded by the feedback network in the form of h11 = RA||RB [13]. The controller has a pole at the origin and two zero–pole pairs. Since the magnitude of the transfer function of the controller has three slopes, the circuit is called the type III controller. An equivalent circuit of the controller for the ac component is depicted in Figure 13.9(b). The Miller integral part of this controller is used to achieve a large lowfrequency gain and, therefore, to reduce both the dc error and the closed-loop output impedance at low frequencies. However, an integral controller introduces a phase lag of –90° at all frequencies. The phase lag can be reduced by means of a lead controller in a limited frequency range. This allows a wider closed-loop bandwidth and, therefore, a faster step

response. The phase boost ϕm of this controller is theoretically 180° and in practice less than 160°. The task for the lead controller is to achieve a high crossover frequency fc of the controlto-output gain, while maintaining a specified phase margin PM.

Figure 13.9 Third-order integral-double-lead controller with two zero–pole pairs (type III controller). (a) Circuit. (b) Equivalent circuit for the ac component. The impedances of the controller are (13.19)

(13.20)

where (13.21) Assume that the open-loop dc gain and the bandwidth of the operational amplifier are infinite. Hence, from (13.19) and (13.20), the voltage transfer function of the controller for the ac component is (13.22)

At vr = 0, ve = −vf and therefore the voltage transfer function of the IDL controller is (13.23) where (13.24) (13.25) (13.26) (13.27) and (13.28) The voltage transfer function of the controller is Av(s) ≡ vc(s)/ve(s) = −Tc(s). Assuming that ωzc1 = ωzc2 = ωzc and ωpc1 = ωpc2 = ωpc and using (13.25) and (13.26), (13.29) Hence, (13.23) becomes

(13.30)

For s = jω, (13.31)

where the magnitude of Tc is (13.32)

and the phase shift of Tc is (13.33)

The maximum value of phase ϕTc occurs at the geometric mean value of the zero frequency and the pole frequency and from (13.25), (13.28), and (13.29) is given by (13.34)

Substitution of (13.34) into (13.33) and using the relationship yields the phase shift at f = fm (13.35) Thus, the maximum amount of the phase shift reduction is (13.36) from which

(13.37)

Hence, (13.38) Figure 13.10 shows ϕm versus K. Note that ϕm increases from 0 to about 160° as K is increased from nearly 0 to 100.

Figure 13.10 Maximum phase boost ϕm versus K for the integral-double-lead controller with two zero–pole pairs (type III controller). Substituting (13.34) into (13.32) and using (13.24) and (13.29), one obtains the magnitude of the controller voltage transfer function at the frequency f = fm

(13.39) The magnitude of the loop gain at the crossover frequency fc = fm is (13.40) Assuming that fc = fm and using (13.39) and (13.40), one arrives at (13.41) The phase shift of the loop gain at the crossover frequency fc is (13.42) The phase boost is (13.43) yielding (13.44) Using (13.35), the phase margin is obtained as (13.45) Hence, the required phase boost is (13.46)

13.5 Design of Integral-Double-Lead Controller A boost PWM converter has VInom = 12 V, VO = 20 V, VR = 2.5 V, RLmin = 40 Ω, RLmax = 200 Ω, Dnom = 0.5, ξ = 0.261, f0 = 784 Hz, fzp = 9.88 kHz, fzn = 21.09 kHz, VTm = 5 V, and Tko = 0.9388. Design a control circuit such that GM ≥ 10 dB and PM = 60°. The voltage transfer function of the feedback network is (13.47) Assuming RB = 620 Ω/0.25 W/1%, one obtains (13.48)

Pick RA = 4.3 Ω/0.25 W/1%. Hence, (13.49) Note that 1/h22 = RA + RB = 0.62 + 4.3 = 4.92 kΩ RLmax = 200 Ω and therefore (1/h22)||RLmax = 192 Ω. Assume that fc = fm = 2 kHz. From (13.15), (13.50)

Since the specified phase margin is PM = 60°, one obtains the required phase boost (13.51) and the K factor (13.52) The frequencies of the poles and the zeros of the controller are (13.53) and (13.54) From (13.13), (13.55)

Next, (13.56) and (13.57) Bode plots of Tc of the controller are shown in Figures 13.11 and 13.12. From these plots, GM = 11 dB and PM = 60°. If GM is too low, fc should be reduced and the entire procedure should be repeated.

Figure 13.11 Bode plot of the magnitude of the voltage transfer function Tc for the designed integral-double-lead controller with two zero–pole pairs (type III converter).

Figure 13.12 Bode plot of the phase of the voltage transfer function Tc for the designed integral-double-lead controller with two zero–pole pairs (Type III). Assuming R1 = 100 kΩ/0.25 W/1% and using (13.29), one obtains (13.58) Pick R3 = 2.2 kΩ/0.25 W/1%. Hence, from (13.41), (13.59) Pick C2 = 150 pF/12 V. From (13.29), (13.60) Pick C1 = 4.7 nF/12 V. Using (13.34),

(13.61) Pick R2 = 100 kΩ/0.25 W/1%. From (13.34), (13.62)

Pick C3 = 4.7 nF/12 V. From (13.24), (13.63)

The frequencies of the poles and the zeros of the controller with standard resistors and capacitors are (13.64) (13.65) (13.66) and (13.67)

13.6 Loop Gain The loop gain of the converter is (13.68)

where

(13.69) Example 13.3 A boost converter has VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, β = 0.125, Tm = 0.2 1/V, kHz, fzp = 9.88 kHz, f0 = 784 Hz, ξ = 0.261, B = 2.7079 × 106 rad/s, fzc = 330.829 Hz, and fpc = 12.09 kHz. Draw Bode plots for the loop gain T of the boost converter for D = 0.5. Solution: Figures 13.13 and 13.14 show Bode plots of the loop gain T for D = 0.5. The crossover frequency is fc = 2 kHz at Dnom = 0.5. The phase margin is PM = 60°. The phase crosses − 180° at kHz and the gain margin is GM = 14 dB.

Figure 13.13 Bode plot of the magnitude of the loop gain T for the boost converter.

Figure 13.14 Bode plot of the phase of the loop gain T for the boost converter.

13.7 Closed-Loop Control-to-Output Voltage Transfer Function The closed-loop control-to-output transfer function is found as (13.70)

It is a fifth order function. Example 13.4 A boost converter has β = 0.125, Tm = 0.2 (1/V), VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, and C3 = 5 nF.

Calculate Tclo = Tcl(0). Draw Bode plots for the closed-loop control-to-output transfer function Tcl of the boost converter for D = 0.5. Solution: The closed-loop control-to-output transfer function at f = 0 is (13.71) Figures 13.15 and 13.16 show Bode plots of Tcl. The bandwidth of the closed-loop control-tooutput transfer function is BWf = 2 kHz at D = 0.5.

Figure 13.15 Bode plot of the magnitude of the closed-loop control-to-output transfer function Tcl for the boost converter.

Figure 13.16 Bode plot of the phase of the closed-loop control-to-output transfer function Tcl for the boost converter.

13.8 Closed-Loop Audio Susceptibility The closed-loop input-to-output voltage transfer function, called the audio susceptibility, is given by (13.72)

Example 13.5 A boost converter has β = 0.125, VTm = 5 V, VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, and C3 = 5 nF. Draw Bode plots for the closed-loop input-to-output transfer function Mvcl of the boost converter for D =

0.5. Solution: Figures 13.17 and 13.18 show Bode plots of Mvcl.

Figure 13.17 Bode plot of the magnitude of the closed-loop input-to-output transfer function Mvcl for the boost converter.

Figure 13.18 Bode plot of the phase of the closed-loop input-to-output transfer function Mvcl for the boost converter.

13.9 Closed-Loop Input Impedance Referring to the block diagram shown in Figure 13.4(a) and setting vr = 0, (13.73) Using tKCL and assuming that RA + RB RL, one obtains (13.74) which gives (13.75)

Substitution of (13.73) into (13.74) yields (13.76) A dc analysis of the boost converter leads to (13.77) Substituting (13.77) into (13.75) gives (13.78) Dividing both sides by vi gives the closed-loop input admittance (13.79) which, after substitution of (13.72), simplifies to (13.80) Dividing Mv by Tp gives (13.81) Substitution of (13.81) into (13.80) produces (13.82) The impedance Z2 is given by (13.83)

where (13.84) and

(13.85) Hence, one arrives at the closed-loop input admittance (13.86) and the closed-loop input impedance (13.87) At low frequencies, |T| 1 and therefore | T|/|1 + T| ≈ 1, |Mvcl| 1, and the low-frequency closed-loop input impedance can be approximated by (13.88) and the dc closed-loop input resistance (13.89) The dc closed-loop input resistance can be expressed in terms of the dc voltage transfer function MV DC = 1/(1 − D) as (13.90) The closed-loop output impedance can also be represented as the closed-loop input resistance and the closed-loop reactance (13.91) where Ricl = |Zicl|cos ϕZicl and Xicl = |Zicl|sin ϕZicl. Example 13.6 A boost converter has β = 0.125, VTm = 5 V, VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, r = 0.316 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, and C3 = 5 nF. Calculate Ricl(0). Draw the plots for the closed-loop input impedance Zicl as the magnitude and the phase and also as the real and imaginary parts for the boost converter. Solution: The closed-loop input resistance is (13.92) Figures 13.19 and 13.20 show plots of versus frequency. Note that the phase ϕZicl is close to − 180° at low frequencies. Figures 13.21 and 13.22 depict plots of Zicl = Ricl +

jXicl versus frequency. The input resistance Ricl is negative at low frequencies from 0 to 400 Hz. This may cause instability.

Figure 13.19 The magnitude of the closed-loop input impedance Zicl versus frequency for the boost converter.

Figure 13.20 The phase of the closed-loop input impedance Zicl versus frequency for the boost converter.

Figure 13.21 The input resistance of the closed-loop input impedance Zicl = Ricl + jXicl versus frequency for the boost converter.

Figure 13.22 The input reactance of the closed-loop input impedance Zicl = Ricl + jXicl versus frequency for the boost converter.

13.10 Closed-Loop Output Impedance The closed-loop output impedance including the load resistance RL is (13.93)

where vt and it are the test voltage and the test current, respectively. The closed-loop output impedance excluding the load resistance RL is given by

(13.94) Since |Zocl| RL, Z′ocl ≈ Zocl. The magnitude of the output impedance |Z′ocl| of an ideal voltage source should be zero at all frequencies. Example 13.7 A boost converter has β = 0.125, VTm = 5 V, VInom = 12 V, VO = 20 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, R3 = 2.2 kΩ, C1 = 5 nF, C2 = 0.15 nF, C3 = 5 nF. Calculate Ricl(0). Draw the plots for the closed-loop output impedance Zocl versus frequency for the boost converter for D = 0.4, 0.5, and 0.6. Solution: Figures 13.23 and 13.24 show the plots of Zocl for the boost converter.

Figure 13.23 Plot of the magnitude of the closed-loop output impedance Zocl versus frequency for the boost converter.

Figure 13.24 Plot of the magnitude of the closed-loop output impedance Zocl versus frequency for the boost converter.

13.11 Closed-Loop Step Responses 13.11.1 Closed-Loop Response to Step Change in Input Voltage Assume that the step change in the input voltage is ΔVI at time t = 0 and the steady-state input voltage before the step change is VI(0−). Therefore, the total input voltage is given by (13.95) which results in a step change in the input voltage in the time domain (13.96) and in the s-domain

(13.97) Hence, one obtains a transient component of the output voltage in the s-domain (13.98) the transient component of the output voltage in the time domain (13.99) and the total output voltage (13.100) Example 13.8 Draw the waveform of the total output voltage vO(t) of the closed-loop boost converter of Example 13.1 as a response to the step change in the input voltage from 12 to 13 V. Find the maximum relative transient ripple of the total output voltage vO. Solution: Figure 13.25 shows the step response of the output voltage vO to the step change in the input voltage vI from 12 to 13 V for the boost converter with negative feedback at β = 0.125, VTm = 5 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, C1 = 5 nF, C2 = 0.15 nF, C3 = 5 nF, and D = 0.5. The output voltage increases from 20 to 20.63 V and then returns back to VO = 20 V after 6 ms. The maximum relative transient ripple of the output voltage is (13.101)

Figure 13.25 Response of vO to a step change in input voltage vI from 12 to 13 V for the boost converter with negative feedback.

13.11.2 Closed-Loop Response to Step Change in Reference Voltage Assume that the step change in the reference voltage is ΔVR at time t = 0 and the reference voltage is VR(0−). The total reference voltage can be described by (13.102) Hence, the ac component of the reference voltage in the time domain is (13.103) and in the s-domain is (13.104)

The transient component of the output voltage in the s-domain can be expressed as (13.105) The inverse Laplace transform of vo(s) produces the transient component of the output voltage (13.106) and the total output voltage (13.107) Example 13.9 Draw the total output voltage vO(t) of the closed-loop boost converter of Example 13.1 as a response to the step change in the reference voltage vR from 2.5 to 3 V. Find the maximum overshoot and the maximum transient ripple. Also, calculate an increase in the steady-state output voltage. Solution: Figure 13.26 shows the step response of the output voltage vO to a step change in the reference voltage vR from 2.5 to 3 V, which corresponds to the step change in the ac component of the reference voltage vr from 0 to 0.5 V at D = 0.5 for the boost converter with negative feedback. The total output voltage vO initially decreases from 20 to 19.8 V, then increases to 23.8 V, decreases again, and finally reaches a steady-state value of 24 V after 5 ms. Notice that output voltage initially decreases because of the presence of the RHP zero in the transfer function Tcl. The peak value of vO is lower than the steady-state value. Therefore, the overshoot can be considered to be zero. At the reference voltage VR = 2.5 V and the output voltage VO = 20 V, the closed-loop controlto-output voltage transfer function should be (13.108) The increase of the reference voltage VR from 2.5 to 3 V causes the output voltage VO to increase to (13.109) or (13.110) Thus, the increase in the steady-state output voltage is (13.111)

The dc output voltage VO increases from 20 V to approximately 24 V.

Figure 13.26 Response of vO to a step change in reference voltage vR from 2.5 to 3 V for the boost converter with negative feedback.

13.11.3 Closed-Loop Response to Step Change in Load Current The load current contains a step change ΔIO at t = 0 is described by (13.112) Hence, the small-signal step change in the load current is (13.113) which gives (13.114)

Therefore, the transient component of the output voltage is given by (13.115)

The transient component of the output voltage in the time domain (13.116) and the total output voltage (13.117) Example 13.10 Draw the waveform of the total output voltage vO(t) of the closed-loop boost converter of Example 13.1 as a response to the step change in the load current iO from 0.5 to 0.6 A. Find the maximum relative transient ripple of the total output voltage vO. Solution: Figure 13.27 shows a step response of the output voltage vO to a step change in the load current iO from 0.5 to 0.6 A for the boost converter with negative feedback at β = 0.125, VTm = 5 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, RLmin = 40 Ω, R1 = 100 kΩ, R2 = 100 kΩ, C1 = 5 nF, C2 = 0.15 nF, C3 = 5 nF, and D = 0.5. The output voltage decreases from 20 to 19.893 V and then returns back to VO = 20 V after 5 ms. The maximum relative transient ripple of the output voltage is (13.118)

Figure 13.27 Response of vO to a step change in load current iO from 0.5 to 0.6 A for the boost converter with negative feedback.

13.12 Closed-Loop DC Transfer Functions The dc voltage transfer function of the forward path is (13.119) where Tco = Tc(0) is the dc gain of the control circuit. The dc loop gain is expressed by (13.120) The dc closed-loop control-to-output voltage gain is

(13.121) If βAo 1, then (13.122) and the dc output voltage is (13.123) To ensure that the dc output voltage VO remains constant and equal to a desired value, the loop gain βAo must be very high and the feedback network voltage transfer function β and the reference voltage VR must be accurate. An accurate value of β is achieved by using precision resistors, for example, 1%. The dc closed-loop audio susceptibility is (13.124) and the dc closed-loop output resistance is (13.125) Example 13.11 For the boost converter given in Example 13.1, calculate Tclo, VO, VE, Zoclo, and Mvclo if Tco = 1000, Tpo = 37.55, β = 1/8, VTm = 5 V, Mvo = 1.939, and Zoo = 1.225 Ω. Solution: The bound resistor is (13.126) Pick Rb = 100 MΩ/0.25 W/5%. The dc voltage transfer function of the forward path is (13.127) The dc loop gain is (13.128) The dc closed-loop control-to-output gain is (13.129)

The dc output voltage is (13.130) the dc feedback voltage is (13.131) and the dc error voltage is (13.132) The dc closed-loop input-to-output voltage transfer function is (13.133) When the reference voltage VR is increased from 2.5 to 3 V, ΔVR = 0.5 V. The increase in the dc output voltage is The dc output voltage is (13.134) The dc output voltage is (13.135) Assuming that the dc input voltage will have a step change from 12 to 13 V, then ΔVI = 1 V. The change in the dc output voltage is (13.136) The dc output voltage is (13.137) The line regulation at IO = 0.5 A is (13.138) The percentage line regulation is (13.139) The dc closed-loop output impedance is (13.140)

Assuming that the dc output current has a step change from 0.5 to 0.6 mA, then ΔIO = 0.1 A. This causes a change in the dc output voltage (13.141) The dc output voltage is (13.142) The load regulation is (13.143) The dc reference-to-output voltage transfer function is (13.144)

13.13 Summary The closed-loop boost converter consists of feedback network, control circuit, pulse-width modulator, and boost converter power stage. It is difficult to achieve good gain and phase margins of the boost converter because of the RHP zero. The bandwidth of the boost converter with voltage-mode control is usually narrow. The input resistance of the closed-loop boost converter is negative.

References 1. R. D. Middlebrook and S. Ćuk, Advances in Switched-Mode Power Conversion, vols. I and II. Pasadena, CA, TESLAco, 1981. 2. R. D. Middlebrook, “Measurement of loop gain in feedback systems,” International Journal of Electronics, vol. 38, no 4, pp. 485–512, April 1975. 3. R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits, New York: Van Nostrand, 1985, pp. 30–42 and 130–135. 4. H. D. Venable, “The K factor: A new mathematical tool for stability analysis and synthesis,” Proceedings of the Powercon 10, 1983, H-1, pp. 1–12.

5. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2003. 6. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, Reading, MA: Addison-Wesley, 1991. 7. R. W. Erickson and D. Maksimović, Fundamentals of Power Electronics, 2nd Ed. Norwell, MA: Kluwer, 2001. 8. V. Vorpérian, “Simplified analysis of PWM converters using the model of the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-26, pp. 497–505, May 1990. 9. D. Czarkowski and M. K. Kazimierczuk, “Energy conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. 29, pp. 1059–1063, July 1993. 10. M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” 2nd IEEE Conference on Control Applications, Vancouver, Canada, September 13–16, 1993, pp. 291–296. 11. M. K. Kazimierczuk and R. C. Cravens, II, “Close-loop characteristics of voltage-mode controlled PWM boost dc-dc converter with integral-lead controller,” Journal of Circuits, Systems, and Computers, vol. 4, no. 4, pp. 429–458, 1994. 12. M. K. Kazimierczuk and R. C. Cravens, II, “Experimental results for the small-signal study of PWM boost dc-dc converter with an integral-lead controller,” Journal of Circuits, Systems, and Computers, vol. 5, no. 4, pp. 747–755, 1995. 13. A. Aminian and M. K. Kazimierczuk, Electronic Devices, A Design Approach, ch. 12. Upper Saddle River, NJ: Prentice Hall, 2003, pp. 523–564.

Review Questions 1. Draw the boost converter along with other stages that form a single-loop negative feedback control circuit. 2. Draw a single-loop control circuit for the boost converter with the feedback network replaced by h-parameters. 3. Draw a single-loop control circuit for the boost converter with the resistances of the feedback network moved to the A-circuit. 4. Derive an expression for the closed-loop gain of the boost converter Tcl. 5. Is it easy to ensure the stability of the boost converter? 6. What is the effect of negative feedback on the audio susceptibility Mvcl?

7. What is the effect of negative feedback on the input impedance Zicl? 8. What is the effect of negative feedback on the output impedance Zocl?

Problems 1. A pulse-width modulator has a ramp output voltage with a peak value VTm = 5 V. Find a transfer function of the modulator. 2. A boost PWM converter has VInom = 156 V, Dnom = 0.65, and the pulse-width modulator VTm = 5 V. Determine the dc reference voltage for a control circuit. 3. A boost PWM converter has VO = 400 V and the reference voltage is VR = 3.25 V. Design a feedback network. 4. A boost PWM converter has Tpo = 1114.27 V, a feedback network has β = 1/123, and a pulse-width modulator has Tm = 0.2 (1/V). Determine the overall voltage transfer function Tko of the three stages at f = 0. 5. A boost PWM converter has VI = 156 V, VO = 400 V, VR = 3.25 V, Tko = 1.8118, β = 1/123, ξ = 0.162, fzn = 159 kHz, fzp = 1.17 kHz, and f0 = 322 Hz. Design a control circuit such that PM ≥ 55°. 6. The transfer function of the feedback network in a boost converter is β = 1/123. Find the value of the closed-loop control-to-input voltage transfer function at f = 0. 7. A closed-loop boost converter has Dnom = 0.65, RLmin = 1.778 kΩ, RLmax = 17.78 kΩ, and r = 2.756 Ω. Find the values of the dc closed-loop input resistance at RLmin and RLmax.

14 Current-Mode Control 14.1 Introduction The control circuit of a power dc–dc converter must decide when to turn the switch (or switches) on and off. Voltage-mode control (VMC), also called duty-cycle control, contains a single loop and adjusts the duty cycle directly in response to the change in output voltage. Current-mode control (CMC) [1–84], also called current-programmed mode (CPM) or current-injected control (CIC), is a multiple-loop control method that contains two loops: the inner-current loop and the outer voltage loop. The inner-current loop controls the inductor peak current, while the outer-voltage loop controls the output voltage. The technique is called CMC because the inductor current is directly controlled, whereas the output voltage is controlled only indirectly by the current loop. The inductor peak current is close to the inductor average current. The inductor average current is related to the load current. In buck and buckderived converters, the load current is equal to the average current. In the boost converter (often used as a power-factor corrector), the average input current is equal to the average inductor current. The inner-current loop initially adjusts the duty cycle in response to the changes in inductor current, and the outer voltage loop produces a reference voltage for the current loop in response to the changes in the converter output voltage. The duty cycle is determined by the time instants at which the inductor or switch current reaches a threshold level determined by a control signal. This threshold level becomes the input to the inner loop. The key feature of the CMC is that the inner loop changes the inductor into a voltage-dependent current source at frequencies lower than the crossover frequency of the current loop. The action of the current loop is similar to that of a sample-and-hold circuit, which is a nonlinear, time-varying (NTV) system. There are seven known types of CMC methods. They, in turn, fall into two categories: constant-frequency and variable-frequency control methods. In the first group, the switching frequency is constant and synchronized to a clock signal fs = fCLK. This group contains peakcurrent-mode control (PCM), valley-current-mode control, the PWM-conductance control with triangle-wave compensation, and average current-mode control (ACM). The second group contains self-oscillating converters, including constant on-time, constant-off time, and hysteretic methods. The most popular method is fixed-frequency peak-current-mode control with fixed-slope compensation ramp. In this chapter, we shall study in detail the principle of operation of the peak-current-mode control, stability of the current loop, slope compensation, the block diagram of PWM converters with CMC, and key characteristics of current-mode controlled converters. The inner-current loop has a tendency to instability, resulting in subharmonic oscillation (also called period doubling). The required relative stability of the inner loop can be accomplished

by means of an artificial ramp current either subtracted from the control current or added to the inductor current waveform. CMC can also be used in constant-current dc-dc converters. There are IC control circuits, for example, UC3843.

14.2 Principle of Operation of PWM Converters with Peak CMC The circuits of the PWM buck, boost, and buck–boost converters with fixed-frequency peakcurrent-mode control are shown in Figures 14.1, 14.2, and 14.3, respectively. Each circuit contains two loops: an inner-current loop and an outer voltage loop. The inner-current loop contains an op-amp voltage comparator, an S–R (set–reset) latch, a clock CLK, and a current sensor, for example, a current transformer or a noninductive sense resistor Rs, which senses the inductor current iL or the switch current iS. In general, Rs represents the transfer function from the inductor or switch current to the sensor output voltage. It is current-to-voltage gain of the sensor. It may be a transfer function of a current transformer, which has corner frequencies in the low-frequency and high-frequency ranges. The latch S input sets (or presets) the Q output to 1, and the latch R input resets (or clears) the Q output to 0. The op-amp comparator, the S–R latch, and the clock CLK form an inductor current modulator. The analog control voltage vC is applied to the comparator inverting input, and the voltage RsiL (proportional to the inductor current iL) or the voltage RsiS (proportional to the switch current iS) is applied to the comparator non-inverting input.

Figure 14.1 Circuit of a PWM buck converter with peak-current-mode control.

Figure 14.2 Circuit of a PWM boost converter with peak-current-mode control.

Figure 14.3 Circuit of a PWM buck–boost converter with peak-current-mode control.

If a non-inductive resistor Rs is connected between the comparator non-inverting input and ground (as shown in Figure 14.1), the current through the resistor Rs is iC = v+/Rs ≈ vC/Rs. This current can be regarded as a control current (or a reference current) for the inner-current loop. Figure 14.4 depicts the waveforms explaining the principle of operation of PWM converters with CMC. The clock generates voltage pulses at a constant clock frequency fCLK equal to the switching frequency fs = 1/Ts. When the clock output voltage vCLK = vS goes high, the latch Q output vQ goes high (i.e., it sets the Q output to 1). Therefore, the gate-to-source voltage vGS also goes high, turning the switch on. This event initiates the transistor on-time and starts the cycle Ts of the switching frequency fs. Since the turn-on times are periodically clocked, a constant-frequency operation is obtained. While the switch is on, the inductor current iL and the switch current iS increase linearly. The inductor current iL, or the switch current iS, is sensed by a current probe (or current transformer). The currents iL and iS are equal during the transistor on-time. The sensed inductor current iL (or the switch current iS) flows through the resistor Rs and develops a voltage RsiL. When the voltage RsiL = v+ is lower than the control voltage vC = v−, the comparator output voltage vR is low. When the voltage RsiL reaches the control voltage vC, the comparator output voltage vR goes high, resetting the latch Q output to 0. Therefore, the gate-to-source voltage vGS goes low, turning the switch off for the remaining time of the switching period. As a result, the inductor current iL decreases. Since RsiL < vC, the comparator output voltage vR goes low. In summary, the clock sets the latch and turns the transistor on at the beginning of the cycle Ts. The comparator resets the latch and turns the transistor off when the inductor current iL reaches the control current iC. Consequently, the peak inductor current ILpk and the peak switch current ISpk follow the control current iC = vC/Rs. Thus, the amplitude modulation (AM) of the inductor current iL takes place, where the control current iC or the control voltage vC is the modulating signal. The average inductor current is (14.1) Since the peak inductor current is directly controlled, this method is called a peak-currentmode control. It can be regarded as an amplitude modulation of the inductor current by the control current. The inner-current loop is capable of responding very rapidly to control voltage (or control current) changes on a cycle-by-cycle or pulse-by-pulse basis. This control strategy is referred to as constant-frequency trailing-edge modulation peak-current-mode control or constant-frequency peak-current-mode on-time control because a fixed-frequency clock signal is used to turn on the switch, and the intersection of the voltage RsiL (proportional to the inductor current iL) with the control voltage vC is used to turn the switch off. The control decision is taken in each cycle. In other words, the clock initiates the on-time interval ton and the control voltage initiates the off-time interval toff . Thus, the switch on-time is controlled at a fixed frequency. This method requires inductor current information during the switch on-time.

The average value of the inductor current is lower than the peak value of the inductor current by one-half of the inductor peak-to-peak current ripple ΔiL; therefore, the average inductor current is controlled indirectly. The outer voltage loop senses the output voltage and develops a control voltage vC, which serves as a reference voltage for the inner-current loop; thus, the outer voltage loop adjusts the control voltage vC. The inductor current is fed back through a sensing resistor Rs and the resulting voltage RsiL is compared with the control voltage vC. The output voltage is fed back through a resistive voltage divider RA–RB, is compared with the reference voltage VR, and sets the control voltage vC. The input to the current loop is the control voltage vC, which is compared to the sensed inductor current iL (or voltage RsiL) and sets the duty cycle. In turn, the duty cycle produces a corresponding inductor current and output voltage. As a first-order approximation, the current loop causes the inductor to act like a voltage-controlled (or current-controlled) current source vC/Rs.

Figure 14.4 Waveforms of PWM converters with constant-frequency, trailing-edge modulation, peak-current-mode control.

A dual modulation strategy uses a constant-frequency clock signal to turn the transistor off and the intersection of the inductor or diode current to turn on the transistor. Thus, the switch offtime is controlled at fixed frequency. This control strategy is referred to as a constantfrequency leading-edge modulation valley current-mode control or constant-frequency valley current-mode off-time control. There are also three variable-frequency modulation strategies. The first is constant on-time control, the second is constant off-time control, and the third is hysteretic control. In hysteretic control, the inductor current waveform is used to turn on and turn off the switch, resulting in free-running operation. In addition to CMC based on instantaneous inductor current, there is also an average CMC method, where inductor current waveform is integrated by a low-pass filter placed at the output of the sense resistor Rs. The advantage of this method is the ability to directly control the average inductor current and increase the noise immunity. The constant-frequency trailing-edge modulation control strategy is the most widely used in practice with a large number of control ICs in the market and, therefore, is studied here in detail. CMC exhibits a feedforward control feature. When the converter input voltage VI is increased, the slope of the rising inductor current also increases. Therefore, the switch turns off sooner, yielding nearly constant volt-second balance and making the converter output voltage VO less dependent on the input voltage VI. In general, basic PWM converters (buck, boost, and buck–boost) are second-order systems, in which one state variable is the inductor current and the other state variable is the capacitor voltage (which is approximately equal to the output voltage). The converter dynamic performance can be improved by controlling both state variables. When CMC is used, the reference signal for the inner loop and the inductor current depends on the converter output voltage. As a result, one variable controls the other. Consequently, there is only one true state variable (i.e., the capacitor voltage), resulting in a system that behaves approximately as a first-order system. CMC offers several advantages over VMC. Firstly, if the maximum value of the control current iC is limited, then the maximum value of switch current iS is also limited. Since the inductor peak current is approximately equal to the inductor average current, which in turn is related to the load current, the output current can be limited simply by clamping the control voltage. The transistor turns off whenever its current becomes too high. Therefore, transistor and diode failures due to excessive currents can be prevented and the load current can be held below a predetermined maximum level. Thus, CMC inherently provides a fast pulse-by-pulse shortcircuit and overcurrent load protection, enhancing the converter reliability. In addition, the transient peak values of the inductor, switch, and diode currents are limited. A Zener diode may be connected between the comparator inverting input and ground to limit the maximum value of the control voltage. Secondly, it is easy to connect power converters with CMC in parallel in order to increase current capability and/or redundancy without load current-sharing problems. This is because the output current of each unit is determined by the control signal. If all the units receive the same control signal, then all of them will deliver the same amount of current. Thirdly, CMC is a perfect solution to transformer imbalance in symmetrical

converters, such as full-bridge and push-pull converters. The imbalance may be caused by the volt-second differences between the positive and negative pulses applied to the transformer. A series capacitor, which is usually used in full-bridge converters to remedy the transformer imbalance, should be removed if CMC is used. A disadvantage of peak-current-mode control is its inherent instability of the inner-current loop when D > 0.5, resulting in subharmonic oscillations. For a duty ratio greater than 0.5, slope compensation is required. Moreover, this control scheme is susceptible to noise, especially when the inductor ripple is small. This noise may corrupt the control voltage, the inductor current or switch current, generating a false signal for the non-inverting comparator input. Current spikes caused by the diode reverse recovery may have a detrimental effect. The CMC scheme requires a current sensor, which is usually a resistor Rs connected in series with the inductor L or the MOSFET source. Current flow through this resistor causes power loss. In addition, the sense resistor connected in series with the MOSFET source causes a degradation of the transistor current capability and may require a larger transistor size [64]. In the average-current-mode control [6–55], the inductor current is sensed and fed to a twopole and one-zero compensation network, which averages the inductor current. Consequently, the average inductor current follows the control reference current. The advantage of this control scheme is good immunity of a converter to switching noise because the average current is sensed. In addition, there is no need for slope compensation. With charge control [56], the inductor current is sensed and used to charge a capacitor. The capacitor voltage is compared to a control voltage, which represents the current to be controlled. As soon as the capacitor voltage reaches the control voltage, the active switch is turned off and the capacitor is quickly discharged to zero by an auxiliary switch connected in parallel with the capacitor. In this technique, the inductor current is indirectly controlled by regulating the peak capacitor voltage, which is proportional to the integral of the inductor current within one cycle. The advantage of this control scheme is good noise immunity due to the integration of the inductor current.

14.3 Relationship Between Duty Cycle and InductorCurrent Slopes Let us assume that a PWM converter is operated in steady state with constant input voltage VI, output voltage VO, load resistance RL, and duty cycle D. Figure 14.5 shows the inductor voltage and current waveforms under these conditions for CCM. The rising and falling slopes of the inductor current waveform are given by (14.2) and

(14.3) Hence, the ratio of the absolute values of the inductor-current slopes for all basic PWM converters in steady state is given by (14.4) Thus, the on-time slope M1 is equal to the off-time slope M2 at D = 0.5, M2 < M1 for D < 0.5, and M2 > M1 for D > 0.5.

Figure 14.5 Steady-state waveforms of the inductor voltage and current in PWM converters for CCM. In general, the rising and falling slopes of the inductor current are

(14.5) and (14.6) For the buck converter, (14.7) and (14.8) For the boost converter, (14.9) and (14.10) For the buck–boost converter, (14.11) and (14.12)

14.4 Instability of Closed-Current Loop A perturbation theory will be used to investigate the stability of the current loop. Consider a PWM converter with constant-frequency, trailing-edge modulation, peak-current-mode control operated in CCM, in which the inner-current loop is closed and the outer voltage loop is open. Assume that there is a small perturbation in iL(0). Figure 14.6 shows two inductor current waveforms: one for steady state and the other after small perturbation |ΔiL0| at the beginning of the transistor on-time interval at t = 0. The difference between the steady-state inductor current waveform iLssn and the perturbated inductor current waveform iLpertn is the small-signal component of the inductor current iln = iLssn − ILpertn. The perturbation causes a series of

changes in the small-signal component of the inductor current ΔiLn from the steady-state waveform in successive cycles in the form of an alternating geometric progression, also known as an alternating geometric sequence, whose common ratio is rp = ΔiLn/ΔiL(n − 1) = −D/(1 − D) = −a. Each new term is equal to the previous term multiplied by the common ratio rp = −D/(1 − D), and its magnitude may decrease, remain constant, or increase with time. Since the common ratio is negative (rp < 1), the geometric sequence is alternating, whose terms alternate from negative to positive and from positive to negative.

Figure 14.6 Steady-state and perturbed (transient) waveforms of inductor current in PWM converters with current-mode control in CCM. Initially assume that the input voltage VI and the output voltage VO are constant, i.e., their ac components are zero. Therefore, the slopes of the inductor current waveform M1 = VL ON/L and M2 = VL OFF/L are also constant, where VL ON and VL OFF are the voltages across the inductor during the transistor on-time and off-time intervals, respectively. These slopes are obtained from geometric considerations as

(14.13) and (14.14) where |ΔiL0| is the absolute value (or the magnitude) of the inductor current change at t = 0 and | ΔiL1| is the absolute value of the inductor current change at t = Ts. Using (14.4), (14.13), and (14.14), one obtains the perturbation ratio defined as the ratio of the inductor current change after one cycle |ΔiL1| to the inductor current change at the beginning of the cycle |ΔiL0| (14.15) The perturbation coefficient, defined as the ratio of the inductor current change after n cycles ΔiLn to the initial inductor current change ΔiL0, is given by (14.16) where a = a2/a1 = an/an − 1. Hence, (14.17)

(14.18) and (14.19) It follows from (14.15) that: 1. The inner-current loop is stable if (14.20) which occurs for The condition of stability of the inner-current loop is satisfied for D < 0.5. In this case, |ΔiL1| < |ΔiL0|, the perturbation magnitude |ΔiLn| decays with time to zero as n

(14.21)

approaches infinity, and the converter returns to its initial state. 2. The inner-current loop is marginally stable if (14.22) which occurs for (14.23) This condition is satisfied at D = 0.5, for which |ΔiLn| = |ΔiL0|, that is, the magnitude of oscillations remains constant, and the converter does not return to its initial state. In this case, the geometric progression is a sequence of constant terms equal to 1. 3. The inner-current loop is unstable if (14.24) which occurs for (14.25) The instability condition of the inner-current loop is satisfied for D > 0.5. In this case, |ΔiL1| > |ΔiL0|, the magnitude of oscillations increases with time, and the converter does not return to its initial state. This leads to subharmonic oscillations at half the switching frequency (14.26) Figure 14.7 shows the steady-state and perturbed (transient) inductor current waveforms for a stable inner-current loop (D < 0.5), a marginally stable current loop (D = 0.5), and an unstable current loop (D > 0.5). For D < 0.5, the perturbed inductor current waveform is convergent to the steady-state waveform. Conversely, for D > 0.5, the perturbed inductor current waveform is divergent and does not return to the steady-state waveform. To achieve a sufficient margin of stability, Dmax should be lower than 0.5, for example, Dmax = 0.2. Figure 14.8 shows smallsignal inductor current waveforms il for PWM converters with CMC for a stable current loop (a < 1), for an unstable current loop (a > 1), and for a marginally stable current loop (a = 1). The small-signal inductor current il is equal to the difference between the steady-state inductor current iL and the perturbed inductor current iL(pert), that is, il = iL − iL(pert).

Figure 14.7 Steady-state (solid line) and perturbed (dashed line) waveforms of inductor current iL for PWM converters with current-mode control. (a) For a stable current loop (D < 0.5). (b) For a marginally stable current loop (D = 0.5). (c) For an unstable current loop (D > 0.5).

Figure 14.8 Small-signal inductor current waveforms il for PWM converters with currentmode control. (a) For a stable current loop (D < 0.5). (b) For a marginally stable current loop (D = 0.5). (c) For an unstable current loop (D > 0.5).

14.5 Slope Compensation 14.5.1 Analysis of Slope Compensation in Time Domain The instability of the current loop can be eliminated by subtracting an artificial periodic ramp waveform from the control signal waveform, or by adding an artificial ramp waveform to the inductor or switch current waveform. We will consider a fixed-slope compensation ramp case. Figure 14.9 shows an implementation of slope compensation, using a differential amplifier. Figure 14.10 shows the waveforms illustrating the slope compensation, where an artificial periodic ramp current waveform iA is subtracted from the control current iC; consequently, the slope M2 is reduced, and the switch turns off when

(14.27)

Figure 14.9 Implementation of slope compensation, using a differential amplifier.

Figure 14.10 Steady-state waveforms of the inductor current iL, the control current iC, an artificial ramp current iA, and iC–iA illustrating slope compensation by subtracting a ramp current iA from the control current iC in PWM converters with current-mode control for CCM. Consider the steady-state and perturbed waveforms of the inductor current, depicted in Figure 14.11. The slope of the inductor current waveform iL during the switch on-time interval 0 < t ≤ DTs is (14.28) and the slope of the ramp current iC–iA is (14.29) producing the magnitude of the inductor current perturbation at t = 0

(14.30) The slope of the inductor current waveform iL during the switch off-time interval DTs < t ≤ Ts is (14.31) resulting in the magnitude of the inductor current perturbation at t = Ts (14.32) From (14.30) and (14.32), one obtains the perturbation ratio expressed as the ratio of the absolute values of the inductor current changes at t = Ts and t = 0 (14.33) The current loop with slope compensation is stable if (14.34) which happens when (14.35)

Figure 14.11 Waveforms of the inductor current iL, the control current iC, and iC–iA used to derive the stability condition for the current loop with slope compensation. Substitution of (14.4) into (14.33) produces a in terms of M1, M3, and D (14.36)

The maximum duty cycle Dlim below which the current loop is stable for a given slope ratio M3/M1 is given by (14.37)

As the normalized compensating ramp slope M3/M1 increases, the range of the duty cycle, in

which the inner-current loop is stable, increases above 0.5. For example, for M3/M1 = 0.5, the inner loop is stable for 0 < D < 2/3. From (14.37), (14.38) The condition of stability can be also expressed by [45] (14.39) At the boundary between unstable and stable operation of the inner loop, (14.40) Figure 14.12 shows the plot of M3/M1 as a function of D. As D is increased from 0.5 to 1, M3/M1 increases from 0 to ∞. The minimum value of the compensating slope is (14.41) At Dlim = 0.5, M3min = 0 as expected. As the maximum duty cycle Dlim is increased from 0.5 to 1, M3min increases from 0 to ∞. To achieve relative stability, one should select M3 sufficiently higher than M3min. Example 14.1 A boost converter has the following specifications: 4 V ≤ VI ≤ 6 V, VO = 10 V, and L = 100 μH. Find the required compensation slope to achieve marginal stability. Solution: The worst case occurs at the minimum input voltage at which the duty cycle reaches its maximum value. The maximum duty cycle is (14.42) The maximum perturbation ratio is (14.43) The minimum slope of the rising inductor current is (14.44) Hence, the compensation slope to achieve marginal stability is

(14.45)

Figure 14.12 Plot of M3/M1 as a function of D. Using (14.4), (14.33) can be expressed in terms of the slopes M2 and M3 and the duty cycle D as (14.46)

yielding the condition of stability [45] (14.47) At the boundary between stable and unstable operation of the inner loop,

(14.48) Figure 14.13 shows M3/M2 as a function of D.

Figure 14.13 Plot of M3/M2 as a function of D. As D is increased from 0.5 to 1, the ratio M3/M2 increases from 0 to 0.5. The minimum compensating slope at a maximum duty cycle Dmax is given by (14.49) For the worst case, which occurs at D = 1, (14.46) becomes (14.50) and the condition of stability at any duty cycle D is given by

(14.51) Note that the falling slope M2 approaches infinity as the duty cycle D approaches 1. This requires an infinite value of M3. From (14.46), a = 0, when the compensating slope M3 is equal to the inductor current falling slope M2, resulting in (14.52) as illustrated in Figure 14.14. In this case, the inductor current waveform reaches steady state in exactly one cycle, yielding the fastest possible response of the inner loop. A perturbation ends within the same cycle in which it starts. Operation at M3 = M2 is called dead-beat control. Note that if M3 = 0, then (14.46) reduces to M2/M1 < 1.

Figure 14.14 Elimination of perturbation in the inductor current waveform in closed-inner loop during one cycle at M3 = M2 (dead-beat control).

From (14.36), the slope of the compensation waveform can be expressed in terms of D and a as (14.53)

14.5.2 Boundary of Slope Compensation for Buck and Buck–Boost Converters The maximum value of the inductor current on-slope corresponding to Dmax for the buck and buck–boost converters is (14.54) Hence, the critical value of slope compensation corresponding to the marginally stable converter is (14.55) Figure 14.15 shows a boundary between the stable and unstable regions for the buck and buck– boost converters. The limiting value of the duty cycle for the buck and buck–boost converters is (14.56)

Figure 14.15 Normalized critical slope compensation M3cr/(VO/L) as a function of the maximum duty cycle Dmax for the buck and buck–boost converters. This plot forms a boundary between stable and unstable regions.

14.5.3 Boundary Slope Compensation for Boost Converter The maximum value of the inductor current on-slope corresponding to Dmax for the boost converters is (14.57) Hence, the critical value of slope compensation is (14.58) Figure 14.16 shows a boundary between the stable and unstable regions for the boost

converter. The limiting value of the duty cycle for the boost converter is (14.59)

Figure 14.16 Normalized critical slope compensation M3cr/(VO/L) as a function of the maximum duty cycle Dmax for the boost converter. This plot constitutes a boundary between stable and unstable regions.

14.6 Sample-and-Hold Effect on Current Loop Modeling the current-mode controlled converters involve discrete-time signals and nonlinear, time-varying (NTV) circuits. Operation of the closed-current loop is similar to that of sampleand-hold circuits. “Sampling” the analog, continuous-time control current iC (or control voltage vC) occurs once in a switching cycle Ts at the instant when the inductor current iL reaches the control current iC, turning the switch off and setting the duty cycle for that switching

cycle. Only the control current values at the sampling instants (i.e., sampled-data information) are used to control the inner loop. The changes in the inductor current waveform and the changes in the average values of the inductor current in successive cycles can be described by the zero-order-hold (ZOH) function. The waveforms of the duty cycle and changes in the duty cycle in successive cycles by their nature are “staircase” (or discrete in magnitude) functions and are similar to the waveforms in the ZOH circuit. Therefore, some waveforms in the current loop are discrete-time signals and can be described in the z-domain. Figure 14.17 shows the waveforms in the inner-current loop. A review of sample-and-hold modeling is given in the Appendix to this chapter.

Figure 14.17 Waveforms in the inner-current loop.

14.6.1 Natural Response of Inductor Current to Small Perturbation in Closed-Current Loop The complete response of a system is equal to the sum of the natural response and the forced

response. The natural response, also called initial condition response, zero-input response, or source-free response) is caused by energy stored in a system. The forced response, also called zero-state response, is the particular solution of the differential equation and the natural solution is the homogeneous solution. We will use this principle to derive the control voltage-to-inductor current transfer function of the closed-current loop, which describes how the inductor current il(k) depends on the control voltage vc(k). Figure 14.18(a) shows a natural response of the inductor current in the closed-current loop [31]. The zero-input response is obtained when all the inputs are identically zero. The zeroinput response is zero if all initial conditions are zero. At t = kTs, a small perturbation in the inductor current iL is introduced when the control voltage with slope compensation remains unchanged and other perturbations are zero, that is, vi = 0 and io = 0. This perturbation causes propagation of inductor current changes over subsequent cycles. The sampling occurs at the intersections of waveforms RsiL and vC − vA. The difference between the perturbed (transient) inductor current waveform iLtr and the steady-state inductor current waveform iLss is equal to the exact waveform of the small-signal inductor current il = iLtr − iLss, shown in Figure 14.18(b). The exact waveform of the small-signal inductor current il can be approximated by a continuous-time “staircase” function depicted in Figure 14.18(c), where the finite slope after the sampling instant t = kTs is replaced by an infinite slope. The difference between the exact and approximate waveforms is very small and can be neglected. The instantaneous inductor current changes can be seen as the average inductor current changes. The approximate waveform of the small-signal inductor current il is the same as the ZOH waveform. The time intervals between the sampling instants are not constant, but the differences between them are small enough to be neglected. Figure 14.19 shows an enlarged part of the natural response depicted in Figure 14.18(a). From geometry, (14.60) and (14.61) resulting in the small-signal component of the inductor current at the time of the perturbation t = kTs (14.62) Similarly, (14.63) yielding the small-signal component of the inductor current after one cycle from the beginning

of the perturbation t = (k + 1)Ts (14.64) Thus, (14.65) where (14.66)

Hence, the discrete-time natural response of the approximate small-signal inductor current from one sampling instant to the next is given by (14.67)

Figure 14.18 Natural response (zero-input response or source-free response) of the inductor current in the closed-current loop. The zero-input response is obtained when all the inputs are identically zero. The zero-input response is zero if all initial conditions are zero. Waveforms of the inductor current in the inner-current loop after a small perturbation in the inductor current iL introduced at time t = kTs. (a) Waveforms of steady-state control voltage vC, steadystate normalized inductor current RsiL (solid line), and perturbed (transient) normalized inductor current Rs(iL + il) (dashed line). (b) Exact waveform of the difference between the steady-state and perturbed waveforms, resulting in a small-signal inductor current il. (c) Approximate waveform of the small-signal inductor current il.

Figure 14.19 Enlarged waveforms of natural response depicted in Figure 14.18(a).

14.6.2 Forced Response of Inductor Current to Step Change in Control Voltage in Closed-Current Loop Figure 14.20(a) illustrates a forced response (or zero-state response) of the inductor current to a step change in the control voltage in the closed-current loop [7, 31]. The zero-state response is due to an arbitrary input and it is obtained when all initial conditions are zero, that is, when the initial state is zero. At time t = kTs, there is a step change (a step perturbation) in the control voltage vC from VC to VC + vc, causing a perturbation in the inductor current waveform iL. It is assumed that the converter input voltage VI and the output voltage VO remain constant, which implies that the inductor rising slope M1 and the inductor falling slope M2 also remain constant. The sampling occurs at the intersection of the compensated control voltage waveform vC − vA and the voltage waveform RsiL, proportional to the inductor current iL. Figure 14.21 the enlarged part of the forced response is shown in Figure 14.20(a). From geometry,

(14.68) and (14.69) yielding the step change of the control voltage (14.70) Likewise, (14.71) producing the small-signal component of the inductor current after one cycle at t = (k + 1)Ts (14.72) Hence, (14.73) The discrete-time forced response is given by (14.74)

Figure 14.20 Forced response of the inductor current in the closed-current loop. Waveforms of the control voltage and the inductor current in the inner-current loop after a step change in the control voltage vC from VC to VC + vc at time t = kTs, causing a perturbation of the inductor current iL. (a) Waveforms of control voltage vC = VC + vc, steady-state inductor current RsiL (solid line), and perturbed normalized inductor current Rs(iL + il) (dashed line). (b) Exact waveform of the difference between the steady-state and perturbed waveforms, resulting in a small-signal inductor current il. (c) Approximate waveform of the small-signal inductor current il.

Figure 14.21 Enlarged waveforms of the forced response shown in Figure 14.20(a). The total response is equal to the sum of the natural response and the forced response. The discrete-time relationship between the control voltage and the inductor current is [31] (14.75)

14.6.3 Relationship Between s-Domain and z-Domain The relationship between the s-plane and the z-plane is useful to understand the relationship between continuous and discrete systems. Using s = σ + jω, the z-transform is defined as (14.76)

This equation describes a circle with a radius and ϕ = ωTs = 2πf/fs. For Re {s} = σ = 0, |z| = r = 1, resulting in a unity circle. This circle constitutes the stability boundary, where the close-inner loop is marginally stable. For Re{s} = σ < 0, |z| = r < 1 and the closed-inner loop is stable. For Re {s} = σ > 0, |z| = r > 1 and the closed-inner loop is unstable. For example, the pole of a second-order polynomial of the form s2 + 2ξωns + ω2n = 0 is (14.77) yielding (14.78)

14.6.4 Transfer Function of Closed-Current Loop in z-Domain From the definition of the z-transform, the sampled inductor current in the z-domain is (14.79) From the shifting theorem, (14.80) and (14.81) Hence, the z-transform of (14.75) is (14.82) which gives (14.83) Thus, the discrete-time control voltage-to-inductor current transfer function of the closedcurrent loop is given by (14.84) where p = −a. Figure 14.22 shows the response of the inductor current to the step change in the control voltage ΔVC = vc = 0.1 V at a = 0.7.

Figure 14.22 Step response of the inductor current to a step change in the control voltage ΔVC = vc = 0.1 V at a = 0.7. The transfer function Hicl(z) contains a pole p = −a. The following three locations of the pole are possible: 1. For a < 1, the discrete transfer function Hicl(z) has a pole located inside the unit circle as shown in Figure 14.23(a), and therefore the closed-current loop is stable. 2. For a = 1, the pole is located on the unit circle, as shown in Figure 14.23(b), resulting in the marginally stable current loop and the steady-state oscillations. 3. For a > 1, the discrete transfer function Hicl(z) has a pole located outside the unit circle as shown in Figure 14.23(c), and therefore the closed-current loop is unstable, causing growing oscillations of the inductor current at fs/2, called subharmonic oscillation. This situation takes place, for example, for M1 < M2 at M3 = 0, that is, for D > 0.5 and no ramp compensation.

Figure 14.23 Locations of the pole p = −a of the discrete-time control voltage-to-inductor current transfer function Hicl(z) of the closed-current loop in the complex plane and sequence of samples. (a) For −1 < p < 0, the current loop is stable. (b) For p = −1, the current loop is marginally stable. (b) For − ∞ < p < −1, the current loop is unstable. The margin of stability of discrete systems is determined by the belt margin BM or the ring margin defined as (14.85) where |a| corresponds to the required gain margin GM or the required phase margin PM. The belt margin BM for discrete systems is illustrated in Figure 14.24.

Figure 14.24 Margin of stability of discrete systems.

14.7 Closed-Loop Control Voltage-to-Inductor Current Transfer Function in s-Domain Figure 14.25 shows a block diagram for converting the closed-loop transfer function from the z-domain into the s-domain. The closed-loop discrete-time control voltage-to-inductor current transfer function Hicl(z) in the z-domain can be transformed to a continuous closed-loop control voltage-to-inductor current transfer function Hicl(s) in the s-domain.

Figure 14.25 Block diagram for converting the closed-loop control voltage-to-inductor current transfer function from z-domain into s-domain.

The transfer function of an ideal sampler can be approximated by (14.86) Using the definition of the z-transform (which is the relationship between the z-domain and the sampled-Laplace s-domain), the discrete closed-loop control voltage-to-inductor current transfer function is (14.87) Figures 14.26 and 14.27 show Bode plots of H*icl(s).

Figure 14.26 Magnitude of closed-current loop |H*icl| as a functions of f/fs for a = 0.1712 for a wide frequency range.

Figure 14.27 Phase of closed-current loop Hicl as a functions of f/fs for a = 0.1712 for a wide frequency range. The ZOH transfer function (which is the relationship between the sampled-Laplace domain and the continuous-time domain) is given by (14.88) The closed-current loop transfer function is given by (14.89)

Figures 14.28 and 14.29 show the magnitude and the phase of Hicl for a wide frequency range. Figures 14.30 and 14.31 depict exact and approximate Bode plots of Hicl as functions of f/fs at

a = 0.1712 in linear scale.

Figure 14.28 Exact and approximate plots of the magnitude of closed-current loop Hicl as a functions of f/fs for a = 0.1712 for a wide frequency range, using the second-order Padé and modified Padé approximations.

Figure 14.29 Exact and approximate plots of the phase of closed-current loop Hicl as a functions of f/fs for a = 0.1712 for a wide frequency range, using the second-order Padé and modified Padé approximations.

Figure 14.30 Exact and approximate plots of the magnitude of Hicl as a functions of f/fs for a = 0.1712.

Figure 14.31 Exact and approximate plots of the phase of Hicl as a functions of f/fs for a = 0.1712.

14.7.1 Approximation of Hicl by Rational Transfer Function In PWM converters with peak CMC, the sampling frequency is equal to the switching frequency fs of the power stage. The transfer functions of the inner loop should be described accurately up to the Nyquist frequency fs/2, that is, in the frequency range of 0 ≤ f ≤ fs/2. In order to convert transfer functions from the z-domain to the s-domain, z is replaced by , which leads to transfer functions that are not rational functions. Exact calculations of transfer functions with terms can be made. To obtain rational transfer functions, approximations of are required. A Taylor series approximation of leads to transfer functions with zeroes and no poles, resulting in improper transfer functions. The transfer function is improper if m > n. The transfer function is a strictly proper function if the order of the denominator polynomial n is greater than the order of the numerator polynomial m (i.e., n > m). If n = m, the transfer function is a proper transfer function. To obtain strictly proper transfer functions, Padé approximations can be used.

The transfer function in (14.89) is not a rational function, that is, it is not a ratio of two polynomials. Using the second-order Padé approximation, we obtain (14.90)

Substitution of the second-order approximation of given by (14.90) into (14.89) gives the control voltage-to-inductor current transfer function of the closed-current loop approximated by a rational function [65] (14.91)

where the corner frequency is (14.92) the damping factor is (14.93) the quality factor is (14.94) and the poles are (14.95) Figures 14.32 and 14.33 show exact and approximate Bode plots of Hicl for a = 0.1712, using the second-order Padé and the second-order modified Padé approximations. Figure 14.34 shows ξi as a function of a. As a increases from 0 to 1, ξi decreases from to 0 and Qi increases from to ∞. Figure 14.35 shows the root locus of the closedcurrent-loop transfer function Hicl(s) at fs = 100 kHz when a increases from 0 to 10. For a < 1, a pair of complex conjugate poles is located in the LHP, which indicates that the inner-loop is

stable. For a = 1, a pair of complex conjugate poles is located on the imaginary axis, which indicates that the inner loop is marginally stable. For a > 1, a pair of complex conjugate poles is located in the RHP, which indicates that the inner loop is unstable.

Figure 14.32 Exact and approximate plots of the magnitude of Hicl as a functions of f/fs for a = 0.1712.

Figure 14.33 Exact and approximate plots of the phase of Hicl as a functions of f/fs for a = 0.1712.

Figure 14.34 Damping factor ξi as a function of a.

Figure 14.35 Root locus of the closed-current-loop transfer function Hicl(s) at fs = 100 kHz for variations of a from 0 to 10. Figures 14.36 and 14.37 show Bode plots of Hicl(s) for selected values of a at Rs = 1 Ω. The closed-loop gain of the inner loop Hicl(s) represents a second-order low-pass filter transfer function and depends only on fs, a, and Rs. At s = 0, (14.96) The maximally flat magnitude response of |Hicl| occurs for (14.97) resulting in the critical perturbation ratio, which produces the maximally flat magnitude |Hicl|

(14.98)

For a > 0.1,

and |Hicl| exhibits peaking. For a = 1, |Hicl| approaches ∞ at f ≈ fs/2.

Figure 14.36 Bode plot of the magnitude of Hicl for selected values of a.

Figure 14.37 Bode plot of the phase of Hicl for selected values of a.

14.7.2 Step Responses of Closed-Inner Loop Figures 14.38 through 14.40 show the responses of the inductor current to ΔVc = 0.1 V at a = 0.7, 1, and 1.2, respectively. As expected, the magnitude of the inductor current waveform decays at a = 0.7, has a constant amplitude at a = 1, and increases at a = 1.2. The current loop is stable for a = 0.7, is marginally stable for a = 1, and is unstable for a = 1.2.

Figure 14.38 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 0.7.

Figure 14.39 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 1.

Figure 14.40 Step response of the inductor current iL to a step change in ΔVc = 0.1 V at a = 1.2.

14.8 Loop Gain of Current Loop 14.8.1 Loop Gain of Inner Loop in z-Domain Figure 14.41 shows a block diagram of the inner loop. The closed-loop transfer function in the z-domain is (14.99) resulting the forward-path gain (14.100)

Figure 14.41 Block diagram of the inner loop.

14.8.2 Loop Gain of Inner Loop in s-Domain The closed-loop transfer function in the s-domain is (14.101) resulting in the forward-path gain (14.102) and the loop gain (14.103) The loop gain of the current loop of all converters with peak CMC operating in CCM is (14.104) Bode plots of the loop gain Ti of the inner loop are shown in Figures 14.42 through 14.45.

Figure 14.42 Bode plot of the magnitude of the inner loop gain Ti at a = 0.1712.

Figure 14.43 Bode plot of the phase of the inner loop gain Ti at a = 0.1712.

Figure 14.44 Enlarged Bode plot of the magnitude of the inner loop gain Ti at a = 0.1712.

Figure 14.45 Enlarged Bode plot of the phase of the inner loop gain at a = 0.1712. Substituting (14.91) into (14.103), we obtain the loop gain of the inner loop in the form of rational transfer function for all PWM converters operating in CCM (14.105)

where (14.106) (14.107)

and (14.108) The loop gain Ti is converter independent. For a = 0, psh = −6 fs. For a = 1, psh = 0. For a > 1, psh is located in the RHP. Figures 14.46 and 14.47 show Bode plots of the loop gain of inner loop Ti.

Figure 14.46 Bode plot of the magnitude of the current-loop gain Ti for selected values of a.

Figure 14.47 Bode plot of the phase of the current-loop gain Ti for selected values of a. The loop gain of the inner loop is independent of converter topology; it depends only on the switching frequency fs and a. One pole of Ti is located at the origin, and therefore the currentloop gain Ti behaves like the transfer function of an integrator. The location of the second pole psh = −ωsh is dependent on a. The second pole is located in the LHP, and the current loop is stable. For a = 1, the second pole is located at the origin and the current loop is marginally stable. For a > 1, the second pole is located in the RHP, and therefore the current loop is unstable. For a = 0, f1 = fs/π. For a = 0.1712, f1 = 0.45 fs. For a = 0.5, f1 = (3/π)fs = 0.955 fs. For a = 0, fsh = 3fs/π = 0.955 fs. For a = 0.1712, fsh = 0.676 fs. For a = 0.5, fsh = 0.318 fs. For s = jω, the loop gain of the inner loop becomes (14.109) where

(14.110)

and (14.111)

In the last equation, the trigonometric identity is used (14.112) Figure 14.48 shows Nyquist plots of the loop gain of current loop Ti(jω) at fs = 100 kHz for selected values of a. It can be seen that the gain margin GM = ∞ at any value of a because the Nyquist plots never cross the negative part of the real axis Re{Ti(jω)}. As a increases from 0 to 1, the phase margin PM decreases from 72° to 0°. For a > 1, the phase margin PM is negative.

Figure 14.48 Nyquist plot of the loop gain of current loop Ti(jω) at fs = 100 kHz for selected values of a.

14.9 Gain-Crossover Frequency of Inner Loop At the gain-crossover frequency fci, the magnitude of the current-loop gain becomes (14.113)

Hence, the normalized crossover frequency of the current loop is

(14.114)

Figure 14.49 shows a plot of fci/fs as a function of a. For a = 0, fci/fs =

=

0.3034. For a = 1, . The ratio of fci/fs at a = 1 is higher than 0.5, which was predicted in the time-domain analysis. This difference is caused by the second-order Padé approximation of .

Figure 14.49 Plot of fci/fs as a function of a.

14.10 Phase Margin of Inner Loop The phase ϕTi at the gain-crossover frequency fci is

(14.115)

The phase margin of the current loop is given by (14.116)

Hence, (14.117)

Rearrangement of this equation gives the relationship between a and the phase margin PM (14.118) For PM = 45°, the perturbation ratio is (14.119) For PM = 60°, the perturbation ratio is (14.120) Figure 14.50 shows a plot of a as a function of PM. Once a is known for a given value of PM, the required amount of slope compensation can be calculated. Figure 14.51 shows the locations of the pole and belt margins BM for the phase margins PM = 45° and PM = 60°.

Figure 14.50 Perturbation ratio a as a function of phase margin PM for the inner-current loop.

Figure 14.51 Belt margins at the phase margins PM = 0, PM = 45°, and PM = 60°. The crossover frequency fci normalized with respect to the switching frequency fs as a function of the phase margin PM is given by (14.121)

For the phase margin PM = 45°, (14.122) For the phase margin PM = 60°,

(14.123) Figure 14.52 shows a plot of fci/fs as a function of PM. Figure 14.52 shows a plot of fci/fs as a function of phase margin PM for the current loop.

Figure 14.52 Normalized crossover frequency fci/fs a function of phase margin PM for the current loop.

14.11 Maximum Duty Cycle for Converters Without Slope Compensation For PWM converters without slope compensation (M3 = 0), a = D/(1 − D) and the maximum duty cycle for a given phase margin PM is (14.124)

Figure 14.53 shows a plot of Dmax as a function of a. As a decreases from 1 to 0, Dmax decreases from 0.5 to 0. The maximum duty cycle Dmax as a function of the phase margin PM is shown in Figure 14.54. As PM increases from 0 to 72.5°, the maximum duty cycle Dmax decreases from 0.5 to 0. For PM = 45°, (14.125) For PM = 60°, (14.126) Thus, PWM converters without slope compensation may have sufficient degree of relative stability only at low values of duty cycle.

Figure 14.53 The maximum duty cycle Dmax as a function of a without slope compensation.

Figure 14.54 The maximum duty cycle Dmax as a function of phase margin PM without slope compensation.

14.12 Maximum Duty Cycle for Converters with Slope Compensation Using (14.36), the normalized slope compensation is given by (14.127) The minimum compensation slope occurs at the minimum on-slope of the inductor current and is given by (14.128)

The maximum duty cycle is (14.129)

For a = 1, we obtain the duty cycle for the marginally stable converters (14.130)

Figure 14.55 shows Dmax as a function of a at fixed values of M3/M1. Plots of the maximum duty cycle Dmax as a function of M3/M1 at selected values of a are depicted in Figure 14.56.

Figure 14.55 The maximum duty cycle Dmax as a function of a at selected values of M3/M1.

Figure 14.56 The maximum duty cycle Dmax as a function of M3/M1 at selected values of a. Substitution of (14.118) into (14.129) produces (14.131)

Figure 14.57 shows plots of Dmax as a function of relative compensation M3/M1 at fixed values of phase margin PM. Plots of Dmax as a function of PM at fixed values of M3/M1 are shown in Figure 14.58.

Figure 14.57 The maximum duty cycle Dmax as a function of M3/M1 at selected values of phase margin PM.

Figure 14.58 The maximum duty cycle Dmax as a function of PM at selected values of M3/M1. From (14.131), one obtains the normalized slope compensation required for achieving the required phase margin at a given maximum duty cycle Dmax (14.132)

The first term in this equation represents the required amount of slope compensation to achieve the marginal stability at a given Dmax and the second term represents the amount of slope compensation for achieving the required phase margin PM at a fixed value of Dmax. For PM = 45°, (14.133)

For PM = 60°, (14.134) Figure 14.59 shows plots of the required amount of compensation M3/M1 as a function of Dmax at selected values of phase margin PM.

Figure 14.59 The required slope compensation M3/M1 as a function of the maximum duty cycle Dmax at selected values of phase margin PM. The normalized crossover frequency fci/fs as a function of the normalized slope compensation M3/M1 is given by

(14.135)

Figure 14.60 shows plots of fci/fs as a function of M3/M1 at fixed values of the maximum duty cycle Dmax.

Figure 14.60 Normalized crossover frequency fci/fs as a function of the normalized slope compensation M3/M1 at selected values of the maximum duty cycle Dmax.

14.13 Minimum Slope Compensation for Buck and Buck–Boost Converter The dc voltage transfer function of the buck converter is

(14.136) The rising slope of the inductor current for the buck converter is (14.137) Substitution of this equation into (14.132) yields the minimum slope compensation for the buck converter at a given phase margin PM of the inner loop (14.138) The dc voltage transfer function of the buck–boost converter is (14.139) The rising slope of the inductor current for the buck–boost converter is (14.140) which is the same as for the buck converter. Figure 14.61 shows plots of M3min/(VO/L) as a function of Dmax for the buck and boost converters. Example 14.2 A buck converter has the following specifications: 16 V ≤ VI ≤ 24 V, VO = 10 V, 0.14 A ≤ IO ≤ 1.4 A, and fs = 100 kHz. The required phase margin is PM ≥ 60°. Calculate the compensation slope. Solution: The minimum, nominal, and maximum values of the duty cycle are (14.141) (14.142) and (14.143) The maximum load resistance is (14.144)

The inductance required for CCM operation for the buck converter is (14.145) Pick a standard inductance L = 220 μH. The on-slope of the inductor current at VImin = 16 V, that is, at Dmax = 0.625, is given by (14.146) The minimum normalized compensation slope to obtain PM = 0 at Dmax = 0.625 is (14.147) Hence, the compensation slope to achieve PM = 0 at Dmax = 0.625 is (14.148) The normalized compensation slope to obtain PM = 60° at Dmax = 0.625 is (14.149)

The slope of the compensating ramp current is (14.150) The amplitude of the control current ramp is (14.151) Assuming Rs = 1 Ω, the amplitude of the control voltage ramp is (14.152)

Figure 14.61 Normalized slope compensation M3min/(VO/L) as a function of the maximum duty cycle Dmax at selected values of the phase margin PM for the buck and buck–boost converters.

14.14 Minimum Slope Compensation for Boost Converter The dc voltage transfer function of the boost converter is (14.153) The rising slope of the inductor current for the boost converter is (14.154) Substitution of (14.154) into (14.132) produces the minimum slope compensation for the boost

converter at a given phase margin PM of the inner loop (14.155) Figure 14.62 shows plots of M3min/(VO/L) as a function of Dmax for the boost converter. Example 14.3 A boost converter has the following specifications: 100 V ≤ VI ≤ 200 V, VO = 400 V, 0.1 A ≤ IO ≤ 0.225 A, and fs = 100 kHz. The required phase margin is PM ≥ 60°. Calculate the compensation slope. Solution: The minimum, nominal, and maximum values of the duty cycle are (14.156) (14.157) and (14.158) The maximum load resistance is (14.159) The minimum inductance for CCM operation is (14.160) Pick a standard inductance L = 2.7 mH. The on-slope of the inductor current at VImin = 100 V, that is, at Dmax = 0.75, is given by (14.161) The minimum normalized compensation slope to obtain PM = 0 at Dmax = 0.75 is (14.162) Hence, the compensation slope to achieve PM = 0 at Dmax is

(14.163) The normalized compensation slope to obtain PM = 60° at Dmax = 0.75 is (14.164)

The slope of the compensating ramp current is (14.165) The amplitude of the ramp current is (14.166) Assuming Rs = 1 Ω, the compensating voltage ramp is (14.167) Example 14.4 A buck–boost converter has the following specifications: 20 V ≤ VI ≤ 36 V, VO = 28 V, 1 A ≤ IO ≤ 2 A, and fs = 100 kHz. The required phase margin is PM ≥ 60°. Find the compensation slope. Solution: The minimum, nominal, and maximum values of the duty cycle are (14.168) (14.169) and (14.170) The maximum load resistance is (14.171) The minimum inductance required for CCM operation of the buck–boost converter is (14.172)

Pick L = 51 μH. The on-slope of the inductor current at VImin = 20 V, that is, at Dmax = 0.5833, is given by (14.173) The minimum normalized compensation slope to obtain PM = 0 is (14.174) Hence, the compensation slope to achieve PM = 0 at Dmax is (14.175) The normalized compensation slope to obtain PM = 60° at Dmax = 0.5833 is (14.176)

The slope of the compensating ramp current is (14.177) The amplitude of the control ramp current is (14.178) Assuming Rs = 1 Ω, the amplitude of the control ramp voltage is (14.179)

Figure 14.62 Normalized slope compensation M3min/(VO/L) as a function of the maximum duty cycle Dmax at selected values of the phase margin PM for the boost converter.

14.15 Error Voltage-to-Duty Cycle Transfer Function Figure 14.63 shows a block diagram of the closed-current loop with the inductor current il as an output. This loop will be used to find the error voltage-to-duty cycle transfer function Tms. Figure 14.64 shows a block diagram of the closed-current loop with the duty cycle d as an output. The duty cycle drives the duty cycle-to-output voltage transfer function Tp in the voltage loop. The control voltage-to-inductor current transfer function of the closed-current loop can be expressed by [65] (14.180) where the duty cycle-to-inductor current transfer function of the converter power stage is

(14.181) Equating the right-hand sides of (14.89) and (14.180), (14.182) yields the sample-and-hold error voltage-to-duty cycle transfer function [65] (14.183)

Using the second-order Padé approximation given by (14.90), one obtains [65] (14.184)

where (14.185) and (14.186) The sample-and-hold error voltage-to-duty cycle transfer can be also determined using the loop gain Ti (14.187)

Thus, the transfer function Tms is converter-dependent because it depends on Tpi. As a increases from 0 to 1, fsh decreases from 3fs/π to 0.

Figure 14.63 Block diagram of the closed-current loop showing the transfer function from the control voltage-to-the inductor current il, used for determining Tms = d/vei. No disturbances are present, that is, vi = 0 and io = 0. (a) Without slope compensation. (b) With slope compensation.

Figure 14.64 Block diagram of the closed-current loop showing the transfer function from control voltage to the duty cycle d, as in actual converters. The disturbances are zero (i.e., vi = 0 and io = 0.) (a) Without slope compensation. (b) With slope compensation. Using the relationship, (14.188) and the substitution

, we obtain (14.189)

For high frequencies, (14.190)

and (14.191) The transfer function Tms can be converted into the z-domain as (14.192) The waveforms of the response to a step change in the duty cycle from 0.55 to 0.65 using a continuous function d(t) and and discrete-time function d0(t) are illustrated in Figure 14.65.

Figure 14.65 Waveforms of d(t) and d0(t) as responses to a step change in the duty cycle from 0.55 to 0.65. It will be shown in the subsequent chapters that the duty cycle-to-inductor current transfer function Tpi for simple transformerless PWM converters, such as buck, boost, and buck–boost converters, is expressed by the equation of the same form

(14.193) For different converters, parameters Tpix, ωzi1, ξ, and ω0 are described by different equations. The error voltage-to-duty cycle transfer function, which is equal to the forward gain of the current loop, is given by [65] (14.194)

where (14.195) Figures 14.66 and 14.67 show Bode plots of Tms at various values of a.

Figure 14.66 Bode plot of the magnitude of the error voltage-to-duty cycle transfer function Tms for selected values of a.

Figure 14.67 Bode plot of the phase of the error voltage-to-duty cycle transfer function Tms for selected values of a. The loop gain of the current loop is (14.196)

Substitution of (14.193) into (14.184) yields the normalized sample-and-hold transfer function for any basic converter (14.197) where Tm = fs/(M1 + M3).

14.16 Closed-Loop Control Voltage-to-Duty Cycle Transfer Function of Current Loop Figure 14.64 shows a block diagram of the closed-current loop with the duty cycle as an output, as it is the case in actual converters. Using (14.196), the control voltage-to-duty cycle transfer function of the closed-current loop is (14.198) Substitution of (14.184) into this equation yields (14.199)

where (14.200) The two poles of Ticl are (14.201) The closed-current loop transfer function depends on converter topology, slope compensation, and sampling-and-hold effect. Figures 14.68 and 14.69 show Bode plots of Ticl over a wide frequency range for a = 0.1712. Figures 14.70 and 14.71 show these same plots over a narrow frequency range. Figures 14.72 and 14.73 show Bode plots for the closed-current loop Ticl at selected values of a for a buck–boost converter as an example. It can be seen that the magnitude of Ticl exhibits peaking at fs/2 for a = 0.5 and 0.9. For a = 1, |Ticl| approaches infinity at f = fs/2. For a > 1, Ticl has two poles in the RHP, making the current loop unstable. The phase ϕTicl has positive values close to 90° at high frequencies, and therefore the closedcurrent loop acts like a partial lead compensator for the outer voltage loop, helping to offset the negative phase of Tp introduced, for example, by the RHP zero for the boost and buck– boost converters, which are non-minimal phase circuits. Alternatively, the positive phase ϕTicl of the closed-current loop may partially offset the negative phase introduced by the poles in all converters, for example, a buck converter.

Figure 14.68 Bode plot of the magnitude of the closed-current loop Ticl(s) for the buck PWM converter at 0.1712.

Figure 14.69 Bode plot of the phase of the closed-current loop Ticl(s) for the buck PWM converter at a = 0.1712.

Figure 14.70 Bode plot of the magnitude of the closed-current loop Ticl(s) for the buck converter at a = 0.1712.

Figure 14.71 Bode plot of the phase of the closed-current loop Ticl(s) for the buck converter at a = 0.1712.

Figure 14.72 Bode plot of the magnitude of the closed-current loop Ticl(s) for selected values of a.

Figure 14.73 Bode plot of the phase of the closed-current loop Ticl(s) for selected values of a.

14.17 Alternative Representation of Current Loop An alternative method of representation of current loop is shown in Figure 14.74. The closedloop transfer function of the current loop is (14.202)

Figure 14.74 Block diagram for the alternative representation of Ticl.

14.18 Current Loop with Disturbances Figure 14.75 depicts a block diagram of the current loop with disturbances by the input voltage vi and the load current io. Figure 14.76 shows block diagram for determining the transfer function from the input voltage to the duty cycle for the closed-current loop. The inductor current is given by (14.203) and the duty cycle is (14.204) resulting in (14.205) Hence, the input voltage-to-duty cycle transfer function is (14.206)

Figure 14.75 Block diagram of current loop with disturbances.

Figure 14.76 Block diagram for determining the input voltage-to-duty cycle transfer function Mvd for the closed-current loop. Figure 14.77 shows a block diagram for determining the transfer function from the load current to the duty cycle for the closed-current loop. From this block diagram, we obtain the inductor current (14.207) and the duty cycle (14.208) yielding

(14.209) Hence, we obtain the load current-to-duty cycle transfer function (14.210)

Figure 14.77 Block diagram for determining the load-current-to-duty cycle transfer function Aid for the closed-current loop.

14.18.1 Modified Approximation of Current Loop A modified Padé approximation [31] can be obtained by placing the corner frequency fh at half the switching frequency fs, yielding (14.211)

Hence, (14.89) becomes (14.212)

where (14.213) (14.214)

(14.215) and (14.216) Substitution of (14.211) into (14.183) gives the normalized sample-and-hold transfer function (14.217)

where (14.218) The normalized sample-and-hold transfer function for any converter is obtained as (14.219) The error voltage-to-duty cycle transfer function of the current loop is (14.220) The loop gain of the current loop is given by (14.221)

The magnitude of the current-loop gain is (14.222)

At the crossover frequency fcim, the magnitude of the current-loop gain becomes (14.223)

Thus, the normalized crossover frequency of the current loop is (14.224)

For a = 1, fcim/fs = 1/2, the current loop is unstable, and it oscillates at half of the switching frequency, as predicted in the time domain. Figure 14.78 shows plots of fci/fs and fcim/fs. As a increases from 0 to 1, fcim/fs increases from 0.3 to 0.5.

Figure 14.78 Crossover frequencies fci/fs and fcim/fs as functions of a. The phase of the current-loop gain is (14.225)

The phase ϕTi at the crossover frequency fcim is (14.226)

The phase margin of the current loop is defined as (14.227) Thus, (14.228) yielding the relationship between a and PM (14.229)

Figure 14.79 shows a as a function of PM for the Padé approximation and for modified approximation. The location of the pole is shown in Figure 14.80 for PM = 45° and PM = 60°. The maximum duty cycle Dmax as a function of the relative slope compensation M3/M1 at a given phase margin PM is (14.230)

Figure 14.81 shows plots of Dmax as a function of M3/M1 at selected values of the phase margin PM. The required normalized slope compensation M3/M1 for achieving a given maximum duty cycle Dmax at a desired phase margin PM is (14.231) Figure 14.82 shows plots of M3/M1 as a function of Dmax at selected values of phase margin PM.

Figure 14.79 a as a function of phase margin PM for the Padé approximation and for modified approximation.

Figure 14.80 Location of the pole for phase margin PM = 0, PM = 45°, and PM = 60° using the Padé approximation.

Figure 14.81 Maximum duty cycle Dmax as a function M3/M1 at selected values of phase margin PM.

Figure 14.82 M3/M1 as a function of maximum duty cycle Dmax at selected values of phase margin PM. The normalized slope compensation required for achieving a sufficient phase margin PM at a given maximum duty cycle Dmax is (14.232)

The first term represents the required compensation to achieve the marginal stability at a desired maximum duty cycle Dmax and the second term represents the required slope compensation to achieve the desired phase margin PM at a given maximum duty cycle Dmax. The normalized crossover frequency fcim/fc as a function of the slope compensation M3/M1 is given by

(14.233)

The control voltage-to-duty cycle transfer function of the closed-current loop is given by (14.234)

14.19 Voltage Loop of PWM Converters with CurrentMode Control 14.19.1 Control-to-Output Transfer Function for Buck Converter Block diagrams for determining the control-to-output transfer function of the buck converter are shown in Figure 14.83. In general, the output signal of the closed-current loop is il. In the buck converter, the inductor current flows into the output circuit C–rC–RL. The impedance of the output filter of the buck converter is (14.235)

where (14.236) and (14.237) The control-to-output transfer function for the buck converter is (14.238) where (14.239)

(14.240) and (14.241)

Figure 14.83 Block diagram for determining the control-to-output transfer function Tco for the buck converter. (a) Block diagram. (b) Simplified block diagram. At low frequencies, (14.242) Figures 14.84 and 14.85 show plots of the magnitude and phase of the control-to-output transfer function for the buck converter with D = 0.5, L = 256 μH, rL = 36 mΩ, C = 68 μF, rC = 0.52 mΩ, RL = 10 Ω, and r = 0.286 mΩ at selected values of perturbation ratio a.

Figure 14.84 Magnitude of the control-to-output transfer function Tco for the buck converter.

Figure 14.85 Phase of the control-to-output transfer function Tco for the buck converter.

14.19.2 Block Diagram of Power Stages of PWM Converters Figure 14.86 shows a block diagram of open-loop PWM converters. Figure 14.87 shows a block diagram of PWM converters with CMC without feedforward gains, where il is the smallsignal component of the average inductor current, Tpi = il/d is the open-loop duty cycle-toinductor current transfer function, Mvi = il/vi is the open-loop input voltage-to-inductor current transfer function, Tp = vo/d is the open-loop duty cycle-to-output voltage transfer function, and Mv = vo/vi is the open-loop input voltage-to-output voltage transfer function.

Figure 14.86 Block diagram of the power stage of PWM converters.

Figure 14.87 Current-mode control block diagram of PWM converters without feedforward gains. Figure 14.87 shows a block diagram of PWM converters with CMC without feedforward gains, where Tc = vc/ve is the voltage transfer function of the control circuit. Figure 14.88 depicts a block diagram of PWM converters with peak CMC for the critical paths only without disturbances, that is, for vi and io = 0, where the peak inductor current is controlled along with the output voltage. The current loop Ti controls the peak inductor current and the voltage loop T controls the output voltage.

Figure 14.88 Block diagram for the critical path of closed-loop PWM converters with currentmode control at vi = 0 and io = 0.

14.19.3 Closed-Voltage Loop Transfer Function of PWM Converters with Current-Mode Control The closed-loop transfer function from the reference voltage vr to the output voltage vo is (14.243)

14.19.4 Closed-Loop Audio Susceptibility of PWM Converters with Current-Mode Control Figure 14.89 shows a block diagram for determining the closed-loop audio susceptibility, which can be obtained by setting vr = 0 and io = 0. The derivation of this transfer function is as follows: (14.244) (14.245) (14.246) (14.247) (14.248)

(14.249) (14.250) (14.251) (14.252) (14.253) (14.254)

(14.255)

(14.256) (14.257)

(14.258) (14.259) (14.260) where (14.261) Finally, the closed-loop audio susceptibility is given by (14.262)

Figure 14.89 Block diagram of PWM converters with current-mode control for determining the closed-loop audio susceptibility. The derivation of an expression for the audio susceptibility for the inner loop only with the outer loop open and vc = 0 is as follows: (14.263) (14.264) (14.265) (14.266)

(14.267)

(14.268) (14.269)

(14.270)

14.19.5 Closed-Loop Output Impedance of PWM Converters with Current-Mode Control Figure 14.90 shows a block diagram for determining the closed-loop output impedance, obtained by setting vr = 0 and vi = 0. The derivation of this impedance is as follows: (14.271) (14.272) (14.273) (14.274) (14.275) (14.276) (14.277) (14.278) (14.279) (14.280) (14.281)

(14.282)

(14.283) (14.284)

(14.285) Finally, the closed-loop output impedance is (14.286)

Figure 14.90 Block diagram of PWM converters with current-mode control for determining the closed-loop output impedance.

14.20 Feedforward Gains in PWM Converters with Current-Mode Control without Slope Compensation The preceding analysis was performed under the assumption of fixed converter input voltage VI and output voltage VO. Let us relax this assumption and consider the case for which the input and output voltages consist of dc and small-signal ac components: vI = VI + vi and vO = VO + vo. The slopes of the inductor current waveform depend on the input and/or output voltages. We will also assume that the duty cycle D is lower than 0.5 so that the inner loop is stable. When the input and output voltages contain small-signal ac components, the slopes also contain dc and small-signal components: mT1 = M1 + m1 and mT2 = M2 + m2. Figure 14.91 shows the waveforms in PWM converters with CMC and without slope compensation, where the control voltage VC is held constant and the slope of the rising inductor current waveform is increased by a small change m1 from the steady-state value M1 to M1 + m1. This causes the duty cycle to decrease from D to dT = D + d, where d < 0. The slopes of the rising inductor current waveforms before and after perturbation are (14.287) and (14.288)

These two equations produce (14.289) from which (14.290) If m1d M1d and m1d Dm1, that is, if the small-signality conditions m1 M1 and d D are satisfied, the product of the small-signal components m1d can be neglected. Hence, one obtains a general and a linear relationship between m1 and d given by [45] (14.291)

Figure 14.91 Waveforms of the inductor current with steady-state slope M1 and with perturbed slope M1 + m1 at fixed control voltage VC in PWM converter with current-mode control and without slope compensation. (a) Waveforms of the inductor and control currents. (b) Waveform of the gate-to-source voltage. For the buck converter, (14.292) where (14.293) and M1 is given by (14.7). As a result, (14.291) becomes [45]

(14.294) Using D = VO/VI, the input feedforward gain is given by (14.295) and the output feedforward gain is given by (14.296) yielding (14.297) For the boost and buck–boost converters, (14.298) where (14.299) and M1 is given by (14.9). Thus, from (14.291), (14.300) where the input feedforward gain is (14.301) and the output feedforward gain is Ko = 0. For the boost converter, VI = (1 − D)VO and (14.301) becomes (14.302) For the buck–boost converter, VI = VO(1 − D)/D and (14.301) becomes

(14.303) Figure 14.92 shows a block diagram of the current-mode pulse-width modulator, in which the feedforward gains Ki and Ko are included. A block diagram of the current loop with feedforward gains and disturbances is shown in Figure 14.93.

Figure 14.92 Block diagram of the current modulator that includes feedforward gains.

Figure 14.93 Block diagram of current loop with disturbances and feedforward gains.

14.21 Feedforward Gains in PWM Converters with Current-Mode Control and Slope Compensation Figure 14.94 shows the waveforms in PWM converters with CMC and with slope compensation, where the control voltage VC is held constant, the slope of the voltage VC − vA remains constant, and the slope of the rising inductor current waveform is increased by a small change m1 from the steady-state value M1 to M1 + m1. Note that (D + d)Ts < DTs; therefore, dTs < 0. The slopes of the rising inductor current waveforms are (14.304)

(14.305) and the slope of the compensating ramp voltage vC–vA is (14.306)

Hence, (14.307) which simplifies to the form (14.308) If the small-signality conditions m1 M1 and d D are satisfied, the product of the smallsignal components m1d can be neglected. Hence, one obtains [45] (14.309)

Figure 14.94 Waveforms of the inductor current with steady-state slope M1 and with perturbed slope M1 + m1 for fixed control voltage VC and compensating slope M3 in PWM converter with current-mode control and with slope compensation.

Substitution of (14.7) and (14.293) into (14.309) produces d for the buck converter (14.310)

where the input feedforward gain is given by (14.311)

and the output feedforward gain is given by (14.312)

Using (14.9), (14.299), and (14.309), one arrives at d for the boost and buck–boost converters (14.313) where the input feedforward gain is (14.314)

and the output feedforward gain is Ko = 0. For the boost converter, VI = (1 − D)VO and (14.314) becomes (14.315) For the buck–boost converter, VI = VO(1 − D)/D and (14.314) becomes (14.316)

Figure 14.95 shows a control block diagram of a PWM converter with CMC, in which feedforward gains Ki and Ko are included.

Figure 14.95 Control block diagram of a PWM converter with current-mode control, where the feedforward gains are included.

14.22 Control-to-Output Voltage Transfer Function of Inner Loop with Feedforward Gains The inductor current with vi = 0 is given by (14.317) The output voltage is (14.318) resulting in (14.319) Hence, the control-to-output voltage transfer function of the inner loop is

(14.320)

14.23 Audio-Susceptibility of Inner Loop with Feedforward Gains The derivation of the audio-susceptibility is as follows: (14.321) (14.322) (14.323) (14.324)

(14.325) (14.326) (14.327)

(14.328) (14.329) (14.330)

(14.331)

(14.332)

For the boost converter, Ko = 0, and therefore

(14.333)

14.24 Closed-Loop Transfer Functions with Feedforward Gains The loop gains are: TcTmsTpβ, TmsTpiRs, and KoTp. For the buck converter, the closed-loop transfer functions with feedforward gains are (14.334)

(14.335) and (14.336) Since |KoTp| | Ti|, KoTp in the denominator of the above equations can be neglected. For the boost and buck–boost converters, Ko = 0 and the transfer functions with feedforward gains are (14.337)

(14.338)

and (14.339) Thus, only Mvcl is affected by the feedforward gains for the boost and buck–boost converters.

14.25 Slope Compensation by Adding a Ramp to Inductor Current Waveform

Slope compensation can also be accomplished by adding an external periodic ramp current waveform to the inductor current waveform, as shown in Figure 14.96. It can be seen that both slopes of the waveform iL + iA are changed. Figure 14.96 shows steady-state and perturbed waveforms of iL + iA in PWM converters with slope compensation obtained by adding a ramp to the inductor current. The slopes of the waveform iL + iA are (14.340) and (14.341) resulting in the current gain (14.342) This equation is the same as that in (14.33).

Figure 14.96 Slope compensation by adding an external periodic ramp current iA to the inductor current waveform iL.

14.26 Relationships for Constant-Frequency CurrentMode On-Time Control A similar analysis reveals that, in constant-frequency current-mode scheme, where the clock initiates the switch on-time, and the control and inductor current intersection initiates the switch-off time, the following relation holds true for the circuit without a slope compensation (14.343) In this case, the inner-current loop is stable for D > 0.5 and is unstable for D < 0.5. If slope compensation is used,

(14.344) and (14.345)

14.27 Summary PWM converters with CMC are nonlinear, time-varying circuits. Modeling the current-mode-controlled converters involves discrete-time signals. CMC scheme contains two loops: a inner-current loop and a voltage outer loop. In CMC architecture, the peak inductor current is controlled along with the output voltage. In CMC, the peak inductor current and the peak switch current are equal to the instantaneous control current iC. In CMC, the control decision is made in each cycle when the inductor or switch current becomes equal to the control current. PWM converters with CMC have inherently short-circuit protection and over-current protection. Since the peak and average current of the inductor is proportional to the control voltage, the output current can be limited by clamping the control voltage. Since the inductor current is controlled by sensing the peak current in the power switch or the inductor, the current can be limited on a cycle-by-cycle basis, resulting in a fast response of the current loop. The inner-current loop is unstable for D > 0.5 for CCM. The instability of the current loop does not occur for DCM. Slope compensation may be used to achieve stability of the inner-current loop. One method of slope compensation is to subtract a ramp voltage from the control voltage. Another method is to add a ramp to the sensed inductor or switch current. As the compensating ramp slope M3 increases, the range of the duty cycle, in which the inner loop is stable, is increased above 0.5. The inner-current loop is stable at any duty cycle D for M3 > 0.5M2. The inner-current loop recovers from a perturbation within one cycle if M3 = M2 (i.e., for dead-beat control). CMC offers several advantages, such as the ease of compensation of the voltage loop, fast dynamic response, inherent line feedforward, low audio susceptibility, good line regulation, automatic overload and short-circuit protection, and easy paralleling of

multiple converters. The continuous-time domain transfer function H*(s) can be obtained from the discrete-time domain transfer function H(z) using the equation: (14.346) As a increases from 0 to 1, fci/fs increases from 0.3 to 0.5. The current loop is wide band with the crossover frequency fci ≈ 0.4fs at PM ≈ 60°. The current loop acts like a partial lead compensator for the voltage loop. Due to sensing the instantaneous inductor current or switch current, the peak CMC scheme is susceptible to noise, especially when the inductor current ripple is low or when the duty cycle is low. VMC is more immune to noise than CMC. The constant-off time CMC has many advantages. CMC can be used in constant-current dc–dc converters. The unity-gain frequency of PWM converters with peak CMC is about three to four times higher than that with VMC.

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Review Questions 1. What is the basic topology of a current-mode control system? 2. Explain the principle of operation of current-mode control. 3. What event turns the transistor on in PWM converters with current-mode control? 4. What event turns the transistor off in PWM converters with current-mode control? 5. How many loops are in the current-mode control scheme? 6. What are the advantages of current-mode control? 7. When is the current loop without slope compensation stable? 8. Explain the principle of slope compensation. 9. When is the current loop with slope compensation stable? 10. What amount of slope compensation will guarantee stability of the current loop under any conditions? 11. What amount of slope compensation will guarantee optimum compensation of the current loop? 12. What is the oscillation frequency of the unstable current loop? 13. Is the peak current-mode control susceptible to noise?

Problems 1. A lossless buck converter with constant-frequency peak CMC and without slope compensation has VO = 5 V. What is the range of the input voltage VI, in which the inner

loop is stable? 2. A lossy buck converter with constant-frequency peak CMC and without slope compensation has VO = 5 V and the efficiency η = 0.9. What is the range of the input voltage VI, in which the converter is stable? 3. A lossy buck converter with constant-frequency peak CMC and without slope compensation has VI = 28 V, VO = 5 V, L = 301 μH, the switching frequency fs = 100 kHz, and the efficiency η = 0.9. Does the converter require slope compensation? 4. A buck converter with constant-frequency peak CMC has VI = 28 ± 4 V, VO = 20 V, L = 301 μH, fs = 100 kHz, and the efficiency η = 1. Is the converter stable? Is slope compensation required in this converter? 5. A buck converter with constant-frequency peak CMC has VInom = 28 V, VO = 20 V, L = 301 μH, fs = 100 kHz, and the efficiency η = 1. Find the ramp slope for the optimum compensation and the peak compensating voltage. 6. A buck–boost converter with constant-frequency peak CMC has VInom = 42 V, VO = −28 V, L = 334 μH, fs = 100 kHz, and the efficiency η = 0.85. Find M3nom and the peak value of the compensation ramp slope at which a = 0.3. 7. A PWM converter with constant-frequency peak CMC has Rs = 0.1 Ω, a = 0.3, and fs = 100 kHz. Find Hicl(z), Hicl(s), and Ti(s). 8. A buck–boost converter has D = 0.407, VI = 48 V, VO = −28 V, M1 = 0.144 A/s, M3 = 0.0986 A/s, and ΔVI = 1 V. Find Ki and ΔD. Assuming that the voltage loop is open and the feedforward voltage is the only change in the circuit, calculate the output voltage VO. 9. A boost converter has the following specs: VI = 1.5 ± 0.5 V, VO = 5 V, IO = 0.2 to 4 A, and fs = 250 kHz. Find Dmax, a, and M3min to achieve PM = 50°. 10. The inner loop of the boost converter has fs = 250 kHz, a = 0.292, and Rs = 0.2 Ω. Determine fi, ξi, and the poles of Hicl. Give a specific expression for a rational closed-loop transfer function Hicl(s). 11. The inner loop of the boost converter has fs = 250 kHz, a = 0.292, and Rs = 0.2 Ω. Determine f1, fsh, and expression for Ti(s).

14.28 Appendix: Sample-and-Hold Modeling 14.28.1 Sampler of the Control Voltage The control voltage at the input of the inner loop vc(t) is an analog, continuous-time function. The control voltage is sampled when the sensed inductor current RsiL intersects with the

controlled voltage, producing a sequence of vc(kTs). The modeling of control voltage sampling is as follows. The train of unit impulses δ(t − kTs) with the period Ts = 1/fs is given by (14.347) The sampler can be modeled by a multiplier of the analog, continuous-time control voltage vc(t) and the train of unit impulses δT(t), as shown in Figure 14.97. The sampled control voltage at the sampler output can be represented by a sequence (i.e., a train) of amplitudemodulated (AM) impulses (14.348) The expression (14.348) can be simplified to the following discrete-time function of time (14.349) because δ(t − kTs) = 0 for t ≠ kTs and δ(t − kTs) = 1 for t = kTs. The impulse-sampled control voltage is represented by the product of the continuous-time control voltage vc(t) and the train of unit impulses δT(t − kTs). The strength of each impulse is equal to the value of the control voltage at the sampling instant vc(kTs). Therefore, an ideal sampler can be regarded as an AM δ-modulator, in which the analog control voltage vc(t) is the modulating signal, the train of unit impulses δT(t) with the switching frequency fs = 1/Ts is the carrier, and the sampler output voltage v*c(t) is the train of the AM modulated impulses.

Figure 14.97 Sampler. (a) Circuit. (b) Model. Since the train of unit impulses is a periodic function with the angular frequency ωs = 2π/Ts, it can be represented by an exponential Fourier series (14.350) where the exponential Fourier series coefficients are (14.351) Hence, (14.352)

Thus, the sampled control voltage at the sampler output can be described by (14.353) Taking the Fourier transform of v*c(t) and using the shifting theorem of the Fourier transform, (14.354) we obtain the frequency spectrum of the sampled control voltage (14.355)

The frequency spectrum of the impulse-sampled control voltage is amplified by a factor of fs = 1/Ts and reproduced an infinite number of times at DC, fs, 2fs, 3fs, etc. The spectrum of the sampled control voltage contains the components at nfs ± f, where n = 1, 2, 3, ... . The sampling process produces the replicas of the input-frequency spectrum centered at DC and the multiples of the switching frequency. The Laplace transform of v*c(jω) in (14.355) is (14.356) If we assume that the spectrum of the control voltage v*c does not contain significant components above the Nyquist frequency fs/2 (i.e., |vc(f)| ≈ 0 for f ≥ fs/2) and therefore there is no aliasing, then we can write (14.357) Hence, the transfer function of an ideal sampler is (14.358) For example, assume that the control voltage is a sine wave of frequency f (14.359) The sampled control voltage is (14.360) The spectrum of the sampled control voltage is

(14.361) Figure 14.98 shows the spectrum of a sine wave before and after sampling for f < fs/2. For f < fs/2, fs − f > fs/2. For f = fs/2, fs − f = fs − fs/2 = fs/2. In this case, the frequencies f and fs − f are superimposed. For f > fs/2, fs − f < fs/2. Thus, any control voltage of frequency f > fs/2 will reflect into the frequency range 0 ≤ f ≤ fs/2, causing the frequency aliasing effect or folding effect. The reflected voltage will be interpreted as low-frequency information and will corrupt the applied control voltage. Therefore, the maximum frequency fmax of the control voltage vc should be lower than the Nyquist frequency fs/2 so that |vc(f)| ≈ 0 for f ≥ fs/2.

Figure 14.98 Spectrum of a sine wave. (a) Before sampling. (b) After sampling for f < fs/2. The transfer function H*icl(s) = i*(s)/vc*(s) from the small-signal control voltage v*c(s) to the small-signal inductor current i*l(s) in the sampled-Laplace s-domain is given by (14.87).

14.28.2 Zero-Order Hold of Inductor Current

The transfer function of the ZOH of the small-signal component of the inductor current il can be derived as follows. Assume that the small-signal component of inductor current il(t) = 0 for t < 0. This component at the output of the ZOH i0l(t) is the step reconstruction and is related to the sample sequence il(kTs) by (14.362)

The difference between the perturbed inductor current and the steady-state inductor current is a continuous-time function with a “staircase” waveform. The Laplace transform of i0l(t) is (14.363)

where the starred transform of the small-signal component of the inductor current is (14.364) In this equation, i*l(s) is a function of the small-signal component of the inductor current and the switching (sampling) period Ts. From (14.363), the ZOH transfer function is given by (14.365) Figures 14.99 and 14.100 show Bode plots of the ZOH transfer function.

Figure 14.99 Magnitude of the zero-order hold transfer function |HZOH| as a function of frequency.

Figure 14.100 Phase of the zero-order hold transfer function ϕZOH as a function of frequency. The transfer function of an ideal sampler and a ZOH is (14.366) The frequency response of the sampler and ZOH can be found as follows. Setting s = jω, (14.367)

where

(14.368)

and (14.369) with (14.370)

Hence, (14.371) and (14.372) Figures 14.101 and 14.102 show Bode plots of Hsh(s).

Figure 14.101 Magnitude of sample-and-hold transfer function |Hsh|.

Figure 14.102 Phase of sample-and-hold transfer function ϕHsh.

14.28.3 Approximations of The first-order Padé approximation is given by (14.373)

The second-order Padé approximation is (14.374)

The third-order Padé approximation is given by

(14.375)

For s = jω, (14.376) and (14.377) Figures 14.103 and 14.104 depict plots of for the exact function (14.377) and for the firstorder, second-order, and third-order Padé approximations given by (14.373) through (14.375) in semi-log scale and linear scale, respectively. The approximation of by the first-order Padé function is not good enough. The phase difference between the exact function and the first-order Padé function is 180° − 115° = 65° at fs/2. The phase difference between the exact function and the second-order Padé function is 180° − 170° = 10° at fs/2. The phase difference between the exact function and the third-order Padé function is 180° − 178.6° = 1.4° at fs/2.

Figure 14.103 Plots of the exact, first-order, second-order, and third-order Padé approximations of the phase of as functions of f/fs in semi-log scale.

Figure 14.104 Plots of the phase of the exact function (14.377) and the first-order, secondorder, and third-order Padé approximations of the phase of as functions of f/fs in linear scale. The second-order modified Padé approximation is (14.378)

15 Current-Mode Control of Boost Converter 15.1 Introduction This chapter is intended to present the open-loop small-signal duty cycle-to-inductor current transfer function, the input voltage-to-inductor current transfer function, and the inductor-tooutput current transfer function for the boost converter operated in CCM. Also, responses of the inductor current to step changes in the duty cycle, the input voltage, and the load current are given for the open-loop boost converter. Next, inner current closed-loop and the outer voltage closed-loop Bode plots and step responses are presented. Current-mode control of the boost converter was studied in [1–16].

15.2 Open-Loop Small-Signal Transfer Functions 15.2.1 Open-Loop Duty Cycle-to-Inductor Current Transfer Function A small-signal model of the PWM boost converter for CCM operation is shown in Figure 15.1(a). This model is obtained by replacing the switching network in the boost converter with a small-signal model. Figure 15.1(b) shows a block diagram of the open-loop boost converter. Setting vi = 0 and io = 0 in Figure 15.1(a), one obtains a small-signal model of the boost converter for deriving the duty cycle-to-inductor current transfer function shown in Figure 15.2. Using the KCL, (15.1) which, using relationship IL = IO/(1 − D) = VO/(1 − D)RL, becomes (15.2) Using the KVL, (15.3)

Figure 15.1 Small-signal model and block diagram of the PWM boost converter for CCM. (a) Small-signal model. (b) Block diagram.

Figure 15.2 Small-signal model of the PWM boost converter used to derive the duty cycle-toinductor current transfer function Tpi. which gives (15.4) Equating the right-hand sides of (15.2) and (15.4) (15.5) Hence, one obtains the duty cycle-to-inductor current transfer function (15.6)

The impedances Z1 and Z2 are given by (15.7) and (15.8)

Substituting (15.7) and (15.8) into (15.6), one arrives at the duty cycle-to-inductor current transfer function in the s-domain (15.9)

where the magnitude of Tpi at f = 0 is (15.10) the magnitude of Tpi(∞) is (15.11) the angular corner frequency or the angular undamped natural frequency is (15.12) the damping ratio is (15.13) the quality factor is (15.14) the zero is (15.15) and the poles are (15.16) The duty cycle-to-inductor current transfer function Tpi is a second-order low-pass function, which has two LHP poles and one LHP zero. The LHP zero zi1 is independent of D and the

poles depend on D. When D is increased from 0 to 1, the corner frequency f0 decreases and the damping factor ξ increases. Example 15.1 The boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, and r = 0.316 Ω. Calculate r, zi1, fzi1, f0, ξ, Q, p1, p2, and fd at RLmin = 40 Ω. Solution: The total parasitic resistance in series with the inductor at Dnom = 0.5 is (15.17) The duty ratio-to-inductor current transfer function at f = 0 is (15.18) and (15.19) The LHP zero is (15.20) and the frequency of the LHP zero is (15.21) The corner frequency is (15.22)

The damping ratio is (15.23)

and the quality factor is

(15.24) The poles are (15.25) and the damped frequency is (15.26) Substituting s = jω into (15.9), (15.27)

where (15.28)

and (15.29)

or (15.30)

Figure 15.3 shows idealized Bode plots of the open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter. Example 15.2 For the boost converter with VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. Draw Bode plots of Tpi at D = 0.5.

Solution: Figures 15.4 and 15.5 show the Bode plots of Tpi.

Figure 15.3 Idealized Bode plots of the open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter (without the delay). (a) |Tpi| versus f. (b) ϕTpi versus f.

Figure 15.4 Bode plot of the magnitude of the open-loop duty cycle-to-inductor current transfer function.

Figure 15.5 Bode plot of the phase of the open-loop duty cycle-to-inductor current transfer function Tpi for the boost converter without and with the delay time td = 1 μs. The delay td introduced by the power transistor, its driver, and the SR flip-flop can be described by , which is not a rational function. This function can be described by a first-order Padé approximation valid for frequencies from dc to fs/2 (15.31)

where ωzd = ωpd = 2/td. The duty cycle-to-inductor current transfer function with the delay times td is given by (15.32)

15.2.2 High-Frequency Open-Loop Duty Cycle-to-Inductor Current Transfer Function At high frequencies, the dynamics of the converter is determined by the inductance L. Figure 15.6 shows a high-frequency small-signal model of the PWM boost converter used to derive the duty cycle-to-inductor current transfer function Tpi. This model can be obtained by simplification of the model shown in Figure 15.2. At high frequencies, the reactance of the inductor L is very high. Therefore, the resistance r and the impedance Z2 can be neglected and replaced by short circuits. In this case, vo = 0 and the voltage-dependent voltage source Dvo can be replaced by a short circuit. The inductor current is given by (15.33) Neglecting the delay time td, the high-frequency duty cycle-to-inductor current transfer function is (15.34) Figures 15.7 and 15.8 show the high-frequency and exact open-loop duty cycle-to-inductor current transfer function Tpi without delay. At high frequencies, both the magnitude and the phase computed from the high-frequency and exact equations are nearly identical. However, there are large differences between the plots at low frequencies.

Figure 15.6 High-frequency small-signal model of the PWM boost converter used to derive the duty cycle-to-inductor current transfer function Tpi.

Figure 15.7 Bode plots of the magnitude of the high-frequency and exact open-loop duty cycleto-inductor current transfer function Tpi for the boost converter without the delay.

Figure 15.8 Bode plots of the phase of the high-frequency and exact open-loop duty cycle-toinductor current transfer function Tpi for the boost converter without the delay time.

15.2.3 Open-Loop Input Voltage-to-Inductor Current Transfer Function Setting d = 0 and io = 0 in the small-signal model of the boost converter of Figure 15.1 gives a small-signal model shown in Figure 15.9 that can be used for deriving the input voltage-toinductor current transfer function Mvi. From the KCL, (15.35) which can be rearranged to the form (15.36) From the KVL,

(15.37) which gives (15.38) Equating the right-hand sides of (15.36) and (15.38), (15.39) Hence, the open-loop input voltage-to-inductor current transfer function is obtained as (15.40)

Figure 15.9 Small-signal model of the PWM boost converter for deriving the input voltage-toinductor current transfer function Mvi. Substituting (15.7) and (15.8) into (15.40), one obtains the input voltage-to-inductor current transfer function

(15.41)

where (15.42) At s = 0, (15.43) For s = jω, (15.44)

where (15.45)

and (15.46)

or (15.47)

Figure 15.10 shows idealized Bode plots of the open-loop input voltage-to-inductor current transfer function Mvi for the boost converter. Note that Mvi = 1/Zi for the boost converter.

Example 15.3 The boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. Calculate fzi2 and Mvio at RLmin = 40 Ω and draw Bode plots of Mvi at Dnom = 0.5. Solution: The frequency of the zero is (15.48) From (15.43), (15.49)

Figures 15.11 and 15.12 show the Bode plots of Mvi.

Figure 15.10 Idealized Bode plots of the open-loop input voltage-to-inductor current transfer function Mvi for the boost converter. (a) |Mvi| versus f. (b) ϕMvi versus f.

Figure 15.11 Bode plot of the magnitude of the open-loop input voltage-to-inductor current transfer function Mvi versus frequency for the boost converter.

Figure 15.12 Bode plot of the phase of the open-loop input voltage-to-inductor current transfer function Mvi versus frequency for the boost converter.

15.2.4 Open-Loop Inductor-to-Output Current Transfer Function Figure 15.13 shows a small-signal model for deriving the open-loop inductor-to-output current transfer function for the boost converter. This model is obtained by setting vi = o and d = 0 in the complete small-signal model depicted in Figure 15.1(a). From the KVL, (15.50) which produces the output voltage (15.51) Using the KCL, (15.52)

from which (15.53) From the KCL, (15.54) Using (15.51) gives (15.55) Equating the right-hand sides of (15.53) and (15.55), one obtains (15.56) resulting in the inductor-to-output current transfer function (15.57) Substitution of (15.7) and (15.8) into (15.57) yields (15.58)

where (15.59) (15.60) and (15.61) Figure 15.14 depicts idealized Bode plots of Ai. Example 15.4 The boost converter has VInom = 12 V, VO = 20 V, Dnom = 0.5, rDS = 0.18 Ω, RF

= 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. Calculate fzn and Aio at RLmin = 40 Ω and draw Bode plots of Ai at Dnom = 0.5. Solution: The zero frequency is (15.62) From (15.43), (15.63) Figures 15.15 and 15.16 show the Bode plots of Ai.

Figure 15.13 Small-signal model of the PWM boost converter for deriving the inductor-tooutput current transfer function Ai.

Figure 15.14 Idealized Bode plots of the open-loop input voltage-to-inductor current transfer function Ai for the boost converter. (a) |Ai| versus f. (b) ϕAi versus f.

Figure 15.15 Bode plot of the magnitude of the open-loop inductor-to-output current transfer function Ai versus frequency for the boost converter.

Figure 15.16 Bode plot of the phase of the open-loop inductor-to-output current transfer function Ai versus frequency for the boost converter.

15.3 Open-Loop Step Responses of Inductor Current 15.3.1 Open-Loop Response of Inductor Current to Step Change in Input Voltage Consider a step change of the input voltage of magnitude ΔVI at time t = 0. The total input voltage is given by (15.64) where u(t) is the unit step function and VI(0−) is the steady-state input voltage before the step change. The step change of the input voltage in the time domain is expressed by (15.65)

which gives the step change of the input voltage in the s-domain (15.66) From (15.41) and (15.66), the transient component of the inductor current of the open-loop boost converter in the s-domain is obtained as (15.67) Hence, one obtains the transient component of the inductor current of the open-loop boost converter in the time domain (15.68)

where (15.69)

and (15.70)

Thus, the total inductor current is (15.71) where IL(0−) is the inductor current at time t = 0−. Setting the derivative of (15.86) to zero, one obtains the time instant at which the first and the highest maximum of il occurs (15.72)

The first maximum value of il is the highest one and occurs for n = 1. The highest maximum value of il is given by

(15.73)

resulting in the maximum overshoot of the transient component of the inductor current il (15.74) where iL(∞) = MvioΔVI is the final steady-state value of the transient component of the inductor current il after the transition. The maximum relative transient ripple of the total inductor current is defined as (15.75) where iL(∞) = IL(0−) + il(∞) is the steady-state value of the total inductor current after the transition. Example 15.5 For the open-loop boost converter specified in Example 15.1, draw the waveform of the inductor current that is a response to the step change of the input voltage vI from 12 to 13 V. Calculate (a) the maximum overshoot of the transient component of the inductor current, (b) the steady-state values of the transient component and the total inductor current, (c) the maximum relative transient ripple of the total inductor current. Solution: Figure 15.17 shows a step response of the transient component of the inductor current iL to the step change of the input voltage vI from 12 to 13 V, which corresponds to the step change of vi from 0 to 1 V, for the boost converter without feedback at Dnom = 0.5, VO = 20 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. The inductor current increases from 1 A to its peak value of 2 A and then reaches its steady-state value of iL(∞) = 1.1 A after approximately 3 ms. From Examples 15.1 and 15.3, ξ = 0.261, fzi2 = 58.35 Hz, f0 = 783.66 Hz, and Mvo = 0.09694 A/V. The load current is IOmax = VO/RLmin = 20/40 = 0.5 A and the dc inductor current is IL = IOmax/(1 − Dnom) = 0.5/(1 − 0.5) = 1 A. The final steady-state value of the transient component of the inductor current is (15.76) resulting in the steady-state value of the total inductor current (15.77) Since fzi1/f0 < ξ, the first maximum of il is given by

(15.78)

resulting in tm = ω0tm/(2πf0) = 1.429/(2π × 783.66) = 0.29 ms. Using (15.74), one can compute the maximum overshoot of the transient component of the inductor current il (15.79)

Hence, the maximum value of the transient component of the inductor current is (15.80) and the maximum relative transient ripple of the inductor current is (15.81)

Figure 15.17 Response of the transient component of the inductor current iL to a step change of vI from 12 to 13 V for the boost converter without feedback for Dnom = 0.5, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω.

15.3.2 Open-Loop Response of the Inductor Current to Step Change in the Duty Cycle Assume a step change of the duty cycle ΔdT at time t = 0. The total duty cycle is (15.82) The step change of the duty cycle in the time domain is given by (15.83) which results in

(15.84) Hence, using (15.9), the transient component of the inductor current of the open-loop boost converter in the s-domain is (15.85) The inverse Laplace transform of the inductor current of the open-loop boost converter in the time domain is (15.86)

where (15.87)

or (15.88)

Example 15.6 For the open-loop boost converter specified in Example 15.1, draw the waveform of the inductor current iL that is a response to the step change of the duty cycle dT from 0.5 to 0.6. Calculate the inductor current for steady state after the transition and the maximum relative transient ripple. Solution: Figure 15.18 shows a response of the transient component of the inductor current iL to a step change of the duty cycle dT from 0.5 to 0.6 for d = 0.1 for the boost converter without feedback at VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. The inductor current iL increases from 1 A to a peak value of 3.1 A and then reaches a steady-state value of approximately 1.4 A after 3 ms. From Example 15.1, Tpio = 3.8775 A, ξ = 0.261, fzi1 = 116.378 Hz, and f0 = 783.66 Hz. The steady-state value of the transient component of the inductor current is (15.89) Thus, the total steady-state inductor current is

(15.90) Since fzi1/f0 < ξ, the first maximum of il occurs at (15.91)

from which tm = 1.507/(2πf0) = 1.507/(2π × 783.66) = 0.3059 ms. The maximum overshoot is (15.92)

yielding the maximum value of the transient component of the inductor current (15.93) and the maximum relative transient ripple of the inductor current (15.94)

15.3.3 Open-Loop Response of Inductor Current to Step Change in Load Current The total load current with a step change ΔIO at t = 0 is (15.95) and the step change of the load current is (15.96) from which (15.97) Thus, the transient component of the inductor current is (15.98) producing

(15.99)

where (15.100)

or (15.101)

Example 15.7 For the open-loop boost converter specified in Example 15.1, draw the waveform of the inductor current iL that is a response to the step change of the load current ΔIO from 0.5 to 0.6 A. Calculate the inductor current for steady state after the transition and the maximum relative transient ripple. For the open-loop boost converter specified in Example 15.1, draw the waveform of the inductor current iL that is a response to the step change of the load current ΔIO from 0.5 to 0.6 A. Calculate the inductor current for steady state after the transition and the maximum relative transient ripple. Solution: Figure 15.19 shows a response of the transient component of the inductor current iL to the step change of the load current ΔIO from 0.5 to 0.6 A for ΔIO = 0.1 A for the boost converter without feedback at VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω. The inductor current iL increases from 1 A to a peak value of 1.3 A and then reaches a steady-state value of approximately 1.2 A after 3 ms. From Examples 15.1 and 15.4, Aio = 1.939, ξ = 0.261, fzn = 21.09 kHz, and f0 = 783.66 Hz. The transient component of the inductor current is (15.102) Thus, the total steady-state inductor current is (15.103) Since fzn/f0 = 21, 090/783.66 = 26.9 ξ = 0.261,

(15.104) producing tm = 3.254/(2πf0) = 3.245/(2π × 783.66) = 0.66 ms. Because fzn/f0 = 21, 090/783.66 = 26.9 ξ = 0.261, the maximum overshoot is given by (15.105)

producing the maximum value of the transient component of the inductor current (15.106) and the maximum relative transient ripple of the inductor current (15.107)

Figure 15.18 Response of the transient component of the inductor current iL to a step change of the duty cycle dT from 0.5 to 0.6 for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, and rC = 0.111 Ω.

Figure 15.19 Response of the transient component of the inductor current iL to a step change of the load current ΔIO from 0.5 to 0.6 A for the boost converter without feedback for VInom = 12 V, RLmin = 40 Ω, rDS = 0.4 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, and rC = 0.111 Ω.

15.4 Closed-Current-Loop Transfer Functions 15.4.1 Forward Gain The transfer function of the current modulator is given by [12] (15.108)

where (15.109)

(15.110) and (15.111) The transfer function Tms depends on the converter topology because it depends on Tpi, which is different for different converters.

15.4.2 Loop Gain of Current Loop The loop gain of the current loop is [12] (15.112)

The current loop gain Ti is independent of converter topology and the sense resistor Rs.

15.4.3 Closed-Loop Gain of Current Loop The closed-loop gain of the current loop is described by [12] (15.113)

where (15.114) For s = 0, (15.115)

The closed-loop control voltage-to-inductor current transfer function is given by (15.116)

Example 15.8 For the boost converter with Rs = 1 Ω, VInom = 12 V, VO = 20 V, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.379 Hz, f0 = 783.66 Hz, ξ = 0.261, η = 0.85, and fs = 100 kHz, find the compensation slope M3nom, which gives the phase margin of the inner loop PM = 60°. Calculate Ticlo at RLmin = 40 Ω. Draw Bode plots of Tms, Ti, Ticl, and Hicl and responses of dT and iL to a step change ΔVc = 0.25 V. Solution: The nominal duty cycle is (15.117) The slope of the rising inductor current is (15.118) and the slope of the falling inductor current is (15.119) Next, (15.120) From (15.109), (15.121) The amplitude of the compensating voltage is (15.122) The damping factor is

(15.123) The corner frequency is (15.124) The unity-gain frequency is (15.125) The closed-loop transfer function of the current loop at f = 0 is given by (15.126)

Figures 15.20 through 15.25 show Bode plots of Tms, Ti, and Ticl. The Bode plots of Ti show that the crossover frequency is fci = 38 kHz, GM = ∞, and PM = 60°. Figure 15.26 depicts the response of the duty cycle to a step change in the control voltage vc. The steady state value of the total duty cycle is (15.127) Figures 15.27 and 15.28 show Bode plots of Hicl. A response of the inductor function iL to a step change in the control voltage vc at a = 0.1716 is depicted in Figure 15.29. The steady-state value of the inductor current is (15.128)

15.4.4 Control-to-Output Transfer Function From Figure 15.2, (15.129) and (15.130)

Figure 15.20 Bode plot of the magnitude of Tms for the boost converter.

Figure 15.21 Bode plot of the phase of Tms for the boost converter.

Figure 15.22 Bode plot of the magnitude of the current loop gain Ti for the boost converter.

Figure 15.23 Bode plot of the phase of the current loop gain Ti for the boost converter.

Figure 15.24 Bode plot of the magnitude of the closed-loop gain of the current loop Ticl for the boost converter.

Figure 15.25 Bode plot of the phase of the closed-loop gain of the current loop Ticl for the boost converter.

Figure 15.26 Response of the duty cycle dT to a step change in the control voltage vc = 0.01 V in the boost converter at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, rC = 0.111 Ω, f0 = 783.66 Hz, fzi1 = 116.379 Hz, and ξ = 0.261.

Figure 15.27 Bode plot of the magnitude of the closed-loop gain of the current loop Hicl for the boost converter.

Figure 15.28 Bode plot of the magnitude of the closed-loop gain of the current loop Hicl for the boost converter.

Figure 15.29 Response of the inductor current iL to a step change in the control voltage vc = 0.01 V in the boost converter at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, Dnom = 0.5, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, r = 0.316 Ω, rC = 0.111 Ω, f0 = 783.66 Hz, fzi1 = 116.38 Hz, and ξ = 0.261. yielding (15.131) and (15.132) This gives (15.133)

The impedances are (15.134) and (15.135)

where (15.136) and (15.137) Substitution of these impedances into (15.133) produces the inductor current-to-output voltage transfer function (15.138) where (15.139) and (15.140) Figures 15.30 and 15.31 shows Bode plots of the inductor current-to-output voltage transfer function Tio.

Figure 15.30 Bode plot of the magnitude of inductor current-to-output voltage transfer function |Tio| for the boost converter.

Figure 15.31 Bode plot of the phase of inductor current-to-output voltage transfer function for the boost converter. The control-to-output function is (15.141)

This function has one LHP zero, one RHP zero, and three poles. At dc and low frequencies, (15.142) Figures 15.32 and 15.33 shows plots of the control-to-output transfer function for the boost converter at D = 0.5, L = 156 μH, rL = 0.19 mΩ, C = 68 μF, rC = 0.52 Ω, RL = 40 Ω, and r = 0.316 Ω at selected values of perturbation ratio a.

15.4.5 Input Voltage-to-Duty Cycle Transfer Function A block diagram for deriving the input voltage-to-duty cycle transfer function Mvd for the closed-current loop without feedforward gain Ki is shown in Figure 15.34. The inductor current is determined by (15.143) and the duty cycle is (15.144) producing (15.145) Thus, the input voltage-to-duty cycle transfer function for the closed-current loop is (15.146) For s = 0, (15.147)

Figure 15.32 Bode plot of the magnitude of control-to-output transfer function |Tco| for the boost converter.

Figure 15.33 Bode plot of the phase of control-to-output transfer function converter.

for the boost

Figure 15.34 Block diagram for deriving the input voltage-to-duty cycle transfer function.

Figure 15.35 Bode plot of the magnitude of Mvd for the boost converter without feedforward gain Ki. which produces |Mvdo| = −32 dB/V. Figures 15.35 and 15.36 show Bode plots of Mvi. Figure 15.37 depicts the response of the duty cycle to a step change in the input voltage from 20 to 21 V. The steady-state value of the duty cycle is (15.148) Figure 15.38 shows a block diagram for finding the input voltage-to-duty cycle transfer function with feedforward control Ki when the outer voltage loop is open. The feedforward coefficient for the boost converter are given by (15.149) and

(15.150) The inductor current is (15.151)

Figure 15.36 Bode plot of the phase of Mvd for the boost converter without feedforward gain Ki.

Figure 15.37 Response of dT to a step change ΔVI = 1 V from 12 to 13 V for the boost converter without feedforward gain Ki = 0.04167.

Figure 15.38 Block diagram for deriving the input voltage-to-duty cycle transfer function Mvdf with feedforward gain Ki. The components of the duty cycle are (15.152) and (15.153) producing the overall duty cycle (15.154) Hence, (15.155) This leads to the input voltage-to-duty cycle transfer function with Ki (15.156) Figures 15.39 and 15.40 depict Bode plots of Mvdf for Ki = −0.04167. A response of the duty cycle dT to a step change in the input voltage ΔVI = 1 V from 12 to 13 V is shown in Figure 15.41. At t = 0, there is a step change in dT from 0.5 to 0.475.

15.4.6 Load Current-to-Duty Cycle Transfer Function

A block diagram for deriving the load current-to-duty cycle transfer function Aicl for the closed-current loop is shown in Figure 15.42. The inductor current is determined by (15.157) and the duty cycle is given by (15.158) resulting in (15.159) Hence, one obtains the load current-to-duty cycle transfer function for the closed current loop (15.160)

Figure 15.39 Bode plot of the magnitude of Mvdf for the boost converter with feedforward gain Ki = −0.04167.

Figure 15.40 Bode plot of the phase of Mvdf for the boost converter with feedforward gain Ki = −0.04167.

Figure 15.41 Response of dT to a step change ΔVI = 1 V from 12 to 13 V for the boost converter with feedforward gain Ki = −0.04167.

Figure 15.42 Block diagram for deriving the load current-to-duty cycle transfer function Aid. For s = 0,

(15.161) Figures 15.43 and 15.44 show Bode plots for Aid. Figure 15.45 shows the response of the duty cycle dT to a step change of the load current from 0.5 to 0.6 A. The steady-state value of the duty cycle is (15.162)

15.4.7 Output Impedance of Closed-Current Loop Figure 15.46 shows a block diagram for finding the output impedance of the closed-current loop with open voltage loop. The inductor current is given by (15.163)

Figure 15.43 Bode plot of the magnitude of Aid for the boost converter.

Figure 15.44 Bode plot of the phase of Aid for the boost converter.

Figure 15.45 Response of dT to a step change ΔIO = 0.1 A due to Aid for the boost converter with the closed current loop.

Figure 15.46 Block diagram for deriving the output impedance Zoi of the closed-current loop.

and the duty cycle is (15.164) Thus, (15.165) yielding the duty cycle (15.166) The components of the output voltage are (15.167) and (15.168) resulting in the total output voltage (15.169) This gives the output impedance of the closed current loop (15.170) At s = 0, (15.171)

For example, for Dnom = 0.5 and RLmin = 40 Ω, (15.172) Figures 15.47 and 15.48 depict the magnitude and the phase of the output impedance of the closed-current loop. Figure 15.49 shows the response of the output voltage to a step change in the load current ΔIO = 0.1 A. The output voltage reaches its steady-state value after the transition.

(15.173)

Figure 15.47 Magnitude of the output impedance Zoi of the closed-current loop for the boost converter.

Figure 15.48 Phase of the output impedance ϕZoi of the closed-current loop for the boost converter.

Figure 15.49 Response of vo to a step change ΔIO = 0.1 A due to Zoi with the closed current loop for the boost converter.

15.5 Closed-Voltage-Loop Transfer Functions 15.5.1 Control-to-Output Transfer Function The open-loop duty cycle-to-output voltage transfer function of the boost converter is expressed by (15.174) where (15.175)

The product of (15.113) and (15.174) yields the control-to-output transfer function (15.176)

where (15.177)

15.5.2 Control Voltage-to-Feedback Voltage Transfer Function The product of (15.113) and (15.174) yields the control voltage-to-feedback voltage transfer function (15.178)

where (15.179) and (15.180) For s = 0, (15.181) Example 15.9 For the boost converter with Ticlo = 0.25979 1/V, Tpo = 37.55 V, VO = 20 V, VR = 5 V, fzi1 = 116.379 Hz, f0 = 783.66 Hz, and ξ = 0.261, find β and Tko. Draw Bode plots of Tco and Tk . Solution: Figures 15.50 and 15.51 show the control-to-output transfer functions. The voltage transfer function of the feedback network is

(15.182) Pick RB = 1.2 kΩ. Hence, (15.183) which gives (15.184) For f = 0, (15.185) Figures 15.52 and 15.53 show Bode plots of Tk .

Figure 15.50 Bode plot of the magnitude of the control to output transfer function Tco for the boost converter.

Figure 15.51 Bode plot of the phase of the control-to-output transfer function Tco for the boost converter.

Figure 15.52 Bode plot of the magnitude of Tk for the boost converter.

Figure 15.53 Bode plot of the phase of Tk for the boost converter.

15.5.3 Loop Gain of Voltage Loop Consider the third-order integral-lead control circuit whose voltage transfer function is given by (15.186) where B = (R1 + R3)/C2[R1R3 + h11(R1 + R3)]. Hence, the loop gain of the outer voltage loop is described by (15.187) where

(15.188) Example 15.10 Design a controller for the boost converter such that the phase margin PM ≥ 60° and the gain margin GM ≥ 10 dB. At Dnom = 0.5 and RLmin = 40 Ω, the converter has ξ = 0.261, fzn = 21.26 kHz, fzp = 9.88 kHz, fzi1 = 116.379 Hz, and f0 = 783.66 Hz. Solution: A third-order integral-lead control circuit (type III) will be used to compensate the voltage loop. Assume that fc = fm = 3 kHz. From Bode plots of Tk , the phase of Tk at f = fc, D = Dnom = 0.5, and RLmin = 40 Ω is ϕTk (fc) = −100°. Thus, (15.189) Hence, the K factor is calculated as (15.190) The frequencies of the zeros and the poles of the control circuit using the K value are (15.191) and (15.192) From Bode plots of Tk , |Tk (fc)| = −20 dB = 0.1. Hence, (15.193) Thus, (15.194) Bode plots of the magnitude |Tc| and the phase shift ϕTc of the designed controller are shown in Figures 15.54 and 15.55. Assuming R1 = 100 kΩ, (15.195) Pick C2 = 56 pF. Then,

(15.196) Pick R3 = 36 kΩ. Then, (15.197) Pick C1 = 150 pF. Next, (15.198) and (15.199)

Pick R2 = 680 kΩ and C3 = 0.75 nF. The frequencies of the zeros and the poles of the control circuit with the standard component values are (15.200) (15.201) (15.202) and (15.203)

Figures 15.56 and 15.57 show Bode plots of T, from which fc = 3 kHz, f− 180 = 12 kHz, GM = 10 dB, and PM = 60°.

Figure 15.54 Bode plot of the magnitude of the third-order integral-lead controller (type III) voltage transfer function Tc.

Figure 15.55 Bode plot of the phase of the third-order integral-lead controller (type III) voltage transfer function Tc.

Figure 15.56 Bode plot of the magnitude of the loop gain of the voltage loop T for the boost converter with an integral-lead controller (type III).

15.5.4 Closed-Loop Gain of Voltage Loop The closed-loop gain of the voltage loop with an integral-lead control circuit is given by (15.204) Example 15.11 For the boost converter with Ticlo = 0.25979 1/V, Tpo = 37.55 V, VO = 20 V, VR = 5 V, β = 0.25, fzi1 = 116.379 Hz, f0 = 783.66 Hz, and ξ = 0.261, find Tclo and draw Bode plots of Tcl for the boost converter with an integral-lead controller. Solution: The low-frequency gain of the closed voltage loop is (15.205)

Figures 15.58 and 15.59 show Bode plots of Tcl. The bandwidth of the closed-loop converter is BW = 8.5 kHz.

Figure 15.57 Bode plot of the magnitude of the loop gain of the voltage loop T for the boost converter with an integral-lead controller (type III).

Figure 15.58 Bode plot of the magnitude of the closed-loop gain of the voltage loop Tcl for the boost converter with an integral-lead controller.

Figure 15.59 Bode plot of the phase of the closed-loop gain of the voltage loop Tcl for the boost converter with an integral-lead controller.

15.5.5 Closed-Loop Audio Susceptibility with Integral Controller The open-loop audio susceptibility of the boost converter is (15.206) where (15.207) The closed-loop audio susceptibility is

(15.208)

where (15.209) For the integral-lead controller, (15.210) where (15.211) It is interesting to note that T = Tv/(1 + Ti). The ratios of the transfer functions for the boost converter are (15.212) and (15.213) Example 15.12 For the boost converter with Ticlo = 0.25979 1/V, Tpo = 37.55 V, VO = 20 V, VR = 5 V, β = 0.25, fzi1 = 116.379 Hz, f0 = 783.66 Hz, and ξ = 0.261, draw Bode plots of Tv and Mvcl. Solution: Figures 15.60 and 15.63 depict Bode plots of Tv. Figures 15.62 and 15.63 show Bode plots of Mvcl.

Figure 15.60 Bode plot of the magnitude of Tv for the boost converter with an integral lead.

15.5.6 Closed-Loop Output Impedance with Integral Controller The open-loop output impedance of the boost converter is (15.214) where ωrl = r/L and (15.215) The closed-loop output impedance is

(15.216) Example 15.13 For the boost converter with Ticlo = 0.25979 1/V, Tpo = 37.55 V, VO = 20 V, VR = 5 V, β = 0.25, fzi1 = 116.379 Hz, f0 = 783.66 Hz, and ξ = 0.621, draw plots of Zocl versus frequency. Solution: Figures 15.64 and 15.65 show plots of Zocl. The magnitude of the closed-loop output impedance |Zocl| is very low at low frequencies. However, at high frequencies, |Zocl| reaches quite high values.

Figure 15.61 Bode plot of the phase of Tv for the boost converter with an integral-lead.

Figure 15.62 Bode plot of the magnitude of the closed-loop audio susceptibility Mvcl for the boost converter with an integral-lead controller.

Figure 15.63 Bode plot of the phase of the closed-loop audio susceptibility Mvcl for the boost converter with an integral-lead controller.

15.6 Closed-Loop Step Responses 15.6.1 Closed-Loop Response of Output Voltage to Step Change in Input Voltage Figure 15.66 shows the closed-loop response of the output voltage vO to the step change of the input voltage vI from 12 to 13 V. The total output voltage vO decreases from 20 V to a minimum value of 20.043 V, and returns to a steady-state value of 20 V after 3 ms. It can be seen that negative feedback reduces the disturbance effect to nearly zero for steady state. The maximum relative transient ripple of the output voltage is (15.217)

Figure 15.64 The magnitude of the closed-loop output impedance Zocl for the boost converter with an integral-lead controller.

Figure 15.65 The phase of the closed-loop output impedance Zocl for the boost converter with an integral-lead controller.

Figure 15.66 Closed-loop response of vO to a step change of the input voltage vI from 12 to 13 V for the boost converter with an integral-lead controller at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.38 Hz, f0 = 783.66 Hz, ξ = 0.261, and β = 0.25 for Dnom = 0.5.

15.6.2 Closed-Loop Response of Output Voltage to Step Change in Load Current Figure 15.67 shows the closed-loop response of the output voltage vO to the step change in the load current ΔIO = 0.25 A from 1 to 1.25 A. The output voltage decreases from 20 to 19.82 V, and reaches a steady-state value of 20 V after 5 ms. Thus, the effect of a step change of the load current on the steady-state output voltage is nearly zero. The maximum relative transient ripple of the output voltage (15.218)

15.6.3 Closed-Loop Response of Output Voltage to Step Change in Reference Voltage Figure 15.68 shows the closed-loop response of the output voltage vO to the step change of the reference voltage VR from 5 to 6 V. The output voltage vO increases from 20 V to a maximum value of 24.54 V, and approaches a steady-state value of 24 V after 0.8 ms. The steady-state value of the transient component is (15.219) yielding the steady-state value of the total output voltage (15.220) The maximum overshoot of the transient component is (15.221)

Figure 15.67 Closed-loop response of vO to a step change of the load current ΔIO = 0.25 A from 1 to 1.25 A for the boost converter with an integral-lead controller at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.38 Hz, f0 = 783.66 Hz, ξ = 0.261, and β = 0.25 for Dnom = 0.5.

Figure 15.68 Closed-loop response of vO to a step change of the reference voltage VR from 5 to 6 V for the boost converter with an integral-lead controller at a = 0.1716, Rs = 1 Ω, VO = 20 V, VInom = 12 V, RLmin = 40 Ω, rDS = 0.18 Ω, RF = 0.072 Ω, L = 156 μH, rL = 0.19 Ω, C = 68 μF, rC = 0.111 Ω, r = 0.316 Ω, fzi1 = 116.38 Hz, f0 = 873.66 Hz, ξ = 0.261, and β = 0.25 for Dnom = 0.5. resulting in the maximum relative transient ripple of the output voltage (15.222)

15.7 Closed-Loop DC Transfer Functions The dc voltage transfer function of the outer loop forward path is given by

(15.223) and the dc loop gain of the outer loop (15.224) The dc closed-loop gain of the outer loop is (15.225) The dc closed-loop audio susceptibility is (15.226)

and the dc closed-loop output impedance is (15.227) Example 15.14 For the boost converter with Tco = 1000, Ticlo = 0.25979 1/V, Tpo = 37.55 V, β = 0.25, Mvo = 1.939, Zoo = 1.225 Ω, Rs = 0.1 Ω, Aio = 1.939, Tpio = 3.8775 A, Mvio = 0.09694 A/V, VO = 20 V, and VR = 5 V. Find Tclo, Mvclo, Zoclo, VO, and VE. Solution: Assuming that the dc voltage transfer function of the control circuit is Tco = 1000, the dc voltage transfer function of the outer loop forward path is given by (15.228) and the dc loop gain of the outer loop is (15.229) The dc closed-loop gain of the outer loop is (15.230) Hence, the output, feedback, and error voltages are (15.231)

(15.232) and (15.233) Next, (15.234) The dc closed-loop audio susceptibility is (15.235)

and the dc closed-loop output impedance is (15.236)

15.8 Summary The small-signal model of the boost converter for current-mode control has two inputs: the small-signal duty cycle d and the small-signal input voltage vi. The small-signal duty cycle d is a control variable and the small-signal input voltage vi is a disturbance. The small-signal model of the boost converter has one output, which is the small-signal component of the inductor current il. The open-loop duty cycle-to-inductor current transfer function Tpi of the boost converter is a second-order low-pass function with two poles and one zero. The zero of the open-loop duty cycle-to-inductor current transfer function Tpi is located in the LHP. The frequency of the zero of the open-loop duty cycle-to-inductor current transfer function Tpi is lower then the corner frequency f0. The minimum value of the phase of the open-loop duty cycle-to-inductor current transfer function ϕTpi is − 90°. In boost and most isolated converters, the simplest way of implementing the switch current sensing is by adding a resistor in series with the MOSFET source. However, this causes additional power loss and requires a transistor with a larger current capability or a higher gate-to-source voltage [10].

References 1. R. D. Middlebrook, “Modeling current-programmed buck and boost regulators,” IEEE Transactions on Power Electronics, vol. 4, no. 1, pp. 36–52, January 1989. 2. R. B. Ridley, “A new, continuous-time model for current-mode control,” IEEE Transactions on Power Electronics, vol. 6, pp. 271–280, April 1991. 3. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3d Ed. New York: John Wiley and Sons, 2004. 4. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics, ch. 11.4. Reading, MA: Addison-Wesley, 1991, pp. 274–280. 5. V. Vorpérian, “Simplified analysis of PWM converters using the model of the PWM switch, Part I: Continuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-26, pp. 497–505, May 1990. 6. A. I. Pressman, Switching Power Supply Design, ch. 12. McGraw-Hill, New York, 1991, pp. 427–470. 7. D. Czarkowski and M. K. Kazimierczuk, “Energy-conservation approach to modeling PWM dc-dc converters,” IEEE Transactions on Aerospace and Electronic Systems, vol. AES-29, pp. 1059–1063, July 1993. 8. M. K. Kazimierczuk and D. Czarkowski, “Application of the principle of energy conservation to modeling the PWM converters,” 2nd IEEE Conference on Control Applications, Vancouver, BC, Canada, September 13–16, 1993, pp. 291–296. 9. F. D. Tan and R. D. Middlebrook, “A unified model for current-programmed converters,” IEEE Transactions on Power Electronics, vol. 10, no. 4, pp. 393–408, July 1995. 10. B. Bryant and M. K. Kazimierczuk, “Effect of a sensing resistor on required MOSFET size,” IEEE Transactions on Circuits and Systems, Part I, vol. 50, pp. 708–711, May 2003. 11. B. Bryant and M. K. Kazimierczuk, “Small-signal duty cycle to inductor current transfer function for boost PWM converter in continuous conduction mode,” IEEE International Symposium on Circuits and Systems, Vancouver, BC, Canada, May 23–26, 2004, vol. V, pp. 856–859. 12. B. Bryant and M. K. Kazimierczuk, “Sample and hold effect in PWM dc-dc converters with peak current-mode control,” IEEE International Symposium on Circuits and Systems, Vancouver, BC, Canada, May 23–26, 2004, vol. V, pp. 860–863. 13. B. Bryant and M. K. Kazimierczuk, “Voltage loop power-stage transfer functions with MOSFET delay for boost PWM converter operating in CCM,” IEEE Transactions on

Industrial Electronics, vol. 54, no. 1, pp. 347–353, February 2007. 14. B. Bryant and M. K. Kazimierczuk, “Open-loop power-stage transfer functions relevant to current-mode control of boost PWM converter operating in CCM,” IEEE Transactions on Circuits and Systems, Part 1: Regular Papers, vol. 52, no. 10, pp. 2158–2164, October 2005. 15. B. Bryant and M. K. Kazimierczuk, “Modeling the closed-current loop of PWM boost dcdc converters operating in CCM with peak current-mode control,” IEEE Transactions on Circuits and Systems, Part 1: Regular Papers, vol. 52, no. 11, pp. 2404–2412, November 2005. 16. B. Bryant and M. K. Kazimierczuk, “Voltage-loop of boost PWM dc-dc converters with peak current-mode control,” IEEE Transactions on Circuits and Systems, Part 1: Regular Papers, vol. 53, no. 1, pp. 99–105, January 2006.

Review Questions 1. Draw a small-signal model for deriving the duty cycle-to-inductor current transfer function Tpi of the boost converter for CCM. 2. How many zeros does the transfer function Tpi have? 3. Where is the zero of Tpi located? 4. How does the zero frequency of Tpi compare to the corner frequency f0? 5. What is the minimum value of the phase ϕTpi? 6. What can you say about the stability of the current loop?

Problems 1. The boost converter designed in Chapter 3 has VInom = 156 V, VO = 400 V, Dnom = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, VF = 1.4 V, RF = 0.0171 Ω, L = 30 mH, rL = 2.1 Ω, C = 1 μF, and rC = 1 Ω. Determine zi1 and fzi1. 2. For the boost converter of Problem 15.1, determine Tpio and Tpix. 3. For the boost converter of Problem 15.1, determine Mvio and fzi2. 4. For the boost converter of Problem 15.1, determine Aio and fzn.

16 Open-Loop Small-Signal Characteristics of PWM Boost Converter for DCM 16.1 Introduction In this chapter, both dc and small-signal circuit models of the open-loop boost converter for DCM operation are presented [1–12]. Control-to-output transfer function, input-to-output voltage transfer function, input impedance, output impedance, duty cycle-to-inductor current transfer function, input voltage-to-inductor current, and output current-to-inductor current are derived and illustrated. Step responses are also given.

16.2 Small-Signal Model of Boost Converter for DCM Figure 16.1 shows a small-signal model of the PWM boost converter for DCM. The smallsignal model of the boost converter of Figure 16.1(a) can be obtained by replacing the switching network by its small-signal model as shown in Figure 16.1(b). This model can be modified by shifting the components representing the diode model from the bottom branch to the upper branch as shown in Figure 16.1(c). Example 16.1 A boost converter has the following parameters: VI = 10 V, VO = 20 V, PO = 40 W, rL = 0.1 Ω, rDS = 0.5 Ω, RF = 0.025 Ω, VF = 0.3 V, rC = 0.1 Ω, fs = 50 kHz, and Vr/VO ≤ 5.5%. Find the components of the small-signal model of the converter for DCM. Solution: The load current is (16.1) and the load resistance is (16.2) The dc voltage transfer function is (16.3) Assuming D = 0.4, one obtains

(16.4) The required inductance is (16.5) The peak switch, diode, and inductor current is (16.6) Assuming that the efficiency is 100%, the input power is PI = PO = 40 W. Hence, the dc inductor current is (16.7) The output ripple voltage is (16.8) The peak-to-peak ripple voltage across rC = 0.1 Ω is (16.9) Thus, the ripple voltage across the filter capacitance C is (16.10) Hence, the minimum capacitance is (16.11) Pick C = 220 μF. For the boost converter, ID = IO, VSL = VI, and VLD = VO − VI. Hence, the small-signal parameters for the boost converter are (16.12)

(16.13)

(16.14)

(16.15)

(16.16) and (16.17)

Figure 16.1 Small-signal model of the PWM boost converter for DCM. (a) Circuit of the boost converter. (b) Small-signal model of the boost converter. (c) Modified small-signal model of the boost converter.

16.3 Open-Loop Control-to-Output Transfer Function Figure 16.2 shows a small-signal model of the boost converter for deriving the open-loop control-to-output transfer function Tp. This model may be obtained by reducing vi and io to zero in the small-signal model of Figure 16.1(c). The currents are given by (16.18) (16.19) and

(16.20) From the KCL, (16.21) from which (16.22) which becomes (16.23) The current through resistance ro is (16.24) resulting in the voltage across ro (16.25) From the KVL, (16.26) which produces (16.27) resulting in (16.28)

Substitution of (16.28) into (16.23) gives (16.29) Hence, one obtains the control-to-output transfer function

(16.30) The impedances Z1 and Z2 are (16.31) and (16.32)

Thus, (16.33) where (16.34)

and (16.35)

The numerator NTp can be rearranged using the relationship (16.36) Hence, the control-to-output transfer function is given by (16.37) where (16.38)

(16.39) (16.40)

(16.41)

(16.42) and (16.43) At s = 0, (16.44)

Figure 16.2 Small-signal model of the PWM boost converter for DCM for deriving the control-to-output transfer function Tp. Example 16.2 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Tpo,

Tpx, f0, ξ, zn, zp, p1, p2, fzn, fzp, fp1, and fp2. Draw Bode plots of Tp. Solution: The parameters of Tp are (16.45)

(16.46)

(16.47) (16.48)

(16.49)

(16.50) (16.51) (16.52)

(16.53) (16.54)

(16.55) and (16.56) Figures 16.3 and 16.4 show Bode plots of Tp. The control-to-output transfer function Tp for DCM has two LHP poles, one LHP zero related to C, and one RHP zero related to L, similarly as for CCM. Thus, the boost converter is a nonminimal phase system for both CCM and DCM. The inductance L is much lower in DCM than that in CCM, typically by a factor of 10–100, reducing the converter magnetic energy storage capability. Therefore, ξ is low for CCM and high for DCM; the ratio of the two is of the order of 10. Since ξ2 1 for DCM, fp2 ≈ 2ξf0 is very high and fp1 is very low in DCM. Consequently, the poles are usually complex conjugate for CCM and real for DCM. In DCM, the pole p1 is dominant. The frequency fzp is higher for DCM than that for CCM because the inductance L is much lower. The frequency fzn is usually lower for DCM than that for CCM because the ripple current through inductor L and filter capacitor C is much higher and therefore the capacitance C is also higher for DCM. The frequencies of pole p2 and zero zp, fp2 and fzp, are higher than fs/2 = 25 kHz and therefore are beyond the frequency range, in which the converter small-signal model is valid. Since fp1 fp2, fp1 fzn, and fp1 fzp, pole p1 is dominant and the control-to-output transfer function can be approximated by (16.57)

16.4 Open-Loop Input-to-Output Voltage Transfer Function Figure 16.5 shows a small-signal model of the boost converter for deriving the open-loop input-to-output transfer function. This model may be obtained by reducing d and io to zero in the small-signal model of Figure 16.1(c).

Figure 16.3 Bode plot of the magnitude of Tp for the boost converter operated in DCM.

Figure 16.4 Bode plot of the phase of Tp for the boost converter operated in DCM.

Figure 16.5 Small-signal model of the PWM boost converter for DCM for deriving the inputto-output voltage transfer function Mv. The currents are given by (16.58) and (16.59) From the KCL, (16.60) which produces (16.61) resulting in (16.62)

The current through resistance ro is (16.63) and the voltage across resistance ro is (16.64) From the KVL, (16.65) which gives (16.66) producing (16.67) Substitution of (16.67) into (16.62) gives (16.68) Rearrangement of this equation produces the input-to-output voltage transfer function (16.69) Substituting impedances Z1 and Z2 into (16.69), one arrives at (16.70)

where (16.71)

and zn, ω0, and ξ are given by (16.39), (16.41), and (16.42), respectively. At s = 0, (16.72) Example 16.3 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Mvo and Mvx. Draw Bode plots of Mv. Solution: The required parameters of Mv are (16.73)

and (16.74)

Figures 16.6 and 16.7 show Bode plots of Mv.

Figure 16.6 Bode plot of the magnitude of Mv for the boost converter operated in DCM.

Figure 16.7 Bode plot of the phase of Mv for the boost converter operated in DCM. Since fp1 fp2 and fp1 fzn, pole p1 is dominant and the input-to-output voltage transfer function can be approximated by (16.75)

16.5 Open-Loop Input Impedance The open-loop input impedance can be derived using a small-signal model of the boost converter shown in Figure 16.5. From the KVL, (16.76) From the KCL,

(16.77) which becomes (16.78) The current through ro is (16.79) and the voltage across ro is (16.80) From the KVL, (16.81) which produces (16.82) Substitution of (16.76) into (16.82) gives (16.83) resulting in (16.84) Hence, one arrives at the open-loop input impedance (16.85) Substituting impedances Z1 and Z2 into (16.85), one obtains (16.86) where

(16.87) and (16.88) At s = 0, (16.89) Example 16.4 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Zio and fpZi. Draw plots of |Zi| and ϕZi versus frequency. Solution: The parameters of Zi are (16.90)

and (16.91)

Figures 16.8 and 16.9 show plots of Zi versus frequency.

16.6 Open-Loop Output Impedance Figure 16.10 shows a small-signal model of the boost converter for DCM operation for deriving the output impedance. From the KVL, (16.92) From Ohm’s law, (16.93) (16.94)

and (16.95) From the KCL, (16.96) which produces (16.97)

Figure 16.8 Plot of the magnitude of Zi for the boost converter operated in DCM.

Figure 16.9 Plot of the magnitude of Zi for the boost converter operated in DCM. From the KCL, (16.98) Equating (16.97) and (16.98), (16.99) Hence, one obtains the open-loop output impedance (16.100) Substitution of impedances Z1 and Z2 into (16.100) produces

(16.101) where (16.102)

and DTp is given by (16.35). Finally, the output impedance is (16.103) where (16.104) (16.105) (16.106) At s = 0, (16.107) Example 16.5 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Zoo, Zox, and fzrl. Draw plots of |Zo| and versus frequency. Solution: The parameters of Zo are (16.108)

(16.109)

(16.110)

and (16.111) Figures 16.11 and 16.12 show plots of Zo versus frequency.

Figure 16.10 Small-signal model of the PWM boost converter for DCM for deriving the output impedance Zo.

16.7 Step Responses of Output Voltage of Boost Converter for DCM 16.7.1 Response of Output Voltage to Step Change in Input Voltage Example 16.6 For the boost converter given in Example 16.1, draw the response of the output voltage to a step change in the input voltage VI from 10 to 11 V. Find the steady-state values of transient and total output voltages. Solution: The steady-state transient and total output voltages are

(16.112) and (16.113) The frequency of the dominant pole of Mv is fp1 = fH = 177.653 Hz. The bandwidth of Mv is BW = fH = fp1 = 177.653 Hz and the rise time is (16.114) The total response is (16.115) Figure 16.13 shows the response of vO to the step change in the input voltage VI.

Figure 16.11 Plot of the magnitude of Zo for the boost converter operated in DCM.

Figure 16.12 Plot of the magnitude of Zo for the boost converter operated in DCM.

Figure 16.13 Response of the output voltage vO to the step change of the input voltage ΔVI = 1 V from 10 to 11 V for the boost converter operated in DCM.

16.7.2 Response of Output Voltage to Step Change in Duty Cycle Example 16.7 For the boost converter given in Example 16.1, draw the response of the output voltage to a step change in the duty cycle from 0.4 to 0.5. Find the steady-state values of transient and total output voltages. Solution: The steady-state transient and total output voltages are (16.116) and (16.117) Figure 16.14 shows the response of vO to the step change in the duty cycle D.

Figure 16.14 Response of the output voltage vO to the step change of the duty cycle dT = 0.1 from 0.4 to 0.5 for the boost converter operated in DCM.

16.7.3 Response of Output Voltage to Step Change in Load Current Example 16.8 For the boost converter given in Example 16.1, draw the response of the output voltage to a step change in the load current from 2 to 2.1 A. Find the steady-state values of transient and total output voltage. Solution: The step change in vo at t = 0 is (16.118) The steady-state transient and total output voltages are (16.119) and

(16.120) Figure 16.15 shows the response of vO to a step change in the load current IO.

Figure 16.15 Response of the output voltage vO to a step change of the load current ΔIO = 0.1 A from 2 to 2.5 A for the boost converter operated in DCM.

16.8 Open-Loop Duty Cycle-to-Inductor Current Transfer Function The small-signal model of the boost converter for DCM shown in Figure 16.2 may be used to derive the open-loop duty cycle-to-inductor current transfer function Tpi. This model may be obtained by reducing vi and io to zero in the small-signal model of Figure 16.1(c). From the model, (16.121)

(16.122) and (16.123) From the KCL, (16.124) which gives (16.125) The current through resistance ro is (16.126) resulting in the voltage across ro (16.127) From the KVL, (16.128) which produces (16.129) resulting in (16.130) Hence, one obtains the duty cycle-to-inductor current transfer function (16.131) Substituting impedances Z1 and Z2 into (16.131), one obtains

(16.132) where (16.133) and (16.134) At s = 0, (16.135) Example 16.9 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Tpio, Tpix, and fzi. Draw Bode plots of Tpi. Solution: The parameters of Tpi are (16.136)

(16.137)

and (16.138)

The frequencies of the poles are fp1 = 177.563 Hz and fp2 = 37.2 kHz. Figures 16.16 and 16.17 show Bode plots of Tpi versus frequency.

Figure 16.16 Bode plot of the magnitude of Tpi for the boost converter operated in DCM.

Figure 16.17 Bode plot of the magnitude of Tpi for the boost converter operated in DCM. Since fp1 fp2 and fzi fp2, pole p1 is dominant and the duty cycle-to-inductor current transfer function can be approximated by (16.139)

16.9 Open-Loop Input Voltage-to-Inductor Current Transfer Function The input voltage-to-inductor current transfer function is (16.140) Substituting impedances Z1 and Z2 into (16.140), one obtains

(16.141) where (16.142) and (16.143) At s = 0, (16.144) Example 16.10 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Mvio and fzMvi. Draw Bode plots of Mvi. Solution: The parameters of Mvi are (16.145)

and (16.146)

Figures 16.18 and 16.19 show Bode plots of Mvi.

Figure 16.18 Bode plot of the magnitude of Mvi for the boost converter operated in DCM.

Figure 16.19 Bode plot of the phase of Mvi for the boost converter operated in DCM.

16.10 Open-Loop Output Current-to-Inductor Current Transfer Function Figure 16.20 shows a small-signal model of the boost converter for DCM operation for deriving the output current-to-inductor current transfer function. From the KVL, (16.147) and from Ohm’s law, (16.148) (16.149)

and (16.150) From the KCL, (16.151) from which (16.152) From the KCL, (16.153) which gives (16.154) Substitution of (16.154) into (16.152) produces (16.155) from which (16.156) From the current divider, (16.157) resulting in the output current-to-inductor current transfer function (16.158) Substitution of impedances Z1 and Z2 into (16.158) produces (16.159)

where DTp is given by (16.35). Hence, (16.160) where (16.161) and (16.162) At s = 0, (16.163) Example 16.11 A boost converter has the following parameters: RL = 10 Ω, ki = 10 A, ri = 5 Ω, gm = 0.4 A/V, ko = 10 A, ro = 5 Ω, r = 0.604 Ω, L = 8 μH, C = 220 μF, rC = 0.1 Ω, and fs = 50 kHz. Find Aix, Aio, and fzn. Draw Bode plots of Ai. Solution: The parameters of Ai are (16.164)

(16.165)

and (16.166) Figures 16.21 and 16.22 show Bode plots of Ai. The frequencies of poles are fp1 = 177.563 Hz and fp2 = 37.2 kHz.

Figure 16.20 Small-signal model of the PWM boost converter for DCM for deriving the output current-to-inductor current transfer function Ai.

Figure 16.21 Bode plot of the magnitude of Ai for the boost converter operated in DCM.

Figure 16.22 Bode plot of the magnitude of Ai for the boost converter operated in DCM.

16.11 Step Responses of Inductor Current of Boost Converter for DCM 16.11.1 Step Response of Inductor Current to Step Change in Input Voltage Example 16.12 For the boost converter given in Example 16.1, draw the response of the inductor current to a step change in the input voltage from 10 to 11 V. Find the steady-state values of transient and total inductor currents. Solution: The steady-state transient and total inductor current are (16.167)

and (16.168) Figure 16.23 shows the response of iL to the step change in the input voltage. The inductor current reaches steady state after 3.5 ms. The maximum inductor current is iLmax = 5.3 A. Hence, the maximum overshoot of the transient component is (16.169) and the maximum relative transient ripple of the inductor current is (16.170)

Figure 16.23 Response of the inductor current iL to the step change of the input voltage ΔVI = 1 V from 10 to 11 V for the boost converter operated in DCM.

16.11.2 Step Response of Inductor Current to Step Change in Duty Cycle Example 16.13 For the boost converter given in Example 16.1, draw the response of the inductor current to a step change in the duty cycle from 0.4 to 0.5. Find the steady-state values of transient and total inductor currents. Solution: The steady-state transient and total inductor current are (16.171) and (16.172) Figure 16.24 shows the response of iL to the step change in the duty cycle. The inductor current reaches steady state after 2.5 ms. It follows from the figure that iLmax = 4.52 A. Hence, the maximum overshoot of the transient component is (16.173) and the maximum relative transient ripple of the inductor current is (16.174)

Figure 16.24 Response of the inductor current iL to the step change of the duty cycle ΔdT = 0.1 from 0.4 to 0.5 for the boost converter operated in DCM.

16.11.3 Step Response of Inductor Current to Step Change in Load Current Example 16.14 For the boost converter given in Example 16.1, draw the response of the inductor current to a step change in the load current from 2 to 2.1 A. Find the steady-state values of transient and total inductor currents. Solution: The steady-state transient and total inductor current are (16.175) and (16.176)

The frequency of the dominant pole of Ai is fp1 = fH = 177.653 Hz. The bandwidth of Ai is BW = fH = fp1 = 177.653 Hz and the rise time is (16.177) The total inductor current response is (16.178) Figure 16.25 shows the response of iL to the step change in the load current.

Figure 16.25 Response of the inductor current iL to the step change of the load current ΔIO = 0.1 A from 2 to 2.1 for the boost converter operated in DCM.

16.12 DC Characteristics of Boost Converter for DCM

16.12.1 DC-to-DC Voltage Transfer Function of Lossless Boost Converter for DCM Figure 16.26 depicts a dc model of the boost converter for DCM. For a lossless boost converter, r = 0 and VF = 0, and therefore, VSL = VI and VLD = VO − VI. Since (16.179) the dc output voltage can be expressed as (16.180) Hence, using the definition for the dc voltage transfer function MV DC = VO/VI, one obtains the equation (16.181) solution of which gives the dc voltage transfer function for a lossless boost converter for DCM (16.182)

Figure 16.26 DC model of the boost converter operated for DCM.

16.12.2 DC-to-DC Voltage Transfer Function of Lossy Boost Converter for DCM For the dc model of a PWM converter for DCM, the following general relationships hold true (16.183) (16.184) and (16.185) For the boost converter, ID = IO and VSL + VLD = VSD = VO. Thus, (16.186)

Hence, (16.187) (16.188) (16.189) (16.190) and (16.191) From Figure 16.26, (16.192) which gives (16.193) Solution of this equation produces

(16.194) and (16.195) Substitution of (16.188) into (16.192) gives (16.196) This leads to the dc voltage transfer function of the lossy boost converter for DCM (16.197)

where μ is given by (16.195). For an ideal boost converter, r = 0 and VF = 0 and therefore VSL = VI and VLD = VO − VI. Hence, (16.198) The duty cycle for an ideal boost converter in DCM, derived in Chapter 3, is given by (16.199) Rearrangement of this produces an equation (16.200) solution of which gives (16.201)

resulting in (16.182). At the boundary between the DCM and CCM and for CCM, D1 = 1 − D, resulting in μ = D. Hence, the dc voltage transfer function of the lossy boost converter for CCM is

(16.202)

16.12.3 Efficiency of Boost Converter for DCM The power loss is given by (16.203) Hence, the boost converter efficiency for DCM is (16.204) where μ is given by (16.195). For CCM, μ = D and the expression for the boost converter efficiency for CCM becomes (16.205)

16.13 Summary The control-to-output transfer function Tp of the boost converter operated in DCM is a second-order function. The control-to-output transfer function Tp of the boost converter operated in DCM has two real LHP poles and two real zeros. One zero related to the C-rC filter capacitor is located in the LHP, and the other zero related to the inductor is located in the RHP. Therefore, the converter is a non-minimal circuit. The damping coefficient ξ for DCM is very high. The control-to-output transfer function Tp of the boost converter operated in DCM has one dominant pole. The frequencies of one pole and the RHP zero of Tp are usually higher than fs/2 and therefore, are beyond the validity of the small-signal model of the boost converter. The input-to-output transfer function Mv of the boost converter operated in DCM is a second-order function. The input-to-output transfer function Mv of the boost converter operated in DCM has two real LHP poles and a single LHP zero related to the C-rC output filter.

The input impedance Zi has a second-order numerator and a first-order denominator. The output impedance Zo is a second-order function. It contains two simple zeros and two simple poles.

References 1. S. Ćuk and R. D. Middlebrook, “A general unified approach to modeling switching dc-todc converters in discontinuous conduction mode,” Proceedings of the IEEE Power Electronics Specialists Conference, 1977, pp. 36–57. 2. R. Tymerski and V. Vorpérian, “Generation, classification, and analysis of switched-mode DC-to-DC converters by use of converter cell,” Proceedings of IEEE INTELEC’86, International Telecommunications Energy Conference, October 1986, pp. 181–195. 3. V. Vorpérian, R. Tymerski, and F. C. Lee, “Equivalent models for resonant and PWM switches,” IEEE Transactions on Power Electronics, vol. 4, no. 2, pp. 205–214, April 1989. 4. V. Vorpérian, “Simplified analysis of PWM converters using the PWM switch, Part II: Discontinuous conduction mode,” IEEE Transactions on Aerospace and Electronic Systems, vol. 26, no. 3, pp. 497–505, May 1990. 5. D. Maksimović and S. Ćuk, “A unified analysis of PWM converter in discontinuous modes,” IEEE Transactions on Power Electronics, vol. 6, no. 3 pp. 476–490, July 1991. 6. Y. Amran, H. Huliehel, and S. Ben-Yaakov, “A unified SPICE compatible averaged model of PWM converters,” IEEE Transactions on Power Electronics, vol. 6, pp. 585–594, October 1991. 7. S. Ben-Yaakov and D. Edry, “Averaged models and tools for studying the dynamics of switch mode DC-DC converters,” Proceedings of the IEEE Power Electronics Specialists Conference, Taipei, 1994, pp. 1218–1225. 8. J. Sun, D. M. Mitchell, M. Greuel, P. T. Krein, and R. M. Bass, “Averaged modeling of PWM converters in discontinuous conduction mode: A reexamination,” Proceedings of the Power Electronics Specialists Conference, June 1998, pp. 615–622. 9. J. Sun, D. M. Mitchell, M. Greuel, P. T. Krein, and R. M. Bass, “Averaged models of PWM converters in discontinuous conduction mode,” Proceedings of the International High-Frequency Conversion Conference, November 1998, pp. 61–72. 10. A. Reatti and M. K. Kazimierczuk, “Current-controlled current-source model for a PWM dc-dc boost converter operated in discontinuous conduction mode,” IEEE International Symposium on Circuits and Systems, Geneva, Switzerland, May 28–31, 2000, Paper III239, pp. 239–242.

11. J. Sun, D. M. Mitchell, M. Greuel, P. T. Krein, and R. M. Bass, “Averaged modeling of PWM converters in discontinuous conduction mode,” IEEE Transactions on Power Electronics, pp. 482–492, July 2001. 12. A. Reatti and M. K. Kazimierczuk, “Small-signal model of PWM converter for discontinuous conduction mode and its application for boost converter,” IEEE Transactions on Circuits and Systems, I, vol. 50, no. 1, pp. 65–73, January 2003.

Review Questions 1. What is the order of the control-to-output transfer function Tp of the boost converter operated in DCM? 2. What are the locations of the poles and zeros of Tp. 3. Is an RHP zero present in Tp for DCM? 4. How high is the frequency of the RHP zero? 5. Is there a dominant pole in Tp? 6. What is the order of the input-to-output transfer function Mv of the boost converter operated in DCM? 7. What are the locations of the poles and zero of Mv?

Problems 1. A boost converter has VI = 156 V, VO = 400 V, RLmin = 1.778 kΩ, RLmax = ∞, rDS = 1 Ω, RF = 0.0171 Ω, rL = 2.1 Ω, rC = 1 Ω, Vr/VO ≤ 1%, and fs = 100 kHz. Find L and C. 2. A boost converter has VI = 156 V, VO = 400 V, D = 0.5, RLmax = 1.778 kΩ, RLmax = ∞, rDS = 1 Ω, RF = 0.0171 Ω, L = 554.4 μH, rL = 2.1 Ω, C = 1 μF, rC = 1 Ω, and fs = 100 kHz. Find the small-signal model parameters. 3. A boost converter has VI = 156 V, VO = 400 V, D = 0.5, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 554.4 mH, rL = 2.1 Ω, C = 1 μF, and rC = 1 Ω. Find Tpo, Tpx, f0, ξ, zn, zp, p1, p2, fp1, and fp2. 4. A boost converter has VI = 156 V, VO = 400 V, D = 0.5, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 3 mH, rL = 2.1 Ω, C = 1 μF, rC = 1 Ω, and fs = 100 kHz. Find Mvo and Mvx. 5. A boost converter has VI = 156 V, VO = 400 V, D = 0.5, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 3 mH, rL = 2.1 Ω, C = 1 μF, rC = 1 Ω, and fs = 100 kHz. Find Zio and fpzi.

6. A boost converter has VI = 156 V, VO = 400 V, D = 0.65, RLmin = 1.778 kΩ, rDS = 1 Ω, RF = 0.0171 Ω, L = 3 mH, rL = 2.1 Ω, C = 1 μF, rC = 1 Ω, and fs = 100 kHz. Find Zoo, Zox, and fzrl.

17 Silicon and Silicon-Carbide Power Diodes 17.1 Introduction Electronic devices are fabricated using three types of materials: semiconductors, conductors, and insulators. Power semiconductor devices are key components for all power electronic circuits. Power diodes [1–22] play an important role in power electronics. This chapter presents basic concepts of intrinsic and extrinsic semiconductors. We will compare electrical and thermal properties of silicon and compound silicon-carbide materials. We will study silicon (Si) and silicon carbide (SiC) pn junction bipolar and Schottky power diodes. We will describe the physical structure of the diodes, explain the principle of operation, present the dc I–V characteristic, analyze the breakdown voltage, describe the diode capacitances, consider the switching characteristics of pn junction and Schottky diodes, and study the diode SPICE large-signal model. An understanding of the diode physics that affects the key performance parameters will help in designing the power electronics circuits.

17.2 Electronic Power Switches Power diodes and power metal–oxide–semiconductor field-effect transistors (MOSFETs) are commonly used semiconductor devices in PWM converters. These devices are used as fast electronic switches to control the flow of power from a source to a load, and vice versa. To ensure the reliability of power circuits, the designer must pay careful attention to semiconductor ratings such as maximum voltages and currents and maximum junction temperature TJmax. Power semiconductor devices must handle high current densities when ON and must withstand high voltages when OFF. In the on-state, the switches should be capable of conducting sufficiently high current (17.1) In addition, the on-resistance rON and the on-voltage drop VON should be as low as possible to reduce the conduction losses. In the off-state, the switches should have a sufficiently high breakdown voltage VBD (17.2) For power diodes, VBD is usually denoted by VRRM or VBR. For power MOSFETs, VBD is usually designated by VDSS. The gate-to-source voltage VGS must be lower than its breakdown voltage VGS(BD)

(17.3) The maximum gate-to-source voltage is usually 20 V. Finally, the junction temperature TJ must be less than the maximum junction temperature TJ(MAX) (17.4) The turn-on and turn-off switching times tsw should be as short as possible to reduce the switching losses and allow for high-frequency operation. To reduce the switching losses, the device capacitances should be as low as possible.

17.3 Atom An atom is the smallest particle of a chemical element that retains all the characteristics of an element. The structure of an atom consists of a nucleus at the center surrounded by orbiting electrons. The nucleus consists of neutrons and protons. The protons carry positive elementary charge q = 1.602 × 1019 C and the neutrons carry no charge. The orbiting electrons carry negative charge -q. The number of protons in the nucleus is equal to the atomic number of an element. The orbiting speed vorbit ≈ 0.75vlight. The electrons of an atom are bound to the nucleus by electromagnetic forces. Each electron is orbiting around the nucleus and spinning around its own axis. The orbiting electrons of an atom are aligned in a structured manner consisting of shells (orbits) and subshells at different distances from the nucleus. Electron energy increases as the shell radius increases. Shells are designated with uppercase letters K, L, M, N, O, P, and Q. Subshells are designated with lowercase letters s, p, d, and f. The nth atom shell can contain up to 2n2 electrons. However, the outermost atom shell, called the valence shell, can contain up to eight electrons. The valence shell of an atom determines the conductivity of a material. There is a maximum of one s subshell, three p subshells, five d subshells, and seven f subshells, which correspond to subenergy levels. The orbits located in subshells s are circular and all other orbits are elliptical. The diameter of an electron is de = 5.64 fm and the diameter of the proton is dp = 2.22 fm. The diameter of a nucleus dn is in the range 1.75–15 fm and the diameter of an atom is in the range 62–520 pm. The diameter of a silicon atom dSi = 235 pm. The mass of an electron in free space me = 9.109 × 10− 31 kg. The mass of a proton mp = 1.673 × 10− 27 kg. The mass of a neutron mn = 1.675 × 10− 27 kg. Hence, mp/me = 1.623 × 10− 27/9.109 × 10− 31 = 1782. Over 99.94% of an atom mass is located in the nucleus. The conductivity of a material σ = 1/ρ depends on the number of electrons in the valence shell. When the atom has one valence electron, it is a very good conductor, such as copper (Cu) (2 + 8 + 18 + 1 = 29), silver (Ag) (2 + 8 + 18 + 18 + 1 = 47), and gold (Au) (2 + 8 + 18 + 32 + 18 + 1 = 79). Valence electrons in conductors are loosely bound to the atoms and can easily become free to conduct current at room temperature, that is, full ionization takes place. When the atom has eight valence electrons, the valence shell is complete, no free electrons exist in the material, and it is an insulator. The conductivity σ decreases as the number of electrons in

the valence shell increases. Electrical materials can be divided into three categories: conductors, semiconductors, and insulators. The primary electrical parameter describing these materials is the resistivity ρ. For conductors (such as metals), ρ < 10− 5Ω • m. Conductors have no energy band gap. For semiconductors (such as silicon), 10− 5Ω • m ≤ ρ ≤ 103 Ω • m. For insulators (such as glass), ρ > 103 Ω • m. For example, the diamond is a high-resistivity insulator with ρ = 1014 Ω • m. The resistivity of semiconductors is intermediate in magnitude between that of conductors and insulators. Semiconductors and insulators have an energy band gap EG, whereas conductors do not have an energy band gap EG. For insulators, EG > 4 eV. For SiO2, EG = 8 eV. Atoms of solid materials can be bonded together in a single-crystal, polycrystalline, or amorphous forms. Semiconductors are crystalline solids. A single-crystal (or a monocrystal) semiconductor is formed by covalent bonding of each atom with its nearest neighbors in a rigid, highly regular, three-dimensional periodic structure. Each electron pair from two neighboring atoms forms a covalent bond. The bonded network of semiconductor atoms in regular periodic arrangement is termed the semiconductor lattice. Ions are atoms that either lost or gained one or more electrons. Crystal materials have atoms or ions that form a regular periodic array. The positions of atoms or ions are fixed, with constant distances between them. Polycrystalline materials consist of small grains of crystallites. Each grain has random orientation and is 0.01–10 μm in size. A monocrystal material consists of a single-crystal, whereas a polycrystal material consists of many crystals with random orientation. An amorphous material has a disordered (non-crystalline) atomic or molecular structure, where atoms have random positions. Silicon oxide, SiO2 (glass), belongs to this category. The singlecrystal growth process was invented by a Polish scientist Jan Czochralski1 in 1916.

17.4 Electron and Hole Effective Mass The movement of an electron in free space due to an externally applied force Fext is described by (17.5) where me is the free electron mass in free space and a is the acceleration. The movement of an electron in the crystal lattice is different from that in free space. There are internal forces Fint in the crystal lattice due to negatively charged electrons and positively charged protons and ions. Therefore, the movement of an electron in the crystal lattice is determined by both the applied external Fext and the internal forces Fint acting on the electron (17.6) In reality, it is difficult to determine all internal forces Fint. Hence, it is convenient to determine the movement of an electron in the crystal lattice in terms of the externally applied force alone and the effective electron mass m*e

(17.7) where the effective mass of an electron is (17.8) The effective mass coefficients for electrons and holes are (17.9) and (17.10) The effective mass of electrons is (17.11) where ml is the longitudinal effective mass and mt is the transverse effective mass for the conduction band. The effective mass of holes is (17.12) For electrons in Si, ml = 0.98, mt = 0.19, and ke = 0.26. For holes in Si, mlh = 0.16, mhh = 0.49, and kh = 0.39. For SiC, ke = 0.3654 and kh = 1. For GaN with the wurtzite crystal structure , ke = 0.232 and kh = 0.247. For Ge, ke = 0.12 and kh = 0.3. For GaAs, ke = 0.068 and kh = 0.5. A large effective mass of charge carriers leads to a low mobility.

17.5 Semiconductors Semiconductors are atoms that contain four valence electrons. Silicon (Si) belongs to group IV of the periodic table. Its atomic number is 14. Figure 17.1 shows a shell structure of the silicon atom. The silicon atom contains 14 electrons (2 + 8 + 4 = 14), which occupy the first three shells. Two electrons occupy the first K shell, eight electrons occupy the second L shell, and four valence electrons occupy the third M shell. In the K shell, two electrons occupy the s subshell. In the L shell, two electrons occupy the s subshell and six electrons occupy the p subshell. In the M shell, two electrons occupy the s subshell and two electrons occupy the p subshell. The configuration of subshells in silicon is 1s2s22p63s23p2. Ten out of 14 electrons are tightly bound to the nucleus and are not significantly perturbed by interatomic forces. The

outermost shell is called the valence shell, and the electrons in the valence shell are called the valence electrons.

Figure 17.1 Shell structure of silicon atom. Silicon is the second most abundant element after oxygen in the earth crust. Electrons can have only discrete energy levels that correspond to the discrete radii of their orbits. The revolving electrons exert attractive forces on the positive charges of the nucleus and repulsive forces on each other. The 10 inner electrons in shells K and L are strongly bound and the four valence electrons in shell M are weakly bound with the atom. The valence electrons are shared with four nearest neighbors and form covalent bonds. The diameter of each silicon atom is dSi = 0.235 nm. Silicon has a periodic diamond crystal structure with tetrahedral bonds. The side length (or the crystal-lattice constant) of the cubic unit cell of silicon is nm. The volume of the cell is Vcell = a3 = (0.5431 × 10− 9)3 = 0.16 nm3. There are eight equivalent atoms in the silicon cell because there are eight atoms in the corners. The silicon cell volume is Vc = a3 = (0.543 × 10− 9)3 = 1.6 × 10− 22 cm3. The concentration of silicon atoms is NSi = 8/a3 = 8/(0.543 × 10− 3)3 = 5 × 1028 atoms/m3 = 5 × 1022 atoms/cm3 = 5 atoms/nm3. The crystal-lattice constant of carbon C is a = 0.35668 nm and silicon-carbide SiC is a = 0.43596 nm.

An ion is an atom in which the total number of electrons is not equal to the total number of protons, resulting in a net positive or negative charge. At high temperature, all valence electrons are free. In this case, each ion of silicon consists of the nucleus and 10 inner electrons, resulting in a positive charge 4q = 4 × 1.602 × 10− 19 C. The four valence electrons of silicon contribute a negative charge − 4q = −4 × 1.602 × 10− 19 C. Thus, the intrinsic silicon crystal is electrically neutral. Semiconductors are materials that contain four valence electrons. A semiconductor is neither a good conductor nor a good insulator. Each atom of a semiconductor shares one valence electron with each of its four neighbors, resulting in a complete subshell for every atom. Sharing of valence electrons with nearest neighbors is called covalent bonding, which produces a stable, tightly bound lattice structure called a crystal or monocrystal. Silicon atoms share one of the four valence electrons with each of four nearest neighbors. Table 17.1 Portion of periodic table III B Al Ga In

IV C Si Ge Sn

V N P As Sb

Table 17.1 gives a portion of the periodic table with chemical elements from groups III, IV, and V. Semiconductors can be divided into two groups: elemental semiconductors and compound semiconductors. Elemental semiconductors are formed from a single type of atoms from group IV of the periodic table of elements, such as silicon (Si) and germanium (Ge). Silicon has four valence electrons in the outermost shell. A compound semiconductor consists of two or more different elements. Compound semiconductors are made up of combinations of elements from groups III and V, such as gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP), or both semiconductors from group IV, such as SiC. GaAs is a III–V compound semiconductor, and SiC is a IV–IV compound semiconductor. Insulators are compound materials that belong to group II–V, for example, SiO2.

17.6 Intrinsic Semiconductors A pure semiconductor without doping (NA = ND = 0) and with no lattice defects is called an intrinsic semiconductor. At low temperatures, almost all valence electrons reside in the covalent bonds and nearly all covalent bonds are intact. Therefore, very few free electrons are available to conduct current and the material behaves as an insulator. At room temperature, thermal or optical energy (heat) causes a small number of covalent bonds to break by thermal ionization and some electrons are free to wander through the lattice and to serve as charge carriers, that is, to conduct current. These free electrons are called conduction electrons. Carriers are the charge or current-carrying entities. Figure 17.2 shows an energy band gap in

semiconductors. The amount of energy required to break a covalent bond is referred to as the band gap energy or forbidden gap (17.13) where EC is the lowest possible conduction band energy and EV is the highest possible valence band energy. A wide energy band gap improves the ability to support a high internal electric field intensity before electrostatic breakdown occurs. In addition, it improves radiation resistance. An ion is an atom in which the total number of electrons is not equal to the total number of protons. If an atom loses an electron, it becomes a positive ion. If an atom accepts an electron, it becomes a negative ion. If an electron gains enough thermal or optical energy (E ≥ EG = 1.12 eV for Si), it may break the covalent bond and becomes a free electron with a negative charge, while leaving a vacancy or a hole with a positive charge. When a covalent bond is broken, an electron leaves behind an uncompensated positively charged donor ion N+D, and two charge carriers are produced: an electron and a hole (a void). In other words, an electron–hole pair (EHP) is generated. A hole represents the absence of an electron in an atom in the valence shell. The mobile electron has a negative charge − q = −1.602 × 10− 19 C and leaves behind an incomplete bond with a positive charge + q. The moving hole behaves as a particle with charge q. The average kinetic energy is equal to the thermal energy of electrons, that is, m*evth2/2 = 3kT/2. At room temperature, electrons move randomly and quite rapidly in different directions in a zigzag fashion with a thermal velocity (17.14) and undergo frequent collisions, where me is the mass of a free electron in free space. At T = 300 K, the thermal velocity of a silicon electron is (17.15) It is 1304 times lower than the speed of light vlight = 3 × 108 m/s. At T = 300 K, the thermal velocity of a silicon hole is (17.16) The mean free time between collisions, called collision time τc, is approximately 0.1 ps. The average distance between collisions (the mean free path) dc = vthτc = 2.3 × 105 × 10− 13 = 23 nm. Collisions of electrons introduce thermal (or white) noise. The concentration of free electrons n is the number of free electrons per unit volume (e.g., per cm3). Similarly, the concentration of holes p is the number of holes per unit volume. Thermal ionization generates identical number of electrons n and holes p per unit volume. Ionization rate is a strong function

of temperature T. Recombination is a process, where some of the electrons fill some of the holes. An EHP is generated when an electron breaks the bond and leaves the atom. An EHP disappears when an electron fills the hole. The rate of EHP generation G is equal to the rate of EHP recombination R in thermal equilibrium. This process is called generation–recombination (G–R) process. The time between the generation and the recombination of an EHP is called the EHP lifetime τGR. The typical value of the EHP average lifetime is τGR = 10 ns to 10 μs.

Figure 17.2 Energy band gap EG in a semiconductor. For germanium (Ge), the energy band gap energy is EG = 0.66 eV and intrinsic concentration is ni = 1013 cm− 3. The germanium atom has 32 electrons and protons. For GaAs, EG = 1.42 eV and intrinsic concentration is ni = 2 × 106 cm− 3. Insulators have very wide energy band gaps, higher than 4 eV. For diamond, EG = 5 eV. The diamond atom has six electrons and protons. For SiO2, EG = 8 eV. Conductors have either very small energy band gaps or no band gaps at all due to an overlap of the conduction and valence bands. Electrons and holes can be thermally excited into the conduction band. Electrons and holes are generated in pairs. In intrinsic (pure) semiconductors in thermal equilibrium, the concentration (or density )of free electrons n is equal to the concentration of holes p (hole density) (17.17) where ni is the intrinsic carrier concentration. Each of the concentrations is denoted by ni. The intrinsic carrier concentration ni increases rapidly with increasing temperature T

(17.18)

where A (cm− 3 K− 3/2) is a constant independent of temperature and related to a specific semiconductor, T is the absolute temperature in K, k = ET/T = 8.617 × 10− 5 eV/K = 1.3792 × 10− 23 J/K is Boltzmann’s constant, h = 6.626 × 10− 34 J • s is Planck’s constant. me = 9.1095 × 10− 31 kg is the (rest) mass of free electron, m*e = keme is the effective mass of electron, and m*h = khme is the effective mass of hole. For silicon, ke = 0.26 and kh = 0.39. The effective mass of an electron in a crystal is different from the electron mass in a vacuum. Electron volts (eV) are often used rather than joules (J) to measure the amount of minimum energy of electrons (1 eV × q = 1 × 1.602 × 10− 19 J). At T = 0 K, ni = 0. The thermal energy ET = kT increases with absolute temperature T. At T = 300 K, kT = 26 meV. The thermal voltage is VT = kT/q = 26 mV at T = 300 K. The band gap energy EG is the minimum thermal energy of vibrating atoms required to break the covalent bond and generate an EHP. It is the difference between the conduction band energy EC and the valence energy band EV, that is, EG = EC − EV. For silicon, EG(Si) = 1.12 eV= 1.12 × 1.602 × 10− 19 = 1.794 × 10− 19 J and the potential is VG(Si) = EG/q = 1.12 V. For silicon carbide, EG(SiC) = 3.26 eV= 3.26 × 1.6 × 10− 19 = 5.216 × 10− 19 J. The ratio of the energy band gaps is EG(SiC)/EG(Si) = 3.26/1.12 = 2.91. In the vicinity of room temperature, the term T3/2 varies slowly in comparison with the exponential term . Hence, the temperature dependence of ni is approximately exponential. For silicon, ni approximately doubles for every 10°C rise. For T > 0 K, EHPs are generated due to thermal energy (heat), which breaks the covalent bonds within the crystal lattice. The generated electrons and holes become charge carriers. The different values of band gap energy EG account for different values of the intrinsic concentration ni for different semiconductors at the same temperature T. An intrinsic semiconductor is a poor conductor at room temperature. For silicon, the intrinsic carrier concentration of EHPs is (17.19)

Hence, ni = 0.17309 × 1010 cm− 3 at room temperature T = 27°C = 300 K, ni = 1.5843 × 1012 cm− 3 at T = 150°C = 423 K, ni = 4.0726 × 1012 cm− 3 at T = 175°C = 448 K, and ni = 9.5166 × 1012 cm− 3 at T = 200°C = 473 K. ni = 1.545 × 1013 cm− 3 at T = 175°C = 448 K, For (kekh) = 1, ni = 1.5 × 1010 cm− 3 at T = 300 K. Usually, the maximum operating temperature of

silicon power devices TJmax is 150°C or 175°C. The density of silicon atoms in the crystal lattice (atomic density) is approximately NSi = 5 × 1022 atoms/cm3. At room temperature, NSi/ni = 5 × 1022/1010 = 5 × 1012. Thus, only one bond in approximately 5 × 1012 silicon atoms is broken at T = 300 K, that is, 1 in 5 trillion. Since each silicon atom has four valence electrons, the concentration of silicon valence electrons is 4NSi = 20 × 1022 cm− 3. At room temperature, the ratio of valence electrons to the free electrons in silicon is 4NSi/ni = 20 × 1022/1010 = 20 × 1012. For comparison, the concentration of free electrons in copper (which is a good conductor) is nCu = 8.45 × 1022 cm− 3. At T = 300 K, ni = 2.4 × 1013 cm− 3 for Ge and ni = 2.1 × 106 cm− 3 for GaAs. As the temperature increases, ni increases and the ratio NSi/ni decreases. An empirical equation for silicon for 275 ≤ T ≤ 375 K is (17.20) For silicon carbide, the intrinsic carrier concentration of EHPs is (17.21)

Hence, Thus, ni = 0.531 × 10− 8 cm− 3 at T = 27°C = 300 K, ni = 0.7593 cm− 3 at T = 150°C = 423 K, and ni = 2.29 × 1010 cm− 3 at T = 600°C = 873 K. Figure 17.3 shows plots of the intrinsic carrier concentrations ni for silicon and silicon carbide as functions of temperature T. Figure 17.4 shows plots of the intrinsic carrier concentrations ni for silicon and silicon carbide as functions of 1000/T. The intrinsic concentration ni of silicon carbide is much lower than that of silicon at the same temperature because the energy band gap EG is almost three times larger for silicon carbide.

Figure 17.3 Intrinsic carrier concentrations ni as functions of temperature T for silicon and silicon carbide.

Figure 17.4 Intrinsic carrier concentrations ni as functions of temperature 1000/T for silicon and silicon carbide. For a semiconductor in thermal equilibrium, the product of electron and hole concentrations is a constant given by the mass-action law (17.22) where B is the material-dependent parameter, for example, B = 1.08 × 1031 K− 3 • cm− 6 for silicon, B = 3.21 × 1031 K− 3 • cm− 6 for germanium, B = 1.27 × 1031 K− 3 • cm− 6 for gallium arsenide, and B = 2.89 × 1032 K− 3 • cm− 6 for silicon carbide. The relative sensitivity of the concentration ni to temperature T in intrinsic semiconductors is (17.23) For silicon, (dni/dT)/ni = 8.3%/K at T = 300 K.

The thermal generation process produces equal concentrations of electrons and holes. Free electrons and holes may contribute to conduction of electric current. The conductivity of intrinsic semiconductors is directly proportional to the concentration of EHPs (17.24) where ρi is the resistivity and μn and μp are the mobilities of electrons and holes, respectively. For silicon, the resistivity is (17.25) At room temperature, the resistivity of silicon is (17.26) As the temperature increases, the mobility of charge carriers decreases. However, the carrier concentration ni and the volume charge density ρv = qni increase more rapidly, resulting in a decrease in the resistivity of intrinsic semiconductors. In contrast, the resistivity of metallic conductors increases with rising temperature. For comparison, the mobility of electrons in conductors is much lower than that of semiconductors. For example, the mobility of electrons in copper is μe = 0.0032 m2/V • s = 32 cm2/V • s. Electrons and holes move through the crystal structure by two mechanisms: drift and diffusion. Drift current is a result of charge carrier motion caused by an applied electric field E. Drift moves the carriers in the direction of the electric field from a higher potential to a lower potential. Diffusion current is caused by gradients in electron and hole concentrations. Diffusion moves the carriers in the direction of decreasing concentration. Electrons move in the direction of lower concentration of electrons, and holes move in the direction of lower concentration of holes.

17.7 Extrinsic Semiconductors Extrinsic (doped) semiconductors are obtained by a process called doping. The conductivity of semiconductors can be increased by adding impurities to the intrinsic (pure) semiconductor. The electron and hole concentrations can be significantly altered by replacing a small number of atoms in the original crystal with impurity atoms, called dopants. The process of adding impurities to a pure semiconductor is called doping. In addition to thermal G–R process of charge carriers, there will be carriers installed by doping. A semiconductor material with dopants is called an extrinsic semiconductor. In extrinsic semiconductors, the concentrations of electrons and holes are not equal (n ≠ p). The ratio of the electron concentration to the hole concentration is changed by doping an intrinsic semiconductor (such as those from the group IV

of the periodic table) with elements from either the group III (acceptors) or the group V (donors). An element from the group III (trivalent) has three valence electrons (B, Ga, In, and Al). An element from the group V (pentavalent) has five valence electrons (P, As, and Sb). At room temperature, the thermal energy is sufficient to ionize almost all donors and acceptors, resulting in complete ionization of impurities. Figure 17.5 shows energy levels in semiconductors. The thermal energy required to ionize donor atoms, called the ionization energy, is of the order of ΔECD = EC − ED = 50 meV, where ED is the donor energy level. This energy is EG(Si)/(EC − ED) = 1120/50 = 22.4 lower than that required to break covalent bonds and generate an EHP in silicon at room temperature. Full donor ionization takes place at room temperature. The concentration of ionized negatively charged acceptors N−A is very close to the total concentration of acceptors NA, that is, N−A ≈ NA. Similarly, the concentration of ionized positively charged donors N+D is very close to the total concentration of donors ND, that is, N+D ≈ ND.

Figure 17.5 Energy levels in semiconductors.

17.7.1 n-Type Semiconductor The n-type extrinsic semiconductor is produced when the intrinsic semiconductor is doped with the elements from group V of the periodic table that have five valence electrons, such as phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi). A silicon atom in the lattice may be replaced by a donor atom whose four electrons form the covalent bonds with neighboring atoms from group IV and one extra electron may be easily ionized. The ionization energy of the extra electron is ΔECD(Sb) = 39 meV, ΔECD(P) = 44 meV, and ΔECD(As) = 54 meV. Therefore, at room temperature, the donor atoms are essentially completely ionized. Each donor atom donates an electron to the conduction band. The conductivity of doped semiconductors may be significantly improved compared to that of intrinsic semiconductors. The n-type impurities donate electrons to intrinsic semiconductors, one electron per donor, and therefore are called donors. Figure 17.6 shows a donor in an n-type semiconductor. No hole is

created when a conduction electron is created. Since the only holes are those caused by thermal energy excitation of electrons, the number of holes is far less than the number of electrons. As a result, there is an excess of electrons (n p). The electrons are the majority carriers and holes are the minority carriers in n-type semiconductors. The concentration of the majority electrons is nn and the concentration of the minority holes is pn. n-type semiconductors doped with donors have many electrons and few holes (nn pn). The material is still electrically neutral because each dopant atom has the same number of protons and electrons. Therefore, the overall numbers of protons and electrons in the material are equal, and therefore the net charge is zero.

Figure 17.6 Donor in an n-type semiconductor. For n-type semiconductors, the donor concentration ND is usually several orders of magnitude higher than the intrinsic concentration ni, that is, nn ≈ ND ni. Therefore, the thermally generated electrons can be neglected at room temperature. In general, the charge neutrality requires that the total negative charge Q− = q(n + N−A) is equal to the total positive charge Q+ = q(p + N+D) (17.27) For n-type semiconductors with NA = 0, N+D ≈ ND, p = pn, n = nn, Q− = qnn, Q+ = q(pn + N+D)

≈ q(p + ND), and pn + ND = nn. Thus, (17.28) The law of mass action remains also valid for extrinsic semiconductors (17.29) yielding (17.30) Thus, the concentration of free electrons is (17.31)

We use the approximation, for x 1, . Hence, observing that ND ni and ND pn, the majority free-electron concentration nn in n-type semiconductors with NA = 0 is approximately equal to the density of donor atoms ND. Likewise, (17.32) which gives (17.33) producing the minority hole concentration (17.34)

which is a very strong function of temperature T. For example, for a donor concentration ND = 2.25 × 1015 cm− 3, nn ≈ ND = 2.25 × 1015 cm− 3 and the hole concentration at room temperature is pn = n2i/ND = (0.176 × 1010)2/(2.25 × 1015) = 1.377 × 103 cm− 3. Thus, the concentration of holes pn is lower by 10 orders of magnitude than the concentration of electrons nn. Few holes remain because recombination with a large number of electrons fills most of them. Figure 17.7 shows donor concentration ND, intrinsic carrier concentration ni, majority electron concentration nn, and minority hole concentration pn as functions of temperature T for n-type silicon with ND = 1015 cm− 3. At low temperatures, nn pn and the semiconductor is extrinsic.

At high temperatures, nn ≈ pn and the semiconductor behaves like an intrinsic semiconductor. The conductivity of the n-type semiconductor is directly proportional to the donor concentration ND (17.35) Thus, the ratio of the resistivity of the intrinsic semiconductor to that of the n-type semiconductor is (17.36) Usually, the ratio of ND/ni should be greater than 1000. Otherwise, an extrinsic semiconductor becomes degenerated. When the temperature increases, ni also increases, causing ND/ni to decrease. When this ratio reduces 1000 times, an extrinsic semiconductor is degenerated. When the ratio reaches 1, an extrinsic semiconductor behaves as an intrinsic semiconductor. Therefore, there is a maximum operating temperature for a minimum doping concentration at a given maximum temperature to satisfy the requirement ND ni.

Figure 17.7 Donor concentration ND, intrinsic carrier concentration ni, majority electron concentration nn, and minority hole concentration pn as functions of temperature T for n-type silicon with ND = 1015 cm− 3. The concentration of the silicon atoms is NSi = 5 × 1022 atoms/cm3. The maximum value of donor concentration is usually NDmax = 1018 cm− 3. Hence, NSi/NDmax = 5 × 1022/1018 = 50, 000 at room temperature. The minimum value of donor concentration is usually NDmin = 1013 cm− 3 so that ND ni. For NSi/ND, a semiconductor becomes a conductor. Example 17.1 What is the hole concentration in an n-type silicon with ND = 1014 donors/cm3 at T = 300 K. Find nn/pn, NSi/ND, NSi/pn, and ρn at room temperature. Solution: For Si in room temperature, ni = 0.176 × 1010 EHPs/cm3. All donor atoms are ionized at room temperature, that is, N+D ≈ ND. Thus, the concentration of the majority carriers is nn = ND = 1014 electrons/cm3. The concentration of the minority carriers is

(17.37) Hence, (17.38) Silicon has NSi = 5 × 1022 atoms/cm3. Thus, (17.39) and (17.40) At room temperature, the resistivity is (17.41)

17.7.2 p-Type Semiconductor The p-type extrinsic semiconductor is produced when the intrinsic semiconductor is doped with atoms from the group III of the periodic table that has three valence electrons, such as boron (B), gallium (Ga), indium (In), and aluminum (Al). The ionization energy is ΔEAV(B) = 45 meV, ΔEAV(Al) = 57 meV, and ΔEAV(In) = 160 meV. Therefore, at room temperature, there is essentially complete ionization of the acceptor atoms. Each acceptor atom accepts an electron from the valence band. The p-type impurities are called acceptors because they accept electrons, thus producing holes. A hole is a missing electron in a crystal structure. There is an excess of holes in the covalent bounding structure. Figure 17.8 shows an acceptor in a p-type semiconductor. Holes are the majority carriers and electrons are the minority carriers. The concentration of the majority holes is pp and the concentration of the minority electrons is np. Intrinsic semiconductors doped with acceptors have many holes and few free mobile electrons. Even though there are holes in the valence bands, the number of protons and electrons remains the same. Therefore, the net charge is zero, and the material is electrically neutral.

Figure 17.8 Acceptor in a p-type semiconductor. For p-type semiconductors with ND = 0, N+A ≈ NA, p = pp, n = np, Q− = q(np + N+A) ≈ q(np + NA), Q+ = qpp, and np + NA = pp. Since the concentration of acceptors NA ni and the majority hole concentration pp is approximately equal to the acceptor density NA, we obtain (17.42) Using the law of mass action, (17.43) which produces (17.44) and (17.45)

Similarly, (17.46) resulting in

(17.47) which produces the minority electron concentration (17.48)

The conductivity of the p-type semiconductor is directly proportional to acceptor concentration NA (17.49) For acceptor doping concentration NA = 1014 cm− 3 in silicon at room temperature, (17.50) Both minority concentrations pn and np are strongly dependent on temperature T because the intrinsic electron and hole concentrations ni and pi are strong functions of temperature. Therefore, the properties of minority (bipolar) devices are strongly dependent on temperature T. In contrast, the properties of majority (unipolar) devices are weakly dependent on temperature T. This is because the concentrations of ionized impurities are very close to the total impurity concentrations ND and NA at room temperature.

17.7.3 Maximum Operating Temperature Figure 17.7 shows plots of ND, ni, nn, and pn as functions of temperature T for n-type silicon with doping concentration ND = 1015 cm− 3. At low temperatures, ND ni and the semiconductor is extrinsic of n-type. As the temperature increases, the increased thermal energy ionizes a significant number of the semiconductor atoms, generating additional electrons and holes. At sufficiently high temperatures, the number of holes is approximately equal to the number of free electrons. As a result, the difference between the n and p-regions disappears and the extrinsic semiconductor becomes an intrinsic semiconductor. The temperature at which the doped semiconductor becomes an intrinsic semiconductor is called the maximum extrinsic temperature. At sufficiently high temperatures, all extrinsic semiconductors become intrinsic because of the increase in the EHP concentration ni above the doping concentration with temperature (n → ni and p → ni). The concentration of dopants does not dominate the electrical property of the semiconductor at high temperatures. For example, the pn junction does not favor carrier movement in only one direction across the junction. The pn junction becomes a resistor and does not control the carrier flow in one direction only. The leakage current becomes very large. The upper inherent temperature limit of each semiconductor

material is determined by its band gap energy EG at a fixed doping level. Semiconductor devices do not operate properly above the upper limit of the extrinsic temperature, called the maximum extrinsic temperature at which pn = 0.1nn, resulting in ni = 0.35ND for the n-region, or np = 0.1pp, resulting in ni = 0.35NA for the p-region. All semiconductor devices have a maximum operating temperature TJmax. At high temperatures, semiconductor devices loose their structures. Figure 17.9 shows plots of ND, ni, nn, and pn as functions of temperature T for n-type silicon and silicon carbide with doping concentration ND = 1015 cm− 3. For silicon, Ti(Si) ≈ 320°C and for silicon carbide, Ti(SiC) ≈ 1100°C at ND = 1015 cm− 3.

Figure 17.9 Donor concentration ND, intrinsic carrier concentration of silicon ni(Si), electron concentration for silicon nn(Si), hole concentration for silicon pn(Si), intrinsic carrier concentration of silicon-carbide ni(SiC), electron concentration for silicon-carbide nn(SiC), and hole concentration for silicon-carbide pn(SiC) as functions of temperature T for n-type semiconductors with ND = 1015 cm− 3. The maximum operating temperature of semiconductor devices is also frequently determined

by interconnections and packaging. High-temperature electronics is used in probes that are sent deep into bore holes of petroleum and geothermal wells as well as in aircraft with trend toward“fly-by-wire” systems. In many applications, electronic circuits should be co-located with monitoring and control transducers and actuators for jet aircraft engines.

17.8 Wide Band Gap Semiconductors Table 17.2 gives the band gap energy EG for various semiconductors and the silicon dioxide (SiO2). Diamond, boron nitride, and silicon carbide are excellent insulators at T = 300 K. However, they can be used as semiconductors at high temperatures, typically in the range 200– 600°C. Wide band gap (WBG) semiconductors have the energy band gap EG greater than 1.7 eV. WBG semiconductors permit power devices to operate at much higher voltages, frequencies, and temperatures than their silicon counterparts [21]. In addition, WBG semiconductors allow for designing smaller, faster, more efficient, and more reliable power devices than the silicon components. The breakdown voltage of WBG semiconductor power devices is 10 times higher than that of comparable silicon devices. The operating frequencies can be also 10 times higher than that of silicon devices. The operating temperatures can be above 300°C. Therefore, WBG devices can operate in harsh and high-temperature applications. Table 17.2 Band gap energies EG for semiconductors and silicon oxide Material

EG (eV) EG (J)

Germanium (Ge)

0.66

1.05 × 10−19

Silicon (Si)

1.12

1.79 × 10−19

Indium phosphide (InP)

1.35

2.16 × 10−19

Gallium arsenide (GaAs) 1.42

2.27 × 10−19

Cadmium selenide (CdSe) 1.70

2.72 × 10−19

Silicon carbide (SiC)

3.26

5.22 × 10−19

Zinc oxide (ZnO)

3.40

5.44 × 10−19

Gallium nitride (GaN)

3.39

5.53 × 10−19

Diamond (C)

5.47

8.76 × 10−19

Aluminum nitride (AlN)

6.20

9.93 × 10−19

Boron nitride (BN)

7.50

12.015 × 10−19

Silicon dioxide (SiO2)

9.00

14.418 × 10−19

WGB semiconductors emit electromagnetic waves in the visible range. This allows for developing the solid-state lighting. WBG light-emitting diodes (LEDs) produce more then 10

times light per watt and have lifetime 30 times longer than corresponding incandescent bulbs. A shell structure of the carbon atom is depicted in Figure 17.10. Silicon carbide is a chemical of group IV–IV compound of silicon and carbide. Its subshell configuration is 1s22s22p2. Two WBG semiconductors are used to fabricate power devices: silicon carbide (SiC) and gallium nitride (GaN). Table 17.3 compares electrical and thermal properties of silicon (Si), silicon carbide (4H-SiC), and gallium nitride (GaN) at T = 300 K. Silicon has low band gap energy EG, low maximum operating junction temperature TJmax, low breakdown (or critical) electric field intensity EBD (also called dielectric strength), low saturation average carrier drift velocity vsat, low thermal conductivity, high availability, low cost, and low melting point. Silicon is available as a natural mineral. The band gap energy EG is the energy required to rise an electron from the valence band to the conduction band in a given semiconductor. Silicon dioxide (SiO2) is a good insulator. It is a crystal in the form of glass. Silicon dioxide is used to form the most critical regions in the device structure, such as the gate oxide in a MOSFET. It is not available as a natural mineral.

Figure 17.10 Shell structure of carbon atom.

Table 17.3 Properties of silicon (Si), silicon carbide (4H-SiC), and gallium nitride (GaN) at T = 300 K and ND = 1015 cm− 3 Property Band gap energy

Sym. Unit EG eV

Si 1.12

4H-SiC 3.26

GaN 3.39

Breakdown electric field

EBD V/cm

2 × 105

2.2 × 106

3.5 × 106

Dielectric constant

εr

−

11.7

9.7

8.9

Electron mobility at T = 300 K

μn

cm2/V • s 1360

900

2000

Hole mobility at T = 300 K

μp

cm2/V • s 480

120

300

Surface mobility μs at T = 300 K μns

cm2/V • s 600

400

660

Saturation electron drift velocity vsat

cm/s

8 × 106

2.7 × 107

2.5 × 107

Intrinsic concentr. at T = 300 K ni

cm− 3

0.66 × 1010 0.49 × 10− 8 10− 10

Maximum junction temperature

TJmax °C

Thermal conductivity

kth

200

600

620

W/K • cm 1.5

4.56

2.2

The desirable properties of semiconductor materials are: high EG, high EBD, high vsat, high TJmax, low εr, and large kth. Silicon carbide has high band gap energy EG, high breakdown electric field intensity EBD, high maximum operating junction temperature TJmax, high average carrier drift saturation velocity vsat, high thermal conductivity, excellent thermal stability, high physical strength, and high chemical inertness. It has a strong covalent bonding. A higher breakdown (critical) electric field EBD allows for thinner and more highly doped devices. Since they can be made thinner and doped higher, faster devices can be built. In WBD semiconductors, the intrinsic carrier density ni is extremely small. For SiC, ni ≈ 10− 8 cm− 3 at room temperature. Silicon carbide is capable of operating at high radiation levels in harsh environments. Silicon carbide is an excellent semiconductor to fabricate high-voltage, hightemperature, and high-frequency power devices. A higher breakdown electric field intensity EBD allows for higher doping concentration, thinner drift region, lower specific on-resistance, and smaller die size for a given breakdown voltage VBD. The doping levels can be in the range 5 × 1015 cm− 3 – 1019 cm− 3. It also allows power devices to have higher breakdown voltages. A higher saturation carrier drift velocity yields higher operating frequencies suitable for high power RF applications. SiC power devices are 30 times faster than Si power devices. High operating temperatures make SiC devices suitable for applications in power supplies, electrical motor controls, car engine sensors, jet engine sensors, spacecraft electronics, energy storage, pulse power, utilities, intelligent machinery, locomotives, oil drilling equipment, chemical reaction monitoring, combustion control, and manufacturing. Thermal management for silicon-carbide devices is much easier than that for silicon devices due to higher thermal conductivity and higher maximum junction temperature, enabling a much easier heat transfer

from SiC devices. Due to a wide SiC energy band gap EG, that is, approximately three times wider than that of Si, the maximum junction temperature TJmax for SiC is projected to be approximately three times higher than that of Si. Silicon carbide has many polytypes, such as 3H-SiC, 4H-SiC, and 6H-SiC. However, the 4H-SiC polytype is preferred because of higher electron mobility μn. The mobility of 4H-SiC is twice as high at that of 6H-SiC. Its much lower thermal minority carrier generation results in lower leakage currents. SiC is currently the most promising material for fabricating high-voltage high-temperature power semiconductor devices. The thermal resistance of a SiC plate of thickness h, cross-sectional area A, and thermal conductivity kth is given by (17.51) Thus, the thermal resistance of an SiC plate is three times lower than that of an Si plate of the same dimensions. The parameters of germanium (Ge) are: EG = 0.67 eV, μn = 3900 cm2/V • s, μp = 1900 cm2/V• s, ni = 2.4 × 1013 cm− 3 at T = 300 K, and kth = 0.58 W/K• cm. Gallium nitride (GaN) is a III–V compound semiconductor. It has very promising properties for new generation of semiconductor devices, such as high electron mobility transistors (HEMTs). The energy band gap is EG = 3.42 eV, which is three times higher than that of silicon, yielding reduced performance degradation at high temperatures. The breakdown electric field intensity is EBD = 3.5 × 106 V/cm. The saturation electron velocity is vsat = 2.5 × 107 cm/s, resulting in much higher speed and greater power density. The intrinsic carrier concentration is ni = 10− 8 cm− 3 at room temperature. The electron mobility is μe = 2000 cm2/V• s. The thermal conductivity is kth = 2.3 W/K • cm.

17.9 Physical Structure of Junction Diodes There are two categories of power diodes: pn junction diodes (also called bipolar diodes) Schottky diodes (also called Schottky barrier diodes (SBDs)). Power diodes are made of silicon (Si) or silicon carbide (SiC). A cross section of a pn junction diode is depicted in Figure 17.11. The pn junction diode is formed within a singlecrystal semiconductor by doping n-region with donors ND and an adjacent p-region with acceptors NA. Donor atoms have five valence electrons and acceptor atoms have three valence electrons. The dopants commonly used for power device fabrication are from group V such as phosphorus (P), arsenic (As), and antimony (Sb) for the n-type region and from group V such as boron (B), gallium (Ga), indium (In), and aluminum (Al) for the p-type region. Example of

doping levels are NA = 1017 cm− 3, ND = 1015 cm− 3, and ND(sub) = 1019 cm− 3. The function of the lightly doped n− drift region is to absorb the depletion region at high reverse voltages (vD < 0) and prevent the diode voltage breakdown. Its thickness xn is between 10 and 200 μm. The drift region should be made of an n-type semiconductor because electrons have a higher mobility than holes (μn > μp), reducing the on-state resistance of the diode. A substrate is a semiconductor wafer used as a starting material for further device construction. The thickness of the n+ substrate is in the range 250– 500 μm to maintain the diode mechanical integrity. Single crystals are grown using the Czochralski method and sliced into wafers that are turned into substrates on which semiconductor devices are made. Highly doped substrate n+ and p+ region form non-rectifying semiconductor–metal contacts.

Figure 17.11 Cross section of pn junction diodes. (a) Cross section. (b) Symbol. Figure 17.12 shows a physical structure of a p+ n junction diode, along with the profiles of doping concentration N, space-charge density ρ, and electric field intensity E. The one-sided diode consists of anode metal contact, highly doped p+ region, depletion region, lightly doped

n− drift region, highly doped n+ substrate, and cathode metal contact. The p-side is doped with NA acceptors/cm3, and the n-side is doped with ND donors/cm3. For a step junction, the doping concentration is uniform in each region and the concentration change at the metallurgical junction is abrupt. The p+ and n− regions outside the depletion region are called quasi-neutral regions. The highly doped p+ and n+ regions form non-rectifying ohmic metal–semiconductor contacts. The resistance of the metal–semiconductor contact should be made as low as possible to reduce the on-state voltage drop during forward current conduction. The typical value of the ohmic contact resistance is 10− 5 Ω/ cm2 = 1 mΩ/mm2. A highly doped n+ and p+ regions have a low barrier height. Above 50 K, nearly all dopant atoms are ionized, resulting in constant values of ND and NA at all practical operating temperatures. A diode is connected to the package by metallization. A metal film is deposited on the surface of the heavily doped semiconductor layer by sputtering (Al) or by evaporation (Au or GaAs).

Figure 17.12 Physical structure of p+ n step junction diodes, doping concentration profile, space-charge density ρ, electric field intensity E, and electrostatic potential V(x).

17.9.1 Formation of Depletion Layer When n-type and p-type semiconductors are placed together to form a pn junction, free electrons diffuse from the n-doped region to the p-doped region, and holes diffuse from the pdoped region to the n-doped region. Since there is a large population of holes in the p-region, the diffused electrons recombine with the holes and both vanish. Thus, the electrons injected from the n-side into the p-side are eliminated by recombination with the holes. When an electron moves from the n-side to the p-side, it leaves behind a positively charged uncompensated immobile donor ion N+D on the n-side. Since the acceptor atom in the p-region near the junction gains one electron, it represents a negative charge. Similarly, when a hole moves from the p-side to the n-side, it leaves behind a negatively charged uncompensated immobile acceptor ion N−A on the p-side. The holes injected from the p-side into the n-side are eliminated by recombination with electrons. The region around the pn junction is depleted of mobile free electrons and holes. As a result, a depletion layer, (also called depletion region, or space charge region) is formed, which contains the negatively charged ions N−A on the pside adjacent to the pn junction interface and the positively charged ions N+D on the n-side adjacent to the interface. A region of the positive space charge is created on the n-side near the junction and a negative space charge is created on the p-side near the junction. Therefore, an electric field intensity E is induced, which is directed from the positive space charge on the nside to the negative space charge on the p-side. This field creates a barrier potential or a built-in potential barrier Vbi across the junction at zero biasing, which opposes the exchange of charge carriers by diffusion. The electric field E forces a drift component of the current from n to p-region, opposing a diffusion component of the current. At vD = 0, the drift current cancels out the diffusion current, resulting in a zero diode current. The net charge in the depletion layer is zero. Therefore, the area of the rectangles in Figure 17.12 are the same. The voltage across the junction is VJ = Vbi − vD. At vD = 0, the net sum of the built-in potential and the metal–semiconductor contact potentials is zero. Therefore, the built-in potential is Vbi = − (Vmn + Vpn). In summary, a donor loses an electron and becomes a positive ion N+D in the nregion near the pn junction, and an acceptor gains an electron and becomes a negative ion N−A in the p-region near the pn junction. Both n-type and p-type semiconductors are called extrinsic because their electrical properties are determined mainly by the dopants: donors and acceptors. For asymmetrically doped (or one-sided) p+ n junctions, NA ND, for example, NA = 1017 cm− 3 and ND = 1015 cm− 3. The electric field E in the depletion region is directed from the positive charge toward the negative charge. The bulk of the n-side is electrically neutral because there are about the same number of electrons and positive donor ions. Similarly, the bulk of the p-side is electrically neutral because there are about the same number of holes and negative acceptor ions. However, the electrons that are near the junction will diffuse away from the region of high electron concentration on the n-side to the region of low electron concentration on the p-side. Likewise, the holes will diffuse from the region of high hole concentration of the p-region to the region of

low hole concentration on the n-side. This will create a thin depletion region, also called the depletion layer. The electron leaves a positive donor ion N+D behind on the n-side and a hole leaves a negative acceptor ion N−A on the p-side. There is no mobile charges in the depletion region. The electrons injected into the p-side recombine with holes and the holes injected into the n-side recombine with electrons. The uncompensated positive ions on the n-side and the uncompensated negative ions on the p-side induce an electric field E in the depletion region and a junction voltage across the depletion region. The mobile carrier density is approximately zero in the depletion region (for vD ≤ 0). The electric field E = −ixE = −ixdV/dx is pointing from the n-side to the p-side and is non-uniform in the depletion region, reaching its peak value Em at the junction. The peak value of electric field intensity Em must be kept below the breakdown value EBD. There is no immobile charge and electric field outside the depletion region.

17.9.2 Charge Transport The charge transport in semiconductor devices takes place through two mechanisms: 1) drift current and 2) diffusion current. Diffusion is a process in which electrons and holes flow from a region of high concentration toward the region of low concentration. The diffusion current is a current that is caused by diffusion of charged current carriers. Drift is the process in which electrons and holes move due to the presence of an electric field E. The drift current Jdrift is caused by the electric field E due to Coulomb’s force on charge carriers, like the current conduction described by Ohm’s law. The electrostatic force exerted on an electron is F = −qE. By Newton’s law of motion, the acceleration of an electron of mass me between collisions is a = F/me = −qE/me. The velocity of electrons is ve = at = −qEt/me for low values of electric field intensity E. Actually, the electrostatic force F causes the carriers to first accelerate and then reach a constant saturation velocity vsat. The average position change davg of a group of N electrons or holes in time interval Δt is called the average drift velocity vd = davg/Δt = (x1 + x2 + + xN)/(NΔt). The mobility is the ratio of the drift velocity to the applied electric field intensity. The drift velocity of electrons is vn = −μnE and the drift velocity of holes is vp = μpE. The volume electron density is ρvn = −qn, and the volume hole density is ρvp = qp. The drift current density of electrons is Jdrift(n) = ρvnvn = −( − qn)μnE = qnμnE = σnE, and the drift current density of holes is Jdrift(p) = ρvpvp = qpμpE = σpE. The diffusion current density Jdiff is caused by diffusion of electrons and holes due to carrier concentration gradient. Assuming a one-dimensional model, the diode current density due to electron flow is (17.52) and the diode current density due to hole flow is (17.53)

where Dn = kTμn/q and Dp = kTμp/q are the diffusion coefficients for electrons and holes, respectively. The current density equation for electrons and holes is (17.54)

In p+ n junctions, the flow of holes is dominant and J ≈ Jp. Conversely, in n+ p junctions, the flow of electrons is dominant and J ≈ Jn. At high values of electric field intensity E, the drift current saturates and becomes independent of the electric field intensity E. For the forward bias of the diode (vD > 0), the depletion region narrows and the barrier potential decreases, causing a large forward current to flow from the p-side to the n-side. Electrons flow from the n-side into the p-side and holes flow from the p-side into the n-side across the depletion region by diffusion. The forward diode current is due to diffusion and recombination charge carriers. The diffusion current increases exponentially with the bias voltage vD and is much larger than the drift current (Jdiff Jdrift). For the reverse bias of the diode (vD < 0), the potential barrier across the junction increases, the depletion layer widens, and a low reverse saturation current IS flows from the n-side to the p-side. The diffusion current decreases to zero and the drift current is dominant (Jdrift Jdiff ). Under reverse bias conditions (vD < 0), the diode current is very small, ID = −IS for vD < −1.5 V. Electrons flow from the p-side into the n-side and holes flow from the n-side into the p-side. However, these are minority carriers. There are few electrons on the p-side and few holes on the n-side. The reverse diode current is due to EHP generation and drift of charge carriers by electric field E.

17.10 Static I–V Diode Characteristic The static diode characteristic consists of the forward-bias region, reverse-bias region, and breakdown region. The Shockley static diode equation for the forward and reverse-biased regions is given by (17.55) where the thermal voltage is (17.56) VT = 25.852 mV at room temperature T = 27°C, k = 1.38 × 10− 23 J/K is Boltzmann’s constant, q = 1.60218 × 10− 19 C is the magnitude of the electron charge, T(K) = 273 + T(°C) is the temperature, n is the emission coefficient, n = 1 for low-level injection and n = 2 for high-

level injection, and IS is the reverse saturation current. The reverse saturation current IS increases with increasing temperature T and is given by (17.57) where AJ is the junction cross-sectional area, pn0 = n2i/ND is the concentration of holes in the n-region, np0 = n2i/NA is the concentration of electrons in the p-region, Dn = μnVT = μnkT/q and Dp = μpVT = μpkT/q are diffusion coefficients for electrons and holes,

and

are diffusion lengths for electrons and holes, and τn and τp are the average lifetimes of minority electrons and holes, respectively. It appears that τn = 1/(αrnpo) = nn/(αrn2i) = NA/(αrn2i) and τp = 1/(αrpno) = pp/(αrn2i) = ND/(αrn2i), where αr is the recombination coefficient. The reverse saturation current IS is proportional to the junction cross-sectional area AJ and to n2i. Therefore, τn/τp = pno/npo = NA/ND. For silicon at T = 300 K, ni = 0.17309 × 1010 cm− 3, Dn = μnVT = 1360 × 0.025852 = 35.15872 cm2/s, and Dp = μpVT = 480 × 0.025852 = 12.40896 cm2/s. For a diode with AJ = 1 cm2, NA = 1016 cm− 3, ND = 1014 cm− 3, and T = 300 K, we obtain pn0 = n2i/ND = (0.17309 × 1010)2/1014 = 0.02996 × 106 cm− 3, np0 = n2i/NA = (0.17309 × 1010)2/1016 = 0.02996 × 104 cm− 3, and τn/τp = pno/npo = NA/ND = 1016/1014 = 100. Assuming τn = 10 μs and τp = 1 μs, τp = 0.1 μs, cm = 187.5 μm and cm = 11.14 μm. at T = 300 K, b = 1.7855 × 10− 37 A and the saturation current (17.58)

Typically, IS = 10− 14 A for small-signal silicon pn junction diodes, IS = 10− 9 A for silicon pn junction power diodes, IS = 10− 5 A for silicon Schottky power diodes, and IS = 10− 20 A for silicon-carbide Schottky power diodes. The reverse saturation current IS doubles for every 10°C increase in junction temperature. This dependence can be approximated by (17.59) As the temperature T increases from 30°C to 150°C, the saturation current IS increases by a factor of IS(150)/IS(30) = 212 = 4096.

Figures 17.13 and 17.14 shows silicon and silicon-carbide static diode characteristics at three temperatures T. The threshold voltage VF of silicon diodes decreases with the increasing temperature T. The thermal coefficient of the threshold voltage for silicon pn junction diodes is given by (17.60) For every 1°C increase in temperature, VF decreases by approximately 2 mV. For siliconcarbide diodes, the threshold voltage decreases with temperature at very low diode currents, but it increases with temperature at high currents. The threshold voltage is expressed as (17.61) where VF0 is the threshold voltage at T = To.

Figure 17.13 Silicon static diode characteristics at three temperatures T.

Figure 17.14 Silicon-carbide static diode characteristics at three temperatures T. The neutral regions exhibit resistances determined by the doping level and dimensions. The resistance of the n− region is Rn and the resistance of the p+ region is Rp. The resistance of the n+ substrate is Rsub. The resistivity of the substrate is low, but its thickness is large to maintain the mechanical integrity, usually of the order of 250 to 500 μm. The resistance of the metal– semiconductor ohmic contacts is Rc. The total series resistance is (17.62) Neglecting the conductivity modulation, the resistance of the n−-region is (17.63) and the resistance of the p+ region is

(17.64) The bulk resistance of the neutral regions is (17.65) The substrate resistance is (17.66) The voltage drop across the diode is (17.67) At high diode currents, the voltage drop across the series resistance RS reduces the voltage drop across the junction VJ = VD − RSID, as shown in Figure 17.15. Therefore, the diode characteristic for high currents is given by (17.68) The reduction in junction voltage VJ lowers the excess carrier injection level and therefore the diode current increases more slowly with increasing voltage VD. The emission coefficient is n = 2.

Figure 17.15 The effect of the voltage drop RSID across the neutral regions and the metal– semiconductor contacts on the diode characteristic at high currents. At high-injection levels, high carrier concentrations reduce the resistivities of the neutral regions, reducing resistances Rn and Rp. The reduction of the resistivity resulting from high level of carrier injection is called conductivity modulation. This effect causes a significant reduction in the resistance of the drift region, reducing the conduction power loss. The diode equation for the high-injection range is given by (17.69) where IH is the high-injection parameter. The maximum diode forward current (17.70) where the maximum forward current density typically is JDmax = 100 A/cm2 = 1 A/mm2. The typical values of the active junction area AJ are from 0.01 to 1 cm2. For example, the junction area of the 15 A diode is 0.15 cm2. To achieve high forward current density, all parasitic resistances must be minimized. The static large-signal piecewise-linear model of a diode consists of an ideal switch, a battery

VF, and a forward resistance RF connected in series, as depicted in Figure 17.16. The voltage across the conducting diode is

Figure 17.16 Piecewise-linear large-signal model of a diode. (17.71) If a line is drawn along the linear high-current portion of the ID–VD curve in the linear scale or in the semilog scale logID–VD extending to the VD-axis, the intercept on the VD-axis is VF and the slope is 1/RF, where RF = ΔVD/ΔID. At T = 300 K, the threshold voltage VF is typically 0.3 V for silicon (Si) Schottky diodes, 0.7 V for Si pn junction diodes, 1–1.5 V for silicon-carbide (SiC) Schottky diodes, and 2.5–2.8 V for SiC pn junction diodes. The forward resistance RF ranges from 15 to 150 mΩ. As the temperature increases, the forward resistance RF decreases for silicon diodes and increases for silicon-carbide diodes. The power loss in a diode is given by (17.72) For silicon-carbide pn junction diodes, the forward voltage drop is VON = 2.8 V, the leakage current is Il = 10− 10 to 10− 4 A, the maximum breakdown voltage is VBDmax = 5 kV, and the maximum junction temperature is TJmax = 400°C.

17.11 Breakdown Voltage of Junction Diodes A reverse-biased diode conducts a small reverse saturation current IS due to thermally generated EHPs. A hole is a missing electron in a crystal structure. As the diode reverse voltage starts to approach the reverse breakdown voltage VBD, the reverse current in the pn junction begins to increase. The breakdown is caused by two conduction mechanisms: the

avalanche breakdown and the Zener breakdown. The avalanche voltage breakdown is caused by impact ionization, which results in carrier multiplication. If either side of the junction is lightly doped, the breakdown mechanism involves the impact ionization. A high reverse-biased junction voltage produces a high electric field E in the depletion region. The electrostatic force acting on an electron is F = −qE. The electrons between the collisions experience a constant acceleration a = F/me = −qE/me, where me is the mass of an electron. The velocity of electrons between collisions is vn = −at = −qEt/me. The electron kinetic energy at the collision is Wk = mev2ec/2 = (qEtc)2/(2me), where tc is the time between collisions. As the applied reverse voltage increases, the electric field intensity E also increases, increasing the velocity of the carriers v = at. For silicon, the carrier velocity may reach the saturation drift velocity of vsat = 107 cm/s at the electric field intensity E = 102 V/cm. During a collision, a carrier may acquire enough kinetic energy from the electric field to break the covalent bond and release an electron, thus generating a free electron and a hole. The intense electric field E sweeps the electrons in one direction and the holes in the other. The newly generated carriers, before leaving the depletion region, are accelerated by the high electric field intensity E, collide with the fixed atoms, and generate new EHPs upon impact, which in turn generate new EHPs. This results in the multiplication of EHPs. For a sufficiently intense electric field E, in the range 2 × 105 V/cm for silicon, the impact-ionization process continues to the point, where a high avalanche diode current is established, causing the avalanche breakdown. Impact ionization is similar to a snow avalanche on a mountainside. The avalanche effect causes the junction breakdown at high voltages, usually for VBD ≥ 8 V. The avalanche breakdown occurs in lightly doped pn junctions, where the depletion region is long and electrons are accelerated to high speeds and are able to knock out other electrons. The breakdown voltage VBD increases as the doping decreases. The breakdown voltage VBD also increases with the band gap energy EG of the semiconductor because more energy is required to initiate impact ionization. The avalanche breakdown voltage VBD increases as the junction temperature TJ increases, resulting in a positive temperature coefficient ΔVBD/ΔT. For silicon, VBD doubles for every 10°C increase in junction temperature TJ. At high temperatures, the atoms oscillate with larger amplitudes. Hence, the average distance between collisions (the mean free path of charge carriers) is shorter at higher temperatures. For this reason, the rate of impact ionization is lower at higher temperatures, resulting in a higher avalanche breakdown voltage. The breakdown voltage is lower for linearly graded junction than that for the uniformly doped planar junctions. Zener breakdown occurs when both p and n-regions are heavily doped, which results in a very thin depletion region. The layer is so thin that the carriers passing through it do not have enough collisions to produce a significant number of secondary carriers. Tunneling of electrons through the depletion layer from the p-side of valence band to the n-side of the conduction band constitutes a reverse diode current flowing from the n-side to the p-side of the junction. If either side of the junction is lightly doped, the depletion region is too wide for electron

tunneling. The Zener effect causes the junction breakdown at low voltages, typically for VBD ≤ 5 V. The Zener breakdown voltage VBD decreases with increasing junction temperature TJ, resulting in the negative temperature coefficient. For breakdown voltages between 5 and 8 V both avalanche and Zener effects may be significant. The diode current in the vicinity of the breakdown voltage VBD is described by an empirical relationship (17.73)

where (17.74) is the multiplication factor and p = 2 – 6, depending on the type of material used for the junction. For p+ n junctions, p = 6. For n+ p junctions, p = 4. Neither of the two breakdown mechanisms is harmful to a junction. When taken out of breakdown, a diode behaves normally. However, the diode in the breakdown region is susceptible to damage due to overheating by the power loss PBD = IDVBD. For silicon diodes, the breakdown voltage VBD ranges from 2 to 2000 V. The avalanche process imposes an important limitation on the output voltage and the output power of semiconductor devices. Therefore, WBG energy semiconductors have been intensively studied to develop high-voltage, high-power devices. Silicon carbide (SiC) and gallium nitride (GaN) are good semiconductors for fabricating such devices.

17.11.1 Depletion-Layer Width In the vicinity of the junction, mobile electrons move out of the n-type region and leave behind immobile ionized donor atoms with a positive charge N+D. Similarly, mobile holes move out of the p-type semiconductor and leave behind immobile negatively charged acceptor atoms N−A. Therefore, the region on both sides of the junction is depleted of mobile carriers and is called depletion layer, depletion region, or space-charge region. The voltage across the diode vD changes the depletion region width W. The n-side and p-side depletion layer widths are given by (17.75)

and

(17.76)

where ε0 = 10− 9/(36 π) = 8.8542 × 10− 14 F/cm = 8.8542 × 10− 12 F/m, εr is the semiconductor dielectric constant, εr(Si) = 11.7 for Si, εr(SiC) = 9.7 for SiC, ln is the length of the n-region, lp is the length of the p-region, and Vbi is the built-in potential barrier or the barrier voltage expressed by (17.77) As the temperature T increases, Vbi decreases. The typical value of Vbi is 0.6–1 V for silicon diodes. The typical value of Vbi is 3 V for silicon-carbide diodes. The built-in potential Vbi is the difference in the potential between the n and p-sides, that is, it is equal to the voltage drop across the junction at vD = 0. As the intrinsic carrier concentration ni increases, Vbi decreases. For n2i = NAND, Vbi = 0. The voltage across the junction is VJ = Vbi − vD. The depletion-layer width is given by (17.78)

where the zero-bias depletion layer width is (17.79) As the temperature T increases, W decreases. The depletion region width W increases with increasing reverse-biased voltage − vD and it is larger for lower doping concentrations. As vD approaches Vbi, W approaches zero. Figure 17.17 shows the depletion region width W as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3.

Figure 17.17 Depletion region width W as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3. The depletion region width W increases with increasing reverse-biased voltage − vD and it is larger for lower doping concentrations. As vD approaches Vbi, W approaches zero. Figure 17.17 shows the depletion region width W as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3. The built-in potential Vbi determines the zerobias depletion region width W. The net charge in the depletion layer is zero. Hence, from the charge-equity condition, (17.80) resulting in (17.81)

where AJ is the cross-sectional area of the junction. The amount of negative charge per unit area in the p-region is equal to the amount of positive charge per unit area in the n-region. The ratios of the doping concentrations are (17.82)

(17.83) and (17.84) The depletion region extends further into a lightly doped semiconductor than it does into a heavily doped semiconductor. For p+ n junctions, ND NA, xn xp, that is, the junction is one-sided, and therefore (17.85)

For n+ p junctions, NA ND, xp xn, and therefore (17.86)

The inverse saturation current IS results from the thermal generation of EHPs in the depletion layer. Therefore, IS is proportional to the volume of the depletion layer (17.87) Hence, (17.88)

17.11.2 Electric Field Intensity Distribution Gauss’ law links the charge density ρ and the electric field intensity E

(17.89) The differential (or point) form of one-dimensional Gauss’ law is given by (17.90) yielding (17.91) and (17.92) For the step pn junction, the doping concentration in the n-type region ND and the doping concentration in the p-type region NA are uniform (constant) and the change of the concentration at the junction is abrupt, Therefore, the space charge is (17.93)

The electric field intensity in the neutral regions is (17.94) The electric field intensity distribution in the p-type region of the depletion layer is given by (17.95)

where E( − xp) = 0. This is because the electric field intensity in the neutral p-type region is zero and is a continuous function. The electric field intensity at the edge of the n-type region of the depletion layer is (17.96) Hence,

(17.97) For the uniformly doped pn junction, the electric field intensity in the depletion region is a linear function of distance. An electric field exists in the depletion region even if the applied bias voltage is zero (i.e., with a short circuit). The maximum electric field strength Em occurs at the interface between the p-region and the nregion. This field at a diode voltage vD is given by (17.98)

For ND NA, (17.99) Figure 17.18 shows the maximum electric field intensity Em as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3. The maximum electric field intensity Em increases with the increasing reverse-biased voltage vD. As the doping concentration ND decreases, Em also decreases at any applied voltage vD.

Figure 17.18 Maximum electric field intensity Em as a function of the diode voltage vD at selected doping concentrations ND for NA = 1017 cm− 3. Poisson’s equation links the electric potential V and the charge density ρ. This equation for 1D is (17.100) Since the electric field intensity at any point x is the negative of the electrostatic potential gradient at that point (17.101) we have (17.102)

Integrating both sides of this equation, we obtain the voltage distribution in the depletion region. The voltage distribution in the p-type region of the depletion layer is given by (17.103)

where the electrostatic potential of the p-type bulk region in thermal equilibrium is (17.104) A p-type semiconductor has a negative electrostatic potential with respect to intrinsic semiconductor. The voltage at the edge of the n-region of the depletion layer is (17.105)

Hence, the voltage distribution in the n-type region of the depletion layer is given by (17.106) where the electrostatic potential of the n-type bulk region in thermal equilibrium is (17.107) An n-type semiconductor has a positive electrostatic potential with respect to intrinsic semiconductor. The voltage distribution in the depletion layer is described by two parabolas and is constant in the neutral regions. The built-in potential is given by (17.108) Figure 17.12 illustrates potentials Vp, Vn, and Vbi. The built-in potential barrier is (17.109) Hence, for vD = 0,

(17.110) The contact potential occurs between any dissimilar pair of materials because of the difference in the potential energy of the conduction electrons, that is, the difference between their work functions. The metal–semiconductor structure can form an ohmic contact. The metal– semiconductor ohmic contact has no rectifying properties and behaves like a battery, whose potential drop is not a function of the forward or reverse current through it. It presents no barrier to electron and hole flow in either direction. The metal–semiconductor ohmic contact has a constant potential and a very low resistance. It requires a heavy doping concentration in the semiconductor. The metal-to-p-type semiconductor ohmic contact voltage drop is Vpm and the n-type semiconductor-to-metal ohmic contact voltage drop is Vmn. For vD = 0, the junction voltage is equal to the potential barrier height between the p and n regions (17.111) When a diode voltage vD is applied, the junction voltage is given by (17.112) The metal–semiconductor ohmic contact potentials Vpm and Vmn are unaffected by the diode applied voltage vD. The flow of diode current can be controlled by controlling the potential barrier height. When vD is negative, the potential barrier height is high and the reverse diode current is very low. The voltage drop across the reverse-biased junction is VJ = Vbi − VD = Vbi + |VD|, where VD < 0. When vD is positive and sufficiently high, the potential barrier height is low and the forward diode current is large. The voltage drop across the forward-biased junction is VJ = Vbi + VD − IDRS, where VD > 0.

17.11.3 Avalanche Breakdown Voltage When Em approaches the breakdown (or critical) electric field intensity EBD, the avalanche breakdown occurs. Setting Em = EBD and vD = −VBD, we obtain the diode avalanche breakdown voltage of a step pn junction with uniform electric field distribution (17.113)

Figure 17.19 shows the breakdown voltage VBD as a function of doping concentration ND at NA = 1017 cm− 3 for silicon and silicon carbide. For ND NA, (17.114)

Reducing the doping concentration on the lightly doped side allows the diode to support higher voltages. Usually, doping levels below 1015 cm− 3 are necessary to achieve high breakdown voltages for silicon.

Figure 17.19 Breakdown voltage VBD as a function of doping concentration ND at NA = 1017 cm− 3 for silicon and silicon-carbide diodes. For silicon, EBD = 2 × 105 V/cm (theoretically, EBD = 3 × 105 V/cm for silicon). The breakdown electric field EBD of a semiconductor increases with increasing band gap energy EG. The breakdown voltage VBD can be increased by using semiconductors with a higher breakdown electrical field strength EBD, such as silicon carbide, which has EBD = 22 × 105 V/cm. Assuming the same doping concentration ND for silicon and silicon-carbide diodes, (17.115)

Figure 17.20 shows the electric field intensity distribution for two levels of doping concentration ND.

Figure 17.20 Electric field intensity distribution for two levels of doping concentration ND. The maximum doping concentration on the lightly doped side of the p+ n junction is (17.116) The maximum donor concentration NDmax must be decreased to achieve a higher breakdown voltage VBD. For silicon p+ n junction, the maximum doping concentration in the n-region is given by (17.117) For silicon-carbide p+ n junction, the maximum doping concentration in the n-region is (17.118) The ratio of the maximum values of doping for silicon carbide to silicon at the same

breakdown voltage is (17.119) Hence, the ratio of resistivities at the same breakdown voltage is (17.120) Substitution of (17.116) into (17.75) produces the length of the n-region at the breakdown voltage vD = −VBD and ND = NDmax for p+ n junction (17.121) For ND NA, (17.122) In practice, ND should be lower than NDmax to provide for a safety factor.

17.11.4 Punch-Through Breakdown Voltage Figure 17.21 illustrates punch-through breakdown voltage of pn junction. When the depletion region reaches one of the edges of the semiconductor neutral regions, the diode current begins to increase very rapidly, causing punch-through voltage breakdown. If the breakdown occurs on the n-side first (like in p+ n diodes), the maximum length of the depletion layer on the n-side at vD = −VBD is (17.123)

The diode must be designed so that ND < NDmax. The maximum length of the depletion layer on the n-side at ND < NDmax is (17.124)

Hence,

(17.125) yielding (17.126) where a = 1.1 –1.25. Substitution of vD = −VBD(PT) into (17.75) produces the minimum length of the n-side of the neutral region (17.127)

The n-region should be longer than xn(max). Thus, ln = bxn(max), where b = 1.1 –1.2. The punchthrough breakdown voltage is (17.128) For p+ n junction, ND NA, and the punch-through breakdown voltage is (17.129) Most diodes are designed to avoid the punch-through voltage breakdown and the maximum reverse voltage is limited by the avalanche breakdown. A non-punch-through drift region corresponds to the case where the drift region thickness is equal or larger than the parallelplane avalanche breakdown width.

Figure 17.21 Electric field intensity distribution in pn junction, illustrating punch-through breakdown voltage when xn = ln. In high voltage diodes, the n− region is so lightly doped that it is nearly intrinsic region. This type of a device is called a pin diode. The electric field intensity is nearly constant in the iregion, reducing the length ln by a factor of two at the same breakdown voltage. Using (17.75) and (17.128) and setting VBD = VBD(PT) and xn = ln, we obtain (17.130) From (17.113), the breakdown voltage can be expressed as (17.131)

Hence, the minimum length of the n-region at the maximum doping concentration is (17.132) The ratio of the drift length of the silicon diode ln(Si) to the drift length of the silicon-carbide diode ln(SiC) at the same breakdown voltage VBD is given by

(17.133)

17.11.5 Edge Terminations So far only parallel-plate (infinitely flat) pn junctions were considered and therefore edge effects were neglected. Actual junctions are manufactured using masks and diffusions of impurities, resulting in pn junctions with curvature. Therefore, the electric field intensity E in the depletion region is nonuniform and has the highest values in the areas with the shortest radius of curvature, reducing the breakdown voltage. By Coulomb’s law, the charge density is the largest at the junction edges. because the charge tends to concentrate at sharp points. The edge effects limit the breakdown voltage of practical diffused pn junctions to values lower than those set by ideal infinitely flat junctions. The electric field concentration occurs at the junction curvature, resulting in a severe reduction in the breakdown voltage. If the junction is poorly terminated, the breakdown voltage can be as low as 20% of the breakdown voltage of the ideal diode. Since the charge balance between the two sides of the junction must be satisfied, the junction curvature leads to electric field crowding as illustrated in Figure 17.22(a). A higher electric field intensity at the junction edges causes larger impact ionization in these areas. Consequently, the junction breakdown occurs at the edges rather than in the parallel-plane portion.

Figure 17.22 Electric field distribution in the pn junction without and with guard ring. (a) Electric field concentration at the corner. (b) More evenly distributed electric field in the diode with guard ring. An effective edge termination technique makes the electric field distribution more uniform at the edges of the diode in order to approach the breakdown voltage of an ideal diode with uniform electric field distribution. Many techniques use guard rings, floating field rings, trench rings, and junction termination extension have been used to achieve this objective. To achieve near-ideal breakdown voltage, an implanted boron edge termination can be used around the device. Figure 17.22(b) shows a guard ring, resulting in a more even distribution of electric field [3]. Multiple guard ring and field plate terminations are also used to reduce high concentrations of the electric field. Figure 17.23 shows the depletion region in a diode with multiple guard rings. The width and the spacing between individual floating rings are reduced with increasing distance from the main junction. Therefore, the depletion region thickness below them becomes progressively smaller. This allows the diode to achieve up to 80% of the breakdown voltage of an ideal parallel plane junction. Beveled edge junction terminations can be used in large diodes to reduce surface electric field. Defects in the semiconductor structure

reduce the junction breakdown voltage.

Figure 17.23 Depletion region profile in the pn junction diode with multiple guard ring termination.

17.12 Capacitances of Junction Diodes Power diodes are often used as electronic switches. Therefore, important parameters are their off-to-on and on-to-off transitions. There are charges stored in the depletion region and in the neutral regions. As a result, there are two capacitances in the pn junction diode model: the junction capacitance CJ and the diffusion capacitance CD. The junction capacitance CJ is dominant in the reverse-biased region and the diffusion capacitance CD is dominant in the forward-biased region.

17.12.1 Junction Capacitance In the reverse-biased region, the depletion region does not contain free carriers and behaves like an insulator between the neutral n and p-regions. This situation is similar to a parallelplate capacitor with capacitance C = εrε0AJ/W. As the reverse voltage increases by ΔvD, the separation of the small-signal junction capacitance plates increases by Δ(xn + xp), the depletion width on the n-side increases by Δxn and on the p-side by Δxp, the charge stored on either side of the depletion layer increases by ΔQ, as shown in Figure 17.24. The junction capacitance can be expressed as (17.134) It turns out that the incremental junction capacitance CJ = ΔQ/(ΔvD) decreases steadily as vD

decreases to more negative values.

Figure 17.24 Changes in the charge stored in the depletion region and the depletion region width due to the diode voltage change ΔvD (usually for the reverse bias). The changes in the stored charge ΔQJn and the depletion region width on n-side Δxn results in the junction capacitance CJ. There is a voltage-dependent charge associated with the depletion region. The immobile depletion charge is stored on both sides of the junction. The immobile positive depletion charge due to donor ions that have been stripped of their mobile electrons is stored on the nside of the depletion region in the volume xnAJ. This charge is given by (17.135)

Figure 17.25 shows plots of QJn, CJ, and WCJ as functions of vD.

Figure 17.25 Charge QJn, junction capacitance CJ, and energy stored in the junction capacitance WCJ as functions of diode voltage vD. (a) Charge stored in the depletion region on the n-side. (b) Junction capacitance CJ. (c) Energy stored in the junction capacitance WCJ. The charge QJn changes with the diode voltage vD, resulting in the junction capacitance. The charge |QJn| increases as the diode voltage vD decreases. The small-signal (incremental) junction capacitance CJ is the modulus of the slope of the QJn-vD curve CJ = ΔQJn/(ΔvD) at the operating point vD = VD. For step junctions, the small-signal capacitance is (17.136)

where CJ0 is the small-signal zero-bias junction capacitance at vD = 0

(17.137)

and Vbi is the built-in potential ranging from 0.55 to 1 V for silicon junction diodes, Vbi = 0.5 V for silicon Schottky diodes, and Vbi = 1.1 V for silicon-carbide Schottky diodes. The expression CJ = εAJ/W is identical to that of the capacitance of two closely spaced parallel plates separated by a distance W by a dielectric of permittivity ε = εrε0. The diode voltage VD modulates the separation W between the capacitor plates. Figure 17.26 shows a plot of the junction capacitance CJ as a function of diode voltage vD for Vbi = 0.75 V, ND = 1015 cm− 3, and AJ = 4 mm2.

Figure 17.26 Junction capacitance CJ as a function of diode voltage vD for Vbi = 0.75 V, ND = 1015 cm− 3, and AJ = 4 mm2. For p+ n junctions,

(17.138) The capacitance CJ0 increases with the doping concentration ND. For impurity concentration profiles more gradual than the step junction, the small-signal junction capacitance is expressed by (17.139)

where m is the grading coefficient. For linearly graded junctions,

. For step junctions,

. For all doping concentration profiles, CJ0 is directly proportional to the junction area AJ. High-current diodes have a large junction area AJ, resulting in a large junction capacitance CJ. If both donor and acceptor concentrations are increased to reduce the series resistance in the on-state, the junction capacitance increases and the breakdown voltage decreases. The energy stored in the junction capacitance CJ at voltage vD is (17.140)

For p+ n junction, a linear relationship between 1/C2J and vD is given by (17.141) The slope is (17.142)

Figure 17.27 shows plots of 1/C2J as a function of diode voltage vD for Vbi = 0.75 V, ND = 1015 cm− 3, and AJ = 4 mm2.

Figure 17.27 1/C2J as a function of diode voltage vD for Vbi = 0.75 V, ND = 1015 cm− 3, and AJ = 4 mm2. The large-signal junction capacitance is given by (17.143)

17.12.2 Diffusion Capacitance When the pn junction is forward biased, the depletion region narrows and the junction capacitance CJ increases. However, a large number of minority carriers injected causes much greater excess charge. The excess minority-carrier charges are stored in the neutral regions. In each region, the excess holes and free electrons represent equal and opposite charges. For example, holes injected across the depletion layer into the n-region are stored in the quasi-

neutral n-region immediately adjacent to the depletion region edge for x > xn. For p+ n junctions, the electron current is negligible and the excess minority hole carrier charge due to diffusion is given by (17.144) where τp is the hole carrier lifetime in the n-type region. The hole carrier lifetime τp ranges from 1 fs to 1 μs. The excess charge QDp increases by ΔQDp as the diode voltage vD increases by ΔvD, yielding the incremental diffusion capacitance CD = ΔQDp/ΔvD, as shown in Figure 17.28. The slope of the QDp-vD curve at the operating point vD = VD is the small-signal diffusion capacitance (17.145)

where rd = dvD/diD is the small-signal resistance of the diode at the operating point vD = VD. Note that τp = rdCD. The diffusion capacitance CD is negligible for reverse-biased junctions because iD ≈ −IS and diD/dt ≈ 0. The small-signal resistance of the diode at an operating point is (17.146) Figures 17.29 and 17.30 shows large-signal and small-signal models of pn junction diodes.

Figure 17.28 Change in minority carrier charge stored in the bulk regions due to a diode voltage change around the dc quiescent diode voltage VDQ. The change in the excess carrier minority charge results in the diffusion capacitance CD.

Figure 17.29 Large-signal model of a pn junction diode.

Figure 17.30 Small-signal model of a pn junction diode. The large-signal diffusion capacitance is

(17.147) There are low-frequency and high-frequency diodes. The high-frequency switching diodes used in power electronics include soft recovery, fast recovery (FR), ultra-fast recovery (UFR), and hyper-fast recovery (HFR) pn junction silicon diodes, in which the reverse recovery switching time and the power loss are reduced. For FR diodes, trr ≤ 500 ns. For UFR diodes, trr ≤ 100 ns. For HFR diodes, trr ≤ 1 ns. For instance, a IFR 8ETH06 HFR diode has trr = 1 ns. For small-signal diodes, 0.75 ns ≤ trr ≤ 5 ns. The forward voltage drop of faster diodes is typically greater than that of slower diodes. The switching loss of a diode is caused by the reverse recovery, when it turns off.

17.13 Reverse Recovery of pn Junction Diodes 17.13.1 Qualitative Description When a forward-biased voltage is applied, a large number of electrons is progressing through the depletion region from the n-type material into the p-type material and a large number of holes is progressing from the p-type material into the n-type material. The electrons in the ptype material and holes in the n-type material establish a large number of minority carriers in each material in the quasi-neutral regions immediately adjacent to the depletion region edges. This excess charge must be removed from both sides of the quasi-neutral regions, when the diode is switched from the forward to the reverse bias, as shown in Figure 17.31. Figure 17.32 depicts the hole distribution as a function of time during the turn-off transition.

Figure 17.31 Change in minority carrier charge stored in the bulk regions during the turn-off transition. This charge must be removed when the diode is turned-off from forward to reverse bias.

Figure 17.32 Hole distribution in the n-region as a function of time during the turn-off transition. When the applied voltage is reversed, the ideal diode should change instantaneously from the conducting state to the non-conducting state and start blocking the voltage. In a real diode, the excess minority carriers stored in the diode must be removed before the diode is able to block the reverse voltage. The stored excess minority charge can be removed by: (1) the flow of a reverse diode current and (2) by the recombination of the minority carriers. When the reverse current flows, the excess carriers are drawn back across the junction. If |IR| IF, most of the excess charge is removed by the reverse current flow. In contrast, if |IR| IF, most of the excess charge is removed by the recombination. The process of removing the excess charge is called reverse recovery.

17.13.2 Reverse Recovery in Resistive Circuits The simplest circuit for studying the transitions in diodes consists of a square-wave voltage source v, a resistor R, and a diode, as depicted in Figure 17.33. Figure 17.34 shows the waveforms for pn junction diodes. The dynamic iD–vD diode characteristic during the turn-off transition is shown in Figure 17.35.

Figure 17.33 Circuit for studying the on-to-off and off-to-on transitions in diodes.

Figure 17.34 Waveforms for on-to-off and off-to-on transitions in junction diodes.

Figure 17.35 Dynamic iD-vD diode characteristic during the turn-off transition in resistive circuit with square wave driving voltage. The forward diode current is given by (17.148) The waveforms during the turn-on transition are shown in Figure 17.36. If a constant current IF flows long enough through p+ n junction, the minority carrier densities reach steady state and the excess stored charge is (17.149) where τp is the hole lifetime.

Figure 17.36 Waveforms for pn junction diode during the turn-on transition. When the source voltage v is abruptly changed from a positive voltage VH to a negative voltage VR, the diode voltage cannot suddenly change because of the charge stored in the diffusion capacitance CD. The diode current jumps to a negative value given by (17.150) During the storage time ts, the stored charge Qp(t) will gradually decrease to zero. The diode remains ON during the storage time ts. At the end of the storage time ts, the excess charge Qp is removed and the diode voltage drops to zero. During the transient time tt, the diode current decreases exponentially from IR to − IS and the diode voltage decreases exponentially from zero to VR, charging the junction capacitance CJ. The storage time ts is the time interval between the instant the diode current passes through zero and the instant the diode current reaches the peak reverse value IR. The transition time

interval tt is defined as the time interval between the instant the diode current is equal to the peak reverse current IR and the instant the diode current reaches 10% (or 25%) of IR. The reverse recovery time trr is defined as the time between the instant the diode current crosses zero and the instant the reverse recovery current decays to 10% of its reverse recovery peak value IR. Most commercially available switching diodes have trr in the range 1 ns to 1 μs. The reverse recovery time trr consists of two time intervals: the storage time ts and the transition time tt (17.151) At time t = 0, the diode begins to turn off. Since the excess charge in the diode cannot change instantaneously, the excess carrier concentrations at the edges of the depletion region are positive, and therefore the diode voltage is also positive, the junction is forward biased, and the diode current decreases from positive to negative. The negative diode current reduces the excess carrier concentrations. At time ts, the excess carrier concentrations at the edges of the depletion region reach zero, the stored charge Q(ts) is zero, and the diode voltage vD(ts) is zero. The product of the diode current and voltage pD(t) = iDvD during the storage time ts is very low and negative because the diode voltage vD is low (between 0.7 V and 0 V) and the diode current iD is negative. The storage time ts increases with increasing temperature T. The storage time ts can be reduced by adding recombination centers to the bulk regions. For silicon, a gold (Au) atom doping of 1014 cm− 3 can reduce the recombination time constant τp, for example, from 100 ns to 1 ns. Figure 17.37 depicts the waveforms during the storage time ts. Figure 17.38 shows the waveform of the excess minority charge Qp during the storage time ts.

Figure 17.37 Waveforms for pn junction diode during the storage time ts.

Figure 17.38 Waveform of the excess minority charge Qp for pn junction diode during the storage time ts. Once the excess carriers are no longer present at the end of storage time interval ts, the diode begins to enter the reverse-biased region. During time tt, the diode voltage vD decreases from zero to VR, the diode is OFF, and the current flows through the diode junction nonlinear capacitance, until the capacitance is fully charged. This current flows through the equivalent resistance of the charging path, causing the turn-off switching loss. For a linear capacitance, both the capacitance voltage and current are exponential functions during the time interval tt. However, the junction nonlinear capacitance is large, when the diode voltage is close to zero and the diode voltage changes slower than that of the linear capacitance. On the contrary, the junction capacitance is small, when the diode voltage is close to the steady-state value VR and the diode voltage changes faster than that of the linear capacitance. Waveforms during the transient time tt are shown in Figure 17.39. The maximum value of the instantaneous dissipated power is equal to IRVR/4.

Figure 17.39 Waveforms for pn junction diode during the transient time tt.

17.13.3 Charge-Continuity Equation The process of storing charge in pn junction diodes is not the same as that of capacitors. The charge in the diode can be created by EHP generation and it can disappear due to recombination. The reverse-recovery process of p+ n junction diodes during the storage time interval ts is described by the charge-continuity equation, also called the charge-control equation or the charge-control model (17.152) where Qp(t) is the excess minority hole charge stored in the n-bulk region adjacent to the depletion region edge and τp is the average hole lifetime in the n-region, also called the mean recombination time of minority holes. The term Qp(t)/τp describes the recombination and generation of EHPs, and the term dQp(t)/dt = iD − Qp(t)/τp describes the change in the stored

minority excess hole charge due to the net carrier flow out from the quasi-neutral region [11]. For (17.153) the charge-continuity equation simplifies to (17.154) In this case, the charge is proportional to the diode current. The diode current supplies the holes to the quasi-neutral n-bulk region at the same rate as they are being lost by recombination in the n-bulk region, whereas the current associated with the rate of change of the excess hole charge is negligible. The entire amount of charge Qp recombines and must be replenished every τp nanoseconds. The total diode current is approximately equal to the hole current injected across the junction. The diode is in a quasi-static steady state. This situation usually takes place, when the diode current is constant and the excess charge is in steady state (long after the turn-on transition) or the ac diode current is slowly varying, for example, a half sinusoidal diode current at low frequencies f < 1/(20πτp). The condition for low-frequency operation takes place for ωτp 0.1. The storage time ts for slowly varying diode current waveforms with low diD/dt at all times is nearly zero. That is why zero-current switching (ZCS) of diodes is desirable. For (17.155) the charge-continuity equation becomes (17.156) In this case, the diode current is equal to the rate of change of the charge, whereas the recombination current is negligible. Solutions of (17.152) are given in [11] for selected waveforms of iD(t). When iD(t) > Qp(t)/τp, holes flow into the diode at a rate higher than the rate of the hole loss. As a result, the stored hole charge increases with time at the rate (17.157) When the diode is driven by a square-wave voltage, the diode current waveform has a step

change from IF to IR at turn-off. The charge equation for the storage time interval becomes (17.158) This equation in the s-domain is given by (17.159) Assuming that the excess charge waveform has reached the steady-state value before the beginning of the turn-off transition, the charge initial value is Qp(0) = τpIF. Rearrangement of (17.159) produces (17.160)

Hence, (17.161) Imposing the condition Qp(ts) = 0, one obtains the storage time (17.162) The storage time ts decreases when IF/|IR| decreases.

17.13.4 Reverse Recovery in Inductive Circuits In many applications, the rate of the diode current change diF/dt is limited during the turn-off transition by an external circuit, such as an inductor connected in series with the diode. For example, this situation is present in PWM dc-to-dc converters. Figure 17.40 shows the diode current and voltage waveforms of a pn junction diode during the reverse recovery for a finite rate of change of the diode current diF/dt. The dynamic iD-vD diode characteristic during the turn-off transition in inductive circuits is depicted in Figure 17.41. When forward current is ramped down at high rate of diF/dt to zero, current flow does not come to an ideal stop. Instead the current briefly reverses its flow and continues with the same slope until a peak value IR is reached. It will diminish thereafter to nearly zero, that is, to the saturation level − IS. During the storage time ts the high reverse blocking voltage does not start appearing until the reverse current peak IR occurs. As the slope |diF/dt| decreases, the magnitude of the peak reverse current |IR| also decreases, as shown in Figure 17.42.

Figure 17.40 Idealized current and voltage waveforms of a pn junction diode illustrating the reverse recovery in inductive circuits.

Figure 17.41 Dynamic iD-vD diode characteristic during the turn-off transition in inductive circuits.

Figure 17.42 Dependence of the peak reverse recovery diode current IR on the slope |diF/dt| during the turn-off transition in inductive circuits. The softness factor or the snapness factor is defined as the ratio of the transient time tt to the storage time ts (17.163) A diode with S ≥ 1 is called a soft-recovery diode and a diode with S < 1 is called a FR diode, snappy-recovery diode, or abrupt diode. The time ts is (17.164) resulting in (17.165) and (17.166) The peak reverse current is given by

(17.167) The reverse-recovery charge stored in the diode, when the diode current is negative, is found as (17.168) which gives (17.169)

Substituting (17.169) into (17.167) yields the peak reverse current (17.170)

As |diF/dt| decreases, |IR| and |Qrr| also decrease [11]. For example, 600 V silicon pn junction diodes have the reverse recovery charge Qrr = 100 –500 nC and the reverse recovery time trr ≈ 100 ns. For 600 V UFR pn junction diodes, Qrr ≈ 100 nC. The reverse recovery charge Qrr increases significantly with temperature T, forward current IF, and diF/dt. The charge stored in the diode during time interval tt is (17.171) The diode current and voltage waveforms during time interval tt can be approximated by (17.172) and (17.173) where IR < 0 and VR < 0. The instantaneous power loss during time interval tt is given by (17.174)

resulting in the average power dissipated during time interval tt (17.175) As |diF/dt| decreases, the power PRR also decreases. Reverse recovery causes switching loss in the diode, increases current stress in the diodes and in other devices connected to the same node (except inductors), and increases harmonics and the level of conducted and radiated electromagnetic interference (EMI). All these adverse effects can be reduced by slowing down the turn-off |diF/dt| rate. The switching power loss in Si pn junction diodes increases dramatically with temperature due to the increase in peak reverse current IR.

17.14 Schottky Diodes Diodes made with a rectifying metal–semiconductor (m-s) contact (junction) are called Schottky diodes or Schottky barrier diodes (SBDs), which are majority carrier devices and the diffusion of minority charge carriers is negligible. A physical structure of a Schottky diode is depicted in Figure 17.43. It consists of anode metal, low doped drift n region, high doped n+ substrate, and cathode metal. Schottky diodes are fabricated by evaporating or sputtering metallic contact onto a semiconductor. The semiconductor is usually an n-type material because of the higher mobility of electrons than that of holes, reducing the on-state resistance of the drift region. The semiconductor is lightly doped to form a rectifying contact with the metal. The doping level of n-type semiconductor is very low, typically, ND = 1014–1016 cm− 3 for silicon. The doping level of the n+ substrate located on the cathode side is very high to form a non-rectifying ohmic contact between metal and n+ type semiconductor. The metal is aluminum, platinum, chrome, molybdenum, tungsten, nickel, or titanium. A thin metal film is usually deposited on an n-type semiconductor. Electrons from the n-type semiconductor flow into the metal, as they would flow into the acceptor semiconductor in the p+ n junction diode, where the p+ region is heavily doped and behaves nearly like a conductor. The forward current is due to injection of the majority charge carriers (i.e., electrons) from the n-type semiconductor into the metal. Therefore, Schottky diodes are unipolar devices. The free electrons in the semiconductor are more energetic than those in metal. The flow of electrons from the semiconductor into metal leaves behind a region in the semiconductor adjacent to the metal–semiconductor interface that is depleted of carriers as in the pn junction, forming a depletion region with a positive space charge of donor atoms N+D. The depletion region is only formed on the semiconductor side. A compensating negative charge is created on the metal surface. Schottky diodes are unique because the conduction is entirely by majority charge carriers. The current in Schottky diodes has only the drift component. The drift current is proportional to the carrier concentration and the average drift velocity. Majority charge carriers move or drift in response to the electric field E. Therefore, there is no need to

accumulate or remove excess carriers. This eliminates the forward and reverse recovery phenomena, enabling very fast switching from on-to-off state. However, reverse-biased Schottky diodes have much higher leakage current than the corresponding pn junction diodes. The series resistance of the diode consists of the drift resistance Rn, the substrate resistance Rsub, and the resistances of the anode and cathode metals Rm (17.176) The on-state voltage is equal to the sum of the voltage drops across the metal–semiconductor contact, the drift resistance, the substrate resistance, and the resistances of the anode and cathode metals. (17.177) For low-voltage Schottky diodes, the drift resistance and the substrate resistance are comparable because the heavily doped substrate region is much longer than the drift region, even though the lightly doped drift region has a higher resistivity. In contrast, for high-voltage Schottky diodes, a drift region is long and lightly doped, both of which increase the drift region resistance.

Figure 17.43 Physical structure of Schottky diodes. The maximum electric field intensity Em occurs at the metal–semiconductor contact. The breakdown voltage occurs when Em = EBD. Silicon Schottky diodes have low breakdown voltage (usually VBD ≤ 200 V) because the voltage drop across the drift region becomes high at high voltages. Diodes with high breakdown voltages require low doping and long drift region. Electrons from the n-type semiconductor have higher energy and diffuse across the metal– semiconductor barrier to the metal side. The migration of electrons from the semiconductor to

the metal leaves behind ionized donors N+D as fixed positive space charges, creating a depletion region, which is similar to the depletion region of p+ n junction diodes. A typical commercial Schottky diode consists of a rectifying metal–semiconductor contact deposited on an optimally designed n− epitaxial layer (a drift region), an edge termination, a highly doped substrate, and a backside ohmic contact. A cross-section of a silicon-carbide Schottky diode is depicted in Figure 17.44 [14]. The diode was designed for a maximum forward current of 6 A and a breakdown voltage of 1200 V. The thickness of the lightly doped n− epi-layer was 10 μm and the doping concentration was ND = 2.7 × 1015 cm− 3. The n+ substrate and the metal form an ohmic non-rectifying contact. The thickness of the substrate is typically 500 μm. The diode diameter was 3 mm. The top side nickel thickness was 0.1 μm. A 1 μm thick gold plating layer was deposited on top of the nickel contact by electron beam evaporation to minimize the spreading resistance. Boron was implanted in a 100 μm ring around the device as a resistive edge termination to achieve a nearly ideal breakdown voltage.

Figure 17.44 Cross section of silicon-carbide Schottky diodes.

The series resistance RS of Schottky diodes consists of the lightly doped n− region resistance Rn and the heavily doped n+ substrate resistance Rsub. For low-voltage devices, these two resistances are comparable because the heavily doped substrate is much (usually two orders of magnitude) longer than the lightly doped n− region. For high-voltage devices, the resistance of the n− region is much higher than that of the substrate because the n− region is long and has a low doping concentration ND. For example, the series resistance is RS = 46.641 mΩ for a silicon-carbide CSD10060 Schottky diode. Conductivity modulation is not present in Schottky diodes to reduce the series resistance during conduction of forward current. Therefore, silicon Schottky diodes with high voltage ratings are not made. In contrast, silicon-carbide Schottky diodes may have high breakdown voltage ratings, above 1 kV. The breakdown voltage of Schottky diodes is due to the avalanche effect caused by a high peak electric field intensity Em at the metal–semiconductor interface. The avalanche current may damage the metal–semiconductor contact. Therefore, all Schottky diodes have a guard or field rings surrounding the metal–semiconductor contact. The rings are made of p+ diffusions that form p+ n junctions. The Schottky diodes are designed in such a way that the avalanche breakdown voltage of the p+ n junction of the ring guard is higher than that of the Schottky metal–semiconductor junction. Ohmic non-rectifying metal–semiconductor contacts are formed by doping the semiconductor heavily in the contact region. An n+ on the n-region or a p+ on the p-region is made prior to deposition of the metal. Typical doping levels are ND = n+ or NA = p+ = 1017–1019 cm− 3. These are m-n+ or m-p+ structures. Their I–V characteristic is linear in both directions. When doping increases, the depletion region width W decreases, and the majority carriers can readily tunnel between the semiconductor and metal. Electrons or holes flow freely in and out of semiconductor.

17.14.1 Static I–V Characteristic of Schottky Diodes The equation for the dc I–V characteristic of Schottky diodes is similar to that of pn junction diodes (17.178) The saturation current is determined by a different equation than that of the pn junction diodes (17.179) where D is the effective Richardson's constant and ϕB is the metal–semiconductor potential barrier height for electron injection from the metal to the semiconductor. It depends on the work function of the metal contact. For silicon, D = 120 A/cm2-K2 and for aluminum to n-type

silicon (Al-Si) junction, ϕB = 0.7 V. The most commonly used metals, such as titanium and nickel, have ϕB = 1.1 eV. The reverse saturation current IS is of the order of 10− 7 A. It is usually four to six orders of magnitude larger than that of the pn bipolar junction diodes with the same junction area AJ. Therefore, the forward voltage drop is 0.25–0.35 V lower than that of pn junction diodes with the same current density JD = ID/AJ. The typical maximum current density of silicon Schottky diodes is JDmax = 100 A/cm2. The threshold voltage is VF = 0.3–0.4 V for silicon Schottky diodes and it is VF = 1.5–2 V for silicon-carbide Schottky diodes. The threshold voltage VF decreases as the junction temperature T increases. For SiC Schottky diodes, the thermal coefficient of VF is (17.180) The reverse-biased Si Schottky diode has a reverse leakage current that is larger than that of a Si pn junction diode with the same junction area AJ. This current increases with temperature. The temperature coefficient for the saturation current of Si Schottky diodes is (17.181) Schottky diodes exhibit nearly zero reverse recovery because there is no need to remove excess carriers as the current flows only by drift. There is only capacitive reverse recovery current due to the junction capacitance. The peak reverse recovery current IR of silicon diodes is much higher than that of silicon-carbide diodes. The current IR increases with increasing temperature for silicon diodes, but it remains nearly constant for silicon-carbide diodes. The reverse breakdown voltage of silicon Schottky diodes is low, typically below 50–200 V. In contrast, the breakdown voltage of silicon-carbide Schottky diodes is high, typically in the range 200–1200 V. High-voltage silicon Schottky diodes (VBD > 200 V) would require increased thickness and resistivity of the drift region material, resulting in an increase of the incremental forward resistance RF. Schottky diodes find applications in high-power, fast switching power circuits. The threshold voltage of silicon-carbide Schottky diodes VF decreases with temperature. The forward resistance RF of these diodes increases with temperature due to the reduction in the mobility of current carriers at elevated temperatures. Therefore, many diodes can be connected in parallel without any unequal current sharing issues. Silicon Schottky diodes are attractive in lowvoltage applications because of low forward voltage VF, whereas silicon-carbide Schottky diodes are attractive in high-voltage, high-frequency, high-temperature applications because of high breakdown voltage and high speed. Silicon-carbide Schottky diodes are used in boost power factor correction (PFC) circuits. The reverse-recovery current of Schottky diodes during turn-off transition is reduced as compared to that of pn junction diodes. The turn-off

reverse-recovery current remains almost constant when the temperature increases because only the junction capacitance is discharged. Conversely, when the temperature of pn junction diodes increases, the reverse charge and the reverse current increase. The typical turn-off time trr = tt of SiC Schottky diodes is less than 50 ns, even at high junction operating temperature TJ. Typically, trr(Si)/trr(SiC) = 1000. For silicon-carbide Schottky diodes, VON = 1–1.5 V, ll = 10− 10–10− 6 A, J 2 Dmax = 8 A/mm , VBDmax = 1400 V, TJmax = 700°C.

17.14.2 Breakdown Voltages of Schottky Diodes The avalanche breakdown voltage is an m-n+ Schottky diode is given by (17.182) The punch-through breakdown voltage is an m-n+ Schottky diode is (17.183)

17.14.3 Junction Capacitance of Schottky Diodes The depletion region width of Schottky diodes is (17.184) The typical values of Vbi are in the range 0.3–0.4 V for silicon diodes and 2–3 V for siliconcarbide diodes. The junction capacitance is (17.185)

where (17.186) Ideally, Schottky diodes do not exhibit reverse recovery. Therefore, the turn-off transient behavior of these diodes is determined by the junction capacitance CJ. The diffusion capacitance CD is zero and therefore the storage time ts is zero. In reality, the lifetime of the minority carriers is very short. For instance, τ = 14.474 ≈ 15 ps for a silicon-carbide CSD10060 Schottky diode. The diode model in the off-state is the junction capacitance CJ. For

example, CJ0 = 381.44 pF, Vbi = 9.99 V, and m = 0.63338 for a silicon-carbide CSD10060 Schottky diode.

17.14.4 Switching Characteristics of Schottky Diodes A simple circuit for investigating off-to-on and on-to-off transitions in Schottky diodes is shown in Figure 17.33. Figure 17.45 depicts idealized waveforms illustrating turn-off and turnon transitions due to junction capacitance.

Figure 17.45 Waveforms of Schottky diodes illustrating the turn-off and turn-on transitions. The current through the junction capacitance CJ can be determined from the equation (17.187)

For example, if the diode voltage is sinusoidal, when the diode is OFF

(17.188) the current through the junction capacitance CJ is given by (17.189)

Figure 17.46 shows the current waveform through the junction capacitance CJ during the turnoff transition for the Cree CSD10060 SiC Schottky diode in a circuit consisting of a sinusoidal voltage source, a resistor R, and a diode connected in series.

Figure 17.46 Waveform of the current through the junction capacitance CJ during the turn-off transition for the Cree CSD10060 SiC Schottky diode at CJ0 = 381 pF, Vbi = 9.99 V, R = 500 Ω, Vm = 9 V, f = 200 kHz, and T = 300 K. Let us consider the turn-off transition, when the junction capacitance is charged and the diode voltage decreases from VF to VR. To gain some insight into dynamics of Schottky diodes,

assume that the junction capacitance CJ is linear. At t = 0, the input voltage v is switched from VH to VR. For t > 0, the diode current, voltage, and instantaneous power waveforms are given by (17.190) (17.191) and (17.192) where τ = CJR is the time constant, R is the resistance in the junction capacitance charging path, including the diode series resistance RS, (17.193) The series resistance RS consists of the spreading resistance of Schottky metal, the drift region resistance, the substrate resistance, the backside resistance, the bond wire resistance, and the package resistance. The average power transferred from the input voltage source v to the diode during the turn-off transition is given by (17.194) for |VR| VF, where fs = 1/T is the switching frequency. The energy corresponding to this power is stored in the junction capacitance CJ. The power delivered from the input voltage source v to the R-CJ circuit during the turn-off transition is (17.195) The switching power loss in the charging path resistor R during the turn-off transition is (17.196) Figure 17.47 shows the waveforms of the diode current iD, the diode voltage vD, and the diode power pD for the Schottky diode during the turn-off transition at VH = 10 V, VR = −10 V, VF = 1.78 V, R = 1 Ω, CJ = 10 ns, and τ = 10 ns.

Figure 17.47 Waveforms for Schottky diodes during turn-off transition. Next, let us consider the turn-on transition, when the junction capacitor is discharged and the diode voltage increases from VR to VF. The diode current, voltage, and instantaneous power waveforms are given by (17.197) (17.198) and (17.199) where

(17.200) The average power loss during the turn-on transition is given by (17.201)

The energy stored in the junction capacitance CJ during the time interval when the diode is in the off-state is lost during the turn-on transition. Therefore, the turn-on switching power loss is given by (17.202) Figure 17.48 shows the waveforms of iD, vD, and pD for the Schottky diode during the turn-on transition for VH = 10 V, VR = −10 V, VF = 1.78 V, R = 1 Ω, and τp = 10 ns.

Figure 17.48 Waveforms for Schottky diodes during turn-on transition. In summary, the total switching power loss during both the turn-off and turn-on transitions is given by (17.203) For SiC Schottky diodes, the transient current and the switching power losses are independent of temperature. In reality, the junction capacitance CJ is nonlinear and the transition processes are more complex. The junction capacitance is large at low diode voltages and low at high reverse voltages. Therefore, the diode voltage changes slower when the diode voltage is close to zero and faster when the diode voltage is close to VR as compared to the case with a linear junction capacitance. High-voltage Schottky diodes store minority carrier charge in lightly doped region and slightly suffer from reverse recovery. In contrast, low-voltage Schottky diodes store very little minority charge and exhibit no significant reverse recovery current. A typical value of the transient time τ for Schottky diodes is 10 ps. Semiconductor devices should be reliable. Reliability measures

the ability of a component or a system to perform the intended functions.

17.15 Solar Cells Light and electrons can interact through the following mechanisms: light absorption and light emission. Electrons gain energy through electron–hole generation, caused by light absorption. A photon generates an EHP. Electrons lose energy through recombination with holes, yielding light emission. A photon is generated when an electron and a hole recombine. Solar cells, also called photovoltaic (PV) cells, are pn photodiodes and belong to the family of optoelectronic devices or photonic devices. Diodes can absorb light energy, which can break the covalent bond, generating EHPs and creating photocurrent. Solar cells can be used to produce green energy. The average solar power density is 300 W/m2. Light consists of packets (quanta) of energy, called photons. The energy of a photon (i.e., the quantum of light energy) is given by (17.204) where λ = c/f is the wavelength of sunlight, h = 6.62617 × 10− 34 J • s is Planck's constant, and c = 2.998 × 108 m/s is the speed of light in vacuum. For silicon, fmin = EG/h = 1.792 × 10− 19/6.626 × 10− 34 = 270 THz or λ max = hc/EG = 1.1 μm. Since almost the complete spectrum of solar radiation is above fmin, silicon is a good semiconductor for PV panels. In order for the photons to penetrate the semiconductor, the electrodes of the solar cells are transparent. When the light shines on the pn junction, the minority carriers (holes) are generated in the n-region within the diffusion length Lp by the photon light energy, then they are diffused into the pn junction, next they are swept across the junction by the built-in electric field, and they cause the photocurrent to flow out of the p-terminal through the external circuit back into the n-terminal. Photons with energy Eph equal to or greater than the band gap energy EG are absorbed by a semiconductor and generate EHPs. Conversely, photons with energy lower than EG are not absorbed by the semiconductor. The thickness of the solar cell t must be larger than the light penetration depth to absorb nearly all photons: tSi > 50 μm and tGaAs > 1 μm. The holes generated within the diffusion distance Lp from the junction in the volume AJLp are collected by the junction and produce the photocurrent. Holes outside this volume recombine with electrons and do not contribute to photocurrent. To achieve a large diffusion length Lp, the semiconductor should be free of defects and impurities. The pn junction area of solar cells is large. The typical efficiency of the light-to-electricity conversion is from 15 to 30%. The total current of a solar cell is given by (17.205) where ISC is the short-circuit photocurrent and is proportional to the cell area AJ and the light

intensity (i.e., the number of photons per second). At VD = 0, the solar cell short-circuit current is obtained ID = −ISC. The open-circuit voltage of a solar cell is obtained by setting the cell current to zero ID = 0 and VD = VOC. Thus, (17.206) Figure 17.49 shows current–voltage characteristics of a solar cell diode for a dark cell and an illuminated cell. When light shines on the cell, its current–voltage characteristic shifts down to the fourth quadrant. As the light intensity increases, the amount of the diode current shift also increases. The short-circuit photocurrent ISC is much larger than the diode reverse saturation current IS and their directions are the same.

Figure 17.49 Solar cell and dark current characteristics of pn junction at ISC = 0.5 A and IS = 10− 10 A. Because ID and VD have opposite signs, solar cells generate electric power. The output power

of a solar cell is (17.207) Figure 17.50 shows power delivered by a solar cell. There is a particular operating point IMP–VMP on the ID–VD curve, called the maximum power point (MPP), that offers the maximum output power of the solar cell. Typically, VMP ≈ 0.9VOC and IMP ≈ 0.9ISC, yielding the power delivered by a solar cell (17.208) A control circuit is used for achieving the maximum power point tracking.

Figure 17.50 Power delivered by a solar cell at ISC = 0.5 A and IS = 10− 10 A. Many cells are connected in series to form a solar cell string to increase the total string voltage. The output voltage of a solar string is usually Vstring = 24 × 0.5 = 12 V. To generate 10 W, typically about 1080 solar cells are required. To obtain a power of 25 W, the total pn

junction area is 1 m2, that is, P/AJ = 25 W/m2. Many cell strings are connected in parallel to form a solar cell panel to increase the output current. In turn, many PV panels are connected in series to form a PV module to increase the module output voltage. The dc output voltage of a PV module in the United States is up to 600 V. Panels or modules of solar cells are installed on rooftops or on open areas in solar farms to generate electric energy. The dc voltage from the solar panels is increased by a step-up dc–dc converter and then is converted into ac voltage by a dc–ac inverter, connected to the utility grid, and synchronized with frequency and phase of an utility line ac voltage. The maximum output power from each module string is achieved when the current from each module is matched. Modules are sorted in advance so that they deliver closely matched currents. The current of individual modules may be mismatched, reducing the output power of the module string. Bypass diodes are connected in parallel with each PV module. Usually, a blocking diode is connected in series with each string. The light intensity is determined by the number of photons per time unit measured in candelas. It may change for the following reasons: changing weather conditions, partial shading due to trees, complicated roof structures, and chimneys, partial soiling due to leaves, dust, sand, and snow. The average consumption of electric power in the world is above 1000 GW. To generate all the electricity by solar cells, the required cell junction area is about 40,000 km2. Solar energy is among the most promising renewable energy source, which reduces the greenhouse effect and global warming.

17.16 Light-Emitting Diodes The diodes designed for light emission are called LEDs. A flow of current through a forwardbiased diode causes recombination of EHPs. As a result, electric energy is converted into visible and invisible (infrared) light. When a pn junction is forward biased, free electrons (the majority carries) cross the depletion layer from the n-side to the p-side to become minority carries and recombine with holes (the majority carries), realising the energy in the from of heat and light energy (photons). For silicon and germanium diodes, most of the realised energy is in the from of heat. In contrast, in diodes made of compound semiconductors, most of the realised energy is in the form of light energy. The frequency of emitted light is (17.209) The frequency spectrum of visible light extends from 400 to 750 THz and the wavelength expends from 400 to 750 nm. The frequency spectrum of infrared light extends from 100 to 400 THz. Compound semiconductors with different content are used to obtain the desired energy band gap EG, and thereby the desired frequency f and color of visible light. Red LEDs have EG

= 1.9 eV and are made of a GaAsP semiconductor. Green LEDs have EG = 2.2 eV and are made of a GaP semiconductor. Blue LEDs have EG = 5 eV and are made of a GaN semiconductor. The light intensity is controlled by the diode forward current ID, which should be in the range 10–25 mA. The human eye is most sensitive to the green color (λ = 550 μm). The forward voltage VF of LEDs ranges from 1.8 to 5 V. VF = 1.8 V for red LEDs, VF = 2.1 V for yellow LEDs, VF = 2.2 V for green LEDs, VF = 5 V for blue LEDs, and VF = 4.1 V for white LEDs. The reverse breakdown voltage of LEDs is in the range 3–5 V. White color can be produced from green, blue, and red colors. Lifetime of LEDs is over 10 years. Light flux is measured in lumens (lm), and light intensity is measured in candelas (cd). The efficacy ηv of LEDs is from 25 to 400 lm/W. LEDs are used as indicator lights, traffic lights, dashboard displays, video billboards, head lamps, EXIT lights, and solid-state artificial light sources. Infrared diodes are used in optical communication. Infrared red diodes are used in remote control, optical coupling, security systems, safety control, car garage openers, and industrial processing.

17.17 SPICE Model of Diodes Figure 17.51 shows a SPICE large-signal model for diodes. The diode SPICE model parameters are given in Table 17.4. The diode dc characteristic in SPICE is given by (17.210) in which the diode current for the forward-biased and reverse-biased regions is (17.211) and the diode current in the breakdown region is (17.212) where the thermal potential is (17.213) and the dependence of the saturation current on temperature T is described by (17.214) IS is the saturation current at T = Tnom, k = 1.38066 × 10− 23 J/K is Boltzmann’s constant, q = 1.602 × 10− 19 C is the magnitude of the electron charge, T = 273 K + temperature in °C is the

temperature in K, and n = 1–2 is the emission coefficient. For T = 25°C, VT = kT/q = T/11609 = 25.7 mV. Typically, IS = 10− 14 A for Si small-signal junction diodes and IS = 10− 11–10− 7 A for Si power junction diodes. For Si Schottky diodes, the typical value of IS is 10− 7 A. For silicon-carbide Schottky diodes, IS is in the range 10− 15 –10− 21 A.

Figure 17.51 SPICE large-signal model for diodes.

Table 17.4 SPICE diode large-signal model parameters Symbol SPICE sym. Model parameter

Default value Typical value

IS

IS

Saturation current

10− 14 A

10 nA

n RS

N RS

Emission coefficient Series resistance

1 0

1.1 to 1.8 0.1 Ω

VBR

BV

Reverse breakdown voltage ∞

100 V

IBR

IBV

Reverse breakdown current 10− 10 A

100 μA

CJ0

CJO

Zero-bias CJ

0

1 nF

Vbi

VJ

Junction potential

1 V

0.8 V

m Eg

M EG

Grading coefficient Band gap energy

0.5 1.11 eV

0.33 to 0.5 1.11 eV

FC

FC

Forward-biased CJ coeff.

0.5

0.5

τ x KF

TT XTI KF

Transit time IS temperature exponent Flicker noise coefficient

0 3 0

150 ns 3 0

AF

AF

Flicker noise exponent

1

1

The diode junction capacitance is given by (17.215)

where VJ = 0.55 V–1 V is the built-in potential and M = 1/3–0.5 is the grading coefficient. The diffusion capacitance is (17.216) Diode Topology Syntax: Dxxxx A K model-name Example: D1N9999 1 0 10A-diode SPICE Diode Model Syntax: .model diode-model-name D (SPICE diode parameters) Example:

.model 10A-diode D (Is = 100nA n = 1.666 Rs = 0.02Ohm BV = 100V IBV = 100nA CJ0 = 1nF TT = 12ns)

17.18 Summary Solid materials can be categorized as single crystals, polycrystals, and amorphous material. A single-crystal has a regular, geometric periodicity. Solid materials can be categorized as conductors, semiconductors, and insulators. The lattice is the periodic arrangement of atoms in the crystal. Semiconductors are materials that have resistivities between those of conductors and insulators. The resistivity of semiconductors is in the range 10− 3 Ω • cm≤ ρ ≤ 106 Ω • cm. At T = 300 K, the resistivity of the intrinsic silicon is ρSi = 2.26 × 105 Ω • cm and the conductivity of the intrinsic silicon is σSi = niq(μn + μp) = 4.4 × 10− 6(Ω • cm)− 1. For comparison, the conductivity of copper (Cu) is σCu = 5.8 × 107(Ω • cm)− 1 and the resistivity of copper is ρCu = 1.724 × 10− 6 Ω • cm. Thus, the conductivity of silicon is 13 orders of magnitude lower than that of copper. The valence electrons are responsible for the conductivity of a material. Electrons have particle and wave properties. Intrinsic Semiconductors A common technique for growing single-crystal materials is called Czochralski’s method. Semiconductors are elemental and compound. In covalent bonding between the atoms, the valence electrons in the outermost orbit are shared between two or more neighbors. In silicon, four valence electrons are shared with four neighbors. Ions are atoms that either gained or lost one or more electrons. A crystal is a solid material whose atoms or ions form a periodic array. The positions of the atoms or the ions is fixed with a constant spacing between the atoms or the ions. A polycrystal material consists of small crystal grains. The length of the unit cell of the silicon crystal is 0.543 nm. The valence and conduction bands are separated by an energy band gap EG, for example, EG(Si) = 1.12 eV and EG(SiC) = 3.26 eV. In intrinsic semiconductors, the electron and hole concentrations are equal, that is, the intrinsic carrier concentration is n = p = ni.

The intrinsic carrier concentration ni increases with temperature T. The concentration of crystalline silicon atoms (atomic density) is NSi = 5 × 1022 atoms/cm3. There are two kinds of electric charge in semiconductors: electrons and holes. A missing electron in a semiconductor atom is equivalent to a hole. The charge carrier concentration can be controlled by the addition of dopants. The semiconductor lattice is the bonded network of semiconductor atoms. Silicon-carbide (SiC) is a chemical compound of silicon and carbide. The greater the band gap EG, the greater the energy required to excite electrons from the valence band into the conduction band. The effective mass of an electron and a hole takes into account all internal forces in the crystal acting on a particle. The intrinsic carrier concentration ni of silicon carbide is much lower than that of silicon at the same temperature due to the larger band gap energy EG of SiC. A charge carrier is an electron or a hole that moves inside the semiconductor by diffusion or drift and may produce electric current. A diffusion is a process in which electrons or holes move from a region of high concentration to a region of low concentration. Generation is a process of breaking the bond and producing an EHP. Recombination is a process in which an electron falls into an empty hole, resulting in the elimination of an electron and a hole from the crystal by completing a broken bond. The electrical conductivity of intrinsic semiconductors increases with temperature. The net thermal velocity of charge carriers is zero if E = 0. Extrinsic Semiconductors Doping is the process of adding atoms (impurities) to an intrinsic (pure) semiconductor to alter its electrical properties, such as conductivity. In extrinsic semiconductors, the concentrations of electrons and holes are not equal (n ≠ p). In a semiconductor doped with donors, the concentration of electrons is far greater than that of holes. The donors are the elements from group V, such as arsenic (As), antimony (Sb), and phosphorus (P). In an n-type semiconductor, electrons are called the majority carriers because they by far outnumber the holes. The holes are called the minority carries.

In a semiconductor doped with acceptors, the concentration of holes is far greater than that of electrons. An ion is an atom, in which the total number of electrons is not equal to the total number of protons, producing a net positive or negative charge. The acceptors are the elements from group III, such as boron (B), gallium (Ga), indium (In), and aluminum (Al). In a p-type semiconductor, holes are termed the majority carriers because they far outnumber the electrons. The electrons are called the minority carries. An electron can be thermally or optically excited out of a covalent bond. It becomes a free electron to participate in conduction of electrical current. Complete ionization of impurities occurs at room temperature, that is, N+D ≈ ND and N+A ≈ NA. At sufficiently high temperatures, all semiconductors (including doped semiconductors) become intrinsic. The concentration of electrons and holes can be controlled by doping of impurities. The electrical conductivity of a semiconductor can be varied by changing the number of impurities. There are two mechanisms of electrical current flow in semiconductors: drift of carries in electric field and diffusion caused by charge concentration gradient. In the diffusion process, both electrons and holes move in the direction of lower concentration of electrons and holes, respectively. The charge carriers move in a zigzag fashion due to collisions in the crystal. The distance between collisions is a few tens of nm. Collisions are caused by lattice vibrations and scattering due to ionized impurities. The mean free time between collisions is typically 0.1 ps. Drift of charge carriers is the net motion of charge carriers caused by an electric field EG. SiC and GaN conduct heat far better than silicon does. pn Junction In a step junction, the doping concentration is uniform in each region and the change of the junction is abrupt. The drift velocity is the average velocity of a large number (a group) of charge carriers averaged over a time period. An ideal diode conducts current in the on-state with zero voltage drop and blocks voltage in the off-state with zero leakage current.

Electrons and holes diffuse into regions with lower concentrations. Electrons diffuse into the p-side and holes diffuse into the n-side. The depletion layer is depleted of any free (mobile) electrons and holes. In the pn junction, electrons diffuse from n to p-regions, leaving behind uncompensated donor ions N+D and creating a positive space charge in the n region near the junction. In the pn junction, holes diffuse from p to n regions, leaving behind uncompensated acceptor ions N−A and creating a negative space charge in the p-region near the junction. In equilibrium, the number of charges on either side of the pn junction is equal. Electric field E is induced in a pn junction and is directed from the positive charge in the n region to the negative charge in the p-region. The positive and negative charges create a voltage drop across the junction, called the built-in potential or the barrier potential. The depletion layer extends deeper into the more lightly doped semiconductor in pn junctions. The electric field E forces a drift component of current from n to p region, opposing the diffusion component of current. The electric field E is zero in the neutral regions outside the depletion region with thickness W. The avalanche breakdown is caused by impact ionization and it begins when the initiating electron has enough energy to knock an electron from the valence band to conduction band. Silicon carbide has a WBG energy, high breakdown electrical field intensity, high thermal conductivity, excellent thermal shock resistance, low thermal expansion, high hardness, high strength, and superior chemical inertness. The avalanche breakdown electric field intensity EBD increases with increasing band gap energy EG. The avalanche breakdown voltage VBD increases with the band gap energy EG. A higher breakdown diode voltage of diodes requires a longer lightly doped drift region and a lower doping concentration. The doping levels below 1015 cm− 3 are necessary to achieve high breakdown voltages in silicon diodes. The drift region should be made of the n-type semiconductor because electrons have higher mobility than holes, reducing the on-state resistance of the drift region. Silicon-carbide diodes are capable of delivering large currents and withstand high voltages, without the need for sophisticated cooling systems. The avalanche breakdown voltage VBD increases with the temperature T. The avalanche breakdown voltage of silicon-carbide junction diodes is about 11 times

higher than that of the silicon junction diodes at the same doping concentration. SiC Diodes Silicon carbide has a higher band gap energy EG, breakdown (critical) electric field EDB, thermal conductivity, and drift saturation velocity vsat than those of silicon. In addition, silicon-carbide devices have the inherent ability to operate at higher junction temperature (up to 600°C) because of the low intrinsic carrier concentration. The WBG of SiC allows for a much higher operating temperature and higher radiation hardness. A high breakdown electric field allows the design of SiC power devices with tinner and higher doped blocking layers. The high thermal conductivity of SiC allows for easy heat conduction from the device, resulting in a large power capability. An effective edge termination technique makes the electric field distribution nearly uniform at the edge of the device in order to approach the ideal breakdown voltage capability. The breakdown voltage of diodes can be increased by using guard rings and field plate terminations to reduce concentrations of the electric field at depletion region corners and chip edges. The breakdown voltage is reduced by defects in the semiconductor structure, especially at the surface and around the corners. Silicon-carbide Schottky diodes can be used in high-voltage, high-temperature, highfrequency applications. Schottky Diodes The threshold voltage VF is 0.3 V for silicon Schottky diodes, 0.7 V for silicon pn junction diodes, 1 V for silicon-carbide Schottky diodes, and 2.8 V for silicon-carbide pn junction diodes. The junction capacitance CJ is identical to a parallel-plate capacitor with its electrodes separated by the depletion region width W(VD) at a particular dc diode voltage VD. If both donor and acceptor concentrations are increased to reduce the series resistances, the junction capacitance increases and the breakdown voltage decreases. The junction and diffusion capacitances prevent the diode from turning on and off instantaneously. When a forward bias is applied suddenly to a pn junction, a charge is supplied to the depletion region and the neutral regions. Junction diodes suffer from reverse recovery due to both the excess minority carrier charge and the junction capacitance. There are two mechanisms of removing the excess minority

charge stored in the quasi-neutral regions adjacent to the edges of the depletion region: reverse current flow and recombination. The minority carrier lifetime τp or τn can be reduced by adding the recombination centers, gold (Au) atoms in silicon to increase the recombination rate. This reduces the storage time t s. Reverse recovery causes switching loss in the diode, high reverse current spikes in the diode and other components (except inductors) connected to the same node, and generates a broad spectrum of harmonics, reducing EMC performance. Switching loss PRR, peak reverse current IR, and EMI level can be reduced by slowing down the turn-off |diF/dt| rate. The forward current in Schottky diodes is only due to majority carrier injection of the silicon to metal. Therefore, Schottky diodes are majority devices. Schottky diodes show much less dependence on temperature than pn junction diodes. The switching loss in silicon diodes increases dramatically with temperature, whereas it remains essentially unchanged for silicon-carbide diodes. Schottky diodes exhibit only capacitive reverse recovery. The switching loss in silicon-carbide diodes remains essentially independent of temperature. Low-voltage Schottky diodes virtually do not exhibit reverse recovery, whereas highvoltage Schottky diodes store some minority charge in the lightly doped region, causing a small effect of reverse recovery (much smaller than in pn junction diodes). Silicon-carbide Schottky diodes have much smaller reverse recovery than silicon Schottky diodes. Silicon-carbide devices can operate at higher frequencies than the silicon devices, reducing the size of passive components. Ohmic non-rectifying metal–semiconductor contacts are produced by heavily doping the surface region of the semiconductor immediately beneath the contact. Solar Cells and LEDs Solar cells convert light energy into electrical energy. Important parameters of solar cells are the short-circuit current, open-circuit voltage, and maximum power. Photodiodes convert optical signals into electrical signals. In LEDs, photons are emitted due to EHPs recombination in the forward pn junction.

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2005. 18. V. P. Galigekere and M. K. Kazimierczuk, “Performance of SiC diodes,” IEEE Midwest Symposium on Circuits and Systems, Montreal, Canada, QC, August 5–8, 2007, pp. 682– 685. 19. C. C. Hu, Modern Semiconductor Devices for Integrated Circuits. Upper Saddle River, NJ: Prentice-Hall, 2010. 20. D. A. Neaman, Semiconductor Physics and Devices, 4th Ed, New York, NY: McGrawHill, 2010. 21. L. F. Eastman and U. K. Mishra, “The toughest transistor yet (GaN transistors),” IEEE Spectrum, vol. 39, no. 5, pp. 28–33, May 2002. 22. P. Goodignen, X. Jarda, M. Vellvehi, X. Perpina, V. Banu, D. Lopez, J. Barbero, P. Brosselard, and S. Masseti, “SiC Schottky diodes for harsh environment space applications,” IEEE Transactions on Industrial Electronics, vol. 58, no. 7, pp. 2582– 2590, July 2011.

Review Questions 1. Describe the atom structure. 2. What is covalent bonding? 3. How can an electron be excited out of a covalent bond? 4. What is an intrinsic semiconductor? 5. What is the source of electrons and holes in an intrinsic semiconductor? 6. What is an elemental semiconductor? 7. What is a compound semiconductor? 8. What is the effective mass of an electron and a hole? 9. What is the resistivity of silicon at T = 0 K? 10. What is the band gap energy EG? 11. What is thermal ionization? 12. What is recombination? 13. Compare the electrical and thermal properties of silicon and silicon-carbide materials. 14. What is an extrinsic semiconductor? 15. What is doping? 16. What is the purpose of doping?

17. What is a donor? 18. What is an acceptor? 19. What is complete ionization of acceptors and donors? 20. What is a space charge in a pn junction? 21. What are the mechanisms of electric current flow in semiconductors? 22. What are characteristics of an ideal diode? 23. What are characteristics of actual diodes? 24. List different types of power diodes. 25. How do characteristics of actual diodes differ from those of an ideal diode? 26. How do characteristics of bipolar pn junction diodes differ from those of unipolar diodes like Schottky diodes? 27. How does the threshold voltage and saturation current depend on temperature for silicon pn junction diodes? 28. What is the typical maximum current density of silicon pn junction diodes and siliconcarbide Schottky diodes? 29. How can we achieve a high breakdown voltage of pn junction diodes? 30. How does the doping concentration affect the breakdown diode voltage? 31. Why are the edge terminations used in power diodes? 32. What kind of capacitances are present in pn junction diodes? 33. List the effects of the reverse recovery on pn junction diodes. 34. What is a rectifying and non-rectifying metal–semiconductor contact? 35. List the properties of Schottky diodes. 36. What kind of capacitance is present in Schottky diodes? 37. Under what condition is the metal–semiconductor contact ohmic (non-rectifying)? 38. Under what condition is the metal–semiconductor contact rectifying? 39. What is the dominant component of the current in Schottky diodes? 40. Describe in your own words the difference between n-type and p-type semiconductors. 41. Describe in your own words the difference between donors and acceptors. 42. Describe in your own words the difference between minority and majority carriers. 43. Why is an electric field formed in the depletion region? 44. Where does the maximum electric field intensity occur in the depletion region?

45. Why does the breakdown voltage of a pn junction decrease as the doping concentration increases? 46. How does the temperature affect the avalanche breakdown voltage? 47. Sketch the I–V characteristic of a solar cell. 48. Sketch the P–V characteristic of a solar cell. 49. What is the short-circuit current of a solar cell? 50. What is the open-circuit voltage of a solar cell? 51. How can different colors be obtained in an LED?

Problems Intrinsic Semiconductors 1. Determine the resistivity and the conductivity of intrinsic silicon at T = 300 K. 2. Determine the resistivity and the conductivity of intrinsic silicon carbide at T = 300 K. 3. An average hole drift velocity is vp = 103 cm/s, when a voltage V = 4 V is applied across a semiconductor bar of length L = 2 cm. What is the hole mobility μp inside the bar?

Extrinsic Semiconductors 4. A silicon sample is doped with 1.5 × 1016 boron atoms/cm3. There are 5 × 1022 silicon atoms/cm3. Find the electron and hole concentrations and the semiconductor resistivity and the conductivity at T = 300 K. What is the ratio of the silicon to boron atoms? What is the ratio p/n? What is the ratio of the resistivities of the intrinsic to doped silicon at T = 300 K? 5. Determine the resistivity of extrinsic silicon that is uniformly doped with ND = 1016 donors/cm3 at T = 300 K.

pn Junction 6. A silicon step junction diode has ND = 1016 cm− 3, NA = 1018 cm− 3, T = 300 K, and VD = 0. Find xp, xn, W, and xn/xp. 7. A silicon step junction diode has ND = 1014 cm− 3, NA = 1016 cm− 3, T = 300 K, and VD = 0. Find xp, xn, W, and xn/xp. 8. A silicon step junction diode has ND = 1014 cm− 3, NA = 1016 cm− 3, T = 300 K, and vD = −200 V. Find xp, xn, W, xn/xp, and Em.

9. A silicon step junction diode has ND = 1014 cm− 3, NA = 1016 cm− 3, T = 300 K, and vD = −600 V. Find xp, xn, W, xn/xp, and Em. 10. A SiC pn junction at T = 300 K with zero applied voltage bias has doping concentrations NA = 5 × 1015 cm− 3, ND = 5 × 1017 cm− 3, and vD = −1000 V. Determine: xn, xp, W, and Em. 11. A SiC step junction has: ND = 1014 cm− 3, NA = 1017 cm− 3, VD = −100 V, and T = 300 K. Find xn, xp, W, xn/xp, and Em.

Reverse Recovery 12. At time t = 0, the current of a p+ n diode was increased from 0 to IF with the rise time equal to zero. Derive an expression for the charge waveform Qp(t) and the diode voltage waveform vD(t). Draw these waveforms using MATLAB®. Neglect the junction capacitance. 13. At time t = 0, the current of a p+ n diode was reduced from IF to IR with the fall time equal to zero. Derive an expression for the charge waveform Qp(t) and draw it using MATLAB®. 14. A dc current source with current IF supplies a p+ n junction diode in the forward direction for a long time and at t = 0 it is suddenly removed. Derive an expression for the excess minority hole charge and draw Qp(t)/(τpIF) as a function of t/τp using MATLAB®. Find the time in terms of τp at which the initial charge decreases to 10% of its initial value. 15. A silicon-carbide pn junction diode has diF/dt < 0, fs = 1 MHz, VR = −600 V, IR = −5 A, and tt = 10 ns. Find the power dissipated during transient time tt. 16. In a p+ n diode with τp = 50 ns, the current is suddenly reduced from 2 A to − 10 A. Find the storage time ts.

Design of Power Diodes 17. Design a SiC diode to meet the following specifications: VBD = 600 V, IDmax = 5 A, Jmax = 100 A/cm2, and Vbi = 3 V. Find AJ, ND, ln, CJ0, and RDR. 18. Design a silicon diode to meet the following specifications: VBD = 50 V, IDmax = 5 A, and Jmax = 100 A/cm2. Find AJ, ND, xn, ln, CJ0, and RDR. 19. Design a SiC step junction diode for VBD = 1 kV and IDmax = 1 A at T = 300°C. Find Vbi, ln, lp, AJ, Em, Rn, Rp, VBD(PT), and CJ0. 20. Design a SiC Schottky diode to meet the specifications: VBD = 1000 V and ID = 5 A. The maximum current density is JD(max) = 80 A/cm2.

Note 1 Jan Czochralski (1885–1953) was a Polish chemist and metallurgist who invented the Czochralski method in 1916, which is used for growing single crystals (monocrystals) and producing semiconductor wafers. He was a Professor of Metallurgy at the Chemistry Department of Warsaw University of Technology, Poland.

18 Silicon and Silicon-Carbide Power MOSFETs 18.1 Introduction The concept of the metal–oxide–semiconductor field-effect transistor (MOSFET) was created in 1930s. The first MOSFET was built in the 1960s. The commercially available power MOSFETs were introduced in 1976. MOSFETs have led the revolution in the semiconductor industry. The MOSFET is by far the most widely used semiconductor device. The power MOSFETs are built using silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). In this chapter, the physical structure and the principle of operation of the enhancement-type power MOSFETs are described; the current–voltage characteristics are derived; short-channel effects are explored. The breakdown voltages are studied for silicon and silicon-carbide power MOSFETs. Expressions for the on-resistance and interelectrode capacitances are derived. A SPICE model of the MOSFET is presented. Power MOSFETs were studied in many publications [1–14].

18.2 Integrated MOSFETs Figure 18.1 shows a physical structure of an enhancement n-channel MOSFET. In integrated small-signal MOSFETs, the source and the drain are on the same side of the chip surface, causing horizontal current conduction. The depletion region of the reverse-biased drain-tobody pn junction diode spreads into the short channel, resulting in a low punch-through breakdown voltage between source and drain. If a MOSFET is designed to withstand high voltages, the channel length L must be increased, which reduces the aspect ratio W/L and the maximum drain current. The breakdown voltage is proportional to the channel length L, whereas the drain current is inversely proportional to the channel length L. The power MOSFET structure allows for a short channel and a high breakdown voltage, resolving the conflict between high current and high voltage in IC MOSFETs.

Figure 18.1 Physical structure of IC MOSFET.

18.3 Physical Structure of Power MOSFETs A physical structure of the discrete power enhancement-type n-channel power MOSFET (NMOS) is shown in Figure 18.2, which is called a vertical double-diffusion (DMOS, DMOSFET, or VDMOSFET) transistor because (1) the drain and source contacts are on the opposite sides of the die, causing vertical current conduction, and (2) two diffusions are used to fabricate first p-wells and second n+-sources.

Figure 18.2 Physical structure of n-channel power MOSFET (NMOS). Two diffusions are employed: one is to form the p-type body regions and the other is to form the n+-type source regions. This process is termed as the double-diffusion (DMOS) process. The MOSFET has four semiconductor layers: n+pn−n+. The transistor is fabricated on an n+substrate, which is a single-crystal silicon wafer that provides physical support to the device. The thickness of the substrate is usually from 400 to 900 μm. Typically, the substrate is an antimony-doped semiconductor with a thickness of 500 μm, a resistivity of 0.01 Ω • cm, and the resistance per unit area of 5 × 10− 4 Ω/cm2. The arsenic-doped substrate has a resistivity of 0.01 Ω • cm. Substrate resistivities up to 20 mΩ • cm are used for high-voltage devices and less then 5 mΩ • cm for low-voltage devices. Then an n−-drift region is grown as an epitaxial layer. Epitaxy produces a crystalline layer, which is an extension of the underlying semiconductor lattice. Additional silicon grows following the lattice pattern of the pre-existing crystal. Next, the p-type wells are diffused. The p-type wells are called the body regions. Finally, n+-sources are diffused. The drain current density J reaches 100 A/cm2. The body is internally shorted to the source by the source metal contact. A heavily doped, highly conductive, n+-polycrystalline silicon (called polysilicon) or metal is used as a gate electrode. Polycrystalline silicon can withstand high temperature without reacting with SiO2. The typical doping concentration of the polysilicon is ND = 1020 cm− 3. Polysilicon gate has a large

resistivity ρG, large gate resistance rG as compared to metal, resulting in a lower speed of the MOSFET. In contrast, metal gate has a low resistivity ρG, a low gate resistance rG, yielding a higher transistor speed. A thin layer of a gate silicon dioxide SiO2 is grown on the p-wells and the n− drift region, called the neck region. The gate oxide SiO2 is a good electrical insulator with the resistivity as high as 1018 Ω • cm, dielectric constant εr(ox) = 3.9, the breakdown voltage V/cm, band gap energy eV, and the concentration of free 8 − 3 2 − 3 electrons n < 10 m = 10 cm at T = 300 K. The thickness tox of the silicon dioxide SiO2 is in the range 0.01–1 μm with a typical value of 0.1 μm. It is in the range 400–1000 atom diameters. The gate oxide SiO2 is covered with a metal or a heavily doped n+-polysilicon, which behaves electrically like a metal electrode. The polysilicon or metal gate, the oxide insulator SiO2, and the channel form a capacitor. For vGS > 0, the positive charge is accumulated on the gate electrode and the negative charge is formed by the electrons in the induced channel. Therefore, an electric field is created, which is directed from the positive to negative charges. This field controls the density of electrons and holes in the channel, the channel conductivity, the channel resistance, and the charge movement in the channel, thus controlling the drain current iD. The region between the p-wells and the silicon dioxide SiO2 is the accumulation region. The n+-substrate and the n+-source form non-rectifying ohmic contacts with metal. The substrate is connected to the metal case. The doping concentration of the drift region ND is usually 1014–1015 cm− 3. The thickness of the drift region WD ranges from 10 to 60 μm. The doping of the p-wells is typically 1016 cm− 3 and is kept below 5 × 1016 cm− 3. The doping of the n+ sources is usually 1019 cm− 3. There are thousands of paralleled cells in the power MOSFET, as depicted in Figure 18.3. The channel length is typically L = 0.5–2 μm. The channel width W1 of each cell is from 20 to 100 μm. The channel width of all n cells is W = nW1. The MOSFET aspect ratio is W/L = nW1/L. There are various patterns of cells: squares on a square grid, squares on a hexagonal grid, squares on an offset square grid, hexagons on a hexagonal grid, hexagons on a square grid, and triangles on a square grid. HEXFET is the trademark of the International Rectifier MOSFETs, which consists of hexagonal cells. Figure 18.4 shows square cells on a square grid and hexagonal cells on a hexagonal grid. The cells have a square or hexagonal pattern to maximize the channel width W1 of each cell (equal to the perimeter of the p-well) and the aspect ratio W/L per unit die area. Figure 18.5 shows a cross section of the n-channel MOSFET with a square pattern. For square pattern cells, W1 = 4Wp, W = nW1 = 4nWp, and W/L = 4nWp/L, where Wp is the width of the p-well. The area of a single square cell is A1 = (Wp + dpp)2, where dpp is the distance between the p-wells. The area of all square cells is (18.1) Hence, the channel width per unit area for square cells is given by

(18.2) The channel width per unit area D = W/Ac is 0.07–0.17 m/mm2. The lower value of D corresponds to the high-voltage MOSFETs and the higher value of D is achieved for the lowvoltage MOSFETs. The cell density is defined as (18.3) Typically, there are 2500–5400 cells/mm2. Recent designs may have the cell density as high as 12.4 × 103 cells/mm2. The high current source and the gate bounding pads are not laid over the active semiconductor to increase the reliability. The field guard rings and field plate terminations are used around the corners and edges of the chip to prevent crowding of the electric field, causing peripheral voltage breakdown. Both the area of the pads Ap and the area of the field guard rings Ar increase the area of the chip by about 25%. The total chip area is (18.4) The chip area utilization is (18.5)

Figure 18.3 Three-dimensional structure of power MOSFETs.

Figure 18.4 Commonly used patterns of power MOSFET cells. (a) Squares on a square grid. (b) Hexagons on a hexagonal grid.

Figure 18.5 Square pattern of n-channel power MOSFET. In the p-channel enhancement-type MOSFET (PMOS), the dopant types, the voltage polarities, and the drain current direction are reversed, as illustrated in Figure 18.6. This transistor has

four layers: p+np−p+. The current flows from source to drain, and Vt < 0, vGS < 0, and vDS < 0. Applying a negative potential to the gate attracts holes in the n-wells under the gate, and the electrons are repelled away from the oxide–semiconductor interface. An overbalance of holes in the formerly n-type semiconductor causes an inversion. The n-type semiconductor becomes a p-type semiconductor, connecting the drain to the source. Holes are the charge carriers. Figure 18.7 shows circuit symbols for the enhancement-type MOSFETs.

Figure 18.6 Physical structure of p-channel power MOSFET (PMOS).

Figure 18.7 Complete and simplified circuit symbols for enhancement power MOSFETs. (a) For n-channel power MOSFET (NMOS). (b) For p-channel power MOSFET (PMOS).

18.4 Principle of Operation of Power MOSFETs 18.4.1 Cutoff Region For vGS ≤ 0 (more exactly for vGS < Vt), the drain and the source are isolated from each other because the pn junction is reverse-biased and there are no charge carriers (electrons) in the ptype material. The drain current iD is zero. The MOSFET channel is in the off-state. It is very important to have a high-quality, low-leakage current pn junction body diode to ensure a low off-state leakage current in the MOSFET.

18.4.2 Formation of MOSFET Channel For vGS > 0, the gate positive potential and the electric field at the Si–SiO2 interface attracts the minority carrier free electrons from the n+ source and the p-type body and repels the majority carrier free holes into the p-type body. The concentration of holes p is nearly equal to the acceptor doping concentration NA in the p-region body. The value of vGS at which the concentration of free electrons n below the oxide is equal to the concentration of holes (i.e., negative acceptor ions NA) is termed as the threshold voltage Vt. The semiconductor below the oxide becomes intrinsic and the pn junction disappears. This is called the threshold inversion point. The threshold voltage Vt increases with the thickness of SiO2 and the doping concentration NA in the p-region. Typical values of Vth are 0.5–4 V for high-voltage devices with thicker gate oxide and 1–2 V for low-voltage MOSFETs. When vGS > Vt, the concentration of free electrons becomes higher than that of holes and the area behaves like an n-type semiconductor and is called an inversion layer. This is because the p-type semiconductor is “inverted” into the n-type semiconductor. An n-type channel or conductive path is created, which connects the drain to the source. The lateral n-channel is induced in the p-wells beneath the gate dioxide SiO2 between the n-type drain and the n+-type source. The resulting channel is short and its thickness is of the order of 10 nm. The threshold voltage Vt is the minimum gate-to-source voltage required to induce the channel. The phenomenon used to modulate the conductivity of a semiconductor and control the current flow by applying an electric field is called the field effect. If the drain-to-source voltage vDS is applied, the drain current iD flows between drain and source through the induced n-channel, carried by the mobile free electrons, which are majority carriers. For vGS > Vt and vDS > 0, iD > 0. Current is conducted by electrons from the source, moving horizontally through the channel, and then vertically down through the neck, the drift region, and the substrate to the drain. For vGS > Vt and vDS < 0, iD < 0 and electrons flow from the drain to source.

18.4.3 Linear Region For vDS < vGS − Vt and vGS > Vt, the electron drift current, equal to the drain current iD, increases almost linearly with the increase in the drain-to-source voltage vDS at a given

voltage vGS. As the gate-to-source voltage vGS is increased, more electrons are attracted to the channel, reducing the channel resistivity and the channel resistance rDS. Therefore, the MOSFET looks electrically like the gate-to-source voltage controlled n-type channel resistor rDS(vGS). Other components of the drain-to-source resistance are neglected in this stage of the analysis. This mode of operation is called the linear region, ohmic region, or triode region because iD = vDS/rDS. When the gate-to-source voltage vGS increases, the slope of nearly linear iD–vDS characteristics increases, which means that the channel-on resistance rDS decreases. The voltage-controlled resistor (VCR) can be called the transfer resistor, which led to the name transistor. The drain current flow iD takes place by the movement of only one type of carriers, which are electrons in NMOS. The electrons are the majority charge carriers in NMOS transistors. Therefore, MOSFETs belong to the family of unipolar semiconductor devices. Due to the absence of minority carrier transport, MOSFETs can be switched on and off at high frequencies. The channel resistance is in the range: 5 mΩ ≤ rDS ≤ ∞. Therefore, MOSFETs are very attractive electronic ON–OFF switches for power electronics applications. The gate-to-drain voltage is vGD = vGS − vDS. For vDS < vGS − Vt > 0 and vGS > Vt, iD > 0 and the voltage vDS drops along the channel due to the channel distributed resistance rDS. This voltage increases from 0 at the source end to vDS at the drain end. As vDS increases, the drain current iD increases, and the ohmic voltage drop along the channel also increases. The overall voltage along the channel decreases from vGD = vGS at the source end to vGD = vGS − vDS at the drain end. As a result, the largest channel depth is at the source end and the smallest is at the drain end, as shown in Figure 18.8. At vGD = Vt = vGS − vDSsat, the drain-to-source voltage at the drain reaches the saturation value vDSsat = vGS − Vt, at vGD = Vt = vGS − vDSsat, the channel depth at the drain end is reduced to almost zero, and the channel is said to be pinched off.

Figure 18.8 Channel structure in the linear region when vDS increases at vGS > Vt.

18.4.4 Saturation Region As the drain-to-source voltage vDS increases beyond vDSsat, the point at which the channel is pinched off moves more and more into the channel, closer to the source end. The electric field intensity E along the channel in the pinch-off region is very high, and the electrons in this part of the channel travel at the saturation drift velocity vsat. Therefore, the drain current does not increase with increasing voltage vDS. When vDS ≥ vGS − Vt and vGS > Vt, the drain current saturates and remains nearly constant, independent of vDS. The additional drain-to-source voltage ΔvDS = vDS − vDSsat is dropped across the depletion region in the range from the pinchoff point to the drain end, as shown in Figure 18.9. This mode of operation is called the saturation region or pinch-off region. When vGS increases, iD also increases. The transistor in the pinch-off region behaves like a voltage-dependent current source.

Figure 18.9 Channel structure in the saturation region when vDS increases. at vGS > Vt.

18.4.5 Antiparallel Diode For vGS ≤ Vt, the transistor channel is in the cutoff region. The p-type body well and the lightly doped n−type drift region form a pn junction, which prevents the current flow and supports a high voltage drop. The pn junction is reverse-biased, so the MOSFET channel disappears, and the MOSFET channel is OFF. The diode is called the body diode or antiparallel body diode. As the drain-to-source voltage vDS increases, the pn junction depletion region extends into the drift region because the doping of the drift region is much lower than that of the body region. The MOSFET drain-to-source breakdown voltage, denoted by VBD or BVDSS, is caused by the avalanche breakdown of the body pn junction diode and is determined by the drift region. The junction breakdown voltage VBD increases as the drift region thickness WD increases and the drift region doping concentration ND decreases. The voltage BVDSS is measured with the gate shorted to the source so that VGS = 0 and at ID = 0.25 mA. If vGS < Vt and iD < 0, the channel is OFF and the body diode conducts the current iD. If vGS > Vt, vDS < 0, and the voltage drop across the MOSFET on-resistance rDS is greater than 0.7 V (i.e., |rDSiD| > 0.7 V), then the body diode is ON, and both the channel and the body diode conduct negative current iD. At high negative currents, the body diode conducts much more current than the channel. When the transistor is turned off at a large negative current iD, the body diode suffers from reverse recovery.

18.5 Derivation of Power MOSFET Characteristics 18.5.1 Ohmic Region Consider the situation shown in Figure 18.10(a), where vGS > Vt and vDS = 0. In this case, vGD = vGS − vDS = vGS > Vt and therefore a channel is induced. The electron charge stored in the channel is given by (18.6) where the gate-oxide-channel capacitance is (18.7) the gate-oxide-channel capacitance (or oxide capacitance) per unit area is (18.8) L is the channel length, W is the channel width, AG = WL is the gate area, and tox is the silicon oxide (SiO2) thickness. As the silicon oxide thickness tox decreases, Cox increases, and the field effect becomes stronger. If the electrons travel the length of the channel L with the average electron drift velocity v, the time it takes to travel that distance is given by (18.9) Hence, the drain current (i.e., the movement of charge) is (18.10) where the electron charge per unit length is uniform along the channel and is expressed by (18.11) The electron charge per unit length QL is directly proportional to vGS − Vt. Assuming that the space-charge density in the channel is uniform, we have (18.12) where A = WH is the inverted-channel cross-sectional area perpendicular to the direction of the drain current flow, Vol = LWH = LA is the channel volume, and H is the channel height. The electron density in the channel is

(18.13) Hence, the channel conductivity is (18.14) This equation describes the channel conductivity modulation by the gate-to-source voltage vGS. The space-charge density ρv, the electron density n in the channel, and the channel conductivity σn are directly proportional to the voltage vGS − Vt that induces the channel. The conductivity σn is also directly proportional to the electron mobility μn in the channel.

Figure 18.10 Voltages in the MOSFET structure in the linear region. (a) For vDS = 0. (b) For 0 < vDS < vDSsat. If the drain-to-source voltage vDS > 0 and is very low, e.g., 0.1 V, vGD > Vt, the voltage drop along the channel will be very low and its effect on the channel height along the channel can be neglected. The channel conductivity σn remains approximately uniform in the linear region at very low values of voltage vDS. The electric field intensity along the channel from drain to source is (18.15) The drain current density J is equal to the drift current density caused by the movement of charge carriers forced by the electric field E

(18.16) Hence, the drain current is given by (18.17) The large-signal channel resistance at a very low drain-to-source voltage is (18.18) Now, consider the situation depicted in Figure 18.10(b), where vGS > Vt, 0 < vDS < vDSsat, and iD > 0. The channel is induced, but it is not pinched off. There is a lateral voltage drop along the channel due to the voltage vDS, which changes from point to point. Let us denote the voltage drop along the channel from the source end to a point x by V(x). From KVL, the voltage between the gate electrode and any local point x in the channel is (18.19) At the source end, V(0) = 0, resulting in (18.20) At the drain end, V(L) = vDS, producing (18.21) As vDS increases at a fixed voltage vGS, the voltage vGD decreases. The charge stored in the channel is (18.22) The electron charge per unit length at point x is (18.23) The space-charge density is given by (18.24) The electron density in the channel is (18.25)

The conductivity of the channel depends on x and is given by (18.26) The channel conductivity σn(x) decreases as x increases from the source to the drain. The electric field along the channel is given by (18.27) The average drift electron velocity caused by the electric field E is (18.28) The drain current is (18.29) where vn = L/t is the average electron drift velocity. Hence, the drain current is given by (18.30) Since the drain current iD along the channel remains constant, V(x) and dV(x)/dx vary in such a way that the product of vGS − Vt − V(x) and dV(x)/dx is independent of x. Regrouping (18.30), we get (18.31) Integrating both sides of the above equation, (18.32) one obtains the drain current for the linear region (18.33)

The first term represents the magnitude of the average charge per unit length in the channel |Qn|/L because the average voltage along the channel is VAV = vDS/2. The second term represents the magnitude of the average electron drift velocity in the channel |vAV| = μnEAV = μnvDS/L, where the average electric field along the channel is EAV = vDS/L.

In summary, a larger Cox and a higher voltage vGS result in a larger electron density n in the channel. A higher gate-to-source voltage vGS yields a higher channel conductivity σn and a lower channel resistance RCh. The voltage drop along the channel inversion layer vCh becomes low for high values of vGS. A higher drain-to-source voltage vDS forces a larger drain current iD. The drain current iD increases quadratically with increasing vDS for a given vGS and reaches the saturation level iD(sat) at vDSsat = vGS − Vt. The large-signal channel resistance is (18.34) This equation simplifies to the form (18.35)

18.5.2 Pinch-off Region At the boundary between the linear region and the saturation region, vGS > Vt, vDS = vDSsat = vGS − Vt, vGD = Vt, and the channel is pinched off just at the drain, as shown in Figure 18.11(a). Substitution of this condition into (18.33) yields the drain current in the saturation region (18.36) The first term represents the magnitude of the average electron charge in the inversion layer, where the average voltage along the inverted channel region is (vGS − Vt)/2, which is independent of vDS. The second term represents the magnitude of the average drift electron velocity in the channel |vAV| = μnEAV = μn(vGS − Vt)/L.

Figure 18.11 Voltages in the MOSFET structure in the saturation region. (a) The channel is pinched off at the drain. (b) The channel is pinched off between the drain and the source. At vGS > Vt and vDS > vGS − Vt, the channel is pinched off between the drain and the source at a point xpo, where V(xpo) = vGS − Vt, that is, at vox = vGS − V(xpo) = Vt. Figure 18.11(b) shows this situation. The voltage drop across the inverted channel between the source and the end of the channel xpo is vch = vGS − Vt. The voltage across the pinched off region located between the point xpo and the drain is vpinch = vDS − vDSsat. The electrons flow from the source to the pinched-off point xpo through the inverted channel, and then are injected into the depletion region between the pinched-off point xpo and the drain. A high electric field in the depletion region sweeps the electrons into the drain. The voltage across the channel is a constant, which is equal to v(xpo) = vGS − Vt. Therefore, the drain current iD is approximately constant and nearly independent of the voltage vDS.

18.5.3 Channel-Length Modulation

Figure 18.12 shows a channel profile in the saturation region. As the drain-to-source voltage vDS increases at a fixed voltage VGS0 in the saturation region, the pinched-off point xpo moves from the drain toward the source and the length of the inverted channel is reduced, resulting in increased drain current. The ratio is (18.37) and (18.38) The effective channel length is (18.39) The phenomenon of channel length variation with voltage vDS is called the channel-length modulation. The drain current in the saturation region is given by (18.40)

Figure 18.12 Channel profile in the saturation (pinch-off) region. Thus, iD > iD(sat) for vDS > vDSsat. As the channel length L decreases, the ratio ΔL/L increases. Therefore, the slope of iD–vDS characteristics increases more in short channel MOSFETs.

18.6 Power MOSFET Characteristics The MOSFET characteristics for the cutoff (or voltage blocking), linear (ohmic or triode), and saturation (or pinch-off) regions are given by (18.41)

where K is the device parameter described by (18.42) W/L is the aspect ratio, μn is the electron mobility in the channel, also called the surface mobility or the effective mobility. Typically, the surface mobility μn = 600 cm2/V • s for Si, Cox is the oxide capacitance C per unit area of the gate-oxide-channel capacitor with the oxide SiO2 acting as a dielectric (18.43)

εox = εrε0 is the oxide permittivity, , ε0 = 8.8542 × 10− 14 F/cm = 8.8542 × 10− 12 F/m, Aox is the silicon dioxide SiO2 area, tox is the silicon dioxide SiO2 thickness, kp is the process constant (also called the transconductance parameter) given by (18.44) Vt is the threshold voltage, defined as the gate-to-source voltage at which the MOSFET begins to conduct and it is increased by the body effect when VSB > 0 (18.45) Vt0 is the threshold voltage at the source-to-body voltage VSB = 0 and the typical values of Vt0 are from 1 to 4 V for power MOSFETs, λ = 1/VA is the channel-length modulation coefficient, which is in the range 0.001 V− 1 ≤ λ ≤ 0.1 V− 1, VA is the early voltage, ϕF is the surface potential, where 2ϕF is in the range 0.3 V≤ 2ϕF ≤ 1 V, and γ is the body-effect parameter, which is in the range parameter is given by

. Typically, γ = 0.5 V1/2 and 2ϕF = 0.6 V. The body-effect

(18.46) The first term of the threshold voltage is given by (18.47)

where Vfb is the flat-band voltage. The threshold voltage Vt0 can be decreased by deliberately decreasing the p-well body doping concentration NA and by decreasing tox. However, the body doping concentration NA is constrained by the need to avoid or to reduce the channel-length modulation effect caused by vDS. Reducing tox makes the MOSFET more vulnerable to gateoxide voltage breakdown. The MOSFET threshold voltage Vt0 is measured at VGD = 0 and ID = 0.25 mA. The electron mobility μn in the channel (i.e., the surface mobility) is lower than that in the bulk of silicon. In addition to lattice and ionized impurity scattering, the mobility in the channel is limited by the surface collisions. The majority carriers move in the MOSFET channel from the source to the drain and encounter microscopic roughness on the semiconductor–oxide interface. When the voltage vGS increases, the gate-induced electric field E accelerates the

carriers toward the semiconductor-oxide interface, causing the collisions with interface defects due to the interfacial roughness. Therefore, the surface carrier mobility is reduced. The typical value of the low-field surface electron mobility μn in silicon MOSFET channels is 600 cm2/V • s at T = 300 K. As the electric field intensity E increases from 0 to 6 × 105 V/cm, the surface electron mobility decreases from 800 to 400 cm2/(V • s) at T = 25°C, from 500 to 300 cm2/(V • s) at T = 100°C, and from 400 to 200 cm2/(V • s) at T = 140°C. The output MOSFET characteristics get steeper as the drain current increases with increasing gate-to-source voltage vGS. If the iD–vDS characteristics are extended to the left, they meet and intersect the vDS axis at voltage − VA = −1/λ. As tox decreases, Cox and kp increase. The drain-to-source voltage at the boundary between the linear and saturation regions is (18.48) The drain saturation current is (18.49) In discrete power MOSFETs, the body is internally connected to the source to keep the body diode reverse-biased for most of the modes of operation. To increase the current capability of the power MOSFET, its width W should be made very large and the length should be made as small as possible. Figure 18.13 shows the n-channel MOSFET vGS–iD and vDS–iD characteristics.

Figure 18.13 Input and output characteristics of n-channel MOSFET.

The maximum rms drain current is limited by the MOSFET power loss. Assuming that the conduction loss PrDS in the MOSFET on-resistance rDS is dominant, the maximum rms value of the drain current is (18.50)

Since the MOSFET on-resistance rDS increases with increasing breakdown voltage VDSS, the maximum rms drain current IDrms(max) decreases with increasing breakdown voltage VDSS. The maximum gate-to-source voltage is ± VGS(max) = ±20 V. The threshold voltage Vt is in the range 2–4 V. A typical maximum operating junction temperature TJ(max) for silicon power MOSFETs is 150°C. The maximum case temperature TC(max) is typically 100°C. For siliconcarbide power MOSFETs, the maximum operating junction temperature is much higher, usually about 300°C. The junction-to-case thermal resistance θJC is typically 1°C/W for silicon devices and θJC is typically 0.3°C/W for silicon-carbide devices. The threshold voltage Vt0 exhibits a negative thermal coefficient (18.51) However, kp decreases with increasing temperature T. The slope of the vGS–iD characteristic decreases when the temperature increases. The drain current iD exhibits a negative thermal coefficient for its higher values. Therefore, MOSFETs do not suffer from thermal runaway at high currents. The parameters of the IRF540 power MOSFET are: VDSS = 100 V, IDmax = 28 A, rDS(ON) = 0.077 Ω, W/L = 1.4 × 106, Vt = 3.5 V, W = 1 m, μn = 0.06 m2/V • s = 600 cm2/V • s, Cox = 3.45 × 10− 4 F/m2 = 3.45 × 10− 8 F/cm2 = 34.5 nF/cm2, and θ = 0.02 V− 1. Hence, kp = μnCox = 0.06 × 3.45 × 10− 4 = 20.7 μA/V2, 106/(1.4 × 106) = 0.7 μm, and

A/V2, L = m.

18.7 Mobility of Charge Carriers The charge carriers in a solid are in constant motion at T > 0 K. Holes and free electrons move through a crystal structure in a random manner at high speed of the order of 107 cm/s, encountering frequent collisions with the vibrating atoms, other electrons, and defects. An applied electric field E exerts forces on the charge carriers, causing them to acquire small average drift velocity. The drift velocity is superimposed on the thermal motion and is much lower than the thermal velocity. Holes move in the direction of the applied field and electrons move in the opposite direction to the electric field. This results in electron and hole drift

currents. The mobility describes the freedom (or the ease) of movement of carriers in a crystal. It has significant influence on the electron and hole transport and the drift region resistance. The mobility of electrons μn is greater than the mobility of holes μp. The bulk carrier mobility is inversely proportional to the amount of scattering within the semiconductor. There are two major scattering mechanisms: (1) the lattice scattering involving collisions with vibrating lattice atoms and (2) ionized acceptors and donors scattering. The thermal vibrations cause the displacement of lattice atoms from their lattice positions. The velocity of a carrier increases linearly with time between the collisions. The velocity just before the collision at time tc is (18.52) where F = qE, a = F/me = qE/me is the acceleration, and me is the electron effective mass. The average drift velocity is vd = vf /2. Thus, the mobility is given by (18.53) where tc is the mean free time interval between the collisions, called the relaxation time. As the number of collisions increases, the mean free time tc decreases, reducing the mobility μ. The mobilities are functions of doping concentration ND or NA, temperature T, and electric field intensity E, that is, μn = f(N, T, E) and μp = f(N, T, E).

18.7.1 Effect of Doping Concentration on Mobility At low doping concentration ND or NA, the mobilities are almost independent of the doping concentrations because the ionized impurity scattering is much lower than the lattice scattering and can be neglected. For silicon, the critical concentration Nc = 1015 cm− 3. At high doping concentrations, the mobilities μn and μp monotonically decrease with increasing doping concentration ND or NA, respectively. This is because the ionized impurity scattering is no longer negligible. The carrier mobility in terms of total doping concentration N = NA + ND at room temperature is given by the Caughey-Thomas equation [12] (18.54) where μ0 = μmax − μmin. For silicon, the low-field doping-dependent bulk mobilities of electrons and holes as majority current carrier at room temperature T = 300 K are given by [10]

(18.55)

and (18.56)

Figure 18.14 shows the mobilities μn and μp as functions of doping concentration N = ND or NA at T = 300 K for silicon. At ND = 1017/cm− 3, μn ≈ 770 cm2/(V • s), and at NA = 1017, μp ≈ 220 cm− 3/(V • s).

Figure 18.14 Low-field electron mobility μn and hole mobility μp as functions of doping concentration N at T = 300 K for silicon. The resistivities of the n-type and p-type semiconductors are

(18.57) and (18.58) where q = 1.602 × 10− 19 C. Figure 18.15 shows the resistivities ρn and ρp as functions of doping concentration at T = 300 K computed from (18.55) through (18.58) for silicon.

Figure 18.15 Low-field resistivities ρn and ρp as functions of doping concentration N at T = 300 K for silicon. For silicon carbide, the low-field mobilities of electrons and holes at T = 300 K are given by (18.59)

and (18.60)

Figure 18.16 and 18.17 show the low-field mobilities μn and μp and resistivities ρn and ρp as functions of doping concentration N at T = 300 K for silicon carbide.

Figure 18.16 Low-field electron mobility μn and hole mobility μp as functions of doping concentration N at T = 300 K for silicon carbide.

Figure 18.17 Low-field resistivities ρn and ρp as functions of doping concentration N at T = 300 K for silicon carbide.

18.7.2 Effect of Temperature on Mobility The atoms in a crystal vibrate due to their thermal energies. When the temperature of a crystal is increased, the amplitude of the atom vibrations also increases. This results in more frequent collisions between the charge carriers and the atoms, reducing the mobility. The general dependence of the mobility on temperature is (18.61) For silicon, the low-field electron and hole mobilities decrease with increasing temperature T and are given by

(18.62)

and (18.63)

For silicon, the low-field mobilities are μn0 = 639 cm2/V • s and μp0 = 230 cm2/V • s at T = 150°C and N = 1015 cm− 3. Figure 18.18 shows plots of the low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at N = 1015 cm− 3 for silicon. Figure 18.19 shows a 3-D plot of the low-field electron mobility μn as a function of the doping concentration N and temperature T for silicon.

Figure 18.18 Low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon.

Figure 18.19 Low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon. For silicon carbide, (18.64)

and (18.65)

Figure 18.20 show plots of the low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T for silicon carbide.

Figure 18.20 Low-field electron mobility μn0 and hole mobility μp0 as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon carbide. The resistivities of n-type and p-type silicon semiconductors as a function of temperature T are given by (18.66) and (18.67) Figure 18.21 shows plots of resistivities ρn and ρp as functions of temperature T at N = 1015 cm− 3 for silicon.

Figure 18.21 Resistivities ρn and ρp as functions of temperature T at constant doping concentration N = 1015 cm− 3 for silicon. The resistivities of n-type and p-type silicon-carbide semiconductors as a function of temperature T are given by (18.68) and (18.69)

18.7.3 Effect of Electric Field on Mobility If an electric field E is applied to a semiconductor, the holes move as a group in the direction of the electric field intensity E and the electrons move as a group in the opposite direction. In

steady state, the carriers gain a net drift velocity from the electric field intensity E. In general, the group average electron drift velocity (over a large number of electrons) in a uniform electric field E is given by (18.70) The mobility μn = vn/E is the average drift speed of electrons or holes (as a group) vn, when the applied electric field intensity E is 1 V/m. The average drift electron velocity in terms of the electric field intensity E is given by (18.71) where Esat = vsat/μn0. Hence, the electron field-dependent mobility is (18.72) Figures 18.22 and 18.23 show the average electron drift velocity v and the electron mobility μn as functions of electric field intensity E for silicon at μn0 = 1360 cm2/V • s and vsat = 8 × 106 cm/s. At low values of the electric field intensity E, the average carrier velocity v is nearly directly proportional to the electric field strength E because the carrier mobility is approximately constant. When the electric field intensity E approaches a sufficiently high level, the carriers collide with the lattice so frequently and the time between the collisions is so short that they do not accelerate much. At high levels of the electric field intensity E, the increase in the electron drift velocity v is very slow with increasing E because the scattering rate dramatically increases. At a very high electric field intensity E, the velocity reaches a saturation level vsat and is independent of the electric field E. Therefore, the mobility is inversely proportional to the electric field intensity E. The saturation velocities of electrons and holes are characteristic parameters of each semiconductor material. For silicon, vsat = 8 × 106 cm/s. The average electron velocity vn = vsat/2 for Esat = 6 × 103 V/cm = 0.6 V/μm. For silicon carbide, vsat = 2.7 × 107 cm/s. A significant portion of the carrier transport occurs under strong electric fields. Therefore, high-field carrier transport dominates the device performance. The following approximations can be made for the average electron drift velocity v and the electron mobility μn.

Figure 18.22 Average electron drift velocity vn as a function of electric field intensity E for μn0 = 1360 cm2/V • s, vsat = 8 × 106 cm/s, and T = 300 K for silicon.

Figure 18.23 Electron mobility μn as a function of electric field intensity E for μn0 = 1360 cm2/V • s, vsat = 8 × 106 cm/s, and T = 300 K for silicon. The electron mobility in terms of the electric field E and temperature T is (18.73) Figure 18.24 shows a plot of μn as a function of E and T at μn0 = 1360 cm2/V • s and vsat = 8 × 106 cm/s.

Figure 18.24 Electron mobility μn as a function of electric field intensity E and temperature T for μn0 = 1360 cm2/V • s, vsat = 8 × 106 cm/s for silicon. The resistivities of n-type and p-type semiconductors as functions of the electric field intensity E are given by (18.74) and (18.75) Figure 18.25 shows plots of resistivities ρn and ρp as functions of the electric field intensity E for silicon.

Figure 18.25 Resistivities of ρn and ρp as functions of electric field intensity E for μn0 = 1360 cm2/V • s, μp0 = 480 cm2/V • s, vsat = 8 × 106 cm/s, N = 1015 cm− 3, and T = 300 K for silicon. Low-Field Range. For silicon, the low-field electron mobility is approximately constant and is given by (18.76) and the low-field average electron drift velocity is directly proportional to the electric field intensity E (18.77) Intermediate-Field Range. For silicon, the intermediate-field electron mobility is fielddependent and decreases with increasing E (18.78)

The intermediate-field average drift electron velocity is (18.79) High-Field Range. For silicon, the high-field average drift electron velocity is equal to the saturation drift velocity (18.80) Hence, the electron mobility is inversely proportional to the electric field intensity E (18.81) At the silicon breakdown electric field EBD = 2 × 105 V/cm and T = 300 K, the average electron drift mobility is (18.82) Hence, (18.83) Figures 18.26 and 18.27 show the average electron drift velocity v and the electron mobility μn as functions of electric field intensity E at T = 300 K for silicon carbide.

Figure 18.26 Average electron drift velocity vn as a function of electric field intensity E for silicon carbide.

Figure 18.27 Electron mobility μn as a function of electric field intensity E for silicon carbide. The average drift saturation velocity decreases with increasing temperature. For silicon, the saturation velocities of electrons and holes are given by (18.84) and (18.85) From these equations, vn(sat) = 7.44 × 106 cm/s and vp(sat) = 6.997 × 106 cm/s at T = 150°C. The drift saturation velocity of holes is about 20% lower than that of electrons at T = 300 K. However, this difference decreases with increasing temperature and both velocities are equal at T = 500 K. Figure 18.28 shows the electron saturation drift velocity vn(sat) and the hole saturation drift velocity vp(sat) as functions of temperature T for silicon.

Figure 18.28 Electron saturation drift velocity vn(sat) and hole saturation drift velocity vp(sat) as functions of temperature T for silicon.

18.8 Short-Channel Effects The short-channel effects are as follows: 1. The decrease in the carrier mobility μn in the channel. 2. The carrier velocity saturates. 3. The decrease in the threshold voltage Vt. 4. The decrease in VA and the increase in λ. 5. The decrease in vDSsat and the increase in iDsat. The electric field distribution in the MOSFET channel is very complex and depends on both the drain-to-source voltage vDS and the gate-to-source voltage vGS. The carrier mobility μn

decreases with increasing electric field E along the channel. Therefore, the average carrier drift velocity first increases with increasing E, and then saturates at high levels of the electric field. along the channel E. For short channels, there is a change in the electric field distribution due to edge effect. Therefore, the threshold voltage Vt decreases with decreasing channel length L (18.86) where Cd is the drain-channel capacitance per unit area.

18.8.1 Ohmic Region Figure 18.8 shows the channel profile in the ohmic region (the linear region), where vDS < vDSsat = vGS − Vt. The electric field intensity in the channel at vDS is (18.87) The electron mobility in the channel at any electric field intensity E is (18.88) The drain current at any average electron drift velocity vn for the ohmic region is (18.89)

Thus, the drain current iD decreases when the electron mobility μn in the channel decreases. Therefore, the channel on-resistance also increases. The drain current in the ohmic region at any average drift electron velocity vn can be expressed as (18.90)

For high-electric field in the channel, vn = vsat and the drain current becomes (18.91) The drain saturation current at vn = vsat is (18.92) For example, the minimum channel length of a silicon MOSFET for low-field operation (i.e., a long channel) at vDS = 0.3 V < vDSsat is (18.93) The maximum channel length of a silicon MOSFET for high-field operation (i.e., a short channel) at vDS = 0.3 V < vDSsat is (18.94) The channel length is intermediate for the range: 50 nm ≤ L ≤ 1 μm.

18.8.2 Pinch-off Region Figure 18.9 shows the channel profile in the pinch-off region (the saturation region) where vDS ≥ vDSsat. At the boundary between the ohmic and pinch-off regions, (18.95) The electric field intensity in the channel at vDSsat is (18.96) where Le = L(1 − λvDS). The electron mobility in the channel at any electric field intensity E is (18.97) where Esat = vsat/μn0 and θ = μn0/(vsatLe) is the mobility degradation coefficient and its typical value ranges from 0.01 to 0.4 V− 1. For the pinch-off region, the drain current at any electric field intensity E in the channel is given by

(18.98)

where θ = μn0/(vsatL) is the mobility degradation coefficient and its typical value ranges from 0.01 to 0.2 1/V. The average electron drift velocity in the pinch-off region is (18.99) For the pinch-off region, the drain current at any value of the average carrier drift velocity vn is given by (18.100)

At vn = vsat, the drain current in the pinch-off region for high field is given by (18.101)

For short-channel MOSFETs that operate in the drift velocity saturated region, the drain current iD is proportional to (vGS − Vt) rather than to (vGS − Vt)2. Equation (18.101) indicates that the drain current is governed by a linear law for vn = vsat. In addition, the drain current iD is independent of the channel length L for a short channel. For example, the minimum channel length of a silicon MOSFET for low-field operation at vDSsat = 0.6 V is (18.102) The maximum channel length of a silicon MOSFET for high-field operation at vDSsat = 0.6 V is

(18.103) The intermediate channel length occurs for 0.1 μm ≤ L ≤ 2 μm. Figure 18.29 shows the iD–vGS characteristics described by the square law, linear law, and exact equation at Vt = 1 V, μn0 = 600 cm2/(V • s), mF/m2, W/L = 105, vsat = 8 × 106 cm/s, and λ = 0. For the linear law case, L = 0.5 μm and W = 0.5 × 105 μm. For L = 0.5 μm, θ = 0.06/(8 × 104 × 0.5 × 10− 6) = 0.375. Figure 18.30 shows the iD–vGS characteristics at fixed gate-to-source voltage VGS0 described by the low-field, intermediate field, and high-field effects.

Figure 18.29 MOSFET iD–vGS characteristics described by square law, linear law, and exact equation for Vt = 1 V, μn0 = 600 cm2/(V • s), mF/m2, W/L = 105, vsat = 8 × 106 cm/s, and λ = 0. Exact plot: L = 2 μm and θ = 1.51/V. Linear law: L = 0.5 μm and W = 0.5 × 105 μm.

Figure 18.30 MOSFET iD–vDS characteristics described by square law, linear law, and exact equation at a fixed gate-to-source voltage vGS0 for Vt = 1 V, μn0 = 600 cm2/(V • s), mF/m2, W/L = 105, vsat = 8 × 106 cm/s, and λ = 0. Exact plot: L = 2 μm and θ = 0.375. Linear law: L = 0.5 μm and W = 0.5 × 105 μm. The short-channel effect also reduces the MOSFET effective channel length Le and the threshold voltage Vt. As Le decreases, Vt becomes closer to zero. In addition, λ is inversely proportional to the channel length. For this reason, the slope of the iD–vDS characteristics is high in the saturation region at short channel. Most devices operate with characteristics intermediate between the constant mobility and the constant velocity. If the constant velocity saturation dominates, the iD–vDS characteristics are more evenly spaced compared to those with the long-channel, constant mobility case.

18.9 Aspect Ratio of Power MOSFETs The current capability of power MOSFETs increases as the aspect ratio W/L increases. The channel of power MOSFETs is short and very wide. The maximum drain saturation current IDsat at the maximum gate-to-source voltage VGSmax is given by

(18.104) For the MOSFET to operate properly as a switch, the maximum switch current ISMmax must be sufficiently lower than IDsat. For example, if (18.105) then the minimum aspect ratio of the MOSFET is given by (18.106) where a is in the range 0.05–0.75 and VGSmax is the maximum gate voltage. For instance, for ISMmax = 10 A, VGSmax = 8 V, Vt = 3 V, kp = 20 μA/V2, L = 1 μm, and a = 0.5, we obtain (W/L)min = 8 × 104 and W = 8 × 104 μm = 8 cm. At high drain currents, the internal parasitic source resistance RS or a current sensing resistor reduces the gate-to-source voltage vGS = vG − RSiD and can cause considerable degradation of the MOSFET characteristics. For the saturation region with a long channel, (18.107) Hence, the aspect ratio is (18.108) Therefore, a larger aspect ratio (W/L) may be required [13] (18.109)

18.10 Breakdown Voltage of Power MOSFETs The blocking voltage capability of power MOSFETs is determined by the avalanche breakdown voltage of the body diode, formed by the p-wells and the n− drain region. Since this is a pn− diode, the drift region is lightly doped, the reverse-biased depletion region extends mostly into the lightly doped drain region and does not spread into the channel. Therefore, the voltage breakdown of power MOSFETs is determined by the avalanche voltage breakdown of the n− side of the depletion region. The avalanche breakdown voltage of a pn junction (the body diode) is given by

(18.110) where ε0 = 8.8542 × 10− 14 F/cm, εr is the semiconductor dielectric constant, q = 1.60219 × 10− 19 C is the magnitude of the electron charge, EBD is the breakdown electric field, NA is acceptor density, and ND is donor density. For Si, εr(Si) = 11.7. where ε0 = 8.8542 × 10− 14 F/cm, εr is the semiconductor dielectric constant, q = 1.60219 × 10− 19 C is the magnitude of the electron charge, EBD is the breakdown electric field, NA is acceptor density, and ND is donor density. For Si, εr(Si) = 11.7. For SiC, εr(SiC) = 9.7. For Si, the theoretical value of the breakdown electric field EBD is 300,000 V/cm and the measured value is 200,000 V/cm = 20 V/μm. For SiC, EBD = 2.2 × 106 V/cm. The band gap energy of silicon is EG = 1.12 eV at T = 300 K and EG = 2.26 eV for silicon carbide. The breakdown voltage VBD is proportional to . The maximum doping concentration of the drift region for the n-channel MOSFET is (18.111) For the pn− junction, the n-type drift region with donor density ND is much more lightly doped than the p-side region with acceptor density NA, that is, ND NA. Hence, for Si n-channel power MOSFETs, (18.112) where ND is in 1/cm3. The breakdown voltage VBD is inversely proportional to the doping density ND. In high-voltage MOSFETs, the drain doping concentration ND is low. Rearrangement of the expression (18.110) for the avalanche breakdown voltage for pn junction diodes given by (18.110) produces (18.113) Substituting this equation into (17.75) for xn and setting vDS = −vD = VBD, we obtain the required minimum thickness of the depletion region of the pn junction body diode on the lightly doped n−side extending into the drift region at the maximum doping concentration required to support the blocking voltage

(18.114)

For ND NA, Vbi VBD, and ND = NDmin, (18.115) The required depletion layer thickness WD is directly proportional to the breakdown voltage VBD. In real designs, the concentration is usually lower than the maximum value. Also, the thickness WD is usually larger than its minimum value. For silicon MOSFETs with ND NA, Vbi VBD, and ND = NDmin, (18.116) The lowest drain thickness WD is located between the n+ substrate and the p-wells. In highvoltage MOSFETs, the drain region is thick. Some of the standard breakdown voltages (VBD = VDSS) of silicon power MOSFETs are 20, 50, 100, 200, 400, and 500 V. Silicon MOSFETs serve applications employing voltages below 600 V because the on-resistance rDS is very high at higher breakdown voltages. For SiC n-channel power MOSFETs with ND NA, (18.117) where ND is in 1/cm3. The breakdown voltage VBD is inversely proportional to the doping density ND. The thickness of the drain region at ND = NDmin is (18.118) Silicon-carbide MOSFETs can operate up to 6–10 kV. The ratios are (18.119) and

(18.120) At the same doping concentration of the drift region ND, the avalanche breakdown voltage of the SiC MOSFET is 100 times higher than that of the Si MOSFET. At the same breakdown voltage VBD, the doping concentration of the drift region ND of the SiC MOSFET can be 100 times higher and the drift region thickness WD can be 11 times lower than those of the Si MOSFET. The avalanche breakdown voltage VDSS decreases as the junction temperature TJ decreases. The minimum breakdown voltage VDSS(min) occurs at the lowest junction temperature TJmin. At lower temperatures, the average distance between collisions, called the mean free path of charge carriers, is longer because the amplitude of the atom oscillations is lower. Therefore, the impact ionization rate is higher, yielding a lower avalanche breakdown voltage VBD. The thermal coefficient of the breakdown voltage is (ΔVDSS/VDSS)/ΔT = 0.001/°C. The breakdown voltage VBD = VDSS is measured at VGS = 0 and ID = 0.25 mA. The breakdown voltage VDSS depends on the defects in the semiconductor structure, especially the defects on the surface and in the curved areas, where the electric field is the strongest. Since it is impossible to predict accurately the distribution of defects, the calculations of the breakdown voltage are uncertain. Data sheets of power MOSFETs usually give lower values of the breakdown voltage than the actual ones. The punch-through breakdown voltage is observed when the depletion region on the drift side of the body–diode junction reaches the epilayer–substrate interface before the avalanche breakdown takes place in the epitaxial layer. When the depletion region edge enters the high concentration substrate, a further increase in the drain-to-source voltage causes the electric field to quickly reach the critical value, starting the avalanche carrier multiplication process.

18.11 Gate Oxide Breakdown Voltage of Power MOSFETs The electric field in the oxide SiO2 increases with increasing gate-to-source voltage vGS. If the electric field in the oxide becomes large enough, breakdown will occur, which causes catastrophic failure of the MOSFET. An electric field causes small displacement of the bound charges in the dielectric material, resulting in polarization. If the electric field is very strong, it pulls electrons out of the molecules, causing permanent dislocations in the molecular structure. Free charges make the material conducting and a large current may flow. For silicon oxide SiO2, the dielectric strength is V/cm. The electric field in the oxide is Eox = vGS/tox. For example, if tox = 50 nm, V. However, a safety margin is necessary because defects in the oxide lower the breakdown electric field .

MOSFETs must be protected against electrostatic discharge (ESD). They have a very large dc input resistance Rin(dc) > 4 GΩ, and a small amount of static charge accumulated on the gate capacitance can cause the voltage breakdown of the oxide. ESD destruction of a MOSFET occurs when the gate-to-source voltage vGS is high enough to puncture the gate dielectric. The arc burns a microscopic hole in the gate silicon dioxide SiO2, resulting in a gate-to-source short circuit or a high leakage current path. The high leakage current path eventually breaks down into a full short circuit. The rated maximum gate-to-source voltage VGSmax is usually two to three times lower than the breakdown voltage of the oxide . MOSFETs should be stored in closed conductive containers. Tables and floors should have grounded staticdissipative covering. Grounded soldering irons should be used to install MOSFETs. Conductive plastic bags are manufactured from carbon or metal-impregnated base.

18.12 Specific On-Resistance Neglecting the edge effects with or without terminations, the resistance of a planar drift region is given by [14] (18.121) where vDR is the voltage drop across the drift region, iD is the drain current, A is the crosssectional area of the drift region, μn is the bulk electron mobility, and Vbi is the built-in potential. The built-in potential Vbi ranges from 0.55 to 0.9 V for silicon junction diodes. For silicon, the low-field electron mobility is μn = 1360 cm2/V s at ND < 1015 cm− 3 and at room temperature T = 300 K, whereas the low-field hole mobility is μp = 480 cm2/Vs at NA < 1015 cm− 3 at room temperature T = 300 K. The electron mobility μn decreases when ND, T, and E increase. For example, μn = 576 cm2/V.s at VBD = 600 V and T = 150°C. In general, the specific on-resistance describing power switching devices is defined as the onresistance-area product (18.122) where A is the active device area. The specific resistance of the drift region with the doping concentration and thickness required to support the desired breakdown voltage is given by (18.123) where J = iD/A is the drain current density. The specific drift on-resistance is inversely proportional to the cube of the breakdown electric field strength EBD and can be reduced if the semiconductor has a higher breakdown electric field strength, such as silicon carbide. For

silicon devices, the specific resistance of the drift region is (18.124) Figure 18.31 shows ARDR as a function of VBD.

Figure 18.31 Specific drift resistance ARDR as a function of breakdown voltage VBD for silicon and silicon carbide. The MOSFET specific resistance of the drift region increases with increasing temperature T. (18.125)

For silicon,

(18.126)

As the temperature T is increased by 100°C, from 27°C to 127°C, the specific drain resistance S increases by a factor of 2 (18.127) Example 18.1 The breakdown voltage VBD of a Si power MOSFET is 500 V and RDR = 0.6 Ω. Calculate ND, WD, S, and A. Solution: The maximum donor density in the drift region is (18.128) The minimum thickness of the drift region is (18.129) The specific drift resistance is (18.130) Hence, the cross-sectional area of the drift region of the power MOSFET is (18.131) Silicon carbide (SiC) has the following properties: εr(SiC) = 9.7, EBD = 2.2 × 106 V/cm, the band gap energy EG = 2.26 eV, μn(300) = 900 cm2/V.s at VBD = 100 V and T = 27°C, μn = 430 cm2/V.s at VBD = 600 V and T = 150°C. For SiC MOSFETs, the specific resistance of the drift region is given by (18.132)

At VBD = 600 V and T = 150°C, μn(Si) = 576 cm2/V.s and μn(SiC) = 148 cm2/Vs. The ratio of specific resistance of silicon to the specific resistance of silicon carbide is given by

(18.133)

The thermal conductivity of silicon is Gth(Si) = 1.5 W/cmK and the thermal conductivity of silicon carbide is Gth(SiC) = 4.56 W/cmK. Thus, the thermal conductivity of silicon carbide is about three times higher than that of silicon. The thermal junction-to-case resistance of silicon devices is typically θJC(Si) = 1.5°C/W and that of silicon-carbide devices is θJC(SiC) = 0.02°C/W. Most of the resistance that controls the drain current flow during the conduction arises in the same portion of the power MOSFET that supports the high voltage during the blocking state. A high breakdown voltage requires a low doping concentration of the drift region, whereas a low resistance of the drift region requires a high doping concentration. Most power MOSFETs are n-channel devices because the mobility of electrons is higher than that of holes by a factor of μn/μp = 1360/480 = 2.833 for silicon. Example 18.2 The breakdown voltage VBD of a SiC power MOSFET is 500 V and A = 0.1479 cm2 at T = 300 K. Calculate ND, WD, S, and RDR. Solution: The required donor density in the drift region is (18.134) The required thickness of the drift region is (18.135) Assuming μn = 900 cm2/V • s. the specific drift resistance is (18.136) Hence, the expected resistance of the drift region of the SiC power MOSFET is (18.137)

18.13 Figures-of-Merit of Semiconductors Parameters of semiconductor materials have a significant impact on the parameters of semiconductor devices. Silicon power semiconductor devices are rapidly approaching their theoretical limits of performance. Johnson’s figure-of-merit of a semiconductor material is given by [4]

(18.138) For silicon, (18.139) For silicon carbide, (18.140) The ratio is (18.141) Baliga’s figure-of-merit of semiconductor materials is given by [5] (18.142) It can be used to compare the performance of various semiconductor materials used for power device fabrication. For silicon at room temperature T = 27°C = 300 K and low field for VBD = 50 V, μn0(Si) = 1360 cm2/V • s. Hence, (18.143) For silicon carbide at T = 27°C = 300 K and VBD = 50 V, μn0(SiC) = 900 cm2/V • s. Thus, (18.144) The ratio of these two factors is (18.145) For silicon at T = 150°C = 423 K and VBD = 600 V, μnSi(BD) = 40 cm2/V • s. Hence, (18.146) For silicon carbide at T = 423 K and VBD = 600 V, μn = 430 cm2/V • s. Hence,

(18.147) The ratio of these two factors is (18.148) Another figure-of-merit of semiconductor materials is given by (18.149) For silicon, FM(Si) = 83 kW/cm2, and for silicon carbide, FM(SiC) = 338.37 MW/cm2. The figure-of-merit of power MOSFETs is defined here as (18.150) where IDMAX is the maximum drain current. For example, IRF540 has VDSS = 100 V, IDMAX = 28 A, and rDS = 0.077 Ω. Hence, (18.151) The figure of merit of power MOSFETs that takes into account the capacitance Cgs is given by (18.152) For example, IRF540 has Cgs = 1620 pF, which gives (18.153)

18.14 On-Resistance of Power MOSFETs The overall MOSFET on-resistance rDS consists of the channel resistance Rch, the accumulation region resistance Ra, the neck resistance Rn, and the drift resistance RDR (18.154) as shown in Figure 18.32. Additional resistances include n+ substrate resistance, n+ source diffusion region resistance, die metallization resistances between the source and silicon and

the drain and silicon, bond wire resistances, and external lead resistances.

Figure 18.32 Components of on-resistance rDS for power MOSFETs.

18.14.1 Channel Resistance The large-signal long-channel resistance can be obtained from the MOSFET characteristics for the linear region (18.155) where vDS 2( vGS − Vt). The channel resistance RCh decreases as the channel length L decreases, the channel width W increases, and the gate-to-source voltage vGS increases. Taking the “short-channel effect” into account, the channel resistance is given by (18.156)

Figure 18.33 shows the long-channel resistance RCh and the short-channel resistance RCh(sc) as a function of voltage vGS − Vt. The short-channel resistance is higher than the long-channel

resistance.

Figure 18.33 Long-channel resistance RCh and short-channel resistance RCh(sc) as functions of voltage vGS − Vt at μn = 600 cm2/V • s, Cox = 34.5 nF/cm2, W/L = 1.4 × 106, Vt = 3.5 V, θ = 0.2 V− 1 for power MOSFET.

18.14.2 Accumulation Region Resistance The resistance of the accumulation region can be determined using the equation for channel resistance. The longest path for the drain current in the accumulation region is equal to dpp/2 and the shortest path is zero, where dpp is the distance between the p-wells. Therefore, the average length of the path for the drain current in the accumulation region is La(av) = dpp/4. Hence, the resistance of the accumulation region is expressed by (18.157)

18.14.3 Neck Region Resistance A top view of the accumulation region is shown in Figure 18.34. The resistance of the accumulation region can be determined using the neck area of a single square cell given by (18.158) resulting in the neck area for n cells (18.159) The resistivity of the neck and drift regions is (18.160) The neck region resistance is (18.161) where hp is the height of the p-well, dpp is the distance between the p-wells, W1 is the channel width of a single cell, and n is the number of cells. The drift region resistivity can be controlled by the addition of dopants into the silicon lattice that contribute either electrons or holes to the conduction process when ionized.

Figure 18.34 Top view of accumulation region.

18.14.4 Drift Region Resistance Assuming that the current through the drift region is uniformly distributed, the drift region resistance is described by (18.162) where WD is the drift region thickness and AD is the drain area. In reality, the current density is higher between the p-wells and lower underneath the p-wells due to the current-spreading effect. Therefore, the effective cross-sectional area of the drift region A is smaller than the die area Ad, and the drift region resistance is higher than that given by (18.169). For example, for the MOSFETs with VBD = 200 V, the actual drift resistance RDR is increased by about 70%. In high-voltage power MOSFETs with VDSS ≥ 400 V, the drift region is lightly doped and thick,

and therefore its resistance RDR dominates the overall resistance rDS in silicon MOSFETs. The drift resistance is independent of the gate-to-source voltage. For example, an IRFPG50 power MOSFET has VDSS = 1000 V, ISMmax = 6.1 A, and rDS = 2 Ω. In low-voltage MOSFETs with VDSS ≤ 100 V, the channel resistance RCh is from 0.3rDS to 0.5rDS. The channel resistance depends on the gate-to-source voltage and a stronger gate drive reduces RCh, reducing rDS. Typically, the silicon MOSFET on-resistance rDS doubles as the temperature rises by 100°C because the electron mobility decreases with increasing temperature. As the temperature increases from T1 to T2, the increase in the silicon MOSFET on-resistance can be approximated by (18.163) Figure 18.35 shows a piecewise-linear model of the MOSFET for the ohmic region, where it is operated as a switch with on-resistance rDS. The MOSFET in the ohmic region behaves like a gate-controlled resistor.

Figure 18.35 Piecewise-linear model of the MOSFET operated as a switch in the linear and cutoff regions with the voltage-controlled on-resistance rDS. GaN power MOSFETs with a voltage rating of VBD = 30 V have the typical on-resistance rDS = 1.5 mΩ. Cree SiC MOSTETs CAS300M12BM2 have VDSmax = 1.2 kV, IDmax = 404 A, pulse current of 1500 A, and rDS = 5 mΩ. They allow us to build power modules with output power levels from 0.1 to 1 MW and 99% efficiency. Example 18.3 Design a silicon power MOSFET with square cells to meet the following specifications: VDSS = 100 V, ISMmax = 28 A, rDS ≤ 0.14 Ω, and kp = μnCox = 20.7 μA/V2. Solution. Assume a = ISMmax/IDsat = 0.05, Vt = 3.5 V, and VGSmax = 10 V. Hence, we obtain the saturation current

(18.164) and the minimum aspect ratio (18.165) Let (W/L) = 1.4 × 106. Assume the channel length L = 0.7 μm, the width of the p-well is Wp = 20 μm, and the distance between the p-wells is dpp = 10 μm. Hence, the channel width is (18.166) The channel width of a single cell is (18.167) The number of cells is (18.168) The area of all n cells is (18.169) Assuming that the source and gate pads and the field guard rings will occupy 25% of the chip, the die area is (18.170) Since the surface electron mobility in the channel is μn = 600 cm2/V • s = 0.06 m2/V • s, the oxide capacitance per unit area is (18.171) Thus, the oxide thickness is (18.172) The maximum doping concentration of the drift region is given by (18.173)

Pick ND = 1015 cm− 3 = 1021 m− 3 and the doping concentration of the p-wells NA = 1016 cm− 3 = 1022 m− 3. The minimum thickness of the drift region is (18.174) Pick WD = 12 μm. The long-channel resistance at VGS = 10 V is (18.175) The resistance of the accumulation region is given by (18.176) Assuming that the thickness of the p-wells is hp = 3 μm, and using the bulk mobility μn = 1360 cm2/V • s, we can calculate the neck region resistance as (18.177)

Assuming that AD = Ac, the drift region resistance is given by (18.178) The current density in the drift region is not uniform due to current-spreading effect. Assuming the current-spreading coefficient Fcs = 1.8, the drift resistance is (18.179) The MOSFET on-resistance is (18.180)

18.15 Capacitances of Power MOSFETs Figure 18.36 shows capacitances of the power MOSFET. Conducting surfaces separated by a

dielectric SiO2 form a capacitance. The body diode depletion layer also represents a junction capacitance. These capacitances govern the MOSFET transient performance because they are charged and discharged during turn-on and turn-off transitions. The rate of charging and discharging depends on the capacitance values and the impedances in the charging and discharging paths. MOSFETs exhibit no minority-carrier storage time.

Figure 18.36 Capacitances of power MOSFET.

18.15.1 Gate-to-Source Capacitance The gate-to-source capacitance Cgs consists of (1) the gate-to-source metal capacitance Cgm, (2) the gate-to-p-well capacitance Cgp, and (3) the gate-to-n+ source diffusion overlap capacitance Cgn. A top view of the MOSFET gate is shown in Figure 18.37. The gate area of a single square cell (18.181) and the gate area of all cells

(18.182) where dpp is the distance between the p-wells, L is the channel length, Ln is the gate-source overlap length, and n is the total number of cells. The gate polysilicon-to-metal capacitance is given by (18.183)

where εox = εr(ox)ε0 and tm is the distance between the gate and the upper source metallization. The capacitance Cgm is linear because it is not a function of voltage. To reduce this capacitance, the thickness of the insulating layer tm should be large.

Figure 18.37 Top view of the MOSFET gate used to determine capacitance Cgm.

The gate-to-p-well capacitance is (18.184) where Ap = LW is the channel area of all the cells regardless of the cell shape. When vDS increases at vGS < Vt, the depletion region in the p-type body diffusion widens. The further the depletion region moves toward the n+ source diffusion, the lower the capacitance Cgp becomes. Only the undepleted region of mobile charge at the surface of body diffusion below the polysilicon gate can form the lower plate of Cgp. Since the depletion region spreads less than 10% across the width of the heavily doped p-type body region as vDS is varied from zero to the rated breakdown value, the change in Cgp is small. For vGS < Vt, the p-well and the n+ source form a reverse-biased pn+ junction diode. The junction capacitance of this diode decreases as the voltage vGS becomes more negative. The junction capacitance and the capacitance Cgp are connected in series. This capacitance is nonlinear; it decreases as vGS decreases and is below Vt. For vGS > Vt, the n-channel is formed, and Cgp is connected directly to the source. The capacitance Cgp is slightly nonlinear. The gate-to-n+ source diffusion overlap capacitance is (18.185) where AS = WLn is the overlapping area of the gate electrode over the n+ source. The gate-to-source capacitance is the parallel combination of the three capacitances (18.186)

This capacitance is approximately linear.

18.15.2 Drain-to-Source Capacitance The drain-to-source capacitance Cds is the body-to-drain capacitance, which is the body diode junction and diffusion capacitance. For the drain voltage vDS ≥ 0, the diode is reverse-biased and the diode capacitance is dominated by the small-signal junction capacitance. The body diode junction area is equal to the area of all p-wells (18.187) where Wp is the width of the p-well and hp is the thickness of the p-well. The zero-bias body diode junction capacitance is

(18.188) Since vD = −vDS, the body diode junction capacitance is given by (18.189)

where

for linearly graded junctions and

for step junctions. The minimum junction

capacitance Cdsmin occurs at the maximum drain-to-source voltage vDSmax. For drain-to-source capacitance Cds(vDS) at the drain-to-source voltage is given by

, the

(18.190) For the drain voltage vDS < 0, the diode is forward-biased and the diode capacitance is dominated by the small-signal diffusion capacitance (18.191) The body diode exhibits reverse recovery during the turn-off transition of transistor negative current due to the excess charge stored in the diffusion capacitance CD. The capacitance Cds is highly nonlinear.

18.15.3 Gate-to-Drain Capacitance The gate-to-drain capacitance Cgd varies with the drain-to-gate voltage vDG. Three regions of the voltage vDG should be considered for capacitance Cgd. (1) For the first region, the voltage range is − vGS ≤ vDG ≤ 0. In this region, the MOSFET is ON, vGS ≈ 5–10 V, vDG = vDS(ON) − vGS ≈ −vGS < 0, the depletion region of the body diode is very narrow, 2xn d − pp, and the width of the neck region is nearly dpp. Hence, the area of the neck region An is large, resulting in a large gate polysilicon-oxide-neck semiconductor capacitance Cga = Cgd. A top view of the neck region is depicted in Figure 18.34. The area of the neck for the single square cell is (18.192) The area of the neck region for n square cells is

(18.193) where W = nW1. The gate-oxide-accumulation region capacitance (or the gate-oxide-neck region capacitance) is given by (18.194)

where Cgdh denotes a high value of Cgd. (2) For the second region, the voltage range is 0 ≤ vDG ≤ vDS(cr). In this region, the MOSFET is in the cutoff region or in the pinch-off region, 2xn < dpp, vGS is at or near zero, and vDG = vDS − vGS ≈ vDS. As the voltage vDS > 0 increases, the voltage vDG also increases. Figure 18.38 shows the components of the gate-to-drain capacitance Cgd, namely Cga1, Cga2, and CDn. The depletion region of the reverse-biased body diode extends into the neck region, and the effective width of the neck region is reduced to dpp − 2xn. Therefore, the area of the neck region that is not occupied by the depletion region of the body diode is reduced, reducing the capacitance Cga1. A top view of the neck region is shown in Figure 18.39. The area of the neck region for the square cells is (18.195)

At the critical value of the drain-to-source voltage vDS(cr), the effective neck area An is reduced to zero. As the voltage vDS increases from zero to vDS(cr), An decreases from its maximum value to zero. The voltage vDS modulates the effective area of the lower plate of the capacitor. The gate-oxide-accumulation region capacitance is given by (18.196)

As the voltage vDS increases from zero to vDS(cr), the capacitance Cga1 decreases from its maximum value to zero.

Figure 18.38 Components of gate-to-drain capacitance Cgd of power MOSFET for 2xn < dpp, when vDS is moderate.

Figure 18.39 Top view of the gate-oxide-accumulation region capacitance Cga of power MOSFET for vDS(ON) < vDS < vDS(cr) and xn > 0. The second component of capacitance Cgd for 0 ≤ vDS ≤ vDS(cr) is formed by the gate polysilicon and the drain semiconductor separated by the silicon dioxide SiO2 and depletion region. It is the capacitance with two dielectric layers: the silicon dioxide SiO2 and the depletion region. This capacitance is equivalent to two capacitances Cga2 and CDn connected in series. The area of the silicon dioxide–depletion layer interface for a single square cell is (18.197) Hence, the area of the silicon dioxide–depletion layer interface for all cells is (18.198) The gate-oxide-depletion region capacitance is

(18.199)

The capacitance formed by the silicon dioxide, depletion layer, and the drain in the neck region is (18.200)

The gate-to-drain capacitance for intermediate voltages vDS is (18.201) (3) In the third region, the voltage range is vDS(cr) ≤ vDG ≤ VDSS and the MOSFET is OFF or in the saturation region. When 2xn ≥ dpp, the entire neck area is occupied by the depletion region of the body diode. Figure 18.40 shows the components of the gate-to-drain capacitance Cgd for high voltages vDS. The gate-to-drain capacitance Cgd is formed by the gate polysilicon, the drain metal, and the two-layer dielectric that consists of the silicon dioxide SiO2 and the depletion region below the dioxide-neck interface. The capacitor that contains a two-layer dielectric can be treated as a series combination of two capacitors: Cgd and CJn. The capacitance formed by the depletion region of the body diode is (18.202)

Using (18.194), one obtains the gate-to-drain capacitance at high voltages vDS (18.203) where Cgdl denotes a low value of capacitance Cgd. The capacitance Cgd is highly nonlinear. The capacitance CJn is a dominant component of Cgd. It can be approximated by Cgd ≈ CJn. The ratio Cgdh/Cgdl ranges from 10 to 100. The gate-to-drain capacitance Cgd significantly increases the transistor input capacitance during off-to-on and on-to-off transitions due to Miller’s effect. Figure 18.41 shows the power MOSFET capacitances as functions of the transistor voltages.

Figure 18.40 Components of gate-to-drain capacitance Cgd of power MOSFET for 2xn = dpp, when vDS is high.

Figure 18.41 Power MOSFET capacitances as functions of transistor voltages. Manufacturers of power MOSFETs usually specify the capacitances Crss = Cgd, Ciss = Cgs + Cgd and Coss = Cgd + Cds measured at VDS = 25 V, VGS = 0, and f = 1 MHz. Hence, (18.204) (18.205) and (18.206) Using the drain-to-source capacitance Cds(25) at VDS = 25 V given in data sheets, we can calculate

(18.207) and (18.208) Manufacturers of power MOSFETs also give plots of capacitances Crss, Ciss, and Coss as functions of voltages. Example 18.4 Calculate the capacitances for the power MOSFET designed in Example 18.3. Gate-to-source capacitance Cgs. Assuming that the gate-to-source overlap length is Ln = 0.2 μm, and the distance between the gate and the metal is tm = 0.8 μm, the gate polysilicon-tometal capacitance is given by (18.209)

The gate-to-p-well capacitance is (18.210) The gate-to-n+ source diffusion overlap capacitance is (18.211) The gate-to-source capacitance is (18.212) Drain-to-source capacitance Cds. The built-in-potential of the body diode is given by (18.213) The area of all p-wells is given by (18.214)

The zero-bias drain-to-source capacitance is (18.215)

Assuming the step junction of the body diode, we obtain the drain-to-source capacitance at VDS = 1 V when the MOSFET is ON (18.216)

and at VDS = 80 V when the MOSFET is OFF (18.217)

Thus, Cds(1)/Cds(80) = 601.49/85.71 = 7.018. Figure 18.42 shows the plot of the drain-to-source capacitance Cds as a function of the drain-to-source voltage vDS. Gate-to-drain capacitance Cgd. When the MOSFET is ON and the drain-to-source voltage vDS is low, the depletion region of the body diode that extends into the neck region can be neglected. The area of the neck region for n square cells is given by (18.218) The gate-to-accumulation region capacitance (or the gate-to-neck region capacitance) at vDS = 0 is given by (18.219) At vDS(cr) = 18.76 V, (18.220)

Figure 18.43 depicts a plot of capacitance CDn as a function of voltage vDS. The neck area is given by

(18.221)

Figure 18.44 shows a plot of An as a function of vDS. The gate-to-accumulation region capacitance is (18.222)

Figure 18.45 shows a plot of Cga1 as a function of vDS. As the voltage vDS increases, the area of the lower capacitor plate An decreases from the entire neck area to zero, reducing the capacitance Cga1. At the critical voltage vDS(cr) = 18.76 V, 2xn = dpp, and the entire neck area is occupied by the depletion region. The capacitance Cga2 increases with increasing voltage vDS because the area of the lower capacitor plate increases with vDS. At vDS(cr) = 18.76 V, the gate-oxide-depletion region capacitance is given by (18.223)

Figure 18.45 shows a plot of Cga2 as a function of vDS for low values of vDS. The gate-to-drain capacitance Cgd at low values of voltage vDS is given by (18.224) At vDS(cr) = 18.76 V, Cga1 = 0 and (18.225) Figure 18.46 shows a plot of Cgd as a function of vDS for high values of vDS. The large capacitance Cgd at low values of voltage vDS dominates the MOSFET input capacitance during later stages of turn-on and the initial stages of turn-off.

For vDS = 80 V, 2xn > dpp. The capacitance formed by the depletion region is (18.226)

Figure 18.47 shows a plot of CJn as a function of vDS. The gate-to-drain region capacitance at VDS = 80 V is (18.227) The ratio is Cgdh/Cgdl = 2158/47.91 = 45.04. Figure 18.48 shows a plot of Cgd as a function of vDS for high values of voltage vDS. The capacitance Cgd is dominated by the capacitance CJn. The gate-to-drain capacitance Cgd over a wide range of voltage vDS is shown in Figure 18.49. Figure 18.50 shows the MOSFET capacitances Ciss = Cgs + Cgd, Crss = Cgd, and Coss = Cds + Cgd as functions of vDS. The plots of Ciss, Cess, and Coss are similar to the corresponding plots given in manufacturer’s data sheets.

Figure 18.42 Drain-to-source capacitance Cds as a function of the drain-to-source voltage vDS.

Figure 18.43 Capacitance CDn as a function of the drain-to-source voltage vDS.

Figure 18.44 Neck area An as a function of the drain-to-source voltage vDS for 2xn < dpp, when vDS is moderate (0 ≤ vDS ≤ vDS(cr)).

Figure 18.45 Capacitances Cga1 and Cga2 as functions of the drain-to-source voltage vDS for 2xn < dpp, when vDS is moderate (0 ≤ vDS ≤ vDS(cr)).

Figure 18.46 Gate-to-drain capacitance Cgd as a function of the drain-to-source voltage vDS for 2xn < dpp, when vDS is moderate (0 ≤ vDS ≤ vDS(cr)).

Figure 18.47 Capacitance CJn as a function of the drain-to-source voltage vDS for 2xn = dpp, when vDS is high (vDS(cr) ≤ vDS ≤ VDSS).

Figure 18.48 Gate-to-drain capacitance Cgd as a function of the drain-to-source voltage vDS for 2xn = dpp, when vDS is high (vDS(cr) ≤ vDS ≤ VDSS).

Figure 18.49 Gate-to-drain capacitance Cgd as a function of the drain-to-source voltage vDS.

Figure 18.50 Capacitances Ciss, Crss, and Coss as functions of the drain-to-source voltage vDS.

Figure 18.51 Capacitances Ciss, Crss, and Coss as functions of the drain-to-source voltage vDS.

18.16 Switching Waveforms The waveforms during the turn-on and turn-off transitions for the power MOSFET are shown in Figure 18.52. Let us assume that the MOSFET is driven by a square-wave voltage source with its internal resistance. The load is the resistance RL. During the turn-on transition, the first time interval is the delay time td, during which the gate-to-source voltage vGS increases from zero or a negative value to the threshold voltage Vt, charging the capacitances Cgs and Cgd with the time constant τG = RG(Cgs + Cgd), where RG is the MOSFET gate resistance connected in series with the drive source resistance. During the delay time, the MOSFET is in the cutoff region, the drain current iD is zero, the drain-to-source voltage vDS is constant, the voltage gain is zero, and Miller’s effect does not exist.

Figure 18.52 MOSFET waveforms during the turn-on and turn-off transitions. The next time interval is the drain current rise time tri. When vGS exceeds the threshold voltage Vt, the transistor turns on and is in the saturation region, the drain current iD rises, the drain-to-source voltage decreases, the voltage gain Av = ΔvDS/ΔvGS is high, and the Miller’s effect is very strong. Therefore, Miller’s capacitance CM = (1 − Av)Cgd is reflected to the transistor input and is connected in parallel with capacitance Cgs. The total input capacitance Ci = Cgs + (1 − Av)Cgd is so large that the gate-to-source voltage vGS increases very slowly. The last time interval is the drain-to-source voltage fall time tvf = tvf1 + tvf2. During the fall time tvf1, the gate-to-drain capacitance is low, Cgd = Cgdl, and therefore the rate of change of vDS is high. During the fall time tvf2, the gate-to-drain capacitance is high, Cgd = Cgdh, and therefore the rate of change of vDS is low. After the turn-on transition is completed, the MOSFET remains in the linear region. The turnoff transition consists of the drain-to-source voltage rise time tvr, the drain current fall time tfi,

and the delay time td. The typical switching times of MOSFETs are in the range 10–200 ns. They depend on the rate at which the transistor input capacitance Ciss can be charged and discharged.

18.17 SPICE Model of Power MOSFETs Figure 18.53 shows a SPICE large-signal model for n-channel enhancement MOSFETs. It is a model for integrated MOSFETs, which can be adopted to power MOSFETs. SPICE parameters for the level 1 MOSFET large-signal model are given in Table 18.1. The diode currents are (18.228) and (18.229)

Figure 18.53 SPICE large-signal model for n-channel MOSFET (NMOS). The body B is short-circuited to the source S for power MOSFETs. The junction capacitances in the voltage range close to zero are (18.230)

and (18.231)

where CJ is the zero-bias junction capacitance per unit area, AD is the drain area, AS is the source area, PB is the built-in potential, and MJ is the grading coefficient. The junction capacitances in the voltage range being far from zero are

(18.232) and (18.233)

Table 18.1 Selected SPICE level 1 NMOS large-signal model parameters Sym. SPICE S. Model parameter Vto VTO Zero-bias threshold voltage

Default value Typical value 0 V 0.3–3 V

μCox KP

Process constant

2 × 10− 5 A/V2 20–346 μA/V2

λ

Lambda

Channel-length modulation

γ

Gamma

Body-effect Vt parameter

0 V

2ϕF

PHI

Surface potential

0.6 V

0.7 V

RD

RD

Drain series resistance

0 Ω

0.2 Ω

RS

RS

Source series resistance

0 Ω

0.1 Ω

RG

RG

Gate series resistance

0 Ω

1 Ω

RB

RB

Body series resistance

0 Ω

1 Ω

RDS

RDS

Drain–source shunt R

∞

1 MΩ

RSH

RSH

Drain–source diffusion sheet R

0

20 Ω/Sq.

IS

IS

Saturation current

10− 14 A

10− 9 A

Mj

MJ

Grading coefficient

0.5

0.36

Cj0

CJ

Zero-bias bulk junction C/m2

0 F/m2

1 nF/m2

Vbi

PB

Junction potential

1 V

0.72 V

0 V− 1

0.5–10− 5 V− 1

Mjsw MJSW

Grading coefficient

0.333

0.12

Cj0sw CJSW

Zero-bias junc. parameter C/m

0 F/m

380 pF/m

VBSW PBSW

Junction sidewell potential

1 V

0.42 V

CGDO CGDO

Gate–drain overlap C/m

0 F/m

220 pF/m

CGSO CGSO

Gate–source overlap C/m

0 F/m

220 pF/m

CGBO CGBO

Gate-bulk overlap C/m

0 F/m

700 pF/m

FC

FC

Forward-biased CJ coefficient

0.5

0.5

tox

TOX

Oxide thickness

∞

4.1–100 nm

μns

UO

Surface mobility

600 cm2/Vs

600 cm2/V • s

nsub

NSUB

Substrate doping

0 cm− 3/Vs

0 cm− 3/V • s

The typical values: Cox = 3.45 × 10− 5 pF/μm

tox = 4.1 × 10− 3μm Cj0 = 2 × 10− 4 F/m2 Cjsw = 10− 9 F/m CGBO = 2 × 10− 10 F/m CGDO = CGSO = 4 × 10− 11 F/m SPICE NMOS Syntax: Mxxxx D G S B MOS-model-name L = xxx W = yyy Example: M1 2 1 0 0 M1-FET L = 0.18 um W = 1800 um SPICE NMOS Model Syntax: .model model-name NMOS (parameter=value ...) Example: .model M1-FET NMOS (Vto = 1V Kp = E-4) SPICE PMOS Model Syntax: .model model-name PMOS (parameter=value ...) SPICE Subcircuit Model Syntax: xname N1 N2 N3 model-name Example: x1 2 1 0 IRF840 Copy and paste the obtained device model. .SUBCKT IRF840 1 2 3 and the content of the model.

18.18 IGBTs A cross section of the n-channel insulated gate bipolar transistor (IGBT) is shown in Figure 18.54. This device is obtained by replacing the n+-substrate in the vertical double-diffusion power MOSFET by a p+ substrate. The p+ substrate, the n−-drift region, and the p-well form a pnp bipolar junction transistor (BJT). Figure 18.55 shows an equivalent circuit of the nchannel IGBT and its circuit symbols. It is a monolithically integrated connection of an nchannel MOSFET and a pnp BJT. The drain of the MOSFET is connected to the base of the

BJT, and the source of the MOSFET is connected to the collector of the BJT. This topology is similar to the Darlington connection. The BJT is driven between the base and the collector, like in the common-collector (CC) configuration. When the MOSFET is ON, the BJT is ON, and therefore the entire IGBT is ON. When the IGBT is ON, the BJT pn− emitter junction is forward biased and injects hole minority carriers into the n− drift region, causing conductivity modulation of the drift region. Therefore, the drift region resistance and the on-voltage drop are greatly reduced, lowering the conduction power loss. The injected holes move across the n − drift region by diffusion and drift. The n− drift region and the p-well form a collector junction of the BJT, which collects the holes. The on-voltage drop is usually 2–3 V. The breakdown voltage is up to 3.5 kV.

Figure 18.54 Cross section of the n-channel IGBT.

Figure 18.55 IGBT. (a) Equivalent circuit of n-channel IGBT, a composite device that consists of an n-channel MOSFET and a pnp BJT. (b) Symbols. The advantages of IGBTs are simplicity of driving a MOSFET and a low on-state voltage drop of a BJT due to conductivity modulation of the drift region, yielding a significant reduction in the drift region resistance of the MOSFET and the conduction power loss. Reversal of the doping types results in a p-channel MOSFET and an npn BJT. However, the p-channel MOSFET exhibits a higher on-resistance than the n-channel MOSFET. IGBTs combine a high speed and a high input impedance of a MOSFET with a high current density and a low conduction loss of a BJT. The BJT suffers from the storage time in the base during the turn-off transition. When the MOSFET is turned off, the negative base current cannot be used to remove the excess charge from the base of the BJT. Therefore, the IGBT output current slowly reduces to zero at turn-off as the excess minority carrier charge stored in the base gradually decreases by recombination, causing considerable turn-off switching loss. This effect is called current tailing. The switching times are typically 1–4 μs. IGBTs are good devices for low-frequency, high-voltage, high-power applications, such as electric motor drives and AC arc welding machines. The maximum operating frequency is usually 50 kHz. Electric motors for electric and hybrid cars are examples of applications of IGBTs. Example specifications for dc–ac three-phase inverters with IGBTs for hybrid cars are: output power PO = 30 kW, VDC = 400 V, and RPM = 3000.

18.19 Heat Sinks Thermal management is an important aspect of semiconductor devices. Power devices dissipate large amounts of power. Therefore, thermal characteristics of the semiconductor material and cooling systems have a significant impact on the converter size. Power losses in power circuit are converted into heat, which increases the device junction temperature TJ. The junction temperature should not exceed the maximum junction temperature TJmax

(18.234) because the device may suffer permanent damage. For silicon devices, the maximum operating junction temperature TJmax is usually 150°C–200°C. For silicon-carbide devices, the maximum operating junction temperature TJmax is usually 250°C–600°C. Heat transfer is thermal energy in transit due to a temperature difference. Heat transfer takes place by three mechanisms: conduction, convection, and radiation. Conduction. Figure 18.56 illustrates heat transfer by conduction. In a solid, conduction may be attributed to atomic and molecular activity in the form of lattice vibrations. Conduction allows for transferring heat from the inside of a device (like the junction) to the surface of the device package, heat sink, or chassis. The rate of heat flux flow by conduction is determined by the temperature gradient (or temperature difference), the thermal conductivity of various layers of material, and the external surface area. Fourier’s law describes the rate of change of heat (18.235) where kth is the thermal conductivity expressed in (W/m • K), ρth = 1/kth is the thermal resistivity, A is the cross-sectional area perpendicular to the power flow through which heat is being conducted, l is the thickness of the layer that conducts heat, w is the width of the layer, ΔT = T1 − T2 is the temperature difference between the temperatures on both sides of a layer, and the derivative dT/dx is the temperature gradient normal to the cross-sectional area A. The thermal resistance of a material layer is (18.236) The relationship (18.243) is similar to Ohm’s law. The temperature T corresponds to voltage, power PD flow to current I flow, and thermal resistivity ρth to electrical resistivity ρ. The thermal resistance has a unit of degree centigrade per watt. For 90% pure aluminum, kth = 220 W/(m • K) and ρth = 4.545 m°C/W. The lengths of all heat flow paths should be as short as possible and the outer areas of the heat sink should be as large as possible for good heat transfer. The drain of the discrete MOSFET is connected to the metal case and must be insulated from the heat sink. The junction-to-ambient thermal resistance of the transistor without a heat sink (having a case only) is large, for example, θJA = 62.5°C/W. The junctionto-case thermal resistance is much lower, for example, θJC = 4.167°C/W. The junction-toambient thermal resistance with a heat sink may be made low, for example, θJA = 12.2°C/W.

Figure 18.56 Heat transfer by conduction. (a) Layer conducting heat. (b) Temperature distribution in a layer of heat conductor. Convection. Convection occurs by the natural or forced movement of matter with different temperatures. The convection is also used to transfer heat. Warm air expands and rises, resulting in natural air circulation. The moving hot air is replaced by cold air. The air movement can be natural or forced. The heat transfer by convection occurs when the device surface is hotter than the surrounding medium, like air or water. Convection permits removal of heat by moving air. It is a complex process that involves conduction of the convecting fluid, changes in the density of the fluid with temperature, the viscosity of the fluid, and the motion of the fluid. Figure 18.57 illustrates heat transfer by convection. Heat can be transferred by natural convection or forced convection. The layer of air in contact with a hot surface expands, becomes lighter, and rises, taking the heat with it. Convection is also used in forced-air cooling with a fan, where heat is carried away from a semiconductor device by the motion of the air. Warmer air will rise up and will be replaced by colder air. The rate of heat removal by convection is proportional to the temperature difference

(18.237) where the thermal resistance is (18.238) hc is the convection heat transfer coefficient, A is the area of the surface form which heat is being convected, TS is the surface temperature of body form which heat is being convected, and TA is the ambient temperature. The heat transfer by convection is described by Newton’s law of cooling (18.239) where a = 1–1.25, A is the area of the surface in m2, F is the air friction factor (it is equal to 1 for vertical surface), and P is the relative barometric pressure. The heat cannot be transferred by convection due to circulating air for equipment operated in vacuum. Convection cannot be used in space to cool electronic circuits in satellites. Wide traces on printed boards should be used to transfer heat by conduction.

Figure 18.57 Heat transfer by convection. (a) Air flow along a hot surface. (b) Temperature distribution. (c) Air velocity distribution. Radiation. All bodies at temperatures above absolute zero radiate electromagnetic energy. The transfer of heat by thermal radiation occurs when the temperature of a body surface is raised above its surroundings and the surface emits radiant energy in the form of electromagnetic waves. Objects radiate energy in the infrared range. The heat transfer by radiation is described by the Stefan–Boltzmann law (18.240) where A is the outer surface area of the heat sink in m2, E is the emissivity factor of the radiated surface A, TS is the body temperature in Kelvin, and TA is the ambient temperature in Kelvin. For an ideal black object, E = 1. For black oxidized aluminum, E = 0.9. For white or highly reflective objects, like polished and bright aluminum, E = 0.05. It is beneficial to use dark heat sinks to maximize the heat transfer by radiation. Therefore, semiconductor device packages and heat sinks are usually black. For black oxidized aluminum,

(18.241) The heat generated in a semiconductor device is conducted to the surface, transferred to the air, and then removed by convection. The cooler air absorbs the heat and rises due to air circulation in the vertical direction. The metal conducts heat, thereby lowering the junction-toambient thermal resistance. Heat sinks have fins to assist cooling by convection. Figure 18.58(a) shows a lumped electrical equivalent circuit for the thermal conduction process in semiconductor devices for steady-state operation. The heat dissipated in a semiconductor device is conducted away from the junction to the case, from the case to the heat sink, and from the heat sink to the surrounding ambience. The junction temperature rise for a transistor with heat sink is given by (18.242) where PD is the power dissipation, θJA is the junction-to-ambient thermal resistance, θJC is the junction-to-case thermal resistance, θCS is the case-to-sink thermal resistance, and θSA is the sink-to-ambient thermal resistance. The maximum junction temperature is (18.243) The typical junction-to-case thermal resistance is θJC = 1°C/W and the typical case-to-sink thermal resistance is θCS = 0.1°C/W. Heat transport is a slow process. The temperature change of a semiconductor device requires a lot of time. Typical time constants are measured in seconds. Therefore, the time-average power dissipation determines the device temperature. Thermal capacitances are used to model the dynamic heat transfer, as shown in Figure 18.58(b). This model represents the thermal processes associated with start-up and pulsed operation, where power loss or temperature varies with time. The die time constant is τD = θJCCJC = 50–500 μs and the case time constant is τC = θJCCJC = 1–5 ms.

Figure 18.58 Electrical equivalent circuits for heat transfer in semiconductor devices. (a) Thermal model for steady-state operation. (b) Thermal model for transients. For steady-state operation, all the energy generated by heat sources inside the case of a semiconductor device is transferred through the outer surface At to the ambient (18.244) where hD is a constant. The temperature rise of semiconductor devices is nearly inversely proportional to the heat radiating surface area At. Assuming that 45% of heat is removed by convection and 55% is removed by radiation, the temperature rise in steady state is given by (18.245) where PD is in W and At is in cm2. Example 18.5 A power MOSFET has TJmax = 150°C and TA = 30°C. (a) Find the maximum power dissipation PDmax and the case temperature TC, when no heat sink is used for θJC = 1.5°C/W and θCA = 50°C/W. (b) Find the maximum power dissipation PDmax when a heat sink is mounted on the transistor at θJC = 1.5°C/W, θCS = 1°C/W, and θSA = 5°C/W.

Solution: (a) The maximum power dissipation is (18.246) (b) The maximum power dissipation is (18.247) When the heat sink is used, the maximum power dissipation increases by a factor of FHS = 16/2.33 = 6.87. The heat sink temperature is (18.248) The case temperature is (18.249) Manufacturer’s data sheets usually give the maximum junction temperature TJmax, the thermal resistance from the junction to the case θJC, and the maximum safe power dissipation PD0 = PD(rated) of semiconductor devices rated at the case temperature TC = TA0 = 25°C, that is, for an ideal cooling of the case with zero thermal resistance between the case and ambient. Under these conditions, the rated power is relatively high and is given by (18.250) In reality, the case temperature TC is higher than the ambient temperature TA and therefore the maximum power dissipation PD(max) is lower than the rated power PD0 and is given by (18.251) This equation describes the power derating curve, which is illustrated in Figure 18.59. The maximum power dissipation can also be expressed by (18.252) where the derating factor is DF = 1/θJC. Ambient temperatures across the glob range from − 50°C to 55°C. The humidity varies up to 100%. High-power semiconductor devices are mounted on finned base plates with fans that circulate ambient air through the fins. Liquid

cooling is also used in high-power devices. Example 18.6 A power MOSFET is rated to dissipate 30 W at TC = 25°C, and TJmax = 175°C. A heat sink is added with θCS = 1°C/W and θSA = 4°C/W. Find PDmax at TA = 25°C. Solution: The junction-to-case thermal resistance is (18.253) The maximum power dissipation is (18.254) Thus, the actual maximum safe power dissipation PDmax is much lower than the rated power PD0.

Figure 18.59 The maximum power dissipation PDmax as a function of the case temperature TC. Failures of many semiconductor devices are the result of overheating the semiconductor material. Failure can be due to excessive average overheating or localized overheating. Reliability can be improved by operating semiconductor devices below their maximum temperature rating. The trade-off is between the reliability and the size and cost of heat sink.

18.20 Summary There are two types of MOSFETs: n-channel and p-channel. MOSFETs are unipolar semiconductor devices because the current transport in the channel is due to only one type of carriers, for example, electrons in n-channel MOSFETs, which are majority charge carriers. Only a drift current flows through the device during the onstate conduction. The positive gate-to-source voltage vGS in an n-channel MOSFET repels the majority carrier holes and attracts the minority carrier electrons. For vGS > Vt, the p-type region is inverted into n-type region, forming an n-channel between the drain and the source. The conducting n-channel is formed in a MOSFET when vGS > Vt is applied and the electron density exceeds the hole density below the gate and the p-type semiconductor is inverted into the n-type inversion layer, connecting the drain to the source. The application of vGS above Vt causes a build-up of free electrons in the inversion layer in direct proportion to the excess of vGS above Vt. The enhancement-mode MOSFET is a normally-off device. The MOSFET threshold voltage Vt can be reduced by reducing the oxide thickness tox and the p-well doping concentration NA because Vt is proportional to tox and

.

The conductivity of the MOSFET channel is controlled by the gate-to-source voltage vGS applied across the metal–oxide–semiconductor (MOS) capacitor. When the drain-to-source voltage vDS increases at a fixed gate-to-source voltage vGS, the drain current iD initially increases, and then it saturates once the channel is pinched off near the drain end. The mobility of current carriers is the ratio of the average drift velocity to the applied electric field intensity, μn = E/vn. The silicon hole mobility is about one-third of the silicon electron mobility. The charge carrier mobility in the MOSFET channel is lower than that in the semiconductor bulk because of channel surface roughness scattering. A MOSFET channel should be wide and short to conduct large drain current. The mobility of electrons decreases as the doping concentration, temperature, and electric field increase. When the electric field E is increased, the scattering rate dramatically increases, and the average electron drift velocity saturates at high electric fields, which appears as a decrease in mobility.

The drain-to-source breakdown voltage BVDSS is the voltage at which the reverse-biased body diode breaks down to flow between the drain and the source by the avalanche multiplication of carrier at VGS = 0. This voltage is usually measured at the drain current ID = 0.25 mA. The punch-through breakdown occurs when the depletion region on the drift side of the body–diode junction reaches the epilayer–substrate interface at the drain-to-source voltage below the avalanche voltage breakdown VDS < BVDSS. High voltage MOSFETs have a high on-resistance rDS, resulting in a high conduction loss. There is a trade-off between the punch-through breakdown voltage that requires a longer channel and the on-resistance rDS that requires a shorter channel. The high breakdown electric field allows the SiC power devices to have thinner and more heavily doped voltage blocking layers, reducing the on-resistance. The heavily doped blocking layer with increased concentration provides 10 times lower resistance of SiC devices than that of Si devices. The 10 times thinner blocking layer of SiC devices reduces the specific on-resistance by a factor of 10. The combination of a tenth of the blocking layer thickness with the ten times higher doping concentration can yield SiC devices with the on-resistance 100 times lower than that of Si devices. The mobility of the charge carriers in the channel of a MOSFET is usually less than that found in the bulk of silicon because the charge carriers travel in a very thin layer just below the oxide, that is, the oxide–silicon interface. The charge carrier collisions with interface defects reduce the mobility. MOSFETs have three regions of operation: cutoff region (also called blocking region), linear region (also called ohmic region or triode region), and saturation region (also called pinch-off region). The carrier mobility in the channel decreases with increasing transverse electric field perpendicular to the gate oxide. For short channel lengths, the carriers travel at the saturation velocity vsat. The drain current iD is related to vGS by the square-law characteristic for low values of vGS. However, the iD–vGS characteristic becomes linear for higher values of vGS as a result of the high electric field along the channel, causing the drift carrier velocity to saturate. The MOSFET on-resistance increases as the breakdown voltage increases because the drift region thickness must be increased and the drift region doping concentration must be decreased. A power MOSFET at low drain currents exhibits a positive temperature coefficient, and therefore the transistor can suffer thermal runaway. The temperature coefficient at high currents is negative.

The gate-to-source capacitance Cgs is essentially linear. The gate-to-drain capacitance Cgd and the drain-to-source capacitance Cds are highly nonlinear. IGBTs are obtained by replacing the n+ substrate in the power MOSFET with the p+ substrate. IGBTs are easy to drive and have a large gate impedance, like MOSFETs. IGBTs have a low on-voltage drop due to conductivity modulation of the drift region, like BJTs. IGBTs exhibit a current tail at turn-off. The turn-off switching time of IGBTs is long because the excess minority carrier charge cannot be actively removed from the BJT base and it slowly decays to zero due to recombination. Finned heat sinks are used to reduce the temperature of semiconductor devices. The temperature rise of semiconductor devices is nearly inversely proportional to the heat radiating surface area. Heat transfer by conduction occurs in a stationary medium due to atomic vibrations and electron collisions when a temperature gradient exists. The energy transfer by conduction occurs in the direction of decreasing temperature. Heat transfer by natural or forced convection occurs through mass movement of air or liquid near the surface when they are at different temperatures. Heat transfer by radiation occurs due to emission of energy in the form of electromagnetic waves. Under steady-state conditions, all the energy generated inside a semiconductor device is transferred through the outer surface.

References 1. E. S. Oxner, Power MOSFETs and Their Applications. Englewood Cliffs, NJ: Prentice Hall, 1982. 2. D. A. Grant and J. Grower, Power MOSFETs, Theory and Applications. New York: John Wiley & Sons, 1989. 3. J. G. Kassakian, M. F. Schlecht, and G. C. Verghese, Principles of Power Electronics. Reading, MA: Addison-Wesley, 1991. 4. A. Johnson, “Physical limitations on frequency and power parameters of transistors,” RCA Review, vol. 26, pp. 163–177, 1963. 5. B. J. Baliga, “Semiconductors for high-voltage, vertical channel FRTs,” Journal of Applied Physics vol. 53, pp. 1759–1764, 1982.

6. J. Baliga, Modern Power Devices. New York: John Wiley & Sons, 1987. 7. B. J. Baliga, “Power semiconductor device of merit for high-frequency applications,” IEEE Electron Devices Letters, vol. 10, no. 10, pp. 435–437, October 1989. 8. B. J. Baliga, Power Semiconductor Devices. Boston, MA: PWS Publishing, 1995. 9. N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications and Design, 3rd Ed. New York: John Wiley & Sons, 2004. 10. R. F. Pierret, Semiconductor Device Fundamentals. Nick, MA: Addison-Wesley, 1996. 11. B. Streetman and S. Banerjee, Solid State Electronic Devices, 6th Ed. Upper Saddle River, NJ: Prentice Hall, 2006. 12. D. M. Caughey and R. E. Thomas, “Carrier mobilities in silicon empirically related to doping and field,” Proceedings of the IEEE, vol. 52, p. 2192, 1967. 13. B. Bryant and M. Kazimierczuk, “Effect of a current sensing resistor on required MOSFET size,” IEEE Transactions on Circuits and Systems-I, vol. 50, no. 5, pp. 708–711, May 2003. 14. A. B. Abou-Alfotouth, A. V. Radun, H.-R, Chung, and C. Winterhalter, “A 1-MHz hardswitching silicon carbide dc-dc converter,” IEEE Transactions on Power Electronics, vol. 21, no. 4, pp. 880–889, July 2006.

Review Questions 1. What is the physical structure of power MOSFETs? 2. What is the difference between the structure of an integrated MOSFET and a power MOSFET? 3. Explain the process of the channel formation in enhancement-mode MOSFETs. 4. How is the MOSFET channel conductivity controlled? 5. How can the MOSFET maximum drain current be increased? 6. How is a large value of the aspect ratio W/L achieved in power MOSFETs? 7. When is the dependence of ID on VGS quadratic and when is it linear? 8. What are the major components of the MOSFET on-resistance? 9. Compare the on-resistance for low-voltage and high-voltage power MOSFETs. 10. Compare the concentration doping of the drift region of low-voltage and high-voltage MOSFETs. 11. Compare the breakdown voltage of Si and SiC power MOSFETs.

12. What is the effect of channel-length modulation on the MOSFET iD–vDS characteristics? 13. What is the effect of channel-length modulation on the MOSFET channel resistance? 14. What is the “short-channel effect” on the MOSFET channel resistance? 15. Is the gate-to-source capacitance Cgs very nonlinear? 16. Are the gate-to-drain capacitance Cgd and the drain-to-source capacitance Cds nonlinear? 17. Is the mobility of carriers transported near the surface the same as that in bulk semiconductor? 18. What is the drift velocity saturation? 19. What is the physical structure of IGBTs? 20. How does the temperature rise ΔT depend on the heat radiating surface area? 21. What are the mechanisms of heat transfer? 22. What are the physical mechanisms of heat transfer?

Problems Power MOSFET Structure 1. A power MOSFET has: L = 1 μm, W/L = 1.6 × 106, Wp = 4 μm, and dpp = 2 μm. Find the overall channel width W, the number of cells n, the area of all cells Ac, the channel width per unit area D, the cell density CD, and the chip area utilization U. Assume that the source pads, gate pads, and the field guard rings increase the chip area by 25%. 2. A silicon MOSFET channel has μn = 600 cm2/V • s. Calculate Cox and kp for: (a) tox = 1 μm, (b) tox = 0.1 μm, and (c) tox = 0.01 μm. 3. Derive an expression for the channel width per unit area D for a power HEXFET and compare it to that of the power MOSFET with square cells.

Mobility 4. The drift velocity of silicon electrons at E = 100 kV/cm is 107 cm/s. Find μn. 5. (a) Calculate the low-field low-concentration electron mobility in bulk SiC at T = 500 K. (b) Calculate the low-concentration electron mobility in bulk SiC at E = 106 V/cm and T = 500 K. (c) Calculate the average drift group velocity of electrons in bulk SiC at E = 106 V/cm and T = 500 K.

Doping and Breakdown 6. Calculate the minimum thickness of the drift region WD for the power MOSFET with the breakdown voltage VBD = 50 V, 100 V, 200 V, and 400 V. 7. Calculate the maximum doping density of the drift region NDmax for the n-channel Si power MOSFET with the breakdown voltage VBD = 50 V, 100 V, 200 V, and 400 V. 8. The donor concentration in the drift region of the silicon n-channel power MOSFET is (a) ND = 1014 cm− 3, (b) ND = 1015 cm− 3, and (c) ND = 1016 cm− 3. Find the breakdown voltage VBD. 9. The donor concentration in the drift region of the silicon-carbide n-channel power MOSFET is (a) ND = 1014 cm− 3, (b) ND = 1015 cm− 3, and (c) ND = 1016 cm− 3. Find the breakdown voltage VBD. 10. A donor concentration in the SiC power MOSFET is ND = 1017 cm− 3. Find the breakdown voltage, the thickness of the drift region, and the resistance of the drift region for A = 0.1 cm2.

Resistances and Capacitances of Power MOSFETs 11. A power MOSFET has μnCox = 20 μA/V2, W/L = 104, Vt = 3 V, θ = 0.1, and VGS = 10 V. Find the drain saturation current at the boundary between the linear and the saturation region IDsat for a long-channel MOSFET, the long-channel resistance Rc, the short-channel resistance Rc(sc), and the ratio Rc(sc)/Rc. 12. A SiC power transistor has WD = 10 μm, ND = 1016 cm− 3, W = 1 m, dpp = Wp, n = 10, 000, hp = 2 μm, and μn = 900 cm2/(V • s), and Fcs = 1.7. Calculate the neck region resistances and the drift region resistance. 13. A power MOSFET has: tox = 0.1 μm, tm = 0.8 μm, L = 0.7 μm, Ln = 0.2 μm, W = 1 m, n = 10, 000, and dpp = W1/4. Calculate the gate-to-source capacitance Cgs.

Design of Power MOSFETs 14. Design a SiC n-channel power MOSFET for switching applications to meet the following specifications: VDSS = 1 kV, ISMmax = 10 A, rDS ≤ 0.2 Ω, μn = 400 cm2/V • s, Vt = 2 V, and VGSmax = 10 V. 15. Design a SiC n-channel power MOSFET for switching applications to meet the following specifications: VDSS = 600 V, ISMmax = 5 A, rDS ≤ 0.2 Ω, μn = 400 cm2/V • s, Vt = 1.5 V, and VGSmax = 10 V.

16. Design a SiC power MOSFET with: tox = 0.08 μm, VDSS = 5 kV, ISMmax = 2 A, VGS = 10 V, and Vt = 1 V. Determine NDmax, ND, WD, L, W, n, RDR, and Rch.

Heat Sinks 17. A power transistor has power dissipation PD = 2 W and the thermal junction-to-ambient thermal resistance θJA = 62.5°C/W. The maximum junction thermal resistance is Tjmax = 160°C. Find the maximum ambient temperature when no heat sink is used. 18. A power transistor has power dissipation PD = 2 W and the thermal junction-to-case thermal resistance θJC = 62.5°C/W. The maximum junction temperature is Tjmax = 160°C, the thermal case-to-sink thermal resistance is θCS = 0.6°C/W, and the sink-to-ambient thermal resistance is θCS = 6°C/W. Find the maximum ambient temperature when heat sink is used.

19 Electromagnetic Compatibility 19.1 Introduction All electrical products, including switch-mode power supplies, must meet various regulatory compliance requirements for safety, conducted electromagnetic interference (EMI) or radio frequency interference (RFI) emission, radiated EMI/RFI emission, and EMI immunity [1–17]. EMI is a form of electrical noise pollution that contaminates the environment. It is a worldwide problem. EMI may cause degradation of performance of other circuits and also selfdegradation of the source circuit. It is unintentional man-made noise, causing corruption of useful and intended signals. All switch-mode power supplies produced today include internal EMI filters to protect these circuits from excessive external noise and to protect other circuits from the EMI noise produced by power supplies. Electromagnetic compatibility (EMC) is the ability of electrical circuit to function sufficiently well in the presence of EMI. This chapter gives definitions of EMI, RFI, EMC, EMI immunity, EMI susceptibility, conducted noise, radiated noise, near field, and far field. It also explores EMI sources, EMC regulatory standards, EMI filters, ferrite beads, and shielding techniques.

19.2 Definition of EMI There are several definitions of EMI in the literature [3–11]. 1. EMI is the electromagnetic energy transmitted from one circuit or system, which degrades or obstructs the effective performance of another circuit or system. 2. EMI and RFI can also be defined as the process by which disruptive electromagnetic energy is transmitted from one electronic device to another through conductive path, radiative path, or both. 3. EMI or RFI is defined as a disturbance that affects electrical circuit or system operation caused by either EMI noise conduction or radiation emitted from an external source. The EMI noise may obstruct, interrupt, degrade, or limit the performance of an electrical circuit or system. Any electrical circuit that carries rapidly changing electric currents may become a source of EMI [3]. EMI is always a detrimental signal and may adversely affect the circuit operation. It is an unwanted signal that propagates by conduction or radiation. Therefore, the EMI must be reduced below a specified level to ensure that various circuits and systems can operate properly in the presence of each other, in which case the systems are said to be compatible. EMI emission is the generation of unwanted electromagnetic energy and must be reduced below certain acceptable limits to ensure that electrical circuits and systems do not cause any

disruption to other electrical equipment.

19.3 Definition of EMC There are several definitions for EMC [3–11]. 1. EMC is defined as the ability of an electrical circuit or system to function sufficiently well in its electromagnetic environment without generating unintentional interference to other circuits or systems. 2. EMC is defined as the capability of electrical systems, equipment, and devices to operate in their intended electromagnetic environment within a defined margin of safety and at design levels or performance without suffering or causing unacceptable degradation as a result of EMI. 3. EMC is defined as the ability of a circuit or a system to operate satisfactorily in its own electromagnetic environment and do not produce intolerable electromagnetic disturbance to other circuits or systems in that environment. 4. EMC is the ability of a system to function reliably in the presence of significant levels of EMI and to limit internally generated EMI to avoid interference with other systems. EMC contains two components: 1. It describes the ability of a circuit or a system to operate correctly as intended within a specified electromagnetic disturbance limits. 2. It describes the ability of a circuit or a system to operate correctly such that it does not produce interference for other circuits or systems above specified limits. The purpose of using EMC measures is to ensure that a variety of different electrical circuits and systems can operate in close proximity without causing any unwanted interference. EMC is an integral part of the design of any electrical circuit or system. Every new product must be tested and meet the relevant EMC standards. Electrical hardware must be designed and manufactured to satisfy the following requirements: 1. The electromagnetic disturbance generated by a circuit or a system does not exceed the level above which these circuits cannot operate as intended. 2. This circuit or system has a level of immunity to the electromagnetic disturbance to be expected in its environment, which allows it to operate without unacceptable degradation of its performance. Manufacturers of electrical circuits and systems are required to sufficiently protect their products from electromagnetic disturbance according to the standards. They are also required to ensure that their electrical products generate very low level of electromagnetic disturbance to the surrounding area, below specified interference limits.

19.4 EMI Immunity Immunity is a relative measure of the ability of a circuit or a system to withstand EMI exposure while maintaining a specified performance level. It is the resistance to noise. A key objective of electrical circuit or system design is to ensure a sufficient level of immunity to all kinds of unwanted noise signals. The conducted immunity of a circuit or a system is a relative ability to withstand electromagnetic energy that penetrates through power cords, external cables, and input–output interconnects. The radiated immunity of a circuit or a system is a relative ability to withstand electromagnetic energy that is received via free space propagation.

19.5 EMI Susceptibility Susceptibility is a relative measure of the tendency of a circuit or a system to be disrupted or damaged by EMI exposure due to lack of immunity. It is the tendency of a circuit or a system toward misbehavior when exposed to EMI. In other words, susceptibility is the opposite of the immunity. A properly designed circuit should satisfy the following conditions: 1. To tolerate a specified degree of interference. 2. Not to generate more than a specified degree of interference. 3. Be self-compatible.

19.6 Classification of EMI Electrical equipment can be affected by permanent interference or transient interference. EMI noise may be broadband or narrowband, and also internal or external. EMI noise can be divided into two categories: 1. Conducted EMI noise (9–30 kHz). 2. Radiated EMI noise often referred to as RFI noise (30 kHz to 1 GHz). Conducted noise travels along electrical conductors, power lines, signal lines, ground loops, wires, cords, cables, printed-circuit board traces, interconnects, component leads, and electrical components. Conducted noise current follows the path of the lowest magnitude of impedance. Current is a continuous quantity and must always return to its source. The conducted noise voltage is measured in dB μV. Radiated noise travels through space as magnetic fields or electromagnetic waves An incidental radiator is defined as a device that generates radio frequency energy during the course of its operation even though the device is not intentionally designed to generate or emit radio frequency energy. The radiated noise emission is tested by measuring the radiated electric field E in dB μV/m.

The device used to measure conducted emissions is a Line Impedance Stabilization Network (LISN). It is connected in series with a power cord of the device under test (DUT). The main purpose of the LISN circuit is to block noise currents from the utility power network from contaminating the test results. The EMI/RFI system model consists of three parts: EMI source, coupling path, and EMI receiver. It is necessary to know how the interference noise is traveling from the transmitting circuit to the receiving circuit. Both these kinds of noise are transmitted from the noise source (an aggressor) to the receptor (a victim) via coupling paths. The conducted noise is conducted via signal lines and power lines. The radiated noise is radiated via magnetic paths, electric paths, and electromagnetic plane waves. There are three categories of coupling paths: 1. EMI conduction due to the existence of a common impedance of two or more adjacent conductors. 2. EMI due to capacitive or inductive coupling (near-field interference). 3. RFI radiation (far-field interference). The frequency range of the conducted noise is from 9 kHz to 30 MHz, and the frequency range of the radiated noise is from 30 MHz to 1 GHz. Capacitive coupling occurs when a timevarying electric field E exists between two or more adjacent conductors. This type of coupling produces electric field interference. Inductive coupling occurs, when a time-varying magnetic field H exists between two or more parallel conductors. The inductive coupling produces magnetic field interference. Conducted EMI noise can be classified as: 1. Common-mode noise (CMN) 2. Differential-mode noise (DMN). Figure 19.1 shows the equivalent circuits for the CMN and the DMN. The CMN currents flowing in both signal and return conductors are in-phase and have equal amplitudes. In other words, two identical noise currents flow in the same direction, that is, ic1 = ic2 = ic. The noise current in each conductor uses the ground as a return path. The current in the ground path is ignd = 2ic.

Figure 19.1 Equivalent circuits for conducted noise. (a) Equivalent circuit for the commonmode noise. (b) Equivalent circuit for the differential-mode noise. Conversely, the DMN currents flowing in both signal and return conductors are out of phase by 180° and have equal amplitudes id1 = −id2 = id. it is ideally the same current. In other words, two identical noise currents flow in opposite directions. One conductor is a feed conductor and the other is a return conductor. Useful signal flows in the same direction as the differentialnoise current. The ratio of the total differential-mode current is usually higher than the common-mode current by a factor of 100. The voltages with respect to ground at two conductors leading to the load are (19.1) and (19.2)

Hence, the common voltage is (19.3) and the differential voltage is (19.4) The common-mode voltage is expressed mathematically as the average of the two voltages with respect to the local ground, common, chassis, or shield. The differential-mode voltage is expressed mathematically as the difference of the two voltages with respect to the local ground or common. The voltage source describing the DMN is connected in series with the useful signal. Conducted noise is usually reduced by EMI filters. The polarity of the voltage and the direction of the current for the DMN signal is the same as the useful signal for normal operation of the circuit. Radiated noise is usually reduced by an appropriate circuit layout and metal shielding.

19.7 Sources of EMI Understanding and optimizing EMC in switch-mode power supplies is an important problem. The switching action of semiconductor devices causes current pulses at the input and output of power supplies. For CCM operation, PWM converters have rectangular current and voltage waveforms with short rise and fall times as well as high rated di/dt and dv/dt. Therefore, these waveforms exhibit a wide and strong harmonic spectrum. For DCM, PWM converters have triangular current and nearly rectangular voltage waveforms. Cross-conduction of current in transistors connected in series generates very narrow and high current spikes. The ripple of the front-end rectifiers of ac power utility lines at 100/120 Hz is also a strong and wide bandwidth noise. In addition, EMI is generated by time-varying magnetic and electric fields. The EMI noise is transmitted by conductive, inductive, and capacitive couplings. PWM converters are therefore notorious sources of EMI and RFI. Switching semiconductor devices such as MOSFETs, IGBTs, and diodes are the main source of EMI/RFI generation. Current spikes generated by reverse recovery of fast power diodes produce a large amount of EMI with a broad current spectrum. The switching frequency of SMPSs is usually in the range 50 kHz to 1 MHz. Therefore, the significant harmonics are up to 20 or 50 MHz. Suppression of EMI is a major issue in switch-mode power converter design. Strong harmonics may interfere with various signals in electronic hardware (i.e., noise receptors), causing EMI internally or externally. For example, strong EMI may cause false triggering of logic circuits. A high slew rate of inductor current diL/dt causes a fast change in inductor voltage vL = LdiL/dt. Hence, differential-mode conducted EMI is caused by the magnetic coupling. Likewise, a high slew rate of capacitor voltage dvC/dt causes a fast change in a capacitor current iC = CdvC/dt, producing current spikes. Therefore, common-mode conducted noise is

caused by electrical coupling. An invisible equivalent circuit of the converter is formed by intentional components and parasitic components. Front-end rectifiers present highly nonlinear loads to the utility power lines, producing significant harmonics and reducing power factor. The ripple frequency of these rectifiers is either 100 or 120 Hz. The conduction angle of the line current is very low on the order of 5°. The order of significant harmonics can be as high as 20. Active and passive power factor correctors are used to reduce these harmonics and improve the power factor. In the United States, an ac voltage of 110 Vrms and 60 Hz exists between the phase (P) line and neutral (N) line conductors. The third conductor is a safety ground called the “green wire” (GW). Common-mode currents are measured in line (P) and neutral (N) with respect of ground (GW). Differential-mode currents are measured between line (L) and neutral (N) conductors.

19.8 Safety Standards Safety certification, validation, testing, and inspection is provided by Underwriters Laboratories (UL). UL is approved to perform safety testing by the US federal agency Occupational Safety and Health Administration (OSHA). There is also the Canadian Standards Association (CSA) that determines safety regulations. A common 0-V reference voltage should be provided for multiple circuits. A connection from ground to earth potential is required for most electrical equipment to protect against shock hazard. Otherwise, the equipment frame or metal chassis may unintentionally have a high potential and anyone touching the frame will provide a conductive path for the current. This may harm or even kill a person or an animal. The connection between the equipment ground and earth is called safety ground, which minimizes the voltage difference between conducting surfaces. AC line EMI filters must contain a bleeding (discharge) resistor connected in parallel with a filter capacitor to avoid a voltage across the filter capacitor in the event of open circuit. Many regulations have been established by the National Electric Codes (NEC) to ensure electrical circuits and systems are designed with proper safety standards.

19.9 EMC Standards Most countries and market areas have legal mandatory requirements on immunity and emission of commercial electronic products to meet stringent electrical noise regulation, that is, EMC standards, before they can be marketed and sold in these countries. The most frequently cited EMC standards are as follows: 1. Federal Communications Commission (FCC) Rules and Regulations, Title 47, Part 15, USA. 2. Testing and Certification Institute (German acronym Verband Deutscher Electrotechnik (VDE)), Germany. 3. International Electrotechnical Commission (IEC), Europe.

4. European Norms (EN). 5. International Special Committee for Radio Interference (CISPR), France, (French acronym Comité International Spécial des Perturbations Radioélectriques). 6. Canadian Standard Association (CSA). 7. Australian and New Zealand standards (AS/NZS). 8. Military standards (MIL-STD). EMC standards regulate the electrical industry by setting: 1. Limits on conducted emission. 2. Limits on radiated emission. 3. Limits on conducted susceptibility. 4. Limits on radiated susceptibility. The FCC Class A standard covers business, commercial, and industrial environments, while the FCC Class B standard covers residential environments. FCC Class B is more restrictive than FCC Class A. For common-mode conduction noise current for f < 1.7 MHz, FCC Class A requires current less than 40 μA, while Class B standard calles for less then 10 μA. For the frequency range from 1.7 to 30 MHz, FCC Class A requires current less than 120 μA, while FCC Class B requires less than 10 μA. For the common-mode radiated noise, FCC Class A requires 24, 15, and 11 μA at 30, 50, and 100 MHz, respectively, while FCC Class B requires 8, 5, and 3.5 μA at 30, 50, and 100 MHz, respectively. The VDE 0873 and VDE 0879 cover the conducted emissions in the frequency range from 0 to 10 kHz, while VDE 0871 and VDE 0872 cover the frequency range from 10 kHz to 30 MHz. The IEC 61000-3-2 international standard [1] sets limits on the maximum level of harmonics. Information technology equipment must comply with EMI standards, such as CISPR-22, which determines the limits of EMI noise generated at frequencies from 150 kHz to 300 MHz. All power supplies must satisfy the IEC555-2 standard for the utility line harmonics. Conducted emission limits in military applications are determined by the MIL-STD461E standard.

19.10 Near Field and Far Field The radiated electromagnetic field can be described as near field or far field. The wavelength of a periodic waveform is given by (19.5) where m/s is the speed of light in vacuum. The near field exists for the short distance from the EMI source

(19.6) For example, the near field is for d < 47.75 cm at f = 100 kHz and for d < 4.775 cm at f = 1 MHz. The far field exists for the long distance from the EMI source (19.7) For the near field, the electric field and the magnetic field can be considered separately. The near field noise is transmitted through magnetic field (inductive) coupling or through electric field (capacitive) coupling. The far field decays with 1/R, where R is the distance from the radiator of electromagnetic waves. The far-field approximation technique is called the inverse distance method. It is used to translate emission levels or emission limits from one value of R to another. The conducted noise is usually suppressed by adding properly designed EMI filters that reduce the power levels of various frequency components in a specific frequency band. EMI filters are connected between the utility line and power supplies of electronic equipment, which is a source of EMI. Metallic shields (e.g., metallic cabinets) are normally used to prevent radiated noise. Another approach to solving this problem is through spectral modification of EMI at source, which affects both conducted and radiated interference emission routes simultaneously. The idea is to spread the spectrum of the converter waveforms such that the power levels at specific frequencies are reduced below the required levels to confirm with EMI standards without any additional filters and shields. One method to accomplish this objective is random modulation of the converter switching (clock) frequency. This produces a random jitter around the normal periodic voltage and current waveforms, which results in spread in the spectrum and consequent reduction of the spectral peaks. Another method is converter operation under chaos and chaotic modulation. All switch-mode converters are strongly nonlinear systems and the occurrence of chaos is quite common in them. The chaotic behavior that naturally occurs in switch-mode dc–dc converters has some inherent problems in practical applications. First, the current ripple and hence the power level of ac components increase under chaotic operation, reducing efficiency. Second, the spectrum under chaotic operation has a higher emission floor, which spreads into the low-frequency range. This may result in audible acoustic disturbances.

19.11 Techniques of EMI Reduction The following techniques may be used to combat high EMI emission and low susceptibility: 1. Low-pass EMI filters 2. EMI/RFI shields 3. Spread spectrum clocking 4. Wide and short trace for return current 5. Feed-through capacitors (or EMI suppression capacitors)

6. Separation of power, digital, analog, and RF currents 7. Grounded layers 8. Double-sided boards 9. Avoiding hard switching 10. Using soft-switching topologies such as resonant converters [14, 15] 11. Avoiding cross-conduction 12. Minimization of the areas of current loops since the parasitic inductance is proportional to the area of the current loop [16] 13. Grounded heatsinks 14. Shielded cables 15. Short leads (l ≤ λ/20) 16. Coaxial cables 17. Bifilar (twisted) wire connections 18. Distributed short air gaps in magnetic cores.

19.12 Insertion Loss The insertion loss is defined as (19.8) were PO(wo) is the output power without the EMI filter and PO(w) is the output power with the EMI filter.

19.13 EMI Filters A common-mode EMI filter is shown in Figure 19.2. Figure 19.3 shows currents and magnetic fluxes in a common-mode EMI filter. A passive EMI filter consists of a ferrite toroidal core and two identical copper windings [16]. They also include “X” and “Y” capacitors. Each winding has N turns of insulated copper wire. Two solid wires are wrapped around the single magnetic core in the opposite directions. Solid wire is used because it has large skin-effect losses at high frequencies, which increases the high-frequency noise attenuation. The turns ratio is N: N = 1: 1. Single-layer windings are usually used in EMI filters. Multiple-layer inductors have a larger distributed capacitance and therefore a narrowband frequency range. Each winding is placed on the opposite side of the core to ensure isolation and reduce winding-to-winding capacitance. The bare wire diameter is determined by the maximum rms

current. Nickel-zinc (NiZn) ferrite cores have μr ≤ 1000, but very high operating frequencies of up to 400 MHz. Manganese-zinc (MnZn) cores have μr ≤ 15, 000, but low operating frequencies, typically below 20 kHz. The magnetic fluxes induced by the common-mode currents ic flow in the magnetic core in the same direction. The net magnetic flux become larger and produces a large inductance. If the coupling coefficient of both windings is k = 1, the total equivalent inductance of each winding is L1 = L2 = L + M = 2L, where is the mutual inductance. The toroidal core makes a very good coupling of both windings, but k < 1, resulting in Lequiv = L + kL = L(1 + k) and the leakage inductance of each winding Ll = (1 − k)L. The large inductance exhibits a large reactance XL1 = ωL1 = 2ωL and opposes the common-mode current flow. The differential-mode currents do not cause the magnetic core saturation. Neglecting the parasitic components such as leakage inductances, stray capacitances, winding resistance, and core loss, the input of the EMI filter for the commonmode operation is (19.9) and the input impedance for the differential-mode operation is (19.10)

Figure 19.2 Common-mode EMI filter.

Figure 19.3 Currents in common-mode EMI filter. (a) Common currents and magnetic flux. (b) Differential currents and magnetic flux. Differential-mode capacitors “X” are placed across the input line. The capacitances of X capacitors are up to CX = 2.2 μF and are typically rated to 365 Vrms for frequencies 50 and 60 Hz. Common-mode capacitors “Y” are connected between line to chassis ground and between natural to chassis ground. The capacitances of Y capacitors are up to CY = 4.7 nF. They are rated for 3 kV. Metalized film dielectrics like polypropylene or impregnated paper have the ability to “self-healing” of the dielectric layer. The turn-to-turn capacitance is [16] (19.11)

where εr is the permeability of the wire insulation, di is the bare wire diameter, and do is the

insulated wire diameter. The self-capacitance of each inductor in the common-mode EMI filter is (19.12) The self-capacitance Cs is connected in parallel with the series combination of the equivalent inductance Lequiv and the winding resistance. The impedance of the inductor above the selfresonant frequency (SRF) fr is capacitive and the current bypasses the inductance and flows through the self-capacitance capacitance, reducing the noise attenuation. In contrast, the difference-mode currents id induce magnetic fluxes that flow in the core in the opposite directions and cancel each other out. Therefore, the common-mode EMI filter ideally presents a zero reactance for the difference-mode currents and also for the useful signal. Thus, the common-mode filter acts only as an inductor for common-mode currents, but not for differential-mode currents. Inductors have a parasitic capacitance, resulting in a SRF. Above this frequency, the reactance of an inductor is capacitive, reducing noise attenuation. The selfcapacitance Cs is connected in parallel with the series combination of the equivalent inductance L1 and the winding resistance. The SRF is . Typical SFR values are in the range 1–10 MHz. A complete EMI line filter for the boost converter is shown in Figure 3.43. Ferrite beads. Ferrite beads are used as RFI passive filters. They are high-frequency attenuators of RF energy. The wire is wrapped around the core through the center of the core, usually 5 or 7 times. As the current flows through the wire, it produces a magnetic field around the wire in the core, producing an inductance. The ferrite and the winding forms an inductor with a very low quality factor Q. Ferrite beads are used in low-impedance lossy filters. The SRF is very high. The current flowing in the conductor induces a magnetic flux in the magnetic core, increasing the inductance and thereby the reactance. The lossy inductor absorbs the EMI noise energy and converts it into heat. A ferrite bead prevents interference conduction in both directions, from and to a circuit. Ferrate beads affect equally both the common-mode and differential-mode currents.

19.14 Feed-Through Capacitors In a feed-through capacitor, the ground terminal is surrounded by a dielectric and the signal terminal passes through this dielectric. These capacitors are installed in the shielding enclosure through the mounting hole and soldered directly to the shielding metallic plate. Since the lead inductances of both the ground terminal and the signal terminal are very low, the SRF is very high, and the reactance of these capacitors is capacitive for very high frequencies. Feed-through capacitors are usually made of a metalized film, which has a self-healing property. The capacitor repairs itself after a high voltage spike. Each layer acts as a single capacitor; if any one layer is damaged, the rest of the capacitors are not affected and the total capacitance is slightly lower.

19.15 EMI Shielding RFI radiation may be blocked or reduced using metallic shields. A shield can be a metallic enclosure or box around a circuit or a conductor. Plastic boxes with conductive coating can also be used. All zero reference or common points of the circuit should be tied to a single point on the shield. A shield can attenuate electromagnetic waves and can also reflect waves on both sides of the metallic shield. The shielding effectiveness is defined as (19.13) where Pt is the transmitted power with no shield and Ps is the transmitted power with the shield. Typically, 40–60 dB of shielding effectiveness is sufficient for most radiated EMI regulations. The power of electromagnetic wave is (19.14) where

is the impedance of air.

In general, the complex propagation constant is given by (19.15) For good conductors used for shielding, σ ωε, and the complex propagation constant simplifies to (19.16) where

and the attenuation coefficient is (19.17)

When the electric field propagates through a metallic shield, the amplitude of the electric field on the shield outer surface is (19.18) where w is the thickness of the metallic shield, Ei is the amplitude of the electric field on the inner surface of the metallic shield, and Eo is the amplitude of the electric field on the outer surface of the metallic shield. Hence, the minimum thickness of the metallic shield is

(19.19) Example 19.1 A switch-mode power supply is operated at f = 10 MHz. The amplitude of the electric field radiated from the SMPS at the inner surface of aluminum enclosure is Eo = 100 mV/m. The required amplitude of the electric field at the outer surface should be not greater than Eo = 1 mV/m. Find the thickness of aluminum shield, radiated power inside and outside the shield, and shielding effectiveness. Solution: The conductivity of aluminum is σAl = 3.54 × 107 S/m. The attenuation coefficient is (19.20) The thickness of the enclosure metallic aluminum is (19.21) The radiated power inside the box is (19.22) The radiated power outside the box is (19.23) The shielding effectiveness is (19.24)

19.16 Interconnections Small-signal paths should be isolated from high-power high-frequency interference sources. PCB traces and magnetic wire act as transmitter and receiver antennas. They should be maintained as short and wide as possible. The widths should be the current capability and spaced apart to avoid voltage breakdown. Inductors should be kept far from sensitive control circuits to reduce the RFI level and heat radiation. High-frequency noise signals generated from the switching action of active devices flow beck to the power line and other circuits in conducted and radiated forms.

Interconnects may serve as paths for a conducted boise and may behave like antennas, which generate radiated noise. The dc resistance of a PCB trace of width w, thickness t, and length l is (19.25) The high-frequency resistance of a PCB trace of width w, thickness t, and length l is (19.26) The dc resistance of round wire of length l, conductive diameter d, and resistivity ρ is (19.27) The ac resistance of round wire is (19.28) where the skin effect is (19.29) The low-frequency internal inductance is (19.30) This gives an inductance of 50 nH/m. The high-frequency internal inductance is (19.31) The high-frequency external inductance is (19.32)

19.17 Summary Switch-mode power supplies are sources of a large amount of EMI. The primary purpose of a safety ground is the protection of people and animals from the hazard of electric shocks. EMC requires that circuits and systems be able to tolerate a specified degree of

disturbance and not generate more than a specified amount of interference. Electrical industry is well-regulated from point of view of safety and EMC. EMI noise can be conducted, radiated, or both. The frequencies of the conducted noise are in the range 9 kHz to 30 MHz. The radiated noise is in the range 30 MHz to 1 GHz. EMI noise can be DMN and CMN. EMI noise can be internal or external. EMI noise can be narrowband or wideband. The return path of the supply current should be short and wide.

References 1. “IEC 61000-3-2 Standards for Electromagnetic Compatibility (EMC), Part 3, Section 2: Limits for Harmonic Current Emission,” International Electrotechnical Commission, Geneva, Switzerland, April 1995. 2. H. Ott, Noise Reduction Techniques in Electrical Systems, 2nd Ed. New York: John Wiley & Sons, 1988. 3. C. R. Paul, Introduction to Electromagnetic Compatibility. New York: John Wiley & Sons Interscience, 1992. 4. W. D. Kimmel and D. D. Gerke, Electromagnetic Compatibility in Medical Equipment. CRC Press, 1995. 5. C. Christopolos, Principles and Techniques of Electromagnetic Compatibility. CRC Press, 1995. 6. T. Williams, EMC for Product Designers, 2nd Ed. New York: Oxford, 1996. 7. M. I. Montrose, Printed Circuit Board Design Techniques for EMI Compliance. Piscataway, NJ: IEEE Press, 1996. 8. R. West, “Common mode inductors for EMI filters require careful attention to core material selection,” PCIM, July 1996. 9. R. Gratz and B. Moeckel, “Understanding and eliminating EMI in microcontroller design,” AN-1050, National Semiconductor, 1996. 10. www.FCC.govp, www.iec.ch, www.Europe.eu.int. 11. M. I. Montrose, EMC and the Printed Circuit Boards. Piscataway, NJ: IEEE Press, 1999. 12. D. A. Watson, Electromagnetic Compatibility: Principles and Compatibility, 2nd Ed. New York: Dekker, 2001.

13. M. Berman, “All about EMI filters,” Electronic Products, pp. 51–53, October 2008. 14. M. K. Kazimierczuk and D. Czarkowski, Resonant Power Converters, 2nd Ed. New York: John Wiley & Sons, 2011. 15. M. K. Kazimierczuk, RF Power Amplifiers. Chichester, UK: John Wiley & Sons, 2014. 16. M. K. Kazimierczuk, High-Frequency Magnetic Components, 2nd Ed. Chichester, UK, John Wiley & Sons, 2014. 17. S. Pasko, M. K. Kazimierczuk, and B. Grzesik, “Self-capacitance of coupled toroidal inductors for EMI filters,” IEEE Transactions on Electromagnetic Compatibility, vol. 57, no. 2, pp. 216–223, April 2015.

Review Questions 1. Give the definition of EMI. 2. Give the definition of EMC. 3. Define the EMI immunity. 4. Define the EMI susceptibility. 5. Give a classification of EMI. 6. Define the common-mode currents. 7. Define the difference-mode currents. 8. List sources of EMI. 9. What are safety standards? 10. What are EMC standards? 11. List four EMC standards. 12. What is the near field? 13. What is the far field? 14. Describe the construction of a common-mode EMI filter. 15. Describe the construction of a ferrite bead. 16. What is an EMI shield?

Problem 1. The amplitude of the electric field radiated from the SMPS at the inner surface of aluminum enclosure is Ei = 100 mV/m. The required amplitude of the electric field at the outer

surface should be not greater than Eo = 1 mV/m. Find the thickness of aluminum shield, the power inside and outside the shield, and shielding effectiveness for a switch-mode power supply operated at the following frequencies: a. f = 1 kHz. b. f = 50 kHz. c. f = 100 kHz. d. f = 1 MHz.

Appendices

A Introduction to SPICE SPICE is an abbreviation for Simulation Program for Integrated Circuits Emphasis. PSPICE is the PC version of SPICE. Analog and digital electronic circuit designs are verified widely by both industries and the academia using PSPICE. It is used to predict the circuit behavior.

Passive Components: Resistors, Capacitors, and Inductors Rname N+ N− Value [IC = TC1] Lname N+ N− Value [IC = Initial Voltage Condition] Cname N+ N− Value [IC = Initial Current Condition] Examples: R1 1 2 10K L2 2 3 2M C3 3 4 100P

Transformer Lp Np+ Np− Lpvalue Ls Ns+ Ns− Lsvalue Kname Lp Ls K Example: Lp 1 0 1mH Ls 2 4 100uH Kt Lp Ls 0.999

Temperature .TEMP list of temperatures Example: .TEMP 27 100 150

Independent DC Sources Vname N+ N− DC Value Iname N+ N− DC Value

Examples: Vin 1 0 DC 10V Is 1 0 DC 2A

DC Sweep Analysis .DC Vsource-name Vstart Vstop Vstep Example: .DC VD 0V 0.75V 1mV

Independent Pulse Source for Transient Analysis Vname N+ N− PULSE (VL VH td tr tf PW T) Example: VGS 1 0 PULSE(0 1E-6 0 1 1 10E-6 100e-6)

Transient Analysis .TRAN time-step time-stop Example: .TRAN 0.1ms 100ms 0ms 0.2ms .TRAN TSTEP TSTOP TSTEP is the printing increment. TSTOP is the final time. TSTART is the starting time (if omitted, TSTART is assumed to be zero). TMAX is the maximum step size. UIC stands for USE Initial Condition.

Independent AC Sources for Frequency Response Vname N+ N− AC Vm Phase Iname N+ N− AC Im Phase Example: Vs 2 3 AC 2 30 Is 2 3 AC 0.5 30

Independent Sinusoidal AC Sources for Transient Analysis Vname N+ N− SIN (Voffset Vm f T-delay Damping-Factor Phase-delay)

Iname N+ N− SIN (Ioffset Im f T-delay Damping-Factor Phase-delay) Examples: Vin 1 0 SIN (0 170V 60Hz 0 -120) Is 1 0 SIN (0 2A 120Hz 0 45)

AC Frequency Analysis .AC DEC points-per-decade fstart fstop Example: .AC DEC 100 20 20kHz

Operating Point .OP

Getting Started the SPICE Program 1. Open the PSpice A/D Lite window (Start > Programs > Orcad9.2 Lite Edition > PSpice AD Lite). 2. Create a new text file (File > New > Text File). 3. Type the example code. 4. Save the file as fn.cir (for example, Lab1.cir), file type: all files, and simulate by pressing the appropriate icon. 5. To include the Spice code of a commercial device model, visit the web site, e.g., http://www.irf.com, http:www.onsemi.com, or http://www.cree.com. For example, for IRF devices, click on (Design > Support > Models > Spice Library).

Example Program Diode I-V Characteristics *Joe Smith VD 1 0 DC 0.75V D1N4001 1 0 Power-Diode .model Power-Diode D (Is=195pA n=1.5) .DC VD 0V 0.75V 1mV .TEMP 27C 50C 100C 150C .probe .end

B Introduction to MATLAB® MATLAB® is an abbreviation for MATrix LABoratory. It is a very powerful mathematical tool used to perform numerical computation using matrices and vectors to obtain two and threedimensional graphs. MATLAB® can also be used to perform complex mathematical analysis.

Getting Started 1. Open MATLAB® by clicking Start > Programs > MATLAB® > R2006a. 2. Open a new M-file by clicking File > New > M-File. 3. Type the code in the M-File. 4. Save the file as fn.m (e.g., Lab1.m). 5. Simulate the code by doing one of the following: a. Click on Debug > Run. b. Press F5 c. On the tool bar, click the icon Run. Use HELP by pressing F1. Use % at the beginning of a line for comments.

Generating an x-axis Data x=Initial-Value: Increment:Final-Value; Example: x=1:0.001:5; or x=[list of all the values]; Example: x = [1, 2, 3, 5, 7, 10]; or x = linspace(start-value, stop-value, number-of-points); Example: x = linspace(0, 2*pi, 90);

or x = logspace(start-power, stop-power, number-of-points); Example: x = logspace(1, 5, 1000);

Semilogarithemic Scale semilogx(x-variable, y-variable); grid on

Log–log Scale loglog(x, y); grid on

Generate a y-axis Data y = f(x); Example: y = cos(x); z = sin(x);

Multiplication and Division A dot should be used in front of the operator for matrix multiplication and division. c = a.*b; or c = a./b;

Symbols and Units Math symbols should be in italic. Math signs (like ( ), =, and +) and units should not be in italic. Leave one space between a symbol and a unit.

x-axis and y-axis Labels xlabel(‘{\it x} (unit) ’) ylabel(‘{\it y} (unit) ’) Example: xlabel(‘{\it v_{GS}} (V)’) ylabel(‘{\it i_{DS}} (A)’) set(gca, ‘ylim’, [1, 10])

set(gca, ‘ytick’, [0:2:10])

Greek Symbols Type: \alpha , \beta , \Omega , \omega , \pi , \phi , \psi , \gamma , \theta , and \circ to obtain: α, β, Ω, ω, π, ϕ, ψ, γ, θ, and ○, respectively.

Plot Commands plot (x, y, ‘.-’, x, z, ‘- -’) set(gca, ‘xlim’, [x1, x2]); set(gca, ‘ylim’, [y1, y2]); set(gca, ‘xtick’, [x1:scale-increment:x2]); text(x, y, ‘{\it symbol} = 25 V’); plot(x, y), axis equal Examples: set(gca, ‘xlim’, [4, 10]); set(gca, ‘ylim’, [1, 8]); set(gca, ‘xtick’, [4:1:10]); text(x, y, ‘{\it V} = 25 V’);

3D Plot Commands [X1, Y1] = meshgrid(x1, y1); mesh(X1, Y1, z1); Example of a code for a 3-D figure: clc clear all close all T1 = 300:10:500; E1 = logspace(1, 7, 100); [E, T] = meshgrid (E1, T1); vsat = 1e6; N = 1e15; mun3001 = 92 + 1268./(1 + (N./1.3e17)0.91); mun01 = mun3001*(300./T).2.4;

mun1 = mun01./(1 + mun01.*E./vsat); figure(1) mesh(E,T,mun1) set(gca,‘XScale’,‘log’, ‘xlim’,[1e1,1e7],‘xtick’,[1e1, 1e3, 1e5, 1e7]) xlabel(‘E (V/m)’); ylabel(‘T (K)’); zlabel(‘μn (cm2/V · s)’) figure(2) loglog(E1, mun1) xlabel(‘E (V/cm)’); ylabel(‘T (K)’); zlabel(‘μn (cm2/V · s)’) Example for 3-D plot: rL1 = 0.213; VF = 0.65; D = 0.55; RL = 6.66; VO = 10:0.1;18; PO = 25:0.1:35; [PO, VO] = mashgrid(PO, VO); PrL =D.*D.*rL1.*(PO/RL); PVF = (PO.*VF./VO).*sqrt(1 − D); Ploss = PrL + PVF; eta = PO./(PO + Ploss); figure(2) mesh(PO, eta*100) xlabel(‘PO (W)’) ylabel(‘VO (V)’) zlabel(‘eta’)

Complex Functions magA = mag(A)

phaseA = angle(A) phasedegA = phaseA*180/pi realA = real(A) imagA = imag(A)

Bode Plots f = logspace(start-power, stop-power, number-of-points) NumF = [a1 a2 a3]; %Define the numerator of polynomial in s-domain. DenF = [b1 b2 b3];  %Define the denominator of polynomial in s-domain. [MagF, PhaseF] = bode(NumF, DenF, (2*pi.*f)); figure(1) semilogx(f, 20.*log10(MagF)) figure(2) semilogx(f, PhaseF)) or F = tf(NumF, DenF)%Converts the polynomial into transfer function. [NumF, DenF] = tfdata(F) %Converts transfer function into polynomial. Example: f = logspace(0, 5, 10000) NumF = [0 2000*pi]; DenF = [1 2000*pi]; [MagF, PhaseF] = bode(NumF, DenF, (2*pi.*f)); figure(1) semilogx(f, 20.*log10(MagF)) figure(2) semilogx(f, PhaseF))

Step Response NumF = [a1 a2 a3]; %Define the numerator of polynomial in s-domain. DenF = [b1 b2 b3];  %Define the denominator of polynomial in s-domain. t = [0:0.00001:0.0005]; [y x] = step(NumF, DenF, t);

figure(3) plot(t, Initial-Value + y); Example 1: NumF = [0 2000*pi]; DenF = [1 2000*pi]; y = step(NumF, DenF, t); t = [0:0.0001:0.05]; figure(3) plot(t, 2 + y); Example 2: Num = [0 2000*pi]; Den = [1 2000*pi]; Mv = tf(Num,Den); t = 0:0.0000001:5e-3; u = step(Mv, t); figure(2) plot(t*1000, u) grid on xlabel(‘t (ms)’) ylabel(‘vo (V)’)

To Save Figure Go to File, click Save as, go to EPS file option, type the file name, and click Save.

Example Program clear all clc x = linspace(0, 2*pi, 90); y = sin(x); z = cos(x); grid on xlabel(‘{\it x}’)

ylabel(‘{\it y}, {\it z}’) plot(x , y, ‘-.’, x, z, ‘- -’)

Polynomial Curve Fitting x = [0 0.5 1.0 1.5 2.0 2.5 3.0]; y = [10 12 16 24 30 37 51]; p = polyfit(x, y, 2) yc = polyval(p, x); plot(x, y, ‘x’, x, yc) xlabel(‘x’) ylabel(‘y’), grid legend(‘Actual data’, ‘Fitted polynomial’)

C Physical Constants Table A.1 Physical constants Physical constants

Symbol

Value 1.3806488 × 10− 23 J/K

Boltzmann’s constant

= 8.62 × 10− 5 eV/K Planck’s constant

h

6.62617 × 10− 34 J · s = 4.14 × 10− 15 eV · s

Electron charge magnitude

q

8.85418 × 10− 12 F/m

Free-space permittivity Free-space permeability

1.60218 × 10− 19 C

μ0

4π × 10− 7 H/m 2.998 × 108 m/s

Speed of light in free space Mass of free electron

me

9.1095 × 10− 31 kg

Mass of free proton

mh

1.673 × 10− 27 kg

Energy

1 eV

1.60218 × 10− 19 J

Thermal voltage

0.0259 V at T = 300 K

Silicon band gap energy

EG(Si)

1.12 eV = 1.793 × 10− 19 J

Silicon-carbide band gap energy

EG(SiC)

3.26 eV = 5.216 × 10− 19 J

Gallium-nitride band gap energy

EG(GaN)

3.39 eV = 5.43 × 10− 19 J 9 eV = 14.449 × 10− 19 J

Silicon-dioxide band gap energy Silicon breakdown electric field

EBD(Si)

2 × 105 V/cm

Silicon-carbide breakdown electric field

EBD(SiC)

22 × 105 V/cm

Gallium-nitride breakdown electric field

EBD(GaN)

15 × 105 V/cm

Silicon-dioxide breakdown electric field Silicon relative permittivity

εr(Si)

60 × 105 V/cm 11.7

Silicon-carbide relative permittivity

εr(SiC)

9.7

Gallium-nitride relative permittivity

εr(GaN)

8.9

Silicon-dioxide relative permittivity

3.9

Silicon electron mobility

μn(Si)

1360 cm2/V · s

Silicon hole mobility

μp(Si)

480 cm2/V · s

Silicon-carbide electron mobility

μn(SiC)

900 cm2/V · s

Silicon-carbide hole mobility

μp(SiC)

120 cm2/V · s

Gallium-nitride electron mobility

μn(GaN)

2000 cm2/V · s

Gallium-nitride hole mobility

μp(GaN)

300 cm2/V · s

Silicon effective mass coefficients

ke(Si), kh(Si)

0.26, 0.39

Silicon intrinsic concentration

ni(Si)

0.173 × 1010 cm− 3 at T = 300 K

Silicon-carbide effective mass coefficients ke(SiC), kh(SiC) Silicon-carbide intrinsic concentration

ni(SiC)

0.3654, 1 0.532 × 10− 8 cm− 3 at T = 300 K

Gallium-nitride effective mass coefficients ke(GaN), kh(GaN) 0.232, 0.247 Gallium-nitride intrinsic concentration

ni(GaN)

1.075 × 10− 10 cm− 3 at T = 300 K

Silicon thermal conductivity

kth(Si)

1.5 W/K · cm

Silicon-carbide thermal conductivity

kth(SiC)

4.56 W/K · cm

Gallium-nitride thermal conductivity

kth(GaN)

1.3 W/K · cm

Answers to Problems

Chapter 1 1. LNR = 10 mV/V, PLNR = 0.303%/V. 2. LOR = 0.2 mV/mA, PLOR = 0.2%, Ro = 0.2 Ω, LLR = 4%/A. 3. ηFL(min) = 22%, ηFL(max) = 55%. 4. MV DC = 0.5, Rin(DC) = 36 Ω. 5. LOR = 100 mV/A, PLOR = 0.25%, and Ro = 0.1 Ω.

Chapter 2 1. MV DC = VO/VI = D. 2. Lmin = 492.2 μH. 3. ISMmax = 2.179 A, VSMmax = 32 V. 4. Vr = 3.214 mV, VCpp = 1 mV, f0 = 1.592 kHz. 5. Vr = 5.4 mV. 6. (a) D = 0.5 at η = 100%. (b) D = 0.625 at η = 80%. 7. For D = 0.1, PrDS = 0.25 W. For D = 0.9, PrDS = 2.25 W. 8. For D = 0.1, PD = 4.95 W. For D = 0.9, PD = 0.55 W. 9. CJ0 = 585.95 pF, Cds(VI) = 25.35 pF, Q(VI) = 20.32 nC, Psw = 8.112 W, Pturn − off = 5.408 W, Psw(FET) = 2.704 W. 10. Lmax = 25.6 μH. 11. POmax = 50 W, POmin = 5 W, RLmin = 0.5 Ω, RLmax = 5 Ω, MV DCmin = 0.3125, MV DCnom = 0.4167, MV DCmax = 0.625, Dmin = 0.3906, Dnom = 0.5209, Dmax = 0.7813, Lmin = 15.235 μH, Vr = 50 mV, ΔiLmax = 1.5235 A, rCmax = 32.82 m Ω, Cmin = 130 μF, VSMmax = VDMmax = 16 V, ISMmax = IDMmax = 10.762 A, PLS = 8.56 W, η = 85.37%. 12. POmax = 96 W, POmin = 9.6 W, RLmin = 24 Ω, RLmax = 240 Ω, MV DCmin = 0.1286, MV DCmax = 0.4, Dmin = 0.143, Dmax = 0.4444, Lmin = 0.5142 mH, Vr = 480 mV, ΔiLmax = 0.3428 A, rCmax = 1.4 Ω, Cmin = 2.1425 μF, VSMmax = VDMmax = 373.35 V, ISMmax = IDMmax = 2.1714 A, PLS = 8.6578 W, η = 91.728%. 13. Lmax = 0.2 μH, Cmin = 589.2 μF, rCmax = 3 m Ω. 14. Lmax = 8.2 μH, Cmin = 228 μF, rCmax = 37.4 m Ω.

Chapter 3 1. MV DC = VO/VI = 1/(1 − D). 2. VSMmax = VDMmax = 380 V, ISMmax = IDMmax = 0.574 A. 3. Lmin = 47 μH. 4. Lmin = 47 μH. 5. (a) D = 0.5 at η = 100%. (b) D = 0.6 at η = 80%. 6. PrDS = 0.247 W, PrDS = 0.625 W, PrDS = 1.224 W, PrDS = 2.222 W, PrDS = 4 W, PrDS = 7.5 W, PrDS = 15.556 W, PrDS = 40 W, PrDS = 180 W. 7. PRF = 2.222 W, PRF = 2.5 W, PRF = 4 W, PRF = 10 W, PRF = 20 W. 8. PrL = 2.469 W, PrL = 3.125 W, PrL = 4.082 W, PrL = 5.556 W, PrL = 8 W, PrL = 12.5 W, PrL = 22.22 W, PrL = 50 W, PrL = 200 W. 9. Lmax = 2.22 μH.

Chapter 4 1. Lmin = 304 μH. 2. Lmin = 283.15 μH. 3. VSMmax = VDMmax = 235 V, ISMmax = IDMmax = 3.666 A. 4. Cmin = 82 μF/63 V/70 mω, rCmax = 79.63 m Ω. 5. PrC = 0.111 W, PrC = 0.25 W, PrC = 0.429 W, PrC = 0.667 W, PrC = 1 W, PrC = 1.5 W, PrC = 2.333 W, PrC = 4 W, PrC = 9 W. 6. Lmax = 126.39 μH. 7. Lmax = 115 μH. 8. For lossless buck converter, For lossy buck converter,

. .

Chapter 5 1. n = 1/3, Dmax = 0.6885. 2. VSMmax = 454 V, VDMmax = 1361 V. 3. Lm(min) = 711 μH. 4. ISMmax = 5.183 A, IDMmax = 1.728 A. 5. Cmin = 1.5 μF/1 kV/1.5 Ω, rCmax = 1.736 Ω. 6. (a)Lm(max) = 172.5 μH. (b)Lm(max) = 57.849 μH.

Chapter 6 1. (a) DMAX = 0.6667. (b) DMAX = 0.3333. (c) DMAX = 0.2. 2. (a) VSM = 3VI. (b) VSM = 1.5VI. (c) VSM = 1.25VI. 3. (a) VD3M = 1.5VI. (b) VD3M = 3VI. (c) VD3M = 5VI. 4. n1 = 8. 5. DMAX = 0.5. 6. Dmin = 0.3119, Dnom = 0.3428, Dmax = 0.381. 7. VSMmax = 684 V, VD1Mmax = 42.75 V, VD2Mmax = 42.75 V, VD3Mmax = 684 V. 8. Lmin = 13.762 μH. 9. Cmin = 229 μF, fo = 2.055 kHz, rCmax = 21.8 m Ω. 10. ID1Mmax = ID2Mmax = 42.753 A. 11. Lm(min) = 2.219 mH. 12. ISMmax = 5.985 A. 13. Lmax = 12.38 μH.

Chapter 7 1. VDMmax = VIMax/(2n). 2. n = 9, Dmin = 0.3424, Dmax = 0.4193. 3. VSMmax = 342 V, VDMmax = 38 V. 4. Lmin = 18.9 μH. 5. Cmin = 41.93 μF, fo = 4.5 kHz. 6. Lm(min) = 5.08 mH. 7. Lmax = 0.6858 μH.

Chapter 8 1. VDMmax = VImax/n. 2. n = 2, Dmin = 0.27021, Dmax = 0.3968. 3. For the transformer center-tapped rectifier, VSMmax = VDMmax = 187 V. For the transformer bridge rectifier, VSMmax = VDMmax = 93.5 V. 4. ΔiLmax = 31.543 A, ΔiLmax/IOmax = 60.6%. 5. Lmin = 60.65 μH. 6. Cmin = 75.58 μF, fo = 1.9 kHz. 7. Lm(min) = 425.788 μH. 8. ISMmax = 35.58 A, IDMmax = 67.7714 A. 9. n = 1/10, Dmin = 0.2815, Dmax = 0.4144. 10. VSMmax = 187 V, VDMmax = 1870 V. 11. Lmin = 21.85 mH. 12. Cmin = 82.88 μF, rCmax = 57.18 Ω.

Chapter 9 1. IS = 0.4IL, VLD = 0.4VSD. 2. rDSAV(S) = 2.5 Ω, RFAV(D) = 40 m Ω, VFAV(D) = 0.7 V. 3. rDSAV(L) = 0.4 Ω, RFAV(L) = 14.4 m Ω, VFAV(L) = 0.42 V. 4. rDSAV(S) = 2.5 Ω, RFAV(S) = 90 m Ω, VFAV(S) = 1.05 V. 5. rDSAV(D) = 1.1111 Ω, RFAV(D) = 40 m Ω, VFAV(D) = 0.7 V. 6. r = 0.6144 Ω. 7. rL(S) = 1.25 Ω, rL(D) = 0.556 Ω. 8. Dil = 0.4il A, ILd = 1.8d A, Dvds = 0.4vds V, VDSd = 24d V, r = 0.6144 Ω.

Chapter 10 1. zn = −200 krad/s, fz = 31.83 kHz, f0 = 2.605 kHz, ξ = 0.3879, Q = 1.289, p1, p2 = −6336.8 ± j15057.175 rad/s, fd = 2.396 kHz. 2. Tpo = 21.49, 25.074, 28.66, 23.72, 27.68, 31.63 V......... 3. fpk = 2.178 kHz, |Tp(pk)| = 35.06 V. 4. Mvo = 0.4476, fpk = 2.178 kHz, |Mv(pk)| = 0.6262. 5. fcr = 1.273 kHz, Ri(0) = 5.36 Ω, Zi(∞) = ∞. 6. frl = 557.04 Hz, Ro(0) = 0.125 Ω. 7. f0 = 2.516 kHz, ξ = 0.2635, Q = 1.8973, f0(actual)/f0(approx) = 1.035, ξactual/xiapprox = 1.472. 8. f0 = 2.526 kHz, ξ = 0.1756, Q = 2.847, p1, p2 = −2787 ± j15, 624.7 rad/s, fd = 2.49 kHz. 9. ξ = 0.02635, Q = 18.974, ξactual/ξapprox = 14.721. 10. Tpo = 27.9553 V, z = −49.952 krad/s, fz = 7.95 kHz, f0 = 1.28 kHz, ξ = 0.1255, Q = 3.984, p1, p2 = −1010.9 ± j7991.35 rad/s fd = 1.272 kHz. 11. Mvo = 0.5541, vo(∞) = 0.5541 V, vOmax = 12.5541 V, Smax = 66.23%, vomax = 0.9237 V, δmax = 2.9%.

Chapter 11 1. MV DC = 8.98 dB, η = 98.41%. 2. zn = −106 rad/s, zp = 7.1683 krad/s, f0 = 323.55 Hz, ξ = 0.162, Q = 3.086, p1, p2 = −329.3 ± j2006.07 rad/s, fd = 319.276 Hz. 3. Tpo = 60.9 dBV, |Tp(∞)| = −3.84 dBV. 4. Mvo = 9 dB. 5. Zi(0) = 220.561 Ω. 6. Zo(0) = 22.217 Ω, Zo(∞) = 1 Ω. 7. Zo(0) = 3.4 Ω, Zo(0) = 10.96 Ω, Zo(0) = 66.329 Ω, Zo(0) = 238.61 Ω. 8. ξlossy/ξlossless = 1.165, Q = 3.597, ξ = 0.139. 9. (a) zpmin = −435.897 rad/s, zpmax = 40.038 krad/s. (b) D = 0.9353.

Chapter 12 1. Tm = 0.4 1/V. 2. VR = 2.5 V. 3. β = 0.2, RA = 3.7 k Ω, RB = 1 k Ω, h11 = 796 Ω. 4. R1 = 5.1 k Ω, R2 = 2.7 k Ω, C1 = 150 nF, C2 = 2.7 nF. 5. |Mvcl| = 0.01, Vr(out) = 10 mV.

Chapter 13 1. Tm = 0.2 (1/V). 2. VR = 3.25 V. 3. β = 1/123 = −41.8 dB. RB = 1 k Ω, RA = 120 k Ω, h11 = 992 Ω. 4. Tko = 5.162 dB. 5. R1 = 100 k Ω, R2 = 10 k Ω, R3 = 390 Ω, C1 = 270 nF, C2 = 3.9 nF, C3 = 33 nF. 6. Tclo = 41.8 dB. 7. Ricl(0) = −215 Ω at RLmin, Ricl(0) = −2175 Ω at RLmax.

Chapter 14 1. VI > 2VO = 10 V. 2. VI > 11.11 V. 3. Stable because D < 0.5. Slope compensation may be required to achieve a sufficient margin of stability. M1 = 76.41 × 103 A/s. 4. Unstable because Dmax > 0.5. Slope compensation is required. 5. VTm = 0.664 V, M3opt = 66.45 × 103 A/s. 6. M3nom = 46.847346 × 103 A/s, Ipk = 0.468 A. 7. Hicl(z) = 13z/(z + 0.3), Hicl(s) = 120 × 1010/(s2 + 323076.9s + 12 × 1010), Ti(s) = 12 × 1010/[s(s + 323076.9)]. 8. VO = −31.154 V. 9. Dmax = 0.8, amax = 0.292, M3min = 0.574 A/ μs. 10. 11. f1 = 145.2 kHz, f)sh = 130.82 kHz, fci = 110.474 kHz,

Chapter 15 1. zi1 = −1124 rad/s, fzi1 = 178.8 Hz. 2. Tpio = 11.19 dBA, Tpix = 142.5 dBA. 3. Mvio = −46.78 dBA/V, fzi2 = 89.46 Hz. 4. Tolo = 9 dB, fzn = 159 kHz.

Chapter 16 1. L = 554.2 μH, C = 1 μF/630 V. 2. r = 4.419, ki = 1.4 A, ri = 443.36 Ω, gm = 2.885 mA/V, ko = 0.9 A, ro = 1.084 k Ω. 3. Tpo = 586.68 V, Tpx = −0.5439 V, f0 = 3.371 kHz, ξ = 7.235, zn = −106 rad/s, fzn = 159 kHz, zp = ωzp = 7.60125 × 105 rad/s. fzp = 120.97 kHz, p1 = −1471 rad/s, p2 = −305 krad/s, fp1 = 234.11 Hz, fp2 = 48.542 kHz. 4. Mvo = 4.0191, Mvx = 1, 416.14. 5. Zio = 273.42 Ω, fpZi = 144 Hz. 6. Zoo = 552.74 Ω, Zox = 0.999 Ω, fzrl = 48.635 kHz.

Chapter 17 1. ρSi = 2.26 × 105 Ω · cm, σSi = 4.424 × 10− 6 S/cm. 2. ρSiC = 5.57 × 1023 Ω · cm, σSiC = 0.1795 × 10− 23 S/cm. 3. μp = 500 cm2 /V · s. 4. p = 1.5 × 1016 hole/cm3, ρp = 0.868 Ω · cm, σp = 1.152 ( Ω · cm)− 1, Silicon-to-boron number of atoms = 3.333 × 106, p/n = 1012, ρSi/ρp = 2.604 × 105. 5. ρn = 0.4596 Ω · cm, σn = 2.176 S/cm. 6. xp = 3.2 nm, xn = 320 nm, W = 323.2 nm, xn/xp = 100. 7. xn = 2.72 μm, xp = 27.2 nm, W = 2.7472 μm, xn/xp = 100. 8. xn = 50.7 μm, xp = 0.507 μm, W = 51.207 μm, xn/xp = 100. 9. xn = 87.69 μm, xp = 0.8769 μm, W = 88.56 μm, xn/xp = 100, Em = 135.53 kV/cm. 10. xn = 103.219 μm, xp = 1.03 μm, W = 104.25 μm, xn/xp = 100, Em = 192.5 kV/cm. 11. xn = 33.19 μm, xn = 33.19 nm, W = 33.133 μm, Em = 61.91 kV/cm. 12.

, vD(t) = nVTln [1 + (IF/IS)(1 − exp ( − t/τp)].

13. 14.

. ,

.

15. PRR = 5 W. 16. ts = 9.116 ns. 17. AJ = 0.05 cm2, NDmax = 2.1623 × 1016 cm− 3, Vbi = 3.0074 V, ln = 5.45 μm, CJ0 = 1.0143 nF, Rn = 4.6238 m Ω. 18. AJ = 5 × 10− 6 m2, ND = 2.586 × 1021 m− 3, ln = 5 μm, CJ0 = 743 pF, Em = 177.1 kV/cm, Rn = 27.528 m Ω. 19. VbI = 3.018 V, AJ = 0.0133 cm2, xmax = 10.31 μm, ln = 0.15 μm, xpmax = 0.1031 μm, lp = 0.15 μm, Wmax = 10.441 μm, Em = 19.2 × 106 V/cm, Rn = 0.077 Ω, Rp = 0.0583 Ω, VBD = 2.095 kV, CJ0 = 202.5 pF.

Chapter 18 1. W = 1.6 × 106 μm, n = 105, Ac = 3.6 μm2, CD = 27, 778 cells/mm2, D = 0.4444 m/mm2, U = 0.3556 m/mm2. 2. (a) Cox = 34.53 μF/m2, kp = 2.07 μA/V2. (b) Cox = 345.3 μF/m2, kp = 20.7 μA/V2. (c) Cox = 3.453 n F/mm2, kp = 207 μA/V2. 3. D = 4Wp/(Wp + dpp)2. 4. μn = 100 cm2 /(V · s). 5. (a) μn0(500K) = 264 cm2 /V · s. (b) μn(E) = 24.5 cm2 /V · s. (c) vn = 2.45 × 107 cm/s. 6. WD = 5 μm, WD = 10 μm, WD = 20 μm, WD = 40 μm. 7. NDmax = 2.586 × 1015 cm− 3, NDmax = 1.293 × 1015 cm− 3, NDmax = 6.465 × 1014 cm− 3, NDmax = 3.232 × 1014 cm− 3. 8. VBD = 1297 V, VBD = 129.7 V, VBD = 12.97 V. 9. VBD = 129.7 kV, VBD = 12.97 kV, VBD = 1.297 kV. 10. VBD = 129.74 V, WD(SiC) = 1.179 μm, RDR = 81.77μ Ω. 11. IDsat = 4.9 A, RCh = 0.714 Ω, RCh(sc) = 1.214 Ω, RCh(sc)/RCh = 1.7. 12. Rn = 0.7399 m Ω, RDR = 2.77 m Ω, RDR(cs) = 4.986 m Ω. 13. Cgs = 1157.44 pF. 14. tox = 0.1 μm, Cox = 34.53 nF/cm2, kp = 13.812 μA/V2, (W/L)min = 4.525 × 105, L = 1 μm, W = 0.4525 m, n = 5.656 × 103, Ac = 5.09 μm2, Adie = 6.363 μm2, NDmax(SiC) = 1.2974 × 1016 donors/cm3, ND = 1016 donors/cm3, WD = 12 μm, Wp = 20 μm, dpp = 10 μm, hp = 3 μm, RCh = 20 m Ω, Ra = 50 m Ω, Rn = 16.554 m Ω, RDR = 45.985 m Ω, rDS = 132.539 m Ω. 15. tox = 0.1 μm, Cox = 34.53 nF/cm2, kp = 13.812 μA/V2, (W/L)min = 2 × 105, L = 1 μm, W = 0.2 m, n = 2, 500, Ac = 2.25 μm2, Adie = 2.8125 mm2, NDmax(SiC) = 2.16 × 1016 donors/cm3, ND(SiC) = 2 × 1016 donors/cm3, WD = 8 μm, Wp = 20 μm, dpp = 10 μm, hp = 3 μm, RCh = 42.6 m Ω, Ra = 106.5 m Ω, Rn = 18.72 m Ω, RDR = 27.74 m Ω, rDS = 196.56 m Ω. 16. Cox = 43.16 nF/cm2, kp = 38.844 μA/V2, (W/L)min = 2.5426 × 104, L = 1 μm, W = 25.4 mm, n = 320, Ac = 0.288 μm2, Adie = 0.36 μm2, NDmax(SiC) = 2.5 × 1015 donors/cm3, ND(SiC) = 2 × 1015 donors/cm3, WDmin = 64.47 μm, WD = 65 μm, Wp = 20 μm, dpp = 10 μm, hp = 3 μm,

RCh = 112.5 m Ω, Ra = 297.8 m Ω, Rn = 147.22 m Ω, RDR = 782.68 m Ω, rDS = 1.3672 Ω. 17. TA = 35° C. 18. TA = 138.466° C.

Index Abrupt junction Acceleration (a) Acceptor Acceptor concentration (NA) Active clamping Ambient temperature (TA) Antiparallel diode Apparent power (|S| = IrmsVrms) Aspect ratio (W/L) Asymmetrical junction Atom Audio susceptibility (Mv) Avalanche breakdown voltage (VBD) Average power (P) Averaged circuit model Baliga's figure-of-merit (BFOM) Band gap energy (EG) Bandwidth (BW) Belt margin (BM) Beveled edge Bidirectional converter Bode plots Body diode Boltzmann's constant (k) Boost-buck converter Boost converter

Breakdown electric field (EBD) Breakdown voltage (VBD) Bridge converter Bridge rectifier Buck converter Buck-boost converter Built-in potential (Vbi) Bulk charge carrier mobility (μn, μp) Capacitance (C) Carrier concentration (n, p) Carrier generation (G) Carrier mobility (μ) Carrier recombination (R) Cascade CCM Center-tapped rectifier Channel length (L) Channel-length modulation Characteristic impedance (Zo) Charge-continuity equation Charge control model Charge neutrality Charge transport Chopper Circuit averaging Clamp circuit Closed-loop transfer function CMOS Collisions

Common-mode noise Compensator Complex power (S) Compound semiconductors Concentration (n, p) Conducted noise Conduction band Conduction loss (PC) Conductivity (σ) Conductivity modulation Continuous conduction mode (CCM) Control-to-output voltage transfer function (Tp) Control voltage (VC, vc) Control voltage-to-duty cycle transfer function (Tm) Controller Core reset Corner frequency (f0, fz) Covalent bonding Cross-conduction Crossover frequency ( fc) Current density (J) Current-mode control Current probe Current ripple Current source Current transformer Ćuk converter Cutoff region Czochralski method of crystal growth

Damped frequency ( fd) Damping factor (σ = ξω0) Damping ratio (ξ) DC model DC transfer function (MVDC) DCM Deadbeat control Delay time (td) Depletion layer Depletion region Differential-mode noise Diffusion capacitance (CD) Diffusion current density (Jdiff) Diode Discontinuous conduction mode (DCM) Discrete-time signal Displacement factor (FDA) Distortion factor (FDF) Disturbance Dominant pole Donor Donor concentration (ND) Doping Drain Drift current density (Jdrift) Drift region Drift velocity (vn, vd) Dual converter Duality

Duty cycle (D) Duty ratio (D) Dwell-duty cycle (Dw) Edge termination Effective channel length (Le) Effective electron mass Effective hole mass Efficiency (η) Electric field intensity (E) Electromagnetic compatibility (EMC) Electromagnetic interference (EMI) Electron Electron mass (me) Electron–hole pair (EHP) Electronic ballast Elemental semiconductor EMC standards EMI EMI filter EMI shielding Energy Energy (W) wide band gap (WBG) semiconductors Equivalent series resistance (ESR) Error amplifier Error voltage (VE, ve) Extrinsic semiconductor Far field Feedback control Feedback loop

Feedback network Feedforward gains Filter Figure-of-merit (FOM) Flip-flop Fluorescent lamp Flyback converter Forced response (ilf ) Forward converter Fourier series Freewheeling diode Full-bridge converter Gain margin (GM) Gain-crossover frequency ( fc) Gallium nitride (GaN) Gate Gate-drive power (PG) Gate oxide (SiO2) Gate oxide breakdown voltage (VBD(SiO2)) Gate threshold voltage (Vt) Gauss's law Grading coefficient (n) Half-bridge converter Harmonics Heat conduction Heat convection Heat radiation Heat sink

Heat transfer Hole h-parameters Ideal transformer IGBT Impact ionization Incremental junction capacitance Inductance (L) Inductor Input impedance (Zi) Input-to-output transfer function (Mv) Insertion loss (H) Instability Insulated gate bipolar transistor (IGBT) Integral control Integral double-lead controller Integral-lead controller Integral single-lead controller Interconnection Intrinsic carrier concentration (ni) Intrinsic semiconductor Isolated converter Johnson's figure-of-merit (JFOM) Junction Junction capacitance (CJ) Kinetic energy (Wk ) Laplace

Latch Lattice Leakage inductance (Ll) Light-emitting diode (LED) Line regulation (LNR) Linear law Linear model Linear region Linear voltage regulator Linearization Linearized averaged circuit Load regulation (LLR) Long channel Loop gain (T) Loss Low-pass filter Majority carriers Majority carrier device Majority electron concentration (nn) Majority hole concentration (pp) Magnetic core Magnetic flux density (B) Magnetizing inductance (Lm) Maximum junction operating temperature (TJmax) Mean free path (dc) Metal-oxide-semiconductor field effect transistor (MOSFET) Metal-semiconductor junction Minority carriers Minority electron concentration (np)

Minority hole concentration (pn) Mobility (μ) Mobility degradation coefficient (θ) Model Modulator MOSFET Multiphase converter Multiple-output converter n-type Natural frequency ( f0) Natural response (iln) Near field Negative feedback Noise Nonlinear circuit Nonlinear capacitance Nyquist frequency Nyquist plot Ohmic contact Ohmic region On-resistance (RON, rDS) One-sided junction Op-amp Open-circuit voltage (VOC) Open loop Output impedance (Zo) Output resistance (Ro) Output voltage (VO, vo)

Overshoot (S) Overload protection p-type Padé approximation PCB Peak rectifier Peaking frequency ( fpk ) Perturbation ratio (a) PFC Phase boost (ϕm) Phase control Phase margin (PM) Photodiode Pinch-off region Pole Polycrystalline solids Polyphase converter Polysilicon Power factor (PF) Power factor correction (PFC) Power quality Proper function Proportional controller Proportional-integral controller Pulse-width modulation (PWM) Pulse-width modulator transfer function (Tm) Punch-through breakdown voltage (VBD(PT)) Push-pull converter PWM

Quadratic buck converter Quality factor (Q) Radio interference (RFI) Rational transfer function Real power (P) Rectifier Rectifying contact Recombination Reference voltage source (VR) Regulation Resistivity (ρ) Reverse recovery Reverse saturation current (IS) Richardson's constant (ϕB) RHP Right-half plane (RHP) zero Ringing Ripple Root locus Safety standards Sampling-and-hold (SH) Saturation current (IS) Saturation drift velocity (vsat) Saturation region Sawtooth voltage Schottky barrier diode Second-order filter Semiconductor

Semiconductor device SH Short-circuit current (ISC) Shoot-through Short-channel effect Silicon (Si) Silicon carbide (SiC) Slope (M) Slope compensation Small-signal model SMPS Snubber Solar cell Specific on-resistance (S) SPICE model Square law Stability Stability margin (SM) State-space averaging Step response Stored charge (SC) Stored energy (w) Surface mobility Switching frequency ( fs) Switching loss (Psw) Synchronous rectifier Tapped-inductor converter Temperature (T)-774 THD

Thermal conductivity (kth) Thermal energy Thermal model Thermal motion Thermal resistance (θ) Threshold voltage (Vt) Topology Total harmonic distortion (THD) Transfer function Transformer Transformer model Transient response Turns ratio (n) Two-switch converter Unstable converter Utility line voltage Utility power factor (PF) Valence band Voltage clamp Voltage-mode control Volt-second balance Voltage regulation Wide band gap (WBG) semiconductors z-domain z-transform Zero ZOH Zero-order hold (ZOH)

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