IPC-7352: Generic Guideline for Land Pattern Design 9781638161424

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IPC-7352

2023 - May Generic Guideline for Land Pattern Design

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IPC-7352

Developed by the 1-13 Land Pattern Subcommittee of the 1-10 Printed Board Design Committee of IPC

Users of this publication are encouraged to participate in the development of future revisions. Contact: IPC 3000 Lakeside Drive, Suite 105N Bannockburn, Illinois 60015-1249 Tel 847 615.7100 Fax 847 615.7105 Provided by Accuris No reproduction or networking permitted without license from Accuris

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Generic Guideline for Land Pattern Design

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Acknowledgment Any document involving a complex technology draws material from a vast number of sources across many continents. While the principal members of the 1-13 Land Pattern Subcommittee of the 1-10 Printed Board Design Committee are shown below, it is not possible to include all of those who assisted in the evolution of this standard. To each of them, the members of the IPC extend their gratitude. 1-10 Printed Board Design Committee

1-13 DFX Land Pattern Subcommittee

Technical Liaison of the IPC Board of Directors

Chair: Philip Henault, Raytheon Vice-Chair: Michelle Gleason, Plexus Corporation

Chair: Michelle Gleason, Plexus

Bob Neves Microtek (Changzou) Laboratories

Land Pattern Subcommittee

Constantino Gonzalez ACME Training & Consulting Pietro Vergine Advanced Rework Technology Jesus Castane Arrival Limited Jeff Schake ASM Assembly Systems Timothy Carey Boeing Research & Development Miguel Dominguez Continental Automotive Russell Steiner Casco Products Geok Ang Tan DSO National Laboratories Gary Ferrari EPTAC Corporation Olga Scheglov EPTAC Corporation Francesco di Maio GESTLABS S.r.l Paul Bartholomew HP Inc. Jennie Hwang H-Technologies Group Joe Hughes Hughes Circuits, Inc.

Perla Wehbe I.F. Engineering Thomas Romont IFTEC Michael Creeden Insulectro Lim L Ming Jabil Circuit Inc. Stephen Golemme JITX Inc. Jasbir Bath Koki Solder America Keld Maaloee LEGO Systems A/S Scott Bowles Lockheed Martin Corporation Kyle Johnson Lockheed Martin Missiles & Fire Control Patti LaRochelle Miraco, Inc. Michael Durkan Mentor Graphics Corporation Richard Henry Mentor Graphics Corporation Gyanesh Mathur Nanowear Inc.

Karen McConnell Northrop Grumman Corporation Mahendra Gandhu Northrop Grumman Space Systems Karl Sauter Oracle America, Inc. Thomas Hausherr PCB Libraries Dale Lee Plexus Corporation Michelle Gleason Plexus Corporation James Daggett Raytheon Company Jeff Shubrooks Raytheon Company Lance Brack Raytheon Missile Systems Rainer Taube Taube Electronics GmbH Arnaud Grivon Thales Global Services Jose Olivares Vitesco Technologies

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IPC-7352

Table of Contents 1 SCOPE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.4

Producibility Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.2 TH Mounting Techniques That Impact Land Pattern .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.5

Density Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.2.1

Axial Land Pattern Design .. . . . . . . . . . . . . . . . . . . . 19

1.5

Use of “Lead” .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.2.2

Radial Land Pattern Design .. . . . . . . . . . . . . . . . . . . 19

1.7

Terms and Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . 2

4.2.3

Solder Side Land Pattern. . . . . . . . . . . . . . . . . . . . . . . 19

4.3

Land Pattern Creation. . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.3.1

Courtyard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

4.4

Through-hole Padstacks. . . . . . . . . . . . . . . . . . . . . . . . 19

2

2.2

APPLICABLE DOCUMENTS. . . . . . . . . . . . . . . . . . . . . 3

Joint Industry Guidelines (IPC). . . . . . . . . . . . . . . . . 3

2.5 Joint Electron Device Engineering Council (JEDEC)2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 SURFACE-MOUNT TECHNOLOGY (SMT)

4.4.1.1 Finite Solder Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

DESIGN REQUIREMENTS. . . . . . . . . . . . . . . . . . . . . . . . 3

3.1.1

Component Tolerancing and Dimensioning. . . . . 4

3.1.2

Solving for Dimension Z. . . . . . . . . . . . . . . . . . . . . . . . 7

3.1.3

Land Tolerancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.1.4

Dimension and Tolerance Analysis . . . . . . . . . . . . . 8

3.2

Tolerance and Solder Joint Analysis.. . . . . . . . . . . . 9

3.3

Courtyard Determination . . . . . . . . . . . . . . . . . . . . . . 13

3.4 Land Pattern Naming Convention for SMD Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.4.1

Land Pattern Naming Convention Notes. . . . . . . 16

3.4.2 Naming Convention Special Character Use for Land Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.3

Suffix Naming Convention for Land Patterns .16

3.4.3.1 SON, QFN, SOP and QFP Components That Have Different Thermal Pad Sizes .. . . . . . . . . . . . 16 3.4.3.2 Gull Wing Components That Have Different Lead Tolerances .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4.3.3

4.4.1 Nominal Hole Diameter for Pb vs Pb-free Solder Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Use Of Lead Geometry In Land Pattern Name .17

3.4.3.4. Components With Hidden, Deleted Or Reversed Pins.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4.4 Land Pattern Naming Convention for Unique Packages and Connectors features. . . . . . . . . . . . . 17

4.4.1.2

Infinite Solder Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4.4.3

Thermal Relief . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.4.4

Anti-Pad. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.5

Press-fit (Compliant) Pin Type .. . . . . . . . . . . . . . . . 21

4.6

Through Hole Padstack – Non-Plated. . . . . . . . . . 21

4.6.1

Maximum Terminal Dimension . . . . . . . . . . . . . . . 21

4.6.2

Nominal Hole Diameter. . . . . . . . . . . . . . . . . . . . . . . . 21

4.6.3

Anti-Pad .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

4.7 Land Pattern Naming Convention for PTH Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.7.1 Land Pattern Naming Convention for Unique Packages and Connectors.. . . . . . . . . . . . . . . . . . . . . . 25 5

PADSTACK NAMING CONVENTION . . . . . . 25

5.1

Basic Land Shape Letters . . . . . . . . . . . . . . . . . . . . . . 25

5.2

Padstack Defaults.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

5.2.1 Examples of the Padstack Naming Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.2

Padstack Naming Convention Modifiers . . . . . . 26

5.2.2.1

Use Of Letter v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

5.2.2 .2 Use Of Letter w.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

THROUGH-HOLE MOUNTED DEVICES.. . . . . . . 18

5.2.3 Examples Utilizing Modifiers  The following provide various examples of the padstack naming convention’s usage of modifiers:. . . . . . 27

4.1

Component Type Descriptions .. . . . . . . . . . . . . . . . 18

5.3 Paste Mask for Thermal Tabs. . . . . . . . . . . . . . . . . . . . . . . . . 29

4.1.1

Axial Terminal Components.. . . . . . . . . . . . . . . . . . . 18

4.1.2

Radial Terminal Components . . . . . . . . . . . . . . . . . . 18

4.1.3

Multiple Pin Terminal Components . . . . . . . . . . . 18

4.1.4

Electrical Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . 18

4

6

LAND PATTERN QUALITY VALIDATION.. . . . . . . 29

7

ZERO COMPONENT ORIENTATIONS. . . . . . . . . . 30

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Appendix A (Informative) Test Patterns – Process Evaluations.. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Test Vehicle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

A.2

Test Patterns -In-Process Validator . . . . . . . . . . . . 31

A.3

Stress Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Polarity Marking Legend. . . . . . . . . . . . . . 34 Bottom Only Terminal Packages . . . . . . . . . . . . . . 34

Figure 3-1 Profile Tolerancing Method. . . . . . . . . . . . . . . . . . 4 Figure 3-2 Example of 3216 (1206) Capacitor................5 Figure 3-3 Profile Dimensioning of Gull wing Leaded SOIC.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Appendix B

Figure 3-4 Courtyard Boundary Area Illustration.. . . . . . 13

B.1

Figure 4-1 Horizontally Mounted Radial Leaded Component .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Appendix C Component Package Naming Reference.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 5-1 Basic Land Shapes. . . . . . . . . . . . . . . . . . . . . . . . . . 25

C.1 Area Array Components (BGA, FBGA, CGA, LGA, Chip Array). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure A-1 General Description of Process Validation Contact Pattern and Interconnect.. . . . . . . . . . . 31

Component Lead Packages. . . . . . . . . . . . . . . . . . . . . 35

Figure A-2 Photo image of IPC Test Board for Primary Side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

C.2

C.3 Concave Chip Array Packages (RESCAV, CAPCAV, INDCAV, OSCSC, OSCCCC). . . . . . 35

Figure B-1 Popular Polarity Marking Shapes. . . . . . . . . . . 33

C.4 Convex Chip Array Packages (RESCAXE, RESCAXS). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure B-2 Gull Wing Terminal Legend Polarity Marking Location. . . . . . . . . . . . . . . . . . . . . . . . . . . 33

C.5 Flat Chip Array Packages (RESCAF, CAPCAF, INDCAF. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure B-3 Sample 0.50 mm Pitch SOP Legend and Polarity Marking Rules.. . . . . . . . . . . . . . . . . . . . . 34

C.6 IPC-7359 No-Lead Components (QFN,

Figure B-4 Bottom Only Terminal Packages. . . . . . . . . . . . 34

PQFN, SON, PSON, DFN, LCC) . . . . . . . . . . . . . 36

Figure B-5 Polarized Chip Packages. . . . . . . . . . . . . . . . . . . . 34

C.6.1

Leadless Chip Carrier (LCC). . . . . . . . . . . . . . . . . . . 36

Figure C-1 Side Concave Chip Component. . . . . . . . . . . . . 35

C.6.2

Quad Flat No-Lead (QFN) .. . . . . . . . . . . . . . . . . . . . 37

Figure C-2 Corner Concave Chip Component. . . . . . . . . . 35

C.6.3

Small Outline No-Lead Package (SON).. . . . . . . 37

Figure C-3 Convex Chip Component “E Version”. . . . . . 36

C.6.4 Small Outline and Quad Flat No-Lead with Pullback Leads (PQFN, PSON). . . . . . . . . . . . . . . . 38

Figure C-4 Convex Chip Component “S Version”. . . . . . 36

Dual Flat No-Lead (DFN). . . . . . . . . . . . . . . . . . . . . . 38

Figure C-6 LCC Component. . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

C.6.5

Figure C-5 Flat Chip Component.. . . . . . . . . . . . . . . . . . . . . . . 36 Figure C-7 Quad Flat No-Lead (QFN) Construction.....37 Figure C-8 QFN Devices with Multiple Paste Mask. . . . 37 Figure C-9 Small Outline No-Lead Package (SON). . . . 37 Figure C-10 PQFN Device with Pullback Leads. . . . . . . . . 38 Figure C-12 Axial Component Examples. . . . . . . . . . . . . . . . 39 Figure C-13 Radial Terminal Components. . . . . . . . . . . . . . . 40 Figure C-15 Pin Grid Array (PGA). . . . . . . . . . . . . . . . . . . . . . . 43 Figure C-16 Connectors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

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A.1

Figures

May 2023

IPC-7352 Tables

Table 3-1 Flat Ribbon L and Gull wing Leads. . . . . . . . . . 9 Table 3-2 J Leads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3-3 Rectangular or Square-End Components with Lead Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3-4 Rectangular or Square-End Components with Pin Widths Smaller than 0.5 mm where Leads are 1, 2, 3 or 5 Sided.. . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 3-5 Cylindrical End Cap Terminations (MELF).. 10 Table 3-6 Leadless Components with Concave/ Castellated Terminations. . . . . . . . . . . . . . . . . . . . . 10 Table 3-7 Butt and I Lead. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3-8 Inward Flat Ribbon L-Leads.. . . . . . . . . . . . . . . . . 11 Table 3-9 Flat Lug Leads2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 Table 3-10 Flat No-Lead with Solderable Vertical Surface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3-11 Ball Grid Array Components. . . . . . . . . . . . . . . . . 12

Table 3-12 Flat No-Lead with Pullback or Under Body Leads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3-13 Corner Concave Lead.. . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3-14 Aluminum Electrolytic Capacitor and 2-pin Crystal1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3-15 Small Outline Components, Flat Lead. . . . . . . 13 Table 3-16 Land Pattern Convention for SMD Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 4-1 Finite Solder Flow (Includes Pin-in-Paste and Captive Solder Charge). . . . . . . . . . . . . . . . . . 20 Table 4-2 Infinite Solder Flow (Includes Wave, Solder Pot, Selective Solder, Hand Solder). . . . . . . . . . 20 Table 4-3 Terminal to Finished Hole Size Adjustments for Board Thickness. . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4-4 Pad Size.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 4-5 Nominal Hole Diameter. . . . . . . . . . . . . . . . . . . . . . 22 Table 4-6 Land Pattern Convention for TH Packages. . . 22

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IPC-7352

IPC-7352 Generic Guideline for Land Pattern Design 1 SCOPE

This document provides generic guidelines on land pattern geometries used for the attachment of electronic components to a printed board, as well as design recommendations for achieving the best possible solder joints to the devices assembled. Adjustments to the information in this guideline may be required to meet company and/or board technology requirements. It is recommended that a company should document the modifications to the IPC-7352 content in corporate command media documentation. $&#

A land pattern is the representation of the area and features on a printed board needed for a component to be placed and attached to the printed board during an assembly process. The land pattern is usually built using ECAD Library tools. hole and surface mount land patterns to ensure sufficient area for the appropriate solder fillet to meet the requirements of IPC J-STD-001, and to allow for inspection, testing and rework of those solder joints. Designers can use the information contained herein to establish guideline land pattern geometries not only for manual designs but also for computer-aided design systems. Whether parts are mounted on one or both sides of the printed board and are subjected to wave, reflow, or other type of soldering, the land pattern and part dimensions should be optimized to ensure proper solder joint and inspection criteria.

Land patterns become a part of the printed board circuitry and they are subject to the producibility levels and tolerances associated with fabrication and assembly processes. The producibility aspects also pertain to the use of solder mask and the registration required between the solder mask and the conductor patterns. In addition to the land pattern geometries required for proper solder joint formation, other mounting conditions should be considered, such as solder mask clearance, solder paste stencil aperture sizes, clearance between adjacent components, clearance between the bottom of the component and the printed board surface (if relevant), keep-out areas (if relevant) and adhesive applications. These additional features become part of the overall land pattern guidelines for each component type. Note 1: The dimensions used for component descriptions have been extracted from the documents listed in 2 Applicable Documents. Designers should refer to the manufacturer’s datasheet for specific component package dimensions. Caution: Users should be aware that individual component datasheets may not meet standardized component outlines (e.g., JEDEC standard component outlines). Note 2: Elements of the mounting conditions, particularly the courtyard, given in this guideline are related to the reflow soldering process. Adjustments for wave or other soldering processes, if applicable, should be carried out by the user. This may also be relevant when solder alloys other than eutectic SnPb or SnAgCu solders are used. Note 3: Heat dissipation aspects have not been considered in this guideline. Note 4: In some cases, the lands shown in this guideline may not apply for a particular application and may need to be altered based on the end-item environmental requirements. For surface mount components, the solder joints provide not only the electrical connection, but the mechanical support as well. Note 5: Shock and vibration effects are not considered in this guideline. 1.2 Classification  This guideline identifies the generic physical design principles involved in the creation of land patterns for

surface mount and through-hole components.

1.3 Performance Classification  IPC-J-STD-001 recognizes that electrical and electronic products are subject to classifications by intended end-item use. Three general end-product classes have been established to reflect differences in producibility, complexity, functional performance requirements and verification (i.e., inspection or test) frequency: CLASS 1 General Electronic Products

Includes products suitable for applications where the major requirement is function of the completed assembly. CLASS 2 Dedicated Service Electronic Products

Includes products where continued performance and extended life is required and for which uninterrupted service is desired but not critical. Typically, the end-use environment would not cause failures. Copyright 2023 by IPC International, Inc. All rights reserved.

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1.1 Purpose  The intent of the information presented herein is to provide the appropriate size, shape and tolerance of through-

IPC-7352

May 2023

CLASS 3 High Performance/Harsh Environment Electronic Products

Includes products where continued high performance or performance-on-demand is critical, equipment downtime cannot be tolerated, end-use environment may be uncommonly harsh, and the equipment must function when required, such as life support or other critical systems. 1.4 Producibility Levels  The producibility levels should be in accordance with the IPC-2221 standard. 1.5 Density Levels  Exact details based on vendor component specifications (i.e., datasheet) should be used when defining the land pattern. These land patterns are designed to a specific component and have an identifying IPC-7352 land pattern name.

Equations can be used to alter the given information to achieve the specific design requirement for the solder connection. These equations should be used once the particular design requirements for solder joints are determined (see 3.1.1). Three land pattern geometry variations are supplied for each of the device families: maximum land protrusion (Density Level A), median land protrusion (Density Level B) and minimum land protrusion (Density Level C). Before adapting a specific land pattern variation, the user should consider design requirements and product qualification testing.

Density Level B: Median (Nominal) Land Protrusion – Products with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for reflow solder processes and should provide a condition suitable for wave or reflow soldering of leadless chip and leaded gull wing type devices. Density Level C: Minimum (Least) Land Protrusion – High component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories. The use of performance class (1, 2, or 3) is combined with that of component density level (A, B, or C) in explaining the condition of an electronic printed board assembly. As an example, combining the description as Levels 1A or 3B or 2C, would indicate the different combinations of performance and component density to aid in understanding the environment and the manufacturing requirements of a printed board assembly. Although all three land pattern geometry variations are considered compliant for Pb-free soldering processes, the Density Level C variant will require more processing capability to ensure a proper wetting of the Pb-free alloy. See 3.2.3 for further information on land pattern design in Pb-free soldering environments. 1.5 Use of “Lead”  For readability and translation, this document uses the noun lead only to describe leads of a component. The metallic element lead is always written as Pb. 1.7 Terms and Definitions  Other than those terms listed below, the definitions of terms used in this standard are in accordance

with IPC-T-50.

Note: Any definition denoted with an asterisk (*) is a reprint of the term defined in IPC-T-50. Chip Carrier – A low-profile, square, surface-mount component semiconductor package whose die cavity or die mounting area is a large fraction of the package size and whose external connections are usually on all four sides of the package (it may be leaded or leadless). Courtyard – The smallest area that provides a minimum electrical and mechanical clearance (i.e., courtyard excess) around the combined component body and land pattern boundaries. Courtyard Excess – The area between the outline circumscribing the land pattern and the component, and the outer boundary of the courtyard. The courtyard excess may be different in the x-and y-direction. *Heel Fillet – The solder fillet formed in the land area behind the lead. *Land – A portion of a conductive pattern usually used for the connection and/or attachment of components. Leaded Chip Carrier – A chip carrier whose external connections consist of leads that are around and down the side of the package (see C.6.1). Leadless Chip Carrier – A chip carrier whose external connections consist of metallized terminations that are an integral part of the component body (see C.6.1). 2

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Density Level A: Maximum (Most) Land Protrusion – For low-density product applications, the ‘maximum’ land pattern condition has been developed to accommodate wave or flow solder of leadless chip devices and leaded gull wing devices. The geometry furnished for these devices, as well as inward and (J) formed lead contact device families, may provide a wider process window for reflow solder processes as well.

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Master Drawing – A control document that shows the dimensional limits or grid locations that are applicable to all parts of a product to be fabricated, including the arrangement of conductors and nonconductive patterns or elements; the size, type and location of holes; and all other necessary information. Mixed Component-Mounting Technology – A component mounting technology that uses both through-hole and surfacemounting technologies on the same packaging and interconnecting structure. Packaging and Interconnecting Structure – The general term for a completely processed combination of base materials, supporting planes or constraining cores and interconnection wiring that are used for the purpose of mounting and interconnecting components. *Side Fillet – The solder fillet formed in the land protrusion to either side of the lead or termination. *Toe Fillet – The solder fillet formed in the land protrusion beyond the lead or termination extremities. 2 APPLICABLE DOCUMENTS 2.1 IPC1 IPC-T-50  Terms and Definitions for Interconnecting and Packaging Electronic Circuits IPC-SM-785  Guidelines for Accelerated Reliability Testing of Surface Mount Solder Attachments IPC-2221  Generic Guideline on Printed Board Design IPC-6012  Qualification and Performance Guideline for Rigid Printed Boards IPC-7093  Design and Assembly Process Implementation for Bottom Termination Components IPC-7095  Design and Assembly Process Implementation for BGAs IPC-7525  Stencil Design Guidelines IPC-9701  Performance Test Methods and Qualification Requirements for Surface Mount Solder Attachments IPC-9797  Press-fit Standard for Automotive Requirements and other High-Reliability Applications IPC-D-422  Design Guide for Press Fit Rigid Printed Board Back Planes 2.2 Joint Industry Guidelines (IPC) J-STD-001  Requirements for Soldered Electrical and Electronic Assemblies 2.5 Joint Electron Device Engineering Council (JEDEC)2 Publication 95 JEDEC  Registered and standard Outlines for Solid State Products 3 SURFACE-MOUNT TECHNOLOGY (SMT) DESIGN REQUIREMENTS 3.1 Dimensioning Systems  This section describes a set of dimensional criteria for components and land patterns, as well as

the development of acceptable solder joints commensurate with reliability and compliance to workmanship/inspection requirements and guidelines. Profile tolerances are used in the dimensioning system to define the size range between maximum and minimum component/ lead dimensions without ambiguity. The profile tolerance is intended to control both size and position of the land. Figure 3-1 shows the profile tolerancing method.

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Figure 3-1 Profile Tolerancing Method Key: (A) "N" Places The use of the profile dimensioning system requires an understanding of the concepts. The use of a set of requirements are adopted and invoke the following rules, unless otherwise modified: · All dimensions are basic (i.e., nominal). · Limits of size control form as well as size. · Perfect form is required at minimum or maximum dimensions as applicable. · Datum references and position tolerances apply at maximum dimensions and are dependent on feature size. · Position dimensions originate from maximum dimensions. · Tolerances and their datum references other than size and position apply Regardless of Feature Size (RFS). The dimensioning concepts used for this system of analysis consider the assembly/attachment requirements as their major goal. Specification (i.e., data) sheets for components or dimensions for land patterns on printed boards may use different dimensioning concepts; however, the goal is to combine all concepts into a single system. Users are encouraged to establish the appropriate relationship between their dimensioning system(s) and the profile dimensioning system and analysis concepts described herein to allow for ease of tailoring these concepts for robust process performance. 3.1.1 Component Tolerancing and Dimensioning The component manufacturers and industry standards organizations are responsible for the dimensioning and tolerancing of electronic components. The basic dimensions and tolerance limits published in the specifications have been converted to a functional equivalent using the profile tolerancing method with all components shown with their basic dimensions as limit dimensions (i.e., maximum or minimum size). The concept for component dimension evaluations is based on evaluating the surfaces of the component terminations and component leads or contacts that are involved in the formation of the acceptable solder joint. Component manufacturers provide dimensions for their parts showing either the limits of size (i.e., max/min) or they provide a nominal size and then put a tolerance on that nominal dimension. In order to facilitate the dimensioning system, these dimensions and their associated tolerances are converted to minimum and maximum size. If only a nominal dimension is provided, it is necessary to empirically determine the variation on the dimension in order to establish the appropriate land pattern.

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As an example, a size C3216 capacitor has a manufactured nominal dimension for its length (L) of 3.2 mm. The tolerance described by the manufacturer is ±0.2 mm. Thus, the minimum dimension of L is 3.0 mm with a unilateral tolerance of 0.4 mm, resulting in its maximum dimension being 3.4 mm. Figure 3-2 shows the characteristics for the C3216 capacitors. Item A in Figure 3-2 shows the component manufacturer's dimensions for the length of the capacitor. Item B in Figure 3-2 shows the component length at its minimum size in the converted dimensions of the system using profile tolerancing. Item C in Figure 3-2 shows the land pattern at its maximum size. These conditions provide for an optimum solder fillet per IPC-J-STD-001. Similar concepts are applied to leaded surface mount parts. The critical dimensional characteristics identified are those that relate to the formation of the toe and heel solder fillet. For components with gull wing leads, the basic dimensions apply across the outer extremities of the part for toe land projection, and within the inside of the formed radius of opposing leads for heel solder fillet formation. The outer dimensions of leaded or even leadless chip carriers are usually easy to determine since these are readily available from the component manufacturer or standards organization. The inner (i.e., heel-to-heel) dimensions are rarely provided in industry standards or manufacturer specifications. These dimensions are more difficult to determine, not only because of the form of the lead, termination, or castellation but also because it is necessary to derive the inner dimensions by subtracting the sum of the dimensions of the leads (i.e., with all their inherent tolerances) from the overall dimensions of the part. Itis important that termination spacing not violate minimum electrical clearances.

Figure 3-2 Example of 3216 (1206) Capacitor Dimensioning for Optimum Solder Fillet Condition Key: (A) Manufacturer's dimensions and tolerances (maximum length of par is 3.4 mm). (B) Part shown with length at "least material condition”, and profile tolerance to indicate maximum range of component length at 3.4 mm. (C) Land pattern with dimension Z at "maximum material condition.” Profile tolerance of part (0.2 X 0.2), plus profile tolerance of land pattern (0.05×2) plus placement accuracy (0.1 diameter of true position) are considered in determining the proper dimension for Z, plus the desired toe fillet. item A in Figure 3-3 shows the concept for the manufacturer's dimensions and tolerances for a gull wing Small-Outline Integrated Circuit (SOIC). Item B in Figure 3-3 shows the converted dimensions to be considered in the overall mounting system requirements. (D) Maximum Component Size.

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Figure 3-3 Profile Dimensioning of Gull wing Leaded SOIC Key: (A) and (B) Dimensions per component manufacturer's datasheet for an SOIC with S at Maximum Material Condition (MMC). Note that if S is not provided by the component manufacturer, it may be determined by subtracting terminal dimension (T) from the length (L) per equation 3-1 below. (C) Land pattern dimensions.

Eq. 3-1 S = L = 2T Item C in Figure 3-3 shows the land pattern dimensions. The basic dimensions define the minimum length as measured across the two outer extremities. As component tolerances for L increases, the maximum length and opportunity for the toe fillet is subsequently reduced. Note: The inner dimensions between heel fillets on opposing sides are the most important. Inner dimensions are derived by: · Establishing the maximum outline of the component as measured from lead termination end to lead termination end. The dimension L is provided by the manufacturer. · Establishing the minimum amount of the lead length as measured across the component contact area (i.e., from heel to toe for gull wing leads). The dimension T is provided by the manufacturer. · Subtracting twice the minimum lead length of T from the maximum overall component length of L to arrive at the maximum length inside the leads across the length of the component (i.e., the inner dimension between opposing heel fillets). Including the tolerances on dimensions L and subtracting the maximum dimension of 2·L will yield the minimum dimension between opposing heels. This signifies the worst-case tolerance analysis. · Three sets of tolerances are involved in the analysis described on the overall component, plus the tolerances for the lead on each end. Since not all three tolerances are considered at their worst case, a recommended method for determining the statistical impact is to sum the squares of the tolerances and take the square root of the sum as the Root-Mean-Square (RMS) tolerance difference. For example, Eq. 3-2 RMS Tolerance Accumulation = Eq. 3-2

6

𝐿

= 𝐿

- 𝐿

𝐿

2 𝑇

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Eq. 3-3

𝑇 = 𝑇

- 𝑇

Where: tol= tolerance max = maximum min =minimum As an example, the SOIC with 16 leads has the following limits for the L (i.e., component length) and T (i.e., terminal length) dimensions: 𝐿 = 5.8 mm, 𝐿 = 6.2mm 𝐿

= 6.2 mm - 5.8 mm = 0.4 mm [Eq. 3-2] 𝑇

𝑇

= 0.4 mm, 𝑇

= 1.72 mm

= 1.27 mm - 0.4 mm = 0.87 mm [Eq. 3-3]

Therefore, the calculations for S minimum and maximum dimensions are as follows: 𝑆 = 𝐿 - 2 𝑇 = 5.8 mm- 2 · (1.27 mm) = 3.26 mm [Eq.3-1] 𝑆

= 𝐿

- 2𝑇

= 6.2 mm - 2 · (0.4 mm)

=5.40 mm [Eq.3-1] 𝑆

= 𝑆

- 𝑆

= 5.4 mm - 3.26 mm =2.14 mm

The difference between 𝑆 and 𝑆 is 2.14 mm, which is probably a larger tolerance range than the actual range within which these components are manufactured. This worst-case scenario for the tolerance range for S can also be calculated by adding the tolerances for the component length and the two terminals: 2 𝑇 · 𝑆 (RMS) = 𝐿 =

0.4𝑚𝑚

2 0.87 𝑚𝑚

=1.30 mm [Eq.3-2]

To arrive at a more realistic tolerance range, the RMS value is calculated using the tolerances on the dimensions involved, L and T: 2 𝑇 · 𝑆 (RMS) = 𝐿 =

0.4𝑚𝑚

2 0.87 𝑚𝑚

=1.30 mm [Eq.3-2]

The difference between worse case and the RMS value is 2.14 mm- 1.30 mm = 0.84 mm. This variation is the difference between the two methods for tolerance analysis. To derive a new maximum and minimum dimension for S to determine land patterns, half (i.e., 5.4-0.42=4.98) and half the difference is added to the worse case of this difference is subtracted from the worst case 𝑆 (i.e.,3.26 mm+0.42 mm=3.68 mm). Thus, 4.98 mm to 3.68 mm becomes the variation (i.e., max/min) for the S dimension. 𝑆 dimension is used in the land pattern equations for calculating 𝐺 This technique is used so that a more realistic 𝑆 the minimum land pattern gap between heel fillets). 3.1.2 Solving for Dimension Z equation.

(i.e.,

Dimension Z is the toe (i.e., outside) span of the land pattern and is calculated with the following

Eq.3-4 Z=𝐿 As an example, if 𝐿

+2·𝐽

is found to be 5.80 mm the equation becomes. 𝑍

=5.80mm+2·𝐽

In the above example, the resulting Z value may be rounded.

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3.1.3 Land Tolerancing Profile tolerancing is used for lands in a manner like that of the components. All tolerances for lands are intended to provide a projected land pattern with individual lands at maximum size. Unilateral tolerances are intended to reduce the land size and thus result in a lesser area for solder joint formation. In order to facilitate companion dimension systems, the land pattern is dimensioned across outer and inner extremities. The dimensioning concept in this guideline uses limiting dimensions and geometric tolerancing to describe the allowable maximum and minimum dimensions of the land pattern. When lands are at their maximum size, the result may be a minimum acceptable space between lands. Conversely, when lands are at their minimum size, the result may be a minimum acceptable land pattern necessary to achieve the minimum required land protrusion. These thresholds allow for gauging of the land pattern for go/no-go conditions. The whole concept of the dimensioning system described in this document is based on these principles and extends to component mounting dimensions and land pattern dimensions, etc., so that the requirements may be examined in order to ensure compliance with the tolerance analysis. 3.1.4 Dimension and Tolerance Analysis In analyzing the design of a component/land pattern system, several things come into play, including the size and position tolerances of the component lead or termination and the tolerances of the land pattern. The result is the land area available for a solder joint that provides a proper formation of toe, heel and side fillets. System equations have been developed for chip components and multiple leaded parts. These concepts assume that the target values of parts and land patterns are maximized to reflect solder joint formation (i.e., outer dimensions of components at minimum size with outer dimensions of land patterns at maximum size). Experience shows that the worst-case analysis is not always necessary. This method assumes that all features will not reach their worst case. The equations for determining component land pattern requirements are as follows: Eq.3-5 Z= 𝐿

+2·𝐽

G= 𝑆

+2·𝐽

X= 𝑊

+2·𝐽

Eq.3-6

Eq.3-7

Where: Z is the overall length of land pattern. G is the distance between lands of the pattern. X is the width of land pattern. L is the overall length of component S is the distance between component terminations (for more information on calculating S, see Eq. 3-1). W is the width of the lead or termination. J is the desired dimension of a solder fillet or land protrusion: JT is the land protrusion at toe. JH is the land protrusion at heel JS is the land protrusion at side. The desired solder joint dimensions are added for outer land pattern dimensions and subtracted for inner land pattern dimensions. The result provides the final land pattern dimensions Z, G and X. Refer to Section 7 of IPC J-STD-001 to assess J dimensions. Use Class reliability to determine land area needed for fillets. Pin pitch is a critical dimension when building land patterns for components. To ensure accuracy, the pin pitch of the land pattern should match the accuracy of the manufacture datasheet for the component.

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3.2 Tolerance and Solder Joint Analysis The following tolerance concepts are used to determine the land patterns for electronic components. These concepts are detailed in and reflect the tolerances on the component and the tolerances on the land pattern (i.e., on the interconnecting substrate). Additionally, the usage of oblong, or rounded, land patten pads is considered advantageous for Pb-free soldering processes in comparison with rectangular pads. An exception to this rule occurs when it is necessary that the heel portion of the land pattern be trimmed due to the component body standoff being less than the paste mask stencil thickness or when it is necessary that the heel be trimmed due to "thermal pad" interference. In these two cases, the rectangular pad shape is preferred to compensate for the reduction in Cu area of the land pattern pad length. Note 1: The following tables are guidelines only, and not intended to be absolute requirements. Design requirements and specific components dimensions may result in applying a combination of levels within a single land pattern. For example, a land pattern designed with the intent of using Maximum Level A conditions may have one dimension on the component being reviewed that cannot meet Level A requirements (e.g., the lead pitch is too small to allow side fillet from Level A). It is acceptable to step down or up a level to meet minimum electrical clearance requirements. Note 2: Caution is advised when using the information presented in Table 3-1. Reduced component standoff height (i.e., less than 0.15 mm) and excessive tolerance ranges for the component dimensions may result in an overly robust land pattern where the heel fillet extends under the component body. In such cases, the combination of a large land pattern and a small component seating plane may result in assembly defects. Table 3-1 Hat Ribbon L and Gull Wing Leads Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 )

0.55 mm

0.35 mm

0.15 mm

Heel (𝐽 )

0.45 mm

0.35 mm

0.25 mm

Side (𝐽 )

0.05 mm

0.03 mm

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Note 3: For gull wing components where dimension 𝑆

is less than or equal to 𝐴

use the following heel fillet goals:

· Density Level A-0.25 mm · Density Level B-0.15 mm · Density Level C-0.05 mm Note 4: For components with lead pitch less than 0.4 mm, use a round-off factor to the nearest three decimal places. Note 5: Apply this guideline to all pins on the device that are flat ribbon, L, or gull wing regardless of the number of sides of the device. Note 6: The values for Toe fillet were derived from a 1.27 mm pitch SOIC gull wing. Table 3-2 J Leads Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 ) (to find G dim)

0.10 mm

0.00 mm

0.00 mm

Heel (𝐽 ) (to find Z dim)

0.55 mm

0.35 mm

0.15 mm

Side (𝐽 )

0.05 mm

0.03 m

0.01 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Note 1: Toe and heel fillets are measured from the apex of the J-lead bend and the foot length of the lead is assumed to be zero unless otherwise noted in the datasheet.

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Table 3-3 Rectangular or Square-End Components with Lead Widths Equal to or Larger than 0.5 mm where Leads are 1,2,3 or 5 Sided Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 )

0.55 mm

25% of the nominal height of the component or 0.5 mm whichever is less

0.15 mm

Heel (𝐽 )

0.00 mm

0.00 mm

0.00 mm

Side (𝐽 )

0.05 mm

0.00 mm

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Table 3-4 Rectangular or Square-End Components with Pin Widths Smaller than 0.5 mm where Leads are 1,2,3 or 5 Sided Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 )

100% of the nominal height of the component

50% of the nominal height of the component

25% of the nominal height of the component

Heel (𝐽 )

0.00 mm

0.00 mm

0.00 mm

Side (𝐽 )

0.00 mm

0.00 mm

0.00 mm

Courtyard excess

0.20 mm

0.15 mm

0.10 mm

Round-off factor Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.) Note 1: Round-off factor is for toe fillet calculation only due to size of components referenced here. Table 3-5 Cylindrical End Cap Terminations (MELF) Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 )

100% of the nominal diameter of the component or 1.00 mm whichever is less

0.40 mm

0.20 mm

Heel (𝐽 )

0.20 mm

0.10 mm

0.02 mm

Side (𝐽 )

0.55 mm

0.35 mm

0.15 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.) Note 1: Side fillets are measured from the apex of the rounded lead and the foot width of the lead is assumed to be zero unless otherwise noted in the datasheet. Table 3-6 Leadless Components with Concave/Castellated Terminations Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 ) (to find G dim)

0.25 mm

0.15 mm

0.05 mm

Heel (𝐽 ) (to find Z dim)

50% of the nominal height of the component or 0.65 mm whichever is greater

25% of the nominal height of the component or 0.45 mm whichever is greater

0.45 mm

Side (𝐽 )

0.05 mm

0.00 m

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

10

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

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Table 3-7 Butt and I Lead Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Periphery

1.00 mm

0.80 mm

0.60 mm

Courtyard excess

1.50 mm

0.80 mm

0.20 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Table 3-8 Inward Flat Ribbon L-Leads Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 ) (to find G dim)

0.25 mm

0.15 mm

0.07 mm

Heel (𝐽 ) (to find Z dim)

25% of the nominal height of the component or 0.80 mm whichever is greater

25% of the nominal height of the component or 0.50 mm whichever is greater

0.20 mm

Side (𝐽 )

0.01 mm

0.00 m

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Table 3-9 Flat Lug Leads Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Periphery

0.05 mm

0.03 mm

0.01 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.) Note 1: Courtyard access depends on thermal requirements. Note 2: The guideline refers components with a bottom plane termination

Table 3-10 Flat No-Lead with Solderable Vertical Surface Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 )

120% of the nominal height of the solderable lead

110% of the nominal height of the solderable lead

100% of the nominal height of the solderable lead

Heel (𝐽 )

0.00 mm

0.00 mm

0.00 mm

Side (𝐽 )

0.00 mm

0.00 mm

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Note: This guideline can be applied components with leads on two, three, or four sides.

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Lead Part Periphery Collapsing Ball Periphery Non-Collapsing Ball or Column or Solder Bump Courtyard excess Round-off factor

Table 3-11 Ball Grid Array Components Maximum (Most) Material Median (Nominal) Material Minimum (Least) Material Level A Level B Level C 15% reduction below nominal 20% reduction below nominal 25% reduction below nominal ball diameter ball diameter ball diameter 15% increase above the 10% increase above the 5% increase above the nominal ball or column nominal ball or column nominal diameter diameter ball or column diameter 2.00 mm 100 mm 0.50 mm Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Table 3-12 Flat No-Lead with Pullback or Under Body Leads Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Periphery

0.05 mm

0.00 mm

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Table 3-13 Corner Concave Lead Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Outer Periphery

0.45 mm

0.35 mm

0.35 mm

Inner Periphery

0.10 mm

0.00 mm

0.00 mm

Courtyard excess

0.50 mm

0.25 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Note 1. The edge of the land associated with the outside of the component body. Note 2. The edge of the land under the component body.

Table 3-14 Aluminum Electrolytic Capacitor and 2-pin Crystal Lead Part

Toe (𝐽 )

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Less than 10.0 mm

0.70 mm

0.50 mm

0.30 mm

10.0 or higher

1.00 mm 0.00 mm

0.70 mm 0.00 mm

0.40 mm 0.00 mm

Less than 10.0 mm

0.50 mm

0.40 mm

0.30 mm

10.0 or higher

0.60 mm

0.50 mm

0.40 mm

1.00 mm

0.50 mm

0.25 mm

Heel (𝐽 ) Side (𝐽 )

Courtyard excess Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Note 1: Components included here have leads coming out from the bottom of the body of the part and extend to the edge of the body. Note 2: The dimensions referred to in the Lead Part column are for component height (see IPC-J-STD-001).

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Table 3-15 Small Outline Components, Flat Lead Lead Part

Maximum (Most) Material Level A

Median (Nominal) Material Level B

Minimum (Least) Material Level C

Toe (𝐽 )

0.30 mm

0.20 mm

0.10 mm

Heel (𝐽 )

0.00 mm

0.00 mm

0.00 mm

Side (𝐽 )

0.05 mm

0.00 mm

0.00 mm

Courtyard excess

0.20 mm

0.15 mm

0.10 mm

Round-off factor

Round off to the nearest two place decimal (i.e., 1.01, 1.02, 1.03, etc.)

Caution: It is the responsibility of the user to verify the SMT land patterns used achieve reliable solder joints under all defined operational conditions of the end item product, including testing and ensuring reliability for the product stress conditions. In addition, the size and shape of the proposed land pattern may vary according to the solder mask aperture, the size of the land pattern extension (i.e., dog bone), the via within the extension, or if the via is in the land pattern itself. 3.3 Courtyard Determination The courtyard of any land patten is the smallest area that provides a minimum electrical and mechanical clearance of both the component maximum boundary extremities and/or the land pattern maximum boundary extremities. The intent of the courtyard is to aid the designer in determining the minimum area occupied by the combination of component and land pattern. The information provided in Table 3-1 through Table 3-15 is intended to relate to those excesses that should be added to the maximum dimension to derive the appropriate courtyard condition. As an example, if a component was the major determining factor of the boundary condition, it would have the excess added to the dimensions. The same holds true for a land pattern that has the greater extremities. If either dimension were 14.5 mm, and the excess from Table 3-1 through Table 3-15 indicated an excess of 0.8 mm, the resulting courtyard would theoretically be 16.1 mm. The tables further define a round-up feature. If the round-up were recommended as being to the nearest 0.5 mm, the courtyard would become 16.5 mm. It should be noted that 16.5 mm is a number that, when divided by two to obtain the component centroid, provides two decimal places to the night of the number. It therefore may be appropriate to keep this number in an even approximation such as 16.6 mm. This would provide 8.3 mm to either side of the center of the component to help designers position the component in relation to some grid or placement algorithm.

Figure 3-4 Courtyard Boundary Area Illustration Key: When it is necessary that manufacturing allowances be considered in (A) Courtyard* the design process the courtyard represents the starting point of the (B) Courtyard Boundary * minimum area needed for the component and the land pattern. (C) Extents of Component/Land Pattern Boundary * Manufacturing, assembly and testing representatives should assist in *This drawing is for illustration purposes only and should determining the additional room needed to accommodate not be used for accuracy of elements or scale. placement, testing, modification and repair. This manufacturing allowance is usually dependent on the density and complexity of the product and is not defined in this document. The manufacturing allowance is determined by application and manufacturing process requirements (see Figure 3-3). 3.4 Land Pattern Naming Convention for SMD Packages Note: The component manufacturer's abbreviated name followed by a hyphen can be used as a prefix for the elimination of duplicate land pattern names. When the package tolerances deviate from one manufacturer to the next, the resulting land pattern pad size and courtyard will be different, but the land pattern name will be the same. To discriminate between various manufacturer's package tolerances, we therefore recommend that you use the component manufacturer's abbreviated name followed by a hyphen as the land pattern name prefix. Example: TI-QFN50P350X350X100-19_15T205X205=Texas Instruments QFN for the RHL Case code.

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Table 3-16 Land Pattern Convention for SMD Packages Land Pattern Name

Capacitors, Chip, Array, Concave

BGA+Pin Qty+C or N+Pitch P+Ball Columns X Ball Rows _Body Length X Body Width X Height+ Density Level BGA+Pin Qty+C or N+Col Pitch X Row Pitch P+Ball Columns X Ball Rows 280_Body Length X Body Width X Height+ Density Level BGAS+Pin Qty+C or N+Pitch P+Ball Columns X Ball Rows_Body Length x Body Width X Note: The C or N= Collapsing or Non-collapsing Balls Height + Density Level BGA CAPCAV+Pitch P+Body Length X Body Width X Height -Pin Qty+ Density Level

Capacitors, Chip, Array, Flat

CAPCAF+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Levet

Capacitors, Chip

CAPC+Body Length+ Body Width X Height+ Density Level

Capacitors, Polarized, Chip

CAPPC+Body Length+ Body Width X Height+ Density Level

Capacitors, Dual Flat No-lead

CAPDFN+Body Length+Body Width X Height + Density Level

Capacitors, Polarized, Dual Flat No-lead

CAPPDFN+Body Length+Body Width X Height + Density Level

Capacitors, Molded

CAPM+Body Length+Body Width X Height + Density Level

Capacitors, Polarized, Molded

CAPPM+Body Length+Body Width X Height+ Density Level

Capacitors, Aluminum Electrolytic

CAPAE+Base Body Size X Height+ Density Level

Ceramic Flat Packages

Crystals (2 leads)

CFP127P+Lead Span Nominal X Height -Pin Qty + Density Level CGA+Pin Qty+C+Pitch P+Pin Columns X Pin Rows _Body Length X Body Width X Height +Density Level PCGA+Pin Qty+S+Pitch P+Pin Columns X Pin Rows_Body Length X Body Width X Height+ Density Level XTAL+Body Length X Body Width X Height + Density Level

Crystals, Dual Flat No-lead

XTALDFN +Body Length X Body Width X Height+ Density Level

Crystals, Side Concave

XTALSC+Body Length X Body Width X Height + Density Level

Diodes, Chip

DIOC+Body Length+Body Width X Height + Density Level

Diodes, Dual Flat No-Lead

DIODFN+Body Length X Body Width X Height-Pin Qty + Density Level

Diodes, Molded

DIOM+Body Length+ Body Width X Height+ Density Level

Diodes, Non-polarized Chip

DIONC+Body Length +Body Width X Height + Density Level

Diodes, Non-polarized Molded

DIONM+Body Length +Body Width X Height + Density Level

Diodes, MELF

DIOMELF+Body Length + Body Diameter + Density Level

Diodes, Side Concave, 2 Pin

DIOSC+Body Length X Body Width X Height- Pin Qty + Density Level

Diodes, Side Concave, 4 Pin

DIOSC+ Pitch P+Body Length X Body Width X Height-Pin Qty +Density Level

Ferrite Bead, Chip

BEADC+Body Length + Body Width X Height+ Density Level

Fuses, Chip

FUSC+Body Length+Body Width X Height+ Density Level

Fuses, Dual Fat No-Lead

FUSDFN+Body Length +Body Width X Height+ Density Level

Fuses, Molded

FUSM+Body Length+Body Width X Height+ Density Level

Fuses, Side Concave

FUSSC+Body Length+ Body Width X Height+ Density Level

Inductors, Chip

INDC+Body Length+Body Width X Height + Density Level

Inductors, Chip, Array. Concave

INDCAV+Pitch P+Body Length X Body Width X Height -Pin Qty + Density Level

Inductors, Chip, Array, Rat

INDCAF+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Level

Inductors, Dual Flat No-Lead

INDDFN+Body Length+Body Width X Height+ Density Level

Inductors, Molded

INDM+Body Length+Body Width X Height + Density Level

Inductors, Precision, Molded

INDPM+Body Length + Body Width X Height + Density Level

Inductors, Side Concave

INDSC+Body Length+ Body Width X Height+ Density Level LGA+Pin Qty+C+Pitch P+Pin Columns X Pin Rows _Body Length X Body Width X Height + Density Level

Ball Grid Array's BGA w/Dual Pitch BGA w/Staggered Pins

Column Grid Array, Circular Lead Pilar Column Grid Array

Land Grid Array. Circular Lead

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Land Pattern Name

LED's, Chip

LGA+Pin Qty+S+Pitch P+Pin Columns X Pin Rows_Body Length X Body Width X Height+ Density Level LEDC+Body Length+ Body Width X Height+ Density Level

LED's, Dual Flat No-lead

LEDDFN+Body Length+Body Width X Height+ Density Level

LED's, Molded

LEDM+Body Length+Body Width X Height + Density Level

LED's, Side Concave, 2 Pin

LEDSC+Body Length X Body Width X Height -Pin Qty + Density Level

Land Grid Array. Square Lead

LED's, Side Concave,4 Pin

LEDSC+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Level

Oscillators, Dual Flat No-Lead

OSCDFN+Pitch P+Body Length X Body Width X Height-Pin Qty + Density Level

Oscillators, Side Concave

OSCSC+Pitch P+Body Length X Body Width X Height -Pin Qty + Density Level

Oscillators, Side Flat

OSCSF+Pitch P+Body Length X Body Width X Height- Pin Qty+ Density Level

Oscillators, J-Lead

OSCJ+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Level

Oscillators, L-Bend Lead

OSCL+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Level

Oscillators, Corner Concave

OSCCC+Body Length X Body Width X Height + Density Level

Plastic Leaded Chip Carriers

PLCC+Pitch P+Lead Span L1 X Lead Span L2 Nominal X Height-Pin Qty +Density Level

Plastic Leaded Chip Carrier Sockets Square

PLCCS+Pitch P+Lead Span L1 X Lead Span L2 Nominal X Height-Pin Qty+ Density Level

Quad Flat Packages

QFP+Pitch P+Lead Span L1 X Lead Span L2 Nominal X Height-Pin Qty +Density Level

Ceramic Quad Rat Packages

CQFP+Pitch P+Lead Span L1 X Lead Span L2 Nominal X Height-Pin Qty + Density Level

Quad Flat No-Head

QFN+Pitch P+Body Length X Body Width X Height-Pin Qty+ Thermal Pad+ Density Level

Pull-back Quad Hat No-lead

PQFN+Pitch P+Body Length X Body Width X Height -Pin Qty+ Thermal Pad+ Density Level

Quad Leadless Ceramic Chip Carriers

LCC+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Level

Quad Leadless Ceramic Chip Carriers (Pin 1 on Side) Resistors, Chip Resistors, Chip, Array, Concave Resistors, Chip, Array, Convex, E-Version (Even Pin Size) Resistors, Chip, Array, Convex, S-Version (Side Pins Diff) Resistors, Chip, Array. Flat

LCCS+Pitch P+Body Length X Body Width X Height-Pin Qty +Density Level RESC+Body Length + Body Width X Height + Density Level RESCAV +Pitch P+Body Length X Body Width X Height-Pin Qty + Density Level RESCAXE+Pitch P+Body Length X Body Width X Height- Pin Qty + Density Level RESCAXS+Pitch P+Body Length X Body Width X Height -Pin Qty + Density Level RESCAF+Pitch P+ Body Length X Body Width X Height -Pin Qty + Density Level

Resistors, Dual Flat No-lead

RESDFN+Body Length X Body Width X Height-Pin Qty + Density Level

Resistors, MELF

RESMELF+ Body Length+ Body Diameter + Density Level

Resistors, Molded

RESM+Body Length+Body Width X Height +Density Level

Resistors, Side Concave

RESSC+Body Length + Body Width X Height+ Density Level

Small Outline Diodes, Hat Lead

SODFL+Lead Span Nominal+ Body Width X Height+ Density Level

Small Outline IC, J-Leaded

SOJ+Pitch P+ Lead Span Nominal X Height- Pin Qty +Density Level

Small Outline IC, L-Leaded

SOL+Pitch P+Lead Span Nominal X Height -Pin Qty + Density Level

Small Outline Integrated Circuit, (50 mil Pitch SOIC) Small Outline Packages

SOlC127P+Lead Span Nominal X Height - Pin Qty + Density Level SOP+Pitch P+Lead Span Nominal X Height -Pin Qty + Density Level

Small Outline No-lead

SON+Pitch P+Body Length X Body Width X Height-Pin Qty + Thermal Pad+ Density Level

Thermistors, Chip

THRMC+Body Length +Body Width X Height+ Density Level

Pull—back Small Outline No-lead

PSON+Pitch P+Body Length X Body Width X Height-Pin Qty +Thermal Pad+ Density Level

Small Outline Transistors, Flat Lead

SOTFL+Pitch P+Lead Span Nominal X Height -Pin Qty + Density Level

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Component, Category SOD (Example: SOD3717X135=JEDEC SOD123) SOT143 & SOT343(JEDEC Guideline Package) SOT143 & SOT343 Reverse (JEDEC Guideline Package) SOT23 & SOT223 Package (Example: SOT230P700X180-4) TO (Generic DPAK – Example: TO228P970X238-3)

Land Pattern Name SOD+Lead Span Nominal+ Body Width X Height + Density Level SOT+Pitch P+Lead Span Nominal X Height -Pin Qty + Density Level SOT +Pitch P+Lead Span Nominal X Height-Pin Qty +R+ Density Level SOT+Pitch P+Lead Span Nominal X Height -Pin Qty + Density Level TO+Pitch P+Lead Span X Height - Pin Qty+ Density Level

Transistors, Dual Flat No-lead

TRXDFN+Body Length X Body Width X Height -Pin Qty + Density Level

Varistors, Chip

VARC+Body Length+ Body Width X Height+ Density Level

3.4.1 Land Pattern Naming Convention Notes · All dimensions are in metric units. · All lead span, height, thermal pad / tab and lead dimension numbers go two places past the decimal point and include trailing zeros. · All lead span, body size, thermal pad/tab and lead dimension numbers go to two places before the decimal point and remove leading zeros. · All chip component body sizes are one place to each side of the decimal point. · Pitch values are two places to the right & left of decimal point with no leading zeros but include trailing zeros. 3.4.2 Naming Convention Special Character Use for Land Patterns · The- (underscore) is the separator between pin qty. in hidden & deleted pin components and to append modifiers at the end. · The- (dash) is used to separate the pin qty. · The X (capital letter X) is used instead of the word "by" to separate two numbers such as height X width like "Quad Packages". · The+ (plus sign) combines the adjoining values without separation and is not included in the name. 3.4.3 Suffix Naming Convention for Land Patterns character in every name) are as follows:

Common SMD land pattern to describe environment use (this is the last

· M Most Material Condition (Density Level A) · N Nominal Material Condition (Density Level B) · L Least Material Condition(Density Level C) Note: This excludes the BGA component family as they only come in the nominal environment condition. 3.4.3.1 SON, QFN, SOP and QFP Components That Have Different Thermal Pad Sizes Thermal pad examples for QFN w/ thermal pads: · QFN50P600X600X100-41T365=Thermal pad size is 3.65 mm square. · QFN50P600X600X100-41T365X200= Thermal Pad size is 3.65 mm X 2.00 mm rectangular. 3.4.3.2 Gull Wing Components That Have Different Lead Tolerances Lead tolerance example for gull wing lead sop package: · SOP65P490X110-8L20 =Lead terminal has a 0.20 mm tolerance.

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3.4.3.3 Use Of Lead Geometry In Land Pattern Name Lead dimensions are included to add an additional differentiator to eliminate incompatible duplication. There are three different formulas of suffix based on lead style: · Chip components, where the lead is the entire width of the part:+L lead length (Ex: CAPC3225X280L45N=Lead length is 0.45 mm nominal). · BGA OR CGA:+D diameter (Ex: BGA100C80P10X10_900X900X150D43N=Ball size is 0.43 mm nominal). · All others:+L lead length X lead width (Ex: SOP65P490X110-8L60X24N=Lead Length X Width is 0.60 mm X0.24 mm nominal). This suffix is added before thermal pad (Ex: QFN50P600X600X100-41L40X25T365X200). Packages with multiple different lead geometries are not captured here and are best implemented using naming per 3.4.4. 3.4.3.4. Components With Hidden, Deleted Or Reversed Pins · Reverse pin order (or mirrored part):-20_RN 20 pin part, reverse pin order, nominal environment · Hidden pins: 20_24N 20 pin part in a 24-pin package. The pins are numbered 1-24 the hidden pins are skipped. The schematic symbol displays up to 24 pins. · Deleted Pins:-24_20N 20 pin part in a 24-pin package. The pins are numbered 1-20. The schematic symbol displays 20 pins. 3.4.4 Land Pattern Naming Convention for Unique Packages and Connectors The land pattern naming convention consists of the manufacturing abbreviated name with an underscore and the manufacturer's part number or case code. Many of the component packages today are unique non-guideline packages or unique connectors. These component packages do not fit into a guideline land pattern name due to many unique features. Many component manufacturers are intentionally creating unique component packages and this trend is growing fast. Therefore, in order to have a single land pattern naming convention that covers every component package in the electronics industry, it is necessary that the land pattern name be associated with the component manufacturer and their part number or case code. All special characters used in the part number will be replaced with a hyphen "-", except for periods ".", which will be replaced with an underscore"_". Manufacturer Name Manufacturer Name

Land Pattern Name Manufacturer Name Abbreviation _Manufacturer Case Code or Manufacturer Part Number

Example 1: Examples of Use · If the component package or connector is unique and has a single manufacturer part number, then part number would be used to generate the land pattern name. · If the component is a guideline package and is associated with multiple manufacturer part numbers, then manufacturer case code would be used to generate the land pattern name. Example 2: Sample Land Pattern Names · FOXCONN_JFM38U1A-2PVT-4F · MOLEX_67503-1020 · SAMTEC_QTH-060-01-L-D-A · TI_RKG41 · MAXIM_L1053-H2 · CUI_SJ-3566AN · CK_CRD16CMOSB · ABRACON_ABM11 · AMPHENOL_101-00565-64

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4 THROUGH-HOLE MOUNTED DEVICES The intent of the following information is to indicate the appropriate size, shape and tolerance of through-hole mount land patterns to ensure sufficient area for the appropriate solder fillet to meet the requirements of IPC-J-STD-001, and to allow for inspection, testing and rework of those solder joints where applicable. The concepts have been segmented so that the information is organized by grouping the different component styles with the terminal patterns of the component. For parts mounted on one or both sides of the Printed Board and are subjected to wave, reflow, or other type of soldering; the land pattern and part dimensions should be optimized to ensure proper solder joint and inspection/test criteria based on the configuration of the part, the footprint and what is needed to insure the proper soldered connection. 4.1 Component Type Descriptions 4.1.1 Axial Terminal Components Axial position is defined when terminal leads extend from both ends in the direction of the major longitudinal axis of a cylindrical, elliptical, or elongated box-shaped package (i.e., the terminals emerge from two opposite ends of an elongated component, through the main axis of the package body). Typically, terminal wires are connected to the following package styles, namely: · Longform · Cylinder or can · Disk button But new package styles may include terminal wires in the future. On axial terminal components it is necessary that the terminals be bent with the correct bend radius and the correct distance away from the package body, weld bead, or solder bead to avoid damages to any coating meniscus or bead. Thus, the minimum distance of the holes in the circuit board is calculated from maximum body length plus bead distance and length, plus appropriate bend radius (i.e., when manually inserted). When the axial component is to be inserted via auto-insertion equipment, it is important that this distance be increased to cater for the equipment driver tips that grip the component during the insertion process. In addition, to minimize tooling costs, it is best to then choose from a standard "terminal insertion pitches" that coincide with the insertion tooling. In axial insertion, the board thickness versus maximum body diameter is important since the overall terminal form length is fixed. Taking board thickness into consideration, the maximum body diameters that are insertable with sufficient terminal remaining for the cut and clinch process are shown below. Wire terminals protrude axially from each end of a typically cylindrical or elongated box-shaped component on the geometrical axis of symmetry. Axial-terminal components resemble wire jumpers in shape and can be used to span short distances on a board, or even otherwise unsupported through an open space in point-to-point wiring. These components are available in non-polarized and polarized variations according to their electrical functionality. The polarized type is equipped with a marking for polarity. 4.1.2 Radial Terminal Components Radial terminals project more or less in parallel from the bottom surface or component package, rather than from opposite ends of the package. Originally, radial terminals were defined as following a radius of a cylindrical component (e.g., a ceramic disk capacitor). Over time, this definition was generalized in contrast to axial terminals, and took on its current form. When placed on a board, radial components "stand up" vertically, occupying a smaller footprint on sometimes-scarce "board real estate", making them denser designs. The parallel terminals projecting from a single mounting surface gives radial components an overall "plugin-nature", facilitating their use in high-speed automated component insertion (i.e., "board-stuffing") machines. Like axial terminal components the radial types also are available in non-polarized and polarized variations according to their electrical functionality. The polarized type is equipped with a marking for polarity on the component body. 4.1.3 Multiple Pin Terminal Components These package families start with three terminals and go up to higher pin counts. They are available with different electrical functionalities. The terminals are attached either on the bottom or the side of the component body. In cases where pins are exiting the component body on the side or from the bottom of a radial part to be mounted horizontally, the pins bent according to the bend radius requirements in IPC-J-STD-001. 4.1.4 Electrical Connectors An electrical connector is a package that physically and electrically connects or disconnects two component/printed board/interconnect structures, transferring electrical signals or current.

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Connectors are available in a wide variety of housings and terminal arrangements. when defining the land pattern, ensure that there is sufficient clearance built into the land pattern to enable the mating connector to connect. 4.2 TH Mounting Techniques That Impact Land Pattern Terminal leads, defined in JESD30, can be formed into various shapes according to the method of assembly. 4.2.1 Axial Land Pattern Design When bending the terminal, several rules should be followed to prevent mechanical damage to the package or to the die within the package. Improper bending of the terminals can result in degradation of the electrical characteristics and/or reliability of the device. To place the hole in the land pattern relative to the body of the part for proper bend radius, refer to IPC J-STD-001. The designer should adhere to defined design standards and company media for the selection of grid values used to determine insertion pitch In the case where the calculated pitch falls between two standard grid values, the pitch should be rounded to the next higher grid value. For automated insertion assembly, additional criteria may need to be taken into consideration for calculating the terminal insertion pitch. Most machines have a minimum and maximum terminal span. The designer should check with manufacturing regarding insertion pitch limits. It is also possible to vertically mount axial parts. The designer should adhere to defined design standards and company media for design of insertion pitch span. 4.2.2 Radial Land Pattern Design Radial parts are typically mounted vertically. On some occasions, radial components can be lead formed to allow for horizontal mounting. For this type of mounting, both terminals extend out from the bottom of the package and are then bent downwards to enter the printed board. In this case, the pitch that the terminals exit from the component body is normally retained as the insertion pitch that the terminals enter the printed board (see Figure 4-1). The max distance away from the body that the bend can occur is governed by the shortest terminal length on the part. Figure 4-1 Horizontally Mounted Radial Leaded

Component

4.2.3 Solder Side Land Pattern On the insertion side where the package body is placed, the annular ring around the hole should be circular. For polarized parts ensure that polarity is indicated on the land pattern in Cu and/or legend.

4.3 Land Pattern Creation 4.3.1 Courtyard · Primary Side Should be minimal to allow for brick-walling while maintaining minimum electrical clearance. · Secondary Side Maintain minimum electrical clearances. 4.4 Through-hole Padstacks-Plated As the terminals of all through-hole components consist of round, square or rectangle cross-sections, the hole and annular ring calculations for all types are very similar. 4.4.1 Nominal Hole Diameter for Pb vs Pb-free Solder Process Hole size is calculated from maximum terminal dimensions. The tables below indicate the different soldering processes and the impact of terminal shape and solder alloy have on the hole size design.

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4.4.1.1 Finite Solder Flow Finite Solder Flow is a solder joint that has a predefined amount of solder that will be used to create the joint. This design is less about the surface tension of the solder but more considering how to best utilize the volume of solder provided See Table 4-1 for guidance on pin to hole size determination. Table 4-1 Finite Solder How (Includes Pin-in-Paste and Captive Solder Charge) Board Thickness 1 mm < Th ≥2.35mm Round Terminal

Square Terminal

Rectangular or Rat Terminal

Pb-Free

Terminal Diameter Max +=>

0.15 mm

SnPb

Terminal Diameter Max +=>

0.15 mm

Pb-Free

Terminal Diagonal Max +=>

0.15mm

SnPb

Terminal Diagonal Max +=>

0.15 mm

Pb-Free

Terminal Diagonal Max +=>

0.10 mm

SnPb

Terminal Diagonal Max +=>

0.10 mm

Plated Through Hole Size Tolerance +/- 0.08 mm 4.4.1.2 Infinite Solder Flow Infinite Solder Flow is a process that allows the solder to be drawn from a much larger quantity so utilizing the quantity is not critical. The concern here is about the surface tension on the solder and how to ensure that the proper amount of solder is extracted from the much larger quantity solder bath. See Table 4-2 for guidance on pin to hole size determination. During infinite bath soldering process, board thickness can influence the ability for solder to flow between the component terminal and the barrel of the plated through hole. Table 4-2 Infinite Solder Flow (Includes Wave, Solder Pot, Selective Solder, Hand Solder) Board Thickness 1 mm < Th ≥2.35mm Round Terminal

Square Terminal

Rectangular or Rat Terminal

Pb-Free

Terminal Diameter Max +=>

0.4 mm

SnPb

Terminal Diameter Max +=>

0.4 mm

Pb-Free

Terminal Diagonal Max +=>

0.4mm

SnPb

Terminal Diagonal Max +=>

0.4 mm

Pb-Free

Terminal Diagonal Max +=>

0.35 mm

SnPb

Terminal Diagonal Max +=>

0.35 mm

Plated Through Hole Size Tolerance +/- 0.08 mm The general rule is that as the printed board thickness decreases, the ability of the solder to flow through the printed board increases. This is primarily due to the reduction in thermal mass of the printed board which results in increased ease of preheating the printed board to an elevated temperature before and during the soldering process. For thicker boards, the reverse is true. As the printed board thickness increases, the ability for solder to flow through the printed board decreases. This is primarily due to the increase in thermal mass of the printed board which results in a decreased ability to preheat the mid-plane (i.e., center) of the printed board to an elevated temperature before and during the soldering process. This inability to sufficiently heat the mid-plane can result in decreased solder fluidity or premature solder solidification. Increasing the terminal to hole clearance increases the thermal mass of the solder material in the hole to allow for good solder joint formation.

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To counteract or reduce the influence of board thickness on the terminal to hole clearance, Table 4-3 may be used for guidance for adjusting standard land patterns based on a specific design need. All these recommendations can be influenced by the capability of the infinite solder flow system being utilized by the assembler and should be consulted for their capabilities and clearance recommendations. Table 4-3 Terminal to Finished Hole Size Adjustments for Board Thickness Board Thickness Terminal to Hole Clearance Adjustment Thinner than .8 mm

Decrease standard terminal to hole clearance by up to 0.2 mm

Greater than or equal to .8mm and less than 1.0 mm

Decrease standard terminal to hole clearance by 0.1 mm

Greater than or equal to 1.0mm and less than or equal to 2.35 mm

Standard terminal to hole clearance

Greater than 2.35 mm and less than or equal to 4 mm

Increase standard terminal to hole clearance by 0.1 mm

Greater than 4mm

Increase standard terminal to hole clearance by up to 0.2 mm

Note: Specialty applications may need to deviate from the values listed in Table 4-3. 4.4.2 Pad size Relative to Finished Hole Size based on soldering process.

Pad size can be calculated using Table 4-4. Pad size adjustments can be made Table 4-4 Pad Size

Finished Hole size

Pad size for Pb Solder

Pad size for Pb-Free Solder