Introduction to VHDL: Solutions manual [1st ed.] 978-0-412-81340-5;978-94-011-5838-1

1,262 69 15MB

English Pages IV, 285 [282] Year 1997

Report DMCA / Copyright

DOWNLOAD FILE

Polecaj historie

Introduction to VHDL: Solutions manual [1st ed.]
 978-0-412-81340-5;978-94-011-5838-1

Table of contents :
Front Matter ....Pages i-1
Chapter 4 (R. D. M. Hunter, T. T. Johnson)....Pages 4-11
Chapter 5 (R. D. M. Hunter, T. T. Johnson)....Pages 12-16
Chapter 6 (R. D. M. Hunter, T. T. Johnson)....Pages 19-25
Chapter 7 (R. D. M. Hunter, T. T. Johnson)....Pages 27-30
Chapter 8 (R. D. M. Hunter, T. T. Johnson)....Pages 31-39
Chapter 9 (R. D. M. Hunter, T. T. Johnson)....Pages 41-53
Chapter 10 (R. D. M. Hunter, T. T. Johnson)....Pages 55-66
Chapter 11 (R. D. M. Hunter, T. T. Johnson)....Pages 67-73
Chapter 12 (R. D. M. Hunter, T. T. Johnson)....Pages 75-79
Chapter 13 (R. D. M. Hunter, T. T. Johnson)....Pages 81-86
Chapter 14 (R. D. M. Hunter, T. T. Johnson)....Pages 87-97
Chapter 15 (R. D. M. Hunter, T. T. Johnson)....Pages 99-108
Chapter 16 (R. D. M. Hunter, T. T. Johnson)....Pages 109-285
Errata (R. D. M. Hunter, T. T. Johnson)....Pages 286-287

Citation preview

Introduction to VHDL

Introd uction to

VHDL Solufions manual

R.D.M. Hunter University of Portsmouth, UK

and

T.T. Johnson

Summit Design Inc., USA

1~!11

SPRINGER-SCIENCE+BUSINESS MEDIA, n.Y.

ISBN 978-0-412-81340-5 DOI 10.1007/978-94-011-5838-1

ISBN 978-94-011-5838-1 (eBook)

First edition 1997

© 1997 R.D.M. Hunter and T.T. Johnson Originally published by Chapman & Hall in 1997

Apart from any fair deal ing for the purposes of research or private study, or criticism or review, as permitted under the UK Copyright Designs and Patents Act, 1988, this publication may not be reproduced, stored, or transmitted, in any form or by any means, without the prior permis sion in writing of the publishers, or in the case of reprographic reproduction on1y in accordance with the terms of the licences issued by the Copyright Licensing Agency in the UK, or in accordance with the terms of licences issued by the appropriate Reproduction Rights Organization outside the UK. Enquiries conceming reproduction outside the terms stated here should be sent to the publishers at the London address printed on this page. The publisher makes no representation, express or implied, with regard to the accuracy of the information contained in this book and cannot accept any legal responsibility or liability for anY errors or omissions that may be made. A catalogue record for this book is available from the British Library

Introduction to VHDL

Preface This manual contains solutions to the end-of-chapter exercises for the textbook Introduction to VHDL. It is not claimed that the solutions presented here are, at all times, the best possible, or the only, solutions to the exercises; on occasion alternative solutions are offered. Where possible suitable designs have been synthesised. In a number of such cases the waveforms and schematics have been included, usually in appendices. While it is recognised that Test Benches are becoming an important issue in VHDL design these are considered beyond the scope of this volume. N.B. The solutions to the exercises have been tested using certain proprietary tools. No guarantee is offered that the models contained herein will simulate, or synthesise, correctly on other vendors' tools.

Introduction to VHDL

E.rroto P 76 It should not be inferred from the statement that 'IEEE.Std_Iogic_1164 recognises a signal type composed of 'X', '0', 'I' and 'z' I that these are the only types recognised by this Standard. It should have been made clearer that the subtype X 0 1 Z would be used throughout, for simplicity, in this introductory text. However, the solutions in this manual do use the full nine-valued set where appropriate.

P 135 Line 11: App C should read App B P 136 Line 9: inter_mediate: a and b ; should read intecmediate := a and b ; P 140 Wait statement not properly terminated, should read wat on d, enable until enable = '1' ;

-- semicolon missing

P 146 Architecture statement should read architecture x of y is signal num, sum: integer := 0; -- '=' sign was missing in signal initialisation begin si~example : process; begin wait for 10 ns ; num i ~

t[),

~fY= ~~ II rrt>r -.

:

II' II

~

.

.

~

~

I

~

h[

g

t5c

~,

~ t3J, -

I !I

\i

ffi:

J:::j) _

I

~,

"

3tl

r-t-

t-

,~

:~p2L>.:. '~ ~-

"

tb:

0,

-

...j

,

~~

r),-

tp: j--L./,

-

~

I

I::::=..

[5t~ ~ Ei

, f---l--" t:::iJ: , f---l--"

~e-I

t=b:

r-

t::j;:

-

r-~

I

-

c:: ~

~E=:1 LLJ:

---

I;:t),-

l

Ff:b.

~U :=:i

.~ i=

LY

~,

R-J,

10-9

Introduction to VHDL 10.10.4 Add ASS ERT statements to Ex. 10.10.3 in order to observe activity and define constraints given the following additional ac characteristics for the shift register: Clock to QO or Q7; tphl = 26 ns, tplh = 22 ns. Clear to QO or Q7; tphl = 27 ns. Clock to IIOO - I/O 7 ; tphl = 26 ns, tplh = 17 ns. Clear to 1/00 - I/07; tphl = 26 ns. Output enable time; tpzh = 13 ns, tpzl = 19 ns. Output disable time; tphz = IOns, tplz = IOns. Solution: library IEEE; use IEEE.Std_Iogic_1164.all ; entity \74299\ is port (cp, mr_bar, ds7, dsO, s 1, sO, oel_bar, oe2_bar : in Std_logic ; io : inout Std_logic_vector (7 downto 0) bus :="00000000" ; qO, q7 : out Std_logic ) ; end \74299\ ; architecture behaviour of\74299\ is signal temp: Std_logic_vector (7 downto 0) ; type shift_steer is array (1 downto 0) of Std_Iogic ; begin shift: process (cp, mr_bar) begin if mr_bar = '0' then temp temp temp io null ; end case; end if; end process shift ; i_o : process (temp, oel_bar, oe2_bar, s I, sO) begin if oe I_bar = '0' and oe2_bar = '0' then if (sl & sO) (= "11" then io mode_cnt then mode_cnt := sam(i) ; POSl

:= I;

end if; end loop; ouCput tmp_output := "0011" ; when "00010000" => tmp_output:= "0100" ; when "00100000" => tmp_output := "0101" ; when "01000000" => tmp_output := "0110" ; when "10000000" => tmp_output := "0111" ; when others => tmp_output := "1111" ; 16-7

Introduction to VHDL

end case; return tmp_output ; end seq_encoder; end components ; c) The following solution uses a top_down approach to the problem. It assumes that a package called threshold_package_l exists or will be created (as in this instance). library ieee; use ieee.std_Iogic_1164.all ; use ieee.std_Iogic_1164_extensions.all ; use work.threshold_package_l.all ; entity threshold_detector is port ( sys_rst : in bit; source: in std_ulogic_vector (2 downto 0) ; elk :in bit; th : in std_ulogic_vector (3 downto 0) ; ; result: buffer std_ulogic_vector (7 downto 0) ; td : buffer std_ulogic ; ); end threshold_detector; architecture inside_detector of threshold_detector is component decoder port ( source: in std_ulogic_vector ( 2 downto 0) ; y7, y6, y5, y4, y3, y2 ,yI, yO: out std_ulogic ); end component decoder; component counter port ( y7, y6, y5, y4, y3, y2, yI, yO: in bit; elk: in bit; rst: in bit; c7, c6, c5, c4 ,c3, c2, ct, cO : buffer std_ulogic_vector (3 downto 0) ); end component counter; component comparator port ( sys_rst : in std_ulogic ; th : in std_luogic_vector ( 3 downto 0) ; c7, c6, c5, c4, c3, c2, c1, cO : in std_ulogic_vector (3 downto 0) ; 16-8

Introduction to VHDL

td : buffer std_Iuogic ; rst : out std_ulogic ; result: buffer std_Iuogic_vector (7 downto 0) elk in std_ulogic );

end component comparator; for all: decoder use entity work. decoder ; for all : counter use entity work.counter ; for all: comparator use entity work.comparator; signal y7, y6, y5, y4, y3, y2, yl, yO: std_Iogic; signal c7, c6, c5, c4, c3, c2, el, cO : std_Iogic_vector (3 downto 0) ; signal rst : std_Iogic ; begin instance_decoder: decoder port map (source, y7, y6, y5, y4, y3, y2, yl, yO) ; instance30unter: counter port map (y7, y6, y5, y4, y3, y2, yl, yO, clk, rst, c7,c6,c5,c4,c3,c2,cl,cO); instance30mparator: comparator (sys_rst, th, c7, c6, c5, c4, c3, c2, cl, cO, td, rst, result, elk) ; end inside_detector; -- Counter component library ieee; use ieee.std_Iogic_1164.all ; use ieee.std_Iogic_1164_extensions.all ; use work.threshold_package_l.all ; entity counter is port ( y7, y6, y5, y4, y3, y2, yl, yO, elk, rst: in std_Iogic; c7, c6, c5, c4, c3, c2, el, cO: buffer std_Iogic_vector (3 downto 0) );

end counter; architecture inside30unter of counter is signal cc7, cc6, cc5, cc4, cc3, cc2, cel, ccO : std_Iogic_vector (3 downto 0) ; begin count: process(rst, elk) begin if rst = '0' then c7

~P~j~[l~~11

~

-{>

k.c_buI4t121

"v

klc_b".2[14J

"-

klc_bu•• 81

V

.

)

.J'

-

1635

(') 0

Introduction to VHDL

3

'0

~

'"0 Cl>

'" clQ' ::s

> c::

S 3~

c. 0

::s 'Eo

g

~

iii

2!0

,....

~

-

Ie.

'0

'~ (l

c:r

'