Interconnect Reliability in Advanced Memory Device Packaging 3031267079, 9783031267079

Table of contents :
Preface
Acknowledgements
Contents
About the Authors
1 Advanced Memory and Device Packaging
1.1 Introduction
1.2 Wire Bonding in Memory Packaging
1.3 Technical Challenges with Memory Device Packaging
1.3.1 Key Challenges with Wire Bonding in Memory Packaging
1.4 Evolutions of Interconnects Materials in Memory Packaging
1.4.1 Evolution of Bonding Wires for Memory Packaging
1.4.2 Evolution of Solder Alloys for Memory Packaging
1.5 Evolutions of Polymeric Materials in Memory Packaging
1.5.1 Evolution of Die Attach Film (DAF) for Memory Packaging
1.5.2 Evolution of Non-conductive Film (NCF) for Memory Packaging
1.5.3 Evolution of Encapsulant Materials for Memory Packaging
1.5.4 Evolution of Underfill (UF) for Flip-Chip Memory Packaging
1.6 Memory Packaging Reliability
1.6.1 Package Reliability Tests
1.7 Summary and Recommendations
References
2 Wearout Reliability-Based Characterization in Memory Packaging
2.1 Introduction
2.2 Concept of Reliability
2.3 Key Fatigue Failure Models and Characteristics
2.3.1 Wearout Failure Mechanisms in Memory Packaging
2.4 First Level Interconnect Wearout Reliability
2.4.1 Ball Bond Reliability in Wire Bonding
2.4.2 Bump and Solder Joint Reliability in Flip Chip Packaging
2.5 Wearout Reliability Studies in Memory Packaging
2.5.1 Solder Joint Reliability
2.5.2 Board Level Drop Test
2.5.3 Monotonic Board Level Bending Test
2.5.4 Implications of Monotonic Bending Test for Memory Mobile Applications
2.6 Cyclic Board Level Bending Test on Memory Modules
2.6.1 Criteria and Test Conditions
2.7 Summary and Recommendations
References
3 Recycling of Noble Metals Used in Memory Packaging
3.1 Introduction
3.2 Possibility of Recycling Noble Metals in Packaging
3.3 Key Enablers of Semiconductor Packages with Recycled Materials
3.3.1 Review Methodology
3.4 Recycling and Recovery of Nobel Metals in Semiconductor Assembly
3.4.1 Recycling of Gold in Semiconductor Packaging
3.4.2 Recycling of Cu in Semiconductor Electronics
3.4.3 Recycling of Sn in Semiconductor Electronics
3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor Industry
3.5.1 Recycled Materials Reliability Perspective
3.5.2 Comparison of Materials Cost and Reliability: Recycled Au Wire with Prime Wire
3.5.3 Interconnect Reliability with Recycled Wire in Semiconductor Packaging
3.6 Key Recycling Initiative by Industry Semiconductor Manufacturers
3.6.1 Key Recycling Initiatives
3.7 Summary and Recommendations
References
4 Advanced Flip Chip Packaging
4.1 Introduction
4.2 Flip-Chip Chip Scale Package (FCCSP) Application in Memory Packages
4.3 Process and Reliability Failure Modes in Flip-Chip Memory Packages
4.3.1 Thin Die Warpage Induced Joint Failure
4.3.2 Cu Pillar Bump Abnormality
4.4 Flip Chip Bonding Technology
4.4.1 Mass Reflow
4.4.2 TCB (Thermal Compression Bonding)
4.4.3 Tack, Gang and Collective Bonding
4.4.4 LAB (Laser Assisted Bonding)
4.5 Flip Chip Interconnection Types of Memory Packages
4.5.1 Types of Cu Pillar Bump
4.5.2 Substrate Technology in Flip-Chip Memory Package
4.6 Advanced Heterogeneous Integration for HBM
4.6.1 2.1D Technology
4.6.2 2.3D Technology
4.6.3 2.5D Technology
4.6.4 EMIB Technology
4.6.5 Si Bridge Technology
4.7 Summary and Recommendations
References
5 Second Level Interconnect Reliability of Low Temperature Solder Materials Used in Memory Modules and Solid-State Drives (SSD)
5.1 Introduction
5.2 Second Level Interconnects
5.2.1 Solder Joint Interfacial Reactions (Surface Finish and the Formation of Intermetallic Compounds)
5.3 Shear Strength of Interfacial IMCs
5.3.1 Kirkendall Effects and Formation of Kirkendall Voiding
5.4 Solder Joint Reliability
5.4.1 Requirements for Hand-held Application
5.4.2 Requirements for Computing Application
5.4.3 Automotive Applications
5.5 Low Temperature Solder Paste (LTS)
5.5.1 Why LTS?
5.5.2 Types of LTS
5.5.3 Benefits of LTS in Memory Module Reliability Performances
5.5.4 Interconnect Reliability with Low Temperature Solders
5.6 Factors Influencing Solder Joint Reliability (SJR)
5.6.1 SJR Performances of Memory Modules and SSDs
5.6.2 Factors Impacting Board Level Drop Performance
5.6.3 Construction Analysis and Solder Joint Characterization
5.7 Reliability Requirements on Solid State Drive (SSD) and Memory Modules
5.7.1 Standard Reliability Requirements
5.7.2 Extended Reliability Requirements
5.8 Potential Applications of LTS for Advance Packaging
5.9 Summary and Recommendations
References
6 Specific Packaging Reliability Testing
6.1 Introduction
6.2 Package Strength Characterization of Memory Packages
6.2.1 Methodologies Used for MCP Strength Evaluation
6.2.2 Effect of Material Properties on Package Strength
6.2.3 Effect of Warpage on Package Strength
6.2.4 Effect of Package Construction on Package Strength
6.2.5 Failure Analysis of Package After Bending Break
6.3 Board Level Drop Test: Strain Measurement for Memory Package on Printed Circuit Board
6.4 Chip Package Interaction (CPI) Assessment on Cu Pillar Bump
6.5 Soft Error Rate (SER) and Alpha Emission Rate (AER) in Memory Packages
6.5.1 AER of Package Materials and Characterization Metrologies
6.5.2 Study of Alpha Particle Induced Memory Failure
6.6 Summary and Recommendations
References
7 Reliability Simulation and Modeling in Memory Packaging
7.1 Introduction
7.2 Simulation for Wire Bonding and Stacked-Die Packages
7.2.1 Wire Bonding Interconnection Reliability
7.2.2 Thermal–Mechanical Reliability of Multi-die Stacked Package
7.2.3 Stacked Die Reliability Issue
7.2.4 Three-Point Bending and Four-Point Bending Simulations
7.3 Simulation for Solder Joint Reliability of Memory Package
7.3.1 Plastic Work Accumulation of BGA Package During Thermal Cycling
7.4 Simulation for Flip Chip Memory Packages
7.4.1 The Effect of Cu Pillar Patterns on FCCSP Memory Reliability
7.4.2 Mold Flow Simulation
7.5 Simulation for Stacked-Die Memory with TSV
7.6 Alpha Particle Emission Simulation in Memory Device
7.7 Summary and Recommendations
References
8 Interconnects Reliability for Future Cryogenic Memory Applications
8.1 Introduction
8.2 Why is There a Need of Cryogenic Memory?
8.3 Immersion Cooling Technology
8.4 Module Packaging for Quantum Computing
8.4.1 Module Packaging for High Performance Computing
8.4.2 Key Challenges and Reliability Considerations with S-MCM in Cryogenic Temperature
8.5 New Materials for Cryogenic Memory
8.5.1 Solder Joint Evolutions at Cryogenic Temperature (CT)
8.5.2 Implications of Solder Joint Brittle Fracture and Mechanical Performance in High Performance Computing Applications
8.6 Characterization of Solders at Cryogenic Temperature
8.6.1 Behavior of Solder Alloys and Polymers at Cryogenic Conditions
8.7 Materials/Memory Modules for Quantum Computing
8.8 Reliability Evaluation for Cryogenic Memory Packages
8.9 Recent Progress by Key Industrial Players
8.10 Recent Progress of Industry Initiatives in Cryogenic Memory Computing
8.11 Summary and Recommendations
References
Index

Citation preview

Springer Series in Reliability Engineering

Chong Leong, Gan Chen-Yu, Huang

Interconnect Reliability in Advanced Memory Device Packaging

Springer Series in Reliability Engineering Series Editor Hoang Pham, Department of Industrial and Systems Engineering, Rutgers University, Piscataway, NJ, USA

Today’s modern systems have become increasingly complex to design and build, while the demand for reliability and cost effective development continues. Reliability is one of the most important attributes in all these systems, including aerospace applications, real-time control, medical applications, defense systems, human decision-making, and home-security products. Growing international competition has increased the need for all designers, managers, practitioners, scientists and engineers to ensure a level of reliability of their product before release at the lowest cost. The interest in reliability has been growing in recent years and this trend will continue during the next decade and beyond. The Springer Series in Reliability Engineering publishes books, monographs and edited volumes in important areas of current theoretical research development in reliability and in areas that attempt to bridge the gap between theory and application in areas of interest to practitioners in industry, laboratories, business, and government. Now with 100 volumes! **Indexed in Scopus and EI Compendex** Interested authors should contact the series editor, Hoang Pham, Department of Industrial and Systems Engineering, Rutgers University, Piscataway, NJ 08854, USA. Email: [email protected], or Anthony Doyle, Executive Editor, Springer, London. Email: [email protected].

Chong Leong, Gan · Chen-Yu, Huang

Interconnect Reliability in Advanced Memory Device Packaging

Chong Leong, Gan Package Development Engineering Micron Memory Taiwan Co. Ltd. Taichung, Taiwan

Chen-Yu, Huang Package Development Engineering Micron Memory Taiwan Co. Ltd. Taichung, Taiwan

ISSN 1614-7839 ISSN 2196-999X (electronic) Springer Series in Reliability Engineering ISBN 978-3-031-26707-9 ISBN 978-3-031-26708-6 (eBook) https://doi.org/10.1007/978-3-031-26708-6 © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 This work is subject to copyright. All rights are solely and exclusively licensed by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors, and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Switzerland AG The registered company address is: Gewerbestrasse 11, 6330 Cham, Switzerland

Preface

In view of vast progression of Moore’s law, compounded with the demands of memory storage, especially in mobile products such as smartphones, tablets, and wearables, memory device packaging, gained much attention for the past 10 years. Memory ICs have evolved and get miniaturized in order to meet both consumer and enterprises’ technical requirements in terms of higher speed, capacity, and reliability performances. Advanced memory device packaging and integration use packaging technology to integrate more chips (either side-by-side, stack, or both methods) with different materials and functions, and from different fabless design houses, foundries, wafer sizes, feature sizes, and companies into a system or smaller subsystem. That memory device integration requires careful reliability performance and characterization from materials selections, reliability assessment, packaging studies till long-term interconnect reliability evaluations. In the past 40 years, memory packaging processes have evolved enormously. The noblest one is from few dice to 32- and or 64-die memory packaging as a result of memory capacity expansion with smaller package form factor. In this book, the reliability and technical challenges such as prevailing first-level interconnect materials, packaging processes, advanced specialty reliability testing, and characterization of interconnects will be discussed. The reliability of wire bonding, lead-free solder joints such as reliability testing and data analyses, design of reliability for hybrid and HBM packages, and their failure analyses will be examined. The special features of this book are the materials covering not only for the second-level interconnects, but also for assembly processes on the first-level interconnects, and for the semiconductor back-end on the 2.5D and 3D stacking memories. Thus, this book is extremely useful and applicable for the comprehensive materials reliability in memory device packaging. This book is written so that readers can quickly learn about the basics of problem-solving methods and understand the trade-offs inherent in making memory device packaging decisions. There are eight chapters in this book, namely (Chap. 1 Advanced Memory and Device Packaging; Chap. 2 Wearout Reliability Based Characterization in Memory Packaging; Chap. 3 Recycling of Noble Metals Used in Memory Packaging; Chap. 4 Advanced Flip Chip Packaging; Chap. 5 Second Level Interconnect Reliability of v

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Low Temperature Solder Materials Used in Memory Modules and SSDs; Chap. 6 Specific Packaging Reliability Testing (i.e., 3-point package level bend test, CPI assessment, and Alpha emission measurement); Chap. 7 Reliability Simulation and Modeling in Memory Packaging; Chap. 8 Interconnects Reliability for Future Cryogenic Memory Applications. Chapter 1 simply defines and classifies the overview of technical challenges dealing with advanced memory packaging, especially for wire bonding on stackeddie packaging and in High Bandwidth Memory (HBM) stacking processes. Technical hurdles and some possible solutions will be discussed in this chapter. Typical technical challenges such as thinner substrate and die thickness which deal with hurdles in overall package warpage and die warpage will be addressed. Chapter 2 simply shows the wearout reliability and reliability characterization in advanced memory device packaging. These include the types of wires (Au, Aucoated Ag wire) and possibly on future recycled Au wire for advanced wire bonding technology. Chapter 3 reviews the feasibility and deployments of recycled metals used in semiconductor and memory packaging. Chapter 4 focuses on technical discussion and evolutions of different adaptations of advanced flip chip in FCCSP assembly with pitch downscaling and thin die attaching using mass reflow or thermal compression bonding. Further, the evolution of heterogeneous integration assembled with HBM packages will be discussed. Chapter 5 provides the history of second-level solder joint reliability, and especially to address technical requirements of solder joint reliability intended in both consumer and automotive applications. Solder joint requirements on memory modules (especially with double-sided boards, symmetrical and different varieties of board thicknesses) will be reviewed and compared to conventional technical requirements of solder joint reliability for non-memory modules. Chapter 6 presents an overview of specific reliability testing deployed in memory packaging reliability assessments such as package level 3-point bending for package strength evaluation. Some specific tests developed for the chip package interaction on BEoL integrity are conducted as well. Chapter 7 illustrates the feasibility of performing reliability modeling of different interconnects used in memory packaging. Chapter 8 focuses on reliability requirements and assessment on future interconnect reliability (which is dealing with extreme cold temperature) for cryogenic memory reliability. For whom is this book most likely intended? Undoubtedly, it will be of great value to all those faced with the challenging problems created by the ever-increasing interest in first level and second level interconnect reliability of memory device packaging. For three groups of specialists in particular: (1) those who are active or intend to become active in research and development of memory packaging materials; (2) those who have encountered advanced memory assembly and reliability problems and wish to further understand and learn more methods for solving such problems; and (3) those who have to choose reliable, creative, high-performance, packaging methodology, and interconnect materials for their memory devices. This book will

Preface

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hopefully provide a fundamental base that will aid in stimulating further research and development on thermal or mechanical reliability, materials, processes, manufacturing, for memory packaging. Also, this book can be used as a text for college and graduate students who have the potential to become our future leaders, scientists, and engineers in the electronics and semiconductor industries. We hope that this book will serve as a valuable reference source for all those faced with the challenging problems created by the ever-increasing interest in memory device packaging. I also hope that it will aid in stimulating further research and development on key enabling technologies and more sound applications to heterogeneous integration products. It is our hopes that the information presented in this book may assist in removing roadblocks, avoiding unnecessary false starts, and accelerating design, materials, process, and manufacturing development of key enabling technologies of memory device packaging and its interconnect reliability. Taichung, Taiwan

Chong Leong, Gan Chen-Yu, Huang

Acknowledgements

The overall development and preparation of Interconnect Reliability in Advanced Memory Device Packaging were facilitated by the efforts of a number of dedicated people. I would like to thank them all, with special mention to Mr. Manju of Springer Nature Scientific Publishing Services (P) Ltd., for his unswerving support and advocacy. My special thanks go to Dr. Chen-Yu, Huang (co-author of this book) for solving many problems that arose during the book’s preparation. It has been a great pleasure and fruitful experience to work with all of them in transferring my messy manuscripts into a very attractive printed book. The material in this book clearly has been derived from many sources, including individuals, companies, and organizations, and we have attempted to acknowledge by citations in the appropriate parts of the book and the assistance that I have been given. Also, we would like to thank several professional societies and publishers for permitting me to reproduce some of their illustrations and information in this book, including the Emerald Publishing, the Institute of Electrical and Electronics Engineers (IEEE) conference proceedings (e.g., Electronic Components and Technology Conference and Electronics Packaging and Technology Conference) and transactions (e.g., Components, Packaging, and Manufacturing Technologies), and Springer Nature Publishing. I would like to thank my current employer, Micron Memory Taiwan Co. Ltd., for providing me with excellent working environments that have fulfilled my need for job satisfaction and enhanced my professional reputation. Working abroad in Taiwan is not easy for a foreigner like me. Hence, I would like to thank my landlords, Yu-Pei, Tsai and Bing-Nan, Chang for their relentless help for the past 2 years. I would like to thank my supervisors, Hem Takiar and Arun Malhotra for their inspiring leadership all these years and for guiding me as packaging expertise. Working and socializing with them have been a privilege and an adventure. I learned a lot about life and advanced semiconductor packaging and materials reliability from them. Lastly, I would like to thank my parents, friends, and colleagues: W. W. Cheah, Y. T, Lou, my brothers (Tzung-Hai, Yen, Chong Wuan) and sisters (Cheng Siew, Cheng Geok, Cheng Hong), my daughter Shernice, my sons: Edmond, Brayden and my ix

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wife M. F. Lim for their encouragements, consideration, and patience by allowing me to focus in completing this book. Their simple belief that I am contributing to the electronics industry was a strong motivation for me! Taichung, Taiwan

Chong Leong, Gan

Contents

1 Advanced Memory and Device Packaging . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Wire Bonding in Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Technical Challenges with Memory Device Packaging . . . . . . . . . . 1.3.1 Key Challenges with Wire Bonding in Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Evolutions of Interconnects Materials in Memory Packaging . . . . . 1.4.1 Evolution of Bonding Wires for Memory Packaging . . . . . 1.4.2 Evolution of Solder Alloys for Memory Packaging . . . . . . . 1.5 Evolutions of Polymeric Materials in Memory Packaging . . . . . . . 1.5.1 Evolution of Die Attach Film (DAF) for Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Evolution of Non-conductive Film (NCF) for Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 Evolution of Encapsulant Materials for Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Evolution of Underfill (UF) for Flip-Chip Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Memory Packaging Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 Package Reliability Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Wearout Reliability-Based Characterization in Memory Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Concept of Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Key Fatigue Failure Models and Characteristics . . . . . . . . . . . . . . . . 2.3.1 Wearout Failure Mechanisms in Memory Packaging . . . . . 2.4 First Level Interconnect Wearout Reliability . . . . . . . . . . . . . . . . . . . 2.4.1 Ball Bond Reliability in Wire Bonding . . . . . . . . . . . . . . . . .

1 1 1 3 3 4 4 5 6 6 9 11 12 15 15 16 18 21 21 21 23 23 23 23

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2.4.2 Bump and Solder Joint Reliability in Flip Chip Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Wearout Reliability Studies in Memory Packaging . . . . . . . . . . . . . 2.5.1 Solder Joint Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.2 Board Level Drop Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5.3 Monotonic Board Level Bending Test . . . . . . . . . . . . . . . . . . 2.5.4 Implications of Monotonic Bending Test for Memory Mobile Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.6 Cyclic Board Level Bending Test on Memory Modules . . . . . . . . . 2.6.1 Criteria and Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3 Recycling of Noble Metals Used in Memory Packaging . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Possibility of Recycling Noble Metals in Packaging . . . . . . . . . . . . 3.3 Key Enablers of Semiconductor Packages with Recycled Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3.1 Review Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Recycling and Recovery of Nobel Metals in Semiconductor Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4.1 Recycling of Gold in Semiconductor Packaging . . . . . . . . . 3.4.2 Recycling of Cu in Semiconductor Electronics . . . . . . . . . . 3.4.3 Recycling of Sn in Semiconductor Electronics . . . . . . . . . . 3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor Industry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.1 Recycled Materials Reliability Perspective . . . . . . . . . . . . . . 3.5.2 Comparison of Materials Cost and Reliability: Recycled Au Wire with Prime Wire . . . . . . . . . . . . . . . . . . . . 3.5.3 Interconnect Reliability with Recycled Wire in Semiconductor Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Key Recycling Initiative by Industry Semiconductor Manufacturers . . . . . . . . . . . . . . . . . . . . . . . 3.6.1 Key Recycling Initiatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4 Advanced Flip Chip Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Flip-Chip Chip Scale Package (FCCSP) Application in Memory Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Process and Reliability Failure Modes in Flip-Chip Memory Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3.1 Thin Die Warpage Induced Joint Failure . . . . . . . . . . . . . . . . 4.3.2 Cu Pillar Bump Abnormality . . . . . . . . . . . . . . . . . . . . . . . . . 4.4 Flip Chip Bonding Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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68 68 68 71 73

Contents

4.4.1 Mass Reflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2 TCB (Thermal Compression Bonding) . . . . . . . . . . . . . . . . . 4.4.3 Tack, Gang and Collective Bonding . . . . . . . . . . . . . . . . . . . . 4.4.4 LAB (Laser Assisted Bonding) . . . . . . . . . . . . . . . . . . . . . . . 4.5 Flip Chip Interconnection Types of Memory Packages . . . . . . . . . . 4.5.1 Types of Cu Pillar Bump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.2 Substrate Technology in Flip-Chip Memory Package . . . . . 4.6 Advanced Heterogeneous Integration for HBM . . . . . . . . . . . . . . . . 4.6.1 2.1D Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.2 2.3D Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.3 2.5D Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.4 EMIB Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6.5 Si Bridge Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Second Level Interconnect Reliability of Low Temperature Solder Materials Used in Memory Modules and Solid-State Drives (SSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Second Level Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2.1 Solder Joint Interfacial Reactions (Surface Finish and the Formation of Intermetallic Compounds) . . . . . . . . . 5.3 Shear Strength of Interfacial IMCs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Kirkendall Effects and Formation of Kirkendall Voiding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Solder Joint Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4.1 Requirements for Hand-held Application . . . . . . . . . . . . . . . 5.4.2 Requirements for Computing Application . . . . . . . . . . . . . . 5.4.3 Automotive Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 Low Temperature Solder Paste (LTS) . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.1 Why LTS? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.2 Types of LTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.3 Benefits of LTS in Memory Module Reliability Performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5.4 Interconnect Reliability with Low Temperature Solders . . . 5.6 Factors Influencing Solder Joint Reliability (SJR) . . . . . . . . . . . . . . 5.6.1 SJR Performances of Memory Modules and SSDs . . . . . . . 5.6.2 Factors Impacting Board Level Drop Performance . . . . . . . 5.6.3 Construction Analysis and Solder Joint Characterization . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Reliability Requirements on Solid State Drive (SSD) and Memory Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Standard Reliability Requirements . . . . . . . . . . . . . . . . . . . . . 5.7.2 Extended Reliability Requirements . . . . . . . . . . . . . . . . . . . .

xiii

73 75 77 78 79 79 81 83 83 86 86 87 88 90 91

95 95 95 95 97 98 100 100 101 101 102 102 103 104 104 105 105 108 109 111 111 111

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Contents

5.8 Potential Applications of LTS for Advance Packaging . . . . . . . . . . 111 5.9 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6 Specific Packaging Reliability Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Package Strength Characterization of Memory Packages . . . . . . . . 6.2.1 Methodologies Used for MCP Strength Evaluation . . . . . . . 6.2.2 Effect of Material Properties on Package Strength . . . . . . . 6.2.3 Effect of Warpage on Package Strength . . . . . . . . . . . . . . . . 6.2.4 Effect of Package Construction on Package Strength . . . . . 6.2.5 Failure Analysis of Package After Bending Break . . . . . . . 6.3 Board Level Drop Test: Strain Measurement for Memory Package on Printed Circuit Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.4 Chip Package Interaction (CPI) Assessment on Cu Pillar Bump . . . . . . . . . . . . . . . . . . . . . . . . 6.5 Soft Error Rate (SER) and Alpha Emission Rate (AER) in Memory Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.1 AER of Package Materials and Characterization Metrologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5.2 Study of Alpha Particle Induced Memory Failure . . . . . . . . 6.6 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

119 119 119 120 122 123 126 127

7 Reliability Simulation and Modeling in Memory Packaging . . . . . . . . 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Simulation for Wire Bonding and Stacked-Die Packages . . . . . . . . 7.2.1 Wire Bonding Interconnection Reliability . . . . . . . . . . . . . . 7.2.2 Thermal–Mechanical Reliability of Multi-die Stacked Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Stacked Die Reliability Issue . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.4 Three-Point Bending and Four-Point Bending Simulations . . . . . . . . . . . . . . . . . . . . . . 7.3 Simulation for Solder Joint Reliability of Memory Package . . . . . . 7.3.1 Plastic Work Accumulation of BGA Package During Thermal Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Simulation for Flip Chip Memory Packages . . . . . . . . . . . . . . . . . . . 7.4.1 The Effect of Cu Pillar Patterns on FCCSP Memory Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4.2 Mold Flow Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Simulation for Stacked-Die Memory with TSV . . . . . . . . . . . . . . . . 7.6 Alpha Particle Emission Simulation in Memory Device . . . . . . . . . 7.7 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

153 153 153 154

131 135 139 143 144 144 148

157 158 159 162 162 168 168 171 173 174 180 183

Contents

8 Interconnects Reliability for Future Cryogenic Memory Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.2 Why is There a Need of Cryogenic Memory? . . . . . . . . . . . . . . . . . . 8.3 Immersion Cooling Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.4 Module Packaging for Quantum Computing . . . . . . . . . . . . . . . . . . . 8.4.1 Module Packaging for High Performance Computing . . . . 8.4.2 Key Challenges and Reliability Considerations with S-MCM in Cryogenic Temperature . . . . . . . . . . . . . . . . 8.5 New Materials for Cryogenic Memory . . . . . . . . . . . . . . . . . . . . . . . . 8.5.1 Solder Joint Evolutions at Cryogenic Temperature (CT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.5.2 Implications of Solder Joint Brittle Fracture and Mechanical Performance in High Performance Computing Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.6 Characterization of Solders at Cryogenic Temperature . . . . . . . . . . 8.6.1 Behavior of Solder Alloys and Polymers at Cryogenic Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7 Materials/Memory Modules for Quantum Computing . . . . . . . . . . . 8.8 Reliability Evaluation for Cryogenic Memory Packages . . . . . . . . . 8.9 Recent Progress by Key Industrial Players . . . . . . . . . . . . . . . . . . . . 8.10 Recent Progress of Industry Initiatives in Cryogenic Memory Computing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.11 Summary and Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

xv

185 185 185 187 188 188 188 190 190

192 193 193 195 197 197 200 202 204

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

About the Authors

Chong Leong, Gan, Ph.D., SMIEEE received the B.S. degree in Chemical Engineering from the National University of Malaysia in 2000, M.S. degree in Chemical Instrumentation in 2003 from University Science Malaysia, and Ph.D. in Nanoelectronic Engineering from University Malaysia Perlis, Malaysia in 2015. He is Fellow of Institute of Materials Malaysia, Fellow of Malaysian Institute of Chemistry, and Associate Fellow of ASEAN Academy of Engineering and Technology (AAET). He has been a Quality and Reliability Member of Technical Staff with Altera Corporation, Product Engineering Manager with Osram Opto-Semiconductors, Senior R&D Engineering Manager with Western Digital and currently working as Package Characterization Director with Micron Technology Inc. He has authored more than 60 peer-reviewed papers in international referred journals and conference proceedings on various aspects of LED optoelectronics reliability, nanomaterials, materials chemistry, microelectronic packaging, and reliability engineering. He is a semiconductor packaging expert with a total of 18 patents issued/filed. His current research interests include advanced packaging technologies, electronic materials characterization, copper ball bond reliability, microelectronics reliability, and nanomaterial engineering. He holds senior membership of IEEE and RACI CChem membership and also serving as journal reviewer of various international referred journals such as Journal of Materials Science: Materials in Electronics, Physica Solidi Status (B), IEEE Access, IEEE Transactions on Reliability, IEEE CPMT journal, IEEE TED, PlosOne, Journal of Materials Science, ASME Journal of Electronics Packaging, Nano-and Micro Letters, and Microelectronics International starting 2012. CL has been with more than 15 international journal editorial board members since 2013. Dr. Chen-Yu, Huang, Ph.D. received the B.S. degree in Mechanical Engineering from Chang Gung University in 2004 and completed his M.S. and Ph.D. in the Institute of Mechanical Engineering from Chang Gung University, Taiwan, in 2005 and 2012, respectively. He has over 10 years of R&D experience in the area of advanced packaging and wafer form assembly process integration. He was the 2.5D and Fanout assembly project manager at SPIL Corporate R&D center (merged with ASE) from 2012 to 2019. After that, he moved to the Micron Memory Taiwan Co., Ltd. xvii

xviii

About the Authors

to be a technology development and process integration engineer and focus on 3D memory stacking, and High Bandwidth Memory (HBM) products. He has authored more than 30 journal and conference publications covering warpage, stresses, reliability, failure analysis, and material characterization relative topics in electronic packaging investigation.

Chapter 1

Advanced Memory and Device Packaging

1.1 Introduction Assembly and reliability of memory device packaging are very important topics in semiconductor manufacturing. There are many books and papers written on them. In this chapter, the assembly of memory devices such as prevailing interconnect materials (bonding wires, solder alloys, solder paste), polymeric materials (epoxy molding compound, die attach film and underfill materials), advanced specialty low temperature solders, technical challenges with stacked die packaging and characterization of electronic packaging materials will be discussed. The reliability of lead-free solder joints such as reliability testing and data analyses, design for reliability, and failure analyses of lead-free solder joints will be discussed in this chapter. Evolution of these key assembly materials will be discussed in terms of its technical challenges and enabling reasoning as well as possible failure modes and mechanisms to address the needs and callouts for identifying those key materials characteristics which are critical to memory stacked die packaging. At the end of this chapter, summary and key recommendation of future works have been provided for better clarity and reference purposes.

1.2 Wire Bonding in Memory Packaging Memory device packaging requires numerous assembly processing steps and one of the key electrical interconnections rely on wire bonding (first level interconnect) after die attaching and stacking [1]. Various types of bonding wires could be selected as interconnect materials depending on its cost, target package reliability and looping profiles. Au wire is softer and beneficial towards better low looping requirements for high stacked die packaging such as 16 die and 32 die in advance memory device © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6_1

1

2

1 Advanced Memory and Device Packaging

Fig. 1.1 Bonding wire and applications in memory device packaging

packaging. Au coated Ag wire could be the alternate option of Au wire however it needs further recipe optimization to resolve some workability issues such as shorttailing issue. There are some market driven initiatives to explore recycled Au wire, but this is mainly to address environmental and sustainability concerns. Recycled Au wire needs more engineering studies in terms of its first ball bond intermetallic compound (IMC) formation, high temperature storage life (HTSL) performance and biased highly accelerated temperature and humidity stress test (bHAST) reliability characterization. Initial key challenges included uniform free air-ball formation with recycled Au wire in memory packaging. Figure 1.1 reveals relative package reliability performance (Temperature cycling and high temperature storage life) comparing different bonding wires. Cu wire is not an ultimate bonding wire solution in semiconductor packaging. Cu wire bonding is more suitable to be deployed in low pin-count semiconductor packaging, Radio-frequency (RF) device packaging, flash memory packaging or high-power devices or Micro-electromechanical system (MEMS) which utilize larger diameter of bonding wire with lower input–output (IO) counts. The various considerations such as its long term extended reliability performance and bond pad cratering challenges still pose a key challenge for full sweep of copper wire bonding in semiconductor packaging. Undeniably, the improved N2 kit (which is installed on wire bonder) will improve the wire bonding process with an inert environment since Cu wire is vulnerable to corrosion and oxidation in the production floor. Recently, some researchers investigated Ag wire (either bare Ag or Ag wire coated with Palladium) which will be the next candidate of wire alloy to replace conventional Au and Cu wire bonding.

1.3 Technical Challenges with Memory Device Packaging

3

1.3 Technical Challenges with Memory Device Packaging There are few key technical challenges identified in memory stacked die bonding includes low looping profile which enables more die stacking, tighter control of wire angle for various bond pad to substrate lead fingers bonding and orientations, bonding onto die with longer overhang (limited by die size and pad designs) and optimized first ball bond force and bonding time to ensure uniform AuAl IMC formation at different die counts (as indicated in Fig. 1.2). In order to accommodate higher memory capacity within a same form factor of DRAM and NAND device packaging, complicated high and low wire looping, bonding at longer overhang die and stitch bond landing angle are among those key challenges in memory packaging. Thinner wire diameter (such as ~ 0.60 mils) still the mainstream however bonding over non-planar contact and different looping are the key hurdles to be overcome.

1.3.1 Key Challenges with Wire Bonding in Memory Packaging Key technical barriers for different first interconnects in semiconductor packaging as tabulated in Table 1.1. It encompasses the key issues and corresponds with industrial know-how and technical solutions.

Fig. 1.2 Key technical challenges identified in stacked-die wire bonding memory package

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1 Advanced Memory and Device Packaging

Table 1.1 Technical challenges, materials issues, and solutions of different bonding wires Type of ball-bond Key process, materials reliability, and IMC issues

Industrial counter measures and technical solutions

References

Au

Kirkendall micro-voiding at HTSL long duration (exceeding 1500 h)

Use doped Au wire to mitigate [2–4] faster Au atomic diffusion into Al bondpad

Ag

Short tailing occurrence during Optimized ~ 10% lower wire bonding process step second bond force

Au

AuAl intermetallic oxidation if left unmolded and exposed to 175 °C HTST test for long duration

Use plasma cleaning and [3, 7] tighter control of staging time (< 48 h) from Wire bonding to molding step

Ag

Lower pressure cooker test reliability with bare Ag wire

Doped with ~ 2% Pd content [8] in Ag alloy. The lifetime in PCT increased with increasing Pd concentration in the Ag wire: Ag-3%Pd wire > Ag-1%Pd wire > Ag wire

Au

Sagging wire and leaning wires defect in stacked die wire bonding

Copper has higher stiffness than gold, leading to better looping control and less wire sagging for fine pitch and ultra-fine pitch wire bonding

[5, 6]

[9–13]

1.4 Evolutions of Interconnects Materials in Memory Packaging 1.4.1 Evolution of Bonding Wires for Memory Packaging Evolutions of bonding wires used for the past 25 years can be summarized in Table 1.2. Au wire is introduced in the early 1980s and still exists till current due to its noble in nature. Copper (Cu) wire starts to emerge in the mid of 1990s but was not deployed in large-scale manufacturing due to its vulnerability to wire corrosion and oxidation properties. There are different Cu wire alloys been introduced since 2010s such as Pd-coated Cu wire, Pd-doped Cu wire and bare Cu wire depends on its applications and humidity reliability performance. Silver (Ag) wire has emerged since 2010s and widely introduced on chip-scale packages (CSP) and light-emitting diode (LED) semiconductor packaging. Future engineering works should be focused on material science and failure mechanisms of first interconnect materials used in memory device packaging. In general, Cu wire is considered as one option, but not a final bonding wire solution in electronic packaging. Cu wire bonding had been applied in high temperature application, low pin-count semiconductor packaging, RF device packaging, flash memory packaging, high-power devices or Micro-electromechanical system (MEMS) which utilize larger diameter of bonding wire with lower IO counts.

1.4 Evolutions of Interconnects Materials in Memory Packaging Table 1.2 Technical applications of different bonding wires

5

Bonding wire

Applications

References

Au wire (with dopants)

ICs, RF, LED, FPGA, memory packaging

[15]

Recycled Au wire

ICs, RF, LED, FPGA, memory packaging

Under evaluation/research stage

Bare Cu wire

ICs, RF, FPGA

[16, 17]

Pd-coated Cu wire

ICs, RF, FPGA

[12]

Pd-doped Cu wire

ASICs, FPGA

[14]

Au-coated Ag wire

PCDRAM, raw NAND

Under product qualification

The various considerations such as its long term extended reliability performance, easy-tended oxidization in air, failure analysis difficulty due to oxidation pretreatment, sensitive process window and bond pad cratering challenges still pose a showstopper for full sweep of copper wire bonding in semiconductor packaging. For the purpose to enhance Cu wire process capability, the forming gas mixture of 95% N2 and 5% H2 had been implemented in wire bonder to improve the wire bonding process. The other wire bonding solution using Ag wire (either bare Ag or Ag wire coated with Palladium) is also investigated recently and which will be the potential candidate of wire alloy to replace conventional Au and Cu wire bonding. Ag wire requires minor process parameter tweaking and similar bonding parameters to Au wire bonding. Ag wire bonding shows higher Pressure Cooker Test (PCT) reliability results with increasing doping of Pd percentage in bare Ag wire. Bare Ag or Pd-coated Ag wire will be one of the next options of wire alloy for semiconductor packaging, but it needs further reliability assessment, electrical characterization and AgAl IMC studies. However, Au wire bonding is the preferably packaging option by industry in lower pin count microelectronics packaging while Cu wire bonding is adopted for higher IO counts due to cost constraint such as Field Programmable Gate Array (FPGA) packaging. Ag wire bonding was recently investigated and some LED manufacturers started to deploy Ag wire bonding in LED semiconductor packaging. There is not a clear bonding wire deployment based on market segments at this moment as Au wire bonding will be kept as backup of Cu wire bonding in high volume manufacturing.

1.4.2 Evolution of Solder Alloys for Memory Packaging In recent years, lead-free solders have been becoming the consensus of electronic industry due to the strategy of environmental protection. Among various groups of

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1 Advanced Memory and Device Packaging

lead-free solders, Sn–Ag–Cu (SAC) ternary alloys with relatively suitable mechanical and physical properties show the highest acceptability [18]. Regarding reliability qualification of different applications, typical SAC105, SAC305, and SAC405 are facing reliability challenge under particular test conditions and test intervals, especially in temperature cycling and mechanical shock. Shnawah et al. [19] reported that SAC405 and SAC305 solder give good temperature cycling reliability which is desirable for high temperature electronic devices used in Aerospace, Military, and Automotive industry. However, SAC405 and SAC305 solder give poor drop shock performance, which is not preferable for portable and handheld electronic devices, such as cameras and cell phones [19]. Therefore, minor elements are doped in conventional SAC alloys to adjust material properties and enhance the performance of reliability. The effects of additions are summarized in Table 1.3. Table 1.4 tabulates overall technical requirements of solder alloys used in memory packaging. Solder alloys (typically doped with Bismuth (Bi) content) have higher performance in temperature cycling. This is reflected in its hardness and tensile strength properties. However, handheld application demands for improved mobile drop shock performance to address end customers’ application and it could be achieved with high Ag added. More robust and predictable Cux Sny intermetallic compound formation with NiAu surface finish compared to Cu-OSP finish. Most recent callout by end customers mainly on lower assembly processing temperature hence lower temperature solder alloy has been introduced by suppliers. It is mainly achieved by enabling surface mounting of Pb free solder alloys with low temperature solder paste (LTS) [31]. LTS is identified as solder paste (with doping of 30–50% of Bi) and it could reduce the reflow temperature tremendously. Other than environmental sustainability, lower reflow peak temperature will impose better package warpage and control hence improving its solder joint reliability margin.

1.5 Evolutions of Polymeric Materials in Memory Packaging 1.5.1 Evolution of Die Attach Film (DAF) for Memory Packaging With the miniaturization in advance memory packaging, technical requirements of die attach film (DAF) have been gone through several evolution in terms of DAF thickness, viscosity, adhesion strength and gap fill ability. There are two main classes of DAF in this case namely DAF and Film over Wire (FOW). FOW is mainly deployed as an alternative of micro-controller die packaging instead of flip chip microcontrollers (in hybrid memory packaging whereby stacked NAND or DRAM die above micro-controller die. Overall technical requirements of DAF are outlined in Table 1.5. Figure 1.3 illustrates typical applications of DAF and FOW in a typical stacked ide memory package.

1.5 Evolutions of Polymeric Materials in Memory Packaging

7

Table 1.3 Requirements and key roles of doped elements of major Pb free solder alloys used in memory packaging Doped element

Characteristics

References

Ag

It gives good cyclic thermal properties (> 3 wt.%)

[18]

It increases solder cost

[18]

It decreases wettability

[18]

It strengthens bulk solder from Ag3Sn dispersion strengthening mechanism

[20]

It affects Sn dendrites in bulk solder microstructure

[21]

It increases 29% electrical resistivity of Sn-0.7Cu (from 0 to 3.5 wt.%)

[22]

It affects the formation of IMC types and shapes on Ni substrate

[23]

It increases interfacial IMC growth rate on Cu substrate

[24]

It strengthens bulk solder from dispersion strengthening mechanism

[25]

Cu

Ni

It depresses the melting temperature of Sn-Ag-based solders

[25]

It decreases the degree of undercooling and refines microstructure

[18]

It changes interfacial reaction layer from Cu6Sn5 to (Cu, Ni)6Sn5 It inhibits Cu dissolution It increases melting temperature and melting range It improves the drop strength of low-Ag SAC alloys on Cu pads It suppresses the growth of the brittle Cu3Sn IMC layer Bi

It reduces solder cost

[18]

It increases around 5% spreading ratio of SAC257 (from 0 to 5 wt.%) It decreases the melting temperature of SAC257 (from 0 to 5 wt.%) It increases around 30% tensile strength of SAC257 (from 0 to 1 wt.%) It increases around 38% elongation of SAC257 (from 0 to 1 wt.%) It improves creep and fatigue properties It increases brittleness and is prone to thermal fatigue in 4.5 < wt.% It increases the solidification range 3 < wt.% It decreases the degree of undercooling and refines the microstructure The strong strengthening effect was attributed to a solid-solution hardening mechanism (continued)

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1 Advanced Memory and Device Packaging

Table 1.3 (continued) Doped element

Characteristics

References

Sb

It improves mechanical properties

[18]

It increases the melting temperature slightly

[18]

It slightly reduces thermal and electrical conductivity

[18]

It is considered toxic (listed on the EACEM list of not-to-be-used substances)

[18]

It forms IMC Cu6 (Sn, Sb)5 and Ag3 (Sn, Sb) in microstructure

[18]

It refines interfacial IMC grain

[26]

It precipitates small particles in the solder matrix with the increase of Sb

[26]

It increases oxides and corrodes readily

[18]

Zn

It requires strong fluxes It generally decreases wettability It facilitates formation of IMC (Cu, Zn)6Sn5 in the reaction layer at the interface Ti

It decreases the degree of undercooling

[18]

It forms Ti2Sn3 IMC which is hard and stiff It increases mechanical strength in low weight percentages (1 > wt.%) It suppresses void formation and coalescence at the Cu/Cu3Sn interface Fe

Co

Ce

It decreases electrical resistivity (when Fe = 0.1 wt.%) while increasing electrical resistivity (when Fe = 0.3 and 0.5 wt.%)

[22]

It decreases the growth rate of IMC Cu3Sn (when Fe = 0.03 wt.%)

[27]

It decreases the growth rate of IMC Cu3Sn (when Co = 0.03 wt.%)

[27]

It forms (Cu, Ni, Co)6Sn5 and (Ni, Cu, Co)3Sn4 at the interface of solder/Ni substrate

[28]

It improves wettability

[29]

It increases the melting temperature slightly

[29]

It improves tensile strength

[29]

It decreases interfacial IMC growth

[30]

It facilitates the formation of Ag3Sn and improves the strength [30] of joints In

It is very expensive and scarce

[18]

It decreases melting temperature

[18]

It improves wettability

[18] (continued)

1.5 Evolutions of Polymeric Materials in Memory Packaging

9

Table 1.3 (continued) Doped element

Characteristics

References

It renders high ductility and low strength in the case of high In-containing solder alloys

[18]

It accelerates oxidation during melting

[18]

It increases tensile strength while decreasing ductility (when In [25] = 2 atomic % and 5 atomic %)

Table 1.4 Technical requirements and roadmaps solder alloys used in memory packaging Technical requirements

Specifications

Technical considerations

Hardness (Hv)

21–31

For solder joint reliability performance especially in automotive memory applications

Melting point (°C)—Pb free solder alloys

205–220

Suitable solder alloys melting point and liquidus temperature for enabling efficient reflow processing

Tensile strength (MPa)

∼ 90

For solder joint reliability performance especially in automotive memory applications

Elongation (%)

25–40

For better package drop and board level drop performances especially for handheld application

Lower temperature for better reflow ability

Typically, 130–150 °C

For low carbon emission and environmental sustainability purposes

In summary, key technical challenges of DAF or FOW including material requirements in enabling higher stacked die packaging while maintaining its assembly yield by mitigating occurrences of DAF micro voiding, DAF delamination, longer overhang wire bonding, zero electrostatic discharge (ESD) events during wafer separation and mold ingression. Micron invented a semiconductor device (as depicted in Fig. 1.4) which has Silicon flow controllers configured to reduce mitigation of mold materials between stacked die layers [32].

1.5.2 Evolution of Non-conductive Film (NCF) for Memory Packaging Non-Conductive Film (NCF) is widely used in recently advanced High Band-width Memory (HBM) device packaging. Evolution of memory packaging from conventional CuSn in Through Silicon Via (TSV) of memory cube in HBM packaging requires NCF material with thinner die to fulfill HBM2 or higher memory packaging roadmaps. Key technical challenge of NCF film requires voids-free after die gangbonding or multiple reflow cycles in HBM packaging. This is associated with thinner

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1 Advanced Memory and Device Packaging

Table 1.5 Technical requirements and roadmaps of DAF and FOW for stacked die memory packaging Technical requirements

Specifications

Technical considerations

Thickness

10 µm to < 5 µm

For thinner memory package on handheld application

Wafer adhesion strength

4 MPa to > 6 MPa

Main die stacks flatness during die bond and reduce occurrence of die warpage and delamination. Also, this will reduce mold ingression phenomenon

Gap fill-ability within a narrow space

Good to excellence

Mitigate die delamination and die warpage

Wafer separation

6 mm to < 5 mm

Enabler for wafer separation and workability

Thermal loading and buffet

Good to excellence

Enable higher die stacking processes (up to 32 die stacking) without DAF void or delamination

Thermal conductivity

3.0 W/mK

For better thermal management as a results of higher stacked die packaging (up to 32 die stacking)

Anti-ESD and surface resistance

1015 Ω to < 1011 Ω

Mitigation of ESD events and yield issue

Fig. 1.3 Application of DAF and FOW in advanced memory stacked die with wire bonding

1.5 Evolutions of Polymeric Materials in Memory Packaging

11

Fig. 1.4 Application of silicon spacer under tunnel to mitigate mold ingression phenomenon in memory stacked die packaging [32]

NCF, thickness variations, suitable NCF viscosity, thermal loading and curing profiles of NCF selected, lower CTE (to reduce CTE mismatches with silicon die), higher thermal conductivity (> 3.0 W/mK), and low halogen content. Thermal management of HBM memory cube is indeed required to over-come overheating especially with high speed and signal integrity. Table 1.6 tabu-lates overall materials characteristics of NCF used in HBM memory packaging. There are several associated assembly defects with HBM memory packaging, such as NCF voiding, through-silicon-via (TSV) shorts and causing leakages, NCF delamination and bulging which induces electrical opens post package reliability tests especially temperature cycling and biased HAST test. Low halogen content is another critical-to-packaging indicator of NCF material as it is a known source of corrosive element and needs to be controlled in NCF material.

1.5.3 Evolution of Encapsulant Materials for Memory Packaging There are three main types of encapsulants used in memory packaging namely: epoxy molding compound (EMC), molded underfill (MUF) and underfill materials (UF). Key functions of these encapsulants are to protect the active integrated circuitry from environment exposures and corrosions. Memory device packaging requires higher EMC materials properties especially in customized LPDRAM and managed NAND packaging (lower package warpage), die microcracking mitigation and better EMC adhesion to solder resists, die surface and polyimides. Thermal management is another key challenge to memory packaging, but it could be mitigated by deployment of high thermal conductivity molding compound, higher Cu balancing of substrate materials. Soft-error rate of memory device could be in control by utilizing low alpha emissivity and usually it is < 0.01 cph/cm2 . This is critical for memory devices

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1 Advanced Memory and Device Packaging

Table 1.6 Technical requirements and roadmaps of NCF characteristics for stacked die memory packaging Technical requirements

Specifications

Technical considerations

Thickness

15 µm to < 10 µm

For thinner memory packaging especially in High Bandwidth Memory (HBM) packaging

Better control of thickness variations

< ± 0.8 µm

Main die stacks flatness during die bond and reduce occurrence of HBM stacked and delamination

Gap fill-ability within a narrow space

Good to excellence

Mitigate NCF micro-voiding and prevent active pillar bumps shorting

Low viscosity

< 2000 Pa.S

Mitigate NCF micro-voiding and optimum processing time

Lower coefficient of thermal expansion (CTE)

< 40 ppm/°C

Match and fitted to Silicon wafer CTE

Thermal conductivity

3.0 W/mK or more

For better thermal management because of higher HBM die packaging

Low chloride ion Cl−content

< 5 ppm

Better moisture reliability and corrosion resistance

and prevent bit-flips occurrences especially with high memory capacity packages. Semiconductor radiation reliability draws more attention lately with higher memory scaling. Table 1.7 tabulates a few key materials characteristics of EMC used in memory device packaging.

1.5.4 Evolution of Underfill (UF) for Flip-Chip Memory Packaging Underfill material (UF) is primarily used as stress buffering and supporting material in semiconductor packaging. With the recent miniaturization and smaller scaling of bump pitch (from ~ 80 µm to < 50 µm), selection of suitable underfill material is crucial to ensure its thermos-mechanical and moisture reliability especially in hybrid packaging in memory devices. There are several key considerations to be given on UF materials selection. These desired characteristics including: smaller silica filler size and filler content, appropriate coefficient of thermal expansion (CTE) which is falling into 20–30 ppm/°C) compatible with substrate (15–25 ppm/°C) and solder bumps (~ 30 ppm/°C), lower viscosity and high flowability (to optimise underfilling throughput and assembly capacity), low creeping rate and good keep-out-zone (KOZ) control, high adhesion strength to Cu substrate traces and low alpha emission rate (typically < 0.001 cph/cm2 ). Interaction of UF material with assembly parameters

1.5 Evolutions of Polymeric Materials in Memory Packaging

13

Table 1.7 Technical requirements and roadmaps of EMC characteristics for stacked die memory packaging Technical requirements

Specifications

Justifications

Top filler cut size

55 µm to < 20 µm

For thinner memory packaging especially in Memory packaging

Mold clearance

3.50 W/mK or more

For better thermal management because of higher memory die packaging

Low chloride ion Cl−content

3.50 W/mK or more

For better thermal management because of underneath micro-controller die being underfilled

Low chloride ion Cl- content

= 1500 cycles Board level drop test, 1.0 mm single sided board, 1500 g 0.5 ms ½ sine pulse, Z-axis, end after 63.2% cumulative failures, >= 10 drops

To meet second level solder joint reliability based on assembled package and board system

Solder ball off pad, connectors For better package drop and damage, lid open board level drop performances especially for handheld application

2.5 Wearout Reliability Studies in Memory Packaging

33

Fig. 2.5 Representative of board level temperature cycling test performed on FOCSP package with variation of different UBM and Cu stud design rules

to ball size, die layout and placement as well as Cu trace routing greatly affecting solder joint reliability of assembled memory packages onto PCB boards.

2.5.2 Board Level Drop Test Board level drop test was widely implemented for solder joint reliability in assembly industry, solder joint was monitored by daisy chain design and real time electrical resistant monitoring to estimate joint life since solder joint failures is the major concern in tradition [37, 38]. Similarly, there are various package design factors (as shown in Table 2.5) affecting board level drop performance of mounted memory packages onto PCB test coupons. Board level drop performance heavily depending on hardness and materials ductility of solder alloy used and PCB pad design. It is well-known that memory die or encapsulation will survive if package strain is less than the maximum package strain which is generated during drop event. Another factor of increasing drop performance includes thickness of PCB, in which thicker PCB will give higher board level drop performance since lesser bounced bending strain induced by thicker PCB during drop event [39–42]. Since package is bent during drop test, a package level bending test is set up and gating criteria can be defined with reason by a pre-drop test with a strain rosette measurement to obtain maximum package strain to save time and cost consuming

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2 Wearout Reliability-Based Characterization in Memory Packaging

Table 2.4 Technical factors influencing board level temperature cycling performance and its associated specifications and considerations Technical requirements

Specifications

Technical considerations

Substrate thickness

Minimum 200 µm

Thicker substrates impose more protections on solder joints

Type of solder alloy

Bi-doped solder alloy (harder) Harder solder alloys provide than non-Bi-doped solder alloy higher resistance towards (softer) thermal expansion and contraction of solder joints under hot and cold temperature cycling Lower Bi additions (1 and 1.5%) alloys showed significantly worse TC than that of higher Bi additions (3 and 4%) alloys. SnAgNi-3% Bi-0.05% Sb gives better temperature cycling performance [34, 35]

Ratio of solder resist opening (SRO): ball size

Increase of ~ 10 to 20%

Provide higher solder joint reliability margin and higher performances

Effects of reflow profile (reflow TAL > 90s, optimised reflow peak temperature, time above peak temperature liquidus—TAL)

TAL 90s profile have better TCT reliability margin compared to effects of lower peak temperature of 250 °C [36]

Die layout, die size, spacer die location

Optimised die stacking, layout of die placement within a memory package

Application of Spacer die will minimize package warpage at high temperature region and improve solder joint reliability margin

Underfilling of components

With and without underfilling

Enable higher die stacking processes (up to 32 die stacking) without DAF void or delamination

EMC materials properties (CTE)

Typically, = 150 µm

Larger mold clearance will create larger distance from top die of a stacked die within a memory package and produces higher package strength

Substrate thickness

>= 150 µm

Minimum substrate thickness which gives larger package strength and strain margin during package bend testing

Loading span of bending test

Range of 3–9 mm (depending on 3-point or 4-point bending methodology)

Different bend loading span will influence on its final package strength and strain values

PCB thickness

1.0 mm against 2.36 mm

The thicker the PCB thickness will give higher package strain margin

Solder alloy type

Bi-doped solder alloy (harder) Harder solder alloys protect than non-Bi-doped solder alloy component mounted onto PCB (softer) boards and mitigate bending

Lower coefficient of thermal expansion (CTE) of EMC

= 5000 µe on 3-point monotonic package level bending test

For assessment of package level strain experienced by end mobile users due to extensive long hours of sittings and different body postures

Board level monotonic bending test [47]

Load rate: 4.33 mm/s Load/support span: 80 mm/100 mm Board type: 0.6 mm single sided board

Suitable for one-off board level bending for with and without underfilled components onto PCB boards

Board level drop and strain measurement [48]

Not clearly defined acceptance criteria

To assess package bending strain experienced onto package level which is mounted onto PCB and gone through board level drop testing

package qualification test and is not meant to replace any product level test that may be needed to qualify a specific product and assembly. There are two types of continuous resistance monitored board level cyclic bend tests and mainly depend on different loading span and radius (as shown in Table 2.8) [49, 50]. Not many customers utilize the spherical board level bending as this is mainly targeted to investigate strain limits of board level device interconnects under spherical bending conditions, worst-case flexure conditions that could occur during printed circuits board assembly, manufacturing, and test operations (more for SMT process induced SMT defects).

2.7 Summary and Recommendations List of key wearout reliability failure modes (for wire bonded, flip chip packaging) at first and second level interconnect have been covered in this chapter. Key critical factors influencing board level temperature cycling, board level drop and bending performances have been discussed as well. Some important results and recommendations are summarized as follows. . Wearout reliability assessment should have been deployed to package level reliability stresses as well as board level reliability for overall packaging margin analysis and useful lifetime prediction. Standard JEDEC level reliability acceptance test is useful for qualification and minimum passing criteria for reliability monitor. Accurate reliability prediction is required based on physics of failures [2].

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2 Wearout Reliability-Based Characterization in Memory Packaging

Table 2.8 Additional two specifical board level bending tests (cyclic bending and spherical bending) and their implications to end users Reliability test item

Implications to end-user experience

References

Cyclic board level bending test

Continuous 4-point bending displacement board level bending which provides t63.2% cumulative failure lifetime which is more representative of end user phone bending experience due to different body sitting postures

[51]

Spherical board level bending test

Continuous spherical bending displacement [52] board level bending which provides t63.2% cumulative failure lifetime which covers strain limits of board level device interconnects under spherical bending conditions, worst-case flexure conditions that could occur during printed and circuits board assembly, manufacturing, and test operations

. Electromigration (1st level solder bump) could be mitigated through decreasing pad opening size and bump height (80 µm against 65 µm). EM performance of Cu Pillar is superior to SnPb, high Pb, and SnAg bumps [24]. This is primarily due to thick Cu Pillar which tends to minimize the current crowding effect at the solder joint level. . Electromigration (2nd level solder joint) could be improved through addition of In (< 1 wt.%) in Pb free solder alloys [28], addition of Ni nanoparticles [29], doped with low % of Indium (In), adding Ni and Ge to the solder alloys [32], and deployment of copper-cored solder ball (CCSB) [31]. . In summary, solder joint reliability deals a lot with CTE mismatching between EMC, substrate and silicon stacked die and second level interconnect such as solder alloy. Best known deployment of Bi-doped solder alloy (solute solution strengthening) [34, 35], higher crack resistance substrate core materials and suitable CTE values of EMC with regards to substrate and PCB favors in enhancing lifetime of board level temperature cycling. . Board level drop performance [54] heavily depending on hardness and materials ductility of solder alloy used and PCB pad design. It is well-known that memory die or encapsulation will survive if package strain is less than the maximum package strain which is generated during drop event. Another factor of increasing drop performance includes thickness of PCB, in which thicker PCB will give higher board level drop performance since lesser bounced bending strain induced by thicker PCB during drop event. . The optimum flexural modulus of EMC used will ease its flexibility during package bending test while larger mold clearance will create a larger distance from top die of a stacked die within a memory package and produces higher package strength [43, 44]. Crack resistant or shock toughness of substrate core

References

.

.

. .

.

41

materials used will resist bending strain and produce higher package level bending margin. Package level strain acquisition [37, 45] could be served as assembled package level bending strain measurement which is meaningful to assess package level strain experienced by end mobile users due to extensive long hours of sittings and different body postures. Board level monotonic bending test is targeted to investigate one-off board level bending for with and without underfilled components onto PCB boards while board level drop and strain measurement is more on bending strain experienced onto package level which is mounted onto PCB and gone through board level drop testing. There are two types of continuous resistance monitored board level cyclic bend tests and mainly depend on different loading span and radius (as shown in Table 2.8) [51, 52, 54]. Not many customers utilize the spherical board level bending as this is mainly targeted to investigate strain limits of board level device interconnects under spherical bending conditions, worst-case flexure conditions that could occur during printed and circuits board assembly, manufacturing, and test operations (more for SMT process induced SMT defects). Bi-doped solder alloy has been identified and widely adopted due to its higher hardness and solder joint reliability performances [59]. Technical considerations should have given to focus on evaluate and determine suitable EMC and UF materials used in memory packaging to minimize package warpage, better SJR performance and address adhesion strength in view of tighter die gap spacing and narrower pitches in flip chip packaging. Deployment of hybrid modeling (AI model and mechanical modeling) will provide optimum reflow profile and enhance solder joint reliability [60]. Memory packages must meet minimum package reliability requirements as laid out in AEC Q104 and JEDEC standards [4, 53–57] prior release to high volume manufacturing.

References 1. McPherson JW (2018) Brief history of JEDEC qualification standards for silicon technology and their applicability to WBG semiconductors. In Proceedings of IEEE international reliability physics symposium (IRPS), 2018, pp 3B.1–1–3B.1–8 2. Thaduri A, Verma AK, Gopika V, Gopinath R, Kumar U (2013) Reliability prediction of semiconductor devices using modified physics of failure approach. Int J Syst Assur Eng Manage 4:33–47 3. Hoang P (2003) Handbook of reliability engineering. Springer, London 4. IPC-9701A IPC/JEDEC Standard (2002) Performance test methods and qualification requirements for surface mount solder attachments 5. Zou YS, Gan CL, Chung MH, Takiar H (2021) A review of interconnect materials used in emerging memory device packaging: first- and second-level interconnect materials. J Mater Sci Mater Electron 32:27133–27147 6. Gan CL, Classe F, Chan BL, Hashim U (2014) Future and technical considerations of gold wirebonding in semiconductor packaging—a technical review. Microelectronic Int 31:121–128

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7. Gan CL, Hashim U (2015) Evolutions of bonding wires used in semiconductor electronics: perspective over 25 years. J Mater Sci Mater Electron 26:4412–4424 8. Gan CL, Francis C, Chan BL, Hashim U (2013) Extended reliability of gold and copper ball bonds in microelectronic packaging. Gold Bulletin 46:103–115 9. Breach CD (2010) What is the future of bonding wire? Will copper entirely replace gold? Gold Bulletin 43:150–168 10. Breach CD, Wulff F (2006) Oxidation of Au4 Al in un-moulded gold ballbonds after high temperature storage (HTS) in air at 175 °C. Microelectron Reliab 46:2112–2121 11. Breach CD, Lee TK (2012) Shear strength and failure modes of as-bonded gold and copper ball bonds on aluminum metallization. J Electron Mater 41:2018–2028 12. Chauhan P, Zhong ZW, Pecht M (2013) Copper wire bonding concerns and best practices. J Electron Mater 42:2415–2434 13. Gan CL, Classe FC, Chan BL, Hashim U (2014) Effects of bonding wires and epoxy molding compound on gold and copper ball bonds intermetallic growth kinetics in electronic packaging. J Electron Mater 43:1017–1025 14. Gan CL, Ng EK, Chan BL, Kwuanjai T, Jakarin S, Hashim U (2012) Wearout reliability study of Cu and Au wires used in flash memory fine line BGA package. In: Proceedings of technical papers—international microsystems, packaging, assembly, and circuits technology conference, IMPACT, pp 232–235 15. Gan CL, Classe FC, Chan BL, Hashim U (2014) Evolution and investigation of copper and gold ball bonds in extended reliability stressing. Gold Bulletin 47:141–151 16. Gan CL, Hashim U (2014) Influence of shear strength on long term biased humidity reliability of Cu ball bonds. J Mater Sci Mater Electron 25:4786–4792 17. Gan CL, Ng EK, Chan BL, Hashim U (2012) Reliability challenges of Cu wire deployment in flash memory packaging. In: Proceedings of technical papers—international microsystems, packaging, assembly, and circuits technology conference, IMPACT 2012, pp 236–239 18. Gan CL, Classe F, Hashim U (2013) Superior performance and reliability of copper wire ball bonding in laminate substrate-based ball grid array. Microelectron Int 30:169–175 19. Tan CM, He FF (2013) Electromigration modeling at circuit layout level. Springer Nature, Singapore 20. Harman G (1999) Wirebonding in microelectronic: materials. McGraw Hill, Processes, Reliability and Yield, New York, pp 135–155 21. Kim G, Son K, Lee JH et al (2022) Size effect on the electromigration characteristics of flip chip Pb-free solder bumps. Electron Mater Lett 22. Ha SS, Kim JW, Yoon JW (2009) Electromigration behavior in Sn-37Pb and Sn-3.0Ag-0.5Cu flip-chip solder joints under high current density. J Electron Mater 38:70–77 23. Chen MY, Liang YC, Chen C (2016) Electromigration in reduced-height solder joints with Cu pillars. J Mater Sci: Mater Electron 27:3715–3722 24. Syed A, Dhandapani K, Nicholls L, Moody R, Berry CJ, Darveaux R (2010) Flip chip bump electromigration reliability: a comparison of Cu Pillar, High Pb, SnAg, and SnPb bump structures. In proceedings of international microelectronics assembly and packaging society conference (IMAPS 2010), Vol 2, pp 1222–1249 25. Wang F, Zhou L, Zhang Z, Wang J, Wang X, Wu M (2017) Effect of Sn-Ag-Cu on the improvement of electromigration behavior in Sn-58Bi solder joint. J Electron Mater 46:6204–6213 26. Seo SK, Kang SK, Cho MG, Lee HM (2010) Electromigration performance of Pb-free solder joints in terms of solder composition and joining path. J Mater 62:22–29 27. Ma L, Xu G, Sun J, Guo F, Wang X (2011) Effects of Co additions on electromigration behaviors in Sn-3.0 Ag-0.5 Cu-based solder joint. J Mater Sci 46:4896–4905 28. Kelly MB, Antoniswamy A, Mahajan R, Chawla N (2021) Effect of trace addition of in on Sn-Cu solder joint microstructure under electromigration. J Electron Mater 50:893–902 29. Bashir MN, Haseeb ASMA, Rahman AZMS, Fazal MA, Kao CR (2015) Reduction of electromigration damage in SAC305 solder joints by adding Ni nanoparticles through flux doping. J Mater Sci 50:6748–6756

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30. Li X, Liu Z, Li C, Guo YX, Wang D, Sun F, Fan R (2021) Effects of trace elements Ag, Bi and Ni on solid-liquid electromigration interface diffusion in solder joints. J Electron Mater 50:5312–5317 31. Jeong H, Lee CJ, Kim JH, Son J, Jung SB (2020) Electromigration behavior of Cu Core solder joints under high current density. Electron Mater Lett 16:513–519 32. Zhao X, Saka M, Yamashita M (2012) The effect of adding Ni and Ge microelements on the electromigration resistance of low-Ag based SnAgCu solder. Microsyst Technol 18:2077–2084 33. Lau JH, Lee NC (2020) Assembly and reliability of lead-free solder joints. Springer Nature, New York 34. Zou YS, Chung MH, Gan CL, Hsu YT, Takiar H (2021) Effects of Sb and Bi addition on IMC morphology and reliability of Pb-free solder/Cu-OSP. In: 2021 IEEE 23rd electronics packaging technology conference EPTC 2021, pp 419–422 35. Zou YS, Chung MH, Tennant T, Gan CL, Hsu YT, Takiar H (2020) Investigation of shear strength and temperature cycling performance of Bi-doped Sn-Ag-Cu solder joints. In: 2020 IEEE 22nd electronics packaging technology conference EPTC 2020, pp 286–290 36. Moideen MZ, Gan CL (2016) Solder joint reliability enhancement through surface mounting solder joint reflow optimization in enterprise grade solid state drives (SSDs). In: Proceedings of the IEEE/CPMT international electronics manufacturing technology (IEMT) symposium, pp 1–4 37. Chen CM, Gan CL, Zou YS, Chung MH, Takiar H (2020) Strain response of a semiconductor package during drop test and fast gating method by bend test. In: 2020 IEEE 22nd electronics packaging technology conference EPTC 2020, pp 49–52 38. Liu Z, Fang M, Shi L, Chen Z, Li J, Long H, Zhu W (2022) Numerical and experimental analyses of component failure risk in a mobile phone under drop test. IEEE Trans Compon Packag Manuf Technol 12:69–79 39. Ong YC, Shim VPW, Chai TC, Lim CT (2003) Comparison of mechanical response of PCBs subjected to product-level and board-level drop impact tests. In: Proceedings of 5th IEEE electronic packaging technology conference EPTC 2003, pp 223–227 40. Xiaohu Y, Zerui F, Miaomiao Y, Xiaoqing Z, Zhiqiang L, Qiang H (2010) Research on reliability of board level package-on-package in drop test. In: Proceedings of 11th international conference of electronic packaging technology high density packaging ICEPT-HDP 2010, pp 1138–1141 41. Jiang DS, Tzeng YL, Wang YP, Hsiao CS (2006) Board level drop test and simulation of CSP for handheld application. In: Proceedings of 7th international conference of electronic packaging technology high density packaging ICEPT-HDP, pp 7–10 42. Lim CT, Low YJ (2002) Investigating the drop impact of portable electronic products. In: IEEE proceedings of electronic components technology conference, pp 1270–1274 43. Che FX, Ong YC, Ng HW, Gan CL, Glancey C, Takiar H (2020) Study on package strength of uMCP (multichip package) for mobile application through three-point bending test and simulation. In: 2020 IEEE 22nd electronic packaging technology conference EPTC 2020, pp 57–62 44. Liu V, Wang Y-C, Tsai C, Chen J, Gan CL, Bansal R, Takiar H (2022) The shift-left die strength analysis method for memory die products. In: 2022 IEEE international conference of electronic packaging, ICEP pp 201–202 45. Liu V, Arifeen S, Bassett C, Chung M, Gan CL, Takiar H (2021) Mechanical suite of flexural bending method for electronic memory packages. In: 2021 IEEE international conference of sensors and nanotechnology, SENNANO 2021, pp 45–49 46. Gan CL, Takiar H (2021) Semiconductor packaging structure for higher package strain and strength. China Patent No. ZL 202121228119.6 47. IPC-9702 IPC/JEDEC Standard (2004) Monotonic bend characterization of board-level interconnects 48. JEDEC standard (2016) JESD22-B111A Board level drop test method of components for handheld electronic products 49. Che FX, Pang HL, Zhu WH, Sun AYS (2006) Cyclic bend fatigue reliability investigation for Sn–Ag–Cu solder joints. In: Proceedings of electronic packaging technological conference EPTC, pp 313–317

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Chapter 3

Recycling of Noble Metals Used in Memory Packaging

3.1 Introduction This Chapter provides an overview of current and future deployment of recycling some noble metals on interconnect metals used in semiconductor assembly and packaging. Also, with the aim to study the key technical barriers, challenges of deployment and its reliability performance of both recycled gold (Au) and recycled copper (Cu) in semiconductor device packaging. This paper lays out the importance of ensuring noble metals in terms of its materials sustainability for the next decade. This article briefly reviews key aspects of deployment of recycled Au wire, recycled Cu, and other noble metals in semiconductor packaging and assembly. List of key technical challenges have been covered in this paper. The research trends on Sustainable Development Goal (SDG) technological and materials aspects highlight the critical role of recycling noble metals technology in semiconductor industry. At the end of this chapter, summary and key recommendation of future works have been provided for better clarity and reference purposes.

3.2 Possibility of Recycling Noble Metals in Packaging Semiconductor memory device has drawn main spotlights recently due to strong consumer and high-performance computing demands across the globe. However, most of the companies are focusing on environmental and social responsibility including to explore recycling materials and reducing waste. Semiconductor industry relies heavily on some of those noble metals as direct materials in semiconductor packaging and assembly. These includes major consumption in interconnect materials as first level, second level, substrate as well as system level printed circuit boards (PCB). Figure 3.1 illustrates categorization of IC memory packaging noble direct materials used as interconnects and surface finishing in advanced stacked die © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6_3

45

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3 Recycling of Noble Metals Used in Memory Packaging

Fig. 3.1 The categorization of noble direct materials used as interconnects and surface finishing in advanced memory IC packaging

packaging. Wire bonding is equally important and is the heart of first level die-tosubstrate interconnects technology in semiconductor packaging [1, 2]. Gold (Au) and Copper (Cu) wire bonding has been the technology invented more than 25year-old and continually sustained in semiconductor electronic packaging [3–14]. This research paper provides a holistic overview of current and future feasibility of recycling some of those direct materials mainly on interconnect metals used in semiconductor assembly and packaging. Also, this section aims to study the key technical barriers, challenges of deployment and its associated wearout mechanisms of both recycled gold (Au), recycled copper (Cu), and also tin (Sn) in semiconductor device packaging, which lays out the importance of ensuring noble metals sustainability for the next decade. Cu wire bonding has been hailed as the primary alternate wire bonding option adopted over Au wire bonding in semiconductor packaging. The great interest in deploying Cu wire bonding is mainly driven by lower cost, higher electrical conductivity, and tool readiness at this moment. However, the lower corrosion resistance of Cu wire especially in biased or unbiased HAST test has drawn technical concerns from the semiconductor industry [15] Cu ball bond with harder material properties cannot deployed with the same Au ball bonding parameters. Excessive first Cu ball bonding on Al bond pad will induce silicon cratering during bonding or post reliability stresses such as Pressure Cooker Test (PCT) [16]. Hence, in-depth first ball bonding should be characterized to minimize underneath silicon cratering phenomenon with Cu wire bonding. Key Cu wire bonding process developments and ongoing reliability monitoring have been laid out extensively to address those technical barriers to replace Au wire bonding in semiconductor packaging [17]. Although recycled Cu wire is not heavily being explored at this moment for semiconductor packaging, it will be a trend in near future owing to its lower cost and thermal conductivity properties.

3.2 Possibility of Recycling Noble Metals in Packaging

47

Fig. 3.2 Key recycling of noble metals used as interconnect materials in memory device packaging and its corresponding memory device types

Among those semiconductor direct materials, two major noble metals could possibly be recycled or recovered from scrapped semiconductor parts. This consists of Au and Cu which are used massively in semiconductor packaging and assembly processes (as shown in Fig. 3.2). Sources of noble metals recovery originate from bonding wires (Au, Cu), solder alloy (Cu), die level flip chip bump materials (Cu), substrate and PCB (Au, Cu). Some researchers investigated sources of metal recovery from wastewater treatment bath, wastes effluent from plating bath (from PCB or substrate manufacturing processes) or from recycled mobile phones. “Wear-out failures” occur as a results of the inherent lifetime of the device deteriorate due to wear, aging, creep and fatigue. When a device enters the wear-out period, the failure rate tends to increase rapidly. This is influenced by the usage conditions. For production of reliable semiconductor devices, it is important to reduce the early failure rate and to ensure the long life, or durability against wear-out failures [18]. Reliability is distinguished from quality in that quality usually refers to timezero compliance or conformance issues for the material/device. Reliability refers to the time-dependence of material/device degradation. All devices (electrical and/or mechanical) are known to degrade with time. Measuring and modeling the degradation rate, the time-to-failure, and the failure rate are the subjects of reliability engineering. Typical memory semiconductor device packaging requires numerous assembly processing steps and one of the key electrical interconnections relies on wire bonding (first level interconnect) after die attaching and stacking. Various types of bonding wires could be selected as interconnect materials depending on its cost, target package reliability and looping profiles. Solder alloys are mounted during solder ball mount step post package level laser marking and selection of solder alloy will influence its second level solder joint reliability [19]. Substrate is another sub-component within

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3 Recycling of Noble Metals Used in Memory Packaging

semiconductor packages which utilizes Au and Cu as electrical traces and served for surface finishing. There are a few key technical challenges identified in using recycled noble metals as direct materials in semiconductor packaging (as indicated in Fig. 3.3). In order to accommodate similar or comparable semiconductor device performances (speeds, functionality etc.), several considerations have to be listed for closer package reliability monitoring. Recycled Au or Cu wires used in wire bonding must be characterized for its intermetallic compound (IMC) coverage, shear strength and IMC growth kinetic to ensure lower risks of first ball bond reliability failure (especially during biased HAST or moisture reliability testing). Workability issues such as occurrence of short-tailing, non-sticking, sagging wire, club-bonds should have been closely monitored. This could be inter-related with wire dopants or breaking load with recycled Au or Cu wire. If Cu is being recovered and used in flip chip solder bump materials, consideration must be given to its electromigration reliability and CuSn IMC formation and grain size microstructures. Solder paste (with recycled Au or Cu) must deal with its solderability during surface mounting processes. Solder micro voiding and uniformity joining solder balls and PCB are critical for its overall solder joint reliability performances. Similarly, recycled Cu metal used in substrate Cu trace manufacturing

Fig. 3.3 Key reliability and process tradeoffs when utilizing recycled noble metals (Au, Cu) in semiconductor packaging and assembly

3.3 Key Enablers of Semiconductor Packages with Recycled Materials

49

Fig. 3.4 Potental issue with non-uniform Intermetallic Compound (IMC) formation when dealing with recycled Au wire compared to prime Au wire

will influence its overall Cu consumption rate during long term high temperature storage aging test (HTSL). Our recent works on long term aging reliability with recycled Au wire in Figure 3.4 reveals cross-sectional images of non-uniform AuAl IMC formation with recycled Au wire compare to prime Au bonding wire. Dimples are observed as bonded and worsen post 336 h of high temperature aging test at 175 °C. As bonded semiconductor parts show comparable AuAl IMC coverage between prime Au wire and recycled Au wire types (as depicted in Fig. 3.5).

3.3 Key Enablers of Semiconductor Packages with Recycled Materials Key technical barriers for different first interconnects in semiconductor packaging as tabulated in Table 3.1. It encompasses the key issues and corresponds with industrial know-how and technical solutions. There is limited reliability characterization and assessment data available on ball bond wearout. Another key concern is more on first ball bond wearout reliability performances with Au and Cu ball bonding. Table 3.1 tabulates all key technical challenges, materials issues, and possible solutions of different recycled noble metals (mainly on Au, Ag, Cu) used in semiconductor packaging processes. Au ball bonds show superior Unbiased Highly Accelerated Temperature and Humidity Stress Test (UHAST) package reliability performance with higher meantime-to failure hours (t50) and characteristics life (t63.2) in UHAST reliability plot (fitted to Weibull distribution) compared to Cu ball bond but not in temperature cycling (TC) stress regardless of EMC (Epoxy Mold Compound) effect. This is notable as Au is much more stable and has higher corrosive resistance compared to

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3 Recycling of Noble Metals Used in Memory Packaging

Fig. 3.5 Micron’s recently successful engineering evaluation with recycled Au wire. Comparable Intermetallic Compound (IMC) coverage is observed on recycled Au wire compared to prime Au wire

Cu. Cu is easily oxidized and corroded under moist environments, especially in the UHAST or biased HAST tests. Wearout reliability of HTSL has also been conducted on FBGA package assembled with both Au and Pd-coated Cu wires. Cu ball bonds (with slower Pd diffusion rate into Al bond pad metallization compared to Au ball bond) exhibit higher HTSL long term reliability margin compared with Au ball bonds. Long term wearout failure mechanism of HTSL belongs to ball bond-IMC interfacial microcracking in Cu ball bond and Kirkendall micro-voiding in Au ball bonds to Al bond pad metallization. The calculated Eaa is 0.91 eV for Au ball bond and 1.00 eV for Cu ball bond in HTSL reliability assessment [6]. Wearout reliability of a product is defined as the stage whereby a product or part’s reliability would give way at its weakest interconnect or link in a system. It is important information to extrapolate and predict the lifetime based on field use conditions. Key reliability challenges such silicon cratering with Cu ball bond; high humidity corrosion mechanism and ball bond shear per mil square have been laid out in our previous works [6, 7]. Wearout failure mechanism of HAST and UHAST stress testing belongs to CuAl and AuAl IMCs interface corrosion and micro-cracking which induced electrical ball bond opens [8, 9]. The values obtained for apparent activation energy (Eaa ) (in eV) of AuAl IMC formation (1.04 eV), while Eaa of CuAl IMC interdiffusion (1.18 eV). It clearly indicates that Au atoms diffuse at least 5 times faster than PdCu atoms in Al metallization of the 110 nm flash device tested [10].

3.3 Key Enablers of Semiconductor Packages with Recycled Materials

51

Table 3.1 Key enablers and possible solutions of different recycled noble metals (mainly on Au, Ag, Cu) used in semiconductor packaging processes Type of recycled metal

Key process, materials reliability, and workability concerns

Key enablers

References

Ag

Short tailing occurrence during wire bonding process step

Optimize ~ 10% lower second bond force

[4]

Cu

Higher inter-metal dielectric (IMD) microcracking with Cu

Ensure recycled Cu wire with similar Cu wire dopants to main its wire softness

[5]

Cu

Lower solder joint reliability margin

Use of higher mechanical strength of Bi-doped Solder alloy

[19]

Au, Cu

IMC formation kinetics with recycled Au and Cu which will impact its overall interconnect reliability post thermomechanical reliability stressing

Perform in-depth IMC kinetic study comparing recycled Au and Cu substances compared to prime metals to eliminate too fast IMC growth rates

[19]

Au

Kirkendall micro-voiding at High Temperature Storage Life (HTSL) long duration (exceeding 1500 h)

Ensure similar contents [20–23] doped Au wire to mitigate faster Au atomic diffusion into aluminium (Al) bond pad

Au

Total AuAl IMC coverage with recycled Au wire

Deploy pre-wirebond plasma cleaning to enhance bondability

[20–23]

Cu

Lifted ball mode observed with Cu ball bond compared to ball shear mode post biased Highly Accelerated Temperature and Humidity Stress Test (HAST) or Temperature Cycling (TC)

Optimize first ball bond force and bonding time to ensure > 80% IMC coverage

[24]

Cu

Lower electromigration Doped with ~ 2% [25] resistance with recycled Cu palladium (Pd) content in used in Cu pillar bumping Cu alloy used in flip chip bumping. Capped Cu pillar bump with Nickel Accurate electromigration lifetime prediction of the copper pillar bumps (continued)

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Table 3.1 (continued) Type of recycled metal

Key process, materials reliability, and workability concerns

Key enablers

References

Cu

Faster Cu consumption especially long duration of HTSL at substrate level. Recycled Cu used in PCB fabrication might affect Cu trace track resistance and grain size

Ensure top Cu layer thickness is plated with sufficient Cu thickness margin (> 10 µm)

[26]

3.3.1 Review Methodology Therefore, a review methodology suits the present study. This study follows a fivestep review methodology process. The literature review methodology process starts with the reviews of previous studies in recycling methodology of noble metals in semiconductor assembly packaging, screening analysis of interconnects in semiconductor materials (bonding wire, solder alloy or metallization). Further literature mining from 2010 till 2021 has been studied and segregated into types of noble metals (Au, Cu). Then, an in-depth technical risk assessment, findings and the writing of the review are involved. All these studies aim to identify the research trends to serve as a basis for knowledge development and key efforts of materials sustainability adopted by key semiconductor manufacturers. The procedures from step 1 to step 5 in Fig. 3.6 highlight the overview of flow-chart in our topical review of recycling of noble metals in semiconductor industry. Key enablers of different recycled noble metals are listed in Table 3.1.

Fig. 3.6 Flowchart for topical reviews of recycled noble metals in semiconductor packaging

3.4 Recycling and Recovery of Nobel Metals in Semiconductor Assembly

53

3.4 Recycling and Recovery of Nobel Metals in Semiconductor Assembly 3.4.1 Recycling of Gold in Semiconductor Packaging Recycling gold from industrial and electronic waste is less straightforward because the gold is embedded in a metal or plastic housing and may only be two percent by weight. Once the pieces containing the precious metal have been stripped, several options exist for processing. The first is chemical stripping with a compound that reacts with the gold. The second option is to melt down the metal components, cool them and grind them up. Both processes require further extraction and purification through smelting. Paulo et al. [28] reported on developing a simple, efficient, and environmentally friendly technology for recycling all main raw materials (gold, copper, and fiber glass (FG) layers) from waste printed circuit boards (WPCBs). Similar gold extraction and recovery methodology has been performed by Wang et al. [29]. In the study, they discovered gold was easily recycled from PCBs gold-plated layer of waste mobile phones in DMF-CuCl2 –CaCl2 (DMF: dimethyl formamide) system what we call “mild aqua regia” without pretreatments or enrichment process, and the reaction system could be cyclic utilized. In such a reaction system, gold could be recycled through leaching, precipitation, and filtration. The reaction parameter optimization and reaction mechanisms were studied. Under the optimized conditions, the gold leaching rate and precipitation rate could reach over 99%. In summary, Au recycling appears to be a feasible option as from semiconductor packages as well as recycling gold from printed circuit boards gold-plated layer of waste mobile phones.

3.4.2 Recycling of Cu in Semiconductor Electronics Zhu et al. [30] developed an effective recycling of Cu from electroplating wastewater effluent via the combined Fenton oxidation and hydrometallurgy route. Cu was efficiently enriched as tenorite from Cu-bearing wastewater, whereas the added Fenton reagent Fe2 P was successfully converted into highly purified hematite. Thus, this method has great potential for recycling Cu from electroplating wastewater. Recovery of Cu and Au from e-waste by a two-stage leaching and solvent extraction process have also been reported by Rao et al. [31]. A new hydrometallurgical route for the technically feasible recycling of copper and gold from waste printed circuit boards (WPCBs) of mobile phones. This process comprises the liberation of the metallic fractions from downsized WPCBs, a two-stage acid leaching process to provide a bulk separation of copper and gold from the other metals present, and subsequent purification of the copper and gold-containing solutions by solvent extraction using highly selective phenolic oxime and amide extractants, respectively.

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3.4.3 Recycling of Sn in Semiconductor Electronics Tin (Sn) is mainly used as composition in solder paste, solder alloys, and surface finishes onto substrate or PCB. However, less research works being conducted to recover Sn from semiconductor package level or PCB scrappage. It could be owing to lower extraction yield and complicated recovery processes. In 1997, Scott et al. [50] has identified the main Sn recovery from stripper bath used in PCB plating line. In this study, a simple aqueous nitric acid stripping solution was identified as an alternative to the present commercial stripping solutions in respect to recycling. Two recycling processes were studied: the electrochemical recycling of all metals and the combination of electrochemical deposition of copper and precipitation of tin and lead which can be followed up by furnace recycling. It focuses on the development of recycling of Sn metal from waste Sn-based alloys by vacuum separation. To recycle waste Sn-based alloys, the vapor–liquid phase equilibrium composition diagrams of Sn–Pb, Sn–Sb and Sn–Zn binary systems were calculated. The calculated results indicate that Pb, Sb and Zn can be separated from Sn effectively. This could be another option of Sn recovery process.

3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor Industry 3.5.1 Recycled Materials Reliability Perspective In general, Cu wire is not an ultimate bonding wire solution in semiconductor packaging. Cu wire bonding is more suitable to be deployed in low pin-count semiconductor packaging, flash memory packaging, high power devices, or Microelectromechanical system (MEMS) which utilize larger diameter of bonding wire with lower IO counts. The various considerations such as its long term extended reliability performance and bond pad cratering challenges still pose a showstopper for a full sweep of copper wire bonding in the semiconductor packaging industry. Undeniably, the forming gas kit (installed on the wire bonder) will improve the wire bonding process with an inert environment since Cu wire is vulnerable to corrosion and oxidation in production floor, but this adds somewhat to infrastructure and cost. Au wire bonding is the preferably packaging option by industry in lower pin count microelectronics packaging while Cu wire bonding is adopted for higher IO counts due to cost constraint such as Field Programmable Gate Array (FPGA) packaging. There is not a clear bonding wire deployment based on market segments at this moment as Au wire bonding will still be kept as backup of Cu wire bonding in high volume manufacturing. Au wire will continue to exist in semiconductor packaging especially in high reliability markets, since extended reliability is a key concern (in markets like the automotive industry). With the recent drop in gold price, there might be a shift of heavy dependence on Cu wire bonding back to conventional Au

3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor …

55

wire bonding due to the perception of extended reliability, even though the previously presented data shows excellent reliability results compared with Au. Au wire bonding will likely “co-exist” with other bonding wires such as Cu and Ag in semiconductor industry. We might see an intermittent swap among these three wire alloys based on the gold pricing. From a performance point of view, gold can be as reliable as copper wire in HTSL, but copper is facing problems in more challenging stress tests such as temperature cycling and HAST that is driving the evaluation of Pd-coated Cu wires. There is no doubt that copper can and should replace gold wherever viable but the main driving force to do so, at present, is cost reduction [22]. There is clearly a place for copper wire bonding in fine and possibly ultra-fine wire bonding, but it is likely that rather than replacing gold wire entirely, copper wire bonding will become another process tool alongside gold wire bonding, flip chip, TSV (through silicon via) and other interconnect methods, which microelectronics package designers can consider for package assembly. Semiconductor manufacturers would only consider wire bonding with Cu for product they wanted to be in a wire bond package and likewise goes for a flip chip product. In summary, Au wire bonding is still attractive and one of the mainstream processes in semiconductor packaging, owing in many ways to its maturity and the perception of greater reliability. All above-mentioned works are mainly focusing on prime noble metals (Au, Cu) used in semiconductor packaging, recycled novel metal is still a new topic and not many wire manufacturers embark on this recycled wire except one or two makers. However, many end customers are exploring the balance between technological evolution as well as environmental sustainability and greener materials. Recycled noble metals especially on Au, Cu and the rest will be the key trends in semiconductor packaging processes in wire bonding, substrate manufacturing, flip chip packaging and High Bandwidth Memory (HBM) packaging.

3.5.2 Comparison of Materials Cost and Reliability: Recycled Au Wire with Prime Wire In a quick summary, a recent engineering evaluation has been performed comparing a semiconductor package assembled with both prime against recycled Au wire and both are passing package reliability tests (as tabulated in Table 3.2). Some considerations should have been taken to ensure process workability and the cost of raw materials is a bit pricy with recycled Au wire. Metal extraction and reclaiming processes might be an added cost in terms of energy emission and release. Nevertheless, with a welldesigned program and the right technology, recycling can be more efficient in terms of energy, money, and natural resources when compared to a system that manufactures everything from virgin materials and sends it all to landfills when consumers discard it [27]. Wernick et al. [32] reported one of the most striking environmental benefits of secondary metals production is the reduction in energy needed to produce a ton of metal. The primary reason for this phenomenon is that melting metal requires less

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Table 3.2 Key comparisons of recycled Au wire and prime Au wire Items

Prime Au wire

Recycled Au wire

Package reliability performance (engineering evaluation)

Passed moisture reliability test (unbiased HAST, biased HAST), thermomechanical test (temperature cycling), HTSL (high temperature storage life)

Passed moisture reliability test (unbiased HAST, biased HAST), thermomechanical test (temperature cycling), HTSL (high temperature storage life)

Process workability

No

Occurrences of wire sway and leaning wire, abnormality in FAB (free air ball) formation, short tail during wire bonding

Cost of materials

1.0

Around 1.01–1.05

Materials sustainability

No

Yes

energy than that needed for reducing naturally occurring oxides and sulfides. Besides conserving energy resources, metals recycling also reduces mining and beneficiation activities that disturb ecosystems. Although land used for the extraction of primary metals represents under 0.1% of Earth’s terrestrial surface, exploration and mining activity can affect surrounding ecosystems owing to necessary infrastructure and by dispersing metal compounds into the environment, either as airborne particles or as ions in aqueous solutions. Developing newly discovered resource deposits can also damage sensitive ecosystems, especially in less developed regions where the need for foreign exchange from mineral rents overshadows domestic environmental concerns. Recycling is not always the cheapest alternative, however, especially when reuse is an option especially on precious noble metals such as Au, Cu, Ag and Pd. We are running out of raw metal earth elements and adopting recycled noble metals is the right path in the future.

3.5.3 Interconnect Reliability with Recycled Wire in Semiconductor Packaging There are very limited studies in reliability assessment in terms of interconnect reliability of recycled noble metals (such as Au, Cu) used in semiconductor packaging. It could be owing to the higher cost of using recycled noble metals either in wire bonding or flip chip packaging. At this moment, only a few semiconductor companies such as Micron are exploring using recycled Au wire in memory device packaging. This is also aligned with materials sustainability in semiconductor assembly and packaging goals called out by some of those semiconductor manufacturers. We expect to see equivalency in terms of interconnect reliability of recycled Au ball bond compared to prime Au ball bond. Notably, in prime Au or Cu wire bonding, CuAl IMC growth mechanism is slightly different from AuAl IMC in microelectronic packages. The IMC between Cu wire and Al pad can be distinguished into five types, as in the case

3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor …

57

of Au wire. However, only two IMC, Cu9 Al4 and CuAl2 , can be typically observed because the Cu–Al IMC forms very slowly and it is very thin in Cu ball bond IMC growth. CuAl IMC will be formed thicker at the edge of Cu ball bond compared to the center of Cu ball bond. This is mainly due to the thermo-compression effect during capillary compression onto Al bond pad during wire bonding induced by capillary compression [6]. Moisture in HAST or UHAST chamber will attack Cu ball bond at both edges of Cu ball bonds. Trace Cl− ion from molding compound will corrode the thin CuAl IMC layer beneath Cu ball bond and hydrolysis of CuAl IMC will occur (see Eq. 3.1). CuAl IMC microcracking will occur as a result of hydrogen outgassing or embrittlement (as in Eq. 3.2). Hydrolysis of CuAl IMC will form a brittle IMC, still conductive in Cu ball bond but resistive and will reach wearout opens (lifted ball bond after corrosion) after extended reliability stressing under HAST or UHAST [6]. Cu9 Al4 + 6H2 O → 2(Al2 O3 ) + 6H2 + 9Cu(Outgassing)

(3.1)

CuAl2 + 3H2 O → Al2 O3 + 3H2 + Cu

(3.2)

Au ball bond is found with higher IMC growth rate at least 5X compared to Cu ball bond in HTSL aging test [6–8]. Hence, there is a slightly different HTSL failure mechanism after long duration of aging stress in Au and Cu ball bonds. Both CuAl and AuAl IMCs are formed in long hours of HTSL test except more uniform AuAl IMC formation compared to CuAl. Thicker CuAl IMC is formed at the edge of Cu ball bond. AuAl IMC is observed with more uniform and thicker, but Kirkendall micro voiding will occur which might induce AuAl IMC microcracking. HTSL wearout opens occur as lifted ball bonds for both Au and Cu balls except with Kirkendall micro voiding in Au ball bonds (Fig. 3.7a and b respectively). Table 3.3 tabulates CTE for materials used in package bills of materials in FBGA memory package. The CTE (Coefficient of Thermal expansion) mismatching between Cu (17.8 ppm/°C) and Au ball bond (14.2 ppm/°C) to the silicon die (3.0 ppm/°C) induces different thermal expansions and contraction rates in the temperature cycling test. The CTE mismatch between Au and Cu ball bonds with Al bond pad of silicon die will impose different thermal expansion rates during hot cycles (150 °C) and contraction rates during cold cycles (−40 °C). IMC formation initiated at the edge of the ball bond (due to the ball bond pressing force by capillary) and microcracking will be induced after long cycles of thermal cycling effects. Micro-cracking occurs in between ball bond IMC and EMC [6, 7]. Those are key prime Au and Cu ball bond wearout failure mechanisms especially after HAST, unbiased HAST, TC, and HTSL long term reliability tests. It is predicted to have similar failure mechanism if we were to use recycled Au or Cu in semiconductor packaging as tabulated in Table 3.4. Several key mitigation measures are being proposed to understand and prevent those similar failure mechanisms.

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Fig. 3.7 a Schematic representation of Cu ball bond micro cracking after long hours of HTSL stressing; b Kirkendall micro voiding as a function of aging hours in Au ball bond

Table 3.3 Key material characteristics of epoxy mold compound (EMC) A and B

Material

Units

CTE (coefficient of thermal expansion)

Au

ppm/°C

14.2

Cu

ppm/°C

17.8

Silicon

ppm/°C

3.0

Al

ppm/°C

22.2

The required activation energies (Eaa ) of interdiffusion of Cu and Au atoms in Al were modeled by using Arrhenius model. The fundamental basis of thermal activation is based on the probability of ascending a potential energy barrier due to Maxwell- Boltzmann energy distribution. This physical explanation was anticipated by Arrhenius work on chemical reaction rates, which one would simply substitute the Rydberg gas constant for the Boltzmann constant and use different units. Thermal activated processes are modeled by Arrhenius equation, and it is given by Eq. 3.3 or 3.4. Rate = R0 exp(−E aa /kT )

(3.3)

Rate = R0 exp(−E aa /RT )

(3.4)

where Ro is the rate constant characteristics of infinite temperature, Eaa refers to apparent activation energy in eV/atom for physics units or Kcal/mole for chemical units, k is the Boltzmann constant, 8.62 × 10–5 eV/Kelvin, R is the Rydberg gas

3.5 Co-existence of Prime and Recycled Bonding Wires in Semiconductor …

59

Table 3.4 Key reliability assessments of recycled Au/Cu wire and their corresponding failure modes and mitigation strategies Key reliability assessments

Possible failure modes with recycled wire (Au/ Cu)

Possible mitigation strategies

Temperature cycling condition-B (T/C-B), −55 °C for 15 min, +125 °C for 15 min, air to air cycling, 1000 cycles [33]

The CTE mismatch between Au and Cu ball bonds with Al bond pad of silicon die will impose different thermal expansion rates during hot cycles (125 °C) and contraction rates during cold cycles (−55 °C). IMC formation initiated at the edge of the ball bond (due to the ball bond pressing force by capillary) and microcracking will be induced after long cycles of thermal cycling effects

Match EMC CTE with regards to Silicon die. Ensure similar materials properties (such as CTE, elongation, breaking load) of recycled Au or Cu wire comparable to prime wires

Temperature cycling condition-C (T/C-C), −65 °C for 15 min, +150 °C for 15 min, air to air cycling, 500 cycles [33]

The CTE mismatch between Au and Cu ball bonds with Al bondpad of silicon die will impose different thermal expansion rates during hot cycles (125 °C) and contraction rates during cold cycles (−55 °C)

Match EMC CTE with regards to Silicon die. Ensure similar materials properties (such as CTE, elongation, breaking load) of recycled Au or Cu wire comparable to prime wires

Biased HAST 110 °C, 85% RH soak, Vcc dependent upon product being tested, 264 h [34]

Moisture in HAST or UHAST chamber will attack Au or Cu ball bond at both edges of ball bonds under biased conditions

Ensure wire resistivity, and low halogen content in EMC especially in recycled Au wire. Not so critical for Au ball bonds

Unbiased HAST (UHAST) of 110 °C, 85% RH soak, no electrical bias, 264 h [35]

Moisture in HAST or UHAST chamber will attack Au or Cu ball bond at both edges of ball bonds under high humidity environment

Ensure wire resistivity, and low halogen content in EMC especially in recycled Au wire. Not so critical for Au ball bonds (continued)

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Table 3.4 (continued) Key reliability assessments

Possible failure modes with recycled wire (Au/ Cu)

Possible mitigation strategies

High temperature storage life (HTSL) 150 °C/175 °C soak, no electrical bias, 1000 h [36]

Au ball bond is found with higher IMC growth rate at least 5X compared to Cu ball bond in HTSL aging test [1, 6] Slightly different HTSL failure mechanism after long duration of aging stress in Au and Cu ball bonds. Both CuAl and AuAl IMCs are formed in long hours of HTSL test except more uniform AuAl IMC formation compared to CuAl. Thicker CuAl IMC is formed at the edge of Cu ball bond. AuAl IMC is observed with more uniform and thicker, but Kirkendall micro voiding will occur which might induce AuAl IMC microcracking

Ensure the dopants of recycled wires (either Au or Cu) are comparable to prime wires to prevent Kirkendall micro-voiding after long duration of HTSL stress

Board level temperature cycling, 1.60 mm/2.36 mm double sided board, 0 °C for 10 min, +100 °C for 10 min, air to air cycling, end after 63.2% cumulative failures, >= 1500 cycles [37]

Expect to observe similar solder joint fracture mode at second level reliability after multiple temperature cycling

No dependency on wire types and conditions

Board level drop test, 1.0 mm single sided board, 1500 g 0.5 ms ½ sine pulse, Z-axis, end after 63.2% cumulative failures, >= 10 drops [38]

Expect to observe similar solder joint fracture mode at second level reliability after multiple board level drops

No dependency on wire types and conditions

constant, 23,063 cal/mole-kelvin and T is the temperature in Kelvin. Using Eq. 3.5, the acceleration factor (AF) for T1 versus T2 is as follows: [ / ] AF = exp (−E aa /kT ) (1/T1 − 1/T2 )

(3.5)

It is noted that the acceleration factor is sensitive to the value for the apparent activation energy, Eaa and the temperature difference. The apparent activation energy, Eaa which is temperature dependence can be determined by plotting graph ln (lifetime of ball bonds) versus 1/kT as in Eq. (3.6). Graph ln T (lifetime) versus (1/T) can be plotted by using Eq. (3.7). T = R0 exp(−E aa /kT )

(3.6)

3.6 Key Recycling Initiative by Industry Semiconductor Manufacturers Table 3.5 Summary of apparent activation energies and associated failure mechanisms comparing prime ball bonds and recycled ball bond in semiconductor devices

61

Ball bond type

Eaa (eV)

Failure mechanism

References

Prime Au

1.00–1.26

Kirkendall voiding

[39]

Prime Cu

0.75

CuAl corrosion

[39]

Prime Cu

0.70

CuAl microcracking

[24]

Prime Pd coated Cu

0.85

CuAl microcracking

[8]

Prime Au

1.10

Kirkendall voiding

[8]

Recycled Au

Under study

Kirkendall voiding

Under study

ln T = −(E aa /R)(1/kT ) + ln R0

(3.7)

where self-diffusion coefficient, Ro is a constant, Eaa is activation energy in eV for the diffusion process, R is molar gas constant in Jmol−1 K−1 and T is lifetime of ball bonds. The apparent activation energy, Eaa can be calculated from the gradient of the plot ln T versus 1/kT. Table 3.5 tabulates the results of Eaa and typical wearout failure mechanisms of Au and PdCu ball bond after HTSL stress of our studies compare to previous engineering works conducted by researchers [24, 39]. In our evaluation, the values obtained for Eaa (in eV) of Au ball bond is similar to value published in JEDEC JEP112 [39] while Eaa of PdCu ball bond is slightly higher than bare Cu ball bond. There is a necessity for industrial researchers to investigate the Eaa of recycled Au & future Cu ball bonds in terms of their IMC growth rate and kinetic under HTSL reliability stress conditions as well.

3.6 Key Recycling Initiative by Industry Semiconductor Manufacturers 3.6.1 Key Recycling Initiatives In recent years, sustainability and social responsibilities have been becoming the focus of electronic industry due to the strategy of environmental protection. Among various aspects of sustainability, Micron focuses mainly on lower carbon and gas emissions as well as recycling of waters used in semiconductor fabrication and assembly. The overall corporate social and sustainability initiatives are summarized in Table 3.6. In summary, there are 3 main area of technological sustainability efforts which encompasses (1) Materials Sustainability: water, plastic, papers, and e-waste

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materials recycling, (2) Environmental Sustainability: carbon zero or zero gas emissions from manufacturing sites and (3) Energy Sustainability: Exploring usage of renewable energy resources. Both Micron and Apple started exploring adopting recycled noble metals (mainly on Au, future possibly on Cu, Sn, Co) in direct materials of semiconductor packaging assembly. This includes both first level, second level as well as substrate or PCB system level semiconductor interconnects. Among those semiconductor direct materials, three major noble metals could possibly to be recycled or recovered from scrapped semiconductor parts. The review pinpoints that the trend of research is more on technological readiness and key sustainability efforts adopted by key semiconductor manufacturers. Careful packaging materials characterization should have been carried out prior to adoption of those recoverable noble metals used in semiconductor components. Out of those listed key semiconductor players (as summarized in Table 3.6), TSMC has established innovative idea in terms of environmental sustainability by cultivating fireflies and larval prey, and continuously improving and monitoring the environment surrounding their wafer fabrication sites. Microsoft has revealed a Project Natick to test and monitor the performance, reliability, and failover of the purpose-built underwater data center, dubbed the Northern Isles. The underwater data center contained 12 racks, 864 servers with FPGA acceleration and 27.5 petabytes of storage. It was sent 117 feet into the sea off Scotland’s Orkney Islands in spring 2018. And Apple has kicked-off and committed to Certified recycled gold in its smartphone manufacturing processes. Recycling is not always the cheapest alternative, however, especially when reuse is an option especially on precious noble metals such as Au, Cu, Ag and Pd. We are running out of raw metal earth elements and adopting recycled noble metals in semiconductor industry is indeed need for materials sustainability point of view.

3.7 Summary and Recommendations Interconnect materials reliability and properties play a pivotal role in emerging memory device packaging. This includes both first level, second level as well as substrate or PCB system level semiconductor interconnects. Among those semiconductor direct materials, three major noble metals could possibly to be recycled or recovered from scrapped semiconductor parts. The review pinpoints that the trend of research is more on technological readiness and key sustainability efforts adopted by key semiconductor manufacturers. Careful packaging materials characterization should have been carried out prior to adoption of those recoverable noble metals used in semiconductor components. In summary, there are 3 main area of technological sustainability efforts which encompasses (1) Materials Sustainability: water, plastic, papers, and e-waste materials recycling, (2) Environmental Sustainability: carbon zero or zero gas emissions from manufacturing sites and (3) Energy Sustainability. Some important results and recommendations are summarized as follows.

3.7 Summary and Recommendations

63

Table 3.6 Key environmental sustainability initiatives by some of the key semiconductor players Key players Technological sustainability initiatives

References

Micron

Micron currently recycles 70–80 percent of the water used each day in the production of semiconductors. This compares to a recycling rate of 30 percent in 1995 Established new greenhouse gas reduction targets and commits to net-zero emissions from its operations by 2050

[40]

Intel

Intel’s website discusses their various recycling practices. They are very active recyclers, claiming to reuse their wastewater and avoid waste in their production processes Intel promised to cut greenhouse gas emissions to zero by 2040

[41]

TSMC

Build in-house recycling systems to remake the waste copper sulfate [42] into regenerated copper tubes. Furthermore, we cooperated with the raw material suppliers to develop smelting processes for purification of copper tube Recycled plastic materials, wastewater, establishing habitats, cultivating fireflies and larval prey, and continuously improving and monitoring the environment

Apple

Nearly 20 percent of all material used in Apple products in 2021 was [43] recycled, the highest-ever use of recycled content 45% certified recycled rare earth elements, 30% certified recycled tin, 13% certified recycled cobalt, kick-off and committed to Certified recycled gold in its smartphone manufacturing processes

Microsoft

Microsoft has revealed a brand-new computer mouse that is made from 20% recycled ocean plastics and a 100% plastic-free in 2021

[44]

Facebook

Facebook has revealed that it achieved net-zero operational emissions in 2020, after eliminating most of its greenhouse gas (GHG) footprint and investing in carbon removal

[45]

Google

Google plans to use 100% carbon-free energy in its data centers by 2030 Committed to use recycled or renewable material in at least 50% of all plastic in all our hardware products by 2025

[46]

Samsung

Incorporating recycled material into all new mobile products, eliminating all plastics in mobile packaging, and achieving zero waste to landfill by 2025

[47]

SK Hynix

Targets carbon-emission cut of 200 million tons by 2030

[48]

• Recycled Au or Cu wires used in wire bonding must be characterized for its intermetallic compound (IMC) coverage, shear strength and IMC growth kinetic to ensure lower risks of first ball bond reliability failure (especially during biased HAST or moisture reliability testing). Workability issues such as occurrence of short-tailing, non-sticking, sagging wire, club-bonds should have been closely monitored. This could be inter-related with wire dopant/s or breaking load with recycled Au or Cu wire. • If Cu is being recovered and used in flip chip solder bump materials, consideration must be given to its electromigration reliability and CuSn IMC formation and grain size microstructures. Solder paste (with recycled Au or Cu) must deal with

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its solderability during surface mounting processes. Solder micro voiding and uniformity joining solder balls and PCB are critical for its overall solder joint reliability performances. • Developing newly discovered resource deposits can also damage sensitive ecosystems, especially in less developed regions where the need for foreign exchange from mineral rents overshadows domestic environmental concerns. Recycling is not always the cheapest alternative, however, especially when reuse is an option especially on precious noble metals such as Au, Cu, Ag and Pd. • Most key semiconductor manufacturers kicked-off technological sustainability efforts other than solely looking into sustainable materials by using recycled direct materials such as bonding wires. That could be extended to future interconnect materials such as recycled Sn and Pd etc. • Memory packages must meet minimum package reliability requirements as laid out in AEC Q104 [49] and JEDEC standards [33–36] prior release to high volume manufacturing.

References 1. Harman GG (1999) Wirebonding in microelectronic: materials, processes, reliability and yield, 2nd edn. McGraw Hill, New York, pp 135–155 2. Zhong ZW (2009) Wirebonding using copper wire. Microelectron Int 26(1):10–16 3. Chauhan PS, Choubey A, Zhong Z, Pecht MG (2014) Copper wire bonding, 1st edn. Springer, New York, pp 235–240 4. Zulkifli MN, Abdullah S, Othman NK, Jalar A (2012) Some thoughts on bondability and strength of gold wire bonding. Gold Bulletin 45:115–125 5. Gan CL, Ng EK, Classe FC, Chan BL, Hashim U (2012) Technical barriers and development of Cu wirebonding in nanoelectronics device packaging. J Nanomater 2012:1–7 6. Gan CL, Classe FC, Chan BL, Hashim U (2013) Extended reliability of gold and copper ball bonds in microelectronic packaging. Gold Bulletin 46(2):103–115 7. Gan CL, Hashim U (2013) Comparative reliability studies and analysis of Au, Pd-Coated Cu and Pd-Doped Cu wire in microelectronics packaging. PLosone 8(11):1–8 8. Gan CL, Hashim U (2013) Reliability assessment and activation energy study of Au and PdCoated Cu wires post high temperature aging in nanoscale semiconductor packaging. J Electron Packag 135(2):0210101–210107 9. Gan CL, Hashim U (2013) Reliability assessment and mechanical characterization of Cu and Au ball bonds in BGA package. J Mater Sci Mater Electron 24(8):2803–2811 10. Gan CL, Classe FC, Chan BL, Hashim U (2014) Evolution and investigation of copper and gold ball bonds in extended reliability stressing. Gold Bulletin 47(2):141–151 11. Gan CL, Classe FC, Chan BL, Hashim U (2014) Future and technical considerations of gold wirebonding in semiconductor packaging—a technical review. Microelectron Int 31(2):121– 128 12. Gan CL, Ng EK, Chan BL, Hashim U (2012) Reliability challenges of Cu Wire deployment in flash memory packaging. In: Proceedings of IEEE proceedings of international microsystems, packaging, assembly and circuit technology conference, Taipei, Taiwan, pp 498–501 13. Gan CL, Ng EK, Chan BL, Kwuanjai T, Jakarin S, Hashim U (2012) Wearout reliability study of Cu and Au wires used in flash memory fine line BGA package. In: Proceedings of IEEE proceedings of international microsystems, packaging, assembly and circuit technology conference, Taipei, Taiwan, pp 494–497

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14. Gan CL, Ng EK, Chan BL, Classe FC, Kwuanjai T, Hashim U (2012) Wearout reliability and intermetallic compound diffusion kinetics of Au and PdCu wires used in nanoscale device packaging. J Nanomater 2012:1–9 15. Gan CL, Toong TT, Lim CP, Ng CY (2010) Environmental friendly package development by using copper wire. In: Proceedings of IEEE proceedings of international electronics manufacturing technology conference, Malacca, Malaysia, pp 1–5 16. Tan CW, Daud AR (2002) Cratering on thermosonic copper wire ball bonding. J Mater Eng Perform 11(1):283–287 17. Chauhan P, Zhong ZW, Pecht M (2013) Copper wire bonding concerns and best practices. J Electron Mater 42:2415–2434 18. McPherson JW (2019) Reliability physics and engineering. Springer Nature, Texas 19. Zou YS, Gan CL, Chung MH, Hem T (2021) A review of interconnect materials used in emerging memory device packaging: first and second level interconnect materials. J Mater Sci Mater Electron 32(8):27133–27147 20. Breach CD, Wulff F (2006) Oxidation of Au4 Al in unmoulded gold ball bonds after high temperature storage (HTS) in air at 175C. Microelectron Reliab 46(12):2112–2121 21. Breach CD, Wulff F (2009) Intermetallic growth in gold ball bonds aged at 175 °C: comparison between two 4N wires of different chemistry. Gold Bull 42(2):92–105 22. Breach CD (2010) What is the future of bonding wire? Will copper entirely replace gold? Gold Bull 43(3):150–168 23. Breach CD, Lee TK (2012) Shear strength and failure modes of as-bonded gold and copper ball bonds on aluminum metallization. J Electron Mater 41(7):2018–2028 24. Classe FC, Gaddamraja S (2011) Long term isothermal reliability of copper wire bonded to thin 6.5 µm aluminium. In: Proceedings of IEEE international reliability physics symposium, pp 685–689 25. Chen F, Chen S, Fu Z, Huang Y, Qin F, An T (2020) Prediction of electromigration lifetime of copper pillar bumps in ceramic packaging device. In: Proceedings of 21st IEEE international conference electronics packaging technology ICEPT 2020, pp 2020–2023 26. Moideen MZ, Gan CL (2016) Solder joint reliability enhancement through surface mounting solder joint reflow optimization in enterprise grade solid state drives (SSDs). In: Proceedings of the IEEE/CPMT international electronics manufacturing technology (IEMT) symposium, pp 1–6 27. Ashley M (2012) The costs of recycling. Stanford University, Fall 28. Paulo MS, Liliana M, Marques AT, Margarida MSMB, Helena MVMS (2022) A closed and zero-waste loop strategy to recycle the main raw materials (gold, copper, and fiber glass layers) constitutive of waste printed circuit boards. Chem Eng J 434:134604 29. Wang R, Zhang C, Zhao Y, Zhou Y, Ma E, Bai J, Wang J (2021) Recycling gold from printed circuit boards gold-plated layer of waste mobile phones in “mild aqua regia” system. J Clean Prod 278:123597 30. Zhu S, Wang Z, Lin X, Sun T, Qu Z, Chen Y, Su T, Huo Y (2020) Effective recycling of Cu from electroplating wastewater effluent via the combined Fenton oxidation and hydrometallurgy route. J Environ Manage 271:110963 31. Rao MD, Kamalesh KS, Carole A, Jason B (2021) Recycling copper and gold from e-waste by a two-stage leaching and solvent extraction process. Sep Purif Technol J 263:118400 32. Wernick IK, Themelis NJ (1998) Recycling metals for the environment. Ann Rev Energy Environ 23:465–497 33. JEDEC standard (2014) JESD22-A104 Temperature cycling 34. JEDEC standard (2021) JESD22-A110 Highly accelerated temperature and humidity stress test (HAST) 35. JEDEC standard (2018) JESD22-A118 Accelerated moisture resistance—unbiased HAST 36. JEDEC standard (2015). JESD22-A119 High temperature storage life—HTSL 37. IPC-9701A IPC/ JEDEC Standard (2002) Performance test methods and qualification requirements for surface mount solder attachments

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38. IPC-9703 IPC/ JEDEC Standard (2009) Mechanical shock test guidelines for solder joint reliability 39. JEDEC Specification JEP-122 (2010) Failure mechanisms and models for semiconductor devices 40. Micron News https://www.micron.com/about/our-commitment/operating-thoughtfully/enviro nment-health-and-safety-policy/resource-conservation 41. Intel News https://www.intel.com/content/www/us/en/environment/intel-and-the-enviro nment.html 42. TSMC News https://esg.tsmc.com/en/update/greenManufacturing/caseStudy/8/index.html 43. Apple News https://www.business-standard.com/article/technology/apple-used-almost-20-rec ycled-materials-in-its-devices-in-2021-122042000244_1.html 44. Microsoft News https://www.crn.com/news/data-center/microsoft-s-underwater-data-centera-success-azure-ahead 45. Facebook News https://sustainability.fb.com/wp-content/uploads/2020/12/FB_Net-Zero-Com mitment.pdf 46. Google ESG Handbook https://store.google.com/magazine/sustainability?pli=1&hl=zh-TW 47. Samsung News https://news.samsung.com/us/samsung-galaxy-for-the-planet-samsung-sustai nability-mobile/ 48. SK Hynix News https://news.skhynix.com/caring-for-the-earth-sk-hynixs-green-2030/ 49. Automotive Electronic Council AEC Q104 standard (2014) AEC Q104 failure mechanism based stress test qualification for multichip modules (MCM) in automotive applications 50. Scott K, Chen X, Atkinson JW, Todd M and Armstrong RD (1997) Electrochemical recycling of tin, lead and copper from stripping solution in the manufacture of circuit boards. Resources, Conservation and Recycling 20 (1): 43–55

Chapter 4

Advanced Flip Chip Packaging

4.1 Introduction Flip Chip (FC) technology has been introduced for over 50 years (by IBM in the early 1960s), which is widely used for electronic packaging due to some benefits like smaller form factor, higher UPH (Units Per Hours), direct thermal dissipation path and good electronic performance. With the continued downscaling of device transistor dimension followed by the shrunk interconnection pitch, there are various interconnection types used in flip chip packages are also continuously developed for better reliability performance. As of now, these types have an evolution from C4 (Controlled Collapse of Chip Connection) to Cu pillar and further to micro-Cu pillar bumps. In general, flip chip interconnection using solder bump has an excellent yield due to the self-alignment characteristic of solder material. However, its high solder volume gives some design limitations and consideration for its reliability performance. From assembly perspective, the C4 interconnection with narrower pitch design is not recommended due to the larger space needed for the spherical solder ball, high bridging risk and the concern on effective current-flow path, which lead to Cu pillar bumps become the mainstream of a first-level, advanced FC package interconnect. Furthermore, the micro-Cu pillar bump (or called micro bump) for advanced interconnection pitch required for heterogeneous integration such as GPU (Graphics Processing Unit) and HBM (High Bandwidth Memory) in 2.5D packages, have been already applied for over 10 years. This Chapter will introduce these flip chip packaging technology, the relative assembly processes and the reliability challenges for memory relative packages.

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6_4

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4.2 Flip-Chip Chip Scale Package (FCCSP) Application in Memory Packages FCCSP (Flip Chip Chip Scale Package) is mainly applied for memory, RF (Ratio Frequency), mobile processor, power management, baseband and antenna applications. In the beginning of this Chapter, FCCSP is firstly conducted as most of the mainstream memory makers have selected FCCSP types to manufacture the GDDR (Graphics Double Data Rate) memory product in recently years. It could provide better electrical performance due to shorter route of electrical signals and larger I/O counts. Also, the main processes, such as flipping memory chips and jointing to a strip type substrate through Cu pillar bumps in mass reflow, CUF (Capillary Underfill) or MUF (Molded Underfill) encapsulation are mature assembly processes with relatively stable yield and UPH. However, various die and package structure design and different packaging material selection could still possibly cause some process and reliability issues. In the following Tables 4.1 and 4.2, the recent studies for the FCCSP process and reliability topics which provide some important take-aways are summarized.

4.3 Process and Reliability Failure Modes in Flip-Chip Memory Packages 4.3.1 Thin Die Warpage Induced Joint Failure In the wafer BEoL (Back End of Line) process, Si wafer warpage during processing can be changed due to the CTE mismatch between the various film layers built up within the active metal layers. The driving mechanisms for the warpage is from thick metal films, which is subjected to high processing temperatures and further induce significant tensile stress to warp wafers [9]. Further, the wafer warpage translates into die warpage that has a significant impact on die pick-up, thin die stacking and attaching [10]. Therefore, the BEoL film stress control is one of the key metrology to control die level warpage and further influence the yield of thin die attaching process. To assess the flip chip process risk of thinner die attached using typical mass reflow process, and also the die warpage behaviors with different BEoL thin film stress, a test vehicle with different die thickness (90 and 150 µm) and BEoL film stress are conducted. In Fig. 4.1, the TSM (Thermal Shadow Moiré) results of the 150 µm thick die with BEOL high compressive (HC) film stress shows the warpage lower than 5 µm from 260 to 217 °C, because the Si stiffness still dominate the die warpage variation. In the other wafer condition, the TSM measurement on the 90-µm thick die with identical, high compressive film stress appears the die warpage distribution along diagonal lines has apparent warpage increasing at 217 °C and smiling shape with

4.3 Process and Reliability Failure Modes in Flip-Chip Memory Packages

69

Table 4.1 Recent studies of FCCSP key process take aways Suppliers

Key take aways

References

NCAP China, 2016 • For MUF flow optimization, key factors such as clamp pressure, mold cavity temperature, transfer pressure and transfer time are considered in the process DOE, and the MUF void can be effectively eliminated

[1]

TSMC, 2016

• Solder cap volume and substrate Cu trace width become key design factors that may impact process yield when Cu pillar pitch is shrunk. Possible failure modes include solder non-wetting, bridging, and Cu trace peeling due to low adhesion post reflow process

[2]

SPIL, 2017

• The typical failure modes of MUF FCCSP package listed as [3] follow: – Mold voids – Solder extrusion between pillar bumps – Delamination induced solder extrusion and interconnection short

ASE, 2019

• Not only CTE material property, but chemical shrinkage is also the key for EMC selection to reduce strip warpage • Chemical shrinkage effect can be ignored at molding step since strip side rail was constrained by mold cavity during filling in EMC

Intel, 2022

• In the assembly process evaluation, mechanical properties [5] of molding compound significantly influence strip and package warpage value • CTE1 and shrinkage rate properties improved package warpage in strip form at room temp • CTE2 in combination with Tg and low modulus can reduce Si and overall package stress and effectively reduce warpage value at high temperature

[4]

warpage around −24 µm at 260 °C as shown in Fig. 4.2, which had resulted in the failed bump-on-trace jointing or non-wetting issues at die edge and corner area as shown in Fig. 4.3. With the efforts of decreasing high compressive film stress to lower one, the wafer residual warpage changed post annealing step as well. The residual stress induced die warpage is also expected to be changed at room temperature and supposed to behave lower die warpage at melting temperature (217 °C) as shown in Fig. 4.4. The TSM warpage of flip chip die with different thickness (90 and 150 µm) and BEoL film stress (low and high compressive) varied at different temperature are drawn in Fig. 4.5. The 150 µm die could provide a much stable warpage variation smaller than 13 µm while 90 µm die performs around 40 µm warpage variation during a thermal cycling. Regarding the Cu pillar jointing at solder melting temperature, the 90 µm thinner die with high compressive film stress performs die warpage higher than 10 µm, which had suffered non-wetting yield loss post reflow attaching process. For 90-µm die warpage variation, the trend line is found to shift from negative to positive as the residual strain changed due to film stress tuning, which reduce

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Table 4.2 Recent reliability relative study on FCCSP Suppliers

Key take aways

Amkor, 2015

• Jointing process induced ultra-low k [6] stress: mass reflow is 5× higher than that by TCNCP (thermo-compression bonding with non-conductive paste) • The TCNCP reliability DOE for the control items including Cu pillar diameter and height, passivation types and opening size is concluded that only the leg with short bump height (less solder volume) failed at TCT 1000×, HAST 192 h and HTS 1000 h conditions

References

TSMC, 2016

• CPI (chip package interaction) performance and assembly process characterization for advanced Si node using Cu BoT (Bump on Trace) with different pitch (min. 60 µm) and thermal reflow are investigated • To reduce the Cu pillar bump ELK stress induced by mass reflow process, the following design trend is preferred based on simulation study: – Higher pillar pitch – Smaller aspect ratio of UBM shape (minor axis/major axis of a non-circular UBM) – Smaller PI opening – Lower substrate core CTE

MediaTek, Inc. and STATS ChipPAC, 2018

• The 10 nm chip package interaction [7, 8] (CPI) study in a 15 × 15 mm FCCSP with finer Cu pillar bump pitch of 60 µm and a 2-layer ETS with finer LW/LS design is studied with various chip attaching processes • The utilizations of TCB, TCNCP and LAB chip attach methodologies can reduce the risk of ELK damage. For mass reflow, the optimized reflow profile using lower cooling rate when below 220 °C and lower exit temperature are both used to mitigate the ELK stress • The chip bumped with 90 µm pitch and non-PI Cu pillars is attached by LAB and showed good results that can pass 30× QTC (Quick thermal cycling) test of and MSL3a conditions with 3× IR reflow

[2]

4.3 Process and Reliability Failure Modes in Flip-Chip Memory Packages

71

Fig. 4.1 3D contours and warpage distributions of the 150 µm thick die with BEOL high compressive film stress from melting (260–217 °C) to room temperature

the die warpage at melting temperature (217 °C) and improve the solder jointing performance.

4.3.2 Cu Pillar Bump Abnormality For the purpose to evaluate the FC bump integrity post assembly and reliability conditions, the non-destructive SAM (Scanning Acoustic Microscopy) technology is usually used to determine the location of bump abnormality on the die. “White bump” is one of the failure modes that shows the white spot or halo in C-SAM images, and most of this failures are found at die edge or corner where the bump stress induced by CTE mismatch between Si die and substrate behaves higher. Another kind of abnormality could be also observed from C-SAM image showing the missing or blurry bump pattern. There have been many studies confirmed these abnormal

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Fig. 4.2 3D contours and diagonal distributions of the 90 µm-thick die with BEOL high compressive film stress from melting (260–217 °C) to room temperature

features on the SAT images are the delamination or crack occurring in the ILD (interlayer dielectric) under C4 or Cu pillar bumps [11–13]. This failure mode is an indication that the stresses between chip and substrate are too high and the stress mitigation design is required, such as adding dummy support pillars, pillar height or solder volume optimization. For the purpose to quickly evaluate the CPI performance and bump integrity of new wafer technology introduction, the QTC (−40to 60 °C) or hammer test (multi reflows) using the sample without underfill encapsulation will be conducted. The Cu pillar bump abnormality found on C-SAM images of typical flip chip memory packages are shown in Fig. 4.6. From their further cross-sectional confirmation, the ILD crack or Al pad missing due to chemical corrosion can be observed.

4.4 Flip Chip Bonding Technology

73

Fig. 4.3 Cross-sectional SEM images of 90-µm thick die with different BEoL film stresses

4.4 Flip Chip Bonding Technology 4.4.1 Mass Reflow The mass reflow (MR) process is the most commonly used for C4 or Cu pillar solder jointing for FCCSP GDDR assembly due to its advantages such as high productivity and self-alignment effect of solder material. The CTE mismatch between Si die and strip substrate and the different design of top and bottom metal/lamination ratio could cause the thermal–mechanical stress and warpage during the cooling after solder jointing temperature. To constrain the strip substrate warpage variation during transporting in the reflow oven, the magnetic carrier and cover jigs are generally required in the FC die bonding step. In recent year, high input/output (I/O) density and fine pitch bumping requirements are driving the smaller feature sized Cu pillar bump on a narrow metal pad or BOL interconnection. There is also increased CPI risk and challenges as these advanced packages are assembled in the die bonding process using a standard mass reflow process and still required to maintain its performance. The following Table 4.3 summarizes the recent studies on the FCCSP manufactured by using mass reflow process.

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Fig. 4.4 3D contours and diagonal distributions of the 90 µm thick die with BEOL low compressive (LC) film stress from melting (260–217 °C) to room temperature

Fig. 4.5 Die warpage variation of different die thickness and BEoL film stress versus temperature by TSM measurement

4.4 Flip Chip Bonding Technology

75

Fig. 4.6 Typical Cu pillar bump abnormality observed by C-SAM and SEM cross-section images

4.4.2 TCB (Thermal Compression Bonding) Fine pitch copper bump technology is widely applied in advanced flip chip packages. However, the conventional die attaching using mass reflow has reached its process margin and cannot meet the accuracy requirement of flip chip mounting as the Cu pillar bump pitch shrunk to less than 40 µm. In addition, the warpage variation control of thin die during the reflow process is another tough homework. To address this concern, thermal compression bonding (TCB) was developed to replace the conventional mass reflow process and implemented for packages with high pin count, thinner die, tighter pitch or multi die vertical stacking using pillars with solder cap. In the HBM assembly, the TCB process is also used to sequentially realize the flip-chip attaching between the multi-layer DRAM chips and the logic chip. TCB technology can fix mounting position of the chip using bonding head, and then heat the chip in a very short time to complete solder jointing of one chip

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attaching rapidly. Figure 4.7 shows the typical thermal compression bonding temperature profile from bump solder cap contact, melting, dwelling, till solidification state. As the typical TCB tool can only attach one chip at a time, the throughput is lower as compared with the mass reflow process. Besides, for TCB with a high-bonding force using pillar with solder cap, the bonding process typically need to combine with the Table 4.3 The process and reliability studies for the FCCSP assembled using mass reflow process Suppliers

Key take aways

Samsung, 2012

• Substrate manufactures typically [14] provide substrate warpage within customer’s specification which does not allow much margin left in assembly considering the number of reflows and curing profiles which the package undergoes during assembly • Coreless substrate is thin and not fabricated with rigid core material and glass fabrics. Therefore, it is easy to warp during reflow condition due to material CTE mismatch, or Cu density difference between upper and lower layers • For thermal/mechanical treatment, it was suggested to use cover and carrier jigs. For a proper flip-chip bump formation, the bump area in cover jig was open. Without using cover and carrier jig, warpage was increased obviously after reflowing

References

SPIL, 2015

• The TV is a 19 × 19 mm2 FCCSP [15] package using fine pitch Cu pillar bump (with and without Ni barrier) on trace interconnection and assembled by using traditional mass reflow bonding, and then encapsulated by mold underfill • After mass reflow, Cu–Sn IMC was formed at both the interfaces between Cu post and solder, substrate Cu trace and solder • During electromigration test, the thickness of the Cu6 Sn5 increases until almost all the Sn in the solder is consumed. At the same time, the thickness of Cu3 Sn IMC is continuously growing at the expense of Cu6Sn5, accompanied by the Kirkendall voids formation and the cracks in both Cu3 Sn/Cu post, Cu3 Sn/Cu trace interface and finally lead to failure (continued)

4.4 Flip Chip Bonding Technology

77

Table 4.3 (continued) Suppliers

Key take aways

References

[16] MediaTek and STATS ChipPAC, 2019 • Mass reflow chip attaching has higher risk of a bump to trace shorts, especially when the design using finer bump pitch of less than 60 µm and finer LW/LS utilizing escaped traces • The results of extended thunder and hammer (multi reflows) test indicate that LAB technology can achieves enhance package assembly yield and improved ELK performance over that using mass reflow Amkor, 2022

• Mass reflow shows more solder side [17] wall creep (wicking) than laser assisted bonding and it is expected that MR will be difficult to be applied for devices with smaller bump pitch

NCP (Non-conductive Paste) or NCF (Non-conductive Film) [18]. In the TCNCP process, the NCP material is usually dispensed on top of joint pad area of substrate, unlike pre-applied NCF that is laminated on die surface at the wafer singulation step. NCP is difficult to use for die stacking as the fillet of NCP cannot be controlled, and possibly pollute the bonding head. In recent years, the film type, underfill-like, NCF has become one of most commonly used materials for TSV die stacking. Same as NCP, NCF is also a kind of thermosetting material which becomes soft to fill the gap between dies at high temperature and then starts curing when it cools down to room temperature.

4.4.3 Tack, Gang and Collective Bonding To address the throughput concern in typical TCNCF bonding, a new bonding procedure consisting of tack bonding (or called pre-bonding) and collective bonding (or called main bonding) is developed. This technology had been applied for HBM multiple DRAM die stacking that chips are pre-bonded in approximately one second each and then are collective bonded to complete the solder joints at a time. The dividing could change the process from serial to parallel and enabled to use the constant heated bonder head, which eliminated the time consuming in the head cooling process of the conventional serial TCB [19, 20]. In the multi-die stacking process, NCF behaves like stress dispersion and adhesive layer in between bumps and chips.

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Fig. 4.7 Typical thermal compression bonding temperature profile

To further improve the throughput concern of TCB process used in chip-towafer process, the “gang bonding” technology has been widely developed by the tool suppliers and applied in 3D multi-die staked memory packages such as HBM. The concept of gang bonding is to use a single head to simultaneously bond a plurality of chips which are horizontally placed at different location and preliminarily aligned well. In the early 1990s, gang bonding had been applied in the SMT (Surface Mount Technology) process and ILB (Inner Lead Bonding) of TAB (Tape Automated Bonding) modules [21, 22]. The recent studies have implemented gang bonding technique to the wafer-level multi-chip process using NCF to demonstrate a high productive TCB solution by a process separation from one to two steps [23–25] (Fig. 4.8).

4.4.4 LAB (Laser Assisted Bonding) This flip chip attaching is to use thermal energy to reflow the solder material and mount the chip to the substrate. Laser assisted bonding (LAB) is a new interconnection technology that applies laser heating instead of direct thermal/convectional heating. As compared to conventional reflow, LAB could provide excellent thermal selectivity, good process time control, faster ramping up speed with purely controlled wavelength and stable interconnection quality. Some study had used LAB for flip chip with thin coreless substrate due to its selective heating area availability [26, 27]. By

4.5 Flip Chip Interconnection Types of Memory Packages

79

Fig. 4.8 Process flow and illustration of laser assisted bonding

using the laser to reflow the solder bumps, the thermal stress induced in the package and on the substrate is minimized allowing implementation of new substrates or new wafer tech nodes that are more sensitive to thermal mechanical stress. In Table 4.4, the comparison of different flip chip die attaching technology are listed for reference.

4.5 Flip Chip Interconnection Types of Memory Packages 4.5.1 Types of Cu Pillar Bump The conversion of package technology from wire bonding to flip chip can provide better signal integrity performance in the high-end memory applications which require tighter noise and timing budgets. To address the issue of simultaneous switching noise in the graphic DRAM application due to the current consumption of I/O circuit variation, FC package had been thought as the better assembly solution [28]. In addition, the selection of interconnection type for FC package also

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Table 4.4 Comparison of different flip chip die attaching technology LAB (laser assisted bonding)

MR (mass reflow)

TCB (thermal compression bonding)

Heat source

Laser induced vibration energy absorbed by target material

Convection heating system in reflow oven

Pulse heater in bond head system

Bonding time

~1s

~ 10 min

~5s

UPH

Medium

High

Low

Equipment cost

High

Low

Medium

Package thermal gradient during bonding

Selective local heating on die

Isothermal, global heating

Selective local heating on die

Package warpage (at room temp.)

Low

High

Low

ILD Stress

Low

High

Low

Force applied during bonding

N/A

N/A

By bond head

Temperature control

By laser power

By setup of temperature Pulse heater in bond at different heating zone head system in reflow oven, and conveyor speed

Environment control

N/A

Nitrogen or forming gas N/A are used. Oxygen control required

plays an important role for its electrical and reliability performance. In the recent graphic DRAM products, Cu pillar solder bump becomes the mainstream interconnection type and many studies have compared the reliability performance of different Cu pillar structures such as the pillars with and without Ni barrier layers [29]. In Figs. 4.9 and 4.10, the SEM images show the morphology of these two kinds of Cu pillar bumps as deposited by using FIB/SEM (Focused Ion Beam/Scanning Electron Microscope), to avoid noise forming during the mechanical polishing. Further, the Cu pillar bumps without Ni barrier are assembled by multi reflow, and further cross sectioned to check the IMC distribution of Cu3 Sn and Cu6 Sn5 . The following Table 4.5 provide the summary of research on the Ni-free Cu pillar bumps and their key take aways.

4.5 Flip Chip Interconnection Types of Memory Packages

81

Fig. 4.9 Cross-sectional images of Cu pillar bump with and without Ni barrier

Fig. 4.10 Map of element distribution in cross-section of the Cu pillar bump without Ni Barrier

4.5.2 Substrate Technology in Flip-Chip Memory Package In recent years, the substrate technology used for FCCSP is typically 2L (2 Culayered) or 4L (4 Cu layered) BOL (Bond on Lead) substrates, and some products have started to apply ETS (Embedded Trace Substrate) technology. The BOL

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Table 4.5 Recent studies of for the flip chip package using Cu pillar with and without Ni barrier Suppliers

Key take aways

IBM, 2011

• The electrical resistance increments [29] during the electromigration (EM) test of Cu/Sn/2.5Ag with and without aging process (150 °C, 2000 h) and Cu/Ni/Sn100 pillar bumps are compared • Cu/Ni/Sn100 pillar has the thinner IMC layer and appears largest resistance increment • The Cu/Sn/2.5Ag with aging process before EM has the thickest IMC layer and shows a smallest resistance increment

References

Université Grenoble Alpes & CEA, LETI, 2017

• The processing, microstructure and [30] mechanical reliability of Cu/SnAg and Cu/Ni/SnAg pillar bumps were examined • Ni layer could suppress the micro-voids and IMC growth (~2–3 µm IMC for the pillar without Ni layer and ~ 1 µm IMC for that with Ni layer) • Before multi-reflow, the shear strength of Cu/Ni/SnAg pillar has around double than Cu/SnAg one. However, Cu/Ni/SnAg pillar has only 19% tougher post 5x reflows, which is smaller than Cu/SnAg with 74% tougher shear strength • The fracture post pillar shear test is always in the solder regardless of IMC growth

ASE, 2018

• The Cu6 Sn5 IMC is the most sensitive [31] to high temperature storage condition (2000 h), which grows 3 to 10 mm • Cu6 Sn5 IMC will convert to Cu3 Sn IMC at the initial stage, followed by the Kirkendall void appearing at the interface of Cu and Cu3 Sn IMC, which may lead to the quality issue once the void density increased (continued)

substrate or the BOT (Bump on Trace) interconnection using Cu pillar bumps with a lead-free solder cap connected to a narrow trace without any solder resist confinement is a novel packaging solution for low cost and small form-factor applications. To take a deep look on the recent substrate design for graphic DDR flip-chip packages from memory industry leaders, the Cu trace surface finish using OSP (Organic Solderability Preservative) to be jointed with the Cu pillar solder bumps has become the mainstream technology that can provide cost-wise, high yield process benefits.

4.6 Advanced Heterogeneous Integration for HBM

83

Table 4.5 (continued) Suppliers

Key take aways

National Chiao Tung University, 2012

• The liquid-state metallurgical reactions [32] in micro-bumps with two solder thicknesses (4 and 6.2 µm) are studied • Theoretical calculations indicated that the Ag concentration increases with reflow, because Sn reacts with the Ni UBM to form Ni3 Sn4 IMCs, thus increasing the Ag concentration in the remaining solder with reflow time, which facilitates the formation of large Ag3 Sn precipitates during the cooling stage • These large Ag3 Sn inclusions may be detrimental to the mechanical properties of the micro-bumps

References

OSP is an organic compound that selectively bonds to copper as an anti-corrosion coating until soldering. In conventional flip chip process, the OSP could be dissolved in flux material that is from flux dipping or jetting steps. Figure 4.11 illustrates the brief manufacturing process flow for the BOL substrate.

4.6 Advanced Heterogeneous Integration for HBM In this section, the recent (within 10 years) new assembly technologies as a solution for multi-die, heterogeneous integration are discussed here. The leaders in advanced packaging industry are continuously developing the evolutionary structure to be more competitive and to achieve cost-wise, higher process yield and productivity, better power efficiency and reliability performance. Silicon interposers with TSV (Through Silicon Via) is one of the technologies could enable heterogeneous stacking of ASIC dies and memories. However, the high cost of interposer wafer fabrication will diminish the relative product’s competitiveness.

4.6.1 2.1D Technology To address the process limits (such as laser drilling, electroless Cu plating or desmearing) of traditional FC-BGA substrate manufacturing, and to meet the demand for miniaturization and high-density interconnection, the new substrate technology featured with narrower pitches and finer wiring dimensions was developed [33, 34]. This organic substrate used for multi-chip or heterogeneous integration is the socalled “2.1D” packages. The key benefits of this built-on organic interposer on

84

Fig. 4.11 Manufacturing process flow for the BOL substrate

4 Advanced Flip Chip Packaging

4.6 Advanced Heterogeneous Integration for HBM

85

Fig. 4.11 (continued)

substrate could eliminates backside C4 or Cu pillar bumps of conventional Si interposer used in 2.5D packages. Furthermore, the fine resin layers become much thinner than a Si interposer. The following Fig. 4.12 shows an illustration of 2.1D FCBGA packages assembled with organic interposer build on substrate frontside with fine lines and thin film RDL layers. Some recent approaches focusing on fine line or via fabrication on panel size substrate were investigated [35, 36]. The 3-um-width copper fine lines and the 25-um laser drilled vias were manufactured using large-sized panel processes by applying large field projection lithography and dry film photoresist. For 2.1D PCB (Printed Circuit Board) panel interposer, the plasma etching had been validated to be good for the fabrication of the fine via pattern with low surface roughness in ABF film which

Fig. 4.12 Schematic illustration of 2.1D FCBGA packages using substrate with fine line and thin film RDL layer

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is usually used as low- CTE build-up layer. Further, many recent studies have implemented the L/S of 2/2 um in the organic substrate [37, 38]. The HBM interconnect was achieved in four metal layers with an L/S of 2/2 um, and the 5 um-diameter vias through a very thin photopolymer layer less than 4 µm thick. Besides, the HAST reliability condition for 2.1D assembly with 2/2 um fine L/S was also evaluated. Due to the shrinkage of L/S of the organic substrate, the electrical characterization of fine lines was also investigated using TDR (Time Domain Reflectometry) to measure their impedance [39]. In 2.5D application, silicon interposer behaves like a stress buffer between top die micro bumps and substrate. However, the 2.1D assemblies may have potential risk such as misalignment and high stress of the micro-Cu pillars post mass reflow process, especially for the application with larger die dimension. There have been some investigations proposing the solution to minimize the offset between Cu pillar bumps and substrate, and the stresses induced during assembling [40]. Recently, a comprehensive study on the warpage, stress behaviors and reliability performance of 2.1D packages is conducted [41]. The micro joint misalignment has been numerically predicted and successively resolved by TCB implementation. The results showed that micro bump joining by TCB had a 45% misalignment improvement as compared to mass reflow process. In stress simulation results, the ELK layer stress in the micro bump using TCB has a 59% reduction than that by mass reflow.

4.6.2 2.3D Technology The 2.3D packaging technology is a novel heterogeneous integration solution proposed by substrate manufacturer in 2019 [42]. Different from 2.1D structure, the high-density organic package named “i-THOP” (Integrated Thin film High density Organic Package) is developed to bond the organic interposer on the build-up substrate by pre-applied NCF (Nonconductive Film). As shown in Fig. 4.13, the interconnections between organic interposer and substrate frontside build-up layers are comprised of low temperature solder (Sn–Bi) and copper posts. The key take-away information and further investigation on the reliability performance and extended application of this 2.3D packages are listed in Table 4.6.

4.6.3 2.5D Technology The 2.5D packaging technology enables heterogeneous assembling of ASIC and memory dies, which has been applied in many products for years. The key features in 2.5D package is the Si interposer with TSV assembled with heterogeneous IC chips (such as GPU and HBM) and build-up substrate. As shown in Fig. 4.14, the chip module is briefly comprised of ASIC/logic dies, memory cubes (HBM), Si interposer, micro-Cu pillars, interposer backside Cu pillars, underfill and molding compound.

4.6 Advanced Heterogeneous Integration for HBM

87

Fig. 4.13 Schematic illustration of 2.3D FCBGA packages with fine line and thin film RDL interposer

There have been many wafer process flows to be proposed for 2.5D package manufacturing [47]. The demand on continuous performance enhancement requires a larger interposer area capable to bond with more ASIC dies and HBM cubes. However, the material’s CTE-mismatch induced chip module (or called molded interposer) warpage is not easy to control when the interposer size increased. The industries have studied its thermal warpage behaviors and the corresponding solutions to improve the process yields and reliability of the FC process attaching large, molded interposer on substrate [48–51].

4.6.4 EMIB Technology In 2016, the world’s famous semiconductor chip manufacturer, Intel, proposed a high density, high bandwidth packaging interconnect solution called “EMIB” (Embedded Multi-Die Interconnect Bridge) which could provide better electrical performance by discarding the popular Si interposer structure with TSV, but still keep the flexibility of heterogeneous integration by embedding a small Si bridge die into the substrate [52]. As illustrated in Fig. 4.15 [53], the computing chips modules and HBM packages are connected to one half of the Si bridge die embedded in substrate. The EMIB die has hundreds or thousands of connections each side and has the benefit of transferring data through silicon without the restrictions brought by the large interposer. Further, the cost of Si bridge die is significantly reduced as its size much smaller than a large interposer. In the recent publication from Intel, the EMIB architecture shows that a thin silicon bridge with four metal layers and one pad layer is embedded in the top two layers of an organic package, and it acts as a localized interconnect between two dies.

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Table 4.6 Recent key research take aways for the 2.3D package technology Suppliers

Key take aways

References

SHINKO, 2019~2021 • The detailed process flow of the organic interposer [42–44] stacking on build-up substrate is presented • 2.3D package warpage with/without stiffener ring, with/without FC die attaching are measured and 2 mm stiffener ring thickness is preferred • Transient Liquid Phase (TLP) technique using Sn-Bi solder has been employed for solder joints between organic interposer and build-up substrate. From the cross-sectional SEM observation, NCF entrapment between the Si-Bi solder and Cu post interface was observed. Design compensation for solder alignment may need to be considered • From the electromigration evaluation, maximum resistance increase of solder joint between organic interposer and build-up substrate is 4%, which is lower than 83% measured from conventional flip chip joint using Sn-Bi Solder Samsung, 2021

• Cost wise 2.3D package solution is performed by applying panel level package (PLP) interposer and conventional coarse pattern substrate • The manufactured PLP Interposer was attached to an 8 layered coarse pattern substrate using a solder joint with pitch 0.4 mm and the joint gap 150 µm

[45]

Unimicron, 2022

• To replace PID (photo-imageable dielectric), Ajinomoto [46] build-up film (ABF) was implemented as the dielectric material to fabricate the fine line RDL-layer in the hybrid substrate. It is fabricated by a fan-out chip-last (RDL-first) process on a large temporary glass carrier (515 mm × 510 mm) • In this 2.3D packages, the interconnection between the fine metal L/S/H (line width/spacing/thickness) RDL-substrate and the build-up package substrate is the C4 (controlled collapse chip connection) solder joints and the gap is dispensed by underfill

Table 4.7 [54] list down the key features of the embedded silicon bridge in EMIB technology.

4.6.5 Si Bridge Technology Around 4 years after EMIB technology was first proposed in 2016 [52], the new package architecture that places a smaller silicon bridge die in the shadow of copper pillar bumps and to connect PHY of logic and memory die is proposed [55]. Unlike EMIB technology that carves out a cavity in the substrate, Si bridge technology can lithographically define this module as a unit without dealing with micro bumps on

4.6 Advanced Heterogeneous Integration for HBM

89

Fig. 4.14 Schematic illustration of 2.5D FCBGA packages with Si interposer

Fig. 4.15 Real product, schematic illustration and exploded viewing of EMIB new application [53] Table 4.7 Key features of the silicon bridge die [54] Attributes

EMIB features

Bridge size range • 2 mm × 2 mm ~ 12 mm × 12 mm (Higher size possible) Metal layers

• 4 metal layers + pad layer in production; higher number of metal layer possible • Metal layers can be used for signal routing or for power distribution • Line/space > 1 µm/1 µm in production; sub 1 µm features are possible • Via-fully landed on metal line

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Fig. 4.16 Schematic illustration of heterogeneous integration using Si bridging die in FCBGA packages

the substrate [56]. Figure 4.16 shows the schematic illustration of heterogeneous integration using Si bridging die in FCBGA packages.

4.7 Summary and Recommendations This Chapter introduce the flip chip packaging technology, the relative assembly processes and the reliability challenges for memory relative packages. Some important research results and recommendations are summarized as follows. For die bonding process yield and reliability improvement: . Solder cap volume and substrate Cu trace width become key design factors that may impact process yield when Cu pillar pitch is shrunk. Possible failure modes include solder non-wetting, bridging, and Cu trace peeling due to low adhesion post reflow process. . CPI (Chip Package Interaction) performance and assembly process characterization for advanced Si node using Cu BoT (Bump on Trace) with different pitch (min. 60 µm) and thermal reflow are investigated. . To reduce the Cu pillar bump ELK stress induced by mass reflow process, the following design trend is preferred based on simulation study: – Higher pillar pitch – Smaller aspect ratio of UBM shape (minor axis/major axis of a non-circular UBM) – Smaller PI opening – Lower substrate core CTE.

References

91

. The utilizations of TCB, TCNCP and LAB chip attach methodologies can reduce the risk of ELK damage. For mass reflow, the optimized reflow profile using lower cooling rate when below 220 °C and lower exit temperature are both used to mitigate the ELK stress. . The BEoL film stress control is one of the key metrology to control die level warpage and further influence the yield of thin die attaching process. For MUF encapsulation process yield and reliability improvement: . For MUF flow optimization, key factors such as clamp pressure, mold cavity temperature, transfer pressure and transfer time are typically considered in the process DOE to effectively eliminate MUF voids. . Not only CTE material property, but chemical shrinkage is also the key for EMC selection to reduce strip warpage. . Chemical shrinkage effect can be ignored at molding step since strip side rail was constrained by mold cavity during filling in EMC. . In the assembly process evaluation, mechanical properties of molding compound significantly influence strip and package warpage value. . CTE1 and shrinkage rate properties improved package warpage in strip form at room temp. . CTE2 in combination with Tg and low modulus can reduce Si and overall package stress and effectively reduce warpage value at high temperature. The recent (within 10 years) new assembly technologies including 2.1D, 2.3D, 2.5D, EMIB and Si embedded bridge assembly structurer which can be used as a solution for multi-die, heterogeneous integration are briefly summarized here.

References 1. Sun P, Xu C, Lid J, Geng F, Cao L (2016) Flip chip CSP assembly with Cu pillar bump and molded underfill. In: 2016 17th international conference on electronic packaging technology, pp 807–811 2. Lin YL, Liu CS, Yu D (2016) Ultra fine pitch/low cost FCCSP package and chip package interaction (CPI) for advanced CMOS nodes. In: 2016 IEEE 66th electronic components and technology conference, pp 595–599 3. Tsai WS, Huang CY, Chung CK, Yu KH, Lin CF (2017) Generational changes of flip chip interconnection technology. In: 2017 12th international microsystems, packaging, assembly and circuits technology conference (IMPACT), pp 306–310 4. Wang MH, Chen KY, Lin GH, Cheng F, Shih MK, Yen SF (2019) Strip warpage evaluation after FCB and molding procedure. In: 2019 IEEE CPMT symposium Japan (ICSJ), pp 205–208 5. Mesa ED, Wagner T, Keser B, Proschwitz J, Waidhas B (2022) Flip-chip chip scale package (FCCSP) process characterization and reliability of coreless thin package with 7 nm Si technology. In: 2022 IEEE 72nd electronic components and technology conference (ECTC), pp 266–270 6. Park JY, Kim YH, Na SH, Kim JY, Lee CH, Nicholls L (2015) High reliability packaging technologies and process for ultra low k flip chip devices. In: 2015 IEEE 65th electronic components and technology conference (ECTC), pp 1–6

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7. Chen CY, Hsu I, Lin S, Kang KT, Hsieh MC (2018) Various chip attach evaluations in a fine bump pitch and substrate flip chip package. In: 2018 IEEE 68th electronic components and technology conference, pp 643–648 8. Chen CY, Hsu I, Lin S, Park DS, Hsieh MC (2018) Laser assisted bonding technology enabling fine bump pitch in flip chip package assembly. In: 2018 7th electronic system-integration technology conference (ESTC) 9. Ostrowicki GT, Gurum SP, Nangia A (2018) Correlated model for wafer warpage prediction of arbitrarily patterned films. In: 2018 IEEE 68th electronic components and technology conference, pp 2110–2114 10. Abdelnaby AH, Potirniche GP, Barlow F, Elshabini A, Groothuis S, Parker R (2013) Numerical simulation of silicon wafer warpage due to thin film residual stresses. In: 2013 IEEE workshop on microelectronics and electron devices (WMED) 11. Feger C, LaBianca N, Gaynes M, Steen S, Liu Z, Peddi R, Francis M (2009) The over-bump applied resin wafer-level underfill process: process, material and reliability. In: 2009 59th electronic components and technology conference, pp 1502–1505ss 12. Peng SL, Huang CY, Yang MH, Tseng S, Lai JY, Lu T, Chen HW, Chiu S, Chen S (2014) Integration study of die strength and various bumping volume and reliability performance on 2.5D silicon interposer assembly. In: 2014 IEEE 64th electronic components and technology conference (ECTC), pp 1–7 13. Islam N, Pandey V, Kim KO (2017) Fine pitch Cu pillar with bond on lead (BOL) assembly challenges for low cost and high performance flip chip package. In: 2017 IEEE 67th electronic components and technology conference, pp 102–107 14. Kim J, Lee S, Lee J, Jung S, Ryu C (2012) Warpage issues and assembly challenges using coreless package substrate. In: Proceedings of IPC APEX/EXPO 15. Kuo KH, Mao C, Wang K, Lee J, Chien FL, Lee R (2015) The impact and performance of electromigration on fine pitch cu pillar with different bump. In: 2015 IEEE 65th electronic components and technology conference, pp 626–631 16. Hsu I, Chen CY, Chen, Lin S, Yu TJ, Cho NJ, Hsieh MC (2019) 7 µm chip-package interaction study on a fine pitch flip chip package with laser assist bonding and mass reflow technology. In: 2019 IEEE 69th electronic components and technology conference (ECTC), pp 289–293 17. Na S, Gim M, Kim C, Park D, Ryu D, Park D, Khim J (2022) Next gen laser assisted bonding (LAB) technology. In: 2022 IEEE 72nd electronic components and technology conference (ECTC), pp 1991–1995 18. Lau JH (2017) Status and outlooks of flip chip technology. In: IPC EXPO proceedings, February 2017, pp 1–20 19. Nonaka T, Kobayashi Y, Asahi N, Niizeki S, Fujimaru K, Arai Y, Takegami T, Miyamoto Y, Nimura M, Niwa H (2014) High throughput thermal compression NCF bonding. In: 2014 IEEE 64th electronic components and technology conference (ECTC), pp 913–918 20. Asahi N, Miyamoto Y, Nimura M, Mizutani Y, Arai Y (2015) High productivity thermal compression bonding for 3D-IC. In: IEEE 2015 international 3D systems integration conference, pp TS7.3.1–TS7.3.5 21. Schiebel G, Munich SA (1992) Automatic gang bonding, the alternative process. In: 12th international electronic manufacturing technology symposium, pp 146–154 22. Hayashi N, Naito H, Osada O, Adachi Y, Kubota Y, Yoshifuku T, Atsumi K, Yamaya Y, Takeno S, Nakano H (1989) Development of TFT-LCD TAB modules. In: Proceedings Japan IEMT symposium, sixth IEEE/CHMT international electronic manufacturing technology symposium, pp 79–82 23. Ahn SG, Kim HK, Kim DW, Hiner D, Kim KS, Hwang TK, Lee MJ, Kang DBYJH (2016) Wafer level multi-chip gang bonding using TCNCF. In: 2016 IEEE 66th electronic components and technology conference, pp 122–127 24. Asahi N, Mizutani Y, Imai K, Tanaka H, Hashimoto Y, Jinda T, Kawakami M, Terada K (2018) Multi-chip gang bonding technology using the thermo-compression bonder for Si substrate. In: 2018 International conference on electronics packaging and iMAPS All Asia conference (ICEP-IAAC), pp 496–499

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Chapter 5

Second Level Interconnect Reliability of Low Temperature Solder Materials Used in Memory Modules and Solid-State Drives (SSD)

5.1 Introduction The purpose of this chapter is to provide an overview of current and future deployment of second level interconnect reliability on types of second level solder alloys used in semiconductor assembly and packaging. Also, with the aim to study the key technical barriers, challenges of deployment and its reliability performance of different solder alloy interconnect reliability requirements in semiconductor device packaging by different market segments. This chapter lays out the benefits of introducing low temperature solder paste (LTS) in semiconductor memory assembly and its second level reliability performances. Factors influencing Solder Joint Reliability (SJR) and board level drop performances also being included in this chapter. Finally, key future potential applications of deployment of LTS are covered before end of the chapter summary. At the end of this chapter, summary and key recommendation of future works have been provided for better clarity and reference purposes.

5.2 Second Level Interconnects 5.2.1 Solder Joint Interfacial Reactions (Surface Finish and the Formation of Intermetallic Compounds) Electrolytic, electroless-plating process and organic solderability preservative (OSP) technology have been used in surface finish of integrated circuit pads and printed circuit boards (PCB) for many years, such as electrolytic Ni or Au, electroless nickel immersion gold (ENIG), electroless nickel or palladium immersion gold (ENEPIG). Electrolytic-NiAu is electro-plated as well as ENIG and ENEPIG surface finishes are chemical-plated on Cu pad to prevent Cu consumption. In addition, ENIG and © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6_5

95

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5 Second Level Interconnect Reliability of Low Temperature Solder …

ENEPIG have been extensively used as surface finish in high-density and fine space application [1]. OSP is another promising option with tens to hundreds of nanometers of coating on exposed Cu metallization, which provides the prevention of Cu surface oxidation and a flux-cleanable surface. Choosing the OSP eliminates the possibility of Au–Sn intermetallic compound (IMC) embrittlement and has the advantages of good solderability, low cost, simple processing, and environment friendly [2]. Different solder alloy compositions associated with substrate and PCB surface finishes could affect material properties of bulk solder as well as forming several types of IMCs at bulk solder and joint interface, which gives significant influence on the performance of solder joint reliability. Table 5.1 shows that a slight variation in Cu content of solder alloy could produce completely different reaction products on Ni substrate [3, 4]. IMC growth is highly temperature-dependance, and interfacial IMC strength decreases with the increases of thermal aging. Therefore, interfacial IMC thickness is identified as an index of solder joint performance. The behavior of interfacial IMC growth was found to increase linearly with the square root of aging time as Eq. (5.1), and the growth rate constant was calculated to be the slope of regression curve of x versus tn. The n value of IMC layer is near 0.5, which is evidence of the growth mechanism controlled by diffusion [4]. x = Dt n

(5.1)

where x is the thickness of reaction layer; D is the growth rate constant; n is the time exponent; and t is the reaction time. The following Arrhenius Eq. (5.2) was used to determine the activation energy for IMC growth: D 2 = D02 exp(−Q/RT )

(5.2)

where D2 is the square of growth rate constant (m2 /s), D02 is the frequency factor, Q is the activation energy, R is the gas constant 8.314 J/ (mol ·K) and T is the aging temperature (absolute units). Table 5.2 summarizes activation energy of IMC growth from the reaction of solder alloy and substrate surface finish. The activation energy of Ni–Sn IMC growth is generally lower than that of Cu–Sn IMC growth, which means that Ni–Sn diffusion must get over larger energy barrier than Cu–Sn diffusion for the formation of IMCs. Therefore, the growth rate of Ni–Sn IMC is slower than that of Cu–Sn IMC. Table 5.1 Interfacial IMC layer of solder alloy with different Cu% on Ni substrate

Cu content (wt%) Interfacial IMC layer 0.2

Ni3 Sn4

0.4

(Ni, Cu)3 Sn4 and (Cu, Ni)6 Sn5

0.7–1.0

(Cu, Ni)6 Sn5

Reference [3, 4]

5.3 Shear Strength of Interfacial IMCs

97

Table 5.2 Activation energy of different reaction couples Reaction couples

Calculated IMC layer

Temperature range (°C)

Activation energy (Q, kJ/mol)

References

Sn3.5Ag/Ni–P

Ni3 Sn4

70–170

49

[5]

Sn3.5Ag/Cu

Cu6 Sn5 , Cu3 Sn

70–170

64.82

[6]

Sn1.5Ag0.7Cu9.5In/Cu

Cu6 (Sn, In)5

130–170

70.9

[7]

Sn3.8Ag0.7Cu/Cu

Cu6 Sn5 , Cu3 Sn

120–190

88.23

[8]

Sn3.8Ag0.7Cu1Bi/Cu

Cu6 Sn5 , Cu3 Sn

120–190

117.87

[9]

Sn3.0Ag0.5Cu/ENIG

(Cu, Ni)6 Sn5

80–150

38.59

[10]

5.3 Shear Strength of Interfacial IMCs Solder joint is always a weak point under board level reliability stressing, and interfacial IMC break can be often seen during failure analysis. W. H. Zhu et al. report that OSP surface finish showed better drop lifetime than NiAu surface finish regardless of the type of SAC305, SAC105 and SAC105–Ni solder alloy used in the assemblies. Moreover, drop impact failures were found to occur at multiple locations, which is mainly the interfacial IMC fracture at either board side or component side [11]. Thus, interfacial IMC strength associated with the design of solder alloy and surface finish is critical to drop impact performance. To have quick assessment prior to mechanical shock, solder ball shear test after multi-reflow or elevated temperature storage is conducted for creating IMC break mode and characterizing IMC strength. Zhang et al. [12] reports that Sn–Ag and Sn–Ag–Cu solder alloy with OSP surface finish shows greater shear strength than the alloy with ENIG after reflowing. However, the shear strength being reduced significantly during the subsequent aging period due to the excessive growth of the interfacial IMCs. The mechanism was claimed that Au–Sn IMC makes the joint susceptible to brittle failure [12]. Zou et al. [13] investigates that interfacial shear strength of SAC–Ni–Bi on Cu–OSP is greater than that of electrolytic NiAu after 3-times reflow. In addition, fracture analysis after ball shear test indicates a continuously thin IMC layer, (Ni, Sn)3 Sn4 , remained on electrolytic Ni layer as shown in Fig. 5.1a. It exhibits the crack induced by shear stressing is prone to propagate along with the interface of IMCs rather than the interface between bulk solder and IMC. By contrast, Kirkendall voids were found in Cu–OSP group as shown in Fig. 5.1b, but the break area was not along with it. The result implies good adhesion strength between (Cu, Ni)6 Sn5 and Cu3 Sn as well as weak adhesion between (Cu, Ni)6 Sn5 and (Ni, Cu)3 Sn4 [13].

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Fig. 5.1 Interfacial images of a (Ni, Cu)3 Sn4 IMC layer from SAC alloy on ENEPIG; b Kirkendall voids observed from SAC alloy on Cu–OSP

5.3.1 Kirkendall Effects and Formation of Kirkendall Voiding The Kirkendall effect refers to the motion of the interface between two metals that resulted from the difference in diffusion rates of the metal atoms. Figure 5.2 shows the schematic mechanism of formation of Kirkendall voids. When metal A is higher diffusion rate than metal B, Kirkendall voids caused by imbalance diffusion fluxes always formed at metal A side with high diffusion rate. Intense Cu–Sn interdiffusion of Pb free SnAg Cu (SAC) on Cu–OSP (Organic Solderability Preservative) induces the formation of Kirkendall voids. The mechanism has been reported in the literature that Cu6 Sn5 forms first, and then the transformation of one molecule of Cu6 Sn5 to Cu3 Sn releases three Sn atoms as Eq. (5.3), which will attract nine Cu atoms to form three molecules of Cu3 Sn as Eq. (5.4).

5.3 Shear Strength of Interfacial IMCs

99

Fig. 5.2 The schematic diagram of formation of Kirkendall voids

Cu dominates interdiffusion in Cu3 Sn because the sublattices have three times more Cu than Sn. The diffusion of nine Cu atoms requires the opposite diffusion of nine vacancies [14]. Cu6 Sn5 → 2 Cu3 Sn + 3 Sn

(5.3)

3 Sn + 9 Cu → 3 Cu3 Sn

(5.4)

The mitigation of Kirkendall voids forming at the interface has been widely discussed in recent years. Alloy dopants, nanotwins in preferred orientation, and Cu grain size are most common solutions to reduce Cu diffusion rate of solder joint interface and the growth of Cu3 Sn. Wang et al. reported that Kirkendall voids were observed only when the Cu is electroplated. It was proposed that impurities in electroplated Cu helped the nucleation of these voids. The Ni additions made the Cu3 Sn layer thinner. For the case of electroplated Cu substrates, the amount of Kirkendall voids decreased correspondingly with the Ni additions [15]. Liu et al. [16] reported that the densely packed nanotwins in highly (111)-oriented Cu can eliminate the formation of Kirkendall voids in solder joint reactions. It was observed that no formation of Kirkendall voids at the interface of the nano-twinned Cu. This was due to the high density of steps and kinks on the nano-twin boundaries, which serve as vacancy sinks. Thus, the vacancy concentration cannot reach supersaturation and nucleate voids [15]. In addition, Chan et al. [17] reported that when the grain boundaries were dense, a lot of vacancies aggregated to form voids at Cu3 Sn/Cu interface. However, when the grain boundaries were sparse, vacancies are few to form voids, but they still exist in the copper deposit. Since the grain size of Cu was inversely proportional to the density of Cu grain boundary, the Cu grain size strongly affected the interfacial microstructure of Sn or Cu joint, the larger is better.

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5.4 Solder Joint Reliability Fatigue behavior and mechanical shock on solder joint reliability of electronic products are considered. Fatigue crack of bulk solder is typically stressed by temperature cycling test, and main failure mode of drop shock test is IMC break at solder joint interface. Three different applications including hand-held, computing, and automotive in memory industry are briefly classified.

5.4.1 Requirements for Hand-held Application The mainstream of handheld device is trending toward miniaturization, pocket-sized, portable, light, and thin. Package form and material dimension are designed to be thinner and narrower, but thinner Cu trace and pad of substrate with intense Cu– Sn reaction during thermal stressing results in less margin on Cu consumption. Therefore, Ni barrier is always designed on the top of Cu trace. On the other hand, reliability problems have been reported when using Ni/Au coatings with Sn-based solders, especially when using the electroless Ni/immersion Au finish [18]. Electroless Ni–P shows more complex system on interfacial solder reaction as compared to Electrolytic-NiAu without phosphorus layer, and Ni–P and Ni–Sn–P IMCs of electroless Ni–P system at the joint interface leads voiding issues during thermal stressing as shown in Fig. 5.3. In summary, electrolytic-NiAu is the recommended surface finish with the consideration of thin Cu pad and reliability. For field application of handheld devices, solder alloys with softer mechanical properties are commonly designed to meet the criterion of drop shock. SAC305 and SAC302 are conventional types with a balance performance of temperature cycling and drop shock, SAC105 and SACN105005 with lower Ag content gives better drop performance than SAC305 and SAC302. Additionally, SACN105005 with few Ni Fig. 5.3 Interfacial image of NiSnP IMC formed from Sn alloyed with Ni-P system

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Table 5.3 Interfacial IMCs of common solder alloy and substrate surface finish of handheld device [13] Solder alloy

Substrate surface finish

Packaging level interfacial IMCs

SACN105005

eNiAu

(Cu, Ni)6 Sn5 , (Ni, Cu)3 Sn4

SAC105

eNiAu

(Cu, Ni)6 Sn5 , (Ni, Cu)3Sn4

SAC302

eNiAu

(Ni, Cu)3 Sn4

SAC305

eNiAu

(Cu, Ni)6 Sn5 , (Ni, Cu)3 Sn4

Table 5.4 Interfacial IMCs of common solder alloy and substrate surface finish of computing application Solder alloy

Substrate surface finish

Packaging level interfacial IMCs

References

SAC405N005i–Bi

Cu–OSP

(Cu, Ni)6 Sn5 , (Cu, Ni)3 Sn

[13]

SAC405N005i–Bi

eNiAu

(Cu, Ni)6 Sn5 , (Cu, Ni)3 Sn

[13]

dopants is recommended to Cu–OSP surface finish for suppressing the growth of IMC layer. Multiple combinations of solder alloys on electrolytic-NiAu are tabulated in Table 5.3.

5.4.2 Requirements for Computing Application For those non-handheld devices that executes calculations and data storage are widely used in servers, desktop, and laptop computers. In those operation environments, the performance of temperature cycling test is main challenge rather than drop shock. Without the consideration of drop shock, solder alloy selection could have harder mechanical properties, and both Copper-Organic Solderability Preservative (Cu– OSP) with electrolytic Ni–Au (eNiAu) are recommended (as depicted in Table 5.4).

5.4.3 Automotive Applications Electronic systems have become an increasingly large component of the cost of an automobile, from only around 5% of its value in 1970 to around 50% in 2030 [19]. Lots of electronic devices are used in vehicles, including engine and power management, telecommunication, autonomous driving system, safety feature systems and so on, and meanwhile safety concern of automotive electronics is being raised. When safety and durability are connected to harsh reliability environment of electronic

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Table 5.5 Interfacial IMCs of common solder alloy and substrate surface finish of automotive application [13]

Solder alloy

Substrate surface finish

Packaging level interfacial IMCs

SAC405N005i–Bi

Cu–OSP

(Cu, Ni)6 Sn5 , (Cu, Ni)3 Sn

products, solder joint design (as tabulated in Table 5.5) is pushed to extremely high performance of temperature cycling, power cycling and hot temperature storage. New solder alloy design with harder mechanical properties must be considered to enhance temperature cycling performance. Moreover, the interfacial IMC layers should not be designed to be too brittle inducing IMC break during mechanical shock. Cu–OSP surface finish is recommended to automotive application because IMCs of Cu–OSP give higher interfacial strength on shear test as compared to that of NiAu. However, severe Cu consumption is driven by thermal stressing of harsh reliability conditions, so the design of Cu pad must be moving to thicker and additional dopants in solder alloy shall play the function of the decrease of Cu–Sn diffusion. Interconnect materials reliability and properties play a pivotal role in emerging memory device packaging. This includes both first level and second level semiconductor interconnects. Solder joint reliability will continue to become the main topic of discussion for the next decades in system level interconnection. Newer solder alloys evolutions are needed to address the needs for diverse applications in automotive, handheld, and high-performance computing.

5.5 Low Temperature Solder Paste (LTS) 5.5.1 Why LTS? Recently however, a technical driver for low temperature soldering has surfaced due to demands for slimmer and lighter electronic products with increasing performance. This has fostered the use of ultra-thin electronic packages. Reduction in package thickness creates new challenges of reflow soldering assembly. Due to various mismatches in the coefficient of expansion (CTE) of materials comprising these electronic packages, their resultant warpage increases markedly at the current SAC reflow temperatures. Reducing the reflow peak temperature improves the surface mount technology (SMT) margin by reducing the dynamic warpage and keeping the ball and paste in contact during reflow [20–22]. The replacement of tin–lead (SnPb) by SAC solder alloys brought many changes to the electronics assembly and packaging segments. For example, SAC305 (96.5% tin, 3% silver, 0.5% copper) melts between 217 and 221 °C and requires reflow temperatures of at least 240 to 255 °C. This represented an increase of 20–35 °C in reflow temperatures. Consequently, PCBs and components were redesigned to include materials that could withstand the higher reflow temperatures required by SAC solder

5.5 Low Temperature Solder Paste (LTS)

103

alloys [22]. This was the first major inflection point in electronics assembly where the soldering technology had to adapt to meet human needs. Reducing the soldering temperature has been on top of the industry’s wish list since the adoption of leadfree soldering. Reduced soldering temperatures can significantly reduce energy and materials costs, which makes it a very compelling proposition.

5.5.2 Types of LTS Alloying additions such as bismuth, indium, and gallium can be used to reduce the melting temperature of tin-based solders (as shown in Table 5.6). Among these, SnBi alloys have a competitive advantage over SnIn or SnGa due to their lower cost and higher availability. In the late 90s, SnBi alloys gathered a lot of attention as possible substitutes for eutectic SnPb. From a manufacturing point of view, using a binary eutectic alloy composition was quite attractive, but there were concerns about limitations due to its lower melting point. A potential solder metallurgy system that meets the requirement of having the melting temperatures in this 125–160 °C range is the Bi–Sn system. The eutectic temperature is this system is 138 °C [23, 24]. There are many other advantages with the Bi–Sn metallurgy in addition to its melting point falling in the desired Inversion Temperature range. Solder pastes with the Bi–Sn metallurgy are widely available from leading solder paste manufacturers. Soldering BGAs (Ball Grid Array) with SAC solder balls using BiSn based solder pastes, with small amounts of Ag added to increase the solder strength and ductility. One of the drawbacks of using the Bi–Sn metallurgy system as a solder material in consumer electronics products has been its brittleness under mechanical shock conditions. Due to rigors of daily use, cell phones, tablets and other mobile devices can be subjected to multiple drops during field use, so the solder joints formed with the solder paste must withstand strict mechanical shock and drop requirements. Table 5.6 Type of low temperature solder alloys

Low-temperature solder alloy

Melting temperature (°C)

Sn–37Pb

183

Sn–xAg–yIn–zBi

171–191

Sn–36Pb–2Ag

179

Sn–58Bi Sn–1Ag–57Bi

138

Sn–52In

118

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5 Second Level Interconnect Reliability of Low Temperature Solder …

5.5.3 Benefits of LTS in Memory Module Reliability Performances Among all recent research findings there are few key benefits with implementation of low temperature solders including better component warpage during reflow at lower temperature, higher surface mount technology (SMT) yields (with optimized component soldering and mounting recipe), lower energy being consumed (for environmental sustainability and lower energy released) and comparable solder joint reliability with LTS (on homogenous and hybrid solder alloys). Additionally, the environmental benefits due to the reduction of CO2 green-house gases can be estimated for low temperature reflow [25, 26]. Table 5.7 summarizes key benefits of LTS deployment reported by previous researchers or industrial experts.

5.5.4 Interconnect Reliability with Low Temperature Solders LTS paste material must meet two primary objectives: (1) Maintain a lower peak reflow temperature (=10 drops

Expect to observe similar solder joint fracture mode at second level reliability after multiple board level drops

Homogeneous LTS joint (LTS solder paste with BiSn solder alloy) will produce higher drop reliability margin than hybrid LTS joint (LTS solder paste with SAC solder alloy). Suggest using homogenous LTS solder joint or use LTS with 20–40% Bi content (for better ductility) on drop margin

By migrating to a low temperature process (e.g., using one of the high-reliability, low temperature (HRL) alloys), warpage during the liquidus state can be reduced or eliminated, allowing high-performance chips to be used in modern designs by board manufacturers. The lower warpage of the packages reduces the risk of forming certain types of solder joint defects, thereby improving solder joint quality and yield. Out of those listed key measures could be considered for improving memory module SJR, component level package warpage also plays pivotal role in affecting solder joint reliability performance in memory module assembly. Below are some of the critical improvements for optimization of package bill-of-materials (BOM) & assembly parameters to optimize package warpage (at component level) (as indicated in Fig. 5.4). (1) EMC filler content ~89% to improve elevated temperature (HT) warpage (2) Post mold cure (PMC) temperature of 175 °C, not much to improve HT warpage, but cure rate 4 h will improve overall package warpage at room temperature (RT) (3) Control substrate & EMC shrinkage to get optimize RT & HT warpage [40, 41] (4) With or without weight bar during post mold cure step not much impact on package warpage at RT (5) Thinner die or DAF (Die Attach Film) thickness will cause more smiley RT warpage. Samsung researchers [40] published an article which related different package warpage and their effects on SJR lifetime. Components with larger warpages lead to shorter SJR lifetime and vice versa. Higher package warpage is reported at HT during reflow temperature of 260 °C [41] which induces smiley warpage causes non-wet solder joint or Head-in-Pillow (HiP) defects. From simulation perspective, cumulative Strain energy density (SED), was as an index for SJR life prediction, the lower the cumulative SED means better SJR margin is predicted. Higher thermal warpage (induced by CTE mismatches between package substrate and PCB) will induce higher strain joint, eventually decrease SJR margins.

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5 Second Level Interconnect Reliability of Low Temperature Solder …

Fig. 5.4 Micron’s simulation on numerous factors impacting package warpage

5.6.2 Factors Impacting Board Level Drop Performance Solder joint formed by using LTS (with high Bi content) will pose high brittleness, but it becomes a main concern in drop reliability. Sn–Bi solder joints was their poor drop reliability. Therefore, the work on reliability of Sn–58Bi solder joints is how to improve the drop performance. Myung et al. [43] have studied the effect of epoxy resins in Sn–58Bi solder paste on the drop reliability at bare Cu and OSP–Cu substrates. Lee et al. [44] further investigated the drop reliability of Sn–58Bi epoxy solder on ENIG and ENEPIG pads and found that their drop reliability was poorer than that on OSP. Therefore, the authors suggested that ENIG and ENEPIG should be carefully selected for Sn–58Bi epoxy solder. Due to the inherent brittleness of Bi element, there exists a substantial risk of brittle fracture of Sn–Bi based solder joints under mechanical shock and drop conditions for electronic products. Currently, there are less achievements on the development of more ductile Sn–Bi solder although many researchers have tried to reduce the Bi content and incorporate the elemental dopants [44]. But it would reduce the SJR reliability margin as well with the reduction of % of Bi in LTS solder paste or solder alloys (Table 5.9).

5.6 Factors Influencing Solder Joint Reliability (SJR)

109

Table 5.9 Key factors for board level drop considerations with LTS solder joints Key factor

Technical considerations

References

Effects of surface finish Cu–OSP

Better board level drop margin with Sn–58Bi onto Cu–OSP compared to ENIG pad surface finishes of PCB test coupon. This could be caused by brittle IMC formation between Sn–58Bi and LTS

[26]

Type of solder joint (Homogenous or hybrid solder joint) with LTS

Better board level drop reliability with homogenous Bi-doped alloy + LTS solder paste

[38]

Use of epoxy collar resin onto solder joint

Additional epoxy collar will give better shock & vibration absorption during board level drop occasion

[38]

Solder-mask defined (SMD) against non-solder mask defined (NSMD) pad design

It has been long established that NSMD [45] pads reduce strain in the solder-joint, offering potential to improve board level drop lifetime

5.6.3 Construction Analysis and Solder Joint Characterization Detailed technical analysis and construction analysis are crucial to understand the robustness of solder joint formed either using homogenous (SnBi based alloy + LTS) or hybrid (SAC based alloy + LTS). This could be achieved by looking into key structural profiling and properties as outlined in Table 5.10. BGA stand-off increases as SAC alloy melting temperatures are not reached. A mixed solder alloy solder joint results with higher stand-off and potentially improves fatigue life. This includes other passive/active components which we need to evaluate closely, BiSnX alloys may be lower strength with reduced ductility with more fatigue life issues. Hence, solder joint mechanical strengths with BiSnX needs to be fully characterized. One of the key indicators is named as % Bi mixing area and detailed SEM imaging on cross-sectioned solder joint (as shown in Fig. 5.5). Typically, SEM images to be taken as assembled against post aged sample (with LTS).

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5 Second Level Interconnect Reliability of Low Temperature Solder …

Table 5.10 List of characterizations with LTS solder joint Key item

Characterization items

Methodology

Post TC and uHAST solder joint characterization

IMC thickness analysis, IMC composition study

Scanning electron microscopy (SEM)/energy dispersive X-ray (EDX) analysis

% Bi mixing area for hybrid SAC + LTS solder joint

IMC cross-sectional analysis and measurement and calculation of % Bi mixing area (at time zero against post aging test)

SEM/EDX analysis

Component shear strength and Passive components shear fracture modes studies strength and fracture mode study

Using dage, component shearing tool

Component solder joint stand-off height analysis

Solder joint cross-sectional analysis and stand-off height measurement

SEM/EDX analysis

Solder joint micro voiding characterization

X-ray solder joint inspection and micro-voids calculation using built-in software

X-ray inspection tool

SSD or module level warpage analysis

Board level warpage analysis using Shadow moiré

Shadow moiré warpage analyzer

Component joint profiling and tombstoning phenomenon

Solder joint cross-sectional analysis and solder paste volume inspection

SEM/EDX analysis

Fig. 5.5 Representative image of micron’s engineering evaluation on aged sample of hybrid SAC alloy + LTS solder paste solder joint

5.8 Potential Applications of LTS for Advance Packaging

111

5.7 Reliability Requirements on Solid State Drive (SSD) and Memory Modules 5.7.1 Standard Reliability Requirements Solid state drives and memory modules are widely used in market segments such as enterprise computing, client service computing, handheld application, and automotive applications. Different market segments demand different system level reliability requirements in accordance to address their end application mission profiles. Memory makers are striving to meet those system reliability requirements in accordance with IPC/JEDEC and some of those specific reliability requirements. Among those reliability requirements are summarized in Table 5.11.

5.7.2 Extended Reliability Requirements There is extended reliability testing being adopted to characterize the solder joint integrity subjected to thermal and humidity loadings, including those mimic acid rain environmental stress conditions. These are crucial to determine how reliable the assembled memory modules and SSDs intended for harsh environments. Those extended reliability test conditions are outlined in Table 5.12.

5.8 Potential Applications of LTS for Advance Packaging As advanced packages get larger with a thinner form factor, the warpage challenges of the PoP (package on package) pre-stack process become even more severe. The thermal stress and warpage encounter by the package during a typical Pb free SAC alloy reflow process will result in a non-wetting soldering defect, solder bridging, and non-contact open (NCO) on the joints between the bottom package and the PoP memory package. During the PoP pre-stacking process, a low temperature reflow process can be used to connect the top and bottom package-on-package (PoP) [38]. The low thermal load on the packages eliminates warpage issues faced during the high-temperature SnAgCu (SAC) reflow. The increase in integration in an everreducing package size for wearable applications means active silicon dies must be stacked or gaps between components will be reduced to where the traditional surface mount process becomes challenging. The reduction in pitch and gaps between components creates potential defects when the package is subjected to multiple reflows [38]. Flexible circuits are more sensitive to heat and can deform, or even decompose, if process temperatures are too high. In these applications, solder pastes and inks with unique properties are applied to certain types of flat, rigid, and semi-rigid polymer

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Table 5.11 Reliability requirements for SSD and memory modules Reliability item

Test conditions

Duration

Purposes

Module/SSD high temperature storage [46]

125 °C, 48 h

48 h

Die level and diffusion related defects (e.g., intermetallic growth in solder joints or wire bonds) as assembled into SSD or memory modules

Module/SSD temperature humidity storage [46]

60 °C/90%RH, 168 h

168 h

Preconditioning for bend, torsion, shock and vibration samples

Module/SSD HAST [35]

110 °C/85%RH/biased

96 h

Evaluate reliability in humid environments

Module/SSD vibration 0–100 °C, random temperature cycle vibration, 12 G (rms), [Micron standard] 2–12 kHz

24 cycles

To detect solder joint manufacturing defects, marginal inherent interconnect issues, and heat sink attachment issues

Module/SSD Condition J: 0–100 °C temperature cycle [33] Condition K: 0–125 °C (to assess reliability margin)

1000 cycles, 1250 cycles (extended data collection)

Evaluate the ability of surface mounted components withstand mechanical stresses induced by alternating high and low temperature extremes

10 insertions 48 h 168 h 30 min × 3 axis

Evaluate the ability of components to withstand vibration conditions in surface mount applications

Module/SSD 30 G, mechanical shock [48] 25 ms–trapezoidal pulse 10 drops × 3 axis + 500G/1 ms–half sine pulse 10 drops × 3 axis

10 insertions 48 h 168 h 10 drops × 3 axis 10 drops × 3 axis

Evaluate the ability of components to withstand shock conditions in surface mount applications

Module level: 3 point bend [49]

5 cycles

To assess resistance to mechanical bending stresses, e.g., due to handling or shipping

Module/SSD random vibration [47]

3.1 G (rms), 5–800 Hz, 30 min/axis

2% deflection (or 0.91 N/mm), 1 min per side 5×

5.9 Summary and Recommendations

113

Table 5.12 Extended reliability stress test and conditions on memory modules and SSDs Reliability item

Test conditions

Duration

Purposes

Dry Flower-of-Sulphur (FoS) @105 °C based on ASTM B 809–95 [50]

105 °C

48 or 168 h

To simulate trace-to-trace shorts/leakage as a result of gaseous induced corrosion

Mixed flowing gas environmental tests

Chlorine (Cl2 ), hydrogen sulfide (H2 S), sulfur dioxide (SO2 ), and nitrogen dioxide (NO2 )

In accordance ASTM B827-97 [51]

To simulate trace-to-trace shorts/leakage from gaseous induced corrosion

Air pressure test on memory module

Air pressure: 0.5 –0.6 MPa

~15 min, CSAM (Confocal scanning acoustic microscopy) analysis to inspect if any die microcracking post air pressure test

To simulate effects of lamination pressure processes onto memory module or individual packages

sheets. They are then heated and formed under pressure into 3D shapes designed to become part of the electronic product itself. Thus, the body of the product is used as the substrate where a part of the electrical system operates, much like a traditional circuit board. Solder pastes and inks used in these applications must maintain electrical pathways even after being reformed. As with flexible circuits, formable electronic substrates normally require processing temperatures much lower than traditional printed circuit assemblies, so the joining materials must have lower melting temperatures. LTS solder paste is also getting hits with future potential application in pressure and touch sensor devices such as membrane touch switch (MST). In general, flexible circuits used in assembly of MST are sensitive and need lower processing temperature hence LTS is needed to enable this type of packaging. In summary, interconnect reliability with LTS and or Bi-doped solder alloys needs careful characterization and analysis prior to high volume manufacturing although there are substantial technical benefits with LTS implementation in future advance applications.

5.9 Summary and Recommendations Second level interconnect materials reliability and properties play a pivotal role in emerging memory device packaging, which includes solder joint reliability and board level drop performances. Few key summaries as illustrated as in follows: 1. IMC growth is highly temperature-dependance, and interfacial IMC strength decreases with the increases of thermal aging. Therefore, interfacial IMC thickness is identified as an index of solder joint performance.

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2. Cu–OSP surface finish is recommended to automotive application because IMCs of Cu–OSP give higher interfacial strength on shear test as compared to that of NiAu. However, severe Cu consumption is driven by thermal stressing of harsh reliability conditions, so the design of Cu pad must be moving to thicker and additional dopants in solder alloy shall play the function of the decrease of Cu–Sn diffusion. 3. LTS paste material must meet two primary objectives: (a) Maintain a lower peak reflow temperature (60% increase in the memory SER/bit at elevated junction temperatures and can be attributed more than 2× increase in alpha emission rate that reaches the active silicon (continued)

148

6 Specific Packaging Reliability Testing

Table 6.7 (continued) Memory type

Key take aways

16 nm/7 nm FinFET SRAMs, 2018

• While the first process scaling from [49] planar to FinFET resulted in large SER reduction, the subsequent scaling from 16 to 7 nm FinFET is shown to follow the bit-cell area • Reduction. Extensive data collected across a range of supply voltages in planar and FinFET processes show strong exponential bias dependence of SRAM SER for FinFET processes, while for the planar process it follows a linear trend

References

Since package is bended during drop test, a package level bending test is set up and gating criteria which can be achieved by using pre-drop test with a strain rosette measurement to obtain maximum package strain and could also save time and cost consuming compared to set up a full-assembled system level or board level drop test. • The Cu/low-k interconnect reliability can be evaluated by the shear test with different tip design or progressive force setup. The failure mechanism was studied experimentally by progressive test method. From the FIB observation, several scenarios for crack propagation were established, corresponding to distinct failure modes: either cratering in the low-k dielectric, delamination at material interfaces in BEoL structure, or more combined. • The alpha emission rate of direct materials is a vital index to determine their purity grade and the soft error risk in the package design stage. The AER distribution of different package material is provided by vendors and categorized. The encapsulation materials such as capillary underfill, mold underfill and die attach films are intended to meet the ULA specification (0.002 cph/cm2 ) as they are designed to directly contact and protect the functional chips in the assembly process. The trend of shrunk interconnection pitch and thinner die stacking for high I/O and high bandwidth requirement had pushed the substrate vendors to develop ULA solder resist or pre-preg due to the shorten distance between substrate and DRAM cells. In other words, substrate materials with AERs higher than 0.002 or further could increase the package SER accordingly.

References 1. IPC/JEDEC-9702 Standard (2004) Monotonic bend characterization of board-level interconnects. JEDEC, June 2004 2. JEDEC JESD22-B111A, board level drop test method of components for handheld electronic products. JEDEC, July 2003

References

149

3. Caers JFJM, Zhao XJ, Wong EH, Seah SKW, Selvanayagam CS, van Driel WD, Owens N, Leoni M, Tan LC, Eu PL, Lai YS, Yeh CL (2010) A study of crack propagation in Pb-free solder joints under drop impact. IEEE Trans Electron Packag Manuf 33(2):84–90 4. Zaal JJM, Hochstenbach HP, van Driel WD, Zhang GQ (2009) Solder interconnect reliability under drop impact loading conditions using high-speed cold bump pull. Microelectron Reliab 49(8):846–852 5. Wong EH, Seah SKW, Shim VPW (2008) A review of board level solder joints for mobile applications. Microelectron Reliab 48(11–12):1747–1758 6. SEMI G-86, Test method for measurement of chip (die) strength by mean of 3-point bending. SEMI, Aug. 2011 7. Tsai MY, Lin CS (2007) Testing and evaluation of silicon die strength. IEEE Trans Electron Packag Manuf 30(2):106–114 8. Chen J, Liu V, Lin L, Chung M, Gan CL, Takiar H (2021) Effects of epoxy molding compound on managed NAND(mNAND) package strain enhancement. Int Conf Electron Packag (ICEP) 2021:131–132 9. Liu V, Arifeen S, Bassett C, Chung M, Gan C, Takiar H (2021) Mechanical suite of flexural bending method for electronic memory packages. IEEE Int Conf Sens Nanotechnol (SENNANO) 2021:45–49 10. Che FX, Ong YC, Ng HW, Gan CL, Glancey C, Takiar H (2020) Study on package strength of uMCP (Multichip package) for mobile application through three-point bending test and simulation. In: 2020 IEEE 22nd electronics packaging technology conference (EPTC), pp 57–62 11. Nelson W (1985) Weibull analysis of reliability data with few or no failures. J Qual Technol 17:140–146 12. Enkhmunkh N, Kim GW, Hwang K-J, Hyun S-H (2007) A parameter estimation of Weibull distribution for reliability assessment with limited failure data. In: 2007 international forum on strategic technology, pp 39–42. https://doi.org/10.1109/IFOST.2007.4798514 13. Kim GW (Jan 2002) A study on the ‘Substation reliability assessment using Weibull distribution. Trans KIEE SIA(I):7–14 14. Li W (2002) Incorporating aging failures in power system reliability assessment evaluation. IEEE Trans Power Syst 17(3):918–923 15. Peng K, Xu W, Qin Z, Feng L, Lai L, Koh W (2017) Reflow warpage induced interconnect gaps between package/PCB and PoP top/bottom packages. In: 2017 IEEE 67th electronic components and technology conference (ECTC), pp 1378–1383. https://doi.org/10.1109/ECTC.201 7.281 16. Peng K, Yang W, Lai L, Xu W, Feng L (2016) Dynamic warpage characterization and reflow soldering defects of BGA packages. In: 2016 IEEE 66th electronic components and technology conference (ECTC), pp 694–699. https://doi.org/10.1109/ECTC.2016.135 17. Halvi AS, Ahn W, Agonafer D, Novotny S (2004) Simulation of PWB warpage during fabrication and due to reflow. In: The ninth intersociety conference on thermal and thermomechanical phenomena in electronic systems (IEEE Cat. No. 04CH37543), vol 2, pp 674–678 18. Chen CM, Gan CL, Zou YS, Chung MH, Takiar H (2020) Strain response of a semiconductor package during drop test and fast gating method by bend test. In: 2020 IEEE 22nd electronics packaging technology conference, EPTC 2020, vol 3, No c, pp 49–52 19. Chung S, Kwak JB (2020) Comparative study on reliability and advanced numerical analysis of BGA subjected to product-level drop impact test for portable electronics. Electron (Switz) 9(9):1–13 20. Kang TM, Lee YC, Bae BK, Song WS, Lee JS (2017) A study on the correlation between experiment and simulation board level drop test for SSD. In: 2017 18th international conference on thermal, mechanical and multi-physics simulation and experiments in microelectronics and microsystems, EuroSimE 2017, pp 1–6 21. Wang W, Robbins D, Glancey C (2016) Simulation model to predict failure cycles in board level drop test. In: Proceedings—electronic components and technology conference, pp 1886–1891

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22. Che FX, Pang JHL (2015) Study on board-level drop impact reliability of Sn–Ag–Cu solder joint by considering strain rate dependent properties of solder. IEEE Trans Device Mater Reliab 15(2):181–190 23. Zhang A (2014) High acceleration board level reliability drop test using dual mass shock amplifier. In: 2014 electronic components and technology conference, pp 1441–1448 24. Lou M, Zhou J, Wen L, Feng W, Lee J (2010) System level drop reliability method research for netbook memory module. In: Proceedings—2010 11th international conference on electronic packaging technology and high density packaging, ICEPT-HDP 2010, No 15, pp 1043–1048 25. JEDEC IPC-9704A, printed circuit assembly strain gage test guideline. JEDEC, Jan 2012 26. Holm G, Eric S, Martin B, Petra H, Kashi V, Frank K, Dirk B, Hans-Juergen E (2013) Experimental analyses of the mechanical reliability of advanced BEOL/fBEOL stacks regarding CPI loading. In: IEEE international reliability physics symposium proceedings 2013, 5C.1.1-5C.1.10 27. Silomon J, Gluch J, Clausner A, Zschech E (2021) Mechanical BEoL stability investigation at Cu-pillars under cyclic load. In: Proceedings of the international symposium on the physical and failure analysis of integrated circuits, IPFA 28. Silomon J, Gluch J, Clausner A, Paul J, Zschech E (2021) Crack identification in BEoL stacks using acoustic emission testing and nano x-ray computed tomography. Microelectron Reliab 121 29. Sart C, Garreignot S, Fiori VF, Kermarrec O, Moutin C, Tavernier C, Jaouen H (2015) Experimental and numerical investigations on Cu/low-k interconnect reliability during copper pillar shear test. In: Proceedings—electronic components and technology conference 2015, pp 1594–1598 30. Baumann RC (March 2001) Soft errors in advanced semiconductor devices—part I: the three radiation sources. IEEE Trans Device Mater Reliab 1(1) 31. Baumann RC (Sept 2005) Radiation-induced soft errors in advanced semiconductor technologies. IEEE Trans Device Mater Reliab 5(3) 32. Wilkinson J, Hareland S (Sept 2005) A cautionary tale of soft errors induced by SRAM packaging materials. IEEE Trans Device Mater Reliab 5(3) 33. Gedion M et al (Dec 2010) Monte Carlo simulations to evaluate the contribution of Si bulk interconnects and packaging to alpha-soft error rates in advanced technologies. IEEE Trans Nucl Sci 57(6) 34. Ziegler J. Interactions of ions with matter. www.srim.org 35. Karnik T et al (April–June 2004) Characterization of soft errors caused by single event upsets in CMOS processes. IEEE Trans Dependable Secure Comput 1(2) 36. Kumar S et al (2013) Soft error issue and importance of low alpha solders for microelectronics packaging. Rev Adv Mater Sci 34(2):185–202 37. Narasimham B et al (2017) Influence of polonium diffusion at elevated temperature on the alpha emission rate and memory SER performance. In: IEEE international reliability physics symposium (IRPS) 38. Kobayashi H et al (2009) Alpha particle and neutron-induced soft error rates and scaling trends in SRAM. In: IEEE international reliability physics symposium 39. Gedion M et al (June 2011) Uranium and thorium contribution to soft error rate in advanced technologies. IEEE Trans Nucl Sci 58(3) 40. Kawasaki H, Clark BM, Nishino T, Gordon MS (2015) Energy dependent efficiency in low background alpha measurements and impacts on accurate alpha characterization. IEEE Trans Nucl Sci 62(6) 41. Wilkinson JD, Clark BM, Wong R, Slayman C, Carroll B, Gordon M, He Y, Lauzeral O, Lepla K, Marckmann J, McNally B, Roche P, Tucker M, Wu T (2011) Multicenter comparison of alpha particle measurements and methods typical of semiconductor processing. In: IRPS 42. Gordon MS, Heidel DF, Rodbell KP, Dwyer-McNally B (Dec 2009) An evaluation of an ultralow background alpha-particle detector. IEEE Trans Nucl Sci 56(6) 43. Mizutani A, Oguma K, Fujinami M (2013) Discrimination of low-alpha 210 lead for electronics material using isotope ratio measurement by ICP-QMS, J-STAGE. Radioisotopes 62(2):73–82

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44. Lee SK, Kang SY, Jang DY, Lee CH, Kang SM, Kang BH, Lee WG, Kim YK (2011) Comparison of new simple methods in fabricating ZnS(Ag) scintillators for detecting alpha particles. Prog Nucl Sci Technol 1:194–197 45. Martinie S, Autran JL, Uznanski S, Roche P, Gasiot G, Munteanu D, Sauze S (2011) Alphaparticle induced soft-error rate in CMOS 130 nm SRAM. IEEE Trans Nucl Sci 58(3) 46. Ramarapu R, Wong R, Clark B, Shen T (2013) A study of temperature induced polonium diffusion on SRAM SER performance. IEEE-SCV SER workshop presentation 47. Mahatme NN, Bhuva B, Gaspard N, Assis T, Xu Y, Marcoux P, Vilchis M, Narasimham B, Shih A, Wen SJ, Wong R, Tam N, Shroff M, Koyoma S, Oates A (2015) Terrestrial SER characterization for nanoscale technologies: a comparative study. In: 2015 IEEE international reliability physics symposium 48. Fang YP, Oates AS (2016) Characterization of single bit and multiple cell soft error events in planar and FinFET SRAMs. In: IEEE Trans Device Mater Reliab 16(2) 49. Narasimham B, Gupta S, Reed D, Wang JK, Hendrickson N, Taufique H (2018) Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs. In: 2018 IEEE international reliability physics symposium (IRPS) 50. Liu V, Chen CM, Chen J, Chung MH and Gan CL (2022) Study of robust package strength characterization of memory packages for handheld application, Memories - Materials, Devices, Circuits and Systems 3

Chapter 7

Reliability Simulation and Modeling in Memory Packaging

7.1 Introduction In the advanced packaging technology development, numerical simulation is one of the indispensable steps that could provide the key index of the failure mechanism, package’s physical behavior in process or under reliability stresses, and further determine the high-risk factors in product design stage. Further, the adoption of simulation tool can extract the information earlier than volume manufacturing and significantly reduce the development cycle time. This concept has no exception that being applied in memory package technology development. The purpose of this chapter is to highlight key reliability concern in different package types, interconnections applied in memory product and their risk management in recent studies using numerical or simulation models. Some well-known simulation software or codes will be conducted in this chapter, such as FEA (Finite Element Analysis) software called ANSYS, Finite Volume approach called moldex3D and the SRIM (The Stopping and Range of Ion in Matter) program for particle emission study. These softwares have been widely used to evaluate the thermal/mechanical reliability relevant cases for component, process capability and system level package reliability topics. In this Chapter, we summarized some of the classic and critical simulation studies from assembly and memory manufacturing industries.

7.2 Simulation for Wire Bonding and Stacked-Die Packages In memory assembly industry, wire bonding interconnection is still the dominating technology in electronic packaging to make electrical connections between Si chip and packaging substrate due to its flexibility. At present, there are still many challenges triggered by the structure factors in the larger and thinner die stacking assembly with wire bonding interconnection, such as the thin die thickness, overhang width, © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6_7

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smaller pitch and opening size of bonding pads, increased stack-up die quantity with lower package height, and decreased mold clearance. Some factors significantly influence the wire bonding reliability, and the preliminary study is needed for the risk mitigation.

7.2.1 Wire Bonding Interconnection Reliability Wire bonding has been a mature interconnection technology that typically applied in most of the memory package types such as the tiny bonding wires application in the memory with stacked NAND flash dies. In this sub-section, the recent simulation studies on wire bonding assembly process are summarized. The realization of low wire loop height is important for the package with an extremely low mold clearance height. However, the conventional wire pull test can only acquire the failed pull force and failure mode through test results and failure analysis. The recent study had applied the wire pull test together with finite element analysis to investigate failure mechanism, modes, and stress distribution at different structures for the bond pad reliability of Cu/low-k chip [1]. The Dage 4000 tester with a precision XY stage was implemented to study failure mode and mechanism for Cu wire bond with different wire pull locations in the pull test. Figure 7.1 is a 3D model illustrating multirow wirebond pads distributed at the peripheral area of the chip and bonded with high- and low-loop wires at the inner and outer row of bond pads. Here the wire pull location is defined as a horizontal distance (100, 200, 500, 1000 and 1500 µm) from the first bond to the pull hook as shown in Fig. 7.2. Pull force is gradually applied vertically through the pull hook with loading speed of 500 µm/s until failure. Such low loading speed ensures that materials are subjected to near static load and effect of strain rate on material behavior can be ignored.

Fig. 7.1 3D model of stacked die with high- and low-loop wires at the inner and outer row of bond pads

7.2 Simulation for Wire Bonding and Stacked-Die Packages

155

Fig. 7.2 Normal 3D FEA model for wire pull test simulation [1]

FEA simulation can provide stress distribution, contours and values, which can be used for studying failure mechanism. A three-dimensional FEA model shown in Fig. 7.2 is used for wire pull test simulation [1]. The following key parameters are created in a reference model including 3.5 mm wire loop length, 0.5 mm pull location, 0.25 mm loop height, and 30 µm diameter of the bonded FAB (Free Air Ball). The appropriate boundary conditions are defined at the first ball bond and the second wedge bond locations. At the first ball bond location, the bottom surface of the chip is constrained with all degrees of freedom. As shown in Fig. 7.2c, both vertical side walls are constrained with a coupling boundary condition with respect to the direction of the wire length. At the second wedge bond, the bottom surface of the Cu wedge bond is constrained in all degrees of freedoms to simulate the wire wedge attached to the bond finger on the substrate. Besides, the wire pulling force was applied onto the Cu wire gradually and vertically at the defined pull location. In the experimental study [1], each wire pull test condition has 8 samples. Five pull distances, including 100, 200, 500, 1000, and 1500 µm, are used for both low and high wire loop samples. Pull force was recorded by the Dage tester. Failed pull force was determined through averaging experimental results for 8 samples with the same test condition. Figure 7.3a shows experimental results of pull force versus different pull test conditions. Failed pull force decreases significantly with increasing distance of pull location away from first ball bond location. For example, failed pull force for the sample with high loop (H = 250 um) decreases from 4.4 g to 2.6 g when pull location varies from 500 µm to 1500 µm. When pull location moves away from the first ball bond, bending effect on ball bond area becomes noticeable. It should be careful when wire pull test is used to evaluate wire bond reliability because failure mode and pull force are affected by pull location significantly. Apparently, pull force is larger for Cu wire with higher wire loop compared to Cu wire with lower wire loop. When pull location is adjacent to the bonded FAB around 100 um away from first ball bond, the influence of wire loop height on failed force becomes smaller because

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test condition is close to pure peeling test condition which is independent on wire loop height. But such influence becomes significant when pull distance increases. Stress of bond pad increases with increasing pull distance when using the same pull force. The stress results as shown in Fig. 7.3b verified this phenomenon. Principal stress along stress path in the low-k layer shows that pull location affects stress significantly. The maximum principal stress increases with increasing pull distance. Fig. 7.3 a Experimental results of failed pull force, b Effect of pull location on principal stress of low-k layer from wire pull simulation [1]

7.2 Simulation for Wire Bonding and Stacked-Die Packages

157

7.2.2 Thermal–Mechanical Reliability of Multi-die Stacked Package For low cost, conventional multi-die stacked packaging, materials like DAF (Die Attach Film), FOW (Film over Wire) and silicon spacer play key role to relief the die stress inside the packages. However, the package construction could still suffer localized high stress and further induce the package failure in the reliability tests. In this sub-section, the classic component-level issues of 2 and 4 die stacked COB (Chip on Board) packages is presented to figure out the failure mechanism resulting in thin film cracks at the bottom die corner during a reliability test from a perspective of simulation study [2]. A stress sensitivity study was also performed using the following key design parameters listed in Table 7.1 to see their effect on the reliability performance of these stacked-die packages. The test vehicle selected for the simulation modelling is a DRAM chips assembled in COB package structure which was subjected to a high-temperature cooled down from 125 to −55 °C to study thermo-mechanical stress distribution. The package has stress-free temperature at 125 °C. All materials were assumed to have a linear-elastic properties for the applicable range of temperatures. Simulation results showed that the package was highly stressed when it cooled down from an elevated temperature. The bottom die corner (active side) experienced the highest stress due to the CTE mismatch between the epoxy pillow and the bottom die attach materials. The location of peak stress correlated with the actual failure location. The other three die only interfaced with the epoxy pillow, so the stress magnitude was lower. A study on the impact of epoxy coverage [2] showed that the peak stress location shifted according Table 7.1 Key experimental design and material parameters [2]

Factor

Name

Value

1

Epoxy coverage

50%, 80%, 100%

2

Resin separation

Normal (filler + resin), resin

3

Stack die attach materials

SDA1, SDA2, SDA3, SDA4

4

Bottom die attach materials

BDA1, BDA2, BDA3, BDA4

5

Package construction

2-COB, 4-COB

6

Die thickness

150 µm, 200 µm

7

Encapsulated thickness

1.4 mm, 1.6 mm

8

Substrate core thickness

100 µm, 150 µm

9

TC conditions

−55 °C to 125 °C, 0 °C to 125 °C

10

Package construction

Epoxy, silicon spacer + DAF

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.4 Impact of epoxy coverage on bottom die stress [2]

to epoxy coverage (Fig. 7.4). Bottom die stress was lower when epoxy coverage was 100%. At 100% coverage, the mold compound was pushed out of the silicon area; therefore, its contribution to the local CTE mismatch can be reduced. The DRAM die failure located at resin-rich areas where the die-to-die gap is filled with more than the maximum allowable resin or with lacking fillers is investigated. The resin-rich structure had been characterized with poor crack resistance and weaker adhesion. The CTE value for a resin-rich region was twice as much as the CTE value for epoxy coverage region, while the modulus was half the typical modulus. The new material information was plugged into the model, and simulation indicated there was a significant increase in the bottom die stress with the presence of a resinrich area (Fig. 7.5). To reduce the stress on die in the package, the use of alternative package construction such as Film-over-Wire (FOW) and silicon spacer plus die attach film (DAF) construction over conventional epoxy stacking was suggested. Simulation results indicated that the model with a silicon spacer had the lowest stress due to its superior intrinsic reliability. Further, the peak stress also shifted from the bottom die active surface to the passive surface. Based on favorable simulation results, both 2-COB and 4-COB packages were advised to adopt silicon spacer package technology.

7.2.3 Stacked Die Reliability Issue For multi-die stacked packages with wire bonding, some assembly risks such as die crack, bondability of metal pad and overhang have been investigated in the industry for years. Wire bonding on thin die with overhang is a crucial enabling process

7.2 Simulation for Wire Bonding and Stacked-Die Packages

159

Fig. 7.5 Simulated bottom die stresses from resin-rich or non-resin-rich regions [2]

for memory die stacking. As die thickness is reduced further, the deflection of the overhang die during wire bond becomes larger due to the decreased rigidity of thinner Si die. This makes it increasingly difficult to obtain reliable and repeatable wire bond. One solution to alleviate this issue is to use DAF that has higher Young’s modulus at wire bonding temperature. From the experimental study [4], it was seen that the die deflection has an obvious reduction if the DAF elastic modulus reached an above ten MPa level as shown in Fig. 7.6a. In the extended simulation study, FEA was performed to obtain the stress distribution in Fig. 7.6b. In this study, the normalized stress ratio between the models with high and normal modulus is 1: 0.78. The max principal stress in the same Fig. 7.6b shows high modulus DAF decreases the die stress by 22% and reduces the deflection by 87%. High modulus DAF allows us to greatly widen the design/process window to either apply much thinner die thickness or larger overhang distance than that with normal DAF. Another recent simulation study related to wire bonding overhang topics are summarized in Table 7.2, and their key take away are listed as well.

7.2.4 Three-Point Bending and Four-Point Bending Simulations Three-point bending (3 PB) and four-point bending (4 PB) tests are commonly used for package level bending in the assembly industry. The suitability of these two tests applied on Multi-Chip Packages (MCP) in memory application is numerically investigated by using finite element analysis (FEA) [9, 10]. For the purpose to predict the package strain distribution under different test loadings, the correlation between experimental and simulated results is absolutely required. In the showing example, a conventional FEA skill called “contacted surface” is implemented for the case of rigid-flexible contact between two bodies. The “contact surface” is defined on MCP surface while the rigid supporting and loading fixtures are defined as a “target surface” in the bending test simulation. The contact point is selected as convex,

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.6 a Die deflection measurement from overhang layer with different material properties [4], b Stress distribution of capillary wire bonded on die overhang structure and simulated principal stresses from DAF with different modulus [3]

finer mesh with high-order elements. The target surface is selected as flat, coarse mesh with low-order elements. Mesh refinement study and accurate elastic molding compound input is recommended before the analysis. The illustrations of strain distribution from 3 and 4 PB FE models are captured from simulation output as shown in Fig. 7.7a, b. Some anomalous strain gradients could be observed and red circled with an inside view of MCP in Fig. 7.8a. The force loadings applied on the stacked die outside area creates a moment at the die edge, where the various failure modes occurred possibly. In contrast, the result in Fig. 7.8b indicates that 4 PB test has less sensitivity to the asymmetry in stacked-die

7.2 Simulation for Wire Bonding and Stacked-Die Packages

161

Table 7.2 Simulation studies on overhang die stress in stacked memory packages Suppliers (year)

Key take aways

References

Samsung (2006)

. CV (Constant Velocity) setup for wire bonding capillary during the bonding process is a dominant parameter for die crack . Unstable contact shear and pressure were observed between ball and metal pad, and the increased overhang length showed scattering and high amplitude change

[5]

ASE (2011)

. Modal, harmonic and nonlinear transient analyses are [6] carried on stacked-die structures with different overhang lengths . Natural frequencies of stacked dies reduce when length of overhang increases. In lower frequency modes, the vibration mainly occurs on cantilever of top die . Resonance could occur on stacked-die structure during wire bonding if its overhang exceeds a certain length

Toshiba (2015)

. The die crack modes are categorized based on the [7] crack location at die side or pad vicinity. Die-side crack appears where the bonding pad is near the die corner and is prominent in case of thin and large overhang length dies. Pad-vicinity failure has a certain steady probability where bonding pads are in some extent away from the die corner

Kulicke and Soffa (2017) . The critical factors influencing die deflection and maximum principal stress are die thickness and overhang distance while substrate thickness and bonding temperature are less dominant

[8]

SanDisk (2016, 2018)

[3, 4]

. Overhang die with high modulus DAF can significantly decrease die deflection to one-third of original during wire bonding process. Besides, front side and back side die stress also decreased by 37% and 11% respectively . Further applying high modulus DAF to all stack layers can decrease wire bonding die deflection and stress, but not significant

package and could generate a more ideal beam-like gradient. Conclusively, 4 PB test is recommended to be a better characterization testing method of package strength. The previous research work [9] also discusses the suitable loading and supporting span used in 3 PB and 4 PB tests. In summary, the bar fixtures in 3 PB test are suggested to apply force within the die area and the smaller span is recommended to produce flexure stress distribution ideally. Regarding to 4 PB test, the fixture diameter has less effect, and the larger top span together with smaller bottom span is suggested to achieve ideal flexural stress distribution during package strength test. As for the 3 PB and 4 PB FE analysis of hybrid-die, multi-stacked MCP package,

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7 Reliability Simulation and Modeling in Memory Packaging

the mold strain against die strain diagrams have been illustrated in Fig. 7.8a, b. Regarding of overall package strain, the two main parts including mold compound area and die stacking area in the MCP package are studied individually and correlated. 6 conditions with different fixture setup on contact diameter and span width are simulated and illustrated in Fig. 7.8a. Local curve irregulars could be observed at mold strain ranging around 3000 micro strains (red circled), because the shear strain in 3 PB simulation is much severed compared with 4 PB one. Also, the contact fixture diameter in the 3 PB simulation has more effect than 4 PB. The smaller fixture diameter can produce higher localized strain by the comparison between 0.6 mm and 2 mm span width, and thus larger fixture diameter is recommended to be used in 3 PB test. In Fig. 7.8b, 7 conditions in 4 PB test are simulated and there are small dimples of curves in some span conditions which is due to the shear or nonlinear effect. In the comparison of condition D2L4 and D2L7, it appears that the fixture contact diameter has less effect to the strain distribution in 4 PB. Briefly summarized for these 7 conditions, D2L4 has the better span condition since its linear behaved curve is closer to ideal strain and flexural distribution.

7.3 Simulation for Solder Joint Reliability of Memory Package Electronic components in automotive environments are subjected to harsh conditions including large temperature variations, mechanical shock, vibration, and other wearout failures. Of the diverse types of failures, second level interconnects are most vulnerable to fatigue failures. These solder interconnects are particularly sensitive to thermal and mechanical loading due to Coefficient of Thermal Expansion (CTE) mismatch with printed circuit boards (PCBs). To assess the robustness of the package and its suitability in the field, a two-pronged approach can be taken. The first is to iteratively test the package in an accelerated environment to get a characteristic life prediction in the expected field conditions. Running these tests can take a considerable amount of time and often output data comes in extremely late in the qualification stage, when there is little time left to rectify any design flaws. To mitigate that, we need to consider an alternative approach where we establish an ecosystem of material characterization, preliminary package testing and finally a detailed simulation model that captures the physics effectively.

7.3.1 Plastic Work Accumulation of BGA Package During Thermal Cycling In this sub-section, a simulation framework was performed to effectively predict the semiconductor package life with varying design and material parameters [11].

7.3 Simulation for Solder Joint Reliability of Memory Package

163

Fig. 7.7 a Simulated 3 PB strain distribution on MCP, b Simulated 4 PB strain distribution on MCP [10]

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.8 a Simulated mold strain versus die strain of MCP in 3 PB test; b Simulated mold strain versus die strain of MCP in 4 PB test [10]

7.3 Simulation for Solder Joint Reliability of Memory Package

165

A 3D model was developed with quarter symmetry of a hypothetical package that does not represent a particular product but with representative of a general BGA package. For the solder ball shape, the interactive program called Surface Evolver is used to determine a curve to best match the nominal ball shape for this package and imported into the simulation model. This shape is determined by many factors including the solder mask defined (SMD) opening on the component side, preform solder ball diameter, stencil opening for the solder paste, solder percentage in the paste and non-solder mask defined (NSMD) pad size on the PCB. Surface tension and gravity are also involved in this calculation. Once the other package details are added to the model (including material properties and all dimensional details), the boundary conditions of symmetry are applied. For quarter symmetry packages, one node is fixed in x, y and z directions and two sides are free to slide separately in the x and y directions only. Ambient temperature is then cycled from a low value to a high value. In this model, a temperature range from −40 to 125 °C with 10-min ramp times up and down and 10-min dwell times at each temperature extreme are applied. After the simulation completion, post processing begins on two slices in each solder ball. The upper slice is located at the top of the solder ball (component side) just below the solder mask and is 25 µm thick. The lower slice is located 25 um above the PCB pad on the PCB side. Both slices have two mesh layers (12.5 µm each). The accumulated plastic work/cycle/volume for both slices are recorded for each ball and reported as Strain Energy Density (SED) [12, 13] in a map of values representing the ball layout of the package. Evaluation of SED enables comparisons of location and magnitude and possible correlation to test data. The maximum SED would be the location of the expected first solder ball failure. Once simulations and testing are completed, the SED output of the simulation is used to fit a power curve and determine a characteristic lifetime, or Eta prediction formula to relative SED values. If no specific test data exists for a specific package, then predictions can be made through past testing and simulation. In regard to the effect of die parameters, one of the most critical parameters both from a functional and mechanical perspective is the silicon die due to its high stiffness and exceptionally low CTE. In the Micron study [11], the varied index including the die count, die thickness, die shape, die size and die stacking are considered. Keeping the thickness of individual die same (45 um), there was an 84% improvement from 8DP to SDP alone as shown in Fig. 7.9a. Usually this is driven by density requirement of the package and not just one variable easily controllable. Die thickness increase from 45 to 65 um for 8DP stack up resulted in around 16% increment of SED (Fig. 7.9b) which can be significant on marginal packages. Typically, this is guided by process capability. Also, the shape or aspect ratio of the die can be critical. A square die can reduce the distance from neutral point relative to the corner ball for the same die area. Similar attention needs to be paid for die stacking (Fig. 7.9c). In some instances, we can see a benefit in stacking the die side by side instead of vertical if routing permits and cross-stacking for rectangular dies also can result in 13% improvement (Fig. 7.9d). Lastly, die area is a big driver for SJR. While package density would typically drive die count, die area and overall silicon, we see extremely high sensitivity to die footprint area in Fig. 7.9e. Conclusively, the die volume and

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7 Reliability Simulation and Modeling in Memory Packaging

die stacking can be the most critical factors, and side-by-side stacking can be the most optimum configuration for package with small thinner die. Pad type can also be modified to improve the performance of the package. There are two main pad types: Solder Mask Defined (SMD) and Non-Solder Mask Defined (NSMD). The later provides extra areas of support in the edges of the pad where the crack originates. In the recent Micron’s study [11], the simulation results showed

Fig. 7.9 SED sensitivity to a die count, b die thickness, c die shape, d die stacking, e die size [11]

7.3 Simulation for Solder Joint Reliability of Memory Package

167

around 14% improvement of SED from SMD to NSMD for the same package as shown in Fig. 7.10a. Solder material is also important to improve temperature cycle fatigue performance. Current research on SACQ type solder that has Bismuth doping (Sn-3.4Ag-1.0Cu-3.3Bi) are more resistant to cracks. Simulations showed about 9% improvement of SED over SAC305, but improvement in experimental test is even higher. The reason simulations can be deceptive is because different solder material will have different life equations. So even though the SED change is only 9% but the eventual life improvement can be up to 50% (Fig. 7.10b). Full development of life equation for each solder material type requires running multiple legs of geometry and creating a test database. This study was conducted before that, so the results are only reflective of the SED change. Mold compound material selection can improve SJR but must consider effects on package stress and warpage. Higher CTE of mold material can improve the effective CTE of the package. In this study, a range of EMC (Epoxy Mold Compound) material from low to high CTE is also investigated. There was about 19% improvement from the baseline to high with a total swing of 35% from low to high as shown in Fig. 7.10c.

Fig. 7.10 SED sensitivity to dissimilar materials: a pad type, b solder material change, c EMC change [11]

168

7 Reliability Simulation and Modeling in Memory Packaging

7.4 Simulation for Flip Chip Memory Packages 7.4.1 The Effect of Cu Pillar Patterns on FCCSP Memory Reliability In FC (Flip Chip) type memory packages, the CTE mismatch between different materials causes package warpage and possibly induces reliability issues under thermal mechanical loadings. These CTE mismatch issues interact with various copper pillar patterns and affect package reliability. The Micron’s study [14] reports on simulation work to optimize the 1st level copper pillar patterns on FC packages. Finite element models have been established to understand the effects of various copper pillar patterns on stress conditions in solder regions. All the models of FC packages in this study were developed using ANSYS software. The model was developed at two levels: The 1st level model includes only die and copper pillar bumps on the substrate (no underfill or mold compound), to capture the effect of copper pillar bump patterns. The 2nd level model has mold compound (550 µm thick) and underfill to capture the effect of different mold compounds and underfill. The active pillars are modeled as rectangular pillars (50 × 70 µm) while outrigger bumps are modeled as cylindrical pillars (40 µm diameter). An outrigger copper pillar bump pitch of 100 µm is used for different outrigger copper pillar bump patterns. All the pillars are modeled with detailed information of copper pillars on the die and substrate side. Lead-free solder joints are modeled as a portion of copper pillars. Figure 7.11 shows different bump layout patterns (quarter symmetry models) for 1st level DCA packages. Pattern 1 has the least number of outriggers, while Pattern 2 to Pattern 7 have many outrigger copper pillar bumps. The main differences between Pattern 2 to Pattern 5 are fewer outriggers near the die center. Patten 6 has extra copper pillar bumps near the die edge and die center, while Pattern 7 has no copper pillar bumps near die center. All the copper pillar bumps for Pattern 7 are near the die edges. The lead-free solder in this study is assumed to exhibit elastic, bilinear kinematic hardening plastic behavior after yield. Elastoplastic material properties in ANSYS can be defined with BKIN option. This option includes the Bauschinger effect and assumes that the total stress range is equal to twice the yield stress. The initial slope of the curve is taken as the elastic modulus of the material and the tangent modulus of material is calculated after yield stress. The constants of C1 and C2 used for the solder bilinear material model are 36 MPa (yield stress @0.2%) and 53 MPa (Tangent Modulus), respectively. Figure 7.12 shows solder stress in copper pillar bumps at room temperature for 1st level models [14]. Maximum active solder stress is calculated for Pattern 1. Table 7.3 shows maximum von Mises stresses in solder for the active and outrigger copper pillar bumps. Stresses in solder joints for active copper pillar bumps are up to 25% lower than stresses in outrigger copper pillar bump solder joints. The outrigger copper pillars in Pattern 1 show the maximum solder stress because there are a small number of outrigger copper pillars to support the die, but it also has low die warpage due

7.4 Simulation for Flip Chip Memory Packages

169

Fig. 7.11 Different outrigger copper pillar bump patterns in a quarter symmetry FE model [14]

to almost no restraint when die is trying to warp or expand at higher temperatures. Pattern 2 to Pattern 5 have comparatively higher warpage and lower solder joint stress in active and outrigger arrays than Pattern1. Pattern 6 has few outrigger copper pillars near the die edge and comparatively lower solder joint stresses for active pillars bumps. Stresses in both active and outrigger copper pillar solder joints are significant, but outrigger pillars are formed to distribute stresses in the package and lower the stresses on active pillars. Outrigger pillars may be sacrificed to lower the stresses on active pillars. Pattern 7 has no copper pillars near the die center but does have some near the die edge. This causes comparatively low stress on solder joints but high die warpage due to more constraints for the die. Although solder joint stress and die warpage does not vary much from outrigger Pattern 2 to Pattern 7, outrigger Pattern 7 shows the lowest solder joint stress and highest die warpage. Results in Table 7.3 show that adding or taking out copper pillars near the die center does not affect the solder joint stress and die warpage significantly (Pattern 2 to Pattern 5), while adding supplementary copper pillars near the die edge may dramatically reduce stresses in the active array (Pattern 6 and Pattern 7).

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Fig. 7.12 Stress (von Mises) behaviors of different outrigger copper pillar bump patterns [14] Table 7.3 Max. von Mises stress in solders [14]

Outrigger bump patterns

Max. von Mises stress (MPa) Active solder joints

Outrigger solder joints

Outrigger pattern 1

68

87

Outrigger pattern 2

57

64

Outrigger pattern 3

57

65

Outrigger pattern 4

57

65

Outrigger pattern 5

58

65

Outrigger pattern 6

53

62

Outrigger pattern 7

52

64

7.4 Simulation for Flip Chip Memory Packages

171

7.4.2 Mold Flow Simulation The semiconductor packaging industry has used high throughput and low-cost transfer molding process for many years. Also, the typical epoxy molding compound are much cheaper than capillary underfill. Hence, it is desirable to use molded underfill for typical FCCSP (Flip Chip Chip Scale Package) type memory packages, particularly when one device type is being made in large quantities per substrate strip. With the development of microchip encapsulation technologies continuously moving toward smaller size and higher density, the existed defective problems during fabrication become more critical and important. The combined effect of the various possible settings of processing conditions, the complexity of molding material properties, chip/substrate layout and mold cavity design has caused manufacturing challenges during encapsulation process. Therefore, the simulation of compound flow behavior inside the mold cavity is required in the early package design stage. It can help the design engineers and assembly process engineers to understand the dynamic resin filling front in different locations during the molding step. To reduce analysis time and construct a complete geometric model, this study explores the mesh design, which is a simplified model of FCCSP package components. By simplifying the model, not only the complete melt front analysis can be seen, but also the experimental data (short shot experiment) can be compared to verify the accuracy of the simulation. In this study, incorporating venting analysis is used and the results of void entrapment can be obtained. Furthermore, the melt front evolution and the position of air trap by using different EMC are investigated. The results can not only provide good guideline for the microchip encapsulation process development but also help understand the flow behavior by different EMC (with max filler sizes 25 µm/20 µm) of microchip encapsulation successfully. In this study, a 3D mold flow modeling of the FCCSP strip using transfer molding process with MUF by the Moldex3D software is performed to optimize design and process parameters that can reduce device defects and enhance yield. The simulated results are used to forecast the risks of air voids in transfer molding process. The key information of FCCSP package structure is shown in Fig. 7.13 and Table 7.4. Further, Figure 7.14a, b showed the 3D mesh of each seperated unit from different views. For the current FVM (Finite volume method) numerical simulation, the strip modeling has been simply modeled to 1/9 stripe size. Different and crucial factors are considered in the simulation including mold temperature, transfer time, transfer speed, clamping force and transfer pressure. To investigate the impact of the flow resistance from each package, all bumps of each flip chip are simulated. The mold flow prediction of MUF filling is shown in Fig. 7.15a. Based on the simulation result, flow distribution is not uniform. The local flow undulation is observed on the chip and bump areas due to flow resistance induced by the narrow flow gaps between chip and substrate. Figure 7.15b shows the prediction of the void/ entrapment location by simulation in BTM view (focus under the bump gap). When mold flow approaches the chip, the front flow is separated. The front flow located at the peripheral and outer die regions are much faster than the area close to the substrate which will cause air void/ entrapment. The simulated results

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.13 Package structure of FCCSP type memory

Table 7.4 Key dimension of FCCSP type memory

Item in Fig. 8.21

Package items

Dimension (µm)

T1

Mold thickness

250

T2

SBT thickness

230

T3

BGA ball height

250

Die thickness

120

Die gap

30

Mold clearance

100

Total height

730

showed the potential locations of voids in molding process, but they are concluded as low void risk from simulation result. The flow undulation due to the narrow gap between chip and substrate and flow resistance of bumps are the main reason for trapped voids. By simplifying the model, not only the complete melt front analysis can be seen (compare with POR model, shown in Fig. 7.16a, b), but also the experimental data (short shot experiment) can be compared to verify the accuracy of the simulation,

7.5 Simulation for Stacked-Die Memory with TSV

173

Fig. 7.14 Modeling mesh of a single unit and b partial (1/9) strip

the verification data shown in Fig. 7.17. The comparison shows a good consistency between simulation analysis and experimental result.

7.5 Simulation for Stacked-Die Memory with TSV In the multi-die stacked package with TSV (Through Silicon Via), the decreased interconnection size is driving the evaluation of micro joint reliability which is critical during the transition from micro-interconnection to a fine pitch equal or even below 10 µm. Micro-bump interconnections have been applied in 2.5D and HBM (High Bandwidth Memory) relevant applications for over 5 years. The effect of underbump metallization (UBM) materials on the electromigration failure mechanism of Sn-Ag micro-bump structures with Cu or Ni UBM layer was investigated under stress conditions at current densities ranging from 0.5 ~1.3 105 A/cm2 at 150 °C [15]. The 3D finite element analysis was performed to determine the Joule heating behavior within the daisy-chain structure under ongoing stress. The Joule heating temperature was predicted via the SOLID 226 3D 20-node coupled-field solid element analysis using ANSYS software. In Figure 7.18, second row shows the mesh geometry used in this study. The electrical resistivities, thermal conductivities, and temperature coefficient resistance of the materials used in this modeling are listed in Table 7.5. The current density distributions of the micro bump with the Ni and Cu UBM under 0.157 amp at 150 °C are presented in third row of Fig. 7.18. Finite element analysis results for the micro bump with the Ni and Cu UBM revealed a maximum current density inside the solder at the point of Al trace entry into the Ni and Cu

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.15 Simulation for a melt front analysis b void location analysis

pillars, without any current crowding effect in the substrate side of the joint. The temperature distributions of the micro bump with the Ni and Cu UBM under 0.157 amp at 150 °C are presented in fourth row of Fig. 7.18. Finite element analysis results suggest that the micro bump temperature was substantially higher than in serious Joule heating involving the solder. A hot spot exiting in the solder near the entrance of the Al trace showed a peak temperature of 155.4 °C in the Ni UBM micro bump.

7.6 Alpha Particle Emission Simulation in Memory Device In Chap. 6, we have discussed the test metrologies for alpha emission rate measurement for package materials. In this Chapter, the simulation metrology for alpha

7.6 Alpha Particle Emission Simulation in Memory Device

175

Fig. 7.16 Melt front analysis a POR modelling; b Simplify modelling

Fig. 7.17 Short shot test comparation a Short shot simulation for simplify modelling; b Short shot experiment of real sample

emission distance will be introduced. For the purpose to assess the potential risk from alpha induced soft error in the early stage of package stack-up determination, the simulation code for alpha particle transmission is implemented in this paper. The free code with program packaging, SRIM (version 2008), is a commonly used Monte Carlo program created by J. F. Ziegler. SRIM could provide the physical calculation features such as the ion stopping and range in matter, ion implementation, Sputtering, ion transmission and ion beam therapy [16]. TRIM (Transport of Ions in Matter) is

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Table 7.5 Materials properties of thermal-electric simulation [15] Materials

Thermal conductivity (W/m K)

Resistivity (µΩ cm)

Temperature coefficient of resistivity (TCR) (1/K)

Sn-2.5Ag

33

12.3

4.6 × 10−3

Ni

76

28

6.8 × 10−3

Cu

403

6.8

4.3 × 10−3

NCF

0.55

–

–

Si

147

–

–

Fig. 7.18 Experimental and numerical electromigration performance between Ni and Cu UBM micro bump [15]

the most comprehensive program included in SRIM and this simulation code based on Monte Carlo calculation is typically implemented to study the interactions of energetic ions traveling through materials. TRIM can support the target model with multi-layered, compound materials with up to eight layers, and setup with different

7.6 Alpha Particle Emission Simulation in Memory Device

177

material characteristics. The following is the alpha particle simulation procedures applied in this study: (1) Step 1: Type of TRIM calculation For the simulation of alpha particle emissive range in target package material, “Ion Distribution and Quick Calculation of Damage” function in the “damage” types was implemented. (B) Step 2: To determine alpha particle decay energy The alpha particle emitted by the natural radioactive decay of unstable isotopes like uranium, thorium, and their daughter isotopes, is the nucleus of a helium atom, consisting of two protons and two electrons . In Fig. 7.19, the common radioactive impurities in electronic packages including 238U, 235U and 232Th are listed based on their decay energy levels and their ratios in total counts of isotopes decay, which are implemented in the TRIM model creation and risk evaluation. As an example of material selection in TRIM model creation, we select helium as alpha particle element in the ion data by using the periodic table function. Furthermore, the energy of different isotopes decay can be filled in the space “Energy (keV)”. (C) Step 3: To confirm package stack-up information As the packages are typically composed of different materials, their stack-up sequence, thickness, and properties of each layer are important and must information for target layers input in TRIM. In the following simulation cases, we acquired the layer’s thickness information from the SEM (Scanning Electron Microscope) crosssection pictures and marked the possible traces of alpha particles emitted from source material to memory die transistors. The distance required to stop an alpha particle is a function of its energy (input in “ion data”) and the properties of the target material

Fig. 7.19 Isotopes decay energy distribution from uranium (238 U), actinium (235 U) and thorium (232 Th) decay series

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.20 LC-FC alpha particle emission modelling by TRIM

(ex: material’s density input in “target data”). Further, the stopping powers can be converted from one material to another based on the material’s density as well. In this paper, a critical part of assembly stack-up structure covering the IC chip attached to substrate front side in different memory package types are evaluated with the hypothesis that alpha particles emitted from substrate materials such as solder resist and prepreg by using the TRIM simulator. In present DRAM packages, AER of solder resist used for substrate is not well controlled within the ULA range. For example, the commonly used SR (Solder Resist) material has been characterized on the AER value around 0.015 cph/cm2 . In the LC-FC (Low-cost Flip Chip) model, the assumption of the alpha particle emitted from substrate SR surface to go through MUF (Molded Underfill), PI (Polyimide), PSV (Passivation), Al pad and were simulated as shown in Fig. 7.20. For the purpose to compare the decay energy required for alpha particle striking on DRAM cells, not only the emission from solder resist but also from prepreg material are simulated in both FC and LC-FC radioactive models. The calculated result shows the decay energy of 5050 keV is enough for the alpha particle transmitted from solder resist to DRAM transistor with a travel distance around 29 µm. Next, the MUF thickness in conventional FC packages is added 10 um to simulate corresponding travel range and threshold decay energy for the scenario of typical Cu pillar height and MUF gap. Some papers had found there are many different radioactive isotopes. 238 U (Uranium), 235 U (Uranium) and 232 Th (Thorium) and their associated daughter products have the highest activities of the naturally occurring radioactive species. Thus, they are the dominant source of alpha particles in materials. The count percentage of isotopes decay energy higher then simulated threshold energy in FC and LC-FC model in Fig. 7.21. Alpha particle with a longer travel range requires higher decay energy to strike DRAM cell, which has lower probability of soft error fail.

7.6 Alpha Particle Emission Simulation in Memory Device

179

Fig. 7.21 Threshold decay energy and the corresponding isotopes decay probability for FC and LC-FC alpha particle emission modelling

In the LPDRAM package model shown in Fig. 7.22, alpha particle emitted from solder mask through 10 µm DAF (Die Attach Film) and 45 µm thick DRAM die are simulated and the threshold energy is around 7250 keV with 47 µm traveling range.

Fig. 7.22 Threshold decay energy and the corresponding isotopes decay probability for LPDRAM alpha particle emission modelling

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7 Reliability Simulation and Modeling in Memory Packaging

Besides alpha particle model in DRAM packages, the simulation for controller in mNAND packages using flip chip attaching is also investigated. As shown in Fig. 7.23a, b, the alpha particle transport scenarios of emission from substrate materials are drawn in the cross-sectional images. The scenarios include the traveling range of alpha particle emissive from non-low alpha prepreg in Path 01 and Path 02, and from solder resist in Path 03. From the simulation results in Fig. 7.24a–c, the risk of soft error is determined by some key factors such as alpha particle distance between emission source to target material, material density in the transportation path and isotopes’ impurity decay energies. The path 01 in Fig. 7.24a reveals the threshold decay energy 8400 keV is required for an alpha particle emitting from prepreg and through the underfill, polyimide, Aluminum and SiO2 layers to controller bulk silicon where the P/N junctions located. This high energy level is only observed in Thorium decay series where the alpha particle (helium ion) emitted from radioactive impurities of isotope 212 Po (Polonium), so we could conclude that the soft error risk of Path 01 is lower. Besides, the underfill material composition (ex: filler content %) will be key factor of SER (Soft Error Rate) risk in flip chip model, and low alpha MUF with higher filler density will benefit the SER reduction as well. In path 02 as shown in Fig. 7.24b, the highest decay energy 8954 keV is applied in the simulation model. However, the alpha particle transportation distance is mitigated by the Cu layer as its high material density (8.92 g/cm3 ) and only reach underfill layers. Another scenario in Fig. 7.24c that the potential sources of alpha particles emitted from substrate solder mask (or solder resist) to the IC transistor layer is simulated in Path 03. The short die gap increases the SER risk and only the threshold energy of 6220 keV is needed for the alpha particle to reach bulk Si layer.

7.7 Summary and Recommendations In summary, we could conclude key takeaways from this Chapter as in follows: . Failed pull force decreases with increasing pull distance between the pull hook and the first bond. Stress from FEA simulation increases with increasing pull distance under the same pull force, which is consistent with experimental results. Sample with low wire loop results in lower failed pull force compared to that with high wire loop when the same pull location is used [1]. . The switch to silicon spacer stacking technology solves the package-level reliability problem at the expense of lower board-level SJR. This raises the concern that high density packages may not meet the more stringent requirements, of some market segment. Therefore, solutions for both package-level and boardlevel problems must strike a balance to optimize the reliability of high density DRAM packages [2]. . The critical factors influencing die deflection and maximum principal stress are die thickness and overhang distance while substrate thickness and bonding temperature are less dominant [8].

7.7 Summary and Recommendations

181

Fig. 7.23 mNAND controller die SEM cross sections with a alpha particle traveling path 01 & 02 b alpha particle traveling path 03

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7 Reliability Simulation and Modeling in Memory Packaging

Fig. 7.24 Simulated alpha particle transportation distance of scenarios a Path 01 b Path 02; c Path 03, same as that drawn in Fig. 7.23 cross-sectional images

. Overhang die with high modulus DAF can significantly decrease die deflection to one-third of original during wire bonding process. Further applying high modulus DAF to all stack layers can decrease wire bonding die deflection and stress, but not significant [3, 4]. . In summary, the bar fixtures in 3 PB test are suggested to apply force within the die area and the smaller span is recommended to produce flexure stress distribution ideally. Regarding to 4 PB test, the fixture diameter has less effect, and the larger top span together with smaller bottom span is suggested to achieve ideal flexural stress distribution during package strength test [9, 10]. . Different design variables such as package stack-up, Cu pillar pattern can be used to improve the solder joint reliability performance. A well calibrated model helps make crucial design decisions on substrate thickness, pad sizes and choice of material for any of the critical layers.

References

183

. This simulation of alpha particles emissive from substrate materials to the die transistors in various memory packaging models have been investigated by using Monte Carlo code (TRIM). The alpha particle traveling range, threshold energy required to induce SE and quantitative risk probability are relevant to the model considerations on the alpha source materials, their properties, package stack-up dimension and the energy of unstable isotopes decay series. All the study results could be used as a guidance in the package design stage. Acknowledgements The authors would like to specially acknowledge the help and support received from the colleagues in Micron simulation team (H. W. Ng, F. Che, C. Glancey and J. Y. Lai) who have contribute this Chapter with their previous published studies and advise to our better understanding on simulation approaches in memory packaging.

References 1. Che FX, Wai LC, Chai TC (2018) Failure mode and mechanism analysis for Cu wire bond on Cu low-k chip by wire pull test and finite element analysis. IEEE Trans Device Mater Reliab 18(2):163–172 2. Ng, Hong Wan (2012), High-density DRAM package simulation. In: 2012 IEEE 14th electronics packaging technology conference (EPTC), pp 700–704 3. Yang L, Ji Z (2018) High modulus DAF introduction to decrease thin die WB crack issue. In: IEEE 20th electronics packaging technology conference 4. Ye N, Li Q, Zhang H, Ji Z, Yang X, Chiu CT, Takiar H (2016) Challenges in assembly and reliability of thin NAND memory die. In: IEEE 66th electronic components and technology conference, pp 1840–1846 5. Shin D, Kwak D, Song Y (2006) Characterization of wire bondability on overhang structured chip in multi-chip package. In: 2006 international conference on electronic materials and packaging 6. Yeh CL, Lee YC, Lai YS (2011) Vibration and bondability analysis of fine-pitch Cu wire bonding. In: 2011 international conference on electronic packaging technology and high density packaging, pp 577–583 7. Sawada K, Aoki H, Matsuura E, Mukaida H, Minami F (2015) Estimation method of cracking probability of stacked overhang die during wire bonding. In: ICEP-IAAC 2015 proceedings, pp 776–780 8. Qin I, Yauw O, Schulze G, Shah A, Chylak B, Wong N (2017) Advances in wire bonding technology for 3D die stacking and fan out wafer level package. In: IEEE 67th electronic components and technology conference, pp 1309–1315 9. Liu V, Arifeen S, Bassett C, Chung MH, Gan CL, Takiar H (2021) Mechanical suite of flexural bending method for electronic memory packages. In: 2021 IEEE international conference on sensors and nanotechnology (SENNANO), pp 45–49 10. Liu V, Chen CM, Chen J, Chung MH, Gan CL (2022) Study of robust package strength characterization of memory packages for handheld application. Memories–Mater, Devices, Circ Syst 3(2022):100018 11. Sinha K, Glancey C (2021) Influence of BGA design parameters on solder joint reliability. In: 2021 IEEE 23rd electronics packaging technology conference (EPTC), pp 413–418 12. Syed A (2004) Accumulated creep strain and energy density based thermal fatigue life prediction models for SnAgCu solder joints, 2004 proceedings. In: 54th electronic components and technology conference, pp 737–746

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13. Madenci E, Guven I, Kilic B (2003) Fatigue life prediction of solder joints in electronic packages with ANSYS. Kluwer Academic Publishers 14. Agrawal A, Fay O, Johnson M (2014) Bump pattern optimization and stress comparison study for DCA packages. In: 2014 electronic components and technology conference, pp 2014–2019 15. Son K, Kim G, Ryu H, Kim YC, Park YB, Yang CW, Park GT, Han JS, Son HY, Kim NS (2019) Effects of NCF and UBM materials on electromigration reliabilities of Sn-Ag microbumps for advanced 3D packaging. In: 2019 IEEE 69th electronic components and technology conference (ECTC), pp 2247–2251 16. Ziegler J. Interactions of ions with matter. www.srim.org

Chapter 8

Interconnects Reliability for Future Cryogenic Memory Applications

8.1 Introduction The utility of the world internet is on the rise as it is recorded that 46% of the world’s population have become internet users who generates data traffic of up to 8 zettabytes daily. This increase has triggered the growth of data center infrastructure as processing, storage, and communication system in the digital world. The data center itself has contributed 1.5% to the total world electricity consumption and this is expected to increase with time. The proportion of energy used in the data center covers 52% for information technology (IT) equipment, 38% for cooling and 10% for supporting devices. One of the problems faced by these centers over the years is the cooling of the information technology (IT) components. Key literature reviews of interconnect materials (solder alloys, solder behavior especially in its ductile to brittle transition temperature, polymers under cryogenic conditions), mitigation strategies of prevention of those associated wearout failure modes at cryogenic temperature are revealed in this chapter. Recent progress of industry initiatives in cryogenic memory computing will be discussed in this chapter. At the end of this chapter, summary and key recommendation of future works have been provided for better clarity and reference purposes.

8.2 Why is There a Need of Cryogenic Memory? With the advent of quantum computing, the need for peripheral fault-tolerant logic control circuitry has reached new heights. In classical computation, the unit of information is “1” or “0”. In quantum computers, the unit of information is a qubit which can be characterized as a “0”, “1”, or a superposition of both values known as superimposed state. When CMOS gets cold enough, for example, data leaks from a CMOS chip stopped completely [1, 2]. It became almost non-volatile. Performance increased © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6_8

185

186

8 Interconnects Reliability for Future Cryogenic Memory Applications

Fig. 8.1 Typical future qubit quantum chip being flip chipped onto interposer and MCM (Multi chip module) and then assembled onto a PCB (Printed circuit board), all integrated in cryogenic computing [3]

to the point that memory could catch up to the speed of processors, eliminating one of the most stubborn bottlenecks in the IC (Integrated Circuits) industry. At very cold temperatures, between 4 and 7 K, wires effectively superconduct, allowing the chip to communicate over long distances using little energy. Cryogenic systems have an added benefit. They can suck the heat out of a stack of memory chips a lot faster than A/C, allowing far greater density of stacked, cubed. Typical quantum chip module is shown in Fig. 8.1. Nowadays, the demand for data center computing services is continuously rising, increasing the total energy consumption of data centers worldwide. In particular, a large portion of the electrical power provided to a data center is drawn by cooling systems, which must guarantee safety thermal requirements for the correct operation of the Information Technology (IT) equipment [1]. Thus, improving the energy efficiency of the data center cooling infrastructure while guaranteeing the thermal constraints is imperative [2], and it can be obtained by combining the use of new cooling technologies and the chances by the design of advanced control systems. Liquid Immersion Cooling (LIC) is a plausible and technologically interesting method to cool high heat flux electrical components in data centers. Lionello et al. [2] derived a control-oriented model of liquid immersion cooling systems, i.e., systems where servers are immersed in a dielectric fluid having good heat transfer properties.

8.3 Immersion Cooling Technology

187

8.3 Immersion Cooling Technology Historically, two types of immersion cooling methods in current market which is used for various industries (as tabulated in Table 8.1). Cooling technology has been applied to photovoltaic cells, data servers, crypto-mining, electric car battery and power transformers. This is because the photovoltaic cells need a cooling system to maintain efficiency to increase solar photovoltaic performance. The rapid development of computing from data center computers and servers requires this technology to improve its efficiency while the 2-Phase immersion systems are perceived as a viable technology to fulfill the power density and energy efficiency of the high-performance computing market in crypto-mining processes. In electric car batteries, immersion cooling could cool the entire cell surface and improve temperature uniformity by reducing the local heating effect on the positive and negative electrodes compared to indirect cooling. Furthermore, the thermal energy management using the system was also found to have the ability to overcome the problem of losing most energy to the environment as heat during transformer operation. Immersion cooling technology was concluded to be feasible and superior to traditional techniques as a cooling method to save energy which is supported by several advantages such as lower cost, easy installation, and maintenance because it uses nonhazardous and non-flammable liquids, simpler construction design and easier maintenance [4, 5]. Single-phase immersion cooling involves using coolants to exchange heat without any phase changes [4]. This method is safer because of this as this means there is no gas or vapor produced by the cooling system, hence, protecting the system from explosion due to excessive pressure. Two-phase immersion cooling. This cooling technique uses coolants to exchange heat when liquid–vapor phase change occurs [4], furthermore, vapors are produced by the system when removing heat. Twophase immersion cooling has the unique attributes of reducing environmental impact, simple design, increase power density up to 10 times. There are several types of fluid that can be used for cooling and the use of liquids is one of the most prominent and efficient as in Table 8.2, with methods that can be directly or indirectly implemented [5]. For the direct method, the fluid must be non-conductive material because the fluid is in contact with electronic devices. Shah et al. [5] investigated various reliability performances of oil-immersion cooled semiconductor fluids and their mechanical properties because exposure of hydrocarbon fluids may alter the length of the useful life of components in fluids. Table 8.1 Types of immersion cooling techniques [4, 5]

Cooling types

Intended industries

Single phase

Solar cells, transformers, IT infrastructures

Two phase

Data centers and servers

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8 Interconnects Reliability for Future Cryogenic Memory Applications

Table 8.2 Some of the known immersion cooling fluids [5]

Type of cooling fluids

Applications

Water

Data centers, stacked die in memory, solar cells

Mineral oil

Servers, transformer

8.4 Module Packaging for Quantum Computing 8.4.1 Module Packaging for High Performance Computing MIT researchers [3, 6] established one way to address this demand is with the use of flip-chip 3D integration of superconducting multi-chip modules (S-MCM) with micro-bump-based interconnects to couple to multiple superconducting qubit chips electrically and mechanically with or without interposers. Indium micro bump-based flip-chip interconnects, capable of maintaining extremely low interconnect resistance, have shown potential advantages for qubit packaging. 3D integration of the readout and control of superconducting qubits has been demonstrated through inductive and capacitive coupling to structures on a superconducting module that is bumpbonded to a qubit chip. The whole overview of module packaging architecture for quantum computing is illustrated in Fig. 8.2. Kudalippalliyalil et al. [6] revealed packaging scheme for a novel quantum chip optoelectronics interposer (QuIP) that will serve as an interface between multiple components and chiplets of the same or different functions to create such a quantum module on an integrated chip for the first time. The interconnects between these components can be either electrical or optical waveguides (as depicted in Fig. 8.3). Auburn university researchers [7] reported use of Molybdenum (Mo) as a substrate for S-MCMs for cryogenic applications (as shown in Fig. 8.4). Mo has higher fracture toughness and ductility compared to Si, which enhances the robustness and reduces the chances of breakage during assembly and fabrication processes. But use of Mo for cryogenic packaging has remained unexplored. From room temperature to ∼4 K, thermal contraction of Mo (∼950 ppm) is closer to Si (∼220 ppm) than most other metals. All bonded assemblies demonstrated similar resistance against temperature curve after 10 thermal cycles (from 25 to −269 °C), which proves the reliability of Indium (In) bonding.

8.4.2 Key Challenges and Reliability Considerations with S-MCM in Cryogenic Temperature Superconducting of single-flux-quantum-based (SFQ) digital integrated circuits (ICs) are a promising candidate for high-speed and ultralow energy dissipation computing systems. Circuits based on several versions of SFQ-type logic, and

8.4 Module Packaging for Quantum Computing

189

Fig. 8.2 3D integrated qubit chips attached to the rigid area of superconducting rigid-flex through the interposer and who cryogenic computing module [3]

AQFP (Adiabatic Quantum-Flux-Parametron) logic have been demonstrated with complexities reaching up to a few tens of thousands of gates. Packaging many superconducting ICs using micro bump (15 µm or less) technology and performing high throughput, nearly lossless data transfer between various superconducting and/or complimentary metal-oxide semiconductor (CMOS) chips are highly desirable for a hybrid superconducting computer architecture, but this density has not yet been demonstrated. Seldom could metals and alloys maintain excellent properties in cryogenic conditions, such as ductility, owing to the restrained dislocation motion [7, 8]. Table 8.3

190

8 Interconnects Reliability for Future Cryogenic Memory Applications

Fig. 8.3 Example of conceptual integration scheme of electronic and photonic quantum components in a heterogeneous packaging [6]

Fig. 8.4 Wearout failure mechanisms of Ball bonds (Au, Cu) post temperature cycling or unbiased HAST (Highly accelerated stress test) test-to-failures [7]

tabulates overall key interconnect brittle fracture wearout failure mode of especially in first level solder bump electromigration and second level solder joint electromigration in semiconductor device packaging. Typically, materials transition from ductile to brittle fracture will affects its solder joint reliability at S-MCM level and SFQ flip chip micro bump solder joints.

8.5 New Materials for Cryogenic Memory 8.5.1 Solder Joint Evolutions at Cryogenic Temperature (CT) Materials with high ductility at low temperatures (LT) are desired for cryogenic applications in space exploration, superconducting devices, nuclear reactors, and storage of cryogens. Face-centered-cubic (FCC) alloys are promising in this regard, as they do not exhibit an obvious ductile-to-brittle transition at low temperature. Fatigue behavior and mechanical shock on solder joint reliability of electronic products are considered especially at cryogenic temperature condition (~ −196 °C). Fatigue crack

8.5 New Materials for Cryogenic Memory

191

Table 8.3 Typical package and board level reliability stress testing to address known brittle fracture failure at cryogenic temperature condition (−196 °C) Reliability conditions

Possible failure modes

Technical considerations

T/C-B, −55 °C for 15 min, + 25 °C for 15 min, air to air cycling, 1000 cycles [9]

Solder bump fatigues and brittleness, underfill (UF) micro cracking at S-MCM level

For overall memory thermomechanical reliability performance especially in meeting cryogenic memory applications

T/C-C, −65 °C for 15 min, + 150 °C for 15 min, air to air cycling, 500 cycles [9]

Solder bump fatigues and brittleness, UF micro cracking

For overall memory thermomechanical reliability performance especially in meeting cryogenic memory applications

Biased HAST 110 °C, 85% RH Substrate trace shorts, (Relative Humidity) soak, Vcc leakage, bump shorts at dependent upon product being S-MCM level tested, 264 h [10]

For substrate, package (EMC, UF) and ball bond moisture reliability performance especially in cryogenic memory applications

Unbiased HAST 110 °C, 85% RH soak, no electrical bias, 264 h [11]

Substrate trace shorts/leakage, bump shorts

For substrate, package (EMC, UF) and ball bond moisture reliability performance especially in meeting cryogenic memory applications

LTSL −40 °C soak, no electrical bias, 1000 h [12]

Solder ball fatigue cracks, bump opens

Long term interconnects (first ball bond, bump, second level solder joint) intermetallic formation and growth kinetics at cryogenic temperature condition

Board level temperature cycling, 1.60 mm/2.36 mm double sided board, 0C for 10 min, +100 °C for 10 min, air to air cycling, end after 63.2% cumulative failures, >=1500 cycles [13]

Solder joint fatigue and brittle fracture at S-MCM level

To meet second level solder joint reliability based on assembled package and board system

Board level drop test, 1.0 mm single sided board, 1500 g 0.5 ms ½ sine pulse, −Z axis, end after 63.2% cumulative failures, >= 10 drops [14]

Solder joint fatigue and brittle fracture at S-MCM level

For better package drop and board level drop performances especially for handheld application

of bulk solder is typically stressed by temperature cycling test, and main failure mode of drop shock test is intermetallic compound (IMC) break at solder joint interface. Ductile fracture occurred at the solder layers at room temperature (25 °C). As the temperature decreased from 25 to −150 °C, the fracture of the Cu/Sn3.0Ag0.5Cu Solder/Cu joint transformed from ductile to brittle. Fracture penetrating the solder layer and the IMC interface was characterized in ductile–brittle mixed fracture. The completely brittle facture occurred at the IMC layer at the cryogenic temperature of

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−150 °C. It was attributed to the cryogenic temperature factor severely inhibited the movement of dislocations, resulting that brittle fracture was prone to came up at the layer with high density dislocations. When the temperature dropped drastically, the IMC was easily cracked at the interface due to mutual extrusion, further evolved into micro-voids causing fracture behavior at the IMC in the end. Graber et al. [15] designed a cryogenic power electronics at megawatt-scale using a new type of press-pack insulated-gate bipolar transistor (IGBT). Reliability hazards for high voltage device microcircuits operating at cryogenic temperatures have been analyzed and three types of degradation mechanisms specific to low temperatures have been revealed: parametric instability due to hot carrier injection, mechanical damage due to increased stresses during excursions to cryogenic conditions, and damage due to high-voltage and high-current transient spikes [16] (Table 8.4).

8.5.2 Implications of Solder Joint Brittle Fracture and Mechanical Performance in High Performance Computing Applications In general, data centers which use high performance computing are installed within a center environment which are free of mechanical shocks and vibrations. Hence, concerns of vibration and drop shock performances are lesser. Owing to this, lesser engineering efforts in investigating mechanical shock and vibration performances with S-MCM module. Development efforts are focused on understanding suitable solder alloys and types of epoxy molding compounds which could handle cryogenic temperature (−196 °C). Figure 8.5 illustrates typical cross-sectional of wire bonded memory packaging (especially in cryogenic environment) which is assembled with epoxy molding compound (with embedded metal fibers), cross-linked metal fibers solder alloy (which is coated with Indium/ SnPb surface finishes [25], and it produces higher package resistance and modulus at cryogenic temperature. These key package structures are critical to maintain its overall package warpage while produces higher interconnect reliability at operating condition of −196 to 0 °C. Some of end data center customers demanded device functionality and electrical connection for long term immersion in liquid nitrogen or liquid helium environment. Device characteristics of dynamic random-access memory (DRAM) devices at cryogenic temperature are important in terms of DRAM cell retention lifetime especially in two distinct regions with the retention time of most cells increasing rapidly with lower temperature exceeding our longest test of 90 min pause retention. The remaining cells show slight variation of retention time with temperature. The number of these cells depends on the part tested but is low enough that either redundancy or error-correction code (ECC) can be used to hide these cells from the system [26].

8.6 Characterization of Solders at Cryogenic Temperature

193

Table 8.4 Technical factors influencing board level temperature cycling performance and its associated specifications and considerations Potential new materials/metrology

Compositions/methodology

Technical considerations

Face-centered-cubic (FCC) CoCrFeNi high entropy alloy (HEA)

(25:25:25:25 atomic %)

Excellent combination [8, 17] of high strength and high ductility at extremely low temperatures. The lower stacking fault energy (SFE) of CoCrFeNi at the liquid-helium temperature directly facilitates the formation of abundant twins

Indium based solder alloy In-doped solder alloy (ductile at cryogenic temperature) than non-In-doped solder alloy (brittleness). In-3Ag, In-34Bi, In-51Bi and In-32Bi-20Sn (weight %)

References

Significant rise in [20] impact values at cryogenic temperature are observed in In-32Bi and In-51Bi solder alloys indicating no loss of ductility at cryogenic temperature even after temperature cycling stress Lower Bi additions (1% and 1.5%) alloys showed significantly worse TC than that of higher Bi additions (3% and 4%) alloys. SnAgNi-3% Bi-0.05% Sb gives better temperature cycling performance [18, 19] (continued)

8.6 Characterization of Solders at Cryogenic Temperature 8.6.1 Behavior of Solder Alloys and Polymers at Cryogenic Conditions Researchers are actively looking for cryogenic compatible interconnects which could operate at cryogenic temperature (~ −196 °C) [27, 28], and there is tendency of solder ball changed from ductileness to brittleness. This is the top key challenge

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Table 8.4 (continued) Potential new materials/metrology

Compositions/methodology

Technical considerations

References

Solder ball materials characterization using liquid nitrogen shear test apparatus

Real-time solder ball shear test onto a BGA (Ball Grid Array) component which is immersed into liquid nitrogen sample holder

Provide new real-time [21] shear strength of solder balls in a low-temperature environment and then even more in the liquid nitrogen environment at cryogenic temperature of −196 °C

Solder alloy ductile to fracture transition temperature

High purity Sn, Sn-0.5%Cu and Sn-0.5%Cu (Ni) alloys have a ductile to brittle transition temperature, around −125 °C

The transition [22] temperature of high purity Sn, Sn-0.5%Cu and Sn-0.5%Cu(Ni) alloys is around − 125 °C The Ag containing solders show a transition at higher temperatures: in the range of −78° to − 45 °C

High-density substrate fabricated from thin particles containing organic laminates (−180 to 25 °C)

No new materials being introduced in this study

Passive resistors [23, 24] showed signs of metallization peeling and separation after thermal cycles, which is associated with solder ductile to brittle transition at −180 °C)

Fig. 8.5 Micron’s proposal future cryogenic compliant memory package construction with embedded fibre and granule fibre metal in SAC solder balls for high performance computing application [25]

8.7 Materials/Memory Modules for Quantum Computing

195

to be resolved for cryogenic memory computing. It is easy to fracture the solder ball at cryogenic condition. Table 8.5 reveals key materials behaviors at cryogenic temperature of various solder alloys in terms of fracture modes, IMC growth rate and ductile to brittle transition temperature. Another key concern relies on evolution of epoxy molding compound at cryogenic temperature. In general, the strength and modulus of materials at cryogenic temperature are compared with that at room temperature. According to these studies, some functionalized polymers showing immense potential for cryogenic application, such as carbon-nanotube (CNTs)/EP, GO/EP and phosphoric EP and so on. Meanwhile, for the polymer used in the LOX (Liquid Oxygen) environment, improving the flame retardancy us and fracture toughness (KIC) of polymers increased. While the impact resistance, tensile fracture strain of polymer decreased dramatically. According to these studies, some functionalized polymers showing great potential for cryogenic application, such as CNTs/EP, GO/EP and phosphoric EP and so on. Meanwhile, for the polymer used in the LOX environment, improving the flame retardancy, toughness of polymer and thermal stability is a good method to enhance its LOX compatibility [29].

8.7 Materials/Memory Modules for Quantum Computing Operation at cryogenic temperatures requires different materials, packaging, testing, and cooling systems, much of which will require new development. State-of-theart systems package a few superconductor ICs in a commercial cryostat. Scaling up systems with higher complexity chips and multi-chip modules will require further reduction of power consumption by all components. Josephson junctions are extremely sensitive to magnetic fields and require shielding, which becomes more challenging as system volumes grow [36]. A superconductor electronic (SCE)circuit-based system needs to operate at temperatures ranging from 4 to 77 K. The cooling is performed by using cryocoolers or by liquid cooling using refrigerants such as Liquid Helium (LHe) or Liquid Nitrogen (LN2). Liquid cooling is featured as follow: (1) Often produces a smaller temperature gradient between the active devices and the heat sink than in vacuum cooling, making it easier to bias all the chips at their optimum design temperature. (2) Also produces a more stable bias temperature due to the heat capacity of the liquid that tends to damp any temperature swings produced by the cooler, often allowing liquid cooled devices to perform better than in vacuum mounted parts [37]. Hence, necessary considerations must be given in providing solid and compatible packaging modules and architectures used in cryogenic conditions (as shown in Table 8.6).

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Table 8.5 Key materials characterization and studies at cryogenic temperature especially on solder alloys Materials characterization items

Engineering observations

References

SAC 305 immersion in liquid nitrogen (−196 to −230 °C)

It shows strength of SAC305 solder joint [30] increased from 35.54 MPa at 0 h to 41.70 MPa at 72 h, 38.0 MPa at 168 h, and 40.51 MPa at 600 h. In addition, the ductility of the solder joints after 24 h of deep cryogenic can be comparable to that of the SAC305 solder joints without cryogenic treatment. The strength and ductility of the solder joint decreased with longer immersion time IMC growth of SAC 305 is not observed

SnPb eutectic solder soaked into − 196–25 °C

IMC in the solder joint does not grow, which could not cause significant influence on the reliability of the solder joint

[31]

SAC 305 solder joint study under 25, 0, −40 to −80 °C

The fracture position of joints changes from solder matrix to solder/Cu6 Sn5 interface with decreasing the testing temperature, exhibiting a ductile-to-brittle transition in fracture mode The temperature corresponding to the fracture position transition increases as joint thickness decreases

[32]

Low temperature brittle fracture of bulk Sn-based solders

The ductile to brittle transition begins at [33] the temperature between −40 °C and − 60 °C and the fracture modes have both intergranular fracture and trans granular fracture for Sn solder A rod-like structure is observed both in the fracture surface of 99.3Sn0.7Cu and SAC305 solder Trans granular fracture occurs because of the presence of the rod-like structure as the second phase structure The fracture mode of 62Sn36Pb2Ag solder is quasi-cleavage fracture and Ag3 Sn particles are observed to be the crack sources at low temperatures

SAC Pb free solders

The transition temperature of high purity [34] Sn, Sn-0.5%Cu and Sn-0.5%Cu (Ni) alloys is around −125 °C. The Ag containing solders show a transition at higher temperatures: in the range of − 78° to −45 °C. The highest transition temperature of −45 °C was measured for Sn-5%Ag, which is ductile only above − 30 °C (continued)

8.9 Recent Progress by Key Industrial Players

197

Table 8.5 (continued) Materials characterization items

Engineering observations

Solder alloy ductility at cryogenic temperature

Solder systems comprised of mainly Sn [35] showed classic ductile to brittle behavior. The more Pb an alloy contained, the more the behavior trended towards that of a pure FCC material

References

8.8 Reliability Evaluation for Cryogenic Memory Packages Micron evaluated DRAM package warpage simulation and extrapolated to −200 °C. Simulation results suggest low temperature warpage can be extrapolated from near room temperature package warpage. This is expected since we linearly extrapolate our material properties to low temperatures. Need characterization data to confirm extrapolation is reasonable to extreme low temperatures. Need to explore other packages (e.g., high silicon content, different warpage) to confirm behavior. The model used for exploring package warpage simulation at extreme low temperatures (−200 °C) as in follows (as depicted in Fig. 8.6): Model details: (1) 1/4 symmetry, minimally constrained model (2) Temperature-dependent material properties (3) Viscoelastic properties for EMC and SR (Solder resist). Table 8.7 reveals input parameters used in DRAM package warpage simulation and modeling. From the simulation results, it shows there might be possibility of high warped package (>100 µm) exceeding −150 °C under long term immersion under cryogenic temperature (as illustrated in Fig. 8.7). Hence, efforts must be made to replace high cross-linked or metal fibers of epoxy molding compounds to further optimize the package warpage within ± 80 µm. However, it is still too early to path find the new composite materials at this moment and further consideration should have been addressed to understand the evolution of CTE (Coefficient of Thermal Expansion) at cryogenic temperature.

8.9 Recent Progress by Key Industrial Players Most quantum computers emerging today have one common need: critical elements of the system need to be cooled to near zero degrees Kelvin temperature. The cooling solutions seen today are quite varied but most cooling systems used are based on a mixture of isotopes of helium that are pumped across the stages of a multistage dilution refrigerator.

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Table 8.6 Some of those cryogenic modules and packaging architectures used in quantum computing Key module construction Institutions in HPC

Cryogenic compliant materials

Qubit and interposer chips are bump-bonded using thermocompression bonding

Indium bumps are used [38] only to connect the ground planes of the two chips; they do not carry active signals Bump bonding is performed at 105 °C in a commercial thermocompression bonding system with a post-bond lateral accuracy of < 1 µm

MIT, United States

References

The superconducting MIT, US multichip module (SMCM) with 16 bonded chips was reflowed and underfilled with cryogenically stable adhesive

The use of indium-based [39] micro bumps to form interconnects between an S-MCM and superconducting ICs, and its electrical performance, are discussed

Cryogenic multiplexer IBMT, Germany system can be described as a flexible and modular host–client architecture. One or more clients (Multiplexer-PCBs) are connected to the host with an appropriate host-adapter

The materials a [40] transponder can be attached to or can be in proximity to in that case, are HDPE for our multi-well sample substrate or metals like stainless steel and aluminium for the storage tank and the standard memory card housings

5 DRAM modules being Rambus, US immersed into cryotube. DRAM modules being immersed into the liquid nitrogen at a speed that depends on the test to be done

Use as off-the shelf [26] DRAM module Examples of these speeds are 0.33 inch per minute (for “gradual dip tests”) or within five seconds (“fast dip tests” for mechanical shock tests)

Cryo-DRAM by Georgia Tech, US characterizing off the shelf DRAM chips at the temperature range of 80 K to 160 K

Use as off-the shelf DRAM module

[18]

(continued)

8.9 Recent Progress by Key Industrial Players

199

Table 8.6 (continued) Key module construction Institutions in HPC

Cryogenic compliant materials

Reliability of RF MEMS US army research Lab, US Use cryostat RF MEMS switches operating in a switches cryogenic (< 6 K) environment while monitoring the repeatability of their contact resistance (Rc) over time

References [19]

Fig. 8.6 DRAM package warpage simulation at extreme low temperatures (−200 °C)

Table 8.7 Simulation input parameters for DRAM package warpage simulation and modeling Specifications

Mold cap thickness, µm

360

Die/DAF thickness, µm

120/10

Mold cap clearance, µm

230

Substrate description

290 um 4L

Fig. 8.7 Simulated DRAM package warpage at extreme low temperatures (−200 °C)

Warpage (um)

Items

200 175 150 125 100 75 50 25 0 -25 -50 -200 -150 -100 -50

0

50 100 150 200 250

Temperature (°C)

Most superconducting qubit-based systems require large refrigeration units to house the critical components. Quantum computing is a paradigm constantly evolving now, with innovative technologies being introduced routinely. This makes it difficult

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to predict the technology trends specifically, although some general trends can be noted: Key short-term challenges: (1) Efforts will continue reducing errors through technology, architectural and packaging innovations. (2) Development of room-temperature alternatives will accelerate. (3) Additional gate types and increased gate depths will be supported. (4) Integration of control/measurement plane logic at low power with a qubit/gates chip as a solution to avoiding complex wiring; reducing errors due to crosstalk will be emphasized. (5) Incremental scaling solutions will be demonstrated. (6) Verifiable quantum supremacy demonstrations on systems with limited programmability will happen. Key long-term challenges: (1) Availability of products with versatile programming capabilities and scalability that target a wider application base will be offered. (2) Significant reductions in form factor will take place, with heterogeneous integration playing a vital role. (3) Room-temperature quantum computers will become mainstream. (4) Quantum supremacy will be demonstrated on fully programmable quantum systems. (5) Potentially, several alternative implementations and architectures with modern technologies will appear, which are difficult from those predicted at this point. Appropriate packaging reliability testing (as shown in Table 8.8) should be adopted in qualifying future cryogenic compliant modules or packages to ensure its solder joint reliability and package warpages especially for cryogenic memory computing end applications.

8.10 Recent Progress of Industry Initiatives in Cryogenic Memory Computing Out of those listed key semiconductor players, MIT research lab [3, 7] has established innovative ideas in terms of packaging solutions in SCE (Superconductor electronic) chips and 3D S-MCM module packaging solutions. Microsoft has revealed a project scaled quantum computing with topological qubits that are theorized to be inherently more stable than qubits produced with existing methods without sacrificing size or speed. Graphic processor manufacturer Nvidia kicked-off a new platform built for quantum research and development across AI (Artificial Intelligence), highperformance computing (HPC), healthcare, finance, and other disciplines. Table 8.9 summarizes all those key initiatives. We are in fact on the right track of keep exploring

8.10 Recent Progress of Industry Initiatives in Cryogenic Memory Computing

201

Table 8.8 All industrial package reliability test methods against cryogenic memory applications Type of test methods

IPC/JEDEC standard

Industrial test conditions

Risks/defects for cryogenic applications

Package reliability-LTSL (Low temperature storage life)

JESD22-A119A [12]

Condition A: −40 °C (−10/+0) °C

Package reliabilityLTSL (Low temperature storage life)

Package reliability-TC (Temperature cycling)

JESD22-A104 [9]

Condition B: −55 °C to + 125 °C

Package reliability-TC (Temperature cycling)

Package reliability-TC (Unbiased/biased HAST)

JESD22-A118 [41]

130 °C/85% RH

Package reliability-TC (Unbiased/biased HAST)

Device reliability-LTOL (Low temperature operating life)

JESD22A-108D [42]

Not at cryogenic conditions but at junction temperature Tj < 50 °C, Vcc Max. duration up to 1 K hours

Memory device characteristic at lower temperature

Package warpage

JESD22-B112B [43]

Conditions: 25C, 150C, 260C, 150C, 25C

Materials sets CTE& shrinkage properties correlate to its package warpage

Board level temperature cycling

JEDEC/IPC-9701A [13]

Temperature range: − 40 °C/ + 125 °C|10 min dwell Board type: 2.36 mm Single Sided board. 1.6 mm Single Sided board Test duration: 63.2% cumulative failure

Solder joint microcracks after temperature differences

Board level drop test

JESD22-B111A [14]

Test profile: 1500 g 0.5 ms ½ sine pulse Direction: −Z axis Board type: 1.00 mm single sided board Test duration: minimum of 30 drops and up to 63.2% cumulative failure

Solder joint microcracks, package microcracks (die) after module drop/phone drop

Board level monotonic bend test

JEDEC/IPC-9702 [44]

Direction: −Z axis Board type: 0.6/0.8/1.0/2.35 mm single sided board Test duration: up to 63.2% cumulative failure

Solder joint microcracks, package microcracks (die) after module bending/phone bending due to seating

(continued)

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Table 8.8 (continued) Type of test methods

IPC/JEDEC standard

Board level cyclic bend JESD22-B113B test [45]

Industrial test conditions

Risks/defects for cryogenic applications

Test Profile: 0.91 N force, 5 cycs Pre and post cyclic bend pass electrical test

Solder joint microcracks, package microcracks (die) after module bending/phone bending due to seating

and on track of realizing larger and higher speed of high-performance computing era whereby massive innovations are needed in enabling this quantum computing. Besides, there are challenges in fabricating superconductor electronic (SCE) chip as well. Superconductor foundries for commercial production now process 200 mm or smaller wafers using equipment lacking state-of-the-art capability. Achieving the yield and throughput for large-scale applications will require process improvements and a move to 300 mm wafers. Planarization and thickness control is challenging in stacks of multiple superconductor layers when the layer thicknesses remain the same, rather than increasing with layer number as in CMOS back-end processes.

8.11 Summary and Recommendations In summary, the demand for data center computing services is continuously rising, increasing the total energy consumption of data centers worldwide. Key critical technical challenges need to be resolved to enable the next generation of cryogenic memory computing. Some important results and recommendations are summarized as follows. • Improving the energy efficiency of the data center cooling infrastructure while guaranteeing the thermal constraints is imperative [2], and it can be obtained by combining the use of new cooling technologies and the chances by the design of advanced control systems. liquid immersion cooling (LIC) is a plausible and technologically interesting method to cool high heat flux electrical components in data centers. • Indium micro bump-based flip-chip interconnects, capable of maintaining extremely low interconnect resistance, have shown potential advantages for qubit packaging. 3D integration of the readout and control of superconducting qubits has been demonstrated through inductive and capacitive coupling to structures on a superconducting module that is bump-bonded to a qubit chip [3, 6]. • Seldom could metals and alloys maintain excellent properties in cryogenic conditions, such as ductility, owing to the restrained dislocation motion. Typically, materials transition from ductile to brittle fracture will affects its solder joint reliability at S-MCM level and SFQ flipchip micro bump solder joints.

8.11 Summary and Recommendations

203

Table 8.9 Key cryogenic memory computing initiatives by some of the key semiconductor players Industrial players

High performance computing (HPC) initiatives

Amazon

Announcement on the opening of the new home of the AWS [46] center for quantum computing, a state-of-the-art facility in Pasadena, California, where we are embarking on a journey to build a fault-tolerant quantum computer

References

D-Wave

Launched quantum annealer. It performs calculations that find low-energy states for different configurations of the hardware’s quantum devices. As such, it will only work if a computing problem can be translated into an energy-minimization problem in one of the chip’s possible configurations

[47]

Google

Embarked on HPC cloud-based data centers

[48]

Intel

Develop ‘hot’ silicon spin-qubits, much smaller computing devices that operate at higher temperatures. Second, the Horse Ridge II cryogenic quantum control chip provides tighter integration. And third, the cryo-prober enables high-volume testing that is helping to accelerate commercialization

[49]

IBM

Released quantum decade roadmap and initiatives for next 5 to 10 years

[50]

MIT

Kicked off packaging solutions in SCE chips and 3D S-MCM module packaging solutions

[51]

Micron

Evaluated DRAM module under 7 K cryogenic conditions in [52] preparation for enabling cryogenic memory market segment

Microsoft

Scaled quantum computing with topological qubits that are theorized to be inherently more stable than qubits produced with existing methods without sacrificing size or speed

Nvidia

Announced a new platform built for quantum research and [54] development across AI, high-performance computing (HPC), healthcare, finance, and other disciplines

Rambus

Researching opportunities to optimize memory and interface [55] solutions for operation at cryogenic temperatures for future generation datacenters. In a manner like “Moore’s law” memory systems have shown exponential improvements in energy efficiency, density and per-bit cost for decades

TSMC

Works with suppliers to develop immersion cooling solution [56] for HPC data center, aiming to save energy by 30% and reduce waste by 50%

[53]

• Fatigue behavior and mechanical shock on solder joint reliability of electronic products are considered especially at cryogenic temperature condition (~ − 196 °C). Fatigue crack of bulk solder is typically stressed by temperature cycling test, and main failure mode of drop shock test is IMC break at solder joint interface. Ductile fracture occurred at the solder layers at room temperature (25 °C).

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• Wire bonded memory packaging [25] (especially in cryogenic environment) which is assembled with epoxy molding compound (with embedded metal fibers), cross-linked metal fibers solder alloy (which is coated with Indium/SnPb surface finishes, and it produces higher package resistance and modulus at cryogenic temperature. These key package structures are critical to maintain its overall package warpage while producing higher interconnect reliability at operating condition of −196 to 0 °C. • The ductile to brittle transition begins at the temperature between −40 and − 60 °C and the fracture modes have both intergranular fracture and trans granular fracture for Sn solder [33]. IMC does not grow when cooling from 0 to −150 °C. • From Micron’s simulation results on DRAM package, it shows there might be possibility of high warped package (>100 µm) exceeding −150 °C under long term immersion under cryogenic temperature. Hence, efforts must be made to replace high cross-linked or metal fibers of epoxy molding compounds to further optimize the package warpage within ± 80 µm. • There are key short term and long-term challenges in enabling infrastructures for quantum computing. Most quantum computers emerging today have one common need: critical elements of the system need to be cooled to near zero degrees Kelvin temperature. • Out of those listed key semiconductor players, MIT research lab [3, 7] has established innovative ideas in terms of packaging solutions in SCE chips and 3D S-MCM module packaging solutions. Microsoft has revealed a project scaled quantum computing with topological qubits that are theorized to be inherently more stable than qubits produced with existing methods without sacrificing size or speed. Graphic processor manufacturer Nvidia kicked-off a new platform built for quantum research and development across AI, high-performance computing (HPC), healthcare, finance, and other disciplines. • Technical considerations should have given to focus on evaluate and determine suitable EMC (Epoxy Mold Compound) and solder alloys used in cryogenic memory packaging to minimize package warpage, better solder joint reliability, and address brittleness especially long-term reliability at cryogenic temperature (−196 °C). Deployment of in-situ package warpage measurements and solder ally ductile-to-brittleness transition temperatures are crucial to ensure overall package warpage. Besides, pathfinding in new EMC (with higher modulus strength) might be helpful to minimize package warpage at cryogenic conditions.

References 1. Pambudi NA, Sarifudin A, Firdaus RA, Ulfa DK, Gandidi IM, Romadhon R (2022) The immersion cooling technology: current and future development in energy saving. Alex Eng J 61:9509–9527 2. Lionello M, Rampazzo M, Beghi A, Varagnolo D, Vesterlund M (2020) Graph-based modelling and simulation of liquid immersion cooling systems. Energy 207:118238

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Index

B Biased highly accelerated temperature and humidity stress test (bHAST), 2, 16

C Chip-scale packages (CSP), 4 Coefficient of thermal expansion (CTE), 12, 13, 24, 35, 106, 162 Complimentary metal-oxide semiconductor (CMOS), 185, 189 Copper-organic solderability preservative (Cu–OSP), 97, 98

D Die attach film (DAF), 6, 9, 10 Dynamic random-access memory (DRAM), 192

E Electroless nickel immersion gold (ENIG), 95 Electromigration (EM), 26 Epoxy molding compound (EMC), 11, 13 Error-correction code (ECC), 192 Electroless nickel or palladium immersion gold (ENEPIG), 95

F Face-centered-cubic (FCC), 190, 193 Fan-out chip scale package (FOCSP), 31

Field programmable gate array (FPGA), 5, 54

G Greenhouse gas (GHG), 63

H High bandwidth memory (HBM), 12 Highly accelerated temperature and humidity stress test (HAST), 51 High temperature storage life (HTSL), 2, 51

I Information technology (IT), 185 Insulated-gate bipolar transistor (IGBT), 192 Integrated circuits (ICs), 188 Inter-metal dielectric (IMD), 51 Intermetallic compound (IMC), 2, 48, 191

K Keep-out-zone (KOZ), 12

L Liquid Helium (LHe), 195 Liquid Nitrogen (LN2), 195 Low temperatures (LT), 190 Low temperature operating life (LTOL), 201

© The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Switzerland AG 2023 C. L. Gan and C.-Y. Huang, Interconnect Reliability in Advanced Memory Device Packaging, Springer Series in Reliability Engineering, https://doi.org/10.1007/978-3-031-26708-6

209

210 Low temperature solder paste (LTS), 6, 95, 102–104 Low temperature storage life (LTSL), 201

M Micro-electromechanical system (MEMS), 4, 54 Molded underfill (MUF), 11

Index S Sn-Ag-Cu (SAC), 6 Solder joint reliability (SJR), 95 Solder resist opening (SRO), 31 Solid state drive (SSD), 24 Strain energy density (SED), 24 Superconducting multichip module (SMCM), 198 Superconductor electronic (SCE), 195 Surface mounted (SMT), 38, 102

N Non-conductive film (NCF), 9

O Organic solderability preservative (OSP), 95

P Pressure cooker test (PCT), 5 Printed circuit boards (PCB), 45

T Through silicon via (TSV), 9 Temperature cycling (TC), 49, 102, 201

U Unbiased HAST (UHAST), 26, 106, 201 Underfill materials (UF), 11, 14, 25