Impedance Source Inverters 9811527628, 9789811527623, 9789811527630

Table of contents :
Contents......Page 5
1.1.1 Energy Situation......Page 10
1.1.2 Traditional Power Inverter Topologies......Page 14
1.2 Impedance Source Inverters......Page 19
1.3.1 Classification of Impedance Source Inverters......Page 24
1.4 Contents Outline......Page 28
References......Page 29
2.1.1 Structure and Equivalent Circuit......Page 37
2.1.2 Circuit Analysis......Page 39
2.1.3 Quasi-Z-Source Inverter......Page 41
2.2.1 Simple Boost Pulse-Width Modulation......Page 43
2.2.2 Maximum Boost Pulse-Width Modulation......Page 47
2.2.3 Other Boost Pulse-Width Modulation......Page 48
2.3.1 Introduction......Page 49
2.3.2 Single-Loop Methods......Page 50
2.4.1 Structure of Current-Fed Z-Source Inverter......Page 51
2.4.2 Modes of Current-Fed Z-Source Inverter......Page 52
2.4.3 Modulation of Current-Fed Z-Source Inverter......Page 53
2.4.4 Closed-Loop Control of Current-Fed Z-Source Inverter......Page 54
2.5 Summary......Page 55
References......Page 56
3.1 Introduction......Page 58
3.2.1 Z-Source Inverter......Page 59
3.2.2.2 High-Performance Improved Z-Source Inverters......Page 60
3.2.3 Neutral Point Z-Source Inverters......Page 62
3.2.4 Reduced Leakage Current Z-Source Inverters......Page 64
3.2.6 Other Basic Z-Source Inverters......Page 65
3.3.1 Switched Components Z-Source Inverters......Page 67
3.3.2 Tapped Inductor Z-Source Inverters......Page 68
3.3.3 Cascaded Quasi-Z-Source Inverters......Page 69
3.4.1 Three-Level Z-Source Inverters......Page 70
3.5.1 High-Frequency Transformer Isolated Z-Source Topologies......Page 71
3.5.4 Low DC-Link Voltage Spikes Y-Source Topologies......Page 72
3.6 Summary......Page 73
References......Page 74
4.1 T-Source Inverter......Page 79
4.2 Trans-Quasi-Z-Source Inverter......Page 81
4.3 Improved Trans-Quasi-Z-Source Inverter......Page 82
4.5 Inductor–Capacitor–Capacitor–Transformer ZSI......Page 84
4.6 Γ-Source Inverter......Page 85
4.7 Summary......Page 86
References......Page 88
5.1 Y-Source Inverter......Page 89
5.2 Improved Y-Source Inverter......Page 91
5.3 Extended Quasi-Y-Source Inverter......Page 93
5.3.1 Startup Current Suppression......Page 94
5.3.2 Operational States......Page 95
5.3.3 Current Ratings and Core Size of Coupled Inductor......Page 98
5.3.4 Component Stresses......Page 102
5.3.5 Loss of ST Duty Ratio......Page 103
5.3.6 DC-Link Voltage Spikes......Page 106
5.3.7 Experimental Results......Page 108
5.4 Modified Y-Source Inverter......Page 112
References......Page 122
6.1 Introduction......Page 124
6.2 Dual Diodes Capacitor–Diode Absorbing Circuits......Page 125
6.2.1 Operational Modes......Page 128
6.2.2 Current Analysis......Page 130
6.2.3 Voltage Analysis......Page 132
6.2.4 Switching Loss Analysis......Page 136
6.2.5 Simulation and Experimental Results......Page 139
6.2.6 Extension of Topologies Range......Page 146
6.3 Single Diode Capacitor–Diode Clamping Circuits......Page 147
6.4 Embedded Capacitor–Diode Absorbing Circuits......Page 148
6.4.1 Operational States......Page 149
6.4.2 Current Analysis......Page 153
6.4.3 Voltage Analysis......Page 157
6.4.5 Simulation and Experimental Results......Page 159
6.5 Cascaded Quasi-Z-Network Clamping Circuits......Page 164
6.5.1 Operational Modes......Page 165
6.5.2 Current Analysis......Page 168
6.5.3 Voltage Analysis......Page 172
6.5.4 Stresses and Lifetime......Page 176
6.5.5 Extra Power Loss Analysis......Page 177
6.5.6 Simulation and Experimental Results......Page 179
6.6 Summary......Page 185
References......Page 186
7.1 Traditional Analysis of Voltage and Current Stresses......Page 187
7.2.1 Current Analysis......Page 191
7.2.2 Voltage Analysis......Page 193
7.2.3 Method Applied to Other Converters......Page 194
7.3 Transient Analysis Based on Impedance Source Inverter......Page 196
7.3.1.1 Derivation of the Coupled Inductor Model......Page 197
7.3.1.2 Derivation of the Whole Circuit Model......Page 200
7.3.2 Switching Transient Analysis......Page 203
7.3.3 Experimental Results......Page 208
References......Page 212
8.1.1.1 Basic Concept of Reliability Theory......Page 214
8.1.1.2 Index of Reliability Evaluation......Page 216
8.1.2.2 Method for Physics of Failure......Page 218
8.1.3.1 Reliability Block Diagram Method......Page 220
8.1.3.2 Monte Carlo Method......Page 224
8.2 Failure Mechanism of Power Devices......Page 225
8.2.1.2 Electrical Structure of IGBT Module......Page 226
8.2.1.3 The Package Structure of IGBT Module......Page 227
8.2.2 Failure Mechanism of IGBT Module......Page 228
8.2.2.1 Package-Related Fault......Page 229
8.2.2.2 Burning Failure......Page 231
8.2.3 Structure of Capacitor......Page 232
8.2.3.1 Classification of Capacitors......Page 233
8.2.4 Failure Mechanism of Capacitor......Page 236
8.3.1 Thermal Model of IGBT......Page 240
8.3.1.1 IGBT Power Loss Model......Page 241
8.3.1.2 IGBT Thermal Model......Page 245
8.3.2 Thermal Model of Capacitor......Page 248
8.4.1.1 Lifetime Model Based on Statistics......Page 250
8.4.1.2 Lifetime Model Based on Physical Mechanism......Page 251
8.4.2 Lifetime Models of DC-Link Capacitors......Page 252
8.5 Reliability Analysis of Life Distribution......Page 254
8.6 Summary......Page 255
References......Page 256
9.1.1 Power Decoupling Characteristics......Page 258
9.1.2 Application of Impedance Source Inverter in Power Decoupling......Page 262
9.2.1 Photovoltaic Power Characteristics......Page 268
9.2.2 MPPT Control and System Control Methods......Page 269
9.2.3.1 An Improved Y-Source Inverter PV System and Simulation Results......Page 270
9.2.3.2 A Quasi-Z-Source Single-Phase Inverter PV System and Simulation Results......Page 274
9.2.3.3 A Single-Phase Z-Source Inverter PV System and Simulation Results......Page 277
9.3.1 Introduction......Page 279
9.3.2.1 Z-Source Inverter for the Wind Power System......Page 280
9.3.2.2 Simulation Results of a ZSI-Based Wind Power System......Page 283
9.3.3 Quasi-Z-Source Inverter......Page 285
9.4.1 Introduction......Page 287
9.4.3 Z-Source Inverter-Based Permanent Magnet Synchronous Motor......Page 288
9.4.5 Modified Z-Source Inverter-Based Three-Phase Induction Motor Drive......Page 289
References......Page 291

Citation preview

Hongpeng Liu · Zichao Zhou · Yuhao Li · Wentao Wu · Jiabao Jiang · Enda Shi

Impedance Source Inverters

Impedance Source Inverters

Hongpeng Liu Zichao Zhou Yuhao Li Wentao Wu Jiabao Jiang Enda Shi •

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Impedance Source Inverters

123

Hongpeng Liu Northeast Electric Power University Jilin, China

Zichao Zhou Aalborg University Aalborg, Denmark

Yuhao Li Delta Electronic Enterprise Management (Shanghai) Co., Ltd Shanghai, China

Wentao Wu China Southern Power Grid Co., Ltd Shenzhen Power Supply Bureau Shenzhen, China

Jiabao Jiang State Grid Zhejiang Electric Power Company Hangzhou Power Supply Company Hangzhou, China

Enda Shi Harbin Institute of Technology Harbin, China

ISBN 978-981-15-2762-3 ISBN 978-981-15-2763-0 https://doi.org/10.1007/978-981-15-2763-0

(eBook)

© Springer Nature Singapore Pte Ltd. 2020 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. The publisher, the authors and the editors are safe to assume that the advice and information in this book are believed to be true and accurate at the date of publication. Neither the publisher nor the authors or the editors give a warranty, expressed or implied, with respect to the material contained herein or for any errors or omissions that may have been made. The publisher remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. This Springer imprint is published by the registered company Springer Nature Singapore Pte Ltd. The registered company address is: 152 Beach Road, #21-01/04 Gateway East, Singapore 189721, Singapore

Contents

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2 Z-Source Inverter and Control . . . . . . . . . . . . . . . . . . . . 2.1 Voltage-Fed Z-Source Inverter . . . . . . . . . . . . . . . . . 2.1.1 Structure and Equivalent Circuit . . . . . . . . . . . 2.1.2 Circuit Analysis . . . . . . . . . . . . . . . . . . . . . . . 2.1.3 Quasi-Z-Source Inverter . . . . . . . . . . . . . . . . . 2.2 Modulation Methods . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1 Simple Boost Pulse-Width Modulation . . . . . . 2.2.2 Maximum Boost Pulse-Width Modulation . . . . 2.2.3 Other Boost Pulse-Width Modulation . . . . . . . 2.3 Closed-Loop Control of Shoot-Through Duty Ratio . . 2.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3.2 Single-Loop Methods . . . . . . . . . . . . . . . . . . . 2.3.3 Dual-Loop Methods . . . . . . . . . . . . . . . . . . . . 2.3.4 Non-linear Control Methods . . . . . . . . . . . . . . 2.4 Current-Fed Z-Source Inverter and Control . . . . . . . . 2.4.1 Structure of Current-Fed Z-Source Inverter . . . 2.4.2 Modes of Current-Fed Z-Source Inverter . . . . . 2.4.3 Modulation of Current-Fed Z-Source Inverter . 2.4.4 Closed-Loop Control of Current-Fed Z-Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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1 Research Status and Development . . . . . . . . . . . . . . . . 1.1 Traditional Source Inverters . . . . . . . . . . . . . . . . . . 1.1.1 Energy Situation . . . . . . . . . . . . . . . . . . . . . 1.1.2 Traditional Power Inverter Topologies . . . . . 1.2 Impedance Source Inverters . . . . . . . . . . . . . . . . . . . 1.3 Classification and Future Trends . . . . . . . . . . . . . . . 1.3.1 Classification of Impedance Source Inverters . 1.3.2 Future Trend of Impedance Source Inverters . 1.4 Contents Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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2.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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3 Developments of Impedance Source Inverters . . . . . . . . . . . . . 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Topology Improvements with Constant Boost Ratio . . . . . . 3.2.1 Z-Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2.2 Improved Z-Source Inverters . . . . . . . . . . . . . . . . . 3.2.3 Neutral Point Z-Source Inverters . . . . . . . . . . . . . . . 3.2.4 Reduced Leakage Current Z-Source Inverters . . . . . 3.2.5 Quasi-Z-Source Inverters . . . . . . . . . . . . . . . . . . . . 3.2.6 Other Basic Z-Source Inverters . . . . . . . . . . . . . . . . 3.3 Topology Developments to Improve Boost Ratio . . . . . . . . 3.3.1 Switched Components Z-Source Inverters . . . . . . . . 3.3.2 Tapped Inductor Z-Source Inverters . . . . . . . . . . . . 3.3.3 Cascaded Quasi-Z-Source Inverters . . . . . . . . . . . . . 3.3.4 Coupled Inductor Z-Source Inverters . . . . . . . . . . . . 3.4 Multilevel and Multiplex Topologies . . . . . . . . . . . . . . . . . 3.4.1 Three-Level Z-Source Inverters . . . . . . . . . . . . . . . 3.4.2 Five-Level Z-Source Inverters . . . . . . . . . . . . . . . . 3.4.3 Cascaded Multilevel Z-Source Inverters . . . . . . . . . 3.4.4 Multiplex Z-Source Inverters . . . . . . . . . . . . . . . . . 3.5 Parameter Optimization of Topologies . . . . . . . . . . . . . . . . 3.5.1 High-Frequency Transformer Isolated Z-Source Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5.2 Inductor Z-Source Topologies . . . . . . . . . . . . . . . . 3.5.3 Extended Quasi-Y-Source Topologies . . . . . . . . . . . 3.5.4 Low DC-Link Voltage Spikes Y-Source Topologies 3.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4 Dual-Winding Impedance Source Inverters . . . . . 4.1 T-Source Inverter . . . . . . . . . . . . . . . . . . . . . . 4.2 Trans-Quasi-Z-Source Inverter . . . . . . . . . . . . . 4.3 Improved Trans-Quasi-Z-Source Inverter . . . . . 4.4 Transformer Quasi-Z-Source Inverter . . . . . . . . 4.5 Inductor–Capacitor–Capacitor–Transformer ZSI 4.6 C-Source Inverter . . . . . . . . . . . . . . . . . . . . . . 4.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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5 Three-Winding Impedance Source Inverter . . . . . . . . . . . . . . . . . . . 5.1 Y-Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Improved Y-Source Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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5.3 Extended Quasi-Y-Source Inverter . . . 5.3.1 Startup Current Suppression . . 5.3.2 Operational States . . . . . . . . . 5.3.3 Current Ratings and Core Size 5.3.4 Component Stresses . . . . . . . . 5.3.5 Loss of ST Duty Ratio . . . . . . 5.3.6 DC-Link Voltage Spikes . . . . 5.3.7 Experimental Results . . . . . . . 5.4 Modified Y-Source Inverter . . . . . . . . 5.5 Summary . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . .

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7 Impedance Source Inverters Analysis . . . . . . . . . . . . . . . . 7.1 Traditional Analysis of Voltage and Current Stresses . . 7.2 Novel Method to Analyze Voltage and Current Stresses 7.2.1 Current Analysis . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Voltage Analysis . . . . . . . . . . . . . . . . . . . . . . . 7.2.3 Method Applied to Other Converters . . . . . . . .

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6 Technology of DC-Link Voltage Spikes Suppression 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 Dual Diodes Capacitor–Diode Absorbing Circuits 6.2.1 Operational Modes . . . . . . . . . . . . . . . . . . 6.2.2 Current Analysis . . . . . . . . . . . . . . . . . . . 6.2.3 Voltage Analysis . . . . . . . . . . . . . . . . . . . 6.2.4 Switching Loss Analysis . . . . . . . . . . . . . 6.2.5 Simulation and Experimental Results . . . . 6.2.6 Extension of Topologies Range . . . . . . . . 6.3 Single Diode Capacitor–Diode Clamping Circuits . 6.4 Embedded Capacitor–Diode Absorbing Circuits . . 6.4.1 Operational States . . . . . . . . . . . . . . . . . . 6.4.2 Current Analysis . . . . . . . . . . . . . . . . . . . 6.4.3 Voltage Analysis . . . . . . . . . . . . . . . . . . . 6.4.4 Voltage and Current Stress Analysis . . . . . 6.4.5 Simulation and Experimental Results . . . . 6.5 Cascaded Quasi-Z-Network Clamping Circuits . . . 6.5.1 Operational Modes . . . . . . . . . . . . . . . . . . 6.5.2 Current Analysis . . . . . . . . . . . . . . . . . . . 6.5.3 Voltage Analysis . . . . . . . . . . . . . . . . . . . 6.5.4 Stresses and Lifetime . . . . . . . . . . . . . . . . 6.5.5 Extra Power Loss Analysis . . . . . . . . . . . . 6.5.6 Simulation and Experimental Results . . . . 6.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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Contents

7.3 Transient Analysis Based on Impedance Source 7.3.1 Derivation of the Novel Model . . . . . . . 7.3.2 Switching Transient Analysis . . . . . . . . 7.3.3 Experimental Results . . . . . . . . . . . . . . 7.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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8 Reliability Research on Impedance Source Inverters . . . . . . 8.1 Existing Reliability Analysis Methods . . . . . . . . . . . . . . . 8.1.1 Basic Concept of Reliability and Evaluation Index 8.1.2 Method for Predicting Device Reliability . . . . . . . 8.1.3 The Method for System Reliability Prediction . . . . 8.2 Failure Mechanism of Power Devices . . . . . . . . . . . . . . . 8.2.1 Structure of IGBT Module . . . . . . . . . . . . . . . . . . 8.2.2 Failure Mechanism of IGBT Module . . . . . . . . . . 8.2.3 Structure of Capacitor . . . . . . . . . . . . . . . . . . . . . 8.2.4 Failure Mechanism of Capacitor . . . . . . . . . . . . . . 8.3 Thermal Model of Power Devices . . . . . . . . . . . . . . . . . . 8.3.1 Thermal Model of IGBT . . . . . . . . . . . . . . . . . . . 8.3.2 Thermal Model of Capacitor . . . . . . . . . . . . . . . . 8.4 Life Prediction of Impedance Source Inverters . . . . . . . . . 8.4.1 Lifetime Models of IGBT Module . . . . . . . . . . . . 8.4.2 Lifetime Models of DC-Link Capacitors . . . . . . . . 8.5 Reliability Analysis of Life Distribution . . . . . . . . . . . . . . 8.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Application of Impedance Source Inverters . . . . . . . . . 9.1 Application of Power Decoupling . . . . . . . . . . . . . . 9.1.1 Power Decoupling Characteristics . . . . . . . . . 9.1.2 Application of Impedance Source Inverter in Power Decoupling . . . . . . . . . . . . . . . . . . 9.2 Application in Photovoltaic Power Generation . . . . . 9.2.1 Photovoltaic Power Characteristics . . . . . . . . 9.2.2 MPPT Control and System Control Methods . 9.2.3 Example Demonstration . . . . . . . . . . . . . . . . 9.3 Application in Wind Power Generation . . . . . . . . . . 9.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 9.3.2 Z-Source Inverter . . . . . . . . . . . . . . . . . . . . . 9.3.3 Quasi-Z-Source Inverter . . . . . . . . . . . . . . . . 9.3.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 Application on Motor Drive . . . . . . . . . . . . . . . . . . 9.4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.2 Z-Source Inverter-Based Permanent Magnet Brushless DC Motor Drive . . . . . . . . . . . . . .

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Contents

9.4.3 Z-Source Inverter-Based Permanent Magnet Synchronous Motor . . . . . . . . . . . . . . . . . . . . . . . . . 9.4.4 Z‐Source Inverter-Based Switched Reluctance Motor . 9.4.5 Modified Z-Source Inverter-Based Three-Phase Induction Motor Drive . . . . . . . . . . . . . . . . . . . . . . . 9.4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ix

. . . . 285 . . . . 286 . . . . 286 . . . . 288 . . . . 288

Chapter 1

Research Status and Development

Abstract Significant developments on highly performance, highly reliable and highly efficient power electrical inverters are underway for renewable energy and other industrial occasions. This chapter introduces the background of renewable energy and traditional source inverters which are widely applied in solar PV and wind power. Then current research status and advanced technologies related to impedance source inverters are presented, including the concepts, classification, and future trends as well as the advantages compared with traditional source inverters.

1.1 1.1.1

Traditional Source Inverters Energy Situation

Greenhouse gas emissions over the next decade have been projected in the Paris Agreement and global average temperature rise is requested well below 2 °C, which means the conventional generations should be replaced by decarbonized power networks [1–3]. Building on the impetus of trend toward decarbonization, energy industry steps in the era of distributed renewable energy resources (DRERs), such as solar photovoltaic (PV), wind generation (WG), hydropower turbines, bio-power, ocean power, concentrating solar power (CSP), and geothermal power that all demand for hybrid inverters [4, 5]. Figure 1.1 reveals the annual global renewable power capacity in the level of gigawatts (GW) from 2007 to 2017 [5]. It is obvious that the world total renewable power capacity has reached 2,195 GW in 2017, which is almost twice than that in 2007. Hydropower accounts for the largest share and is growing every year, while the composition of solar PV and wind power increases significantly annually and becomes one of the most important parts in the renewable power capacity. Other renewable powers like bio-power, ocean, CSP, and geothermal power are developing which will be further studied in the future. The solar PV global capacity and annual additions from 2007 to 2017 are shown in Fig. 1.2 [5]. The total global capacity of solar PV reaches 402 GW in 2017 which © Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_1

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1 Research Status and Development

Fig. 1.1 Annual global renewable power capacity from 2007 to 2017 [5] (Source Reproduced with the permission of REN21)

has increased 98 GW than the last year. Besides, the annual additions of solar PV are almost keeping growing in the past decades, while that of wind power are nearly constant as shown in Fig. 1.3 which illustrates the wind power global capacity and annual additions from 2007 to 2017 [5]. However, both energies contribute more and more capacity to that of total global renewable power. In 2017, the world total capacity of wind power generation has reached 539 GW, which almost constitutes one-quarter of the global renewable power capacity. In order to realize the 100% renewable energy as [2] mentioned, the solar PV and wind power will be still regarded as key development objects in the years ahead. However, the renewable energy still have various issues. As for the solar PV, the output power is restricted to load variations, temperature, and irradiance [6, 7]. The load is variable whether the solar PV system is connected to the grid or off the grid.

Fig. 1.2 Solar PV global capacity and annual additions from 2007 to 2017 [5] (Source Reproduced with permission of REN21)

1.1 Traditional Source Inverters

3

Fig. 1.3 Wind power global capacity and annual additions from 2007 to 2017 [5] (Source Reproduced with permission of REN21)

Thus, the maximum power point tracking (MPPT) technique is applied and the solar PV could output maximum power in a single point of operation when the corresponding insolation is given [8]. Besides, as the temperature and irradiance are influenced by weather, nighttime, shadow on the PV panels, and so on, the output power maybe decreased and even down to zero. Battery storage is integrated into the PV system to avoid the discontinuous electric supply to the load [9, 10]. Moreover, direct current to direct current (DC–DC) converters are requested when the power level of output mismatches with that of PV panels. And the existing loads are almost alternating current (AC), inverters that perform direct current to alternating current (DC–AC) transition are always regarded as the final link to the loads or grid [11, 12]. Figure 1.4 illustrates various configurations of PV systems, where the inverters’ outputs are given to the AC loads or grid [13]. Figure 1.4a shows one PV panel connected with inverter, while a DC–DC converter added to it becomes Fig. 1.4b, which enhances the output power level. Furthermore, several PV panels connected with inverters can be combined into module-based inverters that also improve the power rating [12]. Figure 1.4c, d, e displays the structure of string inverters, where every string contains two or more PV panels. Centralized inverters are shown in Fig. 1.4f, whose each string provides high voltage so that no further amplification is needed. However, the centralized inverters would cause power loss and poor power quality due to the centralized MPPT. Besides, the configurations that contain one-stage converter make the inverter sustain all tasks like MPPT and current control, which may cut its lifespan [13]. Therefore, the structures of Fig. 1.4b, d, e which have two-stage converters are widely utilized. Similarly with solar PV, wind power is almost up to weather and geographic location [14]. Wind speed and wind direction are checkered over time, which leads to wind power fitful, random, and uncontrollable. In order to address these problems, some inverter interfaces that can improve safety and quality when wind power

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(d) (a)

(b)

(c)

DC-DC DC-AC

DC-AC

(f)

(e)

DC-DC DC-AC

DC-AC

DC-DC

DC-DC

DC-AC

DC-AC

Fig. 1.4 Various configurations of PV systems [13] (Source Reproduced with permission of IEEE)

synchronizes and closes have been proposed [15]. The variable speed systems are widely used among the current inverter interfaces because maximum wind power can be extracted by the various speed operations [16]. Among them, the doubly fed induction generator (DFIG) system and permanent magnet synchronous generator (PMSG) system are two typical various speed systems [17], which are mainly composed of wind turbine (WT), generator, and power electronic converters. The abridged general view of DFIG wind power system is shown in Fig. 1.5, of which the gearbox is designed to adjust speed. It is obvious that the stator of DFIG connects to the grid directly while the rotor link with grid through power electronic converters, which makes the power electronic converter work in partial scale. Therefore, the capacity of power converters can be reduced and expected effect can be reached at a fraction of the cost. Besides, the parallel power converter can achieve separate active and reactive power regulation [15]. It is worth mentioning that the power converter in Fig. 1.5 is designed as back-to-back (BTB) converter, which is widely used in traditional DFIG wind power system. The rotor side

DFIG grid gearbox WT

AC-DC

DC-AC

Fig. 1.5 Abridged general view of DFIG wind power system

1.1 Traditional Source Inverters

5

grid gearbox

PMSG

AC-DC

DC-AC

WT Fig. 1.6 Abridged general view of PMSG wind power system

converter undertakes the functions that adjusting electromagnetic torque and providing part of reactive power to insure the magnetization of motor, whereas the grid side converter regulates the direct current (DC) link voltage. However, sharp fluctuations in output power of this system are easily caused by unbalanced voltage when the stator of DFIG directly connects to the grid [18]. Thus, [15] proposed a series way on the basis of traditional parallel, which controls the DC-link voltage by increasing an inverter at the link between output of AC-DC and grid. Nevertheless, the full-scale power converter is easier to satisfy the requirement of grid connection and more flexible to adjust reactive power [19]. Thus, the PMSG system that contains full-scale power converter becomes more and more attractive. Figure 1.6 displays the abridged general view of PMSG wind power system, where the gearbox is optional and PMSG is connected with grid through a BTB converter that can be changed as other power electronic converters according to the rating of PMSG WTs [20]. Diagrammatic drawing in Fig. 1.6 is adopted when the rating of WTs is below 0.75 megawatts (MW). Otherwise, when the rating is above 0.75 MW, the high power capacitor is required to be handled. To address this issue, the BTB converters connected in parallel, employing multiphase PMSGs, adopting distributed power converters are put into practice. Besides, BTB neutral-point-clamped (NPC) power converter that can reduce switch loss and output ripples is applied in above 3 MW rating [20]. Moreover a BTB converter with intermediate boost converter has been proposed in [21, 22] to increase the DC-link voltage at a suitable power rating. Therefore, power converters especially power inverters are vital parts whatever in the solar PV or wind power systems.

1.1.2

Traditional Power Inverter Topologies

Traditional power inverters can be classified as voltage source inverters (VSIs) and current source inverters (CSIs), whose basic topologies are illustrated in Fig. 1.7. The basic topology of VSIs shown in Fig. 1.7a is three-phase two-level voltage source inverter that consists of DC source, input capacitor, three phase legs, output filter, and three-phase load. Each leg contains two power transistors with

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1 Research Status and Development

S6

Lin

(b)

S1 Idc

vc S2

S4

Load or grid

vb

Load or grid

va

C1

Filter

Vdc

S5

S3

S1

Filter

(a)

C1

D1 va S6 D6

S3 D3 vb S4 D4

S5 D5 vc S2 D2

Fig. 1.7 Basic topologies of traditional power inverter

antiparallel diode in series [23]. The inverter is capable of output variable frequency variable amplitude sinusoidal waveform and the size of input and output filters can be reduced when the power transistors are operating at high frequency. Thus, the three-phase two-level voltage source inverter has been applied in AC motor driver [24], active power filters [25], PV systems [26], and wind power systems [27]. However, high current ripple always exists in applications of VSIs, which requires larger capacitors [28]. Besides, shoot-through between two power transistors of the same leg is forbidden [29]. In order to address these issues, a basic topology of CSIs shown in Fig. 1.7b is proposed [30], which has higher reliability and inherent over current protection. Besides, multilevel techniques are introduced into CSIs to decrease the output current’s harmonic content and total harmonic distortion (THD) [31]. Although CSIs have more benefits than VSIs, the latter are more widely wielded because the voltage control is easier to implement. Similarly with CSIs, multilevel voltage source inverters turn up to reduce the harmonic content and THD of output current because the staircase output voltage waveform is nearly sinusoidal [32, 33]. Besides, compared with two-level voltage source inverters, multilevel voltage source inverters have lower switching stresses, lower switching frequency, reduced switching losses, lower dv/dt, and EMI. Moreover, multilevel voltage source inverters can produce high voltage levels and be used for high voltage applications. Cascaded H-bridge (CHB) topology [34], neutral-point-clamped (NPC) topology [35], and flying capacitor (FC) topology [36] are three earlier proposed multilevel voltage source inverters.

V1

V2

S31

va

C1

S33

S51

vb

S53

Filter

S13

S11

7

vc

S12

S14

S32

S34

S52

S54

S41

S43

S61

S63

S21

S23

S42

S44

S62

S64

S22

S24

Load or grid

1.1 Traditional Source Inverters

C2

Fig. 1.8 Five-level cascaded H-bridge inverter

The NPC topology and FC topology both develop gradually from three-level inverters while CHB topology starts from five-level inverters [37]. Figure 1.8 displays five-level CHB inverter where every bridge is able to provide three levels of voltages. The number of voltage level can be defined as 2m + 1, where m represents the number of bridge. One biggest advantage of this topology is that there are no additional capacitors and diodes. Thus, the CHB inverter can generate the same voltage levels by fewer components. Besides, as every bridge of CHB topology requires one separate DC source, the CHB topology is modularized effortlessly. However, the number of separate DC source grows in proportion with the increase of voltage levels and every source needs real power conversion. The structure of three-level NPC inverter is illustrated in Fig. 1.9, which adds six diodes, six power transistors modules, and one capacitor on the basis of two-level

C1

S51

S31 D3

D1 S12

D5 S52

S32 va

Vdc

vb C2

D4

S41

S42

D2

S21

S22

Fig. 1.9 Three-level neutral-point-clamped inverter

D6

vc S61

S62

Load or grid

S11

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Fig. 1.10 One phase leg of five-level neutral-point-clamped inverter

S11 C1

D1

S12

D2

C2

S13 D3

Vdc

S14 va

D4

S61

C3 D5

C4

S62 D6

S63

S64

voltage source inverter. The power transistor is not under full voltage of DC source as the capacitors split source into two parts. Thus, the power rating of device can be reduced. Besides, the NPC inverter has high efficiency and need not any filters to reduce harmonics. And it is worth mentioning that reactive power flow can be controlled [37]. However, the topology of NPC is difficult to be modularized and more number of diodes is needed for higher levels. As shown in Fig. 1.10, one phase leg of five-level NPC inverter has four diodes and four power transistors more than that of three-level NPC inverter [38]. Moreover, five-level NPC inverter requires four capacitors to divide DC source, from which the expression between the number of voltage levels and capacitors can be derived as s + 1, where s represents the number of capacitors. Figure 1.11 shows the topology of three-level FC inverter, which replaces the diodes of three-level NPC inverter by several capacitors. Similarly with NPC inverter, there are no filters implemented to reduce harmonics. And when power outage appears, the FC inverter can provide extra ride through capability. Besides, both real and reactive power flows are controllable [37]. However, as the capacitors are introduced into the topology, the switching frequency and power losses will be high for real power transmission [39]. Moreover, the number of components is also

C1

9

S11

S31

S51

S12

S32

S52

C3

va

Vdc

vb

C4 C2

C5

vc

S41

S21

S61

S42

S22

S62

Load or grid

1.1 Traditional Source Inverters

Fig. 1.11 Three-level flying capacitors inverter

increasing with the voltage level growth, which leads to low efficiency and expensive cost. With the development of multilevel inverters, several novel topologies have been proposed [40]. For example, P2 [41] and active NPC (ANPC) [42] topologies are two improved multilevel inverters. Figure 1.12a displays one phase leg of P2 topology which integrates NPC topology and FC topology. That makes the improved inverter inherit advantages of both topologies and can balance the dc-link voltage without any extra assistant circuits. Besides, the P2 topology is widely applied in PV generation when the capacitors are all replaced by PV panels. Similarly, Fig. 1.12b shows one phase leg of ANPC that possesses the robustness of NPC topology and flexibility of FC topology. Beyond those topologies, there are many other hybrid multilevel inverters, such as one improved cascade inverter as shown in Fig. 1.13. The H-bridge of original cascade inverter is replaced by blocking diodes scheme, while the H-bridge can also be substituted by flying capacitors scheme [43]. These inverters could generate more voltage levels by less DC source which means fewer modules needed. Besides, soft-switched technology has been introduced into multilevel inverters to reduce switching loss. The insertion of soft-switched assistant circuits makes the switch work in zero voltage or zero current stage, which results in less energy loss. Moreover, more and more novel topologies are proposed to improve performance and adapt in various occasions. In order to analyze the novel topologies proposed and further research more advanced topologies, several sub-modules are reviewed and summarized from original topologies [40]. Every sub-module has its own switching characters and different voltages could be output. Therefore, novel topologies can be proposed through connecting the sub-modules in series, in parallel, or in other way.

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Fig. 1.12 Two improved multilevel inverters: a P2 topology, b ANPC topology

(a)

S1

C1

S2

S5

va

C3

Vdc C2

S6

S3

S4

(b) S1

C1 S2

S5

S7 C3

Vdc S3

C2

S6

va S8

S4

1.2

Impedance Source Inverters

Traditional VSIs and CSIs can only work in buck (step-down) mode or boost (step-up) mode, respectively, because of the inherited features. Besides, the dead times for VSIs and overlap delays for CSIs have to be inserted with the compromise of slight output waveform distortions. Moreover, the growth of renewable energy requires wider voltage gain range which is difficult for traditional inverters. Although two-stage traditional inverters that inserting a DC–DC converter between the renewable sources and inverter bridge are proposed to adjust voltage gain range, the complexity and size of system, in turn, increase [44–46]. To address these

1.2 Impedance Source Inverters

11

Fig. 1.13 Improved cascade inverter that embraces NPC topology

S11

C1

D1

S12

S31 D3

S32

va

V1 C2

C1

D4

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S21 S22

problems, various single-stage impedance source inverters that can both buck and boost voltages without demanding for dead times or overlap delays have been proposed [47]. Thus, the impedance source inverters have been introduced into PV power generation [48–54], wind power generation [55–62], electric vehicles [63– 67], and so on. The earliest topology among impedance source inverters is Z-source inverter (ZSI), which can buck or boost its dc-link voltage by changing the shoot-through (ST) time of the same phase leg [68]. Therefore, the ZSI is less affected by inadvertent short circuit and waveform distortions caused by dead times and overlap delays. Figure 1.14 shows the topology of one-phase ZSI, which contains DC source, impedance network, H-bridge, output filter, and AC load. The impedance network is a two-port network that consists of two inductors (L1 and L2) and two capacitors (C1 and C2) connected in X shape, which makes the ZSI have inherited features of impedance source inverters. By simply embedding the impedance

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1 Research Status and Development

L1

D1

S1 Vin

C1

S3 Lf

C2

AC Load

Cf

vdc S2

S4

L2 Fig. 1.14 Topology of Z-source inverter

network between the input source and inverter bridge of traditional three-phase source inverter, three-phase impedance source inverter is produced. Besides, it is worth mentioning that the impedance network can be transplanted to AC–DC, AC– AC, and DC–DC power conversion so that similar function could be realized. Therefore, the impedance network is the most vital part of impedance source inverters and even impedance source converters. In order to briefly analyze the structure of ZSI, the H-bridge, output filter, and AC load are simplified as a switch SW and a current source Io in parallel shown in Fig. 1.15. The ZSI can be divided into ST state and non-shoot-through (NST) state according to whether the power transistors of same phase leg are conducting simultaneously. When the inverter steps into ST state, the equivalent switch SW turns on thus the current source Io is short-circuited and inactive. The SW turns off when ZSI turns to the NST state, and Io is active at this time which represents AC load is connected with source and works steadily. Figure 1.16a illustrates the ST operating state of ZSI, while NST state of that is shown in Fig. 1.16b. The switch state of diode D1 is contrary to SW and then voltage and current stresses of ZSI could be derived. However, the ZSI still has some drawbacks that affect performance of inverter. Thus, several improvements are gradually introduced to ZSI. For example, the bidirectional ZSI (BZSI) was proposed to exchange energy between AC and DC in both directions [69]. The high-performance improved ZSI (HP-IZSI) proposed in

L1

D1

Vin

C1

C2

L2 Fig. 1.15 Equivalent circuit of Z-source inverter

SW

vdc

Io

1.2 Impedance Source Inverters

13

L1

(a) Vin

C1

C2

SW

vdc

Io

L2

L1

(b) Vin

C1

C2

SW

vdc

Io

L2 Fig. 1.16 Operating states of Z-source inverter: a ST state, b NST state

[70] can limit its inrush current at startup and reduce stresses across its capacitors. And the quasi-ZSI (QZSI) has been proposed in [71] to obtain a continuous input current. Besides, in order to realize a higher boost with the same ST duty ratio, switched inductor and switched capacitor ZSI emerged [72, 73]. However, the higher voltage is required, the more diodes, inductors, or capacitors are needed. The extra components increase complexity and cost, and hence lead to the switched component ZSI unprepossessing. Similarly, extended boost ZSI which boosts wider range voltage through combination of some impedance networks [74]. This increases the number of components, which may also lower efficiency of inverter. To reduce components without compromising gain, coupled inductor impedance source inverters (CISIs) have been proposed in [75–81], such as T-source inverter (TSI), gamma-Z-source inverter (ГSI), Y-source inverter (YSI), and so on. Each CISI embedded coupled inductor boosts the output voltage by altering the turns ratio of the coupled inductors. Besides, CISIs can achieve a higher boost even in a small ST duty ratio compared with other impedance source inverters. However, the introduction of coupled inductor renders the appearance of leakage inductance whatever cores or winding techniques are employed, which induces operating problems. For instance, when the CISI transfers from ST to NST state, a great voltage spike will occur at the dc-link due to a sharp change in current through the leakage inductors. Thus, higher rated switches are required to avoid damages which will push up the production cost. Moreover, part of ST duty ratio will be lost when transferring from NST to ST state. Thus, some energy is wasteful, in turn, the

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1 Research Status and Development

efficiency of inverters deceases. Obviously, these issues limit practical application of CISIs, unless the DC-link voltage spikes could be avoided and the lost energy on the leakage inductors can be recycled. One of the methods that is reducing DC-link voltage spikes is changing the structure of coupled inductors. The method brought up in [82] decreases the leakage inductance as well as series resistance on each winding of three-winding CISI by applying a Δconnection rather than Y-connection. But the third winding depends on the other two windings using the Δ-connection structure. Thus, the voltage regulating degree of freedom of coupled inductors decreases which results in the three-winding coupled inductors to perform quite similarly with dual-winding coupled inductors. Besides, this method cannot reduce the DC-link voltage spikes totally causing the leakage inductors still exist in the circuit. Another method is adding an extra absorbing circuit, which can either be of the active or passive type, even if the common purpose of both types is providing a way to absorb the lost energy caused by the leakage inductors. For instance, an active DC–DC buck converter has been applied to the inverter for recycling leakage energy to the capacitors or source [83]. However, the introduction of buck converter also increases one power transistor, which in turn leads to the higher control complexity and cost. Therefore, the passive type without any extra power transistors is more appealing. One of the passive absorbing circuits also proposed in [83] relies on capacitors and diodes for clamping the DC-link voltage, as shown in Fig. 1.17a. The absorbing circuit is drawn in red, while Lcouple represents the coupled inductors which can be dual winding or three winding. However, a huge current will flow through the input voltage Vin, diode DS2, capacitor CS1, and shorted phase leg in the ST state, since there are no series-wound sizable limiting inductance. Then the current is instantaneously large and in turn may damage power transistors or other semiconductor devices unintentionally. To limit this large current, an improved absorbing circuit is proposed in [84] where a series inductance is introduced into the ST loop. The diode DS1 conducts only during the transition of ST to NST state, which can clamp the dc-link voltage in series with CS1 and C1 as shown in Fig. 1.17b. Figure 1.17c illustrates a simplified absorbing circuit which can realize the function similarly with circuit 2 shown in Fig. 1.17b [85]. The spiky DC-link voltage can be clamped during the transfer from ST to NST state by DS in series with capacitors C1 and C2. However, the usable range of both circuit 2 and circuit 3 shown in Fig. 1.17c is limited. They are only suitable for several specific CISIs. [86] introduces a novel passive absorbing circuit which clamps the dc-link voltage by diode DS and capacitors (CS and C2) in series. This absorbing circuit can be generalized to all CISIs and has various configurations when it is applied to one specific topology, one of which has been displayed in Fig. 1.17d. Besides, neoteric passive absorbing circuits embedding other enhanced functions are gradually proposed. One clamping circuit that can also increase voltage gain is proposed in [87]. As shown in Fig. 1.17e, it almost could be regarded as the CISI cascaded with QZSI, thus the voltage gain is further enhanced. Detailed introduction and other more novel absorbing circuits will be presented in Chap. 6.

1.2 Impedance Source Inverters

15

(a) D Lcouple Vin

Lin

CS1 DS1 vdc

DS2

C

CS1

Lcouple C1

DS1

DS2

vdc

C2

(d)

C2

Vin

D

Vin

CS2

(c) Lin

C2

(b)

Lin

D

DS Vin

Lcouple

CS

vdc

DS C1

C2

(e)

D1 C1

vdc

CS2

Lin DS

D1 Vin

C1

LS CS1

vdc

Fig. 1.17 Illustration of passive absorbing a circuit 1 [83], b circuit 2 [84], c circuit 3 [85], d circuit 4 [86], e circuit 5 [87]

Therefore, more and more improvements of impedance source inverters without the compromise of inherited excellent features are turning up. In order to rightly analyze and design the impedance source inverters, it requires more uniformly valid steady and transient analysis methods. Besides, the reliability research on impedance source inverters is noteworthy to work steadfastly. Moreover, impedance source inverters have not only been applied in photovoltaic power generation and wind power generation, but also introduced to application of power decoupling, motor drive, and so on. All of these will be introduced in detail in the latter chapters.

1.3 1.3.1

Classification and Future Trends Classification of Impedance Source Inverters

The impedance source inverters have become very attractive since their appearance. Navigating through the history of impedance source inverters, there are several control techniques proposed to improve the performance of impedance source

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1 Research Status and Development

inverters. Simple boost PWM (SBPWM) is the earliest control technique proposed in [88], which is also the simplest. However, the voltage stresses of switches are high. Thus, maximum boost PWM (MBPWM) is introduced to limit the high voltage stresses of switches [88]. But low-frequency high-magnitude ripples related to the dc-link voltage fundamental frequency result in the size of impedance network to increase. In order to address both issues produced by SBPWM and MBPWM, constant boost PWM (CBPWM) is born, which can decrease the ripples with relatively low voltage stresses [89]. Besides, modified space vector PWM (MSVPWM) is applied to the impedance source inverters with the extensional principle of space vector PWM [90, 91]. The operational range of linear relations is wider under the control of MSVPWM. Moreover, [92] proposes a novel control technology that named discontinuous PWM (DCPWM), which separates the boosting factor and modulation index so that the impedance source inverter could operate in a relative high stable status. However, the improvement of control technology still has small effect on the performance of impedance source inverters. The structure advancement of impedance source inverters impacts the their capability greatly. There are multiple generations of impedance source inverters with the development of technology, as shown in Fig. 1.18. Since the impedance source inverters are improved from traditional voltage source and current source inverters by inserting an impedance network, they can be classified into voltage-fed and current-fed impedance source inverters. Besides, the vital inserted impedance network allows the inverters to operate in ST state and adjust output voltage freely; therefore, almost all improvements are about the impedance network. As is shown in Fig. 1.18, the impedance network topologies could be divided into four categories, i.e., constant boost ratio topologies, improved boost ratio topologies, multilevel and multiplex topologies, and parameter optimization topologies. The impedance source inverters which contain constant boost ratio topologies have the common feature that the boost factors are all the same as that of basic ZSI. And the constant boost ratio topologies can be further subdivided into six sorts. The first sort is Z-source topologies, which mainly contains basic ZSI [68]. And the second sort of constant boost ratio topologies is improved Z-source topologies, which is based on the ZSI, such as BZSI [69], high-performance ZSI (HP-ZSI) proposed in [93], improved ZSI (IZSI) proposed in [94], and so on. Among them, HP-IZSI is produced by combining the IZSI and HP-ZSI [70]. Besides, series Z-source inverter (SZSI) and quasi-resonant soft-switching ZSI (QRSSZSI) are modified from IZSI [95, 96]. While the third sort that neutral point Z-source topologies mainly includes four-wire ZSI (FWZSI) [97], four-leg ZSI (FLZSI) [98], dual ZSI (DuZSI) [99], and neutral point ZSI (NPZSI) [100]. The fourth sort of constant boost ratio topologies is reduced leakage current Z-source topologies, which is divided into ZSI with diode (ZSI-D) and ZSI with switch (ZSI-S) [101, 102]. In order to make the input power source and the dc-link share common ground, the fifth sort quasi-Z-source topologies are proposed [71]. Moreover, there are other basic Z-source topologies that distributed ZSI (DiZSI)

1.3 Classification and Future Trends

17 Z-source topologies

Improved Z-source topologies

Constant boost ratio topologies

Neutral point Zsource topologies

Reduced leakage current Z-source topologies Quasi-Z-source topologies Other basic Z-source topologies

Switched components Z-source topologies

Voltage fed

Improved boost ratio topologies

Tapped inductor Zsource topologies Cascaded quasi-Zsource topologies

Coupled inductors Z-source topologies Impedance network topologies

Three-level Zsource topologies Current fed

Multilevel and multiplex topologies

Five-level Z-source topologies Cascaded multilevel Z-source topologies multiplex Z-source topologies

High-frequency transformer isolated Z-source topologies

Inductor Z-source topologies Parameter optimization topologies

Extend quasi-Ysource topologies Low dc-link voltage spikes Y-source topologies Other optimized topologies

Fig. 1.18 Classification of impedance source inverters

[103], embedded ZSI (EZSI) [104], and bidirectional QZSI (BQZSI) [65], which belongs to the sixth sort. All the impedance source inverters consisting of constant boost ratio topologies will be presented in Sect. 1.2 of Chap. 3.

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As for the improved boost ratio topologies, which are opposite to the constant boost ratio topologies, the boost factor of these type impedance source inverters is enhanced. Generally, they can be divided into four sorts, i.e., switched components Z-source topologies, tapped inductor Z-source topologies, cascaded quasi-Z-source topologies, and CISIs, where the switched components could further be subdivided into switched inductor and switched capacitor Z-source topologies [72, 73]. The switched inductor or switched capacitor is a cell composed of inductor or capacitor with diodes. Then the switched inductor Z-source topologies are produced when the inductors of constant boost ratio topologies are displaced by switched inductor cells, while the switched capacitor Z-source topologies are similarly replaced by switched capacitor cells [105–112]. Similarly with switched inductor Z-source topologies, tapped inductor Z-source topologies replace the inductors by tapped inductor cells, which consist of tapped inductors and diodes [113, 114]. As the quasi-Z-source topology processes the capability of extending boost factor without extra active switches, the quasi-Z-source topology could be an extended passive boost cell, so that the cascaded quasi-Z-source topologies are proposed [115–117]. Besides, the cascaded quasi-Z-source topologies are subdivided into capacitor-assisted (CA) and diode-assisted (DA) topologies whether the connecting component of quasi-Z-source cell is capacitor or diode. These three improved boost ratio topologies mentioned will be introduced in Sect. 1.3 of Chap. 3. Moreover, the latest improved boost ratio topologies, namely, CISIs are widely employed because the coupled inductors reduce the quantity of passive components needed in the impedance network [118]. Therefore, the power density of CISIs can be improved and the cost is reduced accordingly. There are various topologies belonging to CISIs, such as TSI [83], trans-quasi-Z-source inverters (trans-QZSI) [75], improved trans-QZSI [84], transformer ZSI (TZSI) [79], inductor-capacitor-capacitortransformer ZSI (LCCT-ZSI) [77], ГSI [78], YSI [80], improved YSI (IYSI) [81], and so on. All of these topologies will be recommended in Chaps. 4 and 5. The multilevel technology can also be applied to impedance source inverters like traditional inverters, thus the multilevel and multiplex topologies emerge at the right time. Similarly, the multilevel topologies contain three-level and five-level even more level topologies [119–123]. Besides, the multilevel ZSI could be cascaded to get higher voltage gain and system reliability [124, 125]. Moreover, dual-input or dual-output ZSIs have been proposed for specific application [126, 127]. The detailed introduction of multilevel and multiplex topologies will be presented in Sect. 1.4 of Chap. 3. In order to make the impedance source inverters fit different occasions, plentiful improved researches have been underway. For example, high-frequency transformer isolated ZSI (HFTI-ZSI) proposed in [128] can achieve electrical isolation and reduced device stresses. Besides, the inductor Z-source inverter (L-ZSI) which avoids the disadvantages caused by capacitors is proposed in [129]. As mentioned in last section, great DC-link voltage spikes and ST duty loss of CISIs always exists which might damage devices. Therefore, extended quasi-Y-source inverter (particular introduction in Chap. 5) [130] and various low DC-link voltage spikes

1.3 Classification and Future Trends

19

Y-source inverters (detailed presentation in Chap. 6) emerge. Without doubt, more and more optimized impedance source inverters are being studied to achieve higher performance and are generalized to more applications.

1.3.2

Future Trend of Impedance Source Inverters

Obviously, the mentioned improvements of impedance source inverters are almost about impedance network and little amelioration is concentrated on the following inverter bridge. Although the impedance source inverters which contain multilevel and multiplex topologies are improved by changing the inverter bridge’s structure, they could be further developed in the following stages. For example, the inverter bridge of multilevel impedance source inverter can be not only the diode NPC structure, but also FC structure, cascade H-Bridge, P2 structure, ANPC structure, or even more novel hybrid multilevel structure. Moreover, with the development of wide bandgap semiconductors, power electronics field is vibrant. The bandgap semiconductors provide more interesting features than traditional silicon (Si) semiconductors, such as reduced energy loss of switching, high blocking voltage, and less influence by temperature [131]. Therefore, higher power density and efficiency of power electronic systems can be realized. On the basic of wide band gap semiconductors, impedance source inverters can also develop towards higher efficiency and higher power density. Besides, the reliability of power electrical systems is also important because it relates to the life of systems. However, current reliability analysis focuses on the components other than the whole impedance source inverters or even the PV systems that contain the impedance source inverters. Therefore, the reliability analysis of PV systems or wind power systems composed of impedance source inverters and other power electricity will be one direction of development. Moreover, the power rate of impedance source inverters will be further improved with the development of PV generation and wind power generation. The above mentioned are about the hardware improvements of impedance source inverters; however, the control of impedance source inverters is also one future direction. The traditional control technologies of impedance source inverters can be perfect and proposing one novel control method. And the control technologies could also be combined with technologies implemented on original applications, such as the combination with MPPT of PV generation.

1.4

Contents Outline

Obviously, concepts, advantages, classification, and future trend of impedance source inverters have been summarized in this chapter. Then Chap. 2 introduces and analyzes in detail the original Z-source inverter including its operation

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mechanism, modulation, and closed-loop control. The developments of impedance source inverters are presented in Chap. 3 later, where improvements such as boost ability enhancement and parameter optimization are presented based on which many popular and practical derived topologies from original Z-source inverter are introduced systematically. After that, dual-winding impedance source inverters and three-winding impedance source inverters are introduced in detail in Chap. 4 and Chap. 5, respectively. The suppression methods of DC-link voltage spikes and duty loss which would be a problem for most researchers are summarized and implemented in Chap. 6. Common current and voltage analysis method that is given along with the introduction of a new efficient way of calculation stresses is introduced in Chap. 7. After this, failure mechanism and lifetime prediction of impedance source inverters are discussed to guarantee their reliability, which is mentioned in Chap. 8. For conclusion, the impedance source inverter power decoupling method and applications in different occasions are given in examples for practical purposes. In general, in this book, the suppression methods of DC-link voltage spikes and duty loss which would be a problem for most researchers are summarized and implemented. Novel, efficient steady-state and transient analysis methods of significant practical value which are proposed originally will be covered by specific calculation examples. Other than that, the reliability of impedance source inverters is first introduced which adopts methodology from reliability engineering to study the reliability in components and system of impedance source inverters. Many examples are given for the application of impedance source inverters which help engineers to directly use them in practice. Moreover, the book is organized in a clear and coherent way which summarizes all the existing topologies of impedance source inverter more thoroughly than any published books up to date. The book will give the readers an in-depth knowledge on the advantages and disadvantages of these impedance source inverters through comparative discussions, tables, and figures. Examples given in the book will have full explanation along with detailed calculation to help understanding. Confirmatory simulations and experiments will be given in the book to strengthen the persuasiveness.

References 1. C.G. y Garcia, B.A.B. Olvera, The importance of increasing actual INDCs’ ambitions to meet the paris agreement temperature targets: an innovative fuzzy logic approach to temperature control and climate assessment using FACTS, in 2016 6th International Conference on Simulation and Modeling Methodologies, Technologies and Applications (SIMULTECH), Lisbon (2016), pp. 1–5 2. REN21, 2017, Renewables Global Futures Report: great debates towards 100% renewable energy, Paris, REN21 Secretariat (2017) 3. M.P. Evans, S.H. Tindemans, D. Angeli, A graphical measure of aggregate flexibility for energy-constrained distributed resources, in IEEE Transactions on Smart Grid

References

21

4. H.R. Baghaee, M. Mirsalim, G.B. Gharehpetian, H.A. Talebi, A decentralized power management and sliding mode control strategy for hybrid AC/DC microgrids including renewable energy resources, in IEEE Transactions on Industrial Informatics 5. REN21, 2018, Renewables 2018: Global Status Report, Paris, REN21 Secretariat (2018) 6. F.E. Tahiri, K. Chikh, M. Khafallah, A. Saad, D. Breuil, Modeling and performance analysis of a solar PV power system under irradiation and load variations, in 2017 14th International Multi-conference on Systems, Signals & Devices (SSD), Marrakech (2017), pp. 234–238 7. E. Amina, K.M. Shafeeque, Single stage transformer less reconfigurable inverter for PV applications, in 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore (2018), pp. 388–392 8. D. Jain, U.K. Kalla, Anti-hebbian control algorithm for three-phase inverter in grid connected solar PV system, 2016 IEEE 7th Power India International Conference (PIICON), Bikaner (2016), pp. 1–5 9. A.K. Gupta, V. Pawar, M.S. Joshi, V. Agarwal, D. Chandran, A solar PV retrofit solution for residential battery inverters, 2017 IEEE 44th Photovoltaic Specialist Conference (PVSC), Washington, DC (2017), pp. 2986–2990 10. P. Dinesh, B. Kowshick, P.P. Raghav, R.K. Govindarajan, G.S. Ilango, Solar power based intelligent battery charging system compatible with existing home inverters, 2013 Texas Instruments India Educators’ Conference, Bangalore (2013), pp. 157–164 11. R.J. Bravo, S.A. Robles, E. Muljadi, Assessing solar PV inverters’ anti-islanding protection, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, CO (2014), pp. 2668–2671 12. A.K. Gupta, M.S. Joshi, V. Agarwal, On the control and design issues of single phase transformerless inverters for photovoltaic applications, 2014 IEEE 6th India International Conference on Power Electronics (IICPE), Kurukshetra (2014), pp. 1–6 13. S.B. Kjaer, J.K. Pedersen, F. Blaabjerg, A review of single-phase grid-connected inverters for photovoltaic modules, in IEEE Transactions on Industry Applications, vol. 41, no. 5, Sept–Oct 2005, pp. 1292–1306 14. M. Vimala, C. Chellamuthu, Harmonic analysis of multilevel inverter driven by variable speed wind electric generator, in 2013 International Conference on Green Computing, Communication and Conservation of Energy (ICGCE), Chennai (2013), pp. 409–414 15. S. Su, Y. Su, G. Liu, Design of main circuit and control system for connecting series and parallel interface of wind power generating unit, in 2015 5th International Conference on Electric Utility Deregulation and Restructuring and Power Technologies (DRPT), Changsha (2015), pp. 2780–2784 16. A.A. Mohamed, A.L. Haridy, A.M. Hemeida, The whale optimization algorithm based controller for PMSG wind energy generation system, in 2019 International Conference on Innovative Trends in Computer Engineering (ITCE), Aswan, Egypt (2019), pp. 438–443 17. G. Chen, X. Cai, Reconfigurable control for fault-tolerant of parallel converters in PMSG wind energy conversion system. IEEE Trans. Sustain. Energy 10(2), 604–614 (2019) 18. J. Li et al., High voltage ride-through control strategy of doubly-fed induction generator based wind turbines with a series grid-side converter. Power Syst. Technol. 38(11) (2014) 19. K. Ma, M. Liserre, F. Blaabjerg, Reactive power influence on the thermal cycling of multi-MW wind power inverter, in IEEE Transactions on Industry Applications, vol. 49, no. 2, Mar-Apr 2013, pp. 922–930 20. Nityanand, A. K. Pandey, Electrical engineering aspects and future trends for PMSG turbines and power converters: a present market survey, 2018 International Conference on Power Energy, Environment and Intelligent Control (PEEIC), Greater Noida, India (2018), pp. 683–688 21. Y. Xia, K.H. Ahmed, B.W. Williams, Different torque ripple reduction methods for wind energy conversion systems using diode rectifier and boost converter, 2011 IEEE International Electric Machines & Drives Conference (IEMDC), Niagara Falls, ON (2011), pp. 729–734

22

1 Research Status and Development

22. V. Yaramasu, B. Wu, Predictive control of a three-level boost converter and an NPC Inverter for high-power PMSG-Based medium voltage wind energy conversion systems. IEEE Trans. Power Electron. 29(10), 5308–5322 (2014) 23. A. Marzouki, M. Hamouda, F. Fnaiech, A review of PWM voltage source converters based industrial applications, in 2015 International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles (ESARS), Aachen (2015), pp. 1–6 24. K. Hatua, V.T. Ranganathan, A novel VSI- and CSI-Fed active-reactive induction motor drive with sinusoidal voltages and currents. IEEE Trans. Power Electron. 26(12), 3936–3947 (2011) 25. Y. Tang, P.C. Loh, P. Wang, F.H. Choo, F. Gao, F. Blaabjerg, Generalized design of high performance shunt active power filter with output LCL filter. IEEE Trans. Ind. Electron. 59 (3), 1443–1452 (2012) 26. F.E. Lahouar, J. Ben Hadj Slama, M. Hamouda, F. Ben Mustapha, Comparative study between two and three-level topologies of grid connected photovoltaic converters, in 2014 5th International Renewable Energy Congress (IREC), Hammamet (2014), pp. 1–6 27. X. Fan, L. Guan, C. Xia, J. He, A passivity control strategy for VSC-HVDC connected large scale wind power, in 2013 IEEE PES Innovative Smart Grid Technologies Conference (ISGT), Washington, DC (2013), pp. 1–6 28. K.G. Jayanth, V. Boddapati, R.S. Geetha, Comparative study between three-leg and four-leg current-source inverter for solar PV application, in 2018 International Conference on Power, Instrumentation, Control and Computing (PICC), Thrissur (2018), pp. 1–6 29. P. Chamarthi, N. Pragallapati, V. Agarwal, Novel 1-/ multilevel current source inverter for balanced/unbalanced PV sources, in 2014 IEEE 40th Photovoltaic Specialist Conference (PVSC), Denver, CO (2014), pp. 3090–3093 30. W. Wang, F. Gao, L. Zhang, M. Chen, L. Zhou, Optimal switching counts modulation of H7 current source inverter, in 2016 IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI (2016), pp. 1–6 31. T. Noguchi, Suroso, Review of novel multilevel current-source inverters with H-bridge and common-emitter based topologies, 2010 IEEE Energy Conversion Congress and Exposition, Atlanta, GA (2010), pp. 4006–4011 32. R.A. Krishna, L.P. Suresh, A brief review on multi level inverter topologies, in 2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT), Nagercoil (2016), pp. 1–6 33. A.K. Koshti, M.N. Rao, A brief review on multilevel inverter topologies, in 2017 International Conference on Data Management, Analytics and Innovation (ICDMAI), Pune (2017), pp. 187–193 34. W. McMurray, Fast response stepped-wave switching power converter circuit, U.S. Patent 3 581 212, 25 May 1971 35. R.H. Baker, High-voltage converter circuit, U.S. Patent 4 203 151, 13 May 1980 36. T.A. Meynard, H. Foch, Multi-level choppers for high voltage applications, in Proceedings of the European Conference on Power Electronics and Application, vol. 2 (1992), pp. 45– s50 37. I.D. Pharne, Y.N. Bhosale, A review on multilevel inverter topology, in 2013 International Conference on Power, Energy and Control (ICPEC) (Sri Rangalatchum Dindigul, 2013), pp. 700–703 38. S.V. Brovanov, S.D. Egorov, Review of AC voltage generation systems based on multilevel converters and photovoltaic cells, in 2013 14th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices, Novosibirsk (2013), pp. 275– 278 39. K. Jain, P. Chaturvedi, Matlab-based simulation & analysis of three-level SPWM inverter. Int. J. Soft Comput. Eng (IJSCE) 2(1) (2012). ISSN: 2231-2307 40. M. Vijeh, M. Rezanejad, E. Samadaei, K. Bertilsson, A general review of multilevel inverters based on main submodules: structural point of view. IEEE Trans. Power Electron. 34(10), 9479–9502 (2019)

References

23

41. F.Z. Peng, A generalized multilevel inverter topology with self voltage balancing, in Conference Record of the 2000 IEEE Industry Applications Conference. Thirty-Fifth IAS Annual Meeting and World Conference on Industrial Applications of Electrical Energy (Cat. No.00CH37129), Rome, Italy, vol. 3 (2000), pp. 2024–2031 42. P. Barbosa, P. Steimer, L. Meysenc, M. Winkelnkemper, J. Steinke, N. Celanovic, Active neutral-point-clamped multilevel converters, 2005 IEEE 36th Power Electronics Specialists Conference, Recife (2005), pp. 2296–2301 43. J. Rodriguez, J.-S. Lai, F.Z. Peng, Multilevel inverters: a survey of topologies, controls, and applications, in IEEE Transactions on Industrial Electronics, vol. 49, no. 4, Aug 2002, pp. 724–738 44. U.R. Prasanna, A.K. Rathore, Dual three-pulse modulation-based high-frequency pulsating DC link two-stage three-phase inverter for electric/hybrid/fuel cell vehicles applications. IEEE J. Emerg. Sel. Top. Power Electron. 2(3), 477–486 (2014) 45. D. Debnath, K. Chatterjee, Two-Stage solar photovoltaic-based stand-alone scheme having battery as energy storage element for rural deployment. IEEE Trans. Ind. Electron. 62(7), 4148–4157 (2015) 46. Y.F. Wang, L.K. Xue, C.S. Wang, P. Wang, W. Li, Interleaved high-conversion-ratio bidirectional DC-DC converter for distributed energy-storage systems—circuit generation, analysis, and design. IEEE Trans. Power Electron. 31(8), 5547–5561 (2016) 47. O. Ellabban, H. Abu-Rub, Z-source inverter: topology improvements review. IEEE Ind. Electron. Mag. 10(1), 6–24 (2016) 48. L. Liu, H. Li, Y. Zhao, X. He, Z.J. Shen, 1 MHz cascaded Z-source inverters for scalable grid-interactive photovoltaic (PV) applications using GaN device, in Proceedings of the 2011 IEEE Energy Conversion Congress and Exposition (ECCE) (2011), pp. 2738–2745 49. Y. Zhou, L. Liu, H. Li, A high-performance photovoltaic module-integrated converter (MIC) based on cascaded quasi-Z-source inverters (qZSI) using eGaN FETs. IEEE Trans. Power Electron. 28(6), 2727–2738 (2013) 50. D. Sun, B. Ge, F.Z. Peng, H. Abu-Rub, D. Bi, Y. Liu, A new grid-connected PV system based on cascaded H-bridge quasi-Z-source inverter, in Proceedings of the 2012 IEEE International Symposium on Industrial Electronics (ISIE) (2012), pp. 951–956 51. Y. Fayyad, L. Ben-Brahim, Multilevel cascaded Z source inverter for PV power generation system, in Proceedings of the 2012 International Conference on Renewable Energy Research and Applications (ICRERA) (2012), pp. 1–6 52. Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, A modular multilevel space vector modulation for photovoltaic quasi-Z-source cascade multilevel inverters, in Proceedings of the 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) (2013), pp. 714–718 53. Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, An effective control method for quasi-Z-source cascade multilevel inverter-based grid-tie single-phase photovoltaic power system. IEEE Trans. Ind. Informat. 10(1), 399–407 (2014) 54. Y. Xue, B. Ge, F.Z. Peng, Reliability, efficiency, and cost comparisons of MW scale photovoltaic inverters, in Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE) (2012), pp. 1627–1634 55. S. Qu, W. Yongyu, On control strategy of Z-source inverter for grid integration of direct-driven wind power generator, in 31st Chinese Control Conference (CCC), pp. 6720– 6723, 25–27 July 2012 56. X. Wang, D.M. Vilathgamuwa, K.J. Tseng, C.J. Gajanayake, Controller design for variable-speed permanent magnet wind turbine generators interfaced with Z-source inverter, in Proceedings of the International Conference on Power Electronics and Drive Systems (PEDS) (2009), pp. 752–757 57. S.M. Dehghan, M. Mohamadian, A.Y. Varjani, A new variable-speed wind energy conversion system using permanent-magnet synchronous generator and Z-source inverter. IEEE Trans. Energy Convers. 24(3), 714–724 (2009)

24

1 Research Status and Development

58. U. Supatti, F.Z. Peng, Z-source inverter with grid connected for wind power system, in Proceedings of the 2009 IEEE Energy Conversion Congress and Exposition (ECCE) (2009), pp. 398–403 59. T. Maity, H. Prasad, V. R. Babu, Study of the suitability of recently proposed quasi Z-source inverter for wind power conversion, in Proceedings of the 2014 International Conference on Renewable Energy Research and Application (ICRERA) (2014), pp. 837–841 60. W.-T. Franke, M. Mohr, F.W. Fuchs, Comparison of a Z-source inverter and a voltage-source inverter linked with a DC/DC-boost-converter for wind turbines concerning their efficiency and installed semiconductor power, in Proceedings of the 2008 IEEE Power Electronics Specialists Conference (PESC) (2008), pp. 1814–1820 61. Y. Liu, B. Ge, F.Z. Peng, H. Abu-Rub, A.T. De Almeida, F.J.T.E. Ferreira, Quasi-Z-source inverter based PMSG wind power generation system, in Proceedings of the 2011 IEEE Energy Conversion Congress and Exposition (ECCE) (2011), pp. 291–297 62. B.K. Ramasamy, A. Palaniappan, S.M. Yakoh, Direct-drive low-speed wind energy conversion system incorporating axial-type permanent magnet generator and Z-source inverter with sensorless maximum power point tracking controller. IET Renew. Power Gener. 7(3), 284–295 (2013) 63. F.Z. Peng, M. Shen, K. Holland, Application of Z-source inverter for traction drive of fuel cell-battery hybrid electric vehicles. IEEE Trans. Power Electron. 22(3), 1054–1061 (2007) 64. S.M. Dehghan, M. Mohamadian, A. Yazdian, Hybrid electric vehicle based on bidirectional Z-source nine-switch inverter. IEEE Trans. Veh. Commun. 59(6), 2641–2653 (2010) 65. F. Guo, L. Fu, C. Lin, C. Li, W. Choi, J. Wang, Development of an 85-kW bidirectional quasi-Z-source inverter with DC-Link feed-forward compensation for electric vehicle applications. IEEE Trans. Power Electron. 28(12), 5477–5488 (2013) 66. P. Liu, H.P. Liu, Permanent-magnet synchronous motor drive system for electric vehicles using bidirectional Z-source inverter. IET Electr. Syst. Transp. 2(4), 178–185 (2012) 67. Q. Lei, D. Cao, F.Z. Peng, Novel loss and harmonic minimized vector modulation for a current-fed quasi-Z-source inverter in HEV motor drive application. IEEE Trans. Power Electron. 29(3), 1344–1357 (2014) 68. F.Z. Peng, Z-source inverter. IEEE Trans. Ind. Appl. 39(2), 504–510 (2003) 69. J. Rabkowski, The bidirectional Z-source inverter for energy storage application, in Proceedings of the European Conference on Power Electronics and Applications, 2–5 Sept 2007, pp. 1–10 70. L. Yang, D. Qiu, B. Zhang, G. Zhang, A high-performance Z-source inverter with low capacitor voltage stress and small inductance, in Proceedings of the 5th IEEE Conference on Industrial Electronics and Applications, 15–17 June 2010, pp. 2169–2174 71. J. Anderson, F.Z. Peng, Four quasi-Z-source inverters, in Proceedings of the PESC (2008), pp. 2743–2749 72. M. Zhu, K. Yu, F.L. Luo, Switched inductor Z-source inverter. IEEE Trans. Power Electron. 25(8), 2150–2158 (2010) 73. A.-V. Ho, T.-W. Chun, H.-G. Kim, Extended boost active-switched-capacitor/ switched-inductor quasi-z-source inverters. IEEE Trans. Power Electron. 30(10), 5681– 5690 (2015) 74. V. Jagan, J. Kotturu, S. Das, Enhanced-boost quasi-z-source inverters with two-switched impedance networks. IEEE Trans. Ind. Electron. 64(9), 6885–6897 (2017) 75. W. Qian, F.Z. Peng, H. Cha, Trans-z-source inverters. IEEE Trans. Power Electron. 26(12), 3453–3463 (2011) 76. R. Strzelecki, M. Adamowicz, N. Strzelecka, W. Bury, New type T-source inverter, in Proceedigns of the CPE (2009), pp. 191–195 77. M. Adamowicz, LCCT-z-source inverters, in Proceedings of the EEEIC (2011), pp. 1–16 78. P.C. Loh, D. Li, F. Blaabjerg, Г-Z-source inverters. IEEE Trans. Power Electron. 28(11), 4880–4884 (2013) 79. M.-K. Nguyen, Y.-C. Lim, Y.-G. Kim, TZ-source inverters. IEEE Trans. Ind. Electron. 60 (12), 5686–5695 (2013)

References

25

80. Y.P. Siwakoti, P.C. Loh, F. Blaabjerg, G.E. Town, Y-source impedance network. IEEE Trans. Power Electron. 29(7), 3250–3254 (2014) 81. R.R. Ahrabi, M.R. Banaei, Improved Y-source DC–AC converter with continuous input current. IET Power Electron. 9(4), 801–808 (2016) 82. A. Hakemi, M. Sanatkar-Chayjani, M. Monfared, Δ-source impedance network. IEEE Trans. Ind. Electron. 64(10), 7842–7851 (2017) 83. M. Adamowicz, N. Strzelecka, T-source inverter. Electr. Rev. 85(10), 233–238 (2009) 84. M.-K. Nguyen, Y.-C. Lim, S.-J. Park, Improved trans-z-source inverter with continuous input current and boost inversion capability. IEEE Trans. Power Electron. 28(10), 4500– 4510 (2013) 85. Z. Aleem, M. Hanif, Operational analysis of improved Г-Z-Source inverter with clamping diode and its comparative evaluation. IEEE Trans. Ind. Electron. 64(12), 9191–9200 (2017) 86. H. Liu, Y. Li, Z. Zhou, W. Wang, D. Xu, A family of low-spikes, high-efficiency Y-source inverters. IEEE Trans. Ind. Electron. 87. H. Liu et al., High step-up Y-source inverter with reduced DC-link voltage spikes. IEEE Trans. Power Electron. 34(6), 5487–5499 (2019) 88. P. Fang Zheng, S. Miaosen, Q. Zhaoming, Maximum boost control of the Z-source inverter. IEEE Trans. Power Electron. 20(4), 833–838 (2005) 89. S. Miaosen, W. Jin, A. Joseph, P. Fang Zheng, L.M. Tolbert, D.J. Adams, Constant boost control of the Z-source inverter to minimize current ripple and voltage stress. IEEE Trans. Ind. Appl. 42(3), 770–778 (2006) 90. J.W. Jung, A. Keyhani, Control of a fuel cell based Z-source converter. IEEE Trans. Energy Convers. 22(2), 467–476 (2007) 91. H. Rostami, D.A. Khaburi, A new method for minimizing of voltage stress across devices in Z-source inverter, in 2011 2nd Power Electronics, Drive Systems and Technologies Conference (2011), pp. 610–614 92. M.S. Diab, A.A. Elserougi, A.M. Massoud, A.S. Abdel-Khalik, S. Ahmed, A pulse width modulation technique for high-voltage gain operation of three-phase Z-source inverters. IEEE J. Emerg. Sel. Top. Power Electron. 4(2), 521–533 (2016) 93. M. Shen, F.Z. Peng, Operation modes and characteristics of the Z-source inverter with small inductance or low power factor. IEEE Trans. Ind. Electron. 55(1), 89–96 (2008) 94. Y. Tang, S. Xie, C. Zhang, Z. Xu, Improved Z-source inverter with reduced Z-source capacitor voltage stress and soft-start capability. IEEE Trans. Power Electron. 24(2), 409– 415 (2009) 95. J. Wei, Y. Tang, S. Xie, Grid-connected PV system based on the series Z-source inverter, in Proceedings of the 5th IEEE Conference on Industrial Electronics and Applications, ICIEA (2010), pp. 532–537 96. Y. Zhu, M. Chen, X. Lee, Y. Tsutomu, A novel quasi-resonant soft-switching Z-source inverter, in Proceedings of the IEEE International Conference Power and Energy (PECon), 2–5 Dec 2012, pp. 292–297 97. A.S. Khlebnikov, S.A. Kharitonov, Application of the Z-source converter for aircraft power generation systems, in Proceedings of the 9th International Workshop and Tutorials on Electron Devices and Materials, EDM, 1–5 July 2008, pp. 211–215 98. E.C. Dos Santos, J. H. G. Muniz, E. P. X. P. Filho, and E. R. C. Da Silva, Dc-ac three-phase fourwire Z-source converter with hybrid PWM strategy, in Proceedings of the 36th Annual Conference on IEEE Industrial Electronics Society, IECON, Nov. 7–10 (2010), pp. 409–414 99. A.S. Khlebnikov, S.A. Kharitonov, P.A. Bachurin, A.V. Geist, D.V. Makarov, Modeling of dual Z-source inverter for aircraft power generation, in Proceedings of the International Conference and Seminar of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), 30 June 2011–4 July 2011, pp. 373–376 100. P.A. Bachurin, D.V. Makarov, A.V. Geist, M.V. Balagurov, D.A. Shtein, Z-source inverter with neutral point, in Proceedings of the 14th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), 1–5 July 2013, pp. 255–258

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1 Research Status and Development

101. V. Erginer, M.H. Sarul, Modified reduced common mode current modulation techniques for Z-Source inverter used in photovoltaic systems, in Proceedings of the 4th Power Electronics, Drive Systems and Technologies Conference (PEDSTC), 13–14 Feb 2013, pp. 459–464 102. P.E.P. Ferraz, F. Bradaschia, M.C. Cavalcanti, F.A.S. Neves, G.M.S. Azevedo, A modified Z-source inverter topology for stable operation of transformerless photovoltaic systems with reduced leakage currents, in Proceedings of the 2011 Brazilian Power Electronics Conference (COBEP), 11–15 Sept 2011, pp. 615–622 103. S. Jiang, F.Z. Peng, Transmission-line theory based distributed Z-source networks for power conversion, in Proceedings of the 26th Annual IEEE Applied Power Electronics Conf. Exposition (APEC), 6–11 Mar 2011, pp. 1138–1145 104. F. Gao, P.C. Loh, F. Blaabjerg, C.J. Gajanayake, Operational analysis and comparative evaluation of embedded Z-Source inverters, in Proceedings of the IEEE Power Electronics Specialists Conference, PESC, 15–19 June 2008, pp. 2757–2763 105. M. Zhu, K. Yu, F.L. Luo, Topology analysis of a switched-inductor Z-source inverter, in Proceedings of the 5th IEEE Conference on Industrial Electronics and Applications, 15–17 June 2010, pp. 364–369 106. M. Ismeil, M. Orabi, R. Kennel, O. Ellabban, H. Abu-Rub, Experimental studies on a three phase improved switched Z-source inverter, in Proceedings of the Applied Power Electronics Conference and Exposition, APEC, 16–20 Mar 2014, pp. 1248–1254 107. M.-K. Nguyen, Y.-C. Lim, G.-B. Cho, Switched-inductor quasi-Z-source inverter. IEEE Trans. Power Electron. 26(11), 3183–3191 (2011) 108. K. Deng, J. Zheng, J. Mei, Novel switched inductor quasi-Z-source inverter. J. Power Electron. 14(1), 11–21 (2014) 109. F. Ahmed, H. Cha, S. Kim, H. Kim, Switched-coupled-inductor quasi-Z-source inverter. IEEE Trans. Power Electron. 31(2), 1241–1254 (2016) 110. A. Ho, T. Chun, H.T. Kim, Extended boost active-switched-capacitor/switched-inductor quasi-Z-source inverters. IEEE Trans. Power Electron. 30(10), 568–5690 (2015) 111. M.-K. Nguyen, Y.-C. Lim, J.-H. Choi, Two switched-inductor quasi-Z-source inverters. IET Power Electron. 5(7), 1017–1025 (2012) 112. K. Deng, F. Mei, J. Mei, J. Zheng, G. Fu, An extended switched-inductor quasi-Z-source inverter. J. Electr. Eng. Technol. 9(2), 541–549 (2014) 113. M. Zhu, D. Li, P.C. Loh, F. Blaabjerg, Tapped-inductor Z-Source inverters with enhanced voltage boost inversion abilities, in Proceedings of the 2nd IEEE International Conference on Sustainable Energy Technologies, ICSET, 6–9 Dec 2010, pp. 1–6 114. Y. Zhou, W. Huang, J. Zhao, P. Zhao, Tapped inductor quasi-Z-source inverter, in Proceedings of the 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), 5–9 Feb 2012, pp. 1625–1630 115. C.J. Gajanayake, F.-L. Luo, H.B. Gooi, P.L. So, L.K. Siow, Extended-boost Z-source inverters. IEEE Trans. Power Electron. 25(10), 2642–2652 (2010) 116. D. Vinnikov, I. Roasto, T. Jalakas, R. Strzelecki, M. Adamowicz, Analytical comparison between capacitor assisted and diode assisted cascaded quasi-Z-source inverters. Electr. Rev. 88(1a), 212–217 (2012) 117. D. Vinnikov, I. Roasto, T. Jalakas, S. Ott, Extended boost quasi-Z-source inverters: possibilities and challenges. Electron. Elect. Eng. 112(6), 51–56 (2011) 118. Y.P. Siwakoti, F.Z. Peng, F. Blaabjerg, P.C. Loh, G.E. Town, Impedance-source networks for electric power conversion Part I: a topological review. IEEE Trans. Power Electron. 30 (2), 699–716 (2015) 119. P.C. Loh, F. Blaabjerg, C.P. Wong, Comparative evaluation of pulse width modulation strategies for Z-source neutral-point-clamped inverter. IEEE Trans. Power Electron. 22(3), 1005–1013 (2007) 120. P.C. Loh, S.W. Lim, F. Gao, F. Blaabjerg, Three-level Z-source inverters using a single LC impedance network. IEEE Trans. Power Electron. 22(2), 706–711 (2007)

References

27

121. O. Husev, C. Roncero-Clemente, E. Romero-Cadaval, D. Vinnikov, S. Stepenko, Single phase three-level neutral-point-clamped quasi-Z-source inverter. IET Power Electron. 8(1), 1–10 (2015) 122. W. Mo, P.C. Loh, F. Blaabjerg, P. Wang, Trans-Z-source and C-Z-source neutral-point clamped inverters. IET Power Electron. 8(3), 371–377 (2015) 123. F. Gao, P.C. Loh, F. Blaabjerg, R. Teodorescu, D.M. Vilathgamuwa, Five-level Z-source diode-clamped inverter. IET Power Electron. 3(4), 500–510 (2010) 124. B.K. Chaithanya, A. Kirubakaran, A novel four level cascaded Z-source inverter, in Proceedings of the IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), 16–19 Dec 2014, pp. 1–5 125. Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, An effective control method for quasi-Z-source cascade multilevel inverter-based grid-tie singlephase photovoltaic power system. IEEE Trans. Ind. Inform. 10(1), 399–407 (2014) 126. S.M. Dehghan, M. Mohamadian, A. Yazdian, Hybrid electric vehicle based on bidirectional Z-source nine-switch inverter. IEEE Trans. Veh. Technol. 59(6), 2641–2653 (2010) 127. Y. Liu, H. Abu-Rub, B. Ge, F. Blaabjerg, O. Ellabban, P.C. Loh, Impedance Source Power Electronic Converters (Wiley, Hoboken, NJ, 2016) 128. S. Jiang, D. Cao, F. Z. Peng, High frequency transformer isolated Z-source inverters, in Proceedings of the 26th Annual IEEE Applied Power Electronics Conference and Exposition (APEC) (2011), pp. 442–449 129. L. Pan, L-Z-source inverter. IEEE Trans. Power Electron. 29(12), 6534–6543 (2014) 130. H. Liu, et al., Extended quasi-Y-source inverter with suppressed inrush and leakage effects, in IET Power Electronics, vol. 12, no. 4, 4 Oct 2019, pp. 719–728 131. M.A. Briere, GaN based power conversion: a new era in power electronics, in Proceedings of the PCIM Europe Conference (2009)

Chapter 2

Z-Source Inverter and Control

Abstract As the oldest impedance source inverters, Z-source inverter is one of the typical topologies, whose analytical and control methods can be transplanted to other impedance source inverters. Besides, since the impedance source inverters are improved from traditional voltage source and current source inverters by inserting an impedance network, they can be classified into voltage-fed and current-fed impedance source inverters. This chapter presents the structure and analysis of voltage-fed Z-source inverter as well as its modulation methods and closed-loop control of shoot-through duty circle. At last but not the least, the introduction of current-fed Z-source inverter is mentioned, which is different from voltage-fed Z-source inverters.

2.1 2.1.1

Voltage-Fed Z-Source Inverter Structure and Equivalent Circuit

As shown in Fig. 2.1, voltage-fed Z-source inverter is developed from traditional voltage source inverter by inserting an impedance network. Since the existing of impedance network, the voltage-fed Z-source inverter can boost voltage by changing the shoot-through (ST) time of inverter bridge. Besides, the dead times that avoiding traditional voltage source inverter bridge direct connection is no longer needed. Moreover, there is no extra switch in the impedance network, which makes the impedance source inverters more attractive than traditional two-stage inverters [1]. For traditional application in solar photovoltaic (PV), wind generation (WG), and other renewable energy, two-stage inverters are widely used since voltage source inverter is a buck inverter for its own defects. The additional stage is usually a DC–DC boost converter, which can make the output voltage meet expected results. However, the introduction of extra converter needs extra switch, which needs additional control circuit. Thus, the cost and volume of inverter will increase and the efficiency may be suffered. The voltage-fed Z-source inverter that utilizes © Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_2

29

30

2 Z-Source Inverter and Control

L1

Vin

C1

C2 vdc

va

S6

L2

S3

S5

vb S4

vc S2

Load or grid

S1

Filter

D1

Impedance Network Fig. 2.1 Structure of voltage-fed Z-source inverter

impedance network is different. There are only one diode, several inductors, and capacitors composed in impedance network. Therefore, the impedance network without extra switches is more attractive. The voltage-fed Z-source inverter can be divided into two parts roughly as shown in Fig. 2.1. One part is the DC source and impedance network, and another part is the inverter bridge with AC load. For impedance source inverter, the first part is more important because nearly all attractive character of inverter turns up after inserting the impedance network. Besides, the booster feature of impedance network depends on the ST time of inverter bridge. Hence, the inverter bridge of second part could be equivalent to one switch SW. When the impedance source inverter turns into ST state, the equivalent switch turns on. And the equivalent switch turns off while the impedance source inverter enters into non-shoot-through (NST) state. As for the AC load of ZSI, it can be equivalent as a constant current source. The AC load is short out when the equivalent switch turns on, while the AC load represents constant voltage applied to a constant load when the impedance source inverter turns into NST state. Therefore, the equivalent circuit of voltage-fed Z-source inverter shown as Fig. 2.2 can be obtained.

L1

D1

Vin

C1

C2

L2 Fig. 2.2 Equivalent circuit of voltage-fed Z-source inverter

SW

vdc

Io

2.1 Voltage-Fed Z-Source Inverter

2.1.2

31

Circuit Analysis

Based on the equivalent circuit in Fig. 2.2, further research of voltage-fed Z-source inverter can be carried out. Figures 2.3 and 2.4 reveal the ST and NST states of voltage-fed Z-source inverter, respectively. When the equivalent switch SW turns on, namely, the inverter turns into ST state, the diode D1 is blocked as shown in Fig. 2.3. Correspondingly, D1 begins to conduct when the switch SW turns off as demonstrated in Fig. 2.4. The voltage and current analyses of voltage-fed Z-source inverter are displayed as follows. In order to simplify the analysis of voltage-fed Z-source inverter, the inductors L1 and L2 as well as the capacitance of C1 and C2 are assumed to be same, respectively. Therefore, the following equations can be obtained: VC1 ¼ VC2 ¼ VC

ð2:1Þ

vL1 ¼ vL2 ¼ vL

ð2:2Þ

When the voltage-fed Z-source inverter enters into the equivalent circuit as shown in Fig. 2.3, namely, ST state, the voltage across inductors and dc-link could be derived as follows: vL ¼ VC

ð2:3Þ

vdc ¼ 0

ð2:4Þ

And when the inverter turns into the NST state as shown in Fig. 2.4, corresponding voltage across dc-link and inductors can be written as vL ¼ Vin  VC

ð2:5Þ

vdc ¼ VC  VL ¼ 2VC  Vin

ð2:6Þ

L1

Vin

C1

C2

SW

L2 Fig. 2.3 Shoot-through (ST) state of voltage-fed Z-source inverter

vdc

Io

32

2 Z-Source Inverter and Control

L1

Vin

C1

C2

SW

vdc

Io

L2 Fig. 2.4 Non-shoot-through (NST) state of voltage-fed Z-source inverter

Applying volt-second balance to the inductors over a switching period T then leads to VC  dT þ ðVin  VC Þ  ð1  dÞT ¼ 0

ð2:7Þ

where d represents the ST duty ratio. Thus, we have VC 1  d ¼ Vin 1  2d

ð2:8Þ

As for the average voltage across dc-link, it can be derived as Vdc ¼ 0  dT þ ð2VC  Vin Þ  ð1  dÞT ¼ VC

ð2:9Þ

Vdc 1d ¼ Vin 1  2d

ð2:10Þ

Therefore,

Besides, the peak dc-link voltage across the inverter bridge is further expressed as vdc ¼ 2VC  Vin ¼

2ð1  dÞ 1 Vin  Vin ¼ Vin ¼ BVin 1  2d 1  2d

ð2:11Þ

where B represents the boost factor of voltage-fed Z-source inverter. The voltage vdc is also the input voltage of the inverter bridge. Then the peak output voltage from inverter can be obtained as vac ¼ M 

vdc 2

ð2:12Þ

2.1 Voltage-Fed Z-Source Inverter

33

where M is the modulation index. Combining (2.112.11) and (2.12), then vac ¼ M  B 

Vin 2

ð2:13Þ

Compared with the peak output voltage from traditional voltage source inverter, which can be expressed as vac ¼ M  V2in , the peak output voltage of voltage-fed Z-source inverter contains one more boost factor B. Therefore, the output voltage can be stepped up infinitely in theory when the boost factor is large enough. Besides, the peak-to-peak value of output voltage could still be lower than input voltage when the boost factor is small and then the product of M and B is still little than 1, which makes the output flexibility of inverter to increase.

2.1.3

Quasi-Z-Source Inverter

With the development of Z-source inverters, quasi-Z-source inverter (QZSI) that improved from voltage-fed Z-source inverter turns up. For example, the QZSI with discontinuous input current shown in Fig. 2.5 is proposed in [2]. This type of QZSI has several advantages compared with voltage-fed Z-source inverter, such as lower component rating, reduced common-mode noise. Besides, [2] also proposes another type of QZSI as shown in Fig. 2.6, whose one more advantage over the previous type of QZSI is continuous input current. These two types of QZSI are widely applied in practical applications like PV, WG, and motor driver. Analogous to the equivalent circuit of voltage-fed Z-source inverter, the inverter bridge and AC load of quasi-Z-source inverter are equivalent to one switch SW in parallel with a constant current source. The continuous input current is vital in numerous occasions, thus the structure of continuous input current quasi-Z-source inverter is more popular. Figure 2.7 illustrates the equivalent circuit of C2 L2 S1 Vin

C1

vdc

va

S6

S3

S5

vb S4

Quasi-Z Network Fig. 2.5 Quasi-Z-source inverter with discontinuous input current

vc S2

Load or grid

D1

Filter

L1

34

2 Z-Source Inverter and Control

C2 L2 S1 Vin

C1

vdc

va

S6

S3

S5

vb S4

vc S2

Load or grid

D1

Filter

L1

Quasi-Z Network Fig. 2.6 Quasi-Z-source inverter with continuous input current

quasi-Z-source inverter with continuous input current. Similarly, quasi-Z-source inverter can also be divided into two states, i.e., ST state and NST state. When the equivalent switch SW turns on, which means the quasi-Z-source inverter enters into ST state, the diode D1 is blocked. On the contrary, the diode turns on when the equivalent switch turns off, namely, the state of quasi-Z-source inverter changes to NST state. To simplify the analysis of quasi-Z-source inverter with continuous input current, the inductors L1 and L2 as well as the capacitance of C1 and C2 are also assumed to be same, respectively. Thus, the following equations can be obtained: VC1 ¼ VC2 ¼ VC

ð2:14Þ

vL1 ¼ vL2 ¼ vL

ð2:15Þ

C2

L1

Vin

D1

C1

L2

SW

vdc

Io

Fig. 2.7 Equivalent circuit of quasi-Z-source inverter with continuous input current

2.1 Voltage-Fed Z-Source Inverter

35

The voltage across inductors and dc-link of quasi-Z-source inverter in the ST state can be expressed as vL ¼ VC

ð2:16Þ

vdc ¼ 0

ð2:17Þ

And in the NST state, the voltage across inductors and dc-link can be written as vL ¼ Vin  VC

ð2:18Þ

vdc ¼ VC  VL ¼ 2VC  Vin

ð2:19Þ

Obviously, the voltage value of quasi-Z-source inverter is same as that of voltage-fed Z-source inverter. Therefore, the same results can be obtained as given below: Vdc 1d ¼ Vin 1  2d vdc ¼

1 Vin ¼ BVin 1  2d

vac ¼ M  B 

Vin 2

ð2:20Þ ð2:21Þ ð2:22Þ

Thus, the quasi-Z-source inverter also has the flexible voltage output capability since the existence of boost factor B. Moreover, in theory, B can be constructed large enough when the duty ratio d is appropriate which is identical with voltage-fed Z-source inverter. However, the quasi-Z-source inverter is widely used because the advantages like lower voltage stress across capacitors, reduced common-mode noise caused by the joint earthing of the input source as well as the dc-link.

2.2 2.2.1

Modulation Methods Simple Boost Pulse-Width Modulation

All the traditional pulse-width modulation (PWM) schemes can be used in the control of Z-source inverter and their theoretical relationships are still true [1]. The only differentia is that the Z-source inverter has one extra zero vector. The traditional three-phase voltage source inverter has two zero vectors when the AC load is shorted through the upper three switches or lower three switches and six active vectors when the energy flows to AC load normally. However, as for the

36

2 Z-Source Inverter and Control

three-phase Z-source inverter, the ninth vector, namely, extra zero vector appears when the AC load is shorted through both the upper and lower switches of any one phase leg, any two phase legs, or all the three phase legs, i.e., the ST state. Figure 2.8 displays the traditional PWM control sequence based on the triangular carrier methods. There are only two NST zero vectors and two neighboring active vectors are composed to synthesize the desired voltage in every switching cycle. This traditional PWM shown in Fig. 2.8 can be also used in voltage-fed Z-source inverter when the actual output voltage is high enough than the desired output voltage. To obtain the higher output voltage, the modified PWM, namely, simple boost pulse-width modulation (SBPWM) illustrated in Fig. 2.9 is proposed. It is noticeable here that each phase leg switches on and off per switching cycle whatever in the control of traditional PWM or SBPWM. Besides, the ST zero vectors are evenly allocated into each phase without changing the total zero-vector time interval. Thus, the active-vector time is unchanged. However, the dc-link

va* vb* vc*

S1

S3

S5

S6

S4 S2 Fig. 2.8 Traditional carrier-based PWM control sequence without shoot-through zero vectors

2.2 Modulation Methods

37

va* vb* vc* S1

S3

S5

S6

S4

S2 Shoot-through zero vectors Fig. 2.9 Modified carrier-based PWM control sequence with shoot-through zero vectors

voltage is enhanced because of the introduction of ST zero vectors. Moreover, the ST zero vectors also make the equivalent switching frequency viewed from the impedance source network be three times the switching frequency of the inverter bridge. Thus, the required inductance of the impedance source network can be reduced while the equivalent switching frequency is improved. The output voltage is sinusoidal wave when the voltage-fed Z-source inverter is connected with grid in practical application. Thus, the PWM control techniques are improved into sinusoidal pulse-width modulation (SPWM). Then the SBPWM control waveform based on SPWM can be displayed in Fig. 2.10. With regard to switches of upper phase legs, there is a straight line greater than or equal to the peak value of three-phase modulated wave, which is used to generate ST duty ratio based on the traditional SPWM. On the contrary, another straight line smaller than or equal to the negative peak value for switches of lower phase leg is applied to obtain

38

2 Z-Source Inverter and Control

ST duty ratio. Therefore, the maximum ST duty ratio of this simple control technique is limited to (1-M), where M represents the modulation index. The ST duty ratio of impedance source inverter under the control of SBPWM will reach zero when the modulation index is set as one. Moreover, the active-vector time of simple control shown in Fig. 2.10 is still unchanged compared with traditional SPWM because the ST zero vectors are all allocated into original NST zero vectors. As for the one-phase voltage-fed Z-source inverter, analogous SBPWM control technique can be applied. There are only two phase legs in the one-phase voltage-fed Z-source inverter, thus two active vectors, two NST zero vectors, and one extra ST zero vector are composed to composite the expected output voltage. Besides, the extra ST zero vector can be abolished when the actual output voltage is high enough than expected output voltage. In other words, the SBPWM control technique of one-phase voltage-fed Z-source inverter is one particular case of three-phase voltage-fed Z-source inverter.

vp vc*

vb* va*

vn S1

S3

S5

S6

S4

S2 Fig. 2.10 Three-phase simple boost pulse-width modulation control waveform based on SPWM

2.2 Modulation Methods

2.2.2

39

Maximum Boost Pulse-Width Modulation

The SBPWM control technique mentioned in last subsection has the biggest advantage of simplicity. However, the high voltage stress across the switches is its main drawback. Thus, [3] proposes maximum boost PWM (MBPWM) which has the advantage of high total gain with reduced voltage stresses. As shown in Eq. (2.13), the final peak output voltage can be expressed as M*B*Vin/2, thus the total gain of voltage-fed Z-source inverter can be defined as M*B/2. Besides, the voltage stresses across switches are B*Vin according to Eq. (2.11). Therefore, B should be minimized while M should be maximized in order to obtain any given total voltage gain with limited voltage stresses across the switches. However, on the other hand, B is required to be maximized for any given modulation index so that maximum voltage gain can be obtained. Consequently, on the basis of Eq. (2.11), the ST duty ratio could be large enough to enhance the value of boost factor. Figure 2.11 illustrates three-phase MBPWM control waveform based on SPWM, where the ST duty ratio is generated according to the maximum and minimum curve of the three-phase sinusoidal wave. Similarly with SBPWM control technique, the ST zero vectors are inserted when the triangular carrier wave is greater than maximum boundary or smaller than minimum curve of the referenced sinusoidal wave. And the six active vectors of MBPWM are still unchanged compared with original SPWM. The only difference between MBPWM and SBPWM is all the zero vectors of traditional SPWM are changed to be ST zero vectors. Therefore, the time of zero vectors in MBPWM is longer than that in SBPWM, which means the ST duty ratio is larger than SBPWM. Thus, the boost factor B is enhanced by using the MBPWM. Besides, a higher modulation index M can be chosen for any given total voltage gain because of the specific selection of ST duty ratio boundary. In consequence, the corresponding boost factor B can be minimized suitably at the given total voltage gain, then lower voltage stresses across the switches are realized. However, under the maximum control, a low-frequency current ripple is associated with fundamental frequency in the inductor current and the capacitor voltage, which leads to higher requirement of the passive components and bigger size of the impedance source network when the fundamental frequency is very low [4]. Thus, this method is more suitable for the applications that have higher fundamental frequency or fixed output frequency so that the six-time frequency current ripple cannot be a problem. In order to issue this drawback of MBPWM, [4] introduces maximum constant boost PWM (CBPWM). The modulation curves to generate ST zero vectors under CBPWM control are not only composed by the maximum or minimum of three-phase sinusoidal wave, but also two envelope signals that keep the ST duty ratio constant. The inverter turns into ST state when the triangular carrier wave is higher than the upper ST curve or lower than the bottom ST curve. Besides, the boost factor B determined by ST duty ratio can be always maximum when the ST duty ratio is constant under the control of CBPWM. Moreover, similarly with the

40

2 Z-Source Inverter and Control

vc*

vb* va*

S1

S3

S5

S6

S4

S2 Fig. 2.11 Three-phase maximum boost pulse-width modulation control waveform based on SPWM

control of MBPWM, the CBPWM control also can choose a higher modulation index M for any given total voltage gain. Thus, the corresponding boost factor B can be minimized suitably at the given total voltage gain, then lower voltage stresses across the switches are also achievable. Therefore, the CBPWM control produces a maximum constant boost while limiting the voltage stresses.

2.2.3

Other Boost Pulse-Width Modulation

The higher modulation index and lower current harmonics can be obtained in traditional PWM by implementing space vector pulse-width modulation (SVPWM) techniques [5]. There are also six active vectors and two zero vectors in total that could be used to compose other vectors. For example, if the reference voltage vector is located between two active vectors, then the reference vector can always

2.2 Modulation Methods

41

be divided into these two active vectors with appropriate zero vectors. Thus, the sampling interval is also composed of the time of active vectors and zero vectors. Then the synthetic output voltage is more similar with sinusoidal wave under the control of SVPWM, hence the current harmonics are lower. Similarly with SBPWM, the SVPWM should be modified when it is implemented in the control of voltage-fed Z-source inverter. The period of zero voltage vectors should be inserted by the ST zero vectors interval evenly, thus an additional ST period that can boost the voltage can be generated. Therefore, the modified space vector pulse-width modulation (MSVPWM) has been proposed in [6, 7]. The linear relations of this control method are extended to wider range of operation than SBPWM. Besides, the MSVPWM does not enhance the gain of voltage-fed Z-source inverter or minimize the voltage stresses across switches since the introduction of ST period is similar with SBPWM. Although the mentioned PWM control techniques all have their characteristics, the boost factor B is all associated with the modulation index M. Therefore, the voltage-fed Z-source inverters cannot realize very high voltage boost factor due to the limitation of modulation index. In order to issue this problem, [8] introduce one novel control technique that can decouple the interdependent relation between the boost factor and the modulation index, which is named as discontinues pulse-width modulation (DCPWM). In this technique, the modulation index is kept at its maximum value constantly, and the boost factor as well as the ST duty ratio is determined by a new parameter but not the modulation index. Thus, the operation of inverter is high stable since the principle of separation between the boost factor and modulation index. Besides, the DCPWM also can lower the voltage stresses across the switches than that under the control of SBPWM and MSVPWM when the relatively high voltage gain is obtained. In consequence, the DCPWM is more suitable for PV and fuel cell applications, which is required for high voltage gain.

2.3 2.3.1

Closed-Loop Control of Shoot-Through Duty Ratio Introduction

Based on the state-space averaging or small-signal model, closed-loop control of power electronic systems is developed gradually [9, 10]. Liu et al. [9] have summarized the control approaches applied for the ZSI or QZSI, which is shown in Fig. 2.12. The input voltage Vin, voltage across capacitors VC, voltage across the DC-link Vdc, and current through inductors iL of Z-source inverter are the control parameters commonly. The control parameter is always compared with the corresponding reference value to obtain its related differential signal. Then the differential signal flows into proportional–integral (PI) regulators in linear control system or non-linear control algorithms in non-linear control system. With regard to PI regulators as shown in Fig. 2.12a, the command signal that outputs from PI regulators can be the ST duty radio d for single-loop controls or the

42

(a)

2 Z-Source Inverter and Control Second stage of dual-loop controls

Vin*, VC* or V dc*

Vin, VC or V dc

iL

PI regulators

PI regulators d

iL*

Fuzzy

(b) Non-linear control

Sliding mode Controlled variables

Vin, VC, Vdc or iL

Neural network Model predictive

Fig. 2.12 Shoot-through duty cycle control by a PI regulators and b non-linear methods (Source Liu 2014 [9]. Reproduced with permission of IEEE)

inductor reference current i*L for dual-loop controls. As for the non-linear control algorithms, several methods such as fuzzy control, sliding mode control, neural network control, and model predictive control have been proposed to process the controlled variables [11–15]. Next, single-loop methods, dual-loop methods, and several advanced control methods will be presented in detail.

2.3.2

Single-Loop Methods

As shown in Fig. 2.12a, the feedback signal is normally collected from the input voltage Vin [9], voltage across capacitors VC [16], or the dc-link voltage Vdc [17]. Then this feedback signal evolves into ST duty ratio command signal by PI regulator. When the feedback signal is Vin, it is convenient to measure. However, the dc-link voltage is difficult to measure directly because Vdc is a pulse voltage waveform in Z-source inverter. Therefore, [18] proposes another measuring method by adding an assisted sampling circuit. But this assisted sampling circuit not only increases the complication of system, but also adds cost. Thus, the voltage across capacitors is usually applied to control the dc-link voltage indirectly based on the relationship between VC and Vdc [15]. Although the single-loop control of ST duty ratio is simple, the dc-link peak voltage will be changed following the variations of input voltage. Thus, the DC-link peak voltage is not constant when the input voltage is fluctuating. Therefore, it is necessary to introduce dual-loop control of ST duty ratio.

2.3 Closed-Loop Control of Shoot-Through Duty Ratio

2.3.3

43

Dual-Loop Methods

The dual-loop control of ST duty ratio has one more inner inductor current loop than signal-loop control of ST duty ratio. The dotted line diagram shown in Fig. 2.12a is the inner inductor current loop that is designed to stabilize the DC-link peak voltage and realize fast response of whole feedback system. Under the dual-loop control, the command signal of outer loop is the inductor reference current i*L, which provides reference signal for inner loop. Then the differential signal can produce the final command ST duty ratio through proportional (P) or PI regulator, where PI regulator has a wider stability margin [10, 19].

2.3.4

Non-linear Control Methods

Figure 2.12b displays several non-linear control methods of ST duty ratio, such as fuzzy control, sliding mode control, neural network control, and model predictive control. The real-time variable Vin, VC, Vdc, or iL is handled by appropriate algorithms by employing those mentioned non-linear control methods. Then the command signal is received directly by tracking the related reference value. The introduction of fuzzy control, sliding mode control, and neural network control increases the dynamic response than traditional PI regulator. Particularly, sliding mode control dispenses with additional PWM techniques. However, all of these non-linear control methods have the common drawback that the control algorithm is complex. Besides, a simpler non-linear control method than mentioned non-linear control methods is proposed in [15], namely, model predictive control. Through a formulated Z-source network model and a minimized cost function, this non-linear control method can adjust the stability of the impedance network, robustness of transient response, and the quality of the output waveforms. This non-linear control method of model predictive is under investigation with the development of Z-source inverter.

2.4 2.4.1

Current-Fed Z-Source Inverter and Control Structure of Current-Fed Z-Source Inverter

Unlike the traditional current source inverter that can only allow unidirectional power flow and boost voltage, the current-fed Z-source inverter that is a single-stage structure can buck–boost voltage and achieve bidirectional power flow. Besides, at least one upper and one lower switch of traditional current source inverter have to be conducted simultaneously, where the conduction time is called

44

2 Z-Source Inverter and Control

L1

C2

D1 va

vdc S6

D7

D6

D3 vb S4 D4

S5

D5 vc S2

Load or grid

C1

Idc

S3

Filter

S1

D2

Impedance Network Fig. 2.13 Structure of current-fed Z-source inverter

overlap time. However, the current-fed Z-source inverter does not need the overlap time which is necessary for traditional current source inverter [20]. Figure 2.13 shows the structure of current-fed Z-source inverter, where the impedance network is similar with that of voltage-fed source inverter except the location of diode. The current-fed Z-source inverter has an additional open-circuit (OC) state due to the introduction of impedance network. The switches of current-fed Z-source inverter are blocked in the OC state. Besides, all inductive currents do not break in this state, thus the current-fed Z-source inverter can boost the output current. Then the output voltage will be operated at buck mode in turn. Therefore, the current-fed Z-source inverter can realize the function of buck–boost by adjusting the time of OC state. Analogy to voltage-fed Z-source inverter, the OC state in current-fed Z-source inverter is equivalent to the ST state which can boost the voltage of voltage-fed Z-source inverter. Hence, the analysis, modulation, and control of current-fed Z-source inverter all can be in analogy with that of voltage-fed Z-source inverter.

2.4.2

Modes of Current-Fed Z-Source Inverter

The inverter bridge and load of current-fed Z-source inverter can be equivalent as one equivalent switch (SW) series with one voltage source. When the current-fed Z-source inverter turns into non-open-circuit (NOC) state as shown in Fig. 2.14, the equivalent switch turns on, at the meantime the diode begins to be blocked. And the equivalent switch turns off while the impedance source inverter enters into OC state as illustrated in Fig. 2.15. Then the diode conducts during the OC state.

2.4 Current-Fed Z-Source Inverter and Control

45

L1

Idc

C1

SW

C2

Vo

Fig. 2.14 Non-open-circuit (NOC) state of current-fed Z-source inverter

L1

Idc

C1

SW

C2

Vo

Fig. 2.15 Open-circuit (OC) state of current-fed Z-source inverter

2.4.3

Modulation of Current-Fed Z-Source Inverter

All the pulse-width modulation (PWM) schemes and their theoretical relationships used in the control of voltage-fed Z-source inverter are almost suitable in the control of current-fed Z-source inverter, such as SBPWM, MBPWM, CBPWM, MSVPWM, and DCPWM [21]. The biggest difference between the control of current-fed Z-source inverter and voltage-fed Z-source inverter is that the additional zero ST vectors in voltage-fed Z-source inverter should be replaced by extra zero OC vectors, then the control of current-fed Z-source inverter can be obtained. And the switches should be blocked when the triangular carrier wave is greater than maximum boundary or smaller than minimum curve of the referenced sinusoidal wave. Thus, the drive signals of switches in the zero OC vectors are low level while those of the zero ST vectors are in high level. For example, Fig. 2.16 displays the simple boost pulse-width modulation control waveform applied in current-fed Z-source inverter. Compared with Figs. 2.16 and 2.10, the mentioned difference between the control of voltage-fed Z-source inverter and current-fed Z-source inverter can be obvious. As for other PWM control techniques, similar modulation waveform can be obtained.

46

2 Z-Source Inverter and Control

vp vc*

vb* va*

vn S1

S3

S5

S6

S4

S2 Fig. 2.16 Three-phase simple boost pulse-width modulation control waveform applied in current-fed Z-source inverter

2.4.4

Closed-Loop Control of Current-Fed Z-Source Inverter

Figure 2.17 illustrates the schematic diagram of closed-loop control of current-fed Z-source inverter. Different from the closed-loop control of voltage-fed Z-source inverter shown in Fig. 2.12a, the main control parameter is current through Second stage of dual-loop controls iL*

iL

VC

PI regulators

VC*

PI regulators

Fig. 2.17 Schematic diagram of closed-loop control of current-fed Z-source inverter

d

2.4 Current-Fed Z-Source Inverter and Control

47

inductors iL [22]. Thus, the reference current subtracts the current through inductors to obtain the input of PI regulator. Then the command signal which is the OC duty radio for single-loop control or the reference capacitor voltage for dual-loop control is output. As for the non-linear control methods, similar application with voltage-fed Z-source inverter can be realized.

2.5

Summary

This chapter introduces the structures, analysis, modulation methods, closed-loop control of two main kinds of fundamental impedance source inverters, i.e., voltage-fed Z-source inverter and current-fed Z-source inverter. Among them, the voltage-fed Z-source inverter is presented in detail since the voltage control is simple to implement and voltage-fed source inverters are more widely applied practical applications. In this chapter, the original voltage-fed Z-source inverter and voltage-fed quasi-Z-source inverter are introduced. Both inverters are the typical impedance source inverters and have an important influence on the development of impedance source inverters which will be presented in next chapter. Mode analysis of them is presented and their boost factors are consistent although they have large differences in structure. Besides, the quasi-Z-source inverter is easier to analyze and has lower component rating and reduced common-mode noise than Z-source inverter. Several modulation methods such as SBPWM, MBPWM, CBPWM, MSVPWM, and DCPWM are shown in this chapter. The MBPWM has higher voltage gain and lower voltage stresses across switches than SBPWM. And the CBPWM overcomes the disadvantage of the low-frequency current ripple of MBPWM. MSVPWM is proposed to reduce the lower current harmonics and increase modulation index, while DCPWM can decouple the boost factor and modulation index. Thus, the operation of inverter is relatively highly stable under the control of DCPWM. Besides, it is worth mentioning that all of them can be applied in voltage-fed or current-fed Z-source inverters, and the only difference between them is the electrical level of additional zero vectors. Moreover, the closed-loop control of shoot-through duty radio for voltage-fed Z-source inverter is introduced in detail. This chapter enumerates single-loop, dual-loop, and other advanced non-linear control methods. The single-loop control of ST duty ratio is simple to realize. However, the DC-link peak voltage will be changed following the variations of input voltage under the single-loop control. Thus, the DC-link peak voltage is not constant when the input voltage is fluctuating. Therefore, it is necessary to apply dual-loop control of ST duty ratio to the practical applications. In addition, more advanced non-linear control methods are introduced to improve the control quality of impedance source inverters.

48

2 Z-Source Inverter and Control

References 1. F.Z. Peng, Z-source inverter. IEEE Trans. Ind. Appl. 39(2), 504–510 (2003) 2. J. Anderson, F.Z. Peng, Four quasi-Z-source inverters, in 2008 IEEE Power Electronics Specialists Conference, Rhodes (2008), pp. 2743–2749 3. F.Z. Peng, M. Shen, Z. Qian, Maximum boost control of the Z-source inverter, in IEEE Transactions on Power Electronics, vol. 20, no. 4, July 2005, pp. 833–838 4. M. Shen, J. Wang, A. Joseph, F.Z. Peng, L.M. Tolbert, D.J. Adams, Constant boost control of the Z-source inverter to minimize current ripple and voltage stress, in IEEE Transactions on Industry Applications, vol. 42, no. 3, May–June 2006, pp. 770–778 5. Q. Tran, T. Chun, J. Ahn, H. Lee, Algorithms for controlling both the DC boost and AC output voltage of Z-source inverter. IEEE Trans. Ind. Electron. 54(5), 2745–2750 (2007) 6. H. Rostami, D.A. Khaburi, A new method for minimizing of voltage stress across devices in Z-source inverter, in 2011 2nd Power Electronics, Drive Systems and Technologies Conference, Tehran (2011), pp. 610–614 7. J. Jung, A. Keyhani, Control of a fuel cell based Z-source converter. IEEE Trans. Energy Convers. 22(2), 467–476 (2007) 8. M.S. Diab, A.A. Elserougi, A.M. Massoud, A.S. Abdel-Khalik, S. Ahmed, A pulsewidth modulation technique for high-voltage gain operation of three-phase Z-source inverters. IEEE J. Emerg. Sel. Top. Power Electron. 4(2), 521–533 (2016) 9. Y. Liu, H. Abu-Rub, B. Ge, Z-source/quasi-Z-source inverters-derived networks, modulations, controls, and emerging applications to photovoltaic conversion. IEEE Ind. Electron. Mag. 8(4), 32–44 (2014) 10. S. Bacha, I. Munteanu, A. I. Bratcu, Power Electronic Converters Modeling and Control: with Case Studies. Wiley (2013) 11. X. Ding, Z. Qian, S. Yang, B. Cui, F.Z. Peng, A direct dc-link boost voltage PID-like fuzzy control strategy in Z-source inverter, in Proceedings of the IEEE Power Power Electronics Specialist Conference (PESC) (2008), pp. 405–411 12. A.H. Rajaei, S. Kaboli, A. Emadi, Sliding-mode control of Z-source inverter, in Proceedings of the IEEE 34th Annual Conference on IEEE Industrial Electronics, 10–13 Nov 2008, pp. 947–952 13. H. Rostami, D.A. Khaburi, Neural networks controlling for both the DC boost and AC output voltage of Z-source inverter, in Proceedings of the 1st Power Electronics Drive Systems Technology Conference, 17–18 Feb 2010, pp. 135–140 14. W. Mo, P.C. Loh, F. Blaabjerg, Model predictive control for Z-source power converter, in Proceedings of the 8th International Conference on Power Electronics, 30 May–3 Jun 2011, pp. 3022–3028 15. M. Mosa, H. Abu-Rub, J. Rodríguez, High performance predictive control applied to three phase grid connected quasi-Z-source inverter, in Proceedings of the 39th Annual Conference of the IEEE Industrial Electronics Society (IECON) (2013), pp. 5812–5817 16. A. Yazdani, R. Iravani, Voltage-Sourced Converters in Power Systems: Modeling, Control, and Applications. Wiley (2010) 17. Y. Li, S. Jiang, J. Cintron-Rivera, F.Z. Peng, Modeling and control of quasi-Z-source inverter for distributed generation applications. IEEE Trans. Ind. Electron. 60(4), 1532–1541 (2013) 18. C.J. Gajanayake, D.M. Vilathgamuwa, P.C. Loh, Development of a comprehensive model and a multiloop controller for Z-source inverter DG systems. IEEE Trans. Ind. Electron. 54, 2352–2359 (2007) 19. Q.-V. Tran, T.-W. Chun, H.-G. Kim, E.-C. Nho, Minimization of voltage stress across switching devices in the Z-source inverter by capacitor voltage control. J. Power Electron. 9 (3), 335–342 (2009) 20. X.-P. Fang, Z.-M. Qian, B.-G. Qi Gao, F.-Z. Peng, X.-M. Yuan, Current mode Z-source inverter-fed ASD system, in 2004 IEEE 35th Annual Power Electronics Specialists Conference (IEEE Cat. No.04CH37551), Aachen, Germany, vol. 4 (2004), pp. 2805–2809

References

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21. X. Fang, Maximum boost control of the current-fed Z-source inverter, in 2008 IEEE International Conference on Industrial Technology, Chengdu (2008), pp. 1–6 22. D.M. Vilathgamuwa, P.C. Loh, M.N. Uddin, Transient modeling and control of Z-source current type inverter, in Proceedings of the IEEE Industry Applications Conference, 23–27 Sept 2007, pp. 1823–1830

Chapter 3

Developments of Impedance Source Inverters

Abstract The developments of impedance source inverters are presented in this chapter, where improvements such as boost ability enhancement and parameter optimization are presented based on which many popular and practical derived topologies from original Z-source inverter are introduced systematically. Section 3.2 introduces the topology improvements with constant boost ratio, which overcome the inherited drawbacks of original Z-source inverters without enhancing boost factors. Section 3.3 presents the family of high boost ratio impedance source inverters which is proposed to enhance the gain based on the previous impedance source inverters. Then a plenty of multilevel and multiplex impedance source inverters are presented to suit for various applications in Sect. 3.4. After that, several novel impedance source inverters with parameter optimization are unfolded in Sect. 3.5.

3.1

Introduction

As Chap. 1 has mentioned, traditional voltage source inverters (VSIs) and current source inverters (CSIs) can only work in buck (step-down) mode or boost (step-up) mode, respectively, because of the inherited features. Besides, the dead times for VSIs and overlap times for CSIs have to be inserted to ensure the stability of inverters with the compromise of slight output waveform distortions. Moreover, the growth of renewable energy requires wider voltage gain range which is difficult for traditional inverters. Although two-stage traditional inverters adding DC–DC converters between the renewable sources and inverter bridges are proposed to adjust voltage gain range, the complexity and size of system in turn increases [1–3]. To address these issues, various single-stage impedance source inverters that can both buck and boost voltages without the demanding for dead times or overlap delays have been proposed [4]. Then the impedance source inverters have been introduced into PV power generation [5–11], wind power generation [12–19], electric vehicles [20–24], and so on. Besides, the impedance source inverters are © Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_3

51

52

3 Developments of Impedance Source Inverters

deservedly divided into voltage-fed impedance source inverters and current-fed impedance source inverters inherited from traditional voltage source and current source inverters. However, the voltage-fed source inverters are widely applied since the voltage control is simpler to realize. Therefore, the development of impedance source inverters mainly introduces the topologies of voltage-fed impedance source inverters. Besides, the current-fed impedance source inverters can be derived from the presented voltage-fed impedance inverters. Thus, the configurations of impedance source inverters mentioned next are limited to voltage-fed impedance source inverters, while the configurations of current-fed impedance source inverters need to be adjusted from those topologies. For convenience, the voltage-fed impedance source inverters are hereinafter referred to as impedance source inverters.

3.2 3.2.1

Topology Improvements with Constant Boost Ratio Z-Source Inverter

The Z-source inverter (ZSI) is the first proposed impedance source inverter in the year of 2003 to overcome the drawbacks of traditional inverters [25]. The schematic diagram of ZSI is shown in Fig. 3.1, which has been presented in last chapter. The introduction of impedance network renders buck–boost characteristics of impedance source inverters with single-stage conversion. And the same phase of inverter bridge can be shoot-through (ST) since the existence of impedance network. The ZSI improves the reliability of inverter and enlarges the application range by adjusting ST time. However, some drawbacks of ZSI have emerged, such as unidirectional power flow, small load range, high inrush starting current, discontinuous input current, high capacitor voltage, and so on. Therefore, improvements have also been introduced to the ZSI to resolve these shortcomings.

L1

Vin

C1

C2

vdc

L2 Impedance Network Fig. 3.1 Schematic diagram of Z-source inverter

va

S6

S3

S5

vb S4

vc S2

Load or grid

S1

Filter

D1

3.2 Topology Improvements with Constant Boost Ratio

3.2.2

Improved Z-Source Inverters

3.2.2.1

Bidirectional Z-Source Inverter

53

The bidirectional Z-source inverter (BZSI) is proposed in [26] to realize the directional power flow based on the ZSI. Figure 3.2 displays the structure of BZSI, where the components are same as the ZSI expect the switch S. The diode of impedance source network in ZSI is replaced by one bidirectional switch. The power flows to the load or grid through the antiparallel diode just like the operation of ZSI when the switch S is blocked. And the power flow can reverse charge the input source when the switch turns on. Therefore, the unidirectional power flow of ZSI has been issued by BZSI.

3.2.2.2

High-Performance Improved Z-Source Inverters

In order to expend the load range when a small impedance network inductor is used, the high-performance Z-source inverter (HP-ZSI) shown in Fig. 3.3 is introduced [27]. Compared with ZSI, the HP-ZSI has one additional capacitor and one extra bidirectional switch than ZSI. Because of that, the impedance network inductors can be designed small and the dc-link voltage drop of HP-ZSI could be eliminated. S

L1

vdc

va

S6

L2

vb S4

vc S2

S3

S5

Load or grid

C2

Load or grid

C1

S5 Filter

Vin

S3

Filter

S1

Fig. 3.2 Structure of bidirectional Z-source inverter

D1

S

L1 S1

Vin

C

C1

C2

L2

va S6

Fig. 3.3 Structure of high-performance Z-source inverter

vb S4

vc S2

54

3 Developments of Impedance Source Inverters

As the initial voltage across capacitors of ZSI is zero, thus, a huge inrush current will charge the capacitors immediately when the inverter is started. Then the resonance of impedance network capacitors and inductors starts, which renders current surge and large voltage that may destroy the components. Besides, the soft-start capability to suppress resonant starting current is difficult to achieve since the ZSI has inherent current path at startup. Therefore, the improved Z-source inverter (IZSI) is derived by exchanging the position of diode and inverter bridge. Figure 3.4 shows the topology of IZSI, which has no current path at startup so that inrush current can be limited. Moreover, the voltage stresses of capacitors can be reduced although the boost factor is invariable with that of ZSI [28]. After that, the high-performance improved Z-source inverter (HP-IZSI) presented in [29] combines the HP-ZSI and IZSI, which is displayed in Fig. 3.5. The inrush current and voltage at startup are limited, and the voltage stresses of capacitors are also reduced. Besides, the HP-ZSI can operate at a wide load range with a small impedance network like the IZSI. In consequence, the HP-IZSI inherits the advantages of HP-ZSI and IZSI.

va S6

S5

vb S4

vc S2

L1

Load or grid

Vin

S3

Filter

S1

C1

C2 D1 L2

Fig. 3.4 Topology of improved Z-source inverter

D1

va C

S6

S5

vb S4

vc S2

L1 Load or grid

Vin

S3

Filter

S1

C1

C2 S

L2 Fig. 3.5 Topology of high-performance improved Z-source inverter

3.2 Topology Improvements with Constant Boost Ratio

3.2.2.3

55

Other Improved Z-Source Inverters

There is another modified topology that can also lower voltage stresses across capacitors and limit inrush current at startup, which is the series Z-source inverter (SZSI) proposed in [30]. The impedance network is parallel with input source in ZSI, while the impedance network is series between the input source and inverter bridge. Figure 3.6 displays the topology of SZSI. Besides, the soft-switching can be realized in ZSI when a quasi-resonant network is implemented. The quasi-resonant soft-switching Z-source inverter (QRSSZSI) shown in Fig. 3.7 is proposed in [31]. All the switches of this inverter can operate at the conditions of both zero voltage on and zero voltage off. Therefore, the efficiency is higher compared with the original ZSI.

3.2.3

Neutral Point Z-Source Inverters

There are many four-wire systems in practical application, thus a plenty of neutral point Z-source inverter are proposed in [32–35]. The four-wire Z-source inverter (FWZSI) shown in Fig. 3.8 is developed from HP-ZSI, adding an extra

D1

va

D2

S6

S3

S5

vb S4

vc S2

S3

S5

Load or grid

L2

Load or grid

C

S1

C2

Filter

C1

Filter

Vin

L1

Fig. 3.6 Topology of series improved Z-source inverter

D2

L1 Lr1

D1

Vin

C1

C2 Cr L2

D3

Lr2

S1 va

S

vb S4

S6

Fig. 3.7 Topology of quasi-resonant soft-switching Z-source inverter

vc S2

56

3 Developments of Impedance Source Inverters

S1

L1

Vin

C3

C4

C2

C1 N

va

vb

S6

L2

S5

S4

vc S2

Load or grid

S3

S1

Filter

D1

S2 Fig. 3.8 Topology of four-wire Z-source inverter Z-source inverter

Vin

C1

C2

va S6

L2

S3

S5

S7

vc S2

vd S8

vb S4

Load or grid

S1

Filter

L1

D1

Fig. 3.9 Topology of four-leg Z-source inverter Z-source inverter

bidirectional switch and splitting the input capacitor to obtain a neutral point [32]. However, in [33], the neutral point is obtained directly by adding a fourth inverter phase leg based on the original ZSI, i.e., four-leg Z-source inverter (FLZSI), as shown in Fig. 3.9. Besides, Fig. 3.10 displays the dual Z-source inverter (DuZSI) proposed in [34], which contains one more three-phase inverter bridge than FWZSI. Therefore, the output voltage quality of DuZSI is improved and current stresses of switches are reduced since the current is divided by the two parallel inverter bridge. However, the introduction of twice switches increases the cost. S1

C3

C4

C2

C1

B1

N L2 S2

Fig. 3.10 Topology of dual Z-source inverter

B2

Load or grid

Vin

L1

Filter

D1

3.2 Topology Improvements with Constant Boost Ratio

S C1

C2

C

va

N

C3

S3

S1

C4 S6

L2

S5

vb vc S2

S4

Load or grid

Vin

L1

Filter

D1

57

Fig. 3.11 Topology of neutral point Z-source inverter

And the neutral point Z-source inverter (NPZSI) illustrated in Fig. 3.11 is modified from HP-ZSI likewise [35]. But the neutral point of NPZSI is obtained by modified impedance network. The capacitors of HP-ZSI are split into two capacitors, respectively, then the spilt points are connected by two additional inductors, whose middle point is a neutral point.

3.2.4

Reduced Leakage Current Z-Source Inverters

In the three-phase transformer-less PV systems, there is leakage current which is always circulating. However, the leakage current will influence the function of inverters. Thus, two kinds of reduced leakage current Z-source inverters are proposed in [36, 37], as shown in Figs. 3.12 and 3.13. Both can prevent the circulation of leakage current effectively through isolating the PV array and the inverter bridge. The ZSI-D shown in Fig. 3.12 is derived from ZSI, adding one fast recovery diode to guarantee a complete isolation of PV array and inverter bridge in the ST state. Thus, the circulation of leakage current will be prevented [36]. While the ZSI-S displayed in Fig. 3.13 is developed from HP-ZSI, adding an additional switch to realize the same function like ZSI-D. Besides, the ZSI-S has an additional advantage that it can operate stabl for all ranges of the modulation index [37]. L1

Rg

C1

C

C 2 va

Rg

L2

CPV D2 Fig. 3.12 Topology of ZSI-D

S6

S3

S5

vb S4

vc S2

Load or grid

S1

CPV

Filter

D1

58

3 Developments of Impedance Source Inverters

S

L1

C1

C

C 2 va

Rg

S6

L2

CPV

S5

vb S4

vc S2

Load or grid

Rg

S3

Filter

S1

CPV

S Fig. 3.13 Topology of ZSI-S

3.2.5

Quasi-Z-Source Inverters

As the introduction in Chap. 2, the quasi-Z-source inverters (QZSIs) proposed in [38] have several advantages compared with ZSI, such as lower component rating, reduced common-mode noise. One of the QZSI is illustrated in Fig. 3.14, where the input current is discontinuous. Besides, [38] also proposes another type of QZSI shown in Fig. 3.15, whose one more advantage over the previous type of QZSI is continuous input current. These two kinds of QZSIs are widely applied in practical applications like PV, WG, and motor driver, even more than the application of ZSI.

3.2.6

Other Basic Z-Source Inverters

When the impedance source inverters are applied in the occasion of high switching, the parasitic and distributed inductance and capacitance will be a major issue and a troublesome consideration for the design of power inverters. Therefore, the

C2 L2

S1 Vin

C1 vdc

va

S6

Fig. 3.14 Topology of discontinuous quasi-Z-source inverter

S3

S5

vb S4

vc S2

Load or grid

D1

Filter

L1

3.2 Topology Improvements with Constant Boost Ratio

59

C2 L2

S3

S1 Vin

C1

vdc

va

S6

S5

vb vc S2

S4

Load or grid

D1

Filter

L1

Fig. 3.15 Topology of continuous quasi-Z-source inverter

L1

C1

C2

Vin/2 L2

vdc

va

S6

S5

vb S4

vc S2

Load or grid

D1

S3

Filter

S1

Vin/2

Fig. 3.16 Topology of embedded Z-source inverter

distributed Z-source inverter (DiZSI) is presented in [39] to intentionally use these parasitic and distributed inductances and capacitances for electromagnetic interference attenuation and power conversion. Besides, in order to smooth the source current and ensure a continuous input current, [40] introduces the embedded Z-source inverter (EZSI) shown in Fig. 3.16. The input source in EZSI is divided into two isolated DC source and each is connected with the inductor of original impedance network. Moreover, imitating the improvement from ZSI to BZSI, the bidirectional quasi-Z-source inverter (BQZSI) shown in Fig. 3.17 can be derived from continuous QZSI [22]. The diode of QZSI is replaced by a bidirectional switch, thus the BQZSI can realize the bidirectional power flow. All the above improved Z-source inverters try to avoid the drawbacks of ZSI and improve the performance. In addition, the boost factors of all improved Z-source inverters are the same as that of ZSI.

60

3 Developments of Impedance Source Inverters

C2 L2

S1 Vin

C1

vdc

va

S6

S3

S5

vb S4

vc S2

Load or grid

S1

Filter

L1

Fig. 3.17 Topology of bidirectional quasi-Z-source inverter

3.3 3.3.1

Topology Developments to Improve Boost Ratio Switched Components Z-Source Inverters

High boost ratio is required in many applications like PV systems. Thus, the boost factor of impedance source inverters should be enhanced. And the switched components Z-source inverters are one of the impedance source inverters with improved boost factors. The switched component Z-source inverters have high boost capability, which will increase the compactness and power density of inverters. Besides, the dependence between boost factor and modulation index can be improved in switched inductor Z-source inverter. In general, the switched component Z-source inverters could further be divided into switched inductor and switched capacitor Z-source inverters [41, 42]. The switched inductor or switched capacitor is a cell composed of inductor or capacitor with diodes. Then the switched inductor Z-source topologies are produced when the inductors of constant boost ratio topologies are replaced by switched inductor cells, while the switched capacitor Z-source topologies are similarly replaced by switched capacitor cells [43–50]. For example, implementing the switched inductor into QZSI, then the switched inductor quasi-Z-source inverter (SL-QZSI) shown in Fig. 3.18 is proposed in [45]. It is obvious that one of the inductors of QZSI is displayed by a switched inductor, and the SL-QZSI achieves higher boost capability than QZSI. Besides, another inductor of QZSI can also be replaced by switched inductor and the boost factor can be further enhanced [49]. Moreover, the inductor of switched inductor cell can be replaced by a new switched inductor. For instance, the extended switched inductor quasi-Z-source inverter (ESL-QZSI) displayed in Fig. 3.19 is obtained by replacing one inductor of switched inductor cell by a whole switched inductor cell. The ESL-QZSI has further high boost factors and higher gain can be obtained when one inductor of second switched inductor cell is replaced by the third switched inductor.

3.3 Topology Developments to Improve Boost Ratio

61

C2 L3

D3 L2

Vin

D4

va

C1

S5

S3

S1

vb

S6

vc S2

S4

Load or grid

D2

D1

Filter

L1

Fig. 3.18 Topology of switched inductor quasi-Z-source inverter

C2

D2 L2

Vin

S

C3

D3 C4

L3 C1

L4 D4

S1 va S6

S3

S5

vb S4

vc S2

Load or grid

D1

Filter

L1

Fig. 3.19 Topology of extended switched inductor quasi-Z-source inverter

However, the components are increasing when the switched inductor cells are nested and the efficiency will be decreased. Thus, more new impedance source inverters with improved boost ratio are gradually developing.

3.3.2

Tapped Inductor Z-Source Inverters

Similarly with switched inductor Z-source inverters, tapped inductor Z-source inverters replace the inductors by tapped inductor cells, which consist of tapped inductors and diodes [51, 52]. The output voltage can be expended by adjusting the turn radio of tapped inductor. And the ST duration can be shorter since the introduction of tapped inductor, thus the larger modulation index could be obtained which leads to a better output waveform quality. For example, the tapped inductor quasi-Z-source inverter (TL-QZSI) that is replacing one inductor of QZSI by the tapped inductor cell is illustrated in Fig. 3.20. The compactness and power density

62

3 Developments of Impedance Source Inverters

C2 L2

L3

D2 S1

D3

Vin

va

C1

S6

S3

S5

vb S4

vc S2

Load or grid

D1

Filter

L1

Fig. 3.20 Topology of tapped inductor quasi-Z-source inverter

of inverters can be also increased with the increasing of boost factor. Besides, the TL-QZSI gives the same boost factor as that of SL-QZSI when the turn ratio of tapped inductor is one with less component count.

3.3.3

Cascaded Quasi-Z-Source Inverters

As the quasi-Z-source topology processes the capability of extending boost factor without extra active switches, the quasi-Z-source topology could be an extended passive boost cell, so that the cascaded quasi-Z-source inverters are proposed [53– 55]. Besides, the cascaded quasi-Z-source inverters are subdivided into capacitor-assisted (CA) and diode-assisted (DA) topologies whether the connecting component of quasi-Z-source cell is capacitor or diode. The capacitor-assisted cascaded quasi-Z-source inverter (CAC-QZSI) is displayed in Fig. 3.21. And when the capacitor C4 is replaced by diode, the topology will become the diode-assisted cascaded quasi-Z-source inverter (DAC-QZSI). Besides, the inductor L3 can be further replaced by another quasi-Z-source topology C2

C4 L2

D2

L3 S1

Vin

C1

C3

va

S6

S3

S5

vb S4

vc S2

Fig. 3.21 Topology of capacitor-assisted cascaded quasi-Z-source inverter

Load or grid

D1

Filter

L1

3.3 Topology Developments to Improve Boost Ratio

63

and then the boost factor is further enhanced. However, similarly with switched components Z-source inverters, the higher gain needs more components which will decrease the efficiency of inverter.

3.3.4

Coupled Inductor Z-Source Inverters

In order to issue the problem that higher gain needs more components, the latest improved boost ratio topologies, namely, coupled inductors Z-source inverters (CISIs) are widely employed because the coupled inductors reduce the quantity of passive components needed in the impedance network [56]. Therefore, the power density of CISIs can be improved and the cost is reduced accordingly. The CISIs can be divided into dual-winding impedance source inverters and three-winding impedance source inverters in general, which will be presented in detail in the next two chapters, respectively. The dual-winding impedance source inverter could be subdivided into T-source inverter (TSI) [57], trans-quasi-Z-source inverter (trans-QZSI) [58], improved trans-QZSI [59], transformer ZSI (TZSI) [60], inductor-capacitor-capacitortransformer ZSI (LCCT-ZSI) [61], Г-source inverter (ГSI) [62]. Each inverter will be presented in Chap. 4. As for the three-winding impedance source inverter, it can be subdivided into Y-source inverter (YSI) [63], improved Y-source inverter (IYSI) [64], and so on. The YSI and IYSI will be introduced in detail in Chap. 5.

3.4 3.4.1

Multilevel and Multiplex Topologies Three-Level Z-Source Inverters

The multilevel technology can also be applied to impedance source inverters like traditional inverters, thus the multilevel and multiplex topologies emerge at the right time. There are several different three-level Z-source inverters that have been proposed in [65–69]. They are all inserted by impedance networks between the input DC source and the traditional three-level neutral-point-clamped inverter shown in Fig. 1.9. The difference of them is the kinds or combination of impedance network.

64

3.4.2

3 Developments of Impedance Source Inverters

Five-Level Z-Source Inverters

As for the five-level Z-source inverters, they are similar with three-level Z-source inverter [69]. The impedance networks are inserted between the input DC source and traditional five-level neutral-point-clamped inverter. However, the quantity of DC source will be changed with the increase of level with regard to the same kind of three-level and five-level Z-source inverters. Besides, the more level Z-source inverters can be similarly derived.

3.4.3

Cascaded Multilevel Z-Source Inverters

Analogy to traditional cascade H-bridge topology shown in Fig. 1.8, the multilevel Z-source inverters can also be cascaded. The multilevel ZSI could be cascaded to get higher voltage gain and system reliability [70, 71]. The four-level cascaded ZSI in [70] gives a higher output voltage gain compared to the conventional four-level cascaded inverter, with similar harmonic distortion and less complex circuitry and control logic. A combination of a QZSI into cascaded H-bridge reduces the voltage gain and improved the system reliability due to the ST capability.

3.4.4

Multiplex Z-Source Inverters

A dual-output ZSI using nine switches has been proposed in [72] to independently supply two different AC loads with buck–boost capability. This topology will be advantageous for high-power inverter applications, where cost and efficiency are key decision factors. A dual-input and dual-output ZSI with two ac outputs and two dc inputs have been proposed in [73]. The dual-input and dual-output ZSI can control amplitude, frequency, and phase of both ac outputs and also control current of both dc inputs.

3.5 3.5.1

Parameter Optimization of Topologies High-Frequency Transformer Isolated Z-Source Topologies

The high-frequency transformer isolated Z-source inverter (HFTI-ZSI) carefully integrates the Z-source network concept into a two-stage DC–DC–AC topology by employing a high-frequency transformer. In addition to inheriting the merits of

3.5 Parameter Optimization of Topologies

65

basic ZSI, the HFTI-ZSI can achieve electrical isolation and a higher voltage boost ratio with reduced total device stresses, which are not possible with the single-stage ZSI [74].

3.5.2

Inductor Z-Source Topologies

The inductor Z-source inverter (L-ZSI) contains inductors and diodes in the Z-network. The L-ZSI uses a unique inductor and diode network for boosting the output voltage, providing a common ground for the dc source and inverter. Furthermore, it avoids the disadvantage caused by capacitors in most ZSI topologies, especially in prohibiting the inrush current at startup and the resonance of Z-source capacitors and inductors, in addition to improving the converter efficiency [75]. However, if the L-Z-source impedance network works in a DCM mode, the dc-link voltage is increasing infinitely, the output voltage will be uncontrollable, and the system is unstable. To avoid the problem caused by the DCM mode, a snubber circuit (Rs and Cs) is needed. In addition, the L-ZSI operates in large ST duty cycles to obtain higher voltage gains, which reduces output power quality.

3.5.3

Extended Quasi-Y-Source Topologies

An extended quasi-YSI, named as E-QYSI, has been proposed in [76]. It uses a coupled inductor with three windings, and it is hence like the YSI, even though the positions of their windings are slightly different. However, unlike the YSI, the E-qYSI has an improved boost factor, which in turn will permit a smaller ST duty ratio, and hence a larger modulation ratio to be used. Its input current is also continuous, and it is significantly alleviated from a large startup inrush. Moreover, with smaller RMS currents flowing through the windings of its coupled inductor, its magnetic core size can be reduced. Despite that, the leakage inductances in series with the windings still exist, whose effects like loss of ST duty ratio and gain, and large dc-link voltage spikes have been suppressed more prominently by the E-qYSI. Furthermore, when compared with the IYSI, the proposed E-QYSI demonstrates a smaller magnetic core and a higher efficiency, even though both inverters are capable of smoothing their input currents. This topology will be further analyzed in Sect. 5.3 of Chap. 5.

3.5.4

Low DC-Link Voltage Spikes Y-Source Topologies

Impedance source inverters using coupled inductors have been investigated as alternatives for providing high step-up voltages. However, leakage inductances of

66

3 Developments of Impedance Source Inverters

the coupled inductors have commonly led to lower overall effectiveness, in addition to generating high dc-link voltage spikes. The latter raises voltage stresses of switches, which, in turn, may reduce the power levels of the inverters. Thus, a plenty of novel inverters are proposed by inserting absorbing circuits, such as high step-up Y-source inverter (HS-YSI) [77], low-spikes, high-efficiency Y-source inverter (LH-YSI) [78], and so forth. The low DC-link voltage spikes Y-source inverter can be divided into four sorts according to the kinds of absorbing circuits, i.e., dual diodes capacitor-diode absorbing circuits (LH-YSI), single diode capacitor-diode clamping circuits (E-QYSI), embedded capacitor-diode absorbing circuits (dual-winding impedance source inverters), and cascaded quasi-Z-network clamping circuits (HS-YSI). All of these will be recommended in Chap. 6.

3.6

Summary

This chapter presents an overview of impedance source inverters’ development. The detailed topologies illustrated in the chapter are voltage type since the voltage-fed Z-source inverter is more widely applied and current type Z-source inverters can be derived from the voltage-fed Z-source inverters. The Z-source inverters with constant boost ratio, modified Z-source inverters with improved boost ratio, multilevel and multiplex topologies as well as optimized Z-source inverters are list one by one to clarify the history of impedance source inverters. The Z-source inverters with constant boost ratio mainly contain Z-source topologies, improved Z-source topologies, neutral point Z-source topologies, reduced leakage current Z-source topologies, and quasi-Z-source topologies. They are proposed to overcome the drawbacks of ZSI except ZSI itself. Besides, all the topologies of this sort have the common feature that the boost factor is all the same as the original ZSI. The modified Z-source inverters with improved boost ratio mainly contain switched component Z-source topologies, tapped inductor Z-source topologies, cascaded quasi-Z-source topologies, and coupled inductor Z-source topologies. Their aims are all to realize high boost ratio based on the Z-source inverters with constant boost ratio. And the switched component Z-source inverters and cascaded quasi-Z-source inverters need more components when the required boost factor is high. While the tapped inductor Z-source inverters and coupled inductor Z-source inverters can obtain high gain with less components. The multilevel and multiplex Z-source inverters mainly contain three-level Z-source topologies, five-level Z-source topologies, cascaded multilevel Z-source topologies, and multiplex Z-source topologies, which are all similar with traditional multilevel and multiplex inverters.

3.6 Summary

67

The optimized Z-source inverters mainly contain high-frequency transformer isolated Z-source topologies, inductor Z-source topologies, extended quasi-Y-source topologies, and low DC-link voltage spikes Y-source topologies, whose parameters are optimized particularly.

References 1. U.R. Prasanna, A.K. Rathore, Dual three-pulse modulation-based high-frequency pulsating DC link two-stage three-phase inverter for electric/hybrid/fuel cell vehicles applications. IEEE J. Emerg. Sel. Top. Power Electron. 2(3), 477–486 (2014) 2. D. Debnath, K. Chatterjee, Two-stage solar photovoltaic-based stand-alone scheme having battery as energy storage element for rural deployment. IEEE Trans. Industr. Electron. 62(7), 4148–4157 (2015) 3. Y.F. Wang, L.K. Xue, C.S. Wang, P. Wang, W. Li, Interleaved high-conversion-ratio bidirectional DC-DC converter for distributed energy-storage systems—circuit generation, analysis, and design. IEEE Trans. Power Electron. 31(8), 5547–5561 (2016) 4. O. Ellabban, H. Abu-Rub, Z-Source inverter: topology improvements review. IEEE Ind. Electron. Mag. 10(1), 6–24 (2016) 5. L. Liu, H. Li, Y. Zhao, X. He, Z. J. Shen, 1 MHz cascaded Z-source inverters for scalable grid-interactive photovoltaic (PV) applications using GaN device, in Proceedings of the 2011 IEEE Energy Conversion Congress and Exposition (ECCE) (2011), pp. 2738–2745 6. Y. Zhou, L. Liu, H. Li, A high-performance photovoltaic module-integrated converter (MIC) based on cascaded quasi-Z-source inverters (qZSI) Using eGaN FETs. IEEE Trans. Power Electron. 28(6), 2727–2738 (2013) 7. D. Sun, B. Ge, F.Z. Peng, H. Abu-Rub, D. Bi, Y. Liu, A new grid-connected PV system based on cascaded H-bridge quasi-Z source inverter, in Proceedings of the 2012 IEEE International Symposium on Industrial Electronics (ISIE) (2012), pp. 951–956 8. Y. Fayyad, L. Ben-Brahim, Multilevel cascaded Z source inverter for PV power generation system, in Proceedings of the 2012 International Conference on Renewable Energy Research and Applications (ICRERA) (2012), pp. 1–6 9. Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, A modular multilevel space vector modulation for photovoltaic quasi-Z-source cascade multilevel inverters, in Proceedings of the 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC) (2013), pp. 714–718 10. Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, An effective control method for quasi-Z-source cascade multilevel inverter-based grid-tie single-phase photovoltaic power system. IEEE Trans. Ind. Informat. 10(1), 399–407 (2014) 11. Y. Xue, B. Ge, F.Z. Peng, Reliability, efficiency, and cost comparisons of MW scale photovoltaic inverters, in Proceedings of the IEEE Energy Conversion Congress and Exposition (ECCE) (2012), pp. 1627–1634 12. S. Qu, W. Yongyu, On control strategy of Z‐source inverter for grid integration of direct-driven wind power generator, in 31st Chinese Control Conference (CCC), pp. 6720– 6723, 25–27 July 2012 13. X. Wang, D.M. Vilathgamuwa, K.J. Tseng, C.J. Gajanayake, Controller design for variable-speed permanent magnet wind turbine generators interfaced with Z-source inverter, in Proceedings of the International Conference on Power Electronics and Drive Systems (PEDS) (2009), pp. 752–757 14. S.M. Dehghan, M. Mohamadian, A.Y. Varjani, A new variable-speed wind energy conversion system using permanent-magnet synchronous generator and Z-Source inverter. IEEE Trans. Energy Convers. 24(3), 714–724 (2009)

68

3 Developments of Impedance Source Inverters

15. U. Supatti, F.Z. Peng, Z-source inverter with grid connected for wind power system, in Proceedings of the 2009 IEEE Energy Conversion Congress and Exposition (ECCE) (2009), pp. 398–403 16. T. Maity, H. Prasad, V.R. Babu, Study of the suitability of recently proposed quasi Z-source inverter for wind power conversion, in Proceedings of the 2014 International Conference on Renewable Energy Research and Application (ICRERA) (2014), pp. 837–841 17. W.‐T. Franke, M. Mohr, F.W. Fuchs, Comparison of a Z-source inverter and a voltage‐source inverter linked with a DC/DC-boost-converter for wind turbines concerning their efficiency and installed semiconductor power, in Proceedings of the 2008 IEEE Power Electronics Specialists Conference (PESC) (2008), pp. 1814–1820 18. Y. Liu, B. Ge, F.Z. Peng, H. Abu-Rub, A.T. De Almeida, F.J.T.E. Ferreira, Quasi-Z-Source inverter based PMSG wind power generation system, in Proceedings of the 2011 IEEE Energy Conversion Congress and Exposition (ECCE) (2011), pp. 291–297 19. B.K. Ramasamy, A. Palaniappan, S.M. Yakoh, Direct-drive low-speed wind energy conversion system incorporating axial-type permanent magnet generator and Z-source inverter with sensorless maximum power point tracking controller. IET Renew. Power Gener. 7(3), 284–295 (2013) 20. F.Z. Peng, M. Shen, K. Holland, Application of Z-Source inverter for traction drive of fuel cell-battery hybrid electric vehicles. IEEE Trans. Power Electron. 22(3), 1054–1061 (2007) 21. S.M. Dehghan, M. Mohamadian, A. Yazdian, Hybrid electric vehicle based on bidirectional Z-Source nine-switch inverter. IEEE Trans. Veh. Commun. 59(6), 2641–2653 (2010) 22. F. Guo, L. Fu, C. Lin, C. Li, W. Choi, J. Wang, Development of an 85-kW bidirectional quasi-Z-source inverter with DC-Link feed-forward compensation for electric vehicle applications. IEEE Trans. Power Electron. 28(12), 5477–5488 (2013) 23. P. Liu, H.P. Liu, Permanent-magnet synchronous motor drive system for electric vehicles using bidirectional Z-source inverter. IET Electrical Systems in Transportation 2(4), 178–185 (2012) 24. Q. Lei, D. Cao, F.Z. Peng, Novel loss and harmonic minimized vector modulation for a current-fed quasi-Z-source inverter in HEV motor drive application. IEEE Trans. Power Electron. 29(3), 1344–1357 (2014) 25. F.Z. Peng, Z-source inverter. IEEE Trans. Ind. Applicat. 39(2), 504–510 (2003) 26. J. Rabkowski, The bidirectional Z-source inverter for energy storage application, in Proceedings of the European Conference on Power Electronics and Applications, pp. 1– 10, 2–5 Sept 2007 27. M. Shen, F.Z. Peng, Operation modes and characteristics of the Z-source inverter with small inductance or low power factor. IEEE Trans. Ind. Electron. 55(1), 89–96 (2008) 28. Y. Tang, S. Xie, C. Zhang, Z. Xu, Improved Z-source inverter with reduced Z-source capacitor voltage stress and soft-start capability. IEEE Trans. Power Electron. 24(2), 409–415 (2009) 29. L. Yang, D. Qiu, B. Zhang, G. Zhang, A high-performance Z-source inverter with low capacitor voltage stress and small inductance, in Proceedings of the 29th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 2331–2337, 16–20 Mar 2014 30. J. Wei, Y. Tang, S. Xie, Grid-connected PV system based on the series Z-source inverter, in Proceedings of the 5th IEEE Conference on Industrial Electronics and Applications, ICIEA (2010), pp. 532–537 31. Y. Zhu, M. Chen, X. Lee, Y. Tsutomu, A novel quasi-resonant soft-switching Z-source inverter, in Proceedings of the IEEE International Conference on Power and Energy (PECon), pp. 292–297, 2–5 Dec 2012 32. A.S. Khlebnikov, S.A. Kharitonov, Application of the Z-source converter for aircraft power generation systems, in Proceedings of the 9th International Workshop and Tutorials on Electron Devices and Materials, EDM, pp. 211–215, 1–5 July 2008

References

69

33. E.C. dos Santos, J.H.G. Muniz, E.P.X.P. Filho, E.R.C. Da Silva, Dc-ac three-phase fourwire Z-source converter with hybrid PWM strategy, in Proceedings of the 36th Annual Conference on IEEE Industrial Electronics Society, IECON, pp. 409–414, 7–10 Nov 2010 34. A.S. Khlebnikov, S.A. Kharitonov, P.A. Bachurin, A.V. Geist, D.V. Makarov, Modeling of dual Z-source inverter for aircraft power generation, in Proceedings of the International Conference and Seminar of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), pp. 373–376, 30 June 2011–4 July 2011 35. P.A. Bachurin, D.V. Makarov, A.V. Geist, M.V. Balagurov, D.A. Shtein, Z-source inverter with neutral point, in Proceedings of the 14th International Conference of Young Specialists on Micro/Nanotechnologies and Electron Devices (EDM), pp. 255–258, 1–5 July 2013 36. V. Erginer, M.H. Sarul, Modified reduced common mode current modulation techniques for Z-Source inverter used in photovoltaic systems, in Proceedings of the 4th Power Electronics, Drive Systems and Technologies Conference (PEDSTC), pp. 459–464, 13–14 Feb 2013 37. P.E.P. Ferraz, F. Bradaschia, M.C. Cavalcanti, F.A.S. Neves, G.M.S. Azevedo, A modified Z-source inverter topology for stable operation of transformerless photovoltaic systems with reduced leakage currents, in Proceedings of the 2011 Brazilian Power Electronics Conference (COBEP), pp. 615–622, 11–15 Sept 2011 38. J. Anderson, F.Z. Peng, Four quasi-Z-Source inverters, 2008 IEEE Power Electronics Specialists Conference, Rhodes (2008), pp. 2743–2749 39. S. Jiang, F.Z. Peng, Transmission-line theory based distributed Z-source networks for power conversion, in Proceedings of the 26th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 1138–1145, 6–11 Mar 2011 40. F. Gao, P.C. Loh, F. Blaabjerg, C.J. Gajanayake, Operational analysis and comparative evaluation of embedded Z-Source inverters, in Proceedings of the IEEE Power Electronics Specialists Conference, PESC, pp. 2757–2763, 15–19 June 2008 41. M. Zhu, K. Yu, F.L. Luo, Switched inductor Z-source inverter. IEEE Trans. Power Electron. 25(8), 2150–2158 (2010) 42. A.-V. Ho, T.-W. Chun, H.-G. Kim, Extended boost active-switched-capacitor/ switched-inductor quasi-z-source inverters. IEEE Trans. Power Electron. 30(10), 5681– 5690 (2015) 43. M. Zhu, K. Yu, F.L. Luo, Topology analysis of a switched-inductor Z-source inverter, in Proceedings of the 5th IEEE Conference on Industrial Electronics and Applications, pp. 364– 369, 15–17 June 2010 44. M. Ismeil, M. Orabi, R. Kennel, O. Ellabban, H. Abu-Rub, Experimental studies on a three phase improved switched Z-source inverter, in Proceedings of the Applied Power Electronics Conference and Exposition, APEC, pp. 1248–1254, 16–20 Mar 2014 45. M.-K. Nguyen, Y.-C. Lim, G.-B. Cho, Switched-inductor quasi-Z-source inverter. IEEE Trans. Power Electron. 26(11), 3183–3191 (2011) 46. K. Deng, J. Zheng, J. Mei, Novel switched inductor quasi-Z-source inverter. J. Power Electron. 14(1), 11–21 (2014) 47. F. Ahmed, H. Cha, S. Kim, H. Kim, Switched-coupled-inductor quasi-Z-source inverter. IEEE Trans. Power Electron. 31(2), 1241–1254 (2016) 48. A. Ho, T. Chun, H.T. Kim, Extended boost active-switched-capacitor/switched-inductor quasi-Z-source inverters. IEEE Trans. Power Electron. 30(10), 568–5690 (2015) 49. M.-K. Nguyen, Y.-C. Lim, J.-H. Choi, Two switched-inductor quasi-Z-source inverters. IET Power Electron. 5(7), 1017–1025 (2012) 50. K. Deng, F. Mei, J. Mei, J. Zheng, G. Fu, An extended switched-inductor quasi-Z-source inverter. J. Electr. Eng. Technol. 9(2), 541–549 (2014) 51. M. Zhu, D. Li, P.C. Loh, F. Blaabjerg, Tapped-inductor Z-Source inverters with enhanced voltage boost inversion abilities, in Proceedings of the 2nd IEEE International Conference on Sustainable Energy Technologies, ICSET, pp. 1–6, 6–9 Dec 2010 52. Y. Zhou, W. Huang, J. Zhao, P. Zhao, Tapped inductor quasi-Z-source inverter, in Proceedings of the 27th Annual IEEE Applied Power Electronics Conference and Exposition (APEC), pp. 1625–1630, 5–9 Feb 2012

70

3 Developments of Impedance Source Inverters

53. C.J. Gajanayake, F.-L. Luo, H.B. Gooi, P.L. So, L.K. Siow, Extended-boost Z-source inverters. IEEE Trans. Power Electron. 25(10), 2642–2652 (2010) 54. D. Vinnikov, I. Roasto, T. Jalakas, R. Strzelecki, M. Adamowicz, Analytical comparison between capacitor assisted and diode assisted cascaded quasi-Z-source inverters. Electr. Rev. 88(1a), 212–217 (2012) 55. D. Vinnikov, I. Roasto, T. Jalakas, S. Ott, Extended boost quasi-Z-source inverters: possibilities and challenges. Electron. Elect. Eng. 112(6), 51–56 (2011) 56. Y.P. Siwakoti, F.Z. Peng, F. Blaabjerg, P.C. Loh, G.E. Town, Impedance-source networks for electric power conversion Part I: a topological review. IEEE Trans. Power Electron. 30(2), 699–716 (2015) 57. M. Adamowicz, N. Strzelecka, T-source inverter. Electr. Rev. 85(10), 233–238 (2009) 58. W. Qian, F.-Z. Peng, H. Cha, Trans-Zsource inverters. IEEE Trans. Power Electron. 26(12), 3453–3463 (2011) 59. M.-K. Nguyen, Y.-C. Lim, S.-J. Park, Improved trans-Z-source inverter with continuous input current and boost inversion capability. IEEE Trans. Power Electron. 28(10), 4500–4510 (2013) 60. M.-K. Nguyen, Y.-C. Lim, Y.-G. Kim, TZ-source inverters. IEEE Trans. Ind. Electron. 60 (12), 5686–5695 (2013) 61. M. Adamowicz, LCCT-z-source inverters, in Proceedings of the EEEIC (2011), pp. 1–16 62. P.C. Loh, D. Li, F. Blaabjerg, Г-Z-source inverters. IEEE Trans. Power Electron. 28(11), 4880–4884 (2013) 63. Y.P. Siwakoti, P.C. Loh, F. Blaabjerg, G.E. Town, Y-source impedance network. IEEE Trans. Power Electron. 29(7), 3250–3254 (2014) 64. R.R. Ahrabi, M.R. Banaei, Improved Y-source DC–AC converter with continuous input current. IET Power Electron. 9(4), 801–808 (2016) 65. P.C. Loh, F. Blaabjerg, C.P. Wong, Comparative evaluation of pulse width modulation strategies for Z-source neutral-point-clamped inverter. IEEE Trans. Power Electron. 22(3), 1005–1013 (2007) 66. P.C. Loh, S.W. Lim, F. Gao, F. Blaabjerg, Three-level Z-source inverters using a single LC impedance network. IEEE Trans. Power Electron. 22(2), 706–711 (2007) 67. O. Husev, C. Roncero-Clemente, E. Romero-Cadaval, D. Vinnikov, S. Stepenko, Single phase three-level neutral-point-clamped quasi-Z-source inverter. IET Power Electron. 8(1), 1– 10 (2015) 68. W. Mo, P.C. Loh, F. Blaabjerg, P. Wang, Trans-Z-source and C-Z-source neutral-pointclamped inverters. IET Power Electron. 8(3), 371–377 (2015) 69. F. Gao, P.C. Loh, F. Blaabjerg, R. Teodorescu, D.M. Vilathgamuwa, Five-level Z-source diode-clamped inverter. IET Power Electron. 3(4), 500–510 (2010) 70. B.K. Chaithanya, A. Kirubakaran, A novel four level cascaded Z-source inverter, in Proceedings of the IEEE International Conference on Power Electronics, Drives and Energy Systems (PEDES), pp. 1–5, 16–19 Dec 2014 71. Y. Liu, B. Ge, H. Abu-Rub, F.Z. Peng, An effective control method for quasi-Z-source cascade multilevel inverter-based grid-tie single phase photovoltaic power system. IEEE Trans. Ind. Inform. 10(1), 399–407 (2014) 72. S.M. Dehghan, M. Mohamadian, A. Yazdian, Hybrid electric vehicle based on bidirectional Z-source nine-switch inverter. IEEE Trans. Veh. Technol. 59(6), 2641–2653 (2010) 73. S.M. Dehghan, M. Mohamadian, A. Yazdian, F. Ashrafzadeh, A dual-input-dual-output Z-source inverter. IEEE Trans. Power Electron. 25(2), 360–368 (2010) 74. S. Jiang, D. Cao, F.Z. Peng, High frequency transformer isolated Z-source inverters, in Proceedings of the 26th Annual IEEE Applied Power Electronics Conference and Exposition (APEC) 2011, pp. 442–449

References

71

75. L. Pan, L-Z-source inverter. IEEE Trans. Power Electron. 29(12), 6534–6543 (2014) 76. H. Liu et al., Extended quasi-Y-source inverter with suppressed inrush and leakage effects. IET Power Electron. 12(4), 719–728 (2019) 77. H. Liu et al., High Step-Up Y-Source inverter with reduced DC-Link voltage spikes. IEEE Trans. Power Electron. 34(6), 5487–5499 (2019) 78. H. Liu, Y. Li, Z. Zhou, W. Wang, D. Xu, A Family of Low-Spike High-Efficiency Y-Source Inverters. IEEE Trans. Industr. Electron. 66(12), 9288–9300 (2019)

Chapter 4

Dual-Winding Impedance Source Inverters

Abstract The coupled inductors Z-source inverters (CISIs) can be divided into dual-winding impedance source inverters and three-winding impedance source inverters in general, where the dual-winding impedance source inverter could be subdivided into T-source inverter (TSI) [1], trans-quasi-Z-source inverter (trans-QZSI) [3], improved trans-QZSI [4], transformer quasi-ZSI (TQZSI) [5], inductor–capacitor–capacitor–transformer ZSI (LCCT-ZSI) [6], and Г-source inverter (ГSI) [7]. This chapter will present each dual-winding impedance source inverter in detail.

4.1

T-Source Inverter

Magnetically coupled inductors and transformers find a niche in impedance networks to improve the voltage boost capability, as well as the modulation index. In addition, they reduce the number of passive components needed in the network, which improves the power density and reduces the cost of the system [1]. The T-source inverter (TSI) is one modified form of the basic ZSI topology, which is achieved by reducing the size of the Z-network [2]. The two inductors are built together on one core to form a coupled inductor (or transformer) with low leakage inductance. Instead of having two capacitors, only one capacitor is used in the TSI. In addition, the TSI has a common dc rail used between the dc source and the inverter bridge. Furthermore, the most significant advantage of the TSI is the extended possibility of manipulation of inverter output voltage and ST duty ratio using a transformer turns ratio greater than one and reducing the voltage stress on the inverter switches. Figure 4.1 shows the topology of TSI, while the operation modes of TSI are displayed in Fig. 4.2. Similarly with the z-source inverter (ZSI), the operation modes of TSI are also divided into shoot-through (ST) state and non-shoot-through (NST) state. The TSI governing equations can be developed for the Fig. 4.2 using Kirchhoff’s laws and voltage averaging. The average voltage through the coupled © Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_4

73

74

4 Dual-Winding Impedance Source Inverters

N2 S1

Vin

C

vdc

va

S6

S3

S5

vb vc S2

S4

Load or grid

N1

Filter

D1

Fig. 4.1 Topology of the T-source inverter

Fig. 4.2 Operation modes of T-source inverter: a shoot-through state and b non-shoot-through state

N1

(a) Vin

N2

C

N1

(b) Vin

C

SW

vdc

Io

N2

SW

vdc

Io

inductances should be equal to zero for the switching time period Ts. Both the capacitor voltage VC and dc-link voltage vdc are functions of the shoot-through duty ratio d = T0/Ts. Then the voltage across capacitor can be expressed as VC ¼

1d Vin 1  Kd

ð4:1Þ

where the winding factor K = (N1 + N2)/N2, and d satisfies a condition d 2 is smaller than for the ZSI and quasi-Z-source inverter (QZSI). From Fig. 4.2 and from (4.1), the amplitude Vdc of the dc-link voltage vdc during NST operational state can be derived.

4.1 T-Source Inverter

75

Vdc ¼

1 Vin 1  Kd

ð4:2Þ

Therefore, the TSI can realize higher voltage gain than ZSI and QZSI by adjusting the winding factor K and ST ratio d.

4.2

Trans-Quasi-Z-Source Inverter

The trans-quasi-Z-source inverter (trans-QZSI) is another modified form of the basic ZSI topology achieved by reducing the size of the Z-network [3]. The trans-QZSIs can be derived from the voltage/current-fed quasi-Z-source inverters or the voltage/current-fed Z-source inverters. The trans-QZSIs inherit their unique features, and they can be controlled using the PWM methods applicable to the Z-source inverters. Figure 4.3 illustrates the voltage-fed trans-QZSI, while the current-fed trans-QZSI is displayed in Fig. 4.4. As the analysis of last chapter, the voltage-fed source inverters are widely applied since the voltage control is simpler to realize. Therefore, the detail analysis of voltage-fed trans-QZSI will be unfolded in the next. With regard to the analysis of current-fed trans-QZSI, similar results of current-fed trans-QZSI could be obtained. The operational modes of the trans-QZSI can also be divided into ST state and NST state as shown in Fig. 4.5, from which the following equations could be derived: VC ¼

ðK  1Þd Vin 1  Kd

ð4:3Þ

1 Vin 1  Kd

ð4:4Þ

Vdc ¼

C N2 S1 Vin vdc

va

S6

S3

S5

vb S4

vc S2

Fig. 4.3 Topology of the voltage-fed trans-quasi-Z-source inverter

Load or grid

N1

Filter

D1

76

4 Dual-Winding Impedance Source Inverters

L

S3

N1 C

D1 va vdc D 1 S6

D3 vb S4

v S2 c

D6

D4

D2

D5

Load or grid

Vin

S5 Filter

S1 N2

Fig. 4.4 Topology of the current-fed trans-quasi-Z-source inverter

(a)

(b)

C N1

Vin

C N1

N2

SW

vdc

Io

Vin

N2

SW

vdc

Io

Fig. 4.5 Operation modes of voltage-fed trans-quasi-Z-source inverter: a shoot-through state and b non-shoot-through state

where the winding factor K and ST duty ratio d is the same as those of TSI. Compared with the voltage across capacitor between TSI and trans-QZSI, i.e., Eqs. (4.1) and (4.3), the capacitor voltage stress of trans-QZSI is smaller than that of TSI. However, there is a large current flowing to the main circuit at startup, which might damage the components of circuit. Thus, a novel impedance source inverter was proposed to overcome the drawback of trans-QZSI, i.e., the improved trans-QZSI inverter that will be presented in the next section.

4.3

Improved Trans-Quasi-Z-Source Inverter

Figure 4.6 shows an improved trans-QZSI with continuous input current and high boost-inversion capability. It consists of one inductor (L3), one transformer, two capacitors (C1 and C2), and one diode (D). The main characteristics are as follows: the input dc current is continuous with lower ripples and lower current stress flow on the transformer windings and input diode compared with the trans-QZSI topology; it provides resonant current suppression, unlike the trans-QZSI topology in Fig. 4.3, because no current flows to the main circuit at startup and only one inductor and one capacitor are added, and a higher boost factor can be obtained [4].

4.3 Improved Trans-Quasi-Z-Source Inverter

77

C2

N1

N2

Vin

C1

vdc

S5

S3

S1

va

vb

S6

vc S2

S4

Load or grid

D1

Filter

Lin

Fig. 4.6 Topology of improved trans-quasi-Z-source inverter

(a)

C2 Lin

Vin

N1

C1

(b) N2

C2 Lin

SW

vdc

Io

Vin

N1

C1

N2

SW

vdc

Io

Fig. 4.7 Operation modes of improved trans-quasi-Z-source inverter: a shoot-through state and b non-shoot-through state

Analogy to the analysis of TSI and trans-QZSI, the improved trans-QZSI can also be equivalent to ST state and NST state. As shown in Fig. 4.7, the inverter bridge and AC load are still equivalent to one switch and one constant current either in the ST state or NST state. In the ST state, the diode D1 is block while the equivalent switch is closed. The equivalent switch is block and diode is conduct when the improved trans-QZSI turns into the NST state. Using Kirchhoff’s laws and voltage averaging, then the voltage across capacitors can be expressed as VC1 ¼

1d Vin 1  ð1 þ KÞd

ð4:5Þ

VC2 ¼

Kd Vin 1  ð1 þ KÞd

ð4:6Þ

From Fig. 4.7 and expressions of capacitor voltages, the amplitude Vdc of the dc-link voltage vdc during NST operational state can be obtained

78

4 Dual-Winding Impedance Source Inverters

Vdc ¼

1 Vin 1  ð1 þ KÞd

ð4:7Þ

where the winding factor K and ST ratio d is still the same as those of TSI.

4.4

Transformer Quasi-Z-Source Inverter

By replacing two inductors in the classical ZSI topology with two transformers, the transformer ZSI (TZSI) produces a very high boost voltage gain when the turns ratio of the transformers is larger than one. Compared to the trans-ZSI, the TZSI uses a lower transformer turns ratio, which reduces the transformer size and weight, while producing the same output voltage gain. This occurs because the power rating and turn ratio of each transformer in the TZSI are smaller than those of the transformer in the trans-ZSI under the same output power and voltage gain conditions; Fig. 4.8 shows the transformer QZSI (TQZSI) topology [5].

4.5

Inductor–Capacitor–Capacitor–Transformer ZSI

Figure 4.9 shows an inductor–capacitor–capacitor–transformer ZSI (LCCT-ZSI) using one more inductor and one more capacitor in comparison with the trans-ZSI/ trans-QZSI and having the same component count compared to the improved trans-QZSI [6]. The unique property of the LCCT-ZSI is that no energy is stored in the transformer windings. The two dc-current blocking capacitors connected in series with the transformer also prevent the transformer core from saturation.

C2

D1

N21

N22 S1

Vin

C1

vdc

va

S6

S3

S5

vb S4

Fig. 4.8 Topology of improved trans-quasi-Z-source inverter

vc S2

Load or grid

N12

Filter

N11

4.6 C-Source Inverter

79

C2

N1 S1

Vin

N2 C1

vdc

va

S6

S3

S5

vb S4

vc S2

Load or grid

D1

Filter

Lin

Fig. 4.9 Topology of inductor–capacitor–capacitor–transformer Z-source inverter

4.6

C-Source Inverter

The gamma-ZSI (C-ZSI), as shown in Fig. 4.10, uses a unique C-shaped impedance network, composed of a transformer and capacitor, for boosting the output voltage and producing flexible enhanced voltage gain. However, it has a discontinuous input current [7]. The asymmetrical C-ZSI (Asym-C-ZSI), shown in Fig. 4.11, has a continuous input current and uses one coupled transformer, one inductor, and two capacitors, which are the same as the improved trans-QZSI [8]. Unlike other transformer-based topologies, the voltage gain of both C-ZSI and Asym-C-ZSI is raised by lowering their transformer turns ratio rather than increasing it. The Asym-C-ZSI is more widely applied due to the continuous input current and enhanced boost capability. It is achieved by adjusting the turns ratio nC of a coupled transformer. Unlike earlier transformer-coupled topologies though, the gain here is raised by lowering nC within the narrowed range of 1 < nC  2. Their winding turn requirement is thus lower, while yet preserving all other favorable features of a transformer-coupled Z-source inverter.

N1

Vin

N2 vdc

C

va

S6

Fig. 4.10 Topology of gamma-Z-source inverter

S3

S5

vb S4

vc S2

Load or grid

S1

Filter

D1

80

4 Dual-Winding Impedance Source Inverters

C2 N1 S3

S1 N2

Vin

vdc C1

va

S5

vb

S6

S4

vc S2

Load or grid

D1

Filter

Lin

Fig. 4.11 Topology of asymmetrical gamma-Z-source inverter

4.7

Summary

This chapter introduces several two-winding impedance source inverters, such as T-source inverter (TSI), trans-quasi-Z-source inverter (trans-QZSI), improved trans-QZSI, transformer quasi-ZSI (TQZSI), inductor–capacitor–capacitor–transformer ZSI (LCCT-ZSI), and Г-source inverter (ГSI). They are all can boost voltage higher based on the classical ZSI. Besides, the density of impedance source inverters is larger than the switched components impedance source inverters or cascaded quasi-Z-source inverters that can also enhance the voltage of ZSI. Table 4.1 summarizes the basic characteristics of TSI and trans-QZSI compared with ZSI, while the comparison of trans-QZSI, improved trans-QZSI, and TQZSI is presented in Table 4.2. Besides, Table 4.3 illustrates the differences between LCCT-ZSI, ГSI, and Asym-C-ZSI. The boost factors, number of elements in impedance network, and other features of two-winding impedance source inverters are displayed systematically in Tables 4.1, 4.2 and 4.3, where the winding factor

Table 4.1 Basic characteristics of TSI and trans-QZSI compared with ZSI Characteristic

ZSI

TSI

Trans-QZSI

Boost factor Number of elements

1/(1−2d) Two inductors

1/(1−Kd) One coupled inductor One capacitor

1/(1−Kd) One coupled inductor One capacitor

One diode No

One diode Yes

Yes Yes

Yes Yes

Continuous input current Startup inrush current Common earthing

Two capacitors One diode No Yes No

4.7 Summary

81

Table 4.2 Comparison of trans-QZSI, improved trans-QZSI, and TQZSI Characteristic

Trans-QZSI

Improved trans-QZSI

TQZSI

Boost factor Number of elements

1/(1−Kd) One coupled inductor One capacitor One diode

1/(1−(K1 + K2)d) Two coupled inductors Two capacitors One diode

Continuous input current Startup inrush current Common earthing

Yes, but high rippled Yes Yes

1/(1−(1 + K)d) One coupled inductor One inductor Two capacitors One diode Yes No Yes

No Yes

Yes

Table 4.3 Differences between LCCT-ZSI, ГSI, and Asym-C-ZSI Characteristic

LCCT-ZSI

ГSI

Asym-C-ZSI

Boost factor

1/(1−Kd)

Number of elements

One coupled inductor One inductor Two capacitors One diode Yes

1/(1−(1 + (1/(K−1) −1)d)) One coupled inductor

1/(1−(2 + (1/(K−1) −1)d)) One coupled inductor

One capacitor One diode No

One inductor Two capacitors One diode Yes

No

Yes

No

Yes

Yes

Yes

Continuous input current Startup inrush current Common earthing

K = (N1 + N2)/N2 and ST duty ratio d = T0/Ts. Especially, as for the winding factors of TQZSI, K1 = (N11 + N12)/N12, K2 = (N21 + N22)/N22. As shown in the tables, the boost factors of all the two-winding impedance source inverters are bigger than ZSI as the winding factor K of coupled inductor is always larger than one. Compared with ZSI, TSI reduces nearly half of components and realizes common earthing. And the trans-QZSI further achieves continuous input current based on the TSI. The improved trans-QZSI inherits the features of trans-QZSI and suppresses the startup inrush current by adding extra one inductor and one capacitor. Besides, the TQZSI is developed from QZSI by replacing the inductors by coupled inductors. The TQZSI can enhance the gain of impedance source inverter flexibly as two coupled inductors are adopted. The basic characteristic of LCCT-ZSI and improved trans-QZSI is similar; they can obtain the same voltage gain with the same number of elements. Moreover, they can suppress the startup inrush current and have continuous input current and

82

4 Dual-Winding Impedance Source Inverters

common earthing. However, the voltage gain of the Asym-C-ZSI that also has the same number of elements and current characteristic is different from improved trans-QZSI and LCCT-ZSI. Besides, the voltage gain of Asym-C-ZSI is raised by lowering their transformer turns ratio rather than increasing it.

References 1. Y.P. Siwakoti, F.Z. Peng, F. Blaabjerg, P.C. Loh, G.E. Town, Impedance-source networks for electric power conversion Part I: a topological review. IEEE Trans. Power Electron. 30(2), 699–716 (2015) 2. M. Adamowicz, N. Strzelecka, T-source inverter. Electr. Rev. 85(10), 233–238 (2009) 3. W. Qian, F.-Z. Peng, H. Cha, Trans-Zsource inverters. IEEE Trans. Power Electron. 26(12), 3453–3463 (2011) 4. M.-K. Nguyen, Y.-C. Lim, S.-J. Park, Improved trans-Z-source inverter with continuous input current and boost inversion capability. IEEE Trans. Power Electron. 28(10), 4500–4510 (2013) 5. M.-K. Nguyen, Y.-C. Lim, Y.-G. Kim, TZ-source inverters. IEEE Trans. Ind. Electron. 60(12), 5686–5695 (2013) 6. M. Adamowicz, LCCT-Z-source inverters, in Proceedings of the EEEIC (2011), pp. 1–16 7. P.C. Loh, D. Li, F. Blaabjerg, Г-Z-source inverters. IEEE Trans. Power Electron. 28(11), 4880–4884 (2013) 8. W. Mo, P.C. Loh, F. Blaabjerg, Asymmetrical-source inverters. IEEE Trans. Ind. Electron. 61 (2), 637–647 (2014)

Chapter 5

Three-Winding Impedance Source Inverter

Abstract The coupled inductors Z-source inverters (CISIs) can be divided into dual-winding impedance source inverters and three-winding impedance source inverters in general, where the three-winding impedance source inverter could be subdivided into Y-source inverter (YSI) [5], improved Y-source inverter (IYSI) [6], extend quasi-Y-source inverter (E-QYSI) [9], modified Y-source inverter (M-YSI) [15], and so on. This chapter will present these four three-winding impedance source inverters in detail.

5.1

Y-Source Inverter

In order to make the impedance source inverter viable in more types of energy, the T-source inverter (TSI), inductor–capacitor–capacitor–transformer ZSI (LCCT-ZSI), and Г-source inverter (ГSI) presented in the last chapter can achieve higher voltage gain using a coupled inductor with two windings. They differ only in their winding placements which, although simple rearrangements, can lead to different winding requirements. Each of these networks has its own characteristic features, which might at times be helpful depending on the application under consideration [1–3]. It is thus not fair to favor any particular networks, but more appropriate to look for an alternative that can merge all the preferred characteristics. To achieve that, a unique Y-source impedance network is proposed in [4] to realize a very high gain DC–DC converter. The same Y-source impedance network is implemented to realize a very high gain three-phase inverter as shown in Fig. 5.1, whose versatility is demonstrated by implementing different winding factors, turns ratios, and ranges of shoot-through (ST) duty ratio to achieve a higher modulation index [5]. The Y-source inverter (YSI) consists of a Y-source network on the input side, a three-phase bridge inverter, and a filter at the output stage. The Y-source impedance network in its elementary form consists of a passive diode D1 a capacitor C, and, most importantly, a three-winding transformer (N1, N2, N3) for introducing a high boost at a small duty ratio. As the transformer is connected directly to the inverter

© Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_5

83

84

5 Three-Winding Impedance Source Inverter

D1 N3

N1

vdc

N2

va

S6

C

vb vc S2

S4

Load or grid

Vin

S5

S3

Filter

S1

Fig. 5.1 Topology of Y-source inverter

Fig. 5.2 Operation modes of Y-source inverter: a shoot-through state and b non-shoot-through state

(a) N3

N1

Vin

SW

N2

vdc

Io

C

(b) N3

N1

Vin

SW N2

vdc

Io

C

bridge and D1 its coupling must be tight to minimize leakage inductances seen at its windings. This can be done by following the winding style associated with a bifilar coil. Like a traditional impedance source inverter, the Y-source inverter has an extra ST state and non-shoot-through (NST) state that consists of six active states and two zero states. The ST state can be achieved by short-circuiting both the upper and lower switching devices of any/all phase leg(s) of the inverter. By ensuring that, the equivalent circuit during the ST across the inverter bridge is shown in Fig. 5.2a and can be written as (5.1), where n12 = N1/N2 and n13 = N1/N3 are the turns ratios of the transformer. The diode D1 is open circuit in this interval: VC þ vL =n12  vL =n13 ¼ 0

ð5:1Þ

which also means vL ¼

n12 n13 VC n12  n13

ð5:2Þ

5.1 Y-Source Inverter

85

On the other hand, during any NST state interval, diode D1 is conducting and the inverter bridge is modeled as an equivalent current source, as shown in Fig. 5.2b; the circuit expressions change to (5.3) VC þ vL =n12 þ vL ¼ Vin

ð5:3Þ

n12 ðVin  VC Þ n12 þ 1

ð5:4Þ

which means vL ¼

Performing the Kirchhoff’s laws and voltage averaging, the voltage across the capacitor C can be deduced to be VC ¼

1d Vin 1  Kd

ð5:5Þ

where the winding factor K = (N1 + N3)/(N3 − N2), and the ST duty ratio d = T0/ Ts, which represents the ratio of ST state duration T0 with switching period Ts. Thus, the amplitude Vdc of the dc-link voltage vdc during NST operational state can be derived. Vdc ¼

1 Vin 1  Kd

ð5:6Þ

Hence, the boost factor B of YSI can also be represented as 1/(1 − Kd) similar with that of T-source inverter (TSI). However, the expression of winding factor K is different. The winding factor of YSI is determined by three parameters (N1, N2, N3), while that of TSI is depended on only N1 and N2. Therefore, the freedom of adjusting boost factor is increased than TSI.

5.2

Improved Y-Source Inverter

The design freedom of YSI is increased. Hence, this topology is a suitable inverter in different applications. It has higher voltage gain, smaller size and it also utilizes smaller number of elements. The only drawback of this structure is discrete input current that is not proper in some applications. Therefore, an improved Y-source inverter (IYSI) is proposed in [6]. The input current of the proposed Y-source inverter is continuous; hence, the oscillation of the current is decreased which results in circuit elements with smaller size. IYSI introduces an appropriate structure for practical uses. It is worth mentioning that the output voltage gain of the IYSI is increased in comparison with conventional YSI.

86

5 Three-Winding Impedance Source Inverter

Figure 5.3 illustrates the topology of IYSI, which consists of two capacitors (C1, C2), one diode, and four inductors Lin , N1, N2, and N3. N1, N2, and N3 use common core as coupled inductor. Lin is used at the input side of the converter in order to provide continuous input current. The IYSI has three improvements as follows: (1) continuous input current; (2) suppressing startup inrush current; (3) higher voltage gain in comparison with YSI. Similarly with the operational mode of YSI, the IYSI can also be equivalent to ST state and NST state. As shown in Fig. 5.4, the inverter bridge and AC load are still equivalent to one switch and one constant current either in the ST state or NST state. Besides, the coupled inductor is equivalent to a finite magnetizing inductance LM and one winding N1 of three-winding ideal transformer in parallel. C2 D1

Vin

N3

N1

vdc

N2

va

S6

C1

S5

S3

vb vc S2

S4

Load or grid

S1

Filter

Lin

Fig. 5.3 Topology of improved Y-source inverter

Fig. 5.4 Operation modes of improved Y-source inverter: a shoot-through state and b non-shoot-through state

(a)

C2 Lin

Vin

LM

N3

N1

SW N2

vdc

Io

C1

(b)

Vin

C2 Lin

LM

N3

N1

SW N2 C1

vdc

Io

5.2 Improved Y-Source Inverter

87

As depicted in Fig. 5.1a, the diode is not conducting during ST time interval. The inverter side is short-circuited by connecting both of the upper and lower power switches in one of the legs of the inverter. These results are obtained in the following equations, where n21 = N2/N1 and n31 = N3/N1: VC1 n31  n21

ð5:7Þ

VLin ¼ VC2 þ Vin

ð5:8Þ

VLm ¼

In the non-shoot-through state, at time interval (1 − d)Ts, the diode is conducted and inverter side is in the active state as it is shown in Fig. 5.4b. According to this figure, we have VLm ¼

VC1  Vdc n31  n21

VLin ¼ VC2 þ Vin  Vdc VLm ¼ 

VC2 1 þ n31

ð5:9Þ ð5:10Þ ð5:11Þ

By applying the volt-second balance principle to inductors Lm and Lin , the following equations are obtained VC1 ¼

1d Vin 1  ð1 þ KÞd

ð5:12Þ

VC2 ¼

Kd Vin 1  ð1 þ KÞd

ð5:13Þ

Vdc ¼

1 Vin 1  ð1 þ KÞd

ð5:14Þ

where the winding factor K = (N1 + N3)/(N3 − N2) and the ST duty ratio d = T0/Ts are all same as the parameters of YSI. Hence, the boost factor B of IYSI is higher than that of YSI.

5.3

Extended Quasi-Y-Source Inverter

Like other inverters with two windings, the YSI can achieve a high gain with only a small control ST duty ratio. But, with two turns ratios from three windings, it has a greater design flexibility. Despite that, it inherits some common disadvantages from other impedance source inverters, such as its discontinuous input current and large

88

5 Three-Winding Impedance Source Inverter

startup inrush current. Other disadvantages associated with the magnetically coupled inverters, such as large DC-link voltage spikes and losses of duty ratio caused by non-negligible leakage inductances [7], are also experienced by the YSI. The discontinuous input current and large startup inrush current can be removed by adding inductors and/or capacitors for filtering. The quasi-Y-source inverter (QYSI) adopts this method by adding Lin and C2 to the original Y-source inverter with a three-winding coupled inductor (N1, N2, and N3) [8]. However, the boost ratio of QYSI is the same with that of YSI. Therefore, the adding passive components (Lin and C2) make no contribution to the boost ability. An extended quasi-YSI (E-QYSI) has thus been proposed in [9] for ensuring a continuous input current, an acceptable startup inrush current, overall small magnetic core size, high boost ratio, and low voltage spikes, while inheriting all the advantages of the YSI and QYSI. More importantly, influences from leakage inductances have been significantly suppressed, yielding smaller DC-link voltage spikes and more accurate duty ratios. A schematic of the E-QYSI has been drawn in Fig. 5.5, where the three-winding coupled inductor and capacitor C1 of the YSI have been retained. However, the positions of N2 and N3 have been swapped. Other differences are the addition of an inductor Lin and a capacitor C2 to the E-QYSI, and the relocation of its diode D1. These features have also made the proposed E-QYSI different from the IYSI shown in Fig. 5.3, even though they use the same components and draw comparable continuous input currents.

5.3.1

Startup Current Suppression

With the YSI shown in Fig. 5.1, its startup inrush currents through the diode D1, windings N1 and N2, and capacitor C may be large. The explanation for it can be obtained by expressing the DC-link voltage Vdc across each phase leg with two switches as Vdc ¼ VC1 þ VN2  VN3

C2

Vin

N2

N1 N3

D1 C1

vdc

va

S6

S3

S5

vb S4

Fig. 5.5 Schematic of the extended quasi-Y-source inverter

vc S2

Load or grid

S1

Filter

Lin

ð5:15Þ

5.3 Extended Quasi-Y-Source Inverter

89

where VN2 and VN3 are the voltages across windings N2 and N3, and VC1 is the voltage across capacitor C1, whose initial value is zero. Moreover, the windings must be designed such that N3 > N2 or VN3 > VN2 > 0 [4], whose accompanied effect is a negative DC-link voltage at startup. In turn, this negative voltage causes a large inrush current to flow around the loop formed by antiparallel diodes of the switches, the windings N3 and N2, and capacitor C. Through magnetic induction, an equally large transformed current will then be drawn from the input source, and it will flow through the diode D1, windings N1 and N2, and capacitor C. The startup inrush current will however be greatly reduced by the inductor Lin of the E-QYSI as shown in Fig. 5.5. It will now flow from the input source through inductor Lin and diode D1 to charge the capacitor C1. Meanwhile, currents through the windings of the coupled inductor will almost be zero, because of the bypass introduced by the conducting diode D1. Startup inrush currents from the source and through all components of the E-QYSI will hence be significantly reduced.

5.3.2

Operational States

After startup, the E-QYSI in Fig. 5.5 also operates in two states, named as ST state and NST state. The former is caused by the simultaneous turn-ON of two switches from the same phase leg, which in Fig. 5.6a is represented by the turn-ON of the equivalent switch SW. During that time, diode D1 becomes reverse-biased, while the input source and capacitors begin to charge the inductors. To be specific, capacitor C1 starts to charge windings N2 and N3 through the shorted SW, while capacitor C2 and input source charge input inductor Lin, and windings N1 and N2 through the same shorted SW. Currents through the windings and input inductor therefore increase linearly. Simultaneously, relevant voltage expressions can also be written as VC1 ¼ vN1 =n12  vN1 =n13

ð5:16Þ

Vin ¼ VC1 þ vN1 þ vN1 =n13  VC2 þ vLin

ð5:17Þ

where n12 is the ratio of N1 to N2, and n13 is the ratio of N1 to N3. On the other hand, when only one switch per phase leg is ON, the NST state is entered, which in Fig. 5.6b is represented by the opening of the equivalent switch SW. That causes the diode D1 to conduct and hence permits input inductor Lin and source to recharge capacitor C1 through diode D1. The winding inductor N1 and N3 charge the capacitor C2. Since the load now “sees” more voltages in series, it experiences an overall voltage boost, governed by the following:

90

5 Three-Winding Impedance Source Inverter

Fig. 5.6 Voltage gains of different YSIs versus duty cycle

0

0

VC2 ¼ vN1 =n13 þ vN1 0

0

Vdc ¼ VC1 þ vN1 =n13  vN1 =n12 0

Vin ¼ VC1 þ vLin

ð5:18Þ ð5:19Þ ð5:20Þ

By next considering the volt-sec balance of winding N1 using (5.16) and (5.18), the voltage across C2 can be calculated as VC2 ¼

N3 VC1  NN13 þ N2 d

1d

¼

VC1  Kd 1d

ð5:21Þ

where d and K denote duty ratio of the ST state and winding factor, respectively. From (5.16) and (5.19), the dc-link voltage Vdc can also be derived as Vdc ¼

VC1 1d

ð5:22Þ

Moreover, by substituting (5.21) and (5.22) into (5.17) and (5.20), the following boost factor B of the E-QYSI can be derived:

5.3 Extended Quasi-Y-Source Inverter

B¼

91

Vdc 1 ¼ Vin ½1  ðK þ 1Þd

ð5:23Þ

From (5.23), the peak ac output voltage of the E-QYSI can thus be expressed as ^vo ¼ BMVin

ð5:24Þ

Other expressions that can be derived are voltages across C1, C2, and D1. They are listed as follows: VC1 ¼

ð1  dÞVin ½1  ðK þ 1Þd

ð5:25Þ

VC2 ¼

KdVin ½1  ðK þ 1Þd

ð5:26Þ

VD1 ¼ 

KVin ½1  ðK þ 1Þd

ð5:27Þ

These expressions, together with (5.23), have a common denominator, from which tunable ranges for duty ratio d and modulation index M are found as 0  d\dmax ¼ 1=ð1 þ KÞ; 0\M\Mmax ¼ 1  d

ð5:28Þ

The maximum duty ratio and attainable gain are thus both dependent on K. Finally, for comparison, boost factor Bc of the YSI is redefined below: Bc ¼

Vdc 1 ¼ ; ^vo;c ¼ Bc Mc Vin Vin 1  Kc dc

ð5:29Þ

where parameters with a subscript c added are for the YSI. It is thus implicative from (5.23), (5.24), and (5.29) that with the same winding factor and duty ratio, the boost factor of the E-QYSI is higher than that of the YSI. Alternatively, if the same gain is required, the E-QYSI will need a smaller duty ratio than the YSI with the same winding factor. The range of variation for modulation index can hence be widened. Besides, the voltage gains of YSI, QYSI, IYSI, and E-QYSI have been plotted in Fig. 5.6. It can be seen that if the four inverters have the same duty cycle, output voltages of the E-QYSI and IYSI are higher than those of the YSI and QYSI.

92

5.3.3

5 Three-Winding Impedance Source Inverter

Current Ratings and Core Size of Coupled Inductor

Besides, a properly coupled inductor is an essential component in both YSI and E-QYSI. However, its size is a major concern, since other components in the two inverters are usually much smaller. It is thus necessary to consider the magnetizing inductance and winding currents in the coupled inductor, since they determine the overall magnetic core size [10]. Moreover, since the magnetizing inductance is proportional to the square of winding turns, an expression for relating the magnetic core size can be written as Swinding /

3 X

ð5:30Þ

Nj2 i2Nj;rms

j¼1

where Nj is the number of turns of each winding, and iNj;rms is the RMS current flowing through that winding. Additionally, Fig. 5.7 shows the current waveforms flowing through coupled inductors of the YSI and E-QYSI in both ST and NST states. Current expressions for both states can also be derived from features of the inverters, which for the YSI is its input current iin being always equal to its current through winding N1. They will hence have the same average value per switching period, expressed as iN1;ave ¼ iin;ave ¼

P Vin

ð5:31Þ

where P is the average power transferred by the YSI. Using (5.31) and noting that current through winding N1 is zero during the ST state, its value during the NST state can easily be derived as

(a)

(b)

iN1

iN1

iN2

iN3

iN3

iN2 dT

T

t

dT

T

t

Fig. 5.7 Anticipated current waveforms through coupled inductors of a YSI and b E-QYSI

5.3 Extended Quasi-Y-Source Inverter

93

iN1;nst ¼

P Vin ð1  dc Þ

ð5:32Þ

On the other hand, the current through winding N3 is equal to the load current in the NST state and equal to the DC-link current in the ST state. The following expressions can thus be obtained: (

P iN3;nst ¼ iload ¼ BVin ð1d cÞ iN3;st ¼ ist ¼ KVcinP

ð5:33Þ

From (5.32) and (5.33), the current through the last winding N2 can finally be derived as (

c Pdc iN2;nst ¼ VinKð1d cÞ iN2;st ¼  KVcinP

ð5:34Þ

Now, for the E-QYSI, its current through winding N1 is approximately equal to its average input current when it is in the ST state. A related expression can hence be written as 0

0

iN1;st ¼ iin;ave ¼

P Vin

ð5:35Þ

This expression, when used for ampere-second balance of capacitor C2, permits the current through N1 during NST to be determined as 0

iN1;nst ¼ 

Pd Vin ð1  dÞ

ð5:36Þ

Next, the current through winding N2 can be equated to the load and dc-link currents when the converter is in the NST and ST states, respectively. Its value can hence be calculated using 8 P 0 > > < iN2;nst ¼ BV ð1  dÞ in > ðK þ 1ÞP 0 > : iN ¼ ist ¼ 2;st Vin

ð5:37Þ

Finally, the current through winding N3 can be obtained from currents flowing through N1 and N2. The third set of current expressions can thus be derived as

94

5 Three-Winding Impedance Source Inverter

Table 5.1 Winding current expressions of YSI and E-QYSI Current

Y-Source

Extended quasi-Y-source

iN1;st

0

P=Vin

iN1;dst

P=½Vin ð1  dc Þ

Pd=½Vin ð1  dÞ

iN2;st

Kc P=Vin

ðK þ 1ÞP=Vin

iN2;dst

Kc Pdc =½Vin ð1  dc Þ

P=½BVin ð1  dÞ

iN3;st

Kc P=Vin

KP=Vin

iN3;dst

Pð1  Kc dc Þ=½Vin ð1  dc Þ pffiffiffiffiffiffiffiffiffiffiffiffiffi P=ðVin 1  dc Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi  P Kc2 dc þ Kc2 dc2 ð1  dc Þ Vin rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi . P Kc2 dc þ ð1  Kc dc Þ2 ð1  dc Þ Vin

Pð1  KdÞ=½Vin ð1  dÞ pffiffiffi pffiffiffiffiffiffiffiffiffiffiffi P d ðVin 1  d Þ qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi P ðK þ 1Þ2 d þ 1=B2 ð1  dÞ Vin rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ffi . P k 2 d þ ð1  KdÞ2 ð1  dÞ Vin

P=½Vin ð1  dc Þ Kc P=½Vin ð1  dc Þ ðKc  1ÞP=½Vin ð1  dc Þ

P=½Vin ð1  dÞ KP=½Vin ð1  dÞ ðK  1ÞP=½Vin ð1  dÞ

iN1;rms iN2;rms iN3;rms DiN1 DiN2 DiN3

8 Pð1  KdÞ 0 > > < iN3;nst ¼  Vin ð1  dÞ > KP 0 > : iN3;st ¼  Vin

ð5:38Þ

All obtained ST and NST winding current expressions for the two inverters can now be summarized in Table 5.1 for the same input voltage, output power, boost factor, and winding factor. They can also be substituted to (5.39) for determining each RMS winding current expression per switching period: iNj;rms ¼

qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi i2Nj;st d þ i2Nj;nst ð1  dÞ

ð5:39Þ

where j = 1, 2 and 3. The resulting RMS expressions for the two inverters are also summarized in Table 5.1, from which it can be deduced that both inverters carry almost the same RMS current through winding N3. However, RMS currents through windings N1 and N2 of the E-QYSI are smaller than those of the YSI. The following inequality can hence be written, which according to (5.30) implies a smaller coupled inductor core size for the E-QYSI: 3 X j¼1

Nj2 i2Nj;rms [

3 X j¼1

Nj2 i02 Nj;rms

ð5:40Þ

5.3 Extended Quasi-Y-Source Inverter

95

However, the E-QYSI has an extra input inductor Lin, which when considered with the coupled inductor yields the following expression for relating its total magnetic core size: SEQYSI ¼ SYcoupled þ SLin /

3 X

2 02 Nj2 i02 Nj;rms þ Nin iin

ð5:41Þ

j¼1

where SY-coupled and SLin are respective core sizes of the coupled and input inductors found in the E-QYSI, and Nin is the number of turns of the input inductor. The second term in (5.41) can then be computed, before comparing (5.41) with the core size demanded by the YSI. The inequality obtained is found in (5.42), which as intended demonstrates a smaller total core size for the E-QYSI. 3 X

Nj2 i2Nj;rms [

j¼1

3 X

2 02 Nj2 i02 Nj;rms þ Nin iin

ð5:42Þ

j¼1

This implication, without and with Lin included, has been presented in Fig. 5.8, where solid and dashed red curves have been plotted for showing how ratio of two core sizes varies with boost factor. The common parameters used for the plot are Vin = 80 V, K = 3 (N1:N2:N3 = 1:1:2), and a load of R = 60 X connected to each inverter. Evidently, the figure shows that E-QYSI indeed requires a smaller core for its coupled inductor than the YSI, especially at smaller boost values. Even with Lin included, the total core size of the E-QYSI is still smaller than that of the YSI, even though the difference in size may not be as high as that without Lin included.

3.0

Fig. 5.8 Ratios of magnetic core size of YSI to those of E-QYSI (red) and IYSI (green) versus boost factor

Not including Lin Including Lin

2.6

SYSI / SE-qYSI, SYSI / SiYSI

Not including Lin Including Lin

2.2

1.8

1.4

1

0.6

1

1.5

2

2.5

B

3

3.5

4

96

5 Three-Winding Impedance Source Inverter

The same evaluation, when repeated with the IYSI, shows its RMS current expressions being the same as those of the YSI in Table 5.1. But, because its boost factor Bi is 1/[1−(Ki+1)di] with subscript i added for notating IYSI, its duty ratio di is smaller than dc of the YSI, if their parameters are set as Ki= Kc and Bi = Bc. This then implies a slightly smaller core for the coupled inductor found in the IYSI than in the YSI, as indicated by the solid green curve in Fig. 5.8. But, with both extra input inductor Lin and coupled inductor considered, the dashed green curve in the same figure informs that the IYSI needs a larger total magnetic core size than the YSI. It is thus not as favorable in terms of size when compared with the E-QYSI.

5.3.4

Component Stresses

Expressions for calculating the voltage and current stresses experienced by the components in the three considered networks have been summarized in Table 5.2. Specifically, the IYSI has been chosen here, because like the E-QYSI, it includes components for smoothing the input current, even though their placements are noticeably different. Comparing expressions in the first row of the table for the three inverters then yields di = d < dc, if their parameters are set as K = Ki = Kc and B = Bi = Bc, where subscript i is for notating IYSI. This leads to the same voltage across C1, same voltage across C2, and same voltage across D1 for both E-QYSI and IYSI. Their common voltage across C1 and voltage across D1 are however slightly higher than those of the YSI (C2 not found in the YSI). In terms of currents, the smallest and highest peak currents of the E-QYSI are in windings N1 and N2, respectively. As for winding N3, its current is the same as those flowing through similarly notated windings in the YSI and IYSI. The same shoot-through currents have also flowed through the E-QYSI and IYSI, but not the YSI whose value is slightly lower.

Table 5.2 Voltage and current stresses experienced by YSI, IYSI, and E-QYSI Parameter for comparison

Y-source

Improved Y-source

Extended quasi-Y-source

B = Vdc/Vin VC1 VC2 VD

1/[1−(Ki + 1)di] (1−di)BVin KidiBVin −KiBVin

1/[1−(K + 1)d] (1−d)BVin KdBVin −KBVin

iN1;peak

1/(1−Kcdc) (1−dc)BVin NA −(Kc−1) BVin P/Vin(1−dc)

P/Vin(1−di)

P/Vin

iN2;peak

−KcP/Vin

−KiP/Vin

(K + 1)P/Vin

iN3;peak

KcP/Vin

KiP/Vin

−KP/Vin

iST

KcP/Vin

(Ki+1)P/Vin

(K + 1)P/Vin

5.3 Extended Quasi-Y-Source Inverter

97

The above comparative results will nonetheless be different, if parameters of the inverters are set alternatively as d = di = dc and B = Bi = Bc. Winding factors of the three inverters must then be related by K = Ki = Kc − 1, which quantitatively means the E-QYSI and IYSI need smaller winding factors than the YSI for achieving the same performance. Peak currents through windings of the E-QYSI and IYSI have also been found to be close and reduced, which from (5.30), translates to smaller cores than that of the YSI. Other than that, voltages across capacitor C1 and diode D1 remain almost the same among all three inverters. It is thus pertinent to conclude that both E-QYSI and IYSI experience comparable component stresses. Additionally, when compared with the YSI, the E-QYSI does not experience significant increases in stresses that will weaken its advantages of a smaller magnetic core, continuous input current, and lessened inrush impacts. It may thus be the preferred topology, whose other advantages related to leakage inductances have been presented in the following subsections.

5.3.5

Loss of ST Duty Ratio

Equivalent circuits of the E-QYSI with leakage inductances included are drawn in Fig. 5.9. Notations used for the leakage inductances are LN1 , LN2 , and LN3 , whose subscripts denote their associated windings. They are normally not considered when establishing the gain of the inverter, but will influence its response when transiting from one state to the other, even though they are much smaller than the magnetizing inductance or LM>>LN1 , LN2 , LN3 . To illustrate this transitional response, Fig. 5.9a shows an intermediate state, which will occur when transiting from NST to ST state by turning ON the equivalent switch SW. Ideally, diode D1 should block instantaneously, but is delayed, since its current can only be transferred to LN1 gradually. The intermediate state in Fig. 5.9a with both SW and D1 in conduction will hence occur for a short duration. Moreover, in this intermediate state, there is a rapid rise of the currents through LN1 and LN2 , and a rapid fall of the current through LN3 . Applying Kirchhoff’s voltage law to Fig. 5.9a then results in 0

Vin ¼ VC1  VC2 þ vLin þ vN1 ðTÞ þ vN1 ðTÞ =n13 þ vL1 þ vL3

ð5:43Þ

VC1 þ vN1 ðTÞ =n13  vN1 ðTÞ =n12 þ vL3  vL2 ¼ 0

ð5:44Þ

0

Vin ¼ VC2 þ vLin þ vN1 ðTÞ þ vN1 ðTÞ =n12 þ vL1 þ vL2

ð5:45Þ

where vN1 ðTÞ, vN2 ðTÞ, and vN3 ðTÞ are, respectively, the voltages across the coupled windings N1, N2, and N3 during the intermediate state. Further, from (5.43) and (5.44), the expression of the voltage across N1 during the intermediate state can be derived as

98

5 Three-Winding Impedance Source Inverter

C2 LN1 v Vc2 L1

Lin

(a)

v'Lin

LN2 vL2

vN1(T)

N2

N1

LM Vin

N3

Vc1

C1 C2 LN1 v Vc2 L1

Lin

vLin

Vdc

LN3 vL3

D1

(b)

SW

LN2 vL2

vN1(T)

N2

N1

LM Vin

N3

SW

Vdc

LN3 vL3

D1

Vc1

C1

Fig. 5.9 Equivalent circuits of E-QYSI during a NST-to-ST and b ST-to-NST transitions

( vN1 ðTÞ ¼

N1 N1 þ N3

0

ðVin  VC1 þ VC2  vLin Þ  N1 Nþ1 N3 ðvL1 þ vL3 Þ N1 N1 N2 N3 VC1 þ N3 N2 ðvL2  vL3 Þ

ð5:46Þ

Next, from (5.16), (5.18) and (5.20), voltage expressions of winding N1 in the ST and NST states can be obtained as N1 VC N2  N3 1

ð5:47Þ

N1 0 ðVin  VC1 þ VC2  vLin Þ N1 þ N3

ð5:48Þ

v N1 ¼ 0

v N1 ¼

Substituting (5.47) and (5.48) to (5.46) then yields ( vN1 ðTÞ ¼

0

v

þv

L1 L3 1 vN1  N3NN K 2 N1 vN1 þ N3 N2 ðvL2  vL3 Þ

ð5:49Þ

Moreover, to obtain a high gain, K is usually large, which together with earlier mentioned relations of vL1 , vL2 > 0, vL3 < 0 and |vL3 |, |vL2 | > |vL1 | leads to the

5.3 Extended Quasi-Y-Source Inverter

99

Fig. 5.10 Anticipated waveforms of Vdc, iD, and VD for indicating losses of ST duty ratio and generation of voltage spikes due to leakage inductance

d1T

DC-link voltage Vdc

d2T

iD through D ST

ST

Active mode

Freewheeling mode

VD across D dT/2

T

dT/2

0

approximation of vN1 ðTÞ  vN1 . Applying voltage-second balance to winding N1 then results in a shortened ST duty ratio, which is given as d 0 ¼ d  ðDd1 þ Dd2 Þ\d

ð5:50Þ

where Δd1 and Δd2 are intervals occupied by the intermediate state, as marked in Fig. 5.10. They differ only in their initial states, which can be the NST freewheeling or NST active state, before crossing over to the ST state. This difference exists because of the single-phase bridge used with the E-QYSI in Fig. 5.5. Its output can hence be null or active when it is in the NST state. Regardless of that, mathematical derivation of the two intervals is necessary, which for Δd1 can be expressed as   LN1 DiN1    ð5:51Þ Dd1 ¼  vL 1 T  where DiN1 , DiN2 , and DiN3 are the current variations through LN1 , LN2 , and LN3 when operating in the intermediate state. The latter two variations will be used later. In (5.51), only DiN1 and vL1 of winding N1 are needed, which for vL1 can be obtained from (5.43) and (5.45) as v L1 ¼ 

ðN1 þ N3 ÞDiN1 LN1 Vin ½1  ðK þ 1ÞdH

ð5:52Þ

where H ¼ ðN2  N3 ÞDiN1 LN1  ðN1 þ N3 ÞDiN2 LN2 þ ðN1 þ N2 ÞDiN3 LN3

ð5:53Þ

These expressions, after substituted to (5.51), yield the following expanded Δd1:

100

5 Three-Winding Impedance Source Inverter

    ½1  ðK þ 1ÞdH    H     ¼ Dd1 ¼  ðN1 þ N3 ÞTVin  ðN1 þ N3 ÞBTVin 

ð5:54Þ

Through H, Δd1 increases with larger leakage inductances and winding current variations when it is in the intermediate state. It also decreases with the boost factor B, input voltage Vin, and switching period T, and it will depend on the number of turns of each winding. However, its accompanied trend of variation with winding turns is less obvious according to (5.54), and it is hence not generalized. A second expression for Δd2 can also be found, but because its current variations in H have only tiny differences, Δd1 and Δd2 can be assumed nearly equal or Δd1  Δd2. As for the YSI, the same derivative procedure leads to the following loss of the ST duty ratio Δd1,c, where subscript c has again been added for denoting YSI:      ð1  Kc dc ÞHc    Hc ¼  Dd1;c ¼    ðN1 þ N2 ÞTVin ðN1 þ N2 ÞBc TVin 

ð5:55Þ

where Hc shares the same expression as H in (5.53), but has different current variations through the leakage inductances. Expressions for these variations can be obtained from Table 5.1. The outcome is |DiN1 | < |DiN1;c |, |DiN2 | < |DiN2;c | and |DiN3 | < |DiN3;c |, if the winding and boost factors of both E-QYSI and YSI are kept the same. From (5.53), these current inequalities then yield |H| < |Hc| for the two inverters. Furthermore, from (5.21), in order for the winding factor K to be positive, N3 must be larger than N2. Therefore, N1 + N3 in (5.54) will be greater than N1 + N2 in (5.55), which together with other derived inequalities leads to Δd1 < Δd1,c for relating losses of ST duty ratios of the two inverters. The same can be written for the second loss interval in Fig. 5.10, meaning Δd2 < Δd2,c. The loss of ST duty ratio of the E-QYSI is smaller than that of the YSI.

5.3.6

DC-Link Voltage Spikes

Shoot-through will end upon opening the equivalent switch SW, which will also cause diode D1 to conduct almost immediately. The E-QYSI will then enter either its NST active or freewheeling state without any unintended delay, and hence no change to its ST end time. Its equivalent circuit with leakage inductances included is provided in Fig. 5.9b, which can then be used for explaining a transitional problem caused by the opening of the equivalent switch SW. To be precise, opening of SW will cause an instantaneous current mismatch between the leakage inductance LN2 and the equivalent current source located at the right of Fig. 5.9b. The value of this current source can either be the load current if in the NST active state or zero if in the NST freewheeling state. Either value, the current through LN2 will be forced to change abruptly. The outcome is an undesired

5.3 Extended Quasi-Y-Source Inverter

101

high voltage spike at the DC-link. An illustration for showing it is provided in Fig. 5.10, from which another observation noted is the larger spike created when entering the NST freewheeling state. This is related to current through LN2 being completely forced down to zero when it is in the NST freewheeling state. It is hence a more abrupt change than when entering the NST active state. Regardless of that, the voltage spikes tolerated by the E-QYSI are generally smaller than those experienced by the YSI. The explanation for that can be inferred from (5.21), where the winding factor is defined as (N1 + N3) /(N3 − N2). To generate a voltage gain greater than unity then requires K to be positive according to (5.23). That means N3 > N2 and the same requirements apply to the YSI according to its corresponding expressions for winding factor and voltage gain. However, for the E-QYSI, the smaller winding N2 is placed next to its equivalent switch, while for the YSI, it is winding N3 next to its equivalent switch. Since the inductance of each winding is proportional to the square of its number of turns, the E-QYSI will generate smaller voltage spikes, since it breaks the current through a smaller leakage inductance. This improvement can be seen from results presented later.

Filter Inductors Auxiliary Power

S1

S2

S3

S4 Filter Capacitor

Coupled Inductor D1

C1 Lin

C2 Vin

Fig. 5.11 Experimental setup

Vo

102

5 Three-Winding Impedance Source Inverter

Table 5.3 System parameters for test

5.3.7

Parameter

Value/Part number

Input voltage Output voltage (peak value) Power rating Capacitors C1/C2 Switching frequency Turns ratio Magnetic core Switch Diode Filter inductor Lac Filter capacitor Cac

80 V 160 V 200 W 470 lF/100 lF 10 kHz 40:40:80 C055863A2 IRGP4062DPbF STPSC20H12DY 4.5 mH 10 lF

Experimental Results

Experimental testing of a 200 W prototype controlled by a TMS320F28335 digital signal processor has been performed for proving practicality of the proposed E-QYSI. The hardware setup is shown in Fig. 5.11, while its parameters are given in Table 5.3. Further, to facilitate a fair comparison, an experimental YSI has been implemented using the same printed circuit board and parameters, and operated under the same conditions. Their coupled inductors have hence been wound to provide the same winding factor of K = 3. To generate the same voltage gain of 2.5 then requires d of the E-QYSI to be 0.15 and dc of the YSI to be 0.20. Additionally, their leakage inductances have been measured as 2.0 lH for winding N1, 1.8 lH for

(b) Vin, vo (100 V/div) Iin, io (5 A/div)

Vin

0 0 0

vo

io Iin

0

t (10 ms/div)

0

t (20 μs/div)

Iin (5 A/div)

Iin (5 A/div)

Vin, vo (100 V/div) Iin, io (5 A/div)

(a)

Vin

0

vo

0

io

0 Iin

0

t (10 ms/div)

0

t (20 μs/div)

Fig. 5.12 Experimental results Vin, vo, Iin, and io of a YSI and b E-QYSI

5.3 Extended Quasi-Y-Source Inverter

103

Fig. 5.13 Harmonic analysis results of the output voltage and current

N2, and 7.5 lH for N3. These values are 0.55, 0.49, and 0.53% of the magnetizing inductance, and they are common to both inverters. However, it should be emphasized again that positions of N2 and N3 have been swapped in both inverters. Operation of the inverters then leads to the input and output waveforms as shown in Fig. 5.12, where both inverters receive the same input voltage of Vin = 80 V, but only the input current drawn by the E-QYSI is continuous. Moreover, with their common modulation ratio set to be M = 0.8, the peak output voltages generated by the inverters are 150 V for the E-QYSI and 145 V for the YSI. These values are obviously higher than their common input voltage, and hence higher than the output of a normal single-phase full-bridge inverter supplied by the same input voltage. However, they are slightly smaller than their common theoretical peak output voltage of 160 V, calculated using (5.24) and (5.29) for the two inverters. Figure 5.13 shows the harmonic analysis results of the output voltage and current by using WT1800 precision power analyzer. The THD of Uo is 1.537% and the THD of Io is 1.402%. The dynamic performance can be observed in Fig. 5.14, where the load decreases from 110 to 60 X. It can be seen that the inverter can reach steady state in a short time after the load changes. More precisely, Fig. 5.15 shows the dc-link voltages, diode voltages, and their currents measured from the two inverters during their NST-to-ST transitions. As observed, the loss of ST duty ratio is Δd1T  Δd2T  200 ns for the E-QYSI,

104

5 Three-Winding Impedance Source Inverter vo

vo (100 V/div) io (10 A/div)

Fig. 5.14 Experimental results demonstrating load variation

0

Load Switching io 0

t (20 ms/div)

(a)

(b)

Vdc Δd1,cT = 400 ns

VD1 (500 V/div), Vdc(100 V/div)

VD1

iD1

iD1 (10 A/div)

iD1 (10 A/div)

VD1 (500 V/div), Vdc(100 V/div)

iD1

VD1 Vdc Δd1,cT = 200 ns

t (1 μs/div)

t (1 μs/div)

Fig. 5.15 Experimental results iD1 , VD1 , and Vdc of a YSI and b E-QYSI

(b)

Vin VC2

Vin, VC1, Vdc(100 V/div)

Vin, VC1, Vdc(100 V/div)

(a)

VC1 290V Vdc

Vin

548V VC1

Vdc

185V t (20 μs/div)

182V t (20 μs/div)

Fig. 5.16 Experimental results Vin, VC1 , VC2 , and Vdc of a YSI and b E-QYSI

5.3 Extended Quasi-Y-Source Inverter

(b)

iN1

iN1, iN2, iN3(5 A/div)

iN1, iN2, iN3(5 A/div)

(a)

105

iN2

iN3

iN1

iN3

iN2

t (20 μs/div)

t (20 μs/div)

Fig. 5.17 Experimental results iN1 , iN2 , and iN3 of a YSI and b E-QYSI

Efficiency(%)

which is smaller than Δd1,cT  Δd2,cT  400 ns for the YSI. In terms of percentage, they are 2.67% for the E-QYSI and 4% for the YSI. The results are thus in good agreement with earlier theoretical analysis. Figure 5.16 shows voltages across capacitors and DC-link voltages of both inverters, where noticeably smaller DC-link voltage spikes have been observed with the E-QYSI, even though it uses the same coupled inductor as the YSI. Across the extra capacitor C2 of the E-QYSI, its recorded voltage of about 85 V is also comparably smaller than that seen across C1. Its addition will hence hardly affect operational reliability of the E-QYSI. Other shown results are winding currents of the two inverters in Fig. 5.17, from which smaller RMS values of the E-QYSI can be seen. A smaller core size can hence be used for winding the coupled inductor of the E-QYSI, which is an advantage. Finally, measured efficiencies of the YSI, IYSI, and E-QYSI with a common peak output voltage of 160 V have been plotted in Fig. 5.18. They are controlled by a closed-loop control strategy. The peak output voltages of them are set to be 160 V. The power axis of Fig. 5.18 is set according to the output power. The load is

90 88 86 84 82 80 78 76 74 72 70

YSI E-qYSI iYSI 50

100

150

200

Power(W)

Fig. 5.18 Measured efficiencies of YSI and E-QYSI at different output powers

250

106

5 Three-Winding Impedance Source Inverter

pure resistive and the output power will vary with the load. Each time, the efficiency has been measured after the inverter has operated stably for 30 min. Thus, the inverter can achieve thermal stability and the measured efficiency is more accurate. The efficiency of the E-QYSI is higher than that of the IYSI. This is due to smaller RMS winding currents of the proposed E-QYSI, as compared to those of the IYSI. Efficiencies of the E-QYSI and IYSI are however lower than that of the YSI, which are mostly due to power losses of their extra input inductors, rather than their coupled inductors. In conclusion, E-QYSI uses a coupled inductor with three windings, and it is hence like the YSI, even though the positions of their windings are slightly different. But, unlike the YSI, the E-QYSI has an improved boost factor, which in turn will permit a smaller ST duty ratio, and hence a larger modulation ratio to be used. Its input current is also continuous, and it is significantly alleviated from a large startup inrush. Moreover, with smaller RMS currents flowing through the windings of its coupled inductor, its magnetic core size can be reduced. Despite that, the leakage inductances in series with the windings still exist, whose effects like losses of ST duty ratio and gain, and large DC-link voltage spikes have been suppressed more prominently by the E-QYSI. Furthermore, when compared with the IYSI, the proposed E-QYSI demonstrates a smaller magnetic core and a higher efficiency, even though both inverters are capable of smoothing their input currents.

5.4

Modified Y-Source Inverter

As mentioned in the last section, the large DC-link spikes can be caused by the non-negligible leakage inductances of the coupled inductors when the Y-source inverters or other coupled inductor impedance source inverters turn from the ST state to the NST state. The voltage spikes may lead to higher voltage rated switches and thus cause higher on-resistor, which may increase the power losses. Therefore, the leakage inductances should be eliminated to improve the efficiency of the YSI. One method that changing the structure of the coupled inductor can be applied to reduce the leakage inductances of the YSI. For instance, a Δ-connection rather than Y-connection of the three windings is adopted to decrease the leakage inductances [11]. However, the introduction of Δ-connection also decreases the degree of flexibility of the voltage gain, which results in the performance of three coupled inductors being similar to the two coupled inductors. Another method to eliminate the leakage inductances is adding absorbing circuits [12]. The absorbing circuits can be divided into active circuits and passive circuits. The active circuit recycles the leakage energy by extra switches, which may increase the complexity and cost. And the passive circuit proposed in [12] overcomes the weakness of the active circuit, which clamps the DC-link spikes by only capacitors and diodes. However, a huge current will flow through the power supply in ST state without limiting inductance. Moreover, this passive circuit cannot improve the boost ability. Another passive circuit was proposed in [13],

5.4 Modified Y-Source Inverter

107

C2

C4

D1

Vin

vdc

C3

va

S6

C1

vb vc S2

S4

Load or grid

N2

S5

S3

S1

Lo

D2

N3

N1

Filter

Lin

Fig. 5.19 Topology of modified Y-source inverter

which clamped the DC-link voltage by an additional capacitor and a diode. However, the DC-link voltage will be slightly larger when the additional diode conducts. A similar passive circuit proposed in [14] adds only one diode to the original inverter, but inherit the same problem with the one given in [13]. Besides, the E-QYSI proposed in the last section can suppress DC-link spikes at some level without adding extra components based on the IYSI. However, the DC-link spikes cannot be eliminated totally and the boost factor B is same as the IYSI. Therefore, a modified Y-source inverter (M-YSI) has been proposed to eliminate the DC-link voltage spikes and improve the overall boost ability [15]. The circuit diagram of the M-YSI is shown in Fig. 5.19. The circuit shown in black line

iC2

(a)

C2 VC2

Lin vLin Vin Iin

V + LK - i1 i1 N1 LK IM vLM

iC2

Vin Iin

N3 VC3

VC1

iC3 C3

Vin Iin

ist

C1

o ILo

Lin vLin

vLo

N3 VC3

vLo

N3

vLM

iC3 C3 Vdc

Io

Vin Iin

i2 N2

VC3

VC1

iC3 C3

ist

C1 C2 iC4

V + LK - i1 i1 N1 LK IM vLM

C4 VC4 L

i3

VC2 o ILo

C1

IM

C4 VC4 L

i3

iC4

i1 N1

iC2

(d) iC4

i2 N2

LK

VC1

C2

V + LK - i1 i1 N1 LK IM vLM

Lin vLin

o ILo

i2 N2

C2 VC2

vLo

VC2 Lin vLin

C4 VC4 L

i3

VC1

(c)

iC4

iC2

(b)

i3 -

vD2 +

N3 i2 N2

VC3

C4 VC4 L

o ILo

vLo iC3 C3 Vdc

Io

C1

Fig. 5.20 Equivalent circuit of the M-YSI when in a ST state [t0, t1], b ST state [t1, t2], c NST state [t2, t3], and d NST state [t3, t0]

108 Fig. 5.21 Key waveforms of M-YSI with respect to equivalent circuit in Fig. 5.20

5 Three-Winding Impedance Source Inverter

GSW

iC 4 = −i3 t

iC4

t iC2 t iC3 t i3 t i2 t i1 t

iD2

t

vD1

t

vD2

t

vdc t0 t1

t2

t3

t0 t1

t2

t

5.4 Modified Y-Source Inverter

109

is the IYSI, and the passive absorbing circuit has been drawn in red which can overcome the deficiency of other absorbing circuits. Figure 5.20 shows the operational modes of the M-YSI, and the key wave is shown in Fig. 5.21. The inverter bridge is simplified as switch SW and the load is simplified as a current source Io. LM represents the equivalent magnetizing inductance of the three-winding coupled inductor. And the leakage inductance LK is drawn with red wavy lines, whose current is not constant over a switching period. The current will change rapidly when a large voltage is across the LK. Interval I [t0, t1]: As shown in Fig. 5.20a, the switch SW turns on, and diode D1 continues to conduct due to the effect of LK, while diode D2 remains reverse-biased. The current through LK begins to drop rapidly because of the huge voltage VLK. Diode D1 will remain conduct until the current through LK drops to zero. Interval II [t1, t2]: As shown in Fig. 5.20 b, the current through LK drops to zero at t1 and D1 becomes reverse-biased. The inductors Lin, Lo, and LM are charged, while the capacitors C1, C2, C3, and C4 are discharged. It is worth mentioning that this interval is longer than interval I. Interval III [t2, t3]: As shown in Fig. 5.20c, the switch SW turns off at t2, causing its voltage and current to rise and fall, respectively. Both diode D1 and D2 will conduct simultaneously. During this interval, the conduction of D2 permits C3 and C4 to be connected in series for clamping the DC-link voltage across SW. Voltage spikes have hence been intentionally suppressed at ST to NST crossovers. Interval IV [t3, t0]: As shown in Fig. 5.20d, the current through D2 finally drops to zero, and it begins to block. Meanwhile, D1 continues to conduct, which hence permits C1 and C4 to be connected across N2 and N3 for clamping their total voltage. Additionally, the DC-link voltage across SW is no longer solely equal to the combined voltage of C3 and C4 in series, since it now includes the reverse voltage of D2. The interval in Fig. 5.20a is much shorter in duration than the other three intervals. It is nonetheless included for revealing influences caused by leakage inductances. Its circuit expressions have however been omitted from the following mathematical analysis, since energies of passive components have hardly changed during such a short interval between [t0, t1]. Therefore, analyzing the current of capacitors begins from Fig. 5.20b, where both diodes are reverse-biased. And the related current expressions can be written as follows: iC1 ¼ i2 ¼ i3

ð5:56Þ

iC2 ¼ Iin

ð5:57Þ

iC3 ¼ ILo

ð5:58Þ

iC4 ¼ i3

ð5:59Þ

According to the relationship between winding currents and the node current law, the winding current can be expressed as

110

5 Three-Winding Impedance Source Inverter 0

N1 i1 þ ðN3  N2 Þi3 ¼ 0 0

i1 ¼ IM

ð5:60Þ ð5:61Þ

where (5.60) and (5.61) are the current relationship within the coupled inductors. Substituting them into (5.56) and (5.59), then the current of C1 and C2 can be derived as iC1 ¼ iC4 ¼ 

N1 IM N3  N2

ð5:62Þ

From Fig. 5.21, it is obvious that the current of all capacitors during interval III is changed linearly. The capacitors C1 and C2 are charging without any abrupt step at t2, while C3 and C4 are discharging with saltation at t2. And the current of C3 and C4 can be obtained as iC3 ¼ Iin  Io þ

N1 IM N3  N2

iC4 ¼ Iin þ ILo  Io

ð5:63Þ ð5:64Þ

When the diode D2 is blocked, namely, entering the interval IV, the capacitor currents will be constant. And the related current equations can be derived as iC3 ¼ ILo

ð5:65Þ

iC1 ¼ i2 ¼ Iin þ ILo  Io

ð5:66Þ

i1 ¼ Iin þ iC2

ð5:67Þ

iC4 ¼ i3

ð5:68Þ

i3 ¼ Io  ILo þ iC2

ð5:69Þ

According to the relationship between winding currents and the node current law, the winding current can be expressed as 0

N1 i1 þ N2 i2 þ N3 i3 ¼ 0

ð5:70Þ

0

ð5:71Þ

i1 ¼ i1 þ IM

where (5.70) and (5.71) are also the current relationship within the coupled inductors. Then the capacitor currents through C1 and C2 can be written as

5.4 Modified Y-Source Inverter

111

iC1 ¼ Iin þ ILo  Io i C2 ¼

ð5:72Þ

ðN3  N2 ÞðIin þ ILo  Io Þ þ N1 IM  Iin N3 þ N1

ð5:73Þ

Apply the ampere-second principle to each capacitor, which means the current equations of each capacitor should be integrated over a switch period. And the integral equation can be expressed as Z t1

Z

t2

iCx dt þ

Z

¼

t3

t2 dT

Z iCx dt þ

iCx dt t3

Z

ða þ dÞT

iCx dt þ

0

t0

Z

iCx dt þ

dT

T

ða þ dÞT

iCx dt

ð5:74Þ

¼0 2 where a¼ t3 t T is the proportionality coefficient; x = 1, 2, 3 or 4 is an index for the capacitors; and the interval I has been ignored. Then the current equations as the following can be derived, and currents through all components can be obtained by using them:

2 ð1  dÞ 1þK

ð5:75Þ

ILo ¼ Iin

ð5:76Þ

ðN1 þ N3 Þ Iin N1

ð5:77Þ

1  ð2 þ KÞd Iin ð1  dÞ

ð5:78Þ

a¼

IM ¼ Io ¼

N3 where K ¼ NN13 þ N2 is the winding factor of the M-YSI which is still same as that of YSI, and d is the shoot-through duty ratio. If the efficiency is 100%, which means Iin Vin ¼ ð1  dÞIo Vdc , the following expression can be derived:

Vdc ¼ BVin ¼

1 Vin 1  ð2 þ KÞd

ð5:79Þ

where B is the boost factor of M-YSI. The voltage analysis can also begin at interval II, and during this interval, the voltage across the coupled inductors is clamped by C1 and C4. The voltages across the input inductor Iin, the magnetizing inductor IM, and the output inductor ILo can be derived as

112

5 Three-Winding Impedance Source Inverter

vLM ¼ ðVC1 þ VC4 Þ

N1 N3  N2

ð5:80Þ

vLo ¼ VC3

ð5:81Þ

vLin ¼ ðVin þ VC2 Þ

ð5:82Þ

When the inverter enters interval III, it can be observed that intervals III and IV can be merged together when analysis because VD2 is nearly equal to zero. During interval III, the coupled inductors are clamped by C1 and C3. And the related voltage equations across the capacitors can be expressed as vLM ¼ ðVC1  VC3 Þ

N1 N3  N2

ð5:83Þ

vLo ¼ VC4

ð5:84Þ

vLin ¼ VC3  VC2  Vin

ð5:85Þ

Apply the volt-second balance principle to inductor Lin, Lo, and LM, the voltages of capacitors can be derived as VC1 ¼ ð1  2dÞBVin

ð5:86Þ

VC2 ¼ ð1 þ KÞdBVin

ð5:87Þ

VC3 ¼ ð1  dÞBVin

ð5:88Þ

VC4 ¼ dBVin

ð5:89Þ

A gain higher than that of the original YSI can thus be obtained by setting K equal or greater than one. The DC-link voltage Vdc and peak ac output voltage ^v0 of the inverter are expressed as ^vo ¼ BMVin

ð5:90Þ

where M is the modulation index, which together with d, must satisfy as M\1  d

ð5:91Þ

1  ð2 þ K Þd [ 0

ð5:92Þ

Therefore, a larger d to obtain a bigger gain will hence limit the maximum of M, which will influence the output waveform of the inverter.

5.4 Modified Y-Source Inverter

113

Table 5.4 Comparison of voltage and current stresses for two inverters Parameter for comparison

I-YSI

M-YSI

B = Vdc/Vin VC1 VC2 VC3 VC4 VD1 VD2 Iin ILo i1 i2 i3

1/[1−(1 + Kc)d] (1−d)BVin dKcBVin NA NA KcBVin NA P/Vin NA P/(1−d)Vin KcP/Vin KcP/Vin

iST

(1 + Kc)P/Vin

1/[1−(2 + K)d] (1−2d)BVin (1 + K)dBVin (1−d)BVin dBVin KBVin BVin P/Vin P/Vin (1 + K)P/(1−d)KVin (1 + K)P/(1−d)Vin KP/Vin or (K2−1)P/(1−d)KVin (2 + K)P/Vin

Table 5.4 shows the voltage and current stresses of the devices used in the IYSI and the M-YSI. To compare them in same situation, boost factors and shoot-through duty ratio of the two inverters are set to the same value, so the turns ratio (Kc) of IYSI and the turns ratio (K) of the novel topology must satisfy the equation Kc = 1 + K. The boost ratios of both topologies are equal in the Table 5.4. The voltage stress across C1 and D1 of the M-YSI is much smaller than those of the IYSI if the turns ratio K is not big or the duty cycle d is large. The voltage stress of diode D2 is equal to the output voltage. The maxim current flow through N1 and N2 of M-YSI is larger than that of IYSI, while the coil current of N3 is equal or smaller than the IYSI. Whether the coil current of N3 is smaller or equal is depend on the value of K and d. The current stress iST of the inverter bridge is equal in the two topologies. To show the great properties of the M-YSI, the IYSI was also constructed to compare with the M-YSI. Two 200 W prototypes have been built for them. They use the same circuit parameter listed in Table 5.5 and are constructed in the same printed circuit board. To boost an input voltage of 80 V to an output voltage of 160 V, the ST duty ratio d of M-YSI has been set to be 0.12, while that of IYSI has been set to be 0.15, since the circuit use the winding factor K = 3 (N1:N2: N3 = 40:40:80) and modulation index of M = 0.8. The coupled inductor has also been loosely wound to better demonstrate the effects from leakage inductances, which makes a strong contrast with IYSI and M-YSI. Figure 5.22 shows the DC-link voltage, diode voltages, and the diode currents of the IYSI and M-YSI. It can be seen that a huge voltage spike (330 V) occurs in the DC-link voltage of the IYSI, but the voltage spike (60 V) is not obvious in the M-YSI. Also, the ringing phenomenon in the diode D1 is significantly reduced,

114

5 Three-Winding Impedance Source Inverter

Table 5.5 System parameters

(a) Vdc : 200 V/div

Parameter

Value/part number

Input voltage Load resistance Capacitances C1 and C3 Capacitances C2 and C4 Inductances Lin and Lo Switching frequency fsw Turns ratio N1:N2:N3 Core Switches Diodes D1 and D2 Filter inductance Lf Filter capacitance Cf

80 V 60X (200 W) 470 lF 100 lF 4.3 mH 10 kHz 40:40:80 C055863A2 IRGP4062DPbF 30EPH06PBF 5.6 mH 4.7 lF

(b) Vdc : 200 V/div

0

0

t(2 ms/div)

t(2 ms/div)

Vdc : 200 V/div 0

0

Vdc :200V/div vD1:500V/div

0 0 vD2:300V/div

0 vD1: 500 V/div

0

iD1: 4 A/div t(10 μs/div)

0

iD1:4A/div

0

iD2:10A/div t (10 μs/div)

Fig. 5.22 Measured Vdc, vD1 , VD2 , iD1 , and iD2 of a IYSI and b M-YSI

which causes lower power loss on D1. In addition, the current iD2 will drop slowly to zero and the reverse recovery loss is decreased. Figure 5.23 shows the input and output waveforms of both inverters. It can be clearly seen that the peak voltage of M-YSI is 158 V, but the peak voltage of IYSI is 154 V. This voltage drop is mainly caused by the double-frequency power ripple. Since more passive components are applied in the M-YSI, the M-YSI has a strong power filter characteristic, which restrains the DC-link voltage ripple. Figure 5.24 shows the winding currents of IYSI and M-YSI. It can be seen from the figure that the winding currents of the IYSI change from one value to another

5.4 Modified Y-Source Inverter

(a)

115

(b)

0

Vin: 100 V/div

0

vo: 100 V/div

Vin:100V/div

0

Iin: 3 A/div

0

0

0

0

0 io: 2 A/div t (10 ms/div)

vo:100V/div

Iin:3A/div

io:2A/div t (10ms/div)

Fig. 5.23 Measured Vin, vo, Iin, and io of a IYSI and b M-YSI

(a) 0

0

(b) i1: 2.4 A/div ST state

0

i1: 2.4 A/div ST state

0

i2: 5 A/div

i2: 5 A/div

NST state

NST state i3: 4 A/div

i3: 4 A/div 0

0 t(10 μs/div)

t(10 μs/div)

Fig. 5.24 Measured winding currents i1, i2, and i3 of a IYSI and b M-YSI

directly when switching from shoot-through state to NST state. Thus, huge voltage spike will be introduced to the DC-link and the resonation of winding currents is great. However, the winding currents of M-YSI change slowly when enter the NST state, so the voltage spikes of M-YSI are eliminated. Compare with other impedance source inverter, M-YSI has higher voltage gain. More importantly, the proposed topology inherits the advantages of original Y-source inverter and addresses the issue of high voltage spikes on the DC-link without introducing additional switches. The current analysis and voltage analysis are demonstrated to reveal the circuit stress and prove the validity of higher step-up voltage gain. Experimental results have verified its effectiveness. The clamp circuit applied proposed in this paper can also be applied in the other coupled-induction impedance source inverters to eliminate the voltage spikes.

116

5 Three-Winding Impedance Source Inverter

Table 5.6 Basic characteristics of IYSI, E-QYSI, and M-YSI compared with YSI Characteristic

YSI

IYSI

E-QYSI

M-YSI

Boost factor Number of elements

1/(1−Kd) One coupled inductor One capacitor One diode

Continuous input current Startup inrush current Common earthing DC-link voltage spikes

No

1/(1−(1 + K)d) One coupled inductor One inductor Two capacitors One diode Yes

1/(1−(1 + K)d) One coupled inductor One inductor Two capacitors One diode Yes

1/(1−(2 + K)d) One coupled inductor Two inductors Four capacitors Two diodes Yes

Yes

No

No

No

Yes Large

Yes Large

Yes Little

Yes No

5.5

Summary

This chapter introduces several three-winding impedance source inverters, such as Y-source inverter (YSI), improved Y-source inverter (IYSI), extend quasi-Y-source inverter (E-QYSI), and modified Y-source inverter (M-YSI). All of these topologies contain the three-winding coupled inductor; thus, a higher modulation index is obtained by implementing different winding factors, turns ratios, and ranges of ST duty ratio. Besides, the freedom of boost factor is increased than two-winding impedance source inverters. Table 5.6 summarizes the basic characteristics of IYSI, E-QYSI, and M-YSI compared with YSI, where the winding factor K = (N1 + N3)/(N3 − N2), the ST duty ratio d = T0/Ts. The boost factors of IYSI and E-QYSI are identical, and they are all higher than that of YSI, while the boost factor of M-YSI is further higher than all the three topologies with extra passive absorbing circuit. Besides, the M-YSI eliminates the DC-link voltage spikes of original Y-source network inverters effectively through this extra passive absorbing circuit. Moreover, the improved three Y-source network inverters all can overcome the discontinuous input current and large startup inrush current of YSI.

References 1. Y.P. Siwakoti, F.Z. Peng, F. Blaabjerg, P.C. Loh, G.E. Town, Impedance-source networks for electric power conversion Part I: a topological review. IEEE Trans. Power Electron. 30(2), 699–716 (2015) 2. M. Adamowicz, LCCT-z-source inverters, in Proceedings of the EEEIC (2011), pp. 1–16

References

117

3. P.C. Loh, D. Li, F. Blaabjerg, Г-Z-source inverters. IEEE Trans. Power Electron. 28(11), 4880–4884 (2013) 4. Y.P. Siwakoti, P.c. Loh, F. Blaabjerg, G. Town, Y-Source impedance network, in Proceeding of the APEC 2014, Fort Worth, TX, (2014), pp. 3362–3366 5. Y.P. Siwakoti, G.E. Town, P.C. Loh, F. Blaabjerg, Y-source inverter, in 2014 IEEE 5th International Symposium on Power Electronics for Distributed Generation Systems (PEDG), Galway, (2014), pp. 1–6 6. R.R. Ahrabi, M.R. Banaei, Improved Y-source DC-AC converter with continuous input current. IET Power Electron. 9(4), 801–808 (2016) 7. Y.P. Siwakoti, P.C. Loh, F. Blaabjerg et al., Effects of leakage inductances on magnetically coupled Y-Source network. IEEE Trans. Power Electron. 29(11), 5662–5666 (2014) 8. Y.P. Siwakoti, F. Blaabjerg, P.C. Loh, Quasi-Y-source boost DC–DC converter. IEEE Trans. Power Electron. 30(12), 6514–6519 (2015) 9. H. Liu et al., Extended quasi-Y-source inverter with suppressed inrush and leakage effects. IET Power Electron. 12(4), 719–728 (2019) 10. Magnetics Powder Core Catalog (2015). www.mag-inc.com 11. A. Hakemi, M. Sanatkar-Chayjani, M. Monfared, Δ-source impedance network. IEEE Trans. Power Electron. 64(10), 7842–7851 (2017) 12. M. Adamowicz, N. Strzelecka, T-source inverter. Electr. Rev. 85(10), 233–238 (2009) 13. M.-K. Nguyen, Y.-C. Lim, S.-J. Park, Improved trans-z-source inverter with continuous input current and boost inversion capability. IEEE Trans. Power Electron. 28(10), 4500–4510 (2013) 14. Z. Aleem, M. Hanif, Operational analysis of improved Г-Z-Source inverter with clamping diode and its comparative evaluation. IEEE Trans. Industr. Electron. 64(12), 9191–9200 (2017) 15. H. Liu, Y. Li, Z. Zhou, H. Wu, A modified Y-Source inverter, in 2019 IEEE Applied Power Electronics Conference and Exposition (APEC), Anaheim, CA, USA (2019), pp. 3477–3482

Chapter 6

Technology of DC-Link Voltage Spikes Suppression

Abstract The introduction of coupled inductor renders the appearance of leakage inductance whatever cores or winding techniques are employed, which induces operating problems. For instance, when the coupled inductors impedance source inverters (CISI) transfer from shoot-through (ST) to non-shoot-through (NST) state, a great voltage spike will occur at the DC-link due to a sharp change in current through the leakage inductors. It will require higher rated switches and push up the production cost. Therefore, the DC-link voltage spikes should be avoided, and the lost energy on the leakage inductors is recycled through technology of dc-link voltage spikes suppression. This chapter will present several novel absorbing circuits implemented in CISIs that can suppress the dc-link voltage.

6.1

Introduction

The coupled inductors impedance source inverters are proposed to reduce components while improving the capability to step up [1–7]. The coupled inductors impedance source inverters boost the output voltage by altering the turns ratio of the coupled inductors. Besides, even at a small ST duty ratio, the coupled inductors impedance source inverters can gain higher voltage compared with other impedance source inverters. However, the leakage inductors always exist in coupled inductors whatever cores or winding techniques are employed, which will bring out many issues. The efficiency of inverters is decreased because part of energy is consumed on the leakage inductors. Furthermore, as a sharp change in current through the leakage inductors, a large voltage spikes emerge at the DC-link when the inverters transfers from the ST state to the NST state. Thus, the circuit requires a higher rated voltage of switches which will push up the production costs. The practical application of coupled inductors impedance inverters is limited by these issues unless the DC-link voltage spikes can be reduced and the lost energy on the leakage inductors could be recycled.

© Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_6

119

120

6 Technology of DC-Link Voltage Spikes Suppression

One of the methods that reducing DC-link voltage spikes is changing the structure of coupled inductors. The method brought up in [8] decreases the leakage inductance as well as series resistance on each winding of three-winding CISI by applying a Δ-connection rather than Y-connection. But the third winding depends on the other two windings using the Δ-connection structure. Thus, the degree of freedom decreases which means the three-winding coupled inductors performs quite similarly with dual-winding coupled inductors. Besides, this method cannot reduce the DC-link voltage spikes totally cause the leakage inductors still exist in the circuit. Another method is adding an extra absorbing circuit, which can either be of the active or passive type, even if the common purpose of both types is providing a way to absorb the lost energy caused by the leakage inductors. For instance, an active DC–DC buck converter has been applied into the inverter for recycling leakage energy to the capacitors or source [9]. However, the introduction of buck converter also increases one power transistor, which in turn leads to the higher control complexity and cost. Therefore, the passive type without any extra power transistors is more appealing. One of the passive absorbing circuits also proposed in [9] relies on capacitors and diodes for clamping the DC-link voltage, as shown in Fig. 6.1a. The absorbing circuit is drawn in red, while Lcouple represents the coupled inductors which can be dual-winding or three-winding. However, a huge current will flow through the input voltage Vin, diode DS2, capacitor CS1 and shorted phase leg in the ST state, since there is no series-wound sizable limiting inductance. Then the current is instantaneous large and in turn may damage power transistors or other semiconductor devices unintentionally. To limit this large current, an improved absorbing circuit is proposed in [10] where a series inductance is introduced into the ST loop. The diode DS1 conducts only during the transition of ST to NST state, which can clamp the DC-link voltage in series with CS1 and C1 as shown in Fig. 6.1b. Figure 6.1c illustrates a simplified absorbing circuit which can realize the function similarly with circuit 2 shown in Fig. 6.1b [11]. The spiky DC-link voltage can be clamped during the transfer from ST to NST state by DS in series with capacitors C1 and C2. However, the usable range of both circuit 2 and circuit 3 shown in Fig. 6.1c is limited. They are only suitable for several specific CISIs. Therefore, more novel passive absorbing circuits are proposed in this chapter as the following.

6.2

Dual Diodes Capacitor–Diode Absorbing Circuits

A family of low-spikes, high-efficiency y-source inverters (LH-YSIs) is shown in Fig. 6.2, where the absorbing circuits have been drawn by red line [12]. All the absorbing circuits are composed of two capacitors and two diodes where the second diode is sharing with the original topology. The LH-YSI-I, II, and III can be obtained by adding only one diode D2 and a capacitor C3 to the original I-YSI,

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

(a)

121

(b)

D Lcouple Vin

C2 Lin

CS1 DS1 vdc

DS2

C

Vin

CS2

D CS1

Lcouple C1

DS1

DS2

vdc

C2

(c) Lin

Vin

D Lcouple DS C1

vdc

Fig. 6.1 Original passive absorbing: a circuit 1 [9], b circuit 2 [10], and c circuit 3 [11]

while the LH-YSI-IV, V, and VI have been modified from LH-YSI-I, II, and III. The only distinction among these topologies is that they introduce different voltage and/or current stresses across the capacitors. For example, the voltage stress of the capacitor C3 in LH-YSI-II is much less than that in LH-YSI-I, while LH-YSI-II has higher current stress through the capacitor C1. Similarly, the voltage stress of capacitor C2 can be reduced in LH-YSI-III at the cost of higher current stress through C3. Although the position of diode D1 and the coupled inductors N1, N2, and N3 are adjusted in LH-YSI-IV, its voltage stresses across the capacitors are the same as those of LH-YSI-III. However, compared with LH-YSI-I, II, and III, C3 in LH-YSI-IV will suffer a smaller current stress. By making similar adjustment in LH-YSI-V and VI, the current stresses through capacitor C3 are as small as that in LH-YSI-IV. Besides, LH-YSI-V and VI have smaller voltage stress on C1 or C2, but will inevitably suffer higher current stress. The operational principles are similar for these topologies. Therefore, only mathematical derivation for LH-YSI-I has been presented in the next and the final expressions for the six inverters have been summarized as a table to be discussed later. Figure 6.3 shows the circuit diagram of the LH-YSI-I, where the absorbing circuit (D2 and C3) is drawn in red line. As can be seen, the three-winding coupled inductors (N1, N2, and N3) is used to promote the boost ability without adding too many components. Simultaneously, the input inductor Lin and capacitor C2 are introduced to provide a continuous input current. Last but not least, the passive snubber composed of capacitor C3 and diode D2 is embedded in LH-YSI-I to clamp the DC-link voltage and recycle the leakage energy.

122

6 Technology of DC-Link Voltage Spikes Suppression

C2

(a)

C2

(b) Lin

Lin D2

D2

D1

Vin

Vdc

N2

C3 N2

C1

Vdc

C1

C2

(c)

N3

N1 Vin

C3

D1

N3

N1

C2

(d)

Lin

Lin

D2

D1

D1

D2

N3

N1 Vin

Vin

Vdc

N2

N1

N3 C3

C1

N2

Vdc

C1 C3

(e)

C2

(f) Lin

D1

D2

Lin D1

D2

N1

N3 Vin

N3 Vin

C3

C3

Vdc

N2 C2

N1

C1

N2

Vdc

C1

Fig. 6.2 Low-spikes, high-efficiency YSIs: a LH-YSI-I, b LH-YSI-II, c LH-YSI-III, d LH-YSI-IV, e LH-YSI-V, and f LH-YSI-VI

C2 D1

N1

S1 N3

Vin

C3

N2 C1

Fig. 6.3 Topology of LH-YSI-I

S3

S5

va vdc S6

vb S4

vc S2

Load or grid

D2

Filter

Lin

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

6.2.1

123

Operational Modes

The operational modes of the LH-YSI-I are shown in Fig. 6.4. For conciseness, the inverter bridge and load have been simplified to a switch SW and a current source Io. The coupled inductor has been modeled as a leakage inductor LK (in red) and three ideal coupled inductors N1, N2, and N3. In order to facilitate the following analysis, LM that represents equivalent magnetizing inductance of the three-winding coupled inductor is drawn in the diagram. The capacitance of C1, C2, C3 and the inductance of Lin and LM are assumed large enough, so their voltage and current will almost not change during each switching period. Since the inductance of LK is relative small, the current through it will change greatly if bearing a large voltage. With the assumption made before, the key waveforms are summarized in Fig. 6.5, where each switching period has been divided into four intervals to be described next. (1) ST States Interval I [t0, t1]: Switch SW turns on at t0 and Vdc drops to zero. Because the potential of the negative terminal of C2 decreases, the diode D2 remains reverse-bias. But diode D1 is still conducting because of the existence of LK. The great voltage across LK causes current i1 to decrease at the rapid rate. Because this interval is quite small, the energies of all components nearly do not change except LK. Interval II [t1, t2]: The current through LK drops to zero at t1. Diode D1 is also reverse-biased and the energy of C3 remains unchanged. Lin and LM are charged, while C1 and C2 discharged.

(a)

iC2 Lin vLin iC3

Vin Iin

VC3

VC2 V + LK - i1 i′1 N1 i3 LK IM N3 ist vLM i2 LM C3 SW Vdc N2 VC1

iC2

(c) Lin vLin Vin Iin

iC3 VC3

(b)

C2

Lin vLin Io

Vin Iin

VC3

VC1

iC2

(d)

VC2 V + LK - i1 i′1 N1 i3 LK IM N3 vLM i2 LM C3 SW Vdc N2 C1

C2

VC2 V + LK - i1 i′1 N1 i3 LK IM N3 ist vLM i2 LM C3 SW Vdc N2

C1

C2

VC1

iC2

Lin vLin Io

Vin Iin

vD2 iC3 VC3

Io

C1

C2

VLK i1 i′ VC2 - 1 N1 i3 LK IM N3 vLM i2 LM C3 SW Vdc N2 VC1

Io

C1

Fig. 6.4 Equivalent circuits of LH-YSI-I when in a ST state [t0, t1], b ST state [t1, t2], c NST state [t2, t3], and d NST state [t3, t0]

124 Fig. 6.5 Key waveforms of LH-YSI-I

6 Technology of DC-Link Voltage Spikes Suppression

GSW

t

iC2

t iC3

t i3

t i2

t i1

t

iD2

t

vD1

t

vD2

t

Vdc

t0 t1

t2

t3

t0 t1

t2

t

(2) NST States Interval III [t2, t3]: Switch SW turns off at t2. Diodes D1 and D2 begin to conduct. Collectively, they cause currents i1 and i2 to increase linearly without any abrupt step at t2. In contrast, i3 will decrease. During this interval, the conduction of D2 permits C2 and C3 to be connected in series for clamping the DC-link voltage across SW. Voltage spikes have hence been intentionally suppressed at ST state to NST state crossovers.

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

125

Interval IV [t3, t0]: The current through diodes D2 finally drops to zero at t3 and it begins to block. Meanwhile, D1 continues to conduct, which permits C1 and C3 to be connected across N1, N2, and LK for clamping their total voltage. In addition, the DC-link voltage across SW is no longer solely equal to the combined voltage of C2 and C3 in series, since it now includes the reverse voltage of D2. There will hence be a very small DC-link voltage drop (proven later), after entering this interval at t3.

6.2.2

Current Analysis

According to above analysis, the circuit expressions of interval I can be omitted from the mathematical analysis, since energies of passive components hardly changed during the short interval between [t0, t1]. Therefore, beginning with Fig. 6.4b, where SW is conducting, and both D1 and D2 are reverse-biased from t1 to t2, the current expressions of the capacitors can be obtained as iC1 ¼ i2

ð6:1Þ

iC2 ¼ Iin

ð6:2Þ

iC3 ¼ 0

ð6:3Þ

Applying Kirchhoff’s current law (KCL) and the relationship of the winding currents then results in the following current expressions given in (6.4) and (6.5): N1 i01 þ ðN2  N3 Þi2 ¼ 0

ð6:4Þ

i01 ¼ IM

ð6:5Þ

Substituting (6.4) and (6.5) to (6.1) then leads to iC 1 ¼ 

N1 IM N3  N2

ð6:6Þ

The capacitor currents will change after progressing to Fig. 6.4c. D1 and D2 are conducting, while SW is blocking from t2 to t3. The currents through C2 and C3 change abruptly at t2 to: iC2 ðt2 Þ ¼ i3 ðt2 Þ  Io

ð6:7Þ

iC3 ðt2 Þ ¼ Iin þ iC2 ðt2 Þ  i1 ðt2 Þ

ð6:8Þ

Since the current through the leakage inductor LK will not change suddenly, i1 is still equal to zero at t2. Thus, the winding current is the same with that in the last stage.

126

6 Technology of DC-Link Voltage Spikes Suppression

i1 ðt2 Þ ¼ 0 i3 ðt2 Þ ¼

N1 IM N3  N2

ð6:9Þ ð6:10Þ

From (6.7) to (6.10), the following expressions can be obtained: iC2 ðt2 Þ ¼

N1 IM  Io N3  N2

iC3 ðt2 Þ ¼ Iin þ

N1 IM  Io N3  N2

ð6:11Þ ð6:12Þ

The currents through capacitors C1, C2, C3, and leakage inductor LK will change linearly until D2 is reverse-biased. Then the circuit enters the state in Fig. 6.4d, where D2 has stopped conduction. Therefore, the currents through capacitors can be obtained as iC1 ¼ i2

ð6:13Þ

iC2 ¼ Iin

ð6:14Þ

iC3 ¼ i1

ð6:15Þ

i3 ¼ iC 2 þ Io

ð6:16Þ

Applying KCL then results in

0

i1 ¼ i1 þ IM ¼ i2 þ i3

ð6:17Þ

The current relationship of coupled inductors should meet the following expression: N1 i01 þ N2 i2 þ N3 i3 ¼ 0

ð6:18Þ

Therefore, the current expressions of C1 and C3 can be obtained as iC1 ¼

ðN1 þ N3 ÞðIin  Io Þ þ N1 IM N1 þ N2

iC 3 ¼ 

ðN3  N2 ÞðIin  Io Þ þ N1 IM N1 þ N2

ð6:19Þ ð6:20Þ

Related current expressions for each capacitor can now be current-second integrated over a switching period, as expressed below:

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

Z t1

Z

t2

iCx dt þ

Z

¼

t3

t2 dT

Z

Z

0

t0

iCx dt þ

iCx dt þ

127

iCx dt t3

ða þ dÞT

iCx dt þ

dT

Z

T

ða þ dÞT

iCx dt

ð6:21Þ

¼0 2 where a ¼ t3 t T is the proportionality coefficient, x = 1, 2 or 3 is an index for the capacitors. Since interval I has been omitted, the shoot-through duty ratio d ¼ t2 t0 t2 t1 T  T can be obtained. Although currents iCx are variables during [t2, t3], their initial and final values can be obtained. Besides, their changing rates are proportional to that of the current through LK, which is a constant. Therefore, the integrals of iCx from t2 to t3 can be calculated. Eventually, the following expressions can be derived, from which currents through all components of the impedance network can be computed:

2 ð1  dÞ K

ð6:22Þ

ðN1 þ N3 Þ Iin N1

ð6:23Þ

1  ð1 þ KÞd Iin 1d

ð6:24Þ

a¼ IM ¼ Io ¼

N3 where K ¼ NN13 þ N2 is the turns ratio of the coupled inductor. From (6.22), it can be found that if the turns ratio K is less than 2, then a will bigger than 1 − d. That does not cause D2 to be reverse-biased during [t3, t0], which the operating principle of the LH-YSI-I is quite the same with the IYSI. However, in order to make full use of the coupled inductors, K is usually set to a value greater than 2.

6.2.3

Voltage Analysis

The equivalent circuits in Fig. 6.4a and b can be analyzed as a ST state with SW conducting from t0 to t2. The total voltage across N2 and N3 is clamped by C1 due to the conduction of SW. Thus, the relevant voltage expressions during intervals I and II can be written as

128

6 Technology of DC-Link Voltage Spikes Suppression

N1 N3  N2

ð6:25Þ

vLin ¼ ðVin þ VC2 Þ

ð6:26Þ

vLM ¼ VC1

Upon turning off SW, the first NST state is shown in Fig. 6.4c. From t2 to t3, Lin is clamped by the input source and C3 in series, while N2 and N3 are clamped by C1, C2, and C3. Together with other circuit features, the voltage across various inductors can be derived as vLM ¼ ðVC1  VC2  VC3 Þ

N1 N3  N2

vLin ¼ VC3  Vin vLK ¼ ðVC1  VC2  VC3 Þ

ð6:27Þ ð6:28Þ

N1 þ N3  VC2 N3  N2

ð6:29Þ

where VC3 are voltages across C3, and vLK is voltages across LK. From another point of view, because the current through LK increases linearly from zero at t2, its current i1 at t3 can promptly be expressed as 1 i1 ðt3 Þ ¼ 0 þ LK

Z

t3

vLK dt

ð6:30Þ

t2

Substituting (6.15), (6.20), (6.23) and (6.24) into (6.30) then leads to vLK ¼

K2 2ð1  dÞ2 ðK  1ÞT

Iin LK

ð6:31Þ

Then the NST state changes to Fig. 6.4d, where D2 is reverse-biased. Since N1, N2, and LK are clamped by C1 and C3 during [t3, t0], leakage LK and magnetizing LM will hence share the sum of VC1 and VC3 proportionally. These observations permit voltages across various inductors to be expressed as vLM ¼ ðVC1  VC2  VC3 þ vD2 Þ

N1 N3  N2

vLin ¼ VC3  Vin  vD2 vLK ¼

LK LK þ ð1 þ

¼ vD2  ðVC1  VC2

N2 N1 ÞLM

ð6:32Þ ð6:33Þ

ðVC3  VC1 Þ

N1 þ N3  VC3 þ vD2 Þ  VC2 N3  N2

ð6:34Þ

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

129

Since LK  LM, vLK in (6.34) can be approximated as zero from t3 to t0. Thus, by substituting (6.29) and (6.31) into (6.34), the voltage across D2 can be obtained as vD2 ¼

K2 2ð1  dÞ2 ðK  1Þ2 T

ð6:35Þ

Iin LK

By substituting numerical values to it, vD2 can also be proven to be very small and should be omitted during [t3, t0] to simplify the following analysis. Thus, it can be easily found that vLM and vLin during interval IV are the same with those during interval III, respectively. All derived voltage expressions for each inductor can follow-up to be volt-second integrated over a switching period T, in accordance to Z

t2 t0

Z

t0

vLx dt þ t2

Z vLx dt ¼

dT

Z vLx dt þ

0

T

vLx dt ¼ 0

ð6:36Þ

dT

where Lx represents LM or Lin. Finally, the voltages across C1, C2, and C3 can be obtained: VC1 ¼ ð1  dÞBVin

ð6:37Þ

VC2 ¼ dKBVin

ð6:38Þ

VC3 ¼ ð1  dKÞBVin

ð6:39Þ

where B ¼ 1ð1 1þ K Þd is the voltage gain and Vin is the input voltage. Therefore, the voltage gain of the LH-YSI-I is the same with that of IYSI [7]. And the DC-link voltage Vdc and peak ac output voltage ^vo of the inverter are expressed as Vdc ¼ BVin

ð6:40Þ

^vo ¼ BMVin

ð6:41Þ

These expressions have a common denominator, from which tunable ranges for duty ratio d and modulation index M are found as 0  d\dmax ¼ 1=ð1 þ KÞ; 0\M\Mmax ¼ 1  d

ð6:42Þ

Expressions for calculating the current and voltage stresses experienced by the components in the IYSI and the LH-YSIs have been summarized in Tables 6.1 and 6.2. Table 6.1 presents the characteristic comparison between LH-YSI-I, LH-YSI-II, LH-YSI-III and IYSI, while Table 6.2 introduces the parameters

130

6 Technology of DC-Link Voltage Spikes Suppression

Table 6.1 Comparison of voltage and current stresses one Parameters

IYSI

LH-YSI-I

LH-YSI-II

LH-YSI-III

B = Vdc/ Vin VC1 VC2 VC3 VD1 VD2 Iin IM

1/[1 − (1 + K)d]

1/[1 − (1 + K)d]

1/[1 − (1 + K)d]

(1 − d)BVin dKBVin (1 − dK)BVin (K − 1)BVin BVin P/Vin (N1 + N3)P/N1Vin

(1 − d)BVin dKBVin (K − 1)dBVin (K − 1)BVin BVin P/Vin (N1 + N3)P/N1Vin

(K − 1)dBVin dKBVin (1 − dK)BVin (K − 1)BVin BVin P/Vin (N1 + N3)P/N1Vin

|i1|

1/[1 − (1 + K) d] (1 − d)BVin dKBVin NA KBVin NA P/Vin (N1 + N3)P/ N1Vin P/(1 − d)Vin

|i2| |i3| iST

KP/Vin KP/Vin (1 + K)P/Vin

KP/(1 − d)(K − 1) Vin KP/Vin KP/Vin (1 + K)P/Vin

KP/(1 − d)(K − 1) Vin KP/Vin KP/Vin (1 + K)P/Vin

KP/(1 − d)(K − 1) Vin KP/Vin KP/Vin (1 + K)P/Vin

Table 6.2 Comparison of voltage and current stresses two Parameters

IYSI

LH-YSI-IV

LH-YSI-V

LH-YSI-VI

B = Vdc/ Vin VC1 VC2 VC3 VD1 VD2 Iin IM

1/[1 − (1 + K)d]

1/[1 − (1 + K)d]

1/[1 − (1 + K)d]

(K − 1)dBVin dKBVin (1 − dK)BVin (K − 1)BVin BVin P/Vin (N1 + N3)P/N1Vin

(K − 1)dBVin dBVin (1 − dK)BVin (K − 1)BVin BVin P/Vin (N1 + N3)P/N1Vin

(B − dKB − 1)Vin dKBVin (1 − dK)BVin (K − 1)BVin BVin P/Vin (N1 + N3)P/N1Vin

|i1|

1/[1 − (1 + K) d] (1 − d)BVin dKBVin NA KBVin NA P/Vin (N1 + N3)P/ N1Vin P/(1 − d)Vin

|i2| |i3| iST

KP/Vin KP/Vin (1 + K)P/Vin

KP/(1 − d)(K − 1) Vin KP/Vin KP/Vin (1 + K)P/Vin

KP/(1 − d)(K − 1) Vin KP/Vin KP/Vin (1 + K)P/Vin

KP/(1 − d)(K − 1) Vin KP/Vin KP/Vin (1 + K)P/Vin

comparison between LH-YSI-IV, LH-YSI-V, LH-YSI-VI, and IYSI. The expression of other LH-YSIs all can be obtained through the similar analysis with the mentioned analysis applied on the LH-YSI-I.

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

6.2.4

131

Switching Loss Analysis

The switching transient process of CISIs is very complex. During this process, it is tough to calculate the power losses using the original topology, because too many state variables are coupled together. To address above issues, a novel transient model has been built to analyze the power losses of the LH-YSI-I and IYSI. Figures 6.6 and 6.7 show the models of the LH-YSI-I and IYSI, respectively. The further detailed model build process will be covered in Chap. 7. As shown in Fig. 6.6, when SW turns off, the LH-YSI-I enters the NST state. The LK in Loop 2 will prevent the i1 to increase, and iD2 in Loop 1 will increase with the drop of iSW. Therefore, Loop 2 can be neglected during the turn-off transient. The model can be equivalent to a boost converter without parasitic inductor. The relevant turn-off waveforms of SW are shown in Fig. 6.8. WRSW is the consumed energy during turn-off transient and WCSW is the energy absorbed by parasitic capacitor of SW, which will be consumed when SW turns on. The energy WCD2, which is absorbed by the parasitic capacitor of D2 when D2 turns off, will be recycled by be parasitic capacitor of SW and voltage source VD2,ST. Therefore, the loss on SW during the switching transient can be obtained as

Fig. 6.6 Transient model build process of LH-YSI-I

vD2

Loop 2

+

Fig. 6.7 Transient model of the IYSI

−

−

+

Loop 1

+

iD2

−

D2

vLK

vD1

i1 LK VD1,ST

D1

vLK

vD1

i1 LK

D1

VD1,ST

1

VD2,ST

SW 1

Io

vdc

(K+1)Iin

K-1

K:1

iSW SW

vdc

Io

(K+1)Iin

132

6 Technology of DC-Link Voltage Spikes Suppression

Fig. 6.8 The turn-off waveforms of SW in the LH-YSI-I

SW ST

NST t

vD2

t

iSW

WCD2 WRSW + WCSW

vdc

t

BVin ta tb

  T PSWon;LHYSII þ PSWr;LHYSII ¼ WRSW þ WCSW ¼ Win þ WCD2  Wo

t

ð6:43Þ

where PSWr,LH-YSI-I and PSWon,LH-YSI-I are turn-off loss and turn-on loss of SW for the LH-YSI-I, respectively. Win is the input energy from the current source (K + 1) Iin − Io and Wo is the energy absorbed by VD2,ST. From Fig. 6.8, vD2 drops to zero at tb. Therefore, the energy of the parasitic capacitor of D2 drops to zero at tb. The following expression can be obtained as Z WCD2 ¼

tb

vD2 ðtÞiD2 ðtÞdt

ð6:44Þ

ta

Substituting (6.44) to (6.43) then yields to Z WCD2 ¼

tb

vD2 ðtÞiD2 ðtÞdt

ð6:45Þ

ta

As shown in Fig. 6.7, when SW turns off, the IYSI enters the NST state. The model can be equivalent to a boost converter with parasitic inductor LK. The relevant turn-off waveforms of SW are shown in Fig. 6.9. During [ta, tb], the energy absorbed by parasitic capacitor of SW is WCSW1 and energy loss is WRSW1. The parasitic capacitor of D1 is discharged and LK is charged. The energy absorbed by LK is WL0. During [tb, tc], vLK is high and the current i1 increases a lot. The parasitic capacitor of D1 is discharged during this interval. The WC, which has been absorbed by parasitic capacitor of D1 when D1 turns off, is recycled to the other components. The energy absorbed by parasitic capacitor of SW is WCSW2 and the consumed

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits Fig. 6.9 The turn-off waveforms of SW in the IYSI

133

SW ST

NST t

vLK t vdc

BVin t

iSW

WRSW2 + WCSW2

WRSW1+WCSW1

t i1

vD1

Iin/(1−d) WL1 KBVin

WL2 WL0

t

tα tβ tγ tδ

t

energy is WRSW2. But iSW decrease a lot during this subinterval. The energy absorbed by LK during this interval is represented by WL1. During [tc, td], i1 is equal to [(K + 1)Iin − Io]/K = Iin/(1 − d) at tc. The SW is fully turned off. The D1 turns on and the parasitic capacitor of D1 is shorted. The extra energy of parasitic capacitor of SW will gradually transmit to LK. The energy absorbed by LK during this interval is represented by WL2. WL2 will circuited back and forth between the LK and parasitic capacitor of SW after td. The parasitic loss elements in the circuit will cause the ringing amplitude to eventually decay to zero. Therefore, WL2 can be viewed as part of the turn-off loss of SW. Therefore, the switching losses on SW of the IYSI can be obtained as   T PSWon;IYSI þ PSWr;IYSI ¼ WRSW1 þ WRSW2 þ WL2 þ WCSW1 ¼ Win0 þ WC  Wo0  WL1  WL0

ð6:46Þ

where PSWr,I−YSI is turn-off loss, and PSWon,I−YSI is the turn-on loss of SW in the IYSI. Win0 is the energy input from the current source (K + 1)Iin − Io and Wo0 is the energy absorbed by VD,ST.

134

6 Technology of DC-Link Voltage Spikes Suppression

From Fig. 6.9, vD1 nearly drops to zero at td; thus, the energy of parasitic capacitor of D1 nearly drops to zero at tc which can be written as Z WC 

tc

vD1 ðtÞi1 ðtÞdt

ð6:47Þ

ta

Substituting (6.47) to (6.46) then yields to   T PSWon;IYSI þ PSWr;IYSI 

Z

tc ta

Z ¼

tc



 KIin  Ki1 ðtÞ vdc ðtÞdt 1d

ð6:48Þ

iSW ðtÞvdc ðtÞdt

ta

It can be easily found that the form of (6.48) is the same with (6.45). However, the calculation results of (6.48) and (6.45) are obviously different. The main reasons are as follows: 1. The turn-off time duration of SW in the IYSI is typically several times of that of the LH-YSI-I. 2. The IYSI have great voltage spike, which causes the maximum vdc reach a high value. However, the DC-link voltage of the LH-YSI-I is well clamped. 3. As shown in Fig. 6.23, vdc of the IYSI is a convex curve and will reach its maximum value before iSW reaches zero. The i1 is a concave curve during the turn-off transient of SW, which leads iSW of the IYSI to convex curve at the same time, while vdc and iSW are linear curve in the LH-YSI-I. Therefore, the multiply of vdc and iSW of IYSI is greater than that of the LH-YSI-I. As the turn-off time duration of the IYSI is small, the peak value of voltage spike is high. As the peak value of voltage spike of the IYSI is small, the turn-off time duration is long. The huge voltage will decrease during the charging time of LK. Thus, the switching loss on the SW of the IYSI may be several times of that of the LH-YSI-I as shown in the experimental results.

6.2.5

Simulation and Experimental Results

Simulations and experiments have been performed with the IYSI and the LH-YSI-I. To facilitate the comparison, the same parameters listed in Table 6.3 are used in the two inverters and the inductances of N1, N2, and N3 are L1 = 0.3669 mH, L2 = 1.4215 mH, and L3 = 0.3661 mH. The leakage inductances of N1, N2, and N3 are LK1 = 2.29 lH, LK2 = 1.83 lH, and LK3 = 7.77 lH. The results are described as follows. As shown in Fig. 6.10, the key current waveforms closely match with the theoretical waveform illustrated in Fig. 6.6. During the transient of switching from ST

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits Table 6.3 System parameters of LH-YSI-I

135

Parameter

Value/part number

Minimum input voltage Maximum input voltage Output voltage (peak to peak) Dc-link voltage Capacitances C1 and C3 Capacitances C2 Inductances Lin Switching frequency Turns ratio Core Switches Diodes D1 and D2 Filter inductance Lf Filter capacitance Cf

60 V 200 V 160 V 200 V 470 lF 100 lF 4.3 mH 10 kHz 40:40:80 (K = 3) C055863A2 IRGP4062DPbF 30EPH06PBF 5.6 mH 4.7 lF

state to NST state, the currents iC1, iC2, i1, i2, and i3 of I-YSI change rapidly, which induces great voltage spikes at the DC-link, but the capacitors currents and coil currents of LH-YSI-I change linearly during period III. Experimental testing of a 200 W prototype controlled by a TMS320F2812 DSP has been built and shown in Fig. 6.11. It can be configured as IYSI and LH-YSI-I using the same parameters provided in Table 6.3. Its coupled inductor has also been loosely wound to better demonstrate the effects caused by leakage inductances. Figure 6.12 shows the DC-link voltage, voltages, and currents of diodes. As shown in Fig. 6.12a, the current iD1 that flows through diode D1 and the winding N1 changes immediately to another value when entering into NST state. Thus, the DC-link voltage spikes of IYSI can reach 530 V, which is much higher than its stabilized value (194 V). However, current iD1 varies smoothly as shown in Fig. 6.12b; thus, the DC-link voltage spikes of LH-YSI-I can hardly be found and its DC-link voltage reaches 197 V. Moreover, both the voltage stresses across D1 and D2 in the LH-YSI-I are less than that of D1 in the I-YSI, which matches well with the theoretical analysis. According to (6.31) and (6.35) and using the parameters from Table 6.3, vLK during [t2, t3] and vD2 during [t3, t0] are determined as 7.79  104LK and 3.89  104LK, respectively. Their values are thus only a few mV, since the leakage LK is usually from 100 nH to 10 lH. Therefore, it is expected to be unnoticeable, as verified by the third trace in Fig. 6.12b. Furthermore, the ringing effect of D1 in the LH-YSI-I is obviously eliminated when compared with the IYSI. The ringing phenomenon is nearly invisible in diode D2, because the voltage vD2 is clamped by C2 and C3 in series when D2 is reverse-biased. The clamp circuit proposed in [11] has also been researched to make comparison with the LH-YSI-I. By replacing the two-winding coupled inductor in [11] with the

136

6 Technology of DC-Link Voltage Spikes Suppression

(a) 15

10

i2 5

iC2

10

0 5 -5 0

-10 -15 0.09906

0.09916

-5 0.09906

0.09916

Time(s)

Time(s)

10

iD2

10

5 5 0

iC3 0

-5 0.09906

0.09916

0.09916

0.09906

Time(s)

Time(s)

6

15

i1 4

10

2

5

0

0

-2 0.09906

0.09916

i3

-5 0.09906

0.09916

Time(s)

Time(s)

(b) 15

i3 10 5 0 -5 0.09906

t0

t1

t2

t3 t0 t1 Time(s)

t2

t3 0.09916

Fig. 6.10 Simulated iD2, iC2, iC3, i1, i2 and i3 of a I-YSI (red) and b LH-YSI-I (blue) (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

Coupled Inductors

Auxiliary Power

S1 C3

137

Lf

S2

S3

S4

D1

C2

Cf C1

D2

Lin Vo

Vin Fig. 6.11 Laboratory setup of LH-YSI-I

(a)

(b) Vdc :200V/div

Vdc :200V/div

0

0 t(2ms/div)

t(2ms/div)

Vdc :200V/div

0 0

Vdc :200V/div vD1:500V/div

0 0 vD2:500V/div

0 vD1:500V/div

0 iD1:4A/div

0

iD1:4A/div

t(10μs/div)

Linear area

0 iD2:8A/div

t(10μs/div)

Fig. 6.12 Experimental Vdc, vD1, vD2, iD1 and iD2 of a IYSI and b LH-YSI-I (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

Y-type three-winding coupled inductor, the improved three-winding CZSI can be obtained as shown in Fig. 6.13. As shown in Fig. 6.14, the improved three-winding CZSI cannot eliminate fully the voltage spike, and its DC-link voltage spikes reaches 350 V. Therefore, the LH-YSI-I can eliminate DC-link voltage spikes better.

138

6 Technology of DC-Link Voltage Spikes Suppression

C2 D1 N3

N1

Vin

va vb

vdc

N2

D2

S5

S3

S6

C1

vc S2

S4

Load or grid

S1

Filter

Lin

Fig. 6.13 The improved three-winding CZSI

0 Vdc:200V/div t(2ms/div) Fig. 6.14 The DC-link voltage of improved three-winding CZSI (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

Figure 6.15 shows the input and output waveforms of the two inverters. The double-line-frequency ripples can be seen from input currents of both circuits [13, 14]. But the ripples are slightly smaller in the LH-YSI-I. The peak AC output voltages of IYSI have been read as 154 V and those of LH-YSI-I have been read as 155 V. Both values are smaller than their common theoretical value of 160 V. The voltage drop should be attributed to the reduction of effective ST duty ratio caused by leakage inductances and ESRs [8].

(a)

(b)

0

Vin:100V/div

0

vo:100V/div

0 Iin:3A/div

0

0

0

0

0 io:2A/div

t(10ms/div)

Vin:100V/div

vo:100V/div

Iin:3A/div

io:2A/div

t(10ms/div)

Fig. 6.15 Experimental input voltages Vin, input currents Iin, output voltages vo, and output currents io of a IYSI and b LH-YSI-I (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

139

The capacitors voltages can be read from Fig. 6.16, like VC1 = 169 V and VC2 = 86 V from Fig. 6.16a for the IYSI; and VC1 = 168 V, VC2 = 87 V, and VC3 = 109 V from Fig. 6.16b for the LH-YSI-I. Figure 6.17 shows the winding currents of the coupled inductor. The winding currents of the IYSI jump rapidly at the beginning of NST, while the winding currents of the LH-YSI-I change more gradually in NST state. The experimental results of LH-YSI-I with minimum (60 V) and maximum (200 V) input voltage have been shown in Fig. 6.18. To obtain 110 Vrms output voltage requires ST duty ratio to be d = 0.175 and modulation index M = 0.82 if input voltage is 60 V. Similarly, to obtain 110 Vrms output voltage requires ST duty ratio to be d = 0 and modulation index M = 0.8 if input voltage is 200 V. Figure 6.19 shows the measured efficiencies of LH-YSI-I with 60 and 200 V input voltage. The maximum efficiencies with 60 V and 200 V input voltage can reach 84.3% and 93.4%, respectively. Figures 6.20 and 6.21 show the experimental results with 300 W and 400 W output power, respectively. As the power level increases, the voltage spikes of IYSI will exceed the 600 V, while the voltage spikes of LH-YSI-I stay below 300 V. Figure 6.22 shows the transient waveforms when SW turns off. It can be seen that the experimental results are consistent with the theoretical analysis shown in Figs. 6.8 and 6.9. In the IYSI, the time interval of [ta, td] is 300 ns and the peak DC-link voltage is 380 V, while in the LH-YSI-I, the time interval of [ta, tb] is 100 ns and the peak dc-link voltage is 230 V. Therefore, the switching loss on the 380V IYSI may reach 300ns 100ns  230V  k  5k times of the switching loss of the LH-YSI-I, where k > 1 is the multiply factor when taking the reason 3 mentioned in last

(a)

(b)

VC1:100V/div

0

VC1:100V/div

0 VC2:50V/div

0 VC2:50V/div

0

0

t(10ms/div)

VC3:100V/div

t(10ms/div)

Fig. 6.16 Experimental capacitors voltages of a IYSI and b LH-YSI-I (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

140

6 Technology of DC-Link Voltage Spikes Suppression

(a) 0 0

(b) i1:2.4A/div ST state

0

i1:2.4A/div ST state

0

i2:5A/div

i2:5A/div

NST state

NST state i3:4A/div

i3:4A/div

0

0

t(10μs/div)

t(10μs/div)

Fig. 6.17 Experimental winding currents i1, i2 and i3 of a I-YSI and b LH-YSI-I (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

(a) 0

(b) Vin:100V/div

0 0

vo:100V/div

Iin:3A/div

0

0

0

0

0 io:2A/div

t(10ms/div)

Vin:200V/div

Iin:3A/div

vo:100V/div

io:2A/div

t(10ms/div)

Fig. 6.18 Experimental input voltages Vin, input currents Iin, output voltages vo, and output currents io of LH-YSI-I with a 60 V and b 200 V input voltage (P = 200 W)

subsection into consideration. Actually, if applying the numerical method to calculate the loss of the IYSI, the switching loss on IYSI may reach 10–13 times of the switching loss of LH-YSI-I. Figure 6.23 shows the measured efficiencies of the IYSI and LH-YSI-I and the improved three-winding CZSI. The efficiency of the LH-YSI-I is only slightly lower than the improved three-winding CZSI. But the efficiency of the LH-YSI-I is higher than the IYSI. It is because that the leakage energy recycled by the LH-YSI-I exceeds the loss on the additional components. Besides, as the power increases, the efficiency difference between the LH-YSI-I and the IYSI becomes larger. Therefore, the LH-YSI-I is more appealing application cause that it has nearly no voltage spikes and higher efficiency.

6.2 Dual Diodes Capacitor–Diode Absorbing Circuits

141

Fig. 6.19 Efficiency comparison of the LH-YSI-I with 60 and 200 V input voltage

Fig. 6.20 Experimental Vdc of a IYSI and b LH-YSI-I (P = 300 W, Vin = 80 V, d = 0.15, M = 0.8)

(a) Vdc:200V/div

0 t(2ms/div)

(b) Vdc:200V/div 0 t(2ms/div)

6.2.6

Extension of Topologies Range

This dual diodes capacitor–diode absorbing circuits can also be implemented into other CISIs not only YSI. For example, the two-phase topologies shown in Fig. 6.24 can be obtained when these absorbing circuits are applied in improved-trans-Z-source inverter, the LCCT-Z-source inverter, and the asymmetrical C-source inverter, respectively. All the inverters inherit all advantages of the original inverters, while generate no voltage spikes at their DC-links.

142

6 Technology of DC-Link Voltage Spikes Suppression

Fig. 6.21 Experimental Vdc of a IYSI and b LH-YSI-I (P = 400 W, Vin = 80 V, d = 0.15, M = 0.8)

(a) Vdc:200V/div

0 t(2ms/div)

(b) Vdc:200V/div 0 t(2ms/div)

(a)

(b) Vdc(200V/div) BVin

0 Vdc(100V/div)

0 0

0

Iin/(1–d) iD1(2A/div)

0 0

KBVin

tβ tα

tγ tδ

0

vD2(200V/div)

vD1(400V/div) iD2(8A/div) iD1(4A/div)

0 ta tb

t(500ns/div)

t(500ns/div)

Fig. 6.22 Transient Vdc, vD1, vD2, iD1, and iD2 of a IYSI and b LH-YSI-I (P = 200 W, Vin = 80 V, d = 0.15, M = 0.8)

6.3

Single Diode Capacitor–Diode Clamping Circuits

The extended quasi-Y-source inverter (E-QYSI) mentioned in the last chapter is one of the examples of single diode capacitor–diode clamping circuits. Therefore, the introduction of E-QYSI will not be repeated there. Only part of the experimental results is presented in the following. Figure 6.25 shows the DC-link voltages, diode voltages, and their currents measured from the two inverters during their NST-to-ST transitions. As observed, the loss of ST duty ratio is Δd1T  Δd2T  200 ns for the E-QYSI, which is smaller than Δd1,cT  Δd2,cT  400 ns for the YSI. In terms of percentage, they are 2.67% for the E-QYSI and 4% for the YSI. The results are thus in good agreement with earlier theoretical analysis.

6.3 Single Diode Capacitor–Diode Clamping Circuits

143

Fig. 6.23 Efficiency comparison of the LH-YSI-I (-◊-), I-YSI (-D-), and improved three-winding CZSI (-O-)

Figure 6.26 shows voltages across capacitors and DC-link voltages of both inverters, where noticeably smaller DC-link voltage spikes have been observed with the E-QYSI, even though it uses the same coupled inductor as the YSI. Across the extra capacitor C2 of the E-QYSI, its recorded voltage of about 85 V is also comparably smaller than that seen across C1. Its addition will hence hardly affect operational reliability of the E-QYSI. Therefore, the introduction of single diode capacitor–diode clamping circuits can not only suppress the DC-link voltage spikes at some level and but also eliminate the duty loss.

6.4

Embedded Capacitor–Diode Absorbing Circuits

Similarly with the first absorbing circuits, the embedded capacitor–diode absorbing circuits can also restrain the DC-link voltage spikes fully. The high-efficiency T-source inverter (HE-TSI) shown in Fig. 6.27 is one of the examples of embedded capacitor–diode absorbing circuits. HE-TSI can flatten the DC-link voltage spikes without compromising gain, which only adds one diode and one capacitor to the conventional TSI. It therefore inherits all advantages of the TSI, but with no DC-link voltage spikes generated, as demonstrated experimentally next. As shown in Fig. 6.27, C1, C2, and D2 form the absorbing circuit. Capacitor C1 is however a component already included in the original TSI. Thus, the only extra components are C2 and D2, since they cannot be found in the original TSI. Despite that, both TSI and HE-TSI can enter either the ST or NST state. Description of each state, divided into several intervals, is provided below.

144

6 Technology of DC-Link Voltage Spikes Suppression

C2

(a) Lin

D2

D1

N1

N2 S1

Lf

Vin

C1

C3

Cf

vdc S2

S4

S1

S3

AC Load

C2

(b) Lin

D2

D1

N1 Lf

N2

Vin

C3

Cf

vdc C1

S2

S4

S1

S3

AC Load

C2

(c) Lin

Vin

S3

D2

N1

D1

Lf

N2 C3

Cf

vdc C1

S2

AC Load

S4

Fig. 6.24 Topologies with dual diodes capacitor–diode absorbing circuits

6.4.1

Operational States

Figure 6.28 shows equivalent circuits of the HE-TSI, whose inverter bridge and ac load have been simplified to a switch SW and a current source in parallel. Its coupled inductor has also been simplified to a magnetizing inductance LM in parallel with one winding of a two-winding ideal transformer. The differences between an ideal transformer and a coupled inductor are the former has an infinite magnetizing inductance, while the latter has a finite magnetizing inductance LM that needs not be overly large. Instead, it should be designed to a value, whose corresponding current ripple is acceptable to the HE-TSI, just like the usual design of a single-winding inductor.

6.4 Embedded Capacitor–Diode Absorbing Circuits

0

Vdc Δd1,cT = 400 ns

0

iD1

0

iD1 (10 A/div)

VD1

0

VD1 (500 V/div), Vdc(100 V/div)

(b) iD1

iD1 (10 A/div)

VD1 (500 V/div), Vdc(100 V/div)

(a)

145

VD1

0 Vdc Δd1,cT = 200 ns

0

t (1 μs/div)

t (1 μs/div)

Fig. 6.25 Experimental results iD1, VD1, and Vdc of a YSI and b E-QYSI

(b)

Vin

Vin, VC1, Vdc(100 V/div)

Vin, VC1, Vdc(100 V/div)

(a) 0

548V VC1

0

Vdc

182V

0

0 0

Vin VC2 VC1 290V

0

Vdc

185V

0

t (20 μs/div)

t (20 μs/div)

Fig. 6.26 Experimental results Vin, VC1, VC2, and Vdc of a YSI and b E-QYSI

C2 D1

L1

D2

L2 S3

Vin

S1 Lf

C1

Cf S4

AC Load

S2

Fig. 6.27 Topology of high-efficiency T-source inverter

Besides, a small leakage inductance can be added in series with each winding, since perfect coupling between the windings is not realizable in practice. All leakage inductances can then be reflected to the same winding N1 (with LM in

146

6 Technology of DC-Link Voltage Spikes Suppression C2

iC2

(a) D1

LK i1 i1 N1

vD1

VLK

vD2

LM IM vLM

Vin

C1

VC1

SW V dc

Io

D1

LK i1 i1 N1

iD2 D2

vD1

VLK

vD2

LM IM vLM

Vin

C1

C2

iC2

(d)

D1

LK i1 i1 N1

VC2 N2 iD2 D2 i2

vD1

VLK

vD2

LM IM vLM

Vin

C1

VC1

SW V dc

Io

D1

LK i1 i1

N1

iD2 D2

vD1

VLK

LM

vD2

IM vLM

Vin

Vin

D1

LK i1 i1 N1

vD1

VLK

vD2

IM

vLM C1

VC1 iC1

SW V dc

Io

C2

C1

VC2 N2

VC1

i2

SW V dc

Io

SW V dc

Io

Vin

C2

iC2

(f)

VC2 N2 iD2 D2 i2

LM

i2

iC1

C2

iC2

VC1

iC2

iC1

(e)

VC2 N2

iC1

iC1

(c)

C2

iC2

(b)

VC2 N2 iD2 D2 i2

D1

LK i1 i1 N1

VC2 N2 iD2 D2 i2

vD1

VLK

vD2

LM IM

vLM C1

VC1

SW V dc

Io

iC1

Fig. 6.28 Equivalent circuit of the HE-TSI: a ST state [t0, t1], b ST state [t1, t2], c ST state [t2, t3], d NST state [t3, t4], e NST state [t4, t5], and f NST state [t5, t0]

parallel), and approximately summed together as a single lumped inductance LK in series with that winding. Like all inductances, current through LK cannot step abruptly, but since LK is small, sizable variation of its current in a switching period will still occur. In contrast, LM, C1, and C2 are usually large enough, such that current through LM and voltages across C1 and C2 can be assumed as constants in each switching period. Key waveforms incorporating these assumptions can hence be drawn in Fig. 6.29 for the HE-TSI, where each switching period has been divided into six intervals under either ST or NST state. Corresponding equivalent circuits of the six intervals are given in Fig. 6.28, whose descriptions are presented as follows. (1) ST State [t0, t1]: Switch SW turns on at t0. Its voltage starts to fall, while its current increases gradually from zero, since it flows from current paths with at least an inductance in series. As for D1 and D2, they continue to conduct and block, respectively. Particularly, for D1, its current i1 falls gradually because of leakage LK in series. It

6.4 Embedded Capacitor–Diode Absorbing Circuits Fig. 6.29 Key waveforms of the HE-TSI

147

GSW t iC1

t iC2

t i1

t i2 t iD2

t vD1

t vD2

t Vdc

t0 t1 t2

t3 t4

t5

t0 t 1 t 2

t3

t

continues for only a very short duration, since this interval is merely for representing switching transitions of semiconductors. [t1, t2]: Voltage across SW drops to zero at t1, while its current continues to rise. Winding N1 is thus clamped by voltages across the input source and C2, while N2 is clamped by voltage across C1. Meanwhile, D2 continues to block because of

148

6 Technology of DC-Link Voltage Spikes Suppression

positive reverse voltage VC1 + VC2 across it, while D1 retains its conduction with its current i1 decreasing rapidly through LK. [t2, t3]: Switch SW and D2 continue their conduction and reverse-bias, respectively, while i1 through D1 finally reaches zero at t2. That also causes current through C2 to be zero and LM to be linearly charged by winding N1. Energy to N1, in turn, comes from the discharging of C1 to N2. This continues until t3, which also is the longest among the three ST intervals, in which all semiconductors have already reached their intended states. (2) NST State [t3, t4]: Switch SW turns off at t3, causing its voltage to rise and its current to step-decrease abruptly, since inductive current i2 can instantaneously be directed to charge C2 and power the load. The former causes D2 to conduct with its reverse voltage brought down to zero abruptly. Simultaneously, D1 begins to conduct, but with its current i1 rising gradually, even though rapidly, due to the initial charging of LK in series. This initial charging ends only after a very short interval, since LK is usually very small. Meanwhile, C1 continues to discharge to the load. [t4, t5]: Switch SW remains off, while D1 and D2 retain their conduction. Equivalent circuit of this interval is thus the same as the previous interval, but with i1 increasing and i2 decreasing less steeply. Meanwhile, C1 and C2 become in series due to the conduction of D2. They can hence clamp the DC-link voltage Vdc, which now does not experience voltage spikes at ST to NST crossovers. [t5, t0]: Current through D2 finally drops to zero at t5, causing it to block. Meanwhile, D1 continues to conduct, allowing C1, C2, and the input source to appear across N1, N2, and LK for clamping their total voltage. Besides, the DC-link voltage across SW is no longer equal to the combined voltage of C1 and C2 in series, since it also includes the reverse voltage of D2. This reverse voltage is however very small, as demonstrated later. There will hence only be a small voltage drop at the DC-link, upon entering this interval at t5.

6.4.2

Current Analysis

To avoid unnecessarily complex current and voltage expressions, equivalent circuits in Fig. 6.28a and d can be neglected, since their durations represent very short switch transitional times. Their circuit expressions are also similar to those of Fig. 6.28f and c. Figure 6.28 can therefore be simplified to those four circuits in Fig. 6.30. Key waveforms with four subintervals corresponding to the four simplified circuits can also be drawn in Fig. 6.31, where winding currents i1 and i2 have been assumed to change linearly during [t4, t5]. In cases where the coupled inductor has been designed properly or LK being very small, interval [t0, t2] occupied by the circuit in Fig. 6.30a is equally very short. Thus, the circuit expressions of interval [t0, t2] can hence be omitted from the mathematical analysis, since energies of the passive components hardly change

6.4 Embedded Capacitor–Diode Absorbing Circuits C2

iC2

(a) L K i1 i1 VLK

LM IM

Vin

VC2 N2

N1

149

LK i1 i1

i2

vD1

vD2

vLM C1

VC1

iST

C2

iC2

(b)

VLK

VC2 N2

N1 LM

IM vLM

Vin

C1

VC1

VC2 N2

LK i1 i1 N1 VLK Vin

(d)

C2

iC2

i2

LM IM vLM

C1

iST

iC1

iC1

(c)

i2

vD2

VC1 Vdc

Io

Vin

iC1

C2

iC2

LK i1 i1

N1

VLK

LM IM vLM

VC2 N2

i2

vD2 C1

VC1 Vdc

Io

iC1

Fig. 6.30 Simplified equivalent circuits of the HE-TSI: a ST state [t0, t2], b ST state [t2, t4], c NST state [t4, t5], and d NST state [t5, t0]

during such short duration. Therefore, beginning with Fig. 6.30b, where D1 and D2 are blocking and SW is conducting from t2 to t4, related current expressions can be derived as iC1 ¼ i2

ð6:49Þ

iC2 ¼ 0

ð6:50Þ

N1 i01 þ N2 i2 ¼ 0

ð6:51Þ

i01 ¼ IM

ð6:52Þ

By next substituting (6.51) and (6.52) to (6.49), current through C1 can be found as iC 1 ¼ 

N1 IM N2

ð6:53Þ

The conditions change in Fig. 6.30c with D1 and D2 conducting and SW blocking from t4 to t5. Currents through C1 and C2 then start to change abruptly at t4 with their expressions given as

150 Fig. 6.31 Simplified key waveforms of the HE-TSI

6 Technology of DC-Link Voltage Spikes Suppression

GSW

t

iC1

t iC2

t i1

t i2

t iD2

t vD1

t vD2

t Vdc

t0 t2

t4

iC1 ðt4 Þ ¼ Io i C 2 ðt 4 Þ ¼

N1 IM  Io N2

t5

t0 t 2

t4

t

ð6:54Þ ð6:55Þ

The conditions again change in Fig. 6.30d with D2 reverse-biased and currents through capacitors and windings remained nearly constant. Related current expressions can thus be derived as

6.4 Embedded Capacitor–Diode Absorbing Circuits

151

iC1 ¼ i1  Io

ð6:56Þ

iC2 ¼ i1

ð6:57Þ

i2 ¼ iC1

ð6:58Þ

Two other expressions applicable to winding currents of all circuits in Fig. 6.30 can be determined as N1 i01 þ N2 i2 ¼ 0

ð6:59Þ

i1 ¼ i01 þ IM

ð6:60Þ

From (6.56) to (6.60), currents through C1 and C2 can then be determined as N1 ðIM  Io Þ N1  N2

ð6:61Þ

N2 N1 Io  IM N1  N2 N1  N2

ð6:62Þ

iC 1 ¼ iC 2 ¼

All current expressions of C1 and C2 can now be current-second integrated over a switching period to give Z t0

Z

t4

t5

iCx dt þ

Z

¼ 0

t4 dT

Z

t0

iCx dt þ

Z

iCx dt þ

iCx dt t5

ða þ dÞT

iCx dt þ

dT

Z

T

ða þ dÞT

iCx dt

ð6:63Þ

¼0 4 where a ¼ t5 t T , and x = 1 or 2 is the index of each capacitor. Eventually, the following expressions can be derived, from which currents through all components of the impedance network can be computed:

a¼ IM ¼

2N2 ð1  dÞ N1

ð6:64Þ

N2 Kð1  dÞ Io N1 ð1  KdÞ

ð6:65Þ

where K¼ N1 Nþ2 N2 is the winding factor of the coupled inductor, and d is the ST duty ratio.

152

6 Technology of DC-Link Voltage Spikes Suppression

Noting too that output power can be expressed as Po ¼ Vo Io , and IM can eventually be derived as IM ¼

6.4.3

N2 Kð1  dÞ Po N1 Vin

ð6:66Þ

Voltage Analysis

Like in the earlier subsection, equivalent circuits in Fig. 6.30a and b can be analyzed as a single ST state with SW conducting from t0 to t4 and voltage across N2 clamped by C1. Relevant voltage across LM during the ST state can thus be determined as vLM ¼

N1 VC N2 1

ð6:67Þ

On the other hand, the first NST state in Fig. 6.30c has both diodes conducting and SW blocking from t4 to t5. Winding N1 is thus clamped by the input source and C2, and voltages across various inductances can be derived as vLM ¼  vLK ¼ Vin þ

N1 VC N2 2

N1 VC  VC1 N2 2

ð6:68Þ ð6:69Þ

From (6.69) and understanding that current through LK starts to increase linearly from zero at t4, its value at t5 can be expressed as vLK ¼ Vin þ

N1 VC  VC1 N2 2

ð6:70Þ

where LK is leakage inductance of the coupled inductor. Therefore, vLK can be derived as vLK ¼

LK i1 aT

ð6:71Þ

The NST conditions then change to those in Fig. 6.30d with D2 reverse-biased, and voltages across leakage LK and magnetizing LM are given as

6.4 Embedded Capacitor–Diode Absorbing Circuits

vLM ¼

153

N1 ðvD2  VC2 Þ N2

ð6:72Þ

N1 ðvD2  VC2 Þ  VC1 þ vD2 N2 ¼ bðVin þ VC2  VC1 Þ

vLK ¼ Vin 

where b ¼

LK , N LK þ ð1N2 ÞLM

ð6:73Þ

which in practice is close to zero from t5 to t0, since

1

LK  LM. Kirchhoff’s voltage law subsequently leads to voltage across D2 being expressed as vD2 ¼

N2 N1 ðVin þ VC  VC1 Þ N1  N2 N2 2

ð6:74Þ

Comparing (6.69) and (6.74), the term within parentheses of (6.74) resembles vLK when in the first NST interval represented in Fig. 6.30c, which in turn can be substituted by the expression in (6.71). This leads to vD2 ¼

N2 N2 LK i1 vLK ¼ N1  N2 ðN1  N2 ÞaT

ð6:75Þ

from which vD2 can be proven to be very small by substituting numerical values. Intervals [t4, t5] and [t5, t0] can thus be combined, since all their inductive voltages are now approximately equal. Applying volt-second balance to LM over a switching period T then leads to Z t0

t2

Z vLM dt þ t2

t0

Z vLM dt ¼

dT

Z vLM dt þ

0

T

vLM dt ¼ 0

ð6:76Þ

dT

Upon solving, voltages across C1 and C2 can be obtained as VC1 ¼ ð1  dÞBVin

ð6:77Þ

VC2 ¼ dBVin

ð6:78Þ

1 where B ¼ 1Kd is voltage gain of the HE-TSI, and Vin is its input voltage. These expressions eventually lead to the DC-link voltage Vdc and peak ac output voltage ^vo of the inverter being expressed as

Vdc ¼ BVin

ð6:79Þ

^vo ¼ BMVin

ð6:80Þ

154

6 Technology of DC-Link Voltage Spikes Suppression

Table 6.4 Voltage gain and winding factor of HE-TSI with different turns ratio

K

dmax

Voltage gain

2 3 4 5 6 7

1/2 1/3 1/4 1/5 1/6 1/7

(1 (1 (1 (1 (1 (1

− − − − − −

2d)−1 3d)−1 4d)−1 5d)−1 6d)−1 7d)−1

N1:N2 (1:1) (2:1) (3:1) (4:1) (5:1) (6:1)

where M is the modulation index, which together with duty ratio d, must satisfy M þ d\1. Moreover, since B > 0, the following inequality must always be met: 1  Kd [ 0

ð6:81Þ

Thus, both maximum duty ratio and attainable gain are dependent on K. Some example values for demonstrating it are given in Table 6.4.

6.4.4

Voltage and Current Stress Analysis

Expressions for calculating voltage and current stresses of components of the TSI and HE-TSI have been summarized in Table 6.5, where subscript c has been added to notate TSI. And the efficiency of two topologies in this table is assumed to be 1. The first row confirms that if winding and boost factors are set the same or K = Kc and B = Bc, duty ratios demanded by both inverters are equal. Other rows confirm that their voltages across C1, winding currents i2, and shoot-through currents iST are all equal. However, voltage across D1 of the HE-TSI is smaller than that of the TSI, while winding current i1 of the HE-TSI is only slightly higher than that of the TSI. It is thus pertinent to conclude that HE-TSI experiences reduced stress across D1, while those of other components remain nearly unchanged. More importantly, HE-TSI prevents large voltage spikes from occurring at the DC-link, as explained earlier. This has not been captured by the expressions in Table 6.5, where switch transitional transients have not been considered.

6.4.5

Simulation and Experimental Results

Simulations and experiments have been performed with the TSI and HE-TSI for verifying demonstrated theoretical analysis. Parameters used for the verification are given in Table 6.6, while results obtained are described below. To compare more convincingly, coupled inductors with the same leakage and magnetizing inductances have been used for simulating both inverters. Their

6.4 Embedded Capacitor–Diode Absorbing Circuits

155

Table 6.5 Comparison of voltage and current stresses Parameter for comparison

TSI

HE-TSI

B = Vdc/Vin VC1 VC2 VD1 VD2 Io i1 i2 iST

1/(1 − Kcdc) (1 − dc)BcVin NA (Kc − 1)dcBcVin NA Po/BcVin Po/Vin Kc(1 − dc)Po/Vin (1 − dc)dcPo/Vin

1/(1 − Kd) (1 − d)BVin dBVin (K − 2)dBVin dBVin Po/BVin (K − 2)Po/[(K − 1)Vin] K(1 − d)Po/Vin (1 − d)dPo/Vin

Table 6.6 System parameters of HE-TSI

Parameter

Value/part number

Input voltage Output voltage (peak to peak) Load resistance Capacitors C1 and C2 Switching frequency Turns ratio Core Switch Diode D1 and D2 Filter inductor Lf Filter capacitor Cf

80 V 320 V 60 X (200 W) 470lF 10 kHz 60:20 C055087A2 IRGP4062DPbF 30EPH06PBF 5.6 mH 4.7 lF

common winding factor is K = Kc = 3, which when used to obtain the same boost factor B = Bc = 2.5 requires both inverters to have the same ST ratio d = dc = 0.15 according to expressions summarized in Table 6.5. Moreover, with their common modulation ratio set to 0.8, their common peak output voltage generated is theoretically around 160 V based on (6.80). Other key current waveforms of the HE-TSI simulated in Fig. 6.32 have also been found to closely match their theoretical waveforms in Fig. 6.29. Additionally, when transferring from ST to NST state, winding currents i1 and i2 of the TSI change abruptly, since there are no non-inductive paths for them to gradually divert to. They thus lead to large voltage spikes at the DC-link. This does not occur with the proposed HE-TSI, whose winding currents can change more gradually, because of the presence of non-inductive current paths for currents to divert to. Experimental testing with a 200 W prototype controlled by a TMS320F28335 digital signal processor has been performed for proving practicality of the proposed HE-TSI. Hardware setup of the inverter is given in Fig. 6.33, while its parameters are given in Table 6.6. Moreover, to facilitate a fair comparison, a TSI has been

156

6 Technology of DC-Link Voltage Spikes Suppression

5 0

i1

20 10

i2

0

0 -10

iC1

-20 20 10

iC2

0 9.40

9.45

9.50

9.55

× 1e-3

Time(s) Fig. 6.32 Simulated key current waveforms of HE-TSI (green) and TSI (red)

implemented using the same printed circuit board and parameters under the same operating conditions. Coupled inductors of the two inverters have also been deliberately wound loosely to more prominently demonstrate leakage effects. Results obtained including DC-link voltages, voltages, and currents of diodes measured from the two inverters are shown in Fig. 6.34. The immediate observation noted is DC-link voltage spikes of the TSI are as high as 381 V, even though the stabilized DC-link voltage is only 184 V. In contrast, DC-link voltage of the HE-TSI does not have spikes and stabilizes at 190 V. At their inputs, peak input current of the HE-TSI flowing through D1 has also been found to be smaller than that of the TSI. Other key waveforms of the HE-TSI in Fig. 6.34b have similarly been found to match well with theoretical waveforms drawn in Fig. 6.29. They have hence verified the presented analysis. Figure 6.35 shows both inverters supplied by the same input voltage of Vin = 80 V, which when modulated with the same modulation ratio of M = 0.8 leads to a peak output of 151 V for the HE-TSI and 147 V for the TSI. These values are slightly smaller than their common theoretical peak of 160 V, calculated using (6.80). Reasons for the shortfalls are mainly linked to influences from leakage inductances and equivalent series resistances (ESRs).

6.4 Embedded Capacitor–Diode Absorbing Circuits

157

Lf

Auxiliary Power

C2 S1 S2 S3 S4 C1

Coupled D2 Inductors

Cf

D1

Vin

Vo

Fig. 6.33 Laboratory setup of HE-TSI

(a)

(b) 0

0

Vdc:200V/div vD1:500V/div

Vdc:200V/div vD1:500V/div

0

0

vD2:200V/div

0 0

iD1:5A/div

0 0

t(5μs/div)

iD1:5A/div iD2:10A/div

t(5μs/div)

Fig. 6.34 Experimental waveforms of Vdc, vD1, vD2, iD1, and iD2: a TSI and b HE-TSI

Other waveforms, like voltages across capacitors, are given in Fig. 6.36, from which specific values recorded are VC1 = 165 V for the TSI, and VC1 = 165 V and VC2 = 27 V for the HE-TSI. These values again match well with earlier determined theoretical values. Winding currents of the two inverters can next be analyzed in Fig. 6.37, where the critical feature noted is winding currents of the TSI jump abruptly when transferring from ST to NST state. This causes voltage spikes, which for the HE-TSI do not occur since it winding currents change more gradually when crossing from ST to NST state.

158

6 Technology of DC-Link Voltage Spikes Suppression

(a)

(b) Vin:50V/div

Vin:50V/div

0

0 vo:200V/div

vo:200V/div

0

0

io:5A/div

io:5A/div

0

0 t(10ms/div)

t(10ms/div)

Fig. 6.35 Experimental waveforms of input voltage Vin, output voltage vo, and output current io: a TSI and b HE-TSI

(a)

(b)

VC1:50V/div VC1:50V/div

0 0 VC2:10V/div

0 t(10ms/div)

t(10ms/div)

Fig. 6.36 Experimental waveforms of capacitors voltages: a TSI and b HE-TSI

(a)

(b) i1:2.4A/div

0 i1:2.4A/div

0

NST state i2:5A/div

NST state ST state

ST state

0

0 i2:5A/div

t(10us/div)

t(10us/div)

Fig. 6.37 Experimental waveforms of coil currents i1 and i2: a TSI and b HE-TSI

6.4 Embedded Capacitor–Diode Absorbing Circuits

159

Last but importantly, Fig. 6.38 shows efficiency of the HE-TSI being lower than that of the TSI when output power is low. This is likely due to more components used with the HE-TSI. However, as power level increases, efficiency of the HE-TSI becomes higher than that of the TSI. This happens because leakage energy recycled by the HE-TSI, rather than dissipated as heat, now exceeds energy losses in its extra components. The proposed HE-TSI is thus more appealing at higher power level because of its higher efficiency, in addition to its removal of voltage spikes at ST to NST crossings. Besides, also similarly with dual diode capacitor–diode absorbing circuits, the application range of embedded diode capacitor–diode absorbing circuits can extended to other CISIs to suppress the DC-link voltage spikes.

6.5

Cascaded Quasi-Z-Network Clamping Circuits

The cascaded quasi-Z-network clamping circuits are different from the former three absorbing circuits; it can not only restrain the DC-link voltage spikes but also enhance the boost factor of original inverters. The quasi-Z-network is introduced to the CISIs, which can be equivalent to two cascaded impedance network. Thus, the total boost factor of inverters will be enhanced. Moreover, the quasi-Z-network contains the structure of dual diodes capacitor–diode absorbing circuits. Therefore, this kind of clamping absorbing circuits can also realize the function of suppress the DC-link voltage spikes. Figure 6.39 shows the two-phase HS-YSI with its absorbing circuit comprising C3, C4, D2, and Lo (in red) [15]. Like all impedance source inverters, it has two board operational modes, notated as ST and NST, respectively. But, due to leakage influences from its coupled inductor and the non-ideal of semiconductor devices, these two operational modes can be further divided, as explained below. Fig. 6.38 Efficiency comparison between HE-TSI and TSI

HE-TSI TSI

90

Efficiency(%)

89

88

87

86 100

150

200

Output Power(W)

250

300

160

6 Technology of DC-Link Voltage Spikes Suppression

C2 Lin

C4

D1 D2

Vin

L o S1

S3 Lf

N3

N1 N2 C1

C3

Cf S2

AC Load

S4

Fig. 6.39 Topology of high step-up Y-source inverter

6.5.1

Operational Modes

Figure 6.40 shows operational modes of the HS-YSI, where the inverter bridge and ac load have been simplified as a switch SW and a current source Io in parallel. Response times of the switches and diodes have also been assumed to be much shorter than consequential inductive and/or capacitive transitional times. This is especially true, if C1, C2, C3, and C4, and Lin, Lo, and LM are chosen large enough, so that their respective voltages and currents are almost constant during one switching period. It should however be noted that, unlike the others, LM does not represent a discrete inductor. Rather, it represents the equivalent magnetizing inductance of the three-winding coupled inductor, which in practice also has a small leakage inductance in series with each winding. There are therefore three small leakage inductances, drawn with red wavy lines in Fig. 6.40, whose currents are not constant over a switching period. Key waveforms for illustrating them are summarized in Fig. 6.41, where each switching period has been divided into six intervals to be described next. (1) ST State [t0, t1]: Switch SW begins to turn on at t0, but because of leakage inductance of winding N1, diode D1 continues to conduct, while diode D2 remains reverse-biased. Voltage across SW, which is also the DC-link voltage, then begins to drop. This causes voltages across the three leakage inductances to change. Moreover, by tracing through the circuit, it has been found that components of current flowing through SW are all limited by inductances. The turning on of SW is therefore realized with zero current at t0, over this very short semiconductor-switching subinterval. [t1, t2]: Voltage across SW drops to zero, while its current increases significantly. Windings N2 and N3 are now clamped by voltages of C1 and C4 in series, while N1 and N3 are clamped by C2, since D1 is still conducting. However, current through D1 is falling at a rate mostly determined by its parasitic capacitance resonating with leakage inductance of N1.

6.5 Cascaded Quasi-Z-Network Clamping Circuits iC2

(a) Lin

iC4 C4

C2

vD2

vD1 D1

N1 i3

i1

N3

LM

Vin Iin

iC2 Lin

Io

iC4 C4

C2

vD2 N1 i3

i1 LM

Vin

i2

Iin

iC2 Lin

Vin Iin

N3

LM N2

C1

iC4 C4 vD2

i2

Lo

D2 iD2 N3

iC3 SW Vdc

C3 N2

Io

C1

Lo

iC2 Lin

Vin Iin

iC4 C4

C2

vD2

vD1 D1

Io

Io

C2

LM

(f)

iC3 SW Vdc

N2

N 1 i3

i1

Iin

D2 iD2 C3

iC3 SW Vdc

C3

vD1

Vin

iC4 C4 vD2

i2

Lin

Io

C2

N1 i3

i1

iC2

D1

N2

N3

C1

(d)

iC3 SW Vdc

C3

vD1 D1

Iin

Lo

C1

(e)

i2

Lo

D2 iD2

LM

D2 iD2 N3

vD2 N1 i3

i1

Vin

iC3 SW Vdc

iC4 C4

C2

vD1 D1

N2

vD1 D1

Lin

Lo

C1

(c)

iC2

(b)

D2 iD2 C3

i2

161

N1 i3

i1

N3

LM i2

C3 N2 C1

Lo

D2 iD2 iC3 SW Vdc Io

Fig. 6.40 Operational modes of HS-YSI when in a [t0, t1], b [t1, t2], c [t2, t3], d [t3, t4], e [t4, t5], and f [t5, t0]

[t2, t3]: The final ST state has been entered with both D1 and D2 reverse-biased. It is the longest among the three ST subintervals, during which Lin, Lo, and LM charge linearly, while C1 to C4 discharge linearly. (2) NST State [t3, t4]: Switch SW turns off at t3, causing its voltage and current to rise and fall, respectively, over this very short semiconductor-switching subinterval. Simultaneously, reverse voltages and forward currents of D1 and D2 begin to drop and rise. At the end of the subinterval, the DC-link voltage across SW becomes slightly higher than its final NST value, but still significantly smaller than voltage spikes caused by leakage inductances, if an absorbing circuit has not been added. [t4, t5]: Diodes D1 and D2 start to conduct. The three leakage inductances can then form resonating meshes with capacitances in the circuit. In total, three meshes can be drawn with windings of the coupled inductor included. They are mesh 1 formed by N2, N3, C1, and C3; mesh 2 formed by N1, N3, and C2; and mesh 3 formed by N1, N2, C1, Lin, and the input dc source. During this subinterval, the

162 Fig. 6.41 Key waveforms of HS-YSI with respect to equivalent circuits in Fig. 6.40

6 Technology of DC-Link Voltage Spikes Suppression

GSW t

iC4

t iC2

t iC3

t i3

t i2

t i1

t

iD2

vD1

t

vD2

t

Vdc

t

t 0 t1 t 2

t3 t4

t5

t 0 t1 t 2

t3

t

conduction of D2 also permits C3 and C4 to be connected in series for clamping the DC-link voltage across SW. Voltage spikes have hence been intentionally suppressed at ST to NST crossovers.

6.5 Cascaded Quasi-Z-Network Clamping Circuits

163

[t5, t0]: This is the final NST state entered, after current of D2 drops to zero and it begins to block. Meanwhile, D1 continues to conduct, which hence permits C2 to be connected across N1 and N3 for clamping their total voltage. Additionally, the dc-link voltage across SW is no longer solely equal to the combined voltage of C3 and C4 in series, since it now includes the reverse voltage of D2. There will hence be a very small DC-link voltage drop (proven later), after entering this subinterval at t5.

6.5.2

Current Analysis

To avoid complex current expressions that may not have any analytical value, the equivalent circuits in Fig. 6.40 have been simplified to those in Fig. 6.42, where all leakage inductances have been reflected and summed as LK in series with N1. Additionally, since Fig. 6.40a and d for representing very short semiconductorswitching subintervals is similar to Fig. 6.40f and c, they can be ignored, and hence not included in Fig. 6.42. Figure 6.43 then shows simplified key waveforms with only four distinct subintervals and winding currents i1, i2, and i3 assumed to change linearly during [t4, t5]. This figure, like Fig. 6.41, again shows that the state in Fig. 6.42a is much shorter in duration than the other three states. It is nonetheless included for showing influences caused by leakage inductances. Its circuit expressions have however been omitted from the mathematical analysis, since energies of passive components have hardly changed during such short interval between [t0, t2].

iC2

(a) Lin vLin Vin Iin

VC2 V + LK - i1 i1 N1 i3 LK IM N 3 vLM i2 VC3 N2

iC2

(c)

Vin Iin

vLM

VC1

VC4 L

iC2

(b) Lin vLin

o ILo

vLo iC3 C3

ist

Vin Iin

iC4

C4

Lin vLin

o ILo

vLo

i3 N3

C1

VC3

iC3 C3 Vdc

Io

Vin Iin

o ILo

vLo

i3

IM vLM

C4 VC4 L

VC2 i1 N1

iC2

(d)

VC4 L

i2 N2

LK

iC4

C2

N3 i2 N2

VC3

iC3 C3

C2

iC4

C4

VC4 L VC2 V o ILo vD2 + LK - i1 i1 N1 vLo i3 - + LK IM N3 vLM iC3 i2 C3 Vdc VC3 N2 VC1

ist

C1

VC1

C2

VC2 N1

V + LK - i1 i1 LK IM

C4

C1

VC1

Lin vLin

iC4

C2

Io

C1

Fig. 6.42 Simplified equivalent circuits of HS-YSI when in a ST state [t0, t2], b ST state [t2, t4], c NST state [t4, t5], and d NST state [t5, t0]

164 Fig. 6.43 Simplified key waveforms of HS-YSI with respect to equivalent circuits in Fig. 6.42

6 Technology of DC-Link Voltage Spikes Suppression

GSW

t

iC4

t iC2 t iC3

t i3

t i2

t i1

t

iD2

t

vD1

t

vD2

t

vdc

t0 t2

t4

t5

t0 t2

t4

t

6.5 Cascaded Quasi-Z-Network Clamping Circuits

165

Therefore, beginning with Fig. 6.42b, where both D1 and D2 are blocking, and SW is conducting from t2 to t4, their related current expressions can be obtained as iC1 ¼ i2 ¼ i3

ð6:82Þ

iC2 ¼ Iin

ð6:83Þ

iC3 ¼ ILo

ð6:84Þ

iC4 ¼ ðIin þ i3 Þ

ð6:85Þ

N1 i01 þ ðN3  N2 Þi3 ¼ 0

ð6:86Þ

i01 ¼ IM

ð6:87Þ

where (6.86) and (6.87) are for relating currents within the coupled inductor. Substituting them into (6.82) and (6.85) then yields the following current expressions for C1 and C4: iC 1 ¼ 

N1 IM N3  N2

iC4 ¼ Iin 

N1 IM N3  N2

ð6:88Þ ð6:89Þ

The capacitor currents will change, after progressing to Fig. 6.42c, where both D1 and D2 are conducting, while SW is blocking from t4 to t5. Collectively, they cause currents i2 and iC2 to increase linearly without any abrupt step at t4. In contrast, iC4 and iC3 change abruptly at t4 to iC4 ¼ ILo  Io iC3 ¼ Iin  Io þ

N1 IM N3  N2

ð6:90Þ ð6:91Þ

These capacitor currents will again change, after entering the state in Fig. 6.42d, where D2 has stopped conduction and hence leads to the following new set of current expressions: iC3 ¼ ILo

ð6:92Þ

iC4 ¼ ILo  Io

ð6:93Þ

iC1 ¼ i2

ð6:94Þ

166

6 Technology of DC-Link Voltage Spikes Suppression

i1 ¼ Iin þ iC2

ð6:95Þ

i3 ¼ Io  ILo þ iC2

ð6:96Þ

i2 ¼ Iin þ ILo  Io

ð6:97Þ

N1 i01 þ N2 i2 þ N3 i3 ¼ 0

ð6:98Þ

0

ð6:99Þ

i1 ¼ i1 þ IM

where (6.98) and (6.99) are for the coupled inductor. These new expressions then yield the following currents through C1 and C2: iC1 ¼ Iin þ ILo  Io iC2 ¼

ð6:100Þ

ðN3  N2 ÞðIin þ ILo  Io Þ þ N1 IM  Iin N3 þ N1

ð6:101Þ

Related current expressions for each capacitor can now be current-second integrated over a switching period, as expressed below: Z t2

t4

Z iCx dt þ t4

t5

Z iCx dt þ

t0

Z

dT

iCx dt ¼

t5

Z iCx dt þ

0

¼0

ða þ dÞT dT

Z iCx dt þ

T

ða þ dÞT

iCx dt

ð6:102Þ 4 where a ¼ t5 t T is the proportionality coefficient; x = 1, 2, 3 or 4 is an index for the capacitors; and interval [t0, t2]  0 has been omitted. Eventually, the following current expressions can be derived, from which currents through all components of the impedance network can be computed:

a¼

2 ð1  dÞ 1þK

ð6:103Þ

ILo ¼ Iin

ð6:104Þ

ðN1 þ N3 Þ Iin N1

ð6:105Þ

1  ð2 þ KÞd Iin ð1  dÞ

ð6:106Þ

IM ¼ Io ¼

6.5 Cascaded Quasi-Z-Network Clamping Circuits

6.5.3

167

Voltage Analysis

In terms of voltages, equivalent circuits in Fig. 6.42a and b can be analyzed as a single ST state with SW conducting from t0 to t4. The conduction of SW, in turn, causes C1 and C4 to be connected in series for clamping N2 and N3 of the coupled inductor. Relevant voltage expressions can thus be written as vLM ¼ ðVC1 þ VC4 Þ

N1 N3  N2

ð6:107Þ

vLo ¼ VC3

ð6:108Þ

vLin ¼ ðVin þ VC2 þ VC4 Þ

ð6:109Þ

where VC1, VC2, VC3, and VC4 are voltages across C1, C2, C3, and C4; and vLM , vLo , and vLin are voltages across LM, Lo, and Lin, respectively. Upon turning off SW, the first NST state entered is shown in Fig. 6.7c, where leakage current through LK starts to increase linearly from t4 to t5. During this time, N2 and N3 are also clamped by C1 and C3 in series, which together with other circuit features permit voltages across various inductances to be derived as vLM ¼ ðVC1  VC3 Þ

N1 N3  N2

ð6:110Þ

vLo ¼ VC4

ð6:111Þ

vLin ¼ VC3  VC2  Vin

ð6:112Þ

vLK ¼ ðVC1  VC3 Þ

N1 þ N3  VC2 N3  N2

ð6:113Þ

Moreover, since leakage current through LK increases linearly from zero at t4, its current i1(t5) at t5 can promptly be expressed as i1 ðt5 Þ ¼ 0 þ

1 LK

Z

ðd þ aÞT

vLK dt

ð6:114Þ

dT

which together with (6.96), (6.101), (6.103), (6.104), (6.105), and (6.106) permits voltage across LK to be derived as vLK ¼

ð1 þ KÞ2 2ð1  dÞ2 KT

Iin LK

ð6:115Þ

168

6 Technology of DC-Link Voltage Spikes Suppression

The NST state then changes to Fig. 6.42d, in which N1, N3, and LK are clamped by C2 during [t5, t0]. Leakage LK and magnetizing LM will hence share VC2 proportionally. These observations permit voltages across various inductances to be expressed as vLM ¼ ðVC1  VC3 þ vD2 Þ

vLK ¼ VC2

LK LK þ ð1 þ

N1 N3  N2

ð6:116Þ

vLo ¼ VC4  vD2

ð6:117Þ

vLin ¼ VC3  VC2  Vin  vD2

ð6:118Þ

N3 N1 ÞLM

¼ ðVC1  VC3 þ vD2 Þ

N1 þ N3  VC 2 N3  N2

ð6:119Þ

Moreover, since LK  LM, vLK in (6.119) can be approximated as zero from t5 to t0, and by substituting (6.113) and (6.115) into it, voltage across the reverse-biased D2 can be derived as vD2 ¼

ð1 þ KÞ2 2ð1  dÞ2 K 2 T

ð6:120Þ

Iin LK

Later, by substituting numerical values to it, vD2 can be proven to be very small and can hence be safely omitted during [t5, t0] to simplify the final derived expressions. That causes the voltages across various inductances in Fig. 6.42c and d to be the same, which can then be applied to derive the following voltage relationship: ðVC3  VC1 Þ

N1 þ N3 N1 þ N3  VC2 ¼ vD2 0 N3  N2 N3  N2

ð6:121Þ

All derived voltage expressions for each inductor can follow-up to be volt-second integrated over a switching period T, in accordance to Z

t4 t0

Z

t0

vLx dt þ t4

Z vLx dt ¼

dT

Z vLx dt þ

0

T

vLx dt ¼ 0

ð6:122Þ

dT

where Lx represents LM, Lo, or Lin. Performing the integration finally leads to the following voltages across C1, C2, C3, and C4: VC1 ¼ ð1  2dÞBVin

ð6:123Þ

VC2 ¼ dKBVin

ð6:124Þ

6.5 Cascaded Quasi-Z-Network Clamping Circuits

169

VC3 ¼ ð1  dÞBVin

ð6:125Þ

VC4 ¼ dBVin

ð6:126Þ

where B ¼ 1ð2 1þ KÞd is the voltage gain, and K is the turns ratio of the coupled inductor. A gain higher than that of the original Z-source inverter can thus be obtained by setting K equal or greater than one. Regardless of that, the DC-link voltage Vdc and peak AC output voltage ^vo of the inverter are always expressed as Vdc ¼ BVin

ð6:127Þ

^vo ¼ BMVin

ð6:128Þ

where M is the modulation index, which together with d must satisfy M\1  d

ð6:129Þ

1  ð2 þ KÞd [ 0

ð6:130Þ

A larger d to obtain a bigger gain will hence limit the maximum of M, together with some deterioration of output waveform quality. One method to lower d and raise M without compromising gain is to introduce a larger K. Alternatively, multiple cascaded absorbing circuits can be introduced. Figure 6.44 shows two possible topologies, whose cascaded absorbing circuits (in red) are placed at different locations. Despite that, they can both eliminate dc-link voltage spikes at instants of ST to NST crossovers. In Fig. 6.44a, it is ensured by the conduction of Dn, which in turn causes C2n−1 and C2n to be in series across the dc-link of the inverter bridge. The same conduction of Dn in Fig. 6.44b also permits C20 , C2n, and C2n−1 to clamp the DC-link voltage. Both inverters in Fig. 6.44 are therefore effective and have a common gain, which can be expressed as B¼

1 1  ð1 þ n þ KÞd

ð6:131Þ

where n is the number of absorbing circuits cascaded together, which unquestionably is an additional parameter for tuning the gain of the inverter. The main disadvantage here is more discrete components, which in practice should be avoided, if varying K of the coupled inductor can produce the same effect. Nonetheless, the gain in (6.131) is summarized in Table 6.7 for comparison with those of the existing impedance source inverters. In case of HS-YSI, n equals one, which still gives a higher gain than existing impedance source inverters, if they use the same K and d. The same K can, in turn, be realized with different N1: N2: N3 ratios for a three-winding coupled inductor, as seen from Table 6.8. The voltage gains of YSI, IYSI, and HS-YSI have been plotted in Fig. 6.45. If the three

170

6 Technology of DC-Link Voltage Spikes Suppression C2

(a) Lin

C2

C2n

D L1

D1 Vin

Ln S1

Dn

Lf C1

N2

C2n-1

C1

(b)

C2

C2n

L1

Ln

AC Load

Cf

S2

S4

S1

S3

C2

Lin

D D1

Vin

S3

N3

N1

Dn

C1

Lf

N3

N1 C2n-1

S2

C1

AC Load

Cf

N2 S4

Fig. 6.44 HS-YSIs with multiple cascaded absorbing circuits

Table 6.7 Voltage gains of different impedance source inverters with coupled inductors Impedance network

Gain B = Vdc/Vin

T- or trans-Z-source C-Z-source Y-source LCCT-Z-source Improved-trans-Z-source Improved-Y-source HS-YSI (n = 1)

1/(1 1/(1 1/(1 1/[1 1/[1 1/[1 1/[1

Table 6.8 Voltage gains of HS-YSI under different winding factors and turns ratio

− − − − − − −

Kd) Kd) Kd) (1 + (1 + (1 + (1 +

Turns ratio K

K)d] K)d] K)d] n + K)d]

K

dmax

Voltage gain B

2 3 4 5 6 7

1/4 1/5 1/6 1/7 1/8 1/9

(1 (1 (1 (1 (1 (1

− − − − − −

4d)−1 5d)−1 6d)−1 7d)−1 8d)−1 9d)−1

(N1 + N2)/N2 N2/(N2 − N1) (N1 + N3)/(N3 − N2) N1/N2 (N1 + N2)/N2 (N1 + N3)/(N3 − N2) (N1 + N3)/(N3 − N2)

N1:N2:N3 (1:1:3), (1:1:2), (2:1:2), (3:1:2), (4:1:2), (5:1:2),

(2:1:4), (3:1:3), (1:2:3), (2:2:3), (3:2:3), (4:2:3),

(1:2:5) (4:2:5) (5:1:3) (1:3:4) (2:3:4) (3:3:4)

6.5 Cascaded Quasi-Z-Network Clamping Circuits Fig. 6.45 The voltage gains of different YSIs versus duty cycle

171

Voltage Gain B

2.5

2

1.5

1

0

0.02

0.04

0.06

0.08

0.1

0.12

d

inverters are set to same duty cycle, the voltage of HS-YSI is higher than those of YSI and IYSI.

6.5.4

Stresses and Lifetime

From earlier derivations, expressions for calculating voltage and current stresses experienced by components of the HS-YSI can be extracted and summarized in Table 6.9. Also added to the table are corresponding expressions for the IYSI. Both Table 6.9 Comparison of voltage and current stresses for two inverters Parameter for comparison

I-YSI

HS-YSI

B= Vdc/Vin VC1 VC2 VC3 VC4 VD1 VD2 Iin ILo i1 i2 i3

1/[1 − (1 + Kc)d] (1 − d)BVin dKcBVin NA NA KcBVin NA P/Vin NA P/(1 − d)Vin KcP/Vin KcP/Vin

iST

(1 + Kc)P/Vin

1/[1 − (2 + K)d] (1 − 2d)BVin dKBVin (1 − d)BVin dBVin KBVin BVin P/Vin P/Vin (1 + K)P/(1 − d)KVin (1 + K)P/(1 − d)Vin KP/Vin or (K2 − 1)P/(1 − d)KVin (2 + K)P/Vin

172

6 Technology of DC-Link Voltage Spikes Suppression

inverters can then be compared under various conditions. For instance, if they have the same gain B and duty ratio d, their respective turns ratios must satisfy Kc = 1 + K, where subscript c has been added for representing the IYSI. More turns are thus needed by the IYSI, whose voltage stresses across C1, C2, and D1 are also higher than those of the HS-YSI. The HS-YSI however experiences a high voltage stress across D2, which must hence be sized appropriately. As for their coupled inductors, maximum currents flowing through N1 and N2 of the HS-YSI are larger than those of the IYSI, while its current through N3 may either be less than or equal to that of the IYSI, depending on the values of K and d. Despite that, ST current stresses experienced by the switches of the inverter bridges are quite close for both inverters, according to entries for iST in Table 6.9. The lifetime of the system is mainly determined by the components that have the lowest lifetime. The lifetime of diode is always several times higher than that of the capacitor, so we only need to consider the capacitors to evaluate the lifetime of system. The detail analysis of the lifetime models is beyond the scope of this paper, but a ready-made formula in [15] can be used to assess the lifetime L of capacitors:  L ¼ L0 

V V0

n

2

T0 T 10

ð6:132Þ

where L and L0 are the lifetime under the use condition and testing condition, respectively. V and V0 are the voltage at use condition and test condition, respectively. T and T0 are the temperature in Kelvin at use condition and test condition, respectively. n is the voltage stress exponent. Comparing expressions in Table 6.9 for the tow inverters then yields d < dc, if their parameters are set as K = Kc and B = Bi, where subscript c has been added for notating the IYSI. The capacitor C3 in HS-YSI has the highest voltage stress and has the lowest lifetime according to (6.132). These results will however change, if parameters of the inverters are set alternatively as d = dc and B = Bc. Their winding factors must then be related by K = Kc − 1, which quantitatively means the HS-YSI need smaller winding factors than the IYSI for achieving the same performance. The capacitor C1 in IYSI and capacitor C3 in HS-YSI will both have the highest voltage stress, namely, the lowest lifetime. Therefore, the lifetime of HS-YSI is equal to that of IYSI.

6.5.5

Extra Power Loss Analysis

The additional components in the HS-YSI will bring extra power losses to the inverter; thus, it is of great importance to perform loss analysis for estimating the efficiency of the HS-YSI. Since the power losses on D2 and Lo are much higher than those on the C3 and C4, the power losses on D2 and Lo will be analyzed as follows.

6.5 Cascaded Quasi-Z-Network Clamping Circuits Fig. 6.46 The key waveform of inductor Lo

173

GSW t vLo t iLo ILo t0 t2

t4

ΔILo t5

t0 t2

t4

t

Figure 6.46 shows the key waveforms of inductor Lo. The conduction losses of Lo include the hysteresis power loss PH and the copper loss PCu. The copper loss PCu can be calculated as PCu ¼ i2Lorms R

ð6:133Þ

where R is the resistance of the winding, and iLo−rms is the root-mean-square value of inductor current. Since the current ripple DILo of inductor Lo is relatively small, it can be assumed that iLo−rms is equal to the DC component of iLo, namely, ILo. Therefore, (6.133) can be rewritten as 2 PCu ¼ ILo R

ð6:134Þ

The hysteresis power loss PH is caused by the ac component of iLo and can be determined by PH ¼ a1 Bbpk1 f c1

ð6:135Þ

where a1, b1, and c1 are constants determined from core loss curve fitting [16], and f is frequency. The flux density Bpk can be obtained as Bpk ¼

DB BACmax  BACmin ¼ 2 2

ð6:136Þ

where DB is half of the AC flux swing. The flux density Bpk is a function of magnetizing field H. The maximum and minimum of H can be obtained as HACmax ¼

N ðILo þ DILo Þ le

ð6:137Þ

HACmin ¼

N ðILo  DILo Þ le

ð6:138Þ

174

6 Technology of DC-Link Voltage Spikes Suppression

From (6.137) and (6.138), the maximum and minimum of Bpk can be derived as (6.139) and (6.140) 

BACmax

BACmin

2 a2 þ b2 HACmax þ c2 HACmax ¼ 2 1 þ d2 HACmax þ e2 HACmax

x

 x 2 a2 þ b2 HACmin þ c2 HACmin ¼ 2 1 þ d2 HACmin þ e2 HACmin

ð6:139Þ ð6:140Þ

where a2, b2, c2, d2, e2, and x are constants determined from magnetization curve fitting [17]. The losses of D2 include the conduction loss Pf, reverse recovery loss Pr, and the reverse leakage loss Pl. According to Fig. 6.43, the current through D2 will drop to zero slowly at t5. Therefore, the reverse recovery loss Pr is equal to zero. The reverse leakage loss Pl can be calculated as Pl ¼ IR VD2 d

ð6:141Þ

where IR is the reverse current which can be read from [18]. The conduction loss Pf can be calculated as Pf ¼

1 T

Z

aT þ dT

iD2 VF dt

ð6:142Þ

dT

where VF is the forward voltage drop of D2 and can be obtained in [18]. Finally, the total losses brought by the Lo and D2 in nominal output power (200 W) is Ptotal ¼ PCu þ PH þ Pl þ Pf  5:62W

ð6:143Þ

The additional components will surely cause extra power losses. However, the power losses caused by the leakage inductor can be recycled in the proposed topology, rather than wasting in the switches. Besides, since the voltage spikes are fully eliminated at the DC-link, a low-voltage-rate switch with low on-resister can be applied, and the power loss will decrease.

6.5.6

Simulation and Experimental Results

Simulations and experiments have been performed with the IYSI in Fig. 6.1 and HS-YSI in Fig. 6.39 using the same parameters listed in Table 6.10. To boost an input voltage of 80 V to an output voltage of 160 V, ST duty ratios of the IYSI and HS-YSI have been set 0.15 and 0.12, respectively, since they use the same parameters from Table 6.10 and the same modulation index M = 0.8. Their

6.5 Cascaded Quasi-Z-Network Clamping Circuits Table 6.10 System parameters of HS-YSI

Parameter Input voltage Load resistance Capacitances C1 and C3 Capacitances C2 and C4 Inductances Lin and Lo Switching frequency fsw Turns ratio N1:N2:N3 Core Switches Diodes D1 and D2 Filter inductance Lf Filter capacitance Cf

175 Value/part number 80 V 60 X (200 W) 470 lF 100 lF 4.3 mH 10 kHz 40:40:80 C055863A2 IRGP4062DPbF 30EPH06PBF 5.6 mH 4.7 lF

respective theoretical voltages can then be determined as VC1 = 170 V and VC2 = 90 V for the IYSI, and VC1 = 152 V, VC2 = 72 V, VC3 = 176 V, and VC4 = 24 V for the HS-YSI. Their DC-link voltages are however the same at Vdc = 200 V. Their, respectively, obtained results are described next. The key current waveforms of the two inverters shown in Fig. 6.47 have been found to match well with theoretical waveforms drawn in Fig. 6.43. Most importantly, they have demonstrated that all winding current changes through leakage inductances of the HS-YSI have occurred gradually from t4 to t5, rather than instantaneously at t4, after each ST to NST crossover. Voltage spikes are hence not generated by the proposed HS-YSI. A 200 W prototype controlled by a TMS320F28335 digital signal processor has been built and shown in Fig. 6.48. It can be configured as either the IYSI or HS-YSI, using the same parameters provided in Table 6.10. The coupled inductor has also been loosely wound to better demonstrate the effects from leakage inductances, as seen from Fig. 6.49, where dc-link voltages, voltages, and currents of diodes are plotted. Clearly, the DC-link voltage spikes of the IYSI can reach 530 V, even though its stabilized value is only 194 V. It is thus inferior, as compared to the HS-YSI, whose DC-link voltage of 195 V is nearly free of spikes. Other key features from waveforms of the HS-YSI in Fig. 6.49b have also been found to match well with those from the theoretical waveforms drawn in Fig. 6.40. For example, the time duration from t4 to t5 in Fig. 6.49b has been measured as 0.438T, while that in Fig. 6.43 or from (6.103) is 0.44T, where T is the switching period. Furthermore, from (6.120) and using parameters from Table IV, vD2 has been determined as 2.87  104LK from t5 to t0. Its value is thus only a few mV, since the leakage LK is usually from 10 to 100 nH. It is thus expected to be unnoticeable, as verified by the third trace in Fig. 6.49b. Corresponding DC input and AC output waveforms are then shown in Fig. 6.50, where double-line-frequency ripples can noticeably be seen from input currents of

176

6 Technology of DC-Link Voltage Spikes Suppression

(a) 10

5

i2 (A)

iC2 (A)

5 0 0 -5 -10 -15 0.09906

-5 0.09906

0.09916

Time(s)

0.09916

Time(s) 5

20

iC3 (A)

15

0

10

-5

5

-10

0

-15

-5 0.09906

iC4 (A)

-20 0.09906

0.09916

Time(s)

0.09916

Time(s) 15

6

i1 (A) 4

10

2

5

0

0

-2 0.09906

(b)

0.09916

i3 (A)

-5 0.09906

Time(s)

0.09916

Time(s)

15

i3 (A) 10 5 0 -5 0.09906

t0

t2 t4

t5

t0

t2 t4

t5

0.09916

Time(s) Fig. 6.47 Simulated a i2, iC2, iC3, iC4, i1, i3; b i3 of IYSI (red) and HS-YSI (blue)

6.5 Cascaded Quasi-Z-Network Clamping Circuits

Lo

177

Auxiliary Power

Lf

C4 S1 S2 S3 S4 C3 Coupled Inductors

D2 Cf

C2 C1

Lin

D1 Vo

Vin

Fig. 6.48 Laboratory setup of a 200 W HS-YSI

(a)

(b) Vdc: 200 V/div Vdc : 200 V/div

0

0 t(2 ms/div)

t(2 ms/div)

Vdc : 200 V/div

0 0

Vdc : 200 V/div vD1: 500 V/div

0 0 vD2: 300 V/div

0 vD1: 500 V/div

0 iD1: 4 A/div

0

iD1: 4 A/div

t(10 μs/div)

Linear area

0 iD2: 10 A/div

t(10 μs/div)

Fig. 6.49 Measured results of Vdc, vD1, vD2, iD1, and iD2 of a I-YSI and b HS-YSI at 200 W operation

both inverters. The ripples are however slightly smaller in the HS-YSI, where more passive components are used for filtering. Their peak ac output voltages have also been read as 155 V for both the IYSI and the HS-YSI. Both values are smaller than

178

6 Technology of DC-Link Voltage Spikes Suppression

(a)

(b)

0

Vin: 100 V/div

0

vo: 100 V/div

Iin: 3 A/div

0

Vin: 100 V/div

0

vo: 100 V/div

0

0

0

0

Iin: 3 A/div

io: 2 A/div

io: 2 A/div t(10 ms/div)

t(10 ms/div)

Fig. 6.50 Measured input voltages Vin, input currents Iin, output voltages vo, and output currents io of a I-YSI and b HS-YSI at 200 W operation

(a)

(b) VC1: 100 V/div

0 VC1: 100 V/div

0

0

VC2: 50 V/div

VC3: 100 V/div

0

VC2: 50 V/div

0 0

VC4: 20 V/div

t(10 ms/div)

t(10 ms/div)

Fig. 6.51 Measured capacitors voltages of a IYSI and b HS-YSI

their common theoretical value of 160 V, because of reduction of effective ST duty ratio caused by leakage inductances and ESRs. Other than these, most theoretical and experimental values have been found to match closely, like VC1 = 169 V and VC2 = 86 V measured in Fig. 6.51a for the IYSI, and VC1 = 150 V, VC2 = 69 V, VC3 = 176 V, and VC4 = 20 V from Fig. 6.51b for the HS-YSI. Figure 6.52 shows the winding currents of the coupled inductor, which for the HS-YSI change more gradually in the NST state, rather than jump abruptly at the considered ST to NST crossover. However, both IYSI and HS-YSI exhibit oscillatory currents, which may be due to leakage inductances interacting with parasitic capacitances of the semiconductors. Actually, the HS-YSI can obtain a higher voltage applied in the high-gain occasion. To show this property, the shoot-through duty ratio d of HS-YSI is set to 0.15, while the other parameters remain unchanged in paper. In this condition, the boost ratio B is equal to 4, and the theoretical DC-link voltage Vdc and the output

6.5 Cascaded Quasi-Z-Network Clamping Circuits

0 0

i1: 2.4 A/div

0

ST state

179

i1: 2.4 A/div ST state

0

i2: 5 A/div

i2: 5 A/div

NST state

NST state i3: 4 A/div

i3: 4 A/div

0

0 t(10 μs/div)

t(10 μs/div)

Fig. 6.52 Measured winding currents i1, i2, and i3 of a IYSI and b HS-YSI

Fig. 6.53 Measured results of Vdc, Vin, Vo, Iin, Io for HS-YSI

Vdc : 200 V/div 0 t(5 μs/div) Vdc : 100 V/div 0 0

iin: 4 A/div

0 vo: 200 V/div 0 io: 2 A/div t(10 ms/div)

peak voltage are 320 V and 256 V, respectively. The relative experimental results are shown in Fig. 6.53. The Vdc can be read as 296 V, and the output peak voltage can be read as 235 V. The output voltage loss is 21 V, mainly caused by leakage of the coupled inductor and equivalent series resistances (ESRs) in the circuit. Especially with ESRs, their effects increase sharply with B, which thus causes output drop voltage with B = 4 to be greater than that with B = 2.5. Despite that, voltage spikes at the DC-link do not deteriorate further.

180

6 Technology of DC-Link Voltage Spikes Suppression

Fig. 6.54 Efficiency comparison of the IYSI, I-YSI with absorbing circuit in Fig. 6.2c and HS-YSI

Last but not least, Fig. 6.54 shows the measured efficiencies of the IYSI and the HS-YSI. As can be seen, when the power rate is low, the efficiency of IYSI is greater than that of the HS-YSI, since less component is implied in the IYSI. However, when power level is high, the HS-YSI performs better. It is because that the leakage energy recycled by the HS-YSI exceeds the loss on the additional components. Thus, HS-YSI is more appealing in the high power level application cause that it has nearly no voltage spikes and higher efficiency at high power rate. The efficiency of IYSI with absorbing circuit in [11] is greater than those of the IYSI and HS-YSI. However, the voltage spikes at dc-link cannot be entirely eliminated in IYSI with absorbing circuit in [11]. Besides, the voltage gain of the IYSI with absorbing circuit in [11] is lower than that of the HS-YSI.

6.6

Summary

In order to suppress the DC-link voltage spikes of CISIs, this chapter introduces four passive absorbing circuits. All of them can be implemented in CISIs to eliminate the spiky DC-link voltage. The dual diodes capacitor–diode absorbing circuits and embedded capacitor–diode absorbing circuits are both restrain the spikes totally without the compromise of voltage gain, while the cascaded quasi-Z-network clamping circuits can boost the gain with the elimination of DC-link voltage spikes. As for the inverters that contain single diodes capacitor– diode clamping circuits, they can suppress the DC-link voltage spikes and the duty loss.

References

181

References 1. W. Qian, F.Z. Peng, H. Cha, Trans-z-source inverters. IEEE Trans. Power Electron. 26(12), 3453–3463 (2011) 2. M.-K. Nguyen, Y.-C. Lim, Y.-G. Kim, TZ-source inverters. IEEE Trans. Ind. Electron. 60 (12), 5686–5695 (2013) 3. M. Adamowicz, LCCT-z-source inverters, in Proceedings of EEEIC (2011), pp. 1–16 4. P.C. Loh, D. Li, F. Blaabjerg, Г-Z-source inverters. IEEE Trans. Power Electron. 28(11), 4880–4884 (2013) 5. W. Mo, P.C. Loh, F. Blaabjerg, Asymmetrical Г-source inverters. IEEE Trans. Ind. Electron. 61(2), 637–647 (2014) 6. Y.P. Siwakoti, G.E. Town, P.C. Loh, F. Blaabjerg, Y-source inverter, in 2014 IEEE 5th International Symposium on Power Electronics for Distributed Generation Systems (PEDG) (Galway, 2014), pp. 1–6 7. R.R. Ahrabi, M.R. Banaei, Improved Y-source DC–AC converter with continuous input current. IET Power Electron. 9(4), 801–808 (2016) 8. A. Hakemi, M. Sanatkar-Chayjani, M. Monfared, Δ-source impedance network. IEEE Trans. Ind. Electron. 64(10), 7842–7851 (2017) 9. M. Adamowicz, N. Strzelecka, T-source inverter. Electr. Rev. 85(10), 233–238 (2009) 10. M.-K. Nguyen, Y.-C. Lim, S.-J. Park, Improved trans-z-source inverter with continuous input current and boost inversion capability. IEEE Trans. Power Electron. 28(10), 4500–4510 (2013) 11. Z. Aleem, M. Hanif, Operational analysis of improved Г-Z-Source inverter with clamping diode and its comparative evaluation. IEEE Trans. Ind. Electron. 64(12), 9191–9200 (2017) 12. H. Liu, Y. Li, Z. Zhou, W. Wang, D. Xu, A family of low-spikes, high-efficiency Y-source inverters. IEEE Trans. Ind. Electron. 66(12), 9288–9300 (2019) 13. Y. Ran, W. Wang, K. Liu, H.P. Liu, A power decoupling solution for improved single-phase Y-source inverter, in Proceeding of IETC Asia-Pacific (2017), pp. 1–5 14. Y.S. Liu, B.M. Ge, H. Abu-Rub, F. Blaabjerg, Single-phase z-source/quasi-z-source inverters and converters: an overview of double-line-frequency power-decoupling methods and perspectives. IEEE Ind. Electron. Mag. 12(2), 6–23 (2018) 15. H. Liu, Z. Zhou, K. Liu, P.C. Loh, W. Wang, D.G. Xu, F. Blaabjerg, High step-up Y-source inverter with reduced DC-link voltage spikes. IEEE Trans. Power Electron. 36(6), 5487–5499 (2018) 16. MAGNETICS, 2017MPCC (2017) magnetics powder core catalog (2017) 17. H. Wang, F. Blaabjerg, Reliability of capacitors for DC-link applications in power electronic converters—an overview. IEEE Trans. Ind. Appl. 50(5), 3569–3578 (2014) 18. International IAR Rectifier, PD-20879 (2014) 30EPH06PbF datasheet (2014)

Chapter 7

Impedance Source Inverters Analysis

Abstract Traditional way of applying ampere-second and voltage-second balances has commonly been adopted for calculating state variables of a converter. However, it becomes tedious and error prone when used with complicated topologies having many inductors and capacitors. Therefore, to simplify the circuit analysis, a reactive component elimination method has been proposed in this chapter for application to all converter topologies. To demonstrate, current and voltage stresses of a type of coupled inductor impedance source inverter have been determined using both traditional and proposed methods. Besides, the coupled inductor introduces the leakage inductance to the inverters and cause many problems during switching transient. Since the invert stage is coupled with the impedance stage in the impedance source inverters, it is very hard to describe the switching process clearly with traditional inverter models. Therefore, a novel model for the coupled inductor impedance source inverters is proposed in this chapter. The proposed model can be used to analyze the switching transient of the impedance source inverter. Furthermore, with the help of this model, it is easy to tell the power lost during the switching transient.

7.1

Traditional Analysis of Voltage and Current Stresses

Nowadays, inverter topologies have become more and more complex, in order to meet some special demands. One example is the Z-source inverter, or impedance source inverter in general, proposed in 2002 [1]. Subsequently, a few improvements have been introduced to it, leading to other developments documented in [2]. For instance, to raise its voltage gain, while retaining a small shoot-through time, coupled inductors with two windings have been introduced to the basic impedance network, like in trans-Z-source and C-Z-source inverters [3, 4]. A more generic Y-source inverter with three coupled windings has also been proposed in [5]. However, the Y-source inverter inherits some common disadvantages from other elementary two-winding inverters. The improved Y-source inverter with an extra capacitor and inductor has hence been proposed for smoothing current drawn from © Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_7

183

184

7 Impedance Source Inverters Analysis

the source [6]. Recently, a high step-up Y-source inverter (HS-YSI) with more components has also been proposed, whose target is to reduce DC-link voltage spikes at an even higher voltage gain [7]. Current and voltage stresses of these improved converters have, however, always been analyzed by following a traditional procedure of applying ampere-second and volt-second balances [8–12]. The procedure requires each switching period to be divided into several subintervals, and if capacitances and inductances of the inverter are chosen large enough, its capacitive voltages and inductive currents can be assumed constant throughout all subintervals. Capacitive currents and inductive voltages are, however, different for each subinterval. They must hence be explicitly determined in terms of different state variables. The derived capacitive current expressions and inductive voltage expressions can then be current-second and voltage-second integrated over a switching period. The outcomes are expressions for determining all constant capacitive voltages and inductive currents. The expressions can then be used for finding current and voltage stresses of all components of the inverter. However, the traditional procedure may become tedious and error prone, when used with inverters comprising many capacitors and inductors, like in an impedance source inverter. One example is the HS-YSI shown in Fig. 7.1 [7], which broadly can operate in two distinct states, named, respectively, as shoot-through (ST) and non-shoot-through (NST) states. Each state can further be divided into several subintervals, according to operating conditions of the diodes shown in the figure. The total number of initial expressions to be determined for representing capacitive currents and inductive voltages in all subintervals ends up to be twenty-seven as shown in Sect. 6.5 of Chap. 6. This is followed by four current-second and three voltage-second integral expressions for the four capacitors and three inductors (three-winding coupled inductor represented by a single independent magnetizing inductance) noted from Fig. 7.1. The procedure is thus relatively complex with many expressions to solve. C2 Lin

C4

idc

D1 D2

Vin

Lo S1

S3 Lf

N3

N1 N2

C3

C1 Fig. 7.1 Topology of high step-up Y-source inverter

Cf S2

S4

AC Load

7.1 Traditional Analysis of Voltage and Current Stresses

185

The studied two-phase HS-YSI shown in Fig. 7.1 has four distinct operating subintervals, represented by simplified equivalent circuits shown in Fig. 7.2. Figure 7.2a shows subinterval 1, where two switches per phase leg of the inverter have been turned on to initiate the ST state. During this time, diode D1 continues to conduct, while diode D2 remains reverse biased. Conduction of D1 only ends, after leakage current through winding N1 falls to zero a short time later. The inverter then enters subinterval 2 with both D1 and D2 reverse biased, as shown in Fig. 7.2b. In the meantime, the two switches per phase leg are still kept on, which means subinterval 2 is also an ST state. This ST state ends only after turning off one switch of the phase leg, which then leads to NST subinterval 3 shown in Fig. 7.2c with both D1 and D2 conducting. However, D2 stops its conduction sometimes later, resulting in NST subinterval 4 shown in Fig. 7.2d. Moreover, since subinterval 1 has usually been kept much shorter by minimizing leakage inductance, its circuit expressions can safely be omitted without prominently affecting accuracy. Therefore, current analysis can begin with subinterval 2, where the traditional procedure requires all capacitive current expressions to be determined using Kirchhoff’s current law (KCL), before repeating it for subintervals 3 and 4. Twelve capacitive current expressions must, hence, be derived. Besides, in order to establish relations of the capacitive currents to the input current Iin, current of output inductor ILo, and magnetizing current IM, six current expressions for the coupled inductor for all three subintervals must be introduced.

iC2

(a) Lin vLin Vin Iin

VC2 V + LK - i1 i′1 N1 i3 L1 LK IM N3 vLM L3 i2 LM VC3 N2 L2

iC2 Lin vLin

Vin Iin

C2

VC2 V + LK - i1 i′1 N1 i3 L1 L K IM N3 vLM LM i2 L 3 VC3 N2 L2 VC1

C4 VC4 L

iC2

(b) Lin vLin

o ILo

vLo iC3 vSW ist C3

Vin Iin

C1

LK IM

vLM LM

(d)

C4 VC4 L

Lin vLin

o ILo

vLo iC3 C3 Vdc

iC2

Io

Vin Iin

C4 VC4 L

N3

o ILo

vLo

i3

i2 N2

L3 VC3

iC3 vSW C3 ist

C1

VC1 iC4

iC4

C2

VC2 i′1 N1 L1

L2

C1

VC1

(c)

iC4

C2

C2

iC4

C4

VC4 L VC2 V o ILo vD2 + LK - i1 i′1 N1 vLo i3 - + L1 L K IM N3 vLM iC3 L3 LM i2 C3 Vdc VC3 N2 L2 VC1

Io

C1

Fig. 7.2 Simplified equivalent circuits of HS-YSI when in a ST state subinterval 1. b ST state subinterval 2. c NST state subinterval 3. d NST state subinterval 4

186

7 Impedance Source Inverters Analysis

After that, current expressions for each capacitor must be ampere-second integrated over a switching period, which for four capacitors give rise to four more expressions. The total number of expressions is thus twenty-two for current analysis alone. That makes the computation complicated and error prone, even though it has been performed in the last chapter to arrive at the following results: ILo ¼ Iin ðN1 þ N3 Þ Iin N1

ð7:2Þ

1  ð2 þ KÞd Iin ð1  dÞ

ð7:3Þ

IM ¼ Io ¼

ð7:1Þ

N3 where K ¼ NN13 þ N2 , and d is the ST duty ratio. Similarly, voltage analysis begins with subinterval 2 and the finding of all inductive voltages across Lin, Lo, and LM by Kirchhoff’s voltage law (KVL). The same applies to subintervals 3 and 4 with nine equations to be determined for all three subintervals. Related voltage expressions for each inductor can then be integrated over a switching period based on the voltage-second balancing principle. There are thus three integral expressions for the three inductances, which when added to those earlier expressions give a total of twelve equations needed for voltage analysis. Solving them finally gives rise to the following constant voltage across C1, C2, C3, and C4.

VC1 ¼ ð1  2dÞBVin

ð7:4Þ

VC2 ¼ dKBVin

ð7:5Þ

VC3 ¼ ð1  dÞBVin

ð7:6Þ

VC4 ¼ dBVin

ð7:7Þ

where B ¼ 1ð2 1þ KÞd is the voltage gain of the HS-YSI. DC-link voltage Vdc can then be expressed as Vdc ¼ BVin

ð7:8Þ

Combining both current and voltage analyses, thirty-four expressions are thus needed for solving the HS-YSI circuit. Furthermore, to obtain the integral expressions, statuses of all reactive components during all subintervals must be known. The traditional procedure of applying ampere-second and volt-second principles is therefore complicated, especially when applied to converters with many inductors and capacitors.

7.2 Novel Method to Analyze Voltage and Current Stresses

7.2

187

Novel Method to Analyze Voltage and Current Stresses

To simplify the procedure involved with stress analysis, a reactive component elimination method has been proposed in this section for all converters, especially those with complex topologies. As an example, the method has been applied to the HS-YSI shown in Fig. 7.1. Related details are given below.

7.2.1

Current Analysis

Unlike the traditional procedure, current-second balance has first been applied to simplify the HS-YSI, noting particularly that average current values of all its capacitors are zero over a switching period. Mathematically, it means hiC1 iT ¼ hiC2 iT ¼ hiC3 iT ¼ hiC4 iT ¼ 0

ð7:9Þ

where h xiT represents average value of x over a switching period T. Capacitors C1, C2, C3, or C4 will therefore not influence average currents of other components. In other words, branches with any of these capacitors in series can be removed when analyzing average currents. That leads to equivalent average current circuit shown in Fig. 7.3, from which the following current expressions can be deduced: hiD1 iT ¼ hi1 iT ¼ hi3 iT ¼ hiD2 iT ¼ hidc iT ¼ Iin

ð7:10Þ

ILo ¼ Iin
 hi1 iT ¼ i01 T þ IM

ð7:11Þ ð7:12Þ

Moreover, despite winding N2 in series with C2 has been removed in Fig. 7.3, the remaining two windings are still coupled. Their currents must, hence, satisfy
 N1 i01 T þ N3 hi3 iT ¼ 0

i1'

Lin

Vin

Iin

iD1

T

i1

i3

T

N1 T

ILM

ð7:13Þ

LM

Fig. 7.3 The equivalent current circuit of HS-YSI

N3

Lo

T

iD 2

T

idc

T

188

7 Impedance Source Inverters Analysis

Substituting (7.12) and (7.10) to (7.13), then leads to N1 ðhi1 iT IM Þ þ N3 hi3 iT ¼ 0 IM ¼

ðN1 þ N3 Þ Iin N1

ð7:14Þ ð7:15Þ

where the latter is for computing magnetizing current IM. Next, hidc iT can be found from Fig. 7.2 with the much shorter subinterval 1 in Fig. 7.2a again ignored. The ST time is thus contributed by subinterval 2 only in Fig. 7.2b, from which the following current expressions for the coupled inductor can be obtained: N1 i01 þ ðN3  N2 Þi3 ¼ 0

ð7:16Þ

i01 ¼ IM

ð7:17Þ

Then, KCL states that the DC-link current in ST state can be written as idc ¼ ILo þ Iin þ i3

ð7:18Þ

On the other hand, when in the NST subintervals, Fig. 7.2c and d shows that the dc-link current is equal to the load current, and can hence be expressed as idc ¼ Io

ð7:19Þ

Therefore, from (7.16), (7.17), (7.18), and (7.19), the average DC-link current can be derived as hidc iT ¼ dðILo þ Iin þ

N1 IM Þ þ ð1  dÞIo N3  N2

ð7:20Þ

Next, by substituting (7.10), (7.11), and (7.15) into (7.20), Io can also be derived as Io ¼

1  ð2 þ KÞd Iin ð1  dÞ

ð7:21Þ

Obviously (7.11), (7.15), and (7.21) are the same as (7.1), (7.2), and (7.3), respectively. This proves the validity of the proposed method, but with lesser complexity, since only seven initial and intermediate expressions (7.10), (7.11), (7.12), (7.13), (7.15), (7.20), and (7.21) are needed. On the other hand, the traditional procedure involves twenty-two initial and intermediate expressions for current analysis alone, as discussed in last section.

7.2 Novel Method to Analyze Voltage and Current Stresses

7.2.2

189

Voltage Analysis

Analogous to the subsection of current analysis, voltage-second balance, stating that average voltages across all inductors are zero over a switching period T, has been applied to simplify the HS-YSI. Mathematically, it means hvLin iT ¼ hvL1 iT ¼ hvL2 iT ¼ hvL3 iT ¼ hvLO iT ¼ 0

ð7:22Þ

Inductances Lin, L1, L2, L3, and Lo can, hence, be shorted, since they do not affect average voltages of other components. The HS-YSI can therefore be simplified to its equivalent average circuit shown in Fig. 7.4, where hvD1 iT and hvD2 iT can be derived from Fig. 7.2, after ignoring the much shorter ST subinterval 1 in Fig. 7.2a. Voltage analysis therefore begins with Fig. 7.2b, where both D1 and D2 are blocking. According to KVL, voltage across D1 can then be identified as the sum of voltages across C2, N1, and N3. Besides, voltages across windings N2 and N3 are related to VC1 VC1 and VC4 . Then, combining with voltage relationship of the coupled windings, the following expression can be determined: vD1 ¼ VC2 þ KðVC1 þ VC4 Þ

ð7:23Þ

As for voltage across D2, the following expression can be written: vD2 ¼ VC3 þ VC4

ð7:24Þ

after which the inverter enters the NST subinterval shown in Fig. 7.2c, where both D1 and D2 are conducting. Diode D2, however, stops its conduction upon entering the next NST subinterval represented by Fig. 7.2d, while D1 continues to conduct. Despite that, vD2 across D2 can be proven to be very small in Fig. 7.2d. Voltages across D1 and D2 can hence both be assumed zero in the two NST subintervals. Eventually, average voltages across D1 and D2 over a switching period can be derived as C4

C2

Fig. 7.4 The equivalent voltage circuit of HS-YSI

VC2

vD1

VC4

vD 2

T

Vin VC1

C1

T

VC3

C3

Vdc

T

190

7 Impedance Source Inverters Analysis

hvD1 iT ¼ d½VC2 þ KðVC1 þ VC4 Þ

ð7:25Þ

hvD2 iT ¼ dðVC3 þ VC4 Þ

ð7:26Þ

From Fig. 7.4, KVL also states that voltages across the capacitors can be written as VC1 ¼ hvD1 iT þ Vin

ð7:27Þ

VC2 ¼ hvD1 iT

ð7:28Þ

VC3 ¼ VC1 þ hvD2 iT

ð7:29Þ

VC4 ¼ hvD2 iT

ð7:30Þ

Then, by substituting (7.25) and (7.26) to (7.27), (7.28), (7.29), and (7.30), the same capacitive voltage expressions as (7.4) to (7.7) can be derived. Moreover, from Fig. 7.2, switch voltage vSW is noted to be zero and Vdc when in ST and NST states, respectively. Therefore, the average switch voltage can be obtained as hvSW iT ¼ ð1  dÞVdc

ð7:31Þ

According to Fig. 7.4, KVL also states that the average switch voltage can be written as hvSW iT ¼ VC3

ð7:32Þ

By substituting (7.32) to (7.31), the dc-link voltage can thus be expressed as Vdc ¼

1 Vin ¼ BVin 1  ð2 þ KÞd

ð7:33Þ

Obviously, these voltage expressions are the same as those derived in Sect. 7.1. But, in total, only fourteen expressions are involved with the solution of the HS-YSI using the proposed procedure.

7.2.3

Method Applied to Other Converters

Figure 7.5 shows the flowcharts of traditional and novel methods. The red parts respect huge amount of computation, while the light blue parts have less computational complexity. The voltage and current stresses analysis has been greatly simplified, especially with no integral expressions to consider. Furthermore, the capacitors or inductors branches can be removed when only involving the

7.2 Novel Method to Analyze Voltage and Current Stresses

(a)

191

(b)

Capacitive currents

Steady-state values

Inductive voltages

Integration

Equivalent model

Constant parameters

Constant parameters

Fig. 7.5 The flowcharts of a traditional. b novel methods

steady-state values in the procedure of novel method. Thus, the dynamic analytical process can be omitted. Moreover, the novel procedure can be used with other converters for analyzing their current and voltage stresses. Table 7.1 summarizes the number of expressions demanded by both traditional and novel procedures, when they are used with different converters. The observation noted is the number of expressions needed for solving impedance source inverters, which has generally been lesser with the novel procedure, which also requires no integral expression. The reduction of expressions and computational complexity with the novel procedure has also been noted to be more noticeable when the inverters have more capacitors and inductors. In other words, and as proven, the novel procedure does not reduce the number of expressions significantly, when used with elementary DC–DC buck and boost converters. The same applies to DC–DC forward and flyback converters, which elementarily are simply isolated buck and buck–boost converters. The novel reactive component elimination method for analyzing voltage and current stresses of all converters, especially impedance source inverters with

Table 7.1 Comparison of voltage and current stresses one Converter

Traditional method

Integral formulas

Novel method

ZSI TSI CSI YSI I-YSI HS-YSI Buck Boost Buck–boost Forward Flyback

12 10 10 10 16 34 6 6 10 6 12

4 2 2 2 4 7 1 1 2 1 2

8 9 9 9 11 4 6 6 7 6 7

192

7 Impedance Source Inverters Analysis

coupled inductors and many reactive components is presented in this section. The procedure starts by using ampere-second and voltage-second balancing principles to establish simplified equivalent average circuits for the converter. The average circuits then permit various current and voltage expressions to be derived easily.

7.3

Transient Analysis Based on Impedance Source Inverter

The impedance source inverters (ISI), such as Z-source inverter, meet the needs of many modern power electronic applications [1]. Compare with the traditional VSI and CSI, ISIs only have one stage, which promise small volume and low cost. In addition, the shoot-through or open circuit of the phase arm is a normal working state for the ISIs. Therefore, the dead time can be removed from the modulation stage of them, which cause high-quality output waveform and high reliability. Among all the ISIs, those with coupled inductors imbedded have the best boost performance. The so-called coupled inductor impedance source inverters (CISI) can reach a high output voltage with a small shoot-through duty ratio. This leads to high modulation index and low voltage stress on the switches theoretically. However, the leakage inductance in the coupled inductor introduces many problems to the CISIs during switching transient, including big diode ringing and huge DC-link voltage spikes. This phenomenon will induce great energy loss and worsen the voltage stress on the diodes and switches of CI-ISIs [13]. Actually, unlike the stray inductance of the PCB or equivalent series inductance of the capacitors which is too small that can always be neglected in the practical calculation, the leakage inductance is relatively bigger and can cause great influence to the CI-ISIs. These drawbacks may offset the advantages bring by the CISIs and diminish their practical value. Therefore, detail research for the influence of the leakage inductance in CISIs during switching transient is very important. So far, the available literature in the field of CI-ISIs mostly focuses on the topology proposing, control strategy design, and steady-state or small-signal analysis. Tiny researchers pay attention to this question and provide some strategy to alleviate the influence of leakage inductance [14–17]. For example, the paper [17] uses a parallel connection structure of coupled inductor to decrease the equivalent leakage inductance. The article [18] proposes some snubber circuits embedded in the DC-link to eliminate the dc-link spikes. However, all of these articles just give a qualitative analysis for the influence of leakage inductance. The quantitative analysis is neglected from these literatures, thus some important data, such as the quantitative relationship between the diode ringing voltage and the leakage inductance, cannot be derived from these materials. Up to now, no paper provides a viable solution to analyzing the detail of switching transient of CISIs. The quantitative analysis for the simple topology such as flyback converter is very easy, but it is a really tough thing for the CISIs [13]. For example, Fig. 7.6

7.3 Transient Analysis Based on Impedance Source Inverter

C2 Lin

Resonant Loop 1

CD

Resonant Loop 2 LK3

D1 LK1 Vin

193

N1

N3

N2

ST

Io

LK2 C1 Fig. 7.6 Improved Y-source inverter (IYSI)

shows the equivalent circuit of Improve Y-source inverter (IYSI), which is a typical CISI. The inverter bridge is equivalent to a switch and the load is equivalent to a current source Io. And the coupled inductor is represented by the p model [19]. When the inverter bridge shoots through, the equivalent switch will turn on, and the parasitic capacitor of diode will resonant with the leakage inductance. However, there are two resonant loops on the inverter, and the coupled inductor couples these two loops together; it is hard to tell the exact value of leakage inductance that resonant with the parasitic capacitor. Thus, the resonant process cannot be calculated. In the following, a novel model for the CISIs is proposed. The proposed model simplifies the impedance network of the CISIs and provides an easy way to analyze and calculate the switching transient of the CISIs.

7.3.1

Derivation of the Novel Model

The novel model is aimed to research the switching process of the converter. Thus, the performance of switching process in novel model must be consistent with that in original circuit, which means the details of voltage change and current change are common with the original circuit. This condition must be satisfied in the whole derivation of novel model. The specific derivation process is divided into the following two steps.

7.3.1.1

Derivation of the Coupled Inductor Model

Figure 7.7a shows the p model of Y-type coupled inductors, which accurately reflects the leakage inductance and the relationship between current and voltage in each coil. At a certain switching frequency, the working characteristics of p model are consistent with the actual coupled inductors. However, it is too complex for the

194

(a)

7 Impedance Source Inverters Analysis

(b)

i3

i1 N1

1 LK1

LK3 N3

IM

3

i`1

1 LK

i2

N`3

IM

3

N`2

N2 v12

i`3

N`1

v23

v`12

LK2 2

v`23 i`2 2

Fig. 7.7 Model of Y-type coupled inductors: a p model. b simplified model

novel model derivation. Therefore, a simplified coupled inductor model shown in Fig. 7.7b is more acceptable. In order to make the working characteristics of the simplified coupled inductors same as the p model, it is necessary to ensure that the port characteristics of the two coupled inductor models are consistent. It can be summarized into the following two conditions: 1. The coil current should be same, which means when i1 ¼ i01 is met, there must satisfies i2 ¼ i02 or i3 ¼ i03 . 2. The port voltage should be same,which means when v12 ¼ v012 , v23 ¼ v023 must be satisfied. Obviously, if conditions 1 and 2 are met, the static properties of the two models are the same. Meanwhile, conditions 1 and 2 also guarantee that the derivative of coil current and port voltage of the two models will be the same. Thus, the dynamic characteristics of coupled inductors are consistent in the switching process. Therefore, as long as conditions 1 and 2 are satisfied, the simplified coupled inductor model can completely replace the complex p model in the switching process analysis. According to the Kirchhoff’s law of current, it can be derived as i1 ¼ i2 þ i3

ð7:34Þ

i01 ¼ i02 þ i03

ð7:35Þ

Then according to the relationship of coupled inductors, the following equations can be found: N1 ði1  IM Þ þ N2 i2 þ N3 i3 ¼ 0   N10 i01  IM þ N20 i02 þ N30 i03 ¼ 0

ð7:36Þ ð7:37Þ

7.3 Transient Analysis Based on Impedance Source Inverter

195

Based on Eqs. (7.34), (7.35), (7.36), and (7.37), in order to satisfy condition 1, the coupled inductors must meet N2 N20 N3 N30 ¼ ; ¼ N1 N10 N1 N10

ð7:38Þ

which means the turns ratios of two models are the same. For convenience, it is advisable to make the turns ratio of the simplified model the same as that of the p model. Since condition 1 is satisfied, the rate of change of coil current in both models will be the same, which represents when di2 dt

di02 di3 dt , dt

di03 dt .

di1 dt

¼

di01 dt

is satisfied, there must have

¼ ¼ According to Fig. 7.7a, v23 ¼ 

  1 di1 di2 di2 di3 v12  LK1  LK2  LK3 þ LK2 ðK  1Þ dt dt dt dt

ð7:39Þ

N3 where K ¼ NN13 þ N2 is the turns ratio of the coupled inductor. Meanwhile, taking the derivative of Eqs. (7.34) and (7.35), the following expression can be determined:

di2 di1 ¼K dt dt

ð7:40Þ

di3 di1 ¼  ð K  1Þ dt dt

ð7:41Þ

By substituting (7.40) and (7.41) to (7.39), the following equation can thus be expressed as v23

 di  1 1 2 2 v12  LK1 þ K LK2 þ ðK  1Þ LK3 ¼ ðK  1Þ dt

ð7:42Þ

While according to Fig. 7.7b, v023

  1 di1 0 v  LK ¼ ðK  1Þ 23 dt

ð7:43Þ

Thus, by comparing (7.42) and (7.43), it can be seen that when Eq. (7.44) is established, condition 2 is established: LK ¼ LK1 þ K 2 LK2 þ ðK  1Þ2 LK3

ð7:44Þ

196

7 Impedance Source Inverters Analysis

To sum up, when Eqs. (7.38) and (7.44) are established simultaneously, the working characteristics of the simplified model shown in Fig. 7.7b will be consistent with the p model. Therefore, the simplified model can be used to replace the p model in the following analysis. In addition, although the simplified coupled inductors’ model in this section is derived based on Y-type coupled inductors, the same simplification strategy can apply to other types of coupled inductors. This is because other kinds of coupled inductors are the special cases of Y-type coupled inductors. For example, when N1 = 0, LK1 = 0, Y-type coupled inductors will change as C-type coupled inductors. Besides, Y-type coupled inductors will become to T-type coupled inductors when N2 = 0, LK2 = 0 [20].

7.3.1.2

Derivation of the Whole Circuit Model

Figure 7.8 shows the novel model evolution process of the impedance network of IYSI. The original circuit is shown in Fig. 7.8a. The coupled inductors are represented by the simplified model, which include ideal coupled inductor (N1, N2, N3), leakage inductance (LK), and the magnetizing inductor LM. In practice, the capacitance of C1, C2 and the inductance of Lin, LM are chosen large enough and the time duration of the transient state is very small. Therefore, the energy of C1, C2, Lin, LM is assumed not change in the transient analysis. With this assumption, capacitors C1, C2 can be used in a same way as voltage source and inductors Lin, LM can be used in a same way as current source. By replacing the capacitors with voltage sources and replacing the inductors with current sources, Fig. 7.8b can be obtained. For the ideal coupled inductor, if the turns ratio and the voltage and current of one winding are known, the voltage and current of the other windings can also be derived. Therefore, the ideal coupled inductor can be represented by the controlled voltage source and the controlled current source. Choose the voltage v13 across the winding N1 and N2 as the controlled voltage and choose the current i2 as the controlled current. Their value can be derived as v13 ¼ KVC1  KVdc

ð7:45Þ

N1 ðiL  IM Þ þ N2 i2 þ N3 i3 ¼ 0

ð7:46Þ

iL ¼ i2 þ i3

ð7:47Þ

N3 where K ¼ NN13 þ N2 is the turns ratio of the coupled inductor.

7.3 Transient Analysis Based on Impedance Source Inverter

(a)

197

(b)

VC2

C2

SW vdc

N2

−

C1

(d)

VC2

KiL

KIin

−

+

−

SW vdc

Io

+ −

+

−

Io

Kvdc KVc1 KiL

SW

vdc

Io

(K+1)Iin

−

+

(j) −

−

+

−

−

(k)

vLK + vD1

+

iL LK −

VD1,ST

D1

(K+1)Iin

+

Io

vdc

+

KiL SW

−

D1

K:1 SW

VD1,ST

−

+

−

VD1,ST

+

D1 Kvdc

vLK + vD1

iL LK

−

vLK + vD1

iL LK +

(K+1)Iin

+

(K+1)Iin

(i)

Io

−

KiL SW vdc

+

−

+

−

D1 + vLK − vD1 LK iL

Kvdc KVc1

SW vdc

VC2

+

KiL

−

KiL

(h)

VC2

D1 + vLK − vD1 LK iL

Kvdc KVc1

−

−

−

(g)

+

KIin SW vdc KIin

KiL

Iin

+

+

Io

−

Kvdc KVc1

+

−

−

VC2 D1 + vLK − vD1 LK iL

+

−

+

(f)

+

D1 + vLK − vD1 LK iL

KIin

KiL

VC1

VC2

(e)

Io

Kvdc KVc1

Iin Iin

−

SW vdc

+

D1 + vLK − vD1 LK iL

−

Kvdc KVc1

VC1

−

Iin

−

D1 + vLK − vD1 LK iL

Io

VC2

+

+

(c)

SW vdc

N2 +

VC1

N3

IM

Vin

Io

N1

+

−

+

Vin

Iin

N3

IM

+

D1 + vLK − vD1 LK

−

Iin

VC2 N1

+

Lin

−

D1 + vLK − vD1 LK

K:1 RSW

Coes vdc

Fig. 7.8 The novel model evolution process of the IYSI

Io

(K+1)Iin

vdc

Io

(K+1)Iin

198

7 Impedance Source Inverters Analysis

Substituting (7.47) to (7.46) then leads to i2 ¼ KiL 

N1 IM N3  N2

i3 ¼ ðK  1ÞiL þ

N1 IM N3  N2

ð7:48Þ ð7:49Þ

Through the simplified method mentioned in last section, the magnetic inductance of IYSI can be easily obtained, i.e., IM ¼ N1 Nþ1 N3 Iin , substitute it into (7.48) and (7.49) derives i2 ¼ KiL  KIin

ð7:50Þ

i3 ¼ ðK  1ÞiL þ KIin

ð7:51Þ

Then Fig. 7.8c can be obtained. In addition, when a voltage source connects with a current source in series, the voltage source can be removed freely. Therefore, Vin is removed in Fig. 7.8c. We can also freely add or remove a current source that connects with a voltage source in parallel. Therefore, a current source Iin, which is connected in parallel with voltage source VC2, is added in Fig. 7.8d. Because there is no equivalent current flowing through the dash line in Fig. 7.8d, the dash line can be removed. The current source Iin is then connected in parallel with vdc. For the same reason, the dash line in Fig. 7.8e can also be removed, and the current source KIin will connect in parallel with Io. Thus, Fig. 7.8f can be obtained. Figure 7.8g and h can be obtained with same method. Then, the circuit can be divided into two parts as shown in Fig. 7.8i. The value of VD1,ST is VD1 ;ST ¼ VC2 þ KVC1

ð7:52Þ

dK Equations VC1 ¼ 1ð1d 1 þ K Þd Vin and VC2 ¼ 1ð1 þ K Þd Vin can be read through the simplified method mentioned last section easily, and substituting them into (7.52) derives

VD1 ;ST ¼

K Vin 1  ð1 þ K Þd

ð7:53Þ

It can be seen that the controlled sources Kvdc and KiL in Fig. 7.8j perform like a transformer and the ratio is K: 1. Therefore, the controlled source can be replaced by an equivalent direct current (DC) and alternating current (AC) transformers shown in Fig. 7.8k. The inverter bridge can be equivalent to a switch SW. As shown in Fig. 7.8k, when the switch SW turns on or turns off, it can be viewed as a variable resistor RSW in parallel with the capacitor Coes.

7.3 Transient Analysis Based on Impedance Source Inverter

199

It can be easily found that the circuit shown in Fig. 7.8k looks like a boost converter. When the inverter bridge shoot-through, the diode D1 will reverse biased, and when the inverter bridge work on the normal state, the diode D1 is turned on.

7.3.2

Switching Transient Analysis

Figure 7.8k can be further simplified to circuit of Fig. 7.9, where CD represents the parasitic capacitor of the diode D1 and Vi is the voltage across D1 and LK. The corresponding theoretical waveforms are shown in Fig. 7.10 when the inverter bridge shoots through. During [t0, t1], the SW is turning on. Since the current through LK cannot change rapidly, nearly no current will flow through SW and SW can turn on in zero current switching (ZCS) condition. However, the energy stored in the parallel capacitor Coes of SW will consumed in SW, which will be analyzed short after. During [t1, t2], the inductor LK in Fig. 7.9 is discharged and the current through LK will linearly drop to zero. During [t2, t3], the diode D1 is reverse biased. The current iL charges CD, and the voltage vD1 will thus increase. As shown in Fig. 7.10, the WL is the energy absorbed by the LK and WC is the energy absorbed by the CD. WL and WC play different roles when analyzing the diode loss. The energy WC absorbed by CD during [t2, t3] will not dissipate before D1 turns on. For t > t3, the ringing of the resonant circuit formed by the LK and CD causes the WL to be circuited back and forth between them. The parasitic loss elements in the circuit will cause the ringing amplitude to eventually decay to zero, then the energy WL will become lost as heat in the parasitic elements. The turn-off loss of the D1 can be derived as Pr ¼

1 1 WL ¼ LK i2L ðt3 Þ T 2T

ð7:54Þ

1 1 WL ¼ LK i2L ðt3 Þ T 2T

ð7:55Þ

The diode ringing period is Pr ¼

iL(t)

Fig. 7.9 Simplified circuit for Fig. 7.8k

LK

iC(t)

Vi

+

vLK(t)

−

D1

vD1(t)

CD

200 Fig. 7.10 Theoretical waveforms of I-YSI when SW turning on

7 Impedance Source Inverters Analysis

SW NST

ST

t vLK

t

Vi Vi,NST

Vi,ST

t iL

t

WL vD1 Vi,ST WC

t0 t1 t2 t3 t4

t

During [t1, t2], the slop of iL is diL VD ;ST ¼ 1 dt LK

ð7:56Þ

The turning-off transient process of SW is much more complex because both Coes and CD are involved in the resonance with LK at the same time. Define the dc-link current idc as Idc ¼ ðK þ 1ÞIin  Io

ð7:57Þ

Then Fig. 7.11 can be derived. When SW turns off, the corresponding theoretical waveforms are shown in Fig. 7.12. The details of this transient are described as follows. During [t0, t1], Coes is charged by Idc. The current flows through RSW, which causes power losses. The energy absorbed by Coes is WCSW1 and consumed energy in RSW is represented as WRSW1. CD is discharged and LK is charged. The energy absorbed of LK is WL0.

7.3 Transient Analysis Based on Impedance Source Inverter

vD1 +

+

−

Idc

D1

vLK

−

Fig. 7.11 Simplified circuit for Fig. 7.8k

201

iL

LK CD

vdc

RSW

VD1,ST

SW

Coes iSW

Fig. 7.12 Theoretical waveforms of I-YSI when SW turning off

SW ST

NST t

vLK t vSW

iSW

KBVin

WRSW2+WCSW2

WRSW1+WCSW1

t

t iL

Iin/(1−d) WL1

vD KBVin

WL2 WL0

t

t0 t1 t2 t3

t

During [t1, t2], vLK is high and the current iL increases a lot. CD is discharged during this interval. WC, which has been absorbed by CD when D1 turns off, is recycled to the LK and Re. Therefore, the turn-on loss of D1 is zero. Coes and RSW continuously absorb the energy WRSW2 and WCSW2, respectively. But iSW decreases

202

7 Impedance Source Inverters Analysis

a lot during this subinterval. The energy absorbed by LK during this interval is represented by WL1. During [t2, t3], the current through LK is equal to the current Idc. The SW is fully turned off, namely, RSW ! 1. The D1 turns on and CD is shorted. The extra energy of Coes will gradually transmit to LK. The energy absorbed by LK during this interval is represented by WL2. WL2 will circuit back and forth between the LK and Coes after t3. The parasitic loss elements in the circuit will cause the ringing amplitude to eventually decay to zero. Thus, WL2 can be viewed as part of the turn-off loss of SW. The switching loss of the SW includes the turn-off loss PSWr and turn-on loss PSWon. Figure 7.13 shows the energy flow of the system shown in Fig. 7.11. During each interval, the first row represents the input energy, the second row represents the energy hold by the system, and the third row represents the output energy. This energy flow diagram gives an easier way for analyzing the complex energy flowing process of the system. After t2, SW fully turns off and D1 fully turns on, then resonance begins to occur on the circuit. The energy from Idc is equal to the energy absorbed by VD1,ST. Thus, as shown in Fig. 7.13, the above two energy flows can be neglected after t2. From Fig. 7.13, it can be easily found that the turn-off loss of switch is TPSWr ¼ WRSW1 þ WRSW2 þ WL2

ð7:58Þ

where T is the switching period of the SW. As described before, the turn-on loss of switch is the energy on Coes, that is TPSWon ¼ WCSW1

Energy from Idc

ð7:59Þ

Energy from Idc

Input energy

WCSW1 Energy hold by system

Wc

WCSW1

WCSW1

WL0+WL1+WL2

WL0+WL1

WCSW1+WCSW2

WL0+WL1

WL0 Wc

WL0+WL1

WCSW1

WL2 Output energy WRSW2

WRSW1 t0

Fig. 7.13 Energy flow diagram

t1

VD1,ST t2

t3

SW2 turn on

7.3 Transient Analysis Based on Impedance Source Inverter

203

According to Fig. 7.13 and Eqs. (7.58), (7.59), the following expression can be obtained as Z ¼

T ðPSWon þ PSWr Þ ¼ WRSW1 þ WRSW2 þ WL2 þ WCSW1 Z t2 t2 Idc vSW ðtÞdt þ WC  VD1 ;ST iL ðtÞdt  WL1  WL0

t0

Z

t2

¼

t0

Z

t2

Idc vSW ðtÞdt þ WC 

t0

Z ¼

t2

VD1 ;ST iL ðtÞdt 

t0 t2

Z Z

t2

Idc vSW ðtÞdt þ WC 

t0



vLK ðtÞiL ðtÞdt

ð7:60Þ

t0

vLK ðtÞ þ VD1 ;ST iL ðtÞdt

t0

As shown in Fig. 7.12, vD1 nearly drops to zero at t2. Therefore, we can suppose that the energy of CD drops to zero at t2. The following expression can be obtained as Z WC 

t2

vD1 ðtÞiL ðtÞdt

ð7:61Þ

t0

Substituting (7.61) into (7.60) then yields to Z  t0

t2

Z Idc vdc ðtÞdt  t0

t2

T ðPSWon þ PSWr Þ

vLK ðtÞ þ VD1 ;ST  vD1 ðtÞ iL ðtÞdt

Z

¼

t2

Z Idc vdc ðtÞdt 

t0

Z ¼

t2

vdc ðtÞiL ðtÞdt

t0 t2

½ILe  iL ðtÞvdc ðtÞdt t0  Z t2

Iin  iL ðtÞ vdc ðtÞdt ¼K 1d t0  Z t2

KIin ¼  KiL ðtÞ vdc ðtÞdt 1d t0

ð7:62Þ

After t2, since D1 fully turns on, the CD is short-circuited. So LK will only resonant with Coes, and the resonant period can be derived as pffiffiffiffiffiffiffiffiffiffiffiffiffiffi Tresonant ¼ 2p LK Coes

ð7:63Þ

From Eq. (7.62), it can be found that the loss of IYSI is the function of iL, vdc and the time duration of [t0, t2]. From Fig. 7.8k, the LK will cause the iL change slowly, and thus time duration of [t0, t2] will be long. In addition, since the iL change slowly, iSW will also change slowly and will cause great voltage spike in the

204

7 Impedance Source Inverters Analysis

OFF SW, which have great RSW. So vdc will be big. These two reasons can introduce great power loss on the SW of IYSI.

7.3.3

Experimental Results

The experimental parameters are listed in Table 7.2. The inductance of the equivalent magnetizing inductor is LM = 0.366 mH. The leakage inductances of N1, N2, and N3 in the p model are LK1 = 1.23 lH, LK2 = 0.73 lH, LK3 = 5.4 lH. So the LK = 29.4 lH according to Eq. (7.52). The CD = 110 pF. Then the results are described as follows. Experimental testing of a 200 W prototype controlled by a TMS320F2812 DSP has been built and shown in Fig. 7.14. Figure 7.15 shows the DC-link voltage. The normal value of dc-link voltage is 194 V. However, a huge voltage spike (530 V) can be seen from Fig. 7.15. Figure 7.16 shows that the winding current will change suddenly during the switching transient. This sudden change will cause great voltage across the leakage inductances, and then introduce huge voltage spikes in the DC-link. The input and output waveforms are shown in Fig. 7.17. The switching waveform when SW turning on is shown in Fig. 7.18a. It can be easily found that Fig. 7.18a matches well with the theoretical waveform shown in Fig. 7.10. The switching waveform when SW turning off is shown in Fig. 7.18b. Figure 7.18b matches well with the theoretical waveform shown in Fig. 7.12. This proves the correctness of the model. The ringing period read from Fig. 7.19a is Tringing = 0.38 ls, which is very close to the theoretical value 0.357 ls that calculated from Eq. (7.55). The VD1,ST in Table 7.2 System parameters of IYSI

Parameter

Value/part number

Minimum input voltage Maximum input voltage Output voltage (peak to peak) Dc-link voltage Capacitances C1 and C3 Capacitances C2 Inductances Lin Switching frequency Turns ratio Core Switches Diodes D1 and D2 Filter inductance Lf Filter capacitance Cf

60 V 200 V 160 V 200 V 470 lF 100 lF 4.3 mH 10 kHz 40:40:80 (K = 3) C055863A2 IRGP4062DPbF 30EPH06PBF 5.6 mH 4.7 lF

7.3 Transient Analysis Based on Impedance Source Inverter

205

Auxiliary Power

Coupled Inductors

S1

Lf

S2

S3

S4

D1

C3 C2

Cf C1

D2

Lin Vin

Vo

Fig. 7.14 Laboratory setup of IYSI

Vdc:200V/div

0 t(2ms/div) Fig. 7.15 Experimental waveform of Vdc

Fig. 7.19a is about 540 V, while the VD1,peak is about 2 times of the VD1,ST, namely, 1080 V. This fits the resonance theory. The resonant period of the voltage spikes read from Fig. 7.19b is Tresonant = 0.3 ls. The data sheet does not provide the Coes when vdc > 100 V, but with curve fitting technology, the output capacitor of switches is about 35 pF when vdc = 200 V. In a single-phase inverter bridge, the voltage of two paralleled switches will rise when the IYSI enters NST state. Thus, the Coes of SW is equal to 70 pF. The theoretical value is Tresonant = 0.285 ls according to Eq. (7.63).

206

7 Impedance Source Inverters Analysis

0

i1:2.4A/div ST state

0 i2:5A/div NST state i3:4A/div 0 t(10μs/div) Fig. 7.16 Experimental winding currents i1, i2, and i3

0

Vin:100V/div

0

vo:100V/div

Iin:3A/div

0

0 io:2A/div t(10ms/div) Fig. 7.17 Experimental input voltages Vin, input currents Iin, output voltages vo, and output currents io

7.3 Transient Analysis Based on Impedance Source Inverter

(a)

207

(b)

Vdc :100V/div 0

Vdc :200V/div

KBVin

0

iD1:2A/div

Iin/(1-d)

0 vD1:400V/div

iD1:2A/div

0

0

vD1:400V/div

t0

t1

t2

t3

t4

0

t(80ns/div)

t0 t1

t2

t3 t(80ns/div)

Fig. 7.18 Experimental switching waveform of IYSI a SW turning on. b SW turning off

(a)

(b)

Vdc :100V/div 0

0

VD1,pe ak

Vdc :200V/div

iD1:2A/div

iD1:2A/div

0 0

VD1,ST 0

Tringing

vD1:400V/div

vD1:400V/div 0

t(200ns/div)

t(200ns/div)

Fig. 7.19 Experimental switching waveform of a ringing period. b resonant period

The experimental value of Tringing is slightly bigger than the theoretical value. This is mainly caused by the neglection of the stray inductance of the PCB and the equivalent series inductance of the capacitors. The gap between the experimental and theoretical value of Tresonant can be mainly attributed to the inaccuracy of the curve fitting method. With Eq. (7.62) and the numerical method, the switching loss of SW is 10.6 W, which is 5.3% of the whole transferred power.

208

7.4

7 Impedance Source Inverters Analysis

Summary

This chapter firstly presents a reactive component elimination method for analyzing voltage and current stresses of impedance source inverters with coupled inductors and many reactive components. The procedure starts by using ampere-second and voltage-second balancing principles to establish simplified equivalent average circuits for the converter. The average circuits then permit various current and voltage expressions to be derived easily. As an example, both traditional and proposed procedures have been used for analyzing the complex HS-YSI. Then a novel model to analyze the switching transient process of the coupled inductor impedance source inverter is proposed. This model can simplify the complex impedance network to a concise boost converter structure without lost any transient details. With this model, the quantitative analysis becomes very easy for the loss and resonant calculation. In addition, this model can be further extended to other inverter or converters. The experimental results have verified the effectiveness and the accuracy of this model.

References 1. F.Z. Peng, Z-source inverter. IEEE Trans. Ind. Appli. 39(2), 504–510 (2003) 2. O. Ellabban, H. Abu-Rub, Z-source inverter: topology improvements review. IEEE Ind. Electron. Mag. 10(1), 6–24 (2016) 3. W. Qian, F.Z. Peng, H. Cha, Trans-z-source inverters, in Proceedings of ECCE ASIA (2010), pp. 1874–1881 4. P.C. Loh, D. Li, F. Blaabjerg, C-Z-source inverters. IEEE Trans. Power Electron. 28(11), 4880–4884 (2013) 5. Y.P. Siwakoti, G.E. Town, P.C. Loh, F. Blaabjerg, Y-source inverter. in Proceedings of PEDG (2014), pp. 1–6 6. R.R. Ahrabi, M.R. Banaei, Improved Y-source DC–AC converter with continuous input current. IET Power Electron. 9(4), 801–808 (2016) 7. H.P. Liu, Z.C. Zhou, K. Liu, P.C. Loh, W.Wang, D.G. Xu, F. Blaabjerg, High step-up Y-source inverter with reduced DC-link voltage spikes. IEEE Trans. Power Electron. Early Access (2018) 8. K.-I Hwu, W.-Z. Jiang, Analysis, design and derivation of a two-phase converter. IET Power Electron. 8(10), 1987–1995 (2015) 9. L. Yang, X.B. Zhang, B. Wu, K. Smedley, G.P. Li, Constant on-time variable frequency one-cycle control for switched-capacitor converter, in Proceedings of ITEC (2016), pp. 1–6 10. L. Yang, W.J. Zhang, X.B. Zhang, G.P. Li, Nonlinear variable frequency control of high power switched-capacitor converter, in Proceedings of IPEMC-ECCE Asia (2016), pp. 3472– 3476 11. T.J. Liang, K.C. Tseng, Analysis of integrated boost-flyback step-up converter. IEE Proc. Electr. Power Appl. 152(2), 217–225 (2005) 12. G.Q. Chen, J.L. Kang, Methods to recover modulating wave in three-phase inverters simulation, in Proceedings of ICICA (2010), pp. 670–673 13. H. Liu, Y. Li, Z. Zhou, W. Wang, D. Xu, A family of low-spikes, high-efficiency Y-source inverters. IEEE Trans. Ind. Electron. 66(12), 9288–9300 (2019) 14. M. Adamowicz, N. Strzelecka, T-source inverter. Electr. Rev. 85(10), 233–238 (2009)

References

209

15. M.-K. Nguyen, Y.-C. Lim, S.-J. Park, Improved trans-z-source inverter with continuous input current and boost inversion capability. IEEE Trans. Power Electron. 28(10), 4500–4510 (2013) 16. Z. Aleem, M. Hanif, Operational analysis of improved Г-Z-source inverter with clamping diode and its comparative evaluation. IEEE Trans. Ind. Electron. 64(12), 9191–9200 (2017) 17. A. Hakemi, M. Sanatkar-Chayjani, M. Monfared, D-source impedance network. IEEE Trans. Ind. Electron. 64(10), 7842–7851 (2017) 18. M. Forouzesh, A. Abdelhakim, Y. Siwakoti et al., Analysis and design of an energy regenerative snubber for magnetically coupled impedance source converters[C], in 2018 IEEE Applied Power Electronics Conference and Exposition (APEC) (San Antonio, TX: IEEE, 2018), pp. 2555–2561 19. S.-P. Hsu, Problems in Analysis and Design of Switching Regulators[D] (California Institute of Technology, Pasadena, CA, 1980), pp. 61–80 20. Y.P. Siwakoti, F. Blaabjerg, P.C. Loh, New magnetically coupled impedance (Z-) source networks. IEEE Trans. Power Electron. 31(11), 7419–7435 (2016)

Chapter 8

Reliability Research on Impedance Source Inverters

Abstract Advances in power electronics enable efficient and flexible processing of electric power in the application of renewable energy sources, electric vehicles, adjustable-speed drives, etc. More and more efforts are devoted to better power electronic systems in terms of reliability to ensure high availability, long lifetime, sufficient robustness, low maintenance cost, and low cost of energy. The reliability of electronic components was the subject of intensive research over the past decades, and further intensive research will certainly be continued in the future, i.e., the component manufacturers are pressed by new and stringent reliability demands from the component users. On the other hand, the component and technology complexities are continuously growing and setting new problems in analysis and design of component reliability. The component reliability level is increased by improving the design and component technology, and there are real problems to verify the component reliability in a traditional way and to convince the component buyers that a particular product indeed is as reliable as the manufacturer might claim. This chapter will introduce the method of reliability evaluation on impedance source inverters to give an outline on how to design reliability into the power electronic products from the early concept phase.

8.1

Existing Reliability Analysis Methods

8.1.1

Basic Concept of Reliability and Evaluation Index

8.1.1.1

Basic Concept of Reliability Theory

Reliability theory was born in the 1940s. Although it was proposed later, it developed rapidly. It was first used in aerospace, electronics, and other industries in the United States, and then quickly spread to other countries such as the Soviet

© Springer Nature Singapore Pte Ltd. 2020 H. Liu et al., Impedance Source Inverters, https://doi.org/10.1007/978-981-15-2763-0_8

211

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8 Reliability Research on Impedance Source Inverters

Union and Japan. In the 1970s, with the wide application of various electronic devices in various fields, industrial production, and people’s daily life, the application of reliability theory has improved the safety reliability in production and life greatly. After entering the twenty-first century, improving the reliability of products and systems has become an effective way to ensure product quality and system safety. Reliability is usually defined as the product’s ability to perform specified functions under specified conditions and within specified time. Product may mean any component, device, system, or component which is the subject of a study or an experiment. In the study of reliability of impedance source inverters, components refer to the general term for a class of devices that need no further refinement in reliability analysis and can be considered as a whole, such as IGBT, isolation switch, support capacitance, etc. However, the system is a system that contains all the components of the inverter. Generally, components can be divided into repairable components and non-repairable components. For repairable components, if they are damaged during application period, they can be restored to the original working state through maintenance. For non-repairable components, once damage occurs, it is technically difficult to repair, or repairable but not economical. The impedance source inverter itself is a repairable system that needs to be repaired and maintained. Its entire operation cycle includes the whole process of work, failure, rework, and re-failure. However, most components of the inverter are not repairable. When the inverter system breaks down, the relevant faulty components need to be replaced and will be restored as new, while the inverter cannot restore the original reliability. Figure 8.1 shows the working state of repairable system. The system has two states: normal operation state U and fault shutdown state D. The working time TU and repair time TD of components are non-negative random variables. According to the formation of product reliability, reliability can be divided into the using reliability and inherent reliability. The inherent reliability is the reliability given to a product by design and manufacture; using reliability is not only influenced by design and manufacture, but also influenced by the conditions of use. The using reliability is generally lower than the inherent reliability.

U

D

TU

TU

TD

Fig. 8.1 The working state of repairable system

TU

TD

TU

TD

8.1 Existing Reliability Analysis Methods

8.1.1.2

213

Index of Reliability Evaluation

(1) Reliability and unreliability Reliability is the probability of the product completing the specified function under specified conditions and within specified time, which is usually expressed by R(t), also known as reliability function and reliability distribution function. RðtÞ ¼ PðT  tÞ

ð8:1Þ

where t is the specified time, and T is the lifetime of the product. Reliability is a function of time; the initial reliability is the highest, that is, 1. The longer the reliability takes, the less it is. Unreliability is the probability of failure to complete the specified function, usually expressed as F(t); the relationship can be calculated as FðtÞ ¼ 1  RðtÞ

ð8:2Þ

(2) The function of failure density The function of failure density, also known as the failure probability density function, is usually expressed by f(t), which represents the failure probability of the product at time t. Its value is the derivative of the unreliability, and its relationship with the reliability is f ðtÞ ¼ 

dRðtÞ dt

ð8:3Þ

(3) Failure rate Failure rate refers to the probability of failure occurring in unit time after the product which has not failed at a certain time t, also known as instantaneous failure rate and failure function, which is usually expressed as k(t). Failure rate is a kind of conditional probability, also known as failure rate. It can prove that the relationship between failure rate and reliability is (

kðtÞ ¼ d lndtRðtÞ  Rt  RðtÞ ¼ exp  0 kðtÞdt

ð8:4Þ

The failure data of a large number of different types of elements show that the failure curve is generally the bathtub curve, as shown in Fig. 8.2. Corresponding to the three stages of component life in the bathtub curve, failure rate is also divided into early failure rate, accidental failure rate, and loss failure rate. The early failure rate corresponds to the initial period when the component is put into use. The failure rate is relatively high when the component is put into use,

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Failure rate (%)

Fig. 8.2 Failure rate tub curve

Infant Mortality Wear Out Useful life

Time (years)

which is usually due to its own material defect or design defect. With the increase of modulation and service time, the failure rate will gradually decline. The accidental failure rate corresponds to the effective life of the element. In this stage, the failure rate of the element is mainly related to the random change of the working environment and stress conditions of the element. The failure rate is stable at a low level, which is generally considered to be a constant value. Loss failure rate refers to the aging period of components, showing a rapidly rising trend, which is mainly caused by the wear and aging of components after long-term operation. The accidental failure period is the best working period of the components, and the calculation of failure rate also focuses on the accidental failure rate. (4) Mean lifetime Mean lifetime is the mean time without failure or mean time between failures, usually expressed by mean time between failure (MTBF). For unrepairable products, mean lifetime is the average working time before failure, usually expressed as mean time to failure (MTTF). It can be proved that the relationship between MTTF and reliability is Z

1

MTTF ¼

RðtÞdt

ð8:5Þ

0

For a device whose reliability follows an exponential distribution, when the failure rate k(t) is constant k, the above equation becomes MTTF ¼

1 k

ð8:6Þ

(5) Mean time to repair Mean time to repair refers to the average repair time of components, usually expressed as MTTR. If the maintenance density function m(t) is known, there is

8.1 Existing Reliability Analysis Methods

215

Z MTTR ¼

1

tmðtÞdt

ð8:7Þ

0

The truth value of reliability index is only a theoretical value. In practical engineering, the reliability index observation value of components can also be obtained through detailed historical records and certain statistical analysis.

8.1.2

Method for Predicting Device Reliability

8.1.2.1

Method for Stress Analysis

The stress analysis method is a traditional method to calculate the failure rate of products, which is used to quantitatively calculate the reliability level of components. Factors including electrical stress, thermal stress, and its own quality are taken into account. The corresponding reliability prediction handbooks are MIL-HDBK-217F of the US army and GJB/Z 299C of China. In the prediction handbook, the failure rate prediction model of the general component can be expressed in the form of the basic failure rate multiplied by a series of stress coefficients. k p ¼ k b  pE  pQ  pT

ð8:8Þ

where kp represents the failure rate of the device, which is the value desired, kb is the basic failure rate of the device, pE, pQ, and pT, respectively, represent the environment coefficient, mass coefficient, and temperature stress coefficient of the component. The coefficients are derived from statistical data and can be obtained by looking up tables. The data in the reliability prediction handbook, based on a large number of engineering practice statistics, provides basic data and methods for reliability assessment of electronic components and systems. However, since a set of coefficients can only obtain a fixed predicted result, this method does not take into account the time-varying characteristics of component conditions and cannot consider the working history of components. Therefore, this method is more suitable for estimating the reliability of devices under stable working conditions.

8.1.2.2

Method for Physics of Failure

With the development of reliability technology, physics of failure (PoF) has gradually attracted people’s attention in the 1980s. PoF method has become a new reliability evaluation method, including reliability design, evaluation, and reliability prediction. The core of PoF method is to identify the potential failure mechanism of

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products, find out the root cause of failure, determine the weak link of reliability, establish failure mechanism model, conduct data fusion analysis, and establish life prediction equation. The failure physics of components is the basis of PoF method. Electronic components will be subjected to various stresses during working. When the functions of components fail, the failure mode is related to the action mode of various stresses and the characteristics of the components themselves. The process of failure is a process of microscopic change. Under certain conditions, the material itself will gradually change from the normal state to the abnormal state. Over time, the component will irreversibly degrade to a state of failure. Reliability prediction based on PoF is to evaluate the reliability of electronic products or materials according to the cumulative damage mechanism of physical and chemical processes. The conventional life prediction model only can predict the lifetime of the component under a single working condition. PoF studies the process of device transition from normal state to failure state. In this process, the operating condition of component changes with time. Therefore, in order to evaluate the lifetime of component under time-varying condition, it is necessary to establish corresponding PoF model where the linear cumulative damage model is usually employed. In practical work, the junction temperature of power module changes as the change of load and real time. Due to the different thermal expansion coefficients of the device internal materials, each part will cause the change of heat engine stress, and it is due to long-term sustained stress produced by the engine damage accumulating lead to fatigue failure of the power device. Therefore, in addition to the aforementioned failure model, Miner linear damage theory is needed to predict the lifetime of power devices with real-time load changes [1]. According to this theory, each temperature cycle change will cause some damage to the device, and the damage gradually accumulates, eventually leading to the device failure. The linear cumulative damage theory is widely used because of its simple form and convenient use. According to the linear cumulative damage theory, the fatigue damage caused by each stress is a linear accumulation of the damage caused by each stress. The damage of the device under the action of stress Fi is Di = ni/Ni, ni is the number of cycles of the device under the action of stress Fi, and Ni is the number of cycles from operation to failure under the action of stress Fi. The total cyclic damage D can be expressed as D¼

k X i¼1

Di ¼

n1 n2 nk þ þ  þ N1 N2 Nk

ð8:9Þ

And the device fails when D = 1. Compared to empirical failure analysis based on historical data, PoF method requires the knowledge of deterministic science (i.e., materials, physics, and chemistry) and probabilistic variation theory (i.e., statistics). The analysis involves the mission profile of the component, type of failure mechanism, and the associated

8.1 Existing Reliability Analysis Methods

217

Table 8.1 Failure mechanisms, relevant loads, and models in electronics Failure mechanisms

Failure sites

Relevant loads

Failure models

Fatigue

Die attach, wire bond/TAB solder, leads, bond pads, interfaces Metallization Metallization Between metallization

DT, Tmean, DT/dt, dwell time, DH, DV M, DV, T T, J M, DV

Non-linear power law (Coffin–Manson) Eyring (Howard) Eyring (Black) Power law (Rudra)

Metal traces

S, T

Dielectric layers

V, T

Corrosion Electromigration Conductive filament formation Stress-driven diffusion voiding Time-dependent dielectric breakdown

Eyring (Okabayashi) Arrhenius (Fowler– Nordheim)

physical–statistical model. Table 8.1 gives examples of wear-out failure mechanisms for electronic components as presented in [2].

8.1.3

The Method for System Reliability Prediction

The system can be divided into repairable system and unrepairable system. Although most equipment belongs to repairable system, the reliability research method of unrepairable system is the foundation of repairable system. Therefore, in the reliability prediction and evaluation of repairable system, the repairable system is usually simplified to the non-repairable system first, and then the reliability index of repairable system is calculated. The reliability calculation methods of the system mainly include analytical method and Monte Carlo method.

8.1.3.1

Reliability Block Diagram Method

The main advantage of the analysis is that it can use strict mathematical model and effective algorithm to analyze the reliability of the system meticulously, with high accuracy. The analytical method can enumerate the meaning of all possible fault states of the system, weigh the calculated results of each state with probability, and then calculate the reliability index. Clear physical concept is the most significant advantage of analytical method, and the calculation results are relatively accurate. However, with the increase of system scale, the number of states of the system will increase greatly, and the workload of reliability calculation using analytical method

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8 Reliability Research on Impedance Source Inverters

will increase exponentially. Therefore, analytical method is mainly used to calculate the reliability index of simple system. Reliability block diagram method is a commonly used analytical method to calculate the reliability index, which is a logical function diagram to describe the reliability relationship among the system elements. The reliability block diagram method is suitable for the reliability calculation of systems composed of independent and non-repairable units. The reliability diagram mainly includes series system, parallel system, and hybrid system. (1) The series system For the series reliability system composed of n units, the system can work normally only if each component can work normally. Its reliability block diagram is shown in Fig. 8.3. Its reliability is the product of the reliability of each independent unit of the system, and it can be calculated as RS ðtÞ ¼

n Y

Ri ðtÞ

ð8:10Þ

i¼1

The failure rate is the sum of the failure rate of each independent unit of the system, and it can be calculated as kS ðtÞ ¼

n X

ki ðtÞ

ð8:11Þ

i¼1

Assuming the failure rate of the above components is constant, the average trouble-free operating time of the system is 1 MTTF ¼ Pn i¼1

ð8:12Þ

ki

Therefore, the method to improve the reliability of series system is to reduce the number of system elements and improve the reliability of weak link elements. (2) The paralleling system For a parallel reliability system composed of n units, the system can work normally if at least one unit can work normally. Its reliability block diagram is shown in Fig. 8.4.

Fig. 8.3 Reliability block diagram of series system

R1

R2

R3

8.1 Existing Reliability Analysis Methods

219

Fig. 8.4 Reliability block diagram of parallel system

R1

R2

R3

Its unreliability is the product of the unreliability of each independent unit of the system, and its reliability can be calculated as 8 n Q > > Fi ðtÞ < FS ðtÞ ¼ i¼1

n Q > > : RS ðtÞ ¼ 1  ð1  Ri ðtÞÞ

ð8:13Þ

i¼1

MTTF ¼

n X 1 i¼1

ki



X

1 1 þ    þ ð1Þn k k þ k þ k þ    þ kn j 1 2 1  i\j  n i

ð8:14Þ

When the failure rates above are all equal, the above equation can be simplified as MTTF ¼

1 1 1 1 þ þ  þ ¼ ln n k 2k nk k

ð8:15Þ

Therefore, one of the methods to improve the reliability of the system is to increase the redundancy of equipment, so that it forms a parallel system. (3) The hybrid system Hybrid system is composed of series system and parallel system. The most common are series–parallel systems and series–parallel systems. The reliability block diagram of series–parallel system is shown in Fig. 8.5. A part of the unit is first connected in series to form a series subsystem, and then connected in parallel to form a hybrid system. Suppose the reliability of each unit is Rij(t), i = 1, 2, …n; j = 1, 2, …mi. Then the reliability of series–parallel system is RðtÞ ¼ 1 

n Y i¼1

" 1

mi Y j¼1

# Rij ðtÞ

ð8:16Þ

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8 Reliability Research on Impedance Source Inverters

1

2

m1

1

2

m2

1

2

mn

Fig. 8.5 Reliability diagram of series–parallel system

The parallel–series system is composed of subsystems connected in parallel, and then these subsystems compose in parallel. The reliability block diagram of parallel–series system is shown in Fig. 8.6. Suppose the reliability of each unit is Rij(t), j = 1, 2, …n; i = 1, 2, …mj. Then the reliability of parallel–series system is RðtÞ ¼

n Y

"

mj Y   1 1  Rij ðtÞ

j¼1

# ð8:17Þ

i¼1

Obviously, the reliability of the parallel–series system is lower than that of the series–parallel system. Photovoltaic panels usually adopt the connection mode of the parallel–series system as shown in the figure. For high-power inverters, the number of PV series in parallel is very large, and the failure of individual series has little effect on the reliability of the system.

1

1

1

2

2

2

m1

m2

mn

Fig. 8.6 Reliability diagram of parallel–series system

8.1 Existing Reliability Analysis Methods

8.1.3.2

221

Monte Carlo Method

Monte Carlo simulation method is a computer simulation method based on probability and statistics which can be called Monte Carlo method or statistical experiment method for short. The Monte Carlo method is realized by simulating on the computer all the random processes that make up the system. After a considerable period of simulation, the various indicators of the system can be calculated. Monte Carlo method is suitable for reliability calculation of complex systems and can take into account more practical engineering conditions, such as maintenance arrangement, network reconstruction, etc. At this time, block diagram method is difficult to construct mathematical models. However, the accuracy of results calculated by Monte Carlo method is related to the number of samples. In order to reduce the error, it is usually necessary to increase the sample size and number of samples. The application of Monte Carlo method in reliability analysis is mainly to simulate the probability of events and the mean value of random variables. The basic idea is as follows: first, a random process or probability model is established for the knotted problem, and then, by repeated sampling of the process or model, the distribution characteristics of the desired parameters are calculated, and then the simulated approximate solution of the desired problem is given. Its sampling principle is mainly based on the law of large numbers, that is, assuming that the mathematical expectation E(n) of the random variable n needs to be solved is x, we can sample n N times according to the probability distribution of n and obtain a series of ni which are mutually independent, and calculate the arithmetic mean of the sequence. The calculation process is shown in Eq. 8.18. n¼

N 1X n N i¼1 i

ð8:18Þ

When N approaches infinity, there is   P lim n ¼ x ¼ 1 N!1

ð8:19Þ

n is approximately the mathematical expectation E(n) of n. n  EðnÞ ¼ x

ð8:20Þ

Suppose there is a certain element i in the system and its running state is represented by Xi. When Xi = 1, it means the element is running normally; when

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8 Reliability Research on Impedance Source Inverters

Xi = 0, it means the element is failing. The probability of the element being in failure is fi. Then the probability function P(Xi) can be expressed as ð8:21Þ For the impedance source inverter, it is composed of a variety of components, and Xi = (X1, X2, …, Xm) can be used to represent the running state of the whole device. Since each component is independent of each other, the joint distribution function of the device can be obtained as Eq. 8.22 shows. PðXi Þ ¼

Y

PðXi Þ

ð8:22Þ

m

Assuming that F(Xi) is the observed value obtained at the ith sampling, the expected mean value required can be expressed as Eq. 8.23. EðnÞ ¼

X

PðXi ÞFðXi Þ

ð8:23Þ

The accuracy of the obtained observations is proportional to the number of samples.

8.2

Failure Mechanism of Power Devices

As mentioned in Sect. 8.1, understanding of the reliability physics of components applied in power electronics is the most fundamental aspect. The PoF approach is based on analyzing and modeling each failure mechanism under various environmental and usage stresses. In practice, the PoF analysis focuses on critical components under critical stress conditions. Among other components, switching devices and capacitors are two of the most vulnerable components in terms of failure level and time as analyzed in [3–6]. They are considered as the reliability critical components in power electronic converters, especially the IGBT modules in medium- to high-power applications and capacitors for DC-link applications. Therefore, in the following parts, the physical structures of different power electronic components are discussed first. Then, the critical stressors and PoF analysis of IGBT modules and DC-link capacitors are given.

8.2 Failure Mechanism of Power Devices

223

8.2.1

Structure of IGBT Module

8.2.1.1

Physical Structure of IGBT Module

The internal structure of IGBT module is shown in Fig. 8.7. The function part of IGBT module consists of IGBT chip and diode chip. In the module, the chip is welded to the DBC substrate, which has an engraved circuit structure. The DBC substrate is divided into three layers. The upper and lower layers are copper plates, and the middle layer is ceramic insulation made of Al2O3 and other materials. The chip is therefore connected to the substrate at the bottom of the module through the substrate. The copper substrate supports and holds the module, and the heat inside the module is effectively dissipated through the copper substrate connection between the chip and substrate, and substrate is achieved by welding layers, which stabilize the layers together and provide a channel for heat transfer, and bonding wires, which provide a current path between the structures.

8.2.1.2

Electrical Structure of IGBT Module

Figure 8.8a shows a schematic diagram of the electrical structure of the N-channel enhanced IGBT. Compared with the N-channel enhanced MOSFET shown in Fig. 8.8b, there is an additional P+ layer hole region, and then a PN junction is formed with the N+ region. From top to bottom, there are N+, P+, N−/N+, and P+ layers, which constitute the top N+/P+, the middle P+/N−, and the bottom N+/P+ junctions. IGBT shown in Fig. 8.8a has three ports: emitter (E), collector (C), and

Terminal

Resin Cast

Control Terminal Injection Shell Welding Layer

Interconnector High-pressure Silica Gel

Substrate

Tube Core Fig. 8.7 The internal structure of IGBT module

Insulating Substrate

Copper Substrate

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8 Reliability Research on Impedance Source Inverters Gate G

(a)

Emitter E

Source S

SiO2

SiO2 N

Gate G

(b)

+

Channel

P+ Drift Region

N−

Buffer Region

N+

Injection Rregion

P+

+

N+

P+

P+

N

Channel

P+

Drift Region

N−

Substrate

N+

Collector C

N+

Drain D

Fig. 8.8 Schematic diagram of IGBT and MOSFET. a N-channel enhanced IGBT. b N-channel enhanced MOSFET

gate (G). For N-channel IGBT, electrons flow out of the emitter and in from the collector. When the voltage Uce at both ends of IGBT is less than zero, due to the PN junction at the bottom is in the state of reverse deviation, no matter whether the channel at the top is open or not, the current cannot pass between the collector and emitter. Therefore, the PN junction at the bottom of IGBT has the ability to reverse block the current. When the voltage Uce at both ends of IGBT is greater than zero and the gate–emitter voltage Uge is zero, the PN junction in the middle is in the state of reverse deviation, and no effective conductive channel can be formed in the channel area at the top part, so the collector current is zero. Only when Uce is greater than zero and Uge is greater than the opening voltage of IGBT, a conductive channel is formed in the P+ region near the gate, so that IGBT is positively guided through.

8.2.1.3

The Package Structure of IGBT Module

It can be seen from Fig. 8.9 that IGBT module has obvious hierarchical structure, which can be roughly divided into chip, direct copper bonded substrate (DBC) and substrate. If the solder layer between the layers is added, the IGBT power module can be subdivided into seven layers.

8.2 Failure Mechanism of Power Devices

Emitter

Bond wire

225

Collector

Gate

Weld Layer

Chip Solder

Ceramic Substrate

} Copper Substrate Fig. 8.9 The hierarchy diagram of IGBT module

IGBT module is composed of different material layers, and the thermal expansion coefficient and thermal conductivity between module levels are quite different, which may cause unexpected problems in the working process of the device. IGBT module is composed of metal, ceramic, and polymer materials, and various materials are also coated with silica gel to improve heat dissipation performance. There are huge differences in thermal expansion coefficient and thermal conductivity between different materials, which can lead to many problems and even lead to failure and damage of power modules.

8.2.2

Failure Mechanism of IGBT Module

The failure mechanism of power module can be divided into two types. The first kind of failure is caused by external factors, from poor control methods or poor design and manufacturing techniques. The second kind of failure mechanism is caused by internal factors and can lead to the performance of power devices decreasing with the extension of service life. It is worth noting that since power devices often operate near physical limits, their failure triggers are usually due to internal (aging) mechanisms, which are quite different from traditional integrated circuits. Therefore, in order to design reliable devices, an important task in the prototype development phase is to classify the observed fault mechanisms in order to find appropriate methods to correct the external fault mechanisms and to quantify and model the internal fault mechanisms. The systematic failure mechanism of silicon carbide iso-wide bandgap devices is not yet mature. The following failure mechanism is mainly aimed at the silicon-based IGBT power module, which is widely used at present.

226

8.2.2.1

8 Reliability Research on Impedance Source Inverters

Package-Related Fault

The multi-chip module of high-power IGBT devices has a complex multilayer structure composed of different materials to ensure good mechanical stability, conductivity, insulation, and heat dissipation. However, these properties are affected by several of the most common failure mechanisms in the power module, which are mainly caused by the lower thermal engine fatigue stress due to the thermal cycling experienced by some packaging materials during work. The main reasons for these failures include mismatches in thermal expansion coefficients between different materials, different characteristic lengths between layers, and local temperature fluctuations. (1) Bond wire fatigue Multi-chip IGBT modules in high-power applications typically contain up to 1000 wedge-shaped bonding lines. These bonding wires are connected by ultrasonic welding, usually on metal coatings 3–5 microns thick or on stress buffers such as molybdenum plates. Since most of the bonding wires are connected to the working area of the semiconductor device (IGBT and secondary diodes), they are permanently exposed to temperature fluctuations caused by the power dissipation of the silicon-based material and to their own heat generated by the ohmic heating effect. It has been proved by experience that the failure caused by the fracture occurs at the tail of the bond line and then extends along the internal grain boundary of the bond line material until the whole bond line falls off completely, as shown in Fig. 8.10. Because the temperature fluctuations at the IGBT emitter near the bonding line are more severe, the bonding line at the IGBT emitter is more likely to fall off than the bonding line near the gate. The fault of a single bonding line often leads to changes in the contact impedance and current distribution. Such faults can be detected by monitoring changes in collector–emitter voltage VCE, so VCE is usually used as the monitoring quantity for bonding line degradation. During power cycle tests at low voltages, the effective life of the device is related to the last failed bonding line. On the contrary, in the actual operating condition (or in the high-voltage test), the reduction of the current path may lead to the chip function disorder or the circuit cannot work directly or even burn out. (2) Bond wire heel crack In the latest power module, bond line heel crack is relatively rare, but the long-term tolerance test can still find the bond line heel crack phenomenon, and especially prone to occur in the ultrasonic welding optimization is not good. In addition, when the fatigue driving force comes from the ohmic heat effect of the bonding line itself, the heel splintering can also be found at the bonding line terminal connected to the IGBT and the continuous-flow diode.

8.2 Failure Mechanism of Power Devices

227

Fig. 8.10 The bond wire crack propagation process

Bond wire

The crack extends inward along the bond wire

Pin fracture

Silicon chip

(3) Surface reconstruction of aluminum Thermal cycling in IGBT modules leads to the mismatch of thermal–mechanical stresses between the silicon substrate and the aluminum metal, which causes cyclic compression and tensile stresses on the metal coatings of IGBT chips and continuous-flow diode chips. Because of the very high hardness and operating temperature of the silicon substrate, the softer aluminum metal layer is subjected to stresses well beyond its elastic strain limit. In this case, depending on the temperature and stress, the bond line will relax under the influence of diffusion creep, grain boundary slip, and dislocation slip. In IGBT devices, the strain rate of the metal coating is determined by the rate of temperature change, because the typical thermal impedance time constant of IGBT is in the millisecond level. Depending on the texture of the metal coating, such stress relaxation can lead to protrusion of metallic aluminum crystal particles or cavitation of grain boundaries, resulting in protrusions and voids. The main consequence of this failure is that the effective contact area of the foil film is reduced and the impedance of the thin film is increased. With the increase of impedance, the collector–emitter voltage VCE increases steadily and linearly with the number of temperature cycles experienced in the power test. Under the problem of step covering of emitter contact hole, the surface reconstruction of aluminum becomes an important problem that affects reliability. In this case, thermomechanical and electromigration effects combine to cause the metal coating to be completely depleted. (4) Welding fatigue and layering The other major failure mechanism of the power module is always accompanied by thermal–mechanical fatigue of the solder alloy. The most critical link in solder alloys, especially in power modules using copper substrates, is the solder joint between the ceramic substrate and the substrate. The key to the vulnerability of the solder joint here lies in the harsh operating environment and special construction,

228

8 Reliability Research on Impedance Source Inverters

Fig. 8.11 Diagram of cracks and voids in welding materials

Silicon chip Direction of heat diffusion

Copper clad substrate

Chip bonding layer

Crack

Hole

including the most severe mismatch of thermal–mechanical stresses between adjacent materials in the module, extremely high-temperature fluctuations, and the large transverse dimensions of the ceramic substrate. For solder joints between ceramic substrates and substrates, the use of a different substrate material, such as aluminum silicon carbide, can reduce the local thermal stress. Another key solder alloy is located between the silicon-based chip and the ceramic substrate. The solder here is under low circumferential thermal cyclic stress, so the fracture usually occurs at the rounded corner of the solder joint and spreads along the brittle intermetallic compounds or precipitates toward the interface of the substrate chip. The rate of crack diffusion is mainly determined by the number of voids introduced into the welding layer during processing. The more the voids, the faster the crack diffusion. Under the combined action of crack and void, the heat dissipation performance of power module is seriously affected, and the thermal resistance increases with time. The increase of thermal resistance makes it difficult for the temperature to disperse, which may aggravate other failure reactions such as bond line shedding. Figure 8.11 shows a schematic diagram of cracks and voids in welding materials.

8.2.2.2

Burning Failure

IGBT modules often burn out due to either robustness problems or the result of excessive aging. The burning fault is usually caused by the short-circuit state of the module, especially when there is too much current in the module. Through the short-circuit current in the module for a long time, it will inevitably bring the thermal runaway inside the module, and eventually lead to the module damage very quickly. In a high-voltage IGBT module, the contact between the neutron component in the cosmic rays and the semiconductor can also cause serious burnout failures. Neutrons collide with IGBT chips or diode chips in the module, causing a recoil effect in the off state and producing ionization bands in the active region. If it happens in the vicinity of the high field intensity region, it will cause a surge of

8.2 Failure Mechanism of Power Devices

229

carriers, which will lead to a locally self-sustaining filament-like discharge, leading to a partial semiconductor melt.

8.2.3

Structure of Capacitor

Capacitors are widely used for DC-links in power converters to balance the instantaneous power difference between the input source and output load, and minimize voltage variation in the DC-link. In some applications, they are also used to provide sufficient energy during the holdup time. Figure 8.12 shows the typical configurations of power electronic conversion systems with DC-link capacitors. Such configurations cover a wide range of power electronics applications, such as in wind turbines, photovoltaic systems, motor drives, electric vehicles, and lighting systems.

Fig. 8.12 Typical configurations of power electronic conversion systems with DC-link capacitors: a AC-DC-DC or DC-DC-AC power converters with a DC-link. b AC-DC-AC power converters with a DC-link. c AC-DC or DC-AC power converters with a DC-link

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8 Reliability Research on Impedance Source Inverters

8.2.3.1

Classification of Capacitors

In production applications, the type of capacitance is usually determined by factors such as capacity required for the application scenario, rated voltage, maximum operating temperature, frequency characteristics, price, size, reliability, etc. Figure 8.13 shows the capacitance and voltage stress ranges of several capacitors in the field of power electronics. Of these, ultracapacitors (double-layer capacitors) are used as energy storage components with the highest capacity but low voltage capacity. Two kinds of capacitors belong to electrolytic capacitors, namely, aluminum electrolytic capacitors and solid tantalum capacitors, which are often used for low-voltage DC busbars below 100 V. In addition, metallized polypropylene film capacitors and multilayer ceramic capacitors are two common types of capacitors. Aluminum electrolytic capacitors, metallized polypropylene film capacitors, and multilayer ceramic capacitors are three commonly used capacitors that cover most of the capacitance and voltage ranges. Capacitance selection and quantification requires matching specific application scenarios, such as different environments, and electrical and mechanical stresses, according to capacitance characteristics and parameters. Figure 8.14 shows the electrical model of the capacitor. C, Rs, and Ls are, respectively, capacitance value, resistance value of equivalent series resistance, and inductance value of equivalent series inductance. The dissipation factor of capacitance is tan = 2pfRsC; RP is the resistance value of insulation resistance; f is the corresponding frequency; RD is the energy that represents the insulation absorption and electron polarization loss of the insulating medium; and CD characterizes dielectric absorption. The most commonly used simplified form of the electrical 100kV

10kV

Voltage

1kV

film capacitor

100V

10V

ceramic capacitor

tantalum capacitor

aluminium electrolytic capacitor supercapacitor

1V 1pF

1nF

1μF

1mF

1F

Capacitance

Fig. 8.13 Capacitance and voltage ranges of common capacitors

1kF

1MF

8.2 Failure Mechanism of Power Devices

231

RP

Fig. 8.14 The electrical model of the capacitor

C

RD

CD

RS

LP

ESR

ESL

model of a capacitor consists of C, Rs, and Ls. It is important to note that the parameters are values at a specific temperature, voltage, and frequency. If the calculation does not take into account the operating factors, the wrong electrical stress will be generated. Figure 8.15 shows the impedance characteristics of the capacitor, which can be divided into three different frequency bands according to the variation of its impedance [7]. Capacitance impedance is determined by capacitance, equivalent series resistance, and equivalent series inductance, respectively. At the resonant frequency, the capacitance’s equivalent impedance value is the minimum, equal to the resistance value of its equivalent series resistance. The capacitance is not allowed to work beyond this frequency; otherwise, the capacitance will become the inductive element. The property of dielectric materials is a major factor that limits the performance of capacitors. Figure 8.16 presents the relative permittivity (i.e., dielectric constant), continuous operational field strength and energy density limits of Al2O3, polypropylene, and ceramics, which are the materials used in Al-Caps, MPPF-Caps, and MLC-Caps, respectively [8]. It can be noted that Al2O3 has the highest energy density due to high field strength and high relative permittivity. The theoretical limit is in the range of 10 J/cm3, and the commercially available one is about 2 J/cm3. Fig. 8.15 Impedance characteristics of capacitors

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8 Reliability Research on Impedance Source Inverters

Fig. 8.16 Energy storage density for various dielectrics (BOPP: biaxial-oriented polypropylene, which is the preferred film material for capacitors rated above about 250 V)

Ceramics could have much higher dielectric constant than Al2O3 and film; however, it suffers from low field strength, resulting in similar energy density as that of film. The three type of capacitors therefore exhibit specific advantages and short-comings. Fig. 8.17 compares their performance from different aspects in a quali-tative way. Al-Caps could achieve the highest energy density and lowest cost per Joule, however, with relatively high ESRs, low ripple current ratings, and wear out issue due to evaporation of electrolyte. MLC-Caps have smaller size, wider fre-quency range, and higher operating temperatures up to 200 °C. However, they suffer from higher cost and mechanical sensitivity. The recent release of CeraLink series ceramic capacitors [9] is of interest to extend the scope of MLC-Caps for dc-link applications. It is based on a new ceramic material of antiferroelectric be-havior and strong positive bias effect (i.e., capacitance versus voltage stress). MPPF Caps provide a well-balanced performance for high voltage applications (e.g., above 500 V) in terms of cost and ESR, capacitance, ripple current and reli-ability. Nevertheless, they have the shortcomings of large volume and moderate upper operating temperature. The DC-link applications can be classified into high ripple current ones and low ripple current ones. The ripple current capability of the three types of capacitors is approximately proportional to their capacitance values as shown in Fig. 8.18. C1 is defined as the minimum required capacitance value to fulfill the voltage ripple specification. For low ripple current applications, capacitors

8.2 Failure Mechanism of Power Devices

233

Fig. 8.17 Performance comparisons of the three main types of capacitors for DC-link applications Fig. 8.18 Capacitance requirement of low ripple current applications and high ripple current applications

with a total capacitance no less than C1 are to be selected by both Al-Caps solution and MPPF-Caps solution. For high ripple current applications, the Al-Caps with capacitance of C1 could not sustain the high ripple current stress due to low A/lF. Therefore, the required capacitance is increased to C2 by Al-Caps solution while the one by MPPF-Caps solution is C1. In terms of ripple current (i.e., ($/A), the cost of MPPF-Caps is about 1/3 of that of Al-Caps [10]. It implies the possibility to achieve a lower cost, higher power density DC-link design with MPPF-Caps in high ripple current applications, like the case in electric vehicles [11] (Figs. 8.17 and 8.18).

8.2.4

Failure Mechanism of Capacitor

DC-link capacitors could fail due to intrinsic and extrinsic factors, such as design defect, material wear out, operating temperature, voltage, current, moisture and mechanical stress, and so on. Generally, the failure can be divided into catastrophic

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8 Reliability Research on Impedance Source Inverters

Table 8.2 Overview of failure modes, critical failure mechanisms, and critical stressors of the three main types of DC-link capacitors (with emphasis on the ones relevant to design and operation of power converters) Cap. type

Failure modes

Critical failure mechanisms

Critical stressors

Al-Caps

Open circuit

Self-healing dielectric breakdown Disconnection of terminals Dielectric breakdown of oxide layer Electrolyte vaporization Electrochemical reaction (e.g., degradation of oxide layer, anode foil capacitance drop) Self-healing dielectric breakdown

VC, Ta, iC Vibration VC, Ta, iC Ta, iC VC

Short circuit Wear out: electrical parameter drift (C, ESR, tand, ILC, Rp) MPPF-Caps

Open circuit (typical)

Short circuit (with resistance)

Connection instability by heat contraction of a dielectric film Reduction in electrode area caused by oxidation of evaporated metal due to moisture absorption Dielectric film breakdown

VC, Ta, dVC/dt Ta, iC Humidity

VC, dVC/ dt Self-healing due to overcurrent Ta, iC Moisture absorption by film Humidity Dielectric loss VC, Ta, Wear out: electrical iC, parameter drift (C, humidity ESR, tand, ILC, Rp) MLC-Caps Short circuit (typical) Dielectric breakdown VC, Ta, iC Cracking; damage to capacitor body Vibration Oxide vacancy migration; dielectric VC, Ta, Wear out: electrical puncture; insulation degradation; iC, parameter drift (C, micro-crack within ceramic vibration ESR, tand, ILC, Rp) VC—capacitor voltage stress, iC—capacitor ripple current stress, iLC—leakage current, Ta— ambient temperature

failure due to single-event overstress and wear-out failure due to the long time degradation of capacitors. The major failure mechanisms have been presented in [12–15] for Al-Caps [16–20] for MPPF-Caps and [21–23] for MLC-Caps. Based on these prior-art research results, Table 8.2 gives a systematical summary of the failure modes, failure mechanisms, and corresponding critical stressors of the three types of capacitors. Table 8.3 shows the comparison of failure and self-healing capability of Al-Caps, MPPF-Caps, and MLC-Caps. Electrolyte vaporization is the major wear-out mechanism of small size Al-Caps (e.g., snap-in type) due to their relatively high ESR and limited heat dissipation surface. For large-size Al-Caps, the wear-out lifetime is dominantly determined by the increase of leakage current, which is relevant with the electrochemical reaction of oxide layer [24]. The most

8.2 Failure Mechanism of Power Devices

235

Table 8.3 Comparisons of failure and self-healing capability of the three types of capacitors Al-Caps Dominant failure modes Dominant failure mechanisms Most critical stressors Self-healing capability

MPPF-Caps

MLCC-Caps

Ta, VC, iC

Wear out Open circuit Moisture corrosion; dielectric loss Ta, VC, humidity

Short circuit Insulation degradation; flex cracking Ta, VC, vibration

Moderate

Good

No

Open circuit Electrolyte vaporization; electrochemical reaction

Fig. 8.19 Corrosion of the metallized layers of a film capacitor. a Separation of metal film from heavy edge by corrosion. b Incomplete edge separation by corrosion

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8 Reliability Research on Impedance Source Inverters

important reliability feature of MPPF-Caps is their self-healing capability [18, 19]. Initial dielectric breakdowns (e.g., due to overvoltage) at local weak points of a MPPF-Cap will be cleared and the capacitor regains its full ability except for a negligible capacitance reduction. With the increase of these isolated weak points, the capacitance of the capacitor is gradually reduced to reach the end-of-life. The metallized layer in MPPF-Caps is typically less than 100 nm [25] which are susceptible to corrosion due to the ingress of atmospheric moisture. In [26], the corrosion mechanism is well studied. Figure 8.19a and b shows the corrosion of the metallized layers of a degraded film capacitor located in the outer turns and inner turns of the capacitor roll, respectively. It reveals that severe corrosion occurs at the outer layers resulting in the separation of metal film from heavy edge and therefore the reduction of capacitance. The corrosion in the inner layers is less advanced as it is less open to the ingress of moisture. Unlike the dielectric materials of Al-Caps and MPPF-Caps, the dielectric materials of MLC-Caps are expected to last for thousands of years at use level conditions without showing significant degradation [22]. Therefore, wear out of ceramic capacitors is typically not an issue. However, a MLC-Cap could be degraded much more quickly due to the “amplifying” effect from the large number of dielectric layers [22]. In [27], it has been shown that a modern MLC-Cap could wear out within 10 years due to increasing miniaturization through the increase of the number of layers. Moreover, the failure of MLC-Caps may induce severe consequences to power converters due to the short-circuit failure mode. The dominant failure causes of MLC-Caps are insulation degradation and flex cracking. Insulation degradation due to the decrease of the dielectric layer thickness results in increased leakage currents. Under high-voltage and high-temperature conditions, Avalanche breakdown (ABD) and thermal

Fig. 8.20 Leakage current of a barium titanate-based MLC-Cap under high temperature and high voltage stresses (ABD: Avalanche breakdown, TRA: Thermal runaway)

8.2 Failure Mechanism of Power Devices

237

runaway (TRA) could occur, respectively. Figure 8.20 shows a study in [21] on the leakage current characteristics of a MLC-Cap with ABD and TRA failure. ABD features with an abrupt burst of current leading to an immediate breakdown, while TRA exhibits a more gradual increase of leakage current.

8.3

Thermal Model of Power Devices

According to the foregoing, the main cause of power device failure is fatigue accumulation caused by long-term thermal–mechanical stress. In order to ensure the reliability of impedance source inverters, thermal modeling, and heating calculation of power devices are required. This section will introduce the method for thermal model of power devices.

8.3.1

Thermal Model of IGBT

The power loss generated during the operation of the power module flows within the module in the form of heat and the heat dissipation path characteristics of the module will directly affect the junction temperature, and the change of junction temperature will cause the change of electrical parameters. Therefore, the electrical and thermal characteristics of IGBT module are coupled with each other. Electrothermal model of IGBT module consists of two parts, power loss model and thermal model. The power loss model represents power loss during the operation of IGBT with the characteristics of voltage, current, and temperature change, the thermal model represents the heat conduction characteristics of the path through when the power loss flows in the form of heat, and it is the key of power module junction temperature evaluation and heat dissipation design. The junction temperature of a module is determined by its total power loss and thermal parameters, however it is very difficult to obtain the junction temperature accurately. Figure 8.21 shows the diagram of electrothermal model for IGBT module; its working principle is the power loss model using the module of operation parameters (current, duty cycle, junction temperature, etc.) to calculate the power loss, and then

Fig. 8.21 Diagram of electrothermal model for IGBT module

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8 Reliability Research on Impedance Source Inverters

the instantaneous power loss values into the hot model, the thermal model to calculate the transient junction temperature of power module, and then the junction temperature values as parameters feedback into power loss model to calculate the power loss, the junction temperature of power module–time curve is obtained [28]. The establishment of the electrothermal model combines the electrical and thermal characteristics of the power module.

8.3.1.1

IGBT Power Loss Model

As shown in Fig. 8.22, in the inverter circuit, the power electronic power device commonly used is IGBT module. As a result of the inverter structure symmetry, various phase IGBTs and diode work voltage and current waveform shape are the same; only a fixed phase difference between them, therefore, needs only to a single IGBT and single-diode power consumption analysis and modeling; the following will be presented in detail, respectively, in all parts of power loss calculation and modeling process. (1) Conductive-state power loss analysis and modeling Conductive-state power loss refers to the static loss caused by the initial saturation drop and on-state resistance during the conduction of IGBT. When the device operates at a lower switching frequency (generally fSW ≦ 400 Hz), its power loss becomes the main part of the total power loss of the device. When the bipolar PWM linear modulation mode is adopted, that is, the value range of modulation m is [0,1], the load is set as resistive load, the dc terminal voltage is Vdc, and the amplitude of ac output voltage is Vmax, then the modulation system is m¼

S1

Vmax 0:5  Vdc

S3

S5

Vdc S2

S4

Fig. 8.22 Circuit diagram of three-phase inverter

ð8:24Þ

S6

AC Filter And 3-phase Load Or Grid

8.3 Thermal Model of Power Devices

239

Suppose its modulation wave ur is sine wave, there is ur ¼ m  sinðxt þ uÞ

ð8:25Þ

In the formula, the phase angle represents the phase difference between ac voltage and current fundamental wave. At a constant switching frequency, regardless of the dead zone time, the duty cycle of IGBT can be expressed as dðtÞ ¼

1 þ m  sinðxt þ uÞ 2

ð8:26Þ

Within a modulation wave period T, VD2 and IGBT1 in Fig. 8.22 are at work and thus produce switch power loss and the power loss of on-state. Therefore, in the first half of the cycle, the power loss modulation waveform should be close to the waveshape that fluctuates with the current. In the latter half period, VD2 and IGBT1 are both in the blocking state and their power loss is zero. In one carrier cycle TSW, the load current ic flows through IGBT1 during dTSW, and through VD2 during (1 − d)TSW. Then in the switching period, the energy loss of IGBT1 is Z Vce  ic dt ð8:27Þ Econd Tr ¼ dTSW

Since the switching frequency of the power module is very high, the load current changes very little during the opening time dTSW of the switching cycle TSW. Moreover, since the time constant L/R of the inductive load is much larger than the switching period TSW of PWM wave, the fluctuation of load current is ignored, so it can be considered that the load current is constant within the switching period T of this switching period. Then, the load current in the half period before the modulated wave changes continuously according to the waveform of the modulated wave as the carrier cycle varies, and the energy loss of the through state in the kth carrier cycle is Econd

Tr

¼ Vce  ic  dk  TSW

ð8:28Þ

Then the average power loss during the carrier period is Pcond

Tr

¼

Econd Tr Vce  ic  dk  TSW ¼ ¼ Vce  ic  dk TSW TSW

ð8:29Þ

Similarly, the average power loss of the diode in the switching period is Pcond

D

¼ VF  ic  ð1  dk Þ

ð8:30Þ

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8 Reliability Research on Impedance Source Inverters

Fig. 8.23 Output characteristic curves of IGBT

According to the output characteristic curves of IGBT and diode, as shown in Fig. 8.23, the voltage drops Vce and VF in Eqs. 8.29 and 8.30 are both affected by the junction temperature [29]. The curve in Fig. 8.23 is linearized by the threshold voltage drop Vceo stack resistance voltage method, and relevant parameters are extracted. It can be expressed as Vce ¼ Vceo þ ic  rce

ð8:31Þ

In Eq. 8.31, the Vceo is formed due to the internal P–N junction of IGBT, which does not change with the change of current, but is affected by the temperature. Vceo changes approximately linearly as the temperature increases. It can be seen from the above analysis that the on-state loss of IGBT devices is independent of the switching frequency and is a function of ac output current, duty cycle, and junction temperature. (2) Switching loss analysis and modeling Switching loss refers to the loss of the device in the process of switching on and off. Due to the short switching cycle, complex switching process, and the impact of junction temperature and other factors, switching loss is difficult to calculate accurately. To reduce the error, the ESW − ic characteristic curve provided in the device manual is used to establish the energy loss reference table method to calculate the switching loss, and the influence of dc terminal voltage, junction temperature, and gate resistance on the switching loss are also taken into account. As mentioned above, the time constant L/R of inductive load is much larger than the carrier period TSW of PWM wave, and it is considered that the load current ic is

8.3 Thermal Model of Power Devices

241

constant within the opening time dTSW of switching period TSW. According to the ESW − ic characteristic curve, the energy loss of the switching cycle can be checked. The energy loss of the device in a switching cycle is ESW ¼ ESW ðic Þ  KV ðVdc Þ  KTj ðTj Þ  KR ðRg Þ

ð8:32Þ

where ESW is the device switching energy loss (including IGBT on and off energy and diode reverse recovery energy), which is affected by current ic, temperature Tj, gate resistance Rg, and DC voltage Vdc. For IGBT, its average switching loss power in a switching period TSW is PSW

Tr on ðic Þ

¼

ESW on ðic Þ ¼ fSW  ESW TSW

on f ðic Þ

 KV ðVdc Þ  KTj ðTj Þ  KR ðRg Þ ð8:33Þ

The values of DC voltage coefficient KV(Vdc) and temperature coefficient KTj(Tj) in Eq. (8.33) are as follows:  KV ðVdc Þ ¼

Vdc

Vdc

 NV ð8:34Þ

ref

KTj ðTj Þ ¼ 1 þ TCSW ðTj  125  CÞ

ð8:35Þ

Because of gate resistance Rg and capacitance Cies jointly decided the gate time constant s, the smaller the Rg, the smaller the time constant of gate is, the shorter the time of arrival in gate threshold voltage is, and the smaller the opening loss is. The influence factor KR (Rg) of gate resistance Rg on switching energy loss can be obtained from the Rg − ESW curve in the device manual by table lookup. According to Eqs. (8.38–8.35), the switching loss of IGBT and diode under PWM control can be described by the following formula, respectively:  PSW

Tr on

¼ fSW  ESW  KR

on

f ðic Þ 

Vdc

on ðRg Þ

 PSW

Tr off

¼ fSW  ESW  KR

off

f ðic Þ 

 Prr

D

¼ fSW  Err

D f ðic Þ



Vdc

Vdc

NV

Tr

TCSW

Tr ðTj

 125  CÞ

ref

ð8:36Þ NV

Vdc

Vdc

off ðRg Þ

 NV

Vdc

Tr

TCSW

Tr ðTj

 125  CÞ

ref

ð8:37Þ

D

TCSW

D ðTj

 125  CÞ  KR

D ðRg Þ

ref

ð8:38Þ

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8 Reliability Research on Impedance Source Inverters

In the above formula, fSW is the carrier frequency, Vdc is the dc terminal voltage, and Vdc_ref is the reference voltage. NV and TCSW are taken from the empirical values, and values are usually as follows: IGBT coefficient NV_Tr is 1.3–1.4, and diode coefficient NV_D is 0.6. IGBT coefficient TCSW_Tr is set at 0.003, and diode coefficient TCSW_D is 0.006. From Eqs. 8.36–8.38, it can be seen that the switching loss of IGBT and diode increases with the increase of switching frequency, which is a function of ac output current, frequency, junction temperature, DC terminal voltage, and gate resistance, and constantly changes with the fundamental wave of AC output current.

8.3.1.2

IGBT Thermal Model

The power module will generate a lot of heat energy while transferring and processing electric energy. In order to maintain its normal working state, the working junction temperature should not exceed the rated maximum junction temperature, so as to ensure the reliable and safe operation of the module and a long service life. The thermal modeling analysis of the power module refers to the steady-state analysis and transient analysis of the temperature change of its structure by means of mathematical means, so as to find the thermal defects at the initial stage of device design and improve the design. The calculation of instantaneous temperature under different load conditions provides a basis for the thermal management and reliable performance prediction of the optimized system. According to the theory of heat transfer, there are three basic forms of heat transfer: conduction, convection, and radiation. IGBT devices are heated by IGBT and diode chips, which need to be diffused to the surrounding environment through the shell and radiator. There is heat conduction between the layers of IGBT devices, and there is heat convection and radiation heat dissipation between the outer surface of IGBT devices and the surrounding environment. In modeling and simulation, reasonable simplifications and assumptions are generally made as follows: only the heat conduction inside the dominant device is considered, thermal radiation and convection effects are ignored, and the external environment temperature of the radiator is assumed to be constant [30–32]. Heat conduction is similar to Ohm’s law of current passing through a conductor, so the analogical relationship between electrical parameters and thermal parameters can be shown in Table 8.4.

Table 8.4 Electrothermal coefficient conversion

Elements

Electrical domain

Thermal domain

Resistance (Om) Capacitance (F)

Thermal resistance (K/W) Thermal capacitance (J/K)

Voltage (V)

Temperature (K)

Current (A)

Power loss (W)

8.3 Thermal Model of Power Devices

243

Thermal resistance Rth is defined as, under the condition of heat balance, the ratio of temperature difference between the two specified point DT and dissipation power P which generates the temperature difference. IGBT is mainly characterized by thermal resistance and heat capacity. Thermal resistance is a physical quantity that represents the device’s static heat dissipation capacity and is also the most commonly used evaluation parameter in thermal analysis. According to the way of heat dissipation, the thermal resistance from the chip to the case is called internal heat resistance Rjc. The thermal resistance from the case to the radiator is the contact thermal resistance Rcs. The heat resistance from the radiator to the environment is denoted as Rsa. The total thermal resistance is composed of the thermal resistance of each section of material in series, which can be expressed as Rja ¼ Rjc þ Rcs þ Rsa

ð8:39Þ

Similarly, for heat-conducting materials with volume V, specific heat capacity C, and density q, the heat capacity Cth is defined as Cth ¼ q  C  V

ð8:40Þ

The heat capacity is equivalent to the capacitance in the circuit. In the transient process of heat conduction, the heat capacity can be described by the heat resistance. According to the electrothermal analogy theory, the thermal model represents the thermal characteristics of devices by equivalent circuits. The thermal model modeling can be divided into analytical model method, numerical model method and experimental extraction equivalent RC thermal network model method. The equivalent RC thermal network model can be divided into Cauer model and Foster model [33, 34]. R1

(a) Tj

C1

(b)

R1

R2

C2

R2

Rn

Tc

Cn

Rn

Tj

Tc

C1

C2

Cn

Fig. 8.24 Equivalent network structures of thermal circuit for IGBT module. a Cauer model. b Foster model

244

8 Reliability Research on Impedance Source Inverters

Cauer model is shown in Fig. 8.24a. This model reflects the thermal resistance and thermal capacity of the actual physical structure of the device and can predict the temperature of each layer, but the structure needs to obtain the physical parameters of all layers, and then establish them through theoretical calculation. Relevant software can be used for simulation to verify the structure, but it is very difficult to verify the implementation in experiments. As shown in Fig. 8.24b, the Foster model is composed of a RC circuit consisting of a finite number of heat resistance R and heat capacity C in parallel. The structure is independent of the equivalent external model of the internal heat transfer structure of the device, so it cannot reflect the thermal resistance and heat capacity of the actual physical structure of the device, but this model is helpful for controller programming and its application is more. The thermal characteristic parameters of each layer in Foster model can be obtained experimentally by obtaining the transient thermal impedance curves, and then obtained by using the curve fitting method. Cauer and Foster models are both based on lumped parameter method. The disadvantage of lumped parameter method is that it cannot obtain the two-dimensional temperature distribution of each layer of IGBT. The actual heat transfer process of IGBT module is externally equivalent by using Foster thermal network and can be modeled by simulation in the form of circuit network or transfer function. When the power loss exists in a periodic form, the module shows heat capacity, which can be expressed by transient thermal impedance. Transient thermal impedance can be used to calculate the instantaneous junction temperature, and the transient thermal impedance of IGBT is Zthjc ¼

DTjc P

ð8:41Þ

The chip-case thermal network adopts the fourth-order Foster thermal network. Zthjc ¼

4 X

Ri ð1  esi Þ t

ð8:42Þ

i¼1

Thermal grease and heat sink to the environment thermal resistance uses first-order thermal network. The Foster thermal network of IGBT module is shown in Fig. 8.25. Combined with the mentioned hot network above, the junction temperature of IGBT and diode can be expressed as Tj Tj

Tr ðtÞ

¼ PTr  ðZthjc

Tr

þ Zthch

Tr Þ þ ðPTr

þ PD Þ  Zthha þ Ta

ð8:43Þ

D ðtÞ

¼ PTr  ðZthjc

D

þ Zthch

D Þ þ ðPTr

þ PD Þ  Zthha þ Ta

ð8:44Þ

where Ta is the ambient temperature of IGBT module.

8.3 Thermal Model of Power Devices

245

IGBT module

Thermal grease Heat sink

Ploss

R1

R2

R3

R4

R5

R6

Tj

C1

C2

C3

C4

C5

C6 Zthha

Ta Zthjc_Tr

Zthch_Tr

Fig. 8.25 IGBT module Foster thermal network

8.3.2

Thermal Model of Capacitor

In order to analyze the influence of electrical stress and thermal stress on the DC-link capacitor of photovoltaic inverter during the working process, this project is based on the theory of electrothermal analogy and combined with the topology structure of a two-stage inverter without transformer isolation, as shown in Fig. 8.26. On this basis, the thermal model of the DC side of the inverter is established. Assume that the voltage and current input to the grid end of the inverter at the grid side in Fig. 8.26 are sinusoidal functions. The current is ig ¼ Ig cosðx0 tÞ, the voltage is vg ¼ Vg cosðx0 tÞ, among them x0 ¼ 2pfg , fg is the basic frequency of the power grid, and Ig and Vg are the amplitude of the current and voltage at the power grid end, respectively, and then the power input to the power grid end by the inverter is 1 1 P0 ðtÞ ¼ Vg Ig þ Vg Ig cosð2x0 tÞ 2 2

ð8:45Þ

It can be seen from Eq. 8.45 that the power of the inverter is affected by the power grid frequency. Combined with the topology of the inverter, it can be concluded that the ripple current of the dc-link capacitor is ic ¼ iboost  iinv

Boost L ˚C

PV

Fig. 8.26 Topology of photovoltaic inverter

Inverter

ð8:46Þ

Filter

Grid Zg

246

8 Reliability Research on Impedance Source Inverters

where iboost is the output current of the boost-side transformer, and iinv is the input current of the grid side inverter. The RMS of ripple current of dc-link capacitance in inverter can be calculated as

2

IC;rms

8