High voltage direct current transmission : converters, systems and DC grids [Second edition] 9781119566618, 1119566614, 9781119566632, 1119566630, 9781119566540

Table of contents :
Content: Part I HVDC with Current Source Converters 10 1 Introduction to Line Commutated HVDC 11 1.1 HVDC Applications 11 1.2 Line Commutated HVDC Components 12 1.3 DC Cables and Overhead Lines 13 1.4 LCC HVDC Topologies 14 1.5 Losses in LCC HVDC Systems 15 1.6 Conversion of AC Lines to DC 16 1.7 Ultra High Voltage HVDC 17 2 Thyristors 18 2.1 Operating Characteristics 18 2.2 Switching Characteristic 19 2.3 Losses in an HVDC Thyristors 21 2.4 Valve Structure and Thyristor Snubbers 24 2.5 Thyristor Rating Selection and Overload Capability 26 3 6-Pulse Diode and Thyristor Converter 27 3.1 3-Phase Uncontrolled Bridge 27 3.2 3-Phase Thyristor Rectifier 29 3.3 Analysis of Commutation Overlap in a Thyristor Converter 30 3.4 Active and Reactive Power in a 3-Phase Thyristor Converter 33 3.5 Inverter Operation 34 4 HVDC Rectifier Station Modelling, Control and Synchronisation with AC System 37 4.1 HVDC Rectifier Controller 37 4.2 Phase Locked Loop (PLL) 38 4.3 Master Level HVDC Control 40 5 HVDC Inverter Station Modelling and Control 41 5.1 Inverter Controller 41 5.2 Commutation Failure 42 6 HVDC System V-I Diagrams and Operating Modes 45 6.1 HVDC Equivalent Circuit 45 6.2 HVDC V-I Operating Diagram 45 6.3 HVDC Power Reversal 47 7 HVDC Analytical Modelling and Stability 52 7.1 Introduction to Converter and HVDC Modelling 52 7.2 HVDC Analytical Model 53 7.3 CIGRE HVDC Benchmark Model 53 7.4 Converter Modelling, Linearisation and Gain Scheduling 54 7.5 AC System Modelling For HVDC Stability Studies 55 7.6 LCC Converter Transformer Model 57 7.7 DC System Including DC Cable 58 7.8 Accurate DC Cable Modelling 60 7.9 HVDC-HVAC System Model 66 7.10 Analytical Dynamic Model Verification 66 7.11 Basic HVDC Dynamic Analysis 67 7.12 HVDC Second Harmonic Instability 68 7.13 100Hz Oscillations on DC Side 70 8 HVDC Phasor Modelling and Interactions with AC System 71 8.1 Converter and DC System Phasor Model 71 8.2 Phasor AC System Model and Interaction with DC System 71 8.3 Inverter AC Voltage and Power Profile As DC Current Is Increasing 73 8.4 Influence of Converter Extinction Angle 74 8.5 Influence of Shunt Reactive Power Compensation 74 8.6 Influence of Load At the Converter Terminals 75 8.7 Influence of Operating Mode (DC Voltage Control Mode) 75 8.8 Rectifier Operating Mode 77 9 HVDC Operation with Weak AC Systems 79 9.1 Introduction 79 9.2 Short Circuit Ratio and Equivalent Short Circuit Ratio 79 9.3 Background on Power Transfer Between Two AC Systems 82 9.4 Phasor Study of Converter Interactions with Weak AC Systems 83 9.5 System Dynamics (Small Signal Stability) with Low SCR 84 9.6 Control and Main Circuit Solutions for Weak AC Grids 85 9.7 LCC HVDC with SVC (Static Var Compensator) 85 9.8 Capacitor Commutated Converters for HVDC 88 9.9 AC System with Low Inertia 89 10 Fault Management and HVDC System Protection 91 10.1 Introduction 91 10.2 DC Line Faults 91 10.3 AC System Faults 93 10.4 Internal Faults 95 10.5 System Reconfiguration for Permanent Faults 96 10.6 Overvoltage Protection 97 11 LCC HVDC System Harmonics 99 11.1 Harmonic Performance Criteria 99 11.2 Harmonic Limits 99 11.3 Thyristor Converter Harmonics 100 11.4 Harmonic Filters 101 11.5 Non-Characteristic Harmonic Reduction Using HVDC Controls 108 Bibliography Part I Line Commutated Converter HVDC 109 Part II HVDC with Voltage Source Converters 111 12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC 112 12.1 Application of Voltage Source Converters (VSC) in HVDC 112 12.2 Comparison with Line Commutated Converter (LCC) HVDC 113 12.3 HVDC Technology Landscape 114 12.4 Overhead and Subsea/Underground VSC HVDC Transmission 116 12.5 DC Cable Types with VSC HVDC 116 12.6 Monopolar and Bipolar VSC HVDC Systems 117 12.7 VSC HVDC Converter Topologies 117 12.8 VSC HVDC Station Components 122 12.9 AC Inductors 127 12.10 DC Inductors 127 13 IGBT Switches and VSC Converter Losses 129 13.1 Introduction to IGBT and IGCT 129 13.2 General VSC Converter Switch Requirements 129 13.3 IGBT Technology 129 13.4 High Power IGBT Devices 134 13.5 IEGT Technology 134 13.6 Losses Calculation 135 13.7 Balancing Challenges in 2-Level IGBT Valves 139 13.8 Snubbers Circuits 139 14 Single Phase and 3-Phase 2-Level VSC Converters 141 14.1 Introduction 141 14.2 Single Phase Voltage Source Converter 141 14.3 Three Phase Voltage Source Converter 143 14.4 Square Wave, Six Pulse Operation 143 15 2-Level PWM VSC Converters 150 15.1 Introduction 150 15.2 PWM Modulation 150 15.3 Sinusoidal Pulse Width Modulation (SPWM) 151 15.4 Third Harmonic Injection (THI) 153 15.5 Selective Harmonic Elimination Modulation (SHE) 154 15.6 Converter Losses for Two-Level SPWM VSC 154 15.7 Harmonics with Pulse Width Modulation (PWM) 156 15.8 Comparison of PWM Modulation Techniques 158 16 Multilevel VSC Converters in HVDC Applications 160 16.1 Introduction 160 16.2 Modulation Techniques for Multilevel Converters 161 16.3 Neutral Point Clamped Multilevel Converter 162 16.4 Half Bridge Modular Multilevel Converter (HB MMC) 163 16.5 Full Bridge Modular Multilevel Converter (FB MMC) 173 16.6 Comparison of Multilevel Topologies 176 17 2-Level VSC HVDC Modelling, Control and Dynamics 177 17.1 PWM 2-Level Converter Average Model 177 17.2 2-Level PWM Converter Model in DQ Frame 179 17.3 VSC Converter Transformer Model 180 17.4 2-Level VSC Converter and AC Grid Model in ABC Frame 180 17.5 2-Level VSC Converter and AC Grid Model in DQ Rotating Coordinate Frame 181 17.6 VSC Converter Control Principles 182 17.7 The Inner Current Controller Design 182 17.8 Outer Controller Design 185 17.9 Complete 2-Level VSC Converter Controller 188 17.10 Small Signal Linearised VSC HVDC Model 188 17.11 Small Signal Dynamic Studies 191 18 2-Level VSC HVDC Phasor-Domain Interaction with AC Systems and PQ Operating Diagrams 193 18.1 Power Exchange Between Two AC Voltage Sources 193 18.2 Converter Phasor Model and Power Exchange with AC System 195 18.3 Phasor Study of VSC Converter Interaction with AC System 197 18.4 Operating Limits 199 18.5 Design Point Selection 200 18.6 Influence of AC System Strength 201 18.7 Influence of AC System Impedance Angle (Xs/Rs) 201 18.8 Influence of Transformer Reactance 202 18.9 Influence of Converter Control Modes 202 18.10 Operation with Very Weak AC Systems 203 19 Half Bridge MMC: Dimensioning, Modelling, Control and Interaction with AC System 210 19.1 Basic Equations and Steady-State Control 210 19.2 Steady-State Dimensioning 214 19.3 Half Bridge MMC Non-Linear Average Dynamic Model 215 19.4 Nonlinear Average Value Model Including Blocked State 217 19.5 HB MMC HVDC Start-Up and Charging MMC Cells 218 19.6 HB MMC Dynamic DQ Frame Model and Phasor Model 219 19.7 Second Harmonic of Differential Current 224 19.8 Complete MMC Converter DQ Model in Matrix Form 225 19.9 Second Harmonic Circulating Current Suppression Controller 226 19.10 Simplified DQ Frame Model with Circulating Current Controller 229 19.11 Phasor Model of MMC with Circulating Current Suppression Controller 232 19.12 Simplified Dynamic MMC Model Using Equivalent Series Capacitor CMMC 233 19.13 Full Dynamic Analytical HB MMC Model 235 19.14 HB MMC Controller and Arm Voltage Control 237 19.15 MMC Total Series Reactance and Comparison with 2-Level VSC 238 19.16 MMC Interaction with AC System and PQ Operating Diagrams 240 20 Full Bridge MMC Converter: Dimensioning, Modelling and Control 242 20.1 FB MMC Arm Voltage Range 242 20.2 Full Bridge MMC Converter Non-Linear Average Model 242 20.3 FB MMC Nonlinear Average Model Including Blocked State 243 20.4 Full Bridge MMC Cell Charging 244 20.5 Hybrid MMC Design 245 20.6 Full-Bridge MMC DC Voltage Variation Using a Detailed Model 250 20.7 FB MMC Analytical Dynamic DQ Model 251 20.8 Simplified FB MMC Model 253 20.9 FB MMC Converter Controller 253 21 MMC Converter Under Unbalanced Conditions 256 21.1 Introduction 256 21.2 MMC Balancing Controller Structure 256 21.3 Balancing Between Phases (Horizontal Balancing) 257 21.4 Balancing Between Arms (Vertical Balancing) 258 21.5 Simulation of Balancing Controls 259 21.6 Operation with Unbalanced AC Grid 263 22 VSC HVDC Under AC and DC Fault Conditions 266 22.1 Introduction 266 22.2 Faults on the AC System 266 22.3 DC Faults with 2-Level VSC 267 22.4 Influence of DC Capacitors 270 22.5 VSC Converter Modelling Under DC Faults and VSC Diode Bridge 271 22.6 VSC Converter Mode Transitions As DC Voltage Reduces 277 22.7 DC Faults with Half-Bridge Modular Multilevel Converter 278 22.8 Full Bridge MMC Under DC Faults 280 23 VSC HVDC Application for AC Grid Support and Operation with Passive AC Systems 284 23.1 VSC HVDC High Level Controls and AC Grid Support 284 23.2 HVDC Embedded Inside an AC Grid 285 23.3 HVDC Connecting Two Separate AC Grid 285 23.4 HVDC in Parallel with AC 286 23.5 Operation with a Passive AC System and Black Start Capability 286 23.6 VSC HVDC Operation with Offshore Wind Farms 287 23.7 VSC HVDC Supplying Power Offshore and Driving a MW Size Variable Speed Motor 288 Bibliography Part II Voltage Source Converter HVDC 290 Part III DC Transmission Grids 292 24 Introduction to DC Grids 293 24.1 DC Versus AC Transmission 293 24.2 Terminology 293 24.3 DC Grid Planning, Topology and Power Transfer Security 294 24.4 Technical Challenges 294 24.5 DC Grid Building By Multiple Manufacturers -Interoperability 295 24.6 Economic Aspects 295 25 DC Grids with Line Commutated Converters 297 25.1 Multiterminal LCC HVDC 297 25.2 Italy-Corsica-Sardinia Multiterminal HVDC Link 298 25.3 Connecting LCC Converter to a DC Grid 298 25.4 Control of LCC Converters in DC Grids 300 25.5 Control of LCC DC Grids Through DC Voltage Droop Feedback 301 25.6 Managing LCC DC Grid Faults 302 25.7 Reactive Power Issues 303 25.8 Employing LCC Converter Stations in Established DC Grids 303 26 DC Grids with Voltage Source Converters and Power Flow Model 304 26.1 Connecting VSC Converter to a DC Grid 304 26.2 Operating Multiterminal VSC HVDC in China 304 26.3 DC Grid Power Flow Model 306 26.4 DC Grid Power Flow Under DC Faults 308 27 DC Grid Control 311 27.1 Introduction 311 27.2 Fast Local VSC Converter Control in DC Grids 311 27.3 DC Grid Dispatcher with Remote Communication 313 27.4 Primary, Secondary and Tertiary DC Grid Control 313 27.5 DC Voltage Droop Control for VSC Converters in DC Grids 314 27.6 3-Level Control for VSC Converters with Dispatcher Droop 315 27.7 Power Flow Algorithm When DC Powers Are Regulated 316 27.8 Power Flow and Control Study of CIGRE DC Grid Test System 320 28 DC Circuit Breakers 325 28.1 Introduction 325 28.2 Challenges with DC Circuit Opening 325 28.3 DC CB Operating Principles and a Simple Model 326 28.4 DC CB Performance Requirements 327 28.5 Practical HV DC CBs 328 28.6 Mechanical DC Circuit Breaker 329 28.7 Semiconductor Based DC Circuit Breaker 337 28.8 Hybrid DC Circuit Breaker 339 29 DC Grid Fault Management and Protection System 345 29.1 Introduction 345 29.2 Fault Current Components in DC Grids 346 29.3 DC System Protection Coordination with AC System Protection 347 29.4 DC Grid Protection System Development 348 29.5 DC Grid Protection System Based On Local Measurements 349 29.6 Blocking MMC Converters Under DC Faults 352 29.7 Differential DC Grid Protection Strategy 355 29.8 Selective Protection for Star-Topology DC Grids 356 29.9 DC Grids with DC Fault-Tolerant VSC Converters 357 29.10 DC Grids with Full Bridge MMC Converters 361 30 High Power DC/DC Converters and DC Power Flow Controlling Devices 364 30.1 Introduction 364 30.2 Power Flow Control Using Series Resistors 365 30.3 Low Stepping Ratio DC/DC Converters (DC Choppers) 367 30.4 Non-Isolated MMC-Based DC/DC Converter (M2DC) 370 30.5 DC/DC Converters with DC Polarity Reversal 378 30.6 High Stepping Ratio Isolated DC/DC Converter (Dual Active Bridge DC/DC) 379 30.7 High Stepping Ratio LCL DC/DC Converter 384 30.8 Building DC Grids with DC/DC Converters 385 30.9 DC Hubs 387 30.10 Developing DC Grids Using DC Hubs 388 30.11 North Sea DC Grid Topologies 389 Bibliography Part III DC Transmission Grids 392 31 Appendix I Variable Notations 394 32 Appendix II - Analytical Background to Rotating DQ Frame 395 32.1 Transforming AC Variables to DQ Frame 395 32.2 Derivative of an Oscillating Signal in DQ Frame 397 32.3 Transforming an AC System Dynamic Equation to DQ Frame 397 32.4 Transforming N-Order State Space AC System Model to DQ Frame 398 32.5 Static (Steady-State) Modelling in Rotating DQ Coordinate Frame 400 32.6 Representing Product of Oscillating Signals in DQ Frame 400 32.7 Representing Power in DQ Frame 401 33 Appendix III - System Modelling Using Complex Numbers and Phasors 405 34 Appendix IV - Simulink Examples 407 Chapter 3 Examples 407 Chapter 5 Examples 408 Chapter 6 Examples 408 Chapter 8 Examples 410 Chapter 14 Examples 411 Chapter 16 Examples 412 Chapter 17 Examples 414

Citation preview

High Voltage Direct Current Transmission

High Voltage Direct Current Transmission Converters, Systems and DC Grids

Dragan Jovcic University of Aberdeen Aberdeen, UK

Second Edition

This edition first published 2019 © 2019 John Wiley & Sons Ltd Edition History John Wiley & Sons (1e, 2015) All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, except as permitted by law. Advice on how to obtain permission to reuse material from this title is available at http://www.wiley.com/go/permissions. The right of Dragan Jovcic to be identified as the author of this work has been asserted in accordance with law. Registered Offices John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, USA John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, UK Editorial Office The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, UK For details of our global editorial offices, customer services, and more information about Wiley products visit us at www.wiley.com. Wiley also publishes its books in a variety of electronic formats and by print-on-demand. Some content that appears in standard print versions of this book may not be available in other formats. Limit of Liability/Disclaimer of Warranty In view of ongoing research, equipment modifications, changes in governmental regulations, and the constant flow of information relating to the use of experimental reagents, equipment, and devices, the reader is urged to review and evaluate the information provided in the package insert or instructions for each chemical, piece of equipment, reagent, or device for, among other things, any changes in the instructions or indication of usage and for added warnings and precautions. While the publisher and authors have used their best efforts in preparing this work, they make no representations or warranties with respect to the accuracy or completeness of the contents of this work and specifically disclaim all warranties, including without limitation any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives, written sales materials or promotional statements for this work. The fact that an organization, website, or product is referred to in this work as a citation and/or potential source of further information does not mean that the publisher and authors endorse the information or services the organization, website, or product may provide or recommendations it may make. This work is sold with the understanding that the publisher is not engaged in rendering professional services. The advice and strategies contained herein may not be suitable for your situation. You should consult with a specialist where appropriate. Further, readers should be aware that websites listed in this work may have changed or disappeared between when this work was written and when it is read. Neither the publisher nor authors shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. Library of Congress Cataloging-in-Publication Data Applied for ISBN: 9781119566540 Cover Design: Wiley Cover Image: Cover page photograph reproduced with permission of SIEMENS – HVDC Project Brazil Set in 10/12pt WarnockPro by SPi Global, Chennai, India

10 9 8 7 6 5 4 3 2 1

v

Contents Preface xvii

Part I

HVDC with Current Source Converters

1

Introduction to Line Commutated HVDC 3

1.1 1.2 1.3 1.3.1 1.3.2 1.3.3 1.3.4 1.4 1.5 1.6 1.7

HVDC Applications 3 Line Commutated HVDC Components 4 DC Cables and Overhead Lines 7 Introduction 7 Mass-impregnated Cables 7 Low-pressure Oil-filled Cables 7 Extruded Cross-linked Polyethylene Cables 8 LCC HVDC Topologies 8 Losses in LCC HVDC Systems 10 Conversion of AC Lines to DC 10 Ultra High Voltage HVDC 12

2

Thyristors

1

2.1 2.2 2.3 2.4 2.5

13 Operating Characteristics 13 Switching Characteristics 14 Losses in HVDC Thyristors 18 Valve Structure and Thyristor Snubbers 20 Thyristor Rating Selection and Overload Capability 22

3

Six-pulse Diode and Thyristor Converter 25

3.1 3.2 3.3 3.4 3.5

Three-phase Uncontrolled Bridge 25 Three-phase Thyristor Rectifier 27 Analysis of Commutation Overlap in a Thyristor Converter 28 Active and Reactive Power in a Three-phase Thyristor Converter 32 Inverter Operation 33

vi

Contents

4

HVDC Rectifier Station Modelling, Control and Synchronisation with AC System 37

4.1 4.2 4.3

HVDC Rectifier Controller 37 Phase-locked Loop 38 Master-level HVDC Control 40

5

HVDC Inverter Station Modelling and Control 43

5.1 5.1.1 5.1.2 5.1.3 5.1.4 5.2

Inverter Controller 43 Control Structure 43 Extinction Angle Control 43 DC Voltage Control 44 DC Current Control at Inverter 45 Commutation Failure 45

6

HVDC System V–I Diagrams and Operating Modes 49

6.1 6.2 6.3

HVDC Equivalent Circuit 49 HVDC V –I Operating Diagram 49 HVDC Power Reversal 51

7

57 Introduction to Converter and HVDC Modelling 57 Detailed Switching Transients Modelling 57 Modelling with Switchings 57 Analytical Dynamic Modelling of Converters 58 Phasor Modelling 58 HVDC Analytical Model 58 CIGRE HVDC Benchmark Model 60 Converter Modelling, Linearisation, and Gain Scheduling 60 AC System Modelling for HVDC Stability Studies 64 LCC Converter Transformer Model 67 DC System Including DC Cable 68 DC Cable/Line Modelling as a Single 𝜋 Section 68 Controller Model 69 Complete DC System Model 69 Accurate DC Cable Modelling 70 Wideband Cable Model 70 Cable Higher-order Analytical Model in State Space 72 HVDC–HVAC System Model 76 Analytical Dynamic Model Verification 77 Basic HVDC Dynamic Analysis 77 Eigenvalue Analysis 77 Eigenvalue Sensitivity Study 77 Influence of PLL Gains 79 HVDC Second Harmonic Instability 80 100 Hz Oscillations on the DC Side 82

7.1 7.1.1 7.1.2 7.1.3 7.1.4 7.2 7.3 7.4 7.5 7.6 7.7 7.7.1 7.7.2 7.7.3 7.8 7.8.1 7.8.2 7.9 7.10 7.11 7.11.1 7.11.2 7.11.3 7.12 7.13

HVDC Analytical Modelling and Stability

Contents

8

HVDC Phasor Modelling and Interactions with AC System 83

8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8

Converter and DC System Phasor Model 83 Phasor AC System Model and Interaction with DC System 84 Inverter AC Voltage and Power Profile as DC Current is Increasing 86 Influence of Converter Extinction Angle 88 Influence of Shunt Reactive Power Compensation 88 Influence of Load at the Converter Terminals 88 Influence of Operating Mode (DC Voltage Control Mode) 88 Rectifier Operating Mode 90

9

HVDC Operation with Weak AC Systems 95

9.1 9.2 9.2.1 9.2.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9

Introduction 95 Short Circuit Ratio and Equivalent Short Circuit Ratio 95 Definition of SCR and ESCR 95 Operating Difficulties with Low SCR Systems 98 Background on Power Transfer Between Two AC Systems 99 Phasor Study of Converter Interactions with Weak AC Systems 101 System Dynamics (Small Signal Stability) with Low SCR 101 Control and Main Circuit Solutions for Weak AC Grids 102 LCC HVDC with SVC 103 Capacitor Commutated Converters for HVDC 104 AC System with Low Inertia 106

10

Fault Management and HVDC System Protection 111

10.1 10.2 10.3 10.3.1 10.3.2 10.4 10.5 10.6

Introduction 111 DC Line Faults 111 AC System Faults 113 Rectifier AC Faults 113 Inverter AC Faults 114 Internal Faults 115 System Reconfiguration for Permanent Faults 116 Overvoltage Protection 119

11

LCC HVDC System Harmonics 121

11.1 11.2 11.3 11.4 11.4.1 11.4.2 11.4.3 11.5

Harmonic Performance Criteria 121 Harmonic Limits 122 Thyristor Converter Harmonics 123 Harmonic Filters 124 Introduction 124 Tuned Filters 126 Damped Filters 128 Non-characteristic Harmonic Reduction Using HVDC Controls Bibliography Part I: Line Commutated Converter HVDC

133

132

vii

viii

Contents

Part II

HVDC with Voltage Source Converters

137

12

VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC 139

12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.7.1 12.7.2 12.7.3 12.7.4 12.8 12.8.1 12.8.2 12.8.3 12.8.4 12.8.5 12.8.6 12.8.7 12.9 12.10

Application of Voltage Source Converters in HVDC 139 Comparison with LCC HVDC 141 HVDC Technology Landscape 142 Overhead and Subsea/Underground VSC HVDC Transmission 143 DC Cable Types with VSC HVDC 147 Monopolar and Bipolar VSC HVDC Systems 147 VSC HVDC Converter Topologies 148 HVDC with Two-level Voltage Source Converter 148 HVDC with Neutral Point Clamped Converter 150 MMC VSC HVDC Transmission Systems 151 MMC HVDC Based on FB Topology 153 VSC HVDC Station Components 155 AC CB 155 VSC Converter Transformer 155 VSC Converter AC Harmonic Filters 156 DC Capacitors 156 DC Filter 157 Two-level VSC HVDC Valves 158 MMC Valves and Cells 159 AC Inductors 160 DC Inductors 161

13

13.1 13.2 13.3 13.3.1 13.3.2 13.4 13.5 13.6 13.6.1 13.6.2 13.7 13.8

IGBT Switches and VSC Converter Losses 165 Introduction to IGBT and IGCT 165 General VSC Converter Switch Requirements 166 IGBT Technology 166 IGBT Operating Characteristics 167 Fast Recovery Anti-parallel Diode 171 High Power IGBT Devices 171 IEGT Technology 172 Losses Calculation 173 Conduction Loss Modelling 173 Switching Loss Modelling 174 Balancing Challenges in Two-level IGBT Valves 178 Snubbers Circuits 179

14

Single-phase and Three-phase Two-level VSC Converters 181

14.1 14.2 14.3 14.4 14.4.1 14.4.2

Introduction 181 Single-phase VSC 181 Three-phase VSC 184 Square-wave, Six-pulse Operation 185 180∘ Conduction 185 120∘ Conduction 188

Contents

15.1 15.2 15.2.1 15.2.2 15.3 15.4 15.5 15.6 15.7 15.8

193 Introduction 193 PWM Modulation 193 Multipulse with Constant Pulse Width 193 Modulating Signal 194 Sinusoidal Pulse Width Modulation 195 Third Harmonic Injection 197 Selective Harmonic Elimination Modulation 198 Converter Losses for Two-level SPWM VSC 198 Harmonics with PWM 201 Comparison of PWM Modulation Techniques 203

16

Multilevel VSC Converters in HVDC Applications 205

16.1 16.2 16.3 16.4 16.4.1 16.4.2 16.4.3 16.4.4 16.4.5 16.4.6 16.5 16.5.1 16.6

Introduction 205 Modulation Techniques for Multilevel Converters 207 Neutral Point Clamped Multilevel Converter 208 Half Bridge MMC 210 Operating Principles of Half-bridge MMC 210 Capacitor Voltage Balancing 212 MMC Cell Capacitance 214 MMC Arm Inductance 215 MMC with Fundamental Frequency Modulation 218 MMC with PWM Modulation 218 Full Bridge MMC 222 Operating Principles 222 Comparison of Multilevel Topologies 224

17

Two-level VSC HVDC Modelling, Control, and Dynamics 227

17.1 17.1.1 17.1.2 17.2 17.3 17.4 17.5

PWM Two-level Converter Average Model 227 Converter Model in an ABC Frame 227 Converter Model in the ABC Frame Including Blocked State 229 Two-level PWM Converter Model in DQ Frame 230 VSC Converter Transformer Model 231 Two-level VSC Converter and AC Grid Model in the ABC Frame 231 Two-level VSC Converter and AC Grid Model in a DQ Rotating Coordinate Frame 232 VSC Converter Control Principles 233 The Inner Current Controller Design 234 Control Strategy 234 Decoupling Control 234 Current Feedback Control 235 Controller Gains 236 Outer Controller Design 237 AC Voltage Control 237 Power Control 238 DC Voltage Control 239 AC Grid Support 240

15

17.6 17.7 17.7.1 17.7.2 17.7.3 17.7.4 17.8 17.8.1 17.8.2 17.8.3 17.8.4

Two-level PWM VSC Converters

ix

x

Contents

17.9 17.10 17.11 17.11.1 17.11.2

Complete Two-level VSC Converter Controller 240 Small Signal Linearised VSC HVDC Model 242 Small Signal Dynamic Studies 242 Dynamics of Weak AC Systems 242 Impact of PLL Gains on Robustness 244

18

Two-level VSC HVDC Phasor-domain Interaction with AC Systems and PQ Operating Diagrams 247

18.1 18.2 18.3 18.3.1 18.3.2 18.3.3 18.3.4 18.3.5 18.4 18.5 18.6 18.7 18.8 18.9 18.10

Power Exchange Between Two AC Voltage Sources 247 Converter Phasor Model and Power Exchange with an AC System 249 Phasor Study of VSC Converter Interaction with AC System 252 Test System 252 Assumptions and Converter Limits 252 Case 1: Converter Voltages Are Known 253 Case 2: Converter Currents are Known 254 Case 3: PCC Voltage is Known 254 Operating Limits 254 Design Point Selection 255 Influence of AC System Strength 258 Influence of AC System Impedance Angle (X s /Rs ) 258 Influence of Transformer Reactance 258 Influence of Converter Control Modes 262 Operation with Very Weak AC Systems 262

19

Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System 269

19.1 19.2 19.3 19.4 19.5 19.6 19.6.1 19.6.2 19.6.3 19.6.4 19.7 19.8 19.9 19.10 19.11

Basic Equations and Steady-state Control 269 Steady-state Dimensioning 272 Half Bridge MMC Non-linear Average Dynamic Model 275 Non-linear Average Value Model Including Blocked State 276 HB MMC HVDC Start-up and Charging MMC Cells 278 HB MMC Dynamic DQ Frame Model and Phasor Model 279 Assumptions 279 Zero Sequence Model 282 Fundamental Frequency Model in DQ Frame 282 Second Harmonic Model in the D2Q2 Coordinate Frame 284 Second Harmonic of Differential Current 286 Complete MMC Converter DQ Model in Matrix Form 286 Second-harmonic Circulating Current Suppression Controller 287 Simplified DQ Frame Model with Circulating Current Controller 290 Phasor Model of MMC with Circulating Current Suppression Controller 295 Simplified Dynamic MMC Model Using Equivalent Series Capacitor C MMC 296 Full Dynamic Analytical HB MMC Model 300 HB MMC Controller and Arm Voltage Control 301 MMC Total Series Reactance and Comparison with Two-level VSC 304 MMC Interaction with AC System and PQ Operating Diagrams 306

19.12 19.13 19.14 19.15 19.16

Contents

20

Full Bridge MMC Converter: Dimensioning, Modelling, and Control 309

20.1 20.2 20.3 20.4 20.5 20.5.1 20.5.2 20.5.3 20.5.4 20.6 20.7 20.7.1 20.7.2 20.8 20.9

FB MMC Arm Voltage Range 309 Full Bridge MMC Converter Non-linear Average Model 309 FB MMC Non-linear Average Model Including Blocked State 310 Full Bridge MMC Cell Charging 312 Hybrid MMC Design 313 Operation Under Low DC Voltage 313 Overmodulation Requirements 314 Cell Voltage Balancing Under Low DC Voltage 315 Optimal Design of Full Bridge MMC 315 Full Bridge MMC DC Voltage Variation Using a Detailed Model 318 FB MMC Analytical Dynamic DQ Model 320 Zero Sequence Model 320 Fundamental Frequency Model 321 Simplified FB MMC Model 321 FB MMC Converter Controller 322

21

MMC Converter Under Unbalanced Conditions 325

21.1 21.2 21.3 21.4 21.5 21.6 21.6.1 21.6.2

Introduction 325 MMC Balancing Controller Structure 326 Balancing Between Phases (Horizontal Balancing) 326 Balancing Between Arms (Vertical Balancing) 328 Simulation of Balancing Controls 330 Operation with Unbalanced AC Grid 332 Detecting Positive and Negative Sequence Components 332 Controlling Grid Current Sequence Components with MMC 336

22

VSC HVDC Under AC and DC Fault Conditions 339

22.1 22.2 22.3 22.4 22.5 22.5.1 22.5.2 22.5.3

Introduction 339 Faults on the AC System 339 DC Faults with Two-level VSC 340 Influence of DC Capacitors 345 VSC Converter Modelling Under DC Faults and VSC Diode Bridge 345 VSC Diode Bridge Average Model 345 Phasor Model of VSC Diode Bridge Under DC Fault 348 Simple Expression for VSC Diode Bridge Steady-state Fault Current Magnitude 351 VSC Converter Mode Transitions as DC Voltage Reduces 352 DC Faults with Half Bridge Modular Multilevel Converter 354 Full Bridge MMC Under DC Faults 356

22.6 22.7 22.8 23

VSC HVDC Application For AC Grid Support and Operation with Passive AC Systems 359

23.1 23.2 23.3 23.4

VSC HVDC High Level Controls and AC Grid Support 359 HVDC Embedded Inside an AC Grid 360 HVDC Connecting Two Separate AC Grids 361 HVDC in Parallel with AC 361

xi

xii

Contents

23.5 23.6 23.7

Operation with a Passive AC System and Black Start Capability 362 VSC HVDC Operation with Offshore Wind Farms 362 VSC HVDC Supplying Power Offshore and Driving a MW-Size Variable Speed Motor 365 Bibliography Part II: Voltage Source Converter HVDC 366

Part III

DC Transmission Grids

371

24.1 24.2 24.3 24.4 24.5 24.6

373 DC versus AC Transmission 373 Terminology 374 DC Grid Planning, Topology, and Power Transfer Security 375 Technical Challenges 376 DC Grid Building by Multiple Manufacturers – Interoperability 376 Economic Aspects 377

25

DC Grids With Line Commutated Converters 379

25.1 25.2 25.3 25.3.1 25.3.2 25.3.3 25.4 25.5 25.6 25.7 25.8

Multiterminal LCC HVDC 379 Italy–Corsica–Sardinia Multiterminal HVDC Link 380 Connecting the LCC Converter to a DC Grid 381 Power Reversal 381 DC Faults 382 AC Faults 383 Control of LCC Converters in DC Grids 383 Control of LCC DC Grids Through DC Voltage Droop Feedback 384 Managing LCC DC Grid Faults 385 Reactive Power Issues 387 Employing LCC Converter Stations in Established DC Grids 387

26

DC Grids with Voltage Source Converters and Power Flow Model 389

26.1 26.1.1 26.1.2 26.1.3 26.2 26.3 26.4

Connecting a VSC Converter to a DC Grid 389 Power Reversal and Control 389 DC Faults 389 AC Faults 389 Multiterminal VSC HVDC Operating in China 390 DC Grid Power Flow Model 390 DC Grid Power Flow Under DC Faults 395

27

DC Grid Control 399

27.1 27.2 27.3 27.4 27.5 27.6

Introduction 399 Fast Local VSC Converter Control in DC Grids 399 DC Grid Dispatcher with Remote Communication 401 Primary, Secondary, and Tertiary DC Grid Control 402 DC Voltage Droop Control for VSC Converters in DC Grids 403 Three-level Control for VSC Converters with Dispatcher Droop 405

24

Introduction to DC Grids

Contents

27.6.1 27.6.2 27.7 27.8 27.8.1 27.8.2

Three-level Control for VSC Converters 405 Dispatcher Controller 406 Power Flow Algorithm When DC Powers are Regulated 406 Power Flow and Control Study of CIGRE DC Grid Test System 411 CIGRE DC Grid Test System 411 Power Flow After Outage of the Largest Terminal 413

28

DC Circuit Breakers 417

28.1 28.2 28.2.1 28.2.2 28.3 28.4 28.4.1 28.4.2 28.4.3 28.4.4 28.4.5 28.4.6 28.5 28.6 28.6.1 28.6.2 28.6.3 28.6.4 28.6.5 28.6.6 28.6.7 28.7 28.7.1 28.7.2 28.7.3 28.8 28.8.1 28.8.2 28.8.3 28.8.4 28.8.5

Introduction 417 Challenges with DC Circuit Opening 417 DC Current Commutation 417 DC Current Suppression and Dissipation of Energy 418 DC CB Operating Principles and a Simple Model 418 DC CB Performance Requirements 420 Opening Speed 420 DC CB Ratings and Series Inductors 420 Bidirectional Current Interruption 421 Multiple Open/close Operations in a Short Time 421 Losses, Size, and Weight 421 Standardisation 421 Practical HV DC CBs 422 Mechanical DC CB 422 Operating Principles and Construction 422 Mathematical Model and Design Principles 424 Test Circuit for DC CB Simulation 426 Simulation of DC Fault Clearing 427 Negative Fault Current Interruption 427 Multiple Open/close Operations in a Short Time 428 Mechanical DC CB for High Voltages 429 Semiconductor-based DC CB 430 Topology and Design 430 Self-protection of Semiconductor Valves 432 Simulation of Fault Current Interruption 432 Hybrid DC CB 434 Topology and Design 434 Hybrid DC CB for High Voltages 435 Simulation of Fault Current Interruption 436 Bidirectional Operation 437 Fault Current Limiting 438

29

DC Grid Fault Management and Protection System 441

29.1 29.2 29.3 29.4 29.5 29.5.1

Introduction 441 Fault Current Components in DC Grids 442 DC System Protection Coordination with AC System Protection 444 DC Grid Protection System Development 445 DC Grid Protection System Based on Local Measurements 446 Protection Based on DC Current and Current Differential 446

xiii

xiv

Contents

29.5.2 29.6 29.7 29.8 29.9 29.9.1 29.9.2 29.9.3 29.9.4 29.10

Rate of Change of Voltage Protection 447 Blocking MMC Converters Under DC Faults 450 Differential DC Grid Protection Strategy 452 Selective Protection for Star-topology DC Grids 455 DC Grids with DC Fault-tolerant VSC Converters 456 Grid Topology and Strategy 456 VSC Converter with Increased AC Coupling Reactors 457 LCL VSC Converter 459 VSC Converter with Fault Current Limiter 461 DC Grids with Full Bridge MMC Converters 461

30

High Power DC/DC Converters and DC Power Flow Controlling Devices 465

30.1 30.2 30.3 30.3.1 30.3.2 30.3.3 30.3.4 30.4 30.4.1 30.4.2 30.4.3 30.4.4 30.4.5 30.5 30.6

Introduction 465 Power Flow Control Using Series Resistors 466 Low-stepping-ratio DC/DC Converters (DC Choppers) 469 Converter Topology 469 Converter Controller 470 DC/DC Chopper Average Value Model 471 H-Bridge DC/DC Chopper 473 Non-isolated MMC-based DC/DC Converter (M2DC) 473 Introduction 473 Modelling and Design 474 Design Example and Comparison with MMC AC/DC 477 Controller Design 479 Simulation Responses 480 DC/DC Converters with DC Polarity Reversal 484 High-stepping-ratio Isolated DC/DC Converter (Dual Active Bridge DC/DC) 484 Introduction 484 Modelling and Control 486 Simulated Responses 487 High-stepping-ratio LCL DC/DC Converter 490 Building DC Grids with DC/DC Converters 492 DC Hubs 495 Developing DC Grids Using DC Hubs 496 North Sea DC Grid Topologies 496

30.6.1 30.6.2 30.6.3 30.7 30.8 30.9 30.10 30.11

Bibliography Part III: DC Transmission Grids Appendix A

503

Analytical Background to Rotating DQ Frame 505 Transforming AC Variables to a DQ Frame 505 Derivative of an Oscillating Signal in a DQ Frame 507 Transforming an AC System Dynamic Equation to a DQ Frame 507 Transforming an n-Order State Space AC System Model to a DQ Frame 509

Appendix B

B.1 B.2 B.3 B.4

Variable Notations

500

Contents

B.5 B.6 B.7

Static (Steady-state) Modeling in a Rotating DQ Coordinate Frame 510 Representing the Product of Oscillating Signals in a DQ Frame 511 Representing Power in DQ Frame 512

Appendix C

System Modeling Using Complex Numbers and Phasors 515

Simulink Examples 517 Chapter 3 Examples 517 Chapter 5 Examples 517 Chapter 6 Examples 519 Chapter 8 Examples 521 Chapter 14 Examples 523 Chapter 16 Examples 524 Chapter 17 Examples 527

Appendix D

D.1 D.2 D.3 D.4 D.5 D.6 D.7

Index 535

xv

xvii

Preface At the time of writing this book there are over 200 high voltage direct current (HVDC) links installed worldwide. The largest installations operate at ±800 kV DC voltage while the highest DC current ratings are over 4500 A. Although alternating current was the predominant method for transmitting electrical energy during the twentieth century, HVDC has now been demonstrated to be the best solution for many specific application areas and the number of installations per year is constantly increasing at the beginning of the twenty-first century. Despite significant converter station costs, HVDC is techno-economically preferred in many general applications: long-distance large-scale power transfer; subsea and long-distance cable power transmission; interconnecting asynchronous AC systems, or systems with different frequencies; controllable power transfer between different nodes in an electricity market or markets; • AC grid stability support, ancillary service provision, and resilience from blackouts; • connecting isolated systems like offshore wind farms or oil platforms. • • • •

DC transmission technology was used in many instances in the very early power systems, but the modern HVDC transmission began with the 1954 Sweden–Gotland installation. This system, and all of the other HVDCs commissioned until the mid 1970s, was based on mercury arc valves. Significant technical advance came with the introduction of solid-state valves (thyristors) although they only support the line commutated converter concept. In the first decade of the twenty-first century there has been very rapid development of fundamentally new technologies and increasing demand for HVDC technology. The introduction of voltage source converters (VSCs) requires new valves that utilise insulated gate bipolar transistors and also new protection and control approaches. The modular multilevel converters have eventually emerged as the most cost-effective VSC converter concept which practically eliminates filtering needs with HVDC and removes voltage limits with VSC valves. Modular multilevel converter HVDC nowadays has low losses which are comparable with those of thyristor HVDC and new technologies are emerging that open up possibilities for wider application areas. In the second decade of the twenty-first century, it has become apparent that DC transmission grids are both a viable solution to large-scale energy challenges and technically feasible. The primary application drivers are coming from the initiatives like the NorthSea DC grid, Medtech, Desertec, European Overlay Supergrid and various

xviii

Preface

projects in China, where two multiterminal VSC HVDC systems are already operating. It is accepted that the DC transmission grids will have similar or better levels of reliability and technical performance to the AC transmission system. This level of performance, security and reliability is technically feasible, although in many aspects DC grids will be substantially different from traditional AC systems. The development of DC grids brings significant technical advances in HVDC technologies, in particular related to DC CB (circuit breakers), DC/DC converters and DC protection systems, and substantial further research and development is anticipated. Nowadays HVDC and DC grids are associated with green energy, as facilitators of large-scale renewable energy plants. This helps with the public acceptance and image, and facilitates further investments in large public projects. Also HVDC is perceived as a technology that avoids pylons, by using long underground cables, which further strengthens arguments for future funding decisions. The timing of this book is, therefore, in step with accelerated interest in HVDC and projected significant increase and expansion in applications. The book is organised into three parts in order to study all three major HVDC concepts and current research developments: line commutated HVDC, VSC HVDC and DC grids including current research developments. Each part will review theoretical concepts first and analyse aspects of technology, interaction with AC grids, modelling, control, faults and protection with particular emphasis on practical implementation aspects and reported operational issues. The technology described in the first two parts is largely based on the operating HVDC systems, while the topic of DC grids is grounded in the significant volume of research at many institutions. The technical field of HVDC transmission and DC grids straddles three major traditional electrical engineering disciplines: Power transmission engineering – the impact of HVDC systems on the connecting AC transmission systems and the national grids is of primary importance. The influence of AC systems on HVDC is also of significance in terms of technical performance, stability, protection and power transfer security in general. The harmonic interaction will be studied in some depth. Power electronics – each HVDC link involves at least two AC/DC converters while DC grids will have many more including semiconductor DC CBs and DC/DC converters. These converters have similar features to the traditional low-power converters but many other unique requirements exist to develop valves and converter assemblies capable of sustaining up to 800 kV and perhaps over 4500 A. The protection of valves and converters is very important and defining power electronics feature in HVDC. Control engineering – modelling and simulation of HVDC is essential for design and operation and several different modelling approaches exist depending on the model application. In particular, because of high costs of HVDC testing and the consequences of any design issues, model accuracy and simulation speed play a crucial role in the system design. The control systems for HVDC have evolved into very complex technologies which are always multivariable and non-linear with multiple control layers. The above three technical disciplines will be employed in this book in order to analyse all of the essential technical aspects of HVDC and DC grids, aiming to facilitate learning by researchers and engineers interested in this field.

Preface

The material in this book includes contributions from many HVDC researchers and engineers, and it is developed from research projects funded by several research councils and private firms. More importantly, the studies are inspired and built on previous work by numerous HVDC engineers and researchers. The author would like to express gratitude to Dr Khaled Ahmed for signification contribution to the first edition of this manuscript, which has served as the basis for the second edition. The author is particularly thankful to ALSTOM Grid, UK, for making their comprehensive report ‘HVDC Connecting to the future’ available to the authors, as well as to Siemens, Germany, and ABB, Sweden, for their HVDC photographs. I am also indebted to all of the researchers at the University of Aberdeen HVDC research centre and in particular to Dr. Weixing Lin, Dr. Ali Jamshidifar, Dr. Masood Hajian, Dr. Huibin Zhang, Mr. Stefan Kovacevic, and Dr. Lu Zhang for their contributions. Special thanks are reserved for SSE, Scotland, and, in particular, to Andrew Robertson, for their support of the HVDC course at the University of Aberdeen, which provided substantial material for this book. The author is further grateful to the following organisations, which have supported related research studies at the University of Aberdeen: • • • •

EPSRC (Engineering and Physical Sciences Research Council) UK; ERC (European Research Council), FP 7 Ideas program; RTE (Réseau de Transport d’Électricité), France; EU Horizon2020.

January 2019

Dragan Jovcic

xix

1

Part I HVDC with Current Source Converters

3

1 Introduction to Line Commutated HVDC 1.1 HVDC Applications Thyristor-based high voltage direct current (HVDC) transmission has found application in more than 150 point-to-point worldwide installations, and in each case has proven to be technologically and/or economically superior to alternating current (AC) transmission. Typical HVDC applications can be grouped as follows: • Submarine power transmission. AC cables have large capacitance and for cables over 40–70 km the reactive power circulation becomes unacceptable. This distance can be extended somewhat with reactive power compensation. For larger distances HVDC is more economical. A good example is the 580 km, 700 MW, ±450 kV NorNed HVDC between Norway and The Netherlands. • Long-distance overhead lines. Long AC lines require variable reactive power compensation. Typically 600–800 km is breakeven distance, and for longer distances HVDC is more economical. A good example is the 1360 km, 3.1 GW, ±500 kV Pacific DC intertie along the west cost of the USA. • Interconnecting two AC networks of different frequencies. A good example is the 500 MW, ±79 kV back-to-back Melo HVDC between Uruguay and Brazil. The Uruguay system operates at 50 Hz whereas the Brazil national grid runs at 60 Hz. • Interconnecting two unsynchronised AC grids. If the phase difference between two AC systems is large they cannot be directly connected. A typical example is the 150 MW, ±42 kV McNeill back-to-back HVDC link between Alberta and Saskatchewan interconnecting asynchronous eastern and western American systems. • Controllable power exchange between two AC networks (for trading). The AC power flow is determined by the line impedances, and therefore the AC power flow cannot be directly controlled in each line. In complex AC networks it is common to observe loop power flow or even overloading or under-utilisation of some AC lines. Many HVDC systems participate directly in trading power and one typical example is the 200 MW, ±57 kV Highgate HVDC between Quebec and Vermont. There are other less common applications of LCC (line commutated converter) HVDC technology and the 300 MW Levis De-Icer HVDC project will be mentioned. Here, one standard HVDC converter station (converter from Static Var Compensator) is used to provide very high DC of up to 7920 A (feeding essentially a DC short circuit) to enable heating of remote Canadian overhead lines in order to prevent ice build-up. High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

1 Introduction to Line Commutated HVDC

Cost

4

DC

HV HVDC station costs

H

HVAC station costs

C VA

Beakeven distance For cables 40–70 km For overhead lines 600–800 km

Line length

Figure 1.1 HVDC and HVAC transmission cost comparison.

An important argument for selecting HVDC instead of AC for a new transmission line is also the contribution to short circuit level. HVDC is able to limit the fault current and therefore will not require upgrade of substation equipment. Figure 1.1 shows a comparison of costs for DC and AC transmission lines. In the case of HVDC the initial capital investment is much higher because of the converter costs. As the transmission distance increases, the benefits of DC compensate for the capital investment and at certain distance the total cost of the HVDC system is same as that of the AC line. The breakeven distance is in the range of 40–70 km for submarine cables and in the range of 600–800 km for overhead lines. Figure 1.2 shows an aerial view of terminal station of the 500 MW Moyle HVDC link. This HVDC enables controllable bidirectional power exchange between Scotland and Northern Ireland.

1.2 Line Commutated HVDC Components Figure 1.3 shows a typical line commutated converter HVDC schematic interconnecting AC systems 1 and 2. It consists of two terminals and a DC line between them. Each terminal (converter station) includes converters, transformers filters, reactive power equipment, a control station and a range of other components. There are two DC lines in this figure while one line is at ground potential. As shown in Figure 1.3, the major components of an HVDC system include: • Converters. These typically include at least one six-pulse thyristor (Graetz) bridge. Each bridge consists of six thyristor valves which in turn contain hundreds of individual thyristors. With large systems, bridges are connected in series in 12- or 24-pulse configuration. These 12-pulse converters can be connected into poles or bipoles. • Converter transformers. These are of a special converter transformer type that is somewhat more expensive than typical AC transformers of the same rating. The converter transformers are designed to operate with high harmonic currents and to withstand AC and DC voltage stress. In most cases converter transformers will have tap changers that enable optimisation of HVDC operation.

1.2 Line Commutated HVDC Components

Figure 1.2 Terminal station of Moyle HVDC interconnector (bipole 2 × 250 MW, ±250 kV, with light-triggered thyristors, commissioned in 2001). Source: Reproduced with permission of Siemens.

• Smoothing reactors on the DC side. The typical inductance for large HVDC systems is 0.1–0.5 H, which is determined considering DC fault responses, commutation failure and dynamic stability. The reactors are of air-core, natural air-cooling type and costs are modest. • Reactive power compensation. The converters typically require reactive power of around 60% of the converter power rating. A large portion of this reactive power is supplied by filter banks and the remaining part by capacitor banks. Since reactive power demand varies with DC power level, the capacitors are arranged in switchable banks. • Filters. A typical 12-pulse thyristor terminal will require 11th, 13th, 23rd, and 25th filters on the AC side. In addition, a high-pass filter is frequently included. In some cases third harmonic filters are required. Some HVDC systems with overhead lines further employ DC-side filters. • Electrodes. Some old HVDC systems normally operate with sea/ground return but most grid operators no longer allow permanent ground currents for environmental reasons. Electrodes demand ongoing maintenance costs. Many new bipolar systems are allowed to operate with ground return at half power for a short time (10–20 minutes) in case of loss of an HVDC pole. This implies that electrodes are designed for full current, but carry no current in normal operation. • Control and communication system. Each terminal will have a control system consisting of several hierarchical layers. A dedicated communication link between terminals is needed but speed is not critical. An HVDC link can operate in case of a loss of communication link.

5

Terminal 1 AC system 1 3 phase V1g, f1

Smoothing reactor

Smoothing reactor

transformer Y ∆

P1g, Q1g CB

I1dc Thyristor bridge

DC line

V1dcp CB Y Y transformer filters

Terminal 2

Thyristor bridge

CB ∆ Y transformer

AC system 2 3 phase V2g, f2 P2g, Q2g

V2dcp α2

α1

V1g Reactive power compensation

I2dc Thyristor bridge

Thyristor bridge

CB Y Y transformer

DC line filters

V2g

electrodes Reactive power compensation Station 1 control

Communication system

Figure 1.3 Typical HVDC schematic (12-pulse monopole with metallic return).

Station 2 control

1.3 DC Cables and Overhead Lines

1.3 DC Cables and Overhead Lines 1.3.1

Introduction

LCC HVDC has been implemented using both overhead lines and underground/subsea DC cables. Overhead lines are vulnerable to lightning strikes, which are essentially DC faults. Nevertheless DC faults only cause transient disturbances and they are readily managed by LCC HVDC. Contrary to voltage source converter (VSC) HVDC, as will be discussed later, DC faults cause much more serious disturbances. The most common cable technologies that have been developed so far include: • mass-impregnated cables (MI); • low-pressure oil-filled cables; and • extruded cross-linked polyethylene (XLPE) cables. The above cable types have same conductors and their construction is similar but the insulation materials are substantially different. The cable voltage rating depends on the capability of the insulation (dielectric) material, and there are two main types of dielectrics, namely lapped and extruded.

1.3.2

Mass-impregnated Cables

Since 1895, MI cables have been used in power transmission. In MI cables, the dielectric is lapped paper insulation, which is impregnated with high-viscosity fluid. For bulk power transmission, MI cables are still the most suitable solution because of their capacity to work up to 500 kV DC. Also these cables tolerate fast DC voltage polarity reversal, making them suitable for LCC HVDC. The MI cables have a long record of field operation at a voltage of 500 kV and transmission capacity of over 800 MW (1.6 kA) for monopole HVDC, but 600 kV and 1000 MW ratings have been announced. Therefore an HVDC in bipolar connection is able to transmit up to 2000 MW with MI cables. These cables can be installed at depths of up to 1000 m below sea level and with nearly unlimited transmission length. The capacity of this system is limited by the conductor temperature, which can reduce overload capabilities. The 580 km-long, 700 MW, 450 kV cable link between Norway and The Netherlands represents the highest power and longest length for this cable type. At present most (over 90%) submarine cables are of the MI type.

1.3.3

Low-pressure Oil-filled Cables

Low-pressure oil-filled cables are similar in construction to MI cables but are insulated with paper impregnated with low-viscosity oil under an overpressure of few bars. The available technology today ensures voltages up to 500 kV and powers up to 2800 MW for underground installation. It can be used for both AC and DC transmission applications. Since oil flow is required along the cable, the cable length is limited to around 80 km. Additionally, the risk of oil leakage must be taken into account for environmental reasons.

7

8

1 Introduction to Line Commutated HVDC

Table 1.1 DC cables types for underground and submarine applications. Type

Mass-impregnated

Oil-filled

XLPE

Conductor

Cu/Al

Cu/Al

Cu/Al

Insulation

Paper and mass

Paper and fluid

Cross-linked PE

Voltage

600 kV

500 kV

320 kV (525 kV is available)

Capacity per cable

1000 MW

2800 MW

1000 MW

Converter type

LCC or VSC

LCC or VSC

VSC or unidirectional LCC

Distance

Unlimited

Limited because of oil

Unlimited

1.3.4

Extruded Cross-linked Polyethylene Cables

Extruded cross-linked polyethylene cables cannot withstand rapid polarity reversal and they are not normally used with LCC HVDC (unless it is a unidirectional system). They will be discussed further with VSC HVDC. The above three types of cables are used for both underground and submarine cables and their basic properties are shown in Table 1.1. The difference between the underground and submarine cables lies in the conductor material and the armour layer. Armour strengthening is used in submarine cables to withstand the axial mechanical tension during laying and operation. Cables with copper conductors are used for submarine applications while aluminium conductors are generally preferred for underground. Copper has high electrical conductivity and good mechanical properties. Also, it can be used to implement strong joints. However it is heavy and more expensive than aluminium, and for these reasons it is used when its mechanical properties are mandatory, such as in submarine cables. Aluminium has low conductivity and poorer mechanical properties. Splicing is more difficult. It is lighter and less expensive compared with copper.

1.4 LCC HVDC Topologies HVDC systems are divided into transmission systems and back-to-back HVDC. HVDC transmission can be bipolar or monopolar. A monopolar HVDC is typically used for smaller systems and the topology is shown in Figure 1.4. Typically positive DC voltage is adopted because it carries fewer corona issues. The return current can run through the ground or a dedicated cable can be employed. If a return cable is used (metallic return), it will be at ground potential with low insulation level (typically around 10 kV) and costs are therefore lower than for a positive-pole DC cable. A 12-pulse topology is shown with two six-pulse converters in series. Figure 1.5 shows a bipolar HVDC. Bipolar HVDC has two independent poles and it can operate at half-power if one DC cable or pole is out of service. Normally the poles are balanced and there is no ground current, but ground return is used if one pole is out of service. In modern grid codes, ground current is not allowed because of environmental concerns. In some national standards ground currents are allowed only for short periods

1.4 LCC HVDC Topologies

Terminal 1

AC system 1 3 phase V1g, f1

Terminal 2 I1dc

P1g, Q1g

DC cable (p)

I2dc

Y∆ V1dcp Y Y

AC system 2 3 phase V2g, f2

∆Y

P2g, Q2g

V2dcp α2

α1

Y Y V2g

V1g

Figure 1.4 Twelve-pulse monopolar HVDC with ground return.

Terminal 1 bridge Positive pole AC system 1 3 phase V1g, f1 P1g, Q1g

Y∆ bridge YY

I1dc

Terminal 2 bridge DC cable (p)

V1dcp α1

V2dcp

I2dc

α2

electrodes

electrodes

YY V1g

Positive pole AC system 2 3 phase V2g, f2 P2g, Q2g

bridge ∆Y

Y∆ bridge

bridge YY

bridge

Negative pole

∆Y

V1dcn

V2dcn α2

α1 DC cable (n)

bridge Negative pole YY V2g

Figure 1.5 Bipolar HVDC (12-pulse) with ground return.

of time in emergency situations (e.g. secondary reserve start-up for 10–20 minutes). Instead of ground return a third cable or DC cable from the faulted pole can be used occasionally. Figure 1.6 shows a back-to-back HVDC, which is frequently monopolar. In this topology both converter terminals are located in a single station and DC cables are very short. The main purpose of back-to-back HVDC is to provide controllable power transfer between two asynchronous AC systems or AC systems with different frequencies. Since DC cables are very short and therefore transmission losses are low, back-to-back HVDC is designed at low voltage (with as high a current as possible) in order to reduce costs (costs are proportional to insulation level). The smoothing reactors are very small or not required, since there is low probability of DC line faults. Back-to-back HVDC allows for operation with variable DC voltage, and this facilitates some limited reactive power control capability.

9

10

1 Introduction to Line Commutated HVDC

Terminal 1

AC system 1 3 phase V1g, f1 P1g, Q1g

Terminal 2 I1dc

AC system 2 3 phase V2g, f2

∆Y

Y ∆

P2g, Q2g

V1dcp α2

α1

Y Y

Y Y V2g

V1g

Figure 1.6 Back-to-back HVDC topology. 3%

25%

56% 8%

Auxiliaries Converter valves AC harmonic filters Valve cooling plant DC smoothing reactors HF filter Converter transformer

2% 5% 1%

Figure 1.7 Breakdown of typical LCC HVDC station losses at 1 p.u. power.

1.5 Losses in LCC HVDC Systems The losses in HVDC systems will include converter station losses and DC cable losses. Figure 1.7 shows the main components of typical HVDC station losses. The total LCC HVDC station losses will depend on the size of the HVDC station, the voltage level and the configuration, and typically may amount to 0.5–1% of the power transfer. At partial loading the percentage losses will generally increase. Figure 1.8 shows the load dependence of major loss components. As an example, magnetising current in converter transformers will be constant irrespective of loading and at 10% loading the transformer losses are 20%.

1.6 Conversion of AC Lines to DC There have been many studies worldwide on converting existing AC lines into DC, mainly initiated by the desire to increase AC line capacity or to remove stability

1.6 Conversion of AC Lines to DC Converter valves

AC harmonic Filters

DC smoothing reactor

Converter transformer

100

Loss Component (%)

90 80 70 60 50 40 30 20 10 10

20

30

40

50 60 DC Power (%)

70

80

90

100

Figure 1.8 Variation of HVDC station losses with DC power, shown relative to 1 p.u. losses.

constraints. These issues usually require costly line upgrades/reconductoring, series compensation or installation of a device from the FACTS (flexible AC transmission systems) family. In such case, conversion to HVDC can usually offer the biggest capacity increase and a range of other benefits. Typically towers and conductors will not be changed but insulators may need to be upgraded to operate with DC lines. The main advantages of converting existing AC line to HVDC are: • • • • •

an increase in capacity; fewer corona issues, and generally higher operating voltages; better control of active and reactive power, and other system-level benefits; better stability limits and active stabilisation of the grid; and lower transmission losses. Some of the disadvantages of conversion to HVDC include:

• more pollution being attracted to insulators energised with DC – insulator upgrade is recommended; and • converter station costs. Figure 1.9 shows some common options for converting a single-circuit three-phase AC transmission into DC: 1. The first option employs all three conductors for a single DC pole while ground is used for return. This method will significantly increase current carrying capacity but ground return will not be allowed in many modern systems. 2. The second options adopts a DC bipole with metallic return. The neutral conductor can be used for monopolar operation. 3. The third option is based on a tri-pole HVDC concept. This method uses the third conductor alternatively as a positive and negative pole, which exploits the long thermal constants of conductors. A capacity increase of around 37% is achieved (over

11

12

1 Introduction to Line Commutated HVDC

R

S

T AC

+

+

+

+

0

–

+

+/–

–

Figure 1.9 Options for conversion of three-phase AC lines into DC.

DC monopole with ground return DC bipole with metalic return DC tripole with metalic return

bipole configuration) using lines and the RMS values of current in the conductors (over 10 minutes) are equal to the conductor rating. An additional bidirectional converter is required.

1.7 Ultra High Voltage HVDC The standard DC voltage for HVDC is 500 kV and the Itaipu 3150 MW, ±600 kV HVDC has used the highest DC voltage for a long period. However with emerging requirements for bulk power transmission of 5–10 GW over long distances in Asia, Africa and South America in the late 1990s resulted in the progressive development of UHVDC (ultra high voltage DC). Xiangjiaba–Shanghai 6400 MW, ±800 kV UHVDC, implemented in 2010, was the first commercial UHVDC, and four other ±800 kV systems were implemented in 2011–2013, while studies are underway for 1100 kV DC voltages. The progress towards UHVDC has demanded much research and development effort, and the main challenges are summarised below: • improvements in insulation, in particular in polluted areas; • transformer development, including bushings; • development of ultra high voltage (UHV) test centres. It is important to appreciate that all of the equipment, including auxiliaries that connect to DC lines, must be uprated to UHV voltages. In practice this translates to longer units (bushings, arresters, voltage transducers, current transducers, etc.) with more series-connected basic elements. Frequently, the main challenge becomes the mechanical strength in the face of increased forces from seismic requirements, wind and other factors. The use of new insulating materials and corona shields becomes standard to increase insulation levels, although the development of UHV insulators and bushings remains challenging. The UHV valve design is not considered a significant obstacle.

13

2 Thyristors 2.1 Operating Characteristics The thyristor is an essential component in high voltage direct current (HVDC) valves and it is still one of the most common devices used in power-switching applications in all industries. This is attributed to their high power ratings and high efficiency. Single devices have up to 8500 V, 4500 A capability, they are built on single wafers of up to 150 mm diameter, and have been in existence for over 60 years. The thyristor is a four-layer, three-terminal device, as shown in Figure 2.1. The three connections are A-anode, K-cathode and G-gate. When gate current is applied, the layer between J2 and J3 becomes N (negative) and the thyristor becomes a PN device similar to a diode, also shown in Figure 2.1. Functionally, it is similar to a diode but the start of conduction can be delayed using the gate circuit. A thyristor can be considered as a controllable diode, as shown in the operating curves in Figure 2.2. With no gate current, ig = 0, it behaves like an open circuit (OFF state) in both forward and reverse directions. A forward voltage across the device (A positive w.r.t. K) results in junctions J1 and J3 being forward biased, whereas J2 is reverse biased, and therefore only a small leakage current flows. If V AK is increased to a critical limit, the device suddenly switches to a conducting state as the result of the breakdown or breakover of J2. If a gate current ig is applied then the magnitude of V AK needed for breakover is dramatically reduced and the device behaves like a diode. The level of ig required is small compared with the main power current. The current I l is the latching current, which is the anode current required to ensure that the thyristor switches to the ON state. Once anode current reaches I l the gate current can be removed. The gate current is therefore a short pulse of 10–50 μs. Theoretically, a gate pulse is required once per half-cycle, but in practice gate pulses are sent multiple times per half-cycle to ensure firing under all operating conditions. Once the device is conducting, ig can be reduced and the device remains in the ON state. When the device is in conduction, its state is determined solely by the anode current. If the anode current I A falls below some critical value, the holding current I h (typically few a milliamps), the device switches off, reverting to the blocking OFF state. If a reverse voltage is applied across the device (negative V AK ), J1 and J3 become reverse biased, only J2 is forward biased and therefore only a small leakage current flows. If negative V AK is increased sufficiently, then eventually avalanche breakdown occurs across J1 and J3, resulting in damage to the device unless steps are taken to limit the High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

14

2 Thyristors

A (Anode)

A (Anode)

A P

P N K (Cathode)

G (Gate) K

N P N

Figure 2.1 Structure and symbol for thyristor and diode.

A

J1 G J2 K

J3

K (Cathode) (a) Diode

(b) Thyristor I (A) Forward breakdown voltage

I (A)

Forward voltage drop Forward conduction

Reverse breakdown voltage Reverse leakage current Reverse blocking

Reverse breakdown voltage Ih Reverse leakage current

Forward blocking

0

0

Vak (V)

Thyristor in off state

Reverse blocking

Values of Vak when Ig switched in Il Ig1 Ig2 Ig3

Vak (V)

Ig1 3

Strong system

No operating problems

2 < SCR < 3

Weak AC system

Operating difficulties can be expected. Some special controls are required.

SCR < 2

Very weak AC system

Serious operating difficulties can be expected. Very few HCDC systems operate with such low SCR.

The AC system is normally characterised by SCR and ratio X ratio , which enables the calculation of AC system parameters: Rs =

Vs2 LL

1 √ SCR Pdc 2 1 + Xratio

Xs =

Vs2 LL

Xratio √ SCR Pdc 2 1 + Xratio

(9.4)

The SCR can also be expressed using SCL (short circuit level). The SCL is defined as the power that the system in Figure 8.1 can deliver when the converter terminals are short circuited, and this power will also be considered as the base power in this chapter: SCL =

Vs2 LL zs

(9.5)

= Sbase

Further, the voltage and current bases can be defined as: Vbase

LL =Vs LL ,

V S Ibase = √s LL = √ base 3zs 3Vbase

(9.6) LL

The system in Figure 8.1 is quite simple and here SCL can be used to determine SCR. In general, however, SCR and SCL are terms used for completely different purposes and the remote source is selected differently. In the SCR definition in (9.3), zs represents impedance to the nearest bus with fixed AC voltage under normal conditions, which can take full converter power. As an example, a large voltage source converter (VSC) converter or STACOM or wind farm can establish a firm AC voltage bus under normal operation and can be considered as a remote source. On the other hand, zs in the SCL definition in (9.5) is the impedance to the rotating machine which can sustain rated AC voltage under fault conditions. SCL is associated with fault studies, and such a remote source is required since machine speed remains unchanged and constant excitation will give firm back electromotive force for the short fault duration. If SCL is used in the SCR definition, the conclusions on stability may become overly conservative. The AC system strength is classified as shown in Table 9.1. It is extremely difficult to operate HVDC with AC systems having SRC < 2. The SCR can be increased by strengthening the AC system, for example by adding transmission lines or generation plants or by increasing the system voltage. These measures are expensive and other methods should be considered, as discussed below.

9.2 Short Circuit Ratio and Equivalent Short Circuit Ratio

Pdc = 2 GW

Δ Y Lt = 0.02 H

0.05 H

5Ω

0.05 H

5Ω

Remote AC source

220 kV 65.77 μF

Figure 9.1 System in Example 9.1.

In order to include the influence of the reactive power capacitors and shunt filters on the converter bus, the equivalent short circuit ratio (ESCR) is introduced: ESCR =

SCL − Qf Pdc

(9.7)

where Qf is the reactive power supplied by the shunt capacitors/filters. The reactive power capacitors improve the power factor and improve the voltage profile but they also reduce SCR and may reduce the stability limits. With weak AC systems the impedance zs is large and this implies a large voltage swing at the converter terminals as the loading is changing. The maximum power transfer is determined by the system impedance and the voltage level, where larger impedance implies lower maximum power transfer limit. Example 9.1 An HVDC system of 2 GW is connected to the AC system as shown in Figure 9.1. Determine: (1) (2) (3) (4)

SCR; SCR assuming that one line is out of service; ESCR with both lines in service. Comment on the above results, regarding the HVDC operating difficulties.

Solution (1) Both lines in service: z1 = 5 + j2𝜋f 0.05,

z2 = 5 + j2𝜋f 0.05

z1 z2 = 2.5 + j7.854 = 8.24∠72.34 deg z1 + z2 V2 220, 0002 = 2.94 SCR = sll = z3 Pdc 8.24 × 2e9

z3 =

This is a system at the border between strong and weak.

97

98

9 HVDC Operation with Weak AC Systems

(2) One line out of service: SCR =

2 Vsll

z1 Pdc

=

220, 0002 = 1.47 16.48 × 2e9

This is a very weak system and HVDC will not be able to operate. (3) ESCR calculation: Qc =

2 Vsll

1∕(2𝜋fC)

= 1 GVAr;

SCL − Qf = ESCR = Pdc

220,0002 8.24×2e9

− 1e9

2e9

= 2.44

Comments. This example illustrates how shunt reactive power reduces the system strength. Shunt capacitors improve the power factor of the line current but they may create dynamic HVDC operating difficulties.

9.2.2

Operating Difficulties with Low SCR Systems

A weak AC system causes operating issues when connected to inverters whereas connection with rectifiers is less critical. It is unfortunate that weak AC systems are most often connected to inverters since HVDC systems are typically installed to supply power to areas with deficient generation. A rectifier is most frequently connected to stronger AC systems like remote generation regions. Some of the problems that occur with high-impedance AC systems include: • • • • •

voltage instability; small signal control instability; commutation failures; harmonic resonances; temporary overvoltages.

The first two problems will be discussed further in some depth in the following sections. Commutation failure is among the foremost concerns with weak AC systems, but it is linked with voltage instability. The primary cause of commutation failure is the depression of the AC system voltage. The more AC voltage deviates the higher the probability is of commutation failure. Weak AC systems have large impedance and this leads to large voltage swings which increase the commutation failure probability. Moreover, recovery from commutation failure becomes particularly difficult with weak AC systems. During the recovery period the converter operating angle is high, demanding more reactive power, while active power transfer is low, and to exacerbate problem the depressed AC voltage implies that the reactive power supply from capacitors is low. The AC system impedance has characteristic resonant peaks which typically fall at higher frequencies and do not cause harmonic magnification issues. However, with very weak AC systems the first resonant peak will be shifted to lower frequencies and may coincide with low harmonics. If AC harmonics are magnified they can cause control problems with the HVDC firing circuit, resulting in feedback instability as studied in Chapter 8.

9.3 Background on Power Transfer Between Two AC Systems

9.3 Background on Power Transfer Between Two AC Systems As the background, a theoretical study of power transfer between two AC systems is provided. Since a line commutated converter (LCC) converter is a current source for the AC grid, the study considers one AC voltage source and an ideal current source as shown in Figure 9.2. The aim is to explore theoretical limits for power exchange between an AC system and a converter through an equivalent line given by impedance zs . The basic equations for power flow analysis are given in (8.7)–(8.10). Assuming that the converter current magnitude is fixed at I base , which is theoretically the largest possible current, while the current angle 𝜑Ig is an independent variable, the active power Pg and point of common coupling (PCC) voltage V g curves can be obtained as shown in Figure 9.3. The case X ratio = infinity corresponds to the textbook case of power exchange between two AC systems through an inductive line. In this case, the maximum power transfer is obtained for a 90∘ phase shift between the voltages, giving a 45∘ phase shift between any voltage and the current. In such a case the maximum power transfer is equal to the short circuit power (Pdc = SCL). Therefore the theoretical minimum is SCR = 1, and this applies to both rectifier and inverter operations. The converter voltage in such a case would be 1.41 × V s . Figure 9.2 AC system and converter as a current source for phasor interaction studies. remote source

Rs

jXs

X X s /R = 5 s /R s = infi s = 10 nity =2

1.4

=5 X

s /R s

X

s /R s

Vg (p.u.)

= 1 = infi nit 0 y

s /R s

=1

1.6

–0.5

=2 =1

X

100

φlg (deg)

150

1

Rectifier

0.8 0.6

Inverter

0.2

X

–1.5

1.2

0.4

s /R s

X

s /R s

s /R s

–1

50

X /R X s X /R s = 5 s /Rs = 10 X /R s s s =2 s = infi nity X /R s s =1

1.8

Inverter

0

converter

2 Rectifier

X

0 Pg (p.u.)

X

X

s /R s s /R s

0.5

Ig Vg

Vs

1

Pg,Qg

Thevenin equivalent circuit of AC grid

200

0

0

50

100

150

φlg (deg)

Figure 9.3 Maximum power transfer between an AC system and an LCC converter.

200

250

99

9 HVDC Operation with Weak AC Systems Xs /R s = in Xs /R finity s = 10 X /R X s s = 2 s /R s =1 s = 5

0.5

1.5

X s/R s = 1

Xs /R

Rectifier

Inverter Xs/Rs = 2

0

Xs /R

s

–1.5

=2

X/ s R

–1

s

0

0.1

0.2

0.3

0.4

0.5 0.6 lg (p.u.)

0.7

Vg (p.u.)

Pg (p.u.)

–0.5

Xs /R

1

ity fin = in Rs / 0 Xs =1 X s/R s = 5 X s/R s

Inverter

s =5 X/ s R = X / Xs /sR 10 s R s = 1 s = in fin X/ 0 ity s R s =5 X/ s R s = X/ 2 s R s =1

Rectifier 0.5

=1

0.8

0.9

0

1

0

0.1

0.2

0.3

0.4 0.5 0.6 lg (p.u.)

0.7

0.8

0.9

1

Figure 9.4 Maximum power transfer between an AC system and an LCC converter, assuming that the converter current is in phase with the converter voltage.

If the X ratio reduces, then the maximum power transfer reduces for the rectifier and increases for the inverter, as seen in Figure 9.3. As an example, X ratio = 5 gives minimal theoretical SCR = 1/0.75 = 1.33 for rectifier and SCR = 1/1.2 = 0.83 for inverter. However to achieve these values, the current angle would need to be exactly 48∘ for the rectifier or 138∘ for the inverter, which is difficult to achieve in practice. A typical LCC converter operates with current lagging voltage by around 30–40∘ . Figure 9.4 shows the maximum power transfer between an AC system and an LCC converter assuming that the current is in phase with the voltage. Such operating conditions might occur if a STATCOM or a VSC compensates for LCC reactive power at PCC. It is seen that the minimal SCR = 2 is achieved for both rectifier and inverter in case X ratio = infinity. Figure 9.5 shows the maximum power transfer for a more practical case where the converter current is lagging voltage by 30∘ (corresponding to Qg = 0.58 Pg ). It is seen that the theoretically minimal SCR is 1.25 for both rectifier and inverter in the case X ratio = infinity. Where X ratio = 5 the theoretically minimal SCR is 1.5 for the rectifier and 1

2

infinity X s/R s = X /R = 10 s s Xs/Rs = 5 Xs /R s =2 Xs /R = s 1

0.5

Inverter

–0.5

–1

–1.5

0

0.1

0.2

0.3

0.4

0.5 0.6 lg [p.u.]

0.7

0.8

0.9

1

2

Inverter Xs/Rs = 5 Xs /R = s 10 Xs /R s = infin ity X /R s s = 10 X/ s R s =5

1.4 1.2 1

0.8

Xs/Rs = infinity Xs /R = X /R s 10 X / s s =5 s R X s =2 s /R s = 1

=1

= X s/R s

1.6

Vg [p.u.]

0

X s/R s

1.8

Rectifier Pg [p.u.]

100

X/ s R

0.6

X/ s R

Rectifier

s

0.4

s

=2

=1

0.2 0 0

0.1

0.2

0.3

0.4 0.5 0.6 lacm [p.u.]

0.7

0.8

0.9

1

Figure 9.5 Maximum power transfer between an AC system and an LCC converter, assuming that the converter current is lagging converter voltage by 30∘ .

9.5 System Dynamics (Small Signal Stability) with Low SCR 600

–800 0

SC

R

SC

–400 –600

.3 =2

400

= 2.

2

SCR = 6

300

R

–200

2. 5

0

=

200

SCR 500

R SC

=3

200

4 100 SCR = SCR = 5 SCR = 6 0 0 200 400 600 800 1000 1200 1400 1600 1800 2000 ldc (A)

SCR = 6 SC SC R = 5 R= 4 SC R =3

5 2. 3 = . R =2 SC CR S

Pg [MW] Qg (MVAr)

400

600

Vg (kV)

=6 SCR SCR = 3 SC R SC = 2.5 R =2 .2

Maximum available power (MAP) curve

200 400 600 800 1000 1200 1400 1600 1800 2000 ldc (A)

Figure 9.6 Interaction between converter DC and AC system for various AC grid strengths.

0.8 for the inverter. However the maximum allowed voltage swing at PCC bus should also be considered in order to derive general conclusions.

9.4 Phasor Study of Converter Interactions with Weak AC Systems Figure 9.6 shows the interaction between HVDC and AC systems, similarly to Figure 8.4, but the SCR is varied from strong (SCR = 6) to weak (SCR = 2.3). It is observed that the theoretically minimal system strength for the 500 MW test system is around SCR = 2.5, in order to enable a maximum available power higher than the rated power. In practice, however, a margin of at least 10–20% above the theoretical minimum would be needed. On the voltage graph, it is observed that weak AC systems cause very steep voltage slopes as DC power is varied. This amplifies stability problems since any external AC voltage drop (because of a remote fault) further depresses the power curve. The voltage swing between no-load and full-load conditions can be significant. Note also that reactive power supply from shunt capacitors reduces according to a square function of AC voltage, and this further depresses AC voltage.

9.5 System Dynamics (Small Signal Stability) with Low SCR Table 9.2 shows the system eigenvalues for a reduced SCR at the rectifier and at inverter sides, considering the CIGRE HVDC benchmark model studied in Chapter 7. It is seen that in both cases stability deteriorates with lower SCR. Lower SCR at the rectifier side predominantly affects eigenvalues 5 and 6 (referring to labels from Table 7.5), which indicates the presence of oscillations at around 30 Hz. The stability deteriorates very rapidly with reduced SCR at the inverter side, and instability can be expected around the second harmonic (119 Hz on AC side or 59 Hz on DC side). The real part of dominant eigenvalues 3 and 4 reduces by around 30% for a small SCR reduction (from SCR = 2.5 to SCR = 2.0). It is important to note that these dynamic issues arise in addition to all of the problems discussed in previous sections related to low SCR. In practice, when

101

102

9 HVDC Operation with Weak AC Systems

Table 9.2 Dominant CIGRE HVDC eigenvalues with reduced SCR. Original eigenvalues Rec SCR = 2.5, Inv SCR = 2.5

Eigenvalue sensitivity

Rectifier reduced SCR Rec SCR = 2.0, Inv SCR = 2.5

Inverter reduced SCR Rec SCR = 2.5, Inv SCR = 2.0

1

−37.343 + 437.23j

Rec, Rec

−41.60 + 414.29j

−33.19 + 443.37j

2

−37.343 − 437.23j

Rec, Rec

−41.60 − 414.29j

−33.19 − 443.37j

3

−90.311 + 398.73j

Inv, Inv

−81.96 + 397.33j

−63.94 + 374.78j

4

−90.311 − 398.73j

Inv, Inv

−81.96 − 397.33j

−63.94 − 374.78j

5

−118.84 + 195.9j

Rec, Rec

−102.47 + 176.65j

−124.87 + 176.81j

6

−118.84 + 195.9j

Rec, Rec

−102.47 − 176.65j

−124.87 − 176.81j

7

−5.62 + 5.38j

Inv, Inv

−5.39 + 5.43j

−6.13 + 5.93j

8

−5.62 − 5.38j

Inv, Inv

−5.39 − 5.43j

−6.13 − 5.93j

9

−5.49 + 5.049j

Inv, Inv

−5.55 + 4.85j

−5.49 + 5.01j

10

−5.49 − 5.049j

Inv, Inv

−5.55 − 4.85j

−5.49 + 5.01j

11

−43.46

Rec, Rec

−47.82

−29.49

12

−151.01

Rec, Rec

−148.9

−155.73

13

−107.0 + 981.7j

Rec, Rec

−105.02 + 937.95j

−107.26 + 982.51j

14

−107.0 − 981.7j

Rec, Rec

−105.02 − 937.95j

−107.26 − 982.51j

15

−154.4 + 1002.0j

Inv, Inv

−154.63 + 1002.1j

−127.70 + 955.15j

16

−154.4 − 1002.0j

Inv, Inv

−154.63 − 1002.1j

−127.70 − 955.15j

17

−1014.0 + 236.8j

Inv, Inv

−1014.0 + 236.8j

−955.29 + 267.11j

18

−1014.0 − 236.8j

Inv, Inv

−1014.0 − 236.8j

−955.29 − 267.11j

operating problems with weak AC systems arise, it might be difficult to pinpoint the exact cause of converter tripping.

9.6 Control and Main Circuit Solutions for Weak AC Grids If an HVDC is connected to weak AC system, then some special control approaches are required. The simplest solutions include larger extinction angle or various inverter stabilisation control loops. An inverter can be operated in DC voltage mode, which gives better stability. On the downside these approaches always imply larger firing angle, which in turn demands more reactive power, increases losses, produces more valve stresses and generates more harmonics. One possible control solution is to employ DC current control at the inverter terminal (as used at the Korean Jeju island HVDC link which enabled operation with a very weak AC system; SCR < 2). As a negative consequence of this approach the nominal firing angles are larger and both rectifier and inverter are rated for somewhat higher voltages and currents. Synchronous condensers are employed with many HVDC links to avoid low SCR problems, as shown schematically in Figure 9.7. Synchronous condensers provide positive shunt impedance in parallel with the AC system and this improves SCR.

9.7 LCC HVDC with SVC Vdc α

ΔY

Pg,Qg Vg

filters

Ps,Qs

Zs

Remote AC source Vs

Vdc α

Ps,Qs ΔY

Pg,Qg

Controller

Synchronous condenser

Vs Controller

Vg

Qcomp

Remote AC source Zs

Qcomp

SVC

filters TCR

(a) HVDC terminal with Synchronous Condenser

(b) HVDC terminal with Static Var Compensator

Figure 9.7 Synchronous condensers and SVC as solutions for HVDC with weak AC systems.

Also, they increase the system inertia, which helps with transient responses. They can be configured to control reactive power or the AC voltage in a feedback manner, which indirectly improves the stability of the AC system. Synchronous condensers will generally significantly reduce voltage overshoots and improve recovery responses, including commutation failure recovery, but their response is rather slow and settling time is 200–400 ms. As a very effective method of maintaining converter AC voltage, the static var compensators (SVCs) or static synchronous compensators (STATCOMs) may be employed. SVCs are capable of providing reactive power which is rapidly controllable and they can be controlled to maintain AC voltage at a constant level with time constants of 50–200 ms (20–100 ms for STATCOMs). However, an SVC is essentially a shunt capacitor and therefore as all shunt capacitors it will reduce ESCR, which might negatively affect system dynamics. The overvoltage peaks are larger and commutation failure recovery times are generally larger than those with synchronous condensers. STATCOMs have the advantage of the fastest response and a reactive power supply which is independent on the system voltage magnitude.

9.7 LCC HVDC with SVC This section will examine the phasor interaction curves when SVC is employed at PCC. It is assumed that the SVC capacitive circuit will provide the full reactive power requirements for the inverter (250 MVAr for the test HVDC). The inductive circuit of SVC has a 350 MVAr rating in order to provide 100 MVAr of inductive power at light HVDC load. Table 9.3 shows the parameters of the SVC used with the test system. Figure 9.8 shows the inverter operating curves of the test system when fixed capacitors are used, and comparatively when SVC is used for reactive power compensation. In this case a weak AC system is considered (SCR = 2.0) to better illustrate the benefits. The same inverter test system from previous sections is in DC voltage control mode. Two cases of SVC control are considered: (1) SVC regulates the voltage V g . (2) SVC follows the converter reactive power Qg , giving unity power factor as seen from the grid.

103

104

9 HVDC Operation with Weak AC Systems

Table 9.3 SVC parameters in the test case. Rated voltage

V SVC = 300 kV

Capacitive power

Qc = −300 MVAr

Inductive power

Ql = 400 MVAr

Total reactive power

−300 MVAr < Qcomp < 100 MVAr

Converter rating

400 MVA

The first graph in Figure 9.8 illustrates that an inverter with fixed capacitors would not be able to deliver a rated power of 500 MW. It is seen that SVC can significantly increase the maximum available power, practically eliminating the danger of instability. The SVC with pf = 1 shows a less favourable response since full power is achieved only if the DC current increases to 1100 A. The voltage graph (V g ) is particularly important since it illustrates that the HVDC terminal with SVC has a significantly better voltage profile for the whole power range. The fast SVC controls can adjust reactive power in the same control bandwidth as the HVDC controls. Without SVC the voltage swing would be over 40%. The graph with extinction angle (𝛾) proves that SVC support (V g = const. control) enables much higher 𝛾 at the HVDC inverter at high powers, which implies that commutation failure probability will be lower. The last graph shows the required compensator power. SVC rating with constant voltage control should be around 60% of the HVDC rating. Figure 9.9 shows the influence of SVC at rectifier terminal with a weak AC system (SCR = 2.0). In the power graph it is seen that the rectifier with fixed capacitors is not able to deliver the rated power. When the SVC in voltage control mode is connected, the maximum power achieved is over 550 MW. The grid voltage (V g ) profile shows the remarkable benefit of using SVC. It is also interesting that if SVC is operated to follow rectifier reactive power, then the benefit is rather limited. Figure 9.10 shows the operating curves of the joint system HVDC plus SVC, as seen from the grid. The variables Ps and Qs from Figures 9.7 and 8.1 are shown, which is the method more commonly used with VSCs. The operating point can be anywhere within the area, which is a very different shape from the familiar circle-resembling PQ shape with VSC HVDC. The active power is controlled by the HVDC while reactive power is regulated independently by the SVC.

9.8 Capacitor Commutated Converters for HVDC Capacitor commutated converters (CCCs) use series-connected capacitors either on the valve side or on the grid side of the converter transformer. They are more often placed on the valve side as shown by C s in Figure 9.11. The CCC concept has been implemented in two practical projects: 2002, 2200 MW, ±70 kV, back-to-back Garabi (Brazil-Argentina) HVDC and in 2003, 200 MW, ±13 kV, back-to-back Rapid City HVDC. It is convenient that CCCs achieve a reactive power supply that is proportional to the line current and therefore they naturally compensate for converter reactive power

9.8 Capacitor Commutated Converters for HVDC 400

600 Qg (SVC, Vg = const)

300

550

Qg (fixed caps)

100

500

Qg (SVC, pf = 1)

0

Vg (kV)

Pg (MW), Qg (MVAr)

200

–100 –200 –300

–600 0

Pg (SVC, Vg = const) 200

400

600 ldc (A)

800

400

1200

1000

Vg (SVC, pf = 1)

250 0

500

200

400

600 ldc (A)

800

1000

1200

50

480

45

Vdci (SVC, Vg = const)

460

Vdci (SVC, pf = 1)

40 Gamma (deg)

440 Vdci (kV)

Vg (SVC, Vg = const)

300

Pg (SVC, pf = 1)

–500

Vg (fixed caps)

350

Pg (fixed caps)

–400

450

Vdci (fixed caps)

420 400 380

Gamma (fixed caps)

35 30

Gamma (SVC, Vg = const)

25

Gamma (SVC, pf = 1)

360 20

340 320 0

200

400

600 ldc (A)

800

1200

1000

15 0

200

400

600 ldc (A)

800

1000

1200

500 450 400

Qc (MVAr)

350 300

Qcomp (fixed caps)

250 200

Qcomp (SVC, Vg = const)

150 Qcomp (SVC, pf = 1)

100 50 0 0

200

400

600 ldc (A)

800

1000

1200

Figure 9.8 Impact of SVC at HVDC inverter terminal with weak AC system (SCR = 2.0).

variation. As a result only a small amount of external reactive power compensation is required. Another advantage of CCC is that the commutation failure probability is reduced since capacitors provide a more stable (less dependent on the grid condition) commutating voltage. On the downside, CCC introduces higher voltage stress on the valves, requiring higher converter costs and higher harmonics. In the case of DC faults, the fault current will run through series capacitors and this requires capacitor overrating.

105

9 HVDC Operation with Weak AC Systems 600

580

540 520

400

500

Pg (fixed caps) 300

Vg (V)

Pg (MW), Qg (MVAr)

560

Pg (SVC, Vg = const)

500

Pg (SVC, pf = 1)

480

Vg (fixed caps)

460 200

Vg (SVC, pf = 1)

440

Vg (SVC, Vg = const)

420

100

400 0 0

5

10

15

20 25 30 Alpha (deg)

35

40

45

380 0

50

501

5

10

15

20 25 30 Alpha (deg)

35

40

45

50

1200

500.5

Vdcr (SVC, Vg = const)

500 499.5

1000

498.5

Idc (SVC, Vg = const)

800

Vdcr (fixed caps)

499

Idc (A)

Vdcr (V)

Vdcr (SVC, pf = 1)

Idc (fixed caps)

600

Idc (SVC, pf = 1)

498 400

497.5 497

200

496.5 496 0

5

10

15

20 25 30 Alpha (deg)

35

40

45

50

0 0

5

10

15

20 25 30 Alpha (deg)

35

40

45

50

500 Qcomp (SVC, Vg = const)

400

Qcomp (MVA)

106

Qcomp (fixed caps)

300 200

Qcomp (SVC, pf = 1)

100 0 –100 0

5

10

15

20 25 30 Alpha (deg)

35

40

45

50

Figure 9.9 Impact of placing SVC at the HVDC rectifier terminal with a weak AC system (SCR = 2.0).

9.9 AC System with Low Inertia The AC systems with low inertia, when coupled with HVDC, may cause frequency deviation problems. In general, HVDC operation is not affected by frequency deviation since the phase locked loop can adequately track AC frequency and phase changes. The frequency deviation is, however, of concern for the AC system, which must comply with frequency standards, and the interaction with HVDC may exacerbate the issue.

9.9 AC System with Low Inertia

400

Reactive Power Qg (MVAr)

Vs = 430 kV

Vs = 420 kV

300 200 100

Rectifier, Reactive import

Inverter, Reactive import

0 Inverter, Reactive export

–100

Rectifier, Reactive export

–200 –300 –600

–400

–200

0

200

400

600

Active Power Pg (MW)

Figure 9.10 PQ diagram of 500 MW HVDC with a −250/+100 MVAr SVC (SCR = 4). Idc T1 Ia Ib Ic

Va Vb

T5

Cs Cs

Vdc

Cs

Lt

Vc

T3

T4

T6

T2

Figure 9.11 HVDC with capacitor commutated converter.

A representative test system topology involves an HVDC connected to a single-machine AC system, as shown in Figure 9.12. The machine with inertia may be a generator or a synchronous condenser. The basic equation for torque balance on the machine is: J

d𝜔m = Tm − Te dt

(9.8)

where 𝜔m is the mechanical speed, T m is the mechanical torque, T e is the electrical torque and J is the moment of inertia of the generator and turbine. Considering small deviations around the operating point and using per unit notation for all variables, an equivalent equation is obtained: 2Hs

d𝜔mpu dt

= Tmpu − Tepu

(9.9)

107

108

9 HVDC Operation with Weak AC Systems

Pdc AC machine (fs, Hs) Zs

Δ Y

Pm Pacl DC line fault

Figure 9.12 Equivalent circuit for systems with low inertia. Table 9.4 Typical values for inertia constants. Inertia constant (MWs MVA−1 )

Type of machine

Thermal unit, two-pole

2.5–6

Thermal unit, four-pole

4–10

Hydraulic unit

2–4

Synchronous condenser

1–2

where the per unit inertia constant H s is defined as 2

Hs =

1 J𝜔om 2 Sbase

(9.10)

Table 9.4 shows some typical values for the machine inertia constants. Using (9.9) it is possible to derive an expression for frequency deviation Δf depending on the HVDC power and system inertia for the system in Figure 9.12. Δf =

(Pmpu − Paclpu − Pdcpu )fs Δt 2Hs

(9.11)

where Δt is the considered time interval (fault clearing time or HVDC fault recovery time) and all other variables are defined in Figure 9.12. The fault time is typically known from the protection studies, and therefore this expression facilitates a frequency deviation study for given inertia and power levels. The above formula can also be used to determine the maximum DC power that can be connected to the system under the given frequency deviation limits. The same model can further be employed with dead networks, i.e. those that have no active generation. In such a case synchronous condensers are used and therefore Pmpu = 0. Example 9.2 A weak AC system has an equivalent 800 MVA hydro unit with per unit inertia constant of 3 MWs MVA−1 . An HVDC with overhead wires is being considered for connection to this system. Assume that the nominal frequency is 50 Hz and the maximum allowed frequency deviation is 0.5 Hz (0.01 p.u.). The DC fault self-clearing time is 100 ms and typical HVDC recovery time is assumed to be 200 ms. Determine the

9.9 AC System with Low Inertia

maximum rating of HVDC that can be connected, while not exceeding maximum frequency deviation. Assume that governor reaction is negligible in the considered short timeframe. Solution It is assumed that mechanical power is Pmpu = 1 p.u., and that before the fault electrical power balances the mechanical power Pmpu − Paclpu − Pdcpu = 0. While the DC fault is being cleared for 0.1 + 0.2 s, DC power reduces to zero and the power balance equation becomes Pmpu − Paclpu − 0 = Pdcpu . Therefore, Δf =

(Pdcpu )fs Δt

2Hs Δf 2Hs 0.5 × 2 × 3 Pdcpu = = = 0.2 p.u. fs Δt 50 × (0.1 + 0.2) Pdc = Pdcpu MVA = 0.2 × 800 = 160 MW Therefore in the above case the maximum HVDC rating is 20% of the generator rating. In order to increase HVDC penetration, the system inertia could be increased, for example by connecting synchronous condensers.

109

111

10 Fault Management and HVDC System Protection 10.1 Introduction With thyristor high voltage direct current (HVDC) systems, the HVDC controls are generally capable of resolving most transient fault situations in a very short time. On a longer time scale (over 50 ms), if the fault situation persists, various mechanical CBs (circuit breakers) will react. A number of mechanical CBs are associated with an HVDC system but they are used only as a final protection means, i.e. when HVDC controls cannot solve disturbance and permanent isolation is required. The tripping of CBs implies loss of capacity. Figure 10.1 shows some typical fault locations and the means of protection. HVDC controls always first react to a disturbance. A tap changer may also react when a modest AC voltage deviation persists for a long time (remote AC fault or tripping).

10.2 DC Line Faults The line commutated HVDC is capable of rapidly controlling DC voltage in a positive or negative region and therefore it can react to DC faults according to a fault control strategy. This includes limiting the DC current magnitude and changing DC voltage polarity in order to extinguish DC current. Figure 10.2 shows system variables (rectifier and inverter) for a DC fault, at 0.45 s, using the same 500 MW HVDC test system as in Chapter 6. The fault is cleared by special HVDC controls. First, the normal HVDC control response is studied, which applies before 0.57 s, in order to analyse shortcomings in dealing with DC faults: • The rectifier regulates the DC current at a reference value (I dcref_rec = 1 p.u.), which continuously feeds the fault. This requires a substantial reduction of rectifier DC voltage and therefore the rectifier firing angle 𝛼 r is just below 90∘ . It is seen that the reactive power demand is excessive (600 MVAr) because of the operating conditions with rated DC current and very large firing angle. • The inverter current reduces below the inverter reference value (I dcref_inv = I dcref_rec − I margin ) and the inverter moves to current control mode by reducing inverter firing angle 𝛼 i . However in order to keep the same polarity of DC current, the inverter DC voltage polarity changes and the inverter firing angle settles to just below 90∘ . The inverter station now also operates as a rectifier and feeds the DC fault. Inverter reactive power demand is over 500 MVAr. High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

112

10 Fault Management and HVDC System Protection

Transmission line Converter CB

Valve faults

Converter group faults

DC line faults

AC system faults Pole control

Filter faults filters

Electrode line

Figure 10.1 Fault locations and protective means with HVDC systems.

The above response is not suitable as a long-term strategy to DC faults since converters still feed the DC fault arc as seen in the fault resistor current responses. Also, excessive reactive power demand may disturb AC systems. It is necessary to extinguish the fault current (to break the arc) by discharging line energy through converters. Therefore a special DC fault protection control strategy is initiated on detection of DC faults, which changes the DC voltage profile as shown in Figure 10.3. This special control strategy consists of: • rectifier firing angle being forced into inversion (110–120∘ ), which discharges the line energy on the rectifier side; • inverter firing angle being limited to inversion mode (110–120∘ ), which discharges the line energy on the inverter side. The above control action is simulated in the model in Figure 10.2, and it becomes active around 0.57 s. It is seen that both rectifier and inverter angles are temporarily advanced to 110∘ , DC voltage is reversed and the fault current drops to zero. This completely extinguishes the fault current and naturally clears the fault. In Figure 10.2, the DC voltage ramp is initiated immediately after the fault is cleared and normal operation resumes after 300–400 ms. In a practical system, a restart would be attempted after certain delay for deionisation. This above sequence is repeated until the DC voltage is recovered to nominal values. Note that a special discriminatory logic is needed for the detection of DC faults, since the above control strategy is not appropriate in the case of commutation failures (which also bring DC voltage to zero). In the case of DC systems with overhead lines, most DC faults will be transient and they are cleared with rapid DC control action. However with cable systems, DC faults are usually permanent and a slightly different fault management is used.

10.3 AC System Faults 2000 ldcr

ldcr (A) 1000

ldcr_ref 0 0.4 × 105 6

0.5

4

0.6

0.7

0.8

0.9

1

0.7

0.8

0.9

1

DC fault cleared

DC fault

Vdcr (V) 2 0 0.4

0.5

0.6

150 αr (deg) 100 50

CC mode

0 0.4 × 105 2 Vacr (V)

Pr (W), Qr (VAr)

0.6

0.7

0.8

0.9

1

0.5

0.6

0.7

0.8

0.9

1

0.6

0.7 Time (s)

0.8

0.9

1

0.7

0.8

0.9

1

0.7

0.8

0.9

1

0

–2 0.4

× 108

DC fault protection

0.5

5

Pr

0

Qr

–5 0.4

0.5

(a) Rectifier Variables 200 0

ldci_ref

100 ldci (A) 0

ldci

0 0.4 × 105 6

0.5

4

0.6

DC fault

DC fault cleared

Vdci (V) 2 0 0.4

0.5

0.6

150 100 αi (deg) 50

VDC mode

VDC mode CC mode

0 0.4 × 105 2

0.5

DC fault protection 0.6

0.7

0.8

0.9

1

0.5

0.6

0.7

0.8

0.9

1

0.6

0.7

0.8

0.9

1

Vaci (V)0 –2 0.4 × 108 5 Pi (W), 0 Qi (VAr) –5

Qi Pi

0.4

0.5

(b) Inverter Variables 2000 1500 Idc_f (A) 1000

DC fault intiated 500 0 0.4

DC fault cleared

0.5

(c) Current in the fault path

0.6

0.7 Time (s)

0.8

0.9

1

Figure 10.2 HVDC system response to a DC fault at 0.45 s. The fault is cleared by HVDC controls.

10.3 AC System Faults 10.3.1

Rectifier AC Faults

The AC voltage depressions on the rectifier side will result in DC current reduction. The rectifier controller can counteract small AC voltage depressions (a few per cent)

113

Norm

al DC

volta

DC f ault contr and norm ol rea a ction l

0

ge

DC fault

Inverter DC Voltage

10 Fault Management and HVDC System Protection

Rectifier DC Voltage

Figure 10.3 Steady-state DC voltage profile for DC faults and effect of DC fault protection control.

DC fault and fast fault protection at inverter Distance

D fa C f ul au t p lt re rote and ct ct fa ifi io s er n t at

114

by reducing the firing angle until the minimum angle limit is reached (𝛼 r = 2∘ ). In the case of further rectifier AC voltage depressions, the DC current will be reduced and the inverter will finally move to constant current mode by reducing the inverter DC voltage. The HVDC system will now operate at a DC current equal to I dcref_i = I dcref_r − I margin , which is typically 85–90% of the rated current. However if the rectifier AC (and consequently DC) voltage is particularly low it would be inappropriate to operate at 90% of the DC current since firing angles are large and reactive power demand becomes excessive. The experience with weak AC systems has shown very difficult recoveries when converters demand large reactive power. For this reason a special VDCOL (voltage-dependent current order limiter) is introduced, as shown in Figure 10.4. The VDCOL shape and the whole V–I curves are different for different manufacturers, and they are also optimised for particular HVDC installation. The main purpose of VDCOL is to reduce the current order for lower DC voltages. 10.3.2

Inverter AC Faults

The inverter AC system faults will always result in commutation failure, except for very small (a few per cent) voltage disturbances. A commutation failure is a DC short circuit and results in a temporary loss of HVDC power transfer. However commutation failure will not be seen as a short circuit on the AC side. Following detection of commutation failure, the HVDC controls will increase inverter 𝛾 (𝛾 kick) and initiate a gradual power ramp climbing up the V–I curve, using also VDCOL slope, until the normal operating point is reached. The inverter 𝛾 is gradually reduced to nominal values following successful recovery. In some cases repeated commutation

10.4 Internal Faults

VDC

Rectifie

r α = co

Inverter VDC = const Inv ert er γ= c Rectifier CC

Inverter CC

nst

lm

OL

DC

In

ve

rte

on

st

L

rV

O

r

ifie

C VD

t ec

R

0

IDC

Figure 10.4 HVDC V–I diagram with VDCOL.

failure is encountered and recovery attempts are repeated with progressively lower recovery slopes. Figure 10.5 shows a typical commutation failure recovery process which can be completed in 200–500 ms. DC voltage drops to zero, which is sure sign of commutation failure. On detecting low extinction angle, the inverter moves to constant extinction angle mode, which establishes normal commutation, and the power is slowly ramped.

10.4 Internal Faults The internal faults include thyristor faults, valve faults, bridge faults and a range of other faults inside the valve hall, which in turn can be caused by many factors. Each valve consists of many individual thyristors connected in series and fired simultaneously. There are several redundant thyristors in each valve, and a valve will operate normally in the case of a thyristor failure (a thyristor always fails in a short circuit). The voltage stress on the remaining thyristors will marginally increase but the failed thyristors will be replaced at the next scheduled maintenance. The most severe internal fault is the valve fault, which can occur as a flashover between valve external connections. Such a fault will bring extreme current and voltage stress across the other valves. The protection response is bypass and converter tripping, but the components must be designed to withstand fault conditions for the protection operating time. The bypass involves two steps: first, two valves on the same converter leg are fired to provide rapid redirection of the fault current (extinguishing the fault arc) and prevent negative DC voltage. In the second stage, if the fault is not cleared, the mechanical bypass switch (BPS) is closed to provide a permanent DC current path.

115

116

10 Fault Management and HVDC System Protection 3000 ldcr (A) 2000 1000 0 Vdcr (V)

6 4 2 0

ldcr ldcr_ref × 105

150 αr (deg) 100 50 0 × 105 2 Vacr (V) 0 –2 Pr (W), Qr (VAr)

CC mode

× 108

5

Qr

0

Pr

–5 0.4

0.45

0.5

0.55

0.6

0.65 Time (s)

(a) Rectifier Variables 3000 ldci (A) 2000 1000 0 5 6 × 10 4 Vdci (V) 2 0

0.7

0.75

0.8

ldci_ref Commutation failure

VDC mode

0 –2

Pi (W), Qi (VAr)

0.9

ldci

150 VDC mode αi (deg) 100 CC mode 50 CEA mode 0 5 20% AC voltage drop 2 × 10 Vaci (V)

0.85

× 108

5 0 –5

Qi

Pi

0.4

0.45

0.5

(b) Inverter Variables

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

Time (s)

Figure 10.5 HVDC commutation failure recovery (after a 20% AC voltage drop for 50 ms at 0.4 s).

It should be recalled here that with current source systems (like line commutated converter HVDC) there is a large inductance on the DC side which prevents fast current change. Also, inductors store energy, and in the case of disturbances a current path must be provided to ensure the discharge of inductor energy. For these reasons, the fast converter bypass is normally the first protection step, which is achieved by firing simultaneously two valves on the same converter leg.

10.5 System Reconfiguration for Permanent Faults The HVDC controls and the temporary overrating of switches are adequately designed to deal with all transient faults. If the fault condition persists for a longer time, then isolation or reconfiguration is required. As shown in Figures 10.1 and 10.6, each HVDC pole can be isolated using pole CBs and filter CBs.

10.5 System Reconfiguration for Permanent Faults

DS

BPS

Pole CB

BPS - Bypass switch, NBS - Neutral Bus switch, MRTB - Metalic Return Transfer Breaker ERTB - Earth Return Transfer Breaker DS - Disconnector

BPS

NBS ERTB NBS MRTB BPS

Pole CB

BPS DS

Figure 10.6 Arrangement of DC circuit breakers for system protection and reconfiguration.

Figure 10.6 shows the arrangement of DC CBs, but not all of these breakers will be required on all HVDC links. The DC CBs employed for reconfiguration of a bipole HVDC have very low current or voltage ratings (depending on position) and have similar construction to AC CB (common SF6 AC CBs suffice in many cases). Figure 10.7 shows some practical DC CBs. The DC CB technology is further studied in Part III in Section 28.6. The functions of DC CBs are explained below: • The BPS is located across a bridge or pole and it is open in normal operation. In the case of valve or bridge faults it is necessary to trip the affected bridge and to provide a bypass path for the current. The rapid bypass is achieved by first firing two thyristors on the same converter leg, and this is followed by permanent bypass using a mechanical BPS after which the converter is tripped. If a BPS is installed at bridge level, it is possible to operate a pole on a single bridge, at half the pole voltage, in order to minimise the loss of power. The BPS enables the converter to be taken in and out of service without power interruption. • Neutral bus switches (NBSs) are closed and carry rated current in normal operation. In the case of pole faults the current may still flow through faulted-pole NBSs if this current path has lower resistance than the electrode path. In such a case protection will trip the NBS to redirect current to the electrode through a metallic return transfer breaker (MRTB). This enables isolation of the faulted pole and uninterrupted power flow through the healthy pole. • The MRTB is normally closed but carries no current. It will carry rated current if a pole fault occurs and the NBS is tripped. In most HVDC installations it is not permitted to operate the system with an earth return for a prolonged period of time. If both DC lines are available after a pole fault, then the return current is transferred to the

117

118

10 Fault Management and HVDC System Protection

Figure 10.7 DC circuit breakers on Yunnan–Guangdong HVDC. Source: Reproduced with permission of Siemens.

10.6 Overvoltage Protection

DC line on the faulted pole using the following sequence: NBS open, DS close, earth return transfer breaker close and MRTB open. • The earth return transfer breaker is open in normal operation and has the opposite function from the MRTB. It transfers the earth current to the DC line on the faulted pole.

10.6 Overvoltage Protection The HVDC systems include numerous semiconductor-based components which have high costs and limited voltage withstand abilities and therefore must be protected from overvoltages. The stakes are high with converter systems, and it is more expensive to provide large overvoltage margins compared with other electro-mechanical components. For this reason surge arresters (SAs) are extensively used with HVDC systems, at valve level, bridge level, pole level as transformer protection, as DC cable protection and in other places, as shown in Figure 10.8. SAs will be rated according to the insulation coordination strategies. They will always have a protective voltage level below the component rated voltage. Too low an SA protective level would lead to large leakage current, which can cause SA overheating. The purpose of SAs is to clip the voltage spike, but they are not normally designed to damp large energy. If an SA is operated the current will increase and then converter controls and other protection methods will be activated to manage the fault current. Figure 10.9 shows some practical HVDC SAs.

filters

DC auxiliary components

DC line

DC line (low voltage)

Figure 10.8 Location of surge arresters at an HVDC station.

119

120

10 Fault Management and HVDC System Protection

Figure 10.9 Surge arrester on Yunnan–Guangdong HVDC. Source: Reproduced with permission of Siemens.

121

11 LCC HVDC System Harmonics 11.1 Harmonic Performance Criteria The AC current injected by a line commutated converter has been assumed as an ideal sine at the fundamental frequency in previous chapters. This current, however, contains harmonics and the quality of converter power is normally evaluated in terms of the following performance parameters: harmonic factor (HF), total harmonic distortion (THD), and distortion factor (DF). The harmonic factor, is a measure of individual harmonic magnitude, and is defined as: V (11.1) HFn = n V1 where V 1 is the RMS value of the fundamental component and V n is the RMS value of the nth harmonic component. The THD is a measure of closeness between the actual waveform and its fundamental component, and it is defined as: √ √∞ ∑ 1 √ √ V2 (11.2) THD = V1 n=2 n When calculating the THD the largest harmonic is normally set to 50. The THD gives the total harmonic content, but it does not indicate the level of each harmonic component. If a common low-pass filter is used at the inverter AC terminals, the higher-order harmonics will be attenuated more effectively. Therefore, knowledge of both the frequency and the magnitude of each harmonic is important. The DF indicates the amount of harmonic distortion that remains in a particular waveform after the harmonics of that waveform have been subjected to a second-order attenuation. Thus, DF is a measure of effectiveness in reducing unwanted harmonics without having to specify the values of a second-order filter, and it is defined as: √ √ ∞ ( )2 ∑ Vn 1 √ √ (11.3) DF = V1 n=2 n2 The DF of an individual nth harmonic component is defined as: Vn DFn = V1 n2 High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

(11.4)

122

11 LCC HVDC System Harmonics

It is desirable to have as low a value as possible for all of the above harmonic performance indicators.

11.2 Harmonic Limits The harmonics in AC systems cause a range of problems and must be limited. Some common problems resulting from high harmonics include machine heating and pulsations, insulation stress, overloading of capacitor banks, and interference with electronic and telecommunications equipment. With high voltage direct current (HVDC) systems harmonics can also cause control and stability issues. There are also other issues like telephone line interference and audible noise, which have led to cost implications with some HVDC systems but are not examined in detail here. Table 11.1 shows the voltage harmonic limits according to the IEEE and Table 11.2 shows IEC limits. On the DC side of an HVDC system, there are no loads (customers) and the above limits do not apply. There are, however, two main criteria that influence the design magnitude of DC harmonics: • telecommunication interference; • DC cable insulation limits on harmonics. According to CIGRE brochure 219, for DC extruded cables, the maximum DC voltage distortion should be 3%. Note, however, that many thyristor HVDC systems use mass-impregnated DC cables which have better harmonic tolerance. Table 11.1 IEEE Standard 519 harmonic limits. Voltage at point of common coupling

Individual harmonic magnitude HF (%)

Total voltage distortion – THD (%)

69 kV and below

3.0

5.0

69–161 kV

1.5

2.5

161 kV and above

1.0

1.5

Table 11.2 IEC Standard 61000 3-6 harmonic limits. Odd harmonics

Harmonics multiples of 3

Harmonic voltage (%) Order

Even harmonics

Harmonic voltage (%)

Harmonic voltage (%)

MV

HV

Order

MV

HV

Order

MV

HV

5

5

2

3

4

2

2

1.8

1.4

7

4

2

9

1.2

1

4

1

0.8

11

3

1.5

15

0.3

0.3

6

0.5

0.4

13

2.5

1.5

21

0.2

0.2

8

0.5

0.4

21 < n < 45

0.2

0.2

MV, Medium voltage; HV, high voltage.

11.3 Thyristor Converter Harmonics

11.3 Thyristor Converter Harmonics A thyristor converter behaves as a current source on the AC side. At full power, the AC current for a six-pulse converter bridge, as shown in Figure 3.3 and connected through Y–Y transformer, can be expressed using Fourier series (neglecting commutation overlap) as: √ ] 3 [ 1 1 1 1 Ig = 2 Idc sin 𝜔t − sin 5𝜔t − sin 7𝜔t − sin 11𝜔t + sin 13𝜔t + … 𝜋 5 7 11 13 (11.5) which can also be expressed as: √ ∞ 3 ∑1 Ig = 2 Idc sin(n𝜔t), 𝜋 n n=1

n = 6k ± 1,

k = 1, 2, 3, …

(11.6)

It is concluded that all harmonics of the order 6k ± 1 are present on the AC side, where k is any integer. The magnitude of harmonics is inversely proportional to the harmonic order. The AC current generated by a converter with a Y–Δ transformer is: √ ] 3 [ 1 1 1 1 Ig = 2 Idc sin 𝜔t + sin 5𝜔t + sin 7𝜔t − sin 11𝜔t + sin 13𝜔t + … 𝜋 5 7 11 13 (11.7) Therefore, the Y–Δ transformer gives 180∘ phase shifted fifth and seventh harmonics and multiples. The HVDC systems usually use 12-pulse series connection that consists of one Y–Y and one Y–Δ converter. The current in a 12-pulse converter system is the sum of (11.5) and (11.7): √ ] 3 [ 1 1 1 1 Ig = 4 Idc sin 𝜔t − sin 11𝜔t + sin 13𝜔t − sin 23𝜔t + sin 25𝜔t + … 𝜋 11 13 23 25 (11.8) Therefore the 12-pulse system has 11th, 13th and all 12k ± 1 harmonics: √ ∞ 3 ∑1 Ig = 2 Idc sin(n𝜔t), n = 12k ± 1, k = 1, 2, 3, … 𝜋 n n=1

(11.9)

If a commutation overlap of angle 𝜇 is present, the current ‘squares’ are rounded and the harmonic magnitude is lower. The harmonic magnitude with overlap I nov becomes reduced compared with the case of no overlap I n the for nth harmonic: √ H 2 + K 2 − 2HK cos(2𝛼 + 𝜇) Inov = In cos 𝛼 − cos(𝛼 + 𝜇) H = (sin(n + 1)𝜇∕2)∕(n + 1) K = (sin(n − 1)𝜇∕2)∕(n − 1)

(11.10)

123

124

11 LCC HVDC System Harmonics

On the DC side a thyristor converter appears as a DC voltage source with the DC waveform shown in Figure 3.4. This voltage source will have 6k (k = 1, 2, …) voltage harmonics in the case of a six-pulse bridge. With 12-pulse systems only 12k (k = 1, 2, …) harmonics will be present. The above harmonics are called characteristic harmonics. They occur according to the theoretical study of ideal current/voltage waveforms. The non-characteristic harmonic (i.e. second, third, etc.) are not present in theoretical studies but may occur in practical HVDC systems. Some of the causes of non-characteristic harmonics are: • unbalanced AC system caused by small differences in the line impedances in three phases; • converter transformer asymmetry and phase difference in transformer ratios; • converter asymmetry, because of controller firing angle, or driver or thyristor asymmetry. AC grid unbalance is quite a common cause of non-characteristic harmonics. An unbalance on the AC grid will cause the thyristor converter to produce the following AC harmonics: n = kp ± 3,

k = 0, 1, 2, …

(11.11)

where p is the pulse number of the thyristor converter. The same unbalance will produce on the DC side: n = kp ± 2,

k = 0, 1, 2, …

(11.12)

In general an nth harmonic on the DC side will produce an n ± 1 harmonic on the AC side.

11.4 Harmonic Filters 11.4.1

Introduction

At each HVDC station there will be harmonic filters on the AC side and perhaps also on the DC side which are designed to reduce harmonic distortion to within the specified limits. The filters have capacitive reactance at fundamental frequency and they also help to supply the reactive power requirement from converters. Since the HVDC reactive power is variable (it is proportional to active power), the capacitors and/or filters will be arranged in switchable banks which are switched in steps as the HVDC power is varying. The filters are physically large, and together with the switchgear they can occupy over 50% of the HVDC station footprint. Most systems use shunt filters but some systems use a combination of shunt and series AC filters. In the case of capacitor commutated converter HVDC systems, HVDC receives full reactive power compensation from series capacitors and therefore shunt filters are small. Typically, AC-side tuned filters will be used for two to four lowest-order AC harmonics, like the 11th and 13th on 12-pulse systems, or the 23rd and 25th on 24-pulse terminals. Additionally, damped (high-pass) filters will be employed for higher-order

11.4 Harmonic Filters

harmonics. Figure 11.1 shows the possible filter arrangement for a 12-pulse HVDC terminal while Figure 11.2 shows a photograph of some practical AC filters at the HVDC terminal. An HVDC with overhead lines will commonly have a DC-side 12th or 24th filter. The DC cables have high capacitance and they naturally reduce harmonics.

Idc

AC system 3 phase Vs, fs

12th filter

Y Δ

α Y

Y

Reactive power compensation

High pass filter

13th filter

11th filter

Vg

Figure 11.1 HVDC station with harmonic filters.

Figure 11.2 AC filters at Moyle HVDC station (2001). Source: Reproduced with permission of Siemens.

125

126

11 LCC HVDC System Harmonics

11.4.2

Tuned Filters

The simplest single tuned filter is shown in Figure 11.3, where the converter is shown as a harmonic current source. The other commonly used filters are double- and triple-tuned. The filter in this figure consists of a series LC circuit and a resistance, which is typically just the parasitic resistance of the inductor. The equivalent impedance of this filter at a frequency 𝜔 is: V 1 Zf = f = Rf + j𝜔Lf + If j𝜔Cf ( ) 1 − 𝜔2 Lf Cf 1 Zf = Rf + j 𝜔Lf − (11.13) = Rf − j 𝜔Cf 𝜔Cf The characteristic frequency 𝜔f (where capacitive impedance equals inductive impedance) of this filter is: 1 𝜔f = √ LEC f

(11.14)

and the quality factor qf is defined as √ Lf

𝜔L Cf qf = f f = Rf Rf

(11.15)

Typical values for quality factor are in the range 50 < qf < 100. The band pass BP for the tuned filter is defined as: 1 𝜔 (11.16) BP = ± 2qf f Figure 11.4 shows the Bode plot for two different values of qf . It is seen that larger qf (lower Rf ) implies a better-tuned frequency characteristic which provides lower impedance for current harmonics. The filter impedance at characteristic frequency is: (11.17)

Zff = Rf

Therefore the magnitude of the harmonic voltage at frequency 𝜔f is directly proportional to Rf : (11.18)

Vgf = Iff Rf where I ff is the injected current at 𝜔f . The filter loss at 𝜔f frequency is: 2 Rf Pff = Iff

grid Zs

PCC

converter If

Ig

Rf Vs

Vg

(11.19)

Lf Cf filter

Ic

Figure 11.3 Tuned filter at HVDC terminal.

11.4 Harmonic Filters

102

Magnitude (dB)

qf = 10 101

qf = 150

100

10–1 100

200

300 400 500 600 700 1000

f (Hz)

2000

100 80 60

Phase (deg)

40 20 0 –20 –40

qf = 10

–60

qf = 150

–80 –100 100

200

300 400 500 600 700 1000

f (Hz)

2000

Figure 11.4 Bode plot for 11th harmonic tuned filter with two different values of qf .

It is desirable for the impedance at the characteristic frequency to be as low as possible in order to reduce the bus voltage harmonic distortion at this frequency. However, there are physical constraints related to parasitic resistances like inductor size and losses. Also, the filter parameters may change with the ageing of components, in which case the filter with higher qf becomes more detuned. With HVDC systems the filters also provide a reactive power supply at fundamental frequency. Considering (11.13), the impedance at 50 Hz (𝜔1 = 2𝜋50) for the tuned filter is given by: ( Zf1 = Rf + j 𝜔1 Lf −

1 𝜔1 Cf

) = Rf + jY f1

(11.20)

127

128

11 LCC HVDC System Harmonics

and the inverse is determined as R Y 1 = 2 f 2 −j 2 f 2 Rf + Yf1 Rf + Yf1 Zf1

(11.21)

Therefore the active Pf (filter losses) and reactive Qf filter power at 50 Hz are Pf1 = 3Vg1 2

Rf R2f

Qf1 = 3Vg1 2

(11.22)

+ Yf12 Yf

(11.23)

R2f + Yf12

where V g1 is the line-neutral fundamental voltage at the filter bus. 11.4.3

Damped Filters

Figure 11.5 shows the topology for a second-order damped filter. The other commonly used tuned filters are third-order and C-type filters. They are typically high-pass filters which are designed to eliminate all harmonics above the ones that are directly cancelled with tuned filters. As an example, if with 12-pulse HVDC tuned 11th and 13th filters are installed, then a high-pass filter will be designed for the 24th harmonic in order to damp the 23rd, 25th and all higher-order harmonics. The filter impedance at any frequency 𝜔 is: j𝜔Rf Lf 1 + Rf + j𝜔Lf j𝜔Cf Rf 𝜔2 L2f 𝜔Cf (𝜔R2f Lf − R2f + 𝜔2 L2f ) Zf = 2 +j Rf − 𝜔2 L2f R2f − 𝜔2 L2f Zf =

The characteristic frequency 𝜔f of this filter is: √ qf2 + 1 1 𝜔f = √ qf2 Lf Cf

(11.24)

(11.25)

and the quality factor is defined as qf =

Rf 𝜔 f Lf

(11.26)

The quality factor is typically low, 1 < qf < 10, in order to provide damping at wide range of frequencies. Figure 11.6 shows the Bode plot for a high-pass filter designed for the 24th harmonic. grid Zs

PCC Ig

Vs Vg Rf

converter

If Lf Cf filter

Ic

Figure 11.5 Second-order damped filter at HVDC terminals.

11.4 Harmonic Filters

103

Magnitude (dB)

102

qf = 1

qf = 3

101

100 100

200 300 400 500

1000

2000 3000

f (Hz)

100 80 60

Phase (deg)

40

qf = 3

20

qf = 1

0 –20 –40 –60 –80

–100 100

200 300 400 500

1000

2000 3000

f (Hz)

Figure 11.6 Bode plot for 24th harmonic high-pass filter with two different values of qf .

Example 11.1 A 500 MW, 250 kV, 2000 A, 12 pulse HVDC terminal employs 11th, 13th, and high-pass AC filters. The AC voltage level at point of common coupling is 220 kV. The tuned 11th filter has the following parameters: C f = 3.91 μF, Lf = 0.0214 H, Rf = 0.7 Ω. Figure 11.7 shows the circuit diagram. Neglecting the AC system impedance (ideally small at 50 Hz and ideally large at 550 Hz), determine: (1) (2) (3) (4) (5)

the qf factor for this filter; the reactive power supplied by this filter; the power loss in the filter considering only 50 and 550 Hz components; the voltage distortion at the 11th harmonic; the voltage distortion at the 11th harmonic assuming that filter capacitance becomes reduced by 10% because of ageing.

129

11 LCC HVDC System Harmonics

Terminal 1 AC system 1 3 phase Vsr, fr Psr,Qsr

11th filter

130

Rf Lf Cf

Terminal 2 Idcr

YΔ

DC line Vdcr

Isr n Isr_c r

Idci

n 220 kV r

α2

Vgr_c

Vgr

ΔY

Psi,Qsi

Vdci

αr

YY

AC system 2 3 phase Vsi, fi

YY

DC line

Vgi filers

Reactive power compensation

Figure 11.7 HVDC system in Example 11.1.

Solution (1) Quality factor √ qf =

√

Lf Cf

=

Rf

0.0214 3.91 × 10−6 = 105.6 0.7

(2) At 50 Hz the filter impedance is: ( Zf1 = 0.7 + j 2𝜋50 × 0.0214 −

1 2𝜋50 × 3.91 × 10−6

) = 0.7 − j806.7 Ω

Therefore 2 Qf1 = 3Vg1

Yf R2f + Yf12

=3

220, 0002 806.7 = 60 MVar 2 3 0.7 + 806.72

(3) At 50 Hz 2 Pf1 = 3Vg1

Rf R2f + Yf2

=3

220, 0002 0.7 = 52.066 kW 2 3 0.7 + 806.72

At the 11th harmonic, first the converter side AC voltage is needed: 𝜋 𝜋 Vg LL = Vdc √ = 250,000 = 95.82 kV √ B3 2 cos 𝛼 2 × 3 2 cos(15) Therefore the stepping ratio is: 220.0 = 2.296 95.8 The RMS fundamental AC current on the grid side, using (3.5), is: √ √ 6 B 6 2 Is1 = Idc = 2000 = 1358.4 A nr 𝜋 2.296 𝜋 nr =

The AC current at the 11th harmonic is: 1 I = 123.49 A Is11 = 11 s1

11.4 Harmonic Filters

The power loss at the 11th harmonic is: 2 Rf11 = 123.492 × 0.7 = 32.027 kW Pf11 = Is11

The total percentage loss is: Pf1 + Pf11 52.066 + 32.027 100 = 100 = 0.0168% Pdc 500,000

Ploss% =

(4) Voltage at the 11th harmonic: √ √ Vg11 ll = 3Ig11 Rf = 3123.49 × 0.7 = 149.73 V Vg11 ll 149.73 Vg11 ll% = = 100 = 0.0168% Vg1 ll 220,000 (5) The new filter impedance at the 11th harmonic: ( ) 1 Zf11 = 0.4 + j 2𝜋50 × 11 × 0.0214 − 2𝜋50 × 11 × 0.9 × 3.91 × 10−6 = 0.7 − j8.21 Ω Zf11 = |Zf11 | = 8.246 Ω Vg11

ll

Vg11

ll%

√ √ 3Is11 Zf11 = 3123.49 × 8.246 = 1.764 kV Vg11 ll 1764 = = 100 = 0.8017% Vg1 ll 220,000

=

Therefore there is significant increase in the 11th harmonic for a 10% change in capacitance.

Phase Locked Loop Va

AC voltage frame reference

Vb

PLL

θPLL

Vc

δr kl1/s

Idc ref

Pdc ref

180°

kp1

Vdcref

αr

linearise

DC current

0°

PI controller Idcr

Vdc

Fast Fourier Transformation

Sin(.) Vdcf

X kwf

δ3 δ4 δ5 δ6

Filter w ft

δ2 Switch firings 60° interval

Harmonic cancellation Supplementary control

Figure 11.8 HVDC supplementary control for DC harmonic elimination.

131

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11 LCC HVDC System Harmonics

11.5 Non-characteristic Harmonic Reduction Using HVDC Controls Some HVDC systems use special supplementary controls to reduce particular low-order non-characteristic harmonics. This potentially can be an effective and low-cost method but careful studies are required to avoid control instabilities. The scheme can be used with low-order DC-side harmonics that cause problems, like second-harmonic resonance. Figure 11.8 shows the HVDC (rectifier) control schematic with the supplementary control employed for eliminating harmonics at frequency 𝜔f . Since normal HVDC controls have low bandwidth, they are not capable of regulating harmonic voltages. A special oscillator at frequency 𝜔f is used and the magnitude of the injected oscillation is controlled in a feedback manner using fast Fourier transformation processing of the measured DC voltage. The method is used only at a single frequency 𝜔f since any other frequency would require different and carefully tuned gain k wf .

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Part I Line Commutated Converter HVDC

Bibliography HVDC Design and Operation ALSTOM Grid (2010). HVDC Connecting to the Future. ALSTOM France. CIGRE WG 14.05 (2003). On Voltage and Power Stability in AC/DC Systems. CIGRE brochure 222. CIGRE WG 14.07 (1992). Guide for Planning DC Links Terminating at AC Systems Locations Having Low Short Circuit Capacities. CIGRE brochure 68. CIGRE working group 14.03 (1994). A Summary of the Report on Survey of Controls and Control Performance in HVDC Schemes. CIGRE brochure 00. CIGRE working group 14.03 (1994). DC Side Harmonics and Filtering in HVDC Transmission Systems. CIGRE brochure 92. CIGRE working group 14.03 (1999). Guide to the Specification and Design Evaluation of AC Filters for HVDC Systems. CIGRE brochure 139. CIGRE working group B2.41 (2014). Guide to the Conversion of Existing AC Lines to DC Operation. CIGRE brochure 583. Kundur, P. (1994). Power System Stability and Control. McGraw Hill. Analytical Modelling of HVDC Systems Hammad, A.E. (1992). Analysis of second harmonic instability for the Chateauguay HVDC/SVC scheme. IEEE Transactions on Power Delivery 7 (1): 410–415. Jovcic, D. (2003). Phase locked loop system for FACTS. IEEE Transactions on Power Systems 18 (3): 1116–1124. Jovcic, D., Pahalawaththa, N., and Zavahir, M. (1999). Analytical modeling of HVDC–HVAC systems. IEEE Transactions on Power Delivery 14 (2): 506–511. Jovcic, D., Pahalawaththa, N., and Zavahir, M. (1999). Stability analysis of HVDC control loops. IEE Proceedings Generation, Transmission and Distribution 146 (2): 143–148. Jovcic, D., Pahalawaththa, N., and Zavahir, M. (2000). Investigation of the use of inverter control strategy instead of synchronous condensers at inverter side of HVDC system. IEEE Transactions on Power Delivery 15 (2): 704–709. High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

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Padiyar, K.R. (1985). Stability of converter control for multiterminal HVDC systems. IEEE Transactions on Power Apparatus and Systems 104 (3): 690–696. Szechman, M., Wess, T., and Thio, C.V. (1991). First Benchmark Model for HVDC Control Studies, 54–73. CIGRE WG 14.02 Electra No. 135. Zhang, Y. (2011). “Investigation of Reactive Power Control and Compensation for HVDC Systems” PhD Thesis, University of Manitoba.

HVDC Stability and Second Harmonic Instability Burton, R.S., Fuchshuber, C.F., Woodford, D.A., and Gole, A.M. (1996). Prediction of core saturation instability at an HVDC converter. IEEE Transactions on Power Delivery 11 (4): 1961–1969. Gole, A.M., Keri, A., Kwankpa, C. et al. (1997). Guidelines for modeling power electronics in electric power engineering applications. IEEE Transactions on Power Delivery 12 (1): 505–514. Hammad, A.E. (1992). Analysis of second harmonic instability for the Chateauguay HVDC/SVC scheme. IEEE Transactions on Power Delivery 7 (1): 410–415. Jovcic, D. (2001). Control of HVDC systems operating with long DC cables. In: Seventh International Conference on AC–DC Power Transmission (Conf. Publ. No. 485), 113–118. Osauskas, C. and Woo, A. (2003). Small-signal dynamic modeling of HVDC systems. IEEE Transactions on Power Delivery 18 (1): 220–225. Sucena-Paiva, J.P. and Freris, L.L. (1973). Stability of rectifiers with voltage-controlled oscillator firing systems. Proceedings of the Institution of Electrical Engineers 120 (6): 667–673. Thio, C.V., Davies, J.B., and Kent, K.L. (1996). Commutation failures in HVDC transmission systems. IEEE Transactions on Power Delivery 11 (2): 946–957. Woodford, D.A. (1996). Solving the ferroresonance problem when compensating a DC converter station with a series capacitor. IEEE Transactions on Power systems 11 (3): 1325–1331. Yacamini, R. and Oliveira, J.C. (1980). Instability in HVDC schemes at low-order integer harmonics. IEEE Proceedings on Power Apparatus and Systems 87 (3): 179–188.

Capacitor Commutated HVDC Sadek, K., Pereira, M., Brandt, D.P. et al. (1998). Capacitor commutated converter circuit configurations for DC transmission. IEEE Transactions on Power Delivery 13 (4): 1257–1264. HVDC with Weak AC Systems and Commutation Failure Jovcic, D., Pahalawaththa, N., and Zavahir, M. (2000). Investigation of the use of inverter control strategy instead of synchronous condensers at inverter terminal of an HVDC system. IEEE Transactions on Power Delivery 15 (2): 704–709. Nayak, O.B., Gole, A.M., Chapman, D.G., and Davies, J.B. (1994). Dynamic performance of static and synchronous compensators at an HVDC inverter bus in a very weak AC system. IEEE Transactions on Power Systems 9 (3): 1350–1358. Rahimi, E., Gole, A.M., Davies, J.B. et al. (2006). Commutation failure in single- and multi-infeed HVDC systems. In: The 8th IEE International Conference on AC and DC Power Transmission, ACDC 2006, 182–186.

Bibliography

Conversion of AC Lines to HVDC and UHVDC Huang, H. and Ramaswami, V. (2005). Design of UHVDC converter station. In: Transmission and Distribution Conference and Exhibition: Asia and Pacific, 1–6. IEEE/PES. Naidoo, P., Muftic, D., and Ijumba, N. (2005). Investigations into the upgrading of existing HVAC power transmission circuits for higher power transfers using HVDC technology. In: Power Engineering Society Inaugural Conference and Exposition in Africa, 139–142. IEEE. DC Cable Modelling and Modelling in State Space Beerten, J., D’Arco, S., and Suul, J.A. (2016). Frequency-dependent cable modelling for small-signal stability analysis of VSC-HVDC systems. IET Generation, Transmission and Distribution 10 (6): 1370–1381. Gustavsen, B. and Semlyen, A. (1999). Rational approximation of frequency domain responses by vector fitting. IEEE Transactions on Power Delivery 14 (3): 1052–1061.

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Part II HVDC with Voltage Source Converters

139

12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC 12.1 Application of Voltage Source Converters in HVDC The voltage source converter (VSC) systems are based on self-commutating switches (typically insulated gate bipolar transistor, IGBT, technology), which have a number of advantages compared with thyristors. The use of self-commutating devices allows the application of high-frequency (over 1 kHz) pulse width modulation (PWM) techniques, which have been in use in the industrial drives sector since the early 1990s. By the use of PWM, the VSC may synthesise a fully controlled AC voltage, which enables precise control of active and reactive powers. This voltage appears as a fundamental frequency sine with harmonics at the switching frequency and its multiples. The control is very rapid, and with appropriate feedback, the voltage source inverter may respond as a current source. Because of higher switching frequencies, harmonics are lower and therefore filtering requirements are reduced. At higher voltages, including high voltage direct current (HVDC), devices with turn-off capability have facilitated multilevel converters which demonstrate advantages over PWM in terms of losses and harmonics. The use of VSCs for DC power transmission (VSC transmission) was introduced with the 3 MW, ±10 kV demonstrator at Hellsjön, Sweden in 1997, and numerous projects have been installed with ratings up to 1 GW. Figure 12.1 shows the basic schematic of a two-level VSC HVDC. The main advantages of VSC converters, compared with line commutated converters (LCC) are summarised as: • Active and reactive power can be controlled independently. The VSC is capable of generating leading or lagging reactive power independently of the active power level. Each converter station can be used to provide voltage support to the local AC network while transmitting any level of active power, at no additional cost. • If there is no transmission of active power, both converter stations operate as two independent STATCOMs to regulate local AC network voltages. • The use of PWM with a switching frequency in the range of 1–2 kHz is sufficient to separate the fundamental voltage from the sidebands, and suppress the harmonic components around and beyond the switching frequency components. Harmonic filters are at higher frequencies and therefore have low size, losses, and costs. At voltages over 100 kV multilevel converters are most beneficial and harmonics are not needed. High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

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12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC Station 1 PCC AC CB

AC reactor

AC grid 1 Transformer AC filter

Station 2

VSC

VSC DC cable or overhead line

DC DC DC capacitors filters reactor

AC reactor

AC CB

PCC

AC Transformer grid 2 AC DC DC DC filter reactor filters capacitors

Figure 12.1 Symmetrical monopolar VSC HVDC transmission system based on two-level converters.

• Power flow can be reversed instantaneously (50–100 ms) without the need to reverse the DC voltage polarity (only DC current direction reverses). This implies that simpler extruded cross-linked polyethylene (XLPE) DC cables can be used. • Good response to AC faults. Since the VSC converter actively controls the AC voltage/current, the VSC HVDC contribution to the AC fault current is limited to rated current or controlled to lower levels. The converter can remain in operation to provide voltage support to the AC networks during and after the AC disturbance. • Black-start capability, which is the ability to start or restore power to a dead AC network (network without generation units). This feature eliminates the need for a start-up generator in applications where space is critical or expensive such as with offshore wind farms. • VSC HVDC can be configured to provide faster frequency or damping support to the AC networks through active power modulation. In general, VSC HVDC responds faster than LCC HVDC. • Connection to passive AC systems, also called grid forming function. The VSC converter can generate AC voltage using an internal independent oscillator. This facilitates transition from the grid mode to an intended or unintended islanded mode, as required in the development of smart grids. Some VSC HVDC are used to drive dead-loads (no active power generation). • It is more suitable for paralleling on the DC side (developing multiterminal HVDC and DC grids) because of constant DC voltage polarity and better control. • It facilitates modular development using basic constant-voltage cells. In particular, the latest modular multilevel converters (MMCs) use standard low voltage cells with capacitors. The main limitations and disadvantages of VSC technology are summarised as: • Improved control is achieved at the expense of increased losses in the power converter. Increased losses are the result of: ∘ application of high-frequency switching leading to increased switching loss; ∘ IGBT devices exhibiting significantly higher on-state voltage drop compared with thyristors of similar voltage ratings. For a given power level, this will lead to increased conduction loss. • Higher costs than LCC converters. VSC requires a larger number of semiconductors and in particular with modular systems the number of switches is much higher than with LCC. In general the unit cost of an IGBT is much higher than that of a comparable thyristor.

12.2 Comparison with LCC HVDC

• IGBT switches/modules have lower power capability than available thyristor packages, leading to increased power component count. The semiconductor footprint is larger than with thyristors. The largest IGBT voltage ratings are around 4–6 kV (current rating reduces with higher voltage). Modular IGBTs are available at around 2.4 kA, while press-pack IGBTs are available at 3 kA. • IGBT devices have much lower current overload capability than thyristors. Typically, they must be blocked at 2 p.u. current. • High dv/dt transitions may be present at the connecting points (both AC and DC). This can cause problems with dominantly capacitive cable systems and also electromagnetic interference. • DC faults are a serious issue since a VSC behaves like an uncontrolled diode bridge during a DC fault. Diode overrating is typically required and fault is cleared by AC CBs (circuit breakers). The VSC converter reconnection after AC CB tripping may take a long time. • The development of multiterminal DC and DC grids requires very fast DC CBs. • IGBTs naturally fail in open circuits. A cell failure in a short circuit is achieved in commercial units, but at the expense of special packaging, or using much more complex valve design compared with thyristors.

12.2 Comparison with LCC HVDC The LCC HVDC has been studied in Part I, and only the key characteristics are summarised in this section in order to provide comparison with VSC HVDC. The principal advantages of LCC HVDC are: • Thyristor devices are available in robust high-voltage (6–10 kV), high-current (4–5 kA) capacity single-wafer capsules. • Thyristors have excellent overcurrent capability. • Thyristors naturally fail in a short circuit, which is desirable for series strings in high-voltage valves. • Thyristors have lower on-state voltage drop, and the costs are lower than with IGBT. LCC converters require switches for one current direction while VSC converters have semiconductors for two current directions. • Line commutated HVDC systems have an established track record at transmission voltage and power levels. • Systems have resilience to DC side short circuit faults. They can operate well at low DC voltage and DC fault recovery is well controlled. DC faults do not affect the AC system. The notable shortcomings of LCC HVDC which have motivated the development of VSC are: • LCCs inject significant low-order harmonics which must be eliminated using large passive filter arrangements. The presence of these filters may lead to circulating harmonic currents and stability issues which must be mitigated by damping networks. Filters and damping networks may have to be designed specifically for each location and may not be optimal for all operating conditions.

141

142

12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC

• They require large reactive power compensation. This reactive power is supplied using passive filters and switched capacitors and reactors. The switched banks are required since the amount of reactive power needed varies with the active power magnitude and operating mode (inversion or rectification). As a result, the LCC HVDC station has larger footprint than the VSC HVDC station. • The power reversal necessitates the DC link voltage polarity to be reversed. This limits the range of DC cables that can be used (XLPE cables cannot be used if voltage reversal is needed). Also, the time required to reverse the power flow is limited to around 500 ms, which imposes operational constraints. • LCCs are inherently limited in their response time (limited to line frequency switching). The control response time is on the order of 100–200 ms. • There is a practical minimal power flow of around 10%. • It cannot connect to very weak AC networks (with a low short circuit ratio SCR < 2.0). • It suffers from commutation failure, which is caused by a 5–10% voltage drop on the inverter side. A commutation failure causes transient (0.5–1 s) interruption in power transfer. This can be partially mitigated with CCC (capacitor commutated converter) HVDC. • LCC HVDC provides AC system frequency stabilisation in many installations, but performance is limited because of reactive power issues. The AC voltage control is also implemented in some installations, but performance is very limited. • It is vulnerable to DC-side open circuit conditions. This is a very unlikely event and causes overvoltage, which can be limited by surge arresters. • Multiterminal topologies can be built but with serious performance and cost penalties. Generally, only three-terminal systems are accepted in practice. DC grids are very challenging.

12.3 HVDC Technology Landscape HVDC systems are currently implemented using both LCC and VSC technologies. VSC HVDC installations began around 2000, but despite the evident technological advantages, VSC HVDC did not completely replace LCC HVDC. Line commutated HVDC systems retain some advantages, in particular related to costs and ratings, but also importantly LCC represents a well-established technology with many years of experience. LCC HVDC provides a practical solution using robust devices and well proven circuits. At the highest power levels (over 2 GW) it is almost exclusively used. The DC systems with overhead lines are exposed to frequent DC faults, and because of good handling of DC faults, LCC converters are preferred in these applications. Also, LCC HVDC generally has lower costs, and therefore it is still preferred in applications where performance and station space are not critical. In large, long-distance overhead line applications in Asia and America, LCC HVDC is still the preferred choice. The vast majority of LCC HVDC systems employ standard thyristor bridge topology, but CCC HVDC is also on offer for some specific installations. Since 2000, almost all installed cable systems have used VSC HVDC technology. The development of new environmentally friendly cable technologies has been closely linked to the performance characteristics of VSC HVDC. In Europe, where shorter cable systems below 1 GW are demanded, the VSC HVDC has been preferred.

12.4 Overhead and Subsea/Underground VSC HVDC Transmission

VSC HVDC has evolved in several different technologies which have shown progressively improving performance, namely two level, three-level and MMC. Starting from 2010, MMC topology has become the dominant VSC technology for most manufacturers. MMC HVDC has brought significant advances in terms of lower losses and harmonics, and currently MMC HVDC losses are comparable with those of LCC HVDC. In 2023, the first major VSC HVDC with overhead lines will be implemented, which is facilitated by the use of full-bridge (FB) MMC technology. However, MMC has not completely replaced PWM-based VSC, and currently manufacturers are offering VSC HVDC of three different types: two-level VSC, half-bridge and FB MMC. Table 12.1 provides a detailed comparison between high-voltage DC transmission system technologies. The comparison focuses on the most important aspects, listed in the first column, such as control flexibility, fault ride-through capability, conversion losses, electromagnetic compatibility issues, and provision of auxiliary functionality such as voltage, frequency and damping support.

12.4 Overhead and Subsea/Underground VSC HVDC Transmission To transmit electrical energy using direct current over a distance, both cables and overhead transmission lines can be used. The choice is influenced by environmental constraints as well as an overall optimization that considers total capital cost, performance, losses, and transmission system reliability. There is also a small difference between underground and submarine DC cables. The cost of cables is considerably larger than that of overhead lines, perhaps an order of magnitude larger, but there are also other aspects of cable projects that may influence the choice: • Cables often have less impact on the environment than overhead transmission lines. • In recent years, it has become increasingly difficult to secure right of way for new overhead line corridors, or the permission process takes many years, and this has influenced decisions to use underground cables in some projects. • Since a VSC allows only one DC voltage polarity, the cable does not need to be designed for voltage polarity reversal. This allows the use of less expensive and simpler XLPE DC cables. • Cables are less likely to experience faults than overhead transmission lines. In the event of a cable fault, the outage will be permanent and repair time may be significant. • Since overhead transmission lines are always exposed to lightning strikes and pollution, faults are likely. Most line outages are transient, and transmission recommences once air insulation is restored. The current interruption and gradual DC voltage rise can be achieved with LCC HVDC and with FB MMC VSC. With half-bridge VSC HVDC even transient DC faults may require tripping of the whole DC system with significant power flow disturbance. If overhead line faults are permanent they are typically easier to locate and repair. • VSC HVDC converters have difficulties with DC faults and most of the existing links operate with DC cables. It is accepted that, if a cable fault occurs, DC system will be tripped.

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Table 12.1 Comparison between different HVDC technologies. Current source converter based LCC

CCC

VSC based Two-/three-level

MMC half-bridge

MMC full-bridge

Switching device

Thyristor

Thyristor

IGBT

IGBT

IGBT

Switching losses

Negligible

Negligible

High

Low

Low

On-state losses

Low

Low

Moderate

Moderate

Moderate, higher than with half-bridge

Station size

Large

Large but reactive power banks and their circuit breakers are lower

Significantly reduced (around 50% of LCC)

Significantly reduced (around 50% of LCC)

Significantly reduced but higher than with half-bridge

Active power control

Continuous with fast reversal but cannot operate within ±10%

Continuous with fast reversal but cannot operate within ±10%

Continuous From 0 to ±100%

Continuous From 0 to ±100%

Continuous From 0 to ±100%

Active power reversal

DC voltage polarity must be changed (0.5–1 s)

DC voltage polarity must be changed (0.5–1 s)

Instantaneous (0.1 s) and no change of DC voltage polarity

Instantaneous (0.1 s) and no change of DC voltage polarity

Instantaneous (0.1 s) Either DC voltage or current polarity

Independent control of active and reactive power

No

No

Yes

Yes

Yes

Reactive power demand

50–60%

20–40%, but additional series capacitors are required

No

No

No

Reactive power control

Limited (lagging VAr only) and discontinuous using switch shunt capacitors for leading VAr

Limited (lagging VAr only)

Continuous and inherent within the converter control at no additional cost

Continuous and inherent within the converter control at no additional cost

Continuous and inherent within the converter control at no additional cost

Power levels

Up to 6400 MW

Up to 6400 MW

Installed to 1200 MW Higher levels are possible

Installed to 1200 MW Higher levels are possible

Over 1 GW levels are possible

Controllability (response time)

Fast (0.1–0.2 s)

Fast (0.1–0.2 s)

Very fast (0.03–0.05 s)

Very fast (0.03–0.05 s)

Very fast (0.03–0.05 s)

AC filters

Large

Large

Small

No

No

DC filter

Might be required

Might be required

No (rarely used)

No (rarely used)

No (rarely used)

Converter transformer

Expensive with high insulation requirement to withstand harmonics and voltage stresses during power reversal

Expensive with high insulation requirement to withstand harmonics and voltage stresses during power reversal, but with reduced MVA rating

Expensive with high insulation requirement to withstand switching of large voltage steps with high frequency. Additional large AC inductor is needed

Standard AC transformer might be used. Additional large AC inductor is needed

Standard AC transformer might be used. Additional large AC inductor is needed

DC cable

Must withstand fast voltage polarity reversal during power reversal

Must withstand fast voltage polarity reversal during power reversal

Less expensive and light weight extruded cable

Less expensive and light weight extruded cable

Less expensive and light weight extruded cable

HVDC with overhead lines

Yes

Yes

Yes but DC CBs might be needed

Yes but DC CBs might be needed

Yes

Commutation failure

Present for AC disturbances (5–10%)

Present but significantly reduced

No

No

No

Applications with weak AC systems

Connection of strong systems (SCR > 3), connection of weak system is possible but at additional cost by using STATCOM or synchronous condenser

Connection of strong and weak systems with SCR ≥ 2

Very weak and network without generation can be connected

Very weak and network without generation can be connected

Very weak and network without generation can be connected

(Continued)

Table 12.1 (Continued) Current source converter based

VSC based

LCC

CCC

Two-/three-level

MMC half-bridge

MMC full-bridge

AC fault ride-through capability

Possible, undergoing commutation failure and 0.5–1 s recovery if inverter

Possible, undergoing commutation failure and recovery 0.5–1 s if inverter

Excellent (three-level has issues with asymmetrical faults)

Excellent

Excellent

DC fault ride-through capability

Excellent

Excellent

Difficult. AC CB tripping

Difficult. AC CB tripping

Excellent

Multiterminal configuration

Feasible but with performance limitation. three-terminal topologies are preferred

Feasible but with performance limitation. Three-terminal topologies are preferred

Extension to any number of terminals is feasible assuming single protection zone. DC side isolation is very difficult

Extension to any number of terminals is feasible assuming single protection zone. Fast DC CB are needed

Extension to any number of terminals is feasible. Mechanical DC CBs can be used

Redundancy at switch level

Yes

Yes

Yes

Yes

Yes

12.6 Monopolar and Bipolar VSC HVDC Systems

Manufacturers have traditionally been reluctant to offer VSC HVDC with overhead lines. The 300 MW, 350 kV, 2010 Caprivi VSC HVDC link is currently the only VSC HVDC with overhead DC lines. The challenge with VSC overhead transmission is to avoid tripping the whole HVDC system (by AC CBs) for transient DC line faults (lightning strikes) which might be frequent on some corridors. The DC arc on overhead lines will not clear until the circuit is interrupted, and this is only achieved using AC CBs with VSC converters. Even when AC CBs are tripped, the high-impedance DC circuits will continue to conduct DC fault current through converter anti-parallel-diodes. The Caprivi HVDC link has an additional DC-side breaker for managing DC faults. With the introduction of FB MMC topologies (and other new MMC concepts) the VSC HVDC will be in a much better position to operate with overhead lines. The Ultranet HVDC (installed in 2023) also employs overhead lines but FB MMC technology is adopted.

12.5 DC Cable Types with VSC HVDC The most common cable technologies have been discussed in Chapter 1, and include: • mass-impregnated cables (MI); • low-pressure oil-filled (LPOF) cables; and • XLPE cables. The MI and LPOF cables can also be used with VSC HVDC, but so far XLPE cables have mostly been used. XLPE cables are less expensive, their construction is simpler, they allow lower bending radius and they have a number of other installation/transport advantages when compared with MI or LPOF cables. The insulation material (extruded polyethylene), conductor screen and insulation shields are extruded and chemically cross-linked. Most XLPE DC cable installations are at voltages up to 320 kV, but currently XLPE cables are available at 525 kV. XLPE DC cable technology has been closely linked with the development of VSC HVDC. XLPE cables have influenced VSC technology and VSC technology has opened up a market for XLPE cables. The ongoing research and development aimed at increasing the rating of XLPE cables and reducing its cost may also make VSC transmission more attractive for a number of applications. The most recent developments (like P-laser) claim further reduction in manufacturing costs. Figure 12.2 shows a typical XLPE DC cable.

12.6 Monopolar and Bipolar VSC HVDC Systems All of the HVDC topologies, including monopolar and bipolar discussed with LCC HVDC in Section 1.4, can also be used with VSC transmission. However, most installed VSC HVDC systems are symmetrical monopoles. Symmetrical monopoles have positive and negative DC cables (as bipoles) but the system is controlled/operated as a single unit (as a monopole), as schematically shown in Figure 12.1. There are a number of reasons for using a symmetrical monopole (which is not used with LCC HVDC) with the early VSC HVDC. Most VSC HVDC are cable systems, and considering that XLPE cables have been available with limited voltage ratings (320 kV), only symmetrical configuration achieves required pole–pole DC voltage. Also, the power ratings and

147

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12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC

Figure 12.2 Polymeric insulated cable for HVDC. Source: Reproduced with permission of ABB.

voltage levels with installed VSC transmission have been relatively low to justify full bipolar topologies. The Caprivi overhead link is one of the few monopolar VSC HVDC in operation, and it is planned to become a bipole when the second pole is added in the future. The 78 MW, 150 kV, 2011 Valhall HVDC also employs monopolar topology. The Skagerrak 4 is a unique topology, since it is a monopolar VSC HVDC, which operates with another pole of LCC HVDC type (Skagerrak 3).

12.7 VSC HVDC Converter Topologies The VSC HVDC transmission system has been implemented using two-level VSCs, three-level VSCs, and multilevel VSCs. 12.7.1

HVDC with Two-level Voltage Source Converter

The two-level SPWM (sinusoidal pulse width modulation) topology was used in the first generation of VSC HVDC in the period 1997–2006, and Table 12.2 shows some example HVDC installations. It is also currently commercially available in addition to MMC HVDC but mainly for lower voltage/power ratings. Practically, the maximum switching frequency with two-level HVDC converters is around 1.5 kHz (27–33 frequency modulation ratio). Figure 12.3 shows a two-level VSC that uses self-commutated switching devices, mainly IGBTs. The capacitor C dc of the VSC must be sized to maintain a constant DC voltage. The size (footprint) of the two-level VSC HVDC terminal is around 50% of the size of the LCC HVDC station. The main characteristics of this technology are: • simple converter construction which requires a simple control strategy to guarantee stable operation over the entire operating range;

12.7 VSC HVDC Converter Topologies

Table 12.2 Examples of the VSC HVDC transmission systems based on the two-level converter.

Project

Rating

Terranora (Australia)

180 MW, V dc = ±80 kV,

Tjareborg (Denmark) Gotland (Sweden)

PWM strategy

Commissioning year

Applications

Distance

SPWM

Controlled asynchronous connection for trading

59 km

2000

8 MW, V dc = ±9 kV

SPWM

Wind power connection

4.3 km

2000

50 MW, V dc = ±80 kV

SPWM

Permission for underground cable

70 km

1999

Figure 12.3 One phase of a VSC HVDC station based on the two-level converter topology.

DC reactor

Valve with Series connected IGBTs 2Cdc

Vdc PCC

AC reactor 0 Cf

2Cdc

Rf

Lf

LC filter with damping

DC reactor

• lowest number of switches; • high switching losses and relatively high filtering requirements (requires relatively large AC filters with damping, which adds losses) – note that filters are still much smaller than with LCC HVDC; • high dv/dt because of large voltage difference at each switching, with a relatively high switching frequency and high common mode voltage – these impose high insulation requirements on the interfacing transformers, and also generate high electromagnetic interference; • poor DC fault ride-through capability – this represents a major obstacle to the development of multiterminal HVDC, especially in the absence of reliable and proven DC CBs.

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12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC

12.7.2

HVDC with Neutral Point Clamped Converter

As the second-generation VSC HVDC, the three-level diode clamped converter (also known as neutral point clamped (NPC) converter) was developed around 2000, with the following objectives: • to reduce effective switching frequency per device (consequently, lowering switching losses); and • to lower dv/dt, enabling the use of a transformer with reduced insulation requirements. It also enables low total harmonic distortion at the point of common coupling (achieves a further reduction in filter size). Figure 12.4 shows the one-phase leg of the neutral-point clamped converter, which halves the voltage stress and the effective switching frequency per device compared with the two-level converter in Figure 12.3. As an additional benefit, the converter station loss is reduced significantly. However, with the NPC converter it is difficult to meet some grid code transient requirements, such as that the converter must remain in operation during AC grid faults in order to provide reactive power to support the grid. This is an issue since the NPC converter DC capacitor voltage balancing (at 1/2V dc ) is challenging under asymmetrical AC faults, such as a single-phase open circuit fault,

DC reactor Series connected IGBTs

½Vdc

2Cdc

AC reactor

0

PCC

½Vdc 2Cdc

AC filter

DC reactor

Figure 12.4 One phase of the VSC HVDC station based on an NPC converter.

12.7 VSC HVDC Converter Topologies

Table 12.3 Examples of the VSC HVDC transmission systems based on the NPC converter. PWM strategy

Applications

Distance

330 MW, V dc = ±150 kV, f s = 1.26 kHz

SPWM

Grid re-enforcement

40 km

2002

Murray link (Australia)

220 MW, V dc = ±150 kV, f s = 1.35 kHz

SPWM

Grid re-enforcement

180 km

2002

Eagle Pass (USA)

36MVA, V dc = ±16 kV, f s = 1.26 kHz

SPWM

Power trading and power quality

Back-to-back

2000

Project

Rating

Cross Sound (USA) cable

Commissioning year

single-phase-to-ground and line-to-line faults. Consequently, HVDC manufacturers eventually abandoned the NPC converters in favour of improved two-level converters. Table 12.3 lists NPC VSC HVDC transmission installations. 12.7.3

MMC VSC HVDC Transmission Systems

This converter concept exploits the benefits of the multilevel structure and PWM. The filtering requirements are greatly reduced because of the generation of high-quality AC voltage (AC filters might not be required). The AC voltage is shaped in small steps, by switching one cell (module) per arm at a time, which results in only 1–2 kV voltage increments, although some topologies use cells of higher voltages. The use of a large number of levels with small voltage steps, results in low dv/dt seen by the grid and reduced voltage stress on the insulation of the interfacing transformers. This allows the use of standard transformers without the need to withstand the DC link voltage or harmonic currents. Furthermore, the effective switching frequency per device is low, resulting in lower switching losses and lower harmonics. On the downside, modular converters require a larger number of switches, at least twice the number compared with two-level VSC. As with all VSC converters, MMCs can independently control active and reactive AC power since they readily control AC voltage magnitude, phase, and frequency. The most attractive feature is the modularity, since the same basic modules are used in all projects, and only the number of modules differs. The cells are independently controlled; however, they also need to be controlled jointly in a very rapid manner in order to maintain balanced voltage on all cells. This demand for simultaneous balancing of a large number of cells using a central signal processor is a significant new technical challenge. Currently there are two main configurations, namely half-bridge and FB modular converters. Figure 12.5 shows one phase of an n + 1 level modular converter, consisting of n cells in each arm. This converter relies on the cell capacitors to create a multilevel voltage waveform at the converter terminal. Each cell has low voltage which is of the order of a single switch rating or it is built up of a small number of series-connected switches. Typically, hundreds of cells are required to build a single valve for DC transmission requirements. As the number of levels increases, the quality of AC voltage waveform becomes better

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12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC

DC cable or overhead line half bridge

Ccell

1 2 ½Vdc

full bridge

Ccell n Larm

PCC

Larm n+1

n+2

½Vdc

DC cable or overhead line

2n

Figure 12.5 One phase of an n + 1 level MMC HVDC converter.

and the harmonic content becomes lower. The DC link capacitors are not required, since individual cells have capacitors. However, some small DC capacitors (around few microfarad) might be installed in a typical symmetrical monopole configuration in order to create a ground reference for the AC voltages. Since this topology benefits from the redundant combination of module connections for each required AC level, the balancing capability is better than with NPC converters. The MMC performs better than the NPC converter during unbalanced operation and symmetrical/asymmetrical AC faults, which reduces the risk of device failure and high currents. The ability of the modular converter to ride through different types of AC faults makes it suitable for applications subjected to stringent grid code requirements. If there is an issue with one phase on the AC system, the remaining two phases of the converter will operate largely unaffected and potentially at high per-phase power. The absence of DC capacitors also reduces issues with DC faults, considering that MMC cell capacitors will not discharge into the DC fault and this leads to faster post-fault recovery. With two-thirds-level VSC, post-DC fault recovery requires a period of DC capacitor charging. The sizing of the cell capacitors requires careful consideration. They dominate the volume requirement for the cells, but they are required to store sufficient energy to support the converter DC voltage during transient events. Otherwise the system may fail to meet transient requirements. It will be shown in the modelling section that the cell capacitors behave as series-connected AC-side components.

12.7 VSC HVDC Converter Topologies

Table 12.4 Examples of the VSC HVDC transmission systems based on half-bridge MMC converter. PWM strategy Applications

Project

Rating

Trans Bay (USA)

400 MW, MMC V dc = ±200 kV

Valhall, Norway

78 MW, V dc = 150 kV

East–West Interconnector, UK–Ireland

Distance

Commissioning year

Network upgrade using cable supply

85 km

2010

Power supply to offshore platform

292 km

2011

MMC 500 MW, V dc = ±200 kV

Interconnecting two grids

186 km +75 km

2013

INELFE (Spain–France)

2 × 1000 MW, MMC V dc = ±320 kV

Interconnector between two AC systems

65 km

2014

SylWin1 (Germany)

864 MW, MMC V dc = ±320 kV

Offshore wind farm 204 km connection

2014

Mackinac, USA

200 MW, V dc = ±71 kV

Power flow control Back-to-back and voltage stability

2014

MMC NordBalt, 700 MW, Sweden–Lithuania V dc = ±300 kV

Interconnecting grids

400 km

2016

MMC 1400 MW, V dc = ±525 kV

Interconnecting markets

730 km

2021

North Sea link, UK–Norway

MMC

MMC

The first commercial MMC-based HVDC transmission system project is the 85 km, 400 MW, ±200 kV (±170 MVAr STATCOM functionality) Trans Bay cable project, commissioned in the USA in 2010, and some other example projects are listed in Table 12.4. Figure 12.6 shows the valve hall of the 500 kV, 700 MW Skagerrak 4 MMC HVDC. This is the only installed bipolar HVDC which operates one pole using MMC technology (Skagerrak 4) and the other pole using line commutated technology (Skagerrak 3). 12.7.4

MMC HVDC Based on FB Topology

MMC HVDC with FB converters is commercially available, and the first installation is planned for 2023. The FB MMC HVDC converter has similar overall structure to a half-bridge MMC, but each cell uses four switches in full H connection, as shown in Figure 12.5. The FB cell facilitates either positive or negative voltage at the cell terminals while a half-bridge gives only positive voltage. Therefore, FB gives more control flexibility, although at the expense of twice the number of switches. Note that at least three-quarters (but not all) of the cells are required to assume FB topology in order to achieve system-level benefits. There are some important operational advantages of FB over half-bridge MMC: • Full bridge topology can actively control and interrupt the DC fault current. It need not be blocked for DC faults. If it is blocked the FB converter becomes an open circuit for DC faults. • It can operate with reduced DC voltage. This implies that FB MMC can supply full reactive power to the AC system during DC fault conditions.

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12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC

Figure 12.6 Valve hall of 500 kV Skagerrak 4 MMC HVDC. Source: Reproduced with permission of ABB.

• The overrating of antiparallel diodes or cell bypass thyristors (which is required with half-bridge cells) may not be needed, since high fault current cannot occur. The cell design is further discussed in Section 12.8. • DC voltage polarity reversal may be possible, depending on the number of FB cells. This is very important to rapidly extinguish the DC fault current path (it can deionise and extinguish arc on the overhead DC lines as with LCC HVDC in Figure 10.2). The post-fault DC voltage ramp-up can be controlled. • It is possible to provide higher (typically by up to 20–30%) AC voltage for the same DC voltage using overmodulation, which is feasible only with FB topology. This implies that for a given cable DC voltage and IGBT current limitation, FB topology can transfer more power, at the expense of an increased number of cells. The cost of FB MMC cells is expected to be somewhat higher than that of half-bridge MMC cells; however, most other HVDC terminal components will remain similar, and estimates show that the total FB MMC HVDC terminal cost may be expected to be in the range 1.3–1.4 p.u. compared with a similar half-bridge MMC terminal. The first commercial installation of FB MMC HVDC is the ULTRANET project in Germany and the technical details are given in Table 12.5.

Table 12.5 Examples of the VSC HVDC transmission systems based on FB MMC converter.

Project

Rating

PWM strategy Applications

ULTRANET (Germany)

2000 MW, FB MMC V dc = ±380 kV

Distance

Power trading 340 km, DC between regions Overhead line

Commissioning year

2023

12.8 VSC HVDC Station Components

12.8 VSC HVDC Station Components The basic structure of the VSC HVDC system station (terminal) is shown in Figure 12.1. The function and design of the major power components will be summarised in the following sections. 12.8.1

AC CB

The AC CB is employed to connect and disconnect the VSC HVDC system during normal and fault conditions. There are no special design requirements compared with normal AC CBs used in power systems. During a DC fault, the VSC converter cannot interrupt the fault current, since free-wheeling diodes inside the VSC converter will uncontrollably feed the fault from the AC system. Therefore the AC CB is tripped to disconnect the HVDC terminal to prevent feeding of the fault from the AC side. In the case of a temporary DC fault, power transmission can be resumed after a normal start-up sequence of the HVDC system. This can be achieved in the timeframe of few seconds. 12.8.2

VSC Converter Transformer

A three-phase 50/60 Hz converter-grade transformer with tap-changer is used; however, with latest MMC HVDC standard transformers can be employed. The converter-side voltage (filter bus voltage) is commonly controlled by the tap changer to achieve the maximum active and reactive power from the VSC, both consumed and generated. The tap changer can be located on any side though. The transformer sometimes has a tertiary winding which feeds the station auxiliary power system, and if delta connected it suppresses any core triplen fluxes. With the use of the AC filter and the VSC PWM, the current in the transformer windings contains minimal harmonics and is not exposed to any DC voltage. The converter transformer can provide the following functions: • It provides a coupling reactance between the VSC and the AC system, which also reduces fault currents and can decrease size of the AC filter. • It matches the voltage between the AC system and the VSC converter which in turn is determined by the DC voltage. This results in optimum utilisation of the switch ratings and DC cable insulation. • It provides galvanic isolation, enabling optimised grounding of the DC link. • It prevents the flow of zero sequence current between the AC system and VSC. During the transformer design, the specific transformer requirements include: • • • •

the fundamental current stresses; saturation characteristics of the transformer magnetic field; low- and medium-frequency harmonic stresses; dielectric stresses caused by the normal/transient operating voltage especially with PWM VSC, and harmonics.

The converter transformer constitutes a sizeable portion of the terminal costs. Manufacturers have published multiple studies demonstrating possible HVDC implementation without transformers; however, all HVDC projects so far use transformers.

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12 VSC HVDC Applications and Topologies, Performance and Cost Comparison with LCC HVDC

12.8.3

VSC Converter AC Harmonic Filters

AC filters for two-thirds-level VSC HVDC converters have lower ratings than those for LCC HVDC converters and are not required to provide reactive power compensation. Contrary to filtering with LCC HVDC, VSC filters are permanently connected to the converter bus (they are not switched with power loading). A low-pass LC-filter is typically used to suppress high-frequency harmonic components and avoid interaction with the fundamental frequency component. MMC HVDC may not require any AC filters. 12.8.4

DC Capacitors

The DC capacitor is the energy storage element in VSC. It provides the VSC with the stiff DC voltage between switching instants, which is an essential presumption with all VSC topologies. With two-thirds-level VSC there is a single DC capacitor on DC terminals, while with MMC VSC DC capacitors are distributed per cells. The primary functions of the DC capacitor are: • To provide a low-inductance path for switch turn-off current. Because of the stray inductance, the turn-off commutating current results in transient voltage stresses on the switching devices. These stresses can be minimised by reducing the length of the connection between the DC link capacitor and the switching devices. • To provide temporary energy storage between the switching instants, stabilising high-frequency dynamics, which allows the VSC closed loop control to adjust the control signals in lower frequencies. • To reduce DC voltage harmonic ripple. HVDC capacitors commonly use a dry, self-healing, metallised film design, which has advantages over oil-filled technologies. Dry capacitor design is safer and offers high capacity and low inductance, in non-corrosion, no-radiation plastic housing. • To decrease the harmonic coupling between different VSC substations connected to the same DC bus. The design requirements for the DC capacitor include: • continuous operating DC voltage; • the limits of DC voltage ripple under transient conditions, such as faults to the AC system; • harmonic currents passed to the DC side; and • peak discharge current for DC faults. A requirement for small voltage ripple implies a large capacitor. On the other hand, a small capacitor has advantages considering the control and dynamics of the converter, which results in fast active power control. Selecting the size of the DC capacitor is a trade-off between voltage ripple, lifetime, costs, and rapid control of the DC voltage. Based on the ripple specification, a lower limit can be established for the capacitor value: Cdc >

SVSC 2𝜔Vdc ΔVdc

(12.1)

where C dc is DC capacitance, SVSC is the converter MVA rating, V dc is rated DC voltage, 𝜔 is the electrical frequency and ΔV dc is the allowed voltage ripple (peak–peak). DC cable manufacturers typically specify DC voltage ripple of around 3–10% but other

12.8 VSC HVDC Station Components

limits may also apply. Based on the control speed requirements it is possible to set the upper limit: Cdc
0

ia < 0

S1 or D4

D1

D4

S4 or D1

The switching signals for phase a of the inverter are shown in Figure 15.5. The load current and modulation waveform of phase a are defined as: ia = I sin(𝜔t − 𝜑i ) m = M sin 𝜔t

(15.4)

where m is the control signal, and 𝜙I is the load angle. Note that the AC voltage will have the same angle as the modulating signal. Observing Figure 15.5, the duty cycle of switch S1 is defined by d1 = 1∕2[1 + M sin 𝜔t] Therefore, the average current of S1 switch is: 𝜋+𝜑

𝜋+𝜑

i i 1 1 I d1 ia d𝜔t = sin(𝜔t − 𝜑i )[1 + M sin 𝜔t]d𝜔t 2𝜋 ∫𝜑i 2𝜋 ∫𝜑i 2 I IS1av = [4 + 𝜋M cos 𝜑i ] 8𝜋 The RMS current of S1 switch: √ √ 𝜋+𝜑i 1 I2 2 d1 ia d𝜔 = [3𝜋 + 8M cos 𝜑i ] IS1 = 2𝜋 ∫𝜑i 24𝜋

IS1av =

(15.5) (15.6)

(15.7)

The average current of D1 diode: 2𝜋+𝜑i

ID1av =

1 2𝜋 ∫𝜋+𝜑i

d1 ia d𝜔t =

I [4 − 𝜋M cos 𝜑i ] 8𝜋

The RMS current of the D1 diode: √ √ 2𝜋+𝜑i 1 I2 2 d1 ia d𝜔t = [3𝜋 − 8M cos 𝜑i ] ID1 = 2𝜋 ∫𝜋+𝜑i 24𝜋

(15.8)

(15.9)

Considering that S1 and S4 switches operate in a complementary manner, the average and RMS S4 switch currents are: 2𝜋+𝜑

i 1 I (1 − d1 )ia d𝜔t = − [4 + 𝜋M cos 𝜑i ] IS4av = 2𝜋 ∫𝜋+𝜑i 8𝜋 √ √ 𝜋 1 I2 2 (1 − d1 )ia d𝜔 = [3𝜋 + 8M cos 𝜑i ] IS4 = 2𝜋 ∫𝜑i 24𝜋

(15.10) (15.11)

while the average and RMS currents of D4 diode are: ID4av = −ID1av I2D4 = I2D1

(15.12)

199

200

15 Two-level PWM VSC Converters

The negative sign in the average current indicates the current direction and is not considered when calculating power loss. It will be noticed that diodes D1 and D4 carry the same current and similarly for switches S1 and S4 , since they supply same phase. Therefore using (15.6)–(15.9) the total conduction losses for one device (diode and insulated gate bipolar transistor, IGBT) of the three-phase inverter can be estimated as: VD0 I V I r I2 [4 − 𝜋M cos 𝜑i ] + FD [3𝜋 − 8M cos 𝜑i ] + T0 [4 + 𝜋M cos 𝜑i ] 8𝜋 24𝜋 8𝜋 rFT I 2 + (15.13) [3𝜋 + 8M cos 𝜑i ] 24𝜋 The diode is considered as an ideal switch at turn-on, since it turns on rapidly at zero voltage. The turn-on switching energy of the diode is therefore neglected. Therefore the total switching losses for one switching device of the three-phase inverter is: Pc1 =

PswT = fs (Eon PsD = fs Erec

test

test

+ Eoff

test )

Vdc IC Vdctest ICtest

Vdc IC Vdctest ICtest

(15.14) (15.15)

Example 15.1 A 500 A, 300 kV, SPWM VCS HVDC converter with switching frequency of 1050 Hz employs 6.5 kV, 750 A IGBTs and 100 devices are used in each valve. The blocking voltage across each IGBT is 3 kV. The IGBT and freewheeling diode characteristics are shown in Figures 13.4, 13.6, and 13.7. Assume that the modulation index is 0.9, and the AC current angle is zero. Neglecting turn-on loss of the freewheeling diode, calculate total losses in this converter. Solution (1) Conduction losses For the IGBT From the switch figures, V T0 = 2 V, rFT = (3.7 − 3.2)/250 = 2 mΩ For the freewheeling diode From the diode figures, V D0 = 1.5 V, rFD = (3 − 2.4)/250 = 2.4 mΩ Total conduction loss (for all six valves): { VD0 I r I2 [4 − 𝜋M cos 𝜑i ] + FD [3𝜋 − 8M cos 𝜑i ] Pc = 6 × n × 8𝜋 24𝜋 } 2 VT0 I rFT I + [4 + 𝜋M cos 𝜑i ] + [3𝜋 + 8M cos 𝜑i ] 8𝜋 24𝜋 { 1.5 × 500 0.0024 × 5002 Pc = 6 × 100 × [4 − 𝜋 × 0.9 × 1] + [3𝜋 − 8 × 0.9 × 1] 8𝜋 24𝜋 } 2 × 500 0.002 × 5002 + [4 + 𝜋 × 0.9 × 1] + [3𝜋 + 8 × 0.9 × 1] 8𝜋 24𝜋 Pc = 6 × 100 × [34.974 + 24.068 + 271.654 + 110.246] = 264.6kW (2) Switching losses For the IGBT: From the above figures, Eon_test = 4000 mJ/pulse, Eoff_test = 2800 mJ/pulse.

15.7 Harmonics with PWM

The switch current is normally taken as average current. I 500 [4 + 𝜋M cos 𝜑i ] = [4 + 𝜋M cos 𝜑i ] = 136A 8𝜋 8𝜋 V IC PswT = 6nf s (Eon test + Eoff test ) DC VDCtest ICtest 3000 136 PswT = 6 × 100 × 1050(4 + 2.8) = 971kW 3600 500 For the diode: From the above figures, Erec_test = 2400 mJ/pulse IC =

VDC IC VDCtest ICtest 3000 136 PsD = 600 × 1050 × 2.4 = 342 kW 3600 500 Total switching losses = 1313 kW Total losses = 1577.6 kW PsD = 6nf s Erec

test

15.7 Harmonics with PWM VSCs will generate harmonics on both the AC and DC sides because of the switching actions of the converter. For VSC HVDC integration, the amplitude of the harmonics entering the AC network and the DC line should be limited according to the harmonics standards. Different methods are used to reduce the harmonics to required limits such as: • • • •

PWM techniques; multipulse techniques; multilevel techniques; harmonic filters.

In general, the harmonic spectrum of the AC inverter voltage is affected by the modulation technique used. In the case of six-step modulation, the harmonic spectrum can be obtained using the Fourier analysis. The situation will be different in the case of PWM modulation. The non-periodic nature of a PWM switched waveform makes determination of harmonic components difficult. The waveform can be described as a two-variable function that is periodic across both the carrier and the sine reference waveforms. Figure 15.7 shows the SPWM VSC control signals (the triangular carrier signal and the sinusoidal reference voltages), and also the AC voltage of phase a with respect to the midpoint of the DC link capacitor. In this example the frequency of the carrier is nine times the fundamental AC frequency (f m = 9). The switching angles 𝛼 0 , 𝛼 1 , 𝛼 2 , 𝛼 M and 𝜋 are shown in the figure, which are used by the controller to send the firing signals to the IGBT switches. There are 2f m + 1 switching times per cycle. The amplitudes of the harmonics of the AC waveform are given by: ) ( 2fm ∑ 2Vdc k (15.16) Vn = (−1) cos n𝛼k 1+ n𝜋 k=1

201

202

15 Two-level PWM VSC Converters

1 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 α0

α1 α2

α3

αM

π

Figure 15.7 SPWM VSC modulation and AC voltage, assuming frequency modulation ratio of fm = 9.

If the triangular carrier signal frequency is an odd integer multiple of the fundamental frequency, the waveform does not contain even-order harmonics. In a three-phase bridge circuit, all the triple n harmonics, i.e. third, ninth … are eliminated in the line voltages, provided that the AC system voltages are balanced and symmetrical. Also, if the triangular carrier signal frequency is a multiple of 3, the harmonics of the order of the triangular carrier frequency are cancelled in the line- and phase-to-floating neutral voltages. The harmonics produced from the switching inverter AC voltage can be classified as: • low-frequency harmonics (baseband harmonics); • switching frequency harmonics (carrier harmonics); and • high-frequency harmonics (sideband harmonics). Table 15.2 shows the order of the dominant harmonics, and their magnitude in percentages relative to fundamental, for the line-to-line voltage of a three-phase Table 15.2 Magnitude of harmonics on line-line voltage in per cent relative to fundamental for a three-phase SPWM converter. Modulation index, M Harmonic order, n

fm ±2 fm ±4 2fm ±1

0.2

0.4

0.6

0.8

8

15

22

28

1

32

0

0

0

1

2

95

82

62

39

18 3

2fm ±5

0

0

0

2

3fm ±2

22

35

34

22

6

3fm ±4

0

3

8

13

16

Mag (% of Fundamental)

15.8 Comparison of PWM Modulation Techniques

1 0.8 0.6 0.4 0.2 0

0

500

1000

1500

2000

2500

3000

3500

4000

Frequency (Hz)

Mag (% of Fundamental)

(a)

1.5

1

0.5

0

0

500

1000

1500 2000 2500 Frequency (Hz)

3000

3500

4000

(b)

Figure 15.8 Spectra analysis: (a) phase-to-floating neutral voltage spectrum; and (b) line voltage spectrum, assuming modulation ratio of 21 (f s = f m = 1050 Hz).

SPWM converter. It can be seen that harmonic magnitude depends on the modulation index. It is assumed that the frequency ratio is a multiple of 3 and that it is large (at least 9). The AC phase-to-floating neutral and line voltage spectra for SPWM VSC converters are shown in Figure 15.8, for the test system which has carrier frequency of 1050 Hz (21 times fundamental frequency). It can be shown that the THD of phase-to-floating neutral voltage is 68%, while the THD of line-to-line voltage is 99%.

15.8 Comparison of PWM Modulation Techniques The harmonic performance indicators are presented in Part I in Section 11.1, and include magnitude of fundamental, THD and distortion factor (DF). The three different PWM modulating signals – SPWM, THI, DBPWM and SVM – are compared for a three-phase converter at a switching frequency of 450 Hz using the triangular carrier signal. Figure 15.9a shows the fundamental converter phase voltage at different modulation indices for SPWM, THI, DBPWM and SVM. THI, DBPWM and SVM give the highest fundamental component. Figure 15.9b shows the THD of the inverter AC phase

203

Fundamental phase voltage (p.u.)

15 Two-level PWM VSC Converters

0.7 SPWM SVM, THI, DB

0.6 0.5 0.4 0.3 0.2 0.1 0

0.2

0.4 0.6 0.8 Modulation index

1

(a) 400

9

SPWM SVM, THI, DB

350

DF for phase voltage %

THD for phase voltage %

204

300 250 200 150 100

SPWM SVM THI DB

8 7 6 5

50 0

0.2

0.4 0.6 0.8 Modulation index (b)

1

4

0.2

0.4 0.6 0.8 Modulation index

1

(c)

Figure 15.9 Performance comparison for different modulation techniques: (a) fundamental phase voltage; (b) THD for the phase voltage; and (c) DF for the phase voltage.

voltage at different modulation indices. SPWM gives a higher THD compared with the other modulation techniques. The DF for inverter phase voltage at different modulation indices is shown in Figure 15.9c. THI gives the lowest DF at higher modulation indices (which are most commonly used).

205

16 Multilevel VSC Converters in HVDC Applications 16.1 Introduction Nowadays, multilevel converters are considered to be the overall preferable topology at high voltages, and have drawn considerable research/development in the high voltage direct current (HVDC) professional community. To obtain high-quality AC voltage or current with a two-level converter requires high switching frequencies (1–2 kHz). Such high frequency, combined with high voltages in HVDC applications, causes significant switching losses, device/valve voltage rating constraints, and high electromagnetic interference. Multilevel converters use an array of modules to build the required AC voltage level from a number of individual DC power supplies, as shown in Figure 16.1. The DC voltage sources are typically formed using capacitors and a charge balancing scheme is used to keep the capacitor voltages constant. A two-level inverter generates an AC phase voltage with either of the two voltages ( 1/2V dc or − 1/2V dc ), as shown in Figure 16.1a. The three-level inverter generates three voltage levels ( 1/2V dc , − 1/2V dc and 0), as shown in Figure 16.1b, while the five-level inverter generates five voltage levels, as shown in Figure 16.1c. As may be appreciated from this figure, as the number of levels increases, the AC voltage appears closer to the sinusoidal waveform and the total harmonic distortion (THD) reduces. The most utilised multilevel topologies in a wide range of power electronics applications are: • • • •

diode clamped converter; flying capacitor converter; H-bridge cascade converter; and modular multilevel converter (MMC).

Only a diode clamped three-level converter and MMC have been used in HVDC converters. The H-bridge cascade converter has been utilised with other transmission system converters, like STATCOM (Static Synchronous Compensator) for reactive power control applications only. The main purpose of multilevel circuits is to generate a high-voltage waveform using low-voltage basic modules. Typically, series-connected modules are switched sequentially, producing an AC voltage pattern that contains defined discrete steps.

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

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16 Multilevel VSC Converters in HVDC Applications

C1 1/4Vdc C1

½Vdc

C1

0 C2

C2

½Vdc 0

½Vdc

Va0

C2

½Vdc

C3

Va0

C4 0.6

0.6

0.6

0.4

0.4

0.4

0.2

0.2

0.2

0

0

0

–0.2

–0.2

–0.2

–0.4

–0.4

–0.4

0

0.02 (a)

0.04

0

0.02 (b)

0.04

0

c 0 1/4Vdc

1/4Vdc

Va0

1/4Vdc

0.02 (c)

0.04

Figure 16.1 One phase leg of a voltage-source converter with: (a) two levels; (b) three levels; and (c) five levels.

The attractive features of multilevel converters are: • Low THD distortion and lower dv/dt seen by the grid compared with conventional two-level converters at the same effective switching frequency. This implies reduced footprint because of reduced filtering. • The blocking voltage of each module/switch is clamped to the cell capacitor voltage level. This also reduces switching losses. • Smaller common mode voltage, thus reducing insulation stresses. In addition, by using sophisticated modulation methods, common mode voltage can be eliminated. • Modularity and ability to scale converters to high voltage and power levels. • Inherent reliability. If a multilevel converter cell fails, the desired output voltage can still be produced because of module redundancy. Multilevel converter disadvantages involve: • Control becomes complex with the increased number of levels. • Multiple DC sources are required, which are usually provided by capacitors. • Balancing the capacitor voltage is a challenge, because of the requirement for very fast simultaneous feedback control of large number of cells.

16.2 Modulation Techniques for Multilevel Converters

• Conduction losses increase with an increase in the number of switches. • Typically, twice as many (or more) switches are required as for two-level converters. As well as costs, this also implies increased valve-hall footprint. • The current stresses for switching devices are different because of their different conduction duty cycle. In HVDC applications, multilevel converters have inherent advantages since an HVDC valve always consists of many series-connected switches. Instead of firing simultaneously a string of series switches, MMC technology allows AC voltage to be built in steps using individually controlled cells.

16.2 Modulation Techniques for Multilevel Converters All modulation schemes aim to create a train of pulses, which have the same fundamental voltage-second average as a target reference waveform at any instant. The major difficulty with these pulse trains is that they also contain unwanted harmonic components, which should be minimised. Hence, for any pulse width modulation (PWM) scheme, a primary objective is to calculate the duty cycles for the converter switches that create the desired low-frequency target voltage or current output. The secondary objective is to determine the most effective way of arranging the switching processes to minimise unwanted harmonic distortion, switching losses, etc. The modulation methods with multilevel converters include multipulse PWM and fundamental frequency (single pulse per module per half cycle), as shown in Figure 16.2. The common two multilevel PWM techniques are multilevel carrier-based and space vector PWM, which are extensions of conventional two-level PWM strategies, discussed earlier in Section 15.2. With MMCs in high-voltage applications, however, the fundamental frequency switching (a module switches once per cycle) has become attractive because of the low switching frequency per cell, which reduces switching losses. Staircase (fundamental frequency) multilevel modulation methods can be classified as selective harmonic elimination (SHE) and nearest level modulation (NLM), as shown in Figure 16.2. In SHE methods, the switching angles for all modules are computed offline, to eliminate

Modulation Techniques

Fundamental Frequency Modulation

High Switching PWM

Space Vector (SVM)

Multicarrier SPWM

Nearest Level Modulation

Figure 16.2 Multilevel converter modulation techniques.

Selective Harmonic Elimination (SHE)

207

208

16 Multilevel VSC Converters in HVDC Applications

harmonics at each value of modulation index and stored in lookup tables, which are then interpolated according to the operating condition. This requires a large memory, and with a high number of cells this method is not practical. The NLM approximates the desired AC voltage to the closest available voltage level of the converter. Considering that there is large number of modules with converters in HVDC systems, the number of available voltage levels becomes large, and NLM approximates the sine waveform very well. The computation is not complex since at each sampling instant the controller makes only YES/NO decisions if another module should be switched.

16.3 Neutral Point Clamped Multilevel Converter Since the 1980s, three-level NPC (neutral point clamped) or diode-clamped PWM converters have comprised very practical and widely adopted multilevel topology in drives and other industries. They were implemented in the second-generation voltage source converter (VSC) HVDC in the period 2002–2011, as shown in Table 12.3. Figure 16.3 shows a three-level diode clamped converter. The DC bus voltage is split into three voltage levels by two series-connected capacitors, C 1 and C 2 . The connection point between the two capacitors is defined as the zero voltage point (label 0). The AC

Sa1 C1

½Vdc

Db1

Sb1

Da1

Da5

Db5

Dc5

Sb2

Da2

Sa2

Dc1

Sc1

Dc2

Sc2

Db2

0 Vdc

a Sa3 ½Vdc

C2

b Da3

Va0

Da6 Sa4

Sb3

c Db3

Vb0

Sb4

Dc3

Sc4

Db4

ia

Dc4

ib

ic Vbc

Vab Van

Vbn

n

Figure 16.3 Three-level diode clamped converter.

Vc0

Dc6

Db6 Da4

Sc3

Vcn

Va0

200 0

–200

0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.01

0.02

0.03

0.04

0.05

0.06

Vab

200 0

–200

200 Van

Phase voltage (kV)

Line Voltage (kV)

Phase to zero (kV)

16.3 Neutral Point Clamped Multilevel Converter

0

–200

Time (s)

Figure 16.4 The pole, line-to-line and line-to-load neutral voltages of phase ‘a’ for a three-level diode-clamped multilevel converter at 1.35 kHz switching frequency.

voltage V a0 has three states/levels: 0, 1/2V dc , and − 1/2V dc . If leg a is considered as an example, for voltage level 1/2V dc , switches Sa1 and Sa2 are turned on; for 0 switches Sa2 and Sa3 are turned on; and for a − 1/2V dc level, Sa3 and Sa4 are turned on. The components that distinguish this circuit from a conventional two-level converter are clamping diodes Da5 and Da6 . They provide AC voltage connection to zero potential, which is not available in two-level converters. Another purpose of these two diodes is to clamp specific switch voltages to half the DC bus voltage. For example, when Sa1 and Sa2 turn on, V a0 = 1/2V dc ; and diode Da6 balances the voltage sharing between Sa3 and Sa4 with Sa3 blocking the voltage across C 2 and Sa4 blocking the voltage across C 1 . A three-level diode-clamped converter is particularly attractive since only these diodes (Da5 and Da6 ) are required as extra switches over a two-level converter, while the quality of AC voltage improves substantially. Figure 16.4 shows the phase-to-zero voltage, line-to-line and line-to-load neutral voltages for a three-level diode-clamped converter. For a general (n + 1)-level diode clamped multilevel converter, n storage capacitors are required; the voltage stress across each switching device is clamped to V dc /n (one capacitor voltage), n consecutive switching devices in each leg are turned on, and the blocking voltage of each clamping diode is dependent on its position (k) in the structure according to: V diode = (k/n)V dc where 1 ≤ k ≤ n − 1. Some practical difficulties with the basic diode clamped multilevel topology can be summarised as: • It requires high-speed clamping diodes that must be able to carry the full load current and are subjected to severe reverse recovery stresses.

209

210

16 Multilevel VSC Converters in HVDC Applications

• If the number of levels is more than three, the clamping diodes are subjected to different voltage stresses. Therefore, series connection of diodes is required. This complicates the design and raises reliability and cost concerns. • Maintaining the charge balance of the DC capacitors with more than three levels needs careful attention for some operating conditions. Although, a three-level NPC converter was used successfully with some HVDC projects, this topology was not used at higher numbers of levels because of the above issues.

16.4 Half Bridge MMC 16.4.1

Operating Principles of Half-bridge MMC

MMC is an attractive alternative to conventional diode-clamped multilevel converters in medium/high-voltage applications. HVDC experience is demonstrating that this topology provides the most cost-effective approach to constructing a multilevel DC/AC converter with a very high number of levels and high voltage levels. Figure 16.5 illustrates one phase (leg) of a three-level MMC, which is selected for simplicity. Each half-bridge (HB) cell (module) consists of two insulated gate bipolar transistor (IGBT) packs (IGBT plus freewheeling diode) and a capacitor. The two switches are operated exactly like one leg of a two-level HB converter. When one of the switches is fired ON the other switch will be OFF and vice versa. The operation of an HB cell is shown in Table 16.1. There are three cell states: ON (cell inserted, represented by state 1) and OFF (cell bypassed, represented by state 0); and also a cell can be blocked, while a cell can operate under two different current directions. The third column shows the current flow when the cell is blocked (both switches are OFF but the converter is still online). This case is important in some operating conditions, for example, (a) cell passive charging (positive cell current) or (b) converter blocked under a DC fault (negative cell current). The capacitor voltage is kept constant at V cell on all cells. The cell voltage is either V 0 = V cell , or V 0 = 0, depending on switch states and current direction. There are two groups of switches: main switches Sa1 , Sa2 , Sa3 and Sa4 ; and auxiliary switches Sxa1 , Sxa2 , Sxa3 , and Sxa4 . There are four cells per phase and therefore four complementary switch pairs per phase (Sa1 , Sxa1 ), (Sa2 , Sxa2 ), (Sa3 , Sxa3 ), and (Sa4 , Sxa4 ), such that Sai + Sxai = 1, where i = 1–4, and 1 represents the ON-state while 0 represents the OFF-state of the switch. At any time two cells will be ON in each leg, and voltage of each capacitor should be maintained at V cell = 1/2V dc . In each instant four switches will be in the ON-state, two from the main switches and the remaining two from the auxiliary switches. The voltage stress on each switch is limited to the capacitor voltage V cell . If the supply midpoint (0 in Figure 16.5) is the AC voltage reference, then the three-level waveform of phase a voltage can be synthesised as follows: For voltage level V a0 = 1/2V dc , turn on all the upper main switches (Sa1 and Sa2 ) and all lower auxiliary switches (Sxa3 , and Sxa4 ).

Table 16.1 Operation of a HB cell. Cell ON state (symbol 1) Sx = 1 (ON), S = 0 (OFF)

Cell OFF state (symbol 0) Sx = 0 (OFF), S = 1 (ON)

Cell blocked Sx = 0 (OFF), S = 0 (OFF)

Positive current

Vcell

Sx

S

V0

Vcell

Vo = Vcell

Sx

S

V0

Vcell

Sx

S

V0

Vo = Vcell

Vo = 0

Negative current

Vcell

Sx

S

Vo = Vcell

V0

Vcell

Sx

S

Vo = 0

V0

Vcell

Sx

S

Vo = 0

V0

212

16 Multilevel VSC Converters in HVDC Applications

Figure 16.5 Phase a of three-level HB modular converter.

Dxa1 Sxa1 Ccell

Sa1

Da1

Dxa2 ½Vdc

Sxa2 Ccell

Sa2

Da2

Larm iga

0

a

Larm Dxa3 ½Vdc

Sxa3 Ccell

Sa3

Da3

Va0

Dxa4 Sxa4 Ccell

Sa4

Da4

For voltage level V a0 = 0, there are four different switching combinations: • turn on Sa1 , Sa3 , Sxa2 , and Sxa4 ; • turn on Sa2 , Sa3 , Sxa1 , and Sxa4 ; • turn on Sa2 , Sa4 , Sxa1 , and Sxa3 ; • turn on Sa1 , Sa4 , Sxa2 , and Sxa3 . For voltage level V a0 = − 1/2 V dc , turn on all upper auxiliary switches (Sx1 , and Sx2 ) and all lower main switches (Sa3 , and Sa4 ). In a general case of (n + 1)-level MMC, the voltage across each capacitor and switching device is limited to V dc /n. At any time n cells will be ON in each leg. By controlling the number of cells from the upper and lower arms in the ON state, it is possible to control the magnitude of the phase voltage. The total number of capacitors required is 6n (2n per phase) and the number of switches (IGBT plus freewheeling diode) is 4n, which is twice the number required for a diode clamped multilevel converter. Figure 16.6 shows photograph of an HB MMC cell. 16.4.2

Capacitor Voltage Balancing

MMC cell voltages will deviate rapidly under normal operation because of the unequal conduction intervals for each cell. Active balancing is required at each switching instant,

16.4 Half Bridge MMC

Figure 16.6 Half-bridge MMC cell. Source: Reproduced with permission of Siemens.

to charge or discharge particular cells in order that the capacitor voltage always converges towards the desired steady-state value. The arm current should also be measured, since the sign of the capacitor voltage gradient depends on the current direction. This balancing technique must be embedded at the fastest control level, within the modulator, to facilitate the selection of the correct switching combinations that will lead to balanced cell voltages. If a modulation controller requires x cells of an n-cell arm to be switched ON at a particular instant, then the balancing controller will determine which particular cells are switched ON. There are several known methods to achieve capacitor balancing, and one possible method is discussed below, which is based on switching ON a cell with the highest (or lowest) voltage at each switching instant. The case of a three-level modular converter is analysed first. There is an opportunity for DC voltage balancing only when the AC phase is attached to the zero voltage level. The zero voltage level can be synthesised by any of the following four states: 1010/0101, 0110/1001, 0101/1010, and 1001/0110 (1010 stands for Sx1 = 1, S1 = 0, Sx2 = 1, S2 = 0). Consider the switching state (1010 for the upper arm, and 0101 for the lower arm) as an example and assume the current direction in Figure 16.5 as positive. For ia > 0 the upper capacitor C 2 charges and lower capacitor C 4 discharges, while upper capacitor C 2 discharges and lower capacitor C 4 charges for ia < 0. Table 16.2 summarises all switching states and their effect on the individual capacitor’s voltage. Based on this table, the capacitor voltage balancing method for a three-level converter is readily developed. A generalised balancing method for an arm of an (n + 1)-level converter can be similarly derived. At each sampling instant (instant of switching): • determine all available cells for switching ON or switching OFF; • rank the available cells according to their voltages and identify the cells with maximum and minimum voltages;

213

214

16 Multilevel VSC Converters in HVDC Applications

Table 16.2 Redundant switching states effect on capacitor voltages for a three-level modular converter. Load current Switching states for the upper arm

Direction

Path

Effect on capacitors Voltage

1010

ia > 0

Sa1 Dxa2 and Sxa4 Da3

C 2 ↑ and C 4 ↓

ia < 0

Sxa2 Da1 and Sa3 Dxa4

C 4 ↑ and C 2 ↓

ia > 0

Sa2 Dxa1 and Sxa4 Da3

C 1 ↑ and C 4 ↓

ia < 0

Sxa2 Da1 and Sa3 Dxa4

C 4 ↑ and C 1 ↓

ia > 0

Sa2 Dxa1 and Sxa3 Da4

C 1 ↑ and C 3 ↓

ia < 0

Sxa1 Da2 and Sa4 Dxa3

C 3 ↑ and C 1 ↓

ia > 0

Sa1 Dxa2 and Sxa3 Da4

C 2 ↑ and C 3 ↓

ia < 0

Sxa2 Da1 and Sa4 Dxa3

C 3 ↑ and C 2 ↓

0110 0101 1001

↓represents discharging state and ↑ represents charging state.

• at the next request for switching ON of an additional cell, if the current is positive, switch ON the cell with the lowest voltage; • if the current is negative, switch ON the cell with the lowest voltage. The above method is efficient since only one cell is switched at any instant; however, it may not provide adequate cell ripple suppression in case of converters with a large number of cells. Some converters with high cell number use a balancing algorithm where all of the capacitor voltages are measured and ranked (comparing each capacitor voltage with the voltage of the others) at each switching instant. Depending on the particular algorithm, a number of cells are re-arranged (switched ON or OFF) according to their voltage magnitudes in order to optimise switching losses and maintain satisfactory cell voltage ripple. Some new algorithms use adaptive methods where magnitude of current determines how many cells should be ‘rotated’ at each instant. Such method aims to minimise number of cells that need to change state at each switching instant in order to reduce losses. Figure 16.7 illustrates voltages across 10 capacitors on one arm of an 11-level HB 400 kV MMC. The voltage balancing controller maintains cell voltage to 400 kV/10 (around 40 kV). It is seen that the cell voltage ripple is low, at only few per cent. 16.4.3

MMC Cell Capacitance

The cell capacitor design is very important, as the capacitor in MMC is carrying the load current and represents the storage element for the converter instead of the DC-link capacitors. There is always a trade-off between the cell voltage ripple requirements and capacitor size. The cell capacitor is typically selected to enable the cell ripple voltage to be kept within a range of below 10%. In practical converters, the capacitor size is commonly determined using the energy-to-power ratio Es (J V−1 A−1 ), which is defined in (12.3). With MMC converters the energy-to-power ratio should be in the range of Es = 30–40 kJ MVA−1 (where MVA

16.4 Half Bridge MMC

42

Vcell (kV)

41 40 39 38 37 1.6

1.61

1.62

1.63 Time (s)

1.64

1.65

1.66

1.62

1.63 Time (s)

1.64

1.65

1.66

10

nc

8 upper arm

6

lower arm

4 2 0 1.6

1.61

Figure 16.7 Capacitor voltage balancing for an 11-level HB MMC. Top graph: voltages across 10 upper arm capacitors (n = 10). Lower graph: number of on-state cells in upper and lower arms.

refers to the total converter rating). The cell capacitance can be calculated following a similar derivation used for two-level VSC in (12.5), as: Ccell =

2SMMC Es 2 NMMC Vcell

(16.1)

where, SMMC is the apparent power of the converter (MVA), and N MMC is the total number of cells per converter (N MMC = 2np where p is the number of phases and n is the number of cells in each arm). The total instantaneous arm capacitance is the series connection of cell capacitances where the number of series capacitors depends on the control modulation index 0 < nc < n. When the maximum number of cells is ON, nc = n, the arm capacitance is given by (equals to leg capacitance): Carm = 16.4.4

Ccell n

(16.2)

MMC Arm Inductance

The arm inductance Larm is designed considering the following three criteria: (1) magnitude of the circulating current second harmonic, which is analysed in depth in the Chapter 19 on MMC modelling – although Larm significantly affects I diff , all modern MMC converters use active circulating current suppression control, which completely eliminates the second harmonic even with small arm inductance;

215

16 Multilevel VSC Converters in HVDC Applications

0.06 Lres2 - resonance at second harmonic Lres4 - resonance at fourth harmonic 0.05 Carm = 24 uf for Vdc = 640 kV, Vcell = 1.6 kV, Ecell = 30 kJ/MVA Carm = 97 uf for Vdc = 320 kV, Vcell = 1.6 kV, Ecell = 30 kJ/MVA 0.04 Larm (H)

216

Lr

es

0.03

2

(M

=1

)

Lr

es

0.02

2

(M

=0

.1)

0.01

Lre

Lre

s4

0 20

s4 (M = 1) (M = 0.1)

30

40

50

60 Carm (mF)

70

80

90

100

Figure 16.8 Arm inductance value which causes resonance at second and fourth harmonic.

(2) resonance with the arm capacitance; (3) current derivative in the converter arms for DC faults. Considering Kirchhoff’s voltage law for the MMC leg circuit, it is possible to determine value of arm inductance Larm_res that will cause resonance with the arm capacitance C arm at the h harmonic under a modulation index magnitude of M, with a converter operating at frequency 𝜔: Larm

res

=

2(h2 − 1) + M2 h2 Carm 𝜔2 8h2 (h2 − 1) 1

(16.3)

It is highly desirable to avoid resonances at even integer harmonics since these harmonics are naturally excited inside an MMC. Of most concern are the lower-order harmonics, i.e. second and fourth. Figure 16.8 shows the inductance value which causes resonance at the second and fourth harmonics for a range of arm capacitances, and considering two extreme modulation index values. The arm capacitances for two typical DC voltage values are also indicated. For a given arm capacitance, the arm inductance should be selected above the second harmonic resonance curve. This condition gives common values for Larm in HVDC MMC converters in the range 30–100 mH. The critical value for the arm inductor, considering the current derivative in the switches during DC faults, is given by the following formula: Larm

crit

=

Vdc (dIdc ∕dt)cr

(16.4)

The critical current derivative (dI dc /dt)cr for diodes and IGBTs is in the range of 100–1000 A μs−1 . When replaced in (16.4) the minimal value for arm inductance of

16.4 Half Bridge MMC

Figure 16.9 Arm inductors at Trans Bay MMC HVDC station. Source: Reproduced with permission of Siemens.

below the order of millihenries is calculated, which is a less demanding criterion than the resonance condition in (16.3). The practical rule is to use arm inductance of 0.1–0.15 p.u., relative to the converter rating. Together with the transformer leakage reactance 0.05–0.15 p.u., the total series reactance is in the range of 0.2 p.u. Figure 16.9 shows a set of practical MMC HVDC arm inductors. Example 16.1 Consider a 1000 MVA, 640 kV, 401 level MMC HVDC converter. Determine: (1) cell capacitor value; (2) arm capacitance; (3) arm inductance. Solution (1) Number of modules per arm is 400. Therefore cell voltage is: Vcell = 640∕400 = 1.6kV Total number of cells in the converter N = 400 × 6 = 2400. Assuming Es = 30 kJ MVA−1 , 2SEs 2 × 1000 × 30,000 = Ccell = 2 2400 × 16002 NV cell Ccell = 9.76mF ≈ 10mF (2) Arm capacitance is: C 0.1F = 24.4 μF Carm = cell = nc 400

217

218

16 Multilevel VSC Converters in HVDC Applications

(3) The critical arm inductance for resonance at second harmonic (h = 2, M = 1) is Larm_res = 43 mH. Therefore the suggested arm inductance is Larm = 50–60 mH. 16.4.5

MMC with Fundamental Frequency Modulation

This control method is also called square wave control (or staircase modulation), and it is characterised by a single switching of each module per cycle. However, it should be noted that, because of possible current sign changes and depending on the voltage balancing algorithm, a module may actually be switched a few times per cycle. By connecting a sufficient number of modules and using the proper selection of conducting intervals, a nearly sinusoidal output voltage waveform can be synthesised. Figure 16.10 shows a nine-level phase-to-zero voltage waveform and the main switches (S1 –S16 ) conducting periods assuming a typical nine-level MMC circuit. The firing angles 𝛼 1 –𝛼 4 can be calculated according to the adopted modulation method, which is commonly either SHE or NLC (nearest level control) as discussed in Figure 16.2. If SHE is employed, then the goal is to eliminate the 5th, 7th, and 11th harmonics by developing a set of equations for voltage magnitude and then using an iterative method such as the Newton–Raphson method to evaluate the angles for each operating point. With a high number of voltage levels, the complexity involved makes this method impractical, and unnecessary. The NLM method is considerably simpler to implement since it compares a desired reference sine waveform with the available staircase waveform. When the two signal intersect, the controller sends a request to switch in (or out) one cell. Figure 16.11 shows NLM for a single phase of the test nine-level converter, where the crossings between the reference sine and the available converter staircase voltage are used to determine the switching instant for the next module. Since the number of modules is very high in practical HVDC converters, the NLM has proven to be a very attractive modulation technique. Staircase modulation methods are suitable with a high number of voltage levels because the high module number achieves good AC voltage quality, equivalent to using high switching frequency. As an example, a stair wave-controlled 401 level converter has the equivalent of 800 × 50 Hz = 40 kHz switches per cycle and it gives better AC waveform than a two-level converter operating at 40 kHz. Furthermore, in MMC each semiconductor is switching only once (or a few times) per cycle, implying a reduction in the switching frequency and the switching losses. Figure 16.12 shows line-to-zero, line-to-line, and line-to-load neutral voltages for the same nine-level MMC. With the increased number of levels the AC waveforms become closer to ideal sine, with lower THD as shown in Figure 16.13 for a 101-level MMC. Table 16.3 compares THD of phase-0, line and phase voltages for 3-, 9-, 21-, and 101-level MMCs. 16.4.6

MMC with PWM Modulation

Another MMC modulation approach is to adopt PWM modulation with individual modules. This method is also used with some commercial MMC HVDC systems and the topology is known as a cascaded two-level converter. Typically the number of modules is lower than with NLC method, but each module has a higher voltage rating. Each module is switched multiple times per cycle. In the initial projects, each cell is switched

16.4 Half Bridge MMC Vao ½Vdc

α4 α3 α2 α1 π/2

3π/2

–½Vdc S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16

Figure 16.10 The phase 0 voltage of phase ‘a’ for a nine-level modular multilevel converter.

at around 150 Hz, and since for highest DC voltages typically 38 modules are used per arm, the effective switching frequency per leg will be 11.4 kHz. This indicates that the dynamic response of such a converter is much better than two-level converter, while the effective switching frequency is similar to square wave NLC controlled topologies. With this topology, each module is the same HB converter; nevertheless, because of smaller number of modules, each module has a higher voltage and therefore the valve is a string of multiple (typically around 8–10) series-connected IGBTs. All switches in a module switch simultaneously as in two-level valves. Consequently the challenge of voltage sharing exists in this topology but it is less severe compared with the two-level

219

16 Multilevel VSC Converters in HVDC Applications Vao ½Vdc

π/2

3π/2

–½Vdc

Figure 16.11 A typical AC reference and actual converter AC voltage of a nine-level converter, with NLC.

Vao (V)

5000

0

–5000

0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.01

0.02

0.03

0.04

0.05

0.06

Vab (V)

5000 0 –5000

5000 Van (V)

220

0

–5000

Time (s)

Figure 16.12 The phase-to-zero, line-to-line, and line-to-load neutral voltages of phase ‘a’ for a nine-level HB modular multilevel converter.

converter case. On the positive side, cell voltage balancing will be simpler, and the total capacitance and converter footprint will be lower than with NLC MMC. Example 16.2 Consider a 1000 MVA, 640 kV, HB MMC VSC HVDC converter. (1) If a square wave control is used and the cell voltage is 2 kV, determine the number of cells, number of switches, and the effective switching frequency per arm.

Vao (kV)

16.4 Half Bridge MMC

200 0 –200 0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.01

0.02

0.03

0.04

0.05

0.06

0

0.01

0.02

0.03

0.04

0.05

0.06

Vab (kV)

500 0

Van (kV)

–500

200 0 –200

Time (s)

Figure 16.13 The phase-to-zero, line-to-line, and line-to-load neutral voltages of phase ‘a’ for a 101-level HB modular multilevel converter.

Table 16.3 THD of AC voltages for MMC of different levels. Three-level

Nine-level

21-level

101-level

Phase-0 voltage

55.44%

14.05%

5.66%

1.44%

Line voltage

31.30%

7.70%

3.20%

1.16%

Phase voltage

30.77%

7.55%

3.17%

1.06%

(2) Assume that a PWM control is used, and there are 38 cells per arm. If each cell is fired at 165 Hz and the operating switch voltage is 2 kV, determine the number of switches in a cell, the total number of the switches, and effective switching frequency per leg. Solution (1) The number of cells per arm is 640/2 = 320. Since a cell will have two switches the total number of switches per arm is 640. The number of cells per leg is 1280. Since the square wave control is used, the frequency per cell is 50 Hz. The effective switching frequency per arm is f eff = 2 × 320 × 50 = 32 kHz. (2) The cell voltage is 640/38 = 16.8 kV. The number of switches per cell = 2 × 16.8/2 = 16.8 ≈ 17. Total number of switches per arm = 38 × 17 = 646. The effective switching frequency per arm is f eff = 2 × 38 × 165 = 12.54 kHz.

221

222

16 Multilevel VSC Converters in HVDC Applications

16.5 Full Bridge MMC 16.5.1

Operating Principles

In this topology, each module has full-bridge (FB) structure, which consists of four IGBT packs (IGBT plus freewheeling diode) and a capacitor. Here, a module has more AC voltage states, as the cell voltage can be 0, +V cell and −V cell . This increases number of redundant states for each AC voltage level and also opens the possibility of operating with a negative DC voltage. In normal HVDC operation this increased redundancy is not normally required, but it might be advantageous during abnormal operating conditions, like DC faults. Therefore, using double the number of semiconductors, increasing the electronic footprint and almost doubling the semiconductor losses (two switches always conduct) in normal operation should be weighed against performance enhancements. The operation of a FB module is shown in Table 16.4 for the cell ON, OFF, and blocked states. Table 16.4 Operation of a FB cell. Cell ON state

Cell OFF state

Cell blocked

+ve current S1

S3

S4

S2

Vcell

V0

Vo = Vcell, S1 = 0 (OFF), S3 = 1 (ON) S4 = 1 (ON), S2 = 0 (OFF)

S1

S3

S4

S2

Vcell

V0

Vo = –Vcell, S1 = 1 (ON), S3 = 0 (OFF) S4 = 0 (OFF), S2 = 1 (ON)

S1

S3

S4

S2

Vcell

V0

S3

S4

S2

Vcell

S3

S4

S2

Vcell

V0

Vo = Vcell S1 = 0 (OFF), S3 = 0 (OFF) S4 = 0 (OFF), S2 = 0 (OFF)

Vo = 0, S1 = 1 (ON), S3 = 1 (ON) S4 = 0 (OFF), S2 = 0 (OFF)

S1

S1

V0

Vo = 0, S1 = 0 (OFF), S3 = 1 (OFF) S4 = 1 (ON), S2 = 1 (ON)

−ve current S1

S3

Vcell

V0 S4

S1

S3

S4

S2

Vcell

V0

Vo = –Vcell, S1 = 1 (ON), S3 = 0 (OFF) S4 = 0 (OFF), S2 = 1 (ON)

S3

S4

S2

Vcell

S2

Vo = Vcell, S1 = 0 (OFF), S3 = 1 (ON) S4 = 1 (ON), S2 = 1 (OFF)

S1

V0

Vo = 0, S1 = 1 (ON), S3 = 1 (ON) S4 = 1 (OFF), S2 = 0 (OFF)

S1

S3

S4

S2

Vcell

V0

Vo = 0, S1 = 0 (OFF), S3 = 1 (OFF) S4 = 1 (ON), S2 = 0 (ON)

S1

S3

S4

S2

Vcell

V0

Vo = –Vcell S1 = 0 (OFF), S3 = 0 (OFF) S4 = 0 (OFF), S2 = 0 (OFF)

16.5 Full Bridge MMC

The cell can be in an ON state either with positive voltage V cell or with negative voltage −V cell . There are also two possible configurations for a bypassed cell, but in each case current runs through two switches. It should be observed that when cell is blocked there is still current path in both directions, but it always runs through the capacitor in a positive direction. At system level, this implies that the blocked FB MMC inserts full DC voltage and a blocked FB cell becomes an open circuit for DC current (no direct short circuit current path), as discussed in Sections 20.4 and 22.8. Similarly, as with HB cells, the voltage across each switching device is limited to one cell capacitor voltage, V cell . Modulation and capacitor voltage balancing of the FB MMC are similar to those of the HB MMC, except that the use of FB introduces new redundant switch states. This allows a wider range for arm voltages and eliminates dependency on current direction, and cell voltage balancing can be faster. Figure 16.14 shows a one-phase leg of the FB MMC, with two cells per arm. The converter can generate three voltage levels per phase. Similarly to HB topology, DC voltage Figure 16.14 One phase of a three-level FB modular converter. Sa1 Da1

Vcell

Sa3 Da3

Ccell Sa2 Da2

Sa3 Da4

Sa5 Da5

Sa3 Da7

½Vdc

Vcell

Ccell Sa6 Da6

Sa3 Da8

iga

0 Sa9 Da9

Vcell

Sa11 Da11

Va0

Ccell Sa10 Da10

Sa12 Da12

Sa13 Da13

Sa15 Da15

½Vdc

Vcell

Ccell Sa14 Da14

a

Sa16 Da16

223

224

16 Multilevel VSC Converters in HVDC Applications

Figure 16.15 Full-bridge MMC cell. Source: Reproduced with permission of Siemens.

equals the sum of arm voltages. Since each arm can generate either positive or negative voltage, there is very wide range of possible AC voltage magnitudes and it can be shown that normal AC voltage can be generated even with low DC voltage. The module design for FB MMC will be different from that for HB MMC. The FB MMC module will have four IGBT packs but will not require a bypass thyristor or bypass vacuum switch. The initial studies show that cell costs and losses will not double but will be around 1.4–1.6 p.u. compared with HB MMC. It is also mentioned that it is not always necessary that all of the arm cells assume FB topology. Depending on the required minimal operating DC voltage, a required AC voltage can be generated with only a fraction of the arm cells of FB type (the remaining cells can assume HB topology). Figure 16.15 shows a photograph of an FB MMC cell.

16.6 Comparison of Multilevel Topologies A comparison between the three basic multilevel converters for the same AC voltage of n + 1 levels is illustrated in Table 16.5. Half-bridge and full-bridge modular converters are used in HVDC. Multilevel diode bridge converters are used in industry at various power levels, but only three-level topology has been used in HVDC converters.

16.6 Comparison of Multilevel Topologies

Table 16.5 Summary of multilevel inverter topologies in HVDC applications. Multilevel topologies For (n + 1) level

Diode clamped

Modular (HB)

Modular (FB)

Phase-0 voltage levels

n+1

n+1

n+1

Phase voltage levels

4n + 1

4n + 1

4n + 1

Line voltage levels

2n + 1

2n + 1

2n + 1

Switches per phase

2n

4n

8n

Cell capacitors

n

2n per phase

2n per phase

Clamping diodes per phase

2(n − 1)

No

No

Freewheeling diodes/phase

2n

4n

8n

DC supplies

1

1

1

Maximum number of levels

Any

Any

Any

Modularity

No

Yes

Yes

Note: (n + 1) represents the number of phase 0 AC voltage levels.

225

227

17 Two-level VSC HVDC Modelling, Control, and Dynamics 17.1 PWM Two-level Converter Average Model 17.1.1

Converter Model in an ABC Frame

This section employs an average value modelling approach to represent converters (high-power circuits only), like the one given in Figure 15.4. In this way the modelling of switchings is avoided, and therefore simulations can be executed at much higher speeds, perhaps in the range of 50–100 μs, as discussed with high voltage direct current (HVDC) modelling methods in Section 7.1. Outside the converter, the system model retains the full dynamics of analogue components (cables, inductors), and also full control system dynamics, since analogue and linear elements are less demanding on computing resources. Considering the converter modelling methods presented in (15.1), assuming an ideal AC sine waveform, the ABC frame equations for a two-level voltage source converter (VSC) model are: 1 1 vca = Vdc ma = Vdc Ma cos(𝜔t + 𝜑m ) 2 2 ) ( 1 1 2𝜋 vcb = Vdc mb = Vdc Mb cos 𝜔t − + 𝜑m 2 2 3 ) ( 1 1 2𝜋 (17.1) vcc = Vdc mc = Vdc Mc cos 𝜔t + + 𝜑m 2 2 3 It is assumed that the system is symmetrical and balanced. The power conservation equation for the converter is: Pdc = Pac Vdc Idcc = (iga vca + igb vcb + igc vcc )

(17.2) (17.3)

Replacing (17.1) in the above equation, the DC current is obtained: 1 (17.4) (i m + i m + i m ) 2 ga a gb b gc c The two-level VSC behaves as a controllable voltage source on the AC side according to (17.1), and a controllable current source on the DC side according to (17.4). Figure 17.1 shows a typical graphical representation of a symmetrical monopole VSC simulator model. In this figure, Rc represents all current-dependent losses in Idcc =

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

17 Two-level VSC HVDC Modelling, Control, and Dynamics

PCC

transformer Iga Igb Igc

VSC Idc

Lt

Rc

Lt

Vca

Rc

Lt

Rc

PLL

φg

Md dq/ABC

Mq

Ma Mb

Re

2Cdc Vdc 2Cdc

M a M b Mc

X

Mc

Re

Vcc

Vdc

Vg

Idcc

Vcb

Vg

0.5 X

0.5 X

0.5

Vca Vcb Vcc

Iga Igb Igc

X 0.5

X

Idcc

X

Figure 17.1 Implementation of the average two-level VSC model in the ABC frame. 25 Switching Model Agerage Model

20 15

Current (kA)

228

10 5 0 –5 –10 –15

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Time (s)

Figure 17.2 DC current comparison between the detailed model and the average VSC model.

the converter and transformer (conduction and switching loss), while Re represents voltage-dependent loss (leakage and DC capacitors). Figures 17.2 and 17.3 show the simulation results for a step input on active power. It is seen that the average model represents well the dominant system dynamics. It has

17.1 PWM Two-level Converter Average Model

80 60

Voltage (kV)

40 20 0 –20 –40 –60 –80

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Time (s)

Figure 17.3 AC voltage V aN comparison of the detailed model and the average VSC model.

been demonstrated in the literature that the average models are sufficiently accurate for designing the main HVDC control loops, generally in the frequency range below around 50–100 Hz. 17.1.2

Converter Model in the ABC Frame Including Blocked State

Insulated gate bipolar transistors (IGBTs) in a VSC can be blocked by discontinuing transistor firing pulses. In such a case IGBTs become open circuit but the reverse-conducting diodes will still conduct and a two-level VSC becomes a diode bridge as shown in Figure 17.4. Converter blocking is used to protect IGBTs under high current and for initial energisation in some topologies. In the blocked state all of the converter control is lost. Idc

Idcc

AC CB

Lt Lg_a

D1

D3

Ld

D5 2Cdc

Lt

Vdc

Lt Vg

Vc

2Cdc D4

D6

D2

Ld

Figure 17.4 Equivalent circuit of a blocked two-level VSC (VSC diode bridge).

229

17 Two-level VSC HVDC Modelling, Control, and Dynamics

VSC

transformer Iga Igb

Lt Lt

Igc

Lt

Block

Idc

DeBlock Block

Rc

Vca

DeBlock Block

Rc Rc

DeBlock

Vg

Vg

φg

Md Mq

dq/ABC

Ma Mb Mc

Re Re

2Cdc Vdc 2Cdc

Vcc

Ma Mb Mc

Vdc PLL

Vcb

Idcc DeBlock

PCC

Block

230

X X X

0.5

Vca

0.5

Vcb

Iga Igb Igc

Vcc

0.5

X X

0.5

Idcc

X

Figure 17.5 Average value two-level VSC model in the ABC frame, including blocked state.

A converter will normally have block/deblock control input, and Figure 17.5 shows a full non-linear average model including the blocked state with block/deblock signal transfer between the two states.

17.2 Two-level PWM Converter Model in DQ Frame The control signal in the ABC frame from (15.1) and (17.1) can be readily converted to a DQ rotating frame using the methods presented in Appendix B. In the rotating DQ frame the converter will have two control inputs (Md and Mq ) which are related to magnitude and angle (M, 𝜃 m ) as shown in Figure 17.6. These two signals can be used to control the two components of the generated AC voltage (V d and V q ). Note that the q from rectangular to polar Mq

M2 = M2d + M2q

M φM

0

Md

φM = arc tan

Mq Md

d

Figure 17.6 Converter control signal vector representation.

from polar to rectangular Md = M cos(φM) Mq = M sin(φM)

17.4 Two-level VSC Converter and AC Grid Model in the ABC Frame

DC voltage (V dc ) can be assumed to be at the rated value for most operating conditions, since it is usually controlled at a constant level by one of the HVDC converters. The high-power-output voltages V d and V q are therefore directly proportional to the low-power control signals Md and Mq , and VSC responds like a linear amplifier. If the converter model (17.1) is transferred to the synchronously rotating DQ frame: 1 V M 2 dc d 1 Vcq = Vdc Mq 2 The power balance equation in the DQ frame is: Vcd =

(17.5)

3 (17.6) (V I + Vcq Igq ) 4 cd gd Replacing (17.5) in the above equation, and also considering DQ currents, the DC current is obtained: 3 (17.7) Idcc = (Igd Md + Igq Mq ) 4 Vdc Idcc =

17.3 VSC Converter Transformer Model The HVDC converter is connected to the grid or local network through an isolating transformer. Although theoretically the HVDC converter can be connected to the grid directly, in all systems a transformer is used. The single-phase equivalent circuit of the isolating transformer in the low-frequency range is presented in earlier chapters and in Figure 7.8c. The transformer model dynamic equation is: v1 = RT i1 + LT

di1 + nv2 dt

(17.8)

1 (17.9) i n 1 where n is the transformer ratio and LT is the transformer (and any additional reactor) impedance. In many VSC systems the transformer leakage inductance is smaller than the required interface reactance, and an additional series reactor is introduced. i2 =

17.4 Two-level VSC Converter and AC Grid Model in the ABC Frame Figure 17.7 shows the basic schematic of a VSC connected to a local AC grid. In this figure, V s is the voltage of an equivalent remote source (fixed magnitude), V g is the voltage of a local point of connection (voltage for phase locked loop, PLL, synchronisation), V c is the converter AC voltage, V dc is the converter DC voltage, I g is the grid-side line current, I dcc is the converter DC current and I dc is the current from the DC cable/grid. The converter control signals (in static frame) are Ma , Mb , and Mc . The parameters Rs and Ls represent equivalent grid impedance. LT is transformer impedance and for

231

232

17 Two-level VSC HVDC Modelling, Control, and Dynamics

Ma Mb Mc AC, 3Φ 50 Hz

Rs

Ls

Vs

Idc

2Cdc

PCC Pg,Qg

Ig

Idcc

Vdc

Lt

Vg

2Cdc Vca Vcb Vcc

Figure 17.7 VSC with local AC grid.

simplicity, unity stepping ratio is assumed, i.e. n = 1. The dynamic equation for each of the three phases (a, b, and c) in static coordinate frame is: vSa = vCa + Rs ⋅ iga + (Ls + LT ) ⋅ vSb = vCa + Rs ⋅ igb + (Ls + LT ) ⋅ vSc = vCc + Rs ⋅ igc + (Ls + LT ) ⋅

diga dt digb dt digc

(17.10) dt Assuming a lossless converter, the AC power equation at the point of coupling is: (17.11)

Sg = vga iga + vgb igb + vgc igc The DC circuit equation is: Idc = Cdc ⋅

dVdc + Idcc dt

(17.12)

17.5 Two-level VSC Converter and AC Grid Model in a DQ Rotating Coordinate Frame Park’s transformation is used to convert all of the above AC system equations into a synchronously rotating DQ reference frame, as introduced in Appendix B. Assuming a symmetrical and balanced system, (17.10) is transferred as: VSd = VCd + Rs Igd − 𝜔(Ls +LT )Igq + (Ls +LT ) VSq = VCq + Rs Igq + 𝜔(Ls +LT )Igd + (Ls +LT )

dIgd dt

(17.13)

dIgq

(17.14) dt where 𝜔 is electrical system frequency (rad/s), and the d, q suffix represent the coordinate frame axes. The AC power (17.11) in the rotating frame becomes: Sg = Pg + jQg =

3 (V + jV gq )(Igd − jI gq ) 4 gd

(17.15)

17.6 VSC Converter Control Principles

3 (V I + Vgq Igq ) 4 gd gd 3 Qg = (−Vgd Igq + Vgq Igd ) 4 Note that all variables are expressed as instantaneous values. Pg =

(17.16) (17.17)

17.6 VSC Converter Control Principles At a control system level, all of the VSCs have a similar general input–output structure and can be viewed as two-input, two-output, non-linear dynamic amplifiers. The two control inputs (Md and Mq ) are employed to develop feedback regulators to achieve various control functions depending on the converter application. A controller for VSC should meet the following goals: • Regulation of system variables of importance – typically, some of the following variables are regulated at reference values: – DC voltage, to ensure minimum losses and to prevent insulation damage; – power transfer, according to scheduling demands; – reactive power exchange; – AC voltage level – this control may be of importance with very weak (high impedance) AC grids. • Protect converter from damage caused by currents or voltages exceeding rated values. • Ensure system stability and good speed of responses. This requirement implies bounded responses and good transient performance of system variables under all foreseen operating conditions and all disturbances. • Local AC grid support. Typically, with low-inertia AC grids the VSC is required to achieve frequency stabilisation using frequency droop feedback. With high-impedance systems voltage stabilisation may be required. The above control functions are commonly achieved with two-level cascaded converter control where the inner control ensures protection and stability whereas the outer control meets regulation/performance goals. The inner loops normally use fast decoupled current control. The outer control achieves various regulation and stabilisation functions by sending references for the inner current control loops. The above control structure has evolved from traditional controllers used with VSCs in variable speed drives. The primary difference is the size of the VSC HVDC, which means that it can have significant impact on the AC grid. In addition, the VSC with HVDC may connect to long DC cables and therefore DC system dynamics play an important role. The firing circuit level control will depend on the type of converter in use. Without loss of generality it is assumed in this document that sinusoidal pulse width modulation (SPWM) is used with two-level converters, and it is not described in detail. Also the firing synchronisation will be achieved using some form of PLL, which is described in Section 4.2, Part I. The VSC control is based on good understanding of the converter-to-AC system dynamic interactions, and consequently detailed converter modelling is an essential first step. The VSC modelling is typically accomplished by writing a basic per-phase

233

234

17 Two-level VSC HVDC Modelling, Control, and Dynamics

dynamic model and converting this model into a rotating coordinate frame under the assumptions of a symmetrical and balanced three-phase system.

17.7 The Inner Current Controller Design 17.7.1

Control Strategy

It is assumed that the coordinate frame is aligned with the AC terminal voltage, i.e. the voltage vector V g is located on the d axis. In practice this can be achieved with the use of PLL. Under this assumption vgq = 0, (17.16)–(17.17) become: 3 V I 4 gd gd 3 Qg = − Vgd Igq (17.18) 4 It can also be accepted that the terminal voltage is maintained at close to the rated value, and therefore the influence of the terminal voltage can be neglected at this stage, V gd = const. From (17.18) it is possible to control active power by controlling igd and reactive power by controlling igq . The simplicity of (17.18) is one of the main reasons for using DQ current control as the fastest inner control. The second, and perhaps more important, reason is that direct current control is important for preventing converter overheating, in particular during fault conditions. Pg =

17.7.2

Decoupling Control

The current in (17.18) is controlled using converter AC voltage components, but this relationship is more complex. Replacing (17.5), in (17.13) and (17.14) the current equations are: VSd = 0.5Md Vdc + Rs Igd − 𝜔(Ls +LT )Igq + (Ls +LT ) VSq = 0.5Mq Vdc + Rs Igq + 𝜔(Ls +LT )Igd + (Ls +LT )

dIgd dt dIgq

(17.19)

(17.20) dt It is seen in the above equations that control signals Md and Mq can manipulate converter currents I gd and I gq , respectively. However, there are also unwanted cross-coupling terms, since as an example changing Md will change both I gd and I gq . Therefore, at the first design stage decoupling control loops are introduced in an attempt to create two independent control channels. The control signals Md and Mq consist of two terms: MdC and MqC are control signals from the main feedback current loops (described below in the next design stage) and the decoupling terms as described by the following expressions: Md = 2 Mq = 2

Mdc + (Ls + LT )𝜔Igq Vdc Mqc − (Ls + LT )𝜔Igd Vdc

(17.21) (17.22)

17.7 The Inner Current Controller Design

Note that the current signals (igd and igq ) in the above decoupling loops are normally measured in wide bandwidth (filter constant of over 1000 Hz) considering that their dynamics are fast and magnitudes vary significantly during normal operation. These signals are also commonly scaled by dividing with rated current value. The signal V dc is not of a concern since DC voltage is typically tightly controlled V dc = const. (as discussed below) and therefore it need not be compensated. Commonly, the control output is simply divided by the rated V dc , as it is shown in the detailed control diagram in Figure 17.13. The decupling control stage may also include compensation of the impact of remote voltage V s in (17.19).

17.7.3

Current Feedback Control

Replacing (17.21) in (17.19) and (17.22) in (17.20) the following is obtained: VSd = Mdc + Rs Igd + (Ls +LT ) VSq = Mqc + Rs Igq + (Ls +LT )

dIgd

(17.23)

dt dIgq

(17.24)

dt

In the above equations, there are two control signal Mdc and Mqc controlling two independent variables I gd and I gq under external disturbances V Sd and V Sq . Therefore the controller design is reduced to two independent first-order systems. In high power systems, the line resistance Rs is typically very small and X s /Rs > 10. Assuming as the first approximation Rs = 0, the system in (17.23) and (17.24) has dominant integral behaviour. An integrator system is normally controlled with a PD (proportional differential) type controller to achieve good performance and zero tracking error, as a first-order overall system. The dynamic equations of the PD controller in the Laplace domain is therefore in the following form: ( ) sk d1 c Md = kp1 + (17.25) (Igdref − Igd ) Td s + 1 ( ) sk d1 (17.26) Mqc = kp1 + (Igqref − Igq ) Td s + 1 where s is LaPlace operator, k p1 and k d1 are the controller proportional and differential gains, respectively, and T d is the filter constant associated with differential term (very small). Figure 17.8 shows the schematic of the decoupled system with the inner control loops. Replacing (17.26) and (17.25) in (17.23) and (17.24), and neglecting disturbances, the closed loop system is obtained: Igd =

Igq =

(kp1 Td + kd1 )s + kp1 (Ls + LT )Td

s2

+ (Ls + LT + kp1 Td + kd1 )s + kp1

(kp1 Td + kd1 )s + kp1 (Ls + LT )Td s2 + (Ls + LT + kp1 Td + kd1 )s + kp1

Igdref

(17.27)

Igqref

(17.28)

235

236

17 Two-level VSC HVDC Modelling, Control, and Dynamics

kp1 Igd ref +

kd1s –

Igd

Tds + 1

+

1

+

Igd

(Ls + LT)s + Rs

Mcd

d axis controller

AC grid(Rs = 0)

kp1 Igq ref

+

kd1s –

Igq

Tds + 1

+

1

+

Igq

(Ls + LT)s + Rs

Mcq

q axis controller

AC grid(Rs = 0)

Figure 17.8 Block diagram of the inner current feedback loops assuming ideal decoupling.

Since the differential time constant is small compared with the dominant dynamics, it is possible to further assume T d = 0, and (17.27)–(17.28) become: Igd = Igq = 17.7.4

kd1 s + kp1 (Ls + LT + kd1 )s + kp1 kd1 s + kp1 (Ls + LT + kd1 )s + kp1

Igdref

(17.29)

Igqref

(17.30)

Controller Gains

In the above system it is feasible to determine the controller gains. The initial value of the step response is given by k d1 , and the time constant is T I = (Ls + LT + k d1 )/k p1 . Therefore for a desired speed of response (T I ), the gains k p1 and k d1 can be determined. Clearly, k p1 increases speed of transient response whereas k d1 slows the speed of responses. However k d1 increases the initial value of the response. The speed of response is typically limited by the dynamics of feedback filters for current measurement in the decoupling loops in (17.21) and (17.22). As an example, if Ls + Lt = 0.11 H, T d = 0.0004 s, and the desired time constant is T I = 4 ms, then a good choice for control gains is k d1 = 0.6, k p = 200. If there is a finite system resistance Rs , the above controller will give steady-state error equal to Rs /(Rs + k p1 ). To eliminate this error, an integral term, k I1 , is typically added in the inner control loop. The non-zero Rs will also increase the speed of response and the new time constant will be T I1 = (Ls + LT + k d1 )/(k p1 + Rs ). It is noted also that the inner control can be based on estimation of current signals (rather than measurements), which reduces the impact of noise in current measurements, but such control has been shown to be less robust to parameter variations. Figure 17.9 shows the testing of inner control loops on a detailed switching model. Step-up and then step-down inputs are applied on each control channel (at 0.3 s

17.8 Outer Controller Design 0.5

0.4

Igd (p.u.)

Igq (p.u.)

0.6

0.2 0

–0.2 0.25

0 –0.5 –1

0.3

0.35

0.4

0.45 0.5 time (s)

0.55

0.6

0.65

0.25

0.3

0.35

0.4 0.45 time (s)

0.5

0.55

0.6

0.65

0.3

0.35

0.4

0.45 0.5 time (s)

0.55

0.6

0.65

0.1

1

0

0.8

Md

Mq

0.2

–0.1

0.6

–0.2 0.25

0.4 0.3

0.35

0.4

0.45 0.5 time (s)

0.55

0.6

0.65

0.25

Figure 17.9 Step responses of the inner control loops on a detailed model: igqref step at 0.4 and 0.5 s; and igdref step at 0.3 and 0.6 s.

I gdref = 0→0.5, at 0.4 s I gqref = 0→0.5, at 0.5 s I gqref = 0.5→0, at 0.6 s I gdref = 0.5→−1) and both reference current and actual currents are shown. It is seen that tracking is good, the response is fast and that there is only a small coupling between the two channels. The same test system as in previous sections is employed: P = 1000 MW, Ls = 0.01 H, Rs = 0.398 Ω, Lt = 0.1 H (X t = 0.2 p.u.), k d = 0.6, k p = 200, k i = 16 000, current feedback filter frequency is 1200 Hz. In Figure 17.8 it is seen that the feedback gain and time constant depend on the system parameters Rs and Ls . Some HVDC (like Caprivi link in Namibia) operate with low and very variable short circuit ratio (SCR), which may cause problems in the inner fast control loops. They may use some feedback control gain scheduling to compensate for the variation in the system parameters.

17.8 Outer Controller Design The inner controller loops can be viewed as a fast, first-order system, considering the dominant dynamics in (17.29) and (17.30). The outer control loops manipulate current references (igdref and igqref ) to achieve higher control goals. From (17.18) the d current component affects the active power and the q current component affects the reactive power. The d current is therefore used for controlling either power transfer or DC voltage. The q current is typically manipulated to regulate the reactive power exchange or AC voltage level. The outer controllers are typically of proportional integral type in order to ensure satisfactory speed of response and to eliminate tracking error. 17.8.1

AC Voltage Control

The AC voltage control using VSCs may be attractive with very weak AC systems, i.e. systems with high impedance. Figure 17.10 shows the outer AC voltage control system assuming that only the dominant dynamics from the inner q-current control shown in Figure 17.10 are present.

237

238

17 Two-level VSC HVDC Modelling, Control, and Dynamics

kp2 Vg ref

kI 2 s

+ –

(Ls+LT)

+ +

Vg

(kp1 + skd1) Igqref

Igq

Vg X

kp1 + s(kd1 + Ls + LT) Inner q current control

Figure 17.10 Designing outer AC voltage controller.

From Figure 17.10, the transfer function is given by: Vg =

[kI2 kp1 + s(kp2 kp1 + kd1 kI2 ) + s2 kp2 kd1 ](Ls + LT ) (kp1 kI2 )(Ls + LT ) + s[kp1 + (kp2 kp1 + kd1 kI2 )(Ls + LT )] + s2 [kp2 kd1 (Ls + LT ) + kd1 + Ls + LT ]

Vgref

(17.31) The above system is a conventional second-order filter. Therefore for a desired damping ratio 𝜁 2 and frequency 𝜔2 of the AC voltage control system, the two controller parameters (gains k p2 and k I2 ) can be determined: 𝜔22 = 2𝜍2 𝜔2 =

17.8.2

(kp1 kI2 )(Ls + LT ) kp2 kd1 (LAC + LT ) + kd1 + Ls + LT kp1 + (kp2 kp1 + kd1 kI2 )(Ls + LT )

(17.32)

kp2 kd1 (Ls + LT ) + kd1 + Ls + LT

Power Control

Figure 17.11 shows the outer power control system, assuming that only the dominant dynamics from the inner d-current control shown in Figure 17.11 are present. The transfer function is derived from Figure 17.11: [kI3 kp1 + s(kp3 kp1 + kd1 kI3 ) + s2 kp3 kd1 ]Vgd

Pg =

P (kp1 kI3 )Vgd + s[kp1 + (kp3 kp1 + kd1 kI3 )VACd ] + s2 [kp3 kd1 Vgd + kd1 + Ls + LT ] gref (17.33) kp3

PGref

+ – PG

kI 3 s

VGd

+ +

(kp1 + skd1) Igdref

Figure 17.11 Designing outer power controller.

kp1 + s(kd1 + Ls + LT) Inner d current control

Igd

PG X

17.8 Outer Controller Design

Therefore, for a desired damping ratio 𝜁 3 and frequency 𝜔3 , the gains k p3 and k I3 can be determined: (kp1 kI3 )Vgd 𝜔23 = kp3 kd1 Vgd + kd1 + Ls + LT 2𝜍3 𝜔3 =

17.8.3

kp1 + (kp3 kI1 + kd1 kI3 )Vsd

(17.34)

kp3 kd1 Vgd + kd1 + Ls + LT

DC Voltage Control

Considering schematic in Figure 17.7, the DC voltage equation is given as: Cdc

dVdc = Idcc − Idc dt

(17.35)

Since power equations are simpler than current equations, (17.35) is converted to a power equation by multiplying by V dc : 1 d 2 C (V ) = Pdcc − Pdc 2 dc dt dc

(17.36)

The power flow is therefore directly proportional to the differential of square of the DC voltage. This equation also shows capacitor energy dynamics, since from (12.4) the DC capacitor energy is directly proportional to the square of the DC voltage. Considering the significance of the capacitor energy and better control response, the DC voltage controller is frequently designed to control the square of the DC voltage (rather than directly DC voltage). A simple DC voltage controller is shown in Figure 17.12. The transfer function for the system in Figure 17.12, is derived as: 2 Vdc =

[kI4 kp1 + s(kp4 kp1 + kd1 kI4 ) + s2 kp4 kd1 ]2Vsd 2(kp1 kI4 )Vgd + s(kp4 kp1 + kd1 kI4 )2VACd + s2 (2kp4 kd1 Vgd + kp1 ) + s3 (kd1 + Ls + LT )

2 Vdcref

(17.37) The above system has dominant integral dynamics which can be explained considering the magnitude of various terms in the denominator in (17.37). Consequently, it can be controlled with a PD-type controller. However because of the importance of accurate DC voltage regulation, the integral controller gain is essential in practice. Therefore the proportional integral controller is proposed with gains k I4 and k p4 . The controller gains VGd

kp4 Vdc ref

(.)2

V 2dc ref

+ –

V 2dc

kI4 s

++

(kp1 + skd1) Igdref

kp1 + s(kd1 + Ls + LT) Inner d current control

Figure 17.12 Designing outer DC voltage controller.

Pdc1

Igd X

Pg

+–

2 Cs

V 2dc

239

240

17 Two-level VSC HVDC Modelling, Control, and Dynamics

are typically tuned using a root locus technique. Firstly, the controller zero zc = k I4 /k p4 is determined from the controller transfer function: kp4 s + kI4 2 s + zc 2 2 2 Igdref = ) = kp4 ) (17.38) (Vdcref − Vdc (Vdcref − Vdc s s The zero is placed close to the dominant system pole, or close to origin for integral systems. In the next design steps, the proportional gain is varied and location of poles is observed on the root locus. 17.8.4

AC Grid Support

The power reference in Figure 17.11 is typically constant and maintained at a scheduled level for a particular system/station. Alternatively, the power reference can be made dependent on frequency deviations in AC grids. There are two reasons for this additional control function: • Large VSCs in inverter mode should be treated as any large conventional power plant. It is normal that large generators use frequency droop feedback as an additional signal with power regulation. The rectifiers can be treated as any AC system load. • In the case of weak, low-inertia AC systems, it might be beneficial to modulate VSC power exchange in response to AC system frequency deviation. This control function applies equally to rectifiers and inverters. Such control has been used with conventional and VSC HVDC. In particular with VSC HVDC the frequency support can be extended to regulate frequency on dead AC networks. The droop gain for AC grid support can be calculated as: kgdroop =

2Pdc max fgmax − fgmin

(17.39)

where f max and f min are the allowed limits for the AC system frequency deviation and Pdc_max is the maximum converter power deviation allowed for system support. Where dynamic support and AC grid stabilization are needed, a dynamic feedback loop can be developed instead of static gain k gdroop . Such a feedback loop can be designed as a frequency-dependent transfer function to enhance stability (phase or gain margin) in a particular frequency bandwidth. With conventional point-to-point HVDC there is usually one stronger AC system that can dynamically support the other system. Such stabilisation is achieved through HVDC controls, but power is essentially drawn from the remote (stronger) AC system. There are other possible high-level power modulation methods which are discussed in Chapter 23.

17.9 Complete Two-level VSC Converter Controller The complete VSC controller is shown in Figure 17.13. The schematic includes the inner current and decoupling control loops, the outer loops, the PLL synchronisation and also

VGa VGb

PLL

VGc VG

Vg filter

VG ref

+

kp2

Igb Igc

fg

+

– –

Vdc ref

2

(.)

Vdc filter 2

(.)

+

Ig_r n

kp3

–

kp4

Igq

n/d

Igd

–

n

n/d d

φPLL

Ig filter ω(Ls + LT) Ig filter

ω(Ls + LT)

Igdmax Igd ref

+

–

kp1

Igdmin Power/ Vdc

+ ++

kI1/s d Current Controller

DC voltage controller

Figure 17.13 Two-level VSC controller with inner and outer control loops.

min

Vdc_rated √1 – M2d

sKd1/(Tds + 1)

+ +

+ +

+

kI1/s

d

DC power controller kI4/s

kgdroop

Vdc

n/d

+ + +

kp1

Igqmin n

kI3/s

Pdc filter

Pdc ref

sKd1/(Tds + 1)

+ +

φPLL abc to dq

Pdc

q Current Controller Igqmax + Igq ref –

static to rotating frame

Iga

Igq /Vg

k12/s

–

AC Voltage controller

Igq ref

Coordinate frame reference

φPLL

+ –

n

1

d n/d –1

Mq Md

fs δ1

Ma dq Mb to abc Mc

rotating to static frame

δ2 Switch firings

δ3 δ4 δ5 δ6

242

17 Two-level VSC HVDC Modelling, Control, and Dynamics

the switch firings (SPWM at switching frequency f s ). Each of the two outer control loops has a selection switch to provide top-level control choice. The controller outputs are the firing signals for six IGBT switches (S1 –S6 ). The figure shows active power priority selection, since the reactive power control signal Mq is limited depending on the magnitude of Md to ensure M < 1. An additional modulation signal on power reference is shown in the control diagram which stabilises the AC grid. Also, if the converter is part of a DC grid, then DC voltage droop feedback (k gdroop ) can be included in order to enhance the stability of the DC grid, as discussed in Part III, Section 27.5.

17.10 Small Signal Linearised VSC HVDC Model A complete two-level VSC HVDC model can be derived by connecting the three subsystems which are studied in this chapter and in Part I with line commutated converter (LCC) HVDC: • The DC system model which includes converters, DC line, rectifier controller and PLL, inverter controller and PLL, feedback filters and all equations that describe coupling with AC systems. • The rectifier AC system, which is modelled as described with LCC HVDC. • The inverter AC system. The above modelling principles support developing an average value non-linear VSC HVDC model. Depending on the filtering used, the model may have 30–50 equations. In order to perform eigenvalue studies and to use major control design theories it is necessary to use a linearised model. A linearised model is obtained by linearising all non-linear terms around the steady-state operating point. Figure 17.14 shows the verification of a linearised dynamic model for a 1 GW, 640 kV two-level HVDC system with a 100 km DC cable. Both AC systems have SCR = 40, X/R = 10. It is seen that the linearised model shows excellent accuracy for a 5% step input on I dref . It is also seen that the model shows good matching for all variables, including AC and DC variables on both sides (rectifier and inverter). It is important that model represents well all physical variables and parameters in all subsystems in order to enable accurate dynamic, parametric studies and control design.

17.11 Small Signal Dynamic Studies 17.11.1

Dynamics of Weak AC Systems

Figure 17.15 shows the root locus of the dominant eigenvalues for the reduction in AC system strength, (i) on the inverter and (ii) on the rectifier side. It is seen that damping of dominant eigenvalues 1, 2 reduces as the system strength reduces, which is a similar conclusion to that with LCC HVDC. However, VSC HVDC is less susceptible to SCR reduction, and even at SCR = 2, the eigenvalue damping is still around 0.5, which is much better than with LCC HVDC. The dynamic instabilities are expected at frequencies around 11–15 Hz for inverter and 6–10 Hz for rectifier.

17.11 Small Signal Dynamic Studies 0.97

–0.86 –0.88

0.968

Detailed Linearised

0.966 Vdci (p.u.)

Igdi (p.u.)

–0.9 –0.92 –0.94

0.964 Detailed 0.962

–0.96

0.96

–0.98

0.958

–1

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s)

0.956

0.05

1.04

0.04

1.02

0.03

1

Detailed

0.96

Mdi

Igqi (p.u.)

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s)

0.98

0.01 0

0.94

–0.01

0.92

–0.02

0.9

–0.03

0.88

–0.04 Detailed Linearised 0

0.86

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s)

1.05

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s)

0.973 Detailed Linearised

Detailed Linearised

0.972 0.971 Vdcr (p.u.)

1 Igdr (p.u.)

0

Linearised

0.02

–0.05

Linearised

0.95

0.9

0.97 0.969 0.968 0.967 0.966

0.85

0

0.06

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s) Detailed Linearised

0.965

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s) Detailed Linearised

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s)

0.98 0.96

0.04

0.94

0.02

0.92 Mdr

Igqr (p.u.)

0

0

0.9 –0.02

0.88

–0.04 –0.06

0.86

0

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 time (s)

0.84

Figure 17.14 Verification of small signal linearised VSC HVDC model.

243

17 Two-level VSC HVDC Modelling, Control, and Dynamics 200

200

150

SCRr = 40

SCRi

50

2

4 –50

–100

–100

–150

–150 –50

(a) SCR reduction at inverter (Vdc controlling terminal)

4

2

–200 –150

0

3

0

–50

Re

1

3

0

–100

SCRr

50

1

–200 –150

SCRr = 2

100

Im

Im

150

SCRi = 2 SCRi = 40

100

–100

Re

–50

0

(b) SCR reduction at rectifier (Id controlling terminal)

Figure 17.15 VSC HVDC system dynamics with reduction in SCR (2 < SCR < 40).

It is also observed that the rectifier and inverter terminals have similar robustness to SCR reduction, even though the outer controls are different (I gd control at rectifier and V dc control at inverter). This points to the conclusion that inner control loops (which are identical for rectifier and inverter) have a significant impact on stability. 17.11.2

Impact of PLL Gains on Robustness

The original PLL gains were set as k pPLL = 10, k iPLL = 200, k cPLL = 1. Figure 17.16 indicates that the dynamics are generally improving as PLL gains are increased further. However, beyond a certain point the dynamics deteriorate with large PLL gains. It is noted that PLL gains have the most impact at low frequencies, in the region of a few hertz. Higher PLL gains do not improve much the dynamics of HVDC with weak AC systems. With very high PLL gains the dynamics with a weak system may actually deteriorate. This is illustrated in Figure 17.17, which shows the same root locus conditions as in Figure 17.15, but higher PLL gains are used (k cPLL = 10), as seen by the improved position of original eigenvalues 3 and 4. It is observed that root locus branches are longer, indicating greater sensitivity to changes in the AC system strength. 100

100

80

80

60

60

40

3 kcPLL Im

–20

3

0 –20

4 kcPLL = 1

2

kcPLL = 0.1

4

2

–40 –60

–60

–80

–80 –100 –70

kcPLL = 1 kcPLL

1

20

0

–40

kcPLL = 10

40

1

20 Im

244

–60

–20 –10 Re (a) PLL gain reduction 10 times

–50

–40

–30

0

10

–100 –70

–60

–20 –10 Re (a) PLL gain reduction 10 times

–50

–40

–30

Figure 17.16 VSC HVDC system dynamics with change in PLL gains (0.1 < kcPLL < 10).

0

10

17.11 Small Signal Dynamic Studies 200

200

150

150 SCRi = 2

SCRi = 40 100

50

1

3

4

0

2

–50

–150

–150

Re

1

–50

0

(a) SCR reduction at inverter (Vdc controlling terminal)

–200 –150

3

2

–50 –100

–100

SCRr = 2

4

0

–100

–200 –150

SCRr = 40 SCRr

Im

50 Im

100

SCRi

–100

Re

–50

0

(b) SCR reduction at rectifier (Id controlling terminal)

Figure 17.17 VSC HVDC system dynamics with reduced SCR (2 < SCR < 40), using increased PLL gains, kcPLL = 10.

245

247

18 Two-level VSC HVDC Phasor-domain Interaction with AC Systems and PQ Operating Diagrams 18.1 Power Exchange Between Two AC Voltage Sources The first section in this chapter will review the theory of power exchange between two AC systems, which is important to establish the theoretical limits. The study is similar to that in Section 9.3 with current source line commutated converters (LCCs), but in this section there are two AC voltage sources (instead of current sources) which mimic voltage source converters (VSCs). The system under study is shown in Figure 18.1. Assuming that the AC system is symmetrical and balanced, considering that the AC frequency is constant and neglecting dynamics, all AC variables become phasors as discussed in Appendix C. In this notation, all three-phase variables become two-component vectors (zero sequence is neglected) with RMS variables. All impedances will become static complex numbers with reactances as imaginary components. The voltage phasors are: Vsdq = Vs ∠𝜑Vs = Vsd + jVsq

(18.1)

Vgdq = Vg ∠𝜑Vg = Vgd + jVgq

(18.2)

where Vgdq , Vsdq are the phasors, V g and Vs are the magnitudes (line-neutral RMS) and 𝜑Vg , 𝜑Vs are the phase angles of the respective voltages. The subscripts d and q denote corresponding phasor components. The grid current phasor is: Ig =

Vs − Vg

Ig ∠𝜑I =

zs Vs ∠𝜑Vs − Vg ∠𝜑Vg Zs ∠𝜑Z

(18.3)

Assuming that the coordinate frame is linked with the remote source voltage V s : Vs − Vgd − jVgq (18.4) Igd + jIgq = Rs + jX s It is also assumed that the magnitudes of two voltages are equal and constant –: Vs = V g = const., – since this is the case of most interest in transmission engineering: Igd + jIgq = Vs

1 − cos 𝜑Vg − j sin 𝜑Vg Rs + jX s

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

(18.5)

248

18 Two-level VSC HVDC Phasor-domain Interaction

Thevenin equivalent Pg, Qg circuit of AC grid remote source

Rs

jXs

Vs

Ig

Figure 18.1 Test system for studying power exchange between two AC voltage sources. converter

Vg

Rearranging (18.5), the current expression is obtained: Igd + jIgq =

Vs R2s

+ Xs2

[Rs (1 − cos 𝜑Vg ) − Xs sin 𝜑Vg − j(Rs sin 𝜑Vg + Xs (1 − cos 𝜑Vg ))] (18.6)

The condition for maximal real current is calculated by equating the first derivative of the real part with zero: (tg𝜑Vg )maxPg =

Xs Rs

The condition for maximal reactive current is: R (tg𝜑Vg )maxQg = s Xs

(18.7)

(18.8)

In the case that Rs = 0, the maximum current is obtained for 𝜑Vg = 90∘ , which is a known case from transmission system studies, and which equals: Igd + jIgq =

Vs V + j s = 1 p.u. + j1 p.u. Xs Xs

(18.9)

where the p.u. unit system is based on short circuit level as discussed in Section 9.3. Figure 18.2 shows the power exchange between the two AC systems as the phase angle of V g is changing. Considering first the case X s /Rs = infinity, it can be seen that the maximum power transfer is 1 p.u., for both the rectifier and the inverter. This implies that the minimal theoretical short circuit ratio (SCR), according to definition (9.3), is 1. If there is some resistive part in the grid impedance, then the maximum transfer limit reduces for the rectifier but increases for the inverter. Figure 18.3 shows the power transfer limits assuming that the current is in phase with voltage V g , since this is a common operating mode for many converters. In this case, the magnitude of V g is allowed to vary in order to compensate for reactive current. In case of X s /Rs = infinity, it is observed that the maximum power transfer is 0.5 p.u. for both rectifier and for inverter. This implies that the minimal theoretical SCR is 2. However, if V g variation is restricted to 0.9 p.u., then the maximum rectifier or inverter power is 0.3 p.u. (corresponding to minimal SCR or 3.3). If X s /Rs = 5 then the maximum power that a rectifier can receive is 0.4 p.u. (giving a minimum SCR of 2.5) and the maximum power that inverter can deliver to the grid is 0.65 p.u. (giving a minimum SCR of 1.54). Further, if V g variation is limited to 0.9 p.u., then the maximum rectifier power is only 0.2 p.u. while inverter power is limited to 0.5 p.u.

18.2 Converter Phasor Model and Power Exchange with an AC System

s /R s

s

=i nfi nit

Inverter

2

X

X

s /R s

–0.5

s /R Xs / R s = s

Rectifier

y 5 = 10

X/ s R

0 Pg (p.u.)

=1

X

s /R s

X

0.5

=i nfi nit =1 y X 0 X / s R s /R s = s = 5 2

1

s /R s

=

1

X

s /R s

=

–1

X

–1.5 –150

–100

–50

0 φVg (deg)

50

100

150

100

150

2 1.8 1.6 1.4

Rectifier

Inverter

Ig (p.u.)

1.2 1 0.8 0.6 0.4 0.2 0

–150

–100

–50

0 φVg (deg)

50

Figure 18.2 Power exchange between two AC voltage sources assuming the V s = V g = const.

18.2 Converter Phasor Model and Power Exchange with an AC System The study of power exchange between two voltage sources now expands to include realistic limitations associated with a VSC converter. The VSC converter is exchanging power with the AC grid through an interconnecting reactor (transformer reactance), by controlling the converter AC voltage V c , as illustrated in Figure 18.4. This is a slightly different case from that in the previous section since an additional reactance is included.

249

18 Two-level VSC HVDC Phasor-domain Interaction

0.5

Xs/Rs = infinity Xs/Rs = 10 Xs/Rs = 5 Xs/Rs = 2 Xs/Rs = 1

0

Pg (p.u.)

Rectifier

Inverter

–0.5 Xs/Rs = infinity Xs/Rs = 10 Xs/Rs = 5

–1

Xs/Rs = 2 Xs/Rs = 1

–1.5

0

–20

20 40 φVg (deg)

60

80

1.3 1.2

Rectifier

Inverter X/ s R

s

1.1

=1

1 0.9 0.8

=5 X s/R s 10 X s/R s = infinity = X s/R s

0.6 0.5

–20

Xs/Rs = 1

0.7

0

20 40 φVg (deg)

=2 Rs X s/

X /R Xs /R Xs/Rs = 5 s s = 10 s = infinity Xs/Rs = 2

Vg (p.u.)

250

60

80

Figure 18.3 Power exchange between two AC voltage sources assuming that the current is in phase with the voltage V g .

Also, the VSC converter is synchronised with the point of common coupling (PCC) voltage V g using a phase locked loop and therefore the converter control angle is referenced to V g . The converter power exchange is therefore controlled using two voltages across the interfacing reactor but the delivered power must be ultimately exchanged with the remote source V s . The interfacing reactance should be added to the grid reactance (total reactance is X s + X t ) if the study method from the previous section is used.

18.2 Converter Phasor Model and Power Exchange with an AC System

M d Mq

Idcc

Idc

2Cdc

AC, 3 Ф 50 Hz

PCC Pg, Qg

Ig Rs

Vs

Vdc Lt

Ls Vg

VC

2Cdc

Figure 18.4 Two-level VSC converter connected to an AC grid for phasor interaction study.

It is important to note that the grid operators are interested in the power exchange at the PCC. On the other hand, the VSC manufacturers will adequately rate the converter to meet PCC power specifications, considering converter voltage and current capabilities. Since the converter rating must be observed at all times, of particular interest are PQ operating limits at the PCC as the power transfer and operating modes change. The PCC voltage V g and remote source voltage Vs are defined in (18.1) and (18.2). The converter voltage V c is: Vcdq = Vc ∠𝜑Vc = Vcd + jVcq

(18.10)

Since the phase locked loop is used to synchronise the controller with the grid PCC voltage, it is more convenient to assume that V g is located on the d-axis (𝜑Vg = 0): Vgdq = Vgd = Vg ,

Vgq = 0

(18.11)

The converter voltage V c is controllable, and assuming a simple sinusoidal pulse width modulation, the converter phasor voltage components are: V Vcd = Md × √dc 2 2 V Vcq = Mq × √dc 2 2

(18.12) (18.13)

and the modulation ratio magnitude is also expressed as √ M = Md2 + Mq2 < 1

(18.14)

where Md and Mq are the DQ components of the sinusoidal pulse width modulation control signal and V dc is the DC voltage. The converter voltage rating is defined by the DC voltage. Assuming maximum modulation ratio M = 1, the converter-rated AC voltage can be determined from (18.12)–(18.14). The VSC converter current rating is defined by the magnitude of the current through the semiconductors. Either AC or DC current can be specified, but grid operators typically specify AC current requirements. The basic current equation for the circuit in Figure 18.4 is: Igdq =

Vg − Vc jX t

=

Vg − Vcd − jVcq jX t

(18.15)

251

252

18 Two-level VSC HVDC Phasor-domain Interaction

where X t is transformer reactance (Lt = X t /(2𝜋f ), and the grid frequency is f = 50 Hz). Expressing (18.15) using current components: −Vcq

Igd + jIgq =

Xt

+j

Vcd − Vg Xt

(18.16)

which is further represented using two scalar equations as Igd = Igq =

−Vcq

(18.17)

Xt Vcd − Vg

(18.18)

Xt

The PCC complex power can be calculated using (18.16) as: [ ] Vg − Vcd Vcq ∗ Sg = 3Vg × Ig = 3Vg − +j Xt Xt

(18.19)

where ( )* stands for the conjugate complex, which is required to ensure a consistent sign for the reactive power. Separating (18.19) into real and imaginary parts: Pg = −3Vg Qg = 3Vg

Vcq

Xt Vg − Vcd Xt

(18.20) (18.21)

or in terms of the magnitude and angle of control signals, MV dc √ sin(𝜑Vc ) Xt 2 2 MV Vg2 − Vg √dc cos(𝜑Vc )

Pg = −3Vg

Qg = 3

2 2

Xt

(18.22)

(18.23)

18.3 Phasor Study of VSC Converter Interaction with AC System 18.3.1

Test System

Table 18.1 shows the test system parameters in this chapter. The converter is designed considering the requirement for PCC maximum active and reactive power export. For the given grid voltage the rated converter current can be determined. A transformer will normally be used to adjust the ratio between grid voltage and DC voltage but it is omitted here for simplicity. 18.3.2

Assumptions and Converter Limits

In the study in the sections below, various AC system variables and also the VSC converter internal variables are examined as the converter active power is changing, for the

18.3 Phasor Study of VSC Converter Interaction with AC System

Table 18.1 Test system parameters. Rated Sg

1000 MVA

Design point Pg , Qg

Pg = −995 MW, Qg = −100 MVAr

Rated converter current I grated

1540 A

Rated PCC AC voltage V g_ll

375 kV

Rated converter AC voltage V c_ll

390 kV

Rated DC voltage V dc

636 kV

Remote source voltage V s_ll

369 kV

Transformer

X tpu = 0.2 p.u., St = 1000 MVA, V t_ll = 375 kV, n = 1 (X t = 28 Ω, Lt = 0.0895 H)

AC grid

SCR = 10, X/R = 10 (Rs = 1.4 Ω, X s = 14.1 Ω, Ls = 0.0448 H)

test case in Table 18.1. The most important converter operating modes will be separately investigated. The following assumptions are employed: • Coordinate frame is linked to PCC voltage: Vg = Vgd = Vg . • The magnitude of the remote source is constant: Vs = const. (infinite bus). Considering test system data with full VSC power in inverter mode, this voltage is calculated as Vs ll = 369 kV. • DC voltage is constant: V dc = 636 kV. A remote VSC converter controls DC voltage. • Modulation index cannot exceed 1. Converter controller will prevent overmodulation: √ M = Md2 + Mq2 ≤ 1 (18.24) • The converter current cannot exceed the rated value. The converter inner current controller will prevent the current exceeding the rated value: √ (18.25) Ig = I2gd + I2gq ≤ Igrated = 1540 A • Converter q-voltage V cq is an independent variable in the study. This variable is directly determined from the desired active power flow. Then, knowing V cq , from (18.16) the active current can be determined as in (18.17). 18.3.3

Case 1: Converter Voltages Are Known

First, the case where converter voltage V cd is also known is examined, since this case will give system variables when the converter is on the maximum voltage limit (M = 1). The current equation for the circuit in Figure 18.4 is: Igd + jIgq =

Vsd + jVsq − Vg Zs

(18.26)

253

254

18 Two-level VSC HVDC Phasor-domain Interaction

This equation can be converted into two scalar equations, which are squared, then 2 2 + Vsq : added, replacing Vs2 = Vsd (Rs Igd − Xs Igq + Vg )2 + (Xs Igd + Rs Igq )2 = Vs2

(18.27)

Replacing currents from (18.17) and (18.18) into (18.27) a quadratic equation is obtained: Vg2 a1 + Vg b1 + c1 = 0 a1 = R2s + (Xs + Xt )2 b1 = 2Rs (−Vcd Rs + Vcq Xs ) + 2(Xs + Xt )(−Vcd Xs − Vcq Rs ) c1 = (−Vcd Rs + Vcq Xs )2 + (−Vcd Xs − Vcq Rs )2 − Vs2 Xt2

(18.28)

Equation (18.28) enables direct calculation of V g for given converter voltages V cd and V cq . Once V g is known, I gq is determined using (18.18). 18.3.4

Case 2: Converter Currents are Known

The next case assumes that the converter current magnitude I g is given, as will happen if the converter current limit is reached. The reactive current I gq can be determined from (18.25) and (18.18). Therefore the remote source voltage and PCC voltage can be determined from (18.26): Vsq = Xs Igd + Rs Igq √ 2 Vsd = Vs2 − Vsq Vg = Vsd − Rs Igd + Xs Igq

(18.29)

At the final stage the converter voltages can be calculated from (18.16). 18.3.5

Case 3: PCC Voltage is Known

If the PCC voltage is known, V g = const., as is case if the converter is operated to control PCC voltage, then from (18.26) the following quadratic equation is obtained: 2 Vcd a2 + Vcd b2 + c2 = 0

a2 = R2s + Xs2 b2 = −2Rs (Vg Rs + Vcq Xs ) − 2Xs (−Vg (Xs + Xt ) − Vcq Rs ) c2 = (Vg Rs + Vcq Xs )2 + (−Vg (Xs + Xt ) − Vcq Rs )2 − Vs2 Xt2

(18.30)

Equation (18.30) enables calculation of converter voltage V cd , when PCC voltage is known.

18.4 Operating Limits Figure 18.5 shows the four quadrant operating diagrams for the VSC converter. The sign convention applies equally to active and reactive power: positive power means that

18.5 Design Point Selection

the converter (DC system) draws power from the AC grid. The curves show operating limits considering the converter voltage rating (M = 1 limit at rated DC voltage) and the current rating (I g limit). The top-left diagram shows the control variables Md and Mq , and the operating point can be anywhere inside the curve. The upper curve is the limit on the maximum modulation index, which will represent the maximum converter voltage. In practice this is the VSC reactive power export limit. It can be seen in (18.21) that if V cd is larger than V g the converter will export reactive power to the grid, and vice versa. The lower curve represents a low modulation index and in such cases the operating limit is derived considering the converter maximum current. The negative Mq corresponds to positive active power, which represents power delivered to the DC system. The available converter current envelope is also of interest. In the reactive power export mode (positive I gq ) the maximum current curve is not symmetrical since the converter can export more reactive current when importing active power. This is understandable since the V g is lower when power is transferred from the AC system to DC. The diagram with the PCC voltage V g as the converter operates on the limit curves is particularly significant for grid operators. Since the test AC grid is quite strong (SCR = 10) the AC voltage changes by only 5 kV as the operating point moves from full active power export to full import, along the maximal reactive power export. The PQ diagram in this figure is the most commonly used indicator of HVDC power exchange by the manufacturers. It shows the maximum PQ envelope at the PCC for a converter. The converter is designed for Pg = −995 MW and Qg = −100 MVAr (Sg = 1000 MVA). It can be seen that when Qg = 0, the converter can export around −990 MW. However the maximum import power is slightly lower (around 970 MW) since the V g is lower when power is transferred to the DC system. If Pg = 0, the converter exchanges only reactive power and operates as a STATCOM. As a STATCOM, this VSC can export around −180 MVAr and theoretically import up to 880 MVAr. This maximum reactive power import may not be achievable in practice since the PCC voltage would be unacceptably low.

18.5 Design Point Selection For a given MVA power at PCC, the converter nominal operating point can be selected according to grid operator requirements. This selection allows some trade-off between active and reactive power within the converter limits. Some VSC HVDC systems operate with weak AC grids (like Caprivi HVDC in Namibia) and these AC grids require a strong VSC reactive power capability at all active power levels. Figure 18.6 shows the diagrams of operating limits for the three different design points. Selecting a larger reactive power at the design point brings the advantage of a wider reactive power export region. In practice this larger reactive power capability is achieved by changing the transformer ratio (increasing the DC voltage if no transformer is used). On the downside, selecting a design point with larger reactive power implies that: • Converter current or DC voltage increases and therefore converter rating will increase. Losses will also increase.

255

0.95

0.9

Md

0.85

Limit on M Active power import Reactive power export

Active power export Reactive power export Design point P = –995 MW, Q = –100 MVAr

Limit on lg

Limit on M

200

Active power export Reactive power export

0 –200

Active power export Reactive power import

Active power import Reactive power import

Active power export Reactive power import

–1200 –1400

–0.15

–0.1

–0.05

0

0.05

Mq

380

0.15

0.2

–1600 –1500

–1000

–500

0

500

Igd (A)

1000

1000

1500

Limit on M Active power export Reactive power export

Active power export Reactive power import

Limit on lg

Active power import Reactive power import

350

800

Active power import Reactive power export

Design point P = –995 MW, Q = –100 MVAr

360 355

0.1

Limit on lg 600

Qg (MVar)

365

Limit on lg

–1000

Limit on lg

370

Active power import Reactive power import

–800

0.7

375

Limit on lg

–400

0.75

0.65 –0.2

Active power import Reactive power export

Design point P = –995 MW, Q = –100 MVAr

–600

0.8

VgII (kV)

400

Igq (A)

1

400

Active power export Reactive power import

Active power import Reactive power import

200

345

Design point P = –995 MW, Q = –100 MVAr Limit on M

340

0

Limit on lg

335 330 –1000 –800 –600 –400 –200

0

Pg (MW)

200

400

600

800

Figure 18.5 VSC converter operating limits: SCR = 10, X/R = 20, X t = 0.2 p.u.

1000

Active power export Reactive power export

–200 –1000 –800 –600 –400 –200

Active power import Reactive power export 0

Pg (MW)

200

400

600

800

1000

1

400

0.95

200

0.9

0

Design point Pg = –980 MW, Qg = –200 MVAr Design point Pg = –995 MW, Qg = –100 MVAr Design point Pg = –1000 MW, Qg = 0 MVAr

–200

Design point Pg = –1000 MW, Qg = 0 MVAr

0.8

Design point Pg = –995 MW, Qg = –100 MVAr

Igq (A)

Md

0.85

–600 –800

Design point Pg = –980 MW, Qg = –200 MVAr

0.75

–400

–1000

0.7

–1200 0.65 0.6 –0.2

–1400 –0.15

–0.1

–0.05

0

0.05

Mq

380

0.1

0.15

0.2

–1600 –1500

Qg (MVar)

Vgll (kV)

0

500

Igd (A)

1000

1500

600

Design point Pg = –1000 MW, Qg = 0 MVAr Design point Pg = –995 MW, Qg = –100 MVAr

350

–500

800

370

360

–1000

1000

Design point Pg = –980 MW, Qg = –200 MVAr

400

200

340 0 330

Design point Pg = –1000 MW, Qg = 0 MVAr Design point Pg = –995 MW, Qg = –100 MVAr

–200 320 –1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

800

1000

Design point Pg = –980 MW, Qg = –200 MVAr

–1000 –800 –600 –400 –200

Figure 18.6 VSC operating limits for different design points: SCR = 10, X/R = 20, X t = 0.2 p.u.

0

200

Pg (MW)

400

600

800

1000

258

18 Two-level VSC HVDC Phasor-domain Interaction

Table 18.2 System variables for different design points (Sg = 1000 MVA, V g = 375 kV). Design Pg (MW)

Pg (MW) at Qg = 0

Design Qg (MVAr)

Ig

V g (kV)

V dc (kV)

−1000

0

1540

375

625

−1000

−995

−100

1540

375

636

−990

−980

−200

1540

375

648

−980

−954

−300

1540

375

660

−965

• Active power capability at zero reactive power is reduced. • Operation at zero reactive power will require a lower modulation index, bringing more losses and harmonics. Table 18.2 summarises the differences between four operating points for the same apparent power Sg = 1000 MVA and the same grid voltage V g = 375 kV. As an example, selecting −300 MVAr at the design point would imply a 3.6% lower active power capability at unity power factor operation.

18.6 Influence of AC System Strength Figure 18.7 shows the operating limits for four different AC strengths: SCR = 2, SCR = 5, SCR = 10 and SCR = 30. As the AC grid becomes weaker the power exchange capability with the DC system reduces. With weak systems there is a narrow range of voltage which enables full converter power export or import. The maximum active power exchange can occur only for maximum reactive power export. The reactive power import capability also significantly reduces as the AC strength reduces.

18.7 Influence of AC System Impedance Angle (X s /Rs ) The impact of the X/R ratio on the converter operating curves is shown in Figure 18.8. A low X/R ratio means that the AC system is more resistive and generally the AC voltage will swing more as the active power transfer changes. The maximum active power exchange occurs with small reactive power transfer in such cases. Note that the reactive power export capability increases at low X/R ratio but this does not help in maintaining PCC voltage.

18.8 Influence of Transformer Reactance Figure 18.9 shows the impact of transformer reactance on the VSC converter operating curves. There is virtually no change in the active power transfer limits. However larger reactance will marginally reduce the reactive power export capability. The main impact is on the range of control signal variation, which increases as the reactance increases. This implies that a larger converter rating is required for a given DC voltage. Also,

1

600 400

0.9

SCR = 30 SCR = 10 SCR = 5 SCR = 2

200 0

0.8

SCR = 30

0.6

SCR = 5

–200

Igq (A)

SCR = 10

Md

0.7

–400 –600 –800

0.5

–1000 –1200

0.4 0.3 –0.2

SCR = 2 –0.15

–0.1

–0.05

–1400 0 Mq

0.05

0.1

0.15

0.2

–1600 –1500

SCR = 30 350

0 Igd (A)

500

SCR = 10

250

200

–200

0 200 Pg (MW)

SCR = 2 SCR = 5 SCR = 10

200

150 –1000 –800 –600 –400 –200

SCR = 2

400

0

SCR = 2

1500

SCR = 5

600

SCR = 5

1000

SCR = 30 SCR = 10

800

Qg (MVar)

Vg_ll (kV)

–500

1000

400

300

–1000

400

600

800

Figure 18.7 VSC operating limits for variable SCR; X/R = 10, X t = 0.2 p.u.

1000

SCR = 30

–400 –1000 –800 –600 –400 –200 0 200 Pg (MW)

400

600

800

1000

1

X/R = 2

500

0.95

X/R = 5 X/R = 10 X/R = 20

0.9 0

Igq (A)

Md

0.85 0.8

0.75 0.7

X/R = 20 X/R = 10 X/R = 5

–500

–1000

X/R = 2

0.65

–1500 –0.15

–0.1

–0.05

0

0.05

Mq

0.1

380

X/R = 20 X/R = 10 X/R = 5

–500

0

500

Igd (A)

1000

1500

1000 800

400 200 0

X/R = 2

320

–1000

600

350

330

–1500

X/R = 2

360

340

0.2

X/R = 20 X/R = 10 X/R = 5

370

VgII (kV)

0.15

Qg (MVar)

0.6 –0.2

X/R = 20

X/R = 10

–200

X/R = 5

X/R = 2 310 –1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

800

Figure 18.8 VSC operating limits for variable X/R; SCR = 10, X t = 0.2 p.u.

1000

–400 –1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

800

1000

1 400 0.95 200 0.9

Xt = 0.05 p.u.

Xt = 0.3 p.u. Xt = 0.2 p.u. Xt = 0.1 p.u. Xt = 0.05 p.u.

0

0.85 –200

Igq (A)

Xt = 0.1 p.u.

Md

0.8 0.75 0.7

Xt = 0.2 p.u.

–1000 –1200

Xt = 0.3 p.u.

0.55 0.5

–600 –800

0.65 0.6

–400

–1400 –0.25 –0.2 –0.15 –0.1 –0.05

–1600 –1500

0 0.05 0.1 0.15 0.2 0.25 Mq

380

–1000

–500

0 Igd (A)

500

1000

1500

1000

375

365 360

600

Qg (MVar)

VgII (kV)

800

Xt = 0.3 p.u. Xt = 0.2 p.u. Xt = 0.1 p.u. Xt = 0.05 p.u.

370

355 350

400

200

Xt = 0.05 p.u. Xt = 0.1 p.u. Xt = 0.2 p.u. Xt = 0.3 p.u.

345 0

340 335

–200

330 –1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

Figure 18.9 VSC operating limits for variable X t ; SCR = 10, X/R = 10.

800

1000

–1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

800

1000

262

18 Two-level VSC HVDC Phasor-domain Interaction

higher transformer reactance has an impact on the system dynamics since open loop gain decreases as the reactance is increasing.

18.9 Influence of Converter Control Modes Figure 18.10 shows the operating curves with closed loop HVDC control. The two commonly used control modes are studied: constant reactive current and constant PCC voltage. Note that operation with I g = 0, gives a unity power factor. If the converter controller cannot achieve the required PCC voltage, then it settles on either M limit or I g limit. When constant reactive current mode is used, the AC voltage varies as the active power changes. Also, depending on the reactive current reference, the converter may not be able to achieve maximum active power. In constant voltage mode the converter will commonly hit the modulation index limit at higher active power, unless lower PCC voltage reference is selected.

18.10 Operation with Very Weak AC Systems Figure 18.11 shows the operating curves for different control modes when the AC system is very weak (SCR = 1.8). It can be seen that many operating restrictions are present. The main concerns are the variations in PCC voltage and limitations on the power transfer. PCC voltage varies significantly unless voltage control is used. The maximum active power import is limited to 940 MW and this is achieved for a very narrow reactive power range. If reactive current is zero, the maximum import power is only 830 MW, but AC voltage would in such a case drop to 310 kV (0.83 p.u.), which is unacceptable. Therefore, it is not possible to operate with SCR = 1.8 and I gq = 0. Lower SCR can be achieved if current is not in phase with voltage, which is analysed in more depth in Section 18.1. In practice the converter will need to use a large portion of rated current to supply reactive power in order to stabilise the voltage on a weak AC system. This study assume that the remote source voltage is constant (V s = const.). In practice this voltage may vary in particular with weak AC networks. Lower grid voltage will further reduce power exchange capability. Example 18.1 Consider the VSC HVDC terminal as shown in Figure 18.12. Assume that the PCC bus voltage is controlled to 275 kV. (1) Determine converter AC voltage for the following rectifier operating point: Pg = 500 MW, Qg = 100 MVAr. Refer the converter voltage to the grid side and determine the percentage voltage swing. (2) Determine the converter AC voltage for the maximum power export: Pg = −500 MW, Qg = −100 MVAr. Refer the converter voltage to the grid side and determine the percentage voltage swing. (3) Assume that the phase reactance is increased four times because of DC fault problems. Determine the maximum AC voltage swing.

1 0.95

400

Vgll = 375 kV

Igq = 100 A Igq = 0 A Igq = –100 A

Limit on M Vgll = 375 kV

200

Vgll = 370 kV Vgll = 365 kV

0.9

Vgll = 365 kV

–200

Constant reactive current

–400

Md

Igq (A)

0.85

0.8

Igq = 100 A Igq = 0 A Igq = –100 A

Vgll = 370 kV

0

Constant voltage

–600 –800

–1000

0.75

–1200 0.7 0.65 –0.2

–0.15

–0.1

–0.05

0

0.05

Mq

0.1

0.15

–1600 –1500

0.2

370

–500

0

500

Vgll = 370 kV

Igq = 1 Igq = 00 A Igq = 0 A –100 A

Vgll = 365 kV

360 355 350

800

Limit on lg

400

Constant voltage 200

Vgll = 365 kV

Constant reactive current Igq = –100 A Igq = 0 A Igq = 100 A

Vgll = 370 kV

340

0

335 0

1500

600

345

330 –1000 –800 –600 –400 –200

1000

1000

Vgll = 375 kV

Qg (MVar)

Vgll (kV)

365

–1000

Id (A)

380 375

Limit on lg

–1400

200

Pg (MW)

400

600

800

1000

Vgll = 375 kV

–200 Limit on M

–1000 –800 –600 –400 –200

Figure 18.10 VSC operating diagrams in different control modes; SCR = 10, X/R = 10, X t = 0.2 p.u.

0

200

Pg (MW)

400

600

800

1000

Vgll = 375 kV

400

Pg < 0, Qg < 0

200

1 0.9

I gq

=0

Pg > 0, Qg < 0

0

Limit on M

0.8

Limit on M

Pg < 0, Qg < 0

Pg > 0,

Igq = 0 Qg < 0

Vgll = 375 kV

–200 –400

Pg < 0, Qg > 0

Pg > 0, Qg > 0

0.6

Igq (A)

Md

0.7

–600 –800

0.5

Pg < 0, Qg > 0

Pg > 0, Qg > 0

–1000 0.4 –1200 0.3 0.2 –0.2

–1400 –0.15

–0.1

–0.05

0

0.05

Mq

0.1

0.15

400

Vgll = 375 kV 350

= 0 Pg < 0, Qg < 0 I gq

0.2

500

Pg > 0, Qg < 0 Ig q= 0

400

250

–500

0

500

1000

1500

300

Qg (MVar)

VgII (kV)

Pg > 0, Qg < 0

–1000

Igd (A)

Limit on M

300

Pg < 0, Qg > 0

–1600 –1500

200

Pg > 0, Qg > 0

Pg < 0, Qg > 0

V

gll

100

=3

0

–100

75

kV

Igq = 0

Pg > 0, Qg < 0

Pg < 0, Qg < 0

200

Limit on M

–200 150 –1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

800

1000

–300 –1000 –800 –600 –400 –200

0

200

Pg (MW)

400

600

Figure 18.11 VSC converter operating diagrams in different control modes with very weak AC system; SCR = 1.8, X/R = 10, X t = 0.2 p.u.

800

1000

18.10 Operation with Very Weak AC Systems

500 MW 100 MVAr

275 kV AC, 3 Ф 50 Hz

Rs

PCC

Ls

Li = 0.03 H

SCR = 24, X/R = 12

600 MVA 275 V/385 kV Xt = 11%

Vg

5 mH 296 μF

296 μF 5 mH

Figure 18.12 VSC HVDC terminal in Example 18.1.

Solution (1) Converter AC voltage for the rectifier. ) ( 275,0002 2 + 2𝜋 × 50 × 0.03 × (275∕385) 100e6 0.11 Qg (Xt + Xi ) 600e6 Vcd = − + Vg = Vg 275,000 +275,000 = 263 kV Vcq = −

Pg (Xt + Xi ) Vg Vc =

=−

) ( 2 2 + 2𝜋 × 50 × 0.03 × (275∕385) 500e6 0.11 275,000 600e6 275,000

= −60 kV

√ √ 2 2 Vcd + Vcq = 60, 0002 + 263, 0002 = 269.76 kV

ΔV % =

Vg − V c Vg

100 =

275 − 269.76 kV 100 = 1.7% 275 kV

(2) Converter AC voltage for maximum power export. ) ( 2 2 + 2𝜋 × 50 × 0.03 × (275∕385) −100e6 0.11 275,000 Qg (Xt + Xi ) 600e6 Vcd = − + Vg = Vg 275,000 + 275,000 = 287 kV Vcq = −

Pg (Xt + Xi ) Vg Vcmax =

=−

) ( 2 2 + 2𝜋 × 50 × 0.03 × (275∕385) −500e6 0.11 275,000 600e6 275,000

= 60 kV

√ √ 2 2 Vcd + Vcq = 60, 0002 + 287, 0002 = 293.3 kV

ΔVmax % =

Vg − Vcmax Vg

100 =

275 − 293.3 kV 100 = −3.2% 275 kV

The above voltage swing is quite small. (3) The above voltage calculation is repeated with Li = 0.12 H: ΔV % = 1.9% ΔVmax % = −6.6% The total voltage swing is 8.6% which is acceptable, but should be taken into account when dimensioning equipment.

265

266

18 Two-level VSC HVDC Phasor-domain Interaction

Example 18.2 A 200 kV, 1000 A, HVDC is being considered as an interconnection between two AC systems and power flow is unidirectional. The HVDC converter ratings are 200 MVA. The 320 kV, 50 Hz inverter grid draws a total of 150 MVA at a 0.75 power factor, while rectifier VSC draws the power requirement from the 230 kV, 60 Hz network at unit power factor. Sinusoidal pulse width modulation switching is used with a 1350 Hz triangular carrier wave. The 1000 mm2 copper DC cable has resistance per km Rocukm1000 = 1.39 × 10−2 Ω km−1 , and the total distance between terminals is 50 km. Determine: (1) transformer ratio for rectifier and inverter transformers, assuming that transformer leakage reactances are X t50Hzp.u. = 0.1 p.u. and X t60Hzp.u. = 0.16 p.u.; (2) DC cable losses; (3) active and reactive power delivered at the inverter side; (4) active and reactive power drawn at the rectifier side. Solution (1) It is assumed that inverter station controls DC voltage: Vdc50Hz = 200 kV √ Vdc50Hz √ = 70.71 kV, Vc50Hz LL = 3Vc50Hz = 122.47kV 2 2 V2 320, 0002 Xt50Hz = Xt50Hzp.u. 50HzLL = 0.10 = 51.2 Ω St 200,000, 000 S 200 MVA =√ = 360.84 A IL50Hz = √ 50Hz 3 × V50HzLL 3 × 320 kV Vc50Hz =

Vg50Hz

est

Vg50Hz

LL est

= Vc50Hz + jX tr IL50Hz √ = 320∕ 3 + j51.2 × 360.84 = 184.75 + j18.475 kV = 185.671 kV =

√ 3Vg50Hz

est

= 321.59 kV

Transformer turns ratio: 322/122 = 2.63. Rectifier station Rdc = 2Rocu lc = 2 × 1.39 × 10−2 × 50 = 1.39 Ω Vdc60Hz = Vdc50Hz + Rdc Idc = 200,000 + 1.39 × 1000 = 201.39 kV √ Vdc60Hz √ = 71.2kV , VcLL 60Hz = 3V60Hz = 123.32 kV 2 2 2 Vg60Hz LL 230, 0002 = 0.16 Xt60Hz = Xt60Hzp.u. = 42.32 Ω St 200,000, 000 S 200 MVA =√ = 502.04 A IL60Hz = √ 60Hz 3 × Vg60HzLL 3 × 230 kV

Vc60Hz =

18.10 Operation with Very Weak AC Systems

Vg60Hz

= Vg60Hz − jX t60Hz IL √ = 230∕ 3 − j42.32 × 502.04 = 132.79 − j21.246 kV = 134 kV √ Vg60HzLL est = 3Vg60Hz est = 233 kV est

Transformer ratio: 233/123 = 1.89. (2) Losses 2 Pdcloss = Idc Rdc = 10002 × 1.39 = 1.39 MW = 0.7%

(3) The total active power at the inverter is P50Hz = S50Hz × pf 50Hz = 150 MVA × 0.75 = 112.5 MW The inverter reactive power delivered √ √ 2 2 Q50Hz = S50Hz − P50Hz = 1502 − 112.52 = 99.21 MVAr (4) At rectifier side: P60 Hz = 112.5 MW + 2.78 MW = 115.28 MW, Q60 Hz = 0. Example 18.3 A ±150 kV VSC HVDC cable transmission system connects 230 kV, 60 Hz three-phase AC system to a 220 kV, 50 Hz three-phase AC system, some 100 km apart. The VSC converters are interfaced by a Δ–Y transformer with 25 mH of leakage reactance. The DC cable is rated at 1000 A with a total resistance of 2 Ω. Consider the operating point where the 60 Hz inverter grid receives a total of 300 MVA at a 0.85 power factor, while the rectifier VSC draws the power requirement from the 50 Hz network at unit power factor. Determine the phasor diagram for (1) the 60 Hz receiving end (2) the 50 Hz transmitting end. Solution (1) The total active power at the inverter is P60Hz = S60Hz × pf 60Hz = 300 MVA × 0.85 = 255 MW The 60 Hz reactive power is: √ √ 2 2 Q60Hz = S60Hz − P60Hz = 3002 − 2552 = 158 MVAr The 60 Hz AC line current is S 300 MVA =√ IL60Hz = √ 60Hz = 753.1 A 3 × V60HzLL 3 × 230 kV The reference 60 Hz phase voltage is Vg60Hz =

Vg60HzLL 230 kV = √ = 132.8 kV √ 3 3

The angle between the line current and the phase voltage is 𝜑 = cos−1 0.85 = 31.8∘

267

268

18 Two-level VSC HVDC Phasor-domain Interaction

60 Hz receiving end phasor diagram 136.67 kV 2.5° –31.8°

VXL = 7.1 kV

VLN = 132.8 kV

50 Hz transmitting end phasor diagram IL = 676.8 A

VLN = 127 kV

–2.38°

IL = 753.1 A

VXL = 5.3 kV 127.11 kV

Figure 18.13 Phasor diagram in Example 18.3.

The transformer reactance at the 60 Hz system is X L60Hz = 2𝜋fL = 2𝜋 × 60 × 0.025 = 9.42 Ω The 60 Hz converter line to neutral voltage is Vc60Hz = Vg60Hz + jX L60Hz IL60Hz = 132.8 + j9.42 × 753.1∠ − 31.8∘ = 132.8kV + 7.1kV ∠58.2∘ = 136.54 + j6.03 = 136.67kV ∠2.5∘ (2) The ±150 kV DC link has a pole to pole voltage of 300 kV. The DC current is: 255 MW = 850 A 300 kV The DC cable voltage drop is: V Δdc = I dc × Rdc = 850 × 2 = 1.7 kV The VSC DC voltage at the 50 Hz transmitting end is V dc50Hz = 300 + 2 × 1.7 = 303.4 kV The pole DC voltage is 151.7 kV. The 50 Hz VSC power delivered to the DC link is Idc =

Pdc = Idc Vdc50Hz = 850 × 303.4 = 257.9 MW With unity power factor at the 50 Hz sending end, P = S, and the line current is S 257.9 MVA IL50Hz = √ 50Hz =√ = 676.8 A 3 × V50HzLL 3 × 220 kV Vg50HzLL 220 kV Vg50Hz = √ = √ = 127 kV 3 3 The transformer reactance at the 50 Hz end is X L50Hz = 2𝜋fL = 2𝜋 × 50 × 0.025 = 7.85 Ω The VSC line to neutral voltage at the 50 Hz is Vc50Hz = Vg50Hz − jX t50Hz IL50Hz == 127 kV − j7.85 × 676.8 = 127 − j5.3 kV = 127.11 kV Figure 18.13 shows the phasor diagram for both AC systems.

269

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System 19.1 Basic Equations and Steady-state Control Figure 19.1 shows the topology of one-phase modular multilevel converters (MMCs) with n + 1 levels. The labels for individual phases are omitted for simplicity, and the whole study is done per phase, assuming a symmetrical and balanced system. The converter leg consists of positive and negative arms (in power electronics two ‘arms’ make one ‘leg’). Each arm comprises a series chain of n-cells and each of these can assume half- or full-bridge topology. The full-bridge topology will introduce some modelling changes at system level which are analysed in Chapter 20. There are two interfacing inductors Larm , which are necessary to interface the two arms which have different AC waveforms. Rarm represents the internal resistance of the inductor and the switches. The study approach with a two-level voltage source converter (VSC) in Figure 17.1, which is based on a single voltage source per phase power and current source for DC side, cannot be used with MMC converters. The MMC converter model requires two AC voltage sources (vP and vN ) per phase that are individually controlled and provide a direct link between AC and DC sides. The replacement of an arm with a controlled voltage source is the basic principle in average value MMC modelling. This average value approach is justified when the number of cells is high and the voltage increment by switching one cell is small. Higher harmonics, caused by cell switching and cell voltage variations, are neglected. Each of the AC voltages, vP and vN , represents instantaneous voltage across n series connected cells in one arm. The number of cells in ON state (inserted capacitors) at any instant depends on the control signal and can vary between 0 and n. The modulation index for an arm in a half-bridge MMC (mp for positive and mn for negative arm) is defined as the ratio of the number of inserted cells nON and the total number of cells in the arm n: n mP = ONP , 0 < mP < 1 (19.1) n n mN = ONN , 0 < mN < 1 (19.2) n The number of inserted cells will be a discrete number, but considering the large number of cells in a high voltage direct current (HVDC) MMC converter, it can be assumed that the number of inserted cells is a continuous function. It is important to observe the limits on the modulation indices since they represent physical restrictions. High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

–

+

–

Cell n CCell

Rdc

Rarm

0 Vdc

Ip

Larm Ig

In

Larm

Equivalent DC circuit

Vp

Lt Vg

Rarm 1/2 Vdcs

+

Vcell

Cell n+1 Ccell Cell n+2 Ccell

V0

Vn Vc

Rarm Larm Lt

Ip In Rarm Larm

Ig

Equivalent AC circuit Rarm/2 Larm/2

Vn

Vce

Cell 2n Rdc

Larm Rarm

+ –

Vp

CCell

Larm Rarm

–

1/2 Vdcs

Cell 2

0.5 Vdcs

+

CCell

0.5 Vdcs

V0

–

+

+

Cell 1

VCell

Idc/3 0.5 VPM

Rdc

Idc/3

0.5 VNM

Rdc

–

270

Vc

Lt Ig

Simplified AC circuit

Ccell

Figure 19.1 One phase of an n + 1 level modular multilevel converter.

The arm modulation indices will be derived considering the required AC voltage V c . This AC voltage depends on the control signal m which is a sine function synchronised with the reference coordinate frame using a phase locked loop, and can be expressed similarly to two-level VSC converters: m = M cos(𝜔t + 𝜃m )

0 < M < 1, −1 < m < 1

(19.3)

The control signals for each arm are then derived in the following way: 1 (19.4) mP = (1 − M cos(𝜔t + 𝜃m )), 0 < mP < 1 2 1 mN = (1 + M cos(𝜔t + 𝜃m )), 0 < mN < 1 (19.5) 2 The instantaneous arm voltage will be a multiple of cell voltage and the number of inserted cells: vP = vcell nONP

(19.6)

vN = vcell nONN

(19.7)

19.1 Basic Equations and Steady-state Control

Substituting (19.1) and (19.2) in (19.6) the arm voltages, vP , vN can be represented as: vP = mP vM P

(19.8)

vN = mN vM N

(19.9)

The voltages vM , vM are the maximal available arm voltages (when all cells are ON), P N or also called sum arm voltages. They are equivalent to the sum of all cell voltages in an arm, or since it is assumed that the cell balancing controller is active, cells have equal voltage vM = vM = nvcell . Replacing (19.4) in (19.8) and (19.5) in (19.9) P N 1 M (19.10) v − vM P M cos(𝜔t + 𝜃m ), 2 P 1 + vM (19.11) vN = vM N M cos(𝜔t + 𝜃m ), 2 N The above two arm voltages have DC and AC components. By analysing the equivalent DC circuit diagram in Figure 19.1, considering that there are three phases, and using (19.10) and (19.11), the DC equation for one leg is obtained: vP =

1 M 1 M Idc (19.12) v + vN + 2R 2 P 2 3 arm In the derivation of the basic model Rarm can be neglected. Assuming also that the system is balanced, the above equation gives: Vdc =

M vM P = vN ≈ Vdc

(19.13)

From the above equation, the voltage of each MMC cell is derived (considering that there are n balanced cells in each arm): 1 (19.14) V , n dc Substituting (19.14) in (19.8) and (19.9), the range for arm voltages is obtained: Vcell =

0 < vP < Vdc

(19.15)

0 < vN < Vdc

(19.16)

The converter AC voltage vc is of high interest for system designers, but it cannot be directly derived using converter controls because of interfacing arm inductors. Instead, an equivalent MMC AC source voltage for one leg (vce ) is introduced, as illustrated in Figure 19.1: } { v − vP 1 1 vce = N (19.17) , − Vdc < vce < Vdc 2 2 2 This is some imaginary voltage that replaces two voltage sources per leg with a single one, and which enables simple MMC converter model connection with the AC grid model, as analysed later in Section 19.6. Replacing (19.10) and (19.11) in (19.17), the equivalent MMC converter AC voltage is obtained: vce =

1 mV dc 2

(19.18)

271

272

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

This is the first simplification which gives a familiar format resembling AC voltage of a two-level VSC converter. Alternatively, the arm voltages can be expressed using (19.10) and (19.11) in (19.17) as: V vN = vce + dc 2 V vP = −vce + dc (19.19) 2 The grid current is obtained by inspection from Figure 19.1: (19.20)

ig = iP + iN

Rather than using arm currents, it is more convenient to work with differential currents as will be shown later with detailed modelling. The differential or circulating current idiff flows through the two arm inductors of each phase, and can be expressed using arm currents as: (19.21)

idiff = (iP − iN )∕2,

Therefore from (19.20) and (19.21) it is possible to obtain a link between arm currents, phase current and differential current: iP = ig ∕2 + idiff

(19.22)

iN = ig ∕2 − idiff

(19.23)

The differential current idiff can be visualised as an equivalent current in one phase, which will sum with the other two phases to build the DC current: Idc = idiff a + idiff b + idiff

c

(19.24)

Figure 19.2 shows the basic variables for one phase of the MMC converter in Figure 19.1 for a typical 1 GW, 640 kV MMC converter (harmonic suppression control is not used but cell balancing control is). It is seen that the arm currents (ip and in ) are distorted because of the significant second harmonic on the circulating current. It will be demonstrated in later sections that the second harmonic is the result of multiplication of two sine signals: the sine variation of number of capacitors in the current path and the sine grid current. This second harmonic component not only deforms the arm currents, but also increases the cell voltage ripples and increases losses. However the circulating current harmonics have no impact on the connecting AC and DC system currents, since second harmonics will cancel when summed in star-connected three-phase balanced systems as seen in (19.24). Special controls for elimination of circulating current harmonics are discussed in later sections. The arm voltages (vp and vn ) are 50 Hz sine waveforms phase shifted by 180∘ while their sum is approximately DC voltage V dc .

19.2 Steady-state Dimensioning The above MMC model will be used to derive peak current stress in MMC semiconductors. Considering (19.22) and (19.23), it is evident that MMC valves will have AC and

1.5 1

Idc

Ip

1.6

In

1.4

Idiff

1.2 1 I (kA)

I (kA)

0.5 0

0.8 0.6 0.4

–0.5

0.2 –1

0 –0.2

–1.5 2.2

2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29

–0.4 2.2

2.3

700

2.5 2

2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29

2.3

time (s)

time (s)

Ig

Vp

Vn

Vdc

600

1.5 500

1 V (kV)

I (kA)

0.5 0 –0.5 –1

400 300 200

–1.5 100

–2 –2.5 2.2

2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 time (s)

2.3

Figure 19.2 MMC converter basic variables. Circulating current control is not used.

0 2.2

2.21 2.22 2.23 2.24 2.25 2.26 2.27 2.28 2.29 time (s)

2.3

274

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

DC component currents. In order to derive the AC current component, DC power is equated with the active AC power: √ 3Vce Ig cos 𝜑 = Idc Vdc (19.25) where 𝜑 is power factor angle. Replacing the converter AC voltage from (19.18) in (19.25) it can be obtained that the peak AC grid current is: Igpeak =

4Idc 3M cos 𝜑

(19.26)

The DC current in each arm is I dc /3, considering (19.24). Therefore using (19.26) and replacing in (19.22) and (19.23), it is possible to obtain peak arm current: IPpeak = INpeak =

2Idc I + dc 3M cos 𝜑 3

(19.27)

From this equation and considering the common case cos𝜑 ≈ 1 and M ≈ 1, it is deduced that the peak valve current I Ppeak will be similar to the MMC DC current I dc . Equation (19.27) also illustrates that the peak AC current in valves is at least twice the magnitude of the valve DC current and therefore valve current will have both negative and positive intervals. This is important since cell capacitor balancing is possible only if cell current has both positive and negative intervals. Example 19.1 Determine the current rating and the number of 4 kV insulated gate bipolar transistor (IGBT) switches required for a 700 MVA, 100 MVAr, 500 kV, half-bridge MMC HVDC converter connecting to 400 kV AC system. Solution The DC power (and active power) is: √ √ Pdc = S2 − Q2 = 7002 − 1002 = 693MW The DC current is: P 693MW Idc = dc = = 1386A Vdc 500kV Using (19.24) the DC current in each arm is: Idc 1386A = = 461.88A 3 3 The MMC AC voltage will be similar to the two-level VSC AC voltage, and assuming that the modulation index is 0.9: √ √ Vac = 0.9 × 0.5 × Vdc 3∕2 = 0.9 × 0.5 × 500kV 3∕2 = 276kV Idcigbt =

The MMC AC current (RMS): S 700MVA Iac = √ =√ = 1467A 3Vac 3276kV Using (19.22) the peak of AC current component in each arm is: √ √ 2Iac 21467A = = 1037A Iacigbt = 2 3

19.3 Half Bridge MMC Non-linear Average Dynamic Model

Therefore, the required current rating of IGBTs is: Iigbt = Idcigbt + Iacigbt = 461.88A + 1037A = 1499A The number of cells in each arm is (assuming a safety factor of 2): Narm = 2

Vdc 500kV =2 = 250 Vigbt 4kV

The total number of cells is: Ncell = 6Narm = 6 × 250 = 1500 The total number of IGBTs is: Nigbt = 2Ncell = 2 × 1500 = 3000

19.3 Half Bridge MMC Non-linear Average Dynamic Model The MMC VSC HVDC will be modelled using averaging principles with the aim of developing accurate non-linear dynamic models in ABC and DQ frames suitable for control design and stability studies. The average value modelling in the ABC frame is most often used for system studies on electromagnetic transient simulators, and it will be addressed first. From Figure 19.1 the dynamic voltage equations for positive and negative poles of DC circuit are: ( ) V d (19.28) i − vP vc = dc + Rarm + Larm 2 dt P ) ( V d (19.29) vc = − dc + Rarm + Larm iN + vN 2 dt Also, considering the current loop driven by the DC voltage: ( ) d idiff = (iP − iN )∕2, vP + vN − 2 Rarm + Larm idiff − Vdc = 0, dt

(19.30)

The MMC arms can be replaced by an equivalent capacitor. Considering that capacitors are inserted according to the sinusoidal control signals, the equivalent dynamic equations for the positive and negative arms are: dvM P

iP Carm ∕mP iN =− dt Carm ∕mN

dt dvM N

=

(19.31) (19.32)

where C arm is a constant, representing total capacitance in the arm when all capacitors are connected (when all cells are ON): Carm = Ccell ∕n

(19.33)

In the above equation C cell is a single cell capacitance. The expressions C arm /mP and C arm /mN are the instantaneous capacitance values in positive and negative arms,

275

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19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

respectively. Therefore using (19.22) (19.23), (19.31) and (19.32), the differential equations for maximal arm voltages can be obtained: ( ) ig dvM mP P idiff + = (19.34) dt Carm 2 ( ) ig dvM m N = N idiff − (19.35) dt Carm 2 In each of these two equations there is multiplication of two sine signals (ig and m), which will produce DC and a second harmonic, as seen in Figure 19.2. The second harmonic voltage generates circulating differential current and therefore this model will accurately present characteristic even-order harmonics in an MMC converter. The MMC AC voltage dynamic equation can be derived by using the equivalent AC model in Figure 19.1, and paralleling the passive parts of the positive and negative arms: dig 1 1 (19.36) L + vce vc = ig Rarm + 2 dt 2 arm The above model is sufficiently accurate for all power flow and dynamic studies. The second harmonic circulation is also properly represented. The limitations of this MMC model are: very high order harmonics caused by switching individual cells are not represented; cell-level events (faults) cannot be represented; capacitor balancing is not represented; as with all ABC frame models, it uses oscillating AC variables and supports only time domain simulations – studies with multiple variations in parameters/gains are difficult; • phasor modelling is not possible; • linearisation is not possible with oscillating signals in ABC frame. • • • •

The above dynamic expressions for the equivalent arm voltages facilitate building per-arm MMC average model, which is shown schematically in Figure 19.3. The arm voltage expression uses only arm current (ip or in ) and phase control voltage m = Mcos(𝜔t + 𝜃 m ) as the inputs.

19.4 Non-linear Average Value Model Including Blocked State Similarly, as with two-level VSC, the MMC converter may be operated in the blocked state. This could occur under high currents (DC faults for example) or in other conditions like start-up and cell charging. Figure 19.4 shows the equivalent circuit of a blocked half-bridge MMC. It is seen that a blocked MMC converter becomes a diode bridge similarly to two-level VSC. However, the cell capacitors cannot discharge if DC voltage is low, which is an advantage compared with two-level topology. The cell capacitors will maintain charge in the case of transient DC disturbances/faults, and this will result in less current stress (inrush current) and faster responses during the system recovery. It is also seen from this model

19.4 Non-linear Average Value Model Including Blocked State

Idc Vp

Rarm Ip In

+

Larm

1

Ig

Lt

PCC

1 +– Mcos(ωt+θm)

0.5

Vc

++

0.5

1

Vg

X

mp

0 1

Larm

mn

0

Rarm

–

Vdc /2

mp ip Carm V M p

Ip

+ –

Vdc /2

In

X

Vp

Vn

mN iN VNM Carm

Vn

Figure 19.3 One phase of an average value non-linear dynamic model for MMC converter.

Vdc /2 Lt

Larm

Larm

Larm

Larm

Larm

Larm

Lt Lt Vga Vgb Vgc

Vdc /2

Figure 19.4 Equivalent circuit of a blocked HB MMC.

that half-bridge (HB) MMC cells can be charged in the blocked state from either the AC or the DC side, as discussed further in the next section. Considering the above analysis of the MMC blocked state it is possible to derive an MMC average model that includes both normal operation and blocked state, as shown in Figure 19.5. The converter blocking control logic is also shown. In deblock state this model is identical to the model in Figure 19.3. If the model is in the block state, then this model is identical to model in Figure 19.4. There are two diodes

277

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

Idc

Ipc Dpa

Block

Dpb

DeBlock

Vp

1

+ Rarm

–

Ip In

Lt Vc

Larm

+

+ +

Block 1

0.5

m 0 DeBlock p Block 1 1 m

n

0.5

0 DeBlock

PCC

X

Inc

Vg

X

Vp

Vn

mN iNc VNM Carm

Rarm Dna

Inc Dnb

Idc Block

Vdc /2

1

Larm Ig

DeBlock

Vdc /2

mp iNc Carm V M p

Ipc

1 +– Mcos(ωt+θm)

–

278

2pu

comparator Block

Vdc 0.8pu

Vn

comparator

OR

Figure 19.5 HB MMC average model including blocked state.

in each arm: diodes Dpb, Dnb represent diode bridge and enable current flow from the AC to the DC side for low DC voltage, while diodes Dpa and Dna enable the charging of cell capacitors. Note that diodes Dpb, Dnb do not interfere in the deblock state since the arm voltages cannot assume negative values.

19.5 HB MMC HVDC Start-up and Charging MMC Cells The above average model with blocked state is also suitable for the study of HVDC start-up. It enables understanding of the impact of AC and DC side voltages on the cell voltage in blocked state, and similarly transfer of energy from MMC cells to the AC or DC sides. A (V dc = 640 kV, P = 1000 MW, V ll = 370 kV, C cell = 10 mF, Larm = 75 mH, V cell = 2 kV, X t = 0.1 p.u.) MMC HVDC test system is considered with each MMC in staged normal and blocked states in order to illustrate the impact of the AC and DC sides on cell/arm voltage. For illustration purposes, the HVDC start-up sequence is deliberately prolonged, as shown in Table 19.1. The maximal arm voltages and arm currents on the rectifier and inverter HB MMC as well as DC voltage and power are shown in Figure 19.6. Initially prior to 0.1 s, the inverter MMC cells are charged from the AC side through a starting resistor to avoid large inrush current. At 0.1 s the cell voltage is sufficiently high and the charging resistor is bypassed. While the blocked inverter is connected to the AC grid its cells will charge to the peak line–line voltage of 521 kV (approximately

19.6 HB MMC Dynamic DQ Frame Model and Phasor Model

Table 19.1 Cell charging for HVDC start-up in Figures 19.6 and 20.4. Time (s)

Event

Inverter MMC

Rectifier MMC

0.0

Inverter AC CB closed

Charging from AC side through 100 Ω resistor. Cells charged to 0.8 p.u.

Charging from DC side. Cells charged to 0.4 p.u.

0.1

Inverter bypass AC CB closed

Direct charging from AC side. Cells charged to 0.8 p.u.

Charging from DC side. Cells charged to 0.4 p.u.

0.3

Inverter MMC deblocked

DC voltage control. Cells charged to 1 p.u.

Charging from DC side Cells charged to 0.5 p.u.

0.5

Rectifier AC CB closed

DC voltage control

Charging from AC side through 100 Ω resistor. Cells charged to 0.8 p.u.

0.6

Rectifier bypass AC CB closed

DC voltage control

Direct charging from AC side. Cells charged to 0.8 p.u.

0.7

Rectifier MMC deblocked

DC voltage control

Power control. Cells charged to 1 p.u.

80% of DC voltage). At this cell voltage it is possible to deblock MMC converter without concerns for inrush current. While inverter is charging from the AC side, the DC line voltage will follow inverter MMC arm voltage. Therefore, the blocked rectifier is being charged from the DC side. However, the rectifier MMC cell voltage will rise to only 50% of the DC voltage while charging from the DC side. This occurs since the two arms are connected in series across DC voltage in blocked state, as seen in Figure 19.4. At 0.3 s the inverter is deblocked and cell voltage rapidly rises to nominal value. Blocked rectifier cell voltage charges to 0.5 p.u. At 0.5 s rectifier AC circuit breaker (CB) closes and blocked rectifier cells charge from the AC side to 0.8 p.u. At 0.6 s the cell voltage is sufficiently high and charging resistor is bypassed. At 0.7 s the rectifier is deblocked and it resumes normal power control operation.

19.6 HB MMC Dynamic DQ Frame Model and Phasor Model 19.6.1

Assumptions

The DQ frame modelling is essential for power flow, control design and dynamic studies. First, considering modelling complexity, the static model will be derived in the DQ frame, which is the basis for the MMC phasor model required for power flow studies. At a later stage, the full dynamic DQ model will be derived. Similarly, as with previous DQ frame modelling, it is assumed that the system is symmetrical and balanced. The control signal is first assumed to contain only the fundamental component: m = M cos(𝜔t + 𝜑m ) = Md cos(𝜔t) − Mq sin(𝜔t)

(19.37)

where Md and Mq are corresponding components in the DQ frame rotating at fundamental frequency (𝜔). Considering the definition for arm control signals in (19.4) and

279

800

Rectifier MMC deblocked VUARM

600

VLAIM

VLARM

Rectifier AC CB closed Cell charging from AC side (converter deblocked) 400

Cell charging from AC side (diode bridge) Cell charging from DC side (converter deblocked)

200

Maximal arm voltage (kV)

Maximal arm voltage (kV)

800

VUAIM 600

Cell charging from AC side (converter deblocked)

400

Inverter MMC deblocked Cell charging from AC side (diode bridge)

200

Cell charging from DC side (diode bridge) 0

0

0.2

0.4

0.6

Inverter AC CB closed

0.8

1

0

1.2

0

0.2

0.4

0.6

0.8

3

1200

2

1000

IUAI

DC voltage [kV]

Arm current (kA)

Pref

1

IUAR

0 ILAI

–1

ILAR

–2

1

1.2

(b) Inverter MMC phase a maximal arm voltages, VUAIM , VLAIM

(a) Rectifier MMC phase a maximal arm voltages, VUARM , VLARM

800

Vdcref

P

Vdc

600 400 200

–3

0 0

0.2

0.4

0.6

0.8

1

1.2

0

0.2

0.4

0.6

0.8

time (s)

time (s)

(c) Rectifier and inverter MMC phase a arm currents

(d) DC Voltage and Power

Figure 19.6 MMC HVDC system staged start-up showing cell charging from AC and DC sides.

1

1.2

19.6 HB MMC Dynamic DQ Frame Model and Phasor Model

(19.5), they will contain further zero sequences Mp0 and Mn0 , and can be represented as 1 (1 − M cos(𝜔t + 𝜑m )) = MP0 + MPd cos(𝜔t) − MPq sin(𝜔t) 2 ( ( ) ) ( ) Mq Md 1 = + − cos(𝜔t) − − sin(𝜔t) 2 0 2 d 2 q

mP =

1 (1 + M cos(𝜔t + 𝜑m )) = MN0 + MNd cos(𝜔t) − MNq sin(𝜔t) 2 ( ( ) ) ( ) Mq Md 1 = + cos(𝜔t) − sin(𝜔t) 2 0 2 d 2 q

(19.38)

mN =

(19.39)

where subscripts ( )0 , ( )d and ( )q denote 0, d and q components in the coordinate frame DQ rotating at fundamental frequency, and all notations are elaborated in Appendices A and B. The main circuit variables are defined with reference to Figure 19.1 and considering basic equations in Section 19.1. The AC grid current is assumed to be a clean sine signal at fundamental frequency: ig = Ig cos(𝜔t + 𝜑i ) = Igd cos(𝜔t) − Igq sin(𝜔t)

(19.40)

while the differential current (in each phase) consists of zero sequence and the second harmonic idiff = Idiff0 + Idiff2 cos(2𝜔t + 𝜑idiff2 ) = Idiff0 + Idiffd2 cos(2𝜔t) − Idiffq2 sin(2𝜔t) (19.41) where subscripts ( )d2 and ( )q2 denote d and q components in the coordinate frame D2Q2 rotating at twice the fundamental frequency (2𝜔). The arm voltages are assumed to contain zero sequence, first and second harmonics: vP = VP0 + VPd cos(𝜔t) − VPq sin(𝜔t) + VPd2 cos(2𝜔t) − VPq2 sin(2𝜔t)

(19.42)

vN = VN0 + VNd cos(𝜔t) − VNq sin(𝜔t) + VNd2 cos(2𝜔t) − VNq2 sin(2𝜔t)

(19.43)

Similarly, for maximal arm voltages: M M M M M vM P = VP0 + VPd cos(𝜔t) − VPq sin(𝜔t) + VPd2 cos(2𝜔t) − VPq2 sin(2𝜔t)

(19.44)

M M M M M vM N = VN0 + VNd cos(𝜔t) − VNq sin(𝜔t) + VNd2 cos(2𝜔t) − VNq2 sin(2𝜔t)

(19.45)

The DC voltage V dc will be assumed as purely DC with no oscillating components. It is emerging from the above analysis that the MMC converter AC circuit modelling requires equations in three coordinate frames: zero sequence, DQ frame at fundamental frequency and D2Q2 frame at second harmonic, since the coordinate frames are closely interconnected and each coordinate frame plays an important role in both the power flow solution and system dynamics. The above signals will be substituted in the basic MMC equations from Section 19.1 and each equation will result in multiple equations in the three different coordinate frames, which should be separately analysed.

281

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19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

19.6.2

Zero Sequence Model

This section will analyse zero sequence MMC equations after all the variables from Section 19.6.1 are replaced in equations in Section 19.1. Beginning with (19.30), which is represented in the above considered three coordinate frames, the DC expression is first derived as: dI (19.46) 0 = 2Rarm Idiff0 + 2Larm diff0 − VP0 − VN0 + Vdc dt If only the static model is of interest, the derivative can be deleted: 0 = 2Rarm Idiff0 − VP0 − VN0 + Vdc

(19.47)

Since the system is assumed symmetrical and balanced, the above equation becomes: 1 VP0 = VN0 = Rarm Idiff0 + Vdc (19.48) 2 Equations (19.34) and (19.35) are expanded and separated into three coordinate frames using the DQ frame algebra from the Appendix B. The two resulting zero sequence equations are: (m ) P (19.49) i 0 = (mP idiff )0 + 2 g 0 (m ) N 0 = (mN idiff )0 − (19.50) i 2 g 0 Similarly, (19.49) and (19.50) give identical results in the DC coordinate frame: 1 1 1 − M I − M I (19.51) I 2 diff0 8 d gd 8 q gq Equation (19.51) gives the equation for zero sequence of differential current: 0=

1 1 (19.52) M I + M I 4 d gd 4 q gq The above model is valid for any phase, and since the DC current can be derived as the sum of three differential currents in (19.24), under the assumption of a symmetrical and balanced system it gives: Idiff0 =

3 3 (19.53) Md Igd + Mq Igq 4 4 It is evident that the above model in (19.52) and (19.53) is consistent with a two-level VSC converter model for DC current, as previously derived in (17.7). Idc = 3Idiff0 =

19.6.3

Fundamental Frequency Model in DQ Frame

This section will develop fundamental frequency MMC equations after all variables from Section 19.6.1 are replaced in equations in Section 19.1. The main equation for the maximal arm voltage (19.34) is first represented in the DQ frame using the methods given in Appendix B. The d-component of this equation is: ) ( ( ) ig dvM P Carm = (mP idiff )d + mP (19.54) dt 2 d d

19.6 HB MMC Dynamic DQ Frame Model and Phasor Model

Using further assumptions for the signals mp in (19.38) and ig in (19.40) and the rules for product of DQ signals, (19.54) becomes: Igd Mq M M M = − d Idiff0 − d Idiffd2 − Idiffq2 + (19.55) Carm 𝜔VPq 2 4 4 4 Therefore rearranging the above equation, the expression for maximal positive pole arm q-component voltage is: ( ) Igd Mq M M 1 M = Idiffq2 + − d Idiff0 − d Idiffd2 − (19.56) VPq Carm 𝜔 2 4 4 4 Similarly, the q component of (19.34) is: ( ) ( ) ig dvM P Carm = (mP idiff )q + mP dt 2 q

(19.57)

q

Using the same approach (19.57) is expanded as: Igq Mq Mq M M =− Idiff0 + Idiffd2 − d Idiffq2 + (19.58) −Carm 𝜔VPd 2 4 4 4 Therefore, from (19.58) the expression for maximal positive pole arm d-component voltage is: ( ) Igq Mq Mq Md 1 M − + − I I I (19.59) VPd = Carm 𝜔 2 diff0 4 diffd2 4 diffq2 4 The basic expression for zero sequence positive arm voltage is derived using the definition for zero sequence of a product from Appendix B: (mP vM P )0

M MP0 VP0

M MPd VPd

M MPq VPq

+ (19.60) 2 2 Replacing finally (19.56), (19.59), and (19.38), (19.39) in (19.60), the expression for the zero sequence of positive arm voltage becomes: ( ) M Md Igq Mq Igd Md Mq Idiffd2 (−Md2 + Mq2 )Idiffq2 VP0 1 + − + + VP0 = 2 𝜔Carm 16 16 8 16 VP0 =

=

+

(19.61) However, the immediate objective is to obtain a zero sequence of the maximal arm M in the above equation, which is required for the further derivations. Therevoltage VP0 fore equating (19.61) with (19.48) the expression for zero sequence of the maximal arm voltage is derived: ( ) Md Igq Mq Igd Md Mq −Md2 + Mq2 1 M − + Idiffd2 + Idiffq2 VP0 = 2Rarm Idiff0 + VDC − 𝜔Carm 8 8 4 8 (19.62) Considering the negative pole fundamental frequency modelling, a similar approach is used and the following equations are derived: ( ) Igd Mq Md Md 1 M VNq = + + − I I I (19.63) Carm 𝜔 2 diff0 4 diffd2 4 diffq2 4

283

284

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

M VNd =

( ) Igq Mq Mq M Idiff0 + Idiffd2 − d Idiffq2 + − Carm 𝜔 2 4 4 4 1

( M VN0

1 = 2Rarm Idiff0 + Vdc − 𝜔Carm

Md Igq 8

−

Mq Igd 8

+

M d Mq 4

Idiffd2 +

(19.64) −Md2 + Mq2 8

) Idiffq2 (19.65)

From the above derivations it is evident that (19.62) and (19.65) are identical, and M M hence VP0 = VN0 . At the final stage, the equations for the positive pole arm voltages in the DQ frame are obtained using (19.8): VPd = (mP vM P )d

(19.66)

Replacing (19.38), (19.39) in (19.66), the d component of positive pole arm voltage is found: 1 1 M 1 1 M M M + VPd − Md VPd2 − Mq VPq2 (19.67) VPd = − Md VP0 2 2 4 4 Similarly, it is possible to obtain the q component of positive arm voltage: 1 1 M 1 1 M M M VPq = − Mq VP0 + VPq + Mq VPd2 − Md VPq2 2 2 4 4

(19.68)

The negative pole arm voltages can also be derived in the same way: 1 M VM + 2 d N0 1 M = Mq VN0 + 2

VNd = VNq

1 M V + 2 Nd 1 M V − 2 Nq

1 M VM + 4 d Nd2 1 M VM + 4 q Nd2

1 M VM 4 q Nq2 1 M VM 4 d Nq2

(19.69) (19.70)

Therefore the fundamental frequency DQ MMC model is given by (19.62), (19.65), (19.67), (19.68), (19.69), and (19.70). The model also depends on the zero sequence variables and second harmonic variables and clearly there is a strong cross-coupling between the three coordinate frames.

19.6.4

Second Harmonic Model in the D2Q2 Coordinate Frame

This section will analyse D2Q2 variables in MMC equations after the variables from Section 19.6.1 are replaced in equations in Section 19.1. Equation (19.34) is first represented in the DQ frame rotating at 2𝜔, using the methods given in Appendix B. The d2-component of this equation is: ( ) ( ) ig dvM P Carm = (mP idiff )d2 + mP (19.71) dt 2 d2 d2

Using further assumptions for the signals mp in (19.38) and ig in (19.40) and the rules for product of DQ signals, (19.71) becomes: M 2Carm 𝜔VPq2 =

Md Igd Mq Igq 1 Idiffd2 − + 2 8 8

(19.72)

19.6 HB MMC Dynamic DQ Frame Model and Phasor Model

Therefore from (19.72) the q2 component of the positive pole second harmonic maximal arm voltage is: ( ) Md Igd Mq Igq 1 1 M = VPq2 Idiffd2 − + (19.73) 2Carm 𝜔 2 8 8 Similarly, the q2 component of (19.34) is: ( ) ( ) ig dvM P Carm = (mP idiff )q2 + mP dt 2 q2

(19.74)

q2

Using the same approach, (19.74) is expanded as: M = −2Carm 𝜔VPd2

Mq Igd Md Igq 1 Idiffq2 − − 2 8 8

(19.75)

Therefore from (19.75) the d2 component of the positive pole second-harmonic maximal arm voltage is: ( ) Mq Igd Md Igq 1 1 M = + − Idiffd2 + (19.76) VPd2 2Carm 𝜔 2 8 8 The basic expression for the d2 component of the second-harmonic arm voltage is obtained from (19.8): (vP )d2 = (mP vM P )d2 Replacing (19.56), (19.59), (19.76), and (19.38), (19.39) in (19.77): ( ) 3Md Igq 3Mq Igd 1 Md Mq 1 VPd2 = − Idiff0 + + − Idiffq2 𝜔Carm 4 32 32 8

(19.77)

(19.78)

Similarly, the expression for the q2 component of the positive pole second harmonic is obtained from (19.9): ( ) 3Mq Igq 3Md Igd 1 Md2 − Mq2 1 VPq2 = + (19.79) Idiff0 + − + Idiffd2 𝜔Carm 8 32 32 8 Considering the negative pole, using the same approach, the following expressions are obtained: [ ] Md Igd Mq Igq 1 1 M VNq2 = − I + (19.80) 2𝜔Carm 2 diffd2 8 8 [ ] Mq Igd Md Igq 1 1 M VNd2 = − Idiffq2 + + (19.81) 2𝜔Carm 2 8 8 ( ) 3Md Igq 3Mq Igd 1 Md Mq 1 VNd2 = − (19.82) Idiff0 + + − Idiffq2 𝜔Carm 4 32 32 8 ( ) 3Mq Igq 3Md Igd 1 Md2 − Mq2 1 + (19.83) Idiff0 + − + Idiffd2 VNq2 = 𝜔Carm 8 32 32 8

285

286

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

19.7 Second Harmonic of Differential Current The second harmonic component of differential currents I diffd2 and I diffq2 is studied in some depth since this variable appears in a number of equations in the fundamental and second-harmonic model. The d2 component of the dynamic equation for differential current (19.30) is represented in the D2Q2 frame as: 1 (19.84) (2𝜔Larm Idiffq2 )d2 = (−Rarm Idiffd2 )d2 − (VCP + VCN )d2 2 The above equation directly gives the q2 component of the second-harmonic differential current: 1 1 (19.85) Idiffq2 2𝜔Larm = −Rarm Idiffd2 − VCPd2 − VCNd2 2 2 Similarly the d2 component is obtained from (19.30) as: 1 (−2𝜔Larm Idiffd2 )q2 = (−Rarm Idiffq2 )q2 − (VCP + VCN )q2 (19.86) 2 1 1 (19.87) Idiffd2 2𝜔Larm = Rarm Idiffq2 + VCPq2 + VCNq2 2 2 Therefore the system model at second harmonic is given by (19.78), (19.79), (19.82), (19.83), (19.85), and (19.87). This model is interlinked with the fundamental frequency model since many fundamental frequency variables are involved in (19.78), (19.79), (19.82), and (19.83).

19.8 Complete MMC Converter DQ Model in Matrix Form Considering the above modelling, the following observations can be made: M M M M = −VNd , VPq = −VNq VPd M M M M VPd2 = VNd2 , VPq2 = VNq2

(19.88)

Therefore several equations can be eliminated to avoid duplication. The complete MMC DQ static model is expressed in matrix form as: Ax = Bu y = Cx where the model states are: [ M ] M M M M VPq2 VPd VPq VP0 Idiff0 Idiffd2 Idiffq2 xT = VPd2

(19.89)

(19.90)

The model inputs are the grid current components from the AC side, and DC voltage from the DC side: [ ] (19.91) uT = Igd Igq Vdc while the outputs for the basic power flow study are DC current and the converter AC voltages, [ ] (19.92) yT = Idc Vced Vceq

19.9 Second-harmonic Circulating Current Suppression Controller

Considering the derived model in Sections 19.6 and 19.7 the matrix A is obtained as: [ A A = 11 A21

A12 =

] A12 1 , A11 = I5×5 , A22 = A22 2𝜔Larm

1 16𝜔C arm

0 ⎡ ⎢ 0 ⎢ 8M q ⎢ ⎢ −8Md ⎢ ⎣−32Rarm 𝜔C arm

A21

⎡0 1 ⎢ 0 = 8𝜔Larm ⎢ ⎣−2

0 ⎡0 ⎢0 0 ⎢ ⎣0 −Rarm

0 4 −4Mq −4Md 4Md Mq 0 2 0

0 −Mq Md

0 ⎤ Rarm ⎥ ⎥ 0 ⎦

−4 ⎤ ⎥ 0 ⎥ 4Md ⎥ −4Mq ⎥ ⎥ −Md2 + Mq2 ⎦ 0 −Md −Mq

0⎤ 0⎥ ⎥ 0⎦ (19.93)

while matrices B and C are ⎡Mq −Md 0 4 2Mq 4Md 0 0⎤ ⎢ ⎥ 4Mq 0 0⎥ ⎢Md Mq −4 0 −2Md ⎢ 0 0 0 0 0 16𝜔Carm 0 0⎥⎦ ⎣ Mq −2 0 2Md 0 0 0⎤ ⎥ Md 0 −2 2Mq 0 0 0⎥ 0 0 0 0 3 0 0⎥⎦

1 B = 16𝜔Carm

(19.94)

⎡ Md 1⎢ C = ⎢ Mq 4⎢ ⎣ 0

(19.95)

T

The above model enables accurate calculation of fundamental component MMC voltages and second harmonics, for particular control signals (Md and Mq ) and for given inputs: grid current and DC voltage. It is assumed that control signals are constant since they appear as parameters in the model matrices.

19.9 Second-harmonic Circulating Current Suppression Controller The second harmonic on the circulating current in each arm of MMC is quite large and should be separately analysed. It has been shown in Figure 19.2 that the second harmonic in the three phases will cancel when summed both on the AC and the DC side, under balanced conditions. However, a large second-harmonic current will still be circulating in the converter arms, which will cause higher semiconductor stresses and lead to increased losses and heating. Figure 19.7 shows the peak amplitude of circulating second harmonic I diff2 vs arm inductance value for a typical 1 GW (640 kV, 1500 A) MMC converter. The DC component of differential current I diff0 is also shown for comparison. It can be seen that the arm inductance directly affects the circulating current, but even with very large arm inductors the second harmonic is still significant. Increasing arm inductance is not an

287

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System 2000 1800 Idc

1600 1400 1200 Idiff2 (A)

288

1000 800 Idiff0

600 400

Idiff2

200 0 0.05

0.1

0.15

0.2

0.25

0.3

Larm (H)

Figure 19.7 Second harmonic circulating current vs. arm inductance.

effective method of reducing the second harmonic, while large arm inductance has other negative consequences for converter rating and control. It is postulated that the differential current second harmonic can be eliminated using control signal injection at the second harmonic. This controllability is expected by analysing (19.71) and assuming that the control signal includes a second harmonic component. A second harmonic of magnitude M2 , with d and q components given by Md2 and Mq2 , is added on the control signal m as follows: m = M1 cos(𝜔t + 𝜑m ) + M2 cos(2𝜔t + 𝜑m2 ) = Md1 cos(𝜔t) − Mq1 sin(𝜔t) + Md2 cos(2𝜔t) + Mq2 sin(2𝜔t) ( ( ) ) ( ) Mq1 M 1 1 mP = (1 − m) = + − d1 cos(𝜔t) − − sin(𝜔t) 2 2 0 2 d 2 q ( ( ) ) Mq2 Md2 cos(2𝜔t) − − sin(2𝜔t) + − 2 d2 2 q2 ( ( ) ) ( ) Mq1 Md1 1 1 + cos(𝜔t) − sin(𝜔t) mN = (1 + m) = 2 2 0 2 d 2 q ( ( ) ) Mq2 Md2 cos(2𝜔t) − sin(2𝜔t) + 2 d2 2 q2

(19.96)

Replacing (19.96) into equations for maximal arm voltages (19.73) and (19.76): [ ] Md2 Idiff0 Md1 Igd Mq1 Igq 1 1 M − VPq2 = I − + 2𝜔Carm 2 diffd2 2 8 8 [ ] Mq2 Idiff0 Mq1 Igd Md1 Igq 1 1 M VPd2 = − Idiffq2 + + + (19.97) 2𝜔Carm 2 2 8 8

19.9 Second-harmonic Circulating Current Suppression Controller

The above equations show that the second harmonic on the control signal (Md2 and Mq2 ) will generate a second harmonic on the arm voltages which confirms steady-state controllability, and therefore this method can be used for reducing the second-harmonic circulating current. The control loop gain with this method is the zero sequence differential current I diff0 (the term that multiplies Md2 and Mq2 in (19.97)), which has significant value. It is good that this control approach has large gain, since small control inputs can be very effective in reducing circulating current harmonics. Following the above derivation for the arm voltages on both poles and the circulating current, and equating the circulating current second harmonic with zero (I diffd2 = 0, I diffq2 = 0), it is possible to obtain the required magnitude of control signals Md2 and Mq2 to eliminate second-harmonic current: ] ][ ] [ [ Igd (3 − 2Mq2 )Md (3 − 2Md2 )Mq Md2 1 = I = Idiffq2 = 0 Z (Md2 − Mq2 − 3)Md (Md2 − Mq2 + 3)Mq Mq2 Igq diffd2 (19.98) where Z = 8𝜔Carm (2Vdc − Rarm (Md Igd + Mq Igq ) − 3(Md Igq − Mq Igd ))

(19.99)

The above expressions for second-harmonic control signals can be used to develop a feedforward (open loop) second-harmonic controller. An alternative control method to eliminate second-harmonic differential current, and this is more popular in practice, is to use a feedback controller. The circulating current suppression controller (CCSC) is shown in Figure 19.8. The signal 𝜑PLL is the same 50 Hz coordinate frame reference as used for the main control loops. This signal is multiplied by −2 to obtain a reference in the negative sequence coordinate frame rotating at 2𝜔. The differential currents are measured on each phase and converted to d2 and q2 components using common ABC/DQ0 transformation shown in Appendix A. They are separately processed through a proportional integral controller at each channel. The outputs are converted to a static frame (ma2 , mb2 , mc2 ) and added to the control signals from the main control loops at fundamental frequency (ma1 , mb1 , mc1 ). Vga Vgb Vgc

φPLL –2

PLL

–2φPLL

Iq2ref = 0 Idiff_a Idiff_b Idiff_c

abc to dq2

Iq2 Id2

Static to –2ω rotating frame

–

kp2 + ki2/s

Filter

Mq2 Md2 1

+ –

kp2 + ki2/s

P1 D2 current Controller

Figure 19.8 Second-harmonic CCSC.

Ma2

P1 Q2 current –1 Controller

Filter

Id2ref = 0

Ma1 Mb1 Mc1

1 +

–1

dq2 Mb2 to abc Mc2

–2ω Rotating to static frame

+

Ma + +

Mb + +

Mc +

289

290

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

The impact of activation of differential current suppression control is shown in Figure 19.9. The system is operating at a rated 1 GW power in open loop with Md1 = 0.95 and Mq1 = −0.03, and at 2.0 s the CCSC is activated. It is seen that before activation of CCSC the second harmonic is almost half the DC current, which is very large. It can be concluded that CCSC can completely eliminate second-harmonic current in a short time, and the control effort (magnitude of Md2 and Mq2 ) is small and typically below 5% relative to the main control signals (Md1 and Mq1 ). However it should be noted that power flow significantly changes after the activation of CCSC (as seen by reduced I gd and I gq ), despite the fact that Md1 and Mq1 are unchanged. This is an unwanted impact of second-harmonic variables on the fundamental frequency power flow which is seen in (19.62), (19.67) and others. Large second-harmonic differential currents actually increase power flow at fundamental frequencies. As the result of this interaction, Md1 and Mq1 should be increased in order to return to the required power level after CCSC activation. A dynamic interaction between control loops at first and second harmonic is also present. This is a consequence of feedback control dynamics for eliminating second-harmonic circulating current.

19.10 Simplified DQ Frame Model with Circulating Current Controller Since CCSC can completely eliminate second harmonic currents, it is possible to delete the last two equations in the model (19.89). Consequently, the second-harmonic currents are deleted from zero sequence voltages in (19.62) and (19.65) and this will have an impact on reducing power flow. The second-harmonic voltages will still be present but their impact on fundamental frequency power is small. The following two further assumptions will significantly simplify the model while introducing a modest error (below 5%): • The second harmonic arm voltages are neglected. This eliminates the first two equations in (19.89) and (19.90). Also, ripple on the arm voltage is neglected: M VPNO = V dc . • The second-harmonic control signals are neglected. This eliminates altogether second harmonic control signals in (19.97). Considering the above assumptions and simplifying the model (19.89), the MMC static DQ model which consists of only three equations can be derived: ( ( ) ) Md Igq Mq Igd Igd Mq Md 1 1 1 Vced = Md Vdc + Md Rarm Idc + − I − + 2 3 𝜔Carm 16 16 𝜔Carm 12 dc 8 (19.100)

Vceq =

Mq 1 1 Mq Vdc + Mq Rarm Idc + 2 3 𝜔Carm

(

Md Igq 16

−

Mq Igd 16

) +

1 𝜔Carm

( ) Igd M − d Idc + 12 8 (19.101)

Md1

1.6 0.8

1.2 0.6

1 0.8

Md1, Mq1

Igd (kA), Igq (kA)

1.4

Igd

0.6 0.4

0.4 0.2

0.2

Igq

0

Mq1

0

–0.2 –0.2 1.9

–0.4 2

1.9

2.1

2.2

2.3 2.4 time (s)

2.5

2.6

2.7

2.3 2.4 time (s)

2.5

2.6

2.7

2.5

2.6

2.7

0.15

–0.2

Md2, Mq2

Idiffd2 (kA), Idiffq2 (kA)

2.2

Idiffq2

–0.1

–0.3 –0.4 –0.5

0.1

0.05 Mq2

–0.6 –0.7

2.1

0.2

0.1 0

2

0

Idiffd2

–0.8 1.9

2

Md2

2.1

2.2

2.3 2.4 time (s)

Figure 19.9 Activation of second-harmonic CCSC at 2 s.

2.5

2.6

2.7

–0.05 1.9

2

2.1

2.2

2.3 2.4 time (s)

292

19 Half Bridge MMC: Dimensioning, Modelling, Control, and Interaction with AC System

Replacing I dc from (19.53) in (19.100) and (19.101), the above model can be represented in matrix form as: ⎡Vced ⎤ ⎡a11 a12 ⎤ [ ] ⎡bd ⎤ ⎢Vceq ⎥ = ⎢a21 a22 ⎥ Igd + ⎢bq ⎥ V (19.102) ⎥ ⎢ ⎥ Igq ⎢ ⎥ dc ⎢ ⎣bdc ⎦ ⎣Idc ⎦ ⎣a31 a32 ⎦ with the matrix elements defined as: Md2 Rarm

Md Mq Rarm

8 − 3(Md2 + Mq2 )

, 64𝜔Carm Mq2 Rarm 8 − 3(Md2 + Mq2 ) , a22 = a21 = + , 4 64𝜔Carm 4 3 3 1 1 a32 = Mq , bd = Md , bq = Mq , bdc = 0, (19.103) a31 = Md , 2 2 2 2 The following further assumptions can be introduced in order to simplify the model: a11 =

,

4 Md Mq Rarm

Md Mq Rarm 4 Md2 Rarm 4 Mq2 Rarm

2 I 3 dc

(20.15)

Considering further the power balance between converter AC and DC sides under a low DC voltage V dc : Vdc Idc =

3 V Ik 4 g MMC dc

(20.16)

rated

and replacing (20.15) in (20.16), the condition for successful HB cell voltage balancing is 1 (20.17) Vdc > kMMC Vdc rated 2 Therefore, if the DC voltage drops below half the value of k MMC V dc_rated it will not be possible to balance any HB cell in the converter arms. This means that all of the arm cells should be of FB type if the DC voltage is expected to be below the value in (20.17). In such a case the required peak arm voltage gives the required FB voltage capacity and consequently the required number of FB cells can be determined: vP+(Vdc =kMMC Vdc

20.5.4

rated ∕2)

=

kMMC Vdc 4

rated

+

kMMC Vdc 2

rated

(20.18)

Optimal Design of Full Bridge MMC

Starting with the operating requirement for V dcmin and k MMC , the FB MMC design determines the number of required cells in each arm and the percentage of cells that should be of FB type in each arm. Considering the MMC voltage expressions from (19.19) it is possible to determine instantaneous arm voltages vp and vN if the desired AC voltage vce and DC voltage V dc are given. These arm voltages will be constrained between maximum and minimum limits as shown in (20.9): vP− < vP < vP+ ,

vN− < vN < vN+

(20.19)

where the arm voltage limits vp+ , vp -,vN+ and vN - are positive and negative peak values of corresponding arm voltages.

315

20 Full Bridge MMC Converter: Dimensioning, Modelling, and Control

Replacing the required AC voltage given in (20.13) in the expression for positive arm voltage in (19.19) and considering the highest possible DC voltage V dc = V dc_rated , a range for positive arm voltage vP− < vP < vP+ is obtained: vP+(Vdc =Vdc

rated )

= kMMC

Vdc

rated

2 Vdc

+

Vdc

rated

2 Vdc

= (kMMC + 1)

Vdc

rated

2 Vdc

(20.20)

rated rated rated + = (−kMMC + 1) (20.21) 2 2 2 The above equation shows that negative arm voltage is required (since vP− < 0) for k MMC > 1. Since only FB cells can generate negative voltage, some arm cells must assume FB topology if overmodulation is required. Replacing further the AC voltage given in (20.13) in the expression for positive arm voltage in (19.19) but considering lowest possible DC voltage V dc = V dcmin :

vP−(Vdc =Vdc

rated )

= −kMMC

Vdcmin (20.22) 2 V rated vP−(Vdc =Vdcmin ) = −kMMC + dcmin (20.23) 2 2 Equation (20.23) shows that FB cells are required (since vP− < 0) for V dcmin < k MMC V dc_rated . The above equations for extreme conditions will define the FB MMC total number of cells and the number of FB cells. Equation (20.20) determines the peak positive arm voltage and gives the total number of arm cells, which is illustrated in Figure 20.6. It illustrates that only a 50% increase in arm voltage rating is required compared with the peak AC voltage. The number of FB cells in an arm is the larger of the following two requirements: the requirement for FB cells to achieve the peak negative voltage in (20.23) and the required number of FB cells to achieve voltage balancing in (20.18). The minimal number of required FB cells in p.u. (relative to the total number of cells in arm) is illustrated in Figure 20.7, for given V dcminpu = V dcmin /(k MMC V dcrated ) and for a range of k MMC . As an vP+(Vdc =Vdcmin ) = kMMC

Vdc

rated

2 Vdc

+

1.5 1.45 1.4 1.35 Vp + (p.u.)

316

1.3 1.25 1.2 1.15 1.1 1.05 1

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2

Overmodulation index kMMC

Figure 20.6 Required arm voltage capacity (number of arm cells in p.u.) for given overmodulation.

20.5 Hybrid MMC Design

Kmmc = 1.8 Kmmc = 1.6 Kmmc = 1.4 Kmmc = 1.2 Kmmc = 1

1 0.9 0.8

Nfb (p.u.)

0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –1

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

1

Vdcmin (p.u.)

Figure 20.7 Required number of FB cells in p.u. for given kMMC , and for a range of V dcmin .

example, if minimal expected DC voltage is 0.8 p.u. and no overmodulation is required, then only 10% of the cells should be of the FB type. For any DC voltage below 0.5 p.u. the number of FB MMC cells should be at least 75%. Example 20.1 Consider a 1000 MVA, 640 kV, FB MMC VSC-HVDC converter, employing cells of 2.0 kV voltage. The converter is required to generate 400 kV peak phase-neutral AC voltage. It is also required to generate negative DC voltage of Vdcmin = −64 kV under DC faults and converter should be able to exchange rated reactive power under such DC faults. (1) (2) (3) (4) (5)

Determine required overmodulation. Determine the total number of cells per arm. Determine number of FB cells per arm. Determine number of FB cells under normal operation. Sketch waveforms for AC voltage and converter arm voltages assuming nominal DC voltage.

Solution (1) The overmodulation index is k = 400/320 = 1.25. (2) Using (20.20) the maximal required arm voltage is: V V 640 640 + = 720 kV vP+ = kMMC dc rated + dc rated = 1.25 2 2 2 2 Therefore, the number of cells in each arm is n = 720 kV/2 kV = 360 cells. (3) Using (20.18) the required FB voltage capacity in an arm is: vP+(Vdc =kMMC Vdc

rated ∕2)

=

3kMMC Vdc 4

rated

=

3 × 1.25 640 = 600 kV 4

317

20 Full Bridge MMC Converter: Dimensioning, Modelling, and Control vc+ = 400 kV

400

800

overmodulation

vn+ = 720 kV Vn

Vp

600

200

500 Vp, Vn (kV)

100 0

–100

400 300 200

–200

vn– = –80 kV

100

–300 –400

vp+ = 720 kV

700

Vdc /2 = 320 kV

300

Vc (kV)

318

full bridge cells required

0 Vc– = –400 kV 0

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 time (s)

–100

vp– = –80 kV 0

0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 time (s)

Figure 20.8 Converter AC voltage and arm voltages in Example 20.1 (V dc = 640 kV).

Therefore, the number of FB cells is: nfb = 600 kV/2 kV = 300 cells (4) Under normal operation, the required negative voltage is from (20.21): Vdc

640 rated = (−1.25 + 1) = −80 kV 2 2 Therefore under normal operation (V dc = V dc_rated ) only 40 cells will be required to operate with negative voltage. (5) Figure 20.8 shows the converter AC voltage and arm voltages. It is observed that peak AC voltage is higher than V dcrated /2 = 320 kV and also that the arm voltages have negative minimal values vp- = −80 kV, vn− = −80 kV. vP− = (−kMMC + 1)

20.6 Full Bridge MMC DC Voltage Variation Using a Detailed Model A detailed switching model for a 1 GW, 640 kV 21-level FB MMC test system was created as illustrated in Figure 20.9. This model includes four IGBTs per cell and cell voltage balancing is implemented. In a practical 640 kV converter there would be perhaps over 400 levels, but such a system would require excessive simulation time. Since all of the arm cells are of FB type, this converter can operate with any DC voltage in the range −640 kV < V dc < 640 kV. A resistance is connected on the DC side to facilitate voltage/current reversal, but not power reversal. Full bridge MMC

370 kV AC, 3Φ 50 Hz

PCC

Ig

Idc +320 kV Vdc

SRC = 30, X/R = 10

Vg

1000 MVA 370 V/370 kV Xt = 0.2 pu

Figure 20.9 FB MMC test system.

–320 kV

Rdc

20.6 Full Bridge MMC DC Voltage Variation Using a Detailed Model

This detailed model with all 20 cells in each arm is developed in order to better illustrate operating restrictions which may not be evident using average value models. The 21-level converter is expected to have crude control and high voltage jumps, but it should illustrate key operating principles. Figure 20.10 shows the test system responses. Initially the system is operated as a rectifier with 1 GW power transfer. At 0.8 s DC voltage polarity reversal is ordered while maintaining the same power level. This results in DC voltage reversal and also DC current reversal, while the power retains the same sign. Reactive current I gq is regulated at zero through all tests. At 1.8 s DC voltage is reduced to 0.2 p.u. It can be seen that the converter operates well with reduced DC voltage and that it keeps reactive current I gq

1.5

600 400

0

0.5 Idc (kA)

Vdc (kV)

200

1 DC voltage polarity reversal DC voltage magnitude ramp

–200

0

–0.5 Vdc

–400

–1

Vdcref –600

–1.5 1

1.5

2.5

2

3

3.5

4

1

1.5

2

2.5

3

3.5

4

1

1.5

2

2.5

3

3.5

4

2

2.5 time (s)

3

3.5

4

45 1200 40

1000

Vcell (kV)

Pg (MW)

800 600 400 200

35

30

25

0 1

1.5

2

2.5

3

3.5

20

4

3 Igdref 2.5

0.25 0.2

Igd

0.15

2

Igq (kA)

Igd (kA)

0.1

Igq Igqref

0.05

1.5 1

0

–0.05 –0.1

0.5

–0.15 –0.2

0

–0.25 –0.5

1

1.5

2

2.5 time (s)

3

3.5

4

1

1.5

Figure 20.10 Testing 21-level FB MMC for DC voltage magnitude and polarity change.

319

320

20 Full Bridge MMC Converter: Dimensioning, Modelling, and Control

at zero. The cell voltage V cell is maintained at the rated level although transient voltage deviation is large because of the low number of cells. The low cell number also causes a rather rough DC voltage slope.

20.7 FB MMC Analytical Dynamic DQ Model Since the average DQ frame model for FB MMC is largely based on HB MMC modelling, only the specific new equations will be analysed. The modelling is mainly concerned with inclusion of an Mdc control signal in the HB MMC model and understanding of the limits for variables. 20.7.1

Zero Sequence Model

Considering the FB MMC control signal in (20.5) and (20.6), the zero sequence DC side (19.30) can be rearranged to include Mdc control as: M M M + MPd VPd + MPq VPq + 2Rarm Idiff0 Vdc = Mdc VP0

(20.24)

The above equation is identical to (19.118) when the maximal arm voltages are expressed using DC and fundamental frequency components. The equation for zero sequence of arm voltage (19.61) becomes: VP0 =

M Mdc VP0

2 1 + 𝜔Carm

(

Md Mdc Igq 16

−

Mq Mdc Igd 16

+

Md Mq Idiffd2 8

+

(−Md2 + Mq2 )Idiffq2

)

16 (20.25)

While, replacing (19.48) in (20.25), the zero sequence of maximal arm voltage is 2Rarm Idiff0 + Vdc M VP0 = Mdc ( ) Md Igq Mq Igd Md Mq −Md2 + Mq2 1 (20.26) − I + Idiffq2 − + 𝜔Carm 8 8 4Mdc diffd2 8Mdc Similarly, using methods from Appendix B, the zero sequence of (19.49) and (19.50) gives the following: 1 1 Mdc Idiff0 = Md Igd + Mq Igq (20.27) 4 4 The above model is valid for any phase, and since the DC current can be derived as the sum of three differential currents in (19.24), under the assumption of a symmetrical and balanced system it gives: 3 Md Igd + Mq Igq Idc = (20.28) 4 Mdc Comparing the above equation with (19.52) for DC current in HB MMC, and considering (20.24), it is seen that the Mdc control signal acts as the stepping ratio (as a transformer on DC side). The DC current is stepped by dividing by Mdc control, while the DC voltage is stepped by multiplying by Mdc in (20.24).

20.8 Simplified FB MMC Model

20.7.2

Fundamental Frequency Model

The fundamental component of the principal MMC dynamic (19.54) for the case of FB control can be expressed from (19.56), (19.59), (19.63) and (19.64): ) ( Mq M M M 1 M VPq = (20.29) Idiffq2 + dc Igd − d Idiff0 − d Idiffd2 − Carm 𝜔 2 4 4 4 ( ) Mq Mq Md Mdc 1 M VPd = − + − I I I I (20.30) Carm 𝜔 2 diff0 4 diffd2 4 diffq2 4 gq ) ( Mq M M Md 1 M VNq = (20.31) Idiff0 + d Idiffd2 + Idiffq2 − dc Igd Carm 𝜔 2 4 4 4 ) ( Mq Mq Md Mdc 1 M VNd = + − + (20.32) I I I I − Carm 𝜔 2 diff0 4 diffd2 4 diffq2 4 gq The equations for the MMC AC voltage (19.67–19.70) can be expanded in similar way: 1 1 1 1 M M M M + Mdc VPd − Md VPd2 − Mq VPq2 VPd = − Md VP0 2 2 4 4

(20.33)

1 1 1 1 M M M M + Mdc VPq + Mq VPd2 − Md VPq2 VPq = − Mq VP0 2 2 4 4

(20.34)

1 1 1 1 M VM + M VM + M VM + M VM 2 d N0 2 dc Nd 4 d Nd2 4 q Nq2

(20.35)

VNd =

1 1 1 1 (20.36) M VM + M VM − M VM + M VM 2 q N0 2 dc Nq 4 q Nd2 4 d Nq2 The above equations illustrate that Mdc control input will have a substantial impact on fundamental frequency components of arm voltages. The equations for the second harmonic can be derived in a similar manner. VNq =

20.8 Simplified FB MMC Model In (20.24), the first term is usually two orders of magnitude larger than any of the remaining terms, since it has been illustrated in Example 19.2 that fundamental frequency ripple on the arm voltage is small. Simplifying, this equation gives the main principle of controlling DC voltage in FB MMC: M Vdc = Mdc VP0

(20.37)

Under the same assumptions as in Section 19.10, considering the model in (20.29)–(20.36), the FB MMC AC voltages can be obtained: ( ) Md Igq Mq Igd Md 1 1 M + Md Rarm Idc + − Vced = Md VP0 2 3 𝜔Carm 16 16 ( ) Mdc Igq Mq 1 + Idc − (20.38) 𝜔Carm 12 8

321

322

20 Full Bridge MMC Converter: Dimensioning, Modelling, and Control

Vceq

Mq 1 1 M = Mq VP0 + Mq Rarm Idc + 2 3 𝜔Carm ( ) Mdc Igd Md 1 + − I + 𝜔Carm 12 dc 8

(

Md Igq 16

−

Mq Igd

)

16 (20.39)

Neglecting arm resistance and replacing DC current from (20.28) in (20.38) and (20.39): ( ) Md Mq Md Mq 1 M Vced = Md VP0 + − + I 2 16𝜔Carm 16𝜔Carm Mdc gd ) ( Mq2 Md2 Mdc I + + − (20.40) 16𝜔Carm 16Mdc 𝜔Carm 8𝜔Carm gq ) ( 2 2 M M M q 1 dc d M I Vceq = Md VP0 + − − + 2 16𝜔Carm 16Mdc 𝜔Carm 8𝜔Carm gd ( ) Md Mq Md Mq + − (20.41) I 16𝜔Carm 16Mdc 𝜔Carm gq The above model becomes identical to (19.105) for Mdc = 1. Similarly as with HB MMC in (19.105) the first terms in (20.40) and (20.41) are dominant. The remaining terms have combined effect of an equivalent series capacitor, as discussed in Section 19.12. Equation (20.37) describes the principal control method for DC side of FB MMC, while (20.40) and (20.41) describe the principal AC-side control methods. It is clear that the DC component of maximal arm voltage V M PO is the critical term that facilitates both DC side control and AC side control. Therefore, fast arm voltage control (or arm energy control) will be a prerequisite for developing an FB MMC controller.

20.9 FB MMC Converter Controller Figure 20.11 shows the structure of a simplified FB MMC controller. It is very similar to the HB MMC controller in Figure 19.14; however, some important differences are observed. FB MMC can achieve a wide range control of DC modulation index −1 < Mdc < 1. This facilitates independent DC voltage control. Feedback control of arm voltage/energy is essential with FB MMC since it acts as a power balancer on MMC arms considering that FB MMC can independently control power on the DC and AC sides over a wide range. The arm voltage balancing using Mdc control input works well as long as the DC side is available for power exchange. In the case of DC faults, it is desirable for FB MMC to continue operation. When the DC voltage is low the MMC converter cannot exchange power on the DC side and a power imbalance on arms may occur considering that the AC side power continues to flow into or out of converter. For this reason, an additional control loop is added on I dref as seen in Figure 20.11. This control loop responds to any (remaining) error on arm voltage eV M ts and moderates the AC side active current in order to balance arm power.

VGa VGb

PLL

VGc Vg

Coordinate frame reference

φPLL

Vpa Vpb Vpc AC Voltage controller Igq /Vg

Vg filter

Vg ref

AC Voltage controller

+–

Igq ref static to rotating frame

Iga Igc Pdc

fg Vdc Vdcref

Ig_r

n/d d n/d

Pdc filter

Pdcref

– + –

Igq Igd

+

q Current Controller

–

DC power controller

+

Ig filter

Mq

Ig filter

Md

Igd ref –

Idiffb Idiffc

MAp

MA2

+

MAn

(.)2

+

–

V MAp V MBp

V Mtsumref

V MCp V MAn V MBn V MCn

Figure 20.11 FB MMC converter controller.

+

n

n/d d 6

+

–

V Mtsum

Idcref Arm + voltage – control

Arm DC current control Idc

1 –1

Mdc

δpn

upper arm

1

δn1

MAn = 0.5(MDC + MA1 + MA2) –1 1 nearest MBn level MBn = 0.5(MDC + MB1 + MB2) control –1 1 MCn = 0.5(MDC + MC1 + MC2)M Cn

d Current Controller eV Mts

DC voltage controller

δp1

–1

Ma1 dq M b1 to Mc1 abc rotating to static frame

–

1

–1 1 nearest n pc capacitor MBp level MBp = 0.5(MDC – MB1 – MB2) balancing control –1 1 MCp = 0.5(MDC – MC1 – MC2) MCp

Igdmin Vdc filter

Vpcn

MAp = 0.5(MDC – MA1 – MA2)

2nd MB2 harmonic Control MC2

φPLL

Igdmax

kgdroop (.)2

Igqmax

Igqmin n

abc to dq

Igb

φPLL2 Idiffa

Igq ref

φPLL

Vpc1

2

nnc

capacitor balancing δnn

–1 Vna Vnb Vnc

Vnc1

lower arm

Vncn

20 Full Bridge MMC Converter: Dimensioning, Modelling, and Control 1000

700 PdcrefR

600

PdcR

Voltage (kV)

Power (kW)

800 600 400 200 0 0.4

VdcrefI

500

VdcI

400 300 200

0.6

0.8 time (s)

1

100 0.4

1.2

0.6

(a) Rectifier Power

0.8 time (s)

IdrefR

IdI

IdR

–0.2

0.6 0.4 0.2

IqrefR

1.2

IdrefI

0

Current (kA)

Current (kA)

0.8

1

(b) Inverter DC voltage

1

IqR

–0.4 –0.6 –0.8

IqrefI

IqI

0 0.4

0.8 time (s)

0.6

1

–1 0.4

1.2

1

1.2

(d) Inverter grid current

660

660

655

655

650

650 Voltage (kV)

V MtR

645 640 635

640 635 630

625

625 0.6

0.8 time (s)

1

(e) Rectifier arm voltage

1.2

V MtI

645

630

620 0.4

0.8 time (s)

0.6

(c) Rectifier grid current

Voltage (kV)

324

620 0.4

0.6

0.8 time (s)

1

1.2

(f) Inverter arm voltage

Figure 20.12 FB MMC HVDC response to step inputs on power and DC voltage references.

Figure 20.12 illustrates the operation of the FB MMC controller for the same test system as in Section 19.5. At 0.5 s a positive step on power reference is applied, and at 0.7 s a reduction of DC voltage from 1 to 0.2 p.u. is demanded. It is concluded that FB MMC HVDC operates at low DC voltage with full reactive current control capabilities. The control of maximal arm voltages is very fast at both terminals.

325

21 MMC Converter Under Unbalanced Conditions 21.1 Introduction The modular multilevel converter (MMC) analysis and controller development described in previous chapters is based on the presumptions that the converter, AC system and DC system are balanced and symmetrical, as would be the case in most operating conditions. Nevertheless, because of tolerances in circuit parameters, unbalanced loading and faults, the MMC converter may become exposed to unbalanced operating conditions. Also, the MMC converter has individual arm control signals, which further increases converter sensitivity to unbalances. The primary concern under unbalanced conditions is whether the converter will continue operating. The converter self-protection will block the MMC when any variable approaches one of its preset deviation limits. The effectiveness and quality of control in the main control loops may also be affected in unbalanced conditions. Finally, the behaviour of MMC under unbalanced conditions will impact both the AC grid and the DC grid and any negative influence should be minimised. Considering the high controllability, it may be possible to use MMC controls to counter unbalance and improve operation under unbalances. In developing MMC balancing controls, the first question is related to the goal of such controllers. When the MMC is exposed to unbalanced conditions, all internal variables will be unbalanced, but not all variables can be balanced. Studies have demonstrated that predominantly maximal arm voltages should be regulated to the balanced state. Maximal arm voltages are of primary importance since they are directly related to the cell voltages while the quality of cell voltage control has a great impact on cell sizing and costs. Also, maximal arm voltages are highly important for stability at high voltage direct current (HVDC) system level. It is emphasised that the arm currents cannot be simultaneously controlled to a balanced state, and arm currents may even become more unbalanced when arm voltage balancing is active. The MMC converter has six control inputs (modulation indices of six arms) and each control signal has DC, fundamental frequency and second harmonic components. These control signals can be used to achieve balancing inside the MMC converter and even to improve the balance of an AC or DC system. The internal balancing of MMC is analysed first in this chapter, while positive/negative sequence control of AC grid current will be studied in the last section.

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

326

21 MMC Converter Under Unbalanced Conditions

21.2 MMC Balancing Controller Structure Figure 21.1 shows the complete MMC controller with balancing control blocks. In order to achieve balanced six MMC arm voltages, the controller is divided into two segments: (1) balancing between three phases (also called horizontal balancing); and (2) balancing between arms in each phase (also called vertical balancing). M M M M M M , VAn , VBp , VBn , VCp , VCn ) are first proThe measured six maximal arm voltages (VAp M M M , VBsum , VCsum ) are cessed to obtain the sum and difference voltages. Sum voltages (VAsum average values of the two arm voltages per phase, which are used by the phase balancing M M M , VBdiff , VCdiff ) are obtained by subtracting the two controller. Difference voltages (VAdiff arm voltages for each phase and they are used by the arm balancing controller. The outputs of these controllers are added to the outputs of grid current controller and second-harmonic differential current controller described previously. The block ‘phase balancing control’ includes arm balancing controller and the whole controller reduces to the diagram in Figure 19.14 when balancing is inactive.

21.3 Balancing Between Phases (Horizontal Balancing) The balancing between phases of MMC converter operates on similar principles to controllers for grid balancing employed with some grid connected converters (active filtering, some photovoltaic inverters, static synchronous compensators (STATCOMs) with active balancing, etc.). These controllers initiate power exchange between three phases of converter, which counteracts the original unbalance between the phases. The balancing controller includes a detecting unit that identifies unbalance and the control unit, which acts on the arm voltages to reduce unbalance. Figure 22.2 shows the phase balancing controller structure. Since the controlled variables are of DC nature (maximal arm voltages) it is necessary to employ a method that enables the detection of unbalance on three DC variables. This can be achieved using a common ABC/DQ transformation defined in Appendix B. In this case the speed of coordinate frame is set to zero (𝜔 = 0), and this gives the following transformation matrix T ABC/𝛼𝛽 and its inverse (also called ABC/𝛼𝛽 transformation): ⎡I𝛼diff ⎤ ⎢I𝛽diff ⎥ = [T ABC ⎢ ⎥ ⎣I0diff ⎦

⎡IAdiff ⎤ ⎢IBdiff ⎥ , ] 𝛼𝛽 ⎥ ⎢ ⎣ICdiff ⎦ ⎡I𝛼diff ⎤ ⎡IAdiff ⎤ −1 ⎢ ⎢IBdiff ⎥ = [T I ⎥, ] ABC 𝛼𝛽 ⎥ ⎢ 𝛽diff ⎥ ⎢ I ⎣I0diff ⎦ ⎣ Cdiff ⎦

−1∕3 ⎤ ⎡2∕3 −1∕3 √ √ ⎢ 0 − 3∕3 3∕3⎥ = 𝛼𝛽 ⎥ ⎢ 1∕3 ⎦ ⎣1∕3 1∕3 1⎤ ⎡ 1 √0 −1 ⎢−0.5 − 3∕2 1⎥ = TABC 𝛼𝛽 √ ⎢ ⎥ ⎣−0.5 3∕2 1⎦

TABC

(21.1)

(21.2)

In the above transformation, the zero sequence component will correspond to the average value while 𝛼𝛽 components indicate three-phase unbalance of DC variables (𝛼𝛽 components are zero for a balanced system). This method performs averaging over three phases and it is more robust than using simply direct comparisons between individual phases. The controller for zero sequence maximal arm voltage (total arm voltage) is identical to the arm voltage controller in Figure 19.14.

Igq /Vg

Vg_ref

φPLL Igq_ref

Pdc Pdc_ref

DQ grid current control

Igd_ref

DC power controller

Vdc Vdc_ref

DC voltage controller

IgA IgB IgC

Power/ Vdc

Vpa Vpb Vpc

MBp = 0.5(MBDC – MB1 – dMB1 – MB2) MCp = 0.5(MCDC – MC1 – dMC1 – MC2)

Sum and difference calculation

V MCn

Iαdiff_ref

Phase Iβdiff_ref Voltage I balancing 0diff_ref

Differential current DC control

MAdc MBdc MCdc

Coordinate frame reference

MA2 Differential current MB2 2nd harmonic M C2 control Id2ref = 0

2

Iq2ref = 0

φPLL2

φPLL

MCn = 0.5(MCDC + MC1 – dMC1 + MC2)

MBn MCn

nearest level control

nnc capacitor balancing

Vna Vnb Vnc

Vnc1

lower arm

IAdiff, IBdiff, ICdiff

PLL

δpn

δn1

ICdiff VAg VBg VCg

capacitor balancing

upper arm

MAn = 0.5(MADC + MA1 – dMA1 + MA2) MAn

IAdiff IBdiff

MCp

npc

MA2, MB2, MC2

MBn = 0.5(MBDC + MB1 – dMB1 + MB2)

V MBsum_ref = Vdc V MCsum_ref = Vdc

δp1 nearest level control

MAdc, MBdc, MCdc

V MAsum, V MBsum, V MCsum

V MAsum_ref = Vdc

Vpcn

dMA1, dMB1, dMC1

Arm dMB1 Voltage balancing dMC1

V MAdiff, V MBdiff, V MCdiff

V MCp V MAn V MBn

MBp

MA1, MB1, MC1

dMA1

V MBdiff_ref = 0 V MCdiff_ref = 0

Vpc1

MC1 MAp = 0.5(MADC – MA1 – dMA1 – MA2) MAp

V MAdiff_ref = 0

V MAp V MBp

MA1 MB1

MA1, MB1, MC1

Igq_ref

AC Voltage controller

IgA, IgB, IgC

Vg

Figure 21.1 Complete MMC controller including balancing controls.

δnn

Vncn

328

21 MMC Converter Under Unbalanced Conditions V Mαsum_ref = 0 1/(Ts + 1)

V MCsum

αsum

V Mβsum_ref = 0

V MAsum V MBsum

VM

ABC to αβ0

1/(Ts + 1)

VM

V Mtsum

IBdiff ICdiff

KP

++

Iαdiff_ref

+ –

+ –

KP

+ +

Iβdiff_ref

+ –

KP

++

Mαdc

KP

+ +

Mβdc

Ki /s

Ki /s + –

KP

1

Ki /s

Ki /s

βsum

V Mtsum_ref = V dcn

IAdiff

+ –

++

I0diff_ref

+ –

Ki /s

KP

0 1 αβ0 to ABC

MAdc

MBdc

0 1 MCdc ++

M0dc 0

Ki /s

Iαdiff ABC to αβ0

Iβdiff I0diff

Figure 21.2 Controller for phase balancing (horizontal balancing).

The error in each of the three channels is individually processed using proportional integral regulators and corresponding outputs generate references for 𝛼𝛽 components of DC currents in converter legs. The internal current regulation loop is included to further improve control and dynamics. DC current control in arms reduces stresses in semiconductors and it is particularly beneficial when a fast response is needed, like DC fault conditions. The differential arm currents are obtained as discussed with a circulating current suppression controller and as with differential arm voltages. The controller outputs need to be finally converted to ABC frame using 𝛼𝛽/ABC transformation from (21.2). It is noted that the third control channel (related to zero sequence) in Figure 21.2 is identical to the arm voltage and the DC current controller in the MMC controller in Figure 19.14 and the basic full bridge MMC controller shown in Figure 20.11.

21.4 Balancing Between Arms (Vertical Balancing) Figure 21.3a shows the equivalent circuit for vertical balancing. In this case, the arm voltages between two arms in a phase are unequal, and the goal is to exchange power between positive and negative arms in order to balance the phase. Each arm has three controllable voltage sources: at DC, at first harmonic and at second harmonic. In principle vertical balancing can be based on any of these coordinate frames (or even at higher harmonics). The simplest option would be to use DC control (based on the Mdc signal); however research studies have demonstrated the sensitivity of such control to harmonic amplification and instability. The fundamental frequency variables will be used and the equivalent circuit is shown in Figure 21.3b. Figure 21.3c shows the structure of arm balancing controller based on the first harmonic. Proportional integral controllers per phase will generate a control signal in response to any unbalance between arms. This signal multiplies directly the fundamental frequency control signal derived from the grid current controller (MA1 , MB1 , and MC1 ) to generate small oscillating signals at fundamental frequency (dMA1 , dMB1 and dMC1 ). These signals are added to one arm and subtracted from the opposite arm for each phase as illustrated in Figure 21.1. This controller creates a magnitude difference

Idc VPMM1pcos(ωt + θ1) VPMM2pcos(2ωt + θ2)

V MAdiff_ref = 0

VPMM1pcos(ωt + θ1) – + – + – +

In

Ip In

Larm Rarm – +

Ip

Larm

VNMMdcn

Bdiff_ref = 0

Larm

V MBdiff

Rarm

VNMM1ncos(ωt + θ1)

V MCdiff

+ –

1/(Ts + 1)

dMA1 + +

KP

+ +

+ –

KP

+ +

Ki /s

MA1 MB1 MC1

VNMM2ncos(2ωt + θ2) VNMM1ncos(ωt + θ1) (a) Equivalent circuit for vertical balancing

(b) Equivalent circuit for vertical balancing using fundamental frequency

(c) Vertical balancing controller using fundamental frequency variables

Figure 21.3 Equivalent circuit and controller for balancing arms in phases (vertical balancing).

X

dMB1

X

Ki /s

1/(Ts + 1) V MCdiff_ref = 0

Larm

KP Ki /s

1/(Ts + 1) VM

Rarm

Rarm

Vdc /2

Vdc /2

V MAdiff

VPMMdcp

+ –

X

dMC1

330

21 MMC Converter Under Unbalanced Conditions

between the fundamental components of the two arm voltages, and this enables power exchange between the two arms. Alternatively, power exchange can be achieved using a phase shift between the two arms and this could possibly have advantages in terms of losses. Such power exchange based on a phase shift is used with DC/DC converters since much more power is exchanged, as discussed in Section 30.4. However, with unbalanced AC/DC MMC the required power exchange is miniscule and magnitude manipulation has advantages in terms of control simplicity. The arm unbalance will not normally occur for transient disturbances on AC grid. The arm asymmetry is expected to occur as a consequence of parameter unbalance inside the MMC or because of asymmetry on the two poles on DC system and these events will generally have very slow dynamics. For these reasons and in order to avoid dynamic interaction problems, an arm balancing controller can be developed with longer time constants.

21.5 Simulation of Balancing Controls Figure 21.4 illustrates the operation of a balancing controller on a 1 GW, 640 kV MMC HVDC converter. A significant (unlikely) unbalance and asymmetry is created inside the MMC converter by adding 18 Ω resistance in the phase C negative arm and adding 5 Ω resistance in the phase B positive arm. At 1 s, the balancing controller is activated, and then at 1.5 s a 10% negative power reference step is applied. The second harmonic circulating current controller is operating all of the time. It is evident from Figure 21.4e that there is a notable unbalance between three phases since 𝛼 and 𝛽 components have around 4 kV before activation of the balancing controller. The unbalance between arms is even more significant since the differential arm voltages are 50 kV for phase C, 10 kV for phase B and 7 kV for phase C as seen in Figure 21.4f. It can be observed that phase unbalance is eliminated in around 100 ms while arm unbalances are completely eliminated in around 500 ms after activation of balancing controllers. The power reference step at 1.5 s is purposely included to illustrate that normal grid controls are not affected by the additional balancing control loops. The control signals are shown in Figure 21.4i,j, and demonstrate that a very small balancing control effort is adequate. Figure 21.5 shows the MMC converter response to a 200 ms unbalanced AC grid fault while no balancing control is used. This test illustrates the range and significance of possible issues with dynamic unbalanced disturbances. Of primary concern is the substantial unbalance on maximal arm voltages. Also, it can be seen that there is a significant 100 Hz oscillating component on DQ grid currents. Figure 21.6 shows the MMC response to the same fault when balancing controls are used. It is seen that sum maximal arm voltages are balanced within 100 ms but balancing differential maximal arm voltages take longer. The graphs with control variables indicate the range of control signal variation. It is concluded that variables used by balancing controls take a very small range of the modulation signal: dMA1 , dMB1 and dMC1 do not exceed 0.04, while MdcA , MdcB and MdcC , deviate from the steady-state value of 1 by 50 mH for this test system. It is convenient that this inductance value is in agreement with the inductance values required for the DC CB operation. Therefore, DC grid protection system development may not impose additional demands for increasing inductor size. Examining the results for faults on cable 2 in Figure 29.7c and d, it is seen that there is a larger difference between Dvdc measurements at the two ends of faulted cable (CB21 and CB12), which is expected considering that cable 2 is 300 km long. The measurements at the remote end of the faulted cable approach values measured at unfaulted cables. This result indicates the limitation of ROCOV protection. In the case of very long cables, it might be difficult to provide adequate selectivity. The results in this figure would recommend a protection setting of around Dth = −600 kV/ms. Such a setting, 0 CB12, CB21 CB12

–1000

CB21

CB13

CB31

CB13

–1500

CB31

–2000

0

0.05

0.1

0.15 Ldc(H)

0.2

dVdc/dt (kV ms–1)

dVdc/dt (kV ms–1)

0 –500

CB12

–1000

0

CB21

CB13

CB31

CB21 CB12

0

0.05

0.1

0.15 Ldc(H)

0.2

(c) Fault at line side of CB12 (Flt 4)

0.25

dVdc/dt (kV ms–1)

dVdc/dt (kV ms–1)

CB12

–1000

–2000

0.05

0.1

0.2

0.15 Ldc(H)

0.25

(b) Fault at line side of CB13 (Flt 2)

CB13

–1500

CB31

0

CB31

–500

CB13

CB13

(a) Fault at line side of CB31 (Flt 1) 0

CB21 CB31

–1500 –2000

0.25

CB12, CB21

–500

CB31 CB13 CB12

–500

CB21

–1000

CB13

CB31

CB12

–1500 CB21

–2000

0

0.05

0.1

0.15 Ldc(H)

0.2

0.25

(d) Fault at line side of CB21 (Flt 3)

Figure 29.7 Peak value of voltage derivative DVdc vs. DC CB series inductance for four fault locations. Test system with 400 kV DC cables. (a) Fault at line side of CB31 (Flt 1); (b) fault at line side of CB13 (Flt 2); (c) fault at line side of CB12 (Flt 4); and (d) fault at line side of CB21 (Flt 3).

449

29 DC Grid Fault Management and Protection System 0

CB21 CB12

–500 –1000

CB13

–1500 –2000

CB12 CB21 CB13 CB31

CB31

0

0.05

0.1

0.15 Ldc(H)

0.2

(a) Fault at line side of CB31 (Flt 1)

0.25

dVdc/dt (kV ms–1)

0 dVdc/dt (kV ms–1)

450

CB21

CB12 CB21 CB13 CB31

–500 CB12

–1000

CB31

–1500 –2000

CB13

0

0.05

0.1

0.15 Ldc(H)

0.2

0.25

(b) Fault at line side of CB13 (Flt 2)

Figure 29.8 Peak value of voltage derivative DVdc vs. DC CB series inductance for four fault locations. Test system with 400 kV overhead lines. (a) Fault at line side of CB31 (Flt 1); and (b) fault at line side of CB13 (Flt 2).

with Ldc = 50 mH, would provide a margin of at least twofold with respect to worst case positive detection and negative detection decision. Figure 29.8 shows a similar test case as above but 400 kV overhead lines are used instead of DC cables 1 and 2. It is necessary to undertake a separate study in this case since overhead lines have substantially different impedance from cables. The general conclusion is that ROCOV-based protection is feasible with overhead lines, but achieving selectivity is more challenging. Larger series inductors are required, and selectivity margins are smaller. ROCOV-based protection has very good potential for applications in DC grids; however, multiple simulation studies on DC grid models have demonstrated the following limitations: (1) In the case of very long cables, selectivity margins will reduce and for cables over 1000 km the method may not be suitable. (2) Fault impedance affects accuracy and selectivity. The results presented above consider zero impedance faults. As fault impedance increases the magnitude of Dvdc reduces. For fault resistance of 50 Ω the magnitude of Dvdc will be around one-third of the values shown in this section, and therefore it would be difficult to achieve good selectivity. (3) With overhead lines selectivity margins reduce notably. With short overhead lines this method may not be suitable.

29.6 Blocking MMC Converters Under DC Faults The local ROCOV protection in combination with hybrid DC CBs is the fastest of the DC grid protection systems, and many studies have demonstrated adequate selectivity and robustness. Assuming that DC CBs are installed on all DC lines, and that fully selective protection logic is employed, this system is capable of isolating any DC fault within 3–5 ms (the time for DC voltage to recover). However, the crucial question for grid operators is if blocking of MMC converters would occur in this time period while the protection system is dealing with the DC fault. The simple three-terminal DC grid from Figure 29.6 is analysed and a hybrid DC CB model is included and ROCOV protection is used with all DC CBs on both lines. The hybrid DC CB operates in 2 ms. The local AC grids are strong with short circuit

3.4

3.4

3.2

3.2

IdcMMC1 (p.u.)

IdcMMC1 (p.u.)

29.6 Blocking MMC Converters Under DC Faults

3 2.8 2.6 2.4 0.4

0.45

0.5

0.55

0.6

3 2.8 2.6 2.4 0.4

0.65

0.45

Ldc12(H)

3 2.8 2.6 0.5

0.55

0.6

0.6

0.65

(b) IdcMMC1 versus Ldc13

IdcMMC3 (p.u.)

IdcMMC2 (p.u.)

(a) IdcMMC1 versus Ldc21

0.45

0.55 Ldc13(H)

3.6 3.4 3.2

2.4 0.4

0.5

0.65

0.7

0.75

3.6 3.4 3.2 3 2.8 2.6 2.4

0.3

0.35

0.4

Ldc21(H)

Ldc31(H)

(c) IdcMMC2 versus Ldc21

(d) IdcMMC3 versus Ldc31

0.45

Figure 29.9 Peak MMC DC current for a worst case DC fault, vs. inductor size. (a) IdcMMC1 vs. Ldc21 ; (b) IdcMMC1 vs. Ldc13 ; (c) IdcMMC2 vs. Ldc21 ; and (d) IdcMMC3 vs. Ldc31 .

ratio = 10. The largest peak fault current occurs for faults at the middle point on the cables, and therefore worst-case faults at 150 km distance on cable 12 and 100 km on cable 13 are studied. Figure 29.9 shows the measured peak MMC DC current vs. the size of the local inductor. MMC blocking would normally occur at 2–3 p.u. DC current depending on the particular converter. It is concluded that inductors of around Ldc = 700 mH would be required to avoid MMC blocking and larger values would be recommended in order to provide further safety margins. These inductors would be very large and probably not acceptable in DC grids for many other reasons. A possible temporary blocking of MMC converters under DC faults has been widely studied. This method assumes that MMC is blocked but the associated AC CB is not tripped instantaneously. Figure 29.10 shows the control logic for temporary MMC blocking. The MMC is blocked for 10 ms assuming that normally a DC fault would be cleared by DC CBs in this time interval. The benefit of this logic is that the MMC converter can be deblocked in a short time frame since AC CB is not tripped. Temporary MMC blocking has not been used on HVDC projects. The main concerns are related to a worst case scenario where DC CBs do not clear the DC fault and therefore fault conditions would last for 10 ms longer: (1) The fault current stress on MMC diodes (bypass thyristors) will be increased since theoretically the fault current may last 10 ms longer. (2) The current stress on AC CBs and all AC system equipment will last for 10 ms longer. It has been demonstrated in Figure 22.13 that MMC diodes may need to be rated to conduct a DC fault current for over 700 ms because of the DC line energy discharge. Therefore, depending on the MMC original design, adding 10 ms to the fault conduction time may not represent a significant increase in semiconductor stress.

451

452

29 DC Grid Fault Management and Protection System

Figure 29.10 Control logic for temporary blocking MMC.

Normal operation N

idc > 3Idcn Y De-block MMC

Block MMC Wait for Tblock(10 ms) idc > 3Idcn

N

Y Send opening signal to ACCB

Figure 29.11 shows a simulation of a low-impedance DC fault in the middle of cable 12, assuming ROCOV protection on all DC CBs and temporary MMC blocking logic. The inductors of Ldc = 125 mH are used on all DC CBs. It can be seen that the DC fault is successfully isolated by CB12 and CB21, and that MMC1 and MMC2 are temporarily blocked for 10 ms. Full power transfer between MM1 and MMC3 is established in around 30 ms. Since cable 12 is isolated there is no opportunity for MMC2 power exchange after the fault.

29.7 Differential DC Grid Protection Strategy A robust DC grid protection system can be developed using current direction-sensitive measurements on each DC cable. However, some communication between DC CBs will be required, since many DC CBs will have the same direction of fault current. Consider CB at bus 2 (CB25_2) and CB at bus 3 (DC CB34_3) in Figure 29.3, which both see large positive fault current (towards the centre of the cable that they protect) for a fault on cable 34. Only DC CB34_3 and DC CB34_4 should be tripped to clear this fault, and therefore additional information is required for protection selectivity. Differential protection using pilot wire is a well-developed method for component (unit) protection in AC systems. This method is also called a unit protection system. It can be expanded for reliable protection of DC cables, as shown in Figure 29.12. The protection system consists of a direction-sensitive current sensor (S34) and a protection relay (C34) connected to local CB (CB34) at each cable end. Each relay communicates only with the relay at the opposite end of the same DC cable using a dedicated communications cable. No communication with DC CBs on other cables in the grid is required. The trip decision is made at each relay if the sum of measured currents from the two cable sensors exceeds a threshold positive value for a specified period of time. This logic provides very reliable selectivity since for each DC fault location there will be only two relays (those on the same cable) receiving a positive differential signal. The primary drawback of the differential protection is the delays associated with communication between geographically separated sensors. Firstly, there will be a detection

29.7 Differential DC Grid Protection Strategy

delay in the sensor caused by the travelling wave delay. Analysing the curves in the example shown in Figure 29.4, and assuming that the threshold is set to 3 kA (2 p.u.), the sensor at the opposite end, 600 km away, would be able to detect the fault current level after around 12 ms. On the other hand the local sensor can detect the fault current level instantaneously. Additionally, there will be a delay associated with the signal transfer through the pilot wire between the relays at the two cable ends. It is assumed that the speed of signal transfer in the optical communication cables will be close to the speed of light (300 000 km/s), 1.5 blockMMC2

blockMMC1

1.5 1 0.5

blockMMC1

0 –0.5 2.995

3

3.005

3.01

3.015

3

3.005

3.01

Time(s)

Time(s)

(b) block signal of MMC2

3.015

6 IdcMMC(kA)

0.5

blockMMC3

0 –0.5 2.995

3

3.005

3.01

2 0

3.015

Time(s)

(d) DC currents measured at each MMC 1.4 1.2

0.5 0 PdcMMC1

3

3.01 3.02 3.03 3.04 3.05 3.06

(c) block signal of MMC3 1

-1 2.99

3

Time(s)

1.5

–0.5

IdcMMC1 IdcMMC2 IdcMMC3

4

–2 2.99

PdcMMC2

PdcMMC3

Vdc(p.u.)

blockMMC3

0

(a) block signal of MMC1

1

Pdc(p.u.)

blockMMC2

–0.5 2.995

1.5

1 0.8

VdcMMC1 VdcMMC2 VdcMMC3

0.6 0.4 2.99

3.01 3.02 3.03 3.04 3.05 3.06

3

3.01 3.02 3.03 3.04 3.05 3.06

Time(s)

Time(s)

(e) DC power measured at each MMC

(f) DC voltages measured at each MMC 1.5

1 ACCBclose1

0.5 0 –0.5 2.99

3

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

(g) ACCB closing order at MMC1

ACCBclose2

1.5 ACCBclose1

1 0.5

1 ACCBclose2

0.5 0 –0.5 2.99

3

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

(h) ACCB closing order at MMC2

Figure 29.11 ROCOV protection operation with temporary MMC blocking for a fault on cable 12. (a) Block signal of MMC1; (b) block signal of MMC2; (c) block signal of MMC3; (d) DC currents measured at each MMC; (e) DC power measured at each MMC; (f ) DC voltages measured at each MMC; (g) AC CB closing order at MMC1; (h) AC CB closing order at MMC2; (i) AC CB closing order at MMC3; (j) state of CB12; (k) state of CB21; (l) state of CB13; (m) state of CB31; and (n) DC cable currents.

453

29 DC Grid Fault Management and Protection System 1.5 CB12State

1 ACCBclose3

0.5 0 –0.5 2.99

3

CB12State

ACCBclose3

1.5

1 0.5 0 –0.5 2.99

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

3

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

(i) ACCB closing order at MMC3

(j) State of CB12 1.5

CB21State

1 0.5 0 –0.5 2.99

3

CB13State

CB21State

1.5

CB13State

1 0.5 0 –0.5 2.99

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

3

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

(k) State of CB21

(l) State of CB13 6

1.5 CB31State

1

Idc(kA)

CB31State

454

0.5 0

CB12 CB21 CB13 CB31

4 2 0 -2

–0.5

2.99

3

3.01 3.02 3.03 3.04 3.05 3.06 Time(s)

2.995

3

3.005

3.01

3.015

Time(s)

(m) State of CB31

(n) DC cable currents

Figure 29.11 (Continued)

4

3 Relay C34_4 S34_4

Relay C34_3 R34

CB34_4

S34_3 CB34_3

400 km 500 km

100 km

Figure 29.12 Differential protection system for the DC line 34.

not considering optical attenuation. This implies at least a 1 ms delay for each 300 km of cable length. The processing delays in microcontrollers and A/D signal conditioners may account for additional delays. Figure 29.13 illustrates the signal path in the differential protection system of cable 34 for a fault on cable 34 considering the DC grid in Figure 29.3. The fault happens at time 0, as shown on the x-axis and it is located 100 km from the bus 3, as shown on the y-axis. Each relay needs to receive information from two sensors (local and remote) in order to make a positive trip decision. The signal from the local sensor will include only travelling wave delay (around 1 ms for controller C34_3 in Figure 29.13), but the signal

29.8 Selective Protection for Star-topology DC Grids

bus 4 CB34_4

S34_4 trip CB34_4

Distance from bus 3 (km)

500 Relay C34_4

400 300

tt_4

200

tc_4 tc_3

100

bus 3 CB34_3

tt_3 – travelling wave delay to sensor S34_3 tt_4 – travelling wave delay to sensor S34_4 tc_3 – communication delay from C34_3 to C34_4 tc_4 – communication delay from C34_3 to C34_4

tt_3

Realy C34_3

0 S34_3 0

1

2

trip CB34_3 3 4 Time (ms)

5

6

Figure 29.13 Communication and wave delays with DC line differential protection.

from the opposite end will involve two delays: travelling wave delay and communication delay (around 4 ms for controller C34_3 in Figure 29.13). The travelling wave delays will be different for each sensor and will be dependent on the fault location, but the communication delays will stay constant regardless of the fault location. It can be seen in this particular example that the total time to trip DC CB34_4 is around 3 ms while trip time for DC CB34_3 is around 4 ms. The DC CB at the cable end further away from the fault location will always be the first to receive the trip signal. The fact that DC CBs at the two cable ends will not be tripped simultaneously may further complicate the situation in large DC grids. When the first DC CB is tripped, the system topology changes and now all of the remote AC sources begin to feed the fault through the DC CB at the other end of the faulted cable and therefore this DC CB may experience a larger trip current. An additional limitation of this protection method is the dependence on the communication equipment. The communications equipment may include many components and long optical cables, which raises concerns about reliability.

29.8 Selective Protection for Star-topology DC Grids It is highly desirable to have DC fault location logic that uses only local signals. Such logic would be very fast and reliable. Fast protection logic in turn implies that the interrupting fault current will be lower, and this has cost benefits for all grid components and DC CBs. A reliable protection logic based on local sensors is, however, feasible only with special star-grid topology, which has performance limitations. Figure 29.14 shows a four-terminal DC grid based on star topology. All of the DC CBs at the central bus use hybrid DC CB topology. Each VSC terminal includes an AC CB on the AC side of the converter, as would normally be the case with HVDC converters. A fault on cable 35 is shown which would be cleared by DC CB35_5 and AC CB_3. The direction of fault currents is given in red arrows. It can be seen that only one of the main DC CBs has a fault current in the positive direction (CB35_5).

455

29 DC Grid Fault Management and Protection System

2

1

ACCB_2

5a CB15_5

4

CB45_5

CB5b_a

ACCB_1

5b CB25_5 CB5b_b

456

CB35_5

3

ACCB_4

ACCB_3

Figure 29.14 Protection system for a four-terminal star-connected DC grid.

There is an independent protection system for each DC cable. It consists of a DC CB protection controller/relay and a local direction-sensitive current sensor. The protection logic is decentralised and uses only local signals, and the trip criterion is simple. A trip decision is made if the local current sensor detects the current over a threshold and in the positive direction. This implies that protection can operate as fast as hardware dynamics and processing speed will allow. Since hybrid DC CBs are employed, the total fault clearing time may not exceed a few milliseconds. A fault on any DC cable is cleared by one hybrid DC CB and one mechanical AC CB. A split bus at terminal 5 is used to increase reliability. There are two CBs at bus 5 which serve as backup protection. Their protection logic is same as for other DC CBs but a delay is added in the control circuit. If as an example CB35_5 fails to operate for a specified time interval then CB5b_a will operate and isolate bus 5b. Also ACCB_2 will isolate the fault infeed from AC grid at terminal 2. The AC CBs will need a small delay in control logic if backup protection is used. The above protection is applicable only to radial topologies and clearly cannot be used with meshed DC grids. Also, the number of DC lines connecting to a single DC bus will be limited by the DC CB rating, since each DC CB in an n-terminal system will have fault current summing from n − 1 VSC converters.

29.9 DC Grids with DC Fault-tolerant VSC Converters 29.9.1

Grid Topology and Strategy

The fault current in DC grids ultimately comes from AC systems through VSC converters. The study in this section aims to reduce the magnitude of DC fault current through VSC converters, ideally to values comparable with the rated DC current. Such a VSC converter would bring multiple benefits: • The insulated gate bipolar transistors (IGBTs) need not be tripped for DC faults. This means that control is retained through DC faults and post-fault recovery is fast.

29.9 DC Grids with DC Fault-tolerant VSC Converters

• The VSC converters would be able to indefinitely sustain the DC fault situation, and therefore fault clearing time can be extended to a range similar to that with AC systems (20–100 ms). This implies that simpler and more reliable grid-wide protection systems can be used. • The stresses on MMC reverse parallel diodes are reduced, implying cost savings in VSC converters. • If all VSCs in a DC grid can limit the fault current, then the magnitude of fault currents in all cables inside the DC grid will be low. This implies less costly DC CBs. Figure 29.15 shows a four-terminal DC grid which employs four DC fault-tolerant VSCs. If each VSC limits the fault current to 1 p.u., then the worst case fault current magnitude anywhere in the grid can reach 4 p.u. There are 21 DC CBs in this simple grid and the potential cost saving in using lower specification DC CBs, like mechanical DC CBs, is significant. The total cost of 21 hybrid DC CBs would amount to around 7 p.u. (where 1 p.u. is VSC converter cost), according to data in Table 24.1, which is almost twice the total cost of all VSC AC/DC converters in this grid. The total cost of mechanical DC CBs may amount to 0.1 p.u. Therefore, further investment in making VSC converters fault tolerant should be carefully explored. The sections below will review some options for limiting DC fault current in VSC converters. 29.9.2

VSC Converter with Increased AC Coupling Reactors

Figure 29.16 shows a VSC converter (two- or three-level, or HB MMC topology) connected to an AC grid through a reactor X t which can represent joint impedance of transformer and series reactor. It will be explored if an increased X t can sufficiently limit the fault current and what drawbacks would occur. The equation that gives the converter phasor current is: jXt Igdq = Vgdq − Vcdq

(29.1)

1

CB12_2

CB12_1 CB1b

CB25_2

5a CB15_5

4 CB4b

CB45_5

CB2b

CB23_2

5b CB25_5 CB5b_b

CB14_1

CB5b_a

CB15_1

2

3

CB35_5

CB14_4 CB45_4 CB34_4

Figure 29.15 Four-terminal DC grid with DC fault-tolerant VSCs.

CB23_3 CB3b CB35_3 CB34_3

457

29 DC Grid Fault Management and Protection System

S1

PCC

S5 Idc

Rdc I2

Ig

2Cdc

+

AC

Zs

Xt

–

AC

S3

AC

Zs

Xt

+

Zs

Xt Vg

2Cdc Vc

Vdc Vdc

–

458

Rdc S4

S6

S2

Figure 29.16 L VSC converter.

and when separated into real and imaginary components, assuming coordinate frame is linked with V g : Igd = − Igq =

Vcq

Xt Vg − Vcd Xt

(29.2) (29.3)

Assuming normal operation with Qg = 0, the reactive current becomes I gq = 0. From (29.3) it is seen that V cd = V g , and therefore this converter cannot achieve any stepping ratio V g /V c (transformers must be used if voltage stepping is required). Dividing (29.3) by (29.2) the current angle can be obtained and it can be concluded that this angle cannot be equal to voltage V c angle, and therefore this converter cannot have Qc = 0 (reactive power at converter AC bus). Consequently the converter voltage or current will be larger than the optimal value. Introducing the converter utilisation ratio U r : Ur =

Sgrid Sconv

(29.4)

where Sgrid is the required power at the grid coupling point (S1 in the above example) and Sconv is the required converter rating, which enables study of the required converter rating. The ideal utilisation ratio value is U r = 1 which implies that converter ratings (and therefore costs and losses) are optimal. The fault current for the above converter can be determined as: Vg Ifault =√ (29.5) g R2s + (Xs + Xt )2 Figure 29.17 in the left graph shows the required converter DC voltage (in p.u. relative to optimal DC voltage) and the utilization ratio U r , as the function of coupling reactance X t . Larger reactance will imply larger q component of AC voltage V c and consequently larger DC voltage. As DC voltage increases, the converter rating increases, the utilisation ratio will be lower and in practical terms this implies larger capital costs and also larger operating losses. Normally with HVDC converters the coupling reactance is 0.1 < X t < 0.2 and it can be seen that the DC voltage will be only 2–3% larger than optimal, plus perhaps a few percentage for control room.

29.9 DC Grids with DC Fault-tolerant VSC Converters

7 Fault current (p.u.)

1.2

Vdc

1.1 1

Ur

0.9

Normal design range

0.8 0.7

0

0.2

0.4 0.6 Xt (p.u.)

0.8

1

6

0 20 = 3 R = = 10 SC SCR

1.3

R

1.4

SC

Vdc (p.u.) and Ur (%)

1.5

5 4 3 2

SC R SC = 6 R =4

SCR

=2 Normal design range

1 0 0

0.2

0.4 0.6 Xt (p.u.)

0.8

1

Figure 29.17 Converter utilisation ratio and per unit fault currents as the function of interface reactance.

Figure 29.17 on the right-hand graph shows the fault current relative to converter rated current I g fault /I g for a range of grid strengths and coupling reactance values. It can be seen that it is possible to significantly reduce the fault current by increasing the coupling reactance. As an example, with short circuit ratio = 6 and X t = 0.9 p.u. the fault current will be around 1 p.u. Such a converter would have ∼35% larger costs and operating losses, as seen in the left-hand graph. On the positive side such design will imply a range of benefits as discussed above (no requirement for additional antiparallel diodes, lower rating for all DC CBs, simpler protection, etc.). 29.9.3

LCL VSC Converter

Figure 29.18 shows the LCL (L1 , C, and L2 ) VSC converter. It includes an AC/DC converter which can assume any topology (two- or three-level, or HB MMC) and an LCL interface. Compared with the L-interface, the LCL-interface brings more design flexibility, such as the possibility of voltage stepping, i.e. V g /V c , feasibility of achieving zero reactive power at both V g and V c , and reduced fault current (fault current is limited to close to the rated current). S7

S9

S11

I2dc Rdc I2

I2g

AC

Zs

L1

L2

AC

Zs

L1

L2

Zs

L1 Vg

Vcap

C

C

C

2Cdc

L2 Vc

+

Rdc S4

Figure 29.18 LCL VSC converter.

+

Vdc

–

2Cdc

–

PCC

AC

I1g

S6

S2

Vdc

459

460

29 DC Grid Fault Management and Protection System

The basic phasor equations for the LCL circuit in Figure 29.18 are: j𝜔L1 I1gdq = V1gdq − Vcapdq

(29.6)

j𝜔CVcapdq = I1gdq +I2gdq

(29.7)

j𝜔L2 I2gdq = Vcdq − Vcapdq

(29.8)

The above equations can be more conveniently written using parameters k 1 –k 3 as: I1gdq =

Vg k1 − Vcdq

Vcapdq = I2gdq =

(29.9)

j𝜔 × k3 Vg (k1 − 1) + (k2 − 1)Vcdq k2 k1 − 1

Vcdq k2 − Vg

(29.10) (29.11)

j𝜔 × k3

where k1 = 1 − 𝜔2 L2 C

(29.12)

k2 = 1 − 𝜔2 L1 C

(29.13)

k3 = L1 + L2 − 𝜔2 L1 L2 C

(29.14)

k1 < 1,

(29.15)

k2 < 1,

k3 < L1 + L2

The above parameters are introduced to enable the study of fault currents. In (29.9) parameter k 1 is the gain between V g and I 1g , and similarly, in (29.11) parameter k 2 is the gain between V c and I 2g . The final design parameters are L1 , L2 , and C, which can be obtained from (29.12)–(29.14) once k 1 , k 2 , and k 3 are finalised. The converter losses will be minimal when reactive power Qc = 0, implying ∠V c = ∠ I 2g , and it can be shown that this is achieved if k 2 = k 1 s2 , where the stepping ratio is s = V g /V c . The LCL VSC converter can achieve a 100% utilisation ratio at the rated power. The coefficient k 3 is dependent on the rated power only, and therefore k 1 is the only independent design parameter. The active and reactive power at V g can be controlled using DQ components of the converter voltage (through Md and Mq ) as with common L converters. The magnitude of the current through the converter for a DC fault (V dc = V c = 0) relative to the rated converter current r = I 2g fault /I 2g , can be determined from (29.9)–(29.11) as: 1 r2 = (29.16) −k12 s2 + 1 Figure 29.19 shows the fault current ratio from (29.16) as the function of design parameter k 1 and the stepping ratio s. It can be seen that the fault current will be close to the rated current for any stepping ratio and for wide range of k 1 . In general, it is always possible to design the converter to keep the fault current to within 1.2 p.u. In practice this result also implies that the converter will be able to operate under reduced DC voltage.

29.10 DC Grids with Full Bridge MMC Converters

3

1.8

0.4

0.6

=

0.8

1

s=0 .5

1.4 1.2 1 0

2

s = 0.5

2 s=

0.2

s=

1.6

=

1 0

=

0.8

s=0 . s=0 9 .8 s= 1.2 s

s

1.5

1.2

s

2

0. 9

s=

1

2.5

Vcap (p.u.)

1

DC fault current (p.u.)

=

2

s

3.5

0.2

0.4

k1

0.6

0.8

1

k1

Figure 29.19 LCL converter DC fault current (p.u.) and capacitor voltage (p.u.) (base is largest of V g and V c ) as the function of design parameter k1 , and stepping ratio s = V g /V c .

On the downside, as shown in the right-hand graph of Figure 29.19, the capacitor voltage V c will be typically 1.2–1.4 p.u. (relative to the larger of V g and V c ), which implies some cost penalties. Another drawback of this topology is that at partial load it will not be possible to maintain Qc = 0, which implies some more conduction losses. This drawback can be resolved if capacitor size is reduced at partial load, which can be achieved with switchable capacitor banks. If DC fault reduction is of the highest priority, it is likely that the LCL converter will have overall advantages over the common L converter. 29.9.4

VSC Converter with Fault Current Limiter

It is discussed in Section 28.8 that a semiconductor or hybrid DC CB can be employed as a fault current limiting device. The DC CB main switch is in such case operates periodically, not unlike a DC chopper, under an active feedback current control loop. The current can be controlled to low values even under worst-case DC faults, but the duration of this operating mode is limited by the energy capability of switches, surge arresters, and the cooling equipment. Figure 29.20 shows the VSC converter with DC CB acting as a fault current limiter. Jointly with DC CB, this converter can limit the fault current like any of the topologies in previous sections. Some manufacturers are proposing to standardise a seven-switch VSC converter, as in Figure 29.20, which has the capability of DC fault current limiting and interrupting.

29.10 DC Grids with Full Bridge MMC Converters Full bridge MMC converters can operate with low DC voltage; they can limit the DC fault current or bring the DC fault current to zero, as discussed in Sections 20.6 and 22.8. It has been concluded that it is not recommended to block full bridge (FB) MMC under DC fault conditions. If all converters in a DC grid use FB MMC topology, then there are opportunities for substantially reducing the costs of DC grid protection system. A possible protection system is studied on a four-terminal DC grid with all of the FB MMC converters shown in Figure 29.21 (this is a segment of the CIGRE DC grid test

461

29 DC Grid Fault Management and Protection System

S1

S3

Idc

S5

DCCB

Rdc I2

PCC

Ig

+

Zs

Xt

AC

Zs

Xt

+

Zs

Xt

Vdc Vdc

–

AC

–

AC

Vg

Vc

Rdc S4

S6

S2

600 MVA

MMC2

600 MVA

MMC1

200 km

CB

_1

CB_11_4

_2

SA0

FB MMC Mechanical DCCB

Flt_1_2

DC Overhead line AC Overhead line

1 CB_12_4

200 km

+400 kV

Figure 29.20 VSC converter with a DC CB operating as a fault current limiter.

Flt_4_2 200 km

+400 kV SB0

2

200 km

CB_2_4

CB_2_3

400 km 4

CB_4_2

600 MVA

MMC4

+400 kV

CB_2_1

CB_4_12

Flt_4_11 Flt_2_4

CB_4_11

50

0k

m

400 km

Flt_11_4

Flt_2_1

300 km

Flt_2_3 200 km

462

MMC3 600 MVA

Flt_3_2

CB_3_2

+400 kV 3

Figure 29.21 Four-terminal DC grid with all FB MMC converters and mechanical DC CBs.

29.10 DC Grids with Full Bridge MMC Converters

3 2.5 2 1.5 1 0.5 0 –0.5 –1 –1.5 0.98

Idcpu_MMC1

Idcpu_MMC2

Idcpu_MMC4

Idcpu_MMC3

Vdc _MMC1

Vdc _MMC4

Vdc _MMC3

MMC1,2

1

MMC1,2

0.8 MMC4

0.6 0.4

MMC3

0.2 0

MMC3 1

–0.2

1.02 1.04 1.06 1.08

P_MMC1

P_MMC2

1.1

1.12 1.14 1.16 1.18

MMC4

–0.4 0.98

1.2

1

1.02 1.04 1.06 1.08

1.1

Time (s)

Time (s)

(a)

(b)

P_MMC3

P_MMC4

1.2

6

Idc_CB_11_4

1.12 1.14 1.16 1.18

1.2

1.12 1.14 1.16 1.18

1.2

Idc_CB_4_11

5

0.8 MMC1,2 0.4

4 I (kA)

P (p.u.)

Vdc _MMC2

1.2

Vdc (p.u.)

Idc (p.u.)

system). Each FB MMC can control terminal DC current in the case of DC faults; however, they cannot directly control line currents. Line currents will include a DC system energy discharge component which may have long time constants. For these reasons it may not be feasible to employ zero-current disconnectors on lines in such DC grids, or if they are used the operating time will be prolonged. Evidently there is no need to use fast DC CBs, and therefore a lowest-cost mechanical DC CB would suffice. A further benefit would be in reducing the size of series inductors Ldc . Since the speed of protection system operation is not a critical factor in DC grids with FB MMC, differential protection may be a good choice. Unlike ROCOV protection, differential protection can operate with very low values of series inductors Ldc . Figure 29.22 shows the simulation of Flt 11_4. All FB MMC are configured to control DC current to 0.15 kA in the case that a DC fault condition is detected. All DC CBs assume a mechanical topology with 8 ms opening time and very small series inductors are used, Ldc = 5 mH. It can be seen that FB MMCs can reduce local currents and all DC voltages within 10–20 ms. This helps to reduce stresses on DC CBs. The DC CBs on the faulted line interrupt very low current ∼30 ms after the fault. DC grid voltage is restored 70 ms after the fault. Table 29.3 shows the key performance indicators for all faults shown in Figure 29.21. The peak fault current and energy dissipation in DC CBs are very low and substantially lower than in the case of the DC grid based on HB MMC converters. An additional benefit of this topology is that there is no blocking of MMC converters and this implies that reactive power control is undisturbed and there is no risk of loss in capacity for DC faults. On the downside, the recovery time is somewhat longer than with a DC grid based on HB MMC and Table 29.3 indicates 110 ms to be the worst case.

0 MMC3

–0.4

CB_11_4

3 2 1 0

–0.8

MMC4

CB_4_11

–1

–1.2 0.9 0.95 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 1.45 1.5 1.55 1.6

–2 0.98

1

1.02 1.04 1.06 1.08

1.1

Time (s)

Time (s)

(c)

(d)

Figure 29.22 Response of four-terminal DC grid with all FB MMC converters for a DC fault Flt 11_4. (a) MMC DC currents; (b) MMC DC voltages; (c) AC power of each MMC; and (d) DC line currents.

463

464

29 DC Grid Fault Management and Protection System

Table 29.3 Key performance indicators for all faults on DC grid shown in Figure 29.21. Interrupting current (kA) Fault location

Recovery time (ms)

Fault end

1_2

75

0.3

2_1

62

−1.8

Opposite end

DC CB energy (MJ) Fault end

Opposite end

−0.02

0.0018

0.0017

−0.7

0.013

0.022

2_3

70

−1.5

1.8

0.009

0.001

3_2

110

−1.5

0.1

0.001

0.37

2_4

65

−0.7

−0.9

0.016

0.016

4_2

65

−0.4

−0.3

0.0001

0.0005

11_4

70

0.3

−0.02

0.017

0.016

4_11

60

−0.06

−0.2

0.0001

0.0004

465

30 High Power DC/DC Converters and DC Power Flow Controlling Devices 30.1 Introduction It is expected that DC grids will eventually evolve into large meshed networks which will inevitably have multiple DC voltage levels. A DC/DC converter will be needed in order to connect two DC grids operating at different DC voltage levels. One evident DC/DC application is to connect DC cables (which have the highest DC voltage of 600 kV) with overhead DC lines which may have higher DC voltage. The existing high voltage direct current (HVDC) links have a wide range of highly optimised DC voltage levels, and their possible integration into a DC grid may require DC/DC converters. It is also expected that medium voltage DC grids, either distribution or collection systems (like those with offshore wind farms) will rapidly develop following acceptance of DC transmission grids, and their connection to DC transmission will require high-stepping-ratio DC/DC converters. This role is similar to a transformer function in traditional AC systems. Nevertheless, even in a DC grid with a single nominal DC voltage, there might be a need for DC/DC devices in order to regulate power flow in some cables or DC voltage level at some nodes. These devices may have low stepping ratio and perform a similar function to tap changing transformers and phase shifting transformers in AC systems. The power flow in DC grids will be primarily controlled using AC/DC converters located at grid terminals (connecting points with external AC grids). Assuming an n-terminal DC grid, it is theoretically possible to control power flow in up to n DC cables, with an allowance for inaccuracy because of DC voltage droop feedback. If the number of DC cables is greater than n then power flow cannot be controlled in each cable. A complex DC grid may have large number of meshed DC lines, since in a n-terminal DC grid it is possible to connect (n2 − n)/2 cables. It is also beneficial to include some uncontrolled DC substations (as access points to new connections) and in such cases it is not possible to precisely control the power in each DC cable. In order to avoid DC line overloading or underutilisation there is a need for special DC power controlling elements. These devices could be installed in series with DC cables in order to adjust (increase) the cable resistance or to regulate DC voltage. Figure 30.1a shows a five-node, four-terminal (four AC/DC converters) DC grid with seven DC lines. All busses have same nominal DC voltage level. The DC cable 1–5 may be very short (with low resistance) and if it connects to a large rectifier (terminal 1) it will have high current. Another possible need for DC power flow device will be if there is the intention to interconnect two established DC systems. The DC voltage difference of several kilovolts High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

466

30 High Power DC/DC Converters and DC Power Flow Controlling Devices w flo er vice w e po l d o DC ontr c

Rectifier 1

1

Inverter DC power flow control device 2 4

5

4

5

3 (a) DC/DC device used to adjust line resistance

2

6

Rectifier 7

3 (b) DC/DC device used to overcome DC voltage difference

Figure 30.1 Applications of power flow controlling device in DC grids.

might be too large for direct connection using a DC cable. Also, it is understood that DC power flows only from higher DC voltage to lower DC voltage, which might not always be consistent with the desired power flow direction. Figure 30.1b shows an established DC grid (terminals 1–5) and a new DC grid (terminals 6–7) in the vicinity which have the same nominal DC voltage. If terminal 1 is a large rectifier and terminal 6 is an inverter connected to a long DC cable 6–7, the DC voltage difference between busses 1 and 6 may be of the order of 5–10 kV and it may be difficult to directly connect these busses with a short DC cable. In such a case two options are available: • reduce operating voltage on the DC grid 1–5 with the associated reduction in capacity and increased losses; and • incorporate a DC/DC converter with low stepping ratio in the new DC line.

30.2 Power Flow Control Using Series Resistors A simple solution for DC power flow control is by using resistors which can be inserted in series with DC lines. The resistance value should be comparable with the DC cable resistance. A typical 1600 mm2 submarine DC cable has a resistance of around 0.01 Ω km−1 , and therefore several ohms will be the largest required resistance. Assuming a typical ampacity of 1400 A for a 320 kV DC cable there will be loss of 2 MW for each additional 1 Ω of resistors. This heat dissipation is direct revenue loss but also large cooling equipment implications should be considered. Consequently this method might be attractive only if small additional resistance is required. Figure 30.2 shows the total loss in the resistors dependent on the DC voltage stepping ratio d = V dc2 /V dc1 , where the base power is assumed as Pdc = 320 kV × 1.4 kA = 450 MW. The loss becomes substantial if the device is used for DC voltage matching over 1%. Figure 30.3a shows the DC power flow-controlling device based on series resistors with mechanical switches, where n identical series units are assumed. Each unit can be independently controlled in or out of the current path. The mechanical switches are DC circuit breakers (CBs) which must have the capability of breaking and making the rated

30.2 Power Flow Control Using Series Resistors

Total power loss (%), R (Ohm)

3

Vdc = 320 kV Idc = 1400 A

2.5 Se

r ie

sr es

2

ista

nc e( oh

m)

1.5 Powe r lo

ss (%

1

)

0.5 0 0.986

0.988

0.99

0.992 0.994 stepping ratio d

0.996

0.998

1

Figure 30.2 The series resistance value and total resistor loss depending on the stepping ratio V dc2 /V dc1 .

Idc Vdc1

SA1

SA2

SAn

CB1

CB2

CBn

R1

R2

Rn

Vdc2

(a) Series resistors with mechanical switches Idc Vdc1

T1a

T1b R1

SAn

SA2

SA1 T2a

T2b

Tna

R2

Tnb Rn

Vdc2

(b) Series resistors with semiconductor switches

Figure 30.3 Power flow controlling device based on n series resistors.

DC current. The DC CB voltage rating will be equal to the voltage drop across resistors. The current flows either through the CB (CB closed), providing low resistance, or through the resistor (CB open), providing higher resistance. Surge arresters are required since the voltage across resistors will be large in the case of DC line faults or resistor open-circuit failure. Considering that the device is based on mechanical contacts it will have negligible switch losses and the costs will be reasonable. On the downside the wearing of contacts may become an issue if many switch operations are required. In the power flow control application, it is expected that the device will be operated frequently. Some CB manufacturers specify up to 20,000 maximum operations for DC CBs under rated conditions. The additional disadvantage of this device is the speed of operation. The commercial units have total operating speeds in tens of milliseconds. Clearly this limits operating flexibility if the device is used for dynamic power flow control.

467

468

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

Figure 30.3b shows the DC power flow controlling device based on series resistors with semiconductor switches. Two insulated gate bipolar transistors (IGBTs) (or insulated gate commutated thyristor technologies) are assumed in each unit considering two possible current directions. Each unit can be separately controlled by simultaneously setting both transistors a and b ON or OFF. Similarly to the mechanical device, the current flows either through the switches (switches T a and T b ON), providing low resistance, or through the resistor (switches OFF), providing higher resistance. The switches may not require additional snubbers, depending on the parasitic inductance of the resistors. With some more complex pulse width modulation control and additional components the device could be configured to make continuous adjustment of resistance. The number of ON/OFF operations is virtually unlimited and the speed of operation is excellent. On the downside, this device will require cooling systems for semiconductor switches since they will be continuously in an ON state, with the requirement for a valve hall. The ON state losses are another disadvantage compared with the mechanical devices. Example 30.1 A 1.6 kA DC line requires a series mechanical power flow controlling device with 15 control positions and a total resistance of 1.2 Ω. Determine the rating of DC CBs. Calculate the voltage stress across each DC CB in the case that the maximal DC fault current reaches 30 kA. Solution Each resistor will have resistance of: R1 = Rtot /n = 1.2/15 = 0.08 Ω The voltage stress across each DC CB will be V 1 = R1 × I r = 0.08 Ω × 1600 A = 128 V Allowing a twofold voltage margin, each DC CB should be rated for V 1r = 256 V. In the case of a 30 kA fault current, the voltage across a DC CB (which is OFF) will be V1f = R1 × If = 0.08 Ω × 30,000A = 2400 V. Therefore a surge arrester should be appropriately designed to limit the voltage stress. Example 30.2 A semiconductor-based series power flow control device uses seven resistor units of 0.3 Ω each. The IGBT switch data are shown in Table 30.1. The nominal DC current in this 500 kV DC line is 1400 A. Determine total losses in semiconductors when all of the resistors are bypassed. Solution The device consists of seven units and therefore there are seven IGBTs and seven diodes in the current path. Ploss = 7 × 2.4 × 1400 + 7 × 1.6 × 1400 = 39.2 kW The percentage loss is: Ploss% = Ploss∕ Pr = 39.2 kW∕(500,000 × 1400) × 100 = 0.0056% Table 30.1 Basic data for the IGBT switch in Example 30.2.

V CE (V)

IC

IGBT on state voltage V CE (V) (1400 A)

Diode on-state voltage V F (V) (1400 A)

1700

1600

2.4

1.6

30.3 Low-stepping-ratio DC/DC Converters (DC Choppers)

30.3 Low-stepping-ratio DC/DC Converters (DC Choppers) 30.3.1

Converter Topology

A bipolar, low-stepping-ratio DC/DC converter is shown in Figure 30.4. It connects two bipolar DC grids that nominally have the same DC voltage levels but because of power flow conditions their DC voltages will differ. The topology is similar to buck–boost converters used widely in low-power applications. The switch S1 is switched ON/OFF at a constant operating frequency but with varying duty ratio d = T on /T as shown in Figure 30.4, while S2 switch is operated in a complimentary manner. The converter is bidirectional, since current can reverse direction. Note that V dc1 < V dc2 (inductor always connects to lower DC voltage) must be satisfied and voltage cannot change polarity. If voltage V dc1 is expected to become larger than V dc2 in some operating conditions, then an H-bridge topology is needed (another converter leg is added as shown in Section 30.3.4) and costs double. The converter is bipolar and each pole will have an independent controller and can operate independently. In the case of DC faults on DC grid 1 (on the lower voltage side), the current through the converter will be increasing while the rate is limited by the inductor. This converter is capable of interrupting DC fault current by opening switch S1 (either S1p for positive pole faults or S1n for faults on negative pole). However, the converter cannot interrupt faults on DC grid 2, since diodes D1 would uncontrollably transfer fault currents. Note also that DC fault interruption depends on the controller speed and there will be some transient overcurrent. This DC/DC converter can perform the following functions in a DC grid: matching DC voltages; regulating power flow; interrupting DC fault current (for faults on V dc1 only); and balancing of loading between DC poles.

– +

Vdcs1p

Vdcs1n Rdc1

Vdc1p D2p

Rl2p

Idc2p

D2n

Vdc1n

Rdc2

Vdc2p S1p C S2p p

Igdcdc

DC cable 1n Idc1n Ln DC grid 1

D1p

S2n

DC cable 2p Vdc2sp

D1n

S1n

Vdc2n

Idc2n

Bipolar DC/DC converter

S1p

Idcc2

Vdc2sn Rdc2

TS1p TonS1p

S1n

on off on

S2p Rl2n

Cn

– +

Igdc1

DC cable 1p

Idc1p Lp

– +

– +

Rdc1

DC Load

(1) (2) (3) (4)

off on off

TS1n TonS1n

on off on S2n

dp =TonS1p/Ts1p

DC cable 2n DC grid 2

Figure 30.4 Topology of bipolar DC/DC converter connecting DC grid 1 and DC grid 2.

off on off

dn =TonS1n/Ts1n

469

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30 High Power DC/DC Converters and DC Power Flow Controlling Devices

This topology will suffer from all the challenges associated with first-generation two-level voltage source converter (VSC) HVDC converters. Each valve (S1 and S2) is built from numerous series-connected IGBTs which should be switched simultaneously. This implies significant voltage stress, harmonics, and switching losses. Also, this topology cannot provide electrical isolation. 30.3.2

Converter Controller

A possible controller for the above converter is shown in Figure 30.5. It has an independent controller for each pole, and each controller has two cascaded stages. In the inner loop, the DC current is regulated in order to prevent high currents in the switches and to improve the response of the outer loops. In general a DC/DC converter will be able to control one DC grid variable, but there is a wide range of possible control options and the selection will depend on the particular application and the operating scenario. The DC voltage is controlled in the outer loop in Figure 30.5. This control method might be appropriate for a DC/DC converter inside a large DC grid and at a remote location, far from other terminals. It can operate indefinitely in DC voltage mode without any communication. If the desired DC voltage cannot be achieved, the inner control loop will saturate and the converter will operate on maximum current. An alternative control strategy might be constant current/power in the cable, or constant stepping ratio. In such a case, this converter would be required to also respond to DC voltage variation, using droop feedback, in similar manner to with AC/DC converters. The current balancing control is used at the highest level to modulate the DC voltage reference. It can balance an unbalanced LV (low-voltage) side DC pole. When it is enabled, the controller can eliminate LV ground current, but this will generally result in some HV (high voltage) side unbalance. Example 30.3 A DC/DC converter is required to connect a 370 kV DC bus with a 400 kV DC system. The converter rating is 1800 A and assume that DC cable resistance on the 400 kV side is 2 Ω while on the 370 kV side it is 1 Ω. It is necessary to keep DC current deviation to 6%, and the switching frequency is limited to 1500 Hz in order to reduce switching losses.

Vdc2refp0

Vdc2refp

+ +

+ –

Filter

Idc1n

Filter

+ –

klb/s

kppv

Idc1refp

+ +

+ –

On/off

Vdc2p

Filter

kppi

+ +

dp

klpi/s

klpv/s

LV side Current balancing Idc1p

DC current control

DC voltage control

Idc1p

Filter

0 Vdc2refn0

– +

Vdc2refn

DC voltage control + –

kppv

Idc1refn

+ +

klpi/s

klpv/s Vdc2n

Filter

+ –

DC current control dn kppi + +

Idc1n

Filter

Figure 30.5 Controller for bipolar low stepping ratio DC/DC converter.

30.3 Low-stepping-ratio DC/DC Converters (DC Choppers)

(1) (2) (3) (4)

Determine values for the converter inductor L. Determine converter utilisation ratio. Design a feedback controller and simulate converter response to V dc2 drop to 395 kV. Simulate converter response to 300 Ω unbalanced shunt load on the negative pole of grid 2.

Solution (1) The converter duty ratio d is: d=

Vdc1 = 0.925 Vdc2

The inductor value is calculated as: ΔI L dc1 = ΔV Ton 30,000 × 0.925 ΔV d L= = = 0.2 H f 0.06Idc1 1500 × 0.06 × 1800 (2) The converter utilisation ratio is: V UR = dc1 = 0.925 Vdc2

(30.1)

(30.2)

(30.3)

(3) The DC voltage difference is 30 kV and if the two grids are directly connected the DC current will be 10 kA, implying DC cable overload. Because of the large DC voltage difference it would not be cost-effective to use series resistors. At 1500 A converter current (83% load), the converter regulated voltage is V dc2 = 400 − 1500 × 2 = 397 kV. The converter testing results are shown in Figure 30.6. The following intervals are seen: • Before 1 s the converter is regulating V dc2 = 397 kV and the power transfer is 600 MW towards grid 1 (step-down operation). • At 1 s, there is a significant drop in V dc2s to 395 kV. The converter controller maintains V dc2 = 397 kV, which is achieved by power reversal through a DC/DC converter, which now feeds 400 MW to grid 2. This example illustrates the DC/DC converter capability to support DC grid stability, and to transfer power to a DC grid with higher DC voltage. • At 1.5 s there is unsymmetrical load on grid 2 while DC current balancing is disabled. • The converter manages to maintain balanced voltage V dc2p = V dc2n = 397 kV and there is no ground/neutral current in grid 2. The power required to balance grid 2 is drawn from grid 1, requiring large ground current I g1 . • At 2 s, the current balancing control is enabled and grid 1 ground current is eliminated. However DC grid 2 becomes unbalanced as a consequence.

30.3.3

DC/DC Chopper Average Value Model

An average value model for a low-stepping-ratio DC/DC converter is shown in Figure 30.7. It consists of a controlled voltage source on the LV side and a controlled

471

398

Vdc2refp

397.5

Vdc2p Vdc2n

Vdc2n

396.5

Vdc2refn

396

Vdc2n

395.5

1 Current (kA)

397 Voltage (kV)

1.5

0.5 0 –0.5

Vdc2p

395 394.5 394

1

1.2

1.4

1.6 time (s)

1.8

2

1

2.2

1.2

1.4

1.6 time (s)

1.8

2

2.2

2

2.2

600

0.4 0.3

Ig1

200 Power (MW)

0.2 Current (kA)

Idc1n

–1.5

0.5

0.1 Ig3

0 –0.1

Ig2

–0.2

200 0

–200

–0.3

Pp

–400

–0.4 –0.5

Idc1p

–1

Pn 1

1.2

1.4

1.6 time (s)

1.8

2

2.2

–600

1

1.2

1.4

1.6 time (s)

1.8

Figure 30.6 Demonstration of bipolar DC/DC converter operation in V dc2 control mode: at 1 s there is a significant voltage drop in grid 2; at 1.5 s the unbalanced load is added in grid 2; at 2.0 s DC current (Idc1 ) balancing controller is enabled.

30.4 Non-isolated MMC-based DC/DC Converter (M2DC)

Idc1p

+

Filter

–

kp1

+

dp +

kl1/s

Current controller

Idc2p Idc2cp

Vdc2p X

Lp Idc1p V1I1 = V2I2

Idc2cp

Vdc1cp

Vdc2p

+

Idc1pref

Vdc1cp

Vdc1p

Cp

–

X

Idc1p

Figure 30.7 Averaged continuous model of bidirectional DC/DC converter. Figure 30.8 H-Bridge monopolar DC/DC chopper.

Idc2p

Idc1p D1p

D3p Vdc1p S3p L p C1 D 4p

C2

D2p S4p

Vdc2p

S1p

S2p

current source on the HV side. Note that the LV side is interfaced with an inductor but the HV side is connected using a capacitor. The power balance equation V dc1 I dc1 = V dc2 I dc2 (assuming a lossless converter) is used as a simple approximation to link the two sides. This model can be used for power flow studies in DC grids. It also has good dynamic representation in the frequency range of control loop dynamics. However, the simplified model will not accurately represent harmonics or internal faults. 30.3.4

H-Bridge DC/DC Chopper

Figure 30.8 shows one pole of a full bridge (FB) DC/DC converter. It resembles the topology in Figure 30.4 but it includes another two-valve converter leg, and therefore the number of switches is doubled. This converter can accommodate operation with V dc1 < V dc2 or V dc1 > V dc2 . Also, it can interrupt DC faults on either a DC grid 1 or a DC grid 2. Similarly as for the converter in Figure 30.4, this converter can be used only for a small voltage stepping ratio (say 0.8–1.2). It is not suitable for larger stepping ratios because extreme duty ratios cause significant reverse recovery losses in diodes and low utilisation ratio.

30.4 Non-isolated MMC-based DC/DC Converter (M2DC) 30.4.1

Introduction

Figure 30.9 shows the topology for a non-isolated MMC-based DC/DC converter which has attracted a lot of attention because of its modest cost and losses while a wide range

473

474

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

Idc1

VH IH

LH

LH

LH

LL

LL

IL2 LL

Vdc1 (H.V.) IL

L2 L2 L2

Idc2

Vdc2 (L.V.)

VL

Vdc1 > Vdc2

Figure 30.9 Non-isolated, MMC-based DC/DC converter.

of stepping ratios can be used. It enables power exchange between two DC grids, where one pole is common and voltage is adjusted on the other pole such that V dc1 > V dc2 . This converter can be used for interconnecting two monopolar DC systems. It requires a minimum of four valves (two legs), but depending on the required power level, any number of legs can be employed. The half bridge valves can be used on the LV side while FB valves are required on the HV side to enable operation through all DC faults. More precisely, the minimum voltage rating of the string of FB cells in the valves on HV side is V dc2 . It is noticed that DC current running from one DC grid to another passes through one valve only. This implies that semiconductor count and conduction losses will be low.

30.4.2

Modelling and Design

A set of essential steady-state equations will be derived to enable understanding of operating principles and component dimensioning. The basic assumptions in the following derivations are: • the converter is symmetrical and balanced; • all of the internal losses are neglected; • the arm voltages are assumed to have ideal sine waveforms with possibly non-zero average.

30.4 Non-isolated MMC-based DC/DC Converter (M2DC)

It is assumed that arm voltages and currents consist of DC and AC components: vH = VHdc + vHac

(30.4)

vL = VLdc + vLac

(30.5)

iH = IHdc + iHac

(30.6)

iL = ILdc + iLac

(30.7)

The DC and AC circuits will be analysed separately as shown in Figure 30.10. Neglecting AC variables, the following DC circuit equations can be derived: Idc1 = 3IHdc

(30.8)

Idc2 = 3IHdc + 3ILdc

(30.9)

Vdc1 = VHdc + VLdc

(30.10)

Vdc2 = VLdc

(30.11)

For a given DC power transfer: (30.12)

P = Vdc1 Idc1 = Vdc2 Idc2 Considering (30.8)–(30.11) the DC power on each valve is:

1 1 (30.13) I (V − Vdc2 ) = Vdc2 (Idc2 − Idc1 ) 3 dc1 dc1 3 The cells in valves can be considered as switched capacitors with constant DC voltage. Positive DC current through cells implies that capacitors are charging. In order to provide balanced (zero sum) power on each valve, another current component must be provided to remove power from the valve. This can be achieved using AC current, which PLdc = −PHdc =

– +

Idc1 VHdc IH

LH L2

Vdc1

VLdc

ILac

IHac LH

LL LL

Vdc2

– +

IL

Idc2

(a) Equivalent DC circuit

AC

VLac

IL2

L2

VHac

AC

(b) Equivalent AC circuit

Figure 30.10 Equivalent circuit for non-isolated, MMC-based DC/DC converter.

475

476

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

circulates between the upper and lower arms. Since the upper and lower arms have different signs for DC power, the AC power equal to (30.13) should be exchanged between the upper and lower arms. Therefore the power balance equation is derived: (30.14)

PLdc = −PLac = −PHdc = PHac

Considering the equivalent AC circuit in Figure 30.10b, the AC circuit equations are: VLac = ILac jX L − IHac jX H − VHac ,

(XL = 𝜔o L)

VLac = ILac j(XL + X2 ) − IHac jX 2

(30.15) (30.16)

where 𝜔o = 2𝜋 f o is the inner AC frequency of the DC/DC converter. The AC currents through the converter valves I Hac , I Lac , and I 2ac are derived from (30.15) and (30.16): IHac = j

VLac X2 + VHac (XL + X2 ) XL X2 + XH X2 + XH XL

ILac = −j I2ac = j

VHac X2 + VLac (XH + X2 ) XL X2 + XH X2 + XH XL

VHac XL + VLac XH XL X2 + XH X2 + XH XL

(30.17) (30.18) (30.19)

The arm voltages can be expressed using modulation indices, consisting of DC modulation index Mdc and AC modulation index Mac = Macd + jMacq as with all modular multilevel converters (MMC). Assuming that the coordinate frame is linked to the V Hac voltage, the AC components of the arm voltages are: VHac = MHacd VHM

(30.20)

VLac = (MLacd + jMLacq )VLM

(30.21)

where VHM and VLM are maximal arm voltages, equal to the sum of all cell voltages in corresponding arms, defined similarly to MMC AC/DC converters in Chapter 19. These are rated arm voltages, and normally they should be VHM =VLM =V dc1 . Therefore the arm voltages in the time domain are written as: VH = (MHdc + MHac cos(𝜔o t))VHM

(30.22)

VL = (MLdc + MLac cos(𝜔o t + 𝜃L ))VLM

(30.23)

The modulation indices should satisfy: MHdc + MHac ≤ 1 MLdc + MLac ≤ 1

(30.24)

This equation determines the maximum range for AC modulation indices considering that the DC modulation indices can be determined from (30.10)–(30.11). The active component of AC power on each arm is derived from (30.17) and (30.20): Pac = Re(VHac IHac ∗) =

MLacq MHac VHM VLM X2 XL X2 + XH X2 + XH XL

(30.25)

30.4 Non-isolated MMC-based DC/DC Converter (M2DC)

The required AC power exchange is determined from rated DC power exchange as in (30.14), and therefore (30.25) is used to determine values for arm inductors LL and LH , and also for star-point inductors L2 . However transient and fault responses will also impose further design restrictions for these inductors. 30.4.3

Design Example and Comparison with MMC AC/DC

This section examines the impact of converter stepping ratio on the converter ratings, and the design limitations. A P = 600 MW, V dc1 = 320 kV, f o = 350 Hz converter is considered, where a range of V dc2 is examined. The maximum AC power exchange can be achieved for 𝜃 L = 90∘ , but a more realistic case 𝜃 L = 60∘ is considered to allow some control margin, but also to acknowledge internal losses and harmonics on capacitor voltages. The AC power can be increased with lower inductances, as seen in (30.25); nevertheless, practical aspects (faults, harmonics) will impose limitations and the following realistic values are adopted: Lh = Ll = 6 mH, L2 = 60 mH. The foremost question related to this converter is if it is possible to balance AC and DC power assuming that valves are rated for optimal voltages V H M = V L M = V dc1 . The AC and DC power share a modulation index as seen in (30.24) and therefore restrictions may apply on either DC or AC power. Figure 30.11 shows valve DC power Pdc and maximum possible AC power Pac for a range of voltage 0 < V dc2 < 320 kV. The AC power is restricted since the magnitude of AC modulation index is restricted. The largest AC modulation index (Mac = 1/2) is achieved for V dc2 = 1/2V dc1 . The converter can operate only if the available AC power is larger than the DC power transfer and therefore the stable region for this converter would be limited to ∼90 kV < V dc2 < 280 kV. If the converter is to be operated outside this range it is necessary to increase valve voltage rating. Figure 30.12a shows the required valve voltage rating to enable operation in the full range of 0 < V dc2 < 320 kV. It is seen that the valve voltage rating is increased over V dc1 for low and high V dc2 . It is concluded that converter would require ∼3% higher arm 400 350

Pac and Pdc (MW)

300 Pac

250 200 150

Pdc

100 50 0 0

Stable region (Pac > Pdc) 50

100

150 200 Vdc2 (kV)

250

300

Figure 30.11 Valve DC power and maximum possible AC power assuming V H M = V L M = V dc1 . P = 600 MW, V dc1 = 320 kV, 𝜃 L = 60∘ , f = 350 Hz, Lh = Ll = 6 mH, L2 = 60 mH.

477

440

10

Converter currents (kA)

Arm voltage (kV)

420 400 380 360 340

8

6

Idc2/3 2

320 300 0

50

100

150 200 (a) Valve voltage

250

0 0

300

Ilac

Ihac 4

Idc2/3−Idc1/3

Idc1/3

50 100 150 200 250 (b) Peak AC and DC currents in valves

300

10

1.5

Ihpeak, Ilpeak (kA)

8

I2peak (kA)

1

0.5

Ilpeak

6 Ihpeak 4 Ipeak MMC AC/DC 2

0 0

50

100

150 200 Vdc2 (kV) (c) Peak I2 current

250

300

0 0

50

100

150 200 250 Vdc2 (kV) (d) Peak currents in valves

Figure 30.12 MMC DC/DC design for a range of V dc2 . P = 600 MW, V dc1 = 320 kV, 𝜃 L = 60∘ , f = 350 Hz, Lh = Ll = 6 mH, L2 = 60 mH.

300

30.4 Non-isolated MMC-based DC/DC Converter (M2DC)

voltages (VHM = VLM = 330 kV) if a 600 MW converter is installed in the system with V dc2 = 310 kV. It is convenient that valve power reduces as stepping ratio approaches 1, and therefore only a marginally higher valve voltage rating is required. Figure 30.12b shows the valve DC current, peak AC current and also LV side DC current. This figure indicates that current ratings are lowest for high V dc2 , and also that this design is not suitable for very low V dc2 . Figure 30.12c shows the peak current in inductor L2 , which is important for inductor costs and losses. Figure 30.12d shows the valve peak current (sum of DC and AC currents). This is the most important criterion for converter losses and a significant cost indicator. For comparison, the peak valve current of a 600 MW, 320 kV MMC AC/DC converter is also shown (1.85 kA). It is seen that for voltages V 2 > 180 kV the valve currents would be similar or below currents of a comparable AC/DC converter. The design graphs for a range of Ll = Lh (1 mH < Ll = Lh < 20 mH) are shown in Figure 30.13. The conclusion is that higher arm inductances will imply higher valve currents and may also require increased arm voltage rating. 30.4.4

Controller Design

A DC/DC converter can regulate a single DC grid variable which can be chosen depending on requirements. A number of other internal DC/DC variables should be controlled to enable safe operation of the converter. One possible selection for the main goals of MMC DC/DC converter controller is: (1) (2) (3) (4) (5)

Regulate sum arm voltage for upper arm, VHM . Regulate sum arm voltage for lower arm, VLM . Regulate power exchange between two DC grids, P (DC grid variable). Regulate DC current in the upper arms, I Hdc . Regulate DC current in the lower arms, I Hdc .

The control variables that are available are: (1) DC component of upper arm modulation index MHdc . (2) DC component of lower arm modulation index MLdc . 360

2.5

Ihpeak, Ilpeak (kA)

Arm voltage (kV)

350 340 330 320

Ihpeak

2

Ilpeak

1.5

1

Idc2peak

310 0.5 300

0.005

0.01

Lh, LI (H)

0.015

0.02

0.005

0.01

0.015

Lh, LI (H)

Figure 30.13 MMC DC/DC design as the function of arm inductance. P = 600 MW, V dc1 = 320 kV, V dc2 = 250 kV, 𝜃 L = 60∘ , f = 350 Hz, L2 = 60 mH.

0.02

479

480

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

(3) AC component of upper arm modulation index MHac (magnitude only). (4) AC component of lower arm modulation index MLac (magnitude and angle). The AC power exchange between the two arms can be controlled using three variables: MHac , MLac and 𝜃 L , and many options are possible. In order to minimise AC current magnitude (to reduce loss), the magnitude of AC voltage should be high according to (30.25). Therefore a good suggestion is to select the largest possible MHac and MLac to enable cancellation of real parts of AC voltages according to (30.17). The current magnitude then depends on the imaginary part of V Hac and it can be regulated using the angle between the two AC voltages 𝜃 L . There is a firm constraint on the magnitude of the AC modulation index Mac , considering that Mdc depends on the stepping ratio of the converter as given in (30.24): MHac ≤ min(MHdc , 1 − MHdc ) MLac ≤ min(MHdc , 1 − MLdc )

(30.26)

The MMC DC/DC controller schematic is shown in Figure 30.14. The energy in arms is regulated using the DC modulation index: MLdc for the lower arms and MHdc for the upper arms. The inner current loops are necessary to prevent thermal overload of semiconductors. The controller regulates average energy and current between the three arms, assuming a balanced system. Alternatively the controller can be implemented per phase. 30.4.5

Simulation Responses

A 600 MW, 320 kV/250 kV test system model is assumed and the key parameters are given in Table 30.2. Figure 30.15 illustrates the key variables for the full-power steady-state operation, and the values are in agreement with Figure 30.12. It is interesting to observe that the peak current in the upper valves is only 1.9 kA. This is a similar magnitude to the valve current observed in a 600 MW MMC AC/DC converter connected to the same 320 kV voltage. The current in lower valves is somewhat smaller. The selected cell capacitor size and arm inductance reduce arm voltage ripple to within 5% of 320 kV, while the arm voltage controller maintains average arm voltage at 320 kV. The modulation indices change within the full allowable range between 0 and 1, indicating good utilisation of arm voltage rating. The voltage rating for upper valves can be further optimised. Table 30.2 Parameters for the non-isolated 320 kV/250 kV, 600 MW DC/DC test system. Items

Value

Items

Value

Active power P

600 MW

Fundamental frequency f

350 Hz

DC bus voltage V dc1

+320 kV

DC bus voltage V dc2

+250 kV

Arm resistance RdcH

0.96 Ω

Arm resistance RdcL

0.96 Ω

Cell capacitance CH

1 mF

Cell capacitance CL

6 mF

Arm inductance LH

6 mH

Arm inductance LL

6 mH

Inductance L2

60 mH

V1

×

I1 V2

×

V1

Pdc1 Pdc2

0.8

1 2PN

+

Pdc

DebH

comparator

DebL

fs =350 Hz

V2

PN: rated power

I2

comparator

0.8

φVCO VCO

φVCO Pref

Kp1

+–

++ l

Ki1/S

P

VMLref

3ILdcref

1/3

+–

VMLA VMLB

θL

Kp3

+–

–1

++

Kp2

DebL

3ILdc

Ki3/S I1

++ +

VMLC

+–

++

MLac

min

MLdc

MLq

Low pass filter

++

dq θM to to M Ld abc dq

MLa MLb Nearest

++ level MLc control ++

+– I2

Controller for lower arms

l

+–

min

MHac

3IHdcref

1/3

Kp3

Ki3/S

+–

++

DebH

I1

Kp2

++

MHdc

MHq

θM dq to to MHd abc dq

++

MHa

MHb Nearest NHb ++ level MHc control ++ N

Rotating to static frame

Ki2/S

++ +

VMHC

Figure 30.14 Controller for MMC-based DC/DC converter.

NHa

Hc

Low pass filter +–

NLc

Rotating to static frame

φVCO

VMHA VMHB

NLb

Ki2/S

θH = 0

VMHref

NLa

Controller for upper arms

2

2

IL2

Idc1

1.5 1.5 Current (kA)

1 Current (kA)

3IHdcref

0.5 0 –0.5

Idc1–Idc2

3ILdcref

0.5

IH

–1

1

IL –1.5

0

0.002

0.004

0.006

0.008

0

0.002

VLM

340

Voltage (kV)

0.8

M

0.6 MH 0.4

0.004

0.006

0.008

0.01

0.004 0.006 time (ms)

0.008

0.01

350

ML MLdc

1

0

0.01

MHdc

VHM

330 320 310

0.2 300 0 0

0.002

0.004 0.006 time (ms)

0.008

0.01

290

Figure 30.15 Steady-state variables for non-isolated, MMC-based DC/DC converter.

0

0.002

30.4 Non-isolated MMC-based DC/DC Converter (M2DC)

Figure 30.16 shows the non-isolated MMC DC-DC simulation responses, for the following inputs: • At 0.4 s, full power reversal 600 to −600 MW. The steady-state value for angle between the upper and lower AC voltage is 𝜃 L = 18∘ . This angle will depend on the size of inductors, but the angle should not be too large in order to allow some room for control action. • At 0.7 s, a 0.1 s V dc1 fault. It is seen that the upper arms are blocked but the lower arms operate through the fault. This operating condition requires V H valves of FB type, and rated for at least V dc2 .

1000

350 300

Pref 0

P

Vdc1

250

Voltage (kV)

Power (MW)

500

200 150

Vdc2

100

–500

50 –1000

0.5

2

1.5

0

2

Idc1–Idc2

1

1.5

2

1

1.5

2

1 time (ms)

1.5

2

MLdc

3ILdcref

0.8

0 –1

–3

3IHdcref Idc1 0.5

1

1.5

0

2

0.5

30

380

20

V MHref

V MLref

VLM

320

Theta L (deg)

VHM

340

10

θL 0

–10

300

–20

280 260

MHdc

0.2

400

360

0.6

0.4

–2

Voltage (kV)

0.5

1

M

Current (kA)

1

1

0.5

1 time (ms)

1.5

2

–30

0.5

Figure 30.16 Simulation responses for non-isolated, MMC-based DC/DC converter.

483

484

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

• At 1.1 s, a 0.1 s V dc2 fault. It is seen that the lower arms are blocked but upper arms operate through the fault. • At 1.7 s, a 10% V dc1 voltage drop. The converter responds by reducing the MHdc index and increasing the I dc1 , and the nominal power flow is maintained.

30.5 DC/DC Converters with DC Polarity Reversal In order to integrate thyristor LCC HVDC converters into DC grids with bidirectional power flow as shown in Figure 25.5 a special DC/DC converter is required. Figure 30.17 shows the three-phase thyristor-based DC/DC converter connecting low-voltage DC grid V 1 with high-voltage DC grid V 2 . This converter enables power direction reversal by changing DC current polarity at the HV side while changing DC voltage polarity at the LV side.

30.6 High-stepping-ratio Isolated DC/DC Converter (Dual Active Bridge DC/DC) 30.6.1

Introduction

Figure 30.18 shows the DC/DC converter employing an internal AC transformer and two AC/DC converters connected front-to-front (dual active bridge DC/DC). The AC/DC converters can take single-phase or multiphase topologies. In addition to voltage stepping, the internal AC transformer provides electrical isolation between the low-voltage and high-voltage circuits. This has the advantage that the low-voltage AC/DC converter is stressed for low voltage under all operating conditions. Similarly, the high-voltage side is stressed for low current. Also, different grounding points and arrangements can be selected for each side. The utilisation ratio of both converters will be good; however, both converters cannot simultaneously have an ideal utilisation ratio. As discussed with the fault-tolerant VSC converters in Section 29.9, it is not possible to have zero reactive power on both sides of a reactor (or transformer). An important shortcoming of this topology is the power loss in the magnetic circuit of an internal transformer. The losses are directly proportional to the operating frequency and the practical aspects will limit the frequency to below 500 Hz for multi-MW-size converters. A fault current can always be interrupted by one of the two AC/DC converters that face the fault on its AC side. Such fault protection requires appropriately sized AC inductance and therefore this topology may require an additional inductor beside the internal AC transformer (shown as Ls in Figure 30.18). The transformer saturation under fault conditions may also bring design challenges. The current passing through this DC/DC converter will always run through two AC/DC converters (four switches) and this implies larger conduction loss, compared with direct DC/DC conversion as an example with the topology in Figure 30.9.

Low voltage converter

filter Lf1

L1

T1au/dp

I1s

High voltage converter

T1bu/dp T1cu/dp

T2aup

T2adp

T2bup

T2bdp

T2cup

filter T2cdp

I2s L2

Lf2 I2

Ica

Vcr1

Cr

Icb

Vcb Cr

Cf2 Icc

Vcc

Vcr2

c

Vdc1

Cr

T1au/dn T1bu/dn

T1cu/dn

T2aun T2adn

a b c Y connection

Vdc2

–

–

+

b

Vdc2

Vca

–

a Cf1

+

Vdc1

–

+

+

I1

T2bun T2bdn

T2cun T2cdn

T1cun Thyristor labeling: 1 - converter 1 or 2 c - branch a, b or c u - direction up or down n - polarity positive or negative

N

Figure 30.17 DC/DC converter enabling DC voltage polarity reversal at LV side and current polarity reversal at HV side.

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

MMC2

MMC1

LS1 RS1

Lac Rac

LS2

Tr

Lσ

idc2

Rdc2

– +

idc1

– +

Rdc1

RS2

Vdc1

Vdc2

Fault 1

n:1

Vac

Vac2

– +

iac Vac1

– +

486

Fault 2

(a) circuit diagram LS1/2

RS1/2

Lac

Iac

Rac

Lʹ2

Vac1

Rʹ2

Vʹac2 (b) Equivalent AC circuit

Figure 30.18 Dual active bridge DC/DC converter with internal AC transformer (isolated DC/DC).

30.6.2

Modelling and Control

The phasors of a.c. voltages V ac1 and V ac2 are introduced as: Vac1 = Vacd1 + jVacq1 = Vacm1 Md1 + jVacm1 Mq1

(30.27)

Vac2 = Vacd2 + jVacq2 = Vacm2 Md2 + jVacm2 Mq2

(30.28)

and the magnitude of control indices is defined as √ √ M1 = Md1 + Mq1 , M2 = Md2 + Mq2

(30.29)

where subscripts d and q denote the corresponding phasor components in the rotating DQ frame. The current I ac can be expressed as: Iac =

Vac1 − Vac2 RE + jXE

RE = Rac + RS1 ∕2 + R′2 ,

XE = 2𝜋fLE , LE = Lac + LS1 ∕2 + L′2 (30.30)

Replacing (30.27) and (30.28) in (30.30) the expressions for current DQ components are obtained: ′ ′ ) + XE (Vacq1 − Vacq2 ) RE (Vacd1 − Vacd2 (30.31) Id = 2 RE + XE2

30.6 High-stepping-ratio Isolated DC/DC Converter (Dual Active Bridge DC/DC)

Iq =

′ ′ ) − XE (Vacd1 − Vacd2 ) RE (Vacq1 − Vacq2

RE 2 + XE2

(30.32)

The apparent powers at terminals of bridges are: Sac1 = Vac1 Iac ∗,

Sac2 = Vac2 Iac ∗

(30.33)

Replacing expressions (30.31) and (30.32) in (30.33) enables the calculation of exact reactive power at each bridge: P1 = 3(Vacd1 Id + Vacq1 Iq ); Q1 = 3(Vacq1 Id − Vacd1 Iq )

(30.34)

P2 = 3(Vacd2 Id + Vacq2 Iq ); Q2 = 3(Vacq2 Id − Vacd2 Iq )

(30.35)

Assuming that resistances are neglected (RE = 0), then the current expressions from (30.31) and (30.32) are: Id = Iq =

′ Vacq1 − Vacq2

XE ′ Vacd1 − Vacd2 XE

(30.36) (30.37)

One of the control aims will be to minimise losses, which is achieved by minimising current magnitude. To this end, the following strategy is adopted: (1) Keep I q = 0. This can be achieved if Md1 = Md2 , considering (30.37). Since M is regulated as presented below, it follows that Mq1 = −Mq2 , which is more convenient for control. (2) Minimise I d . Considering (30.34) and (30.35), for a desired power level, this is achieved if Md1 and Md2 are maximised. In order to allow some room for control action, the control goal will be to keep the modulation index magnitude high, namely as M1 = M2 = 0.95. Figure 30.19 shows the controller for isolated DC/DC. Each bridge has two control inputs, Md and Mq and control topologies for two bridges are identical. Each bridge has four control loops: (1) Inner I d control, which keeps converter current within thermal limits. (2) Inner I q control, which keeps converter current within thermal limits, but priority is on Id . (3) Power tracking loop. Average power between two bridges is regulated. Balancing Md1 = Md2 is an add-on control loop. (4) Optimisation of working point to maximise voltage by keeping M1 = M2 = 0.95. 30.6.3

Simulated Responses

Figure 30.20 shows the simulated response for a dual active bridge DC/DC converter with the parameters given in Table 30.3. At 0 and 0.2 s, full power reversal is applied, while 0.2 s-long DC faults are applied at 0.5 and 0.9 s. In brief, the key performance indicators that can be observed from the figure are as follows.

487

488

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

vdc1 idc1

×

vdc2 idc2

×

Iaca1 Iacb1 Iacc1

Pdc1

1 2PN

Pdc2 +

Pdc

abc to dq VCO φ VCO Id Iq Static to rotating frame

fs =350 Hz

PN: rated power

Measured Variables

φVCO Active Power Control Id Control Nua1 1 1.1 Pdcref Mq1 Idref Idref Mfa1 Nla1 Kp2 ++ +– +– +– Kp1 ++ DeB1 Nearest Nub1 Limiting Md control dq M fb1 –1 Ki2/S Pdc Idrefbal 1.1 Ki1/S level Priority on Mq Md1 to Id Nlb1 abc Mfc1 control Nuc1 2 Mq1 Idrefbal 1–Mq1 Min Max ++ Nlc1 Ki4/S Rotating to Mq2 Balancing Mq1 and Mq2 static frame Iq Control Mha1 Mhb1Mhc1 M1 Optimization Iq1ref M1ref = 0.95 Circulating K + +– + –1 Kp3 ++ –1 DeB1 p2 + –1 Min Max Harmonic – Control 2 Ki2/S Ki3/S Iq M1 = M2 + M2 d1 q1 M1 I I I φ diffa1 diffb1 diffc1 VCO Idref 1.1– I2dref –1 Limiting Iq current, priority on Id

Idref

MMC1 Controller

Id Control Kp2

1.1 ++

Idrefbal 1.1

––

DeB2

1 ++

Ki2/S

–1

Nearest Limiting Md control dq Mfb2 level Priority on Mq Md2 to Mfc2 control 2 abc Min Max 1–Mq2

–1

Id M2 Optimization

M2ref = 0.95

Kp3

+–

M2

++

–1

+–

Max

Ki3/S Idref

–1 1.1– I2dref

–1

Limiting Iq current, priority on Id

–1

DeB2

Nua2 Nla2 Nub2 Nlb2 Nuc2 Nlc2

Rotating to static frame

Iq Control

Iq2ref Min

φVCO Δ/Y transformer ++ shift 30° Mq2 Mfa2

Kp2 Ki2/S

++

–1

Mha2 Mhb2Mhc2

M2 = M2 + M2 d2 q2

Iq MMC2 Controller

Circulating Harmonic Control

2

Idiffa2 Idiffb2Idiffc2φVCO

Figure 30.19 Controller for dual active bridge DC/DC converter with internal AC transformer.

(1) For power reversal: (a) power reference tracking is fast; (b) efficiency is maximised since modulation indices are maintained at high values M1 = M2 = 0.95 – this ensures that currents are low; (c) bridge currents track their references in the inner loops. (2) For V dc2 fault: (a) MMC2 is blocked, but MMC1 is not – converter operates through the fault; (b) MMC1 regulates current to rated value; (c) currents are within 2.5 p.u. (3) For Vdc1 fault: (a) MMC1 is blocked, but MMC2 is not – converter operates through the fault; (b) MMC2 regulates current to rated value; (c) currents are within 2.5 p.u.

30.6 High-stepping-ratio Isolated DC/DC Converter (Dual Active Bridge DC/DC)

Power (p.u.)

1 0.5

Pdc Pdcref

0 –0.5 –1 0

0.2

0.4

0.6

0.8

1

1.2

Voltage (p.u.)

1 0.8 0.6

Vdc2

0.4

Vdc1

0.2 0 0

0.2

0.4

0.6

0.8

1

1.2

Current (p.u.)

1.5 1

Iqref

0.5 0 –0.5 –1 –1.5

0

0.2

0.5

Mq1

0

Mq2

M (p.u.)

Iq

Idref Id 0.4

0.6

0.8

1

1.2

0.4

0.6

0.8

1

1.2

0.4

0.6

0.8

1

1.2

–0.5 0

0.2

M (p.u.)

1

Mref M

0.8 0.6 0.4

0

0.2

3

Iarmu2 Iarml2

Current (kA)

2 1 0 –1

Iarmu1 Iarml1

–2 –3

0

0.2

0.4

2

0.6

0.8

1

1.2

0.6

0.8

1

1.2

1

1.2

Vc (kV)

Vc2

1.5

1

0

0.2

0.4

Vc (kV)

2

Vc1

1.5

1

0

0.2

0.4

time (s)

0.6

0.8

Figure 30.20 Dual active bridge DC/DC converter response.

489

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

Table 30.3 Parameters for the isolated ±320 kV/±250 kV, 600 MW, DC/DC test system. Items

Value

Items

Active power P

600 MW

Fundamental frequency f

350 Hz

DC bus voltage V dcs1

±320 kV

DC bus voltage V dcs2

±250 kV

DC resistance Rdc1

0.5 Ω

DC resistance Rdc2

0.5 Ω

DC inductance Ldc1

3 mH

DC inductance Ldc2

3 mH

Transformer turn ratio n

1.28

Transformer leakage inductance Lσ

0.16 mH

Series inductance Lac

50 mH

AC total resistance Rac

0.08 Ω

Items

MMC1 value

MMC2 value

Number of SMs per arm

400

313

SM capacitance C SM

1.25 mF

1.6 mF

Arm inductance Lsi

13.73 mH

8.37 mH

Arm resistance Ri

0.51 Ω

0.25 Ω

SM capacitor voltage V SM

1.6 kV

1.6 kV

IGBT (4.5 kV, 1.3 kA)

5SNA1200G450300

5SNA1200G450300

Value

30.7 High-stepping-ratio LCL DC/DC Converter Figure 30.21 shows a DC/DC converter employing an internal LCL circuit. This DC/DC can also be labelled as a dual active bridge, but uses an LCL circuit instead of a transformer, and it is not isolated. The primary motivation is to eliminate all issues associated with high-power high-frequency transformers. The advantage of using inductors which can assume air-core design is that losses will be moderate even with increased operating frequency. Increased operating frequency implies smaller passive components. The appropriately designed LCL circuit (L1 , C, and L2 ) provides the following functions: • It enables AC voltage and current stepping, similarly to a conventional AC transformer.

Vdc1

S3

I1dc g3

g1

Rdc

g4

I2ac

V1ac L1

C1 C1

I1ac

C

Vc

g5

L2

g7 V2ac

L1 S4

S2

I2dc C2 C2

C g2

Rdc

S7

S5

L2

Rdc

g6

g8 S8

Figure 30.21 Symmetrical monopole, LCL IGBT-based DC/DC converter.

I2 – +

– +

Vdc1

I1

S1

– +

Rdc

– +

490

S6

V2dc

Vdc2

30.7 High-stepping-ratio LCL DC/DC Converter

• It provides inherent fault current regulation. • It facilitates zero reactive power circulation (I ac1 is in phase with V ac1 and I ac2 is in phase with V ac2 ). The basic equations are the same as with an LCL VSC converter (29.6)–(29.8); however, both AC voltages are fully controllable: Vac1dq = Vac1 ∠ff1 = Vac1d + jVac1q

(30.38)

Vac2dq = Vac2 ∠ff2 = Vac2d + jVac2q

(30.39)

The voltage components will be controllable using the converter control signals M1d , M1q and M2d , M2q : 1 1 Vac1d = √ M1d kc V1 , Vac1q = √ M1q kc V1 2 2 1 1 Vac2d = √ M2d kc V2 , Vac2q = √ M2q kc V2 2 2

(30.40) (30.41)

where k c is the gain between AC voltage and DC voltage, which depends on the converter topology and the modulation method (for sinusoidal pulse width modulation with two-level converters k c = 1). The voltage angles are defined with respect to a common coordinate frame which is linked to the central capacitor voltage V c . The phasor domain internal circuit equations are similar to those with LCL VSC in Section 29.9.3: j𝜔L1 Iac1dq = Vac1dq -Vcapdq

(30.42)

j𝜔CVcapdq = Iac1dq + Iac2dq

(30.43)

j𝜔L2 Iac2dq = Vac2dq -Vcapdq

(30.44)

The above equations can be more conveniently written using parameters k 1 –k 3 instead of parameters L1 , C, L2 , and the parameter link is given as: k1 = 1 − 𝜔2 L2 C

(30.45)

k2 = 1 − 𝜔2 L1 C

(30.46)

k3 = L1 + L2 − 𝜔2 L1 L2 C

(30.47)

k1 < 1,

(30.48)

k2 < 1,

k3 < L1 + L2

It can be shown that the zero reactive power condition at AC 1 (V1acd /V1acq = I 1acd /I1acq ) is achieved if: M2d = sk 1

(30.49)

where stepping ratio is defined as s = V 1 /V 2 , while the zero reactive power condition at AC 2 (V 2acd /V 2acq = I 2acd /I 2acq ) is achieved if k2 = k1 s2

(30.50)

491

492

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

If (30.50) is satisfied the converter will be operated with constant angle difference: √ 1 tan(𝛼2 − 𝛼1 ) = −1 (30.51) k12 s2 Therefore this DC/DC converter can operate with zero reactive current on both bridges and at any loading. The parameter k 3 is fully defined by the required power rating, and consequently there is only one free design parameter, k 1 . The design parameter k 1 can be selected in the range − 1/s < k 1 < 1, depending on other requirements like fault current magnitude and the position of natural resonant frequency with respect to the operating frequency 𝜔. Because of internal voltage stepping by the LCL circuit, the voltage stress on switches is low and similar to the converter with internal transformer in Figure 30.18. Both AC/DC converters in the LCL DC/DC converter will operate with close to maximal utilisation ratio. The DC fault response of LCL DC/DC converter is excellent. As demonstrated in Figure 29.19, the LCL circuit will keep the currents at low values for a short circuit at any of the terminals. This implies that VSC converters need not be overrated or tripped for DC faults. There will be no DC fault transfer through the DC/DC converter, and the unfaulted side will only see a load rejection. A permanent fault isolation is possible by blocking IGBTs. On the downside this converter has no electrical isolation. It steps DC voltage symmetrically around the central point and therefore it cannot be used with asymmetric monopole HVDC topologies.

30.8 Building DC Grids with DC/DC Converters A DC/DC converter is very versatile device that can take a range of functions in DC grids. It is very important that the DC/DC converter can prevent DC fault propagation and enable the isolation of DC faults. Because of costs, it cannot be used instead of DC CBs, but it can be strategically located in DC grids to provide protection zone separation. Figure 30.22 shows an established 1.0 GW VSC HVDC (terminals 1 and 2), with two new 0.2 GW terminals (terminals 3 and 4) connected using a DC/DC converter. Connecting the third and fourth terminals without using a DC/DC converter would require both new terminals and DC cables 23 and 24 to be rated for high DC voltage (±320 kV) and additionally some DC CB arrangement would be necessary. The use of DC/DC brings the following benefits: • The DC/DC converter crucially prevents propagation of faults from the small terminals to the main HVDC. A fault on DC cable 23 or VSC3 would not affect the operation of terminals 1 and 2. However terminals 1 and 2, and cable 12 still remain in a single protection zone and any fault in this zone implies that terminals 3 and 4 cannot operate. • Cables 23 and 24 have lower DC voltage, implying cost savings. Also all equipment at VSC3 and VSC4 stations have lower voltage. • DC/DC introduces one additional control channel which enables DC voltage control in cables 23 and 24. It is assumed that VSC3 and VSC4 control local wind farm power.

1.0 GW Idc1

Zac1 AC CB1

1.0 GW 1

2 Idc2

DC/DC 1 0.2 GW 320/50 kV 0.2 GW

±320 kV

DC Cable 24, 0.2 GW

VSC1 1.2 GW

AC CB2 Zac2

DC Cable 12 1.0 GW

0.2 GW DC Cable 23, 0.2 GW

AC1

±320 kV

VSC2 1.0 GW

0.2 GW 3

Idc3

±50 kV

AC CB3 Zac3 AC3

VSC3, 0.2 GW 0.2 GW

4 Idc4

±50 kV

Figure 30.22 A VSC HVDC link with third terminal interfaced using DC/DC converter.

AC CB4 Zac4 AC4

VSC4, 0.2 GW

AC2

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

It is noted that some DC/DC converters enable DC voltage polarity reversal. This implies that the third terminal can have LCC converter technology. Figure 30.23 shows an example of 21-terminal DC grid, connecting nine onshore VSC terminals with 12 offshore wind farms. The grid is built using three star points, three DC/DC converters and 24 DC CBs. Some important properties of the grid are: • Each terminal has the opportunity to trade power with any other terminal. • The grid can have three different DC voltage levels. • DC faults are isolated using simple protection logic as discussed with star DC grids in Section 29.8 (no need for communication between terminals). • Meshed topology (alternative power flow routing) exists only between star points. The main principles for building large DC grids adopting star points and DC/DC converters are: • Each new VSC terminal (either onshore of offshore) connects to the nearest star point, using a DC cable and a DC CB at the star connection point. Protection of the cable is simple since the DC CB trips on high positive signal from the local current sensor. • Any two star points are interconnected using a DC cable with DC/DC at one end and a DC CB at the other end. A fault on the interconnecting cable is cleared by the DC CB and DC/DC. DC/DC prevents fault propagation from one star grid to another. If protection fails on one star grid, the remaining grids will not be affected. Each local

10

Central DC Bus 2

14

Central DC Bus 3

18

13

21

17 9

DC/DC 2–3

8

3

Vdc2

Interconnecting cable 1–2

494

20

Interconnecting cable 2–3 16

3

C

D C/

11 3 1– le ab

gc tin ec n on

1–

Vdc3

19

D

15

erc Int

DC/DC 1–2

Central DC Bus 1

7 6

2 1

12

Vdc1

5 4

Figure 30.23 Twenty-one-terminal DC grid with three star points and three DC/DC converters.

30.9 DC Hubs

star DC grid can have a different DC voltage and different protection arrangements (possibly from a single vendor). • The number of star points is determined considering required reliability, losses, and protection methods. In general, more star points will provide better reliability, but costs and losses will increase because of the larger number of DC/DC converters. Redundancy can be incorporated as well as n − 1 power security criteria. In order to enable full offshore power transfer to the shore, assuming that any single onshore VSC or DC cable is faulted, the onshore VSC and DC cables should be overrated. The rating for each VSC converter and cable should be x/(x − 1) (9/8 for the grid in Figure 30.23) of the nominal power where x is the number of onshore terminals.

30.9 DC Hubs The DC hub is a multiport DC/DC converter which consists of an inner AC circuit and AC/DC converters interfacing each DC line. Figure 30.24 shows an N-port DC hub that uses only passive components in the inner two-phase AC circuit. The inner AC circuit may contain AC transformers and AC CBs for port isolation. The inner circuit will probably be operated at frequencies higher than 50 Hz in order to reduce component size. A multiphase topology will provide higher power ratings and increase reliability and possibly redundancy. The number of phases can be changed ‘on the fly’, which infers that a faulty inner phase can be substituted with a stand-by phase circuit. The DC hub will have complex inner control systems which will manage power flow and stability of the isolated inner AC system. A different DC voltage is allowed on each connecting DC line. The appropriate selection of inductor Li and C i for each port enables zero reactive power at each port under full active power. The hub in Figure 30.24 has excellent DC fault responses. It can operate through DC faults on any port without any control action. Permanent DC faults can be isolated by opening inner AC CB on the affected port.

V1dc

V1dc

Port 1

R1dc

C1d S1_1

R1dc

C1d

S4_1

i1ac v1ac L1 L1

S2_1

S3_1

Port 2 i2ac

CB1

CB2

C1

C2

C1

C2 CB1

CB2

L2 v2ac

R2dc

S4_2

S1_2 C2d

S3_2

S2_2

C2d

L2

R2dc

V2dc

V2dc

...

Bus_A Bus_B VNdc

VNdc

Port N

RNdc

CNd S1_N

RNdc

CNd

S4_N

iNac vNac LN LN

S2_N

S3_N

Port i

CBN

CBi

CN

Ci

CN CBN

Ci CBi

...

Figure 30.24 N-Port, two-phase DC hub.

iiac Li viac Li

Ridc

S4_i

S1_i Cid

S3_i

S2_i

Cid

Ridc

Vidc

Vidc

495

496

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

The DC hub can be viewed as an electronic DC substation in DC grids, which assumes these functions: • • • •

voltage stepping between connecting DC lines/cables; power flow control in each DC cable; DC fault isolation on each cable; connection points for expansion – any number of new ports can be added to hubs. The N-port hub design is summarised in the following steps:

• For each port i, the given data are rated AC RMS voltage V acir and rated power Pir . • Select the value for the capacitor RMS voltage V cr . Capacitor voltage will be 10–50% larger than the largest AC voltage in the inner circuit. Select the operating frequency 𝜔. • Determine inductor Li and capacitor C i for each port i: √ Mir Vacir (Vcr )2 − (Mir )2 (Vacir )2 Li = (30.52) Pi 𝜔 √ Pi (Vc )2 − (Mir )2 (Vacir )2 1 (30.53) Ci = 𝜔(Vcr )2 Mir Vacir • For given operating frequency 𝜔, and selected V cr , determine the value for LCL global resonant frequency 𝜔n using: √ √N [ ]) N ( ∑ 1 ∑ (Vackr )2 𝜔n √ 1 √ ∕ 1− >1 (30.54) = 𝜔 L Lk (Vcr )2 k=1 k k=1 The resonant frequency will always be above the operating frequency, but if it is too close to the operating frequency the capacitor voltage should be adjusted to avoid undamped oscillations.

30.10 Developing DC Grids Using DC Hubs Figure 30.25 shows a 10-terminal DC grid with a central DC hub. A centrally located DC hub enables power exchange between any terminals in the DC grid. Each terminal can have different DC voltage and DC power ratings. Note also that faults on any DC cable can be readily isolated and will not disturb operation of the remaining part of the DC grid. Multiple hubs will be required for large, geographically dispersed grids, but the exact number of hubs will be determined using complex optimisation while considering technical performance, reliability, power security, costs, and losses.

30.11 North Sea DC Grid Topologies Figure 30.26 shows the hypothetical North Sea DC grid, in the proposed topology with four DC hubs. Here, 1 GW is assumed to be a suitable rating for all VSC converters and DC cables. Each country has multiple 1 GW DC links which connect to one of the

30.11 North Sea DC Grid Topologies

1

6

AC1

AC6

Pdc1 Pdc6

VSC1

Vdc1

Vdc6

2

VSC6

7

AC2

AC7 Pdc2 VSC2

Pdc7

Vdc2

Vdc7

3 AC3

8 Pdc3

VSC3

Pdc8

AC8

DC Hub

Vdc3 4

VSC7

Pdc4

AC4

VSC8

Vdc8

Pdc9 9 AC9

VSC4

Vdc4 Pdc5 5

Vdc9

VSC9

Pdc10 10

AC5

AC1 0 VSC5

Vdc5

Vdc10

VSC10

Figure 30.25 DC grid with 10 terminals and one DC hub.

hubs through DC cables. If a new terminal is added, it connects to the nearest DC hub. There is no terminal-to-terminal connection. Note that each DC link can have a different DC voltage with different converter and protection topology. The expansion method is simple, since any number of future DC links can be connected to the hubs. No DC CBs are required. A hub of n ports will consist of n 1 GW VSC converters. A similar DC grid can be developed using four DC busses instead of four DC hubs, by interconnecting regional star DC grids, as shown in Figure 30.27. The cables between two DC busses will have a DC/DC converter and a DC CB at the ends. It is of interest to compare the two topologies in terms of total power electronics rating, which directly relates to the capital costs. Table 30.4 summarises the converter rating for the grid with DC hubs and the DC grid with DC/DC converters, taking the

497

498

30 High Power DC/DC Converters and DC Power Flow Controlling Devices

Firth of Forth DC hub IGW×6

IGW×5 IGW×5

Scotland

IGW×5

IGW×6 IGW×6 Norway

Germany DC hub

IGW×11 Hull

IGW×5

Dogger Bank DC hub

IGW×6

Germany IGW×5 IGW×3

IGW×11

IGW×6 IGW×5

South England

IGW×5

East Anglia DC bus IGW×6

IGW×2 Belgium

Figure 30.26 North Sea DC grid schematic with four DC hubs. Table 30.4 Comparison of North Sea DC grid with hubs and with DC/DC converters. Topology with four DC hubs

Topology with four DC busses

Number of 1 GW (1 p.u.) terminals

37 onshore + 35 offshore = 72 37 onshore + 35 offshore = 72

Number of 1 GW lines between hubs

26

Rating of grid converters (p.u.) 37 + 35 + 26 × 2 = 124

26 26 × 2 = 52

Rating of DC CBs (p.u.)

0

(37 + 35) × (1/3) + 26 × 2 × (1/3) = 41

Total converter rating (p.u.)

222

191

30.11 North Sea DC Grid Topologies

IGW×6 Firth of Forth DC bus

IGW×5

IGW×10

Scotland IGW×6 Norway IGW×6

Hull

Dogger Bank DC bus

IGW×5 IGW×6

Germany DC bus IGW×11

Germany IGW×11 IGW×5

IGW×3

IGW×6

IGW×5

East Anglia DC bus IGW×5 South England

IGW×6

IGW×2 Belgium

Figure 30.27 North Sea DC grid schematic with four DC busses and DC/DC converters on all lines between busses.

basic rating assumptions from Table 24.1. It is seen that the amount of electronics in the inner grid (excluding VSC terminals) is 124 GW for DC hubs while it is 93 GW for DC/DC converters. In terms of total DC grid costs, when VSC terminals and DC cables are included, the topology with DC hubs may require a few percent higher investment. However, the topology with DC hubs can utilise a different DC voltage on each DC line and control/protection is considerably simpler. There are also other advantages with DC hubs like reliability and expansion flexibility.

499

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Part III DC Transmission Grids

Bibliography DC Grids Chaudhuri, N.R., Majumder, R., and Chaudhuri, B. (2013). System frequency support through Multi-Terminal DC (MTDC) grids. IEEE Transactions on Power Systems 28 (1): 347–356. CIGRE joined WG A3 and B4.34 “Technical Requirements and Specifications of State of the art HVDC Switching Equipment”, CIGRE, brochure 683, April 2017. CIGRE WG B4.58 “Control Methodologies for Direct Voltage and Power Flow Control in Meshed HVDC Grid”, CIGRE, technical brochure 699, September 2017. CIGRE Working Group B4.52 "Feasibility of DC Grids", CIGRE, brochure 533, 2013. Jovcic, D., Zhang, L., and Hajian, M. (2013). LCL VSC converter for high power applications. IEEE Transactions on Power Delivery 28 (1): 137–145. Van Hertem, D. and Ghandhari, M. (2010). Multi-terminal VSC HVDC for the european supergrid: obstacles. Renewable and Sustainable Energy Reviews 14 (9): 3156–3163. Veilleux, E. and Ooi, B.T. (2012). Multiterminal HVDC with thyristor power-flow controller. IEEE Transactions on Power Delivery 27 (3): 1205–1212. Vrana, T.K., Yang, Y., Jovcic, D. et al. (2013). The CIGRE B4 DC grid test system. ELECTRA issue 270: 10–19. Yang, J., Fletcher, J.E., and O’Reilly, J. (2010). Multiterminal DC wind farm collection grid internal fault analysis and protection design. IEEE Transactions on Power Delivery 25 (4): 2308–2318. DC Circuit Breakers Bachmann, B. et al. (1985). Development of a 500 kV airblast HVDC circuit breaker. IEEE Transactions on Power Apparatus and Systems PAS-104 (9): 2460–2466. CIGRE joined WG A3 and B4.34 “Technical Requirements and Specifications of State of the art HVDC Switching Equipment”, CIGRE, brochure 683, April 2017. High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

Bibliography

T. Eriksson, M. Backman, S. Halen “A Low Loss Mechanical HVDC Breaker for HVDC Grid Applications”, CIGRE, B4-303, 2014. Hafner, J. and Jacobson, B. Proactive hybrid HVDC breakers – A key innovation for reliable HVDC grids. In: Proceedings of 2011 CIGRE Bologna Conference, 1–8. Lin, W., Jovcic, D., Nguefeu, S., and Saad, H. (2016). Modelling of high power hybrid DC circuit breaker for grid level studies. IET Power Electronics 9 (2): 237–246. P. Skarby and U. Steiger, “An ultra-fast disconnecting switch for a hybrid HVDC breaker – A technical breakthrough”, Proceedings of CIGRÉ Session, Alberta, pp. 1–9, 2013. K. Tahata, S. Oukaili, K. Kamei, et al., “HVDC circuit breakers for HVDC grid applications,” Proceedings of IET ACDC 2015 Conference, Birmingham, pp. 1–9, 2015. Tokuyama, S., Arimatsu, K., Yoshioka, Y. et al. (1985). Development and interrupting tests on 250 kV 8 kA HVDC circuit breaker. IEEE Transactions on Power Apparatus and Systems PAS-104 (9): 2453–2459.

DC Grid Protection De Kerf, K., Srivastava, K., Reza, M. et al. (2011). Wavelet-based protection strategy for DC faults in multi-terminal VSC HVDC systems. IET Generation Transmission and Distribution 5 (4): 496–503. J. Descloux, B. Raison, and J-B Curis, “Protection strategy for undersea MTDC grids,” Proceedings of PowerTech, 2013 IEEE, Grenoble, pp. 1–6, 2013. Jovcic, D., Taherbaneh, M., Taisne, J.P., and Nguefeu, S. (2015). Offshore DC grids as an interconnection of radial systems: Protection and control aspects. IEEE Transactions on Smart Grid 6 (2): 903,910. Jovcic, D., Lin, W., Nguefeu, S., and Saad, H. (2018). Low energy protection system for DC grids based on full bridge MMC converters. IEEE Transactions on Power Delivery 33 (4): 1934–1943. Sneath, J. and Rajapakse, A.D. (2016). Fault detection and interruption in an earthed HVDC grid using ROCOV and hybrid DC breakers. IEEE Transactions on Power Delivery 31 (3): 973–981. D Van Hertem, M Ghandhari, JB Curis, O Despouys, A Marzin “Protection Requirements for a Multiterminal Meshed DC Grid”, CIGRE Symposium, Bologna, September 2011. DC Grid Control Beerten, J. and Belmans, R. (2013). Analysis of power sharing and voltage deviations in droop-controled DC grids. IEEE Transactions on Power Systems 28 (4): 4588–4597. Chaudhuri, N.R. and Chaudhuri, B. (2013). Adaptive droop control for effective power sharing in multi-terminal DC (MTDC) grids. IEEE Transactions on Power Systems 28 (1): 21–22. CIGRE WG B4.58 “Control Methodologies for Direct Voltage and Power Flow in a Meshed HVDC Grid”, CIGRE, technical brochure 699, 2017. De Brabandere, K., Bolsens, B., Van den Keybus, J. et al. (2007). A voltage and frequency droop control method for parallel inverters. IEEE Transactions on Power Electron 22 (4): 1107–1115. Jovcic, D. and Jamshidifar, A. (2015). 3-level cascaded voltage source converters converter controller with dispatcher droop feedback for direct current transmission grids. IET Generation, Transmission & Distribution 9 (6): 571–579.

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Jovcic, D., Lin, W., Nguefeu, S., and Saad, H. (2018). Low energy protection system for DC grids based on full bridge MMC converters. IEEE Transactions on Power Delivery 33 (4): 1934–1943. Prieto-Araujo, E., Bianchi, F.D., Junyent-Ferré, A., and Gomis-Bellmunt, O. (2011). Methodology for droop control dynamic analysis of multiterminal VSC-HVDC grids for offshore wind farms. IEEE Transactions on Power Delivery 26 (4): 2476–2485. Vrana, T.K., Beerten, J., Belmans, R., and Fosso, O.B. (2013). A classification of DC node voltage control methods for HVDC grids. Electric Power Systems Research 103: 137–144. Wang, W. and Barnes, M. (2014). Power flow algorithms for multiterminal VSC-HVDC with droop control. IEEE Transactions on Power Systems 29 (4): 1721–1730.

DC/DC Converters C. D. Barker, C. C. Davidson, D. R. Trainer, and R. S. Whitehouse, Requirements of DC–DC Converters to Facilitate Large DC Grids, Cigre, Paris Session, 2012. Hajian, M., Zhang, L., and Jovcic, D. (2015). DC transmission grid with low speed protection using mechanical DC circuit breakers. IEEE Transactions on Power Delivery TPWRD-00491-2014. Jovcic, D. (2009). Bidirectional high power DC transformer. IEEE Transactions on Power Delivery 24 (4): 2276–2283. Jovcic, D. and Lin, W. (2014). Multiport high power LCL DC hub for use in DC transmission grids. IEEE Transactions on Power Delivery 29 (2): 760–768. Jovcic, D. and Ooi, B.T. (2011). Theoretical aspects of fault isolation on DC lines using resonant DC/DC converters. IET Generation Transmission and Distribution 5 (2): 153–160. Jovcic, D. and Zhang, L. (2013). LCL DC/DC converter for DC grids. IEEE Transactions on Power Delivery 28 (4): 2071–2079. Jovcic, D. and Zhang, H. (2017). Dual channel control with DC fault ride through for MMC-based, isolated DC/DC converter. IEEE Transactions on Power Delivery 32 (3): 1574–1582. D Jovcic, Taherbaneh, Mohsen, Taisne, Jean Pierre ; Nguefeu, Samuel “Developing regional, radial DC grids and their interconnection into large DC grids", IEEE PES General Meeting, Washington, DC, July 2014. Kish, G.J., Ranjram, M., and Lehn, P.W. (2015). A modular multilevel DC/DC converter with fault blocking capability for HVDC interconnects. IEEE Transactions on Power Electronics 30 (1): 148–162. CE Sheridan, MMC Merlin, TC Green, “Assessment of DC/DC converters for use in DC nodes for offshore DC grids” IET AC–DC Power Transmission, Birmingham, 2012, pp 31–37. Yang, H. et al. (2016). Phasor domain steady-state modeling and design of the DC–DC modular multilevel converter. IEEE Transactions on Power Delivery 31 (5): 2054–2063.

503

Appendix A Variable Notations Table A.1 shows the notations for two variables (current and voltage) in all three modeling systems used in this book: • static ABC frame; • rotating DQ frame; and • phasor notation with RMS values.

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

504

Appendix A Variable Notations

Table A.1 Notation systems for two variables. Variable

Current

Voltage

Individual variables in static ABC frame

ia = I cos(𝜔t + 𝜑I ) + I0 ( ) 2 ib = I cos 𝜔t − 𝜋 + 𝜑I + I0 3 ( ) 2 ic = I cos 𝜔t + 𝜋 + 𝜑I + I0 3

Static ABC frame

Vector in static ABC frame iabc

⎡ ia ⎤ ⎢ ⎥ = ⎢ ib ⎥ ⎢ ⎥ ⎢ ⎥ ⎣ ic ⎦

va = V cos(𝜔t + 𝜑V ) + V0 ) ( 2 vb = V cos 𝜔t − 𝜋 + 𝜑V + V0 3 ( ) 2 vc = V cos 𝜔t + 𝜋 + 𝜑V + V0 3 ⎡va ⎤ ⎢ ⎥ vabc = ⎢vb ⎥ ⎢v ⎥ ⎣ c⎦

Rotating DQ frame Orthogonal components in DQ frame

Polar components in DQ frame

Id = I cos(𝜑I ) Iq = I sin(𝜑I ) I0 = I0 √ I = Id2 + Iq2 Iq 𝜑I = arctan Id

Vector in DQ frame Idq

⎡Id ⎤ ⎢ ⎥ = ⎢ Iq ⎥ ⎢ ⎥ ⎢ ⎥ ⎣ I0 ⎦

Vd = V cos(𝜑V ) Vq = V sin(𝜑V ) V0 = V0 √ Vd2 + Vq2 Vq 𝜑V = arctan Vd V =

Vdq

⎡Vd ⎤ ⎢ ⎥ = ⎢Vq ⎥ ⎢V ⎥ ⎣ 0⎦

Phasor notation (employs RMS values) RMS (line-to-neutral) components in DQ frame

I I= √ 2 Id Id = √ 2 Iq Iq = √ 2 I0 = I0

V V= √ 2 Vd Vd = √ 2 Vq Vq = √ 2 V0 = V0 √ √ 3 = 3V = √ V 2

RMS (line-to-line) components in DQ frame

–

V

Phasor vector

Idq = Id + jIq

Vdq = Vd + jVq

ll

505

Appendix B Analytical Background to Rotating DQ Frame B.1 Transforming AC Variables to a DQ Frame The AC system variables will be oscillating at fundamental frequency and any transient changes will be seen as magnitude and phase variations of the oscillating variables. These oscillating variables are difficult for processing in control and filtering circuits and they are commonly transferred to the rotating coordinate frame at the first processing stage in microcontrollers. Also, the AC system is modelled on the rotating coordinate frame in order to connect with DC system variables and to enable model linearisation. It is assumed that the AC system is symmetrical and balanced and therefore any three-phase current vector iabc of magnitude I and phase angle 𝜑I can be represented in the static frame as: I cos(𝜔t + 𝜑I ) + I0 ⎤ ⎡ia ⎤ ⎡ ) ( ⎢ ⎢ ⎥ ⎢I cos 𝜔t − 2 𝜋 + 𝜑 + I ⎥⎥ I 0 iabc = ⎢ib ⎥ = (B.1) 3 ⎥ ) ( ⎢i ⎥ ⎢⎢ ⎣ c ⎦ ⎣I cos 𝜔t + 2 𝜋 + 𝜑I + I0 ⎥⎦ 3 This variable can also be represented using rectangular components (I 0 , I d , and I q ): ia = I0 + I cos(𝜔t + 𝜑I ) ia = I0 + I cos(𝜑I ) cos(𝜔t) − I sin(𝜑I ) sin(𝜔t)

(B.2)

ia = I0 + Id cos(𝜔t) − Iq sin(𝜔t)

(B.3)

where Id = I cos(𝜑I ) Iq = I sin(𝜑I ) I0 = I0

(B.4)

The above transformation to a DQ coordinate frame which is rotating at speed 𝜔 is mathematically represented as: ⎡Id ⎤ ⎡ ia ⎤ ⎢ ⎥ ⎢ ⎥ ⎢Iq ⎥ = P ⎢ib ⎥ , ⎢I ⎥ ⎢i ⎥ ⎣ 0⎦ ⎣ c⎦ High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

(B.5)

506

Appendix B Analytical Background to Rotating DQ Frame

q from rectangular to polar I2 = I2d + I2q

I

Iq

φ1

I φ1 = arc tan q Id

Id

0

from polar to rectangular Id = I cos (φ1) Iq = I sin (φ1)

d

Figure B.1 AC current i in rotating DQ coordinate frame.

where P is the transformation matrix given by ⎡ cos(𝜔t) 2⎢ P = ⎢− sin(𝜔t) 3⎢ ⎣ 1∕2

cos(𝜔t − 2𝜋∕3) − sin(𝜔t − 2𝜋∕3) 1∕2

cos(𝜔t + 2𝜋∕3) ⎤ ⎥ − sin(𝜔t + 2𝜋∕3)⎥ ⎥ 1∕2 ⎦

(B.6)

The DQ coordinate frame orientation is shown in Figure B.1. Therefore using (B.1)–(B.6), the current d and q components are obtained as: I cos(𝜔t + 𝜑I ) + I0 ⎤ ⎡ cos(𝜔t) cos(𝜔t − 2𝜋∕3) cos(𝜔t + 2𝜋∕3) ⎤ ⎡ ⎡Id ⎤ ) ( ⎢ 2 ⎥ ⎢I cos 𝜔t − 𝜋 + 𝜑 + I ⎥⎥ ⎢ ⎥ 2⎢ I 0 I sin(𝜔t) − sin(𝜔t − 2𝜋∕3) − sin(𝜔t + 2𝜋∕3) = − 3 ⎥⎢ ⎢ q⎥ 3 ⎢ ⎥ ) ( ⎢ 1∕2 ⎥ ⎢ ⎥ 1∕2 1∕2 ⎣ ⎦ ⎢⎣I cos 𝜔t + 2 𝜋 + 𝜑I + I0 ⎥⎦ ⎣I0 ⎦ 3

(B.7) Considering

) ( ) ( 2𝜋 2𝜋 + cos k 𝜔t + = 0, k = 1, 2, … cos k(𝜔t) + cos k 𝜔t − 3) ( ( )3 sin k(𝜔t) + sin k 𝜔t − 2𝜋 + sin k 𝜔t + 2𝜋 = 0, k = 1, 2, … 3 3 cos2 x = (1 + cos 2x)∕2,

sin2 x = (1 − cos 2x)∕2,

(B.8)

(B.7) simplifies to:

Idq0

⎡Id ⎤ ⎡I cos(𝜑I )⎤ ⎥ ⎢ ⎥ ⎢ = ⎢Iq ⎥ = ⎢ I sin(𝜑I ) ⎥ ⎥ ⎢I ⎥ ⎢ I ⎦ ⎣ 0⎦ ⎣ 0

(B.9)

The vector components in (B.9) are identical to those in (B.4). The variables in (B.9) are static (not oscillating), which illustrates the advantage of the DQ0 frame. The inverse transformation also exists: ⎡Id ⎤ ⎡ia ⎤ ⎢ ⎥ −1 ⎢ ⎥ ⎢ib ⎥ = P ⎢Iq ⎥ ⎢I ⎥ ⎢i ⎥ ⎣ 0⎦ ⎣ c⎦

(B.10)

B.3 Transforming an AC System Dynamic Equation to a DQ Frame

where P−1

⎡ cos(𝜔t) 3⎢ = ⎢cos(𝜔t − 2𝜋∕3) 2⎢ ⎣cos(𝜔t + 2𝜋∕3)

− sin(𝜔t) − sin(𝜔t − 2𝜋∕3) − sin(𝜔t + 2𝜋∕3)

1⎤ ⎥ 1⎥ 1⎥⎦

(B.11)

B.2 Derivative of an Oscillating Signal in a DQ Frame The derivative of an oscillating signal i is a new oscillating signal which can be labelled as z: d [i] = z dt z = Zo + Zd cos(𝜔t) − Zq sin(𝜔t) (B.12) Taking a derivative of (B.3) the following is obtained: d d [i] = [I0 + Id cos(𝜔t) − Iq sin(𝜔t)] dt dt dIq dI d [i] = −𝜔Id sin(𝜔t) + d cos(𝜔t) − 𝜔Iq cos(𝜔t) − sin(𝜔t) dt dt dt [ ] ] [ dIq dId d [i] = − 𝜔Iq cos(𝜔t) − + 𝜔Id sin(𝜔t) dt dt dt d q

(B.13)

Therefore it is possible to get DQ components for the derivative signal considering (B.12) and (B.13): dI Zd = d − 𝜔Iq dt dIq Zq = + 𝜔Id dt dI Zo = o (B.14) dt If only steady-state values are of interest, by neglecting all derivatives in the above expression in (B.14): Zd = −𝜔Iq Zq = 𝜔Id Zo = 0

(B.15)

B.3 Transforming an AC System Dynamic Equation to a DQ Frame If AC dynamics are modelled in detail, the dynamic equations are expressed first in an ABC frame. Starting with a single first-order differential equation for phase a of a three-phase system in LaPlace domain: sLa ia = −Ra ia + va

(B.16)

507

508

Appendix B Analytical Background to Rotating DQ Frame

where s is the LaPlace operator s = d/dt( ) and where ia and va are phase a oscillating variables. Under the assumption that the system is symmetrical and balanced the following is valid: Ra = Rb = Rc = R,

(B.17)

La = L b = L c = L

The three-phase system dynamic equation can now be represented as: ⎡L 0 0⎤ sLiabc = −Riabc + vabc L = ⎢0 L 0⎥ , ⎢ ⎥ ⎣0 0 L⎦

⎡R 0 0 ⎤ R = ⎢0 R 0⎥ ⎢ ⎥ ⎣ 0 0 R⎦

(B.18)

The above model has all states as oscillating variables (50 Hz sine signals). It is necessary to transfer the model into a rotating DQ frame using Park’s transformation (B.6). Replacing all ABC variable with DQ variables in the model in (B.18): sLP−1 Idq0 = −RP−1 Idq0 + P−1 Vdq0

(B.19)

Multiplying (B.19) by P: PsLP−1 Idq0 = −PRP −1 Idq0 + PP −1 Vdq0

(B.20)

Using the following properties of Parks matrix PRP −1 = R ⎡ 1 0 0⎤ PP −1 = I = ⎢0 1 0⎥ ⎢ ⎥ ⎣ 0 0 1⎦

(B.21)

and expanding the dynamic term, (B.20) is rearranged: PsLP−1 Idq0 + LPLP−1 sI dq0 = −RIdq0 + BVdq0

(B.22)

It can be shown that for Park’s matrix the following holds: ⎡0 −1 0⎤ PsP−1 = 𝜔 ⎢1 0 0⎥ = 𝜔W0 , ⎢ ⎥ ⎣0 0 0⎦

⎡0 −1 0⎤ W0 = ⎢1 0 0⎥ ⎢ ⎥ ⎣0 0 0⎦

(B.23)

Therefore using (B.23), (B.22) is written as: sI dq0 = −[RL−1 + 𝜔W 0 ]Idq0 + L−1 Vdq0

(B.24)

The above equation is a DQ frame model for an AC system with a single dynamic equation (one dynamic element).

B.4 Transforming an n-Order State Space AC System Model to a DQ Frame

B.4 Transforming an n-Order State Space AC System Model to a DQ Frame In the case of a complex AC system, the dynamics are represented as an nth order state space model. A phase a model for the system with n states, m inputs and p outputs is represented as: sxa = Aa xa + Ba ua ya = C a xa + Da ua Aa ∈ ℜn×n , Ba ∈ ℜn×m , C a ∈ ℜp×n , Da ∈ ℜp×m

(B.25)

⎡ x1 ⎤ ⎡ y1 ⎤ [ ] xa = ⎢ . ⎥ , ua = u1 . um a , ya = ⎢ . ⎥ ⎢ ⎥ ⎢ ⎥ ⎣xn ⎦a ⎣yp ⎦a Then, the three-phase state-space system model in ABC frame is: sxabc = Aabc xabc + Babc uabc (B.26)

yabc = C abc xabc + Dabc uabc

xabc

⎡ ⎡ x1 ⎤ ⎤ ⎡ ⎡ y1 ⎤ ⎤ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢ ⎢x ⎥ ⎥ ⎢⎢y ⎥ ⎥ ⎢⎣ n ⎦a ⎥ ⎢⎣ p ⎦a ⎥ ] [ ⎢⎡x ⎤ ⎥ ⎢⎡y ⎤ ⎥ ⎡ u1 . u m a ⎤ ⎢⎢ 1 ⎥ ⎥ ⎢⎢ 1 ⎥ ⎥ [ ] ⎥ ⎢ = ⎢⎢ . ⎥ ⎥ , uabc = ⎢ u1 . um b ⎥ , yabc = ⎢⎢ . ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ]⎥ ⎢[ ⎢⎣xn ⎦ ⎥ ⎢⎣yp ⎦ ⎥ u . u ⎦ ⎣ 1 m c b b ⎢ ⎢ ⎥ ⎥ ⎢ ⎡ x1 ⎤ ⎥ ⎢ ⎡ y1 ⎤ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎣⎣xn ⎦c ⎦ ⎣⎣yp ⎦c ⎦ 0n×n

Aabc

⎡ Aa ⎢ = ⎢0n×n ⎢0 ⎣ n×n ⎡ Ca ⎢ = ⎢ 0pxn ⎢0 ⎣ p×n

0p×n

C abc

Ab 0n×n

Cb 0p×n

0n×n ⎤ ⎥ 0n×n ⎥ , Ac ⎥⎦ 0p×n ⎤ ⎥ 0p×n ⎥ , C c ⎥⎦

Babc

Dabc

⎡ Ba ⎢ = ⎢0n×m ⎢0 ⎣ n×m

0n×m

⎡ Da ⎢ = ⎢0p×m ⎢0 ⎣ p×m

0p×m

Bb 0n×m

Db 0p×m

0n×m ⎤ ⎥ 0n×m ⎥ , Bc ⎥⎦ 0p×m ⎤ ⎥ 0p×m ⎥ Dc ⎥⎦

509

510

Appendix B Analytical Background to Rotating DQ Frame

Using the above approach and assuming the system is symmetrical and balanced, the state-space model (B.26) is converted into rotating frame as: sX dqo = Adqo Xdqo + Bdqo Udqo Ydqo = C dqo Xdqo + Ddqo Udqo

Xdqo

⎡⎡x1 ⎤ ⎤ ⎡⎡y1 ⎤ ⎤ ⎢⎢ ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢x ⎥ ⎥ ⎢⎢y ⎥ ⎥ ⎢⎣ n ⎦d ⎥ ⎢⎣ p ⎦d ⎥ ] [ ⎢⎡ x ⎤ ⎥ ⎢⎡ y ⎤ ⎥ . u u ⎡ 1 m d⎤ ⎢⎢ 1 ⎥ ⎥ ⎢⎢ 1 ⎥ ⎥ [ ] ⎥ ⎢ ⎥ ⎢ = ⎢ . ⎥ , Udqo = ⎢ u1 . um q ⎥ , Ydqo = ⎢⎢ . ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ] ⎥ ⎢[ ⎢⎣xn ⎦q ⎥ ⎢⎣yp ⎦q ⎥ ⎣ u1 . um o ⎦ ⎥ ⎥ ⎢ ⎢ ⎢ ⎡ x1 ⎤ ⎥ ⎢ ⎡ y1 ⎤ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ . ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎢⎢ ⎥ ⎥ ⎣⎣xn ⎦o ⎦ ⎣⎣yp ⎦o ⎦

Adqo

⎡ Aa 𝜔I n×n 0n×n ⎤ ⎥ ⎢ = ⎢−𝜔I n×n Aa 0n×n ⎥ , ⎥ ⎢ 0 ⎣ n×n 0n×n Aa ⎦

Bdqo

C dqo

⎡ C a 0p×n 0p×n ⎤ ⎥ ⎢ = ⎢0p×n C a 0p×n ⎥ , ⎥ ⎢0 ⎣ p×n 0p×n C a ⎦

⎡ Da 0p×m 0p×m ⎤ ⎥ ⎢ = ⎢0p×m Da 0p×m ⎥ ⎥ ⎢0 ⎣ p×m 0p×m Da ⎦

Ddqo

(B.27)

⎡ Ba 0n×m 0n×m ⎤ ⎥ ⎢ = ⎢0n×m Ba 0n×m ⎥ ⎥ ⎢0 ⎣ n×m 0n×m Ba ⎦

Note that for a balanced and symmetrical systems the set of zero sequence variables can be removed from the model. It is seen in (B.27) that the system matrix has 𝜔 as multiplier with off-diagonal terms. This implies that a frequency in the DQ frame is increased by f relative to the ABC frame. In general, a frequency component f abc in the ABC frame is transferred to the DQO frame as f dqo where: fdqo = fabc ± f

(B.28)

Once the A, B, C and D matrices are known in (B.27), then the time domain solution can be determined as with any state space system model. Alternatively, it is possible to converter model (B.27) into a transfer function representation: Ydqo = W dqo (s)Udqo W dqo (s) = C dqo [sI-Adqo ]−1 Bdqo + Ddqo

(B.29)

B.5 Static (Steady-state) Modeling in a Rotating DQ Coordinate Frame The above DQ model represents all system dynamics and enables accurate transient responses and dynamic studies. If only the steady-state solution is of interest, the above

B.6 Representing the Product of Oscillating Signals in a DQ Frame

model can be simplified by neglecting all dynamic terms, i.e. s = 0: 0 = Adqo Xdqo + Bdqo Udqo Ydqo = C dqo Xdqo + Ddqo Udqo

(B.30)

Therefore the static model (B.30) becomes: Xdqo = −A−1 dqo Bdqo Udqo Ydqo = C dqo Xdqo + Ddqo Udqo

(B.31)

The above model can be solved using standard matrix methods.

B.6 Representing the Product of Oscillating Signals in a DQ Frame Assume that two single-phase AC signals x and y are given as: x = X0 + Xm cos(𝜔t + 𝜑x ) + Xm2 cos(2𝜔t + 𝜑x ) = X0 + Xd cos 𝜔t − Xq sin 𝜔t + Xd2 cos 2𝜔t − Xq2 sin 2𝜔t y = Y0 + Ym cos(𝜔t + 𝜑y ) = Y0 + Yd cos 𝜔t − Yq sin 𝜔t

(B.32)

where signal x includes also the second harmonic for completeness. It is of interest to determine the DQ components of the product signal z: z = xy

(B.33)

z = Z0 + Zd cos(𝜔t) − Zq sin(𝜔t) + Zd2 cos(2𝜔t) − Zq2 sin(2𝜔t) + Zd3 cos(3𝜔t) − Zq3 sin(3𝜔t)

(B.34)

Replacing (B.32) in (B.33), and using the following trigonometric identities: cos(𝛼 − 𝛽) − cos(𝛼 + 𝛽) cos(𝛼 − 𝛽) + cos(𝛼 + 𝛽) , sin 𝛼 sin 𝛽 = 2 2 sin(𝛼 + 𝛽) + sin(𝛼 − 𝛽) sin(𝛼 + 𝛽) − sin(𝛼 − 𝛽) sin 𝛼 cos 𝛽 = , cos 𝛼 sin 𝛽 = , 2 2 (B.35) cos 𝛼 cos 𝛽 =

(B.33) becomes ( ) ) ( Xq Yq X Y 1 1 + Xd Y0 + X0 Yd + Xd2 Yd + Xq2 Yq cos(𝜔t) z = X0 Y0 + d d + 2 2 2 2 d 0 ) ( 1 1 − Xq Yo + Xo Yq − Xd2 Yq + Xq2 Yd sin(𝜔t) 2 2 q ( ( ) ) Y Xq Yd Xd Yq X Xd Yd q q + cos(2𝜔t) − sin(2𝜔t) − + Xd2 Yo + + Xq2 Y0 2 2 2 2 d2 d2 ) ) ( ( 1 1 1 1 + cos(3𝜔t) − sin(3𝜔t) (B.36) X Y − X Y X Y + X Y 2 d2 d 2 q2 q d3 2 d2 q 2 q2 d q3

511

512

Appendix B Analytical Background to Rotating DQ Frame

Therefore equating (B.34) with (B.36) the components of the product z signal are: Xd Yd Xq Yq + 2 2 1 1 1 1 Zd = Xd Yo + Xo Yd + Xd2 Yd + Xq2 Yq , Zq = Xq Yo + Xo Yq − Xd2 Yq + Xq2 Yo , 2 2 2 2 Xq Yd Xd Yq Xd Yd Xq Yq Zd2 = − + Xd2 Yo , Zq2 = + + Xq2 Yo , 2 2 2 2 1 1 1 1 Zd3 = Xd2 Yd − Xq2 Yq , Zq3 = Xd2 Yq + Xq2 Yd , (B.37) 2 2 2 2 If X d2 = X q2 = 0, as this is a common case in power engineering for symmetrical systems: Xq Yq X Y Zo = Xo Yo + d d + 2 2 Zd = Xd Yo + Xo Yd , Zq = Xq Yo + Xo Yq , Xq Yd Xd Yq Xq Yq X Y Zd2 = d d − , Zq2 = + , (B.38) 2 2 2 2 Zo = Xo Yo +

B.7 Representing Power in DQ Frame Assuming that the instantaneous voltage v and current i are given as: i = Io + I cos(𝜔t + 𝜑i ) = Io + Id cos(𝜔t) − Iq sin(𝜔t)

(B.39)

v = Vo + V cos(𝜔t + 𝜑v ) = Vo + Vd cos(𝜔t) − Vq sin(𝜔t)

(B.40)

The instantaneous electrical power per phase S1p is defined as the product of instantaneous voltage and current: S1p = vi = Vo Io + VI o cos(𝜔t + 𝜑v ) + Vo I cos(𝜔t + 𝜑i ) + VI cos(𝜔t + 𝜑v ) cos(𝜔t + 𝜑i ) (B.41) Therefore when expanded: VI (cos(𝜑v − 𝜑i ) + cos(2𝜔t + 𝜑v + 𝜑i )) + Vo Io + VI o cos(𝜔t + 𝜑v ) 2 + Vo I cos(𝜔t + 𝜑i ) VI = (cos(𝜑v − 𝜑i ) + cos(2𝜔t + 2𝜑v + 𝜑i − 𝜑v )) + Vo Io + VI o cos(𝜔t + 𝜑v ) 2 + Vo I cos(𝜔t + 𝜑i ) VI VI = cos(𝜑i − 𝜑v ) + cos(𝜑i − 𝜑v ) cos(2𝜔t + 2𝜑v ) 2 2 VI − sin(𝜑i − 𝜑v ) sin(2𝜔t + 2𝜑v ) + Vo Io + VI o cos(𝜔t + 𝜑v ) + Vo I cos(𝜔t + 𝜑i ) 2 VI VI = cos(𝜑i − 𝜑v )[1 + cos(2𝜔t + 2𝜑v )] − sin(𝜑i − 𝜑v ) sin(2𝜔t + 2𝜑v ) 2 2 (B.42) + Vo Io + VI o cos(𝜔t + 𝜑v ) + Vo I cos(𝜔t + 𝜑i )

S1p =

S1p

S1p

S1p

B.7 Representing Power in DQ Frame

Note that with three-phase systems the cos term of the second harmonic and also all first harmonics will cancel. By definition, active power is the average of the product of voltage and current in (B.42): VI (B.43) cos(𝜑i − 𝜑v ) 2 while the reactive power is the magnitude of the sine term of second harmonic, P1p = Io Vo +

VI (B.44) sin(𝜑i − 𝜑v ) 2 Replacing now (B.39) and (B.40) in (B.43) the active power is obtained in terms of DQ components: Q1p = −

Vd Id Vq Iq + 2 2 Replacing (B.39) and (B.40) in(B.44):

(B.45)

P1p = Vo Io +

Vq Id

Q1p =

2

−

Vd Iq

(B.46)

2

If the components are given as RMS values, I d =

√ 2I d then (B.45) and (B.46) become:

P1p = Vo Io + Vd Id + Vq Iq

(B.47)

Q1p = Vq Id − Vd Iq

(B.48)

Therefore for a balanced and symmetrical system the 3-phase power is: P = 3(Vo Io + Vd Id + Vq Iq )

(B.49)

Q = 3(Vq Id − Vd Iq )

(B.50)

Example B.1

A simple three-phase system is shown in Figure B.2.

(1) Develop dynamic model in ABC frame. (2) Develop dynamic system model in rotating DQ frame. (3) Develop static model in DQ frame and calculate DQ components of current I g and voltage V g . Ac, 3Φ 50 Hz

Vs

R1

L1

R1

L1

R1

L1

Ig Vs = 200 kV, R1 = 1.2 Ω, R2 = 200 Ω,

Vg

C2

R2

C2

R2

Figure B.2 Sample AC system for DQ frame analysis.

C2

R2

L1 = 0.03 H, C2 = 0.15 μF, ω = 314.15 rad s–1

513

514

Appendix B Analytical Background to Rotating DQ Frame

Solution (1) The single phase state-space model in fixed ABC frame is: [ ] [ ] [1] ⎡ −R1 −1 ⎤ i ig g L1 L1 ⎢ ⎥ s = 1 −1 + L1 vs ⎢ ⎥ vg vg 0 ⎣ C2 C2 R2 ⎦ [ ] [ ][ ] [ ] ig ig 1 0 0 vs = + vg 0 1 vg 0

(B.51)

(2) The DQ frame dynamic model is: −R

−1 1 ⎡ Igd ⎤ ⎡ L1 L1 𝜔 ⎢ ⎥ ⎢⎢ 1 −1 0 ⎢Vgd ⎥ C C R s ⎢ ⎥ = ⎢ 2 2 2 −R 1 ⎢ Igq ⎥ ⎢⎢−𝜔 0 L1 ⎢V ⎥ ⎢ ⎣ gq ⎦ ⎣ 0 −𝜔 1 C2

⎡ Igd ⎤ ⎡1 ⎢ ⎥ ⎢ ⎢Vgd ⎥ ⎢0 ⎢ ⎥=⎢ ⎢ Igq ⎥ ⎢0 ⎢V ⎥ ⎣0 ⎣ gq ⎦

0 ⎤⎡ ⎤ ⎡ 1 0⎤ ⎥ ⎢ Igd ⎥ ⎢ L1 ⎥ [ ] 𝜔 ⎥ ⎢Vgd ⎥ ⎢ 0 0 ⎥ V sd ⎥ ⎥+⎢ 1 ⎥ −1 ⎥ ⎢ V I 0 gq ⎥ ⎢ L1 ⎥ sq L1 ⎥ ⎢ ⎥ ⎢ ⎥ ⎢ −1 ⎥ ⎣Vgq ⎦ ⎣0 0⎦ ⎦

C2 R2

0 0 0⎤ ⎡ Igd ⎤ ⎡0 ⎢ ⎥ 1 0 0⎥ ⎢Vgd ⎥ ⎢0 ⎥⎢ ⎥ + ⎢ 0 1 0⎥ ⎢ Igq ⎥ ⎢0 ⎢ ⎥ 0 0 1⎦ ⎢⎣Vgq ⎥⎦ ⎣0

0⎤ [ ] 0⎥ Vsd ⎥ 0⎥ Vsq ⎥ 0⎦

(B.52)

(3) The static model is: −R

−1 𝜔 ⎡ L1 L ⎡ Igd ⎤ 1 1 ⎢ ⎢ ⎥ ⎢ 1 −1 0 ⎢Vgd ⎥ C2 C2 R2 ⎢ ⎥ = −⎢⎢ −R −𝜔 0 L 1 ⎢ Igq ⎥ ⎢ 1 ⎢V ⎥ ⎢ 0 −𝜔 1 ⎣ gq ⎦ ⎣ C2

−1

0 ⎤ ⎡ 1 0⎤ ⎥ ⎢ L1 ⎥ [ ] 𝜔 ⎥ ⎢0 0⎥ V sd ⎥ ⎢ 1 ⎥ −1 ⎥ ⎢ 0 L1 ⎥ Vsq L1 ⎥ ⎢ ⎥ −1 ⎥ ⎣0 0⎦ C2 R2 ⎦ √ Considering that V sd = 220e3/ 3, and V sq = 0, the currents are obtained: ⎡ Igd ⎤ ⎡ 630.47 A ⎤ ⎢ ⎥ ⎢ ⎢Vgd ⎥ ⎢126.04 kV⎥⎥ ⎢ ⎥=⎢ ⎢ Igq ⎥ ⎢ −23.63 A ⎥⎥ ⎢V ⎥ ⎣ −5.9 kV ⎦ ⎣ gq ⎦

(B.53)

(B.54)

The powers are calculated as: P = 3(Vgd Igd + Vgq Igq ) = 238.8 MW

(B.55)

Q = 3(Vgq Igd − Vgd Igq ) = −2.25 MVAr

(B.56)

515

Appendix C System Modeling Using Complex Numbers and Phasors The phasor modelling of AC variables is adopted under the following assumptions: • The AC system is three-phase, symmetrical and balanced. There are no zero sequence components. • All variables are represented as RMS values assuming constant frequency 𝜔. • All components with energy storage (reactors and capacitors) are represented using reactances at fundamental frequency. Using phasor notation the voltage and current are represented as: Ig = Igd +jIgq

(C.1)

Vg = Vgd +jVgq

(C.2)

The system variables are solved using Kirchhoff’s circuit rules with all of the elements represented using impedance values at fundamental frequency. The basic impedances are as shown in Figure C.1. Under the above assumptions the complex power per phase is the product of voltage and current conjugate complex: ( )∗ S = 3Vg Ig (C.3) Where the ( )* notation stands for conjugate complex. ( )( ) S = 3 Vgd + jVgq Igd − jIgq ( ( )) S = 3 Vgd Igd + Vgq Igq + j Vgq Igd − Vgd Igq The active power is the real part while the reactive power is the reactive part: ( ) P = 3 Vgd Igd + Vgq Igq ( ) Q = 3 Vgq Igd − Vgd Igq

(C.4)

(C.5)

Note that the above method with complex numbers cannot be used for systems with a zero sequence component. Also the method is not valid for general multiplication of two signals.

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

516

Appendix C System Modeling Using Complex Numbers and Phasors

time domain

impedance R

RiR = VR

L C

phasor domain VR = zR IR

zR = R

L

diL = vL dt

VL = z L I L

zL = jωL

C

dVc = ic dt

Vc = z c I c

zc = –j 1 ωC

Figure C.1 Impedances in time domain and in phasor domain.

Example C.1 Consider the same system as in Example B.1. Determine system current I g , voltage V g , and power at V g using phasor methods. Solution z1 = R1 + j𝜔L1 = 1.2 + j9.425 Ω z2 =

R2 j𝜔C2

R2 +

1 j𝜔C2

=

R2 = 199.98 − j1.885 Ω R2 j𝜔C2 + 1

(C.6)

Vs = 630.5 − j23.63 A z1 + z2 = 630.5 A

Ig = Igd

Igq = −23.63 A

(C.7)

Vg = Ig z2 = 126.03 − j5.913 kV Vgd = 126.03 kV Vgq = −5.913 kV

(C.8)

The powers are calculated as: )( ) ( S = 3 Vgd + jV gq Igd − jI gq = Pg + jQg

(C.9)

) ( P = 3 Vgd Iacd + Vgq Iacq = 238.8 MW

(C.10)

) ( Q = 3 Vgq Igd − Vgd Igq = −2.25 MVAr

(C.11)

The above results are consistent with those in Example B.1.

517

Appendix D Simulink Examples D.1 Chapter 3 Examples Example D.1 in Figure D.1

Consider a rectifier connecting an AC source and a DC source as shown

• Determine (by calculation or by simulation) the value of firing angle in order to keep the DC current at 1000 A. • Determine the maximum possible AC voltage drop that can be compensated for by firing angle variation, assuming that the DC current is kept at 1000 A. • Determine the AC voltage that will reduce the DC current to zero. • Determine the maximum possible DC overvoltage that can be compensated for by firing angle variation, assuming that the DC current is kept at 1000 A. Solution A SIMULINK model is developed and the AC source magnitude is progressively reduced as shown in Figure D.2. • The firing angle is around 16 ∘ . • The AC voltage is around 390 kV or 4.8% drop. • The AC voltage is 368 kV or 20% drop. • The DC overvoltage is the same as the AC voltage drop above (4.8%).

D.2 Chapter 5 Examples Example D.2 Study the inverter connecting an AC and a DC source as shown in Figure D.3. Assume that this converter is operated in closed loop DC current control, maintaining I dc = 1000 A. • Determine (by simulation or otherwise) the minimum symmetrical AC voltage drop that causes commutation failure. • Determine the minimum DC current step increase that causes commutation failure. • Explain the impact of commutation failure on the AC system.

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

Appendix D Simulink Examples

Figure D.1 Rectifier in Example D.1.

1000 A 1 H 410 kV 50 Hz 0.01 Ω 0.1 H

2Ω + –

500 kV

5

Vac (kV)

x 10 4 3.8 3.6 0.1

0.15

0.2

0.25

0.3 time (s)

0.35

0.4

0.45

0.5

0.15

0.2

0.25

0.3 time (s)

0.35

0.4

0.45

0.5

0.15

0.2

0.25

0.3 time (s)

0.35

0.4

0.45

0.5

Alpha (deg)

20 10 0 0.1 1000 Idc (A)

500 0 0.1

Figure D.2 Rectifier responses in Example D.1. Idc = 1000 A 425 kV, 50 Hz

T1 0.2 H

T3

1H

2Ω

Vdc

480 kV

T5

Ia Ib Ic T4

T6

–

518

+

T2

Figure D.3 Converter in Example D.2.

Solution By studying the reponses for reduced source voltage magnitude it can be determined that any voltage drop over 4% will cause commutation failure. A DC current step to 1400 A causes commutation failure. Figure D.4 shows responses for a commutation failure caused by a DC current step to 1400 A. It can be seen that the AC voltage is not affected by commutation failure, as seen

D.3 Chapter 6 Examples

5 Va,Vb,Vc

× 105

0

–5 0.04 2000 Ia,Ib,Ic

0.06

0.07

0.08

0.09

0.1

0.05

0.06

0.07

0.08

0.09

0.1

0.05

0.06

0.07

0.08

0.09

0.1

0.09

0.1

0

–2000 0.04 × 105 0 Vdc –2 –4 0.04 Idc

0.05

3000 2000 1000 0.04

Idc

Idcref 0.05

0.06

0.07 Time (s)

0.08

Figure D.4 Converter responses in Example D.2.

by the zero DC voltage. The AC current is also not affected even though the DC current rises to very high values. The problems may arise in practical systems during subsequent recovery from commutation failures because of large reactive power demand.

D.3 Chapter 6 Examples Example D.3 Consider the same test system as in Figure 6.6; however, a 1000 km long DC cable is considered. Use the DC cable ‘T’ model as in the CIGRE HVDC benchmark, where the total cable capacitance is 240 μF, the rectifier/inverter side DC resistance is 13.5 Ω and the rectifier/inverter side inductance is 0.75 H (which includes DC smoothing reactors). (1) Tune the controller gains and make other adjustments to ensure system stability assuming that the inverter is in DC voltage control mode. Ensure that the rectifier firing angle is at least 20∘ at full power. (2) Tune the controller gains to ensure that the system is dynamically stable in constant extinction angle mode. To operate in constant extinction angle mode, reduce the inverter AC voltage. Solution (1) If the same settings as in the short-cable test system are used, the rectifier firing angle will be reduced to around 15∘ in order to compensate for the large DC voltage drop along the DC cable. It is necessary to reduce the DC voltage reference to around 480 kV. Alternatively, the rectifier transformer ratio can be adjusted to increase the converter-side voltage. The reponses are shown in Figure D.5 for a current order step at 1.6 s. The transient response is slow because of the large DC cable impedance.

519

520

Appendix D Simulink Examples 1200 1100 1000 Idcr (A) 900 800 700

DC current ref step 800 A-> 1000 A

1.4 5 5.5 × 10

Vdcr (V)

Idcr_ref

Idcr

1.5

1.6

1.7

1.8

1.9

2

1.5

1.6

1.7

1.8

1.9

2

1.7

1.8

1.9

2

1.7

1.8

1.9

2

1.8

1.9

2

1.9

2

5 4.5 4

1.4

150 αr (deg) 100 CC mode

50 0 Pr (W), Qr (VAr)

6 5 4 3 2

1.4 × 108

1.5

1.6

1.4

1.5

1.6

Time (s)

(a) Rectifier Variables 1200 1100 Idci (A) 1000 900 800 700 1.4 × 105 5.5 Vdci (V)

Idci Idci_ref

1.5

1.6

1.7

Vdci_ref

5

Vdci

4.5 4

1.4

1.5

1.6

1.7

1.8

180 αi (deg)

160

gamma min mode

140

Vdc control mode

120 Pi (W), Qi (VAr)

4 2 0 –2 –4 –6

1.4 8 × 10

1.5

1.6

1.5

1.6

1.7

1.8

1.9

2

1.7

1.8

1.9

2

Qi Pi

1.4

(b) Inverter Variables

Time (s)

Figure D.5 System responses in Example D.3a.

(2) The inverter AC voltage can be reduced to 200 kV to test inverter operation in constant extinction angle mode (simulates remote AC voltage fault or line tripping). The system is unstable. It is necessary to reduce the rectifier and inverter DC current controller gains to 20% of the original values to ensure stability. The reponses are shown in Figure D.6 for a current order step at 1.6 s. It can be seen that the inverter DC voltage is below the reference value since gamma minimum control is used. Also, comparing with the V dc control mode in part (1), the damping of oscillatory mode is reduced.

D.4 Chapter 8 Examples 1200 1100 1000 Idcr (A) 900 800 700 1.4 5 5.5 × 10 Vdcr (V)

Idcr_ref

DC current ref step 800 A->1000 A

Idcr

1.5

1.6

1.7

1.8

1.9

2

1.5

1.6

1.7

1.8

1.9

2

1.5

1.6

1.7

1.8

1.9

2

1.5

1.6

1.7

1.8

1.9

2

1.7

1.8

1.9

2

1.7

1.8

1.9

2

5 4.5 4 1.4 150

αr (deg) 100 50

Pr (W), Qr (VAr)

CC mode

0 1.4 × 108 6 5 Pr 4 Qr 3 2 1.4

(a) Rectifier Variables 1200 1100 1000 Idci (A) 900 800 700 1.4 × 105 5.5 Vdci (V)

Idci Idci_ref

1.5

1.6 Vdci_ref

5 4.5 4 1.4 180

αi (deg)

Time (s)

1.5

1.6

160

gamma min mode

140

120 1.4 8 × 10 4 2 Pi (W), 0 Qi (VAr) –2 –4 –6 1.4

1.5

1.6

1.7

1.8

1.9

2

1.7

1.8

1.9

2

Pi 1.5

1.6

(b) Inverter Variables

Time (s)

Figure D.6 System responses in Example D.3b.

D.4 Chapter 8 Examples Example D.4 Study an 80% AC voltage drop on the rectifier AC system at 0.45 s for 100 ms for the same test system in Figure 6.6. Assume normal HVDC controls and that no VDCOL is used. Explain what mode transitions are occurring at the rectifier and inverter. Discuss the impact on AC systems. Solution Figure D.7 shows the response to an 80% rectifier AC voltage drop.

521

522

Appendix D Simulink Examples

3000 Idcr (A) 2000 1000

×

0 0.4 6 4 2 0 0.4

105

Vdcr (A)

Idcr

Idcr_ref 0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

100

αr (deg)

CC mode Alphamin mode 0 0.4 0.45 0.5 0.55 2 Vacr fault 0

× 105 Vacr (V)

–2 0.4

0.45

× 10 5 Pr (W), 0 Qr (VAr) –5

0.55

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.6

0.65

0.7

0.75

0.8

Pr

8

Qr

0.4

0.5

CC mode

0.45

(a) Rectifier Variables

0.6

0.65

0.7

0.75

0.8

Time (s)

2000 Idci_ref

Idci (A) 1000

× 105 Vdci (V)

0 0.4 6 4 2 0 0.4

αi (deg) 100

× 105 Vaci (V)

Idci 0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

Vdc mode

0 0.4 2

Vdc mode CC mode

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.55

0.6

0.65

0.7

0.75

0.8

0.65

0.7

0.75

0.8

0

–2 0.4 0.45 0.5 × 108 5 Pi (W), Qi (VAr) 0 Pi –5 0.4 0.45 0.5 (b) Inverter Variables

Qi

0.55

Figure D.7 System responses in Example D.4.

0.6 Time (s)

D.5 Chapter 14 Examples

At the rectifier side the converter moves to alpha min mode but it still cannot maintain the DC current. Since the rectifier stays at very low angle (around 2∘ ), there is no increase in reactive power consumption. At the inverter side the DC current drops significantly and the inverter moves to current control. However, this requires significantly lower firing angle alpha (around 100∘ ) in order to reduce the DC voltage below the DC voltage at rectifier side. This implies very large reactive power consumption. At the inverter side active power transfer is only 50 MW but reactive power consumption is over 500 MVAr and this may have negative consequences on the stability of AC grid. For this reason VDCOL control logic is introduced, in order to reduce the DC current during voltage depressions. VDCOL helps fault recovery in particular with weak AC systems.

D.5 Chapter 14 Examples Example D.5 Simulate a single-phase inverter, with circuit as in Figure 14.1, and with V dc = 220 V, f = 50 Hz. (1) Assume purely resistive load R = 50 Ω. Sketch the load voltage and current. (2) Add a series inductor of 100 mH to the AC load. Determine the fundamental maximum AC voltage. Solution (1) It can be seen from Figure D.8 that voltage and current are in phase, as expected with a resistive load.

400

Vab (v)

200 0 –200 –400

0

0.01

0.02

0.03

0.04

0.05 0.06 Time (s)

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05 0.06 Time (s)

0.07

0.08

0.09

0.1

Iab (A)

5

0

–5

Figure D.8 System responses in Example D.5a.

523

Appendix D Simulink Examples

400

Vab (v)

200 0 –200 –400

0

0.01

0.02

0.03

0.04

0

0.01

0.02

0.03

0.04

0.05 Time (s)

0.06

0.07

0.08

0.09

0.1

0.06

0.07

0.08

0.09

0.1

5

Iab (A)

524

0

–5

0.05 Time (s)

Figure D.9 System response with inductor in Example D.5b.

(2) When an inductor is added to the load, the current lags the voltage by the angle of the load power factor, as shown in Figure D.9. The maximum fundamental voltage is 280 V.

D.6 Chapter 16 Examples Example D.6 Simulate a three-phase three-level diode clamped multilevel converter, with the circuit as in Figure 16.3, and with V dc = 1000 V, f = 50 Hz, assuming that the switching frequency is f s = 1.35 kHz. (1) Assuming a resistive load of R = 50 Ω, determine the AC current of phase a and comment on the waveform. (2) Connect an inductor of 100 mH in series to the AC load and comment on the current waveform. Determine the output maximum phase voltage value. Solution (1) With resistive load, the voltage and current will be in phase, as can be seen in Figure D.10. (2) In the case of an inductive load, as seen in Figure D.11b, the load acts as a low-pass filter and the current is closer to ideal sinusoidal wave. The load phase current is lagging the phase voltage by the load angle. The maximum phase fundamental voltage is 500 V.

D.6 Chapter 16 Examples

Voltage (V)

1000 500 0 –500 –1000

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05 Time (s)

0.06

0.07

0.08

0.09

0.1

0.05

0.06

0.07

0.08

0.09

0.1

0.05 0.06 Time (s)

0.07

0.08

0.09

0.1

Current (A)

20 10 0 –10 –20

Figure D.10 System responses in Example D.6a.

Voltage (V)

1000 500 0 –500 –1000

0

0.01

0.02

0.03

0.04

0

0.01

0.02

0.03

0.04

Current (A)

10 5 0 –5 –10

Figure D.11 System responses in Example D.6b.

Example D.7 Simulate a three phase nine-level half bridge modular converter, with circuit as in Figure 19.1 and with V dc = 1000 V, f = 50 Hz, assuming square wave modulation. (1) Assuming resistive load of R = 50 Ω, determine the AC current of phase a and comment on the waveform. (2) Connect an inductor of 100 mH in series to the AC load and comment on the current waveform. Determine the output maximum phase voltage value.

525

Appendix D Simulink Examples

Solution (1) It can be seen in Figure D.12a that voltage and current are in phase. (2) In the case of an inductive load, as shown in Figure D.13b the load acts as a lowpass filter and the current is closer to the ideal sinusoidal wave. The load current lags voltage by the load angle. The maximum phase fundamental voltage is 500 V.

Phase 0 Voltage (V)

1000 0 –1000

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05 Time (s)

0.06

0.07

0.08

0.09

0.1

Phase Voltage (V)

1000 0 –1000

Current (A)

20 0 –20

Figure D.12 System responses in Example D.7a.

Phase 0 Voltage (V)

1000 0 –1000 0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

0

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.1

Phase Voltage (V)

1000 0 –1000 20 Current (A)

526

0 –20 Time (s)

Figure D.13 System responses in Example D.7b.

D.7 Chapter 17 Examples 320 kV

Converter station 1 SCR = 20 PCC1 X/R = 10 Ig1 G1 330 kV 50 HZ

600 μF

10%

Converter station 2

Transmission line

600 μF

10%

PCC2 SCR = 20 X/R = 10

VDC1

10% 500 MVA

VDC2

600 μF

600 μF

Vg1

Ig2 10% 500 MVA V G2 g2 230 kV 50 HZ

Figure D.14 VSC HVDC System in Example D.8.

D.7 Chapter 17 Examples Example D.8 A symmetrical mono-polar 500 MVA, 100 MVAr, 320 kV HVDC system is shown in Figure D.14. The converter station 1 is controlling the active power between the two AC grids, while the converter station 2 controller is regulating the DC voltage. The Q channel at controller 2 regulates the AC voltage at PCC2 to support the AC grid. At station 1 the reactive current is controlled to zero. Sinusoidal pulse width modulation (SPWM) switching is used with triangular carrier wave with a frequency of 1.35 kHz. The copper DC cable is selected with total distance 100 km and the cable parameters are R = 0.0095 Ω km−1 , L = 2.11 mH km−1 , and C = 0.2 μF km−1 . (1) Develop a SIMULINK model for this system and ensure that the system operates in a stable manner for typical operating conditions. (2) Determine (by simulation or otherwise) the transformer ratios. It is desired that at full power in both power transfer directions the converters operate around 0.9 modulation index. (3) Test transient responses for full power reversal. (4) Assuming that system is working at 50% power, test transient responses for a step to 80% power. (5) Apply a line-to-line DC fault at DC bus 2 and determine DC and AC fault current at station 1. Compare the results with analytical values. (6) Run the system at full power but with station 1 as inverter. Apply solid three-phase fault at AC grid 1 and determine peak overcurrent in VSC1. Solution (1) The model responses are shown in Figure D.15. (2) Assume that the power flow is from station 1 to station 2 at rated value: Station 2: Inverter mode Vdc2 = 320 kV V

Vc𝟐 = 0.9 √dc2 = 101.82 kV, with 0.9 modulation index 2 2 √ Vc𝟐 LL = 3Vc𝟐 = 176.36 kV, Xtr2 = Xtr2pu

𝟐 Vgll𝟐

St2

= 0.1

2302 = 10.58 Ω 500

527

528

Appendix D Simulink Examples Vg1_abc (p.u.) 2 0 –2 0.2

0.4

0.6

0.8 Ig1_abc (p.u.)

1

1.2

1.4

0.4

0.6

0.8 Idqref & Idq (p.u.)

1

1.2

1.4

1

1.2

1.4

1

1.2

1.4

2 0 –2 0.2 2

Id 0 –2 0.2

Iq 0.4

0.6

0.8 Pref & P (p.u.) Pref

1

P

0 –1 0.2

0.4

0.6

0.8 Time (s) Vg2_abc (p.u.)

2 0 –2 0.2

0.4

0.6

0.8 Ig2_abc (p.u.)

1

1.2

1.4

0.4

0.6

0.8 Vdc (V)

1

1.2

1.4

0.4

0.6

1

1.2

1.4

1.2

1.4

2 0 –2 0.2 × 105 3.5 3 2.5 0.2 1000

0.8 P & Q (MW, MVar) P

Q

0

–1000 0.2

0.4

0.6

0.8 Time (s)

1

Figure D.15 Full power reversal in Example D.8 (top graph station 1; lower graph station 2).

D.7 Chapter 17 Examples 𝟐 Vgll𝟐 2302 Xr2 = Xr2pu = 0.1 = 10.58 Ω St2 500 √ √ P2 = S22 − Q22 = (500)2 − (100)2 = 489.9 MW

SCR2 =

𝟐 Vsll𝟐

⇒ zg2 =

𝟐 Vsll𝟐

=

2302 = 5.4 Ω 20 × 489.9

SCR2 × Pdc 5.4 Rs2 = √ =√ = 0.537 Ω, 1 + (X∕R)2 1 + (10)2 zs2 Pdc zs2

Xs2 = Rs2 × X∕R = 0.537Ω × 10 = 5.37 Ω Total impedance on the grid side is zs2 = Rs2 + j(Xs2 + Xtr2 + Xr2 ) zs2 = 0.537 + j(5.37 + 10.58 + 10.58) = 0.537 + j26.53 Ω Grid current S Ig2 = √ 3 × Vs𝟐

ll

500 MVA =√ = 1.255 kA 3 × 230 kV

Estimated PCC voltage Vg𝟐

es

√ = Vs𝟐 + zs2 Ig𝟐 = 230∕ 3 + 0.537 × 1255 + j26.53 × 1255 = 132.8 kV + 0.674 + j33.295 kV = 137.56 kV

Vg𝟐

est

= 238.26 kV

Transformer turns ratio: 176.36/137.56 = 1.28 (transformer turns ratio with phase values). Winding voltages 175/230. Station 1: Rectifier mode Idc1 =

Pdc = 1.531 kA Vdc2

Vdc1 = Vdc2 + Rdc Idc = 320,000 + 2 × 1531 × 0.95 = 322.91 kV Vc𝟏 = 0.9 Vc𝟏

Vdc1 √ 2 2

ll

= 102.75 kV, with 0.9 modulation index √ = 3Vc𝟏 = 178 kV,

Xtr1 = Xtr1pu

𝟐 Vgll𝟏

St1 𝟐 Vgll𝟏

= 0.1

3302 = 21.78 Ω 500

3302 = 21.78 Ω St1 500 𝟐 V𝟐 Vsll𝟏 3302 = = 11.11 Ω SCR1 = sll𝟏 ⇒ zs1 = zs1 Pdc SCR1 × Pdc 20 × 489.9

Xr1 = Xr1pu

= 0.1

529

530

Appendix D Simulink Examples

zs1 11.11 Rs1 = √ =√ = 1.1 Ω, Xs1 = Rs1 × X∕R = 1.1 Ω × 10 = 11 Ω 2 1 + (X∕R) 1 + (10)2 Total impedance on the grid side zs1 = Rs1 + j(Xs1 + Xtr1 + Xr1 ) zs1 = 1.1 + j(11 + 21.78 + 21.78) = 54.571 Ω = ∠88.7o S 500 MVA Ig1 = √ 1 =√ = 874.7 A 3 × 330 kV 3 × Vsll𝟏 Estimated PCC voltage. Vg𝟏

est

√ = Vs𝟏 − jzs1 Ig𝟏 = 330∕ 3 − 1.1 × 874.7 − j54.56 × 874.7

= 190.5 kV − 0.962 kV − j47.7 kV = 189.5 kV − j47.7 kV = 195.44 kV Vg𝟏

est

= 338.52 kV

Transformer turns ratio: 178/195.44 = 0.91 (transformer turns ratio with phase values). Winding voltages 175/330. (3) Figure D.15 shows the simulation of full power reversal. (4) Figure D.16 shows the simulation of power step from 50 to 80%. (5) DC fault Grid side fault current √ √ Vsll𝟏 ∕ 3 330000∕ 3 = = 3491.33 A Igf = zs1 54.571 Converter side fault current Vg 330 Igfc = Igf = 3491.33 × = 6583.6 A Vc 175 √ 3 Idcf = Igcf 2 = 8863.7 A 𝜋 It can be seen that the analytical fault current magnitude is in good agreement with the simulations in Figure D.17. (6) Observe peak currents on I d and I q immediately after the fault in Figure D.18. By √ calculation I = (I d 2 + I q 2 ) it can be concluded that peak magnitude is around 1.8, which is acceptable.

D.7 Chapter 17 Examples

Vg1_abc (p.u.) 2 0 –2 0.6

0.65

0.7

0.65

0.7

0.75 Ig1_abc (p.u.)

2

0.8

0.85

0.9

0.8

0.85

0.9

0.8

0.85

0.9

0.8

0.85

0.9

0 –2 0.6 1

0.75 Ig1dqref & Ig1dq (p.u.)

Ig1d

0.5

Ig1q

0 –0.5 0.6

0.65

0.7

0.75 Pg1ref & Pg1 (p.u.)

Pref

1 0.5

P

0 0.6

0.65

0.75 Time (s)

0.7

Vg2_abc (p.u.) 2 0 –2 0.5

0.55

0.6

0.65

0.7

0.75 Ig1_abc (p.u.)

0.8

0.85

0.9

0.95

1

0.55

0.6

0.65

0.7

0.75 Vdc2 (V)

0.8

0.85

0.9

0.95

1

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

0.95

1

0.95

1

2 0 –2 0.5 × 105 3.5 3 2.5 0.5

Pg2 & Qg2 (MW, Mvar)

600 400 200

Q

P

0 0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

Time (s)

Figure D.16 Power step (50% ≥ 80%) in Example D.8 (top graph station 1; lower graph station 2).

531

532

Appendix D Simulink Examples Vg1_abc (p.u.) 2 0 –2 0.8

0.9

1

1.1

1.2 Ig1_abc (p.u.)

1.3

1.4

1.5

0.9

1

1.1 1.2 Ig1dqref & Ig1dq (p.u.)

1.3

1.4

1.5

1.3

1.4

1.5

1.2

1.3

1.4

1.5

1.2

1.3

1.4

1.5

1.2 Ig2_abs (p.u.)

1.3

1.4

1.5

1.2

1.3

1.4

1.5

1.2

1.3

1.4

1.5

1.2

1.3

1.4

1.5

5 0 –5 0.8 2 0 –2 –4 0.8

Ig1q 0.9

1

2

1.1 1.2 Pg1ref & Pg1 (p.u.) P Pref

0 –2 0.8

Ig1d

0.9

1

1.1

0.9

1

1.1

15000

Idc (A)

10000 5000 0 –5000 0.8

Time (s) Vg2_abs (p.u.)

2 0 –2 0.8

0.9

1

1.1

0.9

1

1.1

0.8

0.9

1

1.1

500 0 –500 –1000 0.8

0.9

1

1.1

5 0 –5 0.8 × 105 4 2 0

Vdc (V)

Pg2 (mw)

TIme (s)

Figure D.17 DC fault in Example D.8 (top graph station 1; lower graph station 2).

D.7 Chapter 17 Examples

Vg1_abc (p.u.) 2 0 –2 0.7

0.8

0.9

1

1.1

1.2 Ig1_abc (p.u.)

1.3

1.4

1.5

1.6

1.7

0.8

0.9

1

1.1 1.2 1.3 Ig1dqref & Ig1dq (p.u.)

1.4

1.5

1.6

1.7

1.4

1.5

1.6

1.7

1.4

1.5

1.6

1.7

2 0 –2 0.7 2

Ig1q 0 –2 0.7

Ig1q 0.8

0.9

1

1.1

1.2 1.3 Pg1ref & Pg1 (p.u.)

1

P

0

Pref

–1 –2 0.7

0.8

0.9

1

1.1

1.2 Time (s)

1.3

Vg2_abc (p.u.) 2 0 –2 0.7

0.8

0.9

1

1.1

1.2 Ig2_abc (p.u.)

1.3

1.4

1.5

1.6

1.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1

1.1 1.2 1.3 Pg2 & Qg2 (MW, MVar)

1.4

1.5

1.6

1.7

1

1.1

1.4

1.5

1.6

1.7

2 0 –2 0.7

Vdc (V)

× 105 3.5 3 2.5 0.7

0.8

0.9

1000

Q

0 –1000 0.7

P 0.8

0.9

1.2 Time (s)

1.3

Figure D.18 AC fault in Example D.8 (top graph station 1; lower graph station 2).

533

535

Index a ABC frame 507, 513 AC fault 114, 339, 383, 389 AC networks of different frequencies 3 AC voltage control 237 analytical modelling 57 arm inductance 215 arm voltage control 301 average modeling - 2-level VSC 227 average value model - DC/DC 471 average value modeling - HB MMC 275

commutation voltage drop 31 conduction losses 171 control and communication system control loops 62, 233 converters 4 converter station 4 converter transformers 4 coordinate frame 510 critical DC voltage 346 current margin 45

d b back-to-back HVDC 9 bipolar HVDC 8 black start 360 blocked MMC 276, 310 buck-boost converters 469 bypass switch (BPS) 115

c cable model in state space 70, 72 capacitor commutated converters 104 capacitors voltage balance 212 capital investment 4 cascaded two-level converter 218 cell capacitor 214 characteristic harmonics 124 CIGRE DC grid 411 CIGRE HVDC benchmark 60 circulating current 272, 287 commutation 28, 33 commutation failure 45, 383 commutation overlap 28, 33, 45

damped filter 128 DC cable 7, 147 DC capacitor 156, 210 DC CB 417 DC current control 37, 45 DC/DC converter 469, 473, 484 DC fault 111, 339, 351, 354, 441 DC grid 373 DC grid control 399 DC grid dynamics 399 DC hub 495 DC side reactor 344 DC voltage control 44, 239 DC voltage polarity reversal 52, 319 decoupling loops 235 differential current 272, 286 differential protection 452 diode converter 25 dispatcher 401, 406 DQ frame 507 droop feedback 240, 404 dual active bridge DC/DC 484

High Voltage Direct Current Transmission: Converters, Systems and DC Grids, Second Edition. Dragan Jovcic. © 2019 John Wiley & Sons Ltd. Published 2019 by John Wiley & Sons Ltd.

5

536

Index

e earth return transfer breaker (ERTB) 119 eigenvalues 77, 79, 80, 81, 242 eigenvalue sensitivity 77, 78, 79 electrodes 5 energy to power ratio 214, 305 equivalent short circuit ratio 95 extinction advance angle 34 extinction angle 33 extruded cross-linked polyethylene (XLPE) cables 8, 140

inertia constant 108 inertia contribution 360 injection enhanced gate transistor (IEGT) 172 insulated gate bipolar transistor (IGBT) 165 insulated gate commutated thyristor (IGCT) 165 insulation 12 internal faults 115 inverter 43 Italy–Corsica–Sardinia HVDC 380

f fault isolation 442 fault location 447 filter 124 firewall 360 forward blocking 168 forward output characteristics 168 forward voltage 13 frequency control 41 frequency response 66, 69, 75 frequency stabilisation 41 frequency stability 359 full bridge MMC 151, 222, 309 full-bridge module 222

g gain scheduling 60 gamma minimum control 43 grid stabilization 359

h half bridge MMC 151, 210, 269 harmonics 121, 199 harmonic filters 124 harmonic instability 80 harmonic limits 122 HVDC control 40, 227 HVDC operating point 49 HVDC stability 77, 242 100Hz oscillations 82 hybrid DC CB 434

i ignition advance angle inductors 160, 161

33

l latching current 13 LCL DC/DC converter 490 LCL VSC converter 459 leakage current 13 linearised dynamic model 60, 227 line commutated converter 28 losses 18, 171 losses in HVDC 10 low inertia 106 low pressure oil filled (LPOF) cables

7

m mass-impregnated cables 7 maximum available power 101 mechanical DC CB 422 Metalic Return Transfer Breaker (MRTB) 117 MMC analytical model 269, 309 MMC capacitance 212 MMC cell charging 276, 312 MMC model 276, 310 MMC phasor model 295 MMC start up 278, 312 modelling 57 modelling with switchings 57 modular design 159 modular multilevel converter (MMC) 151, 205, 269, 309 modulating signal 194 monopolar HVDC 8 M2DC 473 multilevel converters 205 multiterminal HVDC 379, 390

Index

n nearest level control 218 neutral bus switches (NBS) 117 neutral point clamped (NPC) converter 150 North Sea DC grid 496

o offshore wind farms 362 on-state resistance 18, 165 operating diagrams 254 overhead lines 7, 142 overvoltages 119

p Park’s ABC-DQ transformation 64, 508 passive AC system 362 phase locked loop 38 phasor model 83, 249 phasor modelling 58 phasor notation 515 power flow 390, 406, 465 power oscillations 359 power transfer between two AC systems 361 PQ diagram 255, 306 press pack design 159 primary system response 402 protection circuits 20 protection logic 446 protection system 446 pulse width modulation (PWM) 193, 218

r reactive power capacitors 88 reactive power compensation 5 rectifier 37 reverse breakdown 14

s safe operating area 166 secondary response 403 second harmonic instability 80 selective harmonic elimination 198 selective protection 445 semiconductor based DC CB 430 short circuit level 96 silicon carbide diodes 171

SIMULINK 517 single-phase inverter 181 sinusoidal pulse width modulation small signal stability 58, 359 smoothing reactors 5 snubber 20 stability 57, 233 state space model 60, 301, 510 static var compensator 103 surge arresters 119 switching characteristic 14 switching frequency 19

195

t tap changer 38 tertiary control 403 third harmonic injection 197 3-phase bridge 27 three phase converters 184 thyristor 13 transformer 155 transformer inductance 28 transformer model 67 tuned filter 126 turn-off switching loss 174 turn-on switching loss 174 two-level voltage source converter

u ultra high voltage DC 12 unit protection 452 unsynchronised AC grids 3

v valves 158, 159 valve structure 20 VDCOL 114 V-I operating curves 49 voltage source converter 181 voltage stability 360 VSC diode bridge 345, 348

w weak AC grids 102 weak AC systems 95, 242 wideband cable model 70

x XLPE cables

8, 140

193

537