High-k Materials in Multi-Gate FET Devices (Science, Technology, and Management) [1 ed.] 0367639688, 9780367639686

Table of contents :
Cover
Half Title
Series Page
Title Page
Copyright Page
Table of Contents
Preface
Editors
Contributors
Chapter 1: Introduction to Multi-Gate FET Devices
1.1 Introduction
1.2 Double-Gate Devices
1.3 Triple-Gate MOSFET Devices
1.4 FINFET Characteristics and Modeling
1.5 Surrounding-Gate SOI MOSFETs
1.6 Additional Multi-Gate FETs
1.7 Materials for Multi-Gate Devices
1.7.1 Requirements and Characteristics of Multi-Gate in Devices
1.8 Nano-Sheet GAA
1.8.1 Nanowire GAA
1.8.2 SOI Multi-Gate MOSFET Designs
1.9 Gate-All-Around (GAA) Nanowire (NW) MOSFETs
1.10 GAA Nanowire (NW) Transistors
1.11 Double-Gate versus Tri-Gate FET
1.12 MIGFET and FinFET Process Technology
1.13 Important Parameters in FinFET
1.13.1 Current
1.13.2 Corner Effects
1.13.3 Sub-threshold Slope
1.14 Conclusion
References
Chapter 2: High- k Gate Dielectrics and Metal Gate Stack Technology for Advance Semiconductor Devices: An overview
2.1 Introduction
2.2 Downscaling Issues and High- k Materials Relevance in Microelectronics Industry
2.3 Material Chemistry and Requirements for High- k  Gate Dielectrics
2.3.1 Energy Band Gap, Barrier Height, and Dielectric Constant
2.3.2 Large k Value
2.3.3 Thermodynamic Stability
2.3.4 Kinetic Stability
2.3.5 High-Quality Interface and Defects
2.4 Oxide Deposition
2.4.1 MOCVD
2.4.2 ALD
2.4.3 PVD
2.5 Metal Gates and Their Work Function Requirements
2.6 Electrical Behavior/Electrical Characteristics of High- k -Based Devices
2.6.1 Flat Band Voltage and Threshold Voltage Control
2.6.2 Mobility Degradation
2.7 Relevance of High- k Gate Dielectrics with TFET
2.8 TFET
2.8.1 TFET Device Structure and Operating Principle
2.8.2 Applications of TFET
2.9 Applications of High- k Materials
2.10 Summary
Acknowledgments
References
Chapter 3: Influence of High- k Material in Gate Engineering and in Multi-Gate Field Effect Transistor Devices
3.1 Introduction: Background and Driving Forces
3.2 Double-Gate Metal Oxide Semiconductor FET (DGMOSFET)
3.3 Cylindrical Gate-All-Around Metal Oxide Semiconductor FET (CGAA MOSFET)
3.4 Gate Engineering of Multi-Gate MOSFET
3.4.1 Dual-Metal Double-Gate MOSFET
3.4.2 Triple-Material Double-Gate MOSFET
3.4.3 Double-Metal Surrounding-Gate (DMSG) MOSFET
3.4.4 Triple-Metal Surrounding-Gate (TMSG) MOSFET
3.5 Impact of High- k Dielectrics in Gate Engineering and Multi-Gate MOSFET Structures
References
Chapter 4: Trap Charges in High- k and Stacked Dielectric
4.1 Introduction
4.2 Need for High- k Dielectric
4.3 Background and History of Research
4.4 Review of Negative BIOS Temperature Instability (NBTI)
4.5 Use of High- k Dielectric
4.6 Trap Time Constant
4.7 Properties of Trap in the High- k with Interfacial Layer
4.7.1 Silicon and Interfacial Layer
4.7.2 Interfacial Bulk Region
4.7.3 IL/HK Interface
4.7.4 HK Bulk
4.7.5 HK and Gate Interface
4.8 Technique for the Trap Extraction from the Stack Structure
4.8.1 Capacitance Inversion Technique (CI)
4.8.2 Charge Pumping Technique
4.9 Summary
References
Chapter 5: Impact of High- k Dielectric on the Gate-Induced Drain Leakage of Multi-Gate FETs
5.1 Introduction
5.2 Gate-Induced Drain Leakage (GIDL)
5.2.1 Transverse-BTBT
5.2.2 Lateral-BTBT GIDL
5.3 Impact of High- k Dielectric on GIDL of MuGFETs
5.3.1 Nanowire FETs
5.3.1.1 Structure
5.3.1.2 GIDL in NWFETs
5.3.1.3 Impact of High- k Sidewall Spacers
5.3.2 Nanotube FET
5.3.2.1 Structure
5.3.2.2 GIDL in Nanotube FET
5.3.2.3 Impact of High- k Sidewall Spacers
5.3.3 Nano-Sheet FETs
5.3.3.1 Structure
5.3.3.2 GIDL in Nano-Sheet FET
5.3.3.3 Impact of High- k Sidewall Spacers
5.4 Conclusion
References
Chapter 6: Advanced FET Design Using High- k Gate Dielectric and Characterization for Low-Power VLSI
6.1 Introduction
6.2 JFETs and MOSFETs
6.3 Scaling and Short Channel Effects (SCEs)
6.4 Multi-Gate MOSFETs
6.5 Leakage Current
6.6 Importance of High- k Materials
6.7 Next-Generation Transistors
6.8 Tunnel Filed Effect Transistors with High- k Dielectric
6.9 DG TFET with High- k Dielectric
6.10 Tri-Gate TFET with High- k Dielectric
6.11 DG TFET with SiO 2 /High- k Stacked Dielectric
6.12 Heterojunction TFET with SiO 2 /High- k Stacked Dielectric
6.13 Junctionless Transistors with High- k Dielectric
6.14 Double-Gate Junctionless Transistor SiO 2 /High- k Stacked Dielectric
6.15 Nanowire FETs with High- k
6.16 Carbon Nanotubes FETs with High- k
6.17 Summary
References
Chapter 7: Simulation and Analysis of Gate Stack DG MOSFET with Application of High- k Dielectric Using Visual TCAD
7.1 Introduction
7.2 Choice for Dielectric Material: Conventional SiO 2 versus High-k Material
7.2.1 SiO 2 as Dielectric
7.2.2 High-k Material as Dielectric
7.3 Choice for Gate Material: Polysilicon Gate versus Metal Gate
7.4 Simulation of DGFET with Application of High-k Dielectric and Metal Gate
7.5 Conclusion
References
Chapter 8: Novel Architecture in Gate-All-Around (GAA) MOSFET with High- k Dielectric for Biomolecule Detection
8.1 Introduction
8.2 Device Design and Simulation
8.3 Results and Discussions
8.4 Conclusion
References
Chapter 9: Asymmetric Junctionless Transistor: A SRAM Performance Study
9.1 Introduction
9.2 Device Structure
9.3 Device Simulation and Electrostatics
9.4 SRAM Cell
9.5 Results and Discussion
9.6 Conclusion
References
Chapter 10: Performability Analysis of High- k Dielectric–Based Advanced MOSFET in Lower Technology Nodes
10.1 Introduction
10.2 Results and Discussions
10.3 Conclusion
References
Index

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