Future Trends in Microelectronics: Frontiers and Innovations 9781118442166, 9781118678107

Citation preview

FUTURE TRENDS IN MICROELECTRONICS

FUTURE TRENDS IN MICROELECTRONICS Frontiers and Innovations

Edited by

SERGE LURYI JIMMY XU ALEX ZASLAVSKY

WILEY

Copyright © 2013 by John Wiley & Sons, Inc. All rights reserved. Published by John Wiley & Sons, Inc., Hoboken, New Jersey. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4470, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., I l l River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, or online at http://www.wiley.com/go/permission. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representations or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services or for technical support, please contact our Customer Care Department within the United States at (800) 762-2974, outside the United States at (317) 572-3993 or fax (317) 572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print may not be available in electronic format. For information about Wiley products, visit our web site at www.wiley.com. Library of Congress Cataloging-in-Publication Data is available. ISBN 978-1118-44216-6 Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1

CONTENTS Preface S. Luryi, J. M. Xu, and A. Zaslavsky

ix

I

INNOVATIONS IN ELECTRONICS AND SYSTEMS

1

Technology Innovation, Reshaping the Microelectronics Industry K. Kim and U.-I. Chung

4

Challenges and Limits for Very Low Energy Computation F. Balestra

49

Getting Rid of the DRAM Capacitor N. Rodriguez, F. Gamiz, andS. Cristoloveanu

59

Physics and Design of Nanoscale Field Effect Diodes for 73 Memory and ESD Protection Applications D. E. loannou, Z. Chbili, A. Z. Badwan, Q. Li, Y. Yang, and A. A. Salman Sharp-Switching CMOS-Compatible Devices with High Current Drive J. Wan, S. Cristoloveanu, S. T. Le, A. Zaslavsky, C. Le Royer, S. A. Day eh, D. E. Perea, andS. T. Picraux

81

Magnetic Tunnel Junctions with a Composite Free Layer: A New Concept for Future Universal Memory A. Makarov, V. Sverdlov, andS. Selberherr

93

Silicon Carbide High Temperature Electronics Is This Rocket Science? C.-M. Zetterling

102

Microchip Post-Processing: There is Plenty of Room at the Top J. Schmitz

110

EUV Lithography: Today and Tomorrow V. Y. Banine

120

Manufacturability and Nanoelectronic Performance M J. Kelly v

133

vi

II

Contents

OPTOELECTRONICS IN THE NANO AGE

139

Ultrafast Nanophotonic Devices For Optical Interconnects N. N. Ledentsov, V. A. Shchukin, andJ. A. Lott

142

Will Optical Communications Meet the Challenges of the Future? D. K. Mynbaev

160

Optical Antennae for Optoelectronics: Impacts, Promises, and Limitations H. Mohseni

173

Spin Modulation: Teaching Lasers New Tricks J. Lee, G. Boéris, R. Oszwaidowski, K. Vyborny, C. Gothgen, and I. Zutić

183

III HARVESTING ENERGY FROM THE SUN AND THE ENVIRONMENT

191

Silicon Photovoltaics: Accelerating to Grid Parity M R. Pinto

194

Two- and Three-Dimensional Numerical Simulation of Advanced Silicon Solar Cells E. Sangiorgi, M. Zanuccoli, R. De Rose, P. Magnone, and C. Fiegna

210

Mechanical Energy Harvesting with Piezoelectric Nanostructures: Great Expectations for Autonomous Systems G. Ardila, R. Hinchet, L. Monies, andM. Mouis

230

Charged Quantum Dots for Photovoltaic Conversion and IR Sensing A. Sergeev, V. Mitin, N. Vagidov, andK. Sablon

244

Active Optomechanical Resonators 254 D. Princepe, L. Barea, G. O. Luiz, G. Wiederhecker, andN. C. Frateschi

Contents

Vll

IV PHYSICS FRONTIERS

263

State of the Art and Prospects for Quantum Computing M. I. Dyakonov

266

Wireless, Implantable Neuroprosthesis: Applying Advanced Technology to Untether the Mind D. A. Borton and A. V. Nurmikko

286

Correlated Electrons: A Platform for Solid State Devices S. D. Ha, Y. Zhou, R. Jaramillo, andS. Ramanathan

300

Graphene-Based Integrated Electronic, Photonic and Spintronic Circuit A. D. Güçlü, P. Potasz, and P. Hawrylak

308

Luttinger Liquid Behavior of Long GaAs Quantum Wires E. Levy, I. Sternfeld, M. Eshkol, M. Karpovski, A. Palevski, B. Dwir, A. Rudra, E. Kapon, and Y. Oreg

319

Toward Spin Electronic Devices Based on Semiconductor Nanowires S. Heedt, I. Wehrmann, K. Weis, H. Hardtdegen, D. Griitzmacher, Th. Schapers, C. Morgan, D. E. Biirgler, andR. Calarco

328

An Alternative Path for the Fabrication of Self-Assembled Ill-Nitride Nanowires A. Haab, M. Mikulics, T. Stoica, B. Kardynal, A. Winden, H. Hardtdegen, D. Griitzmacher, andE. Sutter

340

InAs Nanowires with Surface States as Building Blocks for Tube-Like Electrical Sensing Transistors N. V. Demarina, M. I. Lepsa, andD. Griitzmacher

351

Levy Flight of Photoexcited Minority Carriers in Moderately Doped Semiconductors: Theory and Observation A. Subashiev andS. Luryi

359

Terahertz Plasma Oscillations in Field Effect Transistors: Main Ideas and Experimental Facts W. Knap andM. I. Dyakonov

373

INDEX

395

Preface S. Luryi Dept. of Electrical and Computer Engineering State University of New York, Stony Brook, NY 11794-2350, U.S.A. J. M. Xu and A. Zaslavsky School of Engineering, Brown University, Providence, RI02912, U.S.A.

This book is a brainchild of the seventh workshop in the Future Trends in Microelectronics series (FTM-7). The first of the FTM conferences, "Reflections on the Road to Nanotechnology", had gathered in 1995 on He de Bendor, a beautiful little French Mediterranean island.1 The second FTM, "Off the Beaten Path", took place in 1998 on a larger island in the same area, He des Embiez.2 Instead of going to a still larger island, the third FTM, "The Nano Millennium", went back to its origins on He de Bendor in 2001.3 As if to compensate for small size of Bendor, the fourth FTM, "The Nano, the Giga, the Ultra, and the Bio", took place on the biggest French Mediterranean island of them all, Corsica.4 Normally, the FTM workshops gather every three years; however, the FTM-4 was held one year ahead of the usual schedule, in the summer of 2003, as a one-time exception. Continuing its inexorable motion eastward, the fifth FTM workshop, "Up the Nano Creek", had convened on Crete, Greece, in June of 2006.5 The inexorable motion was then interrupted to produce a semblance of a random walk in the Mediterranean and the FTM-6 "Unmapped Roads" went to the Italian island of Sardinia (June, 2009).6 The last FTM gathering, "Into the Cross Currents", returned to our earlier venue on Corsica (June 2012). The FTM workshops are relatively small gatherings (less than 100 people) by invitation only. If you, the reader, wish to be invited, please consider following a few simple steps outlined on the conference website. The FTM website at www.ece.sunysb.edu/~serge/FTM.html contains links to all past and planned workshops, their programs, publications, sponsors, and participants. Our attendees have been an illustrious lot. Suffice it to say that among FTM participants we find five Nobel laureates (Zhores Alferov, Herbert Kroemer, Horst Stormer, Klaus von Klitzing, and Harold Kroto) and countless others poised for a similar distinction. To be sure, high distinction is not a prerequisite for being invited to FTM, but the ability and desire to bring fresh ideas is. All participants of FTM-7 can be considered authors of this book, which in this sense is a collective treatise. The main purpose of FTM workshops is to provide a forum for a free-spirited exchange of views, projections, and critiques of current and future directions, among the leading professionals in industry, academia, and government. IX

X

Preface

For better or worse our civilization is destined to be based on electronics. Ever since the invention of the transistor and especially after the advent of integrated circuits, semiconductor devices have kept expanding their role in our lives. Electronic circuits entertain us and keep track of our money, they fight our wars and decipher the secret codes of life, and one day, perhaps, they will relieve us from the burden of thinking and making responsible decisions. Inasmuch as that day has not yet arrived, we have to fend for ourselves. The key to success is to have a clear vision of where we are heading. In the blinding light of a bright future, the FTM community has remained mindful of the fact that what controlled the past will still control the future - the basic principles of science. Thus, the trendy, red-hot projections of any given epoch deserve and require critical scrutiny. Some degree of stability is of importance in these turbulent times and should be welcome. Thus, although the very term "microelectronics" has been generally re-christened "nanoelectronics", we have stuck to the original title of the FTM workshop series. The present volume contains a number of original papers, some of which were presented at FTM-7 in oral sessions, other as posters. From the point of view of the program committee, there is no difference between these types of contributions in weight or importance. There was, however, a difference in style and focus and that was intentionally imposed by the organizers. All speakers were asked to focus on the presenter's views and projections of future directions, assessments or critiques of important new ideas/approaches, and not on their own achievements. This latter point is perhaps the most distinctive feature of FTM workshops. Indeed, we are asking scientists not to speak of their own work! This has proven to be successful, however, in eliciting powerful and frank exchange. The presenters are asked to be provocative and/or inspiring. Latest advances made and results obtained by the participants are to be presented in the form of posters and group discussions. Each day of the workshop was concluded by an evening panel or poster session that attempted to further the debates on selected controversial issues connected to the theme of the day. Each such session was chaired by a moderator who invited two or three attendees of his or her choice to lead with a position statement, with all other attendees serving as panelists. The debate was forcefully moderated and irrelevant digressions cut off without mercy. Moderators were also assigned the hopeless task of forging a consensus on critical issues. To accommodate these principles, the FTM takes a format that is less rigid than usual workshops to allow and encourage uninhibited exchanges and sometimes confrontations of different views. A central theme is designed together with the speakers for each day. Another traditional feature of FTM workshops is a highly informal vote by the participants on the relative importance of various fashionable current topics in modern electronics research. This tradition owes its origin to Horst Stormer, who composed the original set of questions and maintained the results over four conferences. These votes are perhaps too bold and irreverent for general publication, but they are carefully maintained and made

Preface

XI

available to every new generation of FTM participants. Another traditional vote concerned the best poster. The 2012 winning poster was "Mechanical energy harvesting with piezoelectric nanostructures: Great expectations for autonomous systems" by Gustavo Ardila. A joyful tradition of FTM meetings is the settling of scientific bets, a custom that dates back to the 1998 wager between Nikolai Ledentsov (pro) and Horst Stormer (con) about the putative future dominance of quantum dot-based lasers - a bet that Horst collected in 2004, at FTM-4. Another risky bet on the future dominance of SOI technology is to be adjudicated at a future (2015) workshop. The precise statement of this "good" bet (worth a six-magnum case of very good champagne) is: by 2015, SOI will cover more than 35% of the CMOS market including memories by value. This bet, proposed by Sorin Cristoloveanu, attracted three cons - Detlev Griitzmacher, Dimitris Ioannou, and Enrico Sangiorgi - who will have to divide the spoils, should SOI fail to reach the mark. Several "bad" (penniless) bets that were supposed to be resolved at FTM-7 were put off as premature by the principals. Hopefully, by 2015 it will become clear whether or not "10% of all man-produced light will be white LED" (Michael Shur), "we shall have hi-fi real-time pocket translators" (Hiroshi Iwai), "most cars will have IP addresses" (Jimmy Xu), or "the Si industry will no longer be recognizable and there will be (essentially) no further improvement in devices" (Paul Solomon). Not every contribution presented at FTM-7 has made it into this book (not for the lack of persistence by the editors). Perhaps most sorely we miss the exciting contribution by David Miller of Stanford University, entitled "The heat death of information processing and why interconnects matter more than logic", in which he illustrated how the energy required by data communication is imposing severe limits on overall information processing, with the demand for communications bandwidth increasing a hundredfold every decade. As a result, he posited very low energy optoelectronics densely integrated with logic as a way of allowing the continued scaling of information processing systems. Abstracts of his and all other presentations can be found on the program webpage, http://w w w. ee. sunysb. edu/~serge/A R W- 7/program. htm I The FTM meetings are known for the professional critiques - or even demolitions — of fashionable trends, that some may characterize as hype. The previous workshops had witnessed powerful assaults on quantum computing, molecular electronics, and spintronics. This time Michel Dyakonov offered another thorough and conclusive update on quantum computing. It seems that by now most of the hype associated with some of these trends has dissipated and perhaps we can take some credit for the more balanced outlook that has emerged since. We have grouped all contributions into four chapters: one dealing with transistors and CMOS or CMOS-compatible technology, another with photonics and lasers, and still another with solar cell and energy harvesting. The last chapter collected the contributions focused on fundamental physics and other, less

Preface

хп

technological subjects. The breakdown could not be uniquely defined, because some papers fit two or even three categories! To produce a coherent collective treatise out of all of this, the interaction between FTM participants had begun well before their gathering at the workshop. All the proposed presentations were posted on the web in advance and could be subject to change up to the last minute to take into account peer criticism and suggestions. After the workshop is over, these materials (not all of which have made it into this book) remain on the web indefinitely, and the reader can peruse them starting at the www.ece.sunysb.edu/~serge/FTM.html home page. Acknowledgments The 2012 FTM workshop on Corsica and therefore this book were possible owing to support from: •

US National Science Foundation

•

U.S. Department of Defense: ARO

•

U.S. DoD European offices: EOARD, ONR-Global

•

Industry: SAIT, Samsung Electronics Co.

•

Academia: SUNY-Stony Brook, Brown University.

On behalf of all workshop attendees sincere gratitude is expressed to the above organizations for their generous support and especially to the following individuals whose initiative was indispensable: William Clark, John Gonglewski, Kinam Kim, Mark Pinto, Shawn Thorne, Robert True, and John Zavada. Finally, the organizers wish to thank all of the contributors to this volume and all the attendees for making the workshop a rousing success.

Preface

хш

References 1. 2. 3. 4. 5. 6.

S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: Reflections on the Road to Nanotechnology, NATO ASI Series E Vol. 323, Dordrecht: Kluwer Academic, 1996. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: The Road Ahead, New York: Wiley Interscience, 1999. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: TheNano Millennium, New York: Wiley Interscience/IEEE Press, 2002. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: The Nano, The Giga, and The Ultra, New York: Wiley Interscience/IEEE Press, 2004. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: Up the Nano Creek, Hoboken, NJ: Wiley Interscience/IEEE Press, 2007. S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: From Nanophotonics to Sensors to Energy, Hoboken, NJ: Wiley Interscience/ IEEE Press, 2010.

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Parti Innovations in Electronics and Systems

I.

Innovations in Electronics and Systems

The incredibly powerful silicon electronics is still full of steam, charging ahead despite the putatively insurmountable barriers and walls (of thermal, power, wiring, and scaling, for example). Equally evident is that the challenges ahead are real, getting greater, and often without a clear answer. One example is transition to EUV lithography, discussed in the chapter by Banine. What are the biggest challenges anticipated and the biggest changes assumed in the existing roadmap? If science is not (yet) the ultimate limit to nanoelectronics, is it manufacturability, discussed in the chapter by Kelly? What are the most desired innovations, and the most disruptive, interesting, and controversial directions? While the drive for ever greater device performance - discussed in a number of chapters devoted to novel memory and logic devices - is becoming prohibitively costly, could the advances in systems and integrated functionalities be sufficiently rewarding to justify and become the next driving force? These questions are addressed in Part I of this book, which opens with an insightful and comprehensive discussion of technology innovation by Kim and Chung, from the innovation powerhouse of Samsung Electronics.

Contributors 1.1

K. Kim and U-I. Chung

1.2

F. Balestra

1.3

N. Rodriguez, F. Gamiz, and S. Cristoloveanu

1.4

D. E. Ioannou, Z. Chbili, A. Z. Badwan, Q. Li, Y. Yang, and A. A. Salman

1.5

J. Wan, S. Cristoloveanu, S. T. Le, A. Zaslavsky, C. Le Royer, S. A. Dayeh, D. E. Perea, and S. T. Picraux

1.6

A. Makarov, V. Sverdlov, and S. Selberherr

1.7

C.-M. Zetterling

1.8

J. Schmitz

1.9

V.Y. Banine

1.10 M.J.Kelly

3

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Technology Innovation, Reshaping the Microelectronics Industry Kinam Kim and U-In Chung Samsung Advanced Institute of Technology, Samsung Electronics Co. Ltd. Giheung, Gyonggi-do, South Korea

1.

Introduction

The remarkable evolution of electronics was enabled by the rapidly advancing silicon technology. The performance of such devices as CPUs and memories has improved tremendously over the past 20 years: CPUs improved by a factor of 2,400, DRAM by a factor of 1,000 and NAND Flash by a factor of 32,000. Mobile network speed has also increased by a factor of 840, stimulated by an increased usage of smartphones and tablets, which have grown by 58%' and 260%2 in 2011, respectively. Furthermore, Internet communication traffic is anticipated to increase by 32% annually, with the traffic reaching an order of zeta (1021) bytes by 2015.3 These performance improvements have been made possible by silicon technology downscaling, which is nearing the 20 nm node and will soon reach 10 nm. Novel fabrication techniques, structures and materials will be required to continue scaling beyond 10 ran to satisfy the data handling, processing and storage requirements of the future. Future device development will be constrained by power consumption, in addition to the traditional scaling issues, since faster and higher data handling and processing will unavoidably require a lot of power. For instance, 1.1 petaflop (1015) computing in 20084 consumed 2.3 MW power for its operation, so an exascale (1018) system might dissipate an estimated 2.3 GW, roughly equivalent to the electricity produced by two nuclear power plants. Most of this energy is lost in the inefficient metal interconnects, which could be reduced by combining photonics with Si technologies. This silicon-photonics convergence will create new applications and markets in the future. Furthermore, silicon technology is bringing innovation to new areas, such as energy, health, and medical applications. Examples of this are ultrafast DNA sequencing, extremely compact and efficient medical imaging devices, and lowcost energy-efficient lighting, among others. These applications, fueled by Si technologies, could eventually take up a major portion of the semiconductor market in the next decade.

4

Technology Innovation, Reshaping the Microelectronics Industry 2.

5

Mainstream silicon technology: Memory

Towards sub-20 nm DRA M DRAM density has doubled every 18 months through scaling of the critical dimensions, approaching the 20 nm node today, as shown in Fig. 1. Major challenges to downscaling to the sub-10 nm regime will require device innovations in cell storage capacitors, cell array transistors (CATs) and patterning processes.5 The minimum cell capacitance must be maintained to provide an adequate signal for sensing and to meet retention time specifications.6 In order to maintain the cell capacitance, as DRAM downscaled from 90 nm to 20 nm, the capacitor structure has been changed from a simple 3D cylindrical shape to an extremely high aspect ratio (AR) supported cylinder or pillar structure, as shown in Fig. 2. For sub-10 nm DRAMs, structural innovation may not help any longer due to physical limitations in accommodating complex 3D structures. At sub-10 nm nodes, the distance between electrodes becomes ~10 nm or less, which in turn requires the physical thickness of the storage electrodes and the dielectrics to be thinner than 5 nm or less. These requirements will be very difficult to meet. However, the limitation of cell capacitance can be compensated by the technological innovation in CAT with extremely low leakage currents and/or array architecture and its integration process to provide high sensing signals. •

From a device point of view, requirements related to the retention limit can be overcome by suppressing the storage node leakage current /LEAK- The data retention time ÍRE is fundamentally determined by the amount of the stored charge and the time-dependent charge loss at the storage node.7 The sensing voltage AVBL is as follows: AV BL =

Cs

■ ARR _ д у

C„, + 0 S. V 'BL

1

L

(1)

where C s is the cell storage capacitance, KARR is the array voltage, C B L is the bit

Figure 1. DRAM technology roadmap of ITRS and top DRAM supplier.

6

Future Trends in Microelectronics

line loading capacitance, and AVL is the voltage loss due to charge loss during the retention. The charge loss can be expressed by QLEAK^ CS(AF L ) = ^LEAKÍRE, from which the data retention time can be obtained as follows:

,

l

№~

_^Ккя/2-АУвь)-Свь(А^) r

LEAK

•

W

As shown in Eq. (2), the leakage current /LEAK must be suppressed as much as possible (to less than sub-fA/cell) to ensure good data retention characteristics. The leakage / LEA K originates mainly from the GIDL, subthreshold current, and junction leakage of the CAT. In recent years, CAT structures have successfully evolved from a planar-channel to a recessed-channel (RCAT), and later to a metal buried-gate (BCAT) structure that eventually will evolve to a vertical-channel (VCAT) structure satisfying the / 0 N/4EAK ~1010 ratio requirement. Figure 2 shows the evolution of the cell array transistor through the years. The sensing signal voltage ДРщ, can also be improved by reducing CBLVertical scaling of the bit line (BL) electrodes with lower resistivity metal and gap filling with lower-к dielectrics between BLs are the key points in reducing C B L and thereby enhancing AVBb. Demands for higher speed devices with reduced power consumption require more stringent processes and technological breakthroughs in transistors. Aggressive scaling employing higher-к gate oxide with multi-thickness, ultrashallow junctions with carefully controlled thermal activation, as well as novel mobility-boosting technologies based on strain effects are possible candidates for the enhancement of device performance and power reduction. ~90nmArF

//

~ 40 nm ArF-i (DPT)

//

< 20 nm EUV

Figure 2. Key technology evolution of DRAM from 90 nm to sub-20 nm: lithography and critical size (top), cell capacitor (middle), and cell array transistor (bottom).

Technology Innovation, Reshaping the Microelectronics Industry

7

With the optimization of the 3D cell storage capacitor and array transistor structures, DRAM is anticipated to downscale to the sub-10nm regime. Nevertheless, in the future, patterning technology, e.g. lithography and etching, will become critical. Currently, the major concern is the productivity of such technologies: i.e. extreme ultraviolet (EUV) and/or double patterning lithography, and high aspect ratio capacitor hole etching. The slow progress of EUVL technology will result in the need for expensive double or quadruple patterning technologies (DPT or QPT) for several critical layers at the 22 nm node. The rapid increase in fabrication costs, as well as overlay and uniformity issues are becoming major challenges due to the drastic increase in the number of process steps. Beyond sub-2 Onm NAND flash The conventional floating-gate (FG) NAND flash cell technology is currently at the 20 nm node.8 Moreover, sub-20nm cells using QPT have also been demonstrated9 using the word line (WL) air-gap technology in order to overcome coupling interference. However, as device technology enters the sub-20 nm region, cell-to-cell coupling interference, the numbers of stored electrons, WL-toWL breakdown, endurance and data retention are becoming major challenges.10 Although circuit technologies including parallel programming, shadow programming and extended ECC (error correcting circuit) were successful in overcoming the cell-to-cell coupling down to the 20 nm node, they would not be effective in overcoming issues for beyond the 20 nm node planar NAND flash because coupling interference ratio is inversely proportional to the design rale for planar structures. Thus, as the design rale decreases, the coupling ratio will further increase, reaching the allowed design limit, which is about 5 at around 20 nm as shown in Fig. 3. •

However, a 3D NAND flash at the 10 nm node can be designed in such a way that the coupling interference ratio is at the same level as that of a 60 nm planar cell. The coupling interference ratio of the 3D vertical NAND (VNAND) remains far below the critical design limit even beyond the sub-10 nm region, as shown in Fig. 3. This is because the bit line coupling interference is almost eliminated by the gate-all-around (GAA) structure, and the WL-to-WL coupling interference can be reduced by the increased spacing between WLs. Among several proposed 3D vertical structures, the terabit CAT (TCAT) is thought to be the most promising. It is based on a damascened metal gate and a TANOS (TiN-AlO-nitride-oxide-Si) cell. The metal gate in this structure could have a wide programming window because TANOS has a better erase speed than SONOS (Si-oxide-nitride-oxide-Si).11 Furthermore, by shrinking the diameter of the channel hole, erase speed can be further improved as the electric field in the tunnel oxide is enhanced. The TCAT erase scheme is the same as that of planar cells, so that it can be compatible with the conventional NAND flash architecture. Furthermore, it has a better array distribution uniformity by a factor of two and ten times the endurance of the 20 nm node planar technology.5

8

Future Trends in Microelectronics

Figure 3. Gate-all-around charge trap flash (CTF) structure (bottom left) and 3D VNAND with gate-all-around CTF structure (top left). The coupling interference ratio of 3D VNAND is much lower than in planar devices. The coupling interference ratio defines the charge build-up in cell while an adjacent cell is programming, and should not exceed the allowed design limit of ~ 5 (dashed horizontal line). Further research will be necessary in order to achieve the required read margin and write speeds, which could be negatively affected by a low mobility and high leakage of channel poly-Si. To reduce the leakage current, the poly-Si has to be thin enough to be fully depleted, and its grain size has to be enlarged in order for its performance to be comparable to that of the single-crystal Si. Process technologies, such as high aspect ratio channel-hole formation, bowing and leaning free stacks, will also require further research. STT-MRA M as apost-DRA M technology As the push for smaller DRAM cells faces formidable technological and economical challenges, a number of alternative post-DRAM devices are under consideration. Because of the severe charge leakage for downscaled storage elements, non-charge-based memory devices seem quite promising. One such device is the spin transfer torque magnetoresistive random access memory (STTMRAM), which has a high operation speed, superior endurance and process compatibility with existing Si technology.12'13'14 The STT-MRAM technology utilizes magnetic tunnel junction (MTJ) tunneling for resistive storage as shown in Fig. 4, where MgO is widely used as the magnetic tunnel barrier. It can reach a similar area density as DRAM, since a cell consists of a single transistor as a selection device and a single MTJ as a storage element. The key challenge in STT-MRAM is reducing the operating current to switch the spin states. The required currents to switch circular-shaped MTJ cells have been estimated to lie in the Jc = 1-I0xl0 6 A/cm2 range, as plotted in Fig. 5. The

•

Technology Innovation, Reshaping the Microelectronics Industry

9

Figure 4. STT-MRAM structure where the magnetic tunnel junction (MTJ) exhibits two different resistance states depending on the relative spin orientation of the MTJ layers.

various drive currents of underlying transistors at each technology node are also shown. In order to successfully write the STT-MRAM cell, smaller J c and/or larger transistor current drive will be required.15 If we assume transistor current drive of -500 uA/um gate width (lower solid line in Fig. 6), Jc will have to be reduced below 3xl06 A/cm2 for STT-MRAM, which is extremely difficult. Thus, we need materials and structures that would require lower currents to switch the spin state.

Figure 5. Current required to switch the spin state of the MTJ cell as a function of the technology node. Lines with symbols show the switching currents depending on the critical current density Jc required to switch the state of the MTJ cell. Solid lines show the available transistor current drive /0N at each technology node.

Future Trends in Microelectronics

10

The critical current density Jc required to switch the magnetic moment of the in-plane free layer is given by the following equation:

Jc = ( y )

С)(ЯКГ

+ nMs2V),

(3)

where a, -n, HK, V, and Ms are the magnetic damping constant, spin torque efficiency, magnetic anisotropy constant, volume of the free layer, and the saturation magnetization, respectively. The nMs2V term in Eq. (3) arises from the surface demagnetization energy due to the out-of-plane precession of the in-plane magnetization during the switchmg. Since this term is absent in the perpendicular magnetic structure, switchmg current reduction will be possible by using materials with perpendicular magnetic anisotropy. To further reduce the critical current density, a higher spin torque efficiency and a smaller damping constant for the perpendicular free layer are needed. However, reduction of HKV will cause data retention problems. As the small storage volume may be vulnerable to random thermal noise, the usage of perpendicular magnetic materials with high crystalline or interfacial anisotropy can improve the data retention.16'17,18 Otherwise, for in-plane magnetic anisotropy, thermal stability can be ensured through a 3D MTJ cell structure, which retains a large free-layer volume without an increased cell footprint by folding the free layer to a special geometry, as shown in Fig. 6. The STT-MRAM will be the most promising candidate around the 12 nm technology node, or about 2018. In addition to reducing the switching current of the MTJs, etching damage and thermal stability of the MgO tunnel barrier also need to be improved in order to obtain adequate retention characteristics.

Figure 6. Two MTJ cell structures with equivalent thermal noise: (left) conventional planar MTJ cell with a long 3Ffootprint, where Fis the minimum feature size; (right) three-dimensional MTJ cell structure with IFfootprint that is robust against thermal noise because of its larger free-layer ratio.

Technology Innovation, Reshaping the Microelectronics Industry

11

ReRA M as apost-NA ND technology Post-NAND devices are also being studied; one proposed technology is the resistive RAM (ReRAM) that makes use of resistance switching phenomena with structural simplicity. ReRAM is characterized by a resistive material acting as the memory element with a control element acting as the switch. Among the currently known material systems, tantalum oxide is the most promising candidate for the future nonvolatile ReRAM. In a Ta205/TaOx bi-layer structure, 1012 cycle endurance and ten-year retention time with fast program and erase pulses on the order of ~10 ns have been reported.19 The resistive switching characteristics and structure of this device are shown in Fig. 7. The resistance switching in this type of ReRAM occurs in the Ta205 layer via a redox reaction. But, the superior cell performance comes from the •

Figure 7. Resistive switching characteristics and structure of the Ta205/TaOx device: (a) typical bipolar dc l-V switching operation of a 30 nm cell (SEM in inset) from high to low resistance state (HRS to LRS); (b) schematic of the TaOx device consisting of a thin Ta 2 0 5 insulating layer and a TaOx base layer. Resistive switching is due to the movement of internal oxygen ions or vacancies.

12

Future Trends in Microelectronics

presence of a TaOx layer that plays two key roles. First, it is able to hold a high density of oxygen ions as an oxygen reservoir that mitigates the oxygen ion depletion that causes reset-switching failures. Second, the TaOx layer limits the set switching with a finite current compliance, thereby preventing overshoot and hard breakdown during the set switching. ReRAM devices can be operated in the metal-insulator-metal (MIM) configuration that can be integrated into a crossbar array. In this case, the device footprint can be reduced to 4F 2 ; and if stacked into multi-layers, the feature size becomes (41ri)!*2,where n is the number of the stacked layers, as shown in Fig. 8. However, the crossbar structure always has a signal disturbance problem due to unwanted stray currents from the neighboring cross-points. Thus, it needs a proper selection device, such as a diode or a threshold switch, serially connected with MIM storage element. As of this moment, it is critical to find an appropriate and reliable selection device and to integrate it with the ReRAM material in a crossbar structure. Another feasible approach is a vertical ReRAM (VReRAM) structure (equivalent to 1T-«R structure), which has a similar layout to the 3D vertical NAND of Fig. 3. In the П-nR, the selection device must be integrated in the ReRAM cell because multiple cells are connected to one transistor. Because the role of the selection device is to filter out the stray current from the n2 ReRAM cells, the specification of selection device for the lT-rcR structure is less tight than that of the crossbar structure. However, in the VReRAM structure, the hole sizes must be to be large enough to accommodate ReRAM cell materials, such as selection, resistive switching and base materials as well as the top electrode. This may keep VReRAM from further scaling. When considering the technological issues of VReRAM and crossbar ReRAM, further research on self-rectifying ReRAM materials that would not require a selection device is urgently needed.

Figure 8. Cross-point ReRAM structure, where a resistive material acts as the memory element.

Technology Innovation, Reshaping the Microelectronics Industry

13

3. Mainstream silicon technology: Logic In order to improve the performance of Si CMOS, logic devices have been continuously downscaled and integrated over the past 40 years, as shown in Fig. 9.20'21 However, as logic device size downscales into the nanometer regime, significant innovation in device structures and new materials have to be introduced in order to maintain the traditional rate of performance enhancement of past decades: e.g. Cu/low-к dielectric at the 120 nm technology node; SiGe source/drain for the 65 nm node; and metal electrode/high-к dielectric gate stacks replacing poly-Si/Si02 gate stacks at the 45 nm node. The conventional planar logic structure will continue to scale down to the 20 nm node through optimizing the HK/MG (high-K/metal gate) technology, introduced at the 32 nm node. However, below 20 nm, equivalent oxide thickness (EOT) will decrease sharply because in order to suppress the short channel effects (SCEs), channel doping concentration has to be increased rapidly. The EOT constraints can be relaxed if a multi-gate structure or fin-FET is used to replace planar layout. Recently, due to the rapid growth of mobile applications, low power consumption has joined speed and performance as a key metric. Power consumption P in logic devices is dominated by VDD as follows: P ~ Cox VvJf [active] + /0FF VDD [standby],

(4)

Figure 9. Logic device downscaling deep into the nanometer regime, highlighting new device structures and materials, such as metal electrode/high-к dielectric gate stacks replacing poly-Si/Si02 gate stacks at 45 nm; high-K/metal gate at 32 through 20 nm; and fin-FETs at the 14 nm node.

Future Trends in Microelectronics

14

where C 0 xis the capacitance, VDD is the input voltage, / 0 FF is the off current a n d / is the frequency. There are three approaches for reducing VVD and / 0FF for low power mobile applications: (i) alternative transistor architectures, such as 3D or GAA layout for better electrostatic control; (ii) high mobility materials for alternative channels; and (iii) alternative devices with low subthreshold swing SS < 60 mV/dec. Of the three approaches, 3D devices with various performance boosting schemes are the furthest along, with fin-FETs being one of the best candidates for the next generation logic. High mobility III-V or Ge channel materials are one of the promising directions for performance improvement as well as reducing power consumption. Even though there are many challenges to the 10 nm technology node or beyond, the improvement of gate stack/channel interface properties and introduction of heterogeneous process integration for new channel materials with higher electron and hole mobility should enable aggressive F D D scaling, thereby reducing power consumption. One of the options to overcome thermal limit of sub-threshold slope below 60 mV/dec in a conventional CMOS is the tunneling FET (TFET). Tunneling FETs have been proposed for low VDv operation below 0.5 V,22 and would greatly benefit from low (effective) band gap energy, increasing the probability for tunneling. As a result, III-V or SiGe/Ge heterojunctions will possibly be the most effective materials for TFETs. Fin-FET devices In the 2011 ITRS roadmap, planar devices disappear below the LG = 20 nm gate length due to short channel effects. As a solution for LG scaling beyond 20 nm, ITRS had considered the fully-depleted SOI (FD-SOI) or multi-gate FETs (MuGFETs), including fin-FET devices. Furthermore, FD-SOI will also likely disappear below LG = 15 nm, leaving MuGFETs as the only viable technology. These predictions arise mainly from the impact of SCEs, such as drain-induced barrier lowering (DIBL) illustrated in Fig. 10. Fully-depleted SOI can potentially improve DIBL, but cannot outperform fin-FETs because of the limited improvement in the junction depth. The influence of the drain electric field on the channel region, which is the physical mechanism underpinning SCEs, can be understood through the "natural length" of the device, expressed as X in the following equation:23 •

H- t s i i o x i

(5)

where eSi, eox> 'SÍJ fox are the permittivities and thicknesses of silicon and oxide, respectively. By moving from bulk to the fin-FET structure, iSi can be markedly reduced. Fin-FETs will be the best choice for minimizing the natural length.

Technology Innovation, Reshaping the Microelectronics Industry

15

Figure 10. Drain-induced barrier lowering (DIBL) vs. gate length /_G of different transistor structures (fin-FET, FD-SOI FET, and bulk FET), calculated with the MASTAR simulator.24

Another fin-FET advantage is the improved channel resistance due to volume inversion. Figure 11 shows the volume inversion effect in the double gate geometry.24 The electron concentration increases not at the surface but near the center region, which results in lower scattering. Due to the double-gate geometry, the vertical electric field near the center of a fin-FET is much lower than in the channel of a planar FET at the same imposed VG. The higher population in the center with relatively lower electrical field causes the channel resistance to decrease, which improves performance as the fin-FET is downscaled. Thus, the fin-FET performance will improve down to ?Si = 5-7 nm, see Fig. 11,25'26 Tri-gated fin-FETs exhibit corner effects. Due to the higher electric field at the fin corner, strong inversion occurs faster than at the fin side. As a result, higher

Figure 11. Volume inversion effect and mobility vs. fin thickness: (a) electron concentration increases as the depth in silicon decreases; (b) volume inversion occurs only at a certain fin thickness (represented as silicon film thickness in the graph).

16

Future Trends in Microelectronics

carrier concentration can be achieved at a lower VT. This corner effect improves the performance at the top of the fin, yielding an improved overall performance. The third advantage of fin-FETs derives from their immunity to random dopant fluctuations, because the fin-FET channel can be nearly undoped.27 However, going from planar FETs to fin-FETs also runs into challenges. A 3D fin-FET is prone to severe variability, in particular work function variability owing to the metal gram boundaries and thickness variations. Also, the sidewall quality of the fin-FET, side orientation and degree of top corner rounding, as well as the uniformity of the interface layer thickness around the fin structure will become variability issues from a structural point of view. Another challenge faced by fin-FETs is source/drain resistance. Normally, as the fin size shrinks, source/drain resistance increases rapidly due to reduced contact area. So the performance bottleneck in fin-FET scaling comes mainly from the source/drain resistance, as shown in Fig. 12. The third challenge is the lack of multi- F T operation. As fin size decreases, the fin-FET Vj can be tuned only slightly by "halo dopant effect", which means more doping near the source and drain to reduce the size of the depletion regions in the vicinity of these junctions: F T = ^ s + 2 # + ( g D - e S s ) / C b x , 2D = eNAW¥m/2 ,

(6)

where 0MS is the work function of the gate, ф? is the difference between £ F and the intrinsic Fermi level, Q0 is the depletion charge, Qss is the surface charge, C 0 x is the oxide capacitance, H^FIN is the width of the fin, and NA is the doping density. As shown by Eq. (6), the threshold voltage and charge depletion in fin-FETs are defined by the fin width.

Figure 12. Parasitic resistance, (a) Resistance vs. technology node. As the technology node scales down, parasitic resistances (source/drain resistance, gate resistance) increase, while channel resistance decreases because of the increase ,28 in channel mobility, (b) Contribution of the various resistance components to the 29 total.

Technology Innovation, Reshaping the Microelectronics Industry

17

If the fm width is small, the QD value becomes small, so the sensitivity of VT to channel doping is reduced. Therefore, overall VT is mainly determined by the metal workfunction and is difficult to control compared to planar devices. Hence, other approaches for achieving multi-FT operation are needed, such as multi-finsize structures and multi-workfunction material processes. Even though fin-FETs will be extended to the 10 nm node, new materials and new structures may be necessary for sub-10 nm nodes. Advanced channel materials for logic As previously mentioned, high mobility III-V or Ge channel materials are promising candidates for improving the performance and reducing power consumption. New channel materials that enhance the electron and hole mobilities enable power reduction by aggressively scaling the VD^. Many III-V compound semiconductors have lower electron effective masses than Si, leading to a higher injection velocity into the channel.30 Thus, III-V channel transistors can have higher / 0 N than Si NMOS at lower operating voltages.31 There has been rapid progress in III-V channel transistors and, recently, InGaAs quantum well fin-FET32 and a GAA structure using the same materials33 have shown promising results for logic applications. For III-V materials to be used with the silicon platform, defect-free III-V on Si is necessary, which is extremely difficult to achieve due to the lattice mismatch. One possible approach is the selective area growth (SAG) of lattice-mismatched materials inside trenches by MOCVD. Threading dislocations are trapped at the bottom of the trench, yielding a high-quality top layer, as shown in Fig. 13. The second technical issue comes from the lack of III-V PMOS; but there has been recent interest in group III-Sb materials, such as InGaSb, for PMOS applications. Additionally, side-by-side integration of III-V NMOS and PMOS transistors on a Si substrate needs to be developed. Another approach for the replacement of the PMOS is using a Ge channel. •

Figure 13. Cross-sectional (a) SEM and (b) TEM images of ~1.9 um thick epitaxial InP layer grown on a patterned Si (001) wafer. As can be seen in the TEM image, defect-free InP crystal can be grown in the Si hole pattern.

18

Future Trends in Microelectronics

Figure 14. Ill-V/Ge hybrid CMOS on Si.

The preparation of a hybrid substrate for NMOS and PMOS transistors is a major challenge. Selective area growth of III-V for NMOS and III-Sb/Ge for PMOS could be a feasible solution - a possible structure is shown in Fig. 14. Low subthresholdswing devices To achieve a high / 0 N at low VDD, subthreshold swing (SS) should also be reduced, which is very critical for low power consumption. Tunneling FETs (TFETs) can be a possible solution for low SS, especially tunneling FET based on III-V materials.22 The subthreshold swing of a TFET can be lower than 60 mV/dec because its operation mechanism is band to band tunneling at a reverse-biased •

Figure 15. (a) Principles of TFET operation, with yellow arrows indicating interband tunneling. Gate bias enhances the tunneling probability by lowering the barrier, (b) Bird's eye view of the л-type GAA nanowire TFET. (c) Cross sectional view of ntype GAA nanowire TFET.

Technology Innovation, Reshaping the Microelectronics Industry

19

source-channel pn junction. Figure 15(a) illustrates TFET operation in terms of band diagram modifications by VQ\ the tunneling length decreases with Vainduced band lowering, which leads to higher tunneling current. The main issue with TFETs is how to increase the / 0 N to > 100 uA/um while retaining low SS. In order to increase / 0 N, recent TFET research has focused on III-V materials because a narrow band gap is preferred for increasing the tunneling probability. Also, to increase the gate controllability and / 0 N, GAA nanowire TFETs have attracted much attention. This structure allows a better control of SS and / 0 FF, which should be as low as possible.34 Schematic illustration of a GAA и-type nanowire TFET is shown in Fig. 15(b) and (c). Another advanced material, graphene, is also being considered as a prime candidate as a FET channel material because of its high mobility.35 However, graphene FETs suffer from a large / 0 FF due to a lack of bandgap, which is key in turning the device off and on by creating an electrostatic potential between the source and the drain. Therefore, in order for graphene to replace silicon in a transistor, generating a bandgap in graphene has been a top priority.36'37'38 So far, there has been a trade-off between the band gap and the high mobility; thus, generating a bandgap without sacrificing the mobility remains the greatest challenge for graphene.

Figure 16. Barrier modulation of graphene barrister39 and graphene tunneling transistor.40 Graphene barrister: (a) 3D structure; (b) ON state, showing Schottky barrier between graphene and silicon determined by the difference between graphene EF and silicon E c ; (c) OFF state. Graphene tunneling transistor: (d) schematic; (e) ON state, with tunneling barrier height set by difference between graphene EF and Ec of barrier insulator (Fowler-Nordheim tunneling assumed); conduction band minimum of tunneling insulator; (f) OFF state. Tunneling barrier is increased by the modulated workfunction of graphene.40

Future Trends in Microelectronics

20

Recently, two new structures have been suggested to resolve this issue: graphene barrister39 and graphene tunneling transistor.40 In the former structure, current is controlled by modulating the Schottky barrier between graphene and the semiconductor, as shown in Figs. 16(b) and (c). In the latter structure, current is controlled by modulating the Fowler-Nordheim tunneling barrier between the graphene and the insulator, as shown in Figs. 16(e) and (f). Both structures rely on a unique property of graphene: workfunction modulation. Since graphene has a low density of states near the Dirac point, its workfunction can be modulated by changing the carrier density. Interestingly, when Schottky (tunneling) barrier is formed between graphene and the semiconductor (insulator), the barrier height can be changed by the work function modulation, since the barrier height is determined by the difference between the £ F of graphene and conduction band minimum of semiconductor (insulator). For instance, if graphene's workfunction increases by, say, 0.35 eV, the Schottky barrier reduces by the same amount to align the Fermi levels on both sides (compare Figs. 16(b) and (c)). The off-state achieved this way could eventually enable graphene logic applications. While MOSFET-type transistor structures are not an obvious fit for graphene, graphene barrister or tunneling transistor could be candidates for logic applications. But compared to III-V materials, graphene is still in its early stages for logic and requires further development, especially with regard to low-defect graphene growth and process integration on silicon. 4.

Emerging computing architectures

The fundamental underlying design of general-purpose computing systems has remained unchanged for decades. However, with the introduction of many-core CPUs and new memory devices, significant redesign of computing architecture is inevitable. In order to reduce power consumption, current systems have to be designed in such a way as to minimize wasted cycles and bandwidth for nonessential computing and data movement. The future may bring powerful computing architectures that mimic the brain, more efficient and capable of processing adaptive tasks. Other computing architectures will become possible thanks to the rapid evolution of emerging memories, such as MRAM and ReRAM. These memories, in combination with logic devices, would allow flexibility in circuit design and faster hardware revisions or updates, which would lead to a reduced hardware development time. Neuromorphic devices Neuromorphic systems refer to analog/digital VLSI and software programs that mimic neural systems for perception, motor control, sensory processing, and decision making. Neuromorphic VLSI chips mostly use an integrate-and-fire (IF) spiking neuron model. Neuromorphic IF neurons compute from inputs in the subthreshold region (on the order of mV) and emit sparse high-voltage pulses (on the •

Technology Innovation, Reshaping the Microelectronics Industry

21

order of volts) for cell-to-cell communication, so that low-power consumption can be achieved. An example of a neuromorphic visual system is shown in Fig. 17. However, subthreshold CMOS circuits are plagued by unavoidable transistor Vj variability due to imperfections and temperature variations in the fabrication process.41 Typical CMOS KT may vary by ±20 mV, causing large errors in subthreshold computation of silicon neurons. Solving this mismatch problem or detouring around it will be a major challenge for achieving massively integrated silicon neuron chips. Wiring large numbers of neurons on a 2D wafer faces higher constraints in comparison to 3D connections of a real brain. It is inefficient to assign independent paths to all connection; e.g., an N neuron chip requires N2 wires to be fully connected. To resolve this problem, most neuromorphic chips adopt a digital bus mechanism, such as address event representation (AER) based on an asynchronous digital pulse-based encoding method.42 Its performance is dependent on the clock speed of connected digital blocks. Another challenge is the implementation of a synapse and its updating. In terms of neuroscience, a synapse is a biological structure that passes an electrical or chemical signal from one neuron to another. The synaptic weight can change over time, so that our brain learns. A fully-interconnected network with N neurons also needs N2 synapses. Therefore, implementation of synapses is more critical for a chip than of neurons. Since many transistors are necessary to form a digital synapse, some researchers are considering the use of memristor devices.43 In the future, neuromorphic chip industry is expected to start growing in lowpower and high-performance sensory preprocessors, and will expand to include cognitive processors that can be used by robots or artificially intelligent computers.

Figure 17. Neuromorphic visual system: (left) biological, (right) electronic.

22

Future Trends in Microelectronics

Recd-tim e hybrid reconfigurable logic (RHRL) Reconfigurable logic (RL) can provide significant flexibility in circuit design, enabling hardware revisions or updates, as well as reduction of hardware development times, all of which is very attractive to many hardware and software engineers. Reconfigurable logic can also reduce the software overhead in the processing units through proper hardware organization. However, device footprint, power consumption and slow operating speeds may outweigh the above benefits. As a result, RL is barely being noticeable in the current logic market, where the major players are ASICs or ASSPs. A typical RL chip, for instance, is the Virtex-7 from Xilinx with about 2 million logic cells. However, due to heavy area/power/performance overheads, its applications have been limited to software field tests and/or low production volume niches. The disadvantage of FPGA is that it takes over a second to access the operational codes stored in an external flash or ROM. This hinders real-time reconfigurability. To increase the programming speed, RL architectures with embedded nonvolatile memories are being considered, i.e. real-time hybrid reconfigurable logic (RHRL). The RHRL makes use of high-speed, high-density nonvolatile memory, such as ReRAM and MRAM, that can be integrated with standard CMOS processes. Figure 18(b) shows an example of an RHRL circuit that dispenses with the bulky look-up tables and interconnect circuits needed in SRAM-based reconfigurable logic, shown in Fig. 18(a). •

Figure 18. Examples of reconfigurable logic, (a) SRAM-based reconfigurable logic, requiring bulky SRAM-based look-up tables and interconnect circuits, as well as external ROM or flash memory, (b) MRAM- or ReRAM-based real-time hybrid reconfigurable logic (RHRL) with embedded memory, which simplifies the system.

Technology Innovation, Reshaping the Microelectronics Industry

23

By using these nonvolatile memories, additional communication with an external flash or ROM becomes unnecessary, so that RHRL accesses the new operating codes within 1~2 clock cycles, i.e. within 10 ns. A second advantage of RHRL comes from low standby current. Standby power consumption can be lowered to almost a tenth of the conventional RL due to the nonvolatile nature of the memories. Finally, RHRL logic chip area, consisting of ReRAM and MRAM, can be reduced 2-3 times compared to conventional RL. Due to these benefits, RHRL using MRAM or ReRAM as logic setters should allow much wider functionality and will likely find usage in multi-standard applications, e.g. radiofrequency communications in 3G, 4G, Wi-Fi, etc. 5.

Silicon technology in the field of energy

Considering how energy has enriched our lives, it is no surprise that energy efficiency is a major topic of interest. The world's primary energy consumption is projected to grow by 1.6% per annum, reaching about 17 billion tons of equivalent oil by 2030.44 Electricity will comprise roughly 40% of this energy, which requires almost doubling the electricity generation capability in the next 20 years. This is not an easy task, especially given environmental concerns, radiation safety, etc. Thus, the current interest in renewable energy is well justified. A renewable energy platform that is derived from silicon technologies is the solar cell, which makes use of a perpetual resource to obtain electricity. Furthermore, silicon technology is bringing innovation to power electronics, which is the key component in renewable energy systems. However, more important than energy generation is energy saving. The U.S. Energy Information Administration estimated that in 2010, about 13% of the total U.S. electricity was spent in residential and commercial sectors. As a drastic measure, countries are banning inefficient but inexpensive incandescent lighting, which is accelerating the adoption of solid-state lighting based on light emitting diodes (LEDs). Current solid-state lighting is still expensive compared to fluorescent lighting, but it will soon become competitive as the LED technology evolves, in part aided by silicon technology. Solar cells The average growth rate of the solar cell industry has been over 25% in recent years. Currently, crystalline Si solar cells hold about 90% of the market, with the rest divided by thin film technologies based on CdTe, CIGS(CuIn1.xGaxSe2), or amorphous Si. For crystalline Si solar cells, due to their structural simplicity, screen printing has been adopted and has become industry standard with its fair efficiency and simple processing, enabling the facility manufacturers to provide turn-key systems. The current cell and module efficiencies are 16-21% and 13-18%, respectively. The highest demonstrated cell efficiency is 24.7% with a passivated emitter rear local (PERL) contact structure by the University of New South Wales,45 but PERL •

24

Future Trends in Microelectronics

structures have not been commercialized to date due to the high wafer and process cost. In the commercial arena, interdigitated back contact (IBC) technology has attracted much research effort worldwide, demonstrating a best cell efficiency of 24.2% and module efficiency of 21.2%.46 The IBC structure has both/»- and ntype contacts on the backside, reducing optical reflection losses due to the metallic contact grid. However, it also suffers from high processing costs and expensive ntype CZ wafers, which limit its applicability to high-efficiency market sectors. In order to reduce costs, modifications of cell structure and materials have been tried. A promising low-cost solution is the interdigitated front contact (IFC) structure, which adopts several advanced semiconductor technologies.47 Also,

Figure 19. Crystalline Si solar cell structures: (a) passivated emitter rear local (PERL) structure; (b) interdigitated back contact (IBC) structure; and (c) interdigitated front contact (IFC) structure.

Technology Innovation, Reshaping the Microelectronics Industry

25

multi-crystalline wafers lower manufacturing cost even though the efficiency suffers from recombination losses at the grain boundaries. Figure 19 shows the schematic diagrams of PERL, IBC and IFC solar cells. Although in theory Si solar cells can reach 29.3% efficiency, the practical efficiency limit is expected to be 26%. Efficiency trends of some solar cell technologies are plotted in Fig. 20. As the efficiency approaches the singlejunction efficiency limit of 26%, efficiency improvement is expected to slow down and saturate because additional processes to improve efficiency incur additional costs. There are various approaches to overcome the single junction limit, relying on quantum dots, intermediate band designs, and multiple junctions. Approaches using quantum dots and intermediate bands are at the stage of device design. On the other hand, the multi-junction approach is considered more promising for mass production. As a practical solution in the multi-junction approaches, double junction structure with the addition of Ge underneath Si48 has been proposed to absorb longer wavelengths than 1100 nm in the Ge junction. Another type of solar cell is the thin film solar cell. The most representative ones are CdTe, CIGS (CuIn,.xGaxSe2) and amorphous Si, which have the advantage of low materials cost. The efficiency is about 6%, lower than that of the crystalline Si. Efficiency losses in thin film solar cells mostly come from recombination at the grain boundaries. The highest reported efficiencies in CdTe and CIGS laboratory devices are 17.3% and 20.3%, respectively, and CIGS technology is gaining momentum to lead the thin film market. The most urgent task for solar cell technology is resolving economic issues, such as lowering the investment cost and reaching grid parity through enhanced efficiency and reduced material costs. Despite of these challenges, the solar cell market will continue to grow because of its inherently clean nature.

Figure 20. Mono-crystalline Si, multi-crystalline Si and thin film solar cell efficiency trend curves.

26 6.

Future Trends in Microelectronics Silicon technology and nitride devices

Solid-state lighting is a strong driving force for the expansion of the LED market in the near future. To take the initiative in leading this expanding market and to overcome the still high cost barrier, manufacturing costs must be reduced. One possibility is the use of large wafers. Although sapphire has been the industry's substrate of choice for nitride epitaxy, large sapphire wafers are problematic because of voids during growth and difficulties in slicing the ingot. Silicon 8" and 12" wafers are the most promising alternative in terms of cost and size. The epitaxial growth of crack-free high crystalline quality GaN on Si has not been achieved yet due to a high lattice and thermal expansion mismatch between Si and GaN. The lattice mismatch is almost 17%, which leads to large dislocation densities in the GaN epitaxial layers. In addition, the thermal expansion mismatch between GaN and Si is 54%, which induces a tensile stress during the post-growth cooling, and eventually generates cracks in the GaN layers when the amount of the tensile stress surpasses the fracture toughness of the film.49 Aside from epitaxy challenges, Si absorbs light, so for high-power LEDs the Si substrate must be removed. Furthermore, the bowing of Si wafers must be minimized during both epitaxy and device fabrication, as shown in Fig. 21. Recently, a robust «-type GaN template on 8" Si substrate has been reported, with both a low dislocation density and a thick crack-free film. This GaN template consists of A1N, which acts as a nucleation layer and, at the same time, as a barrier layer of the Ga-Si eutectic reaction. The transition layer consists of AlGaN and a unique epitaxial structure composed of dislocation-reduction and stresscompensating layers. This structure allowed the growth of a 3.5 um thick Si-doped GaN layer with Nn = 4.5xl018 cm"3 and without any cracks. The FWHM values of GaN (0002) and (10-12) co-rocking curves were 220 and 320 arcsecs, respectively. The dislocation densities were measured with an AFM to be about 2-3x108/cm2.50 A cross-sectional view of the grown LED structure is shown in Fig. 22.

Figure 21. Key challenges for high-efficiency GaN LEDs on Si substrates.

Technology Innovation, Reshaping the Microelectronics Industry

27

Figure 22. A cross-sectional SEM image of a typical LED structure (right) on top of /7-GaN template (left), which is grown on a Si substrate.

By using GaN on Si technology, LED output powers as high as -500 mW have been achieved without phosphor encapsulation. Low reverse leakage current and an operating voltage comparable to sapphire-based LEDs are also possible. Gallium nitride LEDs on large diameter silicon wafers will soon reach the initial stage of mass production. For general-purpose solid-state lighting applications, further cost reduction will be needed, with wafer-level packaging, wafer-level good die selection and phosphor-free white LEDs as topics of further research. Another application of nitride device integration is power devices that promise high-voltage components with better performance in terms of static and dynamic power loss, current density, operating voltage, and operating temperatures. The trade-off relationship between the specific on-resistance R0N and the breakdown voltage F B R in semiconductor materials is expressed as follows: ^0N = 4F BR 2 /eM;cR\

(7)

where e is the specific dielectric constant, u„ is the electron mobility, and £ C R the critical electric field of the material. A material having high ECR and high ^ is needed in order to obtain both low Í? 0 N and high VBR. Wide bandgap materials like GaN have around 3 times higher EG and 10 times higher ECR than Si. So they can have specific on-resistance .RON two orders of magnitude lower than Si at the same breakdown voltage, with the added advantage of lower intrinsic carrier density and hence higher-temperature operation. While high-quality GaN grown directly on silicon has already been demonstrated for LEDs, as described above, another key parameter must be considered for high-power applications: the breakdown voltage of buffer layers. Recently, 8" AlGaN/GaN high electron mobility transistors (HEMTs) on Si substrates have been reported with buffer F BR of 1.7 kV by controlling the growth temperature, V/III ratio and TMGa (trimethylgallium) flow rates. The maximum £ C R of the buffer structure is 1.36 MV/cm.51

28

Future Trends in Microelectronics

The realization of stable normally-off operation has also been one of the major challenges for this technology's commercialization. In order to achieve enhancement-mode GaN power devices, depletion of two-dimensional electron gas (2DEG) channels at the AlGaN/GaN interface is required. Various technologies, like MOS-HEMT, />-(Al)GaN gate stack, fluorine plasma treatment of AlGaN barrier, and GaN MOSFET have been proposed.52'53'54,55 Recently, a GaN HEMT with a p-GaN gate stack on Si substrate with record figures of merit has been reported.56 This device had a threshold voltage VT of 3 V, breakdown voltage of 1600 V, /?ON of 2.9 míícm2, coming very close to 4H-SÍC material limit in the onresistance vs. breakdown voltage trade-off, as shown in Fig. 23. With Au-free fully Si CMOS compatible process, p-GaN gate HEMTs were successfully fabricated on 8" Si wafers and median values of VBD and F T of the packaged 10 A devices were 900 V and 3.3 V, respectively.

Figure 23. (a) Specific on-resistance vs. device breakdown voltage of normally-off GaN HEMTs on Si in comparison with Si IGBT. The star represents the most recent p-GaN HEMT devices results close to 4H-SiC material limit, (b) Device breakdown characteristics on 8" Si wafer (breakdown VBfí = 900 V at 250 uA).

Technology Innovation, Reshaping the Microelectronics Industry

29

Figure 24. GaN monolithic inverter IC on Si (from Ref. 53).

In the near future, further advances in GaN-on-Si based power devices are expected, including on-wafer integration of GaN FET and Si CMOS or GaN monolithic integration ICs on Si (see Fig. 24) for highly efficient and cost-effective next generation power-conversion solutions. 7.

Silicon technology and photonics

Future high-performance exascale systems will naturally evolve into multi-cores that require high-speed and energy-efficient interconnects. This will inevitably bring forth the era of Si-based photonics. A good example of the convergence of silicon technology and photonics would be optical interconnects. To date, optical interconnect technology has been focused on overseas communications, enterprise networks and rack-to-rack; but it will quickly expand to include board-to-board applications as well. As technology advances, it will further extend to the chip-to-chip level, enabled by Si photonics integration. Furthermore, Si CMOS-integrated optical interconnects, in combination with multi-core CPU technology, would bring immediate benefits to consumers who expect more vivid and realistic images in 3D and holography, which require exascale computing performance handling vast amounts of data at high speed. Optical interconnects The advantages of optical interconnects lie in low power consumption and high speed over long distances; eventually optical links could replace their electrical counterparts for short distances also. The most imminent device based on Si CMOS-integrated optical interconnect will be an optically connected DRAM to overcome the bandwidth limitations on DRAM generations beyond DDR5, as shown in Fig. 25.57 Optical interconnects consist of individual active components, such as Si photonic transmitters with lasers, modulators, and fully integrated receivers, as well as passive components, such as multiplexers, de-multiplexers and waveguides. All devices except lasers are fabricated using a Si CMOS process. •

30

Future Trends in Microelectronics

Figure 25. A magnified view of the DDR5 DRAM in a memory slot where optical interconnect circuitry is placed adjacent to the electrical I/O.

There are two kinds of laser schemes for optical interconnects: off-chip and on-chip. The off-chip scheme uses external III-V lasers with an integrated light coupler into a Si photonics chip. Butt or grating couplers are used to deliver the laser beam into the photonics circuit. One of the biggest advantages is that many wavelengths can be delivered from a mode-locked or a comb laser, followed by wavelength division multiplexing (WDM). However, off-chip interconnect has a larger footprint and low power efficiency due to coupling losses. To realize a Si laser on-chip, heteroepitaxial growth approaches have been preferred, and recently, successful lasing at communication wavelengths has been reported.58,59 But until now, lasers that can couple light to the Si waveguide have only been achieved in an evanescent coupling structure through a wafer-bonding processes.60 Another possible route is via a high index-contrast grating and vertical cavity surface emitting lasers (VCSELs). In this structure, the grating provides a good enough reflectivity for the bottom mirror and simultaneously serves as a coupler.61 The next challenge in Si photonics is the optical modulator, which consumes a significant amount of power. The conventional Si Mach-Zehnder device consumes ~3 pj/bit with a speed of 40 Gbit/s.62 Because of footprint constraints, the current trend is focused on improving the performance by using ring resonators which would consume ~3 fJ/bit, but these devices need higher speed, to be achieved by optimizing the RC constant and Q factor.63 The remaining active device that presents a challenge is the photodetector. Germanium photodetectors have proven to excel in terms of speed, dark current and energy consumption. However, compatibility of heteroepitaxial growth on Si with other front-end-of-the-line processes still remains to be fully established. Power losses in passive devices, like waveguides and multiplexers, are negligible compared to the active components described above. Nevertheless, improvements in optical propagation losses are still needed. With cost-effective Si photonics by

Technology Innovation, Reshaping the Microelectronics Industry

31

2015, 64 we should see both inter-chip and intra-chip ultrahigh-speed data communication. A fully integrated optical interconnect on a Si die has the advantage of being compact, reliable and energy-efficient. For instance, intra-chip optical interconnect applications in multi-core CPU systems could employ three different types of Si dies, consisting of multi-core CPU, memory and optical planes, interconnected optically or electrically, as shown in Fig. 26. Routing and circuit switching in a 3D topology will be crucial in multi-core systems, despite the fact that Si photonic interconnect networks are usually complicated, with multiple photonic waveguides and switches made of SiN and poly-Si, respectively. Some work is already being performed in this area. A dvanced Si based im age sensors During the past decade, CMOS image sensor (CIS) technology has been developed to integrate as many pixels as possible in a chip for increasing the resolution. However, as pixel size decreases, signal-to-noise ratio decreases and more optical and electrical crosstalk occurs, requiring pixel sensitivity to be enhanced. There are many ways for increasing the sensitivity of a pixel, such as backside illumination and microlenses. But these methods also have issues due to scaling limitations, so we can anticipate that novel 3D structures will be needed in the future. Another CIS technology trend is the 3D image capturing capability. Through the improvements in pixel densities and performance with added capabilities, digital still cameras will be able to support full-HD video, and also be able to support 3D content by providing the depth information along with the image. Currently, 3D image capturing by using the time of flight (TOF) technique is being developed for this purpose. •

Figure 26. (a) 3D stack with core multichip processor, memory and photonic SoC; (b) three-dimensional circuit switches and waveguides.

32

Future Trends in Microelectronics

High-resolution CMOS image sensors In recent years, the performance of CMOS image sensors (CIS) has improved dramatically due to increasing pixel density. But as the pixel size becomes smaller, so does the amount of light reaching the photodiode, resulting in decreased pixel performance. Traditional frontside-illuminated CIS will reach the limit at around the 1.4 um pixel size.65 Accordingly, researchers have begun searching for new structures and materials.66 The backside-illuminated (BSI) CMOS image sensor is regarded as the next generation sensor that will allow pixel sizes down to 1.1 um because they have a wider photon-receiving area than FSI, see Fig. 27. Because of process complexities67 and scaling limits of the BSI structure, another solution for further scaling will be needed. Next generation sensors are expected to employ vertical stacking of an organic photo-sensitive layer on the conventional silicon image sensor.68'69'70 In this vertical structure, a green organic photodiode is placed on top of the red and blue pixels positioned in the same plane, effectively reducing the pixel size, as shown in Fig. 28. •

Depth sensors Today, 3D movies and 3D television based on stereoscopic technology, as well as the Kinect gaming console, are receiving a lot of attention. As a result, there is considerable research into the next generation 3D capture and display technology, targeting such applications such as robotics, automotive, augmented reality and interactive gaming. Depth information enables electronic devices to recognize and track target objects without complicated post-processing. Among the various depth acquisition technologies, TOF-based depth capturing sensors have been developed based on Si CIS.71,72'73 As shown in Fig. 29, infrared (IR) •

Figure 27. Illustration of frontside-illuminated (FSI) and backside-illuminated (BSI) image sensors.

Technology Innovation, Reshaping the Microelectronics Industry

33

10000 8000 "ć/T

f A

f

HEE !

6000 4000

2000 0 Pixel size (urn)

1.75

1.4

1.1

0.9

0.75

Resolution (M)

3

5

8

12

20

Figure 28. Comparison of planar CIS and stacked organic CIS. In the stacked structure, a green organic photodiode is placed on top of the red and blue pixels, shrinking the pixels and increasing effective pixel number. Below 0.9 um pixel size the sensitivity of the stacked structure is advantageous.

Figure 29. 3D camera to capture color and depth. Infrared (IR) emitted by the camera illuminates the object and reflects back to the camera. The time that the light travels is used to calculate depth information.

34

Future Trends in Microelectronics

light is emitted by the camera, hits the object and reflects back to the camera. The time that the light travels is sensed by opto-electric devices, and the resulting depth image is captured with a Si CIS. This method can deliver a robust high-resolution 3D image. The time-of-flight depth imagers, where the pixels directly provide their own depth information, however, are still difficult to implement with a single image sensor that can acquire images with the color and the depth information simultaneously. This is because the acquisition mechanisms for the two types of images are totally different, resulting in markedly different pixel sizes (1.4 um color vs. 40 um depth in commercial products) and detector devices.

Figure 30. Overall architecture and unit pixel scheme of 1920x1080 2D/3D image sensor with binning pixel structure and time-division color/depth readout scheme.

Technology Innovation, Reshaping the Microelectronics Industry

35

To address this problem, a CMOS image sensor with a typical pin photodiode structure and multi-resolution functionality has recently been demonstrated.74 Figure 30 shows the overall architecture and unit-pixel structure schemes for depth and color sensing. The full color resolution of this sensor is 1920x1080; and to increase IR detection sensitivity, it combines 4x4 pixels as one depth pixel for depth sensing. This sensor can operate in two alternate readout modes for color and depth images in each frame by using a time-division scheme shown in Fig. 30. Figure 31 shows another example of depth and color sensing, a row interlaced RGBZ pixel architecture in which every third row of color pixels is replaced with a row of Z pixels.75 It provides simultaneous color and depth information with a special photodiode process for Z pixels, as illustrated in Fig. 31. 8.

Silicon technology and medical or healthcare applications

Healthcare is one area that has greatly benefitted from silicon technologies in recent years. The current trends and key words in healthcare are predictive, preventive, personalized and participatory - known as the 4Ps. The goal is to prevent any disease from ever appearing. But if it does happen, cancer or another disease should be detected at earlier stages, and each individual should receive customized treatments and cares tailored individually for him or her. Furthermore, every person should be able to monitor his or her health conditions seamlessly. Although indirectly, silicon technology is contributing to the realization of the 4Ps by providing key components for medical devices. One such device monitors vital signs for indications of potential health risks. Other devices are used to improve medical diagnostic imaging, such as ultrasound and x-ray imaging systems. Silicon technology could also accelerate the era of affordable wholegenome sequencing that could be the ultimate solution for realizing the 4Ps.

Figure 31. structure.

Sensor architecture showing the RGBZ pixel array and the pixel

36

Future Trends in Microelectronics

Mobile sensing platform Anomalies in various vital signs indicate potential health problems. Vital signs such as electro-cardiography (ECG), blood pressure and glucose levels, etc. can be continuously monitored over a long period of time, as well as during daily activities. With the rapid advances in silicon technology, wireless communication, microelectronics, as well as cutting-edge sensors, a body sensor network can be envisioned. Such a sensing platforms must be small, lightweight, wireless, and capable of operating on a single battery charge. Many vital sign sensors in the form of wearable smart shirts, wristwatches, belts, and patches have been proposed to date.76 But as of now, most of them are still uncomfortable because they are tight-fitting, relatively large and heavy. An ultralow-power (ULP) mobile vital sign-sensing platform usually consists of various small physiological sensors, an analog front-end (AFE), a wireless RF communication module, and a DSP chip, as shown in Fig. 32. In this platform, the AFE performs conditioning, amplification, and digital conversion of the collected signal that undergoes further processing in the DSP. The microprocessor performs various control-related tasks. The extracted features or the complete sampled signals are then transmitted by the wireless RF to a mobile gateway. This mobile vital sign sensing platform should be thin enough to be attachable to the human skin and should last a week without recharging. Currently, more development is needed in order to optimize the form factor and size while maximizing the user's comfort. A specific example of this type of monitoring system is an ultrathin bandagetype ECG sensor for the mobile management of cardiac diseases. The main specifications of such a system are: low power consumption of 1 mW, dimensions of 70x26x1.5 mm, and weight of 8 g, as summarized in Table 1. Due to its small size, low weight, and low power consumption, combined with good measurement capabilities, this sensing platform is a promising candidate for long-term ubiquitous ECG monitoring. Future work will be needed to develop a zeroexternal-power mobile sensing platform in combination with future energyefficient technologies (ULP DSP and/or the ULP wireless RF communication) and disruptive power scavengers (from solar, thermal, vibration, and electromagnetic energy harvesters) with power densities of mW/cm2 (or mW/cm3). •

Figure 32. A typical mobile vital sign sensing platform (figure courtesy of SAIT).

Technology Innovation, Reshaping the Microelectronics Industry

37

Specifications

Unit

Available

Future

Size

mm

150x60x5

70x26x1.5

System power

mW

3

1

RF power

mJ/bit

15

1

DSP efficiency

uW/MHz

8015 MCU

30

Motion artifact reduction

yes/no

no

yes

Event detection

yes/no

no

99%

Table 1. Specifications of an energy-efficient ubiquitous ECG sensor.

Medical im aging - ultrasound on Si Ultrasonic transducers for medical diagnostic imaging have traditionally been based on PZT (lead zirconate titanate) material. However, due to its limited performance and design flexibility, a more advanced capacitive micromachined ultrasonic transducer (cMUT) is being developed. The cMUT has a wide bandwidth, which enhances sensitivity by using second harmonics. The PZT and cMUT output response versus frequency are compared in Figs. 33(a) and (c). The cMUT's ring-down time, the time required for the resonance frequency to decrease down to a negligible level, is less than half of the PZT, as shown in Figs. 33(b) and (d). This allows for improved depth resolution. Although the lack of output power in the cMUT is often raised as a disadvantage, higher receiving sensitivity with direct integration of the signal processing circuitry keeps the loop sensitivity and overall usability above the benchmarks achieved by the PZT transducer. The other aspects differentiating cMUT from PZT transducers are design flexibility and expandability. The PZT transducers are mechanically ground and hand wired, which leads to a low yield and large performance variation, thereby limiting the number of elements and array construction. The cMUT, on the other hand, is fabricated using semiconductor processes, resulting in a high yield and low performance variation (less than 5%). The cMUT becomes even more expandable for various aperture sizes and form factors with direct integration of the control ASIC, as shown in Fig. 34. The first target application for cMUT-based ultrasound diagnosis is real-time volumetric imaging with a 2D array. With a highly integrated platform like this, it is not difficult to imagine a portable system that consists of the smart cMUT probe with communication capabilities and a control system in the form of tablet PC or even a cell phone. •

38

Future Trends in Microelectronics

Figure 33. (a, c) Output response vs. frequency and (b, d) ring-down times for PZT and cMUT devices. Ring-down times means the time required for the resonance frequency to decrease down to negligible levels.

Figure 34. The cMUT with control ASIC as a single chip solution can be further integrated with a compact beam former into a probe. SoC technology will be utilized for ultrasound on a single chip.

Technology Innovation, Reshaping the Microelectronics Industry

39

X-ray detectors on Si X-rays have been used in medical diagnosis for over a hundred years because they penetrate solids, liquids and gases at wavelengths of 0.01~10 nm, equivalent to energies of 10-120 keV. The main interaction mechanisms for x-ray photons with matter are photoelectric absorption, generation of electron-hole pairs and Compton scattering. A radiation detector can provide output signals as a result of primary ionizations, thermal changes or scintillations that generate electric signals. •

Scintillators are widely used for conventional x-ray imaging by generating visible light after x-ray absorption. The visible light is subsequently collected by photodiodes and converted into electrical signals. A scintillator material consists of chemical elements of high atomic number and density that effectively absorb xray energies, e.g. thallium doped cesium iodide (CsI:Tl). The efficiency of a scintillators is basically determined by visible light output. Direct conversion of x-rays to an electrical signals would be more efficient. Photoconductors such as cadmium telluride (CdTe) and amorphous selenium (a-Se) can absorb the incident x-ray energy and convert it into electrical charges. The xray sensitivity of a direct conversion detector depends on the efficiency of a photoconductor that converts the incident x-ray to electrical charge that can be detected by a CMOS readout circuit. Figure 35 compares schematically the two xray detection schemes.

Figure 35. Concept of x-ray detection: (a) indirect, using a scintillator; (b) direct, using a photoconducting material.

40

Future Trends in Microelectronics

Silicon CMOS-based detectors enable the counting of x-ray photons thanks to their fast counting rate; and in addition they are also able to differentiate the energy levels.77'78 An advanced PCD (photocounting detector) is illustrated in Fig. 36(a). The ultimate goal is to obtain a large-area PCD detector that would allow for full field imaging without having to scan the patient. Moreover, the large areal PCDs have the advantage of minimizing the radiation dose by reducing the x-ray exposure time. The remaining challenge is the development of photo-conducting materials for a high-resolution, high-performance system. A likely photoconductor material for large-area PCDs is Hgl2, which has high sensitivity compared to other photoconductor materials, as shown in Fig. 36(b). Also the large grain size and crystalline orientation are appropriate for photon detection as shown in Fig. 36(c).

Figure 36. (a) A proposed PCD concept: cross-sectional view of x-ray imager device and its unit pixel structure;79 (b) x-ray sensitivity vs. material thickness for typical photoconductor materials; (c) cross-sectional view of evaporation-deposited poly-Hgl2 for large areal PCDs. The grain size is large enough for photon counting.

Technology Innovation, Reshaping the Microelectronics Industry

41

In order to obtain a good x-ray image, energy resolution of the absorbing material should be as narrow as 5 keV. Even though poly-HgI2 could satisfy this resolution requirement, research on large-area single-crystal x-ray absorbing materials and detection circuitry is necessary. DNA sequencing As the knowledge of DNA sequences revolutionized our understanding of biological phenomena, sequencing technology has become indispensable for basic biological research. For the last two decades, sequencing technology has advanced rapidly, reducing the cost for sequencing the whole genome from 10 billion dollars to about $5,000. This development opens up a promising era of individual whole genome sequences in a variety of clinical settings. For the personalized medicine era, however, cost should be reduced below $1,000, and some technical challenges need to be solved. In order to reduce the cost and the time involved in genome sequencing, nextgeneration sequencing (NGS) based on massively parallel methods is currently under development. Most NGS technologies have been based on optical detection, requiring additional processes for dye labeling and massive hardware systems for optics. Racing to reach below $1,000 per test, enormous efforts have been invested during the last decade, and as of today (2012), whole genome sequencing can be performed at a cost of $4,000 by some service providers. Figure 37 illustrates the evolution of DNA sequencing technology through the years. •

Figure 37. Development of DNA sequencing technology: 1st generation of sequencing technology based on capillary electrophoresis using the Sanger method; 2nd generation based on massive parallel sequencing using optical or electrical detection; 3rd generation sequencing is expected to evolve to the single molecule detection technology.

42

Future Trends in Microelectronics

Recently, an innovative sequencing device that uses CMOS sensors has been introduced.80 The FET sensor array of the chip detects potential variations generated by the proton ions during DNA synthesis, as shown in Fig. 38. Advanced CMOS technology can be used to produce a much smaller sensor chip, even though working with DNA synthesis within a small sensor is not an easy task. The true significance of emerging FET technology is the elimination of optical detection apparatus, thus lowering the cost and size of the hardware. As of today, the read length of NGS technologies is still limited to around 200 bases, and a complete DNA sequencing may not be possible with NGS technologies alone. Single-molecule sequencing technology can read through DNA templates in real time without amplification and provide accurate sequencing data. Nanopore

Figure 38. Ion-sensing FET sensor and structure: (a) protons are released when nucleotides (dNTP) are incorporated with target DNA on the bead during DNA synthesis by polymerase enzyme. Protons change the pH of the well, changing the potential AV of the metal-oxide-sensing layer and modulating the source-drain current of the underlying FET; (b) cross-section of ion-sensing FET, showing the well and underlying FET with the sensing layer.80

Technology Innovation, Reshaping the Microelectronics Industry

43

sequencing technology appears the most promising among several single-molecule sequencing technologies. The basic idea of nanopore sequencing is to detect the electrical signals while DNA passes through a nanopore that interconnects two chambers held at different electrical potentials separated by a thin membrane. Graphene is a promising material to overcome the difficulties in nanopore sequencing technology, as it can provide a conductive membrane with atomic scale thickness to comply with the size of a DNA base. Once fabrication processes for graphene are well established in near future, graphene nanopores promise to provide a practical DNA sensor for a daily clinical practice. 9.

Future prospects

In this chapter, we have reviewed breakthroughs in Si technology and their impact on the surrounding industries. Until the 10 nm regime, Si-based memory and logic technologies will continue with the downscaling of the critical dimensions. Advances in material technology will soon allow spintronic, III-V and even graphene-based devices to be integrated with Si devices. Thus, III-V materials in combination with Si are finding important roles in energy-conscious devices, such as solid-state lighting and power electronics. These materials, integrated with Si electro-photonic ICs, can provide a cornerstone for light processing combined with electronics support, which will eventually enable an on-chip optical interconnect technology for future computing and ultrawide-bandwidth data communications. Nonvolatile devices, such as ReRAM, can be used to support important analog memory and processing elements, much like the functions performed by the brain and reconfigurable functions in Si circuits. Nonvolatile devices as synapses in neuromorphic circuits can potentially offer the high connectivity and density required for efficient neuromorphic computing. Silicon platform technology is also underpinning advances in bio, health and medical diagnostics, such as DNA sequencing, integrated polymerized chain reaction (iPCR), medical imaging, etc. Beyond the 10 nm node, Si platform technologies will encounter atomic scale units and quantum states, including spin-based state variables. Furthermore, future devices will need more functional diversification, which will require more interdisciplinary work. Acknowledgments We would like to thank Seung-Ho Cho, Young-Jin Cho, Hyun-Jong Chung, Nam Hur, Kwang-Seok Kim, Dong-Won Kim, Young-Bae Kim, Ho-Jung Kim, JunYoun Kim, Kyu-Sik Kim, Sung Hyun Nam, Dongho Lee, Dong-Wan Lee, Changho Lee, Junsu Lee, Yvette Lee, Hyungjae Shin, I-Hun Song, Kunsoo Shin, and Jaejoon Oh for the helpful technical discussions.

Future Trends in Microelectronics

44

References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11.

12. 13. 14. 15. 16. 17.

Gartner Market Report, Market Share: Mobile Devices by Region and Country, 4Q11 and 2011 (2012). Gartner Market Report, Forecast: Media Tablets by Operating System, Worldwide, 2010-2016, 1Q12 Update (2012). L. C. Kimerling, "Silicon microphotonic integration: Trends and transitions," Microphotonic Center Spring Mtg., Cambridge, MA (April 30, 2012). P. Kogge, K. Bergman, S. Borkar, et al., ExaScale Computing Study: Technology Challenges in Achieving Exa-Scale Systems, DARPA IPTO report TR-2008-13 (2008). K. Kim, U-In Chung, Y. W. Park, J. Y. Lee, J. H. Yeo, and D. C. Kim, "Extending the DRAM and FLASH memory technologies to 10 nm and beyond," Proc. SPIE 8326, 832605 (2012). K. Kim, "From the future Si technology perspective: Challenges and opportunities," Tech. Dig. IEDM (20Щ, pp. 1-9. J. Lee, D. W. Ha, and K. Kim, "Novel cell transistor using retracted Si3N4liner STI for the improvement of data retention time in gigabit density DRAM and beyond," IEEE Trans. Electron Dev. 48, 1152 (2001). K. Prall and K. Parat, "25 nm 64Gb MLC NAND technology and scaling challenges," Tech. Dig. IEDM (2010), art. 5703300. J. Hwang, J. Seo, Y. Lee, et al., "A middle-lX nm NAND flash memory cell (M1X-NAND) with highly manufacturable integration technologies," Tech. Dig. IEDM (20U), art. 6131518. K. Kim, "Future memory technology: Challenges and opportunities," Proc. VLSI-TSA (2008), pp. 5-9. C.-H. Lee, C. Kang, J. Sim, et al., "Charge trapping memory cell of TANOS (Si-oxide-SiN-Al203-TaN) structure compatible to conventional NAND Flash memory," Proc. 21st IEEE Intern. Nonvolatile Semicond. Memory Workshop (2006), art. 1629491. M. Durlam, Y. Chung, M. DeHerrera, et al, "MRAM memory for embedded and standalone systems," Proc. ICICDT (2007), art. 4299546. K. Lee and S. H. Kang, "Development of embedded STT-MRAM for mobile system-on-chips," IEEE Trans. Magn. 47, 131 (2011). S. C. Oh, J. H. Jeong, W. C. Lim, et al., "On-axis scheme and novel MTJ structure for sub-30 nm Gb density STT-MRAM," Tech. Dig. IEDM (2010), art. 5703350. 2011ITRS, Table PIDS 8b. H. Yoda, T. Kishi, T. Nagase, et al., "Highly efficient spin transfer torque writing on perpendicular magnetic tunnel junctions for high density MRAMs," Current Appl. Phys. 10, 87 (2010). J. J. Nowak, R. P. Robertazzi, J. Z. Sun, et al., "Demonstration of ultralow bit error rates for spin-torque MRAM with perpendicular magnetic anisotropy," IEEE Magn. Lett. 2, 3000204 (2011).

Technology Innovation, Reshaping the Microelectronics Industry

45

18. T. Kawahara, K. Ito, R. Takemura, and H. Ohno, "Spin-transfer torque RAM technology: Review and prospects," Microelectronics Reliability 52, 613 (2012). 19. J. H. Hur, M.-J. Lee, C. B. Lee, Y.-B. Kim, and C.-J. Kim, "Modeling for bipolar resistive memory switching in transition-metal oxides," Phys. Rev. B 82, 155321 (2010). 20. M. Bohr, "The evolution of scaling from the homogeneous era to the heterogeneous era," Tech. Dig. IEDM (2011), art. 6131469. 21. S. Naffziger, "Technology impacts from the new wave of architectures for media-rich workloads," Tech. Dig. VLSISymp. (2011), pp. 6-10. 22. A. M. Ionescu and H. Riel, "Tunnel field-effect transistors as energy-efficient electronic switches," Nature 479, 329 (2011). 23. C.-W. Lee, S.-R.-N. Yun, C.-G. Yu, J.-T. Park, and J. P. Colinge, "Device design guidelines for nano-scale MuGFETs," Solid State Electronics 5 1 , 505 (2007). 24. B. Majkusiak, T. Janik, and J. Walczak, "Semiconductor thickness effects in the double-gate SOI MOSFET," IEEE Trans. Electron Dev. 45, 1127 (1998). 25. L. Ge, J. G. Fossum, and F. Gamiz, "Mobility enhancement via volume inversion in double-gate MOSFETs," IEEE Intern. SOlConf. (2003), pp. 153154. 26. G. Tsutsui, M. Saitoh, and T. Hiramoto, "Superior mobility characteristics in [110]-oriented ultra thin body pMOSFETs with SOI thickness less than 6 nm," Dig. Tech. VLSISymp. (2005), pp. 76-77. 27. K. J. Kuhn, "Reducing variation in advanced logic technologies: Approaches to process and design for manufacturability of nanoscale CMOS," Tech. Dig. IEDM (2007), pp. 471-474. 28. S. E. Thompson and S. Parthasarathy, "Moore's Law: The future of Si microelectronics," Mater. Today 9,20 (2006). 30. I. Young, "MOSFET extrinsic parasitic elements," IEDM Short Course (2011), p. 49. 30. S. Takagi, T. Irisawa, T. Tezuka, et al., "Carrier-transport-enhanced channel CMOS for improved power consumption and performance," IEEE Trans. Electron Dev. 55,21 (2008). 31. D. H. Kim, J. A. del Alamo, D. A. Antoniadis, and B. Brar, "Extraction of virtual-source injection velocity in sub-100 nm III-V HFETs," Tech. Dig. IEDM (2009), pp. 861-864. 32. M. Radosavljevic, G. Dewey, D. Basu, et al., "Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-к gate dielectric and scaled gate-to-drain/gate-to-source separation," Tech. Dig. IEDM (20U), art. 6131661. 33. J. J. Gu, Y. Q. Liu, Y. Q. Wu, R. Colby, R. G. Gordon, and P. D. Ye, "First experimental demonstration of gate-all-around III-V MOSFETs by top-down approach," Tech. Dig. IEDM (2011), art. 6131662.

46

Future Trends in Microelectronics

34. K. Tomioka, M. Yoshimura, and T. Fukui, "Steep-slope tunnel field-effect transistors using III-V nanowires/Si heterojunction," Tech. Dig. VLSI Symp. (2012), pp. 47-48. 35. A. Geim and K. Novoselov, "The rise of graphene," Nature Mater. 6, pp. 183191 (2007) 36. X. Li, X. Wang, L. Zhang, S. Lee, and H. Dai, "Chemically derived, ultrasmooth graphene nanoribbon semiconductors," Science 319, 1229 (2008). 37. F. Xia, D. Farmer, Y. Lin, and Ph. Avouris, "Graphene field-effect transistors with high on/off current ratio and large transport band gap at room temperature," Nano Lett. 10, 715 (2010). 38. J. Bai, X. Zhong, S. Jiang, Y. Huang, and X. Duan, "Graphene nanomesh," Nature Nanotechnol. 5,190(2010) 39. H. Yang, J. Heo, S. Park, et al., "Graphene barrister, a triode device with a gate-controlled Schottky barrier," Science 336, 1140 (2012). 40. L. Britnell, R. Gorbachev, R. Jalil, et al., "Field-effect tunneling transistor based on vertical graphene heterostructures," Science 335, 947 (2012). 41. C.-S. Poon and K. Zhou, "Neuromorphic silicon neurons and large-scale neural networks: Challenges and opportunities," Frontiers Neurosci. 5, 1 (2011). 42. K. M. Mhaidat, M. A. Jabri, and D. W. Hammerstrom, "Representation, methods, and circuits for time-based conversion and computation," Intern. J. Circ. Theory Appl. 39,299 (2011). 43. Z. Q. Wang, H. Y. Xu, X. H. Li, et al., "Memristors: Synaptic learning and memory functions achieved using oxygen ion migration/ diffusion in an amorphous InGaZnO memristor," Adv. Funct. Mater. 22, 2758 (2012). 44. Energy Outlook 2030, British Petroleum report (2012). 45. M. A. Green, "The path to 25% silicon solar cell efficiency: History of silicon cell evolution," Prog. Photovolt: Res. Appl. 17, 183 (2009). 46. D. Smith, P. Cousins, A. Masad, et al., "Generation III high efficiency lower cost technology: Transition to full scale manufacturing," Proc. 38th IEEE Photovolt. Specialists Conf. (PVSC) (2012), pp. 1594-1597. 47. Y. G. Kim, "Solar cells and methods of forming the same," U.S. patent 2010/0071764A1. 48. Y. M. Choi, E. C. Do, D. K. Kim, D.-K. Kim, and Y. G. Kim, "Stacked thin film solar cell on crystalline Si," U.S. patent 2012/0266933A1. 49. A. Krost, and A. Dadgar, "GaN-based optoelectronics on silicon substrates," Mater. Sci. Eng. B 93, 77 (2002). 50. J.-Y. Kim, Y. Tak, J. Kim, et al., "Highly efficient InGaN/GaN blue LED on 8-inch Si (111) substrate," SPIEPhotonics West 8262, 82621D (2012). 51. H. Choi, J. Lee, J. Kim, et al., "First demonstration of 8-inch AlGaN/GaN HEMTs on Si with breakdown voltage of 1.7 kV and low sheet resistance," presented at Intern. Conf. MOVPE, Busan, Korea (2012). 52. N. Ikeda, Y. Niiyama, H. Kambayashi, et al., "GaN power transistors on Si substrates for switching applications," Proc. IEEE 98,1151 (2010).

Technology Innovation, Reshaping the Microelectronics Industry

47

53. Y. Uemoto, T. Morita, A. Ikoshi, et cd., "GaN monolithic inverter IC using normally-off gate injection transistors with planar isolation on Si substrate," Tech. Dig. IEDM (2009), pp. 165-168. 54. K. Chen and C. Zhou, "Enhancement-mode AlGaN/GaN HEMT and MISHEMT technology," Phys. Status SolidiA 208, 434 (2011). 55. H. Kambayashi, Y. Niiyama, S. Ootomo, et cd., "Normally off n-channel GaN MOSFETs on Si substrates using an SAG technique and ion implantation," IEEE Electron Dev. Lett. 28, 1077(2007). 56. I. Hwang, H. Choi, J. Lee, et cd., "1.6 kV, 2.9 míícm 2 normally-off p-GaN HEMT device," Proc. Intern. Symp. Power Semicond. Dev. ICs (2012), pp. 41-44. 57. K. Kim, "Electronics and photonics convergence on Si CMOS platform," Proc. Intern. Optoelectronics Commun. Conf. (2012). 58. J. R. Reboul, L. Cerutti, J. B. Rodriguez, P. Grech, and E. Tournié, "Continuous-wave operation above room temperature of GaSb-based laser diodes grown on Si," Appl. Phys. Lett. 99, 121113 (2011). 59. T. Wang, H. Liu, A. Lee, F. Pozzi, and A. Seeds "1.3 ц т InAs/GaAs quantumdot lasers monolithically grown on Si substrates," Optics Express 19, 11381 (2011). 60. G. Roelkens, L. Liu, D. Liang, et cd., "III-V/silicon photonics for on-chip and intra-chip optical interconnects," Laser Photonics Rev. 4, 751 (2010). 61. I. S. Chung and J. Mork, "Silicon-photonics light source realized by Ill-V/Si grating-mirror laser," Appl. Phys. Lett. 97, 151113 (2010). 62. L. Liao, D. Samara-Rubio, M. Morse, et cd., "High-speed silicon MachZehnder modulator," Optics Express 13, 3129 (2005). 63. W. A. Zortman, M. R. Watts, D. C. Trotter, R. W. Young, and A. L. Lentine, "Low-power high-speed Si microdisk modulators," Proc. CLEO (2010), no. 5500977. 64. M. Haurylau, G. Chen, H. Chen, et cd., "On-chip optical interconnect roadmap: Challenges and critical directions," IEEE J. Selected Topics Quantum Electronics 12, 1699 (2006). 65. S. G. Wuu, C. C. Wang, D. N. Yaung, et cd., "A manufacturable back-side illumination technology using bulk-Si substrate for advanced CMOS image sensor," Proc. Intern. Image Sensor Workshop (2009). 66. T. Suzuki, "Challenges of image-sensor development," Tech. Dig. ISSCC (2010), pp. 27-30. 67. G. Agranov, S. Smith, R. Mauritzson, et cd., "Pixel continues to shrink ... small pixels for novel CMOS image sensors," Intern. Image Sensor Workshop (2011). 68. S. Aihara, Y. Hirano, T. Tajima, et cd., "Wavelength selectivities of organic photoconductive films: Dye-doped polysilanes and zinc phthalocyanine/tris-8hydroxyquinoline aluminum double layer," Appl. Phys. Lett. 82, 511 (2003). 69. S. Takada, M. Ihama, and M. Inuiya, "CMOS image sensor with organic photoconductive layer having narrow absorption band and proposal of stack type solid-state image sensors," Proc. SPIE 6068, 60680A (2006).

48

Future Trends in Microelectronics

70. Y. Higashi, K.-S. Kim, H.-G. Jeon, and M. Ichikawa, "Enhancing spectral contrast in organic red-light photodetectors based on a light-absorbing and exciton-blocking layered system," J. Appl. Phys. 108, 034502 (2010). 71. Y. H. Park, Y.-C. Cho, J.-W. You, et al., "Micro optical system based 3D imaging for full HD depth image capturing," Proc. SPIE Photonics West 4, no. 8252-32 (2012). 72. B. H. Na, G. W. Ju, H. J. Choi, Y. C. Cho, Y. H. Park, and Y. T. Lee, "Large aperture asymmetric Fabry-Perot modulator based on asymmetric tandem quantum well for low voltage operation," Optics Express 20, 6003 (2012). 73. S.-J. Kim, J. D. K. Kim, S.-W. Han, B. Kang, K. Lee, and C.-Y. Kim, "A 640x480 image sensor with unified pixel architecture for 2D/3D imaging in 0.11 um CMOS," Dig. IEEESymp. VLSICirc. (2011), pp. 92-93. 74. S.-J. Kim, B. Kang, J. D. K. Kim, K. Lee, C.-Y. Kim, and K. Kim, "A 1920x1080 3.65 цт-pixel 2D/3D image sensor with split and binning pixel structure in 0.11 ц т standard CMOS", Tech. Dig. ISSCC (2012), pp. 396-397. 75. W. Kim, W. Yibing, I. Ovsiannikov, et al., "A 1.5 Mpixel RGBZ CMOS image sensor for simultaneous color and range image capture," Tech. Dig. ISSCC (2012), pp. 392-393. 76. A. Pantelopoulos and N. G. Bourbakis, "A survey on wearable sensor-based systems for health monitoring and prognosis," IEEE Trans. Syst. Man Cybernetics C: Appl. and Rev. 40, 1 (2010). 77. M. Danielsson, "Photon counting is an intuitive way to detect x-rays, which by nature are digital and have a color spectrum," Diagnostic Imaging Europe 25, No. 7 (2009). 78. T. G. Schmidt, "Optimal 'image-based' weighting for energy-resolved CT," Medical Phys. 36, 3018 (2009). 79. H.-S. Kim, S.-W. Han, J.-H. Yang, et al., "A sampling-based 128x128 direct photon-counting x-ray image sensor with 3 energy bins and spatial resolution of 60 цт/pixel," Tech. Dig. ISSCC (2012), pp. 110-111. 80. J. M. Rothberg, W. Hinz, T. M. Rearick, et al., "An integrated semiconductor device enabling non-optical genome sequencing," Nature 475, 348 (2011).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Challenges and Limits for Very Low Energy Computation F. Balestra IMEP-LAHC/Minatec and Sinano Institute 3 parvis Louis Néel, 38016 Grenoble, France

1.

Introduction

The historic trend in micro- and nano-electronics over the last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition. Since the 90 nm node, power supply KDD downscaling has slowed down, leading to accelerated energy consumption and heating, and a move from constant field toward nearly constant voltage scaling. In 2005, the increase in microprocessor frequency abruptly ceased, but the integration level continued to increase, with a general shift to parallel processors. We are thus facing today dramatic challenges dealing with the limits of energy consumption (static plus dynamic) and heat removal, inducing fundamental tradeoffs for the future ICs. Research into ultimate reduction of computation dissipation is essential for the development of future highperformance terascale integration and autonomous nanosystems. This chapter addresses the main challenges, limits and possible solutions for strongly reducing the switching energy per binary bit. Several paths are possible: the adiabatic logic using a slow clock, which will not be addressed in this paper because it cannot be used for high performance devices; logic stochastic resonance; feedbackcontrolled dynamic gate; or conventional logic with a reduction in the stored energy, therefore a decrease of device capacitance C (device integration) or applied bias FDD, which seems to be the most promising for future ICs. The reduction of the stored energy in conventional logic can be done with a strong reduction in VDD using new physics and/or devices with sub-60 mV/decade subthreshold swing (SS). The main proposed alternatives include: energy filtering (tunnel FET or TFET with band-to-band tunneling used to filter the energy distribution of electrons in the source, or nanowire FET with a superlattice in the source), internal voltage step-up (ferroelectric gate FET, inducing a negative capacitance to amplify the change in channel potential induced by the gate), NEMS-based switching, or impact-ionization MOS devices. We will focus here on the most promising direction, TFETs, which could lead to ultra short channel devices with a strong reduction of the applied bias, together with very good performance and reliability.

49

Future Trends in Microelectronics

50 2.

Results and discussion

Irreversible logical operations require energy dissipation of at least £B71n(2) (the so-called Landauer limit). Today, we are very far from this limit, with a switching energy E that is more than three decades larger than this minimum value. The slowdown of KDD scaling and the substantial increase of the subthreshold leakage current / 0 FF lead to a dramatic enhancement of the dynamic and static power consumption. This power dissipation challenge,1 P ~ /OFFFDD3» is largely due to the MOSFET subthreshold slope limit SS > 60 mV/dec at room temperature. A lower limit in energy per operation can be reached, with minimum VDD ~ SS and minimum E ~ SS2, as illustrated schematically in Fig. 1.2 There are two ways to reduce the transistor subthreshold swing SS: SS =

dVc dVc 3v|/_ „ „ „ C.kJT „ „ kj S—- = — ^ -^— = 2.3(1 + —§-)-5- = 2 . 3 m - 5 - , 3(log/ D ) d ¥ s 9(log/D) C.J q q

,,, (1)

where y s is the KG-controlled surface potential and m is the so-called body factor. The body factor m can be reduced by using ultra-thin body SOI, multi-gate or nanowire (NW) architectures, carbon nanotube or graphene channels (leading to m ~ 1) or and negative capacitance FETs, or MEMS/NEMS structures (leading to m < 1). Alternatively, the other 3\|/s/3(log/D) term in Eq. (1) can be reduced, either by low temperature operation, which is not suitable for traditional applications, or by modifying the carrier injection mechanism with impact ionization or band-to-band tunneling (BTBT). The best standard MOSFET devices leading to SS close to its minimum value are using fully depleted channels3'4 (e.g. FD-SOI with very thin buried oxide5) or fully inverted channels with volume inversion,6 that comes closer to perfect electrostatic control of the channel7 (e.g. double-gate, bulk or SOI tri-gate/fm-FET, gate-all-around MOSFET or NW FET).

Figure 1. Schematic lower limit in energy per operation obtained for optimal VDD.

Challenges and Limits for Very Low Energy Computation

51

Figure 2. Subthreshold swing SS obtained by quantum transport numerical simulation as a function of device architecture for gate length LG down to 5 nm: double-gate strained-Si ultra-thin-body MOSFET (fSi = 3 nm), i2-gate strained-Si and InGaAs nanowires with 3 nm diameter, gate-all-around carbon nanotubes (GAA CNTs) with 1 nm and 0.63 nm diameters.

Double-gate devices with gate underlap have also shown to lead to a very good /Dsat, a reduction in the DIBL and drain-gate tunneling current, and a decrease of the gate capacitance, propagation delay, and power.8 Small diameter Si NW FETs have demonstrated experimentally very good / 0 N/ /OFF performance,9 with the best SS ~ 75 mV/dec obtained by numerical simulation down to 5 nm gate length, as shown in Fig. 2.10 However, other innovative devices are needed to overcome the sub-60 mV/dec limit. To outperform standard CMOS, these new devices, called the small swing or small-slope switches (Fig. 3), need an / 0 N in the range of hundreds of uA, an average subthreshold swing well below 60 mV/dec for at least 4—5 decades of/D, a 5 /ON//OFF ratio larger than 10 , and FDD < 0.5 V. Tunnel FETs use interband tunneling in heavily-doped pn junctions with a control of band-bending using VG and a reverse-biased pin junction. In these transistors, the ambipolar effect has to be suppressed by an asymmetry in the doping level or profile, or the use of heterostructures in the channel between source and drain. In order to optimize the BTBT transmission probability and enhance /ON> we need to propose structures with a reduced tunneling effective mass m*, source bandgap EG and/or the tunneling length X, and increasing the band offset ДФ between the conduction band of the source and valence band of the channel. A heterostructure is needed to optimize EG, m*, and ДФ, whereas X can be decreased by a change of device dimensions, abrupt and high doping, gate overlap at the tunnel junction, high-K gate, a multi-gate structure, or the use of materials other than silicon.

52

Future Trends in Microelectronics

Figure 3. Comparison between the MOSFET switch, the small-swing switch, and the ideal switch.

Figure 4. (a) Transfer /D(V G ) curves of LQ = 100 nm n- and p-channel TFETs (fSi = 20 nm); (b) / 0N of LQ = 400 nm SOI, SiGeOI and GeOI n- and p-TFETs (f SiGe = 20 nm, fGe = 60 nm, VD = ±0.8 V, VG = ±2 V).

Challenges and Limits for Very Low Energy Computation

53

It is also worth noting that in TFETs LG has little effect on /D, a source-drain heterostructure is preferable (smaller EG in the source and larger EG in the drain) and complementary TFETs are needed for logic circuits. Figure 4(a) shows the experimental characteristics of SOI TFETs. A very good S down to 42 mV/dec is obtained forp-channel operation, albeit over a small range of/ D . n Using SiGeOI and GeOI TFETs, strong improvements of the driving current, in the 102-103 range, are obtained compared with SOI TFETs, as shown in Fig. 4(b). However, while / 0 FF is very low, the best GOI TFETs provided an / 0 N of only several uA/um. As in the case of standard MOSFETs, technology boosters can also be applied for TFETs, in particular: high-к dielectric, abrupt doping profile at tunnel junction, thinner body, high source doping, multi-gate, gate oxide aligned with /'-region, shorter LG and /-region, etc. The results obtained by numerical simulation are illustrated in Fig. 5, where we can see that short-channel thin Si film double-gate TFET with high-K gate dielectrics and stress at the source junction leads to the best performance with a substantial increase of/ 0 N and reduction of SS. Feedback FETs12 and Z2-FETs13 based on a forward-biased gated pin diode, have shown experimentally very small SS (a few mV/dec) together with good / 0 N, but for biases larger than 0.5 V. Interesting performance has been demonstrated in strained Ge double-gate TFETs with asymmetric source/drain, especially with Si drain, with SS down to 50 mV/dec and / 0 N up to 300 цА/цт for high FD.14 However, these experimental results were obtained with different biasing applied to the front and back gates due to the different front and back gate oxides, and it has been shown that an application of VG proportional to oxide thickness gives an overestimation of the device performance.15

Figure 5. (a) Simulated baseline single-gate SOI TFET with Z.G = 100 nm and 3 nm Si0 2 gate oxide; (b) 4 GPa stress at source junction; (c) high-к gate oxide; (d) double-gate; (e) oxide aligned to /-region; (f) LG = 30 nm.

Future Trends in Microelectronics

54

10s

I , IO"*

0

0.4

0.8

VG (V) Figure 6. Simulated Z.G = 20 nm InAs NW TFET with 5 nm diameter vs. strain, dashed line shows s-Si MOSFET for comparison.

Single-gate, double-gate and gate-all-around InAs TFETs lead to very good simulated results (for VG = VD = 0.2 V), with SS < 20 mV/dec for small wire diameter down to 2 nm, due to the small effective masses and bandgaps of these III-V materials. High performance, with / 0 N up to 1 mA/um at low VD, have been reported by quantum transport simulation on strained InAs NW TFETs, with the the best results found in biaxially strained devices, see Fig. 6.16 The first experimental demonstration of SS < 60 mV/dec (on less than 1 decade of /D) using III-V materials has been reported in InGaAs heterojunction TFETs with LG = 150 nm, thin equivalent oxide thickness and high source doping, with /ON reaching a few uA/pm.17 Carbon-based tunnel FETs were the first device showing SS down to 40 mV/dec experimentally in an individual CNT, but with very low /ON < 1 nA.18 Carbon materials have many advantages - small effective masses, small and direct bandgap, excellent electrostatic control possible in ultra-thin structures - so they could therefore be the best material choice. Graphene has similar properties as CNTs but with planar processing compatibility. However, only theoretical studies have been performed so far. The high potential for graphene nanoribbons or bilayers have been shown by simulation:19 / 0 N ~ hundreds of цА/um, / 0 FF ~ few рА/цт, SS = 20 mV/dec, EG = 200-300 meV, / ON //OFF > Ю3 at VD = 0.1 V, but these results have not been confirmed experimentally up to now. The best trade-off obtained by simulation for complementary TFET performance has been shown with Ge/InAs TFETs, leading to an increase if/ON by a factor of several hundred compared to all-Si TFETs.20

Challenges and Limits for Very Low Energy Computation

55

However, it is worth stressing that to date the best experimental TFET performance has been obtained with Si-based TFETs and that all experimental results are very poor compared to numerical simulations. No experimental TFET demonstration with / 0 N > 100 цА/цт and SS < 60 mV/dec has been reported thus far. Simulation comparisons have been carried out between CMOS and TFET inverters. The heterostructure Ge/InAs TFETs showed the most abrupt transition from 1 to 0 state with the highest differential gain and best noise margins. However, the capacitance properties of TFETs lead to an enhanced Miller effect, with larger effective load capacitance and increased delay time. As a result, the best power-delay product still belongs to CMOS over Si or Ge/InAs TFETs.21 Instead, TFETs seem to do better in energy efficiency for applications at frequencies lower than 1 GHz, as shown in Fig. 7.22 3.

Conclusions

Reducing power consumption is the most important challenge for future IC generations. In order to overcome this dramatic challenge, new physics, materials and device structures are required. This will enable to continue scaling and performance improvement. Multi-gate NW MOSFETs with volume inversion (especially with Si or strained Si) lead to the best short channel effects, SS, / 0 FF, ^DD, P, and £ min for MOSFET architectures. Tunnel FETs are the best small slope switches up to now, with BTBT allowing for SS < 60 mV/dec subthreshold swing, obtained by simulation and experimental results. Tunnel FETs simulations show promise for very good SS, substantial VDD reduction and high / 0 N but additional process improvements are needed to improve real device performance.

1.E-15 —5

> , 1.E-16 en Ф Ш

1.Е-17 1.E-18 1.E-02

1.E-01

1.E+O0

1.E+01

Performance (GHz) Figure 7. Comparison of energy-frequency trade-off between CMOS and TFET.

56

Future Trends in Microelectronics

Heterostructure TFETs (with Ge or III-V) could be viable solutions for / 0 N > 100 (lA/jim, /ON/^OFF > Ю5 and FDD < 0.5 V with improving the technology. However, while all-silicon TFETs have shown theoretically the lowest / 0 FF and poor /0N, they have offered the best experimental performance to date, better than heterostructure TFETs. Performance boosters require a good design, the best choice of materials, and integration on Si platforms. It is also worth noting that the variability of TFETs compared to standard CMOS is reduced for doping or gate length fluctuations, but is increased as a function of the high-к gate process, the abruptness of doping at the tunnel junction, and the film thickness in ultra-thin body devices. Tunnel FETs promise a better energy efficiency at low or moderate performance level. They are ideally suited so far for low-power and low standby power at moderate / on the order of hundreds of MHz. Other possible TFET applications include: low-power SRAM (6T and 4T cells), with a strong reduction of leakage at low KDD; high-temperature switching due to the temperature independence of / 0 N and SS; ultra-low-power analog ICs with enhanced temperature stability. The biggest challenge is the improvement of / 0N without degrading / 0 FF, with SS < 60 mV/dec for more than 4 decades of drain current. For that purpose, many technology boosters are needed together with a substantial improvement of the technology. The heterostructure TFET offers the best performance for complementary logic in UTB or NW platforms, and can be considered as an addon ultra-low-power device option on advanced CMOS platforms. Acknowledgments The Sinano Institute Members and the Nanosil and Nanofunction European Networks of Excellence Partners are acknowledged.

Challenges and Limits for Very Low Energy Computation

57

References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14.

15.

L. Chang, "Practical strategies for power-efficient computing technologies," Proc. IEEE 98,215 (2010). S. Hanson, M. Seok, D. Sylvester, and D. Blaauw, "Nanometer device scaling in subthreshold logic and SRAM," IEEE Trans. Electron Dev. 55, 175 (2008). F. Balestra, J. Brini, and P. Gentil, "Deep depleted SOI MOSFETs with back potential control: a numerical simulation," Solid State Electronics 28, 1031 (1985). J. P. Colinge, "Subthreshold slope of thin-film SOI MOSFETs," IEEE Electron Dev. Lett. 7, 244 (1986). F. Andrieu, O. Weber, J. Mazurier, et al., "Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20 ran low power CMOS and beyond," Tech. Dig. VLSISymp. (2010), no. 5556131. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Doublegate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Dev. Lett. 8,410 (1987). E. Rauly, O. Potavin, F. Balestra, and C. Raynaud, "On the subthreshold swing and short channel effects in single and double gate deep submicron SOI MOSFETs," Solid State Electronics 43,2033 (1999). A. Bansal, B. C. Paul, and K. Roy, "Impact of gate underlap on gate capacitance and gate tunneling current in 16 nm DGMOS devices," Proc. IEEE Intern. SOI Conference (2004), pp. 94-95. C. Dupré, A. Hubert, S. Becu, et al., "15nm-diameter 3D stacked nanowires with independent gates operation: OFET," Tech. Dig. IEDM (2008), no. 4796805. M. Luisier, M. Lundstrom, D. A. Antoniadis, and J. Bokor, "Ultimate device scaling: Intrinsic performance comparisons of carbon-based, InGaAs, and Si FETs for 5 nm gate length," Tech. Dig. IEDM (2011), no. 6131531. F. Mayer, C. Le Royer, J.-F. Damlencourt, et al., "Impact of SOI, SÍ!.xGexOI and GeOI substrates on CMOS-compatible tunnel FET performance," Tech. Dig. IEDM (2008), no. 4796641. A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T.-J. King Liu, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages," Tech. Dig. IEDM (2008), no. 4796643. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "A compact capacitor-less high-speed DRAM using field effect-controlled charge regeneration," IEEE Electron Dev. Lett. 33, 179 (2012). T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, "Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and « 60 mV/dec subthreshold slope," Tech. Dig. IEDM (2008), no. 4796839. J. Brini, M. Benachir, G. Ghibaudo, and F. Balestra, "Subthreshold slope and threshold voltage of the volume inversion MOS transistor," IEE Proc. G: Circ. Dev.Syst. 138, 133(1991).

58

Future Trends in Microelectronics

16. F. Conzatti, M. G. Pala, D. Esseni, E. Bano, and L. Selmi, "A simulation study of strain induced performance enhancements in InAs nanowire tunnel-FETs," Tech. Dig. IEDM (2011), no. 6131492. 17. G. Dewey, B. Chu-Kung, J. Boardman, et al., "Fabrication, characterization and physics of III-V heterojunction tunneling FET for steep subthreshold swing," Tech. Dig. IEDM (2011), no. 6131666. 18. J. Appenzeller, Y. Lin, J. Knoch, and Ph. Avouris, "Band-to-band tunneling in carbon nanotube field-effect transistors, Phys. Rev. Lett. 93, 193805 (2004). 19. G. Fiori and G. Iannaccone, "Ultralow-voltage bilayer graphene tunnel FET," IEEE Electron Dev. Lett. 30, 1096 (2009). 20. A. M. lonescu, L. De Michielis, N. Dagtekin, et al., "Ultra low power: Emerging devices and their benefits for integrated circuits," Tech. Dig. IEDM (2011), no. 6131563. 21. A. M. lonescu and H. Riel, "Tunnel field-effect transistors as energy-efficient electronic switches," Nature 479, 329 (2011). 22. H. Kam, T.-J. King-Liu, E. Alon, and M. Horowitz, "Circuit-level requirements for MOSFET replacement devices," Tech. Dig. IEDM (2008), no. 4796715.

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Getting Rid of the DRAM Capacitor N. Rodriguez and F. Gamiz Dept. of Electronics, University of Granada, 18071 Granada, Spain S. Cristoloveanu IMEP-LA HC/Minatec, Grenoble-INP, 3 parvis Louis Néel, Grenoble, France

1.

Introduction

Since the early days of the DRAM memory, it has been clear that its integration in the rapidly evolving CMOS process would be increasingly difficult.1 However, DRAM has survived for more than 40 years by overcoming the scaling issues faced at each technology node. Nowadays, with 20 nm-class DRAM in production, future scalability of this technology is more in question than ever. Integration of sufficient capacitor area, charge transfer from the storage node into the bit line, and leakage current are major issues pushing towards a paradigm shift.2 The suppression of the external storage capacitor, which simplifies the cell architecture while maintaining fast charge transfer in a single transistor, is a topic attracting high interest. Several single-transistor DRAM variants (lT-DRAMs) have been proposed during the past ten years as candidates for DRAM replacement. "8 Some of them have outperformed the standard DRAM in terms of real estate or operation speed, but none of them has become a serious alternative demonstrating simultaneously low variability, immunity to cell disturbance issues and scalability.9 In this chapter we will review the history and recent developments of ITDRAM cells, which focus on the architectural and conceptual modifications of the standard MOS transistor for better control of the charge stored in the body of the device and larger current ratio between memory states. Dedicated body topology, different doping polarities, underlapped gate regions and the introduction of SiGe layers are examples of the directions that IT-DRAM research has followed in recent years.

2.

Origins of floating-body lT-DRAMs

The introduction of silicon-on-insulator (SOI) technology entailed the rise of a new set of MOSFET devices featuring characteristics not seen in bulk technology.10'11 Beyond its intrinsic radiation hardness, SOI MOSFETs present superior electrostatic integrity, reduced random dopant fluctuations and marginal floatingbody effects (FBE). Initially, FBE were associated only with partially-depleted (PD) SOI transistors; in those devices, the undepleted region of the body can 59

60

Future Trends in Microelectronics

collect extra majority carriers. The charge accumulated in this "neutral" region affects the electrostatic potential of the transistor body, resulting in threshold voltage Vj variations. For a given bias on the transistor source, drain, gate and substrate terminals, a threshold voltage shift immediately translates in a different level of drain current /D. Therefore, 0 and 1 memory states correspond to "low" and "high" /D, respectively, leading to the development of floating-body singletransistor DRAM cells (FB-lT-DRAMs). In the next paragraphs we will briefly review the history of these devices. In 1990, a new phenomenon named multistable charge-controlled memory (MCCM) with potential application in the memory field was reported in zone melting recrystallization (ZMR) SOI technology12 with silicon-film thickness of 450 nm. The back-gate of the SOI transistor, below the buried oxide (BOX), was biased negatively in accumulation, as shown in Fig. 1, whereas the front-gate VG was biased close to the threshold voltage VT. When the drain VD was scanned from zero to 7 V, the output characteristics differed drastically between the first and subsequent scans, as seen in Fig. 2. The different levels of drain current / D are due to the modulation of the accumulated charge at the back interface. Initially, when the back-gate is biased negatively (starting from a thermodynamic equilibrium state at VBG = 0)> the back interface is supposed to accumulate holes. But the only source of holes is the junction leakage current, which is a relatively slow mechanism. As a result, the back interface of the transistor remains in deep depletion, decreasing the potential of the top interface and preventing the formation of the inversion channel - see Fig. 1(b). However, as F D is increased, the few electrons available in the subthreshold current can eventually trigger the impact ionization mechanism:10'13 when VD is high enough, electron-hole pairs are generated at the drain edge of the channel.

Figure 1. (a) Schematic cross section of an SOI NMOSFET. (b) The back-gate is biased to a negative voltage and the front gate is biased slightly above the threshold voltage. When the drain bias is immediately increased the holes have no time to accumulate at the back interface and the concentration of electrons at the frontinterface remains low. (c) If the impact ionization mechanism is triggered, holes are quickly accumulated increasing the potential at the front interface and therefore the current level.

61

Getting Rid of the DRAM Capacitor


0 and VG2 < 0. To write "1", the cathode FK is briefly ramped down to ground and then back to FDD while VG2 is simultaneously ramped up to ground and then back to VG2 < 0. These pulses cause sufficient electron injection from the cathode in to the space beneath gate G2 to turn on the device through positive feedback, and upon return to the hold state an accumulated hole density is stored under G2, which constitutes state "1". To write "0" (from the hold state), gate G2 is briefly grounded so that the stored holes are discharged to ground through the cathode. To read the cell, the cathode is grounded and the current through the anode is monitored: for a carefully selected VDDA value, the presence of stored holes beneath G2 keeps the device in a low impedance state and thus IA will flow (i.e., Rl), whereas the absence of stored holes keeps the device in the high impedance state with small IA (i.e., R0). Figure 3 shows an example of a W0/H0/R0/R1/H1/R1 timing sequence for a typical (nonoptimized) FED cell, where the proper functionality of the cell is clearly demonstrated and the on/off margin is about ten orders of magnitude. Figure 4

Anode voltage VA (V) Figure 2. Simulated anode current-voltage (IA vs. VA) characteristics of a "standard" FED with 100 nm gate lengths and varying gap length in the range 10-50 nm. The SOI film thickness is 20nm and the doping p-type ~ 1016 cm"3. The ON, OFF, and "break-over" regions of operation are all seen very clearly. Note that the forward breakdown voltage VFB is only minimally dependant on the gap length, implying that from the operation point of view the gates can be spaced as closely as allowed by the photolithography.

76

Future Trends in Microelectronics

shows that once written, "1" may be repeatedly read out without any degradation, and Fig. 5 shows that "0" is also characterized by a long ~1 s retention time. Several other operation modes have been identified, similar to TCCT-based memory cells. 3 2.5 2 >. 1.5

1E-02 1E-05

1E-08 - 3 c

Ш

1 o 0.5 0 > -0.5 -1 -1.5 0.00E+00

^

TO

1E-11

1.00E-07

2.00E-07

1E-14 1E-17 3.00E-07

Ф

t

3

O

Time (s) Figure 3. Typical (non-optimized) timing diagram of FED memory cell operation for the W0/H0/R0/W1/H1/R1 sequence: relevant bias waveforms (left) and resulting current (right). Anode voltage VA = VQ1 = 1.2 V.

3 2.5 2 1.5 1

0.01 1E-05

1E-08 .< c

Ф 0 5 O) ^

1E-11

So

o > 0.5 -1 -1.5

0.00E+00

^

1E.14

7.00E-08

1.40E-07

2.10E-07

Time (s)

2.80E-07

Ф Ï

5

Ü

1E-17

Figure 4. The store " 1 " mechanism (i.e., hole accumulation beneath negatively biased gate G2) leads to state " 1 " retention for as long as power is on.

Physics and Design of Nanoscale Field Effect Diodes

77

Figure 5. State "0" retention characteristics: due to various leakage mechanisms, especially in the reverse-biased cathode diode, "0" state is retained up to ~1 s. 3.

FED as an ESD protection element

The electrostatic discharge protection (ESD) of integrated circuits is facing great new challenges with shrinking technology, as the same amount of electrostatic energy must be discharged in ever decreasing chip dimensions. These challenges are even greater for SOI chips because of the presence of the BOX (which, ironically, is the source of the many advantages of SOI technology compared to bulk Si). This is because the BOX leads to increased self-heating on one hand and precludes the use of common protection elements such as vertical diodes and silicon controlled rectifiers (SCRs) on the other. A particularly worrisome concern for high-speed operation is the inevitable ESD capacitive loading of the chip, which for 20 Gbits/s must be kept below 100 fF. To meet some of these challenges, the properties of the FED structure where further investigated; it turned out that FEDs are especially suitable as a "local clamping" ESD device for charged device model (CDM) input protection (Fig. 6), because of their high current handling capability, low capacitance and fast operation. Our first attempt at exploiting the FED for ESD applications in its original form (Fig. 1) had already demonstrated its potential,5 although we found there that in order to achieve proper operation, a bias voltage source of higher value than that of the supply voltage KDD was needed. This led to a detailed study and further optimization of the FED, where the doping under gates Gl and G2 is controlled separately.10 This made possible the design and fabrication11 of ap+/p~/UVT/n+ FED structure with ap-type high threshold voltage region under G2, shown in Fig. 7 (as well as ap+/ri~fH.VT/n+ version with и-type doping under Gl, not shown). Simulated characteristics of this structure10 demonstrated that correct operation is obtained at reasonable bias levels, a fact that was later experimentally confirmed,11 as seen in Fig. 8.

Future Trends in Microelectronics

78

Figure 6. Circuit schematic showing the use of a FED as a charged device model (CDM) ESD input protection device.5,11

Figure 7. FED structure with independently doped regions under the two gates, leading to improved ESD performance at lower bias levels.10,11

1.0E-01

c

Ш

zs o

-e-o

1.0E-04 . -»-0.5 V 0.8 V -♦-1.0V 1.0E-07 • -«-1.2V

JÉP^J i

J$

I

T I

1

CD x> 1.0E-10 i&^kJ*M* o c


0 floods the channel with electrons, promoting interband tunneling in the Ge drain-channel junction, (c) /D( VG) transfer characteristics at VD = -0.2 to -0.8 V in 0.2 V steps. At VG = 0.1 V, /0N reaches ~ 100 nA (~2 uA/um as normalized to NW diameter). Dashed line indicates SS = 60 mV/decade. Inset shows a top-gated device, (d) Simulated b{VG) characteristics at VD = -0.2 to -0.8 V in 0.2 V steps, showing reasonable agreement with experimental data.

3. Bipolar-enhanced TFET: BET-FET As discussed above, TFETs based on low EQ channel materials and multi-gate architectures have been demonstrated with improved / 0 N, but still 2-3 decades lower than that of Si MOSFETs. Since the tunneling current is low, can an internal amplification mechanism come to the rescue? Here, we propose a high-performance device named the bipolar-enhanced tunneling FET (BET-FET), where the Si/Sii.xGex HBT is combined with a gatecontrolled tunneling junction. Previously, a multi-emitter HBT with an Esaki tunnel diode supplying the base current had been demonstrated for enhanced logic functionality.24 In the BET-FET, the tunnel diode base contact is replaced by a TFET region in the reverse-biased collector-base (CB) junction. The tunnelinggenerated holes flow to the base-emitter (BE) junction, forward-biasing it and leading to effective electron injection from the emitter. Due to the bipolar

Sharp-Switching CMOS-Compatible Devices with High Current Drive

85

amplification, our simulated device shows both high / 0 N and low SS over a much wider range of current than a standard TFET.25 Figure 3(a) shows the simulated vertical BET-FET device structure, which is symmetrical and has a short sidewall gate close to the source.26 Both source and drain are heavily «+-doped Si (1020 cm"3) and used as collector and emitter, respectively. A/?+-type Sii.xGex layer with doping concentration of 2x1019 cm"3 is placed above the drain and used as the base, albeit without any direct base contact. The vertical w+-Si source/p+-Si].xGex base/«+-Si drain structure forms an HBT, biased in the conventional way with the source grounded and the drain forward biased (VD< 0). The reverse-biased collector-base junction is used as tunneling junction controlled by the sidewall gates through a 1 nm thick equivalent oxide. The tunneling layer beneath the gate is 10 nm Sii.xGex, of which the upper 5 nm layer is heavily doped. It is separated from the base by an undoped Si buffer layer for reducing the ambipolar tunneling leakage as in optimized TFETs.27 The operating principle of the BET-FET is illustrated in Fig. 3(b). In the offstate, at low \VG\, there is no tunneling current at the CB tunnel junction and hence no base current, leading to negligible emitter-collector current as in a floating-base HBT.24 As \VG\ increases, the hole current (7P) generated in the tunneling CB junction flows to the BE junction and forward biases it, like a standard base current. A high electron current (/„) is then injected from the emitter into the base and subsequently drifts to the collector as in a normal HBT, see Fig. 3(b). Figure 4(a) shows the ID(VG) characteristics of the BET-FET at VD = -1.5 V with Ge content x = 0.3 in both base and tunneling layer. For comparison, a conventional vertical TFET with the same tunnel layer structure as in Fig. 3(a) but a/7+-Si doped drain was also simulated. The difference between the BET-FET and the TFET results from the bipolar amplification, which validates our concept.

Figure 3. (a) The simulated device structure has the following layer sequence: n+doped Si collector: Т00ц= 20 nm; Si^Ge* tunneling layer: 7"tun= 10 nm of which 5 nm is n+-doped; undoped Si buffer layer: 7"bJf= 40 nm; p-doped Si^Ge« base: 7"base = 15 nm; and n+-doped Si emitter: 7"emit= 30 nm. The source stripe width L = 50 nm. (b) Equivalent circuit of the BET-FET in the on state, dashed arrows denote hole (/p) and electron (/n) current.

86

Future Trends in Microelectronics

Figure 4. Comparisons of (a) current and (b) subthreshold swing (SS) between BET-FET and conventional TFET. Dashed line in (a) denotes the bipolar current gain that ensures the superior performance of the BET-FET.

Figure 5. Transfer lD(VG) characteristics of BET-FET vs. Ge content x in (a) the base (x= 0.3 in the tunneling layer) and (b) tunneling layer (x = 0.3 in the base).

Compared to the standard TFET, the BET-FET has much higher / 0 N > 4 mA/цт at VG = -1.5 V. The bipolar current gain of BET-FET is modest under low / D due to the carrier recombination in base-emitter junction, and ramps up rapidly as / D increases. The highest current gain (> 103) is achieved at / D ~ 0.1 mA/um and then decreases due to high injection, as in a standard HBT. Figure 4(b) compares the SS values in BET-FET and TFET: the conventional TFET exhibits SS < 60 mV/dec over a limited two-decade range of /D, the BET-FET has low SS over 7 decades of current. The superior performance of the BET-FET arises from both the bipolar current gain and the BTBT current, affected by the Ge content x in Sii_xGex base and tunneling layers, respectively. Figure 5(a) shows that the increase of x from 0 to 0.3 in the base enhances the current gam and / 0 N- Higher Ge content x in the tunneling layer, on the other hand, increases the tunneling current and reduces the threshold voltage, thanks to the bandgap narrowing, see Fig. 5(b). Figure 6(a) shows an asymmetric planar BET-FET variant, with a Si/Si0.7Ge0.3 HBT at the drain (rbase = 15 nm, p-doped to 2xl0 19 cm"3) and a gatecontrolled tunneling junction at the source. The simulated gate length LQ was 50 nm, with 25 nm nitride spacers, and a 1 nm equivalent gate oxide thickness. The

Sharp-Switching CMOS-Compatible Devices with High Current Drive

87

Figure 6. (a) A variant of BET-FET with planar compact layout, showing the tunneling hole and injected electron currents, (b) Simulated lD(VG) curves for VD = - 1 and-1.5 V.

corresponding simulated /DC^G) curves for VD = -1 and -1.5 V are shown in Fig. 6(b). Again, the device provides high / 0 N > 1 mA/um and SS < 60 mV/dec over a large current range. The same device concept can also be exploited in III-V heterojunctions that are often employed for high-performance HBTs. 4.

A feedback-based high-current sharp-switching device: Z2-FET

Another route towards CMOS-compatible high-current sharp-switching devices is the use of positive feedback devices, such as thyristors,2 FB-FETs,4'8 and multiple-gated FEDs.9'28 A number of these devices have shown promising performance, with sharp switching and high / 0 N, but compact CMOS-compatible versions still face various challenges. Thus, SOI-based compact thyristors using two coupled bipolar transistors triggered by impact ionization are quite temperature-sensitive and require precise doping control in the channel to obtain stable performance.29 The FB-FET, utilizing the feedback between carrier flows and their injection barriers, does not use impact ionization or channel doping, but suffers from the poor controllability of the surface charge that forms the injection barriers. The FED, though using two front gates instead of surface charge for better controllability, faces challenges in fabricating two adjacent front gates. Here, we discuss another feedback device with an intrinsic channel, which uses a single front gate and a back gate. The device is named the Z2-FET30 and exhibits ultra-sharp switching (near-zero subthreshold swing), high / 0 N at operating voltages below 2 V, and gate-controlled hysteresis in the output characteristic that is potentially useful for compact refreshable capacitorless memories.31 The Z2-FET is a forward-biased p-i-n diode with the intrinsic channel partially covered by the front gate (I G ) and the rest ungated (LIN), schematically shown in Fig. 7(a). The device has the same layout structure and fabrication process as the asymmetrical TFET used for reducing the ambipolar tunneling leakage current.27 For the p-type Z2-FET, the p+ source is grounded and the n drain is negatively

88

Future Trends in Microelectronics

biased (Vs= 0, FD< 0). The negatively and positively biased front and back gates (Va< 0, FBG> 0) form electron and hole injection barriers in the LG and Lm regions, respectively, blocking or enabling carrier flow in the forward-biased/?-/-« structure. This biasing scheme emulates a virtual plnlpln thyristor even though the body is undoped. Experimental /D(PD) measurements show that the device is initially in a low-current state at low |KD| and switches on sharply as |KD| increases beyond a turn-on voltage |F 0 N|- As |FD| is swept back to 0, the device stays in the high / 0 N state until |KD| decreases below 0.8 V, at which point it turns off. Since F 0 N is linearly dependent on VG, a large hysteresis is obtained, see Fig. 7(b). The transfer / D ( ^ G ) characteristic also shows sharp switching, where the current increases by 8 decades within a narrow AVC = 1 mV range at VD = -1.5 V, see Fig. 8(a). The switching threshold can be tuned by biasing the VD with grounded Vs (solid curves) or V$ with grounded VD (dashed curves). Compared to other sharp-switching devices, such as the FB-FET, TFET, and impact ionization MOS (IMOS), 32 the Z2-FET shows superior switching performance under reasonably low FDD = 1.5 V supply voltage, see Fig. 8(b).

Figure 7. Schematic structure of the (a) p-type Z2-FETs operating with backgate voltage VBG > 0. (b) Its experimental /D( VD) curves show sharp switching and gatecontrolled hysteresis. The device parameters are Tox = 3 nm Hf0 2 , TSi = 20 nm, TBOX =

1 4 5 nm

> "Í-G = 400 nm and Lm = 500 nm.30

Figure 8. (a) Experimental lD(VG) curves of the p-type Z2-FET show sharp switching with subthreshold swing below 1 mV/decade. The / 0 N exceeds 500 pA/um at VD = -1.5 V. The threshold voltage is determined by the relative biasing of drain and source, (b) Comparison between Z2-FET and other reported sharp-switching devices, including the FB-FET,4 TFET,6 and IMOS.32

Sharp-Switching CMOS-Compatible Devices with High Current Drive

89

Figure 9. (a) Simulated lD{VD) curves reproducing the experimental results in Fig. 7(b). (b) Simulated channel potential of device under three different VD = 0, -1.5, and - 2 V, with constant VG = - 2 V and VBG = 2 V. Arrows indicate the injection of electrons and holes over the relevant barriers.

The Z2-FET device operation is most easily appreciated via TCAD simulations. Figure 9(a) shows the simulated ID(VD) curves under different VG reproducing the p-type Z2-FET experimental results in Fig. 7(b). Including impact ionization has no effect, as shown by the dots in the VG = -2 V curve, confirming that the operation of Z2-FET does not involve impact ionization. Figure 9(b) shows the potential in the channel of the device in Fig. 7(a) as a function of V0 for fixed VG = -2 V and VBG = 2 V. As \VD\ is increased, the electron injection barrier Vn is reduced, increasing injection, until at VD = V0u a sufficiently high electron current is injected to reduce the hole barrier Vr This, in turn, permits hole injection and establishes the positive feedback, leading the device to switch sharply to the / 0 N state. This feedback markedly reduces the electron and hole barriers, as shown in Fig. 9(b) for FD= -2 V. Once the barriers are collapsed, there is a high-density electron-hole carrier plasma in the channel, leading to high / 0 N, as in regular forward-biased p-i-n diodes. The agreement with experimental data is quite good, see Fig. 7(b). Our simulations show that, if built in an advanced SOI structure with ultrathin active layer and buried oxide, the Z2-FET is scalable down to LG = ZIN = 30 nm.33 Besides, thanks to the good reliability and gate-controlled hysteresis, the Z2-FET has also been used as both single-transistor dynamic random-access-memory (DRAM) and static RAM (SRAM) with high access speed.31 5.

Conclusions

This chapter has covered several CMOS-compatible sharp-switching devices with higher current drive than conventional Si TFETs, that can potentially supplement or replace CMOS FETs for future low-power applications. Thus, TFETs with Sio.65Geo.35 channels have been fabricated on SOI substrates and exhibit / 0 N ~ Ю times higher than a comparable all-Si TFET, due to the lower bandgap of Sio.65Geo.35. A further enhancement of the / 0N in TFET has been achieved by

90

Future Trends in Microelectronics

utilizing a tri-gate structure built on Si/Ge heteronanowires to enhance the tunneling electric field. In order to obtain an / 0 N competitive with MOSFETs, the BET-FET has been proposed, combining a TFET with an HBT. Thanks to the sharp switching behavior of TFET and high current drive of HBT, the BET-FET exhibits SS < 60 mV/dec over many decades of current and / 0 N > 4 mA/um in TCAD simulation. Another new, compact sharp-switching device we have named the Z2-FET has been demonstrated experimentally, using a fully CMOScompatible SOI fabrication process. The Z2-FET has simple structure with an intrinsic channel and a single front gate, and shows very high /ON/^OFF > Ю8 ratio and a near-zero subthreshold swing SS < 1 mV/dec. The operation of the Z2-FET, as confirmed by TCAD simulations, involves positive feedback between carrier flow and gate-controlled injection barriers, with no need for impact ionization, enabling good temperature stability and reliability. As a result of its good reliability and gate-controlled hysteresis, the Z2-FET may find applications in high-speed and compact memories. Acknowledgments The work at Minatec was funded by the RTRA program of the Grenoble Nanosciences Foundation. A. Zaslavsky also acknowledges support by the U.S. National Science Foundation (awards ECCS-1068895 and DMR-1203186). Another author (CLR) also acknowledges support by the European STEEPER project (FP7/2007-2013, grant agreement n° 257267). The heteronanowire epitaxy was carried out at the Center for Integrated Nanotechnologies, a U.S. Department of Energy, Office of Basic Energy Sciences user facility at Los Alamos National Laboratory (Contract DE-AC52-06NA25396) and Sandia National Laboratories (Contract DE-AC04-94AL85000).

References 1. 2. 3. 4. 5.

G. E. Moore, "Cramming more components onto integrated circuits," Proc. /£££86,82(1998). M. Shur, Physics of Semiconductor Devices. Englewood Cliffs, N.J.: PrenticeHall, 1990. A. C. Seabaugh and Q. Zhang, "Low-voltage tunnel transistors for beyond CMOS logic", Proc. IEEE 98,2095 (2010). A. Padilla, C. W. Yeung, C. Shin, C. Hu, and T. J. K. Liu, "Feedback FET: A novel transistor exhibiting steep switching behavior at low bias voltages," Tech. Dig. /££>M(2008), pp. 171-174. W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, "Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec," / £ £ £ Electron Dev. Lett. 28, 743 (2007).

Sharp-Switching CMOS-Compatible Devices with High Current Drive 6. 7. 8. 9.

10. 11.

12.

13. 14. 15. 16. 17. 18. 19.

91

F. Mayer, C. Le Royer, J. F. Damlencourt, et al, "Impact of SOI, Sii.xGexOI and GeOI substrates on CMOS-compatible tunnel FET performance," in Tech. Dig. IEDM (200$), pp. 163-167. D. Leonelli, A. Vandooren, R. Rooyackers, et al., "Multiple-gate tunneling field effect transistors with sub-60 mV/dec subthreshold slope," in Proc. Ext. Abstr. SSDM(2009), pp. 767-768. C. W. Yeung, A. Padilla, T. J. K. Liu, and C. Hu, "Programming characteristics of the steep turn-on/off feedback FET (FBFET)," in Tech. Dig. VLSISymp. (2009), pp. 176-177. A. A. Salman, S. G. Beebe, M. Emam, M. M. Pelella, and D. E. Ioannou, "Field effect diode (FED): a novel device for ESD protection in deep submicron SOI technologies," in Tech. Dig. IEDM (2006), pp. 107-111. See also the chapter by Ioannou et al. in this volume. D. Kazazis, P. Jannaty, A. Zaslavsky, C. Le Royer, C. Tabone, L. Clavelier, and S. Cristoloveanu, "Tunneling field-effect transistor with epitaxial junction in thin germanium-on-insulator," Appl. Phys. Lett. 94, 263508 (2009). T. Krishnamohan, D. Kim, S. Raghunathan, and K. Saraswat, "Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and « 60 mV/dec subthreshold slope," Tech. Dig. IEDM (2008), pp. 947-949. S. Mookerjea, D. Mohata, R. Krishnan, et al, "Experimental demonstration of 100 run channel length Ino^Gao^As-based vertical interband tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications," in Tech. Dig. IEDM (2009), pp. 949-951. G. Dewey, B. Chu-Kung, J. Boardman, et al, "Fabrication, characterization, and physics of III-V heterojunction tunneling FETs (H-TFETs) for steep subthreshold swing," in Tech. Dig. IEDM(2011), pp. 33.36.31-34. B. Ganjipour, J. Wallentin, M. T. Borgstrom, L. Samuelson, and C. Thelander, "Tunnel field-effect transistors based on InP-GaAs heterostructure nanowires," ACSNano 6, 3109 (2012). S. Nakaharai, T. Tezuka, N. Hirashita, E. Toyoda, Y. Moriyama, N. Sugiyama, and §• Takagi, "Formation process of high-purity Ge-on-insulator layers by Ge-condensation technique," J. Appl. Phys. 105, 024515 (2009). S. T. Le, P. Jannaty, X. Luo, A. Zaslavsky, D. E. Perea, S. A. Dayeh, and S. T. Picraux, "Axial SiGe heteronanowire tunneling field-effect transistors," Nano Lett. 12, 5850 (2012). D. E. Perea, N. Li, R. M. Dickerson, A. Misra, and S. T. Picraux, "Controlling heterojunction abruptness in VLS-grown semiconductor nanowires via in situ catalyst alloying," Nano Lett. 11, 3117 (2011). A. S. Verhulst, W. G. Vandenberghe, K. Maex, and G. Groeseneken, "Tunnel field-effect transistor without gate-drain overlap," Appl. Phys. Lett. 91, 053102(2007). M. T. Bjòrk, J. Knoch, H. Schmid, H. Riel, and W. Riess, "Silicon nanowire tunnelmg field-effect transistors," Appl. Phys. Lett. 92, 193504 (2008).

92

Future Trends in Microelectronics

20. A. L. Vallett, S. Minassian, K. P. Kaszuba, S. Datta, J. M. Redwing, and T. S. Mayer, "Fabrication and characterization of axially doped silicon nanowire tunnel field-effect transistors," Nemo Lett. 10, 4813 (2010). 21. S. H. Kim, H. Kam, C. Hu, and T.-J. K. Liu, "Germanium source tunnel field effect transistors with record high ION^OW," Tech. Dig. VLSI Symp. (2009), vol. l,p. 178. 22. J. Nah, E.-S. Liu, K. M. Varahramyan, and E. Tutuc, "Ge-SixGei.x core-shell nanowire tunneling field effect transistors," IEEE Trans. Electron Dev. 57, 8 (2010). 23. B. Ganjipour, J. Wallentin, M. T. Borgstr6m, L. Samuelson, and C. Thelander, "Tunnel field-effect transistors based on InP-GaAs heterostructure nanowires," ACSNano 6, 3109 (2012). 24. A. Zaslavsky, S. Luryi, C. King, and R. Johnson, "Multi-emitter Si/GexSibX heterojunction bipolar transistor with no base contact and enhanced logic functionality," IEEE Electron Dev. Lett. 18, 453 (1997). 25. J. Wan, A. Zaslavsky, C. Le Royer, and S. Cristoloveanu, "Bipolar-enhanced tunneling FET (BET-FET) with high / 0 N > 4 mA/um," IEEE Electron Dev. Lett. 34,24 (2013). 26. Simulations used Sentaurus TCAD simulator with dynamic nonlocal tunneling model. 27. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "Tunneling FETs on SOI: Suppression of ambipolar leakage, low-frequency noise behavior, and modeling," Solid-State Electronics 65-66, 226 (2011). 28. Y. Yang, A. Gangopadhyay, Q. Li, and D. E. Ioannou, "Scaling of the SOI field effect diode (FED) for memory application," Proc. Intern. Semicond. Dev. Res. Symp. (2009), pp. 1-2. 29. K. Yang, R. Gupta, S. Banna, et al, "Optimization of nanoscale thyristors on SOI for high-performance high-density memories," Proc. Intern. SOI Conf. (2006), pp. 113-114. 30. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "A feedback silicon-on-insulator steep switching device with gate-controlled carrier injection," Solid State Electronics 76, 109 (2012). 31. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "A compact capacitor-less high-speed DRAM using field effect-controlled charge regeneration," IEEE Electron Dev. Lett. 33, 179 (2012). 32. F. Mayer, C. Le Royer, G. Le Carval, C. Tabone, L. Clavelier, and S. Deleonibus, "Co-integration of 2 mV/dec subthreshold slope impact ionization MOS (I-MOS) with CMOS," Proc. ESSDERC (2006), pp. 303-306. 33. J. Wan, C. Le Royer, A. Zaslavsky, and S. Cristoloveanu, "Z2-FET: A zeroslope switching device with gate-controlled hysteresis," Proc. VLSI-TSA Intern. Symp. (2012), pp. 179-181.

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Magnetic Tunnel Junctions with a Composite Free Layer: A New Concept for Future Universal Memory A. Makarov, V. Sverdlov, and S. Selberherr Institute for Microelectronics, TU Wien, A-1040 Vienna, Austria

1.

Introduction

In modern microelectronic devices the dominant memory types are DRAM, static RAM, and flash memory. These types of memory store data as a charge state. For many decades these memory technologies have been successfully scaled down to achieve higher speed and increased density of memory chips at lower bit cost.1 However, memories based on charge storage are gradually approaching the physical limits of scalability and conceptually new types of memory based on a different storage principle are gaining momentum. Memories based on magnetic moment storage form an important sub-class of the non-volatile memories based on new physical principles.2 Magnetic memory technologies include magnetoresistive random access memory (MRAM), spin transfer torque RAM (STT-MRAM), and racetrack memory,3 although the latter is still in the conceptual stage. Recent advances in STT-MRAM technology makes this type of memory a promising candidate for future universal memory, combining nonvolatility, fast operation, and low power consumption. In this chapter, we will focus our attention on MRAM and STT-MRAM. 2.

Magnetic memory technologies

The basic element of an MRAM is a sandwich of two magnetic layers separated either by a nonmagnetic metal in giant magnetoresistance (GMR) devices, or by a thin insulating oxide in magnetic tunnel junction (MTJ) devices - see Fig. 1. While the magnetization of the pinned layer is fixed due to the fabrication process, the magnetization direction of the free layer can be switched between the two states parallel and anti-parallel to the fixed magnetization direction.

Figure 1. Schematic illustration of a three-layer MTJ in a high-resistance state (left) and low-resistance state (right).

93

94

Future Trends in Microelectronics

Figure 2. Schematic illustration of the free layer with an "in-plane" magnetization (left) and "perpendicular" magnetization direction (right).

Depending on the orientation of the magnetizations the magnetic pillars can be divided into two categories: "in-plane" with magnetization lying in the plane of the magnetic layer and "perpendicular" with out-of-plane magnetization direction. In a conventional field-driven MRAM cell, switching the magnetization of a free layer is performed by applying a magnetic field. In contrast to field-driven MRAM, STT-MRAM does not require an external magnetic field. Instead, switching between the two states occurs due to spin transfer torque arising from the spin-polarized current flowing through the pillar. The theoretical prediction of the spin transfer torque effect was made independently by Slonczewski and Berger.4'5 When electrons pass through the thick magnetic layer, the spins of the electrons become aligned with the magnetization of the fixed layer. When these spinpolarized electrons enter the free layer, their spin orientations align with the magnetization of the free layer within a transition length of a few À. Because of their spin reorientation, they exert a torque on the magnetization of the free layer, which can cause magnetization switching, if the torque is large enough to overcome damping. Smaller torque values result in magnetization precession around the effective magnetic field. The spin-polarized current is only a fraction of the total charge current flowing through the device. Therefore, high current densities from ~107 to ~108 A/cm2 are required to switch the magnetization direction of the free layer, and the reduction of this current density is the most important technological challenge in this area. Switching of the magnetization can occur not only under the influence of the spin-polarized current, but also spontaneously, due to thermal fluctuations - see Fig. 2. This is an unwanted event that leads to the loss of stored information. Thus another important parameter of MRAM (STT-MRAM) is the thermal stability factor, defined as the ratio of the thermal stability barrier to the operating temperature. The thermal stability factor APERP6'7 for perpendicular MTJs (p-MTJs) is given by the interface-induced perpendicular anisotropy field Якрегр as _М,-(ЯГ-4ЯМ,)-У

m

Magnetic Tunnel Junctions with a Composite Free Layer

95

where M s is the saturation magnetization, V is the volume of the free layer, and kB is the Boltzmann constant. To increase the thermal stability factor it is sufficient to increase the cross-section of p-MTJs. However, due to domain formation, this is limited to approximately 70 nm diameter, and therefore increasing the thermal stability factor of p-MTJs above -40-50 remains a challenge.8 In p-MTJs the switching paths by spin transfer torque and thermal agitation are the same, as shown in Fig. 2 (right). Thus, the critical switching currents for pMTJs are proportional to the thermal stability factor. The thermal stability factor Дшр6'7 for in-plane MTJs is determined by the shape anisotropy field Я к шр :

To increase the in-plane thermal stability factor it is sufficient to increase the thickness of the free layer and/or the aspect ratio. However, switching under the influence of the spin current follows a different path from thermal agitation switching, as shown in Fig. 2 (left). This leads to a large additional 27iMs2Kterm in the switching current: J™ ~ M s • V ■ (H? + 2KMS ) = 2к ВГДINP + 2TIMSV ,

(3)

which results in a higher critical current density compared to that in p-MTJs.6'7 Therefore, the in-plane MTJs exhibit a high thermal stability, but still require a reduction of the critical current density. Perpendicular MTJs with an interfaceinduced anisotropy show potential, but still require a reduction of damping and an increase in thermal stability. Thus, further research in new materials and architectures for MTJ structures is urgently needed. 3.

MTJs with a composite free layer

We have recently proposed a five-layer MTJ with a composite free layer.9 The composite magnetic layer consists of two half-ellipses separated by a non-magnetic spacer, as shown in Fig. 3. The magnetization of the magnetic layers lies in the plane. Compared to p-MTJs, the composite free layer his broadens substantially the range of the magnetic materials suited for constructing MTJs. Below we examine the switching characteristics of these structures.

Figure 3. Schematic illustration of the composite free layer.

96

Future Trends in Microelectronics

Thermal stability and thermal agitation switching To find the switching path due to thermal agitations it is necessary to determine the state for which the barrier separating the two stable magnetization states in the free layer is minimal. Figure 4 shows that the switching path due to thermal agitations must go through the state with magnetizations of the halves opposite to each other (the C state in Fig. 4). We investigated the influence of scaling the dimensions on the thermal stability factor for MTJs with a composite free layer. Due to the removal of the central region in the monolithic structure, the shape anisotropy is slightly decreased together with the thermal stability factor. To boost the thermal stability factor, it is sufficient to increase the thickness of the free layer and/or the aspect ratio. Figure 5 shows the thermal stability factors of MTJs with a composite free layer as a function of the free layer thickness d. An MTJ with 52.5x10 nm2 cross-section and d = 5 nm free layer thickness has a thermal stability factor -60, which exceeds all of the p-MTJs demonstrated to date.8 •

Figure 4. Dependence of the demagnetization energy for MTJs with monolithic (a) and composite (b, c) free layers as a function of the cross-sectional area.

Figure 5. Thermal stability barrier for MTJs with monolithic (left) and composite free layer (right) as a function of the short axis length for several free layer thicknesses d. The long axis is fixed at 52.5 nm; fixed layer thickness layer is 5 nm.

Magnetic Tunnel Junctions with a Composite Free Layer

97

Spin transfer torque switching Our simulations of five-layer MTJ switching are based on the magnetization dynamics described by the Landau-Lifschitz-Gilbert (LLG) equation with additional spin torque terms:10 •

^- = +

-Jïtf{(mXh*)+a{mx(mxh 300 °C and high-radiation environments due to absence of gate oxides; self-aligned CMOS is not possible in SiC due to the very high annealing temperatures required after ion implantation (1600 °C).

The process incorporates bipolar npn transistors, diodes, resistors and capacitors. With this bipolar technology any electronic function can be built (amplifiers, analog-to-digital converters, power controllers, radio electronics, and digital electronics). Sensors19 and MEMS have also been demonstrated in SiC, and could be implemented with our technology. Non-volatile memories for high temperature operation could be possible using PZT films on SiC.20"21 5.

Results

We have established a bipolar process for SiC integrated circuits and demonstrated ECL digital circuits, discrete devices and test structures. All devices and circuits were operated from room temperature up to 300°C without failure.12 Figure 3 shows that the current gain in SiC bipolar transistors is reduced at elevated temperatures, and this has to be taken into account when designing circuits. At 300 °C it is around 50% of the room temperature value. Circuit

Figure 3. Photo of manufactured bipolar test transistor, and measured current gain of discrete transistors from room temperature up to 300 °C. For size reference, contacts pads are 100 x 100 urn.

Silicon Carbide High Temperature Electronics—Is This Rocket Science?

107

Figure 4. Measured output characteristics and noise margins NM (high and low) of three different ECL or-nor gates from room temperature up to 7 = 300 °C.

simulations show that a minimum current gain of 10 is required for digital circuits, leading us to believe that 600 °C could be achieved with the current technology if the metallization is changed from the presently used aluminum. However, higher current gains are required for the analog circuitry, so higher room temperature values are aimed at in future batches. The basic building block of ECL logic is the or-nor gate with complementary outputs. Apart from characterizing these and assuring the noise margins were high enough (see Fig. 4), a ring oscillator was made using four of these gates. An odd number of inverting gates connected in a ring will oscillate spontaneously, and the fourth gate is a buffer for measuring the output frequency. Figure 5 shows the logic circuit and a chip photo of the ring oscillator. An oscillation frequency of -2-3 MHz was measured from room temperature up to T= 300 °C.12

Figure 5. Logic circuit and manufactured ring oscillator in ECL technology. The design includes 88 devices (40 transistors and 44 resistors). For size reference, contacts pads are 100 x 100 urn.

Future Trends in Microelectronics

108 6.

Conclusion

After more than 20 years of development, silicon carbide (SiC) has reached maturity and commercial availability. Since SiC can also withstand high temperatures and high levels of radiation, we propose that it is suitable for integrated electronics in space exploration. A surface lander for Venus, which has a surface temperature of 460 °C, would be an interesting challenge. Already, SiC integrated circuits have been proven up to 300 °C without failure, and preliminary radiation tests are encouraging. Even if we do not send a lander to Venus, the challenge of coping with these very harsh conditions will surely lead to to spinoffs in other high temperature electronics areas, such as jet engine monitoring, deep oil and gas drilling, and thermonuclear energy.

Acknowledgm ents Part of this work is supported by the Swedish Foundation for Strategic Research under the HOTSiC (high temperature power electronic systems with SiC ICs) contract.22 My PhD students and colleagues at KTH are acknowledged. References C.-M. Zetterling, ed., Process Technology for Silicon Carbide Devices, London: INSPEC, 2002. 2. J. Rabkowski, D. Peftitsis, and H.-P. Nee, "Design steps towards a 40-kVA SiC inverter with an efficiency exceeding 99.5%," Proc. IEEE Appl. Power Electronics Conf. (APEC) (2012), pp. 1536-1543. 3. S. Hodge, Jr., "SiC Schottky diodes in power factor correction," Power Electronics Technol. 30, 14 (2004). 4. See http://en. wikipedia. org/wiki/Venera 5. See http://www. esa. int/esaMI/Venus_Express/index. html 6. See http://www.jaxa.jp/projects/sat/planet_c/index_e.html 7. See http://www. nasa. gov/topics/solarsystem/features/venus20101119. html 8. C. F. Wilson, E. Chassefière, E. Hinglais, et al, "The 2010 European Venus Explorer (EVE) mission proposal," Exper. Astron. 33, 305 (2012) and also http://www. univie. ac. at/E VE/ 9. See http://www.federalspace.ru/main.php? id=2&nid=9948&hl~venera-d 10. See http://www. cissoid. com/ and http://www. hightempsolutions. com/ 11. C.-M. Zetterling, L. Lanni, R. Ghandi, B. G. Malm, and M. Òstling, "Future high temperature applications for SiC integrated circuits," Phys. Status Solidi C 9, 1647(2012). 12. L. Lanni, R. Ghandi, B. G. Malm, C.-M. Zetterling, and M. Óstling, "Design and characterization of high-temperature ECL-based bipolar integrated circuits in 4H-SÍC," IEEE Trans. Electron Dev. 59, 1076 (2012). 1.

Silicon Carbide High Temperature Electronics—Is This Rocket Science?

109

13. N. Lundberg, M. Òstling, C.-M. Zetterling, P. Tagtstrom, and U. Jansson, "CVD-based tungsten carbide Schottky Contacts to 6H-SÍC for very hightemperature operation," J. Electronic Mater. 29, 372 (2000). 14. S.-K. Lee, C.-M. Zetterling, E. Danielsson, et al, "Electrical characterization of TiC Ohmic contacts to aluminum ion implanted 4H-silicon carbide," Appl. Phys. Lett. 77, 1478 (2000). 15. K. Buchholt, R. Ghandi, M. Domeij, et al, "Ohmic contact properties of magnetron sputtered Ti3SiC2 on n- and p-type 4H-silicon carbide," Appl. Phys. Lett. 98,042108(2011). 16. C.-M. Zetterling, M. Òstling, N. Nordell, O. SchSn, and M. Deschler, "Influence of growth conditions on electrical characteristics of A1N on SiC," Appl. Phys. Lett. 70, 3549 (1997). 17. M. Usman and A. Hallén, "Radiation-hard dielectrics for 4H-SÍC: A comparison between Si0 2 and А12Оз," IEEE Electron Dev. Lett. 32, 1653 (2011). 18. A. Hallén, M. Nawaz, C. Zaring, M. Usman, M. Domeij, and M. Óstling, "Low-temperature annealing of radiation-induced degradation in 4H-SÍC bipolar junction transistors," IEEE Electron Dev. Lett. 31, 707 (2010). 19. I. Lundstrom, H. Sundgren, F. Winquist, M. Eriksson, C. Krantz-Rillcker, and A. Lloyd-Spetz, "Twenty-five years of field effect gas sensor research in Linkoping," Sensors Actuators B 121,247 (2007). 20. S.-M. Koo, S. Khartsev, C.-M. Zetterling, A. Grishin, and M. Òstling, "Ferroelectric Pb(Zr0.52Tio.4g)/SiC field effect transistor," Appl. Phys. Lett. 83, 3975 (2003). 21. M. Òstling, S.-M. Koo, C.-M. Zetterlmg, S. Khartsev, and A. Grishin, "Ferroelectric thin films on silicon carbide for next-generation nonvolatile memory and sensor devices," Thin Solid Films 469-470, 444 (2004). 22. See http://www.hotsic.se

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Microchip Post-Processing: There is Plenty of Room at the Top Jurriaan Schmitz MESA+ Institute for Ncmotechnology, Univ. ofTwente, Enschede, Netherlands

1.

Introduction

Microchip manufacturers have developed a tremendous skill in depositing materials at the nanometer scale. One can wonder why this skill is predominantly used to develop new generations of memory and signal processing chips. The answer lies in the economic rationale behind Moore's Law,1 implying that straightforward miniaturization is the most predictable and effective means of improving the microchip value. But today, the end of traditional scaling is in sight. According to the authoritative ITRS Roadmap,2 the miniaturization of CMOS, DRAM and flash memory technologies will end around the year 2018, at which point disruptive approaches will become necessary to further decrease the cost per function in these types of microchips. The community therefore has embarked on a massive parallel search for new technologies, employing the same microtechnology skill set, but introducing novel device architectures and novel materials. Examples are subthermal switches3 and magnetic memories such as the STT-MRAM,4 among many. Innovation in microchip technology can also involve the addition of new functionality to the chip, often denominated as "more-than-Moore". When a microchip goes beyond the traditional functions of data storage, computation and electrical communication, it may become more valuable. Usually this requires modifications to the microchip fabrication process. Such modifications are reviewed in this chapter. We will first discuss the physical location where new functions can be added to a microchip, and which considerations may lead to the above-IC approach. Then, the boundary conditions for post-processing are sketched. A variety of example microsystems is subsequently reviewed, followed by the conclusions. 2.

Adding functionality to CMOS

The standard CMOS repertoire consists of transistors, diodes, and metal wiring. It is possible to employ these in unconventional ways, e.g. by using a diode as a light-sensing element (active pixel sensors)5 or metallization for mechanical resonators6 and RF MEMS capacitive switches.7 Baltes and co-workers have explored several other functions based on this principle,8 in particular for sensing. 110

Microchip Post-Processing: There is Plenty of Room at the Top

111

Figure 1. Examples of commercialized new functions in a CMOS baseline, indicating in what physical location technology additions have been made: digital micromirrors,9 active pixel sensors (APS),5 liquid-crystal-on-silicon (LCoS),10 microemissive displays,11 surface-integrated sensors,12 integrated MIM capacitors and resistors,13 programmable fuses14 and RF inductors,15 embedded Flash,16 and phase change memories.17 Background image courtesy of Chipworks, Inc.

If the existing CMOS building blocks cannot deliver the desired added functionality, technological additions to the chip are necessary. The physical insertion point of these additions is a key design parameter. Figure 1 shows examples of added functionality in a CMOS baseline technology, indicating where the additions are made: in the front-end-of-line (the transistor level), the back-endof-line (interleaved with the interconnect layers), or above-IC (after completion of the baseline CMOS chip). All three approaches have proven both feasible and profitable. Then, how does one choose where to add the new functionality? The decisive factors include thermal budget, pattern density and geometrical considerations. For instance, a sensor should have a clear line of sight, components may interfere when placed too closely together, etc. Thermal budget In the microchip fabrication process,18 the silicon wafer receives several hundred sequential treatments. Many of these take place at elevated temperatures, such as chemical vapor deposition and impurity activation annealing. The peak temperature tends to become lower and lower in the course of the fabrication •

112

Future Trends in Microelectronics

process, as depicted in Fig. 2. Early on, the fabrication of a single-crystal Si wafer requires exceeding the Si melting point. Subsequently, the field isolation (LOCOS or shallow trench isolation) involves thermal oxidation in the 1000-1050 °C range. Then, to form highly doped regions in the material and to repair process-induced lattice damage, thermal annealing steps at up to -1000 °C are required, until the active devices are completed. The spacer deposition step (by low-pressure chemical vapor deposition) normally takes place at 700-800 °C. Formation of silicides at the silicon surface involves short anneals around 600 °C (Co, Ni, Pt) to 800 °C (Ti). Metallization is then formed on the wafer surface; the use of aluminum and/or copper as wiring material prohibits temperatures above 400-450 °C from this point onwards. Some advanced low-к dielectric materials employed in the back end may further reduce the tolerance to higher temperatures.19 In the course of the metallization sequence, the silicon surface is passivated with hydrogen (using a forming gas anneal at 400-450 °C). After completion of the interconnect and scratch protection (using plasma-enhanced chemical vapor deposition of a silicon nitride coating) the microchip is diced and packaged, in a sequence involving temperatures of 220-280 °C. Completed silicon-based microchips are commonly specified to remain functional up to 125-175 °C operating temperature. These temperature limits are indicative only, as time and gaseous ambient are also relevant, and besides they vary in different IC technologies.

Figure 2. Peak temperatures during microchip fabrication. The temperatures are indicative for CMOS manufacturing in technologies between 0.25 um and 90 nm CMOS (featuring SiON gate dielectrics, dual-flavor polysilicon gates and Si02-based intermetal dielectrics).

Microchip Post-Processing: There is Plenty of Room at the Top

113

Figure 3. Pattern density in different parts of a CMOS microchip, normalized to its feature size F. From bottom to top, we see the CMOS wells (4-5F), the isolation and transistors (1F), the lower metallization layers (1.2F) and upper metallization (2.4F). Derived from Infineon 90 nm technology.20

Pattern density A second consideration is the pattern density required for the new function. When a single component, e.g. a sensor or an inductor, should be embedded in a CMOS chip, the size of this component and its patterning tolerances may be quite relaxed. But for array configurations, such as found in active pixel sensors and embedded memories, a high pattern density may be crucial. Novel concepts emerging from nanotechnology, such as plasmonic sensing, may also require a high level of lithographic control. The pattern density inside a typical CMOS chip is sketched in Fig. 3. The data are derived from a typical 90 nm technology20 but normalized to the feature size F to represent the broader class of deep-submicron CMOS. More accurate information can be obtained from the present and previous ITRS roadmaps.2 It should be noted that vertical feature sizes tend to follow this trend: the thinnest films are (necessarily) found in the smallest-pitch areas. •

3.

Emerging microsystems

In an earlier review paper,21 I described several commercially successful microsystems realized by CMOS post-processing: the CMOS active pixel sensor, which involved the development of color filters, microlenses and dedicated packaging; micro-emissive displays featuring a stack of polymer layers on a chip; the digital micro-mirror device, with moving mirrors on top of an SRAM memory

114

Future Trends in Microelectronics

array; and liquid-crystal-on-silicon chips, also applied in image projection systems. All four have a two-dimensional array of identical elements on top of a CMOS chip laid out in a pixel array architecture. Massively parallel sensing or actuating, as takes place in these chips, yields a high-value compact system that outperforms similar systems fabricated by assembly of separate parts. The benefit is in the high-yield, low-cost fabrication of many identical elements, and in the high density of high-bandwidth, low-noise interconnections. Another factor of importance in the handheld era is the small overall volume and mass ("form factor") of the product. Inspired by these systems, we have studied the addition of several new functions to CMOS chips. For instance, we developed above-IC photonic waveguides,22 SiGe microresonators,23 and embedded thermometers for thermal budget determination.24 In this chapter I will present prototype realizations for nuclear radiation imaging, energy harvesting and plasmon generation. A miniaturized gas-filled detector for nuclear radiation imaging was developed in cooperation with the Nikhef institute in Amsterdam. Such detectors are used to create digital 2D or 3D images of radiation, and find their main application in nuclear and subatomic physics experiments. They are typically assembled from bulk materials, such as copper wires and Kapton foil; the electronic readout is separately designed and interconnection between the detector electrodes and the electronics is laborious and far from fail-safe. The miniaturized version, dubbed InGrid, was directly fabricated as an integrated grid on a readout chip organized in pixels, the Timepix chip.25 A perforated high-voltage electrode is defined 50 um above the chip surface, separated by SU-8 dielectric support posts, see Fig. 4.

Figure 4. Bird's eye SEM image of the integrated-grid (InGrid) radiation detector. Reprinted with permission from Ref. 27.

Microchip Post-Processing: There is Plenty of Room at the Top

115

This system offers granularity and sensitivity much better than existing bulkassembled detectors based on the same (proportional-chamber) principle. Additionally there is the benefit of direct digital readout. After a variety of singlechip experiments, involving different material choices, topologies and chip generations,26"29 this radiation detection system is now produced on 8" wafers at IZM Berlin for several research labs devoted to radiation imaging (the underlying 0.25 Ц.Ш CMOS chip is fabricated by IBM). Another example of adding functionality to CMOS is the implementation of self-powered microelectronic units - so-called Smart Dust concept,30 - by integrating thin-film solar cells on top of CMOS.31'32 Figure 5 shows crosssectional views of such CMOS-PV stacks, using a-Si and CIGS photovoltaic technologies. The solar cell formation was carried out in laboratories of the University of Utrecht (a-Si) and Nankai University (CIGS). Earlier work suggested using the silicon wafer itself for light energy harvesting.33'34 The drawback of this approach is that the silicon area used for energy harvesting is unavailable for electronic functions. The energy supplier and the energy consumer compete for the same space. Instead, when the solar cell is stacked on top, no area penalty is paid in the underlying CMOS. Overall this will lead to more available power, especially in indoor situations, where single-crystal Si PV cells are relatively inefficient compared to the chosen thin-film solar cells. CMOS post-processing offers excellent opportunities for a fusion of optical (and plasmonic) functionality with microelectronics, with several types of photonic integration demonstrated to date.35 By employing low-temperature chemical vapor deposition and atomic layer deposition, we fabricated a high density of Si nanodots embedded in A1203 films.36 This membrane was subsequently used to make an electrically stimulated surface-plasmon emitter at the Amolf Institute in Amsterdam. The experimental device realized is sketched in Fig. 6. Silicon nanodots were deposited at a density of ~1012 cm"2 from trisilane37 and then encapsulated in-situ by ALD alumina. Thermally evaporated gold electrodes surround the dielectric-nanodot sandwich. The patterning of the upper gold layer was achieved by focused-ion beam.

Figure 5. Cross-sectional views of a-Si and CIGS thin-film solar cells realized on top of CMOS. Reprinted with permission from Refs. 31 and 32.

116

Future Trends in Microelectronics

Figure 6. Experimental arrangement to investigate the generation of surface plasmonic waves in a CMOS backend-compatible layer stack. Several layers of CVD-deposited Si nanodots (Si-NDs) are embedded in an ALD-deposited Al 2 0 3 dielectric matrix, and surrounded by metal electrodes.

An electrical current forced through the dielectric excites the nanodots. Their excitation energy can be converted into a surface-plasmonic wave and, at some distance, coupled into free space using a grating. The metal-insulator-metal structure can in principle be fabricated in a CMOS back-end process, with the restriction that choice of metal (Au, Ag) and near-perfect flatness are essential to a large attenuation length for plasmonic waves. 4.

Conclusions

This chapter discussed the addition of new functions to CMOS chips, focusing on post-processing. We have considered the restrictions imposed by thermal budget and pattern density on the choice of where in the chip one should add the new functional devices. Then we discussed a variety of commercial and emerging above-IC microsystems. Today, semiconductor processing is now the most developed fabrication approach and offers many possibilities for the realization of tiny, high-performance electronic systems. Post-processing of CMOS microchips is an attractive approach to make systems with "more-than-Moore" functionality. It makes good use of the existing CMOS infrastructure to obtain an excellent electronic backbone, while the post-processing can be carried out in relative freedom, as long as the boundary conditions, such as thermal budget and stress containment, are properly addressed.

Microchip Post-Processing: There is Plenty of Room at the Top

117

Acknowledgments I am grateful to my co-workers at the Univ. of Twente, Nikhef, Amolf, Utrecht University, Nankai University, and the Medipix/Timepix collaboration. The Dutch Technology Foundation (STW) and the Foundation for Fundamental Research on Matter (FOM) are acknowledged for financial support. References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15.

G. E. Moore, "Cramming more components onto integrated circuits," Electronics (April 19, 1965), pp. 114-117. International Technology Roadmap for Semiconductors, 2011 edition, available at www.itrs.net See chapters on sharp-switching devices in this volume. W. Kim, J. H. Jeong, Y. Kim, et al., "Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node," Tech. Dig. IEDM (2011), pp. 531-534. E. R. Fossum, "CMOS image sensors: Electronic camera-on-a-chip," IEEE Trans. Electron Dev. 44, 1689 (1997). J. L. Lopez, J. Verd, J. Teva, et al., "Integration of RF-MEMS resonators on submicrometric commercial CMOS technologies," J. Micromech. Microeng. 19, 015002 (2009). S. P. Natarajan, S. J. Cunningham, A. S. Morris III, and D. R. Dereus, "CMOS integrated digital RF MEMS capacitors," Dig. 11th IEEE Topical Meeting Silicon Monolithic Integr. Circuits RF Systems (2011), pp. 173-176. A. Hierlemann, O. Brand, C. Hagleitner, and H. Baltes, "Microfabrication techniques for chemical/biosensors," Proc. IEEE 91, 839 (2003). P. F. van Kessel, L. J. Hornbeck, R. E. Meier, and M. R. Douglass, "A MEMS-based projection display," Proc. IEEE 86, 1687 (1998). See the special issue on LCoS technology, Displays 23, no. 3 (2002). I. Underwood, D. C. Burns, and R. J. Woodburn, "Polymer OLED microdisplay technology - pixel design in context," Proc. SPIE 6333, 633306 (2006). R. Thewes, "CMOS chips for biomolecule sensing purposes," Proc. 2nd IEEE Intern. Workshop Advances Sensors Interfaces (2007). P. Zurcher, P. Alluri, P. Chu, et al., "Integration of thin film MIM capacitors and resistors into copper metallization based RF-CMOS and Bi-CMOS technologies," Tech. Dig. IEDM(2000), pp. 153-156. E. Ebrard, B. Allard, P. Candelier, and P. Waltz, "Review of fuse and antifuse solutions for advanced standard CMOS technologies," Microelectronics J. 40, 1755 (2009). J. Burghartz and B. Rejaei, "On the design of RF spiral inductors on silicon," IEEE Trans. Electron Dev. 50, 718 (2003).

118

Future Trends in Microelectronics

16. R. Strenz, "Embedded flash technologies and their applications: Status and outlook," Tech. Dig. IEDM(2011), pp. 211-214. 17. D. Ielmini and A. L. Lacaita, "Phase change materials in nonvolatile storage," Materials Today 14, 600 (2011). 18. J. D. Plummer, M. D. Deal, and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, London: Prentice Hall, 2000. 19. G. Maier, "The search for low-e and ultra-low-e dielectrics: How far can you get with polymers? Part 2: Materials, structures, properties," IEEE Electrical Insulation Mag. 20, 6 (2004). 20. See www.infineon.com: "L90 90 nm CMOS platform technology," ordering no. B192-H9084-X-X-7600, NB07-1055. 21. J. Schmitz, "Adding functionality to microchips by wafer post-processing," Nucl. Instrum. Meth. A 576,142 (2007). 22. B. Rangarajan, A. Y. Kovalgin, K. Worhoff, and J. Schmitz, in preparation (2012). 23. S. N. R. Kazmi, A. A. I. Aarnink, C. Salm, and J. Schmitz, "CMOS-MEMS post processing compatible square plate capacitively transduced SiGe resonator," Proc. 2012 IEEE Intern. Frequency Control Symp. (IFCS-2012), pp. 580-583. 24. E. J. Faber, R. A. M. Wolters and J. Schmitz, "Novel test structures for dedicated temperature budget determination," IEEE Trans. Semicond. Manuf. 25,339(2012). 25. X. Llopart, R. Ballabriga, M. Campbell, L. Tlustos, and W. Wong, "Timepix, a 65k programmable pixel readout chip for arrival time, energy and/or photon counting measurements," Nucl. Instrum. Meth. A 581, 485 (2007) [see also erratum in: Nucl. Instrum. Meth. A 585,106 (2008)]. 26. V. M. Blanco Carballo, C. Salm, S. Smits, et al., "On the geometrical design of integrated Micromegas detectors," Nucl. Instrum. Meth. A 576, 1 (2007). 27. V. M. Blanco Carballo, M. Chefdeville, M. Fransen, et al, "A radiation imaging detector made by post-processing a standard CMOS chip," IEEE Electron. Dev. Lett. 29, 585 (2008). 28. V. M. Blanco Carballo, Y. Bilevych, M. Chefdeville, et al., "GEMGrid: a wafer post-processed GEM-like radiation detector," Nucl. Instrum. Meth. A 608, 86 (2009). 29. Y. Bilevych, V.M. Blanco Carballo, M. Chefdeville et al., "TwinGrid: A wafer post-processed multistage micro-patterned gaseous detector," Nucl. Instrum. Meth. A 610, 644 (2009). 30. B. Warneke, M. Last, B. Liebowitz, and K. S. J. Pister, "Smart dust: Communicating with a cubic-millimeter computer," Computer 34, 44 (2001). 31. J. Lu, A. Y. Kovalgin, K. H. M. van der Werf, R. E. I. Schropp, and J. Schmitz, "Integration of solar cells on top of CMOS chips. Part I: a-Si solar cells," IEEE Trans. Electron Dev. 58, 2014 (2011). 32. J. Lu, W. Liu, A. Y. Kovalgin, Y. Sun, and J. Schmitz, "Integration of solar cells on top of CMOS chips. Part II: CIGS solar cells," IEEE Trans. Electron Dev. 58,2620(2011).

Microchip Post-Processing: There is Plenty of Room at the Top

119

33. A. J. Mouthaan, "Integrated cascade of photovoltaic cells as a power supply for integrated circuits," Sensors Actuators 5,285 (1984). 34. O. Bulteel, R. Delamare, and D. Flandre, "High-efficiency solar cell embedded in SOI substrate for ULP autonomous circuits," Proc. IEEE Intern. SOI Conf. (2009), 2.5.1-2.5.2. 35. L. Fulbert and J.-M. Fedeli, "Photonics-electronics integration on CMOS," Proc. ESSDERC (2011), pp. 13-18. 36. R. J. Walters, R. V. A. van Loon, I. Brunets, J. Schmitz, and A. Polman, "A silicon-based electrical source of surface plasmon polaritons," Nature Mater. 9,21(2010). 37. I. Brunets, A. A. I. Aarnink, A. Boogaard, et al., "Low-temperature LPCVD of Si nano-crystals from disilane and trisilane (Silcore®) embedded in ALDalumina for non-volatile memory devices," Surface Coatings Technol. 201, 9209 (2007).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

EUV Lithography: Today and Tomorrow V. Y. Banine ASMLInc, Veldhoven, The Netherlands

1.

Introduction

In the last 50 years we have seen a significant paradigm shift in the employment of technology for: •

connecting different locations, e.g. land line telephones, to

•

connecting individuals, e.g. mobile phones, and to

•

connecting smart things and devices in the near future, e.g. automotive, home appliances, medical etc.

The more computational technology is embedded in our society, the higher the percentage of power consumption dedicated to it. Though evaluations differ, today server farms alone account for at least a couple of percent of electrical power

Figure 1. Moore's Law for computation per kW.3 120

EUV Lithography: Today and Tomorrow

121

Figure 2. Lithography support of device downscaling beyond 10 nm.

consumption in the United States.1'2 Scalability of the power efficiency of computations becomes a significant additional driver to Moore's Law. Figure 1 shows that computations per kW have a familiar Moore's Law-like behavior.3 This comes hand in hand with a decrease of the printed device feature size, see Fig 2. With the printed feature size of the semiconductor devices continuously decreasing and now dropping below 22 nm, production now relies on doublepatterning (DP) lithography based on 193 nm deep ultraviolet (DUV) sources.4 The step towards extreme ultraviolet lithography (EUVL) is seen as a logical one with respect to cost reduction in equipment space, as well as a driver for further feature downscaling.5 Figure 3 summarizes the ASML EUVL roadmap.6 ASML has recently completed the shipment of its second-generation full-field EUVL Step & Scan systems (NXE:3100) to customers. After shipment of the two demonstration tools to R&D facilities at IMEC (Belgium) and the University of Albany (NY, USA) in 2006, EUVL scanner technology progressed using 0.25 numerical aperture (NA) optics towards the preproduction system NXE:3100.7"13 The third-generation EUVL Step & Scan system, NXE:3300B, is under development now. It utilizes the technology developed in NXE:3100 and other tools. The main advances compared to the NXE:3100 are in the lens, the illumination system, and the source. Further improvement in flare and application of flexible illumination should bring the performance of the next generation NXE tool to 13 nm node. At the same time, the wafer and reticle stages and handlers remain basically unchanged from the NXE:3100. This gradual approach is similar to previous ASML Step & Scan platform developments.

Future Trends in Microelectronics

122

Figure 3. EUV roadmap.

Envisioning further evolution to the 10 nm node and below, which is now under study at ASML and ASML customers, one might simultaneously use NA > 0.33 and extended flex illumination with reduced pupil fill ratio. Thus, the short answer to the question of what will come after EUVL, would be: even more EUVL. 2.

A very short history of EUVL

A short history of EUVL is summarized in Figure 4.14'15 The first paper on the possible application of EUV or soft x-ray, as it was known at the time, for lithography was been published in 1985.16 Already by 1989, Kmoshita et al}1

Figure 4. EUVL came a long way starting from 1985.6'13,16";

EUV Lithography: Today and Tomorrow

123

demonstrated EUV imaging in resist with critical dimensions of -0.5 um, using Schwarzschild projection optics and synchrotron as a source. In 1991-92, EUV images obtained a laser-produced plasma (LPP) source were reported by Bijkerk's group.18 Critical dimension (CD) of -60-80 nm was demonstrated in Japan19 and United States20 in 2000 and 2001, respectively. An EUV lithography program was launched by ASML in 1997. It resulted in the shipment of two demonstration tools to IMEC and the University of Albany in 2006, performmg at 28 nm CD. This progressed further towards the shipment of NXE:3100 preproduction systems.6"13 The EUVL development had a fair share of the major achievements. For example, looking at the performance of the multilayer optics in Fig. 5,6 one can see improvement of the achieved rms mirror roughness from 0.25 nm in 2004 to 0.05 nm rms now. These values are on the level of a single atom!

Figure 5. Roughness results and target levels for mirrors of different EUVL tool generations (left) and coated mirror for the NXE:3300B generation (right).

Figure 6. Added particles per reticle pass (> 85 nm particles) performance of the NXE:3100 before and after scanner optimization. Preliminary NXE:3300B data are also included (this scanner is currently still in the integration phase at ASML).

Future Trends in Microelectronics

124

Significant progress has also been achieved in the contamination control of the mask. Unlike DUV systems, EUV does not use pellicle for mask protection and if contaminating particles close to CD in size if reach the reticle, they may be imaged on the wafer, producing defective chips. Figure 6 demonstrates the recent progress in reticle contamination control, where added defects per reticle pass have decreased by a factor of almost 50.6 At the same time a number of challenges seemed to be more difficult to resolve. One of those is the EUVL source, see Fig. 7. The whole history of the source development can be divided into four main "ages": •

Age of choice. During this period starting from 1998 till roughly 2001-02 the mam understanding of the EUVL system was developed. This age also produced the understanding for the source requirements, in particular the desired power. At the same time a number of EUV production options was investigated,21 including synchrotron-based,22 LPP,23"28 and different types of discharge-produced plasma sources.29"36 The level of the demonstrated power at that time was ~0.1 W.

•

Age of Xe. While the understanding of the EUV source requirements matured, the list of candidates for the sources narrowed down to the Xe laser26 and discharge pinch plasma sources.29'31 The achieved level of power with Xe source in this period of time (before 2003) was of the order of several W. At the end of this period it also became clear that due to a low conversion efficiency of Xe plasma (< 1%), these sources were unlikely to achieve 100 W of clean EUV photons after collection at intermediate focus.21 Thus, the need to change to a different EUV "fuel", namely Sn, was formulated and investigated during this period.21

Figure 7. History of the source development: power requirements and progress in output W at intermediate focus (IF - focal point of collector after all debris mitigation apparatus, spectrally pure).

125

EUV Lithography: Today and Tomorrow

3.

•

Age of Sn. The switch of multiple suppliers to the Sn fuel started in 2003.27'28'30,32"36 The highest achieved power at IF increased by a factor of 5 mainly due to the higher 5-6% conversion efficiency of Sn.36"42 The switch to Sn was not advantageous in all respects. In comparison to Xe, Sn is a rather "dirty" EUV fuel. Thus additional measures had to be taken into account why dealing with decrease in lifetime of collector optics.

•

Age of industrialization. Today we are living in the age of industrialization. It started with the delivery of 2 ADT tools with EUV Sn DPP sources and proceeded with NXE-3100 machines delivered with both Sn DPP and Sn LPP sources. While peak performances of those sources achieved almost 100 W levels,43 the average power and utilization remain a challenge. Still, as can be seen in Fig. 7, the NXE:3100 increased the productivity by more than an order of magnitude.

Present of EUVL: Update on the current situation

The imaging performance of the NXE:3100 tool showed an impressive set of single exposure results for dense line/spaces as well as real patterns.6 Off-axis illumination of the NXE:3100 demonstrated resolution of images down to 16 nm node, see Fig. 8. All images are at a dose of 33 mJ/cm2 and +50 nm focus. Figure 9 demonstrates one of the key advantages of EUV, the ability to print complex 2D patterns in a single exposure without stringent design restrictions, using the metal 1 layer of an SRAM cell at the 22 nm node as the example. As an alternative to EUV lithography, the same complex structures could be produced by at least three alternative techniques: repeated litho-etch; single-spacer; or doublespacer printing. All of those techniques have stringent design constraints. At the same time they also have ~2-5x more process steps and cycle time, which places greater demands on the infrastructure. The overlay performance of the NXE:3100 is also within the lithography specifications. Figure 10 shows the dedicated chuck overlay (DCO) capability of the NXE:3100 with the standard ASML test layout of 44 fields (26x32 mm field size). This is a stacked plot of six wafers with the flyers removed. The overlay result of 1.0 nm for the standard layout is well within the DCO specification.

18p36

17.5p35

17p34

16p32

Figure 8. Images of line/space features down to a CD of 16 nm and 32 nm pitch.

126

Future Trends in Microelectronics

Figure 9. SEM images with the various features.

Figure 10. Stacked wafer plots of 6 wafers, filtered for flyers.

The source power (and thus the corresponding throughput) is on the critical path for cost-effective EUV introduction. With the LPP source, output power has been primarily enhanced by increasing the EUV transmission of the source and increasing the operating duty cycle, while improving dose stability. As a next step, increasing the C02 drive laser power and improving the C02-to-EUV conversion efficiency is under development. Recent progress in droplet generator technology has contributed to improved source availability. For further description of the LPP source concept and status we refer to Ref. 43. An alternative technique for generating EUV radiation is the so-called laserassisted discharge plasma (LDP) source formerly known as DPP. An LDP source is also used on the NXE:3100 system. Increase of power has been primarily achieved by scaling the electrical input power while maintaining the thermal stability of the source. To improve source availability and cost of ownership, an

EUV Lithography: Today and Tomorrow

127

increased source head lifetime was achieved by further thermal and mechanical .

.

.

44

design improvements. With the current EUV power levels of ~10 W achieved in NXE systems installed at end-user facilities, - 7 wafers/hr throughput can be supported. 4.

EUVL and alternatives: The future

As has been mentioned in the introduction, for the future step to the 10 nm node and below one might simultaneously use NA > 0.33 and extended flex illumination with reduced pupil fill ratio, see Fig. 3. Looking out even further, to scaling beyond 2020 and the predicted 7 nm node, another wavelength of around 6.7-6.8 nm can be considered.21 The resolution R of optical lithography is described by the following formula: R = JfcjA/NA where X is the wavelength of the light, kx is an imaging enhancement-dependent coefficient, and NA is the numerical aperture of the lens.45 For an equal-lines-andspaces pattern the minimum feature size would correspond to k\ = 0.25. With NA ~ 0.6, as shown the Fig. 3, the corresponding best achievable resolution for X = 6.7 nm wavelength is ~ 3 nm. At the same time, the development of such a system faces significant challenges compared to existing systems using X = 13.5 nm, such as:21 •

new multilayer materials development with e.g. La and B pairs and larger number of pairs (-200 vs. 60 for X = 13.5 nm);

•

significantly better (~X2) polishing of the substrates to reduce stray light;

•

a narrower spectral bandwidth (-0.5% vs. 2% for X = 13.5 nm) both for high angular spread mirrors and effective EUV radiation coupling of the source;

•

new "fuel" for the source management, e.g. Gd.

In the initial experiments by IPM/Phystex, a single mirror reflectivity of-44% was achieved vs. theoretically achievable -80% value. The theoretical value for the shorter wavelength exceeds the maximum theoretical reflectivity for X = 13.5 nm but the gap between the best reflectivity of -50% measured to date46 and the theoretical one is still to be bridged. As shown in Ref. 21, the highest in-band conversion efficiency (CE) achieved for the Gd fuel by ISAN is -1.8%. This is an impressive result, but an improvement has to be made to reach the best value of CE for Sn of 5-6%.36-42 As discussed in Ref. 47, whereas in 1999 at the 180 nm node the gain in chip performance was mainly achieved by traditional scaling, 12 years later 90% of the gain was achieved by employing new materials and architectural innovations. While in 1980's electronic device manufacturing involved 11 basic materials,

128

Future Trends in Microelectronics

Figure 11. Theoretical reflectivity for a BEUV mirror vs. measured reflectivity in the first experiments by IPM.21

today this number exceeds 60. Progress in materials has also reached the patterning itself, a frightening prospect for most lithographers. Thus, directed selfassembly is now being studied as a possible technique for extension of CD scaling.48"52 The properties of (di)block-copolymers are such that they allow phase separation of the blocks on the tens of nanometers length scale. This leads to precise short range ordering, but long range cannot be reached in such a way automatically. In order to get long range ordering the self-assembly needs to be directed by either graphoepitaxial features, i.e. resist profiles51 or chemical patterns on a substrate.52 An example of such a type of ordering for can be seen in Fig. 12 for ~11 nm dot patterns.48 Though CD values achievable with directed self-assembly are very impressive, defectivity, CD uniformity, overlay and design restrictions remain the main challenges for its insertion in the fabrication process.48 The challenge for overlay is demonstrated in the Fig. 13, which shows the CD placement values of -3-4 nm.

Figure 12. Repeated SEM images (4x5 array) across the width of the wafer.'

129

EUV Lithography: Today and Tomorrow «3row* ■ 4row»

E -S 4 +Ф

E

3

£

2

©

Q.

»7lWS

.• *-i

1 0

10

20

30

40

50

60

70

SEM image Figure 13. Random placement per SEM image at best fitted pitch in X and Y.4

5.

Conclusions

It is expected that the decrease of the minimum feature size according to the Moore's Law will continue for the foreseeable future. EUVL is well on its way to being introduced in high-volume IC manufacturing, with the shipment of the multiple NXE tools to end-users. Imaging and overlay performance shows extensibility of the platform to the 20 nm node and beyond. Significant progress has been made in source development - both in output power and in availability but more is needed to support cost-effective IC manufacturing using EUVL. The potential of the EUVL systems goes beyond 10 nm node with possible extension of it with beyond EUV wavelength. Acknowledgtn ents The author would like to emphasize that the work presented here is based on results achieved by a team effort, with contributions by a large number of people in various organizations: ASML, Zeiss SMT AG, Philips, TNO, Cymer, and Extreme Technologies GmbH. The author wishes to express his gratitude to Jos Benschop, Sander Wuister and Hans Meiling for a valuable contribution to this paper, and to Jon Koomey for his permission to use some of his results. References 1. 2.

R. Konrad, http://news.cnet.com/Server-farms-on-hot-seat-amid-power-woes/ 2100-1017_3-257567.html CNET (2001). See http://enduse.lbl.gov/projects/InfoTech.html

130

3.

4.

5. 6.

7.

8. 9. 10. 11. 12. 13.

14. 15. 16. 17. 18. 19. 20.

Future Trends in Microelectronics J. G. Koomey, S. Berard, M. Sanchez, and H. Wong, "Implications of historical trends in the electrical efficiency of computing," IEEE Annals History Computing 33,46 (2011). J. Finders, M. Dusa, P. Nikolsky, et al, "Litho and patterning challenges for memory and logic applications at the 22-nm node," Proc. SPIE 7640, 76400C1 (2010). C. Wagner, N. Harned, P. Kiirz, et al., "EUV into production with ASML's NXE platform," Proc. SPIE 7636, 76361H (2010). H. Meiling, W. De Boeij, F. Bornebroek, et al., "From performance validation to volume introduction of ASML's NXE platform," Proc. SPIE 8322, 83221G (2012). C. Wagner, J. Bacelar, N. Harned, et al., "EUV lithography at chipmakers has started: Performance validation of ASML's NXE:3100," Proc. SPIE 7969, 7969IF (2011). H. Meiling, E. Boon, N. Buzing, et al., "Performance of the full field EUV systems," Proc. SPIE 6921, 69210L (2008). N. Harned, M. Goethals, R. Groeneveld, et al., "EUV lithography with the alpha demo tools: Status and challenges", Proc. SPIE 6517, 651706 (2007). H. Meiling, H. Meijer, V. Y. Banine, et al., "First performance results of the ASML alpha demo tool," Proc. SPIE 6151, 651508 (2006). H. Meiling, J. P. H. Benschop, R. Hartman, et al., "EXTATIC, ASML's a-tool development for EUVL," Proc. SPIE 4688, 52 (2002). H. Meiling, J. P. H. Benschop, U. Dinger, and P. Kiirz, "Progress of the EUVL alpha tool," Proc. SPIE 4343, 38 (2001). E. van Setten, O. Mouraille, F. Wittebrood, et al., "22 nm node and beyond: When will EUV take over?" presented at Intern. EUVL Symp., Kobe, Japan (2010). J. P. H. Benschop, "EUV: Status and challenges ahead", Intern. Workshop EUVL, Maui, Hawaii (2010). V. Y. Banine, "EUV lithography and EUVL sources: From the beginning to NXE and beyond", Intern. Workshop EUVL, Maui, Hawaii (2011). K. Hoh and H. Tanino, "Feasibility study on the extreme UV/soft x-ray projection-type lithography," Bull. Electrotechnical Lab. 49, 983 (1985). H. Kinoshita, K. Kurihara, Y. Ishii, and Y. Torii, "Soft x-ray reduction lithography using multilayer mirrors," J. Vac. Sci. Technol. B 7, 1648 (1989). H. J. Voorma and F. Bijkerk, "Design of an extended image field soft x-ray projection system," Microelectronics Eng. 17, 145 (1992). H. Kinoshita, T. Watanabe, Y. Li, et al., "Recent advances of 3-aspherical mirror system for EUVL," Proc. SPIE 3997, 70 (2000). D. A. Tichenor, A. K. Ray-Chaudhuri, S. H. Lee, et al., "Initial results from the EUV engineering test stand," Proc. SPIE 4506, 9 (2001).

EUV Lithography: Today and Tomorrow

131

21. V. Y. Banine, K. Koshelev, and G. H. Swinkels, "Physical processes in EUV sources for microlithography," J. Phys. D: Appl. Phys. 44, 253001 (2011). 22. D. Attwood, Soft X-rays and Extreme Ultraviolet Radiation: Principles and Applications, Cambridge: Cambridge Univ. Press, 1999. 23. G. D. Kubiak, L. J. Bernardez, and K. D. Krenz, "High-power extreme-ultraviolet source based on gas jets," Proc. SPIE 3331, 81 (1998). 24. R. H. Moyer, H. Shields, A. Martos, et al, "Laser-produced plasma (LPP) scale-up and commercialization," Proc. SPIE 4343, 249 (2001) 25. H. Shields, S. W. Fornaca, M. B. Petach, et al., "Xenon target performance characteristics for laser-produced plasma EUV sources," Proc. SPIE 4688, 94 (2002). 26. B. A. M. Hansson, Laser-Plasma Sources for Extreme-Ultraviolet Lithography, Ph.D. thesis, KTH, Stockholm, 2003. 27. I. V. Fomenkov, A. I. Ershov, W. N. Partio, et al., "Laser-produced plasma light source for EUVL," Proc. SPIE 7636, 763639 (2010). 28. H. Mizoguchi, T. Abe, Y. Watanabe, et al., "First generation laser-produced plasma source system for HVM EUV lithography," Proc. SPIE 7636, 76363C (2010). 29. J. Pankert, "Philips' EUV source: Update and issues," presented at Intern. EUVL Symp., Miyazaki, Japan (2004). 30. J. Pankert, R. Apetz, K. Bergmann, et al., "EUV sources for the alpha-tools," Proc. SPIE 6151, 61510Q (2006). 31. U. Stamm, "Extreme ultraviolet light sources for use in semiconductor lithography - state of the art and future development," J. Phys. D: Appl. Phys. 37, 3244 (2004). 32. U. Stamm, J. Kleinschmidt, K. Gabel, et al., "Development status of EUV sources for use in alpha-, beta- and high volume chip manufacturing," Proc. SPIE 5751, 236 (2005). 33. H. Meiling, V. Y. Banine, N. Harned, et al., "Development of the ASML EUV alpha demo tool," Proc. SPIE 5751, 90 (2005). 34. M. Corthout, Y. Teramoto, M. Yoshioka, et al, "XTREME technologies: First tin beta SoCoMo ready for wafer exposure," presented at Intern. EUVL Symp., Kobe, Japan (2010). 35. K. Koshelev, V. Krivtsun, V. Ivanov, et al. "New type of DPP source for EUVL based on liquid tin jet electrodes," presented at Intern. Workshop EUV Sources, Dublin, Ireland (2010). 36. M. Yoshioka, Y. Teramoto, P. Zink, G. Schriever, G. Niimi, and M. Corthout, "Tin DPP source collector module (SoCoMo): Status of beta products and HVM developments," Proc. SPIE 7636, 763610 (2010). 37. T. Tomie, T. Aota, Y. Ueno, et al., "Use of tin as a plasma source material for high conversion efficiency Proc. SPIE 5037, 147 (2003).

132

Future Trends in Microelectronics

38. M. Richardson, C.-S. Koay, K. Takenoshita, C. Keyser, and M. Al-Rabban, "High conversion efficiency mass-limited Sn-based laser plasma source for extreme ultraviolet lithography," J. Vac. Sci. Technol. B 22, 785 (2004). 39. I. V. Fomenkov, D. C. Brandt, A. N. Bykanov, et al., "Laser-produced plasma source system development," Proc. SPIE 6517, 65173J1 (2007). 40. Y. Ueno, G. Soumagne, A. Sumitani, A. Endo, and T. Higashiguchi, "Enhancement of extreme ultraviolet emission from a C02 laser-produced Sn plasma using a cavity target," Appl. Phys. Lett. 91, 231501 (2007). 41. K. Nishihara, A. Sunahara, A. Sasaki, et al, "Plasma physics and radiation hydrodynamics in developing an extreme ultraviolet light source for lithography," Phys. Plasmas 15, 056708 (2008). 42. S. S. Harilal, T. Sizyuk, V. Sizyuk, and A. Hassanein, "Efficient laserproduced plasma extreme ultraviolet sources using grooved Sn targets," Appl Phys. Lett. 96, 111503 (2010). 43. I. V. Fomenkov, B. La Fontaine, D. Brown, et al, "Development of stable extreme-ultraviolet sources for use in lithography exposure systems," J. Micro/ Nanolith. MEMSMOEMS11, 021110 (2012). 44. G. Schriever, O. Semprez, J. Jonkers, M. Yoshioka, and R. Apetz, "Laserproduced plasma versus laser-assisted discharge plasma: Physics and technology of extreme ultraviolet lithography light sources," J. Micro/ Nanolith. MEMSMOEMS 11, 021104 (2012). 45. M. Born and E. Wolf, Principles of Optics, Oxford: Pergamon, 1980, p. 187. 46. I. A. Makhotkin, E. Zoethout, E. Louis, A. M. Yakunin, S. Müllender, and F. Bijkerk, "Spectral properties of La/B-based multilayer mirrors near the boron K absorption edge," Optics Express 20, 11778 (2012). 47. S. F. Wuister, J. Fmders, E. Peeters, and C. van Heesch, "Lithography assisted self-assembly of contact holes on 300-mm wafer scale," J. Micro/Nanolith. MEMSMOEMS 11, 031304 (2012). 48. M. P. Stoykovich and P. F. Nealey, "Block copolymers and conventional lithography," Mater. Today 9, 20 (2006). 49. J. Y. Cheng, C. A. Ross, H. I. Smith, and E. L. Thomas, "Templated selfassembly of block copolymers: Top-down helps bottom-up," Adv. Mater. 18, 2505 (2006). 50. C. T. Black, R. Ruiz, G. Breyta, et al, "Polymer self-assembly in semiconductor microelectronics," IBMJ. Res. Dev. 51, 605 (2007). 51. R. A. Segalman, H. Yokoyama, and E. J. Kramer, "Graphoepitaxy of spherical domain block copolymer films," Adv. Mater. 13, 1152 (2001). 52. J. Heier, J. Genzer, E. J. Kramer, F. S. Bates, S. Walheim, and G. Krausch, "Transfer of a chemical substrate pattern into an island-forming diblock copolymer film," J. Chem. Phys. I l l , 11101 (1999).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Manufacturability and Nanoelectronic Performance M. J. Kelly Centre for Advanced Photonics and Electronics, Dept. of Engineering Univ. of Cambridge, 9 JJ Thomson Avenue, Cambridge CB3 OF A, U.K.

1.

Introduction

It has long been appreciated that fundamental constants and materials' properties set limits on the performance of solid-state electronic devices. The speed of light, the charge to mass ratio of an electron and Planck's constant constrain the movement of electrons and photons in solids. The product of the dielectric breakdown field and the saturated drift velocity constrain the speed and power levels in semiconductor devices.1 Of more recent interest are the constraints on device and circuit performance that are imposed by the way they are manufactured.2'3 We consider the borderline between manufacturability and unmanufacturability, and then examine the consequences on device performance. 2.

Manufacturability

Improved performance and cost reductions achieved through miniaturization have driven mainstream microelectronics for 50 years. Prototypes in the laboratory show that this driver still has some way to go in commercial production. In the transition from prototype to product, or from fabrication to manufacturing, several conditions must be achieved. Low-cost, high-volume manufacture requires much more than one-off fabrication. Indeed it needs all three of: (i) a superior prespecified device performance achieved with reproducibility, uniformity and reliability; (ii) a high yield to acceptable tolerance; and (iii) a simulator for both reverse engineering during development and right-first-time design during manufacturing. The manufactured product must have an adequate in-service life and all this must all be achieved at a cost that is less that people are willing to pay to satisfy some perceived need. As present, there are two distinct routes to manufacture of nanoscale artefacts. The dominant route is top-down, sculpting and adding selective volumes of materials to a starting substrate, using combinations of deposition (including epitaxy), etching and lithography. Here one limit on the performance of devices will be set by the ability to make uniform arrays of artefacts with properties that are adequately reproducible. Another will occur when the unintended interactions between adjacent artefacts become too strong to ignore. A third will occur when one tries to write, store and read information from individual artefacts. The other 133

134

Future Trends in Microelectronics

manufacturing approach is the bottom-up route, where small structures, such as nanowires or complex molecules, are deposited in arrays. Here the problems include the uniformity of the fabricated nanowires as described above, or the lack of 5-nines purity starting molecular materials of any level of non-trivial internal complexity, the precise positional ordering of the nanostructures or molecules to achieve long range translational order without point or line defects, tight local orientation order, and the process of wiring up the array elements for addressing. 3.

Reproducibility of artefacts made by top-down methods

Suppose we make an array of artefacts, say a square pillar of side d nm, out of a semiconductor on a semiconductor substrate. The first step will be to define areas of side d nm in a resist material that will allow just this defined material to be etched away or to be left with all the complementary resist material removed. In either case, atoms are removed one by one in the etching process, leaving holes in the resist of side d nm or a remaining pillar of resist of side d nm. The base layer of atoms within the layer will include ad2 atoms where, for example, a = 3.4 for Si and a = 3.1 for GaAs. The statistics of small numbers applied to the basal area of each pillar will give us a standard deviation divided by the average number of atoms of 1/VN~ 0.6/U?. If the areas are to have a standard deviation of 6. We normally expect 6o manufacture, meaning that only a few in a million artefacts are outside the specified tolerance and if this is still ±10% by area, this can only be satisfied for d> 15nm, which is at today's CMOS design rule. For pillars that are relatively well-separated, we will be interested in the energy levels set by quantum confinement across the pillar area, and these will vary inversely as the area with o = 10% at d = 6 nm. For optical applications this gives a pillar-to-pillar variation in the optical transition energy, while for electrical applications it specifies a threshold voltage spread for low temperature transport of electrons to or from the pillar. If the array is square with a spacing of 2d between the centers of the pillars or hexagonal at some slightly greater separation, the inter-pillar interaction becomes highly dependent on the material in the interstices and particularly its quality in terms of defects, etc. For dense arrays, tunneling between adjacent pillars becomes probable and uncontrollable, and any defects will serve to interfere with attempts to either induce or inhibit carrier transport. The conditions of irreproducibility that apply to the formation of the pillars also apply, a fortiori, to the processing to make interconnects with which one might electronically address, and write, store and read the elements of the array. If the initial hole in the resist is used to deposit a metal dot as the catalyst for the growth of nanotubes of any material, the above-cited limitations still apply. In most cases, the tube will resort to a circular geometry once the length to width ratio exceeds a few integers. There is little control over length, unidirectionality and normality to the surface.

Manufacturability and Nanoelectronic Performance 4.

135

Reproducibility of artefacts made by bottom-up methods

To date, bottom-up methods employ fabricated nanostructures4'5 or molecules of different levels of complexity.6 Both techniques face problems associated with the quality of the starting materials, and with the precise positioning and orientation of them on the substrate surface, even before any attempt is made to wire them for addressing. The 6a manufacture achieved by conventional top-down methods used in microelectronics implies a greater than 5-nines integrity of the pillars/nanowires or molecular structures if applied here to bottom-up nanoelectronics. None of the suppliers of nanotubes or nanowires offer as much as 2-nines purity (97% being a recent quotation from Nanotechnology Now portal), and few molecular gases or liquids, and none of any internal complexity as needed as an effective array element here, get anywhere near this in purity of the starting materials: high-purity hydrogen is at 6-nines. The precursors for III-V growth by MOCVD struggle to get to 5-nines purity. Most of the more complex molecular species are quoted in chemical company data books as 2-nines or 3-nines: this comment applies even more strongly to the quotations on nanoparticles, nanowires or quantum dots. The implication is that even before deposition, the resulting quality of the array will be less than one produced by top-down fabrication. The results quoted here are stateof-the-art, and one can ask at what stage the costs of improving on this negate the value of a subsequent product made form purer materials. Little work is reported on aligned nanotube arrays, with quality still well below that required to compete effectively with top-down array quality.7"9 The standard deviations of device properties (threshold voltage, on-current and transconductance) are still very large, typically 30%. In terms of alignment of molecules in block co-polymer arrays, figures of 1° standard deviation for misalignment are quoted.6 Finally the state-of-the-art areas of defect free-arrays of deposited complex molecules is still on the sub-millimeter scale, rather than a 300 mm scale. This is all before any attempt is made to interconnect the elements and to exploit the electronic or optoelectronic properties. 4.

Consequent device performance limits

There have been a number of studies of the failure of small devices, the most similar one in spirit to this study being the 2003 paper by Asenov and coworkers,10 who considered the variation of intrinsic device parameters of individual transistors in an integrated circuit.8 The limitations on quantum dot laser performance in terms of output power at low temperatures seem attributable in part to the intrinsic variability of quantum dot volumes that have persistently remained near o v = 15% of average volume for dots of ~5 nm diameter since first investigated 20 years ago. The limitations on interconnect technology are the limiting feature for dense arrays where information is to be written, stored and read.

Future Trends in Microelectronics

136 5.

Epitaxial control of layer thickness

By contrast with limits placed on device performance imposed by the statistics of small numbers, the ability to grow large-area layers of precisely controlled thickness seems not to be so limited under certain conditions. Recent studies of single tunnel barriers have provided direct evidence of layers controlled to within 0.1 monolayer and with a variation across the 3" wafer as low as 0.02 monolayers in one direction and 0.06 monolayers in the perpendicular direction, for AlAs layers designed to be precisely 10 monolayers in thickness with GaAs layers on either side. The precision and device-to-device uniformity (and wafer-to-wafer reproducibility) of the current-voltage characteristics of diodes from three wafers lead to this conclusion. Tunneling electrons in this structure have a coherence area on the order of 10 nm and it is an area of such diameter that is being sampled by the tunneling electrons.11,12 The net radial variation of the Al beam intensity across the wafer on a rotating three-wafer platen is in close quantitative agreement with the measured variation, which in turn could be further reduced by growing the wafers in a production environment. Earlier studies show that layers of non-integer layer thickness have tunnel currents that can vary by as much as 25% from one point on a wafer to another in the GaAs/AlAs layer by virtue of the degree of lack of ordering at the monolayer alloy interfaces on either side of the barrier.13 It is the absence of these alloy interface layers that have contributed to the uniformity and reproducibility of the device results.

6.

Zeolite pores as wires

Limitations such as those discussed above cry out for means of circumvention. In terms of producing uniform parallel wires, the pores in zeolite crystals are an obvious possibility. One could in principle form a dense bundle of quasi-onedimensional wires by intercalation of alkali metals at sufficiently high density.14 Initial experiments do not achieve the density required, with a sequence of atomic clustered being formed in the larger area cages where the pores at right-angles meet.15'16 Even if the density could be increased, the precise definition of the cross section of the wires is still needed and there is no prospect as yet of engineering right-angle bends in such wires where needed, as would be required for interconnect wiring. 6.

Conclusions

There is an enormous body of research work on nanostructures that is potentially incapable of production, i.e. the results presented are intrinsically one-off and not able to meet the various criteria for volume mamifacturability described above. Many authors in fact allude to this problem explicitly in their work. In the interests

Manufacturability and Nanoelectronic Performance

137

of the end-to-end effectiveness of applied research on nanostructures, the issue of manufacturability should become center stage: it is a critical requirement for any real applications. Acknowledgments This work was supported in part by the EPSRC. References 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13.

E. O. Johnson, "Physical limitations on the frequency and power parameters of transistors," RCA Rev. 26, 163 (1965). M. J. Kelly, "Intrinsic top-down unmanufacturability," Nanotechnology 22, 245303(2011). M. J. Kelly, "Intrinsic unmanufacturability in nanoelectronics," Proc. IEEE Intern. Conf. Nanotechnology (2011), pp. 508-11. W. Lu and C. M. Lieber, "Nanoelectronics from the bottom up," Nature Nanomaterials 6, 841 (2007). C. M. Lieber, "Semiconductor nanowires: A platform for nanoscience and nanotechnology," MRS Bull. 36, 1052 (2011). J. Y. Cheng, C. A. Ross, E. L. Thomas, H. I. Smith, and G. J. Vancso, "Fabrication of nanostructures with long-range order using block copolymer lithography," Appl. Phys. Lett. 81, 3657 (2002). W. I. Park, G. Zheng, X. Jiang, B. Tian, and C. M. Lieber, "Controlled synthesis of millimeter-long silicon nanowires with uniform electronic properties," NanoLett. 8, 4 (2008). N. Patil, A. Lin, E. R. Myers, et al, "Wafer-scale growth and transfer of aligned single-walled carbon nanotubes," IEEE Trans. Nanotechnology 8, 498 (2009). H. T. Ng, J. Han, T. Yamada, P. Nguyen, Y. P. Chen, and M. Meyyappan, "Single crystal nanowire vertical surround-gate field-effect transistor," Nano Lett. 4, 1247 (2004). A. Asenov, A. R. Brown, J. H. Davies, S. Kaya, and G. Slavcheva, "Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs," IEEE Trans. Electron Dev. 50,1837 (2003). C. Shao, P. Dasmahapatra, J. Sexton, M. Missous, and M. J. Kelly, "Highly reproducible tunnel currents in MBE-grown semiconductor multilayers," Electronics Lett. 48, 792 (2012). P. Dasmahapatra, J. Sexton, M. Missous, C. Shao, and M. J. Kelly, "Thickness control of MBE-grown layers at the 0.01-0.1 monolayer level," Semicond. Sci. Technol, 27, 085007 (2012). M. J. Kelly, "The unacceptable variability in tunnel currents for proposed electronic device applications," Semicond Sci. Technol. 21, L49 (2006).

138

Future Trends in Microelectronics

14. M. J. Kelly, "A model electronic structure for metal-intercalated zeolites," J. Phys. C. 7, 5507 (1995). 15. P. A. Anderson, A. R. Armstrong and P. P. Edwards, "lonization and delocalization in potassium zeolite L: A combined neutron diffraction and electron spin resonance study," Angewandte Chemie 33, 641 (1994). 16. U. Simon and M. E. Franke, "Electrical properties of nanoscaled host/guest compounds," Microporous Mesoporous Mater. 41, 1 (2000).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Part II Optoelectronics in the Nano Age

II. Optoelectronics in the Nano Age While silicon electronics continues its dominance in the information-processing arena, photonics is also expanding its presence and exerting its power in the nano age, particularly in long-haul communications, displays, and data storage. An emerging theme is bandwidth and energy constraints on data communication. The chapter by Ledentsov et al. that opens Part II of this volume, serves as an explicit example of optoelectronic integration in the service of contmued scaling of computing systems; whereas Mynbaev's chapter covers the anticipated bandwidth demand over the next decade. Mohseni's chapter approaches the issue from an interestingly different end by analyzing the impact, promise, and limitations of capturing light by electronic means - plasmonic responses in nanoscale optical antennae. The final chapter addresses the intriguing possibility of adding spin as a controlling variable in semiconductor lasers.

Contributors 2.1

N. N. Ledentsov, V. A. Shchukin, and J. A. Lott

2.2

D. K. Mynbaev

2.3

H. Mohseni

2.4

J. Lee, G. Boéris, R. Oszwaldowski, K. Vyborny, C. Gathgen, and I. Žutić

141

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Ultrafast Nanophotonic Devices for Optical Interconnects N. N. Ledentsov,* V. A. Shchukin,* and J. A. Lott Vl-Systems GmbH, Hardenbergstrasse 7, D-10623 Berlin, Germany

1.

Introduction

Silicon scaling continues at unabated speed. Major manufacturers of CMOS integrated circuits are presently shipping products at the 20-22 nm device node. Furthermore, Intel and Nvidia announced 8 nm technology will become available by 2015.1 Consequently, the computational power of processors continues to roughly double each year2 for all major products, from supercomputers to laptops and smartphones. To match the related bandwidth demand, the single channel bit rate must increase 20-fold every decade in all major electrical and optical interfaces and interconnects. Furthermore, the core networking speed must increase 100-fold during the same period, which thus requires a five-fold increase in the number of single channels per link. Presently, in high-performance computing (HPC) the links already operate at bit data rates of 10 Gb/s and above, and the major market for interfaces is targets links operating at 14 Gb/s. A new generation of interfaces (CEI-25G-LR, CEI-28G-SR, CEI-28G-VSR) is currently being standardized at 25-28 Gb/s.3 Furthermore, by 2014 a single-channel bit data rate of electrical and optical interfaces should reach 56 Gb/s to match the bandwidth density scaling law. The related standard is being developed by the OIF (Optical Internetworking Forum) standards group (CEI-56G).4 Even at 10 Gb/s copper-based links become too bulky and power-consuming. Thus a shift towards optical interconnects is necessary. Modern supercomputers from IBM (Blue Gene/Q, Power7 systems, and others) employ about 5 million optical links, each operating at 10 Gb/s, to reach 10 petaflop performance (where 1 petaflop or PF = 1015 floating point operations per second). A major fraction of these links are located within the compute card and I/O drawers, on top of the backplane and rack-to-rack links. Above one billion optical links are forecast by IBM for systems operating close to 1 exaflop (EF, equal to 103 PF), and the first systems operating at 0.4 EF should be available as early as 2016.5 On average, the number of optical links per single supercomputer increases a hundred-fold every 3 years, whereas the bit data rate per channel approximately doubles. In the coming exascale era, over 80% of the system power and up to 5090% of its performance will be defined by optical interconnects.6

On leave from A. F. Ioffe Institute, Saint Petersburg, Russia. 142

Ultrafast Nanophotonic Devices for Optical Interconnects

143

2. Vertical-cavity surface-emitting lasers The device that is presently dominating optical interconnects in HPC facilities and data centers is the vertical-cavity surface-emitting laser (VCSEL), a vertical microcavity device with a very small lateral size of the active region - see Fig. 1. The aperture has a diameter of only a few micrometers and the actual chip size is largely basically by the tooling equipment used for bondmg and packaging. If properly designed, the VCSEL may operate at a very low bias current, exhibiting a low capacitance and high energy conversion efficiency. As the size of the device can be made very small, the cost of each device is extremely low. The possibility of directly attaching lift-off VCSELs to the electrical IC interconnect layers may enable a low-cost high-frequency packaging scheme based on optical pin connector arrays rather than electrical pins. A schematic representation of a VCSEL is shown in Fig. 1. Multilayer top and bottom Ga(Al)As-Al(Ga)As distributed Bragg reflectors (DBRs) with optical power reflectivity > 99% create a high-finesse vertical resonant cavity. A gain medium is introduced between the two DBRs. For the wavelength range of 800 nm and above, the DBRs are composed of quasi-binary AlGaAs alloy layers with high and low Al compositions. This combination of materials provides a high refractive index contrast necessary to achieve significant optical reflectivity combined with good thermal conductivity. The current is usually delivered through the doped DBRs, while the electrical confinement is realized by

Figure 1. Schematic representation of the vertical-cavity surface-emitting laser (VCSEL). Multilayer top and bottom Ga(AI)As-AI(Ga)As distributed Bragg reflectors with optical power reflectivities > 99% create a high-finesse vertical resonant cavity.

144

Future Trends in Microelectronics

selective lateral oxidation of specially-introduced Al(Ga)As aperture layers with an Al content of -98%, higher than that in the DBRs, and therefore having a high lateral oxidation rate in water vapor. This allows for the selective conversion of crystalline Al(Ga)As epitaxial layers into amorphous and nonconducting Al(Ga)0 "oxide aperture" layers. The lasing wavelength of the device is defined primarily by the longitudinal optical mode of the vertical cavity. Typically, the fundamental optical cavity mode wavelength must spectrally overlap with the gain curve of the photon-generating active region to enable good performance. As the thermal shift of the cavity resonance wavelength is weaker than the thermal wavelength shift of the gain peak, which is defined by the thermal shift of the bandgap, the gain curve should be broad enough to ensure proper device operation over a significant temperature range. Depending on the gain medium chosen (GaAs, InGaAlP, InGaAs, InGaAsN, quantum wells, quantum wires, quantum dots) the spectral range of GaAs-based VCSELs can be typically tuned in the 0.6-1.3 ц т range.7 Presently, VCSELs at 850 nm are dominating optical networks at link distances below 300 m because they match the standardized and broadly deployed 850 nm wavelength-optimized multimode fiber. Worldwide, billions of 850 nm VCSELs are now used daily in data communications and optical mice, while smaller numbers of VCSELs at longer wavelengths (-980 nm) are predominantly used in military applications. Optical transition oscillator strength in III-V semiconductor materials increases with bandgap. Lasers at shorter wavelength also require thinner DBRs for the same number of periods, thereby achieving a stronger optical confinement factor for the same gain medium. As a combination of these two factors, a much higher differential gain can be achieved in shorter-wavelength GaAs VCSELs, making them advantageous for high-speed applications. A thinner multilayer DBR structure enables also more efficient heat dissipation, lower series resistance, and lower epitaxial costs. Moreover, for the same AlGaAs barrier material, the shorter the wavelength, the weaker the electron confinement of nonequilibrium carriers in the gain region, and the faster the degradation of the device performance due to a temperature increase. Standard oxide-confined 850 nm VCSELs demonstrate a certain spectral width of the emission (-0.5 nm) even at moderate (6-10 цт) oxide-confined aperture diameters. Thus, a typical 850 nm VCSEL is multimode, i.e. lases in several transverse optical modes each having a slightly different wavelength and a very different angular distribution of the far-field emission pattern.8 These features of multimode VCSELs significantly limit the possible transmission distance of a conventional optical fiber communication link due to the spectral and modal dispersion of modern multimode optical fibers. As the optical far field of the VCSEL is complex, and also varies with the current density and the temperature of the device, the efficient coupling of VCSELs to waveguides and optical fibers requires significant design and rather precise assembly work. To overcome these deficiencies, we propose the use of single mode or quasi-single mode VCSELs9 for the next generation of optical interconnects.

Ultrafast Nanophotonic Devices for Optical Interconnects 2.

145

Optical modes in conventional VCSELs

In Figs. 2 and 3 we give examples of the refractive index profile and the calculated longitudinal (ID) optical field strength of an 850 nm VCSEL along the center line through the VCSEL's nonoxidized cavity region (Fig. 2) and along a line that runs through the selectively oxidized part of the VCSEL structure (Fig. 3), respectively. In Fig. 4(a) we show optical power reflectance spectrum of the VCSEL of Fig. 2(a) calculated at normal incidence and revealing a cavity "etalon dip" at 850 nm. The optical power reflectance spectrum for the oxidized part of the structure is shown in Fig. 4(b) and reveals a blue shift of the VCSEL-like mode in the oxidized region. Once the angle of the VCSEL mode in the aperture region deflects from the normal to the surface, the cavity mode wavelength decreases and approaches the wavelength of the fundamental cavity mode in the oxidized part at a certain critical angle - see Fig. 4(c). For small apertures, the cavity modes in the aperture region become quantized with each high-order transverse mode having a related tilt angle of the emission lobes in the far-field pattern.8 The VCSEL transverse mode matching the critical angle becomes delocalized and cannot contribute to lasing due to a very low overlap with the gain region and a high leakage loss. The related angle defines the short wavelength limit of the VCSEL multimode emission

Figure 2. (a) Refractive index profile of a typical 850 nm vertical cavity surface emitting laser (VCSEL) in the aperture region, showing unoxidized AIGaAs layers. (b) Corresponding electric field amplitude profile calculated for the vertical optical mode of the VCSEL structure in the aperture (non-oxidized) region.

146

Future Trends in Microelectronics

Figure 3. (a) Refractive index profile of the 850 nm VCSEL structure of Fig. 2(a) but showing oxidized (Ga)AIOx layers in the oxide-confined part of the VCSEL surrounding the aperture region, (b) Corresponding electric field amplitude profile of the vertical optical mode in the oxidized region surrounding the VCSEL aperture.

and also the maximum angle of the lobes in the far field pattern. For the angle of the mode of 7.5° calculated with a reference to the Gao.85Alo.15As layer the angle in the air corresponds to -25°. Thus, for this particular VCSEL design, the maximum full width at half maximum of the emission pattern may reach -50°. As the highorder tilted modes exhibit lower optical overlap with the electrically pumped aperture region and also show higher optical losses, these modes typically appear at high current densities above the lasing threshold and play a very negative role in data transmission. Once the diameter of the oxide-confined aperture region is reduced, the fundamental VCSEL mode becomes strongly quantized and its wavelength undergoes a blue shift.10 Once the shift becomes comparable to the spectral separation of the cavity dip features in the oxidized and non-oxidized regions, only the fundamental mode remains localized. Thus, the true single mode regime can be achieved only at small aperture sizes. One way to achieve single mode operation at large apertures is to reduce the blue shift of the cavity mode in the oxidized region. This may be achieved by thinning the aperture region and placing it in the node position of the optical field, while separating the aperture from the Al-rich X/4 layers of the Bragg reflector to prevent unintentional tapered oxidation of this part of the structure.8

Ultrafast Nanophotonic Devices for Optical Interconnects

147

Figure 4. (a) Optical power reflectance spectrum of the VCSEL of Fig. 2(a) calculated for the non-oxidized (aperture) region at normal incidence, revealing an etalon dip at 850 nm. (b) Optical power reflectance spectrum of the oxidized part of the VCSEL of Fig. 2(b), calculated at normal incidence, revealing an etalon dip shifted to a shorter 843 nm wavelength, (c) Optical power reflectance spectrum of the VCSEL depicted in Fig. 2(a) with s-polarization, calculated for the aperture region at oblique incidence, tilted by 7.5° with respect to the normal to the surface (the angle being defined for a Gao.e5Alo.15As layer) revealing an etalon dip at 843 nm. At this angle the high-order tilted VCSEL-mode in the aperture region reaches the continuum of the vertical cavity fundamental mode in the oxidized region. Thus, no confined modes exist in the oxide-confined aperture, (d) Same as (b), to make the comparison easier.

In certain cases, the top semiconductor DBR of the device may be replaced by a DBR made of dielectric materials. Also, the cavity region and a part of the bottom DBR can be fabricated from dielectric materials. The latter approach is well-suited for devices where the vertical cavity section is intended for photonic crystal patterning, for VCSELs with complete temperature stability of the lasing wavelength (by choosing the appropriate dielectric materials with the required thermal coefficients of the refractive indices), for VCSELs in systems where native semiconductor materials with sufficient refractive index contrast are not available, and in the case where the thermal conductivity of the alloy materials to be used for DBRs is too low. This approach represents a passive cavity VCSEL concept, which was successfully prototyped recently.11

148 3.

Future Trends in Microelectronics High-speed data transmission using VCSELs

Just a few years ago it was believed that 850 nm VCSELs would not likely operate at bit data rates significantly above 10 Gb/s.12 The main reason was the need for very high current densities to shorten the response time under current modulation, which were expected to result in the acceleration of degradation processes. To shorten the response time of the device for the same gain medium one has to reduce the lifetime of the stimulated emission in the micro-resonator and, also, increase the resonance frequency of the device. The resonance frequency fK is described by an equation

where gn is the differential gain, p0 is the average photon density in the cavity, and Tp is the cavity photon lifetime. It is clear that the "simple" approach of increasing fR by increasing p0 in the cavity via increased current density is limited. To increase the resonance frequency by a factor of 2.5 to enable 25 Gb/s data transmission (instead of 10 Gb/s), an increase in the current density by a factor of 6.25 is needed. However, even at 10 Gb/s, standard GaAs quantum well (QW) VCSELs operate close to the thermal roll-over point and may suffer from reliability problems. An increase in the current density in this case does not improve the performance significantly but causes a dramatic acceleration of the degradation processes (a ten-fold reduction in the lifetime has been reported12 when the current density is increased by a factor of 1.5). A much better approach may be the replacement of the GaAs QWs with thin InGaAs insertions in an AlGaAs matrix used as the gain medium. When properly engineered, these insertions are suitable for gain generation at X = 850 nm. At the same time, strain and quantum dimensionality engineering13 allow the VCSEL designer to increase the differential gam by about an order of magnitude, increasing / R by a factor of 3 over a GaAs-based QW device at the same current density. Another problem is the device capacitance, which makes it difficult to reach a -30 GHz 3-dB electrical bandwidth. A proper design of the oxide-confined aperture region and of high-frequency (HF) contact pads, as well as careful device processing are necessary to reach the requested performance without degrading the reliability of the VCSEL. The relaxation resonance frequency of 850 nm VCSELs as a function of current at different diameters of the oxide-confined apertures is shown in Fig. 5. Higher resonance frequencies are observed at smaller aperture diameters. The effect is found to be exclusively related to much higher current densities needed to reach thermal roll-over in the case of smaller aperture sizes. For small apertures heat dissipation is much more efficient for the same current densities due to the larger role of "perimeter" cooling.

Ultrafast Nanophotonic Devices for Optical Interconnects

149

X

3 СГ Ш k.

c TO c o W 0)

cc

Current (mA) Figure 5. Relaxation resonant frequency of 850 nm VCSELs at different aperture diameters as a function of forward bias current. Higher resonant frequencies are observed for smaller aperture sizes. Resonant frequencies at similar current densities below roll-over are roughly the same for all studied aperture sizes.

Furthermore, very low aperture diameters increase the series resistance of the device. Due to the finite bond pad capacitance, the performance becomes limited by electrical parasitics. However, the lower the resistance of the top DBR, the smaller the allowed aperture, which in turn allows for better VCSEL performance, including a high energy efficiency per bit of information transferred (well below lOOfJ/bit).14 In Fig. 6(a) we show a VCSEL module used for data transmission experiments (product V40-850M produced by Vl-Systems GmbH). A 30 GHz bandwidth 850 nm pin photodetector (PD) module (product D30-850M produced by Vl-Systems GmbH) is used for signal detection. The related bit-error ratio (BER) versus received optical power data for the VCSEL-to-PD link is shown in Fig. 6(b). In Fig. 7 we show optical eye diagrams and the experimental setup for the data transmission experiment performed in the non-return to zero (NRZ) coding scheme using a pseudo-random binary sequence (PRBS) of word length 2 7 -l. We used 40 Gb/s transmitter and receiver subassemblies from Vl-Systems GmbH integrated with 40 Gb/s driver and transimpedance amplifier integrated circuits (ICs). Optical "eye diagrams" for the data transmission experiments are shown. These diagrams show "0" and "1" voltage levels superimposed onto the time period for a single bit transmission. For error-free data transmission the related "1" and "0" horizontal levels must remain well separated in the vertical (voltage) and in the horizontal (time) space for any random sequence of bits ("1" after "0", "1" after multiple "0"s, and so on). The ultimate bit rate is limited by the finite rise and fall times of the optical devices. Operating the device at different power levels is typically accompanied by relaxation oscillations and overshoot effects that distort the optical eye diagrams via the broadening of measured voltage levels. These effects may result in "1" and "0" levels broadened and overlapped even in the case where the

150

Future Trends in Microelectronics

Figure 6. (a) Multimode fiber (MMF)-coupled VCSEL transmitter module of VISystems GmbH and (b) experimental data transmission at different data bit ratios over 100 meters of OM3+ MMF. No pre-emphasis was used for driving the VCSEL module.

Figure 7. Experimental setup and optical eye diagrams using the standard NRZ coding scheme with a PRBS of word length 27-1 at different bit data rates. TO-form factor 40 Gb/s transmitter and receiver modules with integrated driver and transimpedance amplifier electronics were used, with no feed-forward equalization.

151

Ultrafast Nanophotonic Devices for Optical Interconnects

rise and fall times of the device are very short. Thus a wide eye opening as revealed in Fig. 7 indicates that the existing VCSEL and pin PD chips and the related electronics are suitable for high-speed data transmission at low power consumption up to 40 Gb/s. No electronic corrections of the rise and fall times of the device were applied.16 4. Improved temperature stability of 850 nm VCSELs The main reason of degradation of the VCSEL performance is an overheatinginduced leakage of nonequilibrium carriers from the gain medium into the surrounding AlGaAs-based injector regions.16 While the barrier height for the heterojunction band offset in the valence band is very significant (0.5-0.6 eV for the GaAs/AlAs heterostructure), the barrier height in the conduction band is much smaller (< 0.2-0.3 eV). This barrier height can be increased somewhat by using Alo.4Gao.6As barrier layers (compositions close to the Г-Х cross-over point), but not very significantly (to -250-350 meV). Since this is a fundamental problem in AlGaAs materials, the only solution is to extend the layer compositions by using additional III-V materials having more suitable band offsets. Among these materials, GaP provides the highest conduction band energy and thin GaP insertions may be suitable for effective electron confinement17 of nonequilibrium carriers in modern GaAs-based VCSELs. On the other hand, as it follows from Fig. 8, A1P provides a very significant barrier in the valence band. In the case where the insertions, made of the related materials, are properly introduced into the epitaxial structure surrounding the gain region, the leakage of nonequilibrium electrons and holes can be significantly suppressed.

A£c~-0.4eV|

o O

AlP EG

~ 2.45 eV

J^"

GaP

EG - 2.26 eV

£V

0.59 eV £

0.2

0.4

0.6

0.8

Al content x in AlGaAs

Figure 8. (a) GaP provides the highest conduction band energy among the other conventional lll-V materials; (b) conduction and valence band energies of the AlxGa^xAs alloy at room temperature. Conduction band minimum and valence band maximum of the unstrained GaP are superimposed in the figure to show the advantage of this material for achieving an optimal electron confinement.

152

Future Trends in Microelectronics

We note that GaP and GaAs lattice parameters differ significantly and the tensile biaxial strain applied to thin GaP layers may affect the X minimum energy of the conduction band significantly. In Fig. 9 we show the calculated X-point conduction band minimum energy of a strained GaP film as a function of substrate lattice parameter and orientation. Evidently, misorientation towards the crystallographic direction dramatically increases the conduction barrier height. Another important consideration is related to the surface morphology. Highindex GaAs surfaces misoriented towards the direction, like GaAs (611)A or GaAs (311)A, spontaneously transform to periodic arrays of nanofacets during the epitaxial growth. This periodic surface nanofaceting stimulates the formation of natural tilted superlattices through the step-edge-driven alloy phase separation.18 The InGaAlP barrier regions around the active zone have been shown to be corrugated in thickness,18 further suppressing the biaxial strain. Our experience with strained GaP-rich (Ga,As)(Al,P) barrier structures demonstrates that 850 nm VCSELs with good and temperature-insensitive parameters up to 100 °C can be fabricated by this approach. Thus, high conduction band barriers are clearly feasible. Relaxation resonance frequencies above 10 GHz were realized at currents a factor of ~4 lower than the roll-over current. Both the resonance frequency and the optical eye diagram at 25 Gb/s were nearly unchanged in the range between room temperature and 100 °C.

Figure 9. Calculated X-point conduction band minimum of a strained GaP film vs. substrate lattice parameter on (100) and (111) substrates. Substrate misorientation from the exact (100) surface towards a (111) surface results in a significant increase in the barrier height.

Ultrafast Nanophotonic Devices for Optical Interconnects S.

153

Single-mode VCSELs for data transmission

The major limiting factor for multimode VCSEL transmission over large distances at high data rates is the chromatic dispersion of the optical fiber. To extend the link length, VCSELs with a narrow emission spectrum - ideally, single-mode (SM) devices - are necessary. Previously, 1300 nm SM laser transmission over MMF was demonstrated, resulting in the 10 Gb/s IEEE 802.3.aq standard.19 More recently, 1300 nm links were shown to operate at 40 Gb/s over 400 m of wavelength-optimized MMF.20 To meet the IEEE standards, the encircled flux condition in the MMF should be fulfilled at large coupling tolerances for the alignment between the VCSEL and the MMF. In our coupling experiments, a significant decrease of power was observed only at a -12 um offset of the VCSEL with respect to the center of the 50 um fiber for both SM and MM devices, with no impact of the tilt angle (0-80).9 Figure 10 presents MMF data transmission experiments at 25 Gb/s, showing error-free data transmission over 600 m of MMF.

Figure 10. (a) 25Gb/s data transmission from 3 m up to ~600 m of MMF; together with emission spectrum (b) and the two optical eye diagrams (at 3 m and at 603 m) (c) recorded at the low received powers just sufficient for error-free operation at 25 Gb/s. The detector is a 35 /vm-diameter pin PD chip (VIS model D20-850M).

6.

Large-aperture single-mode VCSELs and coherent VCSEL arrays

Single-mode VCSELs with large apertures are challenging to produce. One approach to reach SM operation is to minimize the impact of the aperture on the refractive index contrast between the gain and the surrounding regions by using proton implantation. However, the overall properties of such devices are inferior and they are much less energy-efficient than oxide-confined VCSELs. As discussed in Section 2, unless very small aperture diameters of about 4 um or less are used, high-speed VCSELs typically operate in multiple transverse modes. Additionally, small apertures require extreme processing tolerances to ensure high manufacturing yields. Small aperture devices also suffer from electrostatic discharge effects. An approach of thin oxide aperture layers placed at the node positions, separated from A/4 DBR layers with a high AlAs-composition has been

154

Future Trends in Microelectronics

proposed. It is claimed that this may allow single mode operation up to an oxide aperture diameter of -10 цт. 8 However, once the aperture layer is made very thin, the capacitance of the device increases. The fundamental optical mode also becomes sensitive to thermal lensing at moderate temperature gradients and also to nonuniformities in the oxidation process. An alternative approach to SM VCSELs at large aperture sizes is based on anti-guiding VCSEL designs. These are typically obtained by etching the VCSEL mesa and then completing an overgrowth with a higher refractive index material, which suppresses the high-order modes via leakage.21 This effect may additionally be used for the coherent coupling of antiguided VCSELs into lateral arrays. Interestingly it is usually assumed that oxide-confined VCSELs with relatively thick aperture layers are index-guided devices and are inherently multimode at large apertures. However, unlike infinite-length multimode optical fibers with multiple index-confined guided modes, the VCSEL mode is inherently leaky. This mode represents a highest order mode of the vertical micro-resonator, which has lateral dimensions much larger than the vertical extension of the optical field. In addition to the VCSEL mode, there are multiple other modes propagating through the structure at the same X but at different tilt angles with respect to the layer planes. The fundamental mode of the VCSEL structure is the mode propagating parallel to the surface at a minimum tilt angle with respect to the lateral plane. In the absence of an oxide aperture exists, the coexisting VCSEL and tilted modes are quasi-orthogonal, as they have a different number of nodes in the optical field profile in the vertical direction. Thus, a VCSEL mode cannot be converted to a lower order mode of the structure without an optical defect to disturb the optical field. This is also true in the case of different optical modes propagating through a thick multimode waveguide or multimode glass fiber. Once oxidized AlGaAs regions are introduced in the VCSEL structure, the optical fields in the oxidized and non-oxidized parts of the structure become very different. The related VCSEL and surrounding medium modes become nonorthogonal, basically allowing leakage of the VCSEL modes into the surrounding oxidized region. As the excited VCSEL modes have field intensity maxima shifted towards the edge of the aperture region, they may interact with the modes in the oxidized section more effectively and can be selectively suppressed by enhanced leakage to avoid undesirable effects. In commonly used oxide-confined VCSEL designs these effects are relatively weak, however, because the optical field in the oxidized part is only weakly affected by the oxide apertures and the modes of the two different parts of the structure remain quasi-orthogonal. The related overlap integral reaches only a few percent. On the other hand, in VCSEL designs where the optical field is strongly disturbed, the leakage can be enhanced and intentionally engineered by allowing a resonant leaky mode in the oxidized section with a very significant overlap integral (30-70%). Thus the high-order transverse modes can be dramatically suppressed, while the fundamental mode remains strongly localized by the thick oxide layers. The refractive index profile and optical field distribution of an 850 nm VCSEL suited for SM operation at large oxide-confined apertures is shown for the cavity region (Fig. 11) and for the oxidized part (Fig. 12) of the VCSEL structure.

Ultrafast Nanophotonic Devices for Optical Interconnects

155

Figure 11. (a). Real refractive index profile of a resonant-leakage VCSEL in the aperture region showing AI(Ga)As layers subject to oxidation that are not oxidized. (b). Electric field strength profile calculated for the vertical optical mode of the VCSEL structure of Fig. 11 (a) in the aperture region.

Figure 12. (a). Real refractive index profile of a resonant-leakage VCSEL in the region surrounding the aperture showing oxidized AI(Ga)As layers in the oxideconfinement part of the VCSEL structure, (b) Electric field profile calculated for the vertical optical mode of this VCSEL-like structure in the oxidized region surrounding the aperture. The mode has a wavelength of 864 nm.

Future Trends in Microelectronics

156

In Fig. 13 we show the optical power reflectance spectrum of the resonant leakage VCSEL of Fig. 11(a) calculated for the nonoxidized aperture region at normal incidence and revealing an etalon dip at 850 nm. The optical power reflectance spectrum for the oxidized part of the structure of Fig. 11(b) reveals a blue shift of the cavity mode in the oxidized region, as well as the appearance of the second cavity resonant mode with a basically similar optical field profile as the VCSEL mode in the aperture region. As it follows from Fig. 13 the VCSEL fundamental mode appears to be in the continuum of the cavity mode in the oxidized region, which has a similar field distribution. The tilt angle of the VCSEL-like mode in the oxidized region necessary to reach the wavelength of the fundamental mode of the VCSEL section (a)

Г

VCSEL in aperture region at normal V incidence

a3

o

VCSEL in aperture region at normal incidence i—r

T—I—I—I—I—I—I—I—I—I—Г

780 800 810 820 830 810 860 860 870 880 8 » M 0 810

790 800 810 820 830 840 850 860 870 880 890 800 910

Wavelength (nm)

(b),

(d), L

Wavelength (nm)

0>

1

i_ 0.1

I

VCSEL in oxide region at

O. normal incidence ao3 „

п

1 1 1 1 1 1 1 1 1 r

790 800 810 820 830 840 850 880 870 880 890 900 910

I

1.

Wavelength (nm)

VCSEL in oxide region oblique incidence, 10° in AIGaAs

T—I—I—I—I—I—I—I—I—I—I-

790 800 810 820 830 840 850 860 870 880 890 900

Wavelength (nm)

Figure 13. (a) Optical power reflectance spectrum of the VCSEL of Fig. 11(a) calculated for nonoxidized aperture region at normal incidence, with an etalon dip at 850 nm. (b) Optical power reflectance spectrum of the oxidized VCSEL section of Fig. 12(a) at normal incidence, with etalon dip shifted to a shorter 843 nm wavelength and another peak at 865 nm. (c) Same as (a) for comparison to (d) optical power reflectance spectrum of the oxidized part of the structure calculated at oblique incidence and with s-polarization, tilted by 10° with respect to the surface normal. At this angle, the tilted VCSEL-like mode in the oxidized region reaches the VCSEL fundamental mode and the modes can transform into each other with a high probability (30% overlap). The interaction with the resonant leakage mode in the oxidized region is much stronger for the excited lateral modes, which have intensity maxima shifted towards the edges of the aperture region.

Ultrafast Nanophotonic Devices for Optical Interconnects

157

corresponds to the leakage angle of the VCSEL mode into surrounding areas. In spite of the different number of nodes in the VCSEL and the oxide VCSEL mode, the overlap integral easily reaches values of 30-70% dependmg on the exact matching of the optical fields. The smaller the spectral separation between the etalon dips and the larger the overlap integral, the higher the leakage. This resonant leakage oxide-confined VCSEL approach is also useful for the fabrication of field-coupled coherent VCSEL arrays, which are otherwise realized by etching and overgrowth. Two-dimensional beam steering can be realized by providing different currents to different VCSEL segments of the structure. A practical approach for fabrication of such arrays is illustrated in Fig. 14. The coherent VCSEL array device can be made possible by in-phase coupling of the optical fields through the leakage into the oxidized regions, as in Fig. 14. 7.

Conclusions

To conclude, we have briefly described the recent progress in oxide-confined 850 nm VCSELs and made proposals for their improvement. Ultrahigh speed, extreme temperature stability, a stable far field pattern, and single-mode operation at large aperture sizes are feasible in these advanced VCSELs.

Figure 14. Schematic top view of the coherently coupled VCSEL array realized through resonant leakage in the oxidized regions (grey areas). White circles are holes etched through the structure to enable the lateral oxidation process. Crosshatched areas are the oxide-confined aperture regions for current injection.

158

Future Trends in Microelectronics

Acknowledgments We appreciate support of the SEPIANet grant of the EU PIANOPLUS project. Helpful discussions with J.-R. Kropp, P. Moser, P. Wolf, G. Larisch, A. Mutig, G. Fiol, T. Germann, A. Payusov, S. A. Blokhin, L. Ya. Karachinsky, M. V. Maximov, A. M. Nadtochiy, and D. Bimberg are greatly appreciated. References 1. 2. 3. 4. 5.

6. 7. 8. 9. 10. 11. 12. 13. 14.

See, for example: http://www.hardwareboard.eu/topnews/intel-mit-8nmfertigung-in-2 015-187/ See http://www.top500.org/ See IEEE tutorial: http://www.ieee802.org/802_tutorials/2012-07/BWA Tutorial_Dl_12_0716.pdf CEI-56G-VSR project start proposal http://www.parallaxgroup.com/media/ oif2012.088.03.pdf P. Pepeljugoski, P. Coteus, "Bandwidth needs in HPC taking into account link redundancy," IEEE 802.3 Ethernet Bandwidth Assessment Ad Hoc, IEEE Plenary Meeting, Atlanta, GA (Nov. 8, 2011), see http://grouper.ieee.org/ groups//802/3/ad_hoc/bwa/public/novl l/pepeljugoski_01 _111 l.pdf A. Benner, "Optical interconnects for HPC: Short-distance high-density optical interconnects," OIDA Roadmapping Workshop, Stanford Photonics Research Center, Stanford University, CA (April 12-13, 2011). N. N. Ledentsov, J. A. Lott, V. A. Shchukin, et al., "Quantum dot insertions in VCSELs from 840 to 1300 nm: Growth, characterization, and device performance," Proc. SPIE 7224, 7224-23 (2009). V. P. Kalosha, N. N. Ledentsov, and D. Bimberg, "Design considerations for large-aperture single-mode oxide-confined vertical-cavity surface-emitting lasers," Appl. Phys. Lett. 101, 071117 (2012). N. N. Ledentsov, J. A. Lott, J.-R. Kropp, et al, "Progress on single mode VCSELs for data- and tele-communications," Proc. SPIE 8276, 82760K (2012); doi:10.1117/12.902643 M. J. Noble, J.-H. Shin, K. D. Choquette, J. P. Loehr, J. A. Lott, and Y.-H. Lee, "Calculation and measurement of resonant-mode blueshifts in oxideapertured VCSELs," IEEE Photonics Technol. Lett. 10, 475 (1998). J. A. Lott, V. A. Shchukin, N. N. Ledentsov, A. M. Kasten, and K. D. Choquette, "Passive cavity surface emitting laser," Electronics Lett. 47, 717 (2011). J. Tatum, "Optical components for 100 Gb/s," IEEE 802.3 Higher Speed Study Group Meeting (2006), see http://grouper.ieee.org/groups/ 802/3/hssg/public/nov06/tatum_01_l 106.pdf N. N. Ledentsov, J. A. Lott, D. Bimberg, et al, "High-speed single-mode quantum dot and quantum well VCSELs," Proc. SPIE 7952, 79520J (2011), doi:10.1117/12.880404. P. Moser, P. Wolf, J. A. Lott, et al, "81 fJ/bit energy-to-data ratio of 850 nm vertical-cavity surface-emitting lasers for optical interconnects," Appl. Phys. Lett. 98,231106(2011).

Ultrafast Nanophotonic Devices for Optical Interconnects

159

15. A. V. Rylyakov, C. L. Schow, J. E. Proesel, et al, "A 40-Gb/s, 850-nm, VCSEL-based full optical link", Proc. Optical Fiber Commun. Conf. (2012), paper OThlE. 16. P. P. Baveja, B. Kogel, P. Westbergh, et al, "Impact of device parameters on thermal performance of high-speed, oxide-confined, 850 nm VCSELs," IEEE J. Quantum Electronics 48, 17 (2012). 17. N. E. Christensen, "Possibility of heterostructure band offsets as bulk properties: Transitivity rale and orientation effects," Phys. Rev. B 38, 12687 (1988). 18. V. A. Shchukin, N. N. Ledentsov, I. P. Soshnikov, et al, "Nanofaceting and alloy decomposition: From basic studies to advanced photonic devices" Microelectronics J. 37, 1451 (2006). 19. D. M. Kuchta and C. J. Mahon, "Mode selective loss penalties in VCSEL optical fiber transmission links," Photonics Technol Lett. 6, 288 (1994). 20. P. Matthijsse, G. Kuyt, F. Gooijer, et al, "Multimode fiber enabling 40 Gb/s multi-mode transmission over distances > 400 m," Proc. Optical Fiber Commun. Conf. (2006), paper OWI-13, doi: 10.1109/OFC.2006.215497. 21. Y. A. Wu, G. S. Li, R. F. Nabiev, K. D. Choquette, C. Caneau, and C. J. Chang-Hasnain, "Single-mode, passive antiguide vertical cavity surface emitting laser," IEEEJ. Selected Topics Quantum Electronics 1, 629 (1995).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Will Optical Communications Meet the Challenges of the Future? Djafar K. Mynbaev Dept. of Electrical and Telecommunications Technology New York City College of Technology-CUNY, Brooklyn, NY 11201, U.S.A.

1.

Introduction

For the last 25 years, optical communications has transformed our lives thanks to its ability to deliver enormous data streams at the highest possible transmission speeds. Indeed, optical communications are the backbone of the Internet, cable TV, telephone (both landline and mobile), and business data networks. In fact, today optical networks deliver more than 98% of the total telecommunications traffic. The global optical network has increased its transmission capacity by a factor of 1000 over the last 20 years, but to meet the exponentially growing traffic demand, the capacity has to be increased another thousand-fold over the next two decades. Is this achievable? A network's transmission capacity is defined by: (i) transmission speed, determined by the capability of the ensemble of all the physical components of the network to transmit traffic at the required rate; and (ii) the network's bandwidth requirements, determined by its load, architecture and protocols. Developments in the logic (intelligent) network layer will eventually result in a decrease in the traffic burden, but they fall outside the scope of this chapter. Here we will concentrate on the physical layer of the optical network, which will have to contribute the largest portion of the transmission capacity's future growth if the industry is to meet tomorrow's demand for high-speed, highvolume traffic flow. At the physical layer, the transmission capacity is determined by the capacity of both the links (optical fibers and optical amplifiers) and the nodes. The theoretical limit of the transmission capacity of a conventional fiber-optic communication link is about 100 Tb/s over a typical long-distance span, and even higher transmission has been demonstrated in the laboratory. Another important factor to note is spectral efficiency (SE). Experimental transmission at SE approaching the theoretical limit (which is about 9 bit/s/Hz) have been recently reported. Thus, the optical link is coming ever closer to its theoretical limits. The role of nodes in expanding the capabilities of the optical network can best be demonstrated by reference to the immediate past. During the 1990's, growth in the transmission capacity of the optical network was achieved mainly through wavelength-division multiplexing (WDM), made possible by optical amplifiers. Over the last several years we have seen transmission capacity rise from 10 Gb/s to 160

Will Optical Communications Meet the Challenges of the Future?

161

100 Gb/s, due mainly to coherent communications that rely on sophisticated modulation formats in conjunction with digital signal processing (DSP) of the received signal. All these advances relied on great progress in the development of electronic and photonic components for the optical networks - that is, the components residing in the nodes. However, the node equipment, particularly the electronics, is also beginning to approach technological limits. This chapter will discuss the current status of optical communications technology and the relevant limitations. We will consider some directions in future developments that would catalyze another thousand-fold increase in transmission capacity of optical networks over the next 20 years. An analysis of the problems of modern optical communications and projections of potential solutions to these problems should spur future research and development in both the optical and electronics fields to the mutual benefit of both industries in the years ahead. 2.

The road to modern optical transmission technology

An ideal optical communication system consists of a transmitter (Tx), optical fiber (OF), and a receiver (Rx). A digital electrical input signal is processed by the Tx electronics and is transformed into a light signal by the laser diode (LD). The light signal travels through an optical fiber to a destination point, where it is converted back into electrical form by the photodiode (PD) and processed by the Rx electronics for delivery to an end user. The real system, however, suffers from two mam drawbacks: the attenuation of signal power over the transmission distance and the decrease in the optical link's transmission capacity due to spreading of the optical pulse caused by dispersion. Signal attenuation - the first major hurdle in expanding optical links over the long distance - was initially overcome by using repeaters (regenerators). These are devices based on optical-electrical-optical (OEO) conversions with power recovery and dispersion compensation performed electronically. The main breakthrough in developing optical networks came with the advent of optical amplifiers (OAs), in which amplification is done completely in the optical domain. Dispersion - both chromatic dispersion (CD) and polarization-mode dispersion (PMD) - was the second hurdle that put limits on transmission distance. The goal of eliminating OEO repeaters (and any other electronic parts, for that matter) in an optical link was partly achieved by using all-optical dispersion-compensation modules (DCMs). All these explanations are visualized in Fig. 1 and discussed in more detail elsewhere.1'2 Initially, the development of optical communications relied on the tremendous potential transmission capacity of OF, but as the volume of traffic grew, it became clear that even for a simple point-to-point link, the transmission capacity is determined by the entire system, rather than just the fiber. For one thing, an optical fiber could theoretically support a 100 Tb/s data rate, whereas a Tx and Rx could, until recently, support only 10 Gb/s.

162

Future Trends in Microelectronics

Figure 1. Evolution of an optical communications link: (a) ideal optical link; (b) attenuation and loss of bandwidth due to signal degradation; (c) optical compensation for the loss of power and pulse spread. An optical pulse in a fiber loses power primarily because of scattering and bending, and broadens due to dispersion. To compensate signal degradation in the optical domain, the industry developed optical amplifiers (OAs) and dispersion-compensation modules (DCMs). Wavelength division multiplexing was a technology that solved this problem. By combining N different wavelengths into one stream traveling through one OF, WDM increases of transmission capacity by a factor of N. The key technology allowing for successful commercialization of WDM was OAs, which boost the power of optical signals of all wavelengths without OEO conversions. As a result, WDM systems were responsible for tremendous increase of optical networks without installation of additional OF links. Indeed, with more than 80 wavelengths (channels) available today at 100 Gb/s each, the data rate rises to 100 Gb/s x 80 = 8000 Gb/s, which is still very far from the theoretical capacity of an OF. From standpoint of the optical transmission system, there were two other important advances enabling to an increase in the data rate. The first was the advent of external optical modulators (OMs), which modulate cw light generated by LDs operated in a steady-state regime, thereby increasing the capacity of a single Tx up to 40 Gb/s. Thus, OMs increased the transmission capacity of the interfaces between incoming electrical signals and OFs. The second was the development of optical switches, such as optical cross-connects and reconfigurable optical add-drop multiplexers, which redirect the light signals in optical domain.

Will Optical Communications Meet the Challenges of the Future?

163

Thus, the transition from electronic to optical technology (OA, DCM, WDM + OA, external OM, optical switching) enabled achievement of 10 Gb/s data rates by the beginning of this century. This transition reflected the mam trend in the development of optical communications: replacing electronic components with the optical ones. The ultimate goal is to build an all-optical network in which information signal will be transmitted, routed and processed in the optical domain, leaving electronic formats outside the optical segment of a network. Today, partial implementation of this approach has increased the optical transmission capacity to up to 100 Gb/s in commercial networks and 1 Tb/s in research trials.

3.

Today's optical communications - developments and limitations

Thus, over the last 25 years, the data rate of optical networks has increased a thousand-fold, from 100 Mb/s to 100 Gb/s. Let us briefly consider some of the limitations on the key advances that led to this progress. Modulation formats From its inception, until late in the last decade, optical communications has used intensity modulation (IM), where a light pulse represents logic 1 and a period of darkness represents logic 0. This IM format eventually became a bottleneck limiting the bit rate of a Tx. Though a modern Tx can operate at a bit rate up to 40 Gb/s today, it still modulate the intensity of light and, because of this, its ability to further increase the bit rate looks problematic. New modulation formats increase the transmission capacity by encoding more bits per symbol, thus delivering more bits "wrapped" into fewer transmitted symbols. This is achieved by modulating not the amplitude but the phase of the light carrier signal. An example is the quadrature phase-shift keying (QPSK) modulation, which encodes two bits per symbol. Along with dual polarization (DP), the DP-QPSK format allows for the transmission of four bits per symbol - see Fig. 2. Building higher-order modulation formats (encoding more bits per symbol) is the main trend in the development of optical transmission systems. Using the 16quadrature amplitude modulation (16-QAM) format along with polarizationdivision multiplexing (PDM) and other cutting-edge technologies, a transmission bit rate of 16.672 Tb/s over almost 7,000 km was recently demonstrated.3 A limitation on progress in this area is inherent in Shannon's limit: increasing the number of bits per symbol requires a substantial improvement in the optical signal-to-noise ratio (OSNR). For example, a bit rate of 224 Gb/s using 16-QAM modulation requires a minimum 17.4 dB OSNR, whereas a bit rate of 448 Gb/s using 256-QAM needs a minimum 31.9 dB OSNR.4'5 What's more, higher-order modulation formats decrease the system's tolerance to OF nonlinearities because each symbol requires more power. Improvement in OSNR could be achieved by increasing the power of an optical signal, but an increase of this power will make nonlinear effects more pronounced. Still unresolved, this contradiction sets the limitation on transmission distance. •

164

Future Trends in Microelectronics

Figure 2. Modulation formats: (a) dual polarization (DP) and (b) constellation diagram for the on/off key (OOK), and the in-phase (I) plus quadrature-phase (Q) components for quadrature phase-shift keying (QPSK), DP-QPSK, and DP 16 quadrature amplitude modulation (16-QAM). The figure also shows the number of bits per symbol that each modulation format carries.

Coherent transmission technology This technology is the major breakthrough that has raised the optical bit rate tenfold, from 10 Gb/s to 100 Gb/s, over the last several years. Interestingly, optical coherent detection was proposed at the dawn of the fiber-optic communications era; however, even 10 years ago it was not considered a promising approach to improving the optical transmission.2 Today, coherent transmission is the front-end technology being deployed at a fast rate all around the world. This change happened due to a revolution in modern electronics. A coherent detection system employs a local oscillator (LO) laser whose optical signal is mixed with the incoming signal, which contains a combination of an optical carrier and information signal. When the local signal's frequency coincides with the carrier frequency, they eliminate each other and the information is detected. This process occurs simultaneously and independently for each channel (wavelength) in WDM transmission. The detected information signals undergo DSP in real time (this is where modern electronics comes into play!) and the DSP provides the electronic compensation for both CD and PMD dispersions. Combined with modern modulation formats, coherent technology has increased the bit rate up to 100 Gb/s today with the potential for increasing the bit rate up to 1 Tb/s in the near future. •

Figure 3 demonstrates the principle of operation of a coherent transmission system. The coherent Tx in Fig. 3(a) uses the external modulators that are driven by analog signals obtamed after digital-to-analog conversion (DAC). Before transmission, the modulated signals undergo phase shifts, polarization rotations and optical combination. The coherent Rx in Fig. 3(b) extracts the information signals by mixing the LO laser signal with the received signal. The recovered information signal undergoes analog-to-digital conversion (ADC) and digital signal processing (DSP) in real time. The opto-electronic segment of a coherent detector working with a DP-QPSK signal is illustrated in Fig. 4(a), whereas a modern 90 nm CMOS ASIC chip8 with 23 Gsample/s ADCs and 1.2xl013 operations per second is shown in Fig. 4(b). Dual polarization can be used without coherent detection, but modern coherent techniques allow for more accurate extraction of polarization-multiplexed signals without using the polarization-maintenance (PM) components.

165

Will Optical Communications Meet the Challenges of the Future?

(a) ■■« oAc ■

>:

—•»: DAc ;

>; '■;:•■'•

[

>| Beamsplitter |

User

I

->i DAC •

•>: ,...•' jf ^ *

■--* OAC ;

Modulator 2 Modulator ^(~n/2

v

^гт

Н\ч

>!

(b)

+ » Received signal

Balanced I I photoreceiver array Polarization rotator

Polarization beamsplitter

WTT'

90° optical hybrid

^"~—"~^ I "

GST +

:

ADC + DSP

••« LO Laser

^

Beamsplitter

90° optical hybrid

+ + Figure 3. Principles of operation of a coherent transmission system: (a) coherent transmitter; (b) coherent detector.6

The underlying physics of the coherent technology is that the detection of an IM signal is based on a square-law response (power in, current out), whereas coherent detection is based on a linear law in a detecting electric field. Since both chromatic dispersion and polarization-mode dispersions are distortions that are linear with respect to the signal's electric field, coherent detection can remove dispersion-caused distortion of a signal by a linear filtering (DSP) process.

166

Future Trends in Microelectronics

Figure 4. (a) Waveforms7 and constellation diagrams of a received signal in optical and electronic domains, showing how the opto-electronic segment of the coherent detector works for one of the DP-QPSK signals, (b) An example of the electronics used in modern coherent detectors:8 90-nm CMOS receiver ASIC with 23 Gsample/s ADCs and 12 trillion operations per second [reprinted with permission].

A list of other advantages of coherent transmission technology includes: (i) a significant improvement in noise tolerance compared with direct detection; (ii) elimination of DCMs and accompanying OAs because of full electrical dispersion compensation; and (iii) more efficient use of the transmission spectrum, exemplified by a DP-QPSK system, where one wavelength carries the same amount of information that four wavelengths would using IM modulation. In coherent detection, linear digital filters are used to compensate for dispersioncaused signal impairments. However, when signal line rates reach 10 Gb/s and above, these filters cannot be built on microprocessors or FPGAs because they are not capable of supporting such high-speed operation. As a result, the industry moved to CMOS ASICs - see Fig. 4(b) for an example.8 The shift from electronics based on III-V elements to silicon CMOS has lowered the cost of circuitry, increased the integration scale and decreased the heat dissipation. In addition to the limitations imposed by increasing the order of the modulation formats mentioned above, two major limitations to the capacity of the current coherent transmission technology are on the horizon. First, even today's transmission systems operate at the edge of electronic processing capabilities; thus,

Will Optical Communications Meet the Challenges of the Future?

167

increasing the bit rate will require another revolution in electronic technology. A second limitation is that the higher transmission capacity will become more sensitive to the fiber's nonlinearity, such as nonlinear phase noise and cross-phase modulation.2 Wavelength division multiplexing, optical amplifiers, and spectral efficiency As explained above, WDM and OAs technologies were two breakthroughs that enabled the leap from a bit rate of Mb/s to Gb/s. In its current form, WDM is facing a new challenge because channels with bit rate beyond 100 Gb/s do not fit the ITU-T grid, as shown in Fig. 5. The solution to this problem is a transition to gridless (flexible) WDM transmission. Abandoning the standard grid will also result in a 30% increase of the available spectrum within the C- and L-bands used for long-term optical transmission. It should be noted, however, that while gridless WDM transmission is easy to implement in a point-to-point link, it will be difficult to operate without standard wavelength allocation in a network environment. As for OAs, the workhorse of this technology today is erbium-doped fiber amplifiers (EDFAs). The EDFA technology suffers from: (i) restricted bandwidth, since one EDFA can cover either the C- or the L-band, but not both; (ii) low noise figures resulting in degradation of the line's OSNR; and (iii) additional nonlinearities in OF because of their lumped nature. The use of Raman amplification in hybrid configuration with EDFAs significantly mitigates these •

Figure 5. WDM transmission: spectral widths of various bit-rate signals vs. ITU-T grid.9 Channels with bit rates beyond 100 Gb/s will not fit the ITU-T grid, but the proposed flexible grid could accommodate any channel.

Future Trends in Microelectronics

168

problems. Still, we have yet to reach the ideal features of an OA - a wide spectral bandwidth, low-noise operation and the minimal imposition of nonlinearities, along with the desired adaptive gain, - in real optical amplifiers. A fundamental limitation of WDM transmission is the spectral bandwidth (SBW), that is, the range of wavelengths where attenuation of a silica fiber is minimal. Long-range optical transmission uses the C-band (1530-1562 nm) and the L-band (1565-1625 nm). Thus, SE is defined as line rate divided by the available SBW; it is the integral criterion of optical transmission performance because it shows how efficiently we use the available spectrum for transmission. Though the theoretical limit for fixed channel spacing is considered to be around 9 bit/s/Hz, the fundamental limit is still the available SBW. Figure 6 shows the various approaches to improving SE. In general, as SE increases, the receiver sensitivity (and therefore - the transmission distance) decreases. However, using sophisticated modulation and decoding techniques, researches have achieved a 160x100 Gb/s bit rate over 6,860 km (a record-high transmission) with SE = 5.2 bit/s/Hz and good receiver sensitivity.3 There are a number of other important aspects of optical transmission, in particular the issues of optical networking. Their detailed discussion falls outside the scope of this chapter, though we refer to some of these issues in Table 2 below. 3.

A glance into the future

Ironically, even as industry has dreamt about all-optical communication from the dawn of fiber-optic communication, the main breakthroughs to date have been

Figure 6. Possible approaches to improving the spectral efficiency in WDM transmission. This figure also shows the limitations specific for each approach.

Will Optical Communications Meet the Challenges of the Future?

169

achieved with electronics. However, the demand for a further increase in transmission speed continues to grow: at a 40% compound yearly growth rate, traffic volume will increase by a factor 1000 in 20 years. Given that the current optical network capacity approaches 1 Tb/s, we will need a transmission speed of 1 Pb/s. The current state and trends in developing of telecom electronics do not promise such a rapid increase any time soon. Therefore, we need to consider other optical network resources, with two main directions being:10 (i) technological advances aimed at increasing network capacity; and (ii) architectural enhancements intended to reduce the capacity demand. Table 1 presents our projections in technological advances and quantitative measures of these advances — cumulative capacity multipliers. The following general comments on Table 1 are intended to further clarify the anticipated developments. Opticalfiberand optical amplification Reducing attenuation would result in increasing transmission distance. Over the last decade, the attenuations of single-mode (SMF) and multi-mode (MMF) fibers have been reduced from 0.2 to 0.16 dB/km and from 3.0 to 2.5 dB/km, respectively; achieving SMF attenuation smaller than 0.1 dB/km could be possible. Reducing dispersion (more precisely, the tolerance of high-bit-rate signals to CD and PMD) would also increase the transmission distance. Reducing the tolerances •

Optical link

Advances

Individual capacity increase

Optical fiber and optical amplification

Reducing attenuation, dispersion and nonlinearities and expanding usable SBW (better manufacturing, large-effective area, new glasses, less dispersive OF, even amplification, and new OAs)

~2

Spatial-division multiplexing (multi-core fiber and few-modes fiber)

~6

Fixed grid WDM networks (bit rate and channel spacing)

-1.2

GridlessWDM networks (multiple carriers and flexible bandwidth allocation)

-1.4

Componentsand systems

Photonic integrated circuits and silicon photonics (transceivers, OAs, ROADMs, and switches.)

-1.6

Electronics

CMOS and other technologies (all interface and inlineequipment)

-1.7

Software

FEC(soft- and hard-decision), interface cards' operations, and DSP.

-1.3

Spectral efficiency

Capacity multiplierin technological advances

-70

Table 1. Projected technological advances to increase optical network capacity.

170

Future Trends in Microelectronics

to nonlinearities would enable the launching of more power into an OF, thus increasing the OSNR and transmission distance. Expanding usable SBW would result in more available spectrum for WDM and, hence, less need to increase the SE. Improvements in optical amplification would lead to expanding the transmission distance without exceeding the light-power threshold at any given point in order to avoid inducing additional nonlinearities. Spatial-division multiplexing This is one of the most effective ways of increasing fiber transmission capacity. The concepts of possible approaches—using multi-core fiber and fewmode fiber—have been proven11. Both methods, however, require replacement of millions and millions of kilometers of the existing in-place global optical fibers with new optical fibers. •

Spectral efficiency As illustrated in Fig. 6, going to a gridless WDM network is likely to yield the greatest improvement. •

Components and systems Replacing the existing bulky optical and opto-electrical circuits with photonic integrated circuits (PIC) and the use of silicon photonics would result in more efficient operation of both interface and in-line equipment; it would also reduce the cost of the equipment and improve the equipment miniaturization. •

• Electronics Progress in electronics would result in improved current systems and allow for developing new approaches to optical transmission. Software Software developments would result in more effective operations of such techniques as forward-error-correction codes and DSP as well as the operation of each interface and in-line card. •

Capacity multiplier in technological advances An individual capacity increase shows how much a transmission capacity can be increased by a specific development. The capacity multiplier is the product of all individual multipliers. We have rounded down the exact result, 71.285, to 70 to stay at the conservative estimate. In these calculations we follow the approach developed in Ref. 10. •

Although we have not discussed in detail any architectural enhancements in this chapter, let us complete the picture by summarizing the possible trends in Table 2. Again, some comments on the various projections in Table 2 will follow.

Will Optical Communications Meet the Challenges of the Future?

171

Network

Advances

Individual capacity increase

Elasticoptical networking

Elastictransmission (dynamic assignment of modulation format, adaptive ratio of FEC and payload, intelligent spectrum allocation, and the use of superchannels)

-1.4

Sliceabletransceivers (bandwidth variable transceivers [BVT] and slicing BVT into virtual transceivers)

-1.2

Flexible client i nterconnect

-1.2

IP over optical network

Dynamic connections

-1.3

Packet optical transmission

~4

Efficient IP packing

-1.6

Capacity multiplierin architectural advances

-16

Total capacity multiplierin increasing network capacity

-1120

Table 2. Projections in architectural advances.

Elastic optical networking This is a new approach to building optical networks that features two key aspects: flexible slicing of an available optical SBW and elastic allocation of the network bandwidth.9'11 The latter implies that transceivers can generate optical paths with a variable bit rate and intelligent optical switches can dynamically reconfigure the optical network. We broke down this approach into several relatively distinct advances that are self-explanatory. •

IP over optical network Moving to packet routing, broadly referred to as Internet protocol (IP) transmission, has been the general trend in optical transmission for a number of years now. Still, actual routing occurs in the electronic domain, which, obviously, requires OEO conversion. Progress in optical packet transmission has been made and several technologies are available today. However, all-optical packet transmission (which could be considered mamly as a technological issue), along with efficient IP packing, should contribute the most toward increasing the optical network capacity through architectural advances. •

Capacity multiplier in architectural advances The product of all multipliers gives us 16.773, which we conservatively reduce to 16. •

Total capacity multiplier in increasing network capacity Finally, the total product of capacity multipliers from Tables 1 and 2 shows that a thousand-fold increase of the capacity of future optical networks is achievable, obviously assuming that all of our projections are reasonably accurate. •

Future Trends in Microelectronics

172 4.

Conclusions

We have considered the current state of the art and the main trends in the development of optical networks. Current achievements in optical networking have resulted in our ability to transmit all required information at an acceptable speed, which itself is nothing short of a technological miracle. In the future, however, the demand for network capacity will continue to soar, but fortunately our projections based on current research and trends in technology show that optical communications should meet the challenges of future demands. References 1.

Djafar K. Mynbaev, "What will modern photonics contribute to the development of future optical communication technology?" chapter in: S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: From Nanophotonics to Sensors to Energy, New York: Wiley, 2010. 2. Djafar K. Mynbaev and Lowell L. Scheiner, Fiber-Optic Communications Technology, Upper Saddle River, NJ: Prentice Hall, 2001. 3. H. Zhang, J.-X. Cai, H. G. Batshon, et ah, "16QAM transmission with 5.2 bits/s/Hz spectral efficiency over transoceanic distance," Optics Express 20, 11688(2012). 4. See http://www.lightwaveonline.com/content/lw/en/articles/2012/07/the-pathbeyond-1 OOg. html 5. Y. Miyamoto, A. Sano, E. Yoshida, and T. Sakano, "Ultrahigh-capacity digital coherent optical transmission technology," NTT Tech. Rev. (2012). 6. A. M. Joshi, S. Datta, and A. Crawford, "Multilevel modulation formats push capacities beyond 100 Gb/s," Laser Focus Worlds, 58 (2012). 7. S. J. B. Yoo, "Flexible bandwidth terabit coherent optical communication networks by arbitrary waveform generation and measurement," IEEE Photonic Soc. Newsletter 25, 5 (2011). 8. "Key technology enabiers of 100 Gb/s in carrier networks," Ciena white paper (2011), see www.ciena.com 9. O. Gerstel, M. Jinno, A. Lord, and S. J. B. Yoo, "Elastic optical networking: A new dawn for the optical layer?" IEEE Commun. Mag. 50, S12 (2012). 10. A. A. M. Saleh and J. M. Simmons, "Technology and architecture to enable the explosive growth of the Internet," IEEE Commun. Mag. 49, 126 (2011). 11. T. Morioka, Y. Awaji, R. Ryf, P. Winzer, D. Richardson, and F. Poletti, 'Enhancing optical communications with brand new fibers," IEEE Commun. Mag. 50, S31(2012). 12. G. Shen and M. Zukerman, "Spectrum-efficient and agile CO-OFDM optical transport networks: Architecture, design, and operation," IEEE Commun. Mag. 50,82(2012).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Optical Antennae for Optoelectronics: Impacts, Promises, and Limitations Hooman Mohseni Bio-Inspired Sensors and Optoelectronics Lab (BISOL), EECS Department, Northwestern University, Evanston, IL 60208, U.S.A.

1.

Introduction

Light particles, or photons, have some of the most amazing properties of any particles we know of. They travel with the maximum possible subluminal speed, and carry very little momentum. Their weak interaction with other particles that form common matter allows them to travel through many objects and media without significant loss. Hence photons bring us information from distant corners of the universe. Nonetheless, there are many applications that could benefit tremendously from enhancing photon interaction with an electronic (quantum) transition. Most notable examples are single-molecule sensing, solar power harvesting, and single photon detection - all of which suffer from the weak interaction of photons and quantum emitters or receivers. Therefore, there is growing interest in developing methods that could enhance such interaction where needed. In particular, optical antennae and related plasmonic devices have proved to provide a unique opportunity in this regard. In this chapter, we will first look at the reason for the weak coupling of the photons and electronic transitions in matters. We will then look at metallic structures, and see how they can enhance the coupling in the near-field by hundreds of times, but fail to do so for the far-field. An example of an optical antenna that is capable of radiation enhancement of a quantum emitter and efficient coupling of such radiation from the near field to the far field is then presented. Finally, the optical antenna is compared with the conventional "radio" antenna to show that in fact there is a major difference between the two that could lead to significant unexplored benefits from the optical antenna. 2.

Source of weak coupling of photons to electronic transitions

The source of the weak interaction of photons with an electronic quantum emitter or receiver is the large momentum mismatch between electrons and photons in such a system. In order to provide an easy view of this mismatch, and without losing generality, we can assume an electron confined in a three-dimensional potential well of a linear dimension L. We would like to evaluate the interaction of 173

Future Trends in Microelectronics

174

this "quantum emitter/receiver" with a free-propagating photon. Our electronic quantum system is simply a quantized oscillator that is coupled to another oscillator (i.e. the photon in vacuum), and exchanges energy. The main source of the weak coupling between the two systems is the wavelength (or inversely, the momentum) disparity caused by the energy-momentum dispersion of the electrons and photons. The wavelength of the electron is the order of L, while the wavelength of the photon that could resonate with the quantum transition between the two energy levels of the electronic system is many orders of magnitude larger than L. For a typical atom, this modal mismatch is about three orders of magnitude. It is interesting to ask what L would equalize the momentum of the two particles. The answer turns out to be quite interesting, as the photon energy will be about the equivalent mass of the electron (-OTQC2), which I believe sheds some light on the intimate relation between electrons and photons. Classical evaluation of a simple case: Dipole emission A useful exercise is to evaluate the radiation power of a dipole antenna. This is a classical counterpart of a quantum transition, and despite the significant differences, it provides a tangible insight. Using Maxwell's equations for a dipole with length L, and assuming that L « X (which as we saw in the above is a very good assumption for our case), one can calculate the radiated power for an oscillating current with amplitude /, as:

'«^■T^I ■

where co is the (angular) modulation frequency. In amplitude modulation (AM), there is only a steady-state polarization: J = J 0 + Re[&/(Cu)exp(-icuO], PJ = PJO-

(2)

In contrast, for polarization modulation (PM), there total injection is fixed: J = Jo, Pi = PJO + Re[5P(cú)exp(-KoO] •

(3)

An early paper on spin-lasers has shown the feasibility for slow PM using optical wavepiates at a fixed J (JT1 < J < JV2) and the resulting 400% modulation of emission intensity.1 Fast (со/2л ~ 40 GHz) PM can be implemented using, for example, coherent electron spin precession in a transverse magnetic field for pulsed laser emission with alternating circular polarization, a mode conversion in a ridge waveguide electro-optic modulator, or birefringence.13,17,18 Fast PM from electrical spin injection might be more challenging, but there are independent encouraging developments which seek implementation of fast PM for magnetically storing and reading information.19 An important figure of merit to characterize the dynamic operation of lasers is their bandwidth, which can be calculated from small-signal analysis and the response function R(G>) = |55'(со)|/|5Дсо)|. In normalized form,20

186

Future Trends in Microelectronics |Д(со)/Л(0)| = coR2 [(coR2- co2)2 + y V ] ~m ,

(4)

where coR is the relaxation oscillation frequency and y is the damping factor. The normalized response function coincides with the amplitude of a harmonically driven damped harmonic oscillator.9 The bandwidth of a laser, co3dB, is the frequency at which the square of |Л(со)/7?(0)| is reduced by 3 dB.9 Often, many trends in соз). In Fig. 3 we consider both modulation schemes: AM and PM for different injection polarizations and JTl 0. In this regime, there is a pronounced effect of spin-filtering or spin amplification: emitted light has only negative helicity and thus coR2 is proportional to So'.13 This dependence is analogous to the conventional lasers, in which coR and the bandwidth both increase with the square of the output power.

Figure 3. Frequency response for different injection polarizations Pj. Infinite spin relaxation time xs is assumed except for the broken curves, which are drawn for Pj = 0.5 and TS = XR. Adapted from Ref. 13.

Spin Modulation: Teaching Lasers New Tricks

187

A common feature of the presented AM and PM results is a desirable bandwidth enhancement that becomes bigger with an mcrease in Ph even at constant input power, i.e. at constant (J- J T ). This could be viewed as a dynamic manifestation of the threshold reduction with P}. For AM, the several curves in Fig. 3 calculated for the simplified case of an infinitely long i s still represent an accurate approximation. Even for a relatively short spin relaxation time (t s = xR, broken curve in Fig. 3),the change in the response function at P} = 0.5 is modest, confirming that a finite but long xs ~ 10TR relevant for experiments5'21 in spin-lasers at 300 K would lead only to a very small corrections from an infinite TS. For PM, we find an additional bandwidth enhancement with the reduction of is (broken curve), but it comes at a cost of a reduced modulation signal.

3.

Tailoring chirp in spin-lasers

The usefulness of semiconductor lasers is often limited by an undesired frequency modulation, or chirp, a direct consequence of the intensity modulation, and the dependence of the refractive index in the gain medium on the carrier density n. Such a parasitic frequency modulation of the emitted light, 6v(i), is associated with linewidth broadening, enhanced dispersion, and a limited telecommunication bitrate. The chirp can be expressed as20 5v(0=[rg0/(4n)]oo5«(0,

(5)

where Г is the optical confinement factor, g0 the gain coefficient, and oto the linewidth enhancement factor, expressed as the ratio of the derivative of the real part to imaginary part of the complex refractive index with respect to carrier density n(t).

Figure 4. Broadened spectra of the output electric field amplitude IE(co)l of a laser vs. optical and modulation frequencies co0 and coM. Conventional lasers with (solid) and without chirp (dotted) are compared to a spin-laser (dashed line). Arrows indicate chirp reduction with spin injection. Adapted from Ref. 14.

Future Trends in Microelectronics

188

If we take v0 and co0 to be frequency and angular frequency of the output, and vM and coM to be the corresponding harmonic modulation frequencies, the output spectrum is dominated by the emission peak at co0 and the sidebands at (co0± COM). The undesirable alteration to the original spectrum of the electric field emitted from a laser due to chirp can be quantified by the sideband ratio between the heights of the first sidebands with and without chirp:20 sideband ratio = [1 + 4|FM/IM|2]1/2,

(6)

where the ratio of frequency and intensity modulation can be expressed as FM/IM = [6V(COM)/VM]/[65'(COM)/5O]. In conventional lasers, for high-frequency modulation |FM/IM| = cco/2. We can use this result to measure the effects of chirp for a simple comparison between conventional and spin-lasers.14 From small-signal analysis, in Fig. 4 we compare the results for chirp arising in AM for conventional and spin-lasers. As indicated by arrows, the presence of spin injection (dashed line) leads the spectrum approaching an idealized, chirp-free case. From a naive application of 5и(0 = 0 to Eq. (5) we might expect that PM with 5и_(0 = -bn+(i) would completely eliminate the chirp. However, the corresponding generalization of chirp for spin-lasers requires introducing both spindependent refractive index and linewidth broadening, leading to a finite chirp even for 8w(f) = 0. A detailed analysis of the chirp in spin-lasers still allows for a zerochirp case. One of the spin-resolved injections (J+ for P10 > 0) would be the input signal, while the other would be used only to cancel the chirp. This procedure can be viewed as an example of the dual modulation scheme, proposed previously by simultaneously considering modulation of injection and temperature to improve the laser operation.22'23 In spin-lasers we find that a zero-chirp can be implemented together with the bandwidth enhancement.14

4.

Conclusions

Continued advances in VCSELs and their potential for many applications24'25 could be significantly enhanced by considering spin modulation.9'13'14 In addition to the previously demonstrated steady-state threshold reduction, we have shown several desirable features present in their dynamic operation: spin-filtering, enhanced bandwidth, and chirp reduction. Optical methods and circularly polarized light could provide a simple means of implementing spin modulation, which could be beneficial for high-performance optical interconnects.26'27 Additionally, electrical spin injection and the concept of polarization modulation could also stimulate novel spin interconnects,15'16 offering an increase of several orders of magnitude in the effective bandwidth, compared to conventional metallic interconnects. We expect that the continued research into spin-lasers will have two important implications: in the traditional laser community it will promote the understanding of often ignored spin degree of freedom, whereas in the spintronic community focused on the magnetoresistive effects10'19'28 it may stimulate novel roomtemperature device concepts.

Spin Modulation: Teaching Lasers New Tricks

189

Acknowledgments This work was supported by the NSF-ECCS, US ONR, AFOSR-DCT, NSF-NRI NEB 2020, and the SRC. References 1. 2. 3. 4. 5.

6. 7. 8. 9. 10. 11. 12. 13. 14.

J. Rudolph, D. Hagele, H. M. Gibbs, G. Khitrova, and M. Oestreich, "Laser threshold reduction in a spintronic device," Appl. Phys. Lett. 82, 4516 (2003). J. Rudolph, S. Dohrmann, D. Hagele, M. Oestreich, and W. Stolz, "Room temperature threshold reduction in vertical-cavity surface-emitting lasers by injection of spin-polarized carriers," Appl. Phys. Lett. 87, 241117 (2005). M. Holub, J. Shin, and P. Bhattacharya, "Electrical spin injection and threshold reduction in a semiconductor laser," Phys. Rev. Lett. 98, 146603 (2007). D. Basu, D. Saha and P. Bhattacharya, "Optical polarization modulation and gain anisotropy in an electrically injected spin laser," Phys. Rev. Lett. 102, 093904 (2009). H. Fujino, S. Koh, S. Iba, T. Fujimoto, and H. Kawaguchi, "Circularly polarized lasing in a (HO)-oriented quantum well vertical-cavity surfaceemitting laser under optical spin injection," Appl. Phys. Lett. 94, 131108 (2009). S. Hovel, A. Bischoff, N. C. Gerhardt, et al, "Optical spin manipulation of electrically pumped vertical-cavity surface-emitting lasers," Appl. Phys. Lett. 92,041118(2008). I. Žutić, R. Oszwaldowski, C. Gothgen, and J. Lee, "Semiconductor spinlasers," in: E. Y. Tsymbal and I. Žutić, eds., Handbook of Spin Transport and Magnetism, New York: CRC Press, 2011, pp. 731-745. J. Sinova and I. Žutić, "The new moves in the spintronics tango," Nature Mater. 11, 368 (2012). J. Lee, R. Oszwaldowski, C. Gothgen, and I. Žutić, "Mapping between quantum dot and quantum well lasers: From conventional to spin lasers," Phys. Rev. £ 8 5 , 045314(2012). I. Žutić, J. Fabian, and S. Das Sarma, "Spintronics: Fundamentals and applications," Rev. Mod. Phys. 76, 323 (2004). C. Gethgen, R. Oszwaldowski, A. Petrou, and I. Žutić, "Analytical model of spin-polarized semiconductor lasers," Appl. Phys. Lett. 93, 042513 (2008). I. Vurgaftman, M. Holub, B. T. Jonker, and J. R. Mayer, "Estimating threshold reduction for spin-injected semiconductor lasers," Appl. Phys. Lett. 93, 031102 (2008). J. Lee, W. Falls, R. Oszwaldowski, and I. Žutić, "Spin modulation in semiconductor lasers," Appl. Phys. Lett. 97, 041116 (2010). G. Boéris, J. Lee, K. Vyborny, and I. Žutić, "Tailoring chirp in spin-lasers," Appl. Phys. Lett. 100, 121111 (2012).

190

Future Trends in Microelectronics

15. H. Dery, Y. Song, P. Li, and I. Žutić, "Silicon spin communication," Appl. Phys. Lett. 99, 082502 (2011). 16. I. Žutić and H. Dery, "Taming spin currents," Nature Mater. 10, 647 (2011). 17. S. Hallstein, J. D. Berger, M. Hilpert, et ah, "Manifestation of coherent spin precession in stimulated semiconductor emission dynamics," Phys. Rev. B 56, R7076 (1997). 18. N. C. Gerhardt, M. Y. Li, H. Jahme, H. Hopfner, T. Ackemann, and M. R. Hofmann, "Ultrafast spin-induced polarization oscillations with tunable lifetime in vertical-cavity surface-emitting lasers," Appl. Phys. Lett. 99, 151107(2011). 19. E. Y. Tsymbal and I. Žutić, eds., Handbook of Spin Transport and Magnetism, New York: CRC Press, 2011. 20. L. A. Coldren and S. W. Corzine, Diode Lasers and Photonic Integrated Circuits, New York: Wiley, 1995. 21. S. Iba, S. Koh, K. Ikeda, and H. Kawaguchi, "Room temperature circularly polarized lasing in an optically spin injected vertical-cavity surface-emitting laser with (110) GaAs quantum wells," Appl. Phys. Lett. 98, 081113 (2011). 22. V. B. Gorfinkel and S. Luryi, "High frequency modulation and suppression of chirp in semiconductor lasers," Appl. Phys. Lett. 62, 2923 (1993). 23. V. B. Gorfinkel and S. Luryi, "Dual modulation of semiconductor lasers," Proc. SPIE 2146, 204 (1993). 24. S. F. Yu, Analysis and Design of Vertical Cavity Surface Emitting Lasers, New York: Wiley, 2003. 25. D. Bimberg, M. Grundmann, and N. N. Ledentsov, Quantum Dot Heterostructures, New York: Wiley, 1999. 26. B. Ciftcioglu, R. Berman, S. Wang, et al, "3-D integrated heterogeneous intrachip free-space optical interconnect," Optics Express 20,4331 (2012). 27. D. A. B. Miller, "Device requirements for optical interconnects to silicon chips," Proc. IEEE 97, 1166 (2009). 28. J. Fabian, A. Mathos-Abiague, Ch. Ertler, P. Stano, and I. Žutić, "Semiconductor spintronics," Acta Phys. Slovaca 57, 565 (2007).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Part III Harvesting Energy From the Sun and the Environment

III. Harvesting Energy from the Sun and the Environment Energy harvestmg as a topic may seem far from the core interests of microelectronics or the famed semiconductor industry roadmap. It however has been a central concern of the FTM workshops, that began long before the heat wave of solar and green energy, and has undoubtedly benefited from the participation of leading figures like Martin Green, Mark Pinto, and Shawn Qu. While the solar industry may be experiencing growing pains, entrapped in a web of government policies and capacity over-supply, the technology has never stopped advancing. In fact, solar is accelerating to "grid parity", as one will find in an authoritative chapter by Pinto that opens Part III of this volume. Readers may be just as pleased to see that science is evolving on other energy-harvesting fronts, interestingly but not surprisingly including mechanical energy.

Contributors 3.1 M. R. Pinto 3.2 E. Sangiorgi, M. Zanuccoli, R. De Rose, P. Magnone, and C. Fiegna 3.3 G. Ardila, R. Hinchet, L. Montès, and M. Mouis 3.4 A. Sergeev, V. Mitin, N. Vagidov, and K. Sablon 3.5 D. Princepe, L. Barea, G. O. Luiz, G. Wiederhecker, and N. C. Frateschi

193

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Silicon Photovoltaics: Accelerating to Grid Parity M. R. Pinto Applied Materials, Inc., Santa Clara, CA 95052-8039, U.S.A.

1.

Introduction

Lost in recent headlines about solar company failures, reduced government support and depressed stock valuations, is the fact that photovoltaic (PV) systems continue to be installed at an extremely healthy rate - a ten-fold increase between 2007 and 2012, to a cumulative 100 GWp of installations worldwide. The primary factor behind this remarkable growth has been cost reduction at the installed system level afforded by manufacturing and technology improvements to the basic crystalline silicon (c-Si) PV cell. In fact in the past two years, c-Si module cost learning curves have accelerated over their historical norms as a function of both volume and time, and as a result c-Si PV has reached parity with conventional forms of electricity in more and more places in the world. We will show how even a slower than historical rate of learning in future implies that unsubsidized, cost-effective PV electricity could be delivered to > 95% of the world's population by 2020. 2.

The case for PV

The idea of solar generated electricity dates to discovery of the PV effect1 in 1839 through to the first practical silicon solar cell2 in 1954. Attracted by the inexhaustible resource of the sun together with the lack of harmful emissions, PV has been projected to be a key source of future "clean" electricity for more than 50 years.3 However, initial PV applications were limited primarily to off-grid power generation, such as satellites or remote microwave repeaters, as early on-grid systems had a substantial cost disadvantage versus other sources of electricity. Through steady improvements in technology and manufacturing cost together with renewable energy incentive programs in Japan and Germany, the number of on-grid installations began to become substantial beginning in the mid-1990's. In addition to demonstrating long term reliability, the experiences from these installations have substantiated specific advantages of PV deployment, including the ability to distribute power throughout a grid, the value of PV time-of-day generation (overlapping a substantial part of the peak daily need), the speed of installation versus a conventional utility power plant, and the ability to scale to different applications. Since 2007, annual PV installations have been growing at a compound annual growth rate (CAGR) of > 50% and are expected to exceed 30 GWp in 2012 for a cumulative installed capacity just over 100 GWp, see Fig. 1. 194

Silicon Photovoltaics: Accelerating to Grid Parity

195

Year

2007

2008

2009

2010

2011

2012

Cumulative install. (GW)

10.6

16.6

25.0

44.2

70.1

105.2

% c-Si modules

86%

83%

79%

89%

87%

89%

Figure 1. Annual PV installations, dominated by c-Si, have increased ten-fold since 2007, reaching a cumulative total of > 100 GW (2012 data is forecast). Data source: Photon Consulting.4

Given that comparative electricity cost has been the central issue in PV adoption, it is important to review the elements of PV cost. The upfront capital cost of a P V system is the sum of the cost of the modules (the price charged to the project developer) and cost of installation, known as the balance of systems (BOS) cost: GSYS ■N,MOD x

CB

CM

NMODXCW.

-NrMOD X Cnv + Cn

(1)

Here the BOS is divided into fixed (e.g. permits, monitoring, central inverters) and variable (e.g. wiring, mechanical support, labor) components, depending on the number of modules used NMOD = ^SYS/^MOD, where PS\s is the peak power plant output and /"MOD is the peak power per module. As a measure of comparison, it is typical to express project costs on a per peak watt basis, e.g. C

SYS ~ Q Y S ^ S Y S ~~ CMOQ/PMOD

+

CBV/^MOD

+

CBF/PSYS >

(2)

where the lower case c is used henceforth to denote costs normalized by power. The cost per (peak) watt of the module c M0D is a universally tracked measure that can be usefully to rewritten as the ratio of areal costs and power: CMOD ~ СМОГ/PMOD

—

0

+

g)x

C^MODO / [ ^ S U N

X

TIMOD] >

(3)

where CAMOD0 is the cost per area to manufacture the module; g is the gross margin (profit) in the module price; PASw is the solar incident power density, typically measured under standard test conditions (1000 W/m2 at 25 °C and AM 1.5 air mass); and T|MOD is the conversion efficiency of the module. Such a production cost per unit-output measure is found in other industries and typically follows a learning curve over time5 as discussed below.

196

Future Trends in Microelectronics

Table 1. Effect of efficiency on system cost based on a representative 15% 2012 c-Si module. The variable fraction of the base BOS is 60% with a 5% module gross margin. Up to cost per area premiums of 34% (0.34 0/cm2), a 20% module has lower cost/Wp to manufacture and will deliver cheaper systems independent of BOS. A premium of 0.5 0/cm2 (+15% on a cost/Wp basis) can be tolerated even when the starting BOS is the same as the base module cost, but the added efficiency cannot overcome a +30% cost/Wp premium even for BOS0 up to 2X the base module cost.

A key question that arises in comparing PV technologies is the value of conversion efficiency on total cost. From above it is noted that both CMOu and PMOD are functions of TIMOD- Increasing T|MOD always decreases the variable BOS cost in eq. (2) but may or may not decrease CMOD depending on cost to manufacture. As a consequence increasing TIMOD is typically beneficial when BOS is high and/or the manufacturing cost penalty to achieve higher efficiency is minimal. However, lower T|MOD modules can be favored for applications or regions with low BOS. Table 1 compares 15% and 20% modules with different costs as an illustration. It is especially critical to note the extremely low areal manufacturmg cost of current c-Si (~$0.01 cm"2 implying a fully processed cell cost of $1.42 per 156x156 mm2 wafer) when considering non-silicon alternatives, as shown at the end of Section 4. The ultimate comparison of PV versus other sources is made via a levelized cost of electricity (LCOE), which expresses the implied cost of electricity per kWh from a PV system over its lifetime, including cost of capital, operating costs, system performance degradation and local sunlight. A simplified LCOE can be written as: LCOE = [cSYS + cM&0 • Й=?(1 + r)-fc] x [PAsm/(PR • /L0C)] / S ^ K l - d)/(l + r)]k ,

(4)

where cM&0 is the annual cost per Wp of maintenance and operation; N is the system life in years; r is the financial discount rate; /LOc is the annual insolation (in Wh/m2), which depends on location and panel orientation; PR is the system performance ratio accounting for power losses in the system and d is the power degradation in the module per year. A more sophisticated LCOE model developed by NREL6 includes detailed systems parameters as well as financing costs, taxes and incentives. Figure 2 shows the dependence of LCOE from this model for

Silicon Photovoltaics: Accelerating to Grid Parity

197

different U.S. locations. Note that for a system cost < $3.75/Wp - the so-called retail "grid parity" point - the PV system delivers cheaper electricity than retail utilities for both cities if the U.S. investment tax credit (ITC) is applied. But even without the ITC, a PV system in San Diego reaches retail grid parity at $5.25/Wp due to the high insolation. While system cost is a primary driver, lower interest rates also help PV economics - the San Diego LCOE would be 6-12% lower if the interest and discount rate were reduced by 1 point from the values used in Fig. 2. In Fig. 2, an average residential retail electricity rate was used as a simple basis of comparison. However, making a more accurate assessment, as for instance would be required to determine parity at the utility generation level, is quite complex. First, the value of PV electricity to a utility is higher per kWh due to the correspondence with time of day and the ability to distribute as noted above. Other conventional energy sources need fuels that can vary widely in price - comparison with a 30 year PV system would need a fuel price forecast over that same period. (However, we can say confidently that PV generation became cheaper than diesel sources in most climates several years ago.) Finally, there is also the possibility of future carbon taxes on fossil fuel alternatives which is relevant to the model if implemented sometime in the lifespan of the PV system; for instance a modest tax of $25/ton is estimated to raise average OECD electricity rates by 1.5 0/kWh.8 3. Basic c-Si PV cell and cost per Watt trends Despite significant investments in alternative technologies, PV installations continue to be dominated by c-Si cells as shown in Fig. 1. Of the ~90% of the PV installations forecast to be based on c-Si cells in 2012 (up from 79% in 2009),

Figure 2. Modeled PV LCOE6 vs. total installed cost for San Diego and Chicago, with and without the federal investment tax credit (ITC). For comparison, average residential utility rates for each city7 are also shown (dashed horizontal lines).

198

Future Trends in Microelectronics

Figure 3. The basic "Gen 1" c-Si cell, featuring a blanket diffused л-type emitter, a silicon nitride layer for light coupling and passivation, metal finger contacts to the nlayer on the front through the nitride and an unpatterned metal back contact. the vast majority will be based on the conventional blanket n-emitter cell design, illustrated in Fig. 3, which continues to be the industry workhorse for the past 30 years. In fact, it can be argued that since its inception, aside from materials and process optimization, the primary structural change to this cell - which we will refer to here as "Genl" - has been the incorporation of the top-side silicon nitride antireflection and passivation film.9 For a detailed history of the evolution of c-Si cell and module technology up to 2005, refer to the review article by Green.10 The manufacturing supply chain for c-Si modules can be divided into 5 main steps - polysilicon feedstock, ingot formation, wafer slicing, cell formation and module assembly, see Fig. 4. Because of the significant contribution of Si to product cost, unlike ICs, the PV industry uses much thinner wafers (today's mainstream thickness is typically 180-200 p.m). It has also developed cheaper alternatives to highly pure Czochralski (Cz) pulled mono-c-Si, most successfully by turning to multi-c-Si from ingot casting. The low materials cost of the latter, together with continued cell efficiency improvements and lower relative cell-tomodule (CTM) losses,11,12 have thus far delayed the long-expected transition to mono-c-Si for the highest volume applications. The costs of each of the steps in Fig. 4 determine the overall module cost per Watt in Eq. (3). Manufacturing efficiencies and technology improvements have lowered this cost over time as shown in the learning curve in Fig. 5(a), plotted as a sales price (or cost to a system installer) in 2010 dollars. The starting point of $90/Wp in 1975 is more than lOOx the price at the end of 2012, clearly illustrating why PV was not close to being grid-competitive back then. The beginning of large-scale PV manufacturing is best referenced to the first 1 MW factory in 1980,13 which produced 9.7% modules at $28/Wp in 2010 dollars. Through 2003 the actual costs tracked a linear 20% cost reduction for every doubling of volume - less than the -30% for ICs (which benefit from device scaling embodied in Moore's Law), but still impressive. Nemet14 has analyzed the factors behind cost reduction from 1979-2001 and found that 30% came from efficiency while 70% came from materials and processing productivity in the numerator of Eq. (3), even though the efficiency starting point was relatively low.

Silicon Photovoltaics: Accelerating to Grid Parity

199

Figure 4. Value chain for multi-crystalline and mono-crystalline (Cz) modules. The gaps on the mono module come from the non-square wafers cut from Cz-ingots.

Figure 5. (a) Module cost per Wp in constant 2010 dollars plotted with a 20% per doubling learning curve; (b) cost breakdown of a $1/Wp module from early 2012. Beginning around 2003, the increasing volume of PV installations drove a supply-demand imbalance in polysilicon feedstock, which caused a deviation from the historical learning curve, evident in Fig. 5. In fact by 2007, PV began to consume more polysilicon than electronics,15 and the relatively long 2-3 year lead time for polysilicon plant construction drove prices up ~15x to over $450/kg in early 2008. However as new plants came on line, the module cost returned to the historical trend line by 2010, at which time new factories had expanded in scale to hundreds of MWp each. By the end of 2011, the effect of massive investments throughout the PV value chain led to further cost efficiencies, but also to intense price competition, with spot prices racing past $1.00/Wp to $0.70/Wp in late 2012. It is important to emphasize that the cost improvement associated with the industry scale-up is based on more than just improved factory productivity. As the

200

Future Trends in Microelectronics

industry gets larger, more R&D is invested and the synergy of so many firms throughout the value chain pushing in similar directions leads to accelerated progress. As shown in Fig. 5(b), even after the return of rational polysilicon prices, module costs are still dominated (> 60%) by materials - besides poly, other significant contributors are metal pastes (primarily Ag) and packaging encapsulants. Not only does scale bring more investments to materials optimization and manufacturing processes, but the overall buying power of the industry helps stimulate more competition to drive lower pricing. Taken together, these factors are additive to drive down total cost. From Fig. 5(b), not only do raw materials dominate PV costs, but equipment depreciation is not major contributor, again unlike the IC industry. On the other hand, like ICs, PV has minimal dependence on labor costs - given their higher contribution, utility costs could actually be more important in siting new factories. While the industry is unlikely to maintain the recent accelerated learning trajectory, cost-effective methods to increase T|MOD together with materials reductions or replacements should allow continued progress on CMOD> likely to values < $0.50/Wp before reaching the 1,000 GWp of cumulative installations predicted by the historical learning curve. The rapid reduction in c-Si module costs and corresponding improvements in BOS have led directly to measurably more economical PV systems. Figure 6(a) shows actual costs for German rooftop systems with recent projects reaching ~ €l.75/Wp ($2.25/Wp).16 The resulting increase in PV installations has driven up Germany's percentage of renewable electricity from PV, as shown in Fig. 6(b). Note that the total amount of electricity produced in Germany from PV is still less than 5% on an annualized basis (see below), but the results from May 2012 demonstrate that PV can be effective at large relative percentages on the grid. It should also be noted that rooftop systems are generally more expensive to install per Wp than large-scale ground mounted systems, German labor costs are higher than those in developing economies, and German insolation is relatively low, all of which bodes well for prospects in new markets and applications globally.

Figure 6. (a) Trend of average PV system prices in Germany for installed roofmounted systems of up to 100 KWp.16 (b) PV production vs. time of day in Germany on Friday May 25, 2012, peaking at > 22GW or 33% of total demand.17

Silicon Photovoltaics: Accelerating to Grid Parity 4.

201

The evolution of c-Si technology

Without major changes, modules based on the Genl c-Si cell architecture have not only been able to reach substantially lower production costs but also have steadily improved in efficiency. Figure 7 shows the progress in c-Si production technologies from 2003 through 2011 by plotting the distribution of module efficiencies from a database of commercially available products.18 Notably, the improvement in the mode of the distribution had its largest year on year increase in 2011 (+1.1 points) to TIMOD = 14.5%, equivalent to TICELL ~ 17%. Based on recent progress, it can be expected that the most common modules will achieve r|M0D > 15% and T|CELL > 17.5% in 2012. It is interesting to contrast this rate of progress with reported research records.19 For multi-c-Si, the champion research T|CELL has improved < 1 point in 15 years. There are significant challenges in approaching theoretical TICELL values reproducibly even for robust material systems. Numerous ventures have failed on the premise that hero results could be directly transferred to manufacturing, and some approaches simply may never be viable in production. The increase in c-Si efficiencies, emphasized especially by the 2011 acceleration, is a testament to the principles behind the learning curve. While most of the innovation underlying the advances of common modules is applicable to a wide variety of cell and wafer types, perhaps the most striking example supporting the learning thesis is multi-wafer quality. Many observers believed the huge casting capacity build in China would quickly be made obsolete as the industry mainstream moved to Cz-mono wafers - instead the magnitude of the investments accelerated learning on the basic casting process and even re-exploration of mono seeding,20 resulting in significant improvements in multi-wafer quality and cost.

Figure 7. Efficiency distributions of commercial c-Si modules from a published database.18 The efficiency of the most common multi-c-Si module improved +2.6 points over 8 years, but +1.1 points from 2010 to 2011 alone. Note corresponding cell efficiencies are typically 2+ points higher due to cell to module losses.

202

Future Trends in Microelectronics

Advances responsible for the data in Fig. 7 have also come through optimization of established cell processes, such as surface texturing to increase optical absorption21 or advances in screen-printed metal interconnects to improve collection area.22 As an example of the latter, Fig. 8 shows a comparison of fine line metal fingers made with a single screen-printed step versus two aligned steps. The increased aspect ratio of the double-patterned structure maintains conductance while blocking less of the wafer. Additionally, splitting the printing creates an opportunity to reduce overall paste usage through the improved geometry of the fingers and also allows for layout optimization on wider bus bars. Better results can be achieved using different pastes for the two prints, analogous to contact and conductor metals in ICs. As suggested by the cost table in Fig. 5(b), the savings in paste (-20%) and the value of TICELL (-0.2 points) far outweigh the cost of an extra printer, making double printing an effective incremental improvement for c-Si cells. Several more slightly more complex improvements have been proposed for the Genl cell. These include selective heavily doped emitters,23 back passivation with localized metal contacts,24 and the replacement of diffused dopants with ion implantation to achieve better emitter profiles.25 In each of these cases, substantive TICELL improvements have been shown - as much as 1.0 point, to over 20% with mono wafers (and additive when combining front and back enhancements) - but implementation has been more selective to date due to cost and integration details. Another key consideration in the adoption of incremental technology elements is their effect on yield. The PV functional yield is relatively high, but cell performance distributions can be challenging to manage. A simple illustration of why this is critical can be understood by considering the interconnection of cells in a module - to get high voltage and power, cells are connected in series, so current collection in the panel is limited by the worst cell. As a result, cells are aggressively binned before they are packaged, and there is a substantial advantage in processes that yield tight distributions around the maximum achievable performance.

Figure 8. Interconnect cross sections with (a) single print (b) double print. Double print has been demonstrated to increase efficiency by opening more of the wafer to photon collection, reducing expensive paste consumption, and improving yield.

Silicon Photovoltaics: Accelerating to Grid Parity

203

Figure 9. Yield and binning improvements through advanced process technologies: (a) double metal printing, (b) ion implantation.

Omitting other factors, purely adding process steps places an additional burden on control - typically, the more steps added, the wider the distribution. However some steps by their nature can actually improve distributions. For instance, double-printed interconnects suppress the low-performance tail due to the second print bridging random opens, as shown in Fig. 9(a). Another yield-friendly technology is ion implantation, which produces tighter dopant profiles for n emitters than standard POCl3 diffusion, see Fig. 9(b). In both of these cases, the value to the manufacturer is more Watts out of their factory, less material scrapped, more efficient binning, and better installed system performance. Figure 10 shows a trio of second generation (Gen2) c-Si structures - metal wrap through (MWT),26 heterojunction (HJT),27 and interdigitated back contact (IBC)28 cells - that deviate more noticeably from the simple Genl device, but also show substantively higher efficiencies. Of the three, MWT can be implemented with the smallest change to a Genl process - through-wafer vias are added to make back to front contacts - and also the cell has been shown to work well on either multi- or mono-c-Si material. Conversely, the Sunpower-pioneered IBC requires a more complicated process, but it has demonstrated a record ПСЕИ. = 24% in volume production. Likewise, HJT cells have until recently been driven primarily by one module manufacturer, Sanyo, and in addition to demonstrating higher TICELL than Genl cells, HJT cells typically show better thermal performance in the field. It should also be noted that amorphous silicon layers can be added to MWT or IBC cells in order to obtain similar benefits. Further, MWT and IBC cells have additional advantages when interconnected in modules exclusively from the back. Back contacts require less front side metal in fact, IBC has no metal on the front side at all - improving collection area and also aesthetics by projecting a uniform dark panel. Back-contacted cells also allow the use of a flex circuit backsheet29 to remove high current interconnects from the wafer, in much the same way as an IC circuit board. With no thick metal on the wafers, the backsheet also reduces stress to improve module yield, especially for large, thin wafers. The better interconnect on the backsheet also can decrease CTM loss by ~ 2x, allowing T|MOD to approach closer to 1.5 points of п СЕи ,.

204

Future Trends in Microelectronics

Figure 10. Gen2 c-Si PV cell structures: (a) metal wrap through; (b) silicon heterojunction; (c) interdigitated back contact.

Gen2 cells have already had some market success, and there are many efforts underway throughout the industry to develop lower-cost implementations that would create an inflection to move the bulk of the market from Genl. For instance, since some Gen2 structures require highly uniform mono-c-Si wafers, there have been implementations on even thinner wafers than the industry mainstream. Some cells can benefit in performance from thinner wafers, depending on minority carrier lifetime and structural elements such as back mirroring layers. There have been projections" that wafer thicknesses will trend down to ~120 )j.m (with associated kerf reductions) in parallel with the cell roadmap as a result of advances in wire saw technologies and manufacturing automation. The ultimate solution to reducing silicon costs is likely to be "kerfless wafers" - e.g. wafers grown by epitaxy on a re-usable substrate. Significant progress has been made recently on these "Gen3" c-Si concepts. Moslehi et. a/.30 reported T|CELL > 20% on a 43 ц т epi absorber. In addition to using less silicon ~7x less than a current standard 180 ц т multi-c-Si wafer - these Gen3 cells could also offer advantages in improved yield {e.g. via higher reproducibility of specific wafer specs) and in-situ doping or even heteroepitaxy. Regarding the latter possibility, although the theoretical limit of c-Si cells is 29%,31 cost-effective solutions above 25% have not been demonstrated. A natural question is whether heteroepitaxial layers on a c-Si cell are viable for mainstream applications. Using the $2.10/Wp example in Table 1, a 30% module (likely requiring T|CELL > 33% given CTM losses) would need a process cost < $0.025/cm2

Silicon Photovoltaics: Accelerating to Grid Parity

205

to be advantageous. Assuming III-V MOCVD layers, LED cost models32 predict the epi step alone incurs ~$0.30/cm2 per ц т of deposition using a state-of-the-art commercial reactor. Thus, adding an MOCVD step seems viable only with very thin epilayers and/or a much higher productivity tool. Alternatively, as alluded to previously, a heterolayer might be included directly in the Gen 3 substrate growth. 5.

Market implications of c-Si roadmap opportunities

Unlike CMOS, there is no consensus step-by-step roadmap for the PV industry, but there are certainly enough paths forward to inspire confidence that a cost reduction learning curve will be maintained in the foreseeable future. Looking at each of the components of cost qualitatively, there is still room to reduce the materials cost in all steps in the value chain. Efficiency can also be a driver of lowering cost if implemented effectively - recall from Table 1 that even with some manufacturing cost premium per wafer, it is still possible to lower overall module cost per Wp, as well as leverage the higher efficiency to lower variable BOS costs. Finally, there is still much that can be done to reduce fixed BOS costs as the industry learns best practices - e.g. in the U.S. where "soft costs" are still much higher than Germany.33 To estimate potential future PV costs, we return to the learning curve to project a reduction in cost of a specific component from year Y0 to Yx as L0Í. q, CAGR) = [l + / 0 • tk=JfY°(X + CAGR)kf82 ( 1 _ 4 ) ,

(5)

where q is the rate of learning per doubling of volume, CAGR is the growth rate of annual installations andf0 is the percentage of volume at the end of year Y0 that was added in year Y0. Applying a separate learning rate to the module and BOS costs in Eq. (2) and accounting for variable BOS reduction with increased conversion efficiency, one obtains the following for the installed cost in the year Yy: CSYSCI) = L(n.4MOD.CAGR) ■ CMODWI) +

L(YV qB0S, CAGR) ■

[(T^AU

' cm(Yo) + Свг(Уа)].

(6)

where r)o and r\x are the module efficiencies in years Y0 and Y\ respectively. The fact that Eq. (6) connects system cost to market growth via learning is also consistent with the inverse - that the end market grows if costs come down, a relationship demonstrated by recent experience. In fact, most industry analysts have under-forecast growth by 30-50% over the past 3 years - even predicting negative growth both in 2011 and 2012 - by focusing on changes in incentives such as the European feed-in-tariffs (FITs), rather than the potential for cost reduction that has proven sufficient to compensate for lower FITs. Most analysts estimate long term PV annual installation growth at 15-20% per year,4 driven by markets outside of Europe. Figure 11 illustrates the huge market potential, with some of the largest countries still stuck at low PV fractions, not to mention the growing electricity consumption in countries like China and India. For conservative cSys modeling, if

206

Future Trends in Microelectronics

Figure 11. (a) Fraction of electricity supplied by PV by country in 2012.34 (b) Installed PV required for varying levels of global electricity demand: over 1000 GWp of new PV would be needed for the world average to reach Italy's 2012 percentage.

we take CAGR = 15% from the lower end of growth estimates - 4x slower than the 2007-2012 CAGR in Fig. 1 - the cumulative PV in 2017 reaches -350 GWp, requiring 250 GWp of new installations over the next 5 years. To put this number into a very realistic context, it would take 275 GWp for the US and China alone to reach half the current penetration in Italy. In addition to the installation growth, forecasting CSYS requires estimates of learning rates. Because of its large and well-documented experience base, Germany is an ideal reference for reliable estimates. Using the published $2.25/Wp CSYS for 2012,16 a value of ~$1.60/Wp is projected in for 2017 German rooftop systems, based on: (i) module prices returning to their slower historical learning rate of quoo ~ 20% per doubling; (ii) BOS costs trending at ^Bos ~ 10% per doubling, corresponding to the average implied in Fig. 6(a); and (iii) average module efficiencies climbing a modest 0.75 points per year to 19.25%. The $1.60/Wp systems cost assumes CMOD - $0.50/Wp, likely requiring a 30-50% reduction in materials costs depending on the scaling of the non-materials components in Fig. 5(b). Using a projected cSYs, LCOEs can be estimated from Eq. (4) to determine how PV electricity prices might evolve in comparison to existing utility rates, as shown in Fig. 12 for the same six countries as in Fig. 1. For Germany, we used the published 2012 cSYs, while for the other countries a 1.5x multiple of the German 2012 CSYS was assumed to account for the efficiencies in German installations and as a simple basis of comparison. In forecasting the 2017 results, we assume that developed countries converge to German best practices while lower-cost regions like China and India gain a 20% advantage due to lower (-30%) BOS costs. We find that both Germany and Italy have reached retail grid parity before 2012, but Italy's better insolation does not make up for the higher CSYS and real discount rate (6% vs. 3%). Japan has a higher LCOE than the U.S., but it

Silicon Photovoltaics: Accelerating to Grid Parity

207

Figure 12. LCOE vs. local 2012 retail electricity rates. LCOEs are obtained from Eq. (4) without incentives using average insolations, N = 30 years, PR = 90%, d = 0.5%/yr, 1.5% O&M and country-dependent discount rates (3%, 6%, 9%, 12%). System costs are modeled from Germany as described in the text.

reaches parity first due to higher retail rates. While some parts of the U.S. could generate PV electricity below retail in 2012 without incentives (e.g. San Diego in Fig. 2), most of the U.S. reaches parity if the ITC were included - the credit essentially eliminates the excess cost in the U.S. versus Germany. India and China have the highest 2012 LCOEs due to higher real discount rates (6% and 9%), but they see the fastest declines going forward due to lower local BOS costs. The LCOEs suggest that all 6 countries will reach retail grid parity by 2017 - without any PV incentives or assumptions about the real utility rates rising due to fossil fuel price increases or carbon taxes. As incentives do wind down around the world, LCOE becomes the universal driver of growth - in fact, incentives like the FIT will have served their intended purpose of helping the market grow and become self-sustaining. Going ahead, the onus will be on the growing base of installers to market the LCOE benefits to grow their businesses. The development of new financing models, such as leasing in the U.S. - which works as long as the LCOE is below the utility rate so that the leasing firm can profitably offer an incentive to consumers - is evidence of this trend. Finally extending the same approach, we find 48 countries at retail parity by the end of 2012, up from 23 in 2010 (although 21 of these were islands using diesel generation). By 2017, the learning curve predicts parity will reach 135 countries, representing three quarters of world population. However, this still underestimates the extent to which PV would be truly cost-effective as published local retail rates in developing countries can be substantially below real costs - for instance Indonesia, with 3.5% of global population, has an electricity cost of-12 ji/kWh but a subsidized retail rate of 6 eVkWh.35 Assuming instead the best rate in an OECD country (Canada, 9.9 jc/kWh) as a proxy for true lowest utility cost, then 213

208

Future Trends in Microelectronics

countries would be at unsubsidized parity, makmg the "limitless resource" foreseen in 19563 available cost-effectively to 97% of the people on the planet. Acknowledgments The helpful inputs from Sandeep Bandil, Kevin Chen, Charlie Gay, Bharat Ramakrishnan, Ashish Shrotriya and Sue Stein are gratefully acknowledged. References 1. E. Becquerel, "On electric effects under the influence of solar radiation," Compt. Rend. 9, 561 (1839). 2. D. M. Chapin, C. S. Fuller, and G. L. Pearson, "A new silicon p-n junction photocell for converting solar radiation into electrical power," J. Appl. Phys. 25, 676 (1954). 3. F. Daniels, "A limitless resource: Solar energy," The New York Times, March 18, 1956. 4. Photon Consulting, Oct. 2012. 5. M. R. Pinto, "Nanomanufacturing technology: Exa-units at nano-dollars," chapter in: S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: Up theNano Creek, New York: Wiley, 2007, p. 154. 6. NREL System Advisor Model (SAM), see http://sam.nrel.gov/, May, 2012. 7. U. S. Energy Information Administration, Electric Power Annual, released September, 2012. 8. "Promising domestic fiscal instruments for climate finance," International Monetary Fund Report for G20 Finance Ministers, November, 2011. 9. K. Kimura, "Recent developments in poly crystalline silicon solar cell," Tech. Dig. 1st Intern. Photovoltaic Sci. Eng. Conf. (1984), p. 37. 10. M. A. Green, "Silicon photovoltaic modules: A brief history of the first 50 years," Progress Photovoltaics: Res. Appl. 13, 447 (2005). 11. I. Haedrich, H. Wirth, M. Storz, and G. Klingebiel, "PV module efficiency analysis and optimization," Fraunhofer ISE Webinar, September, 2012. 12. International Roadmap for Photovoltaics, http://www.itrpv.net, 3rd Ed., 2012. 13. C. F. Gay, "The ARCO Solar one MW photovoltaic power plant," Proc. 8th Biennial Intern. Cong. Solar Energy Soc. (1984). 14. G. F. Nemet, "Beyond the learning curve: Factors influencing cost reductions in photovoltaics," Energy Policy 34, 3218 (2006). 15. J. E. Bartlett, R. M. Margolis, and C. E. Jennings, "The effects of the financial crisis on photovoltaics: An analysis of changes in market forecasts from 2008 to 2009," NREL Report no. TP-6A2-46713 (2009). 16. BSW-Solar Price Index, http://www.solarwirtschaft.de/preisindex, November, 2012.

Silicon Photovoltaics: Accelerating to Grid Parity

209

17. "Germany sets new solar power record, institute says," Reuters, May 26, 2012. Data from EEX transparency platform, see http://www.transparency.eex.com 18. Photon International, Annual Solar Module Database (2003-2011). 19. See http://www.nrel.gov/ncpv/images/efficiency_chart.jpg (2012). 20. X. Gu, X. Yu, K. Guo, L. Chen, D. Wang, and D. Yang, "Seed-assisted cast quasi-single crystalline silicon for photovoltaic application: Towards high efficiency and low cost silicon solar cells," Solar Energy Mater. Solar Cells 101, 95 (2012). 21. D. H. Macdonald, A. Cuevas, M. J. Kerr, et al., "Texturing industrial multicrystalline silicon solar cells," Solar Energy 76, 277 (2001). 22. M. Galiazzo, V. Furin, D. Tonini, G. Cellere, and A. Baccini, "Double printing of front contact Ag in c-Si solar cells," Proc. 25th Eur. Photovoltaic Solar Energy Conf. (2010), p. 2338. 23. S. K. Chunduri, "Be selective," Photon International 11, 108 (2009). 24. P. Saint-Cast, J. Benick, D. Kania, et al, "High-efficiency c-Si solar cells passivated with ALD and PECVD aluminum oxide," IEEE Electron Dev. Lett. 31, 695 (2010). 25. W. Han, W. Shan, Q. Jiang, et al., "Mass production implementation of Solion ion implantation technology," Proc. 27th Eur. Photovoltaic Solar Energy Conf. (2012), p. 1498. 26. A. W. Weeber, R. Kinderman, P. D. de Jong, and C. J. J. Tool, "17% cell efficiencies on large back-contacted multi-crystalline silicon solar cells," Proc. 21st Eur. Photovoltaic Solar Energy Conf. (2006), p. 605. 27. M. Taguchi, Y. Tsunomura, H. Inoue, et al, "High-efficiency HIT solar cell on thin ( P 20 V, 6цА, 0.2 W/cm3 58 V, 134 uA, 0.78 W/cm3 0.7 V, 4 uA/cm2, 2.8 mW/cm3 3.2 V, 72 nA, 0.6 mW/cm3

Input: %strain @ strain rate/s 0.12% @ 3.56% s'1 palm impact tapping @ 1-50 Hz 0.23% @ 12.8% s"1 (0.33 Hz)

Table 3. Mechanical harvesters based on vertically integrated nanostructures. Material ZnO

PZT

PVDF

Size: surface 5, length L, width W Conical NWs dispersed in PMMA over a Kapton cantilever, L = 30 um, 5 = 1.5x2 cm38 Z, = 50um, FF=200nm, S = 1 cm2, NWs deposited on t= 125 um Kapton31 S = l c m 2 , L = 1 0 0 u m , W=5 um, 500 nm thick NWs (5 um separation), on Kapton9 ^ = 3 7 0 nm, NWs integrated on PET, S = 15 mm x 0.8 mm x 5 um16 W = 60 nm, L = 500 um NWs integrated on Si, covered by PDMS24 Single W = 0.5-6.5 um, L = 100-600 um NWs on t = 0.75 mm plastic10

Performance ^oc> he, P 3.3 V, 50 nA, 165 nW

Input: %strain @ strain rate/s 0.11% at 3.67% s_1 (deformations at 0.3-2.63Hz)

2 V, 107 nA, llmW/cm 3 0.25 V, 40 nA, 10 nW 6 V, 40 nA, 0.12 uW (200 uW/cm3) 1.63 V, 0.03 W

0.1% at 5% s"1 (deformation at 0.3 Hz) 0.05% (tapping at 3.2 Hz)

30 mV, 4nA, 0.12 nW

0.085% (deformation at 2 4 Hz)

stretching at 0.5 Hz 7.5x10"5% (tapping at 40 Hz)

Table 4. Mechanical harvesters based on laterally integrated nanostructures.

Mechanical Energy Harvesting with Piezoelectric Nanostructures

239

From these tables, we find that few devices have reached a power density comparable to MEMS devices, the maximum being at -0.78 W/cm3.37 Many conclusions can be inferred from these tables and from the preceding calculations: (i) using the materials with best piezoelectric coefficients is important to increase the energy harvested but integration issues must be considered to increase their performance (i.e. maximizing the number of NWs in parallel); (ii) vertical integration is better suited to applications with higher the mechanical inputs, such as impact;30'37 (iii) lateral integration is better suited to applications with low amplitude mechanical inputs, only if enough stress is transferred to the piezo nanostructures. Integration into plastic substrates seems a better option in this case. The required mechanical input can be reduced if the substrate is: thinner, more flexible and if the mass of the system is increased. Two other general conclusions are: (iv) in general, longer and thinner NWs will produce more energy at a given strain, except for laterally integrated NWs where an optimal diameter exists; and (v) no optimization of supporting structures (i.e. resonant cantilevers) is needed as long as enough strain is transferred to the piezo nanomaterials.

4.

Further improvements at the nanoscale

The piezoelectric properties of nanostructures can be further improved, with resulting increase of energy harvesting efficiency. Indeed, recent qualitative measurements on 25 nm wide, 500 nm long GaN NWs featuring an 8 nm A1N barrier along their axis resulted in an estimated value of the effective piezoelectric coefficient which was ~9 times larger than for their intrinsic GaN counterparts.27 This would increase the efficiency of energy conversion by a factor -80, leading to a ten-fold improvement compared to ZnO.32 Although this theoretical prediction might be difficult to reach due to contact quality or process-induced size dispersion,39 the use of heterostructured NWs is undoubtedly opening very interesting prospects.

5.

Towards completely autonomous systems: Multisource approach

An ideal totally autonomous system would rely on more than one kind of energy, from any available source. This idea is known as the multisource approach and has been studied, but usually at larger length scales.40 Only a few examples of multisource harvesting on the nanoscale have been reported, harvesting either (i) solar and mechanical energy or (ii) biomechanical and biochemical energy. The first prototype combines the piezoelectric properties of vertically grown ZnO NWs to harvest the ultrasonic ambient mechanical energy and their good optical properties to create a solar cell.41 The NWs were assembled in a compact design acting as a serial connection. Combining both energy-harvesting mechanisms increased the overall power by 6% compared to the solar cell only value of 32.5 nW/cm2.

Future Trends in Microelectronics

240

The second prototype combined mechanical energy harvesting using laterally integrated PVDF NWs with a fuel cell, using multiwalled CNTs with immobilized glucose oxidase, laccase, and using a biofluid-containing glucose (such as blood) as fuel.42 The combined effect of both sources doubled the potential generated from 50 to 95 mV. These prototypes are not optimal and do not integrate the best prototypes of mechanical energy harvesters, but show the feasibility of combining two energy sources into a single device. 6.

Conclusions and future prospects

We discussed mechanical energy harvesting using piezoelectric nanostructures (NWs) from a theoretical point of view and presented optimization guidelines relying on simple mechanical and piezoelectric laws. Highlights of the moststudied materials and best-performing devices were presented. Their performances can be now compared to MEMS energy harvesters, with which they could be integrated on the same substrates. Multisource approaches (solar, mechanical, RF, etc.) could contribute to build real autonomous systems working in any ambient condition. GaN seems a better material to improve the piezoelectric coefficients at the nanoscale as they can be engineered (doped, heterostructured), although InN and PMN-PT also appear promising because of higher piezoelectric coefficients. The main challenge is to integrate the maximum of piezoelectric elements, collectively contributing to the power output. Material defects and NW misalignment will lead to only a fraction contributing to the total power output. A thorough understanding of the underlying electromechanical physical phenomena is still lacking in the literature {i.e. effects of doping, heterostructures, etc.), as are characterization methods to quantitatively measure individual nanowires properties. Acknowledgments This work has been supported in part by the European Union FP7 Program, within the Network of Excellence NanoFunction under grant FP7/ICT/NoE no. 257375.

Mechanical Energy Harvesting with Piezoelectric Nanostructures

241

References 1. MEMS chapter added in ITRS 2011 edition, see http://www.itrs.net 2. K. A. Cook-Chennault, N. Thambi, and A. M. Sastry, "Powering MEMS portable devices—a review of non-regenerative and regenerative power supply systems with special emphasis on piezoelectric energy harvesting systems," Smart Mater. Struct. 17, 043001 (2008). 3. A. Nechibvute, A. Chawanda, and P. Luhanga, "Piezoelectric energy harvesting devices: An alternative energy source for wireless sensors," Smart Mater. Res. 2012, 853481 (2012). 4. M. Minary-Jolandan, R. A. Bernal, I. Kuljanishvili, V. Parpoil, and H. D. Espinosa, "Individual GaN nanowires exhibit strong piezoelectricity in 3D," NanoLett. 12,970(2012). 5. D. Zhu, M. J. Tudor, and S. P. Beeby, "Strategies for increasing the operating frequency range of vibration energy harvesters: A review," Measure. Sci. Technol. 21, 022001 (2010). 6. M. Marzencki, Y. Ammar, and S. Basrour, "Integrated power harvesting system including a MEMS generator and a power management circuit," Sensors Actuators A 145-146, 363 (2008). 7. M. H. Zhao, Z. L. Wang, and S. X. Mao, "Piezoelectric characterization on individual zinc oxide nanobelt under piezoresponse force microscope," Nano Lett. 4, 587 (2004). 8. R. Agrawal and H. D. Espinosa, "Giant piezoelectric size effects in zinc oxide and gallium nitride nanowires. A first principles investigation," Nano Lett. 11, 786(2011). 9. Y. Qi and M. C. McAlpine, "Nanotechnology-enabled flexible and biocompatible energy harvesting," Energy Environ. Sci. 3, 1275 (2010). 10. C. Chang, V. H. Tran, J. Wang, Y.-K. Fuh, and L. Lin, "Direct-write piezoelectric polymeric nanogenerator with high energy conversion efficiency," Nano Lett. 10, 726 (2010). 11. C.-T. Huang, J. Song, C.-M. Tsai, et al., "Single-InN-nanowire nanogenerator with up to 1 V output voltage," Adv. Mater. 22, 4008 (2010). 12. J. H. Jung, M. Lee, J.-I. Hong, et al., "Lead-free NaNb0 3 nanowires for a high output piezoelectric nanogenerator," ACS Nano 5, 10041 (2011). 13. S. Xu, G. Poirier, and N. Yao, "PMN-PT nanowires with a very high piezoelectric constant," Nano Lett. 12, 2238 (2012). 14. Z. Zhong, F. Qian, D. Wang, and C. M. Lieber," Synthesis of p-type gallium nitride nanowires for electronic and photonic nanodevices," Nano Lett. 3, 343 (2003). 15. R. Songmuang, O. Landré, and B. Daudin, "From nucleation to growth of catalyst-free GaN nanowires on thin A1N buffer layer," Appl. Phys. Lett. 91, 251902(2007) 16. W. Wu, S. Bai, M. Yuan, Y. Qin, Z. L. Wang, and T. Jing, "Lead zirconate titanate nanowire textile nanogenerator for wearable energy-harvesting and self-powered devices," ACS Nano 6, 6231 (2012).

242

Future Trends in Microelectronics

17. D. Yuan, R. Guo, Y. Wei, et al, "Heteroepitaxial patterned growth of vertically aligned and periodically distributed ZnO nanowires on GaN using laser interference ablation," Adv. Functional Mater. 20, 3484 (2010). 18. X. D. Wang, J. H. Song, P. Li, et al, "Growth of uniformly aligned ZnO nanowire heterojunction arrays on GaN, A1N, and Alo.5Gao.5N substrates," J. Amer. Chem. Soc. 127, 7920 (2005). 19. S. S. Lin, J. I. Hong, J. H. Song, et al, "Phosphorus doped Zn[.xMgxO nanowire arrays," Nano Lett. 9, 3877 (2009). 20. S. Xu, Y. G. Wei, M. Kirkham, et al, "Patterned growth of vertically aligned ZnO nanowire arrays on inorganic substrates at low temperature without catalyst," J. Amer. Chem. Soc. 130, 14958 (2008). 21. C.-T. Huang, J. Song, W.-F. Lee, et al," GaN nanowire arrays for high-output nanogenerators," J. Amer. Chem. Soc. 132, 4766 (2010). 22. B. Alloing, S. Vezian, O. Tottereau, P. Vennéguès, E. Beraudo, and J. ZunigaPéreza, "On the polarity of GaN micro- and nanowires epitaxially grown on sapphire (0001) and Si(lll) substrates by metal organic vapor phase epitaxy and ammonia-molecular beam epitaxy," Appl. Phys. Lett. 98, 011914 (2011). 23. S. Xu, B. J. Hansen, and Z. L. Wang, "Piezoelectric-nanowire-enabled power source for driving wireless microelectronics," Nature Commun. 1, 93 (2010). 24. X. Chen, S. Xu, N. Yao, and Y. Shi, "1.6 V nanogenerator for mechanical energy harvesting using PZT nanofibers," Nano Lett. 10, 2133 (2010). 25. Y.-Z. Chen, T.-H. Liu, C.-Y. Chen, et al, "Tapered PbZro.2Tio.eO3 nanowire arrays: From controlled growth by pulsed laser deposition to piezopotential measurements," ACS Nano 6, 2826 (2012). 26. S. J. Pearton, B. S. Kang, B. P. Gila, et al, "GaN, ZnO and InN nanowires and devices," J. Nanosci. Nanotechnol 8, 99 (2008). 27. X. Xu, A. Potié, R. Songmuang, et. al, "An improved AFM cross-sectional method for piezoelectric nanostractures properties investigation: application to GaN nanowires," Nanotechnology 22, 105704 (2011). 28. M. H. Zhao, Z. L. Wang, and S. X. Mao, "Piezoelectric characterization on individual zinc oxide nanobelt under piezoresponse force microscope," Nano Lett. 4, 587 (2004). 29. H. Fu and R. E. Cohen, "Polarization rotation mechanism for ultrahigh electromechanical response in single-crystal piezoelectrics," Nature 403, 281 (2000). 30. Y. Hu, L. Lin, Y. Zhang, and Z. L. Wang, "Replacing a battery by a nanogenerator with 20 V output," Adv. Mater. 24, 110 (2012). 31. G. Zhu, R. Yang, S. Wang, and Z. L. Wang, "Flexible high-output nanogenerator based on lateral ZnO nanowire array," Nano Lett. 10, 3151 (2010). 32. G. Ardila, R. Hinchet, M. Mouis, and L. Montès, "Scaling prospects in mechanical energy harvesting using piezoelectric nanostractures," Dig. IEEE Intern. Semicond. Conf. Dresden-Grenoble ISCDG (2012).

Mechanical Energy Harvesting with Piezoelectric Nanostructures

243

33. P. X. Gao, J. Song, J. Liu, and Z. L. Wang, "Nanowire piezoelectric nanogenerators on plastic substrates as flexible power sources for nanodevices," Adv. Mater. 19, 67 (2007). 34. W. Young and R. Budynas, Roark's Formulas for Stress and Strain, 7th ed., New York: McGraw-Hill, 2002. 35. R. Hinchet, J. Ferreira, J. Keraudy, G. Ardila, E. Pauliac-Vaujour, M. Mouis, and L. Montès, "Scaling rules of piezoelectric nanowires in view of sensor and energy harvester integration," Tech. Dig. IEDM(2012), paper 6.2. 36. M. Khoury, G. E. Tourtollet, and A. Schroder, "Contactless measurement of the elastic Young's modulus of paper by an ultrasonic technique," Ultrasonics 37, 133 (1999). 37. G. Zhu, A. C. Wang, Y. Liu, Y. Zhou, and Z. L. Wang, "Functional electrical stimulation by nanogenerator with 58 V output voltage," Nano Lett. 12, 3086 (2012). 38. Y. Hu, Y. Zhang, C. Xu, G. Zhu, and Z. L. Wang," High-output nanogenerator by rational unipolar assembly of conical nanowires and its application for driving a small liquid crystal display," Nano Lett. 10, 5025 (2010). 39. S. Xu, Y. Qin, C. Xu, Y. Wei, R. Yang, and Z. L. Wang, "Self-powered nanowire devices," Nanotechnology 5, 366 (2010). 40. J. Colomer-Farrarons, P. Miribel-Catala, A. Saiz-Vela, and J. Samitier, "A multiharvested self-powered system in a low-voltage low-power technology," IEEE Trans. Industrial Electronics 58,4250 (2011). 41. C. Xu and Z. L. Wang, "Compact hybrid cell based on a convoluted nanowire structure for harvesting solar and mechanical energy," Adv. Mater. 23, 873 (2011). 42. B. J. Hansen, Y. Liu, R. Yang, and Z. L. Wang, "Hybrid nanogenerator for concurrently harvesting biomechanical and biochemical energy," ACS Nano 4, 3647(2010).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Charged Quantum Dots for High-Efficiency Photovoltaics and IR Sensing A. Sergeev and V. Mitin Dept. of Electrical Engineering, SUNY-Buffalo, Buffalo, NY 14260-1920, U.S.A. N. Vagidov Optoelectronic Nanodevices LLC, Amherst, NY 14226-5126, U.S.A. K. Sablon U.S. Army Research Laboratory, Adelphi, MD 20783, U.S.A.

1.

Introduction

For many years significant efforts of scientific and engineering communities have been devoted to IR solar energy conversion that could drastically increase the output of the usable electric energy. As shown in Fig. 1, in a single-junction solar cell (SC) the conversion efficiency is limited by the phonon-mediated relaxation of photoelectrons to band-edges during the process of conversion of photons with above-bandgap energies, as well as by the cut-off of IR photons with energies below the bandgap. The maximum theoretical efficiency for conversion of unconcentrated solar energy, known as the Shockley-Queisser limit, is 31% for AMO spectrum.1 In single-junction GaAs SCs, more than 30% of solar energy falls into the IR sub-bandgap spectral region and more than 20% of solar energy is lost during the thermalization of high-energy photocarriers.

Figure 1. Usable power, thermalization losses, and losses of sub-bandgap photons vs. the bandgap in a single-junction solar cell. 244

Charged Quantum Dots for High-Efficiency Photovoltaics and IR Sensing

245

Quantum-dot (QD) optoelectronic materials and structures have attracted much attention2"4 due to their ability to match electronic transitions to specific IR photons and to increase electron coupling to IR radiation. The strong coupling enables high quantum efficiencies crucial for conversion of IR radiation and sensing. However, together with strong coupling to radiation, the optoelectronic materials for IR conversion and sensing should also provide long photocarrier lifetime and small recombination losses. Initial hopes for long lifetimes of photoexcited carriers were pinned on the theoretically predicted suppression of the electron-phonon relaxation in QDs, known as the "phonon bottleneck". Over several years, the results remained controversial, with some data supporting and other data contradicting the phonon bottleneck concept.5 Further investigations have shown that while the relaxation in QDs is slower than in bulk semiconductors, this effect is weak and insufficient for sensing and photovoltaic conversion.6 While the electron-phonon interaction is weakly suppressed in QDs, strong confinement of electrons in QDs drastically enhances inter-electron interaction. Therefore, in the relaxation of high-energy photocarriers, the electron energy is redistributed in the electron subsystem and is not wasted in the form of heat via electron-phonon interaction. For the first time, this effect was experimentally observed by Schaller and Klimov.7 They found that the inverse Auger process leads to very effective multiplication of electron-hole pairs. The multiple exciton generation (MEG) by absorbed high-energy photons is especially favorable for photovoltaic conversion. Theoretical calculations6 show that in a single-junction SC, MEG with maximum carrier multiplication increases the limiting efficiency by one third, to ~44%. However, for tandem SCs the MEG-related improvement of photovoltaic efficiency is limited to 2% only. Recent experiments8 demonstrated that MEG in PbSe QD SC increases the internal quantum efficiency to 130% and the total photocurrent by ~1 mA cm"2, which is still small for practical applications. Quantum dots also provide numerous possibilities for 3D band engineering. The most investigated QD SC design is the intermediate-band SC, where the intermediate band (IB) is formed by electron tunneling between QDs.4'9 In such a photovoltaic device, the electron-hole pairs may be generated in a two-step process. The electron is excited from the valence band to IB by the first photon and then it is excited from IB to a conduction band by a second photon. Such solar cell with optimized IB position is expected to have a limiting efficiency of 62%. To obtain an IB, an array of QDs of similar shapes and sizes is required in the active medium. In solid-state structures with QD layers, the correlated positions of QDs are realized via a local stress transferred from one layer to another. Accumulation of strain results in various defects, which, in turn, enhance recombination processes. While various technologies for reduction of the stress accumulation are proposed and employed, recombination losses in QD structures are still strong and prevail over the IR converted power. This is one of the main reasons why the QD band engineering has shown rather limited progress in photovoltaic and sensing applications.

246

Future Trends in Microelectronics

Looking for other ideas of employing of QDs, we have recently proposed10'11 and experimentally investigated12"14 3D nanoscale potential engineering by charged quantum dots in order to increase the photoelectron lifetime and reduce the recombination losses. In this technology, the nanoscale potential profile is created by quantum dots with built-in charge (Q-BIC) that are charged via selective doping of the regions between the dots. 2.

3D nanoscale potential profile in Q-BIC structures

Operation of semiconductor devices is essentially based on tunable potential barriers for electrons and holes. In the majority of modern devices, the potential profile changes only in one direction, but a 3D potential profile can provide more functionality and scalability to optoelectronic materials and structures. Tunable nanoscale potentials can provide an effective means for the engineering of electron processes for specific applications, opening wide perspectives for the development of adaptive optoelectronic materials. Charged quantum dots provide unique possibilities for creation of specific 3D potential profiles favorable for photovoltaic and sensing applications. Potential barriers around QDs are always created when electrons from dopants outside QDs fill the dots. In the simplest case, uniformly distributed charged quantum dots create local potential barriers. Charged quantum dots with correlated positions, such as QD clusters, planes, rows, etc. may be used to create higher collective potential barriers separating the QDs from conducting channels. It is well understood that the QDs are effective recombination centers. To suppress the photocarrier capture into QDs, the potential barrier around QD should be two-three times larger than kBT. Therefore, at room temperature, the local barriers should be ~ 0.05 eV. To evaluate and illustrate the potential created by a single dot, in Fig. 2(a) we present the electric potential of the half-filled spherical

Figure 2. (a) Electric potential ф of half-filled spherical InAs quantum dot in a GaAs matrix (left) and a number of localized electron states n per quantum dot (right) vs. the quantum dot radius R. (b) Schematics of Q-BIC solar cell structure with 6-doping of the spacers.

Charged Quantum Dots for High-Efficiency Photovoltaics and IR Sensing

247

InAs quantum dot in a GaAs matrix as a function of a QD radius R. As seen in Fig. 2, for small spherical dots even a weak QD charge of 2-3 electrons per dot creates substantial potential barriers that prevent the capture of thermally excited electrons. Now let us discuss real structures and nanoscale potential profiles in these structures. In the ongoing research, we employ Q-BIC structures with random dot positioning in QD planes. The Q-BIC structures have been fabricated using molecular beam epitaxy with typical growth temperatures of 500 ± 10 °C. The InAs QDs are grown on GaAs or AlGaAs surfaces by deposition of approximately 2.1 monolayers of InAs. To charge quantum dots, the structures have been doped in two different ways: with intra-dot doping, i.e. direct doping of QD layers, and with inter-dot (selective) doping, i.e. doping of the spacers separating the QD layers. The typical structure of the solar cell with 5-doping in the middle of the spacer is shown in Fig. 2(b). The dopant sheet concentration was chosen to provide up to 6 electrons per dot. The potential barriers in real structures are strongly anisotropic. To calculate the potential profile in such devices we employed nextnano3 software.15 As seen from Fig. 3(a), the charged QDs in the form of truncated pyramids with a large base and a small height create strongly asymmetric potential barriers. The barriers in the QD planes, /. e. in the direction perpendicular to the current, are substantially smaller than the barriers in the direction of the current. Therefore, the electron trapping is most effective for electrons moving along the A-B direction shown in Fig. 3(a). The fraction of such electrons decreases in structures with vertically correlated QD positions, where electrons move mainly in the channels between dots - see the white circles in Fig. 3(a). Let us note that the potential barrier in the A-B direction increases by -2.5 meV per electron, which is approximately one order of magnitude smaller than the increase of potential per electron in the C-D direction, compare the scales in Figs. 3(b) and (c). The potential in the C-D direction is similar in magnitude to the spherical dot of Fig. 2(a).

Figure 3. (a) The 3D potential profile in Q-BIC structure with QDs in the form of truncated pyramids combined with potential profiles along the A-B (b) and C-D (c) cross-sections.

248

Future Trends in Microelectronics

3. Photoelectron kinetics in Q-BIC structures Processes in QDs strongly depend on the electron/hole level structure. As we will see, the huge difference between electron and hole trapping by QDs are mainly determined by structures of electron and hole energy levels. The level structure in InAs/GaAs QDs was investigated via photoluminescence measurements. All data show practically equidistant level positions of electrons and holes,16"18 as shown in Fig. 4(a). The total level spacing, AE = AEE + Д£ н , where AEE and AEE are the electron and hole level separations respectively, was directly determined by photoluminescence measurements to be 60-80 meV. The A£E/A£H ratio varies between 2 and 8.16"19 By associating equidistant positions of energy levels with the quasi-parabolic confinement potential in InAs/GaAs QDs and invoking the hole and electron effective masses, obtain A£E = 55 meV and Д£ н ~ 14 meV. Thus, the electron spacing in QDs significantly exceeds the thermal energy and therefore electron transitions cannot be induced by thermal phonons, while the hole transitions are easily induced by thermal phonons. So we conclude that «-doping is strongly preferable to stimulate electron escape from QDs by IR radiation. Figure 4 shows the IR-assisted photogeneration of electron and hole pairs in undoped (Fig. 4(b)) and «-doped InAs/GaAs QD structures (Figs. 4(c)-(e)). Figure 4(c) describes a two-step process induced by «-doping with an IR electronic transition from a localized QD state to the conduction band. Figures 4(d) and 4(e) show other «-doping induced processes that involve inter-electron interactions in QDs. In Fig. 4(d) the radiation excites two electrons to QD excited states, then one of these electrons transfers to the conduction band while the other transfers to a low-energy state. In Fig. 4(e) the relaxation of electron to a low-energy state leads to the escape of a hole from the QD. We would like to highlight that due to the small hole level spacing, hole escape from QDs can be easily generated by hot (excited) electrons. Thus, doping should stimulate the radiation-induced electron escape from QDs. Therefore, contrary to the lasing applications of QDs, which are strongly enhanced by p-doping,19 the photovoltaic applications require «-doping.

Figure 4. (a) Level structure in InAs/GaAs quantum dots and transitions measured in photoluminescence measurements; IR-assisted photogeneration of electron-hole pairs in undoped QD structures (b) and various processes in n-doped Q-BIC structures (c, d, e).

Charged Quantum Dots for High-Efficiency Photovoltaics and IR Sensing

249

The photoelectron capture by repulsive и-charged QDs may be realized via tunneling through the barrier or thermal excitation above the barrier. Calculations show10 that in QDs with radius larger than 5-10 nm at room temperature, the thermal excitation processes dominate over tunneling in the photoelectron capture. In this case, the temperature dependence of the capture rate is given by:10 1

i ,

— = nNDRTE exp

"capt

Ne2 kBTKR

(1)

where N^ is the dot concentration, TE is the electron-phonon inelastic scattering time that corresponds to transitions with characteristic electron level spacing in QD, eN is the charge of the quantum dot, and к is the permittivity. The hole capture by the repulsive и-charged QDs is given by:20

-L = inND(R*f^ ^capl

3

,

(2)

where тн is the hole cascade relaxation time (тн ~ х0(ЗквТ/АЕи), т0 is the relaxation time between adjacent hole levels); R* is the larger of the dot radius R or Thomson's radius e2N/(KkBT). According to Fig. 2(a), for the suitable for Q-BIC technology parameters, the characteristic capture radius R* is equal to the dot radius. Thus, according to Eqs. (1) and (2), the «-charging of QDs exponentially suppresses electron capture processes, but does not much affect hole capture. Suppression of photoelectron capture by «-charging of QDs exponentially increases the photoelectron lifetime in all QD unipolar devices. In QD photodetectors, the long photoelectron lifetime increases the photoresponse, decreases the generation-recombination noise, and improves the sensitivity.13 The «-charging of QDs is favourable for photovoltaic applications also. In undoped or weakly doped InAs/GaAs QD structures, the capture of electrons is substantially faster than the capture of holes. Suppression of the fastest capture processes by ncharging of QDs decreases the recombination via QDs and recombination losses. We would like to highlight that under illumination the electron and hole capture rates can be tuned by changing the QD charge. In "underdoped" structures QDs will be filled by photoelectrons, in the "overdoped" structures electrons will leave QDs. Therefore, to optimize the potential profile in QD solar cell, one should choose the optimal doping that provides equal electron and hole capture rates Tcapt of Eqs. (1) and (2) by changing N, the number of electrons per dot. As discussed above, the hole capture rate is practically independent on QD charge and, therefore, at the optimal «-doping the capture rate of electrons and holes under the sunlight is equal to the slow hole capture rate. 4.

Q-BIC solar cells and IR detectors

We have experimentally investigated quantum dot infrared photodetectors (QDIPs) and QD SCs based on Q-BIC structures with random positions of dots in QD planes. The main parameters of our Q-BIC solar cells are summarized in Table 1.

Future Trends in Microelectronics

250 N (electrons) Ref. cell (no dots) 0 2 3 6

àJsc (mA/cm2)

J'oc (V)

Fill Factor (%)

Efficiency (%)

14.6

0

0.81

80

9.07

15.1 17.3 18.5 24.3

4.1 7.2 8.1 9.3

0.77 0.74 0.79 0.78

77 76 75 72

9.31 9.73 12.1 14.0

-'sc (mA/cm2)

Table 1. Parameters of Q-BIC solar cell devices.

The Q-BIC solar cell with maximal и-doping (six electrons per dot) demonstrates a strong increase in the short-circuit current JSc from 15.1 mA/cm2 to 24.3 mA/cm2, with negligible degradation of the open-circuit voltage Voc. The third column in Table 1 shows the IR contribution AJSc to the short-circuit current. These data have been directly obtained in experiments, where the above-bandgap part of solar spectrum was completely suppressed by the corresponding filter (so the reference cell without QDs did not show any photoresponse). As seen from Table 1, the conversion of IR radiation of Q-BIC solar cells increases with the increase of the built-in-dot charge. At the и-doping level that provides six electrons per dot, the conversion of solely IR radiation via QD transitions gives ~9 mA/cm2 contribution to the Jsc. Thus, in our current Q-BIC devices the harvesting and conversion of IR part of solar spectrum give additional 5% to the photovoltaic efficiency. In Table 2 we have summarized parameters of our QDIP devices. In devices B44 and B52, the charging of QDs has been realized via doping of QD layers (intra-dot doping); whereas in devices B45 and B53, the QDs were charged by doping of spacers (inter-dot doping). The effective average charge of the QDs and the corresponding potential barriers in the QD plane (see Fig. 3) were found by modelmg, described in Section 2. The measured spectral dependences show a maximum photoresponse at -329 meV with the half maximum width -40 meV.

Device

Doping

B44 B45 B52 B53

Intra-dot Inter-dot Intra-dot Inter-dot

Donor concentration (10 n cm- 3 ) 2.7 2.7 5.4 5.4

Table 2. Parameters of Q-BIC IR photodetectors.

Effective QD charge (electrons) 1.8 2.8 3.45 6.1

Potential barrier (meV) 4.5 7 8.6 15.3

Charged Quantum Dots for High-Efficiency Photovoltaics and IR Sensing 10

E o

111 fi 1111111111111 (1111111 ii M 11 |i 11 г т ^ т г г р т п т г г т т т г т т т т i'j 11

; - • — IR contribution to J$c in Q-BIC solar cells —A—-IR photoresponse in Q-BIC detectors, — — "

.

35 30

251

c3 .a

25 m

E *****

20 "c Ф

15 h

O


]U- [(a>0+goMx)/Q0]U+ $Rsph(o0V, dVdi 2 + 2(QM/QM)dx/dt + CïM2x = -UgOM/(meííit number using 72k3 elementary quantum gates; e.g., factoring 15 requires 4608 gates operating on 21 qubits.17 However, Ref. 17 introduced a compiling technique that exploits properties of the number to be factored, allowing the implementation of Shor's algorithm with a vastly reduced number of resources. One might say that this is a sort of (innocent) cheating: knowing in advance that 15 = 3x5, we can take some shortcuts, which would not be possible if the result were not known beforehand. All the existing experimental testing of Shor's algorithm use this simplified approach. Recently, in a very remarkable report of Martin-López et a/.,18 this approach allowed for the first time the factoring of 21 in an optical experiment, where an iterative procedure of recycling a single qubit was successfully implemented. The demonstration of the full Shor's algorithm for factoring 15 is still well beyond the reach of experimental possibilities (see the prediction in Ref. 19). As to the liquid NMR quantum computing technique, it seems that it should rather be regarded as a classical simulation of the quantum algorithm.19 This was also pointed out in Refs. 15 and 20: "The ability to describe the correlations observed in NMR experiments in terms of classical correlations between the qubits casts doubt on the 'quantumness' of the experiments".20 Error correction. Several outstanding recent experiments21"23 (references to some earlier work can be found therein) demonstrated elementary error correction with 3 to 8 qubits in line with the 2007 goals of the experts' panel. Schindler et al.2i implement multiple quantum error correction cycles for phase-flip errors in a system of three trapped-ion qubits. Each cycle consisted of: (i) encoding one qubit and two auxiliary (ancilla) qubits into an entangled state; (ii) error incidence; (iii) detecting and correcting the error; and (iv) resetting the ancillas. Reed et al.22 realized three-qubit quantum error correction with superconducting circuits by implementing the three-qubit Toffoli gate. They performed both bit- and phase-flip error corrections with fidelity around 80%. Yao et al.23 reported the first experimental demonstration of "topological" error correction with a polarization-encoded eight-photon cluster state (see Refs. 23-25 for an explanation of the idea of topological cluster state computing). The authors demonstrated that: (i) if only one physical qubit suffers an error, the noisy qubit can be located and corrected; and (ii) if all qubits are simultaneously

Future Trends in Microelectronics

270

subjected to errors with equal probability, the effective error rate is significantly reduced by error correction. The artificial errors introduced and then corrected in such experiments are strong: basically the state |0) is changed to |1>. Using classical language, the error consists in reversing the direction of some vector (or rotating it by 90°). However, the relevant errors, with which we are supposed to fight, are weak: the noise transforms the state |0) to a|0)+è|l),with |è| « 1 (the vector is rotated by a small angle). Error correction consists in detecting the unwanted admixture of state |1) and eliminating this admixture. This task is especially difficult because in any experimental setup one will always have some uncontrolled admixture of state 11) from the start (see Section 8). So, we will have to wait until somebody demonstrates the possibility of preparing a qubit in the state |0) with a precision of 10~6-10~4, detecting an error of the same order of magnitude, and then correcting it with the same precision. (In the eventual quantum computer such repetitive cycles are supposed to be performed simultaneously on at least a thousand qubits). 5.

Proposals: Quantum computing with ...

The multitude of proposals of different ways to do quantum computing, as well as of various physical objects that can serve as qubits, is truly amazing. A simple list of such proposals would require the entire space allocated for this article. To show just the tip of the iceberg, below is a small number of randomly picked proposals (source: arXiv.org, references can be easily found there). For more information the reader is invited to Google "quantum computing with". non-deterministic gates bosonic atoms highly verified logical cluster states Pfaffian qubits hyperfine clock states four-dimensional photonic qubits (known as qudits) quantum-dot cellular automata in dephasing-free subspace generalized binomial states ID projector Hamiltonian quantum-dot spin qubits inside a cavity graphene nanoribbons alkaline earth atoms Jaynes-Cummings model doped silicon cavities Read-Rezayi states electron spin ensemble ultra narrow optical transition of ultracold neutral atoms in an optical lattice p-wave superfluid vortices

State of the Art and Prospects for Quantum Computing

271

railroad-switch local Hamiltonians global entangling gates semiconductor double-dot molecules decoherence-free qubits superqubits defects devices whose contents are never read alkaline-earth-metal atoms ionic Wigner crystals nanowire double quantum dots waveguide-linked optical cavities orbital angular momentum of a single photon probabilistic two-qubit gates non-deterministic gates small space bounds interaction on demand perpetually coupled qubits only one mobile quasiparticle moving quantum dots generated by surface acoustic waves para-hydrogen programmable connections between gates incoherent resources and quantum jumps v = 5/2 fractional quantum Hall state spin ensemble coupled to a stripline cavity vibrationally excited molecules Kerr-nonlinear photonic crystals atoms in periodic potentials Heisenberg ABAB chain endohedral fullerenes harmonic oscillators Isn't this wonderful? Apparently, there is nothing at all that is not suitable for quantum computing! Let us consider just one of the proposals listed above, "quantum computing with the v = 5/2 fractional quantum Hall state".26 The experimentally observed v = 5/2 Hall plateau is unlike all the others (for which the denominator of the filling factor v is odd) and it does not fit into the composite fermion concept. Some people think that this is a manifestation of anyons, hypothetical particles intermediate between bosons and fermions that may exist in two dimensions. (See also the Anyon Theory o/High-Tc Superconductivity,21 now completely forgotten). Others think differently, and nobody really knows. Hence the obvious proposal: to use these anyons for quantum computing. We must move them around one another producing complex topological structures, so that knot theory may be used. The great advantage is that topological structures are intrinsically protected against noise.28

Future Trends in Microelectronics

272

The disadvantages are mostly on the practical side. Quantum Hall plateaus are observed in high magnetic field with a roughly 3x6 mm sample immersed in liquid helium. The sample has several wires attached, typically 6, to apply and measure voltages and currents. The number of 2D electrons in the sample is about 1010, and presumably it contains a similar number of anyons. So how are we supposed to create topological structures with these hypothetical anyons, just by applying voltages to the 6 (or, if one insists, even 6000) wires at our disposal? However, this is an old story by now. Currently, it is supposed that the Majorana fermions,29 rather than anyons, are responsible for the 5/2 Hall plateau. Consequently, it became obvious that quantum computing with Majorana fermions is extremely promising. The Majorana fermion theory of high Tc superconductivity is likely to emerge in the near future. The reader might have an immediate impulse to propose topological insulators, of which we have recently heard so much, for topological quantum computing, simply because both are "topological" (like "quantum dots for quantum computing"). Too late! This has been done already.30 A by-product of this frenetic activity is that every physical object has become a qubit, irrespective of the quantum computing context: electron spin qubit hole spin qubit nuclear spin qubit Josephson superconducting qubit cavity photon qubit trapped ion qubit Heisenberg ABAB chain qubit para-hydrogen qubit etc. This looks pretty, like some modern poetry. So, instead of saying like in the good old days, "we are studying nuclear spin resonance", one should now say: "We are studying the decoherence of nuclear spin qubits", thus implying that this work is directly related to the big problems of the day. 6.

Theory: Assumptions (axioms) underlying the threshold theorem

Like any theorem, the threshold theorem relies on a number of assumptions, considered as axioms: 1. 2. 3. 4.

Qubits can be prepared in the |00000...00) state. New qubits can be prepared on demand in the state |0); The noise in qubits, gates, and measurements is uncorrelated in space and time; No undesired action of gates on other qubits; No systematic errors in gates, measurements, and qubit preparation;

State of the Art and Prospects for Quantum Computing 5. 6. 7.

No undesired interaction between qubits; No "leakage" errors; Massive parallelism: gates and measurements simultaneously to many qubits;

273

can

be

applied

and some others. While clearly stated in the original work, the existence of these assumptions was largely ignored later, especially in presentations to the general public (Ref. 12 is one of many examples). One would expect that the above assumptions, treated as axioms (i.e. as being exact), would undergo a close scrutiny to verify that they can be reasonably approached in the physical world. Moreover, the term "reasonably approached" should have been clarified by indicating with what precision each assumption should be fulfilled. So far, this has never been done (assumption 2 being an exception31'32), if we do not count the rather naive responses provided in the early days of quantum error correction.33-35 It is quite normal for a theory to disregard small effects whose role can be considered as negligible. But not when one specifically deals with errors and error correction. A method for correcting some errors on the assumption that other (unavoidable) errors are nonexistent is not acceptable, because it uses fictitious ideal elements as a kind of a gold standard.36 7.

Precision of continuous quantities and the basic axiom

Below are some trivial observations regarding manipulation and measurement of continuous variables. Suppose that we want to know the direction of a classical vector, like the compass needle. First, we never know our coordinate system exactly. We choose the x, y, z axes related to some physical objects, with the z axis directed, say, towards the Polar Star. However, neither this direction, nor the angles between our axes can be defined with an infinite precision. Second, the orientation of the compass needle with respect to the chosen coordinate system cannot be determined exactly. So, when we say that our needle makes an angle 9 = 45° with the z axis, we understand that cosG is not exactly equal to the irrational number 1/V2, but rather falls somewhere around this value within some interval determined by our ability to measure angles and other uncertainties. We also understand that we cannot manipulate our needles perfectly, that no two needles can ever point exactly in the same direction, and that consecutive measurements of the direction of the same needle will give somewhat different results. In the physical world, continuous quantities can be neither measured nor manipulated exactly. In the spirit of the purely mathematical language of the quantum computing theory, this can be expressed in the following form: Axiom 1: No continuous quantity can have an exact value. Corollary: No continuous quantity can be exactly equal to zero.

Future Trends in Microelectronics

274

To a mathematician, this might sound absurd. Nevertheless, this is an unquestionable reality of the physical world in which we live.37'38 Note that discrete quantities, like the number of students in a classroom or the number of transistors in the on-state, can be known exactly and this is what makes the great difference between the digital computer and an analog computer. Axiom 1 is crucial whenever one deals with continuous variables. Thus if we devise some technical instruction, each step should contain an indication of the needed precision. Do not tell the engineer: "Make this angle 45°, and then my proposed vehicle will run as predicted, under the assumption that the road is flat". This makes no sense! Tell him instead: "Make this angle 45° ± 0.0Г, and then my proposed vehicle will run as predicted, provided the roughness of the road does not exceed 10 nm" (or 10 cm, whatever the theory says). Only then will the engineer be in a position to decide whether this is possible or not. All of this is quite obvious, and nobody is going to believe that even in a thousand years somebody will manage to make the angle exactly 45° and provide an absolutely flat road to implement our invention. 8.

Precision of quantum amplitudes

Apparently, things are not so obvious in the magic world of quantum mechanics. There is a widespread belief that the |0) and |1) states "in the computational basis" are something absolute, akin to the on/off states of an electrical switch, or of a transistor in a digital computer,39 but with the advantage that one can use quantum superpositions of these states, see Fig. 2. It is sufficient to ask: "with respect to which axis do we have a spin-up state?" to see that there is a serious problem with such a point of view. It should be stressed once more that the coordinate system, and hence the computational basis, cannot be exactly defined, and this has nothing to do with quantum mechanics. Suppose that, again, we have chosen the z axis to point towards the Polar Star, and we measure the z-projection of the spin with a SternGerlach beam-splitter. There will be inevitably some (unknown) error in the alignment of the magnetic field in our apparatus with the chosen direction. Thus, when we measure some quantum state and get (0), we never know exactly to what state the wavefunction has collapsed. Presumably, it will collapse to the spin-down state with respect to the (not known exactly) direction of the magnetic field in our beam-splitter. However, with respect to the chosen z axis (this direction is not known exactly either), the

Figure 2. The theorist's image of a qubit.

State of the Art and Prospects for Quantum Computing

275

wavefunction will always have the form a|0) + è|l), where hopefully \b\2 « 1. Another measurement with a similar instrument or a consecutive measurement with the same instrument will give a different value of b. Quite obviously, the unwanted admixture of the |1) state is an error that cannot be corrected, since (contrary to the assumption 1 above) we can never have the standard exact |0) and 11) states to make the comparison. Thus, with respect to the consequences of imperfections, the situation is quite similar to what we have in classical physics. The classical statement "the exact direction of a vector is unknown" is translated into quantum language as "there is an unknown admixture of unwanted states". The pure state |0) can never be achieved, just as a classical vector can never be made to point exactly in the z direction, and for the same reasons - after all, quantum measurements and manipulations are done with classical instruments. Clearly, the same applies to any desired state. Thus, when we contemplate the "cat state" (|0000000)+| 1111111»W2, we should not take the л/2 too seriously, and we should understand that some (maybe very small) admixture of all other 126 possible states of 7 qubits must be necessarily present. Exact quantum states do not exist. Some admixtures of all possible states to any desired state are unavoidable. This fundamental fact, described by Axiom 1 (nothing can be exactly zero!), should be taken into account in any prescriptions for quantum error correction. Note, that the "digitization" of noise, which is the cornerstone of the existing errorcorrecting schemes, is based on the opposite assumption, that the exact |0) and |1) states can be prepared. At first glance, it may seem that there are possibilities for achieving a desired state with an arbitrary precision. Indeed, using nails and glue, or a strong magnetic field, we can fix the compass needle so that it will not be subject to noise. We still cannot determine exactly the orientation of the needle with respect to our chosen coordinates, but we can take the needle's direction as the z axis. However: (i) we cannot align another fixed needle in exactly the same direction; and (ii) we cannot use fixed needles in an analog machine; to do this, they must be detached to allow for their free rotation. Quite similarly, in the quantum case we can apply a strong enough magnetic field to our spin at a low enough temperature, and wait long enough for the relaxation processes to establish thermodynamic equilibrium. Apparently, we will then achieve a spin-down |0) state with any desired accuracy (provided there is no interaction with other spins in our system, which is hardly possible). However, "spin-down" refers to the (unknown exactly) direction of the magnetic field at the spin location. Because of the inevitable inhomogeneity of the magnetic field, we cannot use the direction of the field at the spin location to define the computational basis, since other spins within the same apparatus will be oriented slightly differently. Moreover, if we want to manipulate this spin, we must either switch off the magnetic field (during this process the spin state will

276

Future Trends in Microelectronics

necessarily change in an uncontrolled manner), or apply a resonant ac field at the spin precession frequency, making the spin levels degenerate in the rotating frame. The high precision acquired in equilibrium will be immediately lost. Likewise, an atom at room temperature may be with high accuracy considered to be in its ground state. Atoms at different locations will be always subject to some fields and interactions, which mix the textbook ground and excited states. Also, such an atom is not yet a two-level system. In order for it to become a qubit, we must apply a resonant optical field, which will couple the ground state with an excited state. The accuracy of the obtained states will depend on the precision of amplitudes, frequencies, and duration of optical pulses. This precision might be quite sufficient for many applications, but certainly it can never be infinite. Thus, Axiom 1 applies to all continuous variables, quantum amplitudes included.

9.

The fundamental trouble with the error-correction theory

The trouble lies in not respecting Axiom 1, i.e. in assuming that all the numerous assumptions (axioms) behind the threshold theorem are fulfilled exactly. This is not possible, not in our world.37 Of course, if the assumptions underlying the threshold theorem were approached with a high enough precision, the prescriptions for error-correction could indeed work. So, the real question is: what is the required precision with which each assumption should be fulfilled to make scalable quantum computing feasible? How small must we make the undesired, but unavoidable errors due interaction between qubits, influence of gates on other qubits,40 systematic errors of gates and measurements,34 leakage errors, random and systematic errors in preparation of the initial |0) states, etc.1 Quite surprisingly, not only is there no answer to these crucial questions in the existing literature, but they have never even been seriously discussed! Had this problem been realized, the threshold theorem would not be formulated in terms of "error per qubit per gate" only, but also by indicating the required precision with which various assumptions should be fulfilled. Obviously, this gap must be filled, and the required precision for each assumption should be specified. Until this is done, one can only speculate about the final outcome of such a research. The optimistic prognosis would be that some additional threshold values e b e2... for corresponding precisions will be established, and that these values will be shown neither to depend on the size of the computation nor to be unacceptably small. In this case, the dream of factoring large numbers by Shor's algorithm might become reality in some distant future. The pessimistic view, which I share, is that the required precision must increase with the size of computation, most probably in an exponential manner, and this would sink quantum computing as a practical technique. Classical physics gives us some enlightening examples regarding attempts to impose a prescribed evolution on quite simple continuous systems. Consider some number of hard balls in a box. At time t = 0 all the balls are on the left side and

State of the Art and Prospects for Quantum Computing

277

have some initial velocities. We let the system run for some time, and att = t0 we simultaneously reverse all the velocities. Classical mechanics tells us that at t = 2t0 the balls will return to their initial positions on the left side of the box. Will this ever happen in reality, or even in computer simulations? The known answer is: Yes, provided the precision of the velocity inversion is exponential in the number of collisions during the time 2t0. If there is some slight noise during the whole process, it should be exponentially small too. Thus, if there are only 10 collisions, our task is difficult but it still might be accomplished. But if one needs 1000 collisions, it becomes impossible, not because Newton's Laws are wrong, but rather because the final state is strongly unstable against very small variations of the initial conditions and very small perturbations. This classical example is not directly relevant to the quantum case (see Ref. 41 for the relation between classical and quantum chaos). However, it hints why, although some beautiful and very difficult experiments with small numbers of qubits have been done (see Section 3 for recent results with 3-8 qubits), the goal of implementing a concatenated quantum error-correcting code with 50 qubits (set by the ARDA experts' panel for the year 2012!) is still nowhere in sight. To summarize, I reiterate my main points: 1. The hopes for scalable quantum computing are founded entirely on the "threshold theorem": once the error per qubit per gate is below a certain value, indefinitely long computations are possible; 2. The mathematical proof of the threshold theorem heavily relies on a number of assumptions supposed to be fulfilled exactly, as axioms; 3. In the physical world nothing can be exact when one deals with continuous quantities. For example, it is not possible to have zero interaction between qubits, it can only be small; 4. Since the basic assumptions cannot be fulfilled exactly, the question is: What is the precision to which each assumption should be fulfilled? 5. Until this crucial question is answered, the prospects of scalable quantum computing will remain uncertain. 10. Mathematics and physical reality Besides having an enormous intrinsic value, mathematics is indispensable for understanding the physical world, as well as for all practical human activities. However, there are many ways of abusing mathematics. For example, you want to discuss the very complex phenomenon of love. If you are a poet or a sexologist or, better still, if you have some experience of your own, you may have a chance to say something reasonable. But if the only thing you have up your sleeve is to write the Hamiltonian of the couple as H = Hx + H2 + V, with V being a sum of products of operators belonging to the subspaces 1 and 2, and then, under certain assumptions, you prove some theorems, quite obviously your rigorous results will be both wrong and irrelevant. And the reason is that you

278

Future Trends in Microelectronics

simply have no idea even about #i_ and still less about H2, not to mention V. As a consequence, whatever your assumptions are, they are groundless.42 Another example, nearer to our subject, can be found in Jaroslav Hašek's masterpiece.43 The good soldier Švejk spends some time in a madhouse, where one of the professors among the patients tries to convince everybody that "inside the terrestrial globe there is another globe of a much greater diameter". In fact, that mad professor's claim is consistent with the well-known fact that, in certain metric spaces, a ball of a bigger radius may be properly contained in one of a smaller radius. Another (perfectly rigorous) result, which he also anticipated in a way, is the famous Banach-Tarski paradox that was discovered 10 years later;44 see the very clear article in Wikipedia.45 A version of the Banach-Tarski theorem states that, given a small ball and a huge ball in the usual 3D Euclidean space, either one can be partitioned into pieces and then reassembled into the other. Note that the number of pieces is finite, and the reassembly process consists in moving them around, using only translations and rotations (but no stretching). Thus, as Wikipedia puts it, "a pea can be chopped up and reassembled into the Sun". The interested reader must learn about metric space, nonmeasurable sets, and other mathematical technicalities in order to understand how it is possible that a rigorously proved theorem contradicts our common sense, and whether we should revise our common sense accordingly. The short answer is no, because our common sense is based on the structure of the surrounding physical world, while the axioms behind the theorem are not. Now, imagine some society on another planet, where an army of scientific journalists not familiar with the technicalities cites the distinguished experts, affirming (quite correctly, in some sense) that it has been proved that one can build a full-scale skyscraper on the basis of its 1000:1 model without using any additional material, and more importantly, that the same applies to a tank or a submarine. Scientists in top-secret labs are developing the technical procedures, and many promising materials have been already proposed, such as endohedral fullerenes, ionic Wigner crystals, and some others. That's what is happening in some places of our planet with respect to the threshold theorem: "The theory of fault-tolerant quantum computation establishes that a noisy quantum computer can simulate an ideal quantum computer accurately. In particular, the quantum accuracy threshold theorem asserts that an arbitrarily long quantum computation can be executed reliably, provided that the noise afflicting the computer's hardware is weaker than a certain critical value, the accuracy threshold".*6 In other words, the possibility of scalable quantum computing has been rigorously proved As we have seen, this is not true. No theorem can be proved without a set of axioms on which it relies. It is not the mathematician's concern whether his axioms describe the physical reality correctly or not. However, this should be the main concern for those who want to apply the theorem to the physical world. This question lies outside mathematics and the only way to solve it is to consult experiment and the "engineers". They will ask some hard questions, because "decoherence-free subspaces" and

State of the Art and Prospects for Quantum Computing

279

"approaching with arbitrary precision any unitary transformation on n qubits by an appropriate number of gates from the universal set" is not in their vocabulary. Dorit Aharonov, one of the authors of the threshold theorem, wrote in 1998: "In a sense, the question of noisy quantum computation is theoretically closed. But a question still ponders our minds: Are the assumptions on the noise correct?"47 And indeed, the question is closed in the sense that, based on a number of axioms, the theorem has been proved. However, if by "noise" we mean all sorts of uncertainties and undesired disturbances inevitably occurring in reality, then the assumptions on the noise are not correct, because some unavoidable noise is assumed to be absent, and some quantum states are assumed to be exact. In this other sense, the question remains wide open. Until somebody specifies the required precision with which various assumptions should be approached, the prospects of scalable quantum computing will be far from clear. 11. More powerful in doing what? Suppose that, in spite of the above arguments, a quantum computer will be built one day. Why should anyone need it? Fifteen years ago, John Preskill wrote:48 But suppose I could buy a truly powerful quantum computer off the shelf today - what would I do with it? I don't know, but it appears that I will have plenty of time to think about it! My gut feeling is that if powerful quantum computers were available, we would somehow think of many clever ways to use them." At the same time, Andrew Steane put it somewhat differently:1 The idea of "Quantum Computing" has fired many imaginations simply because the words themselves suggest something strange but powerful, as if the physicists have come up with a second revolution in information processing to herald the next millenium.49 This is a false impression. ... If large quantum computers are ever made, they will be used to address just those special tasks which benefit from quantum information processing. So, after 15 years of thinking, what are those clever ways and those special tasks? Apparently, just like fifteen years ago, there are only two of them:50 factoring very large numbers by Shor's algorithm and simulation of quantum systems, which was the original idea of Feinman51 who started the whole field 30 years ago. Let us discuss the utility of these two potential applications. Factoring. Some (but not all) of existing cryptographic systems depend on the difficulty of factoring very large numbers (products of two or several very large primes). This means that Shor's algorithm could break cryptography codes. This, in turn, implies the need for quantum cryptography. Thus we encounter the following logic: (i) we will build quantum computers, then we will be able to know our enemies' secrets, and this is good; but (ii) after some time our enemies will also manage to build their own quantum computer,

280

Future Trends in Microelectronics

then they will be able to know our secrets, this would be very bad; so (iii) anticipating this threat, we should develop the methods of quantum cryptography now, even before the first quantum computer is built. So, it appears that the justification for implementing large-scale Shor's algorithm is solely in opening the need for quantum cryptography, because otherwise the existing cryptography methods are quite safe. This logic would be understandable, from a certam point of view, had it not been for the existence of several cryptography systems, that do not depend on factoring, and cannot be broken by a quantum computer, at least by any known means.52 Thus there seems to be no practical sense in performing factoring with a quantum computer. In my opinion, this does not diminish the importance of Shor's outstanding theoretical achievement.13 Simulating quantum systems. In 1996 Lloyd53 proved the correctness of Feynman's conjecture51 that quantum computers can be programmed to simulate any local quantum system. Some people believe that, because of this, quantum computing will have a revolutionary impact in physics, chemistry, and biology. The last statement seems too strong, since so far numerical calculations and simulations, while useful, were never of primary importance for these fields. However, obviously many theorists would like to have a device that could efficiently solve quantum problems of strongly interacting particles, when no simplifying approximations can be justified. Since the dimension of the Hilbert space increases exponentially with the number of particles N, making numerical calculations for N = 50 is usually impossible and one has to be content with small values of N, up to 10 or 15, and extrapolate the results to the limit N -» a>. This is not always easy, so it would be really nice if it were possible to do such calculations, say, up to N = 1000 (see the recent review54 for existing ideas and algorithms for quantum simulation). In summary, it appears that simulation of strongly interacting quantum systems is the only meaningful possible application of the hypothetical quantum computer. Certainly, this would be an interesting and useful achievement, but hardly revolutionary, unless we understand this term in some very narrow sense. 12. Quantum computing as a sociological problem I believe that, despite appearances, the quantum computing story is nearing its end, not because somebody is about to prove that it is impossible, but rather because 20 years is a typical lifetime of any big bubble in science, because too many unfounded promises have been made, because people get tired and annoyed by almost daily announcements of new "breakthroughs",55 because all the tenure positions in quantum computing are already occupied, and because the proponents are growing older and less zealous, while the younger generation seeks for something new. The brilliant works of Feynman,51 Deutsch,56 Shor,13 and some others, will certainly remain for a long time because new and audacious ideas are always

State of the Art and Prospects for Quantum Computing

281

valuable, whether they lead to practical results, or not. However, this does not apply to the major part of the huge QC literature. In fact, quantum computing is not so much a scientific as a sociological problem, which has expanded out of all proportion due to the US system of funding scientific research (which is now being copied all over the world). While having some positive sides, this system is unstable against spontaneous formation of bubbles and mafia-like structures. It pushes the average researcher to wild exaggerations bordering on fraud, and sometimes beyond. Also, it is much easier to understand the workings of the funding system, than the workings of Nature, and these two skills only rarely come together. The QC story says a lot about human nature, the scientific community, and the society as a whole, so it deserves in-depth psycho-sociological studies, which should begin right now, while the main actors are still alive and can be interviewed. A somewhat similar story can be traced back to the 13th century when Nasreddin Hodja57 made a proposal to teach his donkey to read and obtained a tenyear grant from the local Sultan. For his first report he put breadcrumbs between the pages of a big book, and demonstrated the donkey turning the pages with his hoofs. This was a promising first step in the right direction. Nasreddin was a wise but simple man, so when asked by friends how he hopes to accomplish his goal, he answered: "My dear fellows, before ten years are up, either I will die or the Sultan will die. Or else, the donkey will die." Had he the modern degree of sophistication, he could say, first, that there is no theorem forbidding donkeys to read. And, since this does not contradict any known fundamental principles, the failure to achieve this goal would reveal new laws of Nature.58 So, it is a win-win strategy: either the donkey learns to read, or new laws will be discovered. Second, he could say that his research may, with some modifications, be generalized to other animals, like goats and sheep, as well as to insects, like ants, and flies, and this will have great potential for national security: these beasts could easily cross the enemy lines, read the secret plans, and report them back to us. The modern version of this love-song for military sponsors might run as follows: The transistors in our classical computers are becoming smaller and smaller, approaching the atomic scale. The functioning of future devices will be governed by quantum laws. However, quantum behavior cannot be efficiently simulated by digital computers. Hence, the enormous power of quantum computers will help us to design the future quantum technology. This may look good to a project manager, or in some science digest magazine, but for anyone who understands something about simulation, quantum laws, transistors, and atoms, this does not make any sense at all. The saga of quantum computing is waiting for a deep sociological analysis, and some lessons for the future should be learnt from this fascinating adventure.

282

Future Trends in Microelectronics

Acknowledgments I thank Konstantin Dyakonov for very useful discussions and suggestions. References 1. A. M. Steane, "Quantum computing," Reports Prog. Phys. 61, 117 (1998); arXiv: quant-ph/9708022. 2. A Quantum Information Science and Technology Roadmap, Part 1: Quantum Computation. Available at http://qist.lanl.gov/qcomp-map.shtml 3. P. W. Shor, "Fault-tolerant quantum computation," in: Proc. 37th Symp. Foundations Computing, New York: IEEE Computer Society Press, 1996, p. 56; arXiv: quant-ph/9605011 4. J. Preskill, "Fault-tolerant quantum computation," in: H.-K. Lo, S. Papesku, and T. Spiller, eds., Introduction to Quantum Computation and Information, Singapore: World Scientific, 1998, p. 213; arXiv:quant-ph/9712048 5. D. Gottesman, "An introduction to quantum error correction," in: S. J. Lomonaco, Jr., ed., Quantum Computation: A Grand Mathematical Challenge for the Twenty-First Century and the Millennium, Providence, RI: American Mathematical Society, 2002, p. 221; arXiv:quant-ph/0004072 6. A. M. Steane, "Quantum computing and error correction," in: A. Gonis and P. Turchi, eds., Decoherence and its Implications in Quantum Computation and Information Transfer, Amsterdam: IOS Press, 2001, p. 284; arXiv:quantph/0304016 7. A. R. Calderbank and P. W. Shor, "Good quantum error-correcting codes exist," Phys. Rev. A 54, 1098 (1996). 8. A. M. Steane, "Error correcting codes in quantum theory," Phys. Rev. Lett. 11, 193 (1996). 9. D. Aharonov and M. Ben-Or, "Fault tolerant quantum computation with constant error," in: Proc. 29th Annual ACM Symp. Theory Computation, New York: ACM Press, 1998, p. 176; arXiv:quant-ph/9611025 and arXiv:quantph/9906129 10. A. Yu. Kitaev, "Quantum error correction with imperfect gates," in: O. Hirota, A. S. Holevo, and C. M. Caves, eds., Quantum Communication, Computing, and Measurement, New York: Plenum Press, 1997, p. 181. 11. E. Knill, R. Laflamme, and W. Zurek, "Resilient quantum computation: Error models and thresholds," Proc. Royal Soc. London A 454, 365 (1998); arXiv: quant-ph/9702058 12. E. Knill, "Quantum computing," Nature 463,441 (2010). 13. P. W. Shor, "Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer," in: Proc. 35th Annual Symp. Found. Computer Sci. (1994); arXiv:quant-ph/9508027

State of the Art and Prospects for Quantum Computing

283

14. L. M. K. Vandersypen, M. Steffen, G. Breyta, C. S. Yannoni, M. H. Sherwood, and I. L. Chuang, "Experimental realization of Shor's quantum factoring algorithm using nuclear magnetic resonance," Nature 414, 883 (2001). 15. B. P. Lanyon, T. J. Weinhold, N. K. Langford, et al, "Experimental demonstration of a compiled version of Shor's algorithm with quantum entanglement," Phys. Rev. Lett. 99, 250505 (2007). 16. E. Lucero, R. Barends, Y. Chen, et al, "Computing prime factors with a Josephson phase qubit quantum processor," Nature Phys. 8, 719 (2012). 17. D. Beckman, A. Chari, S. Devabhaktuni, and J. Preskill, "Efficient networks for quantum factoring," Phys. Rev. A 54, 1034 (1996); arXiv:quant-ph/ 9602016 18. E. Martin-López, A. Laing, T. Lawson, R. Alvarez, X.-Q. Zhou, and J. L. O'Brien, "Experimental realization of Shor's quantum factoring algorithm using qubit recycling," Nature Photonics 6, 773 (2012); arXiv:l 111.4147 (2011) 19. M. I. Dyakonov, "Quantum computing: a view from the enemy camp," in: S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics. The Nano Millennium, New York: Wiley, 2002, p. 307; arXiv:cond-mat/ 0110326 20. N. C. Menicucci and C. M. Caves, "Local realistic model for the dynamics of bulk-ensemble NMR information processing," Phys. Rev. Lett. 88, 167901 (2002). 21. P. Schindler, J. T. Barreiro, T. Monz, et al, "Experimental repetitive quantum error correction," Science 332, 1059 (2011). 22. M. D. Reed, L. DiCarlo, S. E. Nigg, et al, "Realization of three-qubit quantum error correction with superconducting circuits," Nature 482, 382 (2012); arXiv:l 109.4948 (2011) 23. X.-C. Yao, T.-X. Wang, H.-Z. Chen, et al, "Experimental demonstration of topological error correction," Nature 482, 489 (2012); arXiv: 1202.5459 24. R. Raussendorf and H. J. Briegel, "A one-way quantum computer," Phys. Rev. Lett. 86, 5188(2001). 25. E. Dennis, A. Landahl, A. Kitaev, and J. Preskill, "Topological quantum memory," J. Math. Phys. 43, 4452 (2002). 26. S. Bravyi, "Universal quantum computation with the v = 5/2 fractional quantum Hall state," Phys. Rev. A 73, 042313 (2006); arXiv:quant-ph/ 0511178 27. F. Wilczek, ed., Fractional Statistics andAnyon Superconductivity, Singapore: World Scientific, 1990. 28. A. Yu. Kitaev, "Fault-tolerant quantum computation by anyons," Annals Phys. 303, 2 (2003); arXiv:quant-ph/9707021 29. F. Wilczek. "Majorana returns," Nature Physics 5, 614 (2009). 30. J. E. Moore, "The birth of topological insulators," Nature 464, 194 (2010). 31. Many publications were devoted to the study of different noise models in the context of quantum error correction, see Ref. 32 for a review, and it was

284

32. 33. 34.

35.

36.

37.

38. 39.

40.

41.

Future Trends in Microelectronics shown that assumption 2 can be somewhat relaxed by allowing for certain types of noise correlations. D. Staudt, "The role of correlated noise in quantum computing," arXiv:111 1.1417 (2011). J. Preskill, "Reliable quantum computers," Proc. Roy. Soc. London A 454, 469 (1998); arXiv:quant-ph/9705031, which claims: "In principle, systematic errors can be understood and eliminated." There is not and never will be a single device dealing with continuous quantities that makes zero systematic errors. Moreover, for reasons that are not yet well understood, all electronic devices, even the most precise that we have, the atomic clock, suffer from the so-called flicker or 1//" noise. The parameters of the device slowly but chaotically change in time, and the longer we wait the more changes we see. J. Preskill, "Fault-tolerant quantum computation," chapter in: H.-K. Lo, S. Popescu, and T. P. Spiller, eds., Introduction to Quantum Computation, Singapore: World Scientific, 1998; arXiv:quant-ph/9712048: "Future quantum engineer will face the challenge of designing devices such that qubits in the same block are very well isolated from one another." Before designing devices, the future engineer would like to know how well the qubits should be isolated, but no indications will be found in the existing literature. M. I. Dyakonov, "Is fault-tolerant quantum computation really possible?" chapter in: S. Luryi, J. M. Xu, and A. Zaslavsky, eds., Future Trends in Microelectronics: Up the Nano Creek, New York: Wiley, 2007; arXiv:quantph/0610117 It is possible that Axiom 1 does not apply to one of the Everett's many worlds. There will probably be no problem in building a quantum computer in that world. By the way, David Deutsch, the father of quantum computer, is an active proponent of Everett's many worlds interpretation. H. Everett, "Relative state formulation of quantum mechanics," Rev. Mod. Phys. 29,454(1957). The image in Fig. 2 is a source of the commonly accepted idea that the quantum computer will be able to do everything that a classical digital computer does, it suffices to use |0) and |1) states as classical bits and abstain from using their superpositions. Theoretically, this may be true. However, if such a device is based on microscopic two-level systems, it will be an analog machine with all the consequences. Why not build this classical limit of a quantum computer with quantum dots or trapped ions and see whether it works? This should be infinitely easier than building a true quantum computer. Due to the required massive parallelism, thousands of gates, which in practice are electromagnetic pulses, will be applied simultaneously, so that the quantum computer will resemble a huge microwave oven. It will be a real challenge to exclude the unwanted action of gates on other qubits. M. C. Gutzwiller, Chaos in Classical and Quantum Mechanics, New York: Springer, 1990.

State of the Art and Prospects for Quantum Computing

285

42. To put it bluntly, one should refrain from proving theorems about systems and phenomena of which one has no profound understanding. 43. Jaroslav Hašek, The Fateful Adventures of the Good Soldier Švejk During the World War, transl. by Z. K. Sadlon, SAMIZDAT, 2007; amazon.com/FatefulAdventures-Soldier-Svejk-During/dp/1585004286 44. S. Banach and A. Tarski, "Sur la decomposition des ensembles de points en parties respectivement congruents," Fundamenta Mathematicae 6, 244 (1924). 45. Seewww.wikipedia.org/wiki/Banach_Tarski 46. P. Aliferis, D. Gottesman, and J. Preskill, "Accuracy threshold for postselected quantum computation," Quantum Inf. Comput. 8, 181 (2008); arXiv:quantph/0703264 47. D. Aharonov, "Quantum computation," in: D. Stauffer, ed., Annual Reviews of Computational Physics, Vol. VI, Singapore: World Scientific, 1999, p. 259; arXiv:quant-ph/981203 48. J. Preskill, "Quantum computing: Pro and con," Proc. Roy. Soc. London A 454, 469 (1998); arXiv:quant-ph/9705032 49. This is exactly what is being told to the general public even today. 50. Quantum algorithms that provide (with an ideal quantum computer!) only polynomial speed-up compared to digital computing, like the Grover algorithm, became obsolete due to the polynomial slow-down imposed by error correction. 51. R. P. Feynman, "Simulating physics with computers," Intern. J. Theor. Phys. 21, 467 (1982); "Quantum mechanical computers," Found. Phys. 16, 507 (1986). 52. D. J. Bernstein, "Introduction to post-quantum cryptography," chapter in: D. J. Bernstein, J. Buchmann, E. Dahmen, eds., Post-Quantum Cryptography, Berlin: Springer, 2009. 53. S. Lloyd, "Universal quantum simulators," Science 273, 1073 (1996). 54. K. L. Brown, W. J. Munro, and V. M. Kendon, "Using quantum computers for quantum simulation," Entropy 12, 2268 (2010); arXiv: 1004.5528 55. When a spin relaxation time of 10 ns is measured, instead of 1 ns previously, this is heralded as another breakthrough on the way to quantum computing. 56. D. Deutsch, "Quantum theory, the Church-Turing principle and the universal quantum computer," Proc. Royal Soc. London A 400, 97 (1985). 57. Nasreddin Hodja was a populist philosopher and wise man believed to have lived around 13th century during the Seljuq dynasty and remembered for his funny stories and anecdotes. According to Wikipedia, the International Nasreddin Hodja festival is celebrated annually in July in Aksehir, Turkey. 58. This kind of reasoning is quite common in our days: "Because there are no known fundamental obstacles to such scalability, it has been suggested that failure to achieve it would reveal new physics."12

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Wireless, Implantable Neuroprostheses: Applying Advanced Technology to Untether the Mind D. A. Borton and A. V. Nurmikko School of Engineering, Brown University, Providence, RI02912, USA

1.

Introduction

The average neuron in the human brain maintains roughly 7,000 synapses1 and rests among 100 billion co-inhabitants. Neurons communicate with each other over synaptic links, which help them accomplish tasks not only in their immediate cortical neighborhoods, but also across the vast landscapes of the nervous system to control, for example, a toe. The dynamics of the 1.3 liters of semi-transparent neuronal goo consisting of a quadrillion interconnections are exceedingly complex. How do we observe these dynamics? How much can we expect to "hear"? How does one neuron affect the entire system? With such a complicated, interwoven system comes the potential for serious communication failure. Neuromotor disease and stroke affect the lives of millions of people worldwide. In severe cases, such as the locked-in syndrome, a completely functional central nervous system is disconnected from a completely functional body. The birth of the neuroprosthetics field came from the idea of "unlocking" this state by building devices to bridge the nervous system gap, detecting individual thoughts and translating them into actions. Recent success in first human clinical trials2-5 has highlighted how accessing the human motor cortex by intra-cortical multielectrode array (MEA) implants6'7 provides important clues to the function of the cortex and the underlying neural communication codes.8"14 Early prosthetics research focused on demonstrating that recordings from an intact brain can enable people to regain the ability to communicate and control their environment through assistive devices. In addition, pilot studies have added much insight into how one must engineer neural sensors to interface with the brain's biological system environment.15-22 The aim of this chapter is to describe how neuroengineers have surmounted many of the challenges to the development of a versatile, implantable, low-power and mobile neural interfaces and to highlight the recent history, current trends, research opportunities, and contemporary challenges in a young, but rapidly-evolving field.

2.

Context and motivation

Much as small advances in the fundamentals of basic physics enabled quantum leaps in our understanding of the universe, evolutionary developments of new 286

Wireless, Implantable Neuroprostheses

287

biomedical technologies unveil new challenges as well as opportunities for innovation in medical care. Before Albert Hyman's description of the artificial pacemaker in 1932, people with severe bradycardia and heart block were simply told that their hearts may fail and that their lifespans were limited. Now, millions of people across the world are alive and healthy with an implanted biomedical device pacing their heart. Before the development of the cochlear implant in 1978, 230,000 people with damaged cochlear hair cells had severe and incurable hearing loss. Now, ever-advancing biomedical implants help those persons re-experience sound. These advances not only addressed a clear clinical need, but they signaled a leap in the interfacing of modern microelectronic devices with the human body. We as a community are on the brink of making such technological discoveries, changing the course of brain-body interfaces. The brain is a very complicated and interwoven computing machine. To give a rough perspective on power consumption, the human brain, a highly distributed, parallel, and hierarchal biological computer, is composed of about 1011 neural cells, which for computational purposes one can equate to "transistors". Details of the local brain microcircuitry vary widely from region to region, but one universal feature of this 3D ULSI design is the large number of interconnects between neurons, each plastic in nature, operating a uniquely complex "software" neural code. Arithmetically, this is equivalent to petaflop computational rates even though the speed of individual communication is on the order of milliseconds (or at kHz frequencies). Perhaps most impressive is that all of this is accomplished with total power consumption of roughly 20% of the body's resting energy consumption (-23.3 W), on the order of a laptop computer23 and comparable to a dim light bulb (ironically, we iconify ideas as a bright light bulb ...). Not only does the brain operate efficiently, but it also transmits astonishing amounts of data between the neural superhighways, or synapses. While individual point-to-point communication occurs on the ms time scale, many other more slowly changing signals, superimposed across vast regions of neural tissue, also contain useful information. One can ask whether recording from 1000, 10,000, 100,000, or more neurons may improve the decoding (or encoding) performance. Until we develop the ability to actually record from orders of magnitude more neurons (and maybe eventually all 100 billion) in the brain, we may ask if there are simpler surrogates that meaningfully convey a partial summary of the spiking activity of these neurons. The point should be made that, in contrast to contemporary implantable technologies like pacemakers, neural stimulators, and cochlear implants, the amount of continuous data a wireless neurosensor implant must transmit from the brain is orders of magnitude higher.20'24 The higher data rate and requirements for ultra low-power systems have driven implantable device innovations discussed in this chapter. Innovation has not only occurred in neural recording and simulation technologies, but also prosthetic effectors. These range from prosthetic limbs for manipulation of the outside world (see Fig. 1) to computer user interfaces for communication.25 Most recently, a locked-in patient was able to control on her

288

Future Trends in Microelectronics

Figure 1. Robotic prosthetics developed around the world.

own volition a prosthetic limb, bringing her favorite beverage (coffee) to her mouth for a sip, a powerful gesture for both patient and researcher.3 Extraordinary microelectronic technologies for acquiring and processing neural data have been developed and deployed in conjunction with percutaneous skull-mounted modules in non-human primates, including relatively compact active neurosensors,15'22,26"30 powerful digital signal processors,21'31'32 and radiofrequency transmitters.16'26'33 In addition, a new technique of using light to perturb neural state has recently emerged, bringing new technological innovations and challenges. We report here on technological advances that allow the emergence of a truly implantable, chronically usable, and mobile neuroprosthetic system, ultimately enabling the untethering of the locked-in mind.

3.

Listening to the brain: Sensing dynamic changes in neural activity "Clocks tick, bridges and skyscrapers vibrate, neuronal networks oscillate.,S4

Ongoing multiscale and multimodal brain-sensing research offers tantalizing hints as to the importance of accessing cortical circuits at individual neuron resolution12'35'36 and its use in rehabilitative technology.37 Presently, these technologies are cumbersome, percutaneous, and limited in their scalability for larger cortical coverage. Advances in understanding the brain and its constituent units could not have come about without coincident advances in technology to probe the nervous system. There are multiple electrical and chemical neural signal modalities that convey useful information about the nervous system. These signal modalities span many temporal and spatial scales. As described above, these

Wireless, Implantable Neuroprostheses

289

signals contain unique information about neural processing. Unfortunately, no single signal recording modality can "listen" across this extremely wide spatial and temporal scale. Several neural interfaces, or probes, have been developed over the last century and are used today to understand the brain. Microelectrode arrays composed of bundles of wires or so-called "microwire arrays" have been now largely replaced by "monolithic" arrays for work in primates38^0 (monkeys, and now in first human trials). Of these, we mention the Si-based arrays where lithographic and electrochemical techniques are combined to fabricate tapered microscale beds of needles.6'7'41 For example, in the so-called "Utah" microelectrode array (now fabricated commercially by Blackrock Microsystems, based in Utah), Pt or Pt/Ir coats each approximately pyramidal 1-2 mm long electrode, with its p-S\ shank insulated by biocompatible Parylene-C, at its tip. The heavily doped Si provides a low-loss conducting path onto the planar support substrate wherefrom a wire-bonded bundle (for a 100-element electrode array, 100 nylon-insulated 1 mil Au wires) transports the recorded neural signals through the skull and the skin to exterior electronics. Operationally, specialized neurosurgical techniques are employed to access cortical areas of interest with the arrays inserted to the brain typically using calibrated pneumatic single-tap impactors.42 The fabrication of this type of intracortical microelectrode structure has now been advanced to wafer scale processing, so that the physical length of the microelectrodes can, in concept, be graded in a controlled fashion and mass fabrication becomes possible.

Figure 2. Passive neural interface (left) and active neural interface (right). Active components enable drastic reduction in implant size as well as fully implantable data and power telemetry.

290

Future Trends in Microelectronics

Microelectrode arrays are among a host of neural activity-sensing probes, each with their specific field potentials representing the spatial average of the electrical potentials generated by a large population of neurons. The subthreshold (analog, transmembrane currents) and suprathreshold (discrete spikes) electrical activity of a many neurons generates current sinks and sources at different points in the cortex and subsequent potential changes near the electrode. These signals are used in both basic neuroscience and state-of-the-art neuroprosthetics as control inputs. Thus, neural interface systems, at least for the foreseeable future, need to consider a broad band of signals that may be useful to extract command signals. Why do these various dynamic potentials emerge? The generators of these non-spike fields are transmembrane currents arising from changes in the endogenous neurotransmitter concentration (glutamate, dopamine, serotonin, etc.) at the synapses, which modify the amount of current flow and thus the surrounding electric field. These changes can be recorded extracellularly and, following the superposition principle, are summed across many neurons. This sum is referred to as the field potential. Some of these field potentials are oscillatory in nature, which may emerge either from the neural circuit itself or the biophysics of membranes.43 Importantly, some of these field potentials may be symptoms of a broader computational system, while others may be the actual computations themselves.44 Examples of microelectronic devices we have developed to sense, digitize, and transmit these broadband signals are shown in Fig. 2. The custom operational transconductance amplifier array18 multiplexes and amplifies the voltage changes at the tip of the MEA with an RMS noise value of - 4 uV. Data are then digitized using analog-to-digital converters and passed to the output telemetry system. Lowpower, long-range data transmission at very high bit-rates is a key technology necessary for broadband neural data. The RF transmitter is implemented as a monolithic microchip in a state-of-art BiCMOS process, achieving up to 100 Mb/s transmitting data rate and 35% overall power efficiency when 4 mW output power is delivered. For better bit error rate (BER) performance, binary phase shift keying (BPSK) modulation scheme is adopted. The whole transmitter, including a wide tuning-range voltage controlled oscillator (VCO), a wideband BPSK up-conversion mixer, and a high-efficiency power amplifier operates on a 3 V supply. The frequency tuning range of VCO is 3-4 GHz, enabling the flexibility to choose a "proper" carrier frequency according to the wireless. The simulated power consumption of the whole transmitter is typically below 12 mW, and the estimated chip area is 2x2 mm. For comparison, our earlier RF transmitter designs consumed -50 mW. An ASIC controller chip injects a synchronization word in the data stream before it is sent to the transmitter for parity. The complete microsystem, shown in Fig. 3, is hermetically sealed in grade-2 titanium with a single-crystal sapphire window for electromagnetic transparency. When running, the implanted device consumes -100 mW, fueled by a medical grade rechargeable 200 mAh Liion battery (Quallion). Recharging is accomplished through the skin by inductive coupling with an external primary coil. The implantable neural interface has been evaluated in swine and non-human primates for over one year of use, indicating the exciting possibility of its use in humans for prosthetic control.

Wireless, Tmplantable Neuroprostheses

291

Figure 3. A chronically implanted, wireless neural interface (a) together with an exploded view of the device (b); x-ray images of implanted neural interfaces (c) in swine (top) and non-human primates (bottom); a concept of a human implant, to scale (d).

Recently, researchers at Brown University and Mass General Hospital in Boston have shown the ability of a paralyzed individual to drink a cup of coffee on her own volition.3 Signals from her motor cortex were sensed by a passive (percutaneous) microelectrode array (developed nearly 10 years ago), interpreted on a desktop computer with a trained linear Kalman filter, and finally used to command a robotic arm developed by the German space agency (DLR). This feat not only represents an impressive advance in neurotechnology, but also promises fully implantable devices - see Fig. 3 - allowing safer and more mobile operation of prosthetic control in the near future. Future "brain-prosthesis" interfaces may not be limited to external robotic control. Many researchers around the globe are working to deliver electrical stimulation to remaining muscle and nerve fibers to enable control of one's own limb again. For example, one group has made extensive progress in the development of externally-controlled spinal interfaces for persons with spinal cord

292

Future Trends in Microelectronics

injury, with current work focusing on a "brain-spine" interface for locomotor rehabilitation.37 Another exciting use of broadband intracortical sensing technology has been in the diagnosis of neurological disease, with researchers beginning to uncover the underlying dynamics of neural activity in epilepsy.35 Wirelessly collected cognitive information, such as that shown in Fig. 4 from our neural interfaces, will not only significantly expand the clinical application space, but will also allow for mobile operation of prosthetics - a feature especially important for amputees. Mobile data transfer brings along with it concerns of security, or "neuro-security". Just as packets of data on the internet can be "sniffed" and decrypted for their content, neural information leaving the brain of a cortical implant recipient could be intercepted and used for other purposes. While we have taken early steps to encrypt data transferred over wireless communication methods, efforts should continue in the field to define the best methods (and regulation) of sensitive information generation and transfer from our minds. A major challenge to all researchers attempting to create compact, subcutaneous, active chronic implantable neural sensors is the electrical isolation, or packaging of the microsystem. It was learned early onfromthe development of the first commercial pacemakers, that reliable packaging of fully implantable biomedical devices is critical to their success. Even state-of-the-art biocompatible polymeric insulation processes offer erratic long-term reliability against the wet, ion-rich, and warm interior of the human body. Hence, most packaging schemes for chronic applications have been limited to solid titanium hermetic packages or equally rigid ceramics (as we have used above). However, this type of packaging

Figure 4. Wirelessly recorded neural data from non-human primates during natural behavior: (a) diagram of recording setup; (b) single-channel extracted waveforms, (c) extracted waveforms over the entire microelectrode array, and (d) raster plot of action potential timestamps.

Wireless, Implantable Neuroprostheses

293

has a limited future as next generation implantable brain-interface devices continue to increase in functionality, number of components and sensors, while requiring smaller footprints, e.g. for placement in the subcutaneous spaces available in the head. For these chronic implantable devices, a new type of packagmg scheme using thin flexible materials is necessary. However, developing such a chronic, impermeable, and biocompatible thin-film protection layer against, for example, electric field induced ion transport is a tall order, especially since ionic transport mechanisms alone in polymeric insulators are not well known. Here, neuroengineers are taking a lesson from the microelectronic packaging industry and exploring the use of combinations of organic and inorganic thin film multilayers for flexible, chronic electrical isolation. We are currently exploring the adaptation to neural interface implants of a recently developed PDMS/Si0 2 nanocomposite packaging material. The thin conformal films are deposited via PECVD from a HMDSO and 0 2 plasma mixture. The deposited materials have been reported to provide a reliable hermetic permeation barrier for highly water sensitive OLEDs.45 The films deposited by this process are a heterogeneous micro/nanoscale mixture composed of SÍO2 and silicone, where networked SÍO2 is seen as important for successfully blocking diffusion paths within the silicone. It has been reported through infrared absorption techniques, wetting angle measurements, and indentation hardness experiments that these films are uniform on the macroscale. In addition to the permeation barrier properties, the films are highly flexible and have been reported to remain intact over 58,600 bending cycles. This is an extremely promising microelectronic packaging technique for implantable devices, the application of which to neural interfaces may be a key enabler for future integrated, active, and flexible devices. 4.

The write operation: Perturbing the brain with light

Targeted spatiotemporal access to neural populations at single neuron resolution is important to the study of neural circuits and cellular conditions, both for basic understanding of their functions as well as developing diagnosis and treatment approaches to many classes of neurological disorders. Modulating neural circuitry by intracortical electrical stimulation is a well-established tool in electrophysiology and clinical neurosurgery, even if uncertainties are inherently present, given such non-selective activation of cells by the complex patterns of current flow. In a broader context, the utility of external neuromodulation methods are made complicated by the nonspecific nature associated with electrical, magnetic and pharmacological targeting. Nonetheless, electrical stimulation has been used to outstanding effect first in pacemakers (1920's), then cochlear implants (1970's), and, more recently, in deep brain stimulators for treatment of the symptoms in Parkinson's disease. Worldwide, companies such as Medtronic have implanted over 4 million electrical pacing devices. A new approach to neural modulation has recently blossomed with the discovery of a light-sensitive ion channel, Channelrhodopsin-2 (ChR2),46 followed

294

Future Trends in Microelectronics

by the discovery of an optically activated chloride pump, Halorhodopsin (NpHR), and a proton pump, Archaerhodopsin (Arch).48 This "optogenetic" combination of methods led to rapid advances in targeting neurons in mammalian animal models. Light-induced modulation enables both neuronal excitation and inhibition, each for inducing well-defined neuronal events with ms time resolution. Among the practical advantages of optical stimulation over electrical stimulation, the optical method has minimal instrumental interference with simultaneous electrophysiological recording techniques. Furthermore, the method is technically scalable for accessing potentially multiple target areas for controllable spatiotemporal modulation across the cortex and deeper brain structures. To advance such prospects, development of "dual-function" chronically implanted devices for simultaneous light delivery and electrophysiological recording is needed. For localized light delivery, glass optical fibers have seen wide use in optogenetics to date, given their abundant commercial availability as flexible (though fragile) low-loss optical waveguides. In addition, an implanted optical fiber allows in vivo fluorescence detection in the intact brain for minimally invasive assessment of local opsin expression.49 So far, recording of optically evoked neural activity in vivo for rodent and non-human primate models has been mainly limited to the use of individual extracellular electrodes adhesively attached in parallel to the optical fiber. We have successfully implanted and tested a polymer optical fibermicroelectrode integrated array device50 (POF-MEA) into the arm/hand area of primary motor cortex in a rhesus macaque. The device was implanted immediately following injections with the AAV5-CAMK2-ClVl-eYFP viral construct (packaged viruses provided by colleagues at Stanford University). The C1V1 is a mutant protein of the ChR2 with slightly faster kinematics and heightened sensitivity to photon excitation. The POF-MEA device was based on a 10x10 Blackrock Microsystems array with the center electrode replaced by a tapered optical fiber. Thus, we are able to deliver light at one specific target in the cortex while performing electrophysiology at dozens of surrounding sites and monitor the resulting effects of optogenetic stimulation on population-level neural activity and network patterns. Using the device we have recorded more than 100 well-isolated individual neurons surrounding the optic fiber, a shown in Fig. 5. Ten days after the implant surgery we identified neurons with clear response to laser stimulation, confirming successful viral transfection. The unique capabilities of the chronic POF-MEA device will allow researchers to monitor the increase of light-induced neural responses in as a function of time, tracking the opsin expression across the cortical surface. In addition, because stimulation with light does not cause electrical artifacts (as electrical stimulation most certainly does), we are able to observe neural activity during stimulation. The POF-MEA further enables observation of the population-level neural network as it is perturbed by the stimulation - dynamics never before seen with such resolution. One very interesting (if not surprising) result of optical stimulation in nonhuman primates is the lack of muscle twitch as seen quite obviously during electrical stimulation of motor cortex. Optical stimulation is in fact very precisely

Wireless, Implantable Neuroprostheses

295

exciting neurons expressing the appropriate opsins (measured electrophysiologically). This apparent dichotomy has caused researchers in the field to appreciate the subtlety that optogenetics affords us: we now have a tool to locally excite (or inhibit) specific neurons or networks. It is clear that such a tool has and will continue to help researchers tease apart fine mechanisms of disease and

Figure 5. Optrode and optical-MEA for analysis of light stimulation effects on neural activity: (a-d) fabrication and optical verification of device; (e) single channel recording during light stimulation in non-human primate motor cortex; (f) implantation of optical-MEA and (g) responsive neurons (gray) to optical stimulation at insertion site (star). Adapted from Ref. 50.

296

Future Trends in Microelectronics

Figure 6. Transformation towards patient mobility and autonomy: current BrainGate neuro-sensing platform for locked-in patients (left) vs. the neural interface of the future (right). The future interface would be implanted completely under the skin of the patient and would send high-fidelity wireless data to a researcher or primary care physician, leaving the patient untethered and mobile.

dysfunction in the nervous system. It is the authors' opinion that this technique will very soon lead to profound observations in neural dynamics and, perhaps more importantly, paradigm-shifting treatments to neurological disease and disorder. 5. Summary As illustrated in the rest of this book, microelectronic innovation continues to bring new devices to both simplify and enrich our everyday lives. Microelectronics has played a significant role in simplifying medicine and making hospital care more efficient and effective. We can now, for example, diagnose many diseases by placing a droplet of blood on microfluidic channels with nanoscale sensors determining partial compositions of cell types and proteins. However, we have yet to see "smart" electronics in the form of implantable devices and interfaces to the human mind - but the prospects look bright, as shown in Fig. 6. Future microelectronic innovation and discovery can (and we contend, will) provide researchers working at the boundary of neuroscience, neurology, and neurotechnology, the tools necessary for advancing neuro-critical care. Boundless opportunity awaits researchers, patients, and even society as we begin to unlock and understand the function of what we carry on our shoulders. Acknowledgments This work was supported in part by the National Institute of Health (NIBIB and NCMRR/NICHD, 1R01EB007401-01), the NSF EFRI program (#0937848), and the DARPA Repair Program (contract N66001-10-C-2010).

Wireless, Implantable Neuroprostheses

297

References 1. 2.

3. 4. 5. 6. 7. 8. 9.

10. 11. 12. 13. 14. 15. 16.

D. A. Drachman, "Do we have brain to spare?" Neurology 64,2004 (2005). J. D. Simeral, S.-P. Kim, M. J. Black, J. P. Donoghue, and L. R. Hochberg, "Neural control of cursor trajectory and click by a human with tetraplegia 1000 days after implant of an intracortical microelectrode array," J. Neural Eng. 8, 025027(2011). L. R. Hochberg, D. Bacher, B. Jarosiewicz, et al., "Reach and grasp by people with tetraplegia using a neurally controlled robotic arm," Nature 485, 372 (2012). V. A. Zerris, J. D. Donoghue, L. R. Hochberg, D. K. O'Rourke, and E. A. Chiocca, "BrainGate: Turning thought into action- first experience with a human neuromotor prosthesis," Neurosurgery 57, 425 (2005). L. R. Hochberg, M. D. Serruya, G. M. Friehs, et al., "Neuronal ensemble control of prosthetic devices by a human with tetraplegia," Nature 442, 164 (2006). K. E. Jones, P. K. Campbell, and R. A. Normann, "A glass/silicon composite intracortical electrode array," Ann. Biomed. Eng. 20,423 (1992). C. Nordhausen, E. Maynard, and R. A. Normann, "Single unit recording capabilities of a 100 microelectrode array," Brain Res. 726, 129 (1996). P. J. Rousche and R. A. Normann, "Chronic recording capability of the Utah intracortical electrode array in cat sensory cortex," J. Neurosci. Methods 82, 1 (1998). A. K. Bansal, C. E. Vargas-Irwin, W. Truccolo, and J. P. Donoghue, "Relationships among low-frequency local field potentials, spiking activity, and three-dimensional reach and grasp kinematics in primary motor and ventral premotor cortices," J. Neurophysiol. 105, 1603 (2011). C. E. Vargas-Irwin, G. Shakhnarovich, P. Yadollahpour, J. M. K. Mislow, M. J. Black, and J. P. Donoghue, "Decoding complete reach and grasp actions from local primary motor cortex populations," J. Neurosci. 30, 9659 (2010). J.D. Long and J.M. Carmena, "A Statistical Description of Neural Ensemble Dynamics." Front Comput Neurosci 5, 52 (2011) A. Afshar, G. Santhanam, B. M. Yu, S. I. Ryu, M. Sahani, and K. V. Shenoy, "Single-trial neural correlates of arm movement preparation," Neuron 71, 555 (2011). M. Nicolelis, D. Dimitrov, J. Carmena, and R. Crist, "Chronic, multisite, multielectrode recordings in macaque monkeys" PNAS100, 11041 (2003). S. M. Chase, R. E. Kass, and A. B. Schwartz, "Behavioral and neural correlates of visuomotor adaptation observed through a brain-computer interface in primary motor cortex," J. Neurophysiol. 108, 624 (2012). R. R. Harrison, R. J. Kier, C. A. Chestek, et al., "Wireless neural recording with single low-power integrated circuit," IEEE Trans. Neural. Syst. Rehabil. Eng. 17, 322 (2009). H. Miranda, V. Gilja, C. A. Chestek, K. V. Shenoy, and T. H. Meng, "HermesD: A high-rate long-range wireless transmission system for simultaneous multichannel neural recording applications," IEEE Trans. Biomed. Circuits. Syst. 4, 181 (2010).

298

Future Trends in Microelectronics

17. D. Kipke, J. Williams, J. Hetke, J. Henderson, and C. Garell, "Intracranial neural interface system," US patent no. 7979105 (2011). 18. Y.-K. Song, D. A. Borton, S. Park, et al, "Active microelectronic neurosensor arrays for implantable brain communication interfaces," IEEE Trans. Neural. Syst. Rehabil. Eng. 17, 339 (2009). 19. D. A. Borton, M. Yin, J. Aceros, et al, "Developing implantable neuroprosthetics: A new model in pig," Conf. Proc. IEEE Eng. Med. Biol Soc. (2011), pp. 3024-30. 20. A. V. Nurmikko, J. P. Donoghue, L. R. Hochberg, et al, "Listening to brain microcircuits for interfacing with external world - Progress in wireless implantable microelectronic neuroengineering devices," Proc. IEEE 98, 375 (2010). 21. M. Rizk, I. Obeid, S. H. Callender, and P. D. Wolf, "A single-chip signal processing and telemetry engine for an implantable 96-channel neural data acquisition system," J. Neural Eng. 4, 309 (2007). 22. P. Afshar, D. Moran, A. Rouse, X. Wei, and T. Denison, "Validation of chronic implantable neural sensing technology using electrocorticographic (ECoG) based brain machine interfaces," Intern. IEEE EMBS Conf. Neural Eng. 2011), pp. 704-707. 23. A. Mahesri and V. Vardhan, "Power consumption breakdown on a modern laptop," Lecture Notes Comp. Sci. 3471, 165 (2005). 24. B. S. Wilson, C. C. Finley, D. T. Lawson, R. D. Wolford, D. K. Eddington, and W. N. Rabinowitz, "Better speech recognition with cochlear implants," Nature 352, 236 (1991). 25. K. Tringale, D. Bacher, and L. R. Hochberg, "Towards the optimal design of an assistive communication interface with neural input," in: 38th Annual Northeast Bioengineering Conference (NEBEC) (2012), pp. 197-198. 26. H. Miranda and T. H. Meng, "A programmable pulse UWB transmitter with 34% energy efficiency for multichannel neuro-recording systems," Proc. Custom Integr. Circuits Conf. (2010), art. no. 5617608. 27. T. Denison, K. Consoer, W. Santa, A.-T. Avestruz, J. Cooley, and A. Kelly, "A 2 uW, 100 nV/Vl·lz chopper-stabilized instrumentation amplifier for chronic measurement of neural field potentials," IEEE J. Solid-State Circ. 42, 2934 (2007). 28. T. Denison, W. Santa, R. Jensen, D. Carlson, G. Molnar, and A.-T. Avestruz, "An 8 uW heterodyning chopper amplifier for direct extraction of 2 |iV RMS neuronal biomarkers," Tech. Dig. ISSCC (2008), pp. 162-163. 29. R. R. Harrison and C. Charles, "A low-power low-noise CMOS amplifier for neural recording applications," IEEEJ. Solid-State Circ. 38, 958 (2003). 30. W. R. Patterson, Y.-K. Song, C. W. Bull, et al, "A microelectrode/ microelectronic hybrid device for brain implantable neuroprosthesis applications," IEEE Trans. Biomed. Eng. 51, 1845 (2004). 31. M. S. Chae, Z. Yang, M. R. Yuce, L. Hoang, and W. Liu, "A 128-channel 6 mW wireless neural recording IC with spike feature extraction and UWB transmitter," IEEE Trans. Neural. Syst. Rehabil. Eng. 17, 312 (2009). 32. M. Yin and M. Ghovanloo, "Using pulse width modulation for wireless transmission of neural signals in multichannel neural recording systems," IEEE Trans. Neural. Syst. Rehabil. Eng. 17, 354 (2009).

Wireless, Implantable Neuroprostheses

299

33. M. Yin and M. Ghovanloo, "A clockless ultra-low-noise low-power wireless implantable neural recording system," Proc. IEEE Inter. Symp. Circ. Syst. (2008), pp. 1756-59. 34. G. Buzsàki and A. Draguhn, "Neuronal oscillations in cortical networks," Science 304, 1926(2004). 35. W. Traccolo, J. P. Donoghue, L. R. Hochberg, et al, "Single-neuron dynamics in human focal epilepsy," Nature Neurosci. 14, 635 (2011). 36. M. Velliste, S. Perel, M. C. Spalding, A. S. Whitford, and A. B. Schwartz, "Cortical control of a prosthetic arm for self-feeding," Nature 453, 1098 (2008). 37. R. Van den Brand, J. Heutschi, Q. Barraud, et al, "Restoring voluntary control of locomotion after paralyzing spinal cord injury," Science 336, 1182 (2012). 38. E. M. Schmidt, M. J. Bak, and J. S. Mclntosh, "Long-term chronic recording from cortical neurons," Exper. Neurology 52, 496 (1976). 39. D. R. Humphrey, "A chronically implantable multiple microelectrode system with independent control of electrode positions," EEG Clinical Neurophysiol. 29, 616 (1970) 40. D. R. Humphrey, E. M. Schmidt, and W. D. Thompson, "Predicting measures of motor performance from multiple cortical spike trams," Science 170, 758 (1970). 41. R. A. Normann, "A Penetrating, cortical electrode array: Design considerations" Proc. IEEE Intern. Conf. Syst. Man Cybernetics (1990), pp. 918-920. 42. R. A. Normann, P. J. Rousche, and K. W. Horch, "Impact inserter mechanism for implantation of a biomedical device," US patent no. 5361760 (1994). 43. G. Buzsaki, Rhythms of the Brain, 1st ed., Oxford: Oxford University Press, 2006, p. 464. 44. T. Bullock, "Signals and signs in the nervous system: The dynamic anatomy of electrical activity is probably information-rich," PNAS 94, 1 (1997). 45. P. Mandlik, J. Gartside, L. Han, et al, "A single-layer permeation barrier for organic light-emitting displays," Appl. Phys. Lett. 92, 103309 (2008). 46. G. Nagel, T. Szellas, W. Huhn, et al, "Channelrhodopsin-2, a directly lightgated cation-selective membrane channel," PNAS 100, 13940 (2003). 47. B. Schobert and J. Lanyi, "Halorhodopsin is a light-driven chloride pump," J. Biol Chem. 257, 10306 (1982). 48. B. Y. Chow, X. Han, A. S. Dobry, et al, "High-performance genetically targetable optical neural silencing by light-driven proton pumps," Nature 463, 98 (2010). 49. I. Diester, M.T. Kaufman, M. Mogri, et al., "An optogenetic toolbox designed for primates," Nature Neurosci. 14, 387 (2011). 50. J. Wang, F. Wagner, D. Borton, et al, "Integrated device for combined optical neuromodulation and electrical recording for chronic in vivo applications," J. Neural Eng. 9, 016001 (2011)

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Correlated Electrons: A Platform for Solid State Devices Sieu D. Ha, You Zhou, Rafael Jaramillo, and Shriram Ramanathan Harvard University, Cambridge, MA 02138, U.S.A.

1.

What is a correlated oxide?

Correlated electron materials are those for which the electronic and magnetic properties cannot be described by the Hartree-Fock mean-field approximation. In these cases, the interactions between individual excitations must be explicitly counted in order to understand the material properties. Correlated electron phenomena frequently arise when weakly-interacting electron band theory begins to fail. In electron band theory, each electron (or quasiparticle, more appropriately) in the crystal is treated as an individual particle that moves in a periodic potential independently of other electrons, and the interactions between electrons and between electrons and other excitations (e.g. phonons) are treated in an average way. Within such a model the electronic conductivity is determined by the band filling, and therefore by the electronic configurations of the constituent ions. Sir Neville Mott famously pointed out that this assumption is unphysical in the case of low electron density, and he illustrated his point with the example of a ID periodic chain of hydrogen atoms.1 No matter how far apart the atoms are, the electron band would always be half-filled and therefore metallic according to band theory. This is clearly inconsistent with our intuition that a regular chain of hydrogen atoms cannot conduct electricity for arbitrarily large inter-atomic spacing. Mott, and later Hubbard, argued that the failure of band theory in the case of low electron density results from ignoring the weakly-screened local Coulomb interaction between electrons. Again, using the example of the hydrogen chain, an electron hopping from one atom to another leaves one atom unoccupied and the other doubly occupied. The on-site Coulomb interaction resists this double occupancy and is typically quantified by the so-called Hubbard energy (U). For sufficiently strong UIW, where W is the electronic bandwidth determined by band theory, a single electronic band will split into two, called the lower and upper Hubbard bands (LHB and UHB).2 In this way, a half-filled band, which is expected by band theory to conduct electricity, can split into a full LHB and an empty UHB and therefore become insulating. Thus, by changing the bond lengths in a material we can affect the bandwidth W, and thereby induce an insulator-tometal transition that is controlled by the UIW ratio. Many transition metal oxides (TMOs) exhibit correlated electron behavior and are therefore referred to as "correlated oxides". In a TMO, oxygen has filled the 2p shells and the electrical properties are largely determined by the partially filled 3d-, 300

Correlated Electrons: A Platform for Solid State Devices

301

4f-, or J/-electronic shells on the metal sites. The 3c/-orbitals in particular are tightly bound to their metal ion, and this confinement is usually the root cause of correlated behavior. Besides the effects of electron correlation the local crystal environment can split the 3d orbitals, resulting for example in the e% and f2g representations in the case of octahedral symmetry. Finally, many transition metal ions are magnetic, and therefore intra-site (Hund) and inter-site magnetic interactions can be important. These multiple effects make the metal ion a very busy place and explain why correlated TMOs often have inter-dependent charge, spin, lattice, and orbital degrees of freedom. In the case of a u?-electron ion the Coulomb interaction U can be expressed as the following function of electron occupation: U = E(dn+1) + E(dnA) - 2E(dn), where E(dn) is the total energy for an ion with electron configuration dn. The U expression for 4f-, or 5f- TMOs is similar. In correlated oxides, U ranges from a few eVs to 10 eV, whereas d and/band W ~ 1-2 eV because of the small overlap between d and /orbitals. 2 ' 3 For semiconductors such as Si and Ge, W~ 10-20 eV, much larger than the corresponding U of a few eVs.4'5 This is the reason why electron correlation is usually unimportant in conventional semiconductors. The interdependence of the charge, spin, lattice, and orbital degrees of freedom opens up many possibilities for inducing phase transitions through external perturbations such as stress, temperature, or electromagnetic fields (e.g. Fig. 1). Naturally, the electronic and magnetic properties of correlated TMOs are also strongly variable with substitutional doping. Unlike conventional semiconductors, in which the electronic bandstructure is more-or-less rigid against carrier doping, the electronic structure of correlated oxides often undergoes dramatic changes upon carrier doping; one example is the onset of unconventional superconductivity in response to hole doping in cuprate high-r c super-

Figure 1. Temperature-controlled phase transition in correlated vanadium dioxide from an insulator with monoclinic crystal structure at low temperature to a metal with tetragonal crystal structure at high temperature. This phase transition is accompanied by a dramatic change in resistivity.

Future Trends in Microelectronics

302

conductors. It is this ability to effect dramatic change in material properties through external tuning that we hope to harness in a new generation of electronic devices with unprecedented and/or multiple functionality. 2.

Challenges in materials synthesis

Synthesizing interesting and potentially useful correlated oxide materials is often challenging for many of the same reasons that the materials are interesting in the first place, namely the strong coupling between lattice, orbital, charge, and spin degrees of freedom. Furthermore, for several electronics applications it is necessary to synthesize correlated oxides in thin-film form and in combination with other materials that are chosen as much for their functionality in an eventual device (e.g. a gate dielectric) as for their compatibility with oxide growth. Therefore the thermodynamics, growth kinetics, and possible reconstructions at interfaces are every bit as important as the bulk thermodynamics of the oxide under consideration. Here we illustrate these issues with two examples involving rareearth nickelates of the form RNi0 3 , where R is a lanthanide. The RNi0 3 family of materials exhibits metal-insulator and magnetic transitions that are controlled by the effect of the R3+ ionic radius on the perovskite-derived crystal structure.6 In the case of LaNi0 3 , the crystal structure is rhombohedral (R3c) and bulk LaNi0 3 is a paramagnetic metal at all temperatures. When La3+ are replaced by smaller and heavier lanthanide ions, the crystal structure changes to orthorhombic (Pbnm) and an insulating, antiferromagnetic phase develops at low T. The critical temperatures Tc for the metal-insulator transition (MIT) and for the Néel transition are controlled by the choice of R. In particular, Tc varies from 130 K for PrNi0 3 to 600 K for LuNi0 3 . It is believed that the entire electronic and magnetic phase diagram of the RNi0 3 family can be explained by the changes in the Ni-O-Ni bond angles (9) and the Ni-0 bond lengths (rNi_o) that result from the change in R3+ radius. The variability of Tc is attractive for electronics applications. However, before devices can be engineered and tested, the changes in the electronic phase diagram between bulk ceramics to thin films must be understood. The case of LaNi0 3 is the most thoroughly studied (for reasons we describe below). It is a paramagnetic metal at all T, but experiments show that it is "close" to an insulating state.7'8 This prompts the question of whether an MIT can be driven by an external perturbation, such as epitaxial strain. Like all perovskite-derived correlated oxide materials, LaNi0 3 thin films are usually synthesized by epitaxial growth on another perovskite-derived oxide. In the case of compressive (tensile) strain, the in-plane 6 and rNi.0 both decrease (increase). Since these two terms have opposite effects on the electron hopping integral between Ni es* orbitals, and therefore on the eg* bandwidth W, it is difficult to predict what epitaxial strain will do to the electronic phase diagram. A thorough study including growth, microscopy, diffraction, and electronic and magnetic measurements is needed to clarify the effects of epitaxial strain.

Correlated Electrons: A Platform for Solid State Devices

303

A good example of the complications introduced by epitaxial growth is that of (LaNi03)N/(SrMn03)M superlattices. In bulk form, SrMn03 has an undistorted perovskite structure with no octahedral rotations (9 = 180°), whereas LaNi03 has 6 = 165.2° with an a"a"a" Glazer rotation pattern. Using high resolution x-ray diffraction it was recently shown that coherently strained (LaNi03)N/(SrMn03)M superlattices grown on SrTi03 substrates can induce octahedral rotations in the SrMn03 layers, or suppress the rotation in the LaNi03 layers, depending on the repeat lengths m and n? Furthermore, the same work showed that in superlattices 9(Ni-0-Ni) can increase while rNi.0 decreases, thus producing a more rapid change in the electronic bandwidth than is possible with single layer epitaxy. The optimistic outlook on these results is that superlattice structures enable a higher degree of control over the electronic phase diagram of a potentially useful correlated oxide. At the same time, the strong interplay between epitaxial strain, interfacial reconstruction, and electronic properties probably means that extensive and challenging experiments are required for every new combination of materials before devices can be engineered in a meaningful way. It is worth noting that the experimental procedure of Ref. 9 is, as of the time of writing, only applicable to material systems with cubic symmetry in the plane of growth. It remains to be seen what interfacial reconstructions are realized in the case of epitaxial growth of oxides such as RNi03 (R Ф La) with symmetry lower than rhombohedral. LaNi03 is the only material in the RNi03 family with no metal-insulator transition in bulk form. For R Ф La materials, Tc can be varied from cryogenic to furnace temperatures, thus opening up the prospect of room-temperature electronic switches. In the case of SmNi03, Tc ~ 400 K, making it compatible with CMOS operating temperatures (typically 350 K). Therefore there is growing interest in the synthesis and electronic properties of the R Ф La materials. However, it is thought that LaNi03 is also the only material in the RNi03 family that is thermodynamically stable under ambient conditions. Furthermore, based on the extrapolation of thermodynamic trends from other lanthanide perovskite-derived material families, it has been predicted that all RNi03 with R Ф La are thermodynamically unstable in typical oxide growth conditions of 1100 K and low oxygen pressure.10 Epitaxial growth can be used to stabilize the desired phase, and epitaxial strain can be used to tune the electronic properties.11'12 However it remains to be seen whether single phase thin films can be obtained on non-latticematched substrates, such as Si02 gate dielectrics. 3. High-speed electronic switches A subset of correlated oxides exhibit phase transitions from the insulating to metallic state with external excitation, as noted above.13 This metal-insulator transition (MIT) is accompanied by a resistivity change that can be many orders of magnitude and may be induced with temperature, pressure, magnetic field, or doping. The large resistivity change is suggestive of electronic switching applications. Since the carrier concentrations in the insulating and metallic states

304

Future Trends in Microelectronics

of correlated systems are comparable, the switching process does not require generation and drift of minority carriers, as in field-effect devices. Switching in correlated materials may therefore occur on much faster time scales. Indeed, subpicosecond phase transitions have been demonstrated with femtosecond laser pulses.14 Note also that switching in MIT oxides is an inherent material property and does not depend on specific device architecture. There is currently considerable research effort aimed at implementing correlated MIT oxides in electronic devices, including in our group. With respect to electrical switching, the simplest device architecture is a two-terminal switch in which the oxide is sandwiched between electrodes in a metal-insulator-metal (MIM) structure. Here, we discuss implementations of two-terminal electronic switches utilizing the MIT in correlated oxides. Vanadium dioxide (V0 2 ) is a widely studied MIT material because the transition temperature is above room temperature (340 K), the resistivity change across the MIT is 3-5 orders of magnitude (see Fig. 1), and thin film growth is readily achievable on a variety of substrates. The MIT in V0 2 is also observed electrically in I-V measurements,15 in which a very abrupt increase in current occurs above a critical voltage, as shown in Fig. 2. This threshold electrical switching has been exploited in a number of two-terminal applications. Kim and co-workers examined the varistor aspects of V0 2 for surge and on-chip circuit protection.16 They found that V0 2 thin film varistors have improved surge protection characteristics as compared to powdered ZnO, which is used commercially. V0 2 may also be a useful component for emerging crossbar resistive memory arrays. Crossbar memory with resistive nonvolatile switches is a promising technology for high density universal memory, but parasitic leakage between adjacent cells is a significant problem that can cause bit read errors. Lee and co-workers eliminated read/write errors by introducing a series V0 2 layer in each cell, which reduced leakage currents at low read voltages but still allowed for write operations to occur at high voltages.17 Even with the additional V0 2 layer,

Figure 2. Abrupt current jump in I-V measurement of V0 2 thin film two-terminal device due to metal-insulator phase transition.

Correlated Electrons: A Platform for Solid State Devices

305

write times down to 10 ns were demonstrated. Aside from current blocking and shunting applications, it has been demonstrated that negative differential resistance can occur in V0 2 , which allows for utilization of V0 2 in oscillator devices.18 Without capacitive, inductive, or active circuit elements, a voltage pulse across a two-terminal V0 2 device was shown to induce voltage oscillations across a series resistance with frequencies of nearly 0.5 MHz. Further, V0 2 also shows promising behavior for microwave frequency devices. Crunteanu and co-workers investigated the transmission properties of a two-terminal V0 2 waveguide when switched with an electrical DC bias.19 The device showed very large transmission modulation of nearly two orders of magnitude up to 25 GHz between the insulating and metallic states. The flat frequency response indicates that V0 2 may be useful for RF switching applications where broadband characteristics are necessary. The variety of two-terminal switching devices realized with V0 2 is an example of the promise of correlated oxide electronics. Indeed, two-terminal switching is only a small part of the total device possibilities. Many other device architectures and applications of correlated oxides are currently being investigated.

4.

Exploratory transistor devices

There have been efforts to build three-terminal field-effect transistors (FETs) and to electrostatically induce phase transitions in correlated oxides. The idea is to induce a large change in the conductivity in a correlated oxide channel by inducing a metal-insulator transition and therefore to achieve large transconductance. Newns and co-workers attempted to fabricate a FET with У^РГхВагСизО?^ as channel material and undoped SrTiC>3 as top gate oxide.20 Nonlinear transconductance was demonstrated and an increase in the mobility was achieved by gating. There have also been efforts to achieve a gate-controlled MIT in V0 2 , but experiments to date have shown only a modest field effect with time-dependent phenomena.21'22 This is an emerging area of research, and such correlated transistors require advances in gate stack processing techniques. Correlated oxide transistors could also be based on a heterojunction, as an analog of junction gated field-effect transistors (JFETs) or heterostructure field-effect transistors (HFETs). By growing NdNi03/La-doped SrTi0 3 heterostructures with different La concentration, the conductance of NdNi0 3 can be tuned because of different amount of charge transfer among these junctions.23 Demonstrating dynamic control of the channel resistance through an external gate voltage is the next step for such devices. Besides using correlated oxides as channel materials, there are also proposals to use these materials as the dielectric layer in three-terminal transistor devices. Owing to the ability to tune the dielectric and transport properties of these materials electrically or thermally, one could achieve three-terminal devices with new functionality. For example, Kim and co-workers have demonstrated a new phase transition memory element using vanadium dioxide.24 The device is similar to a transistor but instead of using a single oxide layer as a gate dielectric, a Si0 2 /V0 2 /Si0 2 heterostructure structure is utilized. When the V0 2 goes through its metal-insulator transition, either due to thermal or electrical stimulus, the

Future Trends in Microelectronics

306

effective capacitance of the gate stack changes in response to the conductivity and permittivity changes in V0 2 . This could lead to a shift in the threshold voltage of the metal-oxide-semiconductor structure. In addition, many correlated oxides exhibit ferroelectric-like behavior making them an important part of ferroelectric field-effect transistors. For example, by integrating a ferroelectric oxide, lead zirconate titanate, with a high-Гс superconducting copper oxide, electrostatic tuning of the superconducting temperature by several K has been demonstrated.25

5.

Conclusions

Correlated electron materials, particularly oxides, hold promise for developing a new class of solid-state devices for information processing, high frequency applications, and related circuits. The field is in early development stages and requires a deep understanding of materials and interface issues while simultaneously demonstrating proof-of-concept devices. A rigorous set of device physics models should emerge out of this research that will eventually allow one to critically examine the promise of correlated oxides in future device technologies. Acknowledgments The authors acknowledge the ARO MURI (W911-NF-09-1-0398), ONR (N0001410-1-0131) and NSF (DMR-0952794) for financial support. References 1. N. F. Mott, "The basis of the electron theory of metals, with special reference to the transition metals," Proc. Phys. Soc. London A 62,416 (1949). 2. V. I. Anisimov, J. Zaanen & O. K. Andersen, "Band theory and Mott insulators: Hubbard U instead of Stoner/," Phys. Rev. B 44, 943 (1991). 3. A. Fujimori, T. Yoshida, K. Okazaki, et al, "Electronic structure of MottHubbard-type transition-metal oxides," J. Electron Spectrosc. Relat.

4. 5. 6. 7.

Phenom.

117-118,277(2001). M. Cardona and F. H. Pollak, "Energy-band structure of germanium and silicon: The k p method," Phys. Rev. 142, 530 (1966). B. Moyzhes, T. H. Geballe, S. Jeong, D. Gitlin, and J. Karp, "Current through Si0 2 gate oxide and its low frequency fluctuations: Trapping on charged dangling bonds with negative Hubbard U," J. Appl. Phys. 97, 074104 (2005). M. L. Medarde, "Structural, magnetic and electronic properties of RNi0 3 perovskites (R = rare earth)," J. Phys. Condensed Matter 9, 1679 (1997). D. G. Ouellette, S. Lee, J. Son, et al, "Optical conductivity of LaNi0 3 : Coherent transport and correlation driven mass enhancement," Phys. Rev. B 82,165112(2010).

Correlated Electrons: A Platform for Solid State Devices 8. 9.

10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25.

307

M. K. Stewart, C.-H. Yee, J. Liu, et al, "Optical study of strained ultrathin films of strongly correlated LaNi0 3 ," Phys. Rev. B 83, 075125 (2011). S. J. May, C. R. Smith, J.-W. Kim, E. Karapetrova, A. Bhattacharya, and P. J. Ryan, "Control of octahedral rotations in (LaNi03)„/(SrMn03)m superlattices," Phys. Rev. B 83, 153411 (2011) [see also erratum Phys. Rev. B 85, 039905 (2012)]. A. R. Kaul, O. Gorbenko, I. Graboy, et al, "Epitaxial stabilization in thin films of oxides," Proc. MRSSymp. 755 (2003), pp. 291-302. M. K. Stewart, J. Liu, M. Kareev, J. Chakhalian, and D. N. Basov, "Mott physics near the insulator-to-metal transition in NdNi0 3 ," Phys. Rev. Lett. 107, 176401(2011). G. H. Aydogdu, S. D. Ha, B. Viswanath, and S. Ramanathan, "Epitaxy, strain, and composition effects on metal-insulator transition characteristics of SmNiOj thin films," J. Appl. Phys. 109, 124110 (2011). M. Imada, A. Fujimori, and Y. Tokura, "Metal-insulator transitions," Rev. Mod. Phys. 70, 1039(1998). C. Kübler, H. Ehrke, R. Huber, et al, "Coherent structural dynamics and electronic correlations during an ultrafast insulator-to-metal phase transition in V0 2 ," Phys. Rev. Lett. 99, 116401 (2007). G. Stefanovich, A. Pergament, and D. Stefanovich, "Electrical switching and Mott transition in V0 2 ," J. Phys. Condensed Matter 12, 8837 (2000). B.-J. Kim, Y. W. Lee, S. Choi, S. J. Yun, and H.-T. Kim, "V0 2 thin-film varistor based on metal-insulator transition," IEEE Electron Dev. Lett. 31, 14 (2010). M. J. Lee, Y. Park, S.-D. Suh, et al, "Two series oxide resistors applicable to high-speed and high-density nonvolatile memory," Adv. Mater. 19, 3919 (2007). Y. W. Lee, B.-J. Kim, J.-W. Lim, et al, "Metal-insulator transition-induced electrical oscillation in V0 2 thin film," Appl. Phys. Lett. 92, 162903 (2008). A. Cranteanu, J. Givernaud, J. Leroy, et al, "Voltage- and current-activated metal-insulator transition in V02-based electrical switches: A lifetime operation analysis," Sci. Technol Adv. Mater. 11, 065002 (2010). D. M. Newns, J. A. Misewich, C. C. Tsuei, et al, "Mott transition field effect transistor," Appl. Phys. Lett. 73, 780 (1998). D. Ruzmetov, G. Gopalakrishnan, C. Ko, V. Narayanamurti, and S. Ramanathan, "Three-terminal field effect devices utilizing thin film vanadium oxide as the channel layer," J. Appl. Phys. 107, 114516 (2010). S. Sengupta, K. Wang, K. Liu, et al, "Field-effect modulation of conductance in V0 2 nanobeam transistors with НЮ2 as the gate dielectric," Appl. Phys. Lett. 99,062114(2011). J. Son, B. Jalan, A. P. Kajdos, et al, "Probing the metal-insulator transition of NdNi0 3 by electrostatic doping,"^/?/. Phys. Lett. 99, 192107 (2011). M. Kim, S.-H. Lee, C. Ko, S. Ramanathan, J.-W. Lee, and S. Tiwari, "A new single element phase transition memory," Proc. 10th IEEE Conf. Nanotechnology (2010), pp. 439^142. C. H. Ahn, S. Gariglio, P. Parach, T. Tybell, L. Antognazza, and J. Triscone, "Electrostatic modulation of superconductivity in ultrathin GdBa2Cu307.x films," Science 284, 1152 (1999).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Graphene-Based Integrated Electronic, Photonic and Spintronic Circuit A. D. Güçlü,* P. Potasz,+ and P. Hawrylak Emerging Technologies Division, National Research Council of Canada, Ottawa, K1A 0R6 Ontario, Canada

1.

Introduction

At present, information processing is divided into three physically separate functions realized with three different classes of materials: information processing per se with silicon transistors; communication with photons using compound semiconductors, mainly InAs, InP and GaAs; and information storage with ferromagnetic metals. Such division is inefficient and, with some materials that are found in limited quantities, such as indium, not sustainable. Graphene1"16 and, in particular, graphene quantum dots17"36 offer an alternative to today's information technologies. As discussed below in greater detail, it has been recently predicted theoretically26"36 that there exists a special class of nanoscale graphene triangular quantum dots (GTQDs) with zigzag edges which fulfills all three functions needed for information processing: (i) size quantization turns graphene, a semimetal, into a semiconductor like silicon, with a bandgap tunable from THz to UV, enabling a GTQD-based single electron transistor for information processing; (ii) unlike silicon, GTQDs are equivalent to direct-gap semiconductors that absorb and emit light, and hence can be used for communication; and (iii) GTQDs exhibit a voltage-tunable magnetic moment that can be used for information storage. Therefore, graphene quantum dots might potentially be used as elements of graphene-based integrated electronic, photonic and spintronic circuit. Since carbon atom does not have nuclear spin, graphene-based chips utilizing electron spin as information carrier could form the basis of quantum technology. Alternative applications may include photovoltaics, single molecule sensing and printed electronics. Below we describe progress toward the understanding of the electronic, optical and magnetic properties of graphene quantum dots.

2.

Electronic properties of gated graphene quantum dots

In this chapter, we will discuss triangular quantum dots with zigzag edges30"36 as shown in the inset of Fig. 1(a). The carrier density is controlled by a metallic gate, Also with Dept. of Physics, Izmir Institute of Technology, 35430 Izmir, Turkey. * Now with Institute of Physics, Wroclaw University of Technology, Wroclaw, Poland. 308

Graphene-Based Integrated Electronic, Photonic and Spintronic Circuit

309

not shown, separated by a distance dG from a graphene quantum dot. At zero applied gate voltage, the island is charge-neutral while applied voltage leads to removal/addition of electrons to the island. The single-electron properties are described by a tight-binding (TB) Hamiltonian:1

where the operator cia+ creates a pz electron on fth atom with spin a. The tightbinding parameters xu 1018 cm"3, EF at the surface is mainly located above Ej, so the band bending is determined by the negatively charged acceptor-type surface states, the evenly distributed ionized donor atoms and the free electrons - see Fig. 3(b), lower panel. Unlike donor-type surface states, the acceptor-type states trap the free electrons coming from the donor atoms in the я-doped NW. In this case, there is almost no conduction band bending, electrons are distributed over the whole wire and do not accumulate at the surface. Figure 3(a) shows also that an increase in lattice temperature does not change the general tendency, although £ F pinning occurs at a slightly higher total ns due to the smearing of the Fermi-Dirac function at room temperature. An increase or decrease in nanowire radius R does not alter qualitatively the results presented in Fig. 3(a).

InAs Nanowires with Surface States as Building Blocks

355

Figure 3. (a) The location of the conduction band edge at the surface of the InAs nanowire (R = 50 nm) with respect to EF vs. the surface state density at low (solid line) and room (dotted line) temperature. The doping of the nanowire is set to 0 (squares), 5x1017 (circles), 1018 (triangles), 1.5x1018 (rhombi), and 2x1018 cm"3 (hexagons), (b) Schematic plot of the density of surface states, conduction Ec and valence E v bands, and £ F in the InAs nanowire for the dominant donor-type (upper) and acceptor-type (lower) surface states.

In order to reveal the influence of the NW geometry on electron population of the nanowire we calculate the average electron density, n = 2n]n{r)rdr/nR2 , 0

(4)

/

as a function of the nanowire radius for surface state densities above 5xl0 cm"2, i.e. when the Fermi level is pinned at the surface. Figure 4 shows that an increase in doping changes the dependence of the electron density on the radius of the nanowire. For low ND, the electron density in the nanowire decreases with R, whereas for ND > 1018 cm"3 it increases. The qualitative behavior of the calculated curves can be derived from the nanowire charge neutrality. Note that the total charge of the nanowire comprises the charge of the donor and acceptor-type surface states with the density »SD and «SA, correspondingly, the ionized donor atoms due to ND and free electrons: QTOT=0 = nSDx2nR-nSAx2nR

12

+ NDxnR2-nxnR1.

(5)

Thus, the average electron density is described by the following expression n = nSDx2/R-nSAx2/R

+ ND .

(6)

356

Future Trends in Microelectronics

Figure 4. The electron density n in the InAs nanowire vs. the nanowire radius R at low (solid line) and room (dotted line) temperature for the surface state density above 5x1012 cm' 2 at ND = 0, 5x1017, 7x1017, 1018, 1.5x1018, and 2x1018 cm"3.

As discussed above, in the case of the intrinsic nanowire, the donor-type surface states dominate and the electron density n ~ «SDIR. For the highly «-doped NWs, the profile of the conduction band is mainly determined by acceptor-type surface states and the ionized donors, thus n — « S A x 2IR + ND. Figure 4 also shows that increasing the lattice temperature T affects the electron density only slightly. This we attribute partly to the assumption of the full ionization of the donor atoms used in our model. Due to the large surface-tovolume ratio, surface states dominate the carrier density for narrow NWs, so doping has almost no impact. Modern passivation techniques may substantially lower the density of surface states, thus unpinning the Fermi level at the surface. Accordingly, we calculate the electron density as a function of the NW R also for lower surface states densities. Figure 5 illustrates that lowering of the total ns from 1013to 5xl0 10 cm"2 reduces the electron density due to the smaller amount of electrons supplied by the donor-type surface states. However, the general behavior of the curves does not change from the results calculated with £ F pinned at the surface. This is not surprising, as our interpretation of the obtained results based on the charged neutrality of the nanowire does not apriori assume any particular surface state density and holds for any ns. However, the impact of doping on the electron density in narrow NWs becomes more pronounced with decreasing surface state densities. The calculated dependence of the electron density on the radius of intrinsic InAs nanowires agrees well with the experimental data published recently.8

InAs Nanowires with Surface States as Building Blocks

357

Figure 5. The electron density n in the InAs nanowire vs. nanowire radius R at room temperature for the surface state density n s = 5x1010, 1011, 5x1011, 1012, and 1013 cm"2 and NW doping ND = 0, 5x1017, and 1018 cm"3.

4.

Conclusions

In conclusion, our theoretical study based on the solution of coupled SchrQdinger and Poisson equations shows that the conduction band bending and the electron density in the InAs nanowires are strongly affected by the charged surface states at both low and room temperature. The electric field induced by the positively charged donor-type surface states bends the conduction band downwards and for a surface states density above 5xl0 12 cm"2 the Fermi level is pinned above the conduction band edge. Thus, InAs nanowires with a radius above 20 nm show significant electron density even without doping due to the donor-type surface states providing free electrons. Further, и-type doping of the nanowire can substantially flatten the conduction band and redistribute electrons over the entire cross section of the nanowire. Our study provides design criteria for NW-based tube-like electrical sensing devices and field-effect transistors.

Future Trends in Microelectronics

358 References 1. 2. 3. 4. 5. 6. 7. 8.

Y. Xia, P. Yang, Y. Sun, et al. "One-dimensional nanostructures: Synthesis, characterization, and applications," Adv. Mater. 15, 353 (2003). U. Yogeswaran and S.-M. Chen, "A review on the electrochemical sensors and biosensors composed of nanowires as sensing material," Sensors 8, 290 (2008). S. A. Dayeh, C. Soci, P. K. L. Yu, et al., "Influence of surface states on the extraction of the transport parameters from InAs nanowire field-effect transistor," Appl. Phys. Let. 90, 162112 (2007). Q. Hang, F. Wang, P. D. Carpenter, et al, "Role of molecular surface passivation in electrical transport properties of InAs nanowires," Nano Lett. 8, 49 (2008). Ch. Blomers, M. I. Lepsa, M. Luysberg, D. Grützmacher, H. Liith, and Th. Schapers, "Electronic phase coherence in InAs nanowires," Nano Lett. 11, 3550(2011). H. Hasegawa and T. Sawada, "Photoionization and thermal activation of compound semiconductor MOS interfaces and origin of interface states," J. Vac. Sci. Technol. 21, 457 (1982). C. Affentauschegg and H. Wieder, "Properties of InAs/InAlAs heterostructures," Semicond. Sci. Technol. 16, 708 (2001). S. A. Dayeh, E. T. Yu, and D. Wang, "Transport coefficients of InAs nanowires as a function of diameter," Small 5, 77 (2009).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Levy Flight of Photoexcited Minority Carriers in Moderately Doped Semiconductors: Theory and Observation Arsen Subashiev and Serge Luryi State University ofNew York, Stony Brook, NY 11794-2350, U.S.A.

1.

Introduction

Diffusive transport of charge carriers in semiconductors has been the subject of detailed studies for at least half a century because of its importance for all electronic and optoelectronic devices.1"7 These studies have been based on two main approaches. In the first approach, a stationary distribution of minority carriers is created either by optical excitation or an electron beam. One then measures the surface photo-voltage by a capacitance2 or a Kelvin3 probe. Alternatively, one registers the photoluminescence spectra4 or the electron-beam induced currents.5 These studies give a measure of the diffusion length / = (Dr)m, the average distance travelled by minority carriers before they recombine, which is determined from the exponential decay of the distribution with distance from the excitation area. Here D is the diffusion constant and x is the carrier lifetime. The second approach, originating from Haynes and Shockley,6 uses the timeof-flight measurements,7 when a short injection pulse (or optical excitation pulse) creates an excess concentration of minority carriers at the edge of a long sample. An external field (the sweep field) across the sample initiates carried drift. Both the drift and the diffusion of carriers are registered by placing two probes along the sample, separated by a certain distance d. The drift velocity is measured as vD = d/t0, where t0 is the time of carrier drift between contacts, measured from pulses in the two probes. The diffusion coefficient is determined through the width at halfmaximum of the pulse at the second probe. By this experiment one can validate the Einstein relation between the diffusion coefficient and the carrier mobility. As demonstrated by these studies, the diffusion equation with a drift term (if an electric field is present) and appropriate boundary conditions can amply describe with few exceptions all the experimental results in various semiconductor structures. The underlying physics in the diffusion process is random motion of particles. If their speed is so large that the effects of the finite time of free flight are not observable, this random motion is equivalent to a random walk with some probability distribution for the size of a single step. Statistical analysis of this type of problems relies on the central limit theorem (CLT). The theorem predicts the distribution function of the final positions of spreading particles after a large number of steps. These positions emerge as a sum of many random steps with an 359

360

Future Trends in Microelectronics

identical single-step probability distribution (SSPD) function, T(x). According to the CLT, the final distribution should be normal (Gaussian), for any SSPD. The width of the distribution, which gives an average spread of the final positions after n steps, depends on the SSPD. It is given by = n, where is the second moment of the SSPD and n is the number of steps. For a given average temporal interval between the steps , the spread variance is = 2D, where D = /(2) defines the diffusion coefficient. The linear growth of the spread variance with time is a key feature of the normal diffusive process. Exceptional cases when the normal diffusion description is not sufficient are of special interest. Besides quantum modifications of the carrier transport, a fairly wide range of classical transport effects that do not follow the normal diffusion pattern have been reported. In this anomalous transport (often referred to as the "anomalous diffusion") the spread variance deviates from the linear growth in time.8 Clearly, such a deviation must be rooted in a failure of the CLT. From the definition of the diffusion coefficient D one can identify two possible mechanisms of anomalous kinetics. For some SSPD that slowly decay with the distance, the variance may become infinitely large. Alternatively, the diffusion is also anomalous when is infinitely large. The latter case is typical for the transport kinetics in disordered solids where impurities serve as capture centers for carriers. The random jumps then originate from the capture center activation, and the slowly decaying function is the distribution of waiting times between the jumps. Importantly, in both cases the CLT does not hold: the distribution of a sum of random numbers does not converge to a Gaussian. Still, the resulting distributions for these sums are well understood by the modern probability theory and are known as stable distributions.9 Recently, a rather dramatic example of anomalous diffusion was found in the studies of minority-carrier transport in semiconductors with high radiative efficiency,10'12 when the spread of minority carriers is primarily due to the photon recycling process with the emission-reabsorption events repeated multiple times. The secondary photons, when emitted in the red wing of the emission spectrum, can propagate to large distances, leading to a "heavy-tailed" SSPD, with a powerlaw decrease with the distance. The resulting anomalous carrier transport features super-diffusive temporal variation and an anomalously wide stationary distribution of the minority carriers. Such transport processes are called the Levy flight (after Pierre Levy, the discoverer of the stable distributions). Here we discuss the results of direct studies12 of a stationary distribution of the minority carriers, created by an optical excitation in the geometry that combines the advantages of the Haynes-Shockley experiment with those of the photoluminescence spectroscopy. These results provide an unambiguous demonstration of the Levy flight transport of holes in moderately doped и-ШР. 2. Anomalous diffusion of the minority carriers We consider the spatial distribution of holes created by optical excitation of an ndoped semiconductor. The energy relaxation time for non-equilibrium minority

Levy Flight of Photoexcited Minority Carriers in Semiconductors

361

carriers, created by reabsorption is due to electron-phonon interaction and at room temperature it is in the picosecond range, i.e. much shorter than the radiative recombination time. Therefore the temporal evolution of the hole concentration p(r,t) can be studied using the integro-differential transport equation:10"14 dp/dt-DAp = -ph + G(r,t) + R(r,t),

(1)

where G(r,t) is the generation function defined as the concentration of holes generated optically per unit time. For a single hole generated at r = 0 at time t = 0, this function is G(r,t) = 5(r)5(i). The recombination process is characterized by an average lifetime т of holes, which depends on the electron concentration and is in the nanosecond range. It can be either radiative (TR) or nonradiative (xNR), and the rates of these processes are additive, l/т = 1/TR + 1/TNR. The relative probability of radiative recombination is given by the emission quantum efficiency т\:

Ч-ГЙ--

(2)

The non-radiative lifetime in high-quality crystals reaches several microseconds and т| can be as high as 99%. Therefore, the emitted photons disappear mainly via interband absorption process, resulting in the generation of a new hole and then a new photon emitted. The last term in Eq. (1) is the recycling function R(r,t) given by R(r,t) = ^\T(\r-r4)p(r\t)dr',

(3)

which describes the concentration of holes generated per unit time at point r due to the radiative recombination of holes present in the crystal at the time t. For a finite sample, the solution of Eq. (1) should satisfy the boundary conditions for holes -D(dp/dn)\b = (Sxp)\b

(4)

where S is the surface recombination velocity, b stands for the boundary surface, and d/du denotes the derivative along direction normal to the boundary. 3.

Single step probability distribution

The factor T(\r-r'\) in the integrand of Eq. (3) describes the probability that a hole at r' generates another hole at r by the above-described emission-reabsorption process. For the two points separated by the distance r = |r - r'| this probability is given by nr)=l4E)EE^mai(E)dE,

(5)

where a(E) is the total absorption coefficient and щ(Е) is the absorption due to interband processes only. The integrand in Eq. (5) is the product of three probabilities: (i) the probability of emission of a photon of energy E, described by the normalized emission spectral function N{E); (ii) the propagation probability of

362

Future Trends in Microelectronics

this photon over the distance r = |r - r'| (this probability is described by the intensity distribution produced by a unit point source); and (iii) the absorption probability of this photon, described by the factor щ(Е). It should be noted that for a finite sample one must also consider the boundary conditions for the photons. These would modify the probability in Eq. (5). However, due to the high index contrast between the crystal and the ambient, the angle of total internal reflection is small and the radiation escape cone is narrow. Therefore, we shall further assume that the boundary surfaces are totally reflective for photons. The escape of radiation can be accounted for by an apparent decrease of quantum efficiency. For moderately doped «-type InP the distribution T(r) can be evaluated using Eq. (5) and the experimentally measured10"12'15"17 interband absorption coefficient (ц(Е) and the residual free-carrier absorption. With the known щ(Е), the spectral density N{E) of photon emission in a quasi-equilibrium radiative recombination process can be obtained from the thermodynamic relation due to van Roosbroek and Shockley,18 HE) = A щ(Е)Е2ехр[-Е/кТ\,

(6)

which we shall refer to as the VRS relation. Expression (6) represents the "intrinsic" emission spectrum and it agrees very well with room-temperature luminescence spectra measured from thin epitaxial layers (see, e.g. Ref. 19). Note that even in an infinite space without boundaries the solution of Eq. (1) cannot be factorized into product of functions depending on x, y, and z separately, since the transport processes along perpendicular directions are correlated due to the recycling term. However, it can be studied by starting with a one-dimensional (ID) problem and then finding the point-source distribution through it.11 To accomplish this one needs the ID reabsorption probability, which is given by T(x) = J T(r)dydz . Numerical evaluation of T(x) using experimental absorption spectra of InP has shown10"11 that for low-doped samples in the entire range of x, the dependence is very close to

where xmia ~ 0.1 |im is a distance scaling parameter that stems from truncation of the power law at short-distances and normalization of the distribution in Eq. (7). The essential parameter of the distribution is the exponent y, called the index of the distribution. For the Urbach-tailed absorption spectrum17 an approximate analytic expression for the index is:10"11 у=1-Д/А7\

(8)

where Д is the tailing energy. Numerical calculations based on a(E) measured for moderately doped samples show10"11 that the index varies from y = 0.69 to 0.64 in the ND = 2-óxlO17 cm"3 doping range, so that y decreases slightly as ND increases.

Levy Flight of Photoexcited Minority Carriers in Semiconductors

363

The empirical values of y are in agreement with Eq. (8), which is valid for a tailing region that is broad enough (compared to kT). The step distribution (7) is heavy-tailed for y < 1 as in Eq. (8). Its second moment diverges already for y < 2, which a hallmark of the anomalous diffusion. Sum of the steps does not follow the CLT and is not Gaussian. The heavy-tailed distribution arises due to the tailing in the absorption and emission spectra: the photons emitted in the red wing of the emission spectrum can propagate far away from the emission point, making the average square of the reabsorption length infinitely large. This property depends on the shape of the interband absorption spectrum and, in particular, on the width of the tailing region. In direct-gap semiconductors, the interband absorption is often approximated by щ(Е) ~ (E-EG)112. This approximation neglects the absorption tails, and hence misses the tailing effect in the reabsorption probability. Equation (8) correctly predicts the decrease of y with increasing doping level. This effect is due to the smearing of the absorption edge at higher doping, described by increasing tailing energy Д. Lower values of y are also predicted for lower temperatures. The residual free-carrier absorption (FCA) leads to the truncation of the step distribution (7) at distances x > l/aFC: n*)~(l/*)' + Y exp[-a F C x],

(9) 18

where aFC is the FCA coefficient. In и-InP one has aFc ~ 1.3xl(T ND, where aFC is in cm"1 and No is in cm"3. The truncated single-step distribution (9) has a finite second moment and one could expect restoration of the central limit theorem, so that the stationary particle distribution would exponentially decay from the source, as in ordinary diffusion. However, as we shall show both theoretically and experimentally, the truncation does not restore the exponentially decaying stationary distribution. 4.

Distribution along a band: Boundary effects

Consider a sample in the shape of a long (in x direction) band, whose width (y) and thickness (z) are both much larger than the ordinary hole diffusion length. Let a stationary photo-excitation be uniform across the short edge face, as shown in Fig. 1. Neglecting the loss of holes or photons at the front and the back broadside surfaces, the hole concentration will remain uniform in the cross-section (y, z) and the problem becomes one-dimensional. In this geometry, Eq. (1) is of the form -D(d2p/dx2) + - = G{x) + - J [Пх-х')

+T(x + *')] p(x') dx',

(10)

with the boundary conditions (4) at the x = 0 edge (see Fig. 1) and Eqs. (7, 9) for the kernel function. We have assumed total reflection of photons from the edge face surface by including an image source in the integrand. One can see that this •effect can be accounted for if one extends both the hole concentration p(x) and the

Future Trends in Microelectronics

364

Figure 1. Schematic illustration of the experimental geometry.12 An 808 nm laser excitation beam is focused on a narrow strip in the 7 mm edge of the sample and the photoluminescence is observed from the broadside.

range of integration to the entire axis by setting p(-x) = p(x). This brings Eq. (10) into the form: -D(d2p/àx2) + - = G(x) + -j Пх-х')р(х')

àx'.

(11)

Using the Fourier transformation, one can bring Eq. (11) into algebraic form. We write down the solution for the case of low-doped samples, when the Fourier transform of the kernel function (7) at k « l/xmin is given by T(k) = 1 - Dyky. The Fourier transform of the hole concentration p(k) is then given by пл

G(fc) - 25p(0)

Here / = (DT) 1/2 is the normal diffusion length, while DY is the anomalous diffusion coefficient: D

T

=

*min

r(Y)sin(jry/2)T'

,

v

.

'

The spatial hole distribution can be found by the inverse Fourier transform of Eq. (12), which however involves the edge concentration p(Q). An equation for p(0) is obtained by applying the result at x = 0. In this way, we finally find ш

x

_

1

G(k)cos(kx)

where J=

- 2f

Ki(l-n)

x

+ k^

+ nDyzkydk-

(15)

365

Levy Flight of Photoexcited Minority Carriers in Semiconductors

It follows from Eq. (14) that the surface recombination does not change the hole distribution profile: it manifests itself only through a multiplier factor which can be interpreted as an effective decrease of the excitation intensity due to some losses of holes at the surface. Therefore, we shall omit this factor from this point onwards. For optical excitation with an absorption coefficient cio, the generation function is of the form G(x) = I0aoexp[-a(pc] and its Fourier transform is given by

From Eq. (16) one can see that when the absorption length 1/ao for the optical excitation is smaller than the diffusion length / of holes, one can approximate the generation function as G(k) ~ I0. When the quantum radiative efficiency is low, n < 0.5, the photon recycling is immaterial and Eq. (14) reduces to the well-known solution that describes normal diffusion: p(x) = /0(T//)exp[-jt//]. menme s

(17)

rea

Furthermore, if / » (D T T)" , P d of holes due to anomalous diffusion is negligible, even though the recycling effect may enhance the effective diffusion length: Y

/EFF = /(1-Tir 1/2 -

(18)

The enhancement is due to the increase of the carrier lifetime by recycling. Of prime interest to us, however, is the opposite case when (D r T) l / y » /. In this case, the hole distribution profile is dominated by the anomalous diffusion and the normal diffusion term can be omitted for all x »I, leading to: p(x) s

,

t/ 0

7 cos(kx) J , / ' dk,

(19)

where xF is the excitation "front" distance, (20)

IF = ( O D / .

Here Ф = r|/(l - Г|) is the recycling factor, i.e. the average number of steps in the recycling process; for x\ ~ 99% one has Ф = ~ 100. Next let us consider the asymptotics of p(x) at small and large distances. To obtain these asymptotics, one can integrate Eq. (19) by parts. This gives /4

P W

T/

=

O*FY f K^sinQQ я(1 - n)x«ir Jo (1 + [ ( * F / * ) K F ) 2

'

K

}

It follows that in the limit of large x » xT one has p(x)s

mi-^yr(1 +

tfsin^/2)

i22)

Future Trends in Microelectronics

366

We see that at large distances the distribution is proportional to the probability of a single big jump, multiplied by the recycling factor that reflects the number of attempts available before the jump occurrence. Conversely, at small distances, x « x?, one has from Eq. (21) p(x) =

*'%

Г(1 -Y)sin(yK/2),

(23)

so that the decay of concentration still follows a power law, but with a smaller exponent. The rapid decay (21) of the concentration begins at x ~ xF, which can hence be regarded as the distance to the excitation front characterizing the particle spread. In contrast to the normal diffusion, for which the particle spread is proportional to U2, for the Levy flight process the excitation front distance (20) grows as l,y, which for y < 1 and large can be many orders of magnitude larger. The experimental results,12 described in the next Section, show that the observed effect is huge: the spread of holes is increased from a few microns (characteristic of ordinary diffusion) to several millimeters. The effect can be further drastically increased by lowering the temperature. 5.

Experimental luminescence spectra and observation of the Levy flight distribution of the minority carriers

The geometry of the experiment12 was shown in Fig. 1. The photoluminescence was optically excited by an above-bandgap laser (808 nm) at the edge face of an InP slab and both the luminescence radiation spectra and luminescence intensity were observed from the broadside and measured as a function of the distance x from the edge. The intensity distribution was obtained by scanning of the CCD image. The observed intensity was proportional to the excitation intensity. Apart from the normalization, the luminescence spectra were identical for all distances x > d. Moreover, their shape agreed with the c&\cw\zitúfilteredspectra, S(E) = Fi{E)T(E)M.E),

(24)

where F^E) is a one-pass filtering function that describes wavelength-dependent attenuation of the luminescence by sample absorption on the way out, d

F,{E) = t(z)exp[-a(£)z] dz,

(25)

and T(E) is a factor that accounts for multiple surface reflections. The function in Eq. (24) can be easily calculated assuming a uniform hole distribution across the sample, P(x,z)\x>d = p(x).

(26)

Levy Flight of Photoexcited Minority Carriers in Semiconductors

367

Figure 2. Spectra of luminescence observed from the broadside at varying distances from the edge. Solid line shows the spectrum evaluated according to Eqs. (23) and (24) with an accurate account for surface recombination in the calculated p(z) profile. Dashed line corresponds to a simplified model that neglects surface recombination. Also shown is the absorption spectrum, exhibiting a clear Urbach-tail behavior below the bandgap energy.

The experimental spectra are shown in Fig. 2 for several distances x from the edge. We also show the spectrum calculated using Eq. (23) as well as using a simplified model that ignores surface recombination (solid and dashed lines, respectively). The simplified model gives higher intensity in the blue wing and lower intensity in the red wing of the spectrum. More accurate calculations, taking into account the decrease of the hole concentration in a narrow region near the surface, give excellent agreement with the experiment for the entire spectrum. Near the emission maximum, the variation of the absorption coefficient is well reproduced by the Urbach exponent, and multiple reflections are negligible, so that one can take T-\ and set p(z) to a constant value. The position of the observed maximum can be then evaluated by setting dS(E)/dE = 0, which gives EMAX ~ 1.303 eV, in a very good agreement with experiment. The excellent agreement of the calculated spectrum with the experiment and the independence of the spectral shape from x is strong evidence for the proportionality of the luminescence intensity I(x) to the local hole concentration p(x). Note that the luminescence escapes into a narrow cone normal to the surface, therefore the observed I(x) corresponds to local concentration inside the wafer. The observed intensity distribution I(x) is shown in Fig. 3 (in log-log scale) for two samples with different doping. One can see a huge enhancement of the spread of the carrier concentration - extending to several millimeters - compared with a micron-range spread typical for the normal hole diffusion.4 For the low-doped sample, a power-law decay is clearly seen at distances x > 300 urn. A power-law

368

Future Trends in Microelectronics

fit for the index y gives -0.7, which agrees well with the theoretical estimate (8). The power law is dramatically distinguishable from an exponential decay (17) expected for normal diffusion - irrespective of any enhancement of the diffusion length (a diffusive curve for / = 210 um is shown for comparison by a dashed line). For the heavily doped sample, the power law decay is truncated at large distances, x > 1000 um, while the spread (the distance to the excitation front) remains anomalously large. This truncation of the distribution is due to the residual free-carrier absorption, which truncates the SSPD, see Eq. (9). Solid lines show the results of calculations, using Eq. (18) for the low-doped sample and a more accurate solution of Eq. (11) that accounts for the residual absorption in the heavily-doped sample. Both are in a very good agreement with experiment. Note that in spite of the truncation (that provides a finite diffusivity), the stationary distribution reproduces at large distances the single-step probability distribution (9). This is typical for anomalous diffusion.

6.

A single big jump approximation for the truncated Levy flight

The residual free carrier absorption that truncates the SSPD also makes its variance finite. Thus, one can use Eq. (9) to calculate a photon-assisted contribution to the diffusion coefficient, Dm = /2x. However, it is clear that when the truncation

Figure 3. Luminescence intensity and the hole concentration p(x) in n-lnP samples of different ND vs. distance from the sample edge (presented on a log-log scale). Solid lines show the theoretical curves obtained by solving the integro-differential transport Eq. (11). For the lightly-doped sample, p(x) follows an asymptotic power law with Y = 0.7. For the heavily-doped sample, the distribution is truncated at large distances (x > 1 mm) by free-carrier absorption. Dashed lines show "the single big jump" approximation, Eq. (32); dashed-dotted line shows the best fit by an exponential dependence (17) with an enhanced diffusion length /=210 um.

Levy Flight of Photoexcited Minority Carriers in Semiconductors

369

modifies SSPD only at very large distances (as is the case for truncation by FCA), then its effect on the experimental carrier distribution can hardly be dominant. More detailed analysis of the truncation shows that, for a slowly decaying step distribution, convergence of the sum of N steps to a Gaussian distribution can be very slow. It requires many more steps than the average, N » and the range of the distances from the source, in which the distribution is close to Gaussian, depends on N. Therefore at large distances from the source the distribution can be far from Gaussian even for the truncated SSPD. As an illustration, consider the probability of reaching a large distance x in two steps:20 РгОО = Í4\x - *'|ЖМ)аУ.

(27)

The integrand of Eq. (27) has two factors, sharply peaked at x' = 0 and JC' = x, respectively. At the peak of one factor, the other factor is declining with a gentle slope, which is true for both the power-law (7) and the exponentially-truncated (9) SSPD. In the limit x —> «>, we can take the slowly declining factor outside the integration with the value it has at the peak of the other factor. This gives T2(x) = 2T(x)JT{\x4)dx' ■

(28)

Equation (28) implies that the most probable way to reach a large distance in two jumps is to do it with one big jump, followed or preceded by a small jump. This is to be contrasted with a rapidly declining SSPD, where the maximum probability would correspond to both steps being of similar size, i.e. close to x/2. Furthermore, there is a rather broad class of distributions,20 including the truncated power-law distribution (9), for which the probability of reaching a large enough distance x in n steps is close to Tn(x)~rtT(x)[ÍHW\)àxTl-

(29)

Equation (29) implies that at very large distances x, a single big jump dominates the probability to reach x even in n steps. The mathematical theorem corresponding to Eq. (29) can be proven by induction, using (28). The theorem (29) suggests a way of solving Eq. (11) for a heavy-tailed SSDP - by sequential iterations in the asymptotic region at large distances from the source - making the "longest step approximation" (29) in all terms of the iterative series. This corresponds to choosing one of the steps to equal the total distance, while keeping all the other steps small. In Eqs. (28) and (29) the integration limits are not important and can be extended to infinity since the integrals converge at distances much shorter than x. One can, however, choose the limits in such a way that a good approximation is obtained at small distances too. To do this, we replace the integral in (29) by: ex

J = ÍTQx'lW = 2 J T&W , (30) o and determine the constant c by sewing together the solutions at small and large x.

Future Trends in Microelectronics

370

Using Eqs. (29) and (30), we can sum the iterative series obtained from (11) as a geometric progression, to find p(x) = nT/(l-4J)2,

(31)

or Gx p

w

ФТ(х)

( I - T 0 [ I + 5 THz and the short gate length limit requires La < 30 nm. If the LG fulfils this condition, the photoresponse will be resonant, corresponding to the excitation of discrete plasma oscillation modes in the channel. F o r / = 0.5 THz low frequency regime, one finds the characteristic gate length distinguishing short and long gate cases to be around 100 nm. In all cases except for the high-frequency short-gate limit, the FET will operate as a broadband detector. For a long gate, there is no qualitative difference between the low-frequency regime (COT « 1), where plasma waves do not exist, and the high frequency regime (ют » 1), where plasma oscillations are excited. There are however some quantitative differences, see Eq. (11) below. The excitation of plasma waves in the high-frequency, long-gate case has been clearly confirmed by the recent detection experiments in a magnetic field.21 In a magnetic field, the dispersion law for plasma waves reads: co = [coc2 + 2 12 (JÀ:) ] ' , where coc is the cyclotron frequency. Thus, plasma waves cannot propagate below the cyclotron frequency, since co < шс is possible only for imaginary values of the wavevector k. Therefore, in experiments with a fixed radiation frequency, the photoresponse is strongly reduced when the magnetic field increases above the cyclotron resonance.25 This is probably the most striking manifestation of the importance of plasma waves in THz detection by FETs and will be presented in more detail later in this chapter. Another interesting feature appearing in a magnetic field at low temperatures is related to Shubnikov-de Haas oscillations of the mobility. This provides an additional mechanism for the nonlinearity producing the photoresponse. Turning to the nonlinearity mechanisms, the most important is the modulation of the electron concentration in the channel, and hence of the channel resistance, by the local ac gate-to-channel voltage, as described by Eq. (5). Because of this, in the expression for the electric current/ = nev, both the concentration n and the drift velocity v will be modulated at the radiation frequency. As a result, a dc current will appear:y'DC = e, where n^t) and vi(t) are the modulated components of n and v, and the angular brackets denote averaging over the oscillation period

Terahertz Plasma Oscillations in Field Effect Transistors

381

2л/со. Under open-circuit conditions, a compensating dc electric field will arise, resulting in the photoinduced source-drain voltage ДЕЛ To date, the most relevant case experimentally has been that of a long gate. Here, independently of the value of the parameter COT, the ac current excited by the incoming radiation at the source cannot reach the drain side of the channel. For this case, the following result for the photoinduced voltage can be derived within the hydrodynamic approach:2 r

4U0 K

1+

2m

Vl + (oJT)2 J

(11)

As can be seen from this formula, the photoresponse changes by only a factor of 3 as the parameter COT increases from low to high values, despite the significant change of the underlying physics (for COT > 1 plasma waves are excited, whereas for COT < 1 they are not). Finally, for the low-frequency, long-gate limit, a phenomenological approach was recently developed,29 relating the expected detector signal with the channel conductivity a((7). The resulting simple formula reads: AU = &

\_da_ odU

(12)

Equation (12) takes into account the possible dependence of the mobility on gate voltage, and it remains valid even for U0 < 0. This approach allows calculating the expected photoresponse by a simple differentiation of the transfer characteristic. This formula also describes the observed contribution of Shubnikov-de Haas oscillations of the mobility to the photoresponse: these oscillations depend on the Fermi energy, and hence on electron concentration, which is governed by the gate voltage.

5.

Studies of THz emission from FETs

To measure a weak emission ( « I n W ) in the THz range, one needs a highly sensitive measurement system in which the background radiation and water vapor absorption can be avoided or compensated. We used two such systems: the cyclotron resonance spectrometer and vacuum fast Fourier spectrometer.30'31 In one of the first emission experiments, lattice-matched InGaAs/InP HEMTs with LG = 60 nm and the drain-source separation of 1.3 urn were used. An InGaAs/InP HEMT was chosen for its high carrier mobility (resulting in high quality factor values). The emission spectrum was relatively broad but it displayed a maximum that shifted from -0.4 THz to -1.2 THz with increasing drain voltage. This emission appeared only above a certain threshold value of the drain voltage and sharply increased (by orders of magnitude) with increasing the bias.3 A second

382

Future Trends in Microelectronics

Figure 4. Emission intensity as a function of source-drain bias in a magnetic field Bfrom0to6T. 4 superconducting coil, at the transistor side, was used to tune the emission. The threshold voltage increased with applied magnetic field due to the increase of the channel resistance in a magnetic field, as shown in Fig. 4.4 The threshold behavior for different magnetic fields served as the main argument for interpreting the observed emission as due to plasma wave instability. Other experimental results, obtained on GalnAs transistors, have also demonstrated that THz emission appears when the drain current exceeds a certain threshold. Also, the radiation frequencies were in a reasonable agreement with estimates for fundamental plasma modes. However, some other features predicted in by the ID theory,1 such as a strong dependence of the radiation frequency on the gate length and the gate bias were not observed. This is illustrated in Fig. 5 showing the emission spectra from an InGaAs HEMTs with LG varying from 50 nm to 100 nm. One can see that emission occurs always in the same frequency range and does not noticeably depend on LG. We believe that the edge instability20 discussed in Section 1 can explain most of the observed broadband emission spectra that are not influenced by gate voltage or gate length. As for tunable emission, THz emission tuneable by the gate bias has been observed only recently in AlGaN/GaN-based HEMTs.6 It persisted from cryogenic up to room temperatures. Unlike previous experiments, the emission peak was found to be tunable by the gate voltage between 0.75 and 2.1 THz. The highest emission was obtained from transistors with a modified architecture that included the so-called field plate - an additional metal layer deposited between the gate and the drain terminals (see inset of Fig. 6). The emission appeared in a threshold manner indicating plasma instability as its origin. Figure 6 presents the emission spectra for one of the samples and Fig. 7 shows the position of the emission peak vs. gate voltage. The solid line shows the dependence of the fundamental frequency on the gate bias calculated according to the theory.1'32

Terahertz Plasma Oscillations in Field Effect Transistors

383

Figure 5. Emission spectra from InGaAs HEMTs with (a) L^ = 150 and 300 nm and (b) LQ = 50 nm vs. VG = 0, - 0 . 1 , -0.2, -0.35 V (top to bottom).

The THz emission results obtained using the field plate GaN/AlGaN HEMTs show three main features: the emission appears at a certain drain bias in a threshold-like manner; the radiation frequency corresponds to the lowest fundamental plasma mode in the gated region of the transistor; and the radiation frequency is tuned by the gate bias which modifies the velocity s of plasma waves. These features are inherent attributes of the Dyakonov-Shur plasma wave instability in a gated 2D electron gas, and their presence provides a convincing argument that we observe this phenomenon. Summarizing the current experimental state of the art concerning plasma wave instabilities and THz emission from HEMTs, one can state that different types of instabilities with threshold-like behaviour of the emission intensity have been observed. Broadband gate length- and gate voltage-independent THz emission can be attributed to the edge instability.20 The broadband edge emission often dominates.

384

Future Trends in Microelectronics

Figure 6. Emission spectra for a GaN/AIGaN transistor (LG = 250 nm) at VD = 4 V vs. VQ. Inset shows schematic of AIGaN/GaN HEMT with a field plate.6

Figure 7. Experimental data (points) and calculations (lines) of emission f vs. VG for transistors with LQ = 150nm (dashed line) and 250 nm (solid line).6

Terahertz Plasma Oscillations in Field Effect Transistors

385

Although the results on field plate HEMTs are very promising, much more experimental research is necessary to establish the architecture of the best gatevoltage-controlled THz emitters. The power levels currently registered are typically of the order of ~0.1 \iW. This power is relatively small when compared with other existing sources. The real importance of FET-based emitters comes from the fact that using modern electronics technology many of these elements can be easily integrated into matrices to make high power sources. 6.

Experimental studies of THz detection by FETs

Below we describe the most significant experimental results on detection of subTHz radiation by FETs. The experimental setup for detection experiments is usually designed using monochromatic sources. The radiation is generated either by an electronic source (e.g., a Gunn diode), a backward wave oscillator (BWO), or a CCVpumped molecular THz laser. Terahertz radiation is guided using mirrors or light pipes and coupled to the FET by contact pads and bondmg wires or specially designed antennas. The experiments with polarized radiation usually show a well-defined preferential orientation of the electric field of the incident radiation related to the geometry of the antennas (or bonding wires playing the role of antennas).33 Typical results of detection experiments are shown in Fig. 8. A photovoltaic signal between source and drain is recorded as a function of VG, i.e. the carrier density in the channel. For a high carrier density (open channel) the signal is relatively small. The signal increases and saturates when the gate voltage approaches the threshold and rapidly decreases in the subthreshold region.28 i

40 I l l

JËL 3 0

f

Ф

w § 20 a. «

Mi

7=8K 80 K 150 K 296 K

-

600 GHz

Ф

o

JZ

a.

o

-I

1

-0.6

1

1-

-0.4

—1

,.'5Д

-0.2

Gate voltage VG (V)

o.o

Figure 8. Photoresponse of a GaAs/AIGaAs 0.15 /vm FET to 600 GHz radiation. The radiation-induced source-drain voltage is shown as a function of the gate voltage for different temperatures. The arrow marks the feature corresponding to the resonant detection observed at the lowest temperature.28

Future Trends in Microelectronics

386

The modeling of FET photoresponse uses the theoretical approach presented in the Section l.2'9 In the case of nonresonant detection, the signal should increase inversely with the decreasing carrier density n. However, as discussed in Section 1, this conclusion is valid only well above the threshold. As shown in Fig. 8, for voltages close to the threshold the signal saturates and decreases in the subthreshold region. The main reasons behind this discrepancy are the assumption of a linear dependence of the carrier density on the VG, as well as the omission of leakage currents and loading effects from the analysis. The linear dependence of n on VG is applicable to the on-state of the transistor (i.e. well above the threshold), but is not valid in the subthreshold region. The analytical expressions describing the signal vs. gate voltage for a realistic carrier density dependence were given in Ref. 28. It was shown that in the case of an exponential carrier versus gate voltage dependence (which is a standard approximation below threshold), the photoresponse saturates at a constant value:

Д1/ = Д г . 41/

(13)

where UA is the voltage induced between source and gate by incoming radiation and U* is the voltage that defines the exponential decay of the carrier density in the subthreshold range. This voltage can be written U* = x\kT/e, where i\ is the ideality factor of the transistor. A full quantitative interpretation of the experimental results is not possible without taking into account the loading effects of the external circuit. They become particularly important as the channel resistance mcreases exponentially close to the threshold. In this case both input resistance of the measurement system and parasitic capacitances start to be important. Due to loading effects, the signal below threshold can decrease even in the absence of a leakage current. The most complete approach to the quantitative interpretation of the experimental results was recently presented in Ref. 34. It was shown that to reproduce the experimental results one should begin by calculating the maximum expected signal AC/ by differentiation of the transfer characteristics - see Section 1. Then one has to divide ДС/the by a factor (1 + Rçu!2), where Л с н is the channel resistance and Z is the complex load impedance of the read-out setup. It is important that Z contain not only the load resistance of the preamplifiers but also all the parasitic capacitances. The inductance component can usually be ignored. Terahertz detection by silicon FETs represents the most promising application of this technological domain. This is because Si MOSFETs offer the advantages of room temperature operation, together with easy on-chip integration with read-out electronics and high reproducibility. The first demonstration of sub-THz and THz detection by Si CMOS FETs in silicon dates back to 2004.36 In 2006, Tauk and coworkers have shown that CMOS FETs at room temperature can reach a noise equivalent power competitive with the best conventional room temperature THz detectors.37 The first focal plane arrays in silicon technology have been designed for imaging at 300 GHz and 600 GHz by Schuster et al.38'39 and Ojefors et a/.40 see Fig. 9.

Terahertz Plasma Oscillations in Field Effect Transistors

387

Figure 9. Responsivity vs. f for VG = 0.2 V. Symbols: measured points, dashed line: guide for the eye. Inset: raster scan image of the source beam at 1.05 THz, where AU is the photo-induced drain-source voltage.38

Recently it has been demonstrated that by using an appropriate antenna and transistor design one can reach a record responsivity up to ~5 kV/W and a noiseequivalent power (NEP) below 10pW/Hz05 for detectors operating in the atmospheric window around 300 GHz, which is an important result for potential applications. The record responsivity and NEP were obtained thanks to the careful design of the antenna. Also, the FET gate length that was chosen to be close to the leakage length / - see above. Thus the channel was limited to the actively rectifying region, avoiding the series resistance of the passive part. Room temperature imaging with FETs has been demonstrated by a number of research groups. However, to date, most of the results were obtained in the subTHz range. There are only very few results on imaging with FETs at frequencies above 1 THz. This is because in the broadband detection regime, the photovoltaic signal decreases strongly with the increase of radiation frequency either because of the reduction in coupling efficiency or because of water vapor absorption. In Fig. 10 images of leaves obtained with 300 GHz source and a Si MOSFET are compared with an image of a metallic object in an envelope obtained with C0 2 pumped far infrared laser (1.6 THz) and GaAs FET. The images were recorded in a transmission mode by mechanical raster scanning the sample in X and Y directions. Good resolution, contrast, and an acquisition rate high enough for video-rate imaging were obtained. Generally, FETs are excellent candidates for fast room-temperature THz imaging at sub-THz and THz frequencies.41 When cot > 1, the condition for resonant detection is satisfied. A signature of resonant detection is the additional peak that appears in the data of Fig. 11 at the lowest temperature. Here, as in most experiments, the incoming radiation is a monochromatic beam and the source-drain voltage is recorded as a function of VG.

388

Future Trends in Microelectronics

Figure 10. Images of tree leaves at 300 GHz (a) and a metallic cross in an envelope at 1.6 THz (b) obtained in transmission mode at room temperature.41

Figure 11. Experimental (a) and calculated (b) photoresponse vs. VG as a function of temperature T = 300, 180 and 8 K (bottom to top). Inset in (a) shows the resonant signal after subtraction of the background. Inset in (b) shows the evolution of the carrier mobility and the corresponding quality factor Q at 600 GHz.9

389

Terahertz Plasma Oscillations in Field Effect Transistors

The gate voltage controls the carrier density in the channel and tunes the resonant plasma frequency. A resonant enhancement of the registered voltage is observed once the resonant plasma frequency coincides with the frequency of the incoming THz radiation and the quality factor condition Q = шт >1 is fulfilled. The resonance appears at low temperatures when the relaxation time becomes long enough (lower scattering rate). In Fig. 11 the experimental results are compared to calculations according to the theory of Ref. 2. The higher quality factor condition (Q from 2 to 4) can be obtained in high carrier-mobility InGaAs transistors,9 where well-defined resonances were measured - see Fig. 12. In Fig. 12(b), the position of the resonant maximum is shown. As the excitation frequency increases from 1.8 THz to 3.1 THz, the plasma resonance moves to higher swing voltages in approximate agreement with theoretical predictions (solid line). It is should be noted that the resonances observed in all of the experiments, Figs. 11 and 12, are broader than theoretically expected. This significant plasma resonance broadening appears to be one of the main unresolved problems of the resonant THz detection by FETs. The two main hypotheses concerning broadening point to either the existence of oblique plasma modes20 or to additional damping due to the leakage of gated plasmons to ungated parts of the transistor channel.42

c

xi 3-

3

. (a) •

Ф

•

••••

•

Г=10К * 3.1 THz

c o

Q. CO CD i-

o o

» ....

N

cr

•

2.5 THz %

(b)

>. o c _

CD 2 i

1.8 THz

i

*

i &

i

i

л

Ф

£ 1

-0.4

-0.3

-0.2

Gate voltage VG (V)

-o.i

Figure 12. (a) Photoresponse of InGaAs/lnAIAs transistors at 1.8, 2.5, and 3.1 THz at T= 10 K. (b) Signal maximum vs. VQl solid line is a result of calculations.10

390

Future Trends in Microelectronics

Figure 13. (a) Photoresponse at 10 K vs. VG in a multichannel InGaAs HEMT at 540 GHz, as a function of drain voltage VD = 0-100 mV. Curves vertically shifted for clarity, (b) Quality factor of the resonance as a function of VD.43,44

Narrowmg of the channel plasma wave resonances can be obtained either by changing the geometry of the channel or by increasing the current. Narrowing of the channel may decrease the role of oblique modes. Transistors with narrow channels were investigated in Refs. 43,44. In Fig. 13(a) we present the photoresponse of a narrow multichannel transistor at 540 GHz for a few values of the applied dram voltage FD. For the first time a relatively narrow line with quality factor around 10 was observed. This result clearly shows that using FETs with narrow channels is a good way to improve the quality factor. Another way to decrease the broadening of the plasma resonances is to apply a drain current. The drain current affects the plasma relaxation rate by driving the two-dimensional plasma in the transistor channel towards the Dyakonov-Shur plasma wave instability. As shown in Ref. 13, the resonant response in the presence of a drain current has an effective width 1Лед- that depends on carrier drift velocity v according to equation lAtfi =l/x - y, where y is the instability increment (see Section 1), which depends on the drift velocity v. For v «s,y = v/LG, where LG is the channel length. With increasing the current, the electron drift velocity increases, leading to the increase of the quality factor Q = ште{г. The effect of the current-driven line narrowing is illustrated in Fig. 13(b). Systematic studies have shown that the quality factor could thus be increased by more than an order of magnitude.43'44 The good agreement between the experimental data and calculations (solid line in Fig. 13(b)) confirms the model and clearly indicates that a dc current may be used to decrease the broadening of the plasma resonances.

Terahertz Plasma Oscillations in Field Effect Transistors

391

7. Conclusions We have presented an overview of the main physical ideas and experimental results concerning the THz plasma oscillations in field effect transistors (FETs) for the generation and detection of terahertz radiation. Both THz emission and detection, resonant and non-resonant, have been observed experimentally at cryogenic, as well as at room temperatures, clearly demonstrating effects related to the excitation of plasma oscillations. Currently, the most promising application appears to be the broadband THz detection and imaging in the non-resonant regime. However resonant THz emission and detection by excitation of plasma waves with high quality factors are yet to be achieved and deserve further exploration.

Acknowledgments This work was supported in part by French-Japanese (ANR-JST) project WITH and GDR-I "Semiconductor Sources and Detectors of Terahertz Radiation". References 1. 2. 3. 4. 5. 6. 7. 8.

M. I. Dyakonov and M. S. Shur, "Shallow water analogy for a ballistic field effect transistor: New mechanism of plasma wave generation by dc current," Phys. Rev. Lett. 71, 2465 (1993). M. I. Dyakonov and M. S. Shur, "Plasma wave electronics: novel terahertz devices using two dimensional electron fluid," IEEE Trans. Electron Dev. 43, 380 (1996). W. Knap, J. Lusakowski, T. Parenty, S. Bollaert, A. Cappy, V. V. Popov, and M. S. Shur, "Terahertz emission by plasma waves in 60 ran gate high electron mobility transistors," Appl. Phys. Lett. 84, 3523 (2004). N. Dyakonova, F. Teppe, J. Lusakowski, et al, "Magnetic field effect on the terahertz emission from nanometer InGaAs/AlInAs high electron mobility transistors," J. Appl. Phys. 97, 4313 (2005). N. Dyakonova, A. El Fatimy, J. Lusakowski, et al, "Room temperature terahertz emission from nanometer field-effect transistors," Appl. Phys. Lett. 88, 141906 (2006). A. El Fatimy, N. Dyakonova, Y. Meziani, et al, "AlGaN/GaN high electron mobility transistors as a voltage-tunable room temperature terahertz sources," J. Appl Phys. 107, 024504 (2010) J.-Q. Lu, M. S. Shur, J. L. Hesler, L. Sun, and R. Weikle, "Terahertz detector using two-dimensional electronic fluid," IEEE Electron Dev. Lett. 19, 373 (1998). J.-Q. Lu and M. S. Shur, "Terahertz detection by high-electron-mobility transistor: Enhancement by drain bias," Appl. Phys. Lett. 78, 2587 (2001).

392 9.

10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23.

Future Trends in Microelectronics W. Knap, Y. Deng, S. Rumyantsev, and M. S. Shur, "Resonant detection of subterahertz and terahertz radiation by plasma waves in submicron field-effect transistors," Appl. Phys. Lett. 81, 4637 (2002); W. Knap, Y. Deng, S. Rumyantsev, et al, "Resonant detection of subterahertz radiation by plasma waves in a submicron field-effect transistor," Appl. Phys. Lett. 80, 3434 (2002). A. El Fatimy, F. Teppe, N. Dyakonova, et al, "Resonant and voltage-tunable terahertz detection in InGaAs/InP nanometer transistors," Appl. Phys. Lett. 89, 131926(2006). W. Knap, M. Dyakonov, D. Coquillat, et al, "Field effect transistors for terahertz detection: Physics and first imaging applications," J. Infrared Millimeter Terahertz Waves 30, 1319 (2009). F. Stern, "Polarizability of a two-dimension electron gas," Phys. Rev. Lett. 18, (1967) 546. A. V. Chaplik, "Energy spectrum and electron scattering processes in inversion layers," Sov. Phys. JETP 33, 997 (1971) [Zh. Ebp. Teor. Fiz. 60, 1845(1971)]. M. Nakayama, "Theory of surface waves coupled to surface carriers," J. Phys. Soc. Japan 36, 393(197'4). A. Eguiluz, T. K. Lee, J. J. Quinn, and K. W. Chiu, "Interface excitations in metal-insulator-semiconductor structures," Phys. Rev. B 11,4989 (1975). S. J. Allen, D. C. Tsui, and R. A. Logan, "Observation of the two-dimensional plasmon in silicon inversion layers," Phys. Rev. Lett. 38, 980 (1977). D. C. Tsui, E. Gornik, and R. A. Logan, "Far infrared emission from plasma oscillations of si inversion layers," Solid State Commun. 35, 875(1980). A. P. Dmitriev, A. S. Furman, V. Yu. Kachorovskii, G. G. Samsonidze, and Ge. G. Samsonidze, "Numerical study of the current instability in a twodimensional electron fluid," Phys. Rev. B 55, 10319 (1997). M. Dyakonov and M. S. Shur, "Current instability and plasma waves generation in ungated two-dimensional electron layers," Appl Phys. Lett. 87, 111501 (2005). M. I. Dyakonov, "Boundary instability of a two-dimensional electron fluid," Semiconductors 42, 984 (2008). D. Veksler, F. Teppe, A. P. Dmitriev, V. Yu. Kachorovskii, W. Knap, and M. S. Shur, "Detection of terahertz radiation in gated two-dimensional structures governed by dc current," Phys. Rev. B 73, 125328 (2006). T. A. Elkhatib, V. Yu. Kachorovskii, W. J. Stillman, S. Rumyantsev, X.-C. Zhang, and M. S. Shur, "Terahertz response of field-effect transistors in saturation regime," Appl. Phys. Lett. 98, 243505 (2011). A. Lisauskas, U. Pfeiffer, E. Ojefors, P. H. Bolivar, D. Glaab, and H. G. Roskos "Rational design of high-responsivity detectors of terahertz radiation based on distributed self-mixing in silicon field-effect transistors," J. Appl. Phys. 105,114511(2009).

Terahertz Plasma Oscillations in Field Effect Transistors

393

24. S. Boubanga-Tombet, M. Sakowicz, D. Coquillat, et al, "Terahertz radiation detection by field effect transistor in magnetic field," Appl. Phys. Lett. 95, 072106(2009). 25. M. B. Lifshits and M. I. Dyakonov, "Photovoltaic effect in a gated twodimensional electron gas in magnetic field," Phys. Rev. B 80, 121304 (2009). 26. Withm the hydrodynamic approach [1], the left-hand side of Eq. (18) contains an additional "convective" nonlinear term v(dv/8x). The hydrodynamic approach is valid when the collisions between electrons are more frequent than collisions with impurities and phonons. 27. M. I. Dyakonov and A .S. Furman, "Charge relaxation in an anisotropic medium and in low-dimensional media," Sov. Phys. JETP 65, 574 (1987) [Zh. Eksp. Teor. Fiz. 92, 1012 (1987)]. 28. W. Knap, V. Kachorovskii, Y. Deng, et al, "Nonresonant detection of terahertz radiation in field effect transistors," J. Appl. Phys. 91, 9346 (2002). 29. M. Sakowicz, M. B. Lifshits, O. A. Klimenko, et al, "Terahertz responsivity of field effect transistors versus their static channel conductivity and loading effects," J. Appl. Phys. 110, 054512 (2011); see also M. B. Lifshits, "Terahertz photoresponse of field effect transistors near the threshold", Abs. 31st Intern. Conf. Phys. Semicond. (ICPS) (2012), p. 242. 30. W. Knap, D. Dur, A. Raymond, et al., "A far infrared spectrometer based on cyclotron-resonance emission sources," Rev. Sci. Instrum. 63, 3293 (1992). 31. W. Chaubet, C. A. Raymond, W. Knap, J. Y. Muiot, M. Baj, and J. P. Andre, "Pressure dependence of cyclotron mass in GaAs /GaAlAs heterojunctions by far infrared emission and transport experiments," Semicond. Sci. Technol. 6, 160(1991). 32. V. Ryzhii, A. Satou, W. Knap, and M. S. Shur, "Plasma oscillations in highelectron-mobility transistors with recessed gate," J. Appl. Phys. 99, 084507 (2006). 33. M. Sakowicz, J. Lusakowski, K. Karpierz, M. Grynberg, W. Knap, and W. Gwarek, "Polarization sensitive detection of 100 GHz radiation by high mobility field-effect transistors," J. Appl. Phys. 104, 024519 (2008). 34. H. Videlier, S. Nadar, N. Dyakonova, et al., "Silicon MOSFETs as room temperature terahertz detectors," J. Phys.: Conf. Series 4, 0129095 (2009). 35. R. Tauk, J. Lusakowski, W. Knap, et al., "Low electron mobility of field-effect transistor determined by modulated magnetoresistance," J. Appl. Phys. 102, 103701 (2007). 36. W. Knap, F. Meziani, N. Dyakonova, et al., "Plasma wave detection of subterahertz and terahertz radiation by silicon field-effect transistors," Appl. Phys. Lett. 85, 675 (2004). 37. R. Tauk, F. Teppe, S. Boubanga, etal, "Plasma wave detection of terahertz radiation by silicon field effect transistors: Responsivity and noise equivalent power," Appl. Phys. Lett. 89, 253511 (2006). 38. F. Schuster, D. Coquillat, H. Videlier, et al, "Broadband terahertz imaging with highly sensitive silicon CMOS detectors," Optics Express 19, 7828 (2011).

394

Future Trends in Microelectronics

39. F. Schuster, W. Knap, and V. Nguyen, "Terahertz imaging achieved with lowcost CMOS detectors," Laser Focus World*!, 37 (2011). 40. E. Ojefors, U. Pfeiffer, A. Lisauskas, and H. Roskos, "A 0.65 THz focal-plane array in a quarter-micron CMOS process technology," IEEE J. Solid-State Circ. 44, 1968 (2009). 41. S. Nadar, H. Videlier, D. Coquillat, et al, "Room temperature imaging at 1.63 and 2.54 terahertz with field effect transistor detectors," J. Appl. Phys. 108, 054508 (2010). 42. V. V. Popov, O. V. Polischuk, W. Knap, and A. El Fatimy, "Broadening of the plasmon resonance due to plasmon-plasmon intermode scattering in terahertz high-electron-mobility transistors," Appl. Phys. Lett. 93, 263503 (2008). 43. A. Shchepetov, C. Gardes, Y. Roelens, et al, "Oblique modes effect on terahertz plasma wave resonant detection in InGaAs/InAlAs multichannel transistors," Appl. Phys. Lett. 92,242105 (2008). 44. S. Boubanga-Tombet, F. Teppe, D. Coquillat, et al, "Current driven resonant plasma wave detection of terahertz radiation: Toward the Dyakonov-Shur instability," Appl. Phys. Lett. 92,212101 (2008). 45. O. A. Klimenko, Yu. A. Mityagin, H. Videlier, et al, "Terahertz response of InGaAs field effect transistors in quantizing magnetic fields," Appl. Phys. Lett. 97,022111(2010).

Future Trends in Microelectronics: Frontiers and Innovations. Edited by Serge Lviryi, Jimmy Xu and Alex Zaslavsky. © 2013 John Wiley & Sons, Inc. Published 2013 by John Wiley & Sons, Inc.

Index

ballistic transport, 329 band structure, 301, 306, 351, 352 bandgap engineering, 328 bandwidth, 20, 29, 37, 127, 141, 142, 148, 149, 160, 162, 167, 168, 171, 172, 185-188, 231, 258,259, 300-303 base current, 65, 82, 84, 85 BiCMOS, 290 biomolecules, 117 bistability, 259 bit error rate (BER), 44, 149, 290 Boltzmann constant, 95, 352 brain, 20, 21, 43, 286, 287, 288, 289, 292, 293, 294, 297, 298 breakdown voltage, 27, 28, 46, 7375, 79, 102, 103 buffer layer, 27, 85,241,343

A/D converters, 106,290 absorption, 39, 47, 132, 251, 256, 261, 293, 318, 342, 347, 349, 361, 362-368,370,371,381,387 free-carrier, 362, 363, 368, 371 adaptation, 293, 297 AlGaAs, 143-145, 148, 151, 154, 247,321,322,326,385,393 AlGaN, 26-28,46,47, 382-384, 391 algorithm, 267-269, 276, 279,280, 283, 285 aluminum (Al), 28,47, 107, 109, 112,136,143,144,152,155,209, 221,227 amorphous silicon, 115, 118, 203 amplifier, 149, 150, 290, 298 Anderson localization, 326 anomalous diffusion, 360, 363-365, 368 antenna, 173, 174, 176-181, 378, 387 optical, 141, 173, 175, 177, 178, 179, 180, 181 antireflection (AR) coating, 340, 349 arsenic (As), 6, 8, 10, 12, 14-17,22, 23,25,29,32,41,42,53,55,60, 64, 66, 67, 70, 84, 85, 88-90, 100, 125-127, 133, 135, 137, 143-146, 152-156, 162, 166, 167, 170, 188, 195, 196, 199, 202, 207,216, 218, 220-224, 234, 244, 247-251, 255, 256, 258, 259, 267-269, 278, 288, 296, 308, 310, 320, 321, 323, 324, 329,334,335,337,342,351,356, 359, 369, 371, 378, 380, 381, 382, 386, 389, 390 atomic force microscopy (AFM), 26, 242 atomic layer deposition (ALD), 115, 209

cadmium, 39 capacitance, 5, 6, 14, 16, 49, 50, 55, 77, 143, 148, 149, 154, 306, 374, 378, 379 carbon, 50, 51, 58, 104, 137, 197, 207,308,310,314,316,319 cavity optomechanics, 254 cellular automata, 270 central limit theorem (CLT), 359, 363 channel potential, 49, 89 chemical vapor deposition (CVD), 111, 112, 115,232,326 metal-organic (MOCVD), 17, 135,205,232 plasma-enhanced (PECVD), 209, 218, 228, 293 chip size, 143 circular polarization, 183, 185, 188, 190 clock synchronization, 290 395

396 CMOS, 13, 14, 18, 21, 22, 28-32, 35, 39, 42,45-48, 51, 55-59, 68-70, 73,80,82,89-92,105, 106, 110119, 134, 142, 164, 166, 205, 298, 303, 328, 386, 393, 394 post-processing, 32, 110, 113, 115,116,118 scaling, 3-6, 12, 14-17, 31, 32, 44, 45,49, 50, 55, 57, 59, 66, 69, 71,79,81,96, 100,110, 126128, 141, 142, 198,206,230, 234-237,328,331,351,362 scaling factor, 234, 235,237 coherent optical transmission, 172 computer, 118, 267, 268,270, 274, 277-287, 291 conduction band, 19, 20, 51, 63, 83, 151,152,245,248,310-313,332, 351-357 conductivity, 103, 177, 300, 305, 306, 317-321, 331, 332, 339, 374, 379, 381, 393 contact resistance, 218, 222, 224, 225, 326 copper, 13, 112, 114, 117,306 correlated electrons, 265 correlated oxide, 300-306 correlation effects, 311 Coulomb blockade, 311,317 critical dimension (CD), 5, 43, 123 crosstalk, 31,330 current drive, 9, 89 current gain, 86, 106, 107 data center, 143 depletion, 12, 16, 28, 60, 64, 68, 102,322,323,331,378 charge, 16 region, 16 detectivity, 182 detector infrared (IR), 179,249 diblock copolymer, 132 dielectric, 13, 27, 45, 53, 67, 83, 97, 105, 112, 114, 116, 133,147,218,

Index 221, 234, 302, 305, 307, 316, 333, 337, 374 diffusion coefficient, 359, 360, 364, 368 dislocations, 17, 343 display, 32, 117,255 liquid crystal (LCD), 243 DNA,4,41,42,43 domain, 95, 132, 161, 162, 163, 171, 181,214,219,334,386 donkey, 281 doping profile, 53, 211, 212, 213, 214,219,225,227 drain current, 56, 60, 61, 62, 63, 68, 378, 382, 390 drain-induced barrier lowering (DIBL), 14, 15, 51 dynamic RAM. See memory effective mass, 17, 51, 54, 248, 257, 332, 352, 374, 378 efficiency, 10, 23,25, 30, 37, 39, 46, 55, 56, 108, 121, 124, 125, 126, 127, 130, 131, 132, 143, 149, 170, 178,179,195,196,198,201,202, 205, 208-219, 221, 223-228, 239, 241, 244, 245, 250, 252, 290, 298, 360-365,370,371,372,387 electric field, 7, 14, 15, 27, 68, 83, 90, 102, 145, 146, 165, 174, 177, 187, 188, 220, 233, 290,293, 329, 337,352,357,359,374,381,385 electron spin, 138, 185, 270, 272, 308,310,328 electron-electron interaction, 310, 313,319,321 electrostatic discharge (ESD), 73, 74,77-80,91,153 emitter-coupled logic (ECL), 105, 106, 107 energy conversion, 143, 239,241, 244, 252, 260 energy resolution, 41

Index epitaxy, 26, 90, 133, 204,232, 242, 303, 322, 340 molecular beam epitaxy (MBE), 232,247,333,335,337,351 error correction, 267, 268, 269, 273, 275, 282, 283, 285 excitons, 245, 315 far infrared (FIR), 387,393 feature size, 10, 12, 113, 121, 127, 129,351 field-effect diode (FED), 73-82, 87, 91,92 fin-FET. See transistor fluctuations, 16, 56, 59, 94, 137, 175, 181,254,306,317 fluorescence, 294 frequency domain, 181 frequency modulation, 187, 190 frequency response, 305 fuel cells, 105, 240 GaAs, 47, 83, 134, 136, 144, 148, 151, 152, 190, 229, 244-253,261, 308, 319-324, 327, 351, 371, 385, 387, 393 GaN, 26-29,46, 47, 231-235, 239242,341-350,383,384 template, 26 gate capacitance, 51, 57 gate oxide, 6, 53, 67, 86, 105, 106, 305, 306 gate stack, 13, 14, 28, 305, 306 genome, 41,48 germanium (Ge), 14, 17, 18, 25, 45, 53-56, 82-6, 90, 180, 301, 306, 322,331,339,372,392 germanium-on-insulator (GeOI), 52, 53,57,91 giant magnetoresistance (GMR), 93, 185 gold, 115, 177, 178, 179,273 grain boundaries, 16, 25 graphene, 19, 20, 43, 46, 50, 54, 58, 265,270,308-318 nanoribbons, 46, 54, 270, 318

397 quantum dots (QDs), 308-318 grid parity, 25, 193, 196, 206, 207 hafnium oxide (Hf02), 82, 83, 88, 307 Hall effect, 316, 317, 327, 335, 337 fractional quantum Hall effect (FQHE),310 spin (SHE), 329 Hanle effect, 337, 338 heterojunction, 46, 54, 58, 82, 83, 91,92,151,203,204,242,305 heterostructure, 51-57, 83, 91, 92, 151,159,305,321,335 AlGaAs/GaAs, 326 GaN/GaAIN, 27, 28, 46, 47, 382, 384, 391 hexagonal, 134, 314 Hgl 2 ,40 hydrogen, 112, 135, 300, 315, 334 hysteresis, 62, 70, 87, 88, 89, 90, 92 ideality factor, 386 impact ionization, 50, 60-65, 82, 8792 implants, 287, 293, 298 Ino.53Gao.47As, 91,338 InAs, 47, 54, 55, 58, 246-253, 308, 329-331,338,351-358 InN, 231, 232, 240, 242, 331-340 InP, 17, 83,254, 255, 261, 308, 331, 335, 338, 339, 362, 366, 370, 372, 381,392 input/output (I/O), 30, 142 integrated circuit (IC), 29, 47, 55, 58,77,81,90,105-108,112,117, 119,129,135,142,143,149,170, 200, 203,297, 298, 316, 328, 330 integration, 5, 14, 17, 20, 27, 29, 37, 44,49,56,59,81, 115, 119,123, 141, 166, 202, 230-236, 239,243, 364, 369, 386 interconnect, 22, 29, 30, 31, 111114,135,136,143,203,286,330 optical, 29, 30, 31,43,47, 142, 143, 144, 158, 188, 190

398 interface states, 358 Internet, 4, 160, 171, 172 Internet protocol (IP), 171 intersubband transition, 179 inversion layer, 392 ion implantation, 47, 72, 104, 106, 202, 203,209 ITRS roadmap, 3, 5, 14, 47, 69, 113, 121, 122, 193, 204, 205,267, 268 kink effect, 61 laser cavity, 258 diode, 47, 161 population inversion, 256, 257, 259 quantum cascade (QCL), 180, 182 quantum dot (QD), 135 quantum well, 189 semiconductor, 141, 183, 187, 189, 190 spin, 184, 189 terahertz (THz), 385 VCSEL array, 153,157 vertical cavity surface emitting (VCSEL), 30, 143, 144-159, 183 femtosecond, 304 lattice mismatch, 17, 26 lattice temperature, 352, 354, 356 leakage current, 5-8, 27, 50, 59, 60, 83, 87, 304, 328, 386 levelized cost of electricity (LCOE), 196,206,207 Levy flight, 359, 360, 366-371 lifetime, 79, 125, 126, 148, 190, 196, 204, 220, 223, 224, 227, 230, 245, 249, 251,280, 307, 328, 329, 359, 361,365 carrier, 79, 204, 220, 223, 359, 365 photoelectron, 246, 249 light-emitting diode (LED), 23, 26, 27, 46, 205, 342, 348, 349 linewidth, 187, 188,258

Index liquid crystal on silicon (LCoS), 111, 114,117 lithography, 3, 6, 7, 121-125, 130133, 137, 322, 333 electron-beam, 333, 334, 337 EUV sources, 124, 131 extreme ultraviolet (XUV), 121, 132 optical, 75, 127, 322 local oxidation of silicon (LOCOS), 112 Luttinger liquid, 319, 325-327 magnetic anisotropy, 10, 44, 97 magnetic RAM. See memory magnetic tunnel junction (MTJ), 810,44,93-101,117 magnetization reversal, 335 magnetoresistance, 185, 335, 337, 339, 393 manufacturability, 3, 45, 133, 136 mass production, 25,27, 62 mean-field approximation, 300 mechanical energy harvesting, 231, 232, 236,240, 242 membranes, 43, 115,299 memory A2RAM, 68, 69, 70, 72 biological, 20, 21, 43, 286-289, 292-294, 297, 298 cell, 44, 62, 64, 65, 66, 67, 68, 69, 70,71,72,73,74,75,76,79 dynamic random access (DRAM), 4-8, 29, 30,44, 57, 59, 60, 62, 64, 69, 70-72, 80, 89,92,93,110 flash, 22, 44, 93, 110 magnetic random access (MRAM), 20, 22, 23,44, 93, 94 MRAM composite free layer, 9598, 100 MRAM free layer, 10, 93-100 MRAM pinned layer, 93, 97, 100, 101 MRAM thermal stability, 94, 95, 96, 100

Index one-transistor IT-DRAM, 59, 66, 67,69,70,71,72 resistive RAM (ReRAM), 11,12, 20, 22, 23,43 spin transfer torque STT-MRAM, 8-10,44,93-95,100,101,110, 117 static random-access (SRAM), 56, 57,80,89,91,113,125 memristor, 21,46 mesa, 154,322 metal-insulator transition, 302, 303, 305, 307 metal-organic vapor phase epitaxy (MOVPE), 46, 232, 322, 340, 341, 342, 349 microelectronics, 36, 115, 132, 133, 135,193,242 microprocessor, 36,49 mobility, 8, 14-19, 27, 45, 212, 213, 220, 227,296, 305, 333, 340, 345, 359, 372-375, 380, 381, 388-393 degradation, 213 model, 213, 220 modulation, 19, 20, 60, 103, 148, 161-168, 172, 182,185-190,290, 293, 294, 298, 305, 307, 339, 380 modulation formats, 161, 163, 164, 166, 172 modules, 150, 161, 162, 195, 196, 198,199,201,203,208,288 molecular electronics, 311 monolithic integration, 29 Moore's Law, 81, 110, 120, 121, 129, 198 more-than-Moore devices, 110, 116 nanoelectronics, 3, 70, 135, 137 nanomaterials, 239 nanotube carbon (CNT), 50, 51, 54, 58, 137, 319 nanowire (NW), 18, 19, 49-58, 83, 84, 91, 92, 137, 234-237, 240-243,

399 271, 331, 333-337, 340, 342-346, 351-358 hetero-NW, 83, 84, 90, 91 national security, 281 negative resistance, 74 neural network, 46,294 neuron, 20,21, 286, 288, 293 interface, 286, 289, 290, 291, 292, 293, 296, 298 neurotechnology, 291, 296 nitrides, 231 noise, 10, 55, 106, 107, 166, 167, 249, 260,267, 270-272, 275-279, 283, 284,290, 386, 393 \lf, 284 low-frequency, 92 nonvolatile memory, 22, 109, 307 numerical aperture (NA), 16, 121, 122, 127, 220, 224 ohmic contact, 333 optical cavity, 144 optical communication, 160-163, 172,317 optical fiber, 144, 153, 159-161, 170, 294 multi-mode, 144, 154 optical modulator, 30, 162 optical network, 144, 160-163, 168172 optical pumping, 257 optogenetics, 294, 295 parasitic capacitance, 386 passivation, 105, 198, 202, 218, 315, 318,356,358 permittivity, 249, 306, 333 personal computer (PC), 37 phase coherence, 358 phase transition, 301-305, 307 phonon, 248, 300, 393 bottleneck, 245 phosphorus, 212 photodetectors, 30, 149, 179, 182, 251,252,317 infrared (IR), 179, 249 infrared QD, 249,252

400

photodiode, 39 photo luminescence (PL), 248, 341, 342, 345, 346, 349, 359, 364, 366, 370-372 photon, 40, 118, 148, 173-175, 181, 184, 186, 202, 245, 252, 256, 272, 294, 312, 360, 361, 362, 365, 370 emission, 362 recycling, 360, 365, 370 photonic crystal, 147, 271 photonics, 4, 29, 30, 47, 141, 172 photovoltaics (PV). See solar cell piezoelectricity, 241 planarization, 334 plasma, 28, 89, 123-126, 131, 132, 265, 293, 341-346, 350, 373-383, 389, 390-394 plasma instability, 382 plasmonics, 113, 115, 116, 141, 173, 182 plasmonic emitter, 115 Poisson equation, 352, 357 polysilicon, 112, 198, 199,200 population inversion, 256, 257, 259 potential barrier, 67, 246-253, 328 potential well, 64, 66, 67, 68, 69, 173, 353 power dissipation, 50, 69, 74, 174, 175, 329 power electronics, 23,43 power management, 241 power-delay product, 55 propagation delay, 51 pyramids, 247 quantized conductance, 326, 327 quantum computation, 265-285 fault-tolerant, 267, 278,284 quantum confinement, 134 quantum dot (QD), 16, 17,25, 135, 144, 158, 175, 189,245-253,258, 271,272,284,308-318,331 built-in charge, 246, 252,253 quantum entanglement, 283 quantum gate, 267, 269

Index quantum well (QW), 17, 45, 48, 66, 67,71, 144, 148,158,179, 182, 183,189, 190,252,322 quantum wire, 144, 319, 320, 322, 323, 324,325, 326, 327, 338 qubit, 267,268, 269, 270, 272, 274, 276, 277,283 radiation, 23, 39, 40, 59, 102-108, 114-118,126,127,132,173-179, 208, 245,248, 250-253, 265, 350, 362, 366, 371-373, 378, 380-394 rate equation, 185, 186, 254,256, 259 reactive ion etching (RIE), 334, 335, 340-344, 347, 349, 350 recombination, 25, 86, 183, 184, 210-228, 245, 246, 249, 251, 346, 361, 365, 367, 372 radiative, 213, 361,362 rectifier, 74 redundancy, 158 refractive index, 143, 145, 147, 153155, 187,188,257 relaxation time, 184, 249, 331, 360, 374, 375, 379, 389 reliability, 49, 63, 66, 89, 90, 106, 133, 148, 194, 292 resistance, 9, 11, 15, 16, 46, 103, 149, 210-218,220-227, 305, 323327, 332, 337, 339, 350, 378-382, 386 resolution, 31, 35, 37,41,48, 125, 127, 293, 294, 303, 387 resonant tunneling, 327 response time, 148 reverse engineering, 133 ring resonator, 30 samarium nickelate (SmNi03), 303, 307 saturation, 10, 83, 95, 97,220, 251, 266, 392 regime, 392

Index scattering, 15, 39, 162,249, 257, 331, 345, 349, 350, 389, 392, 394 Schottky, 19, 20,46, 103, 108, 109, 234, 322, 372 barrier, 19, 20, 46, 372 Schr6dinger equation, 352 scintillators, 39, 371, 372 screen printing, 23 seismic monitoring, 104, 105,231 self-assembly, 128, 132, 340, 351 semiconductors III-V, 14, 17, 18, 19, 20, 30,4347, 54-58, 82, 87, 135, 144, 151,166,205,331,332,337, 351,353 work function, 16, 17, 19, 20 sensors, 31, 32, 36, 42,47, 105, 110, 111, 113,117,230,231,241,286, 292, 293, 296, 358 network, 36 series resistance, 144, 149, 210, 213, 218,220,222,224,305,387 short channel effects, 13, 14, 55, 57 SiGe, 13, 14, 59, 66, 67, 82, 83, 84, 91, 114, 118 silicon, 3-5, 13-21, 23, 27,29, 32, 35,36,46,47,51,63,66,67,70, 73,74,77,92,102-112,115,117, 137, 141, 166, 170, 190, 194, 198, 204,208-210,214, 218, 226-229, 260, 270, 297, 306, 308, 338, 339, 350, 386, 392, 393 photonics, 47, 170 silicon carbide (SiC), 102, 103, 104, 105, 106, 108, 109 silicon dioxide (Si0 2 ), 13, 53, 67, 105, 109, 218, 254, 293, 303, 305, 306,333,351 silicon nitride (Si3N4), 81, 112, 198, 214, 218, 228, 229, 254, 260, 333 silicon-on-insulator (SOI), 14, 45, 50-53, 57, 59-63, 66, 67, 70-82, 89-92,105,119 fully-depleted (FD-SOI), 14, 15, 50,61,64,66,71 partially-depleted (PD-SOI), 63

401

single photon, 173, 181,271 small-slope switch, 51, 55 software, 20, 22, 247,287 solar cell, 23-25, 46, 115, 118, 119, 194, 208-229, 239, 244-253 CMOS integration, 115 interdigitated back contact (IBC), 24,25, 203, 204 kerfless, 204, 209 metal wrap through (MWT), 203, 204 quantum dot (QD), 249, 252 rear point contact (RPC), 225,226 selective emitter, 225, 226, 227 silicon heterojunction (HJT), 203 space charge, 353 space exploration, 108 spectral efficiency, 160, 167, 168, 172 speech recognition, 298 spin, 8-10, 44, 93-97, 100, 101, 141, 183-190, 270-275, 285, 301, 302, 308-312,315-318,328-339 accumulation, 331, 336 amplification, 186 current, 95, 190 injection, 183, 185, 187-189, 331, 335-339 relaxation, 184, 186, 187,285, 329,330,331,337,338 transport, 330, 338 wave, 100 spin valve, 331, 335, 336, 337, 339 spin-orbit interaction, 184, 329, 330, 331,333,337 spintronics, 189, 190, 328, 330, 331, 337 spontaneous emission, 257 spreading resistance, 219, 224,226 stimulated emission, 148, 257 stored charge, 5, 66 strain, 6, 54, 58, 148, 152, 230, 234, 235, 236, 237, 238, 239,245, 302, 303, 307, 346 subthreshold slope, 50, 57, 83, 91, 92

402

subthreshold swing (SS), 14, 18, 19, 49,50,51,55-58,81-91 supercomputer, 142 superconductors, 272,283, 306, 382 supercoupling effect, 66 superlattice, 49, 303 switching, 9-11, 12, 31, 45, 46,49, 50, 56, 57, 81, 82, 87-90, 92, 94101, 103, 163, 303-307, 328, 329, 335,337 optical, 163 telecommunications, 169, 187 terahertz (THz), 258, 265, 308, 312, 313,373,377-394 imaging, 373, 379, 386, 387, 393 laser, 385 thermal budget, 111, 114, 116 thermal conductivity, 143, 147 thermal noise, 10 thermal stability, 10, 94-97, 100, 101, 126 threshold, 12, 16, 28, 57, 60, 61, 63, 77, 82, 86, 88, 134, 135,146, 170, 183-189, 257,258, 267, 268, 272, 276, 277-279,285, 304, 306, 335, 374,375,376,381-386,393 voltage, 16, 17, 21, 28, 57, 60-66, 77, 82, 86, 88, 134, 135, 306, 374, 378, 382 threshold theorem, 267, 268, 272, 276-279 timing, 75, 76 transconductance, 135,290, 305 transfer characteristics, 83, 84, 386 transistor, 6-9, 12-15, 19-21, 44,46, 50, 57, 59-68, 71, 72, 80, 90, 106, 109,111,265,274,305-308,311, 316, 329, 338, 373, 378, 379, 382389,390,391-394 bipolar junction (BJT), 65, 67, 109 dual gate, 79 field-effect (FET), 14, 15, 19, 29, 42,45,46,49,50,57,58,71, 90-92,137,305,306,328,329,

Index 333, 357, 358, 373-380, 385387, 391-393 fin-FET, 13-17, 50, 67,74,79 gate-all-around, 7, 8, 14, 17-19, 45,50,51,54,79 heterojunction bipolar (HBT), 82, 84-86, 90, 92 high-electron mobility (HEMT), 28,47,381,384,390 metal gate, 7, 13 metal oxide semiconductor (MOSFET), 28,45, 50-55, 58, 59,65,68,71,81,328,380, 387 modulation-doped (MODFET), 253 multi-gate (MuGFET), 13, 14, 50, 51,53,74,79,80,84 single-electron (SET), 311 spin, 329, 338 tunneling (TFET), 14, 18, 19, 49, 53-58,81-92 Z2-FET, 82, 87-92 transmission line, 329, 330, 379 trench, 17, 62, 112 tungsten, 109 tunnel (Esaki) diode, 84 tunneling, 8, 14, 18, 19, 20, 46, 51, 57,58,61,81-92,134,136,185, 245,249,314,331,337 Fowler-Nordheim, 19, 20 interband, 49, 50, 51, 55, 64, 68, 69,86 junction, 51, 53, 56, 85 oxide, 7 two-dimensional electron gas (2DEG), 28, 322, 326, 329, 333, 335, 339, 393 ultra large-scale integration (ULSI), 287 unipolar device, 249 Urbach tail, 362, 367 valence band, 51, 83, 151, 184,245, 313

403

Index vanadium oxide (V0 2 ), 304, 305, 307 variability, 16, 21, 56, 57, 59, 69, 135, 137, 302 variable range hopping (VRH), 321 Venus, 102-105, 108 very large-scale integration (VLSI), 20,45,46,48,57,71,91,92,118 wavefunction, 267, 274, 275, 352 wavelength division multiplexing (WDM), 30, 160, 162-168, 170

wireless, 36, 230,231, 241, 242, 287, 290, 291, 292, 296, 297, 298, 299 wiring, 3, 110,112, 134, 136,195 x-ray diffraction (XRD), 303 yield, 37, 133, 170, 202, 203, 204 zinc oxide (ZnO), 231-239, 241, 242, 304