Embedded Mechatronic Systems, Volume 2: Analysis of Failures, Modeling, Simulation and Optimization [2 ed.] 1785481908, 9781785481901

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Embedded Mechatronic Systems, Volume 2: Analysis of Failures, Modeling, Simulation and Optimization [2 ed.]
 1785481908, 9781785481901

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Embedded Mechatronic Systems 2

Revised and Updated 2nd Edition

Embedded Mechatronic Systems 2 Analyses of Failures, Modeling, Simulation and Optimization

Edited by

Abdelkhalak El Hami Philippe Pougnet

First edition published 2015 in Great Britain and the United States by ISTE Press Ltd and Elsevier Ltd © ISTE Press Ltd 2015. This edition published 2020 in Great Britain and the United States by ISTE Press Ltd and Elsevier Ltd Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address: ISTE Press Ltd 27-37 St George’s Road London SW19 4EU UK

Elsevier Ltd The Boulevard, Langford Lane Kidlington, Oxford, OX5 1GB UK



Notices Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary. Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility. To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein. MATLAB


is a trademark of The MathWorks, Inc. and is used with permission. The MathWorks does not

warrant the accuracy of the text or exercises in this book. This book’s use or discussion of MATLAB® software or related products does not constitute endorsement or sponsorship by The MathWorks of a ® particular pedagogical approach or particular use of the MATLAB software. For information on all our publications visit our website at http://store.elsevier.com/ © ISTE Press Ltd 2020 The rights of Abdelkhalak El Hami and Philippe Pougnet to be identified as the authors of this work have been asserted by them in accordance with the Copyright, Designs and Patents Act 1988. British Library Cataloguing-in-Publication Data A CIP record for this book is available from the British Library Library of Congress Cataloging in Publication Data A catalog record for this book is available from the Library of Congress ISBN 978-1-78548-190-1 Printed and bound in the UK and US


Electronics are increasingly used in controlled and embedded mechanical systems. This leads to new mechatronics devices which are lighter, smaller and use less energy. However, this mechatronics approach which enables technological breakthroughs must take into account sometimes contradictory constraints such as lead-time to market and cost savings. Consequently, implementing a mechatronic device and mastering its reliability are not always entirely synchronized processes. For instance, this is the case of systems that function in harsh environments or in operating conditions which cause failures. Indeed, when the root causes of such defects are not understood, they can be more difficult to control. This book answers to these problems. It is intended for stakeholders in the field of embedded mechatronics so that they can reduce the industrial and financial risks linked to operational defects. This book presents a method to develop mechatronics products where reliability is an ongoing process starting in the initial product design stages. It is based on understanding the failure mechanisms in mechatronic systems. These failure mechanism are modeled to simulate the consequences, and experiments are carried out to optimize the numerical approach. The simulation helps to reduce the time required to anticipate the causes of these failures. The experiments help to refine the models which represent the systems studied.


Embedded Mechatronic Systems 2

This book is the result of collaborative research activities between private (big, intermediate and small businesses) and public sector agents (universities and engineering schools). The orientations of these research works were initiated by the Mechatronics Strategical Branch of the Mov’eo competitive cluster (Domaine d’Action Stratégique) to meet the need to have reliable mechatronics systems. This book is directed at engineers and researchers working in the mechatronics industry as well as at Masters or PhD students aiming to specialize in experimental investigations, in experimental characterization of physical or chemical stresses, in failure analysis, and in failure mechanism modeling to simulate the consequences of causes of failure and wanting to use statistics to assess reliability. These subjects match the needs of the mechatronics industry. It is organized into two volumes. Volume 1 presents the statistical approach for optimizing designs for reliability and the experimental approach for characterizing the evolution of mechatronic systems in operation. Volume 2 looks at trials and multi-physical modeling of defects which show weaknesses in design, and the creation of metamodels for optimizing designs. Chapter 1 of this volume discusses a methodology for carrying out highly accelerated life tests (HALT) in a humid environment. The principle is to subject the device under test (DUT) to humid air. The ability of the HALT chamber to vary the temperature while applying vibrations enhances the penetration of humidity into the DUT, especially in the case of a failure of water-tightness. Depending on the temperature, this humidity may be in the form of steam or frost on electronic circuit boards and highlight the weaknesses in the assembly or interconnections and failure of water-tightness. Electromagnetic disturbances are also sources of failures. Weaknesses in the design of circuits and components are checked by ensuring the electromagnetic compatibility (EMC) through a characterization of the disturbances produced and the emissions before and after the highly accelerated tests.



Chapter 2 describes how to conduct life tests on high-frequency power transistors under operational conditions. The originality of this test is to follow the performance of the component in an automated way over thousands of hours while applying electric and thermal stresses. The test examines high power components in pulsing mode and tracks deviations by in situ static and dynamic electric characterizations. The life cycle results obtained for high-power laterally diffused metal oxide semiconductor (LDMOS) transistors are presented. Chapter 3 presents the methodology for analyzing failures of mechatronic systems. The advantages and disadvantages of different techniques of opening the resin and ceramic casings are described as well as the precautions to be used to preserve the operational and structural integrity of the component. The technique of detecting and locating defects by photon emission microscopy (PEM) is combined with the optical-beam-induced resistance change (OBIRCH) technique to guide the analysis and determine the cause of the failure. Four case studies of failure analysis are presented: a defective IGBT-power component after the test, a metal oxide semiconductor field effect transistor (MOSFET) damaged by the electrical overvoltage stress test, a GaN technology transistor damaged during reliability testing and a LDMOS component damaged during life test. The results of these analyses are presented, helping to identify the cause of the defects (X-ray analysis, electrical analysis, optical microscopy analysis, thermal analysis, photon emission analysis, transmission electron microscopy analysis). Chapter 4 examines the phenomenon of thermal transfer due to the heat dissipation in a power module and its effects. During the assembly of a mechatronic module, void defects may appear in the interconnection material (ICM). By trapping thermal energy, these defects are potential sources of failure in the module. The goal of this study is to determine the effect of such imperfections on reliability by using the maximum temperature parameters of the chip and the thermo-mechanical constraints at the interfaces as indicators.


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Chapter 5 describes modeling techniques based on the finite element methods to study the effect on electronic circuit boards of temperature cycling, vibrations and electric loads. The electric, thermal and mechanical behavior of a mechatronic structure is presented. Details of two types of coupling of physical phenomena are given. The first is strong coupling: it uses finite elements with all degrees of freedom necessary for an electro-thermo-mechanical study. The second is weak coupling: it consists of decoupling the three physical phenomena, with a sequential calculation. This method is applied to the electronic circuit board of an engine control unit and to a radar power amplifier. Understanding the mechanical behavior of electric circuit boards requires the modeling of several physical phenomena. A multi-physical model is presented which takes into account the interdependencies and interactions between various physical phenomena: electric, thermal and vibratory. Chapter 6 presents a number of methods to optimize the reliability of mechatronic systems. The principle is to combine a finite element numerical model describing the physical response of a mechatronic system with a stochastic model. The results of numerical modeling make it possible to build a meta-model using the response surface. By using this meta-model, the level of control factors is adjusted, the sensitivity of the mechatronic system to sources of variability is reduced (noise factors) and the response of the system is adjusted to meet the reliability objective. Chapter 7 presents a probabilistic approach of aging and fatigue phenomena in solder interconnects caused by temperature cycles. This approach is applied to study the effect of thermomechanical stresses on the reliability of a solder joint in an embedded mechatronic system. It takes into account uncertainties resulting from the random nature of temperature fluctuations, the geometric dimensions of an electronic assembly and the properties of materials. The volume of the solder interconnect material is optimized and the solder joint strength relative to the thermomechanical stresses caused by thermal loads is improved.



Chapter 8 presents a study of the reliability of a radiofrequency power amplifier for RADAR applications using Gallium-Nitride Highelectron-mobility transistors (HEMT) of A1GaN/GaN technology. In order to determine the parameters which impact the reliability of this power amplifier, electric characterizations, aging tests and physical analysis are combined. The results show that temperature is the most significant parameter determining aging and that the gate contact of the HEMT is the most sensitive element. A model of the HEMT component integrating the effect of aging is presented. Chapter 9 presents a method for predicting the reliability of solder joints in Tape-Chip-Scale Packages (T-CSP) that take into account uncertainties in the properties of materials. This approach, which is based on metamodeling techniques, combines FEM simulation, metamodels and Monte Carlo simulation (MCS). The approach consists of building and validating a metamodel. Then, this metamodel is used to perform Monte Carlo simulations. This probabilistic approach is efficient and accurate enough to evaluate and improve the reliability of T-CSPs. The authors would like to thank DGCIS, CR Haute-Normandie, CG 95, CG91, CG78, CRBN, CRIF, CA Cergy Pontoise, MOV’EO and NAE for supporting the project AUDACE.

Abdelkhalak EL HAMI Philippe POUGNET August 2019

1 Highly Accelerated Testing

“Highly accelerated life testing” (HALT) was invented in the USA in the 1980s. In Europe, this method is called both HALT and “highly accelerated testing” (HAT). HALT and HAT are experimental tests which reveal design weaknesses of electronic devices by subjecting them to vibration, temperature and ramp temperature stresses. These tests are best used at technology readiness level 4 or 5 in product development as specified in the international norm ISO 16290. HAT tests take place in a dry environment. Humidity is an important factor of stress which may lead to failures in embedded mechatronic systems [ZVE 13]. This chapter will present an HAT method in a humid environment. The principle is to apply humid air to the device under test (DUT). The HAT chamber makes it possible to vary the temperature rapidly at the same time as vibrations resulting in the humidity penetrating the DUT, especially when the sealing is defective. Depending on the temperature, this humidity takes the form of vapor or ice on the electronic boards and exposes the weaknesses of assemblies, interconnects or tightness defects. The design defects of the electromagnetic compatibility (EMC) circuits are revealed by performing conducted and emitted radiation tests before and after HAT.

1.1. Introduction Recently, there has been a huge increase in mechatronic product developments in spite of the trend to reduce the time to market lead time. Mechatronic products offer more functions and are expected not to fail during the product life time. In order to meet these market

Chapter written by Philippe POUGNET, Pierre Richard DAHOO and Jean-Loup ALVAREZ.


Embedded Mechatronic Systems 2

requirements, it is necessary to identify the maximum number of design flaws, reduce test durations significantly and apply and validate corrective actions. HAT is an experimental approach based on the vibration and thermal stresses which reveal design and technology weaknesses, and operational and destruct limits [HOB 05, BNA 05, MCL 09, IEC 13]. HAT is not used to qualify products but rather to optimize design. These tests are best used at technology readiness level 4 or 5 in product development as specified in the international norm ISO 16290.2013 [ISO 13]. The prototypes are tested at the beginning of product development to reveal defects or flaws when it is still easy and not expensive to modify the design. Correcting these flaws improves product strength to operational and environmental loads and optimizes the design, reducing potential failures in service. As validation testing time is shortened, development cost is reduced, which makes the product more competitive. The reduction in the rate of returned parts during the warranty period improves brand image. Temperature, vibrations and humidity are sources of stress for mechatronic systems [ZVE 13]. These stresses act separately or interact, leading to complex physical chemical electrical mechanisms of degradation or failure. To improve design, these factors need to be analyzed and effective counter measures taken. The principle of HAT is to reproduce these external causes of failure in extreme conditions (maximum stress, reduced test time) in order to understand the physical or chemical causes of failure and assess their respective impact. In this approach, stress is increased step by step to a far higher degree than the levels which are specified in the contract that defines operational functioning. Mechatronic systems are often equipped with protection that prevents these extreme conditions. In this case, this protection should be disabled so that intrinsic functioning limits can be reached.

Highly Accelerated Testing


Discovering the design weaknesses requires a test that can detect whether the mechatronic system has failed to function either partially or totally. At each step, this test characterizes the ability of the system to perform its expected functions. It also measures the critical parameters and diagnoses potential failures. The stresses applied (temperature, vibration) to the areas at risk in the DUT are measured and recorded. The HALT and HAT approaches are designed to find the functioning and destruction limits in a dry atmosphere. The “Super HAT” method goes a step further since it includes humidity. The DUT is subjected to increased humidity levels and this combined with stresses creating vibrations and rapid temperature ramps reveals significant additional weaknesses. These defects would not have been detected otherwise and would have led to failures in operation. It is possible to acquire equipment to test a combination of two of these three factors (e.g. vibration and temperature or temperature and humidity). However, no other highly accelerated test equipment exists that combines all three (vibration, temperature and humidity) except for the Super HAT. 1.2. Load characteristics of the Super HAT equipment Combining a thermal, vibration and humid environment, the Super HAT system produces highly accelerated loads. The temperature range is −100 to 200°C and the maximum ramp used to increase or decrease the temperature is 60°C/min. Random vibrations have 6 degrees of freedom (3 degrees for translation movement and 3 degrees for rotating). The root mean square (RMS) vibration amplitude can be varied from 0 to 50 Grms. The frequency bandwidth of the applied vibrations is 10–10,000 Hz. Maximum relative humidity is 95% at 95°C.


Embedded Mechatronic Systems 2

The Super HAT system can handle devices up to 60 cm × 60 cm with a height of 40 cm and a maximum weight of 50 kg. DUTs are attached to the vibration table by specifically designed fixtures. The pilot system can be used to establish test profiles.

Figure 1.1. Schematics of the Super HAT system

1.3. Description of the Super HAT system 1.3.1. System configuration A HAT chamber and a large volume humidity chamber are used to reproduce the stresses caused by humidity, vibrations and temperature. The chambers are connected by two ducts. To avoid the condensation of humid air, the two ducts are thermally insulated (Figure 1.2). A four-way electrovalve regulates the flow of moisture on the DUT. A fan helps humid air flow between the two chambers.

Highly Accelerated Testing


Figure 1.2. Thermally insulated connection between the two chambers

The DUT is placed in a sealed casing (Figure 1.3) which limits the volume of humid air to ensure an initial humidity ratio of 85% and maintain a humidity rate between 65% and 85% during the test cycles. This insulated casing is fixed to the side walls of the HAT chamber. Airtightness is achieved by using a flexible material which allows random vibrations to be applied in a humid atmosphere. An additional generator is available to maintain the humidity ratio of the test profiles especially when the cycles are repeating.

Figure 1.3. Airtight casing to reduce the volume of moisture

In order to control any rapid increase and decrease in temperature, the casing is connected to the dry nitrogen supply of the HAT chamber. Valves are used to control the dry nitrogen flow.


Embedded Mechatronic Systems 2

1.3.2. Control and monitoring system The control system initiates and controls the functioning of the two chambers. It synchronizes the optimal conditions for the transfer of humid air from the humidity chamber to the casing in the HAT chamber. It records the progressive change of physical test parameters (temperature, humidity and vibration). Low thermal inertia thermocouples, low mass accelerometers and a precise relative humidity sensor (Figure 1.4) are positioned in the two chambers and on the DUT to measure the characteristics of the applied loads (temperature, vibration and humidity).

Figure 1.4. Relative humidity sensor in the casing

The monitoring system allows us not only to record the signals given by the temperature, vibration and humidity sensors positioned in the chambers, but also the signals from the sensors positioned on the critical elements on each DUT (Figure 1.5). Thus, the stresses applied on the DUT are monitored directly. A multichannel data acquisition system records the effective applied stress levels measured by the sensors. The control system detects the resulting failures and malfunction levels that are correlated to the data.

Highly Accelerated Testing


Figure 1.5. Three axis accelerometer and thermocouple positioned on the DUT

1.3.3. Test profiles Different test profiles can be set by the control system. An example of such a cycling test profile is given in Figure 1.6. aaa



100 90 80 70

Relative humidity (%)

Temperature (°C)

60 50 40 30 20 10





























0 -10


-20 -30 -40 -50

Temperature Temperature

Relative humidité humidity relative

Temp Setpoint Temp Setpoint °C ºC

Figure 1.6. Applied test profile: a) temperature setting (°C), b) DUT temperature (°C) and c) relative humidity (%). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

The initial DUT temperature is fixed at room temperature in the casing. This temperature is then decreased to −20°C at a rate of 50°C/min by blowing cold dry nitrogen gas inside. After a 10 min dwell time at this temperature, the DUT is heated to 90°C (setting temperature) at a rate of 50°C/min by this time blowing hot dry nitrogen gas inside. Once the temperature has stabilized, the valves of the nitrogen gas ducts are closed. Moisture is introduced from the second apparatus by activating the four-way valve. Relative humidity reaches a peak value of 80% to finally stabilize at 70%. The moisture dwell time is approximately 8 min. Then, the four-way electrovalve is closed and the electrovalves of the nitrogen gas ducts are opened to obtain condensation of humidity on the electronics. Cold nitrogen is then blown on the DUT to reduce its temperature over more than 3–5 min down to −40°C. The electronics are covered by ice for 10 min. Then, the DUT is heated to 90°C at a rate of 50°C/min by blowing hot dry nitrogen gas. This turbulent hot nitrogen flow decreases the humidity level. After a 7 min dwell time, moisture is reintroduced and a new cycle begins. This test profile is designed to precipitate defects due to humidity. Moisture can seep into the DUT housing due to defects in the sealing joints or connectors, or through the microporous membrane which balances the pressure inside and out of the DUT and which is permeable to water vapor because of its function. The climate inside the DUT results from leakages of the moisture absorbed by the polymer materials used in assembly or potting or from the temperature cycles of the electronics. The preceding test profile is designed to increase the defects due to humidity inside the DUT casing because it is colder and therefore at a lower pressure than the surrounding atmosphere. Reducing the temperature to a very low −40°C ensures that moisture is condensed on the electronic components and on the walls of the casing. At a high temperature, this condensed moisture melts and water interacts with potting and sealing materials to reveal their weaknesses.

Highly Accelerated Testing


1.3.4. Utility operating conditions The Super HAT system functions if the following conditions [HOB 05] are met: – a liquid nitrogen tank equipped with a heating element to produce gas, vents and manual and automatic safety valves; – trucks carrying liquid nitrogen must be able to access an outside refueling line equipped with a valve; – a vacuum-jacketed line to the HAT chamber and a nitrogen gas line; – specific liquid nitrogen pipes (equipped with a manual safety valve), nitrogen gas pipes (equipped with a safety valve and pressure regulator), thermally insulated pipes to extract the nitrogen gas out of the building, a degassing valve between the safety valve and the HAT chamber bayonet and the evacuation pipe for the degassing pot of the liquid nitrogen line; – a set of sensors and alarm systems warning if nitrogen leaks may cause a risk of lack of oxygen for the personnel; – an automatic command system for closing down the liquid and nitrogen gas valves; – an oil-free air compressor equipped with filters and a storage tank; – an electric power supply line (3 phases 400 V, 80 A). Standard performance includes: – a 5,000 l tank for liquid nitrogen; – a non-continuous liquid nitrogen flow rate of 50 l/min at 3.45 bars; – a nitrogen gas flow rate of 8,488 l/h at 1 bar (maximum pressure 4.8 bars, nominal pressure 0.3–0.5 bar); – a compressed air flow rate of 2.27 m3/min at 5.5 bar (this air should be dry − dew point between 1.6 and 3.9°C − filtered at 1–5 µm, oil free, and a 500 l minimum storage tank).


Embedded Mechatronic Systems 2

The moisture chamber requires a 3 phase 400 V 32 A power supply and 10–30 l of distilled water per test. 1.4. Application The Super HAT tests consist of applying step stresses according to the HAT protocol before introducing moisture and experimental combinations of temperature and humidity and variations in temperature, random vibrations and humidity. 1.4.1. Device under test The DUT is a device that controls the compressor of an electric automotive air conditioner (Figure 1.7). Its main functions are to regulate the inside temperature and to control the battery temperature when it is charged at low or high speed. This device must function without failure for a 25,000 h lifetime. The temperature operation specification that needs to be met is from −10 to 100°C. Nominal operation temperature is 85°C. The torque supplying the heat-retaining fluid compressor varies from 1.5 to 5 Nm.

Figure 1.7. The DUT equipped with two thermocouples

Highly Accelerated Testing


The DUT is composed of two electronic boards (a power board and a control board) which are enclosed in an aluminum alloy casing. The power board is coated in resin and is attached to the casing. The casing contains a 350 V High Voltage (HV) direct current connector (positive and negative terminals are labeled HV+ and HV–), a 13.5 V Low Voltage (LV) connector (positive and negative terminals are labeled LV+ and LV–), a Controlled Area Network (CAN) bus and a ball bearing. The casing is designed to be waterproof. To avoid stresses on the casing lid and on the sealing joints, a microporous membrane has been added. This membrane is waterproofed against water but not against steam. In operation, the bottom of the casing is in contact with the cooling fluid which can lead to water condensing on the electronics. The following prototypes are tested: − N°114 (uncoated power board equipped with thermocouples and without lid); − N°112 (resin-coated power board, sealed lid and microporous membrane); − N°120 (uncoated power board, equipped with thermocouples, sealed lid and microporous membrane). 1.4.2. Mounting of the DUT on the HAT vibration table The HAT vibration table is set to vibrate by repetitive shocks from numerous pneumatic actuators which are positioned under the table in specific places. The spectral content is multiaxial and random on a wide frequency bandwidth (from 10 Hz to 10 kHz). However, to avoid damping, the DUT should be attached with flexible fixtures. The DUT is thus mounted on the vibration table with light alloy fixtures and with threaded rods blocked by nuts and locknuts (Figure 1.8).


Embedded Mechatronic Systems 2

3/8 threaded rod

Top Aluminum bar


Bottom Aluminum bar with washer inside

Set of nut and locknut tightened at 10 Nm

Figure 1.8. Mounting of the DUT and the nitrogen pipes

1.4.3. Testing for operating temperature limits To discover the operating temperature limits, it is recommended to remove the protective casing lid to optimize thermal exchanges between the electronics and the nitrogen gas flow. The temperature levels and the thermal ramps activate defects. Prototype N°114 is tested for operating limits. The casing is open and power components are not coated in resin. The test protocol is as follows: at each temperature step change, once the DUT temperature is stabilized, power cycles are activated and functioning is checked. Testing for low-temperature operating limit The DUT functioning is checked at a temperature of 20°C. The temperature is lowered to 0°C and the functioning is rechecked. The temperature is lowered progressively to 20°C at a time. Dwell time at each step is 15 min. Figure 1.9 shows the evolution of the DUT temperature over time.

Highly Accelerated Testing


Figure 1.9. Operating limit at low temperature: DST temperature (°C) and testing time (min)

When power cycles are activated, the temperature of the power board increases from 10 to 35°C depending on the location of the sensors. No defects are revealed until 60°C when testing is stopped. Testing for high-temperature operating limit The DST functioning is checked at 20°C and again at 65°C. The step dwell time is 15 min. The DUT is checked again at 100°C. The temperature is then increased by 10°C steps. No defects are revealed and the test is stopped at 120°C.

Figure 1.10. Operational limit at high temperature: DUT temperature (°C) versus testing time (min)


Embedded Mechatronic Systems 2

1.4.4. Testing for weaknesses due to rapid temperature changes Prototype N°114 undergoes five rapid temperature cycles. The ramp rate is 60°C/min. The thermal cycle extremes are −40 and 105°C (Figure 1.11).

Figure 1.11. Testing for weaknesses due to rapid thermal changes: DST and setup temperature (°C) versus time (min)

The DUT functioning is checked after each cycle at the end of the hot temperature dwell time (105°C). Dwell time is 25 min. No defects are detected. 1.4.5. Testing for random vibration limits Prototype N°112 is tested for vibration limits. Its power board is coated in resin to limit movements and reduce deformations of passive power components caused by vibrations. One objective of this test is to check that this resin protects against vibrations. The vibrations created by the pneumatic actuators are random multiaxial vibrations with a large frequency bandwidth. However, they are not controlled. The only control data available are the RMS amplitude of the signal from the acceleration under the vibration table. In order to obtain the spectral power density applied on the DUT, acceleration sensors are placed precisely where potential weaknesses

Highly Accelerated Testing


have been identified. The location of the accelerometers is shown in Figure 1.12. Monoaxial sensors are positioned on the power capacitor of the power board and at the middle of the control board. A triaxial accelerometer is placed on the casing.

Figure 1.12. Location of accelerometers on control board (carte), power capacitor (capa) and casing

RMS acceleration from DUT sensors (Grms)

Figure 1.13 displays the RMS acceleration measured by the accelerometers of the DUT versus the RMS acceleration obtained from the vibration table sensor. The RMS acceleration of the control board and power board does not vary linearly with the RMS acceleration from the table sensor that is used at a set point. It is thus important to position accelerometers on previously identified potential defects in order to have precise data on the applied power spectral density.

RMS acceleration from table sensor (Grms)

Figure 1.13. Root mean square acceleration (Grms) of DUT sensors versus root mean square acceleration from table sensor (Grms). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

Figure 1.14 displays the RMS acceleration from the DUT sensors versus frequency. These data are necessary to know the power spectral density that is applied locally on the DUT. Channel 4 CARTE Z

Power spectral density (Grms/)2/Hz

Channel 5 CAPA Z

Channel 1 Casing X Frequency (Hz)

Figure 1.14. Power spectral density (Grms2/ Hz) obtained from the DUT acceleration sensors (Y, X, Z), (CAPA) and (CARTE) versus frequency (Hz). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

1.4.6. Testing for limits due to the combined stresses of rapid temperature changes and random vibrations Prototype N°112 is tested simultaneously for rapid thermal changes (from −40 to 105°C) and random vibrations. The thermal ramp is 60°C/min. The random vibration level is increased step by step. These steps (9, 18, 27, 35 and 45 Grms) are shown in Figure 1.15. Several defects are revealed at the last vibration step (45 Grms) and at the temperature of 105°C: – failure of one high-side insulated gate bipolar transistor (IGBT) transistor of the power board (suspected design flaw); – disconnection of the interlock loop (this wire was not mounted using standard production line procedure) assembly;

Highly Accelerated Testing


– disconnection of two capacitances (these were not properly coated by resin, an assembly process defect); – the screw connecting the DUT to the earth was completely removed.

Figure 1.15. Testing for limits due to combined rapid thermal changes and vibrations: DUT temperature (°C) and RMS acceleration versus time (min). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

1.4.7. Testing for limits due to the combined stresses of rapid temperature changes, random vibrations and moisture Prototype N°120 is protected against potential external environment stresses by a metallic casing and sealing joints. Air pressure inside this prototype is regulated by a microporous membrane that balances external and internal pressures when the power board is activated and heats up. To test the limits for moisture, the DUT is subjected to combined thermal and humidity cycles. The temperature cycle varies from −40 to 95°C. The ramp rate is 60°C/min. The temperature dwell time is 15 min. The DUT is exposed to 80% moisture for 6 min (Figure 1.16). No defects are detected.


Embedded Mechatronic Systems 2

Figure 1.16. Testing for weaknesses to rapid thermal variations and moisture: DUT temperature (°C) versus time (min)

1.4.8. Testing for weaknesses to rapid thermal variations, random vibrations and moisture Prototype N°120 is exposed to a combination of rapid thermal variations, moisture and random vibrations to find potential weaknesses to moisture. The temperature cycles vary from −40 to 95°C. The ramp rate is 60°C/min. The temperature dwell time is 15 min. The DUT is exposed to 80% moisture for 6 min. The random vibration level is increased step by step. These steps (9, 18, 27, 35 and 45 Grms) and the DUT thermocouples’ temperature are shown in Figure 1.17. At the end of each high-temperature dwell time when the DUT temperature is stabilized, the DUT functioning is checked. Several defects are revealed at the last vibration step (45 Grms) and at a temperature of 95°C: – the DUT does not start at a high temperature (design flaw); – damage to the quartz oscillator (insufficient space between casing and this component).

Highly Accelerated Testing


Figure 1.17. Testing for weaknesses to rapid thermal variation, random vibrations and moisture: DUT temperature (°C) and RMS acceleration versus time (min)

1.4.9. Test for weaknesses in electromagnetic compatibility functions to thermal stresses There are specific electronic components to ensure EMC. These components must continue to function even after thermal high-amplitude stresses. EMC tests are performed before and after Super HAT tests on prototype N°114, as shown in Figure 1.18.

Figure 1.18. a) Conducted emission test and b) radiated emission test


Embedded Mechatronic Systems 2

These tests are conducted according to the CISPR 25 standard. They characterize emissions conducted on the terminals HV+, HV-, LV+, LV- and vertical and horizontal polarization-radiated emissions. Super HAT tests on prototype N°114 consisted of: – testing for operating limits between −65 and 120°C; – testing for defects by applying five cycles of rapid temperature variations (60°C/min) between −40 and 105°C. Conducted emissions There are significant changes on terminals HV + and HV− at low frequency (frequency less than 10 MHz) and the standard is not respected. There are similar changes on terminals LV+ and LV−. Inspection shows that certain components have changed their characteristics under the applied Super HAT stresses. Radiated emissions Certain components reveal changes which impact the EMC functions. Conducted emission - comparison before and after HAT - LV+ Average values 120



Level (dBµV)






-20 0.1



Frequency (MHz) Before HAT_Proto_114LV+:Average Conduit

After HAT_Proto_114LV+:Average Conduit


Highly Accelerated Testing


Conducted emission - comparison before and after HAT - HV+ Average values 120



Level (dBµV)






-20 0.1




Frequency (MHz) Before HAT_Proto_114 HV+:Average Conduit

After HAT_HV+_proto114:Average Conduit

Figure 1.19. Conducted emissions before (black line) and after Super HAT test (gray line): a) terminal LV+ and b) terminal HV+. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

1.5. Conclusion To be proactive in an evolving market that is driven by innovation mechatronics, manufacturers need to find, process and design weaknesses during the design phase, and also find countermeasures and validate them rapidly. Combining a highly accelerated test chamber and a moisture chamber, the Super HAT reveals functional and destructive limits relative to the three main causes of failure which are temperature, vibrations and humidity. Super HAT tests are relatively short (5–6 days). After a battery of tests, the device under test (DUT) is analyzed and improvements are proposed. The possibility of validating these improvements through tests in extreme conditions leads to achieving design maturity rapidly and still guarantees a higher level of reliability in operation.


Embedded Mechatronic Systems 2

The specific electronic components that ensure EMC must function in operational stresses. The Super HAT reveals changes to certain components which impact the EMC functions and this leads to the EMC standard not being respected. 1.6. References [BNA 05] BNAE R.G., AERO00029 A, Guide pour la définition et la conduite d’essais aggravés, Issy-les-Moulineaux, 2005. [HOB 05] HOBBS G., HALT and HASS Accelerated Reliability Engineering, Hobbs Engineering Corporation, Westminster, CO, 2005. [IEC 13] IEC 62506 Norme internationale, Méthode d’essais accélérés de produits, IEC, Geneva, 2013. [ISO 13] ISO 16290:2013 Norme internationale, Systèmes spatiaux – Définition des Niveaux de Maturité de la Technologie (NMT) et de leurs critères d’évaluation (TRLs), BSI, London, 2013. [MCL 09] MCLEAN H., “HALT, HASS, and HASA explained accelerated reliability techniques”, Amer Society for Quality, 2009. [YAM 97] YAMAMOTO T., Fundamental concepts of physics and chemistry, ESPEC Technology Report no. 4, Tabai Espec Corp., Japan, 1997. [ZVE 13] ZVEI, Robustness Validation Working Group, Handbook for Robustness Validation of Automotive Electrical/Electronic Modules, Frankfurt am Main, Germany, ZVEI Publications, p. 52, 2013.

2 Aging Power Transistors in Operational Conditions

This chapter describes how to perform power microwave transistors lifetime tests in operational conditions. The originality of this test bench is its ability to monitor automatically component performance during thousands of hours and to apply electrical and thermal stresses. This equipment is used to test high power transistors operating in pulsed mode and to record electrical parameter drifts using in situ static and dynamic electrical characterization. The results of different aging processes of laterally diffused metal oxide semiconductor (LDMOS) high power transistors are presented

2.1. Introduction For radar system manufacturers equipment reliability is a major concern. Reliability is therefore taken into account in product design. Radar systems designers use electronic commercial components and must ensure good performance under specific operating conditions. During the product lifetime, power transistors will be required to function effectively in severe stress conditions (high or extremely low temperatures, very short pulse regime, high power, etc.). To ensure that the selected power components maintain a satisfactory level of performance throughout their life, aging tests are conducted respecting the operational conditions of the mission profile. Chapter written by Pascal DHERBECOURT, Olivier LATRY, Karine DEHAIS-MOURGUES, Jean-Baptiste FONDER, Cédric DUPERRIER, Farid TEMCAMANI, Hichame MAANANE and Jean-Pierre SIPMA.


Embedded Mechatronic Systems 2

The test equipment presented in this chapter is used to study the reliability of microwave power transistors for the L frequency band for radar applications. This equipment is designed and built to provoke aging processes in power transistors due to operational pulsed mode use of radar systems [MAA 05]. It can apply stresses above the limits of the component specifications to accelerate the occurrence of failure. Failure mechanisms, however, must be identical to those caused by aging in real use conditions. This chapter describes the design and the realization of the bench. The feasibility of in situ characterization measurements of the component under test (CUT) is developed. Tests under operating radar conditions are conducted over 5,000 h. These tests confirm that the 300 W LDMOS power transistor meet the reliability requirements [LAT 10]. Test results in an overvoltage operation regime show that, after a relaxation period the CUT regains its original characteristics, demonstrating that the degradation phenomenon is not permanent [LAC 11]. Aging tests in a short pulse regime and in extreme cold conditions show that the electrical performance of the CUT is stable [DHE 14]. 2.2. Aging microwave power electronic components under operational conditions 2.2.1. Definition of the specifications for the realization of the workbench The aging behavior of the CUT depends on the operating conditions (voltage, current, power, etc.) and on the environmental conditions (temperature, humidity and vibrations). As the test equipment is designed and built to study the aging process of power transistors, the stresses that are applied reflect the operational conditions and the electrical and thermal parameters are recorded automatically. The equipment specifications are: – an ability to test and monitor several components simultaneously, under operational conditions;

Aging Power Transistors in Operational Conditions


– 24-h operation; – computer control (dedicated software); – supply and precise control of the voltages and currents of the component; – implementation and monitoring of environmental constraints (including temperature); – secure storage of measurement data for performance indicators over several thousand hours; – an ability to impose specific constraints on the radiofrequency component (e.g. introduction of an impedance mismatch or (voltage standing wave ratio (VSWR)), overvoltage, etc.); – radiofrequency characterization of the components before and after aging; – equipment integration and reasonable dimension. The workbench records the suitable electrical parameters of the behavior of the power transistor in real operation conditions. It contributes to the improvement of the reliability of the transistors of different technologies, such as GaN high-electron-mobility transistor (HEMT) technology and LDMOS high power. Concomitantly with the aging stresses, static current-voltage characteristics (I-V) using pulsed S-parameters are recorded [MAA 05]. The bench has four sub-units. Each sub-unit is equipped with a device to connect the component to be aged. Temperature and component supply voltages are fixed. In order to meet the requirements of the operational reliability study of microwave power transistors, several criteria are taken into account: – expansion and adaptation over a wide range of power electric stress tests of the L frequency band;


Embedded Mechatronic Systems 2

– monitoring of the characteristics of the components (static I-V and dynamic S-parameters in situ); – implementation of the extreme cold start and stop condition tests (a need to cool to –40°C in order to test the device under load with thermal cycling). 2.2.2. Applying stresses and measuring aging process parameters The test equipment is designed for high-power microwave transistors that supply 30 A radiofrequency (RF) pulses. The equipment measures static current-voltage characteristics (I-V) in pulse mode and dynamic parameters (reflection coefficients and scattering matrix (S)) at different times without disconnecting the RF connections. The defects caused by aging are thus recorded and the measurement error is minimized. This in situ principle ensures repeatable measurements and eliminates the offset due to the loss of calibration by attaching and removing connectors. Figure 2.1 shows the test bench architecture.

Figure 2.1. Schematic view of the workbench for aging and characterization. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

The heart of the system synchronizes all supply signals: gate voltage, drain voltage, input power level and soleplate temperature. Figure 2.2 provides a control timing for the GaN HEMT transistor.

Aging Power Transistors in Operational Conditions


Figure 2.2. Chronograms for the command of the workbench, drain and gate voltages Vds and Vgs. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

The control unit synchronizes the radiofrequency pulse generator and provides synchronization of the input and the output power measurements of the CUT. Measuring the reflected power denoted as (Pref) is achieved in continuous mode (CW). Each channel has an adjustable attenuator, a coupler for measuring the input power and a circulator for the reflected power of the CUT, measured into a matched load impedance. The amplification of the radiofrequency signal is provided by a two-stage amplifier (A and B amplifiers). Measurement parameters during aging are driven by the heart of the system. This ensures the correct measurements of the currents and the voltages for drain and gate, the input and output powers, the reflected power, and the room temperature, the soleplate and dissipation radiators’ temperature. To characterize the aging of the device, 15 parameters are measured. Table 2.1 shows all of these parameters.


Embedded Mechatronic Systems 2

Signal generation Electrical supply

Drain supply

Parameter measured Vds

High level




60 V

80 mA


–15 V

+15 V

–200 mA

+200 mA



Low level Ids

High level Low level

Gate supply


High level Low level


High level Low level


RF parameters

Recorded temperature

Power supply



Dissipated temperature


External temperature


Peltier power



100 W

Input power

Peak power


50 W

Output power

Peak power


1 kW

Reflected power

Average power


50 W

Table 2.1. Physical parameters recorded by the workbench

2.2.3. In situ I-V static characterization in pulse mode The test bench operates in two phases: the gate pulsed mode aging phase and the static characterization (I-V) and S-pulsed parameters phase. During the static characterization phase, the probes of the pulsed system replace the control power supplies, the latter being dedicated to the aging stresses. However, these sensors must be close to the CUT. To meet these requirements, a circuit is positioned on a mezzanine above the CUT as shown in Figure 2.3.

Aging Power Transistors in Operational Conditions


Figure 2.3. Setting of the CUT on its test mount, constituting a mezzanine setup suitable for the I-V in situ characterization

Figure 2.4 shows a schematic view of the support which is built around the thermal elements (sink, Peltier cell, etc.). The copper soleplate is thermally controlled. It receives the CUT applied through interface circuits. The metal plate screwed to the heat sink provides mechanical support for the various elements of the media. The electronic control is embedded and hidden under the tray.

Figure 2.4. Schematic view of the test mount

During the aging process, the CUT is supplied by two drain probes containing the highest values of capacitors connected to the interface circuit. The gate connection is provided by a cable connecting the support and the interface circuit. Four jumpers placed on the


Embedded Mechatronic Systems 2

interface circuit have the function of connecting the drain supply voltage of the filter capacitors. During the the I-V pulsed mode measurement phase, the CUT is connected to the power supply through the probes of the measuring I-V bench. Figure 2.5 represents the principle of this setup. The jumpers are manually removed to disconnect the filter capacitors. Centering stems limit the mechanical stress on the probes. An example of an I-V characteristic is shown in Figure 2.6 for a 300 W LDMOS transistor. The tests are conducted on a soleplate temperature range from +10 to +80°C. A slight oscillation is observed at low drain voltages Vds and at low temperature. PIV Module Grid Alim

Drain Alim

Grid Pulser (30A) Att.


Drain Pulser (30A)


Load DUT

Figure 2.5. I-V static measurements in pulsed mode principle

Figure 2.6. Static I-V characteristic in pulsed mode for an LDMOS 300 W transistor subjected to different temperatures. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Aging Power Transistors in Operational Conditions


2.2.4. Description of the in situ S-pulsed parameters measures The measurement of pulsed S-parameters can be done on only one sub-unit of the workbench. Technical integration of a vector platform network analyzer (PNA) requires using appropriate couplers. The specific setup developed for this measurement prevents disassembling the RF bench cables. Figure 2.7 illustrates the principle of the measurement. The insertion of the PNA in situ is ensured by suitable switches and by couplers.

Figure 2.7. In situ pulses S-parameters measurement setup

The data acquisition part is achieved by software to exploit the measures over time. The principle adopted is taking a measurement at regular intervals defined by the experimenter, having the advantage of simplifying the process. 2.2.5. Setup developed to study transistor behavior in extreme cold start conditions The objective is to study the behavior of transistors in start and stop mode at extreme temperatures equal to –40°C. The temperature


Embedded Mechatronic Systems 2

variations of the component are derived from the power supplies and electric power changes during operating, as well as changes in ambient temperature. The CUT is brought to a low temperature and undergoes successive starts and stops under load cycles. The tester comprises a temperature self-control device coupled to a thermal chamber. The setup can be used to test power transistors under temperatures ranging from –40 to +125°C with accuracy and stability. Thermal stresses are applied in situ during the aging process. The CUT is supplied by the control unit in continuously mode (CW) and radiofrequency mode (RF). The test mount with its type N microwave cables is disconnected from the Peltier module and is located inside the thermal chamber. The Peltier module is positioned outside the thermal chamber. The thermal chamber is sized to accommodate components of different technologies. Figure 2.8 represents a 300 W LDMOS transistor inside the chamber. The environmental temperature can be varied from +30 to –40°C in 30 min.

Figure 2.8. CUT placed on its test mount in the thermal chamber

The parameters that can be measured in situ during the extreme cold test are: – Pin input power; – Pout output power;

Aging Power Transistors in Operational Conditions


– reflected Pref power; – the gate and drain voltages Vgs and Vds; – the drain current Ids; – the gate current Igs. The question is, can the extreme cold encountered in operational conditions result in transistor performance degradation or destruction? To answer this question, two modes are considered. The first mode relates to a very short pulse of a few hundred nanoseconds with the shortest possible rise time. In these operating conditions, the transistor temperature does not rise. This operation can cause instability of the amplifier, where it can then enter into an oscillation state. Under these conditions, the destruction of the transistor can occur within seconds. The second mode tests the resistance of the CUT to thermal cycles due to self-controlled heating. Two components are tested simultaneously in the thermal chamber. One is continuously supplied (CW), the other in continuous (CW) and RF conditions. The CUT operates in a long pulse mode. 2.3. Application transistors







The results for the 300 W LDMOS technology are presented. Tests conducted on 1 kW LDMOS transistors validate the mezzanine card that is a technical constraint solving to secure the two operating modes (aging and characterization). 2.3.1. Reliability study of microwave LDMOS 330 W power transistor in operational conditions The 330 W LDMOS power transistor is aged in the L frequency band under operational conditions using the workbench on the strip bench L [LAT 10].


Embedded Mechatronic Systems 2

The test bench records several parameters, such as temperature, power, voltage and current. These recordings show that these parameters are stable throughout the three successive periods of the testing phase. For a total of 5,000 h (210 days), a good stability of these parameters is observed. Figure 2.9 shows the stable output power of the component throughout the aging. A power increase is observed on the third run due to the temperature of the soleplate of the CUT set at + 10°C (while it is +80°C for runs 1 and 2).

Figure 2.9. Output power measurement during the 5,000 h aging process. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Gain parameters, power added efficiency (PAE) and drain efficiency (DE) are calculated before and after periods of operation. For the third period (denoted as run 3), the curves in Figure 2.10 show a good stability of the RF parameters of the transistor. Note the observation of a slight variation of the drain current, without affecting the RF parameters, highlighting the injection phenomena of hot carriers. The literature study reveals a phenomenon disappearing with a relaxation period.

Aging Power Transistors in Operational Conditions


Figure 2.10. RF parameters measurement before and after run 3. For a color version of the figure, see www.iste.co.uk/elhami/mechatronic2.zip

After this aging process in operational conditions, variations in electrical parameters are negligible. The test proves that the 300 W LDMOS technology is suitable for the targeted radar applications. 2.3.2. Accelerated aging by overvoltage on LDMOS 330 W transistor Previous tests in operational conditions achieved on LDMOS power transistors for amplifiers were conducted over 5,000 h. They showed no degradation of RF performance, but a slight drift of the static operating point. With the aim of observing the possible damage to higher electric fields, the CUT is aged by gradually increasing the drain voltage Vds [LAC 11].


Embedded Mechatronic Systems 2 Description of the experimental procedure The CUT is aged over 168 h in RF pulse mode operating with a duty cycle equal to 1%. The soleplate temperature is fixed to 10°C, the junction temperature is estimated at 43°C for an output power Pout equal to 250 W. The damages induced by thermal effects are not observable. Only those induced by a high electric field (e.g. hot electrons) can be observed. A period of rest at room temperature (25°C) succeeds each stress period. This relaxation reveals the reversibility of degradation. Then, a new aging period is implemented, the drain voltage Vds is increased after each relaxation period for a period of 168 h. Operational operating conditions are summarized in Table 2.2. Input power Frequency Duty cycle (dBm) 37



RF pulse duration (µs)

Gate voltage Vgs (V)



Drain voltage Temperature Vds (V) (°C) 50 to 56 in successive steps


Table 2.2. Operational conditions of the aging for the CUT

The first drain voltage stress is Vds = 50 V (test A), the second over-voltage stress is Vds = 52 V (test B), the third is Vds = 54 V (test C) and the fourth is Vds = 56 V (test D). During phases of aging and successive relaxation phases, fixed measurements are made regularly at times t = 0, t = 1 h, t = 48 h, t = 96 h and t = 168 h. These measures allow us, on the one hand, to measure the I-V characteristics, and, on the other hand, to measure the output power depending on the input power (Pout-Pin curve). Analysis of the experimental results Test results show that the CUT RF performance does not vary throughout the test except for the static performances such as the drain current Ids which evolves significantly. Figure 2.11 shows that

Aging Power Transistors in Operational Conditions


the Ids current drops during the aging. This evolution is even more important when the drain voltage Vds is high. Test C is not significant because there was no relaxation period between the aging phase tests B and C.

Figure 2.11. Ids drain current during aging process for: A (Vds = 50 V), B (Vds = 52 V), C (Vds = 54 V) and D (Vds = 56 V)

This decrease in drain current Ids also shows up during measures as demonstrated in Figure 2.12. The percentages of variation and the variation of the resistance Ron are calculated and reported in Table 2.3 for drain voltages Vds equal to 50, 52 and 56 V. This degradation mechanism is dependent on the electric field applied to the drain. The decrease in the drain current Ids is a result of the increase in the drain-source on-state resistance Ron. The analysis of the I-V characteristics shows an offset value of the threshold voltage denoted as VTH during aging. The current under the threshold increases during aging especially as the drain voltage Vds is important. However, these changes are not sufficient to generate a change in the transconductance Gm. Despite the evolution of the current Ids, RF performances of the CUT remain stable. This is explained by the fact that the small change in Ids induced a small displacement of the operating point on the I-V characteristic. This


Embedded Mechatronic Systems 2

change is not sufficient to create significant variations of the RF performance.

Figure 2.12. I-V characteristic during an aging process for a) Vds = 52 V and b)Vds = 56 V. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

A: Vds = 50 V

B: Vds = 52 V

C: Vds = 56 V





ΔRon (Ω)



Table 2.3. Drain current variations Ids and on-state resistance Ron

Aging Power Transistors in Operational Conditions


Between the aging phases A and B, C and D, relaxation periods are performed. They prove that the observed degradation is reversible. We conclude that the cause of this degradation is the trapping of electrons in the oxide and/or Si/SiO2 interface and/or the creation of interface states at that interface. Discussion In order to know the origin of the degradation of the drain current Ids and the shift of the voltage VTH, let us consider the equation that governs the threshold voltage: VTH = Φ ms + 2ϕ f +

2ε qN MAX ⋅ 2ϕ f COX



In this equation all parameters are constant. However the charge stored in the oxide under the gate varies. This electric charge denoted as Qox is the sum of the fixed charge in the oxide denoted as Qf and the charge denoted as qtrap induced by electrons which are trapped in the oxide: Qox = Q f +Qtrap


The Qo charge is negative because the threshold voltage VTH decreases during aging. The electrons acquire energy greater than that of the crystal lattice under the action of electrical polarization and therefore the electric field. These special types of charges are referred to as hot carrier injections (HCIs). Figure 2.13 shows the injection mechanism of HCI in the oxide. A part of these, charged with high energy, crosses the Si/SiO2 barrier and becomes trapped in the oxide; they thereby constitute a negative charge. The presence of the trap phenomenon is enhanced by the relaxation phases. Indeed, these tests show that at 25°C (instead of


Embedded Mechatronic Systems 2

10°C during aging) the drain current Ids finds its level before the stress. This degradation phenomenon is, therefore, reversible and a trap phenomenon is plausible. G

Traps unfilled


Oxide P


a) before stress test G





Traps filled Oxide


b) during stress test






D Oxide





c) during relaxation test Figure 2.13. Description of hot carrier injection mechanism – a) the traps state before the aging, b) during aging and c) during the relaxation process

The evolution of the Ids drain current during the aging C process compared to the aging B process strengthens this hypothesis. Between these two periods, no relaxation phase took place. We observed that the decrease in the current Ids is lower for the C process compared to the B process. This result is contrary to the theory because Vds drain voltage for the period C is greater than Vds drain voltage for the period B. The only plausible explanation is that some traps are already filled in during the test B period and only a smaller proportion of hot electrons can be trapped in the oxide during the C period. The analytical modeling of HCI phenomenon A model of hot carrier injection (HCI) based on the trapping of electrons in the oxide under the gate is proposed for LDMOS structures. The change in the drain current Ids versus time shown

Aging Power Transistors in Operational Conditions


in Figure 2.14 follows an exponential distribution, where a, b and c are the fitting parameters and t is time (in seconds), so: I ds = a × exp ( −t / b ) + c


Figure 2.14. Ids drain current evolution in aging process measured and modeled for two drain voltages Vds = 52 V and 56 V

The electrons injected into the oxide create a negative charge. This phenomenon induces a positive charge in the channel. The consequence is a decrease of electron density in the channel and therefore, a decrease in the drain current Ids.The drain current Ids gradient by this mechanism is dependent on the density of electrons injected into the ΔN oxide, so: I ds =

I ds0 1+ Δ N


Comparisons between simulation and measurement results are presented in Figures 2.14 and 2.15. Figure 2.14 shows the variation of the drain current Ids, Figure 2.15 shows the evolution of the on-state Ron resistance which is at the origin of the variation of the drain current. Two drain voltage conditions are explored; Vds = 52 V and Vds = 56 V.


Embedded Mechatronic Systems 2

Figure 2.15. Simulation and measurement of Ron resistance versus time for two drain voltages: Vds = 52 V and 56 V. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

2.3.3. Low temperature endurance tests on 330 W LDMOS transistors The study of thermal constraints is an important issue for radar applications. The new technologies based on power silicon LDMOS transistors have now matured, offering high gain and linearity performance over a wide area. The operational reliability of these components is now recognized for standard mission profiles [LAT 10]. Moreover, the thermal environment of the component directly affects the performance and reliability of radar-type equipment. Studies show the evolution of the electrical characteristics, including increase of the on-state resistance with temperature over the range of 100 and 500 K [KOO 07]. The high power transistors operate with drain voltages exceeding 50 V. The breakdown voltage of the structures is a sensitive parameter studied in the literature [CHA 10], the operation combining a strong electric field and low temperature leads to hot carrier phenomena [CHO 05], limiting the performance of the amplifiers.

Aging Power Transistors in Operational Conditions


Aging involves subjecting the transistor to harsh conditions, combining extreme low temperature start and stop operations and short pulse mode. These operational conditions are critical when the mission profile combines high gain and spectral enhancement of the input signal. The risk that the amplifier oscillates when started is not only due to the component itself, but also to the environment of the transistor placed on the test support plate and to extrinsic components such as the capacitor, which can no longer filter certain critical frequencies. The context of the study This pulsed operating mode can be described as two successive phases [DHE 14]. In the first phase of aging, the pulse is long enough to generate a perceptible self-heating of the transistor. The power generated during the pulse may temporarily cause local temperatures well above the average maximum junction temperature specified by the component manufacturer. The CUT is subjected to high temperature variations. As the control pulse lasts a long time, the spectrum contains no critical frequencies. The frequency spectrum of a pulse duration τ is defined as a cardinal sinus function with peaks which occur as a multiple of 1/τ on the frequency axis. Considering the second phase of aging, the pulse is very short. The transistor does not undergo self-heating under the thermal time constant of much greater duration than the duration of the pulse. The junction then remains at a low temperature when the transistor is placed in a very low temperature environment; the low temperature generates a maximum gain value. The spectrum is rich in harmonics; so in these conditions, the transistor amplifier may enter into oscillatory mode. This oscillation mode, under these conditions, may cause a catastrophic failure, or even destruction of the system in the case of operational radar conditions. Setup description Figure 2.16 shows the test bench meeting the requirements of aging a power LDMOS transistor operating in the L frequency band, in pulse operating mode and at low temperatures.


Embedded Mechatronic Systems 2

Figure 2.16. Workbench dedicated to transistor in extreme cold operating mode

The pulse drives, on the one hand, the microwave source generator operating in continuous mode to generate the CW microwave pulse, and, on the other hand, a second pulse generator for the transistor gate control. The synchronization of the three generators ensures temporal framing of the microwave pulse from the gate signal to limit any overheating of the CUT outside pulse duration. The microwave source delivers a power signal equal to 14 dBm. A preamplifier is used to increase the power signal to 37 dBm. A coupler and a circulator are placed at the output of the preamplifier, they control the input power applied to the CUT and the reflected power. The transistor output power Pout under these conditions reaches 55 dBm in a matched 50 Ohm load. The output power is measured by a microwave probe, the drain Vds signal is monitored by an oscilloscope with a bandwidth equal to 6 GHz. The Vds drain voltage is continuously stabilized at constant value, the voltage is maintained at 50 V. The gate voltage is set to 2.25 V defining the operating point of the amplifier in class B. The drain current Ids is controlled by the oscilloscope by a 0.047 Ohm shunt resistance. To meet the requirements of this test, the transistor mounted on its support is placed in a thermal enclosure cooled to a temperature equal to –40°C. A thermocouple is inserted under the CUT test carrier closer to the flange to control the average temperature during the aging.

Aging Power Transistors in Operational Conditions

45 Thermal behavior study of the transistor The component under consideration is a commercial transistor with power rating 300 W, scheduled for operation in the L frequency band with a drain voltage Vds equal to 50 V. The manufacturer guarantees for these biased conditions a power gain equal to 18 dB and an efficiency equal to 60%. I-V static measurements are conducted on the component through a test pulsed bench to overcome the self-heating of the transistor. It is placed on a Peltier cell, the temperature is set to a variable range extending between 0 and +100°C. The recording of input and output I-V characteristics facilitates a complete study of the CUT. The dynamic behavior is studied over a temperature range extending from –40 to +40°C. To carry out this measurement, the component is positioned in the thermal chamber. Electrical parameters such as voltage, current, input power, reflected and output power are recorded at each 10°C step. The analysis of the results shows an increase of the output power Pout, the gain, the efficiency and the drain current Ids as the temperature decreases. The gain variation is equal to 0.74 dB over the full 80°C range which matches the theoretical data provided by the manufacturer. Table 2.4 shows the electrical parameters’ variations at three temperatures (–40°C, 0°C and +40°C). Temperature °C

Pout (W)

Pout (dBm)

Power efficiency (%)

Gain (dB)
















Table 2.4. Electrical parameters measurements for three different temperatures


Embedded Mechatronic Systems 2 Aging in pulse operating mode: results and analysis During the pulse, the Pout output power measured is equal to 54.48 dBm, or 280 W for an ambient temperature equal to 25°C. The calculated efficiency is beyond 60%, for an Ids drain current during the pulse equal to 9.20 A. The reflected power is equal to 0.67 W. By applying to the gate a pulse of duration equal to several hundred microseconds, we measure in the time domain the ΔIds resulting drain current drop caused by the self-heating of the CUT. By a method of extraction of constant time, we found the τ value of the thermal time constant of the entire amplifier in its environment is equal to 200 µs. The decrease of the drain current according to an exponential law corresponds to a very rapid rise in the junction temperature of the transistor. Considering this value, we feel that for a pulse duration equal to 1,000 µs (or 1 µs), the temperature of the junction has reached its maximum value and stabilized. The estimate of this value is paramount, it will allow us to set the test parameters for the aging process. For long duration pulse operating modes, we choose a duration of 1,000 µs, a pulse period of 1 s and a duty ratio of 0.1% so that the junction temperature will drop to –40°C between two pulses. Long pulse operating mode This test is conducted at a temperature of –40°C by setting the pulse width denoted as Pw to a value equal to 1,000 μs, and a duty cycle equal to 0.1% allowing the temperature rise of the junction and complete cooling between two successive pulses. In this operating mode, the component is stressed by thermal shocks caused by self-heating, at a rate of one cycle per second, or 3,600 cycles per hour. No significant change in electrical performance was found over an aging period of 24 h. This is equivalent to a number of start and stop cycles equal to 86,400. The transistor resists the long pulses leading to its self-heating. No significant variations of the electrical characteristics are observed.

Aging Power Transistors in Operational Conditions

47 Short pulse operating mode A microwave pulse is applied to the input of the component at each second. The duration of the pulse is gradually reduced starting from 100 μs down to 100 ns to prevent any risk of the amplifier oscillating. The pulse duration is short and well below the thermal constant of the amplifier. The transistor does not heat up and undergoes stop start cycles at extreme low temperature. The gain remains at a maximum value. The pulse is short and the input signal spectrum is rich in harmonics. Figure 2.17 represents the output signal Pout for a 900 ns pulse duration and the gate control pulse signal leading to the pulse microwave signal. For minimum pulse conditions, set at 100 ns, the component undergoes start and stop cycles at extreme cold temperature for a period of 10 h corresponding to 36,000 cycles. No significant variation in performance and no catastrophic failure are observed.

Gate control pulse framing the hyper pulse

Figure 2.17. Gate control and microwave signal for a 900 nanosecond duration. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip Results analysis for extreme cold robustness measure The power LDMOS transistor has undergone extreme cold aging with two different pulse ways. For the aging in long pulse mode, thermomechanical problems did not reveal failures for a series of


Embedded Mechatronic Systems 2

starts spread over a total period of 24 h at a rate of one cycle per second. For the study of aging in short pulse mode for a period fixed at 100 ns, at a temperature of –40°C, the transistor showed no failure. These extreme temperature aging tests suggest several perspectives. First, a search for the precise value of the temperature reached by the junction in long pulse mode at –40°C is possible – static I-V measurements without self-heating could be exploited for this purpose. In the second step, component cooling between two successive pulses, it would be interesting to confirm these initial results by continuing the long pulse mode aging over longer periods in order to highlight the thermomechanical phenomena. Simulations or measurements of deformation are useful to complete this analysis. 2.4. Conclusion This test bench makes it possible to characterize the lifetime of power transistors used in radar applications under operational conditions. The frequency bands used are L and S bands. The maximum power of the components under test reaches 1 kW during the pulse. Variable pulse durations within frames make it possible to reproduce the real operating conditions of the devices. Start and stop severe conditions are reproduced at very low temperatures down to –40°C. The test equipment allows static I-V and dynamic S-parameter characterizations in pulse mode. These characterizations are performed in the vicinity of the component without removing or attaching the RF connectors, thus avoiding any need for calibration after each series of measurement during the aging process. I-V pulse mode current levels reach 30 A. Therefore high power components can be tested. The studies presented in this chapter validate the performance of embedded components in operating conditions. The reliability of the power transistors tested in these conditions is thus guaranteed.

Aging Power Transistors in Operational Conditions


2.5. References [CHA 10] CHANG Y.H. et al., “Optimization of high voltage LDMOSFETs with complex multiple-resistivity drift region and field plate”, Microelectronics Reliability, vol. 50, no. 7, pp. 949–953, 2010. [CHO 05] CHOU Y.C. et al., “Hot carrier reliability in GaAs PHEMT MMIC power amplifiers”, IEEE 43rd Annual International Reliability Physics Symposium, San Jose, 2005. [DHE 14] DHERBECOURT P. et al., “Realization of a dedicated bench for reliability and robustness studies of high LDMOS power transistors”, International Journal of Microwave and Optical Technology, vol. 9, no. 6, pp. 429–436, 2014. [KOO 07] KOO Y.S. et al., “Analysis of the electrical characteristics of power LDMOSFETs having different design parameters under various temperature”, Microelectronics Journal, vol. 38, pp. 1027–1033, 2007. [LAC 11] LACHÉZE L., LATRY O., DHERBECOURT P. et al., “Characterization and modeling of hot carrier injection in LDMOS for L-band radar application”, Microelectronics Reliability, vol. 51, no. 8, pp. 1289–1294, August 2011. [LAT 10] LATRY O., DHERBECOURT P., MOURGUES K. et al., “A 5000 h RF life test on 330 W RFLDMOS transistors for radars applications”, Microelectronics Reliability, vol. 50, nos 9–11, pp. 1574–1576, 2010. [MAA 05] MAANANE H., Etude de la fiabilité des transistors hyperfréquences dans une application RADAR en bande S, PhD thesis, University of Rouen, 2005.

3 Physical Defects Analysis of Mechatronic Systems

This chapter presents the failure analysis methods used for mechatronics systems. The advantages and disadvantages of resin and ceramic casing opening methods are described as well as the use precautions which are required to maintain the functional and structural integrity of the component. The technique of detecting and locating defects using photoelectron microscopy (PEM) is combined with the optical-beaminduced resistance change (OBIRCH) technique to provide direction to the analysis and determine the cause of the failure. Examples of analysis of physical defects caused by stress tests are given. These defect analyses are carried out on complete mechatronic systems and individual components. Four failure analysis cases are studied: an insulated gate bipolar transistor (IGBT) power component broken down during highly accelerated testing, a metal oxide semiconductor field effect transistor (MOSFET) transistor damaged by electrical overvoltage stress testing, a component of Gallium Nitride (GaN) technology damaged during reliability testing and a laterally diffused metal oxide semiconductor (LDMOS) component damaged during life test. The results of the various defect analyses leading to defect localization are presented (X-ray analysis, electrical analysis, optical microscopy analysis, thermal analysis, photon emission analysis and transmission electron microscopy (TEM) analysis).

3.1. Introduction The objective of the failure analysis of a defective microelectronic component is to determine the physical and chemical failure mechanism(s) leading to a specific failure mode. The failure analysis method is based on systematic observations comparing structures Chapter written by Christian GAUTIER, Eric PIERAERTS and Olivier LATRY.


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before and after test; its goal is to establish a link between electric performance degradation and the physical mechanisms leading to this degradation. This approach requires that the stresses applied during testing do not destroy the component. It is also requires the observed losses in electrical performance to be irreversible and to lead to detectable physical modifications. To respond to the challenges caused by the electronic component miniaturization trend, a wide variety of failure analysis techniques now exists. These techniques are used according to the failure observed or to the likely type of failure to provide electrical and physical characterizations or defect localization. To localize the failure on the chip of the component, nondestructive analysis tools (X-ray radiography and tomography, acoustic microscopy and time-domain reflectometry) are used before opening the component casing. Depending on the materials used in the component package, the component casing is opened chemically, mechanically or thermomechanically [KER 14]. Photo emission microscopy (PEM), optical-beam-induced resistance change (OBIRCH) and thermally induced voltage alteration (TIVA) are also used to identify the defects. Four failure analysis cases are studied: an IGBT power component broken down during Highly Accelerated Testing, a MOSFET transistor damaged by electrical overvoltage stress testing, a GaN technology transistor damaged during reliability testing and a LDMOS component damaged during life test. For each case study, the stresses applied to the system or the component during testing are described and the results of the various analysis techniques used are presented. Physical characterization is produced using optical microscopy, digital holographic microscopy [DOM 13]. For observations on a nanometric scale scanning electron microscopy (SEM), transmission electron microscopy (TEM) and atomic force microscopy [DEL 11] or focused ion beam (FIB) are used.

Physical Defects Analysis of Mechatronic Systems


This chapter describes the main experimental techniques for observing, identifying and analyzing defects in mechatronic systems. Examples of physical defects analysis caused by step stress tests or reliability tests are given. Failure analyses are done on mechatronic systems and on single components which are tested and aged individually. Four case studies of failure analysis are examined: an IGBT power component defected after the strength test, a MOSFET transistor switch damaged by the electrical surge test, a component of GaN technology damaged after the reliability test and an LDMOS test component also damaged after the reliability testing. For each case study, the constraints applied to the system or the component are recalled and the results of the various analysis techniques used to identify the defect and establish the root cause of the failure are presented. 3.2. Equipment and methodology for analyzing failure in mechatronic systems The analysis of the physical mechanisms responsible for failure requires cutting-edge methods which are able to detect defective areas and ensure detailed investigations with high-resolution levels. 3.2.1. Opening ceramic and resin casings Two packaging techniques are used for the electronic chips of this study: – the chip is coated with resin (D2PAK package and GaN45W package); – the chip and its circuit board are located in a ceramic casing (LDMOS package).


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Casing opening techniques should maintain the operational and structural integrity of the component. Depending on the materials and the size of the samples, three casing opening techniques are used: – mechanical opening which uses a controllable micromilling machine. It is especially suitable for partial openings at the front and back where other techniques are not viable; – laser opening (Figure 3.1(a)) which removes the resin around the electronic chip but requires particular care around the wiring (cutting risk) and the silicon (loss of functionality if the laser touches the silicon); – opening using the chemical method (Figure 3.1(b)) consists of firing jets of concentrated acid onto the case in order to completely or partially remove the resin.

Figure 3.1. a) Laser ablation machine and b) chemical cutting machine

Opening using the chemical method is very effective for plastic cases, but is not suitable for opening ceramic cases. For this type, laser ablation remains the technique of choice (the chemical method is ineffective and the mechanical approach too laborious). The use of the laser is simply a preliminary step in opening the case. It is generally combined with finishing using chemicals or plasma. Opening the cases is a delicate stage. Many tests and experiments are necessary to find the optimal settings, given that each component requires its own approach.

Physical Defects Analysis of Mechatronic Systems


It is often necessary to know the position of the electronic board in the casing beforehand as well as the position of the bondings. This information can be obtained using X-ray imaging. For a plastic D2Pack case, a combination of laser and chemicals is used to access the electronic board and particular care is taken with regard to the position of the bondings with the laser before opening. When opening a plastic GaN45W case, after using a combination of laser beam and chemicals, small balls of glass can be observed at the component’s interdigital structures. These balls of varying size appear to come from the resin’s filling material. They can cause the component to malfunction. To avoid such particles from forming, laser ablation is not used during the preopening stage, but rather a chemical cutting process preceded by a mechanical polishing of the resin. The opening of power components LDMOS300W is carried out exclusively by laser ablation. This opening procedure consists of weakening the outer casing along two lengths as shown in Figure 3.2. Thereafter, a mechanical method is used to delicately separate the component from the case. To avoid damaging the bonding with the laser (Figure 3.2(a)), the thickness of the ceramic to be removed is ascertained using X-ray microscopy (Figure 3.2(b)).

Figure 3.2. Opening of power transistor LDMOS 330W by laser ablation. a) Deterioration of the bonding heads following the use of the laser. b) X-ray image to ascertain the thickness of the ceramic to be removed. c) Successful opening


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The characteristics of laser and chemical opening equipment are summarized in Table 3.1. Laser opening

Chemical opening

Technical characteristics

Nd:YAG laser diode 1,064 nm, 10 W pulsed Q-switch Duration of pulses < 110 ms at 5 KHz Diameter of laser beam 1.5– 1.8 mm Maximum power 8 W Marking zones 112 × 112 mm

Mixture of sulfuric acid/nitric acid Cutting controller Fixed cutting head made up of SiC Pneumatic electric pump

Variable parameters

Laser power Q-Switch frequency Duty cycle Scanning speed Spot size

Volume of acids Cutting method (vortex or pulsed) Temperature Reaction time Mixture of acids

Table 3.1. Main characteristics of opening equipment

3.2.2. Equipment and technique for detecting and locating defects When it is combined with the laser stimulation technique OBIRCH, PEM is effective at detecting and locating defects (Figure 3.3).

Figure 3.3. Confocal IR photoelectron microscope with OBIRCH. A double-sided probe system is fitted to this equipment

Physical Defects Analysis of Mechatronic Systems


The detection of photons requires direct access between the emitting area and the detection system. Metallic covering can disrupt or obstruct the signal being emitted. When laser stimulation is used, the area stimulated must be able to be heated. Conducting plates (metal) limit the detection of variations in the current and reduce the system’s detection sensitivity. There are a number of ways to solve this problem: – remove the metal layer while retaining the electronic functionality of the component; – carry out a 90° analysis to maneuver around the metal layers; – use infrared thermography as an alternative to PEM and laser stimulation. Examples of images taken with confocal microscopy of GaN transistors are shown in Figure 3.4. In the case studies, since the IGBT and MOSFET underwent over voltage stress (OVS), the PEM or OBIRCH analysis could not be carried out because the components had been destroyed by this test. The characteristics of the confocal microscope are as follows: – detector: SI-CCD camera – high-sensitivity next-generation Hamamatsu C11231; – motorized lens rotation including 0.8×, 5×, 20×, 50× optimized 1,300 nm, and 100×; – probe system: PM8 DSP SUSS-microtek front and back fitted with four probe holders; – option IR-OBIRCH: laser 90 mW 1,300 nm; the sensitivity limits of the amplifiers are summarized in Table 3.2; – option lock in 50 and 5 KHz; – option dynamic analysis by laser stimulation (DALS); – option confocality: front side imaging; – spatial resolution of the order of micrometers.


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Figure 3.4. a) Confocal image acquired from the front of the GaN45W, after extraction of the electronic chip (resin case); the image is taken through the silicon without prior polishing. b) OBIRCH image of a GaN transistor showing variations in the current measured after TLS. The variation in the contrast (white line) highlights the presence of a defect. c) Superimposed profile image of the electronic chip and the signal of emitted photons at a polarization of Vgs= −1.62 , Vds = +20 V and Ids = 100 mA. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Type of amplifier

Constant voltage

Constant current

High-sensitivity constant voltage

Applied voltage

10 mV to 10 V

10 mV to 10 V

10 mV to 25 V

Maximum current

100 mA

100 mA

100 µA

Minimum detectable

10 nA

10 nA

10 pA

Table 3.2. Characteristics of the three amplifiers fitted to the PHEMOS 1000 for OBIRCH

Physical Defects Analysis of Mechatronic Systems


3.3. Analysis of physical defects 3.3.1. Analysis of an IGBT component after a highly accelerated test Failure analysis is carried out on the IGBT IRGS4062DPbF component (IGBT with ultrafast soft recovery diode). This component is fitted to the power board of an electronic control unit (ECU) of an air-conditioning compressor (Figure 3.5(b)). This electronic board controls the speed variations of a synchronous machine and a three-phase power inverter. The power board is made up of six IGBT power transistors (Figure 3.5(a)).

Figure 3.5. Power board (SMI) and ECU Test conditions and analysis Highly accelerated tests (HATs) are carried out on the ECU to highlight the design defects. The constraints which bring about the failure of the ECU are a combination of random vibrations (GRMS), rapid temperature variations and power cycles (Figure 3.6). The electrical failure occurs at the final level of vibrations (45 Grms) at a temperature of 105°C. A measurement of electrical continuity shows short-circuiting in the IGBT in the first transistor (HS1). The defects


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caused by vibrations are the disconnection of the two conductors with electromagnetic compatibility (EMC) and the loosening of a screw holding the FR4.

Figure 3.6. Profile applied during the HAT test

The environmental conditions of the test are as follows: – temperature stages of 20 min; – temperature changes of ±60°C/min; – almost nitrogen-saturated approximately 10%.




The conditions of the electrical tests are as follows: – 350 V on the HV bus; – 10 A RMS virtually sinusoidal at output (three-phase RL load in a star configuration) corresponding to a peak current of 14.1 A in the IGBTs; – electrical frequency of the current at a load of 100 Hz; – switching frequency of the IGBT of 10 kHz; – duty cycle change 35%–65%.

Physical Defects Analysis of Mechatronic Systems

61 X-ray analysis X-ray analysis reveals no defect in the transistor, apart from the imperfections in the interconnection material (Figure 3.7). Imperfections are observed in other components. No anomaly differentiating the failed HS1 transistor from other IGBT components is visible in the X-ray analysis.

Figure 3.7. X-ray view of HS3 IGBT in the SMI: a) normal mode and b) relief mode Electrical analysis In a static mode, the current–voltage (I–V) measurements confirm that the HS1 transistor has short-circuited and that transistors LS1, LS2, LS3, HS2 and HS3 are behaving normally. To produce characterizations in dynamic mode, a switching signal of 10 kHz (0–8 V) is applied to the gate. A resistance of 10 kΩ is placed between the collector and the 20 V energy output. To verify the switching time Ton and Toff, the collector voltage is measured with a high impedance probe. Figure 3.8 shows the switching of transistors LS1, LS2 and LS3. The ON switching time of LS1 is twice as long as for LS2 and LS3. The OFF switching time is also different. The switching behavior of transistor LS1 can generate undesirable voltages as well as peaks in current over the other transistors HSx and LSx during the transition phase at high power (application mode).


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LS1: Timescale 0.5 μs/div

LS1: Timescale 0.1 ms/div

LS2 and LS3: Timescale 0.2 μs/div

LS2 and LS3: Timescale 2 μs/div

Figure 3.8. Switching time: gate signal (light) and collector signal (dark). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip Analysis with optical microscope Laser opening is carried out on the defective transistor HS1 and transistor LS1. A fusion linked to the transistor’s emitter is observed (Figure 3.9). No visible defect is observed on the LS1 transistor.

Figure 3.9. Laser opening of HS1 component

Physical Defects Analysis of Mechatronic Systems

63 Thermal analysis A thermal gradient on the power board (SMI) and different breakdown voltage characteristics according to the temperature applied for the transistor and the flyback diode may be the root cause of the failure observed. To check each hypothesis, an infrared mapping of the SMI is carried out with the help of a thermal camera as well as a characterization depending on the temperature of the breakdown voltage of the transistor and the flyback diode. Infrared mapping of the SMI Six resistors in the D2Pak case are fitted to the SMI board instead of the IGBTs. The SMI is embedded in the case which is then fixed to the electric motor. The components then interact thermally with the motor and the transfer fluid in the loop. The motor is supplied by a remote variator. A continuous current crosses the resistors simulating the heat loss of power transistors. The photograph in Figure 3.10, taken using an infrared camera, shows an ECU casing fitted with the SMI. The SP01 resistor corresponds with the HS1 transistor. The SP06 resistor is relatively hot, but is poorly soldered. The temperature difference between the resistors is approximately 2–3°C (Figure 3.10). The highest temperature is at transistor HS1.

Figure 3.10. Infrared mapping of the SMI. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2 Characterization of breakdown voltage according to temperature After electrically isolating the transistors and flyback diodes of the two IGBT components, I–V measurements are taken to ascertain their breakdown voltages. I–V measurements are taken at 105, 60, 80 and 25°C (Figures 3.11 and 3.12). The current is fixed at 70 µA and breakdown voltages are measured at 10 µA. Although the location of the HS1 component is the hottest part of the SMI, the breakdown voltage of the transistor always remains higher than that of the diode. The fusion of the HS1 component is therefore not linked to the temperature gradient observed on the SMI.

Figure 3.11. Temperature evolution of I–V curves: a) flyback diode and b) transistor

Figure 3.12. Temperature evolution of breakdown voltage of the transistor and diode

Physical Defects Analysis of Mechatronic Systems


3.3.2. Analysis of a MOSFET component after electrical surge tests The MOSFET IRFR3710ZPbF component which is embedded in a D-pack case is used in switching circuits for a direct current (DC)–DC supply. This component is examined using the OVS test. To view the OVS marks, a construction analysis is carried out. Knowledge of the geometry and composition of the D-pack case helps in opening it correctly. After it is opened, the OVS marks can be characterized using optical microscopy. Construction and opening analysis The construction analysis is then carried out by optical inspection (Figure 3.13) and by X-ray inspection (Figure 3.14).

Figure 3.13. Optical inspection: a) from above and b) from below

Figure 3.14. X-ray inspection: a) normal mode and b) improved contrast


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Figure 3.15. X-ray inspection: zoom on the part containing the electronic board, a) normal mode, b) relief mode and c) 90° view

The absence of a visible wire in the X-ray image and the lack of a “bump”-type connection indicate the probable presence of an aluminum wire. The thickness of the plastic can be estimated from the X-ray image to facilitate laser and chemical opening.

Figure 3.16. Case opening: a) overview and b) connection wires

Figure 3.17. Cross-sections: a) after burn-in before transistor and b) after burn-in to the level of the transistor

Physical Defects Analysis of Mechatronic Systems

67 Analysis of failure by optical microscopy An OVS mark is observed close to the contact gate (Figure 3.18).

Figure 3.18. OVS analysis by optical microscopy

Opening the case after the OVS test often reveals major fusions: a supplementary TLS-/OBIRCH-type analysis is useless since it provides no additional information. 3.3.3. Analysis of a GaN50W–HEMT component after the reliability test Characteristics of the amplifier and experimental aging conditions The study examines commercial components with AlGaN/GaN high-electron-mobility transistor (HEMT) technology in ceramic casings. The conditions of the aging tests are as follows: – Vds0 = 45 V; – Idq = 0 mA; – 3 GHz operational frequency; – 20°C base temperature; – pulses radio frequency (RF) of 450 µs with 3 ms periods; – duration of 700 h.


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After 700 h of testing, the electrical performance of the amplifier is modified. The following can be observed: – a decrease of 10% in output power; – a decrease of 6% in the average drain current; – a decrease of 6% in PAE; – an increase of 150% in the gate current. The following can be measured: – a 6% decrease of the Gm in the area of the bend/pinch of the characteristic Id-Vds; – an 8% increase of the on state drain source resistance Rds on. The pinch voltage is moved toward negative values (of approximately 30 mV) giving rise to a greater drain current in the area of saturation. To assess if failure mechanisms are reversible or not, the I–V characteristics of the aged transistor are measured after a 4,000 h rest period at room temperature. In this rest period, the component is not polarized, the component casing is opened and the surface of the chip is illuminated [FON 12a]. The Ig–Vdg characteristics of the diode show up a reduction of the inverse gate current. The gate current is measured close to its nominal value after a 4,000 h rest period under illumination. Usually, this phenomenon is combined with the movement of the pinch voltage (Pv) toward positive values. Figure 3.19 shows a period in which the Pv moves toward increasingly negative values after the application of the tests and period of rest and light. A decrease in the potential barrier of 0.1 eV can also be noted.

Physical Defects Analysis of Mechatronic Systems


Figure 3.19. Deterioration of Pv (Vp0 is the initial value): the movement of Pv toward negative voltages c) is caused by a combination of irreversible a) and reversible mechanisms b). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

This deterioration in Pv (Figure 3.19(c)) may signify: – a reversible mechanism caused by loads being trapped (Figure 3.19(b)); – an irreversible mechanism related to the physical deterioration of the transistor (Figure 3.19(a)). After these electrical characterizations, an analysis of the physical deterioration is undertaken. Photoelectron microscopy PEM is a non-invasive method for locating defects. It is based on the emission of photons from radiative recombinations of electron–hole pairs between the valence and conduction bands, or the intermediate energy levels related to the presence of impurities. It can also come from intraband transitions related to the relaxation of load carriers which acquired a large amount of energy.


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The objective of PEM is to detect a deterioration in a component through modifications in the electroluminescence signature between an element not subject to constraints (which we will call a control) and an element constrained to certain conditions. The components are polarized by continuous voltage. The signal is acquired due to a high-sensitivity CCD sensor cooled to −70°C in a detection window of wavelengths between 400 and 1,100 nm. Figure 3.20 shows the signature obtained at the emission of photons for the control component and the component subject to constraints. The images are acquired with the same exposure time and color range for identical polarization conditions (Vds = 20 V and Ids = 100 mA).

Figure 3.20. PEM images for the two GaN50W components. The polarization conditions are Vds = + 20 V and Ids = 100 mA. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

On the control component, the distribution of emitted photons is relatively uniform along the 80 fingers of the chip. Focusing on one individual finger (Figure 3.21) reveals that the optical signal is

Physical Defects Analysis of Mechatronic Systems


localized in the area between the gate and the drain where there is only a passivation layer and no metallic layer. The scanning electron microscope micrography (Figure 3.21(b)) reveals a field plate covering the source and the gate. At higher resolution (Figure 3.21(c)), the emission of photons is not observed as being continuous along the gate in the gate–drain area, but as a series of luminous spots. This may be caused by trapping mechanisms or by hot electron generation as is the case with AlGaN/GaN heterojunction HEMTs.

Figure 3.21. Correlation between a) optical microscopies, b) scanning electron and c) photoelectron ×100 in order to identify the photon-emitting areas on the transistor. D: drain; G: gate; F: field plate; S: source. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

On the stressed component, the observed distribution of the signal on the chip is different. The signal level is high at the center of the chip and no emission is detected along the edges. This signature indicates an uneven degradation. As the emitted luminous intensity is due to the electrical field and to the current flow, it is likely that the drain current distribution is uneven. According to [FON 12b] Vp voltage is more negative at the center of the chip than at its edges.


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On multi-finger components, there are thermal interactions between gates. These interactions lead to a localized temperature increase and the temperature maximum is at the center of the chip. This leads to different transient temperatures for each finger and different electrical behavior. The thermal stress applied on the fingers varies with their location. The fingers are thus damaged at different levels. The PEM signatures reveal two areas of interest. These areas are studied in closer detail by TEM. Transmission electron microscopy analysis Three TEM blades are prepared by the “life-out” technique using a Zeiss scanning electron microscope fitted with a FIB (Figure 10.22). The first blade is extracted from the central part of an element in the control component, as shown in Figure 10.23 (TEM-1). The other two TEM blades are extracted from the edge (TEM-2) and the center (TEM-3) of the component subject to constraints [LAT 13]. The electrical results suggest that the alteration in the Schottky contact is responsible for the component’s loss of performance. Particular attention is given to the condition of this interface in electron microscopy. The observations are conducted with a JEOL JEM ARM 200F HR TEM microscope (Figure 3.22). The analysis is carried out using high-resolution scanning TEM (STEM) high-angle annular dark field (HAADF) imaging with a camera 8 cm in length and a probe size of 0.1 nm. Elementary composition is carried out by EDS spectroscopy with a probe size of 0.2 nm. Figure 3.23 shows the elementary chemical composition of the Schottky contact on the TEM-3 blade of the stressed component. It is made up of layers of gold (Au) (gate contact), nickel (Ni), AlGaN and GaN. At the Ni/AlGaN interface, a thin layer of nickel oxide (1 nm) is observed on both components (control and constrained). The effect of this oxide with higher resistance is to decrease the leakage current of the gate and increase the height of the barrier.

Physical Defects Analysis of Mechatronic Systems


Figure 3.22. a) Scanning electron microscope with double-column MEB/FIB Zeiss NVision 40. b) High-resolution transmission electron microscope and analytical configuration JEM ARM 200F Jéol

Figure 3.23. Elementary composition acquired by EDS of the Schottky contact on blade TEM-3 (stressed component). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Close analysis of the Schottky contact reveals modifications before and after the application of the constraint. On blade TEM-1, the layer of Ni with a thickness of 20 nm shows a clear interface with the layer of Au (Figure 3.24, Tem-1). The deposit of Ni along the length of the gate is not regular, especially at the drain side of the gate (Figure 3.24, Tem-1). After the application of the constraint, the layer of Ni is highly altered (Figure 3.24, Tem-2 and Tem-3). This is displayed by greater undulation and more interrupted limits with the Ni/Au interface. Comparing blades TEM-3 and TEM-2, it can be noted that the deterioration of the Schottky contact is more significant on blade


Embedded Mechatronic Systems 2

TEM-3 and correlate with the intensity of the PEM signature. On blade TEM-3, the variation in the thickness of the Ni layer ranges from 10 to 20 nm, which means that this layer has partially been dissolved, or in places has completely disappeared. The Schottky contact which is initially made up of Au/Ni/NiO/AlGaN evolves into Au/NiO/AlGaN. There is a change in the Ni/NiO interface, while the NiO/AlGaN interface remains intact. These observations using an electron microscope correlate perfectly with the heightening of the barrier by 0.1 eV and the fall in Pv, as shown previously by the electrical tests [FON 12a]. Furthermore, the more significant diffusion of Au for the central elements is in line with the channel temperature distribution on the electronic board, during the RF tests.

Figure 3.24. Micrographies STEM HAADF showing the Schottky gate contact, respectively, for the control component (Tem-1), and for a stressed component, transistor at the edge (Tem-2) and at the center (Tem-3) of the electronic board. Scale = 100 nm

Physical Defects Analysis of Mechatronic Systems


3.3.4. Analysis of an LDMOS component after a high temperature operating life test (HTOL) A power transistor LDMOS 330 W is analyzed after a life test in operational conditions. After 5,000 testing hours, the electrical performance of the component is stable (RF power, drain currents and voltage, gates and S parameters) [LAT 10]. Failure analysis is still carried out on this component in order to: – define the opening procedure of its ceramic case; – study the impact of the opening on its electrical characteristics; – correlate its photon emission signature with its base structure. Opening of the LDMOS 300 W ceramic casing The case is opened by laser ablation. The procedure consists of weakening the case along both lengths and making incisions along both widths. Measurements are carried out on I–V to verify that the opening does not affect the static electrical characteristics of the component. Figure 3.25 shows that the output networks before and after opening are identical. The laser opening procedure does not modify the electrical characteristics of the transistor.

Figure 3.25. IdVds characteristics before and after opening the ceramic case of the component LDMOS 330 W for Vgs0 = 0; Vds0 = 0 at 25°C. The Ids–Vds output networks before and after opening are absolutely identical. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2 Photon emission At the scale of optical microscopy, the LDMOS component displays a complex structure (Figure 3.26).

Figure 3.26. Structure of the electronic board of the LDMOS 330 W

At the point of nominal polarization (Vgs = 2.25 V, Vds = +50 V, Ids = 0.15 A), the emission of photons is localized in the area of the drain gate. There is intense emission at the nodes of the gate shown by the white arrows (Figure 3.27(c)). At regular intervals, some areas do not emit due to an absence of electrical contact with the drain linked to the structure. In a similar way to the GaN study, the morphology of the transistor on an ultrastructural level correlates with the optical signature obtained through PEM (Figure 3.28). It can be noted that emission is limited to the area bordering the drain in the drain gate area.

Physical Defects Analysis of Mechatronic Systems


Figure 3.27. Superimposed images of the structure of the LDMOS and the signal of photons emitted for nominal conditions of polarization. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Figure 3.28. Ultrastructure of the transistor obtained after the cross-section of the MEB FIB. a) MEB micrography of the surface of a fraction of the electronic board. b) Cross-section showing the morphology of the drain, the source and the gate covering in two field plates. c) PEM image. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

3.4. Conclusion The X-ray analysis of the defective IGBT power transistor after highly accelerated testing does not reveal any specific defect. Continuous electrical measurements confirm that there is a short circuit in the high side IGBT chip between the collector and the emitter. Visual inspection of this chip after opening the casing shows the signature of an electrical overvoltage. This electrical overvoltage defect may be caused either by a variation in inductance (poor or deteriorated solder joint), or by a variation in the ramp of the input signal due to poor motor control. The case opening of the MOSFET switching transistor damaged after testing in pulsed RF mode is done with a laser beam and specifically adapted chemical etching. Visual inspection of the chip surface after casing opening provides a rapid diagnosis in case of an electrical surge defect. After opening the casing it is possible to make supplementary TLS/OBIRCH type electrical measurements. The defect observed on the chip is due to electrical overvoltage stress in the vicinity of the gate contact. The failure analysis of the component of GaN HEMT technology damaged by high temperature operation life testing localizes defects in the nickel layer at the Schottky-type contact. This analysis shows a diffusion of gold in the nickel layer of the Schottky contact. This failure mechanism of the Schottky-type contact is in agreement with the electrical measurements. 3.5. References [DEL 11a] DELAROQUE T., DANILO K., VOIRON F. et al., “Scanning capacitance microscopy: A valuable tool to diagnose current paths in 3Dcapacitors process”, Conference Proceedings of the 37th International Symposium for Testing and Failure Analysis (ISTFA 2011), San Jose, CA, 13–17 November, 2011. [DEL 11b] DELAROQUE T., DOMENGES B., COLDER A. et al., “Comprehensive nanostructural study of SSRM nanocontact on silicon”, Microelectronics Reliability, vol. 51, no. 9, pp. 1693–1696, 2011.

Physical Defects Analysis of Mechatronic Systems


[DOM 13] DOMENGES B., DELAROQUE T., GAUTIER C. et al., “Evaluation of digital holography microscopy for roughness control prior wafer direct bonding”, Conference Proceedings of the 39th International Symposium for Testing and Failure Analysis (ISTFA), San Jose, CA, 3–7 November, 2013. [FON 12a] FONDER J.B., LATRY O., DUPERRIER C. et al., “Compared deep class-ab and class-b ageing on AlGaN/GaN HEMT in S-band pulsed-RF operating life”, Microelectronics Reliability, vol. 52, no. 11, pp. 2561– 2567, 2012. [FON 12b] FONDER J.B., CHEVALIER, L., GENEVOIS C. et al., “Physical analysis of Schottky contact on power AlGaN/GaN HEMT after pulsedRF life test”, Microelectronics Reliability, vol. 52, nos 9–10, pp. 2205– 2209, September 2012. [KER 14] KERISIT F., DOMENGES B., OBEIN M., “Comparative study on decapsulation for copper and silver wire-bonded devices”, Conference Proceedings of the 40th International Symposium for Testing and Failure Analysis (ISTFA), Houston, TX, 9–13 November, 2014. [LAT 10] LATRY O., DHERBECOURT P., MOURGUES K. et al., “A 5000h RF life test on 330 W RF-LDMOS transistors for radars applications”, Microelectronics Reliability, vol. 50, nos 9–11, pp. 1574–1576, 2010. [LAT 13] LATRY O., FONDER J.B., CHEVALIER L. et al., “Fiabilité d’amplificateurs de puissance à base de GaN: analyse de la défaillance”, Colloque International (TELECOM), Marrakech, Morocco, 13–15 March, 2013.

4 Impact of Voids in Interconnection Materials

This chapter deals with the study of heat transfer phenomena related to the dissipation of thermal energy in a power module and its subsequent effects. In the packaging process of a mechatronic module, defects may appear in the form of voids inside the interconnection material (ICM). By trapping thermal energy, these voids can act as a potential source of failure in the module. Indeed, they introduce an inhomogeneous character into the distribution of temperature at the interface of the different assembled components and within the ICM, and the resulting thermomechanical stresses weaken the packaging. Because a theoretical study of these effects is difficult, they are simulated using finite element methods (FEMs). The temperature distribution in the power module was determined by considering different types of ICMs, Sn60Pb40, Sn95,5Ag3Cu0,5, Ag and sintered Ag. Then, the thermomechanical stresses were simulated to determine the temperature effects on the packaging when voids are present in the ICM. This study aims to determine the influence of voids on the reliability of a module by using the parameters which are the maximum temperature of the chip and the thermomechanical stresses at the interfaces as indicators. This chapter gives an example of the importance of simulation in the design of a reliable mechatronic device. We not only obtain results which allow quick anticipation of the root cause of failures, but also significant data to optimize the bench tests to be implemented in order to improve the fabrication process and increase efficiency.

4.1. Introduction This study is devoted to the thermal phenomena generated by fast commutations in the active element of insulated gate bipolar Chapter written by Pierre Richard DAHOO, Malika KHETTAB, Christian CHONG, Armelle GIRARD and Philippe POUGNET.


Embedded Mechatronic Systems 2

transistor (IGBT, SiC, GaN, etc.) semiconductors which impact the operation of power mechatronic modules and as a result contribute to their failure. An electronic power module is an assembly of several electronic components (Figure 4.1): silicon (transistors and diodes) and passive electrical components are connected by an ICM to a copper base. The ICM maintains the components on the cooled copper substrate.

Figure 4.1. Layout of a power module in a mechatronic system connected by wires. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

When they operate, the power modules are subjected to thermal cycles and, under the influence of the resulting thermal flux, the differences in the coefficient of thermal expansion of the various components in contact lead to significant constraints in the ICM. This in turn leads to failures characterized by the initiation or the amplification of a crack and its subsequent propagation in the ICM. When joined either during the industrial process or during the development step, defects can arise at the ICM, as shown in Figures 4.2, 4.3 and 4.4. Figures 4.2 and 4.3 show 2D and three-dimensional (3D) x-ray tomography images of Ag material sintered by spark plasma sintering (SPS) [ALA 11, ALA 14] sandwiched between two substrates of copper. There is in fact a hole with a trapezoidal crosssection and average height of 800 nm through the entire thickness of the material. In Figure 4.4, the x-ray tomography image of a

Impact of Voids in Interconnection Materials


component soldered on an FR4 substrate [KHE 14] allows us to observe the air bubbles on the thickness of the lead-free solder.

Figure 4.2. 3D x-ray tomography image of sintered Ag material sandwiched between two SPS copper substrates

Figure 4.3. 2D planar view observed by x-ray tomography of Ag material sintered by SPS sandwiched between two copper substrates

Figure 4.4. X-ray tomography image of an electronic component soldered on an FR4 substrate, showing air bubbles on the thickness of the lead-free solder. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

These defects can occupy between 10 and 60% of the surface and throughout the thickness of the solder. If in terms of the volume percentage of material, these defects remain below a certain limit (near 12%), then the strength of the connection can be guaranteed. We want to determine the consequences of these porosities under operating conditions of the mechatronic module from the thermal cycling effect resulting at each switch. The results obtained in this chapter can be compared to experimental studies from test benches to devise and implement. In a first step, a model system was studied analytically and numerically. Comparison of the results validated the simulation by FEM. As the theoretical study is more difficult to apply to real systems, the thermal effects in the ICM were modeled and simulated by FEM to take into account the defects. Several cases were considered by considering ICM with or without defects, i.e. without a void, with a centered void and with voids arranged regularly and irregularly. The influence of these defects on the heat dissipation in a power module was studied first. Then, thermomechanical phenomena induced on the chip were simulated for different percentages of defects. The case of sintered Ag as ICM was also considered from recent available data [ALA 11, ALA 14]. 4.2. Thermal transfer and thermo-elasticity Heat transfer is modeled by means of partial differential equations (PDEs) which determine the evolution of thermal characteristic parameters of a system, such as its temperature, in space and over time, from the initial equilibrium state to the final equilibrium state [BRU 62, PRI 62, KIT 64]. In thermo-kinetics, a transfer of thermal energy or heat due to a temperature difference is characterized by the thermal current density vector which corresponds to the heat flux. Heat transfer occurs in three modes, conduction, convection and radiation. Conduction is the transfer of heat through a stationary medium (fluid or solid), convection refers to the transfer between a surface and a moving fluid and radiation, or thermal radiation, is the emission of thermal energy from a surface at a fixed temperature, in the form of electromagnetic waves. In general, the joint use of the first law of thermodynamics and physical laws associated with these

Impact of Voids in Interconnection Materials


modes allows for the study of phenomena related to heat transfer. Then, material deformation resulting from a temperature change can be studied from thermomechanical effects or thermo-elasticity [BRI 38, BRU 55, BIO 56, NYE 61, LAN 67, DUP 87]. 4.2.1. Conduction Heat conduction, which is a transfer mode caused by a temperature difference between two parts of the same medium, or between two materials in contact, occurs without global motion of matter contrary to the transfer mode by convection. The propagation of heat by conduction inside a solid body takes place according to two distinct mechanisms: by transmission of the vibrations of the atoms or molecules (phonons) and, if it is a metal, by transmission of thermal energy by free electrons. Heat transfer by conduction is modeled by Fourier’s law which is expressed as:

  Φ = − kS ∇ T .n


 where k is the heat conduction coefficient, S is the surface, ∇T is the  temperature gradient and n is the flux direction.

4.2.2. Convection Convection is a transfer mode which occurs by an exchange of energy between a body and a fluid. According to the kind of fluid flow, convection is termed free or forced. When the fluid currents are caused by temperature differences, the convection is called natural or free. If the fluid motion is caused by an external action, such as pump or a fan, it is termed forced convection. Convective heat flux is modeled by Newton’s law of cooling:

Φ = − hS (Ts − T∞ )



Embedded Mechatronic Systems 2

where Φ is the heat flux, h is the coefficient of convection, S is the surface, TS is the temperature of the surface and T∞ is the ambient temperature. 4.2.3. Radiation Heat is transferred from one body at a high temperature to another body at a low temperature as electromagnetic radiation (photons); the two bodies are both in a transparent medium (such as air or a vacuum). In this transfer mode, there is no movement of matter, no contact between the media exchanging thermal energy. The transport of energy (even in a vacuum) occurs in the form of electromagnetic waves. The flux is given by Stefan’s law:

Φ = −σε S S (TS4 − T∞4 )


where σ is the Stefan constant, εS is the emissivity of the radiating surface, TS is the temperature of the surface and T∞ is the ambient temperature. 4.2.4. Equation of heat diffusion The heat equation is a consequence of a balance of heat flux. Conservation of flux requires that, for a closed system, the amount of incoming heat flux and that which is generated inside is equal to the sum of the outgoing heat flux and the heat flux stored by the system. In the context of the conversion of electricity into heat, for example, through the thermoelectric effect (Joule effect), the incoming and outgoing energies are heat flux in and out of the system, the generated electric power is converted into heat and the stored energy is the rate of change of thermal energy stored by the matter in the system.

Impact of Voids in Interconnection Materials


The general heat equation expresses a relationship between the temperature T and the variables x, y, z and t as follows:


 ∂T = k div(∇T ) + Q ∂t


where ρ is the volume density, C is the specific heat capacity, k is the  coefficient of thermal conductivity, div is the divergence operator, ∇T is the temperature gradient and Q is a heat source or sink. The mathematical solution of this linear PDE of the second order admits, in principle, an infinite number of solutions [SOM 64]. Therefore, its resolution requires, on the one hand, the knowledge of the initial conditions, i.e. the initial temperature distribution of the medium at any point T (x, y, z, 0), and, on the other hand, the law governing the time variation of the temperature or its normal derivative on the surface S. These are the boundary spatiotemporal conditions. The common boundary conditions which specify the interaction of the surroundings with the system in thermal problems are the following: − Dirichlet boundary conditions: the temperature is given at the surface:

TS = f ( M S , t )


− Neumann boundary conditions: the flux density is given at the surface:

Φ = −k (

∂T )S = f (M S , t ) ∂n


− Fourier conditions: the flux density is a linear function of the temperature difference between the surface temperature and that of the surroundings (fluid medium):

Φ C = −k (

∂T ) S = h(TS − T∞ ) ∂n



Embedded Mechatronic Systems 2

4.2.5. Thermo-mechanics and thermo-elasticity In a homogeneous body, the temperature increase leads to the expansion that is characterized by a thermal expansion coefficient α, which is expressed as:

α =−

1  ∂V  V  ∂T  S


where V is the volume of the body and T is the temperature. To model the thermomechanical effects, it is more convenient to use tensor calculus [BRI 38, BRU 55, BIO 56, NYE 61, LAN 67, DUP 87]. In a 3D Euclidean space with Cartesian axes (notation 1= x, 2 = y and 3 = z), the tensor is related to the physical quantity it represents and how this quantity changes in a coordinate transformation. Thus, the temperature T, which is a scalar, is a zeroorder tensor (one component), a force F , which is a vector, is a tensor of order 1 (three components), which is denoted by Fk, and to represent the coupling between two vector quantities in the same coordinate system, we use a tensor of order 2 (nine components). In tensor notation, equation [4.1] can, for example, be written as:

Φ / Sei = ji = − kik

∂T ∂xk


where Φ is the thermal flux, S is the surface through which the flux flows, ei is the base vector of the vector space along i, ji is the ith component of the current vector density of the heat flux, kik is the thermal conductivity tensor of order 2 and ∂T/∂xk is the kth component of the temperature gradient, a tensor of order 1. The Einstein convention is used when two indices are repeated to indicate that it is a sum in order to simplify the notation. The distortion of a material considered as a continuous medium in the framework of small displacements is determined by a translation vector u(r) of a point of the material denoted by r, and the derivatives of this vector with respect to the coordinates. This results in nine derivatives which are generally expressed as a symmetric strain tensor

Impact of Voids in Interconnection Materials


(tensor of order 2) which gives the deformation of the point r in terms of the displacement gradient:

1  ∂ui ∂uk  +  2  ∂xk ∂xi 

ε ik = 


and an antisymmetric tensor:

1  ∂ui ∂uk  −  2  ∂xk ∂xi 

ωik = 


which represents the rotation of the material around the point. For a homogeneous temperature change ΔT of the material, the thermal expansion is expressed as:

ε ik = α ik ΔT


where αik are the coefficients of the symmetric thermal expansion tensor [αik] and εik are the coefficients of the symmetric strain tensor [εik]. In the principal axes of the expansion tensor, equation [4.12] is expressed as:

ε i = α i ΔT


where αi are the principal coefficients of expansion. The theory of elasticity, which is a macroscopic theory, considers volume over distances that are large compared to those of the constituents of the material (atoms, molecules, etc.) but small in comparison to the dimensions of the material itself. The forces responsible for the internal stresses during a mechanical deformation are short range and limited to close neighbors. They correspond to the forces exerted by one of its elements on neighboring ones. In a given volume inside the material, these forces thus act only at the surface of the volume. The sum of forces acting on the latter which is given by an integral over the volume may be reduced to a surface integral as follows:


Embedded Mechatronic Systems 2


Fi dV =


∂σ ik dV =   σ ik dAk ∂xk volume



where Fi is the ith component of the force acting on the volume, ∂σik/∂xk is the divergence of the symmetric stress tensor [σik], a secondorder rank tensor, dAk is the surface element whose orientation is along the unit vector nk and where the integral is determined over the surface enclosing the volume V. Equation [4.14] shows that σik dAk is the ith component of the force acting on the surface dA. σik is the ith component of the force acting on the unit surface perpendicular to axis xk. Thus, when a material is subjected to a uniform compressive force (pressure P), called a hydrostatic force, we write:

σ ik = − Pδ ik


where δik is the Kronecker symbol (0 if I ≠ k, 1 otherwise). Similarly, at equilibrium, a deformed material is subjected to (sum when indices are repeated):

∂σ ik =0 ∂xk


For small deformations, the material undergoes elastic deformation, that is to say returns to its initial undeformed state when external forces are removed. We then say that the stored energy density is a state function. However, if a permanent deformation remains, it is termed as being plastic. In the case of an elastic deformation, the variation of internal energy is expressed as:

dU = TdS − σ ik d ε ik


which reduces to the well-known expression of the first principle of thermodynamics:

dU = TdS − PdV


Impact of Voids in Interconnection Materials


under uniform compression equation [4.15], since δikdεik is equal to dεii (trace of [dεik] which is an invariant), the elementary volume dV and where T is the temperature and S is the entropy. Expression [4.17] being suitable for adiabatic transformations (S = 0), it is more convenient to use the Helmholtz free energy, F = U-TS for isothermal transformations (T = 0), from the expression:

dF = − SdT − σ ik d ε ik


Equations [4.15] and [4.17] show that the stress tensor can be expressed as the derivative of U or F at constant entropy and temperature, respectively, as:

 ∂U   ∂F   =   ∂ε ik  S  ∂ε ik T

σ ik = 


Note that by choosing the thermodynamic potential Φ = F- σikεik, then:

d Φ = − SdT − ε ik dσ ik


and εik can be determined as:

 ∂Φ    ∂σ ik T

ε ik = − 


From the power series expansion in terms of εik of F, the Helmholtz free energy, or U, the internal energy, we can determine the stress tensor as a function of the strain tensor for an isothermal and isentropic deformation, respectively, as:

 ∂2 F   ∂ 2U  ε or σ =  lm   ε lm ik  ∂ε ik ∂ε lm T  ∂ε ik ∂ε lm  S

σ ik = 



Embedded Mechatronic Systems 2

These relationships are generally expressed as follows: T S σ ik = Ciklm ε lm or σ ik = Ciklm ε lm


where Ciklm are the isothermal or isentropic elastic constants. This form is Hooke’s law, which pertains to linear elasticity. These constants are also called stiffness constants. Similarly, we can express Hooke’s law in the reverse form: T S ε ik = Siklm σ lm or ε ik = Siklm σ lm


where Siklm are called compliances. Because the strain and stress tensors are symmetrical and of rank two, they can be split into a spherical part and a deviatory part in the following manner:

1 3

1 3

ε ik = (ε ik − δ ik ε ll ) + ε ll


1 3


1 3

σ ik = (σ ik − δ ikσ ll ) + σ ll

The first term of equation [4.26] corresponds to a slide or a shear (without distortion of volume change) and the second term corresponds to a uniform compression (distortion without change of shape). The expression of the free energy F is then given by:

1 2 F − F0 = μ (ε ik − δ ik ε ll ) 2 + (λ + μ )ε ll2 3 3


1 K F − F0 = μ (ε ik − δ ik ε ll ) 2 + ε ll2 3 2


Impact of Voids in Interconnection Materials


where F0 is the free energy for deformation, and λ and μ are the Lame coefficients. K is the uniform compression modulus or stiffness while μ is the shear modulus (K > 0 and μ > 0). Note that these modules can be expressed as follows:


E 2(1 + ν )



E 3(1 − 2ν )


where E is the Young’s modulus and ν is the Poisson’s ratio. In the case of distortion when the temperature varies, it can be shown that the expression of the free energy is of the form:

1 K F (T ) − F (T0 ) = − K α (T − T0 )ε ll + μ (ε ik − δ ikε ll ) 2 + ε ll2 3 2


where F(T0) is the free energy in the absence of distortion at temperature T0, and α is the coefficient of thermal expansion of the material. It should be noted that, in the presence of a heat flux, the heated region is not free to expand and is subject to compressive stresses from colder regions. Similarly, cold regions are subjected to tensile stresses from the warmest regions. It is necessary to take account of these additional constraints when applying Hooke’s law. It can be shown that:

σ ik = −3Kα (T − T0 ) + 2 με ik +

Eν ε llδ ik (1 + ν )(1 − 2ν )


and that:

ε ik = α (T − T0 )δ ik +

1 +ν ν σ ik − σ llδ ik E E



Embedded Mechatronic Systems 2

These equations are used to determine the distortion when the temperature varies, either in the weak coupling regime by first determining the thermal effect and then the mechanical effect or in the strong coupling regime when both effects are considered simultaneously. 4.3. Description of the numerical method

For numerical simulations, a piece of software that allows physical problems expressed as PDE [SOM 64] by FEM [COU 43, ZIE 71, PRI 80, WHI 76] in different fields such as electromagnetism, structural mechanics or thermal physics to be resolved is applied. It also enables multi-physics coupling combining different physical phenomena, such as electrical and thermal (electro-thermal) phenomena, or thermal and mechanical (thermomechanical) phenomena, to be solved. Given the physical problem to be studied, a model consisting of a set of PDE whose solutions must verify boundary and initial conditions is established for a system in one, two or three dimensions, limited by a boundary. The equations describe, for example, the spatial and temporal variations of an unknown variable, such as temperature (T), and the method consists of seeking an approximate solution of T after a discretization of the geometry of the physical system to be studied, divided into meshes connected by nodes. The solution is interpolated on basis functions (Lagrange polynomials). The interpolation functions of the software are defined on each mesh element (non-zero on the element and zero elsewhere), a mesh and its interpolation functions constituting a finite element. The graphical user interface (GUI) of the software is shown in Figure 4.5, where we find three main windows: from left to right, the model builder, a window to enter the model parameters and a window for displaying the results.

Impact of Voids in Interconnection Materials


Figure 4.5. Graphical interface of the software

The steps required to model a physical system consist of three parts: the construction of the physical system, solving the PDE driving the physical phenomenon of interest and post-processing of data to extract the most significant results, i.e.: – model builder: - drawing or importing the geometry in 1D, 2D or 3D; - setting the values of the physical properties of the materials in the different domains constituting the geometry according to the physical model built (we assign the physical parameters such as thermal conductivity, thermal expansion coefficient, etc.); - setting the initial and the boundary conditions at the borders and the source terms (or sinks). – solving PDEs: - showing results in graphical form, table or animation;


Embedded Mechatronic Systems 2

- determining the values of unknowns from the variables set by the boundary conditions variables. The software solves the equations by the FEM with solvers adapted to determine the values of variables on any geometry by iterating until convergence (determined by a convergence criterion). – post-processing of data: - showing results in graphical form, table or animation; - data export. 4.4. Simulation of thermal and thermomechanical effects in the interconnection material of an electronic module

A simplified schematic of the power module comprising an electronic chip (silicon material transistor) connected (Ag or sintered Ag or SnPb or SnAgCu) to a base plate of copper (substrate) is used for simulation (Figure 4.6). The chip is a square with sides 10 mm long and a thickness of 245 μm. An IMC is a square with 10 mm sides and a thickness of 130 μm. The base plate is a larger square, 15 mm sides and 1.5 mm thick. The physical properties of the packaging materials are gathered in Table 4.1.



Figure 4.6. Geometry of the module: a) without and b) with a centered defect of 300 µm diameter

Impact of Voids in Interconnection Materials



Sintered Ag -7




Cu -8


Resistivity (Ω/m)


1.5 × 10

4 × 10

6.1 × 10

1.67 × 10

Coefficient of thermal expansion (ppm/K)






Specific heat capacity (J/kg/K)






Density (kg/m )






Thermal conductivity (W/m/K)






Young’s modulus (GPa)






Poisson’s ratio






Relative permittivity







Table 4.1. Physical properties of the materials of the module

The power module is considered as an open thermodynamic system that exchanges heat with the surroundings in the form of radiation and convection. Its modeling uses PDEs for determining its response, in terms of temperature changes, to an excitation generated by the switching of a power transistor (IGBT, complementary metal oxide semiconductor (CMOS), etc.). This excitation results in a sudden rise in temperature due to the energy generated in the form of heat by the Joule effect over a short period of time. This heat is then dissipated throughout the module from top to bottom through the ICM (SnPb or SAC or sintered Ag or Ag) to the substrate. The heating of the chip by the Joule effect is simulated by expressing the heat source Q in equation [4.4], by:

 Q = σ ∇Ve




Embedded Mechatronic Systems 2

where Q is the heat flux (W/m3), Ve is the electric potential difference (V) and σ is the electric conductivity (S/m). A voltage Ve of 600–1,200 V is fixed between the upper and lower face of the module. On the upper surface, a free convection of 5 Wm-2, with T∞ = 293.15 K (equation [4.2]) is applied. On the underside of the device, attached to the copper, the cooling system is simulated by a forced convection with water at a flow rate of 2,000 m/s over the length of the cooling plate (1.5 mm). Based on these boundary conditions, the temperature, heat flow and mechanical deformation due to heat transfer between the various elements of the module are determined. For the mechanical stresses induced by the thermal expansion (equations [4.10], [4.12], [4.14], [4.31] and [4.32]), the software uses the following expressions:  [4.34] −∇ × σ = Fv

σ =S


S − S 0 = c (ε − ε 0 − ε inel )



ε = (∇u )T + ∇u  2


ε inel = α (T − Tref )


 where ∇ is the nabla operator, σ or S is the stress (M Pa), Fv is the force per unit volume, ε 0 is the initial deformation, ε inel is the inelastic deformation corresponding to the thermal expansion and u is the displacement vector.

4.4.1. Variation of the temperature and strain in the presence of a void defect

In Figure 4.7, the results obtained with an ICM consisting of SnPb in the presence and absence of a void defect are compared. Recall that

Impact of Voids in Interconnection Materials


the heat is dissipated laterally and above by natural convection, and under the copper substrate by forced convection. The temperature decreases from the center to the edge, but in the presence of a void defect simulation shows a concentration of thermal energy in the vicinity of the defect, and consequently, a higher temperature of 3–4°C in this region.

Figure 4.7. Temperature mapping at each point on the volume geometry: a) free from defects; b) with a void defect in the center. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

A similar temperature mapping is determined for the other ICM (SAC, Ag and sintered Ag), the only difference being the temperature values that depend on the thermal properties of each. The localization of the heat is due to the increase of the thermal resistance between the chip and the substrate by the presence of the void defect. Note that the heat flow is essentially vertical in the thickness of the chip and the ICM except possibly at the boundaries. Regarding the deformations induced by the heat accumulated in the assembly (Figure 4.8), the overall distortion (Von Mises criterion) is around 800 nm in the presence and absence of a centered void defect. A greater contrast is obtained with larger deformations at the interfaces, the borders of the chip and the SnPb ICM and around the defect. We can anticipate that these zones are potential sources of failures. Mapping deformation occurs in a similar manner for other ICMs.


Embedded Mechatronic Systems 2

Figure 4.8. Strain mapping at each point on the volume geometry: a) free from defects; b) with a void defect in the center. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

4.4.2. Maximum temperature as a function of the voltage or the size of the defect

The maximum temperatures as a function of the voltage applied to the chip are shown in Figure 4.9 for different ICMs (SnPb, SAC, Ag and sintered Ag). SnPb SnPb SAC SAC Ag Ag

180 160

sintered Ag Ag fritté

Tmax (°C) (°C) Tmax

140 120 100 80 60 40








Applied (V) Potentiel voltage électrique(V)

Figure 4.9. Variation of the maximum temperature as a function of the applied voltage for different ICMs (SnPb, SAC, Ag and sintered Ag). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

The difference in temperature is in a small interval (1–4°C) for the different ICMs, but it significantly increases nonlinearly from 60 to 170°C when the voltage is varied from 600 to 1,200 V. It is expected that the thermomechanical effects will be more important at a voltage

Impact of Voids in Interconnection Materials


of 1,200 V and that the ICM has a key role in the absorption of mechanical stresses, and thus in the reliability of the packaging. By varying the radius of the void defect from 1.26 to 4.00 mm, a systematic study of the temperature distribution was conducted as a function of the porosity induced in the ICM (5–50% by volume). On the temperature mapping shown in Figure 4.10 for 10 and 50%, respectively, in the latter case, simulation gives temperatures higher by 10°C on average and equal to 30°C for the maximum value.



Figure 4.10. Mapping of the temperature at each point of the volume geometry: a) with a void defect of 10% by volume; b) with a void defect of 50% by volume. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

The simulation shows that the maximum temperature increases nonlinearly for all ICMs (Figure 4.11). The temperature difference is 15°C between SnPb or SAC and Ag. It is noted that for radii between 1.78 and 2.18 mm, corresponding to the range of 10–15% as the percentage of defect allowed in industrial processes, a significant difference of 5°C is determined. Maximum temperatures with sintered Ag are higher (1–3°C) than with Ag, but systematically lower than with SnPb and SAC. From this point of view, ICM Ag is a better material with respect to the constraint temperature.


Embedded Mechatronic Systems 2

Figure 4.11. Variation of the maximum temperature depending on the radius for various ICMs (SnPb, SAC, Ag and sintered Ag). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

4.4.3. Study of the effect of void defects in size and position in the ICM

To study the influence of defects on the temperature of the chip, a comparative study was performed according to the size and position.

Figure 4.12. Mapping of the highest temperature depending on the position and size of the voids: a) r = 2.52 mm, porosity = 40%; b) r1 = 2.52 mm, r2 = 1.78 mm porosity = 30%. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Temperatures are higher at the upper surface of the chip and always located above all the defects present in the ICM, as shown in Figure 4.12. In both cases of Figure 4.12, the maximum temperature is

Impact of Voids in Interconnection Materials


shown on the defect of the largest radius. It is equal to 75°C, corresponding to a rise of 55°C in the case of SnPb (it is lower by about 5°C for Ag). In Figure 4.13, the study based on the distribution of three defects shows that the position of the defect influences the maximum temperature reached (62°C). It is higher if a defect is near the center of the chip. If the defect is close to the borders (cases a, b and d), the temperature decreases, and even more so if the defect is on the main diagonal (cases a and b). Note that the temperature differences are low in the static mode (1–2°C). Extrapolating these results in dynamic mode when the mechatronic module is subjected to power cycles, the difference in temperature will necessarily increase. Consequently, these heat trapping zones will induce thermomechanical stresses in the chip.

Figure 4.13. Mapping of the temperature of three circular defects distributed over the symmetry elements of the geometric form of ICM (radius 1.26 mm, porosity 15%). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

4.4.4. Study of the effect of the disposition of void defects in the ICM

For the same degree of porosity of 40%, the maximum temperature is recorded on the defect of the largest radius (66°C for case (a) and 70°C for case (b)) as shown in Figure 4.14. The mapping of the temperature can be interpreted on the basis of the heat flux. In case (a), the isotherms are circular, which implies a homogeneous flow of heat radiating from localized hot spots on the defects. In case (b), the heat flow is inhomogeneous since hot spots are irregularly distributed. Thermomechanical shear stress is highest in areas where the temperature is high. In case (a), the homogeneous distribution of hotspots will induce a separation of the chip in the middle, in the region that surrounds these points. In case (b), the shear stress can be better absorbed.

Figure 4.14. Temperature mapping with circular defects distributed in the ICM: a) regularly (radius 2.2 mm, porosity 40%); b) at random (maximum radius 1.8 mm, porosity 40%). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

In summary, the main results are that the increase in the temperature of the silicon is a function of the spatial distribution and size of defects, with a maximum temperature located above the larger defect. A study based on the shape of the defects has also shown similar results in the evolution and mapping of temperature [ADA 12]. We might think that the analysis of circular gaps could also be applied to other forms. If the faults are uniformly distributed, the risk of chip’s lift off is more likely.

Impact of Voids in Interconnection Materials

4.4.5. Thermomechanical effects mechatronic power module






The results of the thermomechanical simulation given in Figure 4.15 show a maximum deformation of the same order of magnitude (800 nm) in SnPb and sintered Ag with a defect at the center. When defects are irregularly distributed (Figure 4.16), the maximum deformation varies little, being of the order of 650 nm on the Ag material and SnPb. Deformation with sintered Ag is lower than with the SnPb alloy or Ag metal. The difference is 20 nm.

Figure 4.15. Thermomechanical simulation with a circular void defect centered in ICM: a) sintered Ag; b) SnPb. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Figure 4.16. Thermomechanical simulation with circular defects irregularly distributed in the ICM: a) sintered Ag; b) SnPb. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

For uniformly distributed defects (Figure 4.17), the maximum deformation is lower, being around 600 nm for the Ag metal and SnPb. The mechatronic module deforms more with the Ag metal or alloy SnPb than with sintered Ag (range 20 nm).



Figure 4.17. Thermomechanical simulation with circular defects regularly distributed in the ICM: a) sintered Ag; b) SnPb. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

4.4.6. Analysis of results

Simulation results show that the maximum temperature depends on the degree of porosity. For the same degree of porosity, it is localized on the defect of larger radius. We find: T max (n = 1) > T max (n = 2) > T max (n = 3), where n is the number of defects. There is an increase in the maximum temperature with the size of the defects as the porosity ratio increases. The maximum deformation increases with the porosity up to 21%, and beyond this threshold it decreases. From the variation of the deformation as a function of radius of the void defect (Figure 4.18), we calculate an increase of the deformation according to the radius of the defect up to a threshold of 2.3 × 10-3 mm (deformation of 450 nm). Beyond this value, the deformation decreases.

Impact of Voids in Interconnection Materials


Figure 4.18. Variation of strain with the radius of the defect in an IMC: a) Ag; b) SnPb

4.5. Conclusion

The results discussed in this chapter are an example of where simulation on a macroscopic scale makes it possible to evaluate the evolution of the parameters of temperature and deformation in response to thermal stress in the presence of porosity in the ICM. The results allow us to anticipate the causes of failure when using new materials and concepts to gain market share or to comply with legislation. The objective of the work on simulation carried out by applying the FEM focuses on the effect of defects (absence of material) on the maximum temperature reached and the thermomechanical effect on the silicon chip. Different ICMs are considered in the calculations, especially sintered Ag with parameters from [ALA 11] and [ALA 14]. The introduction of a single void in the IMC is considered to model the porosity observed in the solder. Simulation shows that the defect acts as a heat sink, which results in a rise in temperature on the surface of silicon. The results show that the maximum temperature of the silicon is not dependent on the number of voids, but on the size of the largest void. The presence of a large number of small void defects in the IMC only induces a small increase in the temperature of the silicon. However, a larger defect significantly increases the maximum temperature and the average value. The layout of the defects also has an effect on the deformation. Chips are more likely to lift off when the


Embedded Mechatronic Systems 2

distribution of void defects is regular. Deformations are higher around the defects and in the vicinity of interfaces and borders. Regarding the nature of the ICM, Ag dissipates heat better than sintered Ag and SnPb, but sintered Ag better absorbs deformations induced by temperature. Lead-free SAC305 solder shows a thermomechanical behavior similar to that of SnPb. This study shows that sintered Ag achieves the best compromise in terms of the demand on the properties of ICM. 4.6. References [ADA 12] ADAMIDI E., CHONG C., KHETTAB M. et al., “Thermal impact of solder voids in the electronic packaging of power modules: Modeling and simulation of thermal effect on IGBT”, Euripides Forum, Gratz, Austria. Available at: http://www.hitech-projects.com/euprojects/thor/downloads_ files/FORUM2012_POSTER_Euripidis-Forum-Gratz-june2012eleniadamidi.pdf, June 2012. [ALA 11] ALAYLI N., Frittage de pâte de nano et micrograins d’argent pour l’interconnexion dans un module de mécatronique de puissance: élaboration, caractérisation et mise en œuvre, PhD Thesis, UVSQ, Versailles, 2011. [ALA 14] ALAYLI N., SCHOENSTEIN F., GIRARD A. et al., “Spark plasma sintering constrained process parameters of sintered silver paste for connection in power electronic modules: microstructure, mechanical and thermal properties”, Materials Chemistry and Physics, vol. 148, pp. 125– 133, 2014. [BIO 56] BIOT M.A., “Thermoelasticity and irreversible thermodynamics”, Journal of Applied Physics, vol. 27, pp. 240–253, 1956. [BRI 38] BRILLOUIN L., Les Tenseurs en Mécanique et en Elasticité, Masson et Cie, Paris, 1938. [BRU 55] BRUHAT G., Mécanique, Masson et Cie, Paris, 1955. [BRU 62] BRUHAT G., Thermodynamique, Masson et Cie, Paris, 1962. [COU 43] COURANT R., “Variational methods for a solution of problems of equilibrium and vibrations”, Bulletin of the American Mathematical Society, vol. 49, pp. 1–23, 1943.

Impact of Voids in Interconnection Materials


[DUP 87] DUPOUY J.M., PHILIBERT J., QUERE Y.N., Eléments de Métallurgie Physique, INSTN CEA, Saclay, 1987. [KHE 14] KHETTAB M., Étude de l’influence du résinage au niveau de L’IML (Insulated Metal Lead frame), dans le packaging de module commutateur de courant mécatronique, PhD Thesis, UVSQ, Versailles, 2014. [KIT 80] KITTEL C., KROEMER H., Thermal Physics, W.H. Freeman & Company, New York, 1980. [LAN 67] LANDAU L., LIFCHITZ E., Théorie de l’Elasticité, MIR, Moscow, 1967. [NYE 61] NYE J.F., Propriétés Physiques des Cristaux, leur représentation par des tenseurs et des matrices, Dunod, Paris, 1961. [PRI 62] PRIGOGINE I., Introduction to Thermodynamics of Irreversible Processes, John Wiley & Sons, New York, 1962. [ROC 75] ROCKEY K.C., EVANS H.R., GRIFFITHS D.W., Nethercott D.A., The Finite Element Method, 2nd ed., New York, Wiley, 1975. [SOM 64] SOMMERFELD A., Partial Differential Equations in Physics, Academic Press Inc., New York, 1964. [WHI 76] WHITEMAN J.R., The Mathematics of Finite Element and Applications II, Academic Press, London, 1976. [ZIE 71] ZIENKIEWICZ O.C., The Finite Element Method in Engineering Science, McGraw-Hill, New York, 1971.

6 Meta-Model Development

Up to now, there has been no robust, homogenized and standardized method for the design of mechatronic systems. This chapter presents a number of methods to optimize the reliability of mechatronic systems. These methods are based on knowledge and expertise in deterministic and stochastic modeling. The objective is to combine a finite element numerical model describing the physical behavior of a mechatronic system with a stochastic model of its behavior. The results of numerical modeling make it possible to build a meta-model using the response surface. By using this meta-model, the level of control factors is adjusted, the sensitivity of the mechatronic system to sources of variability is reduced (noise factors) and the response of the system can be adjusted to meet the target (objective).

6.1. Introduction The reliability of a mechatronic system can be assessed by simulating the behavior of the system to the stresses applied in the use conditions during its expected life. This approach involves building a finite element model of the most critical failure modes. The data obtained from the simulations are expressed as the number of stress cycles to failure or the cumulated probability of failure. These reliability results should meet the specified reliability targets. The finite element models built to simulate the reliability of mechatronic systems are often complex. They have a large number of

Chapter written by Bouzid AIT-AMIR, Philippe POUGNET and Abdelkhalak EL HAMI.


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parameters and various factors (physical, chemical, thermal, mechanical, etc.) have a strong effect on their behavior. It is not easy to apply stochastic methods on these complex finite element models because of very long calculation times. In this chapter several methods are presented to develop a simplified mathematical model which approximates the real physical behavior of the system (modeled by the finite element method). This mathematical model or meta-model is used to obtain the stochastic behavior of the system reliability when specific stresses are applied. Once the factors having a strong impact on the reliability of the system are selected, computer generated designs of experiments are defined to obtain a simulated response surface (Doehlert and Latin Hypercube designs). The response surface is adjusted by using methods such as partial least square (PLS) regression or Kriging. A sensitivity analysis is performed to evaluate which factors have a strong effect on the variability of the response. A robust design method is then applied using confounding factors. This method is applied to optimize the reliability of critical design elements of a mechatronic system. 6.2. Definition of a meta-model Finite element models describing the expected failure modes of mechatronic systems are often complex and lead to long calculation times. A meta-model is a simplified mathematical model of the simulated response of the system, which makes it possible to assess the effect of the variability of the design parameters and of the sources of noise on the response of the system, which in this case is its probability of functioning without failure or error. 6.3. Selection of factors: screening Finite element numerical models of mechatronic systems depend on a very large number of parameters or design factors. Generally

Meta-Model Development


speaking, in a numerical model, any variation of factor induces modifications of the values of the response. This is true for all factors, but at different scales. Some factors have a significant effect on the response. They are said to be influential factors. Other factors have little effect on the response and therefore can be considered as sources of noise on the response. Screening is a selection process that determines the influential factors elements in an initial set of factors. This method compares the variations of the response caused by two sources: – variations of the factor studied; – variations which are not considered as having an effect on the response (noise). A statistical test is carried out to assess whether or not to reject the hypothesis that a factor does not cause significantly greater variations in the response than those caused by the noise. Likewise, a factor is deemed influential if its action on the response studied is statistically higher than a given level, pre-established by the researcher. By extension, screening ranks the factors in terms of their effect on the system response. This technique improves the understanding of the system as a whole, making it possible to only retain the factors which are influential. It is a good practice to test a large number of factors, even if certain factors are not expected to have a strong effect on the response. Two trials are necessary to analyze the effect of a factor on the response. When a trial is performed, the factor under study is set to its high and low level. The effect on the response is usually studied graphically by displaying the response versus the high/low level values of this factor. These trials are repeated. The effect is evaluated quantitatively by calculating an estimate of the average response


Embedded Mechatronic Systems 2

change from the high to the low level of the variable, and a statistical test is used to evaluate if the effect is statistically significant or not. Figure 6.1 displays how the twenty various factors of a system affect the response. The screening underlines only three variables which have a significant effect (Student’s t-test). It is often wise not to eliminate factors considered insignificant by the test when their effect is significantly above zero. It is interesting to include factors which initially are assumed to have no effect on the response and preferable to include “too many” factors than to ignore them.

Figure 6.1. Average response change (%) from the high/low level of various factors of a system. The graph displays the significant limits of Student’s t-test. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

When several factors interact, the application of the statistical principle of orthogonality means that this process needs to be repeated for each variable, while the other variables are successively set at their two possible values (high/low). For k factors, this represents 2k tests to be carried out. This calculation process corresponds to the full factorial design. The main disadvantage of the full factorial design method is the number of tests required when the number k of design factors is high. Its greatest advantage is that no bias is introduced. Alternative methods can be used because they require fewer tests. These include: – Fractional factorial designs: these designs of experiments use the principle of confounding effects. This technique reduces the number of

Meta-Model Development


points per design. The drawback of this method is that each effect calculated by this type of design is, in reality, the sum of simple effects (those deduced from a full factorial design). This inconvenience can be accepted if it is ensured that there is only one significant effect in each sum; – Taguchi’s designs: these designs were developed for industrial applications. These are fractional factorial designs which take into account the interactions deemed important and reject any others; – Plackett–Burman designs: these designs arise from the screening properties of Hadamard matrices and have the advantage of allowing significant savings in terms of number of tests. The screening process is set according to the following points: – the number of experiments (N) to be conducted; – the terms that can be calculated with each model. For instance, Plackett–Burman designs do not assess interactions, whereas full factorial designs do. 6.4. Creation of designs of experiments When the number of factors is specified, various designs of experiments (DOE) can be created to obtain a response surface. These designs are described according to their main characteristics (number of experiments, variance, etc.) [MYE09]. Though they have good statistical characteristics, the full factorial designs are not presented here because they generate significantly more trials than the designs described below. 6.4.1. Central composite designs The central composite (CC) designs (Box and Wilson designs) are 1 2 3 constituted of a full , factorial or fractional design. The points at the 1 “Full” means that the design of experiments is made up of all the factor combinations possible. 2 “Factorial” means that all the levels of all the factors are coded. 3 “Fractional” means that the design of experiments is solely made up of some of the possible combinations.


Embedded Mechatronic Systems 2

center of the experimental domain and the “star” points outside this domain make it possible to estimate the curvature of the response surface (see Figure 6.2).

Figure 6.2. Generation in a central composite design of points: in the center of the domain under study, plus star points outside this domain

The levels of the points of a factorial design are ±1 and those on a “star” design are ±α where |α|≥1. The value of the α parameter is set according to the calculation possibilities and the required precision of the estimation of the surface response. The quality of the estimation is determined by the positioning of the points. The setting of α value and the number of trials at the center of the domain have an effect on the accuracy of the estimation. There are three types of CC plans: circumscribed (CCC), face-centered (CCF) and inscribed (CCI). Their characteristics are described in Table 6.1

Meta-Model Development

Type of design


Circumscribed (CCC)

The star points are outside the initial experimental domain (distance α). This design requires five levels per factor.

Face-centered (CCF)

α = ±1, the star points are located on the faces of the experimental domain. This design requires three levels per factor.

Inscribed (CCI)

α = ±1, this design is used when it is not possible to leave the experimental domain. The CCC design is then reduced to fit within this domain. This plan requires five levels per factor.



Table 6.1. Characteristic of three types of central composite designs: circumscribed (CCC), face-centered (CCF) and inscribed (CCI)

The quality of a design of experiments is measured by the variability of the estimate of its coefficients and consequently by the variability of the response estimate. One important characteristic is iso-variance per rotation (rotatability). This means that the prediction error is identical for all the points located at the same distance from the center of the domain. Figure 6.3 displays the prediction variance for three types of two-factor designs: rotatable, orthogonal, and rotatable and orthogonal. The prediction variance increases, moving from green to red. The rotatable design provides a less accurate estimation than the orthogonal design at the center of the domain. The rotatable and orthogonal design is a compromise between these two. The processing software for the design of experiments provides values of α and the number of points at the center for the qualities chosen. Table 6.2 displays the α parameter and the number of center


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points of rotatable, orthogonal and rotatable-orthogonal CC designs as a function of the number Nf of experiments in the factorial plans, the total number N of trials and the number k of factors. Standard deviations and parameter correlations


Prediction variances



Rotatable and orthogonal

Figure 6.3. Prediction variances of two-factor rotatable, orthogonal and rotatable-orthogonal CC designs. For a color version of this figure, see www.iste.co.uk/elhami/mechatronic2.zip



Number of points at the center


α = 4 Nf


Orthogonal Rotatable and orthogonal


Nf *N − Nf 2

α = 4 Nf


N 0 = 4 N f + 4 − 2k

Table 6.2. Parameters of rotatable, orthogonal and rotatable-orthogonal CC designs where Nf is the number of experiments of a factorial design, N is the total number of trials and k is the number of factors

The number of experiments to perform in a CC design is determined by the following formula when the factorial design is full: N = 2k + 2k + N0 Table 6.3 displays for a CC DOE the number of trials and the number of coefficients to estimate according to the number of factors.

Meta-Model Development

Number of factors Number of coefficients to estimate Number of trials

2 6

3 10

4 15

5 21

6 28







Table 6.3. Number of trials in a CC design

If the number of factors increases, it is recommended to limit the number of tests once more. Specialized software provides CC designs based on fractional factorial designs which limit the number of tests. For instance, it is possible to process six factors with 30 tests (rather than 77 tests). 6.4.2. Box–Behnken designs The Box–Behnken designs of experiments provide modeling of the response surface. These designs are not based on full or fractional factorial designs. The design points are positioned at the middle of the subareas of the dimension k-1. In the case of three factors, for instance, the points are located in the middle of the edges of the experimental domain (see Figure 6.4).

Figure 6.4. Example of a three factor Box–Behnken design

These designs require three levels per factor. The Box–Behnken design for three factors does not comply with the criteria of iso-variance per rotation. However, the designs above, having more than three factors, can meet the iso-variance criteria if center points are added. These designs can also respect the orthogonality criteria.


Embedded Mechatronic Systems 2

The Box–Behnken designs make it possible to study sequentially the effect of the various factors of the design if, during the study of the first factors, the other factors are maintained at a constant level. Table 6.4 shows for a Box–Behnken DOE the number of trials and number of coefficients to estimate in case of 3, 4, 5 and 6 factors. Number of factors





Number of coefficients to estimate





Number of trials





Table 6.4. Number of trials in a Box–Behnken design (one trial in the center point)

6.4.3. D-optimal designs The D-optimal designs are often used when the experimental domain is not fully accessible. For example, when there are constraints which prevent access to certain areas of the domain being studied. These experimental designs allow a larger part of the experimental domain to be explored despite the restrictions caused by the constraints. They are also useful when the number of trials needs to be reduced from that usually required for a traditional design. Once the number of trials is set, an algorithm calculates the optimal designs and sets the best experimental points for a given model. It is possible to include previous test results when creating a new design. D-optimal designs are an essential solution when the calculation cost is an important criterion in choosing a design of experiments. 6.4.4. Doehlert designs Doehlert designs (1970) are an integral part of the family of networks. The process of setting up these designs is iterative and consists of taking an initial simplex in the exploration domain to start with and applying isometries to one of its apexes (translation and

Meta-Model Development


rotations). By proceeding through iterations, a specific set of points is obtained (Figure 6.5). For each variable on [-1,1] interval, this means successively subtracting the coordinates of each point of the initial simplex from the other points. These designs generate points regularly in experimental space. This is particularly useful when the domain needs to be explored in its entirety (boundaries and interior) without providing an a priori model representing the response. Subsequently, the density of points will be determined by the size of the initial simplex.

Figure 6.5. A 45-point Doehlert design in the square unit area with its initial simplex: the equilateral triangle

These DOEs have other advantages. They allow a sequential approach to the response surface. For example, if the most interesting experimental area is not in the pre-selected domain, but located in a neighboring area, it is possible to build a new collection of experiments around one of the points of the initial design which includes part of the trials already conducted, without consequently destroying the pre-existing uniformity. It should be noted that this property is not valid for factorial designs.


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Since each simplex can be derived from the immediately lower dimension simplex, it is easy to increase the number of factors progressively without having to restart all the experiments when it is obvious that the exploration domain is not correct. To do so, it is simply necessary to add d-th column of zeros for the first d points of the simplex of dimensions d−1 and add a new point whose coordinates are given in Table 6.5. Variable

d - q(> 0)


1 (2(d + 1) - d )(d - q)

d +1


d -3

d -2

d -1


1 (2(d -1)(d - 2))

1 (2d (d -1))

(d + 1) / 2d

Table 6.5. Coordinates of the (d+1)-th point of the simplex

Doehlert DOE simplify the study of a restricted zone by changing the dimensions of the initial simplex. The minimum number of distinct points, n, for a Doehlert DOE having k factors is n = k² + k +1. This is an advantage for large dimensional designs. For example, if k=20, then n will be equal to 421. However, the regularity of these designs leads to a loss of information, due to alignments in the area as can be seen in Figure 6.5. 6.4.5. Latin hypercube sampling (LHS) designs By definition, a n trials Latin hypercube design is a design of experiments in which: – each parameter has the same number of levels n. If this number n is high, the mesh is finer and the adjusted model determines more accurately the optimums; – each parameter is set for each level only once and the levels are equally distributed. Thus, each column of the design of experiments is a random sample without replacement among {1, 2,…, n}.

Meta-Model Development


When parameters have different variation ranges, each parameter takes n equally distributed levels between its minimum and maximum values. An LHS design for three parameters in 10 trials is described in Table 6.6. The main characteristics of LHS designs are: – space-filling: the trials of the LHS DOE should fill the input domain as much as possible. This criterion is calculated using the distance between the closest two points on the design. The objective is to maximize this distance; – independence: it is desirable for the parameters to be as orthogonal as possible. This means that they are as uncorrelated as possible (if there is a correlation between two parameters A and B, it is difficult to separate the effect of A from the effect of B). This criterion is calculated using the determinant of the parameter correlation matrix. The objective is to maximize this determinant (if there is no correlation at all, it is equal to 1 and the design is orthogonal). Test no. 1 2 3 4 5 6 7 8 9 10

Factor 1 6 5 10 3 7 2 1 4 9 8

Factor 2 10 1 8 6 3 9 2 4 5 7

Factor 3 10 2 1 3 6 7 4 8 9 5

Table 6.6. Example of a 10 trials 3 parameter LHS design of experiments


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LHS designs are particularly suitable for numerical designs of experiments. In this case, a very high number of designs are generated and the design which contains the best space-filling and independence criteria is selected. This design is not unique and the space-filling and independence criteria are relative. 6.5. Modeling of the response surface: PLS regression and Kriging The analysis of the results of the DOE plan consists of modeling the values of the response according to the various cofactor values defined by the design of experiments. The choice of the method depends on the objective of the study. If the objective is to describe or predict the behavior of the system according to the combination of values taken by the cofactors, then regression-type methods are used. If the objective is to find the optimal value of the system then Kriging methods are used. 6.5.1. PLS regression Partial least square (PLS) regression is a statistical exploratory method [DUV 10] which is used to analyze large-scale “individual variable” tables when the variables are quantitative or qualitative. Its objective is to summarize the information contained in the data in order to make it easier to use. PLS regression aims to explain a collection of target variables Y (response) using a collection of explanatory variables X (descriptors, predictive variables and cofactors). To do so, the descriptors are summarized in a series of factors th (factorial axes, components and X scores) which are orthogonal two by two. Unlike principle component analysis (PCA), these factors are arranged in such a way so as to best explain Y (as well as summarizing the information as best as possible). In the same way, the target variables are summarized in a series of components uh (Y scores). The orthogonality constraint is not applied to these, as they are mainly useful for interpretation.

Meta-Model Development


During the modeling process, the PLS regression builds a series of factors (uh, th) so that their covariance is maximized. The number of factors cannot exceed the number of explanatory variables. PLS regression is a particularly suitable method when: – there is a strong correlation (or co-linearity) between the explanatory variables, as linear regression in this case can lead to incoherent interpretations; – the number of explanatory variables is higher than the number of observations. To carry out a PLS regression, it is necessary to determine: – the number of factorial axes: this number is selected by cross validation from indices measuring the marginal contribution of each PLS axis th to the predictive power of the model; – the number of variables: this number is chosen with the help of a criterion called variable importance for the projection (VIP), which characterizes the relative importance of variables in the explanation of the values of Y. The variables whose VIP is higher than 0.8 are deemed important. The process for carrying out a PLS regression is as follows: – choose the number of factorial axes (by cross validation) and then the number of explanatory values (VIP criterion); – recalculate the factorial axes with the help of the variables conserved from the previous step; – reselect the number of factorial axes and explanatory variables to retain, as well as the number of explanatory variables. This iterative procedure leads to an efficient synthesis of the initial information. The overall quality of the regression is given by the proportion of variance explained by the explanatory variables for the descriptors X and response Y. Table 6.7 summarizes these proportions, both individually for each axis and combined for the first three axes.


Embedded Mechatronic Systems 2

In the case of descriptors X, the proportion of the variance explained corresponds to the quality of representation of the variables on the axes. In the case of response Y, it corresponds to the explanatory power of the model. Descriptors (X) Axis

% individual

% combined

Response (Y) % individual

% combined
















Table 6.7. Example of the quality of a PLS regression: proportion of the variance explained by the descriptors X on three factorial axes and proportion of the variance of the response Y explained by the 3 factorial axes

The first three components explain approximately 60% of the variation of the descriptors. Regarding response Y, the predictive power of the model is good, since 95% of the variations of the response are explained by the first three components.

6.5.2. Kriging Kriging is a method of spatial interpolation. It was introduced in the 1950s by the mining engineer D.G. Krige, who wanted to predict the spatial distribution of minerals using a drilling assembly. The basic idea of Kriging is to predict the assumed values by a natural phenomenon in any site using observations of this phenomenon in neighboring observation sites. The prediction (Figure 6.6) is created so as to constitute a linear combination of the neighboring observation sites.

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Figure 6.6. Prediction versus observation graph

Kriging gives the best unbiased linear estimation of the punctual values of a variable, in terms of minimum variance. The variable y to be estimated can be represented by the following model:

y ( x) = F ( x) + z ( x)


– F(x) is the regression model known as a “global” approximation;

– z(x) is the spatial correlation model known as “local” deviations. The concept of Kriging is to consider that spatial correlation is a decreasing function of the distance between the points (in the space of input variables x). The theory is that the variable being interpolated can be treated as a regionalized variable. A regionalized variable is an intermediate between a truly random variable and a completely deterministic variable, since it constantly changes from one place to another. Consequently, the points which are close to each other have a certain degree of spatial correlation (they have a degree of “resemblance”), but points which are separated by large distances are statistically independent.


Embedded Mechatronic Systems 2

In this type of model: – the function F(x) can be chosen as a constant, linear or polynomial function of input parameters x; – the function z(x), also known as the correlation model, is zero (E(z) = 0) according to an expectancy assumption and has a known dependence structure (in the Kriging model, errors are supposedly spatially dependent). The correlation model z is chosen to represent the behavior of a random variable with an average of zero, interpolating the m sites of the sample of data available, so that the variance is minimized over all of the m sites. Figure 6.7 displays an example of spatial interpolation results obtained using the Kriging method. Such a model can be implemented using the Matlab toolbox Design and Analysis of Computer Experiment (DACE), which was especially designed to use Kriging, especially for numerical models.

Figure 6.7. Example displaying data points y(x) to interpolate, versus regression model (R), correlation model (C) and Kriging model (R ) + (C) results

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6.5.3. Model comparison and validation

Once a model is built, the next step is validation. To choose one model or another two properties of the response surface are assessed as to their ability to match the experimental data and make predictions. Certain mathematical criteria make it possible to test how the model results match the data. This is performed by the coefficient of determination R², the adjusted R² coefficient, or the study of the residues, etc. The determination coefficient R², which is the criterion generally used in linear regression to test how the model matches the data, is defined by: n

R2 = 1 −


− yi ) 2




i =1 n



− y)

i =1

where y is an estimation of the average response and n is the number of points in the design of experiments. The R² criterion can be used to measure the percentage of the total variability of the response explained by the model. This coefficient should not be used to compare between various models, since it is highly dependent on the model used. Indeed, R² increases when the number of terms goes up, even if all the predictors are not significant. 2 To overcome this problem, the adjusted determination coefficient Radj can be used instead, defined by:

2 Radj

n 1 ( yi −  yi ) 2  n − ( p + 1) i =1 = 1− 1 n  ( yi − yi )2 n − 1 i =1



Embedded Mechatronic Systems 2

where p represents the number of terms in the model (constant term 2 is expressed in terms of R², it can be noted that not included). If Radj 2 is always smaller than R² and that the difference between these Radj 2 two coefficients increases with the number of predictors. Radj is,

therefore, a compromise between a model which faithfully represents the variability of the response and a model which is not too rich in predictors. Some methods have underlying hypotheses on the residuals , … , ̂ . For instance, for regression, the residuals are assumed to be centered. A residual analysis may be useful to compare the information provided by the determination coefficients. Once the ability of the model to match the experimental data is checked, a second diagnosis is performed to check the ability of the adjusted surface to perform predictions. The experimental design space represents only a small domain of the possible values for the explanatory variables, whereas the adjusted model must be able to construct an approximate value of the response at any point in the field of study. It is therefore necessary to study if the proposed model can be applied to the total field of study and thus provide accurate predictions. This method consists in comparing the predictions of the model at points which differ from those of the design of experiments. In the case where the number of feasible simulations is not constrained, it is possible to define a set of test points on which the prediction error criteria (MAE, RMSE, etc.) are evaluated. If not, it is possible to use cross-validation techniques. In order to study the predictive qualities of the model, it is assumed that there are a reasonable number of test points. The indicators proposed below generally measure the mismatch between the prediction calculated by the adjusted model and the value of the response given by the simulator.

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The determination coefficient R² evaluated over a test process (also known as external R²) gives an indication of the prediction ability of the meta-model. The value of R² can be negative, meaning that the model creates variability in comparison to a model providing constant prediction mismatch. The mean square error (MSE) corresponds to the mean of the square of the prediction errors (L2– criterion method): MSE =

1 n ( yi −  yi ) 2  m i =1


where m represents the number of data from the test set. This criterion measures the mean square error of the mismatch between the predicted results and the test data. A low MSE value means that the predicted values match the real values. The root mean square error (RMSE) criterion can also be used. It is defined by: RMSE = MSE The RMSE depends on the order of magnitude of the observed values. It may, therefore, vary significantly from one application to the next. There are two ways to solve this problem. The first solution is to center and reduce the response (which is the solution usually taken). The second solution is to consider the criteria as being relative both in terms of mean (RRM) and standard deviation (RRE) defined as follows:


yi 1 m yi −   m i =1 yi

y − yi  RRE = Var  i  yi   




Embedded Mechatronic Systems 2

The mean absolute error (MAE) criterion (which corresponds to standard L1) is defined by: MAE =

1 m  | yi − yi | m i =1


This criterion is similar to the RMSE coefficient. Nevertheless, it is more robust since it is less sensitive to extreme values than MSE. All distance measurements (MSE, RMSE and MAE) are equivalent and make it possible to quantify how the approximated solutions match the simulated data. A small value for these criteria means that the estimated model is able to predict the values of the response of the more complex model. PLS regression Kriging


Cmix 1.4×10-4 1.4×10-2 2×10-5 5.4×10-3

PdC 2.6×10-7 1.6×10-2 1.2×10-8 3.6×10-3

BPR 2.7×10-2 2.2×10-2 4.3×10-4 2.6×10-3

Table 6.8. Comparison of MSE and MAE criteria results for two meta-models (PLS regression and Kriging) on three responses Cmix, PdC and BPR

6.6. Sensitivity analysis of decomposition, Sobol criterion




6.6.1. Principle

The objective of the sensitivity analysis is to evaluate how disturbances on the input values of the model lead to disturbances on the response. The overall sensitivity analysis examines how the variability of the input data impacts the variability of the response, determining what portion of the variance of the response is explained by a given input or a given set of inputs.

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The sensitivity analysis makes it possible to highlight the most influential input variables, namely those which contribute to the variability of the response. To make a parallel with PLS regression, the results of the sensitivity analysis are comparable to the graph of contributions produced using the VIP criterion. Various methods for carrying out a sensitivity analysis exist. However, in this chapter, only the global methods based on variance decomposition and on the Sobol sensitivity indices are presented. The sensitivity indices to be used are selected according to the characteristics of the model: – if the model is linear, then standardized regression coefficient (SRC) or partial correlation coefficient (PCC) indices based on traditional linear regression can be used; – if the model is nonlinear, but monotone then standardized rank regression coefficient (SRRC) or partial rank correlation coefficient (PRCC) indices, identical to the previous indices but based on the transformation of classifications can be used; – if the model is nonlinear and non-monotone, then the Sobol index is the most suitable. The advantage of the Sobol index approach is that it can be applied to any type of model. Prior hypotheses of linearity or monotony from the model are not required. In the case of a mathematical model, composed of a collection of random input variables X = (X1, …, Xp), a deterministic function f, and a random output (response) variable Y, the Sobol method is applied to decompose the function f in Y = f(X) into a sum of functions with increasing dimensions. In other words, function f is decomposed in the same way as for an analysis of variance (ANOVA) into fixed


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effect, principle effects, effects linked to double interactions, and so on: p

f ( x1 , , x p ) = f 0 +  f i ( xi ) + i =1

f i , j ( xi , x j ) +  + f1,2,, p ( x1 , , x p )

1≤ i < j ≤ p

Following this approach, it can be shown that the variance V can be expressed in the same way as: p

V =  Vi + i =1

V j +  + Vi p


1≤ i < j ≤ p

This means that the total variance is equal to the sum of the variances of each variable, plus the sum of the variances of double interactions plus etc. The first and second order of the Sobol sensitivity indices (Si and SU respectively) are defined by: Si =

Vi V ( E [Y | X i ]) = V V

S ij =

Vij V



The total sensitivity index expresses the total sensitivity of variance (V) on a given variable, which is the sensitivity of this variable in all its forms:

STi =  S k k#i

where #i represents all the sets of indices containing the index i.


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6.6.2. Application of Kriging to a model

To calculate the Sobol indices for the response of the design of experiments, two steps are required: – verification of the monotony of the response dependent on the input parameters; – calculation of the Sobol indices with the help of a Matlab toolbox, the “SA interface”, which helps display the indices in the form of box plots. N simulations are carried out with the input parameters. The response is calculated (using the Kriging model). Subsequently, in order to study the sensitivity of one of the parameters, another sample is produced for all the other parameters apart from this one. This step is repeated many times by bootstrap. Subsequently, in order to study the sensitivity of one of the parameters, another sample is produced for all the other parameters apart from this one. This step is repeated many times by bootstrap. The Sobol indices for the parameter studied are then calculated, using the total variance and the variances relating to the parameter studied. A statistical distribution is obtained for each index, which is represented in the form of a boxplot, helping to estimate a trust interval for the value of the index. Two indices are calculated: – the first-order index for parameter Xi which expresses the sensitivity of the response variance to parameter Xi; – the total index for parameter Xi, which expresses the total sensitivity of the response variance to parameter Xi, which is the sensitivity of this parameter in all its forms (Xi, Xj, …). One thousand simulations are carried out to simulate the input parameters and 100 Sobol indices are calculated. Figures 6.8 and 6.9 present the results of the Sobol index in the form of a boxplot (). In these graphs, the abscissa corresponds to the 15 input parameters (one index per parameter), the ordinate to the median value of the index, and to its confidence interval.


Embedded Mechatronic Systems 2

Figure 6.8. First-order Sobol index

Figure 6.9. Total Sobol index

6.7. Robust design

Once the factors having a strong effect on the response are identified, Monte Carlo simulations are carried out in order to determine the distribution of the response, according to the variations of these factors.

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In this approach: – for each factor which does not have a strong impact on the response, the nominal value is attributed; – for each factor of significant impact, a uniform sampling is produced in its variation domain. Here, the most neutral hypothesis possible is recommended, unless previous experience suggests specific distributions; – finally, the value of the response is calculated by the validated model (in this case, the Kriging model). This procedure is repeated a lot of times (107) in order to obtain the response distribution. The factors having a significant effect on the response and which can be controlled by the designer are called control factors. The factors which are not under control are called noise factors. This method is applied to the case study of Chapter 1, Volume 1 [EL 15] to adjust the Kriging model of the stresses applied on a solder joint of a microcontroller component. This solder joint is a design element which is critical for the reliability of the mechatronic system.

Figure 6.10. Procedure to estimate the distribution of the stress on the solder joint

Figure 6.10 displays the procedure applied to obtain the distribution of this stress distribution in this critical solder joint. The histogram of the calculated stress is shown in Figure 6.11.


Embedded Mechatronic Systems 2

Figure 6.11. Histogram of the stress (MPa) on the critical solder joint

This distribution can be estimated by a parametric model, e.g. a model mixing Gaussian distributions. An algorithm based on expectation maximization (EM) is then used to estimate the parameters of the solder joint stress probability density (Figure 6.12).

Figure 6.12. Estimation of the probability density of the stress applied on the solder joint

The objective of robust design is to adjust the level of the control factors reducing the sensitivity of the system to sources of variability (noise factors) and enabling the response of the system to reach its target (objective).

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Once the solder joint stress distribution is estimated (with its mean and range of variation), it is necessary to set the maximum stress value which should not be reached, and then optimize the control parameters so that the probability of having a stress below this maximum value is as high as possible (e.g. > 99%) (see Figure 6.13).

Figure 6.13. Principle of robust design

In the case of this specific solder joint, the Sobol index method proves that the ALPX COMP factor (thermal expansion coefficient in X direction of the package of the component) has a strong effect on the applied stress (positive influence). Thus, stress in the solder joint can be reduced if the domain of variation of this factor is controlled. Figure 6.14 shows the stress distribution for a restricted domain of variation of ALPX COMP factor.

Figure 6.14. Optimized distribution of the stress (MPa) on the solder joint


Embedded Mechatronic Systems 2

If the maximum acceptable value of the stress is set at 60, then the probability of having a stress below this critical value is higher when the domain of variation of factor ALPXCOMP is under control Moreover, the mean stress in the solder joint which was originally at a value of 58 is reduced to 44. Figure 6.15, which displays the optimized and non-optimized stress distributions, shows that the distribution of the stress on the solder joint can be optimized by adjusting control factors.

Figure 6.15. Comparison of the optimized and non-optimized solder joint stress probability density distributions

6.8. Conclusion

In this chapter an approach for optimizing the reliability of the structures of mechatronic systems is presented. This probabilistic approach is based on multi-physics finite element models of failure mechanisms. In order to reduce calculation time, a meta-model of the failure mechanism model is developed using numerical designs of experiments. The co-factors which have a significant effect on the response of the system are selected using a screening method. A set of numerical experiments is created. A response surface is obtained from the data using the Kriging method. Once the meta-model is validated a sensitivity analysis is carried out using the Sobol index method. In order to reduce the sensitivity of the system to significant sources of variability and allow the system response to respect specifications, the

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control factors of the meta-model are adjusted. Optimizing the strength of the system to failure causing stresses leads to the optimization of the design (robust design). 6.9. References [DUV 10] DUVEAU C., AIT-AMIR B., Analyse statistique par la méthode PLS des vibrations d’un turboréacteur, article LambaMu, 2010. [EL 15] EL HAMI A., POUGNET P., Embedded Mechatronic Systems – Volume 1, ISTE Press Ltd, London and Elsevier Ltd, Oxford, 2015. [FRA 08] FRANCO J., Planification d’expériences numériques en phase exploratoire pour la simulation des phénomènes complexes, PhD Thesis, 2008. [GOO 11] GOOS P., JONES B., Optimal Design of Experiments, John Wiley & Sons, 2011. [GOU 05] GOUPY J., Pratiquer les Plans d’Expériences, Dunod, Paris, 2005. [MYE 09] MYERS R., MONTGOMERY D., ANDERSON-COOK C., Response Surface Methodology, John Wiley & Sons, New York, 2009. [RAS 11] RASCH D., PILZ J., VERDOOREN R. et al., Optimal Experimental Design with R, CRC Press, Boca Raton, 2011. [VIV 02] VIVIER S., Stratégies d’optimisation par la méthode des plans d’expériences et Application aux dispositifs électroniques modélisés par éléments finis, PhD Thesis, 2002.

7 Probabilistic Study and Optimization of a Solder Interconnect

Electronic boards are composed of three sub-elements: a printed circuit board (PCB), electronic components and solder joints that enable mechanical and electrical interconnections between the components and the board. Modeling can be used to analyze and predict aging and fatigue phenomena in solder interconnects caused by temperature cycles. In this chapter, a probabilist study of the stress in a solder interconnect is presented. This approach takes into account uncertainties resulting from the random nature of temperature fluctuations, the geometric dimensions of an electronic assembly and the properties of materials. The assembly of a mechatronic system may fail if these uncertainties are ignored. Probabilistic methods are used to improve the ability of the design to resist stresses and to estimate the impact of parameter uncertainties regarding structure robustness. The volume of the solder interconnect is optimized to improve its resistance to thermomecanical stresses caused by thermal cycles.

7.1. Introduction The applications of mechatronics systems have been considerably developed since the beginning of the 1980s. In fields such as transportation (hybrid car, bus, tram, railway, etc.), renewable energy, telecommunications, space, etc., require faster response times, more compact dimensions, more complex performances, lower power consumption, lower fabrication costs and improved reliability.

Chapter written by Bouchaib RADI, Nadia SAADOUNE and Abdelkhalak EL HAMI.


Embedded Mechatronic Systems 2

Finite element modeling (FEM) is widely used to evaluate how the structures of a system react to thermal, mechanical, electromagnetic and combined stresses. The modeling of electronic boards has taken a considerable step forward recently and the need for simulation has become essential in mechatronics. Modeling reduces both the time to market and the development costs. It also makes it possible to increase the reliability of the designed systems. Probabilistic design is a technique for analyzing the effect of uncertain input parameters on the response of a finite element model. It is used to determine the extent to which model parameter uncertainties affect the response. Uncertainty (or random quantity) is a parameter whose value is unknown at a given time (if it is timedependant) or in a given place (if it is space-dependant). An example is the ambient temperature. In a process of designing a mechatronic system, optimization occurs throughout the different levels of modeling. At the highest level of design, optimization enables the choice between logical and physical architectures, those that best meet the objectives defined by the requirements of the system and the company strategy. Optimizaton is based on metrics (such as performance, cost, reliability target, availability, etc.). In system design, the response of a mechatronic system is optimized through the correct choice between the multiphysical parameters related to the system parameters. At the level of the detailed design, the choice of the shape, the dimensions and the suitable topology of the components of the retained system design is carried out by a geometrical optimization. The latter is necessary to determine the optimal geometrical configurations taking into account the multi-physical constraints. 7.2. Electronic equipment An embedded mechatronic system often consists of several assembled electronic boards, interconnected with each other in order to perform the desired functions. Each electronic board is composed of three sub-elements: a printed circuit board (PCB), electronic components and solder joints that enable the mechanical and electrical connections to be made between the components and the board.

Probabilistic Study and Optimization of a Solder Interconnect


7.2.1. Printed circuit board The printed circuit board (PCB) attaches and connects together a set of electronic components. The PCB has multiple layers, consisting of alternating copper conductive layers (CU) and fiber glass dielectric layers (FR4) or other insulating materials (Figure 7.1). The number of copper layers varies between a single layer of copper and several layers of copper and insulating materials stacked on top of one another.

Figure 7.1. Diagram of the layers of the PCB. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

7.2.2. Electronic components An electronic system has various components, which can be classified according to the way technology is used to attach them to the PCB such as through pin lead wire technology, lead components, ball grid array (BGA), or surface-mount technology (SMT) (Figure 7.2).

Figure 7.2. Interconnection modes. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip


Embedded Mechatronic Systems 2

7.2.3. The solder materials Most connections between the various components of an electronic board are made by solder joints (chip/substrate, substrate/sole, metal/ceramic). These interconnects have thermal and mechanical functions. Solder interconnects attach the copper transfer pads on the PCB to the metal terminations of the component. Soler joints provide mechanical support, allow heat flow and good electrical contacts. The soldering process is essential to ensure the reliability of an electronic system [DOM 11].

Figure 7.3. Leadless surface-mounted component

Figure 7.4. Solder ball of a BGA component

7.2.4. Solder alloys Solder materials were traditionally made of lead-based alloys but recently, the use of lead has been banned because of its toxicity.

Probabilistic Study and Optimization of a Solder Interconnect


The choice of a solder alloy is based on its melting temperature, which is much lower than that of the two solids to be assembled [KOR 07]. A solder alloy should satisfy several criteria: low electrical resistivity for the assembly (current circulation), good thermal conductivity to ensure the evacuation of the calories dissipated within the chips, a coefficient of thermal expansion (CTE) close to the assembled elements and good mechanical strength of the solder.

Figure 7.5. QFP (Quad Flat Package)

Figure 7.6. Cross section of a leaded solder component attached to a PCB


Embedded Mechatronic Systems 2

Component pin

Solder paste

PCB: printed circuit board Figure 7.7. Cross section of a leaded solder joint

7.3. Thermal modeling of the electronic board The electronic board is modeled on a parallelepiped as it is the most widespread form in electronics. It can exchange heat with the environment through different modes of transfer. Heat exchange will occur naturally between the board and the environment as soon as there is a temperature gradient, no matter the medium considered. Three types of transfer are to be considered: conduction, convection and radiation. These three modes of exchange will interact at the electronic board level. Heat dissipation of the components occurs most often on the surface, so any volume dissipation produced within the board, such as the joule effect in the tracks, can be neglected. 7.3.1. Boundary conditions Boundary conditions are of several types: – Dirichlet condition: a temperature distribution is set on the boundaries of the domain. = ( , ) for a map orthogonal to the z axis


Probabilistic Study and Optimization of a Solder Interconnect


The set of points having the same temperature will define an isothermal surface. – Neumann condition: a flux density is set on the walls of the domain:  ∂θ ( x, y, z )i  = f ( x, y ) on the z axis  ∂z   z = z0


ϕ = − k z ,i . 

The adiabatic case corresponds to the particular case where the flux density is zero. – Fourier condition: a convective flow is exchanged between the solid and the fluid medium, with displacement of matter. This can be expressed by the following relation where ϕ is the thermal flux density, T the solid temperature and Tref is the cooling fluid temperature: ϕ = h c . (T − T




The parameter hc represents the coefficient of thermal convection. Conventionally, the plate is likened to a plane plate and an empirical correlation based on a set of adimensional parameters, such as Grashoof (Gr), Prandtl (Pr) or Rayleigh (Ra) numbers for natural convection, which provides the value of this coefficient. For example, if one considers a plate subjected to a uniform temperature, the expression of h can be written in the form: h



k A .C . L


rL . P r




k A .C . L







7.3.2. Modeling the soldering of an electronic component Most solder interconnects are fabricated by a thermal reflow soldering process. The solder powder and flux are preblended to form a solder paste material which is deposited by stencil technology onto the PCB pads. The SMT components are then placed. The solder paste


Embedded Mechatronic Systems 2

serves as a temporary glue and holds the components in place prior to the soldering process. The board is then heated above the liquidus temperature of the solder to reflow the solder powder. At this temperature, the flux reacts and removes oxides of both the solder powder and the metallization of leads and pads which allows the solder to form solder joints. Simulation model Finite element simulations were performed using ANSYS Mechanical (APDL) software. The course of the simulations is done in three stages. First is the “preprocessing” phase, which is the phase during which the geometry of the model will be constructed (Figure 7.8) with its mesh and the type of elements that will be used. We will also define the behavior of the different material parameters as well as the boundary conditions in the ANSYS thermal and thermomechanical simulation software.

Figure 7.8. Geometric model

The SOLID70 element has a 3D thermal conduction capability. This element has eight nodes with a single degree of freedom at each node. The element is applicable to 3D thermal analysis, at stable or transient state. The element can also compensate for mass flow from a constant velocity field of heat. The element can be replaced by an equivalent structural element like SOLID185 or SOLID90.

Probabilistic Study and Optimization of a Solder Interconnect


Figure 7.9. The SOLID70 element

Before any simulation, it is necessary to define a mesh adapted to the studied structure, taking care to detail the influential zones (soldering). Figure 7.10 represents the mesh, with the element SOLID70.

Figure 7.10. Finite element model

– Material properties For thermomechanical analysis, using the local model, the solder joint material (SnAgCu) (96.5% tin, 3% silver, and 0.5% copper) is assumed to have a viscoplastic behavior. The development of plastic


Embedded Mechatronic Systems 2

deformations in the solder joint material depends on the loading speed. Many authors have studied the response of lead-free solder joints (SnAgCu) and proposed equations modeling this response. One of the models developed is the Anand model [ANA 82]. It integrates viscoplasticity and time-dependent plasticity. Wang et al. [WAN 01] propose a unified framework for the viscoplastic behavior of SnAgCu materials which are called Anand’s equations. The parameters of the SnAgCu material of the Anand model are obtained from the experimental results. These parameters are presented in Table 7.1 [WAN 01]. Material properties




Young’s modulus (GPa)




Poisson’s ratio




Density (Kg/m3)




CTE (K (–1))




Shearmodulus (GPa)




Table 7.1. Material properties

Anand’s model [ANA 82] differentiates between elastic and inelastic deformations, but combines creep and instantaneous plastic deformation into one term. This is justified by the hypothesis that inelastic deformations, whether time dependent or not, are supposed to come from the same mechanisms (dislocation movements). This is why many studies have used the Anand model in the description of SAC alloys. – Boundary conditions and loading When dimensioning electronic components, temperature acts as the main constraint. To simulate the effect of operational thermal loads, thermal cycles are applied to the structure under study. The duration of the temperature cycle is 60 min and the temperature varies from -40 °C to 150 °C [JED 00].

Probabilistic Study and Optimization of a Solder Interconnect


Figure 7.11. Fracture of a solder joint under a lead [CIA 02]

Figure 7.12. Distribution of inelastic strain in the solder joint. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Figure 7.12 shows that temperature cycles cause plastic deformation in solder joints of electronic board components. The accumulation of these thermomechanical stresses can lead to the beginning of cracks in the solder joints. These cracks propagate very rapidly because of high temperature amplitudes that impose high thermomechanical stresses [RAD 16]. The resulting solder joint breakage and delamination causes a mechanical failure of the component of the electronic board and the electrical failure of the complete electronic system.


Embedded Mechatronic Systems 2

– Measurement of crack propagation velocity The propagation velocity of the cracks in the solder is given by the following equation:

ν σ

d a d N = E ε


(μ m

c y c le )



with a being the length of the delaminated zone and N the number of cycles that led to this delamination. The length of the cracks varies very slightly during the cycling and, for this reason, the average crack propagation speed is considered as being the ratio between the crack length at the end of the cycle and the number of cycles that led to this crack. ν =


a f

− N0



where N f and N 0 respectively are the total number of cycles and the number of cycles initiating the cracks. The length a is measured along a line forming a 45° angle at each corner of the solder. – Effect of the mesh An iterative process is used to optimize the mesh of the elements of the model and thus the accuracy of the results. The main stages of convergence of the mesh are: - create a mesh using a reasonable number of elements, and then analyze the model; - recreate the mesh by increasing the mesh density, recalculate it, and compare the results with the first calculation; - continue to increase the mesh density, re-analyze the model, then check that the results converge satisfactorily.

Probabilistic Study and Optimization of a Solder Interconnect


Figure 7.13. Mesh (10922 elements)

Figure 7.14. Refined mesh (86853 elements)

This type of mesh convergence study has made it possible to have good numerical results, with a sufficiently dense mesh.


Embedded Mechatronic Systems 2

Figure 7.15. Response of the solder after refinement of the mesh. For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

7.4. Probabilistic study of the effect of thermomechanical stresses on a solder joint To correctly model a structure, it is necessary to integrate the sources of uncertainties. Three major sources of uncertainty can be identified: – environmental elements (temperature, current, operating conditions) which are at the origin of the loads applied to the structure; – geometric and mechanical data characterizing the structure; – the imperfect nature of the theoretical models used to represent phenomena (idealizations, imperfections, misunderstanding of problems, etc.). To cope with uncertainties and dispersion, the following questions should be answered: – If the input variables of a finite element model are subject to diffusion, what is the dispersion of the output parameters? What is the robustness of the output parameters? We can site as examples the

Probabilistic Study and Optimization of a Solder Interconnect


maximum temperature, stress, deformation or deflection of the model, etc. – If the output is broadcast due to the variation of the input variables, what is the probability that a given design criteria for the output parameters will no longer be met? What is the probability that an unexpected and unwanted event will occur (what is the probability of failure)? – Which input variables contribute the most to the dispersion of an output parameter and the probability of failure? What are the sensitivities of the output parameter with respect to the input variables? 7.4.1. Probabilistic design methods Several probabilistic design methods are available. The main methods are: the Monte Carlo simulation and the response surface method [ANG 75]. The options of the Monte Carlo simulation method include the Latin hypercube sampling method and the direct sampling method. The response surface method options include the central composite design and the Box–Behnken matrix design method. Monte Carlo simulation The Monte Carlo simulation is the most common and traditional method for probabilistic analysis. This method makes it possible to simulate the effect of loads and specific boundary conditions on a component. For Monte Carlo simulations, either direct sampling or Latin hypercube sampling methods are used. Response surface analysis methods Response surface analysis is based on the fundamental assumption that the influence of random input variables on the random output parameters can be approximated by a mathematical function. Therefore, the response surface methods locate the sampling points in the random input variable space so that an appropriate approximation


Embedded Mechatronic Systems 2

function can be found as efficiently as possible; typically, it is a quadratic polynomial. In this case, the approximation function is described by:

Yˆ = C









  i=1

C ij X i . X



j =1

where C 0 is the coefficient of the constant term, ci , i = 1, ... NRV are the coefficients of the linear terms and cij , i = 1, ... NRV and j = i, ..., NRV are the coefficients of the quadratic terms. To evaluate these coefficients, a regression analysis is used and the coefficients are usually evaluated so that the sum of the squared differences between the true simulation results and the approximation function values is minimized [ALL 71]. The basic principle of surface response methods is that once the coefficients of an appropriate approximation function are found, then this approximation function can be used instead of looping through the finite element model. To perform a finite element analysis, minutes to hours of computation time can be spent, whereas the evaluation of a quadratic function requires only a fraction of a second. Therefore, the use of one approximation function makes it possible to evaluate the approximate response parameter numerous times. 7.4.2. Effect of the probability of properties of materials Damage to the solder results from the accumulation of mechanical stress in the CTE (coefficient of thermal expansion) between the materials. The probabilistic study is used to quantify the uncertainties of the properties of the material in the context of the numerical model. For temperature-dependent materials, the randomness is expressed by separating the dependence of the temperature from the scattering effect. In this case, the average values of the properties of the materials are required. If M (T) denotes an arbitrarily temperature-

Probabilistic Study and Optimization of a Solder Interconnect


dependent material property, the following methods propose the following: – multiplication equation: M (T )rand = Crand M (T )


– additive equation: M (T )rand = M (T ) + ΔM rand


– linear equation: M

(T )r a n d

= C rand M

(T ) +




where M (T ) is the average value of the material property as a function of temperature. In the multiplication equation, the function of the mean value is scaled with a Crand coefficient and this coefficient is a random variable describing the dispersion of the material property. In the “additive” equation, a random variable ΔM rand is added to the average value M (T ) . The linear equation combines the two

approaches, and Crand and ΔM rand are random variables. However, one must take into account that for the “linear equation” approach, Crand and ΔM rand are correlated. Young modulus The Young modulus, or the modulus of elasticity, is the constant that relates the tensile (or compression) stress and the deformation for an isotropic elastic material:

σ = E .ε where σ is the stress, E is Young’s modulus and ε is the strain.



Embedded Mechatronic Systems 2 Coefficient of thermal expansion (CTE) Due to the inadequacy of the thermal expansion coefficients of the various materials assembled, the assembly undergoes deformations, resulting in the appearance of thermomechanical stresses in the solder joints. These can lead to the degradation of these joints, as well as create difficulties for assemblies. The coefficient of thermal expansion (CTE) α defines the relationship of proportionality that exists between the relative elongation ΔL L of a material for a change in temperature ΔT and is expressed in ppm/°C or (ppm/K).

ΔL = α × L × ΔT


where ΔL is the variation of the length in meters [m] and α is the coefficient of thermal expansion in 1/Kelvin [K–1], L is the initial length in meters [m] and ΔT is the variation of temperature in kelvin [K]. For tests carried out on the electronic boards, it can be assumed that: – The coefficient of thermal expansion (CTE) varies according to the temperature range. The value of the CTE is lower on the temperature range that is higher. – Few deformations were observed on the materials of the chip and the substrate. On the contrary, there is a lot of deformation on the materials constituting the solder. The CTE of the solder is therefore more important than that of the chip and the substrate. In certain cases, the uncertainties of Young’s modulus or of the coefficient of thermal expansion have a strong effect on the component under study. To carry out a thermal analysis and evaluate the thermal stresses (the thermal stresses are directly proportional to Young’s modulus as well as to the coefficient of thermal expansion of the material), the following equation can be used:


th e r m

= E .α . Δ T


Probabilistic Study and Optimization of a Solder Interconnect


If Young’s modulus has a Gaussian distribution with a standard deviation of 5%, then there is a 16% probability that the stresses are 5% higher. This probability increases if the coefficient of thermal expansion is described by a Gaussian distribution. When Young’s modulus and the coefficient of thermal expansion are random input variables, a full quadratic regression model reads as follows:


th e r m

= c 0 + c 1 . E + c 2 .α + c 3 . E .α


A full regression model uses the available sampling points to determine the values of all the regression coefficients C0 at C3 . Of course, the values of C0 at C2 will be zero or very close to zero, by taking into account the coefficients necessary to reduce the degrees of freedom of the algebraic equation to solve in order to evaluate these coefficients. This, in turn, reduces the precision of the coefficients that are important for the regression fit. Young’s modulus and the coefficient of thermal expansion both have a linear effect on thermal stresses.

7.4.3. Analysis of the variability of the properties of materials The thermomechanical modeling of the electronic board must take into account the propagation of the uncertainties by relying on a probabilistic modeling of the fluctuations of the input parameters. This approach, which is often called mechano-probabilistic modeling, calculates the impact of uncertainties regaring the response of the structure. These uncertainties are mainly composed by the hazard of input parameters (geometric dimensions, loading and properties of materials) and modeling uncertainties [ELH 11]. There are several approaches to analyze the propagation of uncertainties in the response of the structure [BLA 09]. In this chapter, the Monte Carlo method and the response surface analysis method (RSM) are used to calculate the variations of Young’s modulus and


Embedded Mechatronic Systems 2

the CTE. In the probabilistic analysis of the solder response, thirteen influential parameters are considered as random variables. They are classified in three categories (see Table 7.2): parameter loading, geometric parameters and material parameters. Inelastic deformation is the output variable (response) of the probabilistic analysis [ASS 12]. Average

Standard deviation

Distribution law

TF (°C)




BRAS_EP (mm)




BRCH_H (mm)




BRCH_L1 (mm)
























FR4_CTEXY (µm/K)
















Random parameters Thermal load parameters

Geometric parameters

Material parameters

Table 7.2. Random variables of the probabilistic analysis

The effect on the response (inelastic strain) of the random variation of Young’s modulus and the coefficient of thermal expansion are studied by two probabilistic methods: the Monte Carlo simulation and the RSM.

Probabilistic Study and Optimization of a Solder Interconnect


The results are presented in Table 7.3: Monte Carlo simulation (MCS)

Response surface analysis method (RSM)

final initial



final initial



Young’s modulus (EX) (GPA)







Coefficient of thermal expansion (CDT) (K–1)







Table 7.3. Variation of the random variables of the probabilistic analysis

Young’s modulus varies between 43.1 and 57.6 for the Monte Carlo simulation and between 31.6 and 53.1 for the RSM probabilistic method. The CTE varies between 11.7 and 23.8 for the Monte Carlo simulation and between 19.4 and 23.5 for the RSM probabilistic method [RAD 16]. 7.5. Optimization of the solder joint In a multi-disciplinary design such as mechatronics, optimization is part of the design process at different levels of modeling. At the detailed design level, the geometric optimization method makes it possible to define the appropriate shape, dimensions and topology of the components of the chosen solution. These geometric configurations can be closely related to the physical parameters of the components. A geometrical optimization with weak or strong multiphysics coupling is necessary to find the optimal geometrical configurations taking into account the multi-physical constraints. In addition, the complexity of the mechatronics system increases the size of the optimization domain. Some optimization algorithms can provide results if only a few design variables are considered, but become ineffective when there is a high number of variables [TOU 08]. The challenge of multi-disciplinary optimization in the


Embedded Mechatronic Systems 2

design process of mechatronic systems is closely related to the interaction between the different problems related to the design method and the modeling tools. However, for the design of a mechatronic system, it is common to explore geometric configurations in order to find the optimal configuration.

Figure 7.16. Implementing the optimization of structures

7.5.1. Multiobjective optimization (MOO) The treatment of the problem of designing a mechatronic system in a global way makes it possible to define a set of inputs/outputs with objectives for which a single evaluation function is fixed. Therefore, the use of multiobjective optimization is adequate to solve this type of problem. In order to solve a multiobjective problem, the state that obeys a set of constraints and improves a set of objective functions is determined. The constraints are based on parameters that meet requirements. A multiobjective problem is defined as follows [GUI 14]: – A vector of decisions is formed by variables of the problem: =( ,


with n the number of variables



Probabilistic Study and Optimization of a Solder Interconnect


A set of constraints, designated by g i ( x ) with i = 1, ..., m with m the number of constraints. – An objective function vector f defined by: f ( x ) = f1 ( x ) , f 2 ( x ) , ........., f k ( x )


with k the number of goals and f i the functions to optimize. Generally, objective functions f i are defined in such a way that they are minimized. 7.5.2. Optimization using metamodels The term “metamodel”, also called the substitution model, is used to express in a mathematical form the relation between input and output variables (objective functions or constraints) of a complex model [TUN 00]. By knowing the exact value of such a function in a certain number of points called master points, the metamodel makes it possible to replace the evaluation of this function by an approximation. It also makes it possible to carry out a sensitivity analysis in order to study the influence of the input variables on the output variables and to give an exact idea as to the pace of the function studied. It plays an important role in the analysis of optimization problems. Several techniques have been used to build a metamodel. In this section, we present the technique most commonly used: the methodology of RSM polynomial response surfaces. Response surface methodology (RSM) Response surface methodology (RSM) is considered to be a combination of mathematical and statistical techniques necessary for the improvement, development and optimization of complex processes [MYE 09]. This technique is widely applied in the industrial sector, especially when input variables have a large influence on output variables results. It is known by other names, such as the polynomial model in [JIN 05] and the polynomial regression model in [QUE 05].


Embedded Mechatronic Systems 2

– Construction of the RSM model The RSM consists of representing a function f as being the sum of a polynomial of low degree of order one or two at the most and of a term expressing an error e having a variance equal to σ 2 and a normal distribution with a mean zero E (e) = 0. For example, a second-order polynomial metamodel with two input variables x1 and x2 (also called regression variables) is considered. The answer f is represented as follows: f = α


+ α 1 x 1 + α 2 x 2 + α 1 1 x 12 + α


x 22 + α 1 2 x 1 x 2 + ε [7.17]

The expression of f is called the multiple linear regression model [MYE 09] and the coefficients αi , i = 0, ..., n are called the regression coefficients. Overall, the answer f is written in the following form: f = α0 +




xj + ε


j =1

where n is the number of regression variables. – Validation of the RSM metamodel This refers to most-used metamodel for the minimization of computation time related to the optimization of multi-disciplinary problems. In order to validate the constructed RSM metamodel, the following two aspects must be verified: - the hypotheses proposed to build the RSM metamodel, - and the precision of the RSM metamodel.

Probabilistic Study and Optimization of a Solder Interconnect


– Validation of the hypotheses proposed to build the RSM metamodel The hypotheses proposed to build a RSM metamodel [BON 07, HUA 16] are as follows: - responses must be additively and linearly expressed in terms of the regression variables, - E ( ε ) = 0 : the average of the error is zero, 2 - Var ε i = σ : the variance of the error is constant for all

evaluation instances X i , - The error is distributed normally, - c o v (ε i , ε



0 , ∀ i ≠ j : the errors are independent.

– Validation of the accuracy of the RSM metamodel Once the RSM metamodel is built and its assumptions are verified, it is very interesting to evaluate its accuracy. The cross validation method can be used to study this accuracy. Each solution i calculated (exact solution) is successively removed from the metamodel and the next metamodel is reconstructed in its absence. The difference between the exact solution f i and that of f − i gives an idea of the prediction error of the metamodel: e − i = fi −  f −i


If the prediction error, given by equation [7.19], is null for all the considered points, then the metamodel is efficient. In this case, the results of the cross validation are visualized by a curve that represents the variation of the approximate solution f − i as a function of the exact solution f i .


Embedded Mechatronic Systems 2

7.5.3. Structural optimization methods Optimization methods are traditional techniques that minimize a function that is subject to constraints [VAN 84]. Several optimization methods are available. Design optimization Design optimization is formulated by the search for the parameters involved in the design which minimize an objective function (initial costs, rigidity, etc.) and verify the mechanical, physical and geometric performance constraints. An optimal design, a design that meets all the specified requirements but requires a minimum such as weight, area, volume, stress, cost and other factors, can be determined [HE 03]. The independent variables in an optimization analysis are the design variables. These variables are quantities appearing in the definition of the problem and whose optimal value is sought. In mechanics, these variables represent the wall thicknesses of a structure, the position and the number of structural members, etc.). These are the unknowns of the optimization problem. The vector of the design variables is indicated by: X = [ X 1 X 2 X 3 ........ X n ]


In the case of structure optimization, the value of a design variable is mostly limited by a lower bound and an upper bound. Design variables are subject to n constraints with upper and lower bounds: X i ≤ X i ≤ X i ( i = 1, 2 , 3 ,  , n )


where n is the number of design variables. Shape optimization Given the increased competition between manufacturers, shape optimization has become a decisive factor in the design of new products involved in almost all areas of engineering science. It consists in determining the best shape, the best internal properties

Probabilistic Study and Optimization of a Solder Interconnect


and/or better working conditions of a structure obeying known constraints, thus producing an extremum (minimum or maximum) of a chosen quantity characterizing the structure [BAN 02]. Most optimization problems consist of shape optimization where one or both ends are variables (Figure 7.17). In the general case of a shape optimization problem, we consider the problem of making the functional extremal:

J  y ( x )  =

x1 x2

F ( x , y , y ′ )dx


J being the form, x the independent variable, y = y (x) and y’ = dy/dx, whose solution is a curve y: y (x) x1 ≤ x ≤ x2 where x1 and x2 can vary by satisfying: y (xi) = Yi (x)i = 1.2. This is an optimization problem with Y1 (x) being the left and Y2 (x) the right border curves.

Figure 7.17. General problem of shape optimization

In simple optimization problems, the solution (the optimum) is most often obtained by searching for the zeros of the derivative of the function to be optimized, or of its gradient in the cases of higher dimension. This provides in most cases local optimals, among which one must find the true optimum. The shape optimization allows modification of the contours of the object, which allows us to have more degrees of freedom. A shape optimization problem is defined by:


Embedded Mechatronic Systems 2

– a model (typically a partial differential equation) which makes it possible to evaluate the mechanical response of a structure; – a criterion that should be minimized or maximized, and possibly several criteria (an objective function can be defined); – an admissible set of optimization variables that takes into account any constraints imposed on the variables. The goal of a shape optimization analysis is to find the best use of material for a body. Typically, this involves optimizing the distribution of the material so that a structure has the maximum rigidity for a set of loads [HE 03]. In shape optimization problems, where the finite element mesh can change from loop to loop, it is important to check the adequacy of the mesh. By specifying the mesh divisions in terms of parameters or absolute size, they can be appropriately modified for each loop. When





f1 ( s )



optimization, the following equation is used: F

(S ) =


 f1 ( S )     f1 ( S in i ) 



where SG is a factor that depends on the purpose of the objective function (-1 for minimization and 1 for maximization) and Sini is the initial value of the design variable. For shape optimization, this value is set by default to the range of motion that was specified when configuring mesh deformation. Simulation results The objective function is the volume of the solder (solder joint thickness multiplied by the area of the contact pad on the PCB). Convergence is studied by two methods: sub-problems and the first-order method. The optimization of the solder volume is studied by two methods: “design optimization” and “shape optimization” (Figures 7.18 and 7.19). The results are presented in Table 7.4.

Probabilistic Study and Optimization of a Solder Interconnect


Figure 7.18. Optimized structure (design). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Figure 7.19. Optimized structure (shape). For a color version of the figure, see www.iste.co.uk/elhami/embedded2b.zip

Initial volume of the solder (mm3)

Optimized volume of the solder (design) (mm3)

Optimized volume of the solder (shape) (mm3)

4.87 × 10–3

4.02 × 10–3

3.65 × 10–3

Table 7.4. Variation of the volume of the solder


Embedded Mechatronic Systems 2

The structure under study is optimized by decreasing the volume of the solder joint by 17% using design optimization and by 25% using shape optimization [RAD 17]. This can be done either by choosing a specific solder paste and reflow process and/or by adjusting the copper pad dimensions on the PCB. 7.6. Conclusion In the mechatronics design process, modeling and numerical simulations have an important place for design verification and validation. Nevertheless, these two tasks are particularly difficult if one deals with the design of mechatronic systems, because mechatronics involves different domains and, consequently, different modeling methods. Simulation results give a local or global understanding of the response of the component area under study. A detailed thermal simulation of an electronic board with several components can be difficult. Many projects have been discussed and work is still ongoing with the permanent objective of simplifying the different parts of the electronic systems while maintaining sufficient representativeness. The understanding of the effects of thermal loads is very important for the optimization of the components of electronic boards of a mechatronic system. This chapter presents a study of the damage of solder joints resulting from the accumulation of the mechanical stresses in the solder due to the difference of CTE between the materials. These mechanical stresses gradually generate cracks in the solder, until delamination and eventually failure. The miniaturization of electronic systems, with the increasing density of electronic boards causes heterogeneity of the thermal and mechanical properties of the materials used. Optimization strategies can improve performance by adjusting the geometric or physical parameters of the structure. Shape optimization methods respond to this need by proposing a new parameterization of the structure, based on the shape of the structure.

Probabilistic Study and Optimization of a Solder Interconnect


7.7. References [ANA 82] ANAND L., “Constitutive equations for the rate-dependent deformation of metals at elevated temperatures”, Transaction of the ASME 104, pp. 12–17, 1982. [ANG 75] ANGUE H.-S. and TANG W.H., Probability Concepts in Engineering Planning and Design, vol. 1, John Wiley & Sons, New York, USA, 1975. [ALL 71] ALLYN R.C., Response Surface Methodology, Allyn and Bacon, Inc., Boston, USA, 1971. [ASS 12] ASSIF S., AOUES Y., AGOUZOUL M. and EL HAMI A., “Modèle numérique pour la simulation probabiliste de la fatigue des joints de brasure des composants électroniques embarqués”, Journées d’études techniques, Marrakech, Morocco, May 2012. [BAN 02] BANICHUK N.V., Introduction to Optimization of Structures, Springer Verlag, New York, USA, 2002. [BLA 09] BLATMAN G., Adaptive sparse polynomial chaos expansions for uncertainty propagation and sensitivity analysis, PhD thesis, Université Blaise Pascal, Clermont-Ferrand, France, 2009. [BON 07] BONTE M.H., Optimisation strategies for metal forming processes, PhD thesis, University of Twente, The Netherlands, 2007. [CIA 02] CIAPPA M., “Selected failure mechanisms of modern power modules”, Microelectronics Reliability, vol. 42, pp. 653–667, 2002. [DOM 11] DOMPIERRE B., Fiabilité mécanique des assemblages électroniques utilisant des alliages du type SnAgCu, PhD thesis, École centrale de Lille, France, March 2011. [ELH 11] EL HAMI A. and RADI B., “Comparison study of different reliability-based design optimization approaches”, Advanced Materials Research, vol. 274, p. 119–130, 2011. [GUI 14] GUIZANI A., HAMMADI M., CHOLEY J.-Y., SORIANO T., ABBES M.S. and HADDAR M., “Multidisciplinary approach for optimizing mechatronic systems: Application to the optimal design of an electric vehicle”, Advanced Intelligent Mechatronics IEEE/ASME International Conference, IEEE, pp. 56–61, 2014. [HE 03] HE X., “ANSYS tutorial”, Department of Mechanical Engineering, University of Minnesota, USA, October 2003.


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[HUA 16] HUANG C., RADI B. and EL HAMI A., “Uncertainty analysis of deep drawing using surrogate model based probabilistic method”, International Journal of Advanced Manufacturing Technology, nos 9–12, pp. 3229– 3240, 2016. [JED 00] JEDEC, Temperature cycling, JESD22-A104-B. JEDEC Solid state technology association, Report, July 2000. [JIN 05] JIN Y., “A comprehensive survey of fitness approximation in evolutionary computation”, Soft computing, vol. 9, no. 1, pp. 3–12, 2005. [KOR 07] KOREN I. and KRISHNA C.M., Fault-Tolerant Systems, Elsevier, Amsterdam, The Netherlands, 2007. [MYE 09] MYERS R.H., MONTGOMERY, D.C. and ANDERSON C.M., Response Surface Methodology: Process and Product Optimization Using Designed Experiments, vol. 705, John Wiley & Sons, Hoboken, USA, 2009. [QUE 05] QUEIPO N.V., HAFTKA R.T., SHYY W., GOEL T., VAIDYANATHAN R. and TUCKER P.K., “Surrogate-based analysis and optimization”, Progress in Aerospace Sciences, vol. 41, no. 1, pp. 1–28, 2005. [RAD 16] RADI B. and SAADOUNE N., “Probabilistic study an embedded system”, IEEE, Doi: 978-1-5090-0751-6/16/2016, 2016. [RAD 17] RADI B. and SAADOUNE N., “Modeling and optimization of an electronic component”, Advances in Theoretical and Applied Mechanics, vol. 10, no. 1, pp. 1–10, 2017. [TOU 08] TOUYA T., Méthodes d’optimisation pour l’espace et l’environnement, PhD thesis, Université Paul Sabatier-Toulouse III, France, 2008. [TUN 00] TUNALI S. and BATMAZ I., “Dealing with the least squares regression assumptions in simulation metamodeling”, Computers & Industrial Engineering, vol. 38, no. 2, pp. 307–320, 2000. [VAN 84] VANDERPLAATS G.N., Numerical Optimization Techniques for Engineering Design with Applications, McGraw-Hill Book Co., Inc., New York, USA, 1984. [WAN 01] WANG G.Z., CHENG Z.N., BECKER K. and WILDE J., “Applying Anand model to represent the viscoplastic deformation behavior of solder alloys”, Journal of Electronic Packaging, vol. 123, Issue 3, pp. 247–253, 2001.

8 High-Efficiency Architecture for Power Amplifiers

This chapter concerns the study of radiofrequency power amplifiers’ reliability, for RAdiowave Detection And Ranging (RADAR) applications, based on gallium nitride transistors. Compared to the literature, this study combines electrical characterization, aging tests and physical analysis. It shows that temperature is the main degradation parameter and the gate contact is a more sensitive transistor element. All analysis tools lead to this conclusion. We also present in this chapter a novel and preliminary electrical model which consists of introducing reliability early in the design phase.

8.1. Introduction Radiofrequency power amplifiers are the key elements in communication and RADAR systems. Their active devices usually operate under high voltage, high electric field and high temperature. In this chapter, we apply physical analysis and techniques to estimate the main reliability parameters. In section 8.2, we introduce time dependent parameters in a large-signal high-electron-mobility transistor (HEMT) model to predict the power amplifier behavior and to take into account the reliability parameters early in the design step. The ways to integrate it in a large signal model are discussed.

Chapter written by Farid TEMCAMANI, Jean-Baptiste FONDER, Cédric DUPERRIER and Olivier LATRY.


Embedded Mechatronic Systems 2

8.2. Main reliability parameters The objective is to identify the main parameters affecting the reliability of a radiofrequency power amplifier, used in Thales RADAR systems [FON 12a]. We choose the AlGaN/GaN HEMT technology as the active device. It combines high mobility due to the heterostructure and the material wide bandgap, shows performances and ability for high power, high frequency and high temperature operation [LEV 99, MAT 09]. Many performance records have been published since the early 1990s [KAW 84, CHI 04, DEF 07, WU 06, JOH 04, THE 05, QUA 08]. Commercial power transistors have been on the market for about 10 years. In spite of their impressive performances, their long-term reliability remains relatively unknown. The AlGaN/GaN heterostructures have to deal with defects coming from the material properties and fabrication process. As a result, many researchers have been led to the evaluation and enhancement of device reliability in working conditions as close as possible to those of the final application [FON 11, FON 12a, FON 12b, FON 12c, FON 12d, FON 12e, ZHA 03]. Influent parameters on the reliability are principally electrical constraints related to high voltage and current operation, and thermal constraints related to the transistor self-heating effects. To establish the hierarchy of these parameters, we rely on aging tests, electrical characterization and physical failure analysis. In this chapter, we present a summary of our investigations. A more detailed presentation is published in Fonder’s PhD dissertation [FON 12a]. 8.3. Methodology We will study the evolution of AlGaN/GaN HEMT performances in RADAR operation (in radiofrequency with pulsed signal and saturation operation). Beyond the component evolution in nominal conditions for over 1,000 h, we focus on parasitic phenomena (such as trapping and heating) and their impact on reliability. Another goal is to determine the most influential parameters.

High-Efficiency Architecture for Power Amplifiers


The chosen methodology is based on many steps, from the amplifier design to microstructural analysis of the transistor failure zones, including aging tests and electrical characterizations. The component is first widely characterized to understand as finely as possible its structural, thermal and electrical properties. This step is required to gather sufficient information for the design, fabrication and measurement of prototype amplifiers. In the second phase, the amplifiers were build and measure [FON 11, FON 12b]. The amplifiers are then aged in RADAR nominal conditions, but exposed to higher temperature and electrical field constraints [FON 11, FON 12e]. The results of these tests and numerous characterizations make it possible to draw conclusions on the degradation scenario and the component lifetime. The last part of this study concerns the physical analysis of structure failures [FON 12c, FON 12e].

Figure 8.1. Power characterization bench

Analysis tools range from simple visual inspection to transmission electron microscopy (TEM) images, including radiography and photon


Embedded Mechatronic Systems 2

emission microscopy. They will allow confirmation of assumptions formulated after electrical characterization and aging tests. The following is a description of experimental tools and techniques necessary for carrying out these objectives. 8.4. Aging tests Five transistors are aged on the test bench. This number seems to be small considering that the bench is designed for a maximum of eight devices. We should bear in mind that the test must be preceded by a long characterization of transistors and amplifiers. The cumulated duration of the five components’ aging is about 3,600 h. Technical risks also limit the number of tested components. As shown later, only small dispersions are observed between different transistors and amplifiers. 8.4.1. Test protocol The objective is to highlight the dominating phenomenon which causes the decrease in the amplifiers’ performances. Identical amplifiers (with identical matching circuits) are tested. Only biasing conditions (VDS0 and ID0) are modified. Indeed, the amplifiers’ power efficiency has little dependence on the drain-to-source bias voltage VDS0. Proceeding in this way allows the simultaneous increase in the drain voltage excursion and the dissipated power in the transistor (i.e. channel temperature). Channel temperatures induced by these tests could sometimes exceed 350°C, therefore, the base plate temperatures are fixed to smaller values. Load and source impedances show little variations and the load curve is only translated horizontally compared to its nominal position with VDS = 28 V. Consequently, the gate to source junction will be conducive before the transistor starts operating in the ohmic zone (i.e. time-varying VGS becomes greater than threshold value before load curve reaches the knee zone of the I-V network). This is

High-Efficiency Architecture for Power Amplifiers


evident during measurements. Thus, input power is fixed according to the average gate current. The protocol of these tests is inspired from that related to the nominal operation. It is as follows: – frequency: 3 GHz; – base plate temperature: 20°C; – pulsed radio frequency (RF) signal: duty cycle 15%, pulse width: 450 μs; – input power, PIN = 39.5 dBm, (fixed so that the average gate current IG is greater than +300 μA). It corresponds to soft gain compression (about 1 dB). Tests biasing conditions are: – VDS0 = 40 V and ID0≈0 mA (class-B); – VDS0 = 40 V and ID0=600 mA (deep class-AB, IDSS≈6 A); – VDS0 = 43 V and ID0≈0 mA (class-B); – VDS0 = 45 V and ID0 ≈0 mA (class-B); – VDS0 = 45 V and ID0=200 mA (deep class-AB). Operation in class-AB is tested to evaluate the quiescent current effect on amplifier performances degradation. Simulations showed that the breakdown voltage is not reached in these tests. In the worst case (VDS0 = 45 V), the maximum reached voltage is about 90 V. It leaves a sufficient margin (the measured breakdown voltage is greater than 110 V). The power characteristic POUT(PIN) of each amplifier is measured before and after each test. A pulsed I(V) and a CW S-parameter measurement is also performed. Finally, we point out that the tests were performed without interruption. Each amplifier is tested over hundreds of hours. The test durations are presented in Table 8.1.


Embedded Mechatronic Systems 2


Test duration (hours)

40 V–0 mA


40 V–600 mA


43 V–0 mA


45 V–0 mA


45 V–200 mA


Table 8.1. Duration of each aging test

8.4.2. Impact of pulsed RF signal on the idle current ID0 In class-AB operation, a specific HEMT AlGaN/GaN phenomenon should be considered. We observe an important dependence of the idle current ID0 on the RF power injected into the transistor. ID0 decreases when input power increases. A similar observation of current reduction is published in the literature. It seems to be related to surface trapping effects. To explore this effect in more depth, we carried out the following characterization: we measured the quiescent current between RF pulses for several input power values, for a 28 V and 200 mA biasing. Base plate temperature was maintained at 20°C. Pulsed RF signal with 100 μs pulse width and 15% duty cycle was injected over 5 s and then stopped for 20 s, while ID0 was still measured during this time. We observed that application of pulsed RF signals caused an immediate decrease in ID0. When the input power was greater, the current decrease was stronger. When the RF signal is turned off, the ID0 recovery time is longer. Time constant dissymmetry between current falling and recovery means that this property is related to trapping effects rather than thermal effects. It is known that substrate traps are dependent on the VDS voltage and the surface traps rather than the VGS voltage. So, this characterization is performed for different VDS0 and VGS0 (i.e. ID0) and it gives an explanation as to the exact origin of the phenomenon. It is highlighted that it is mainly sensitive to the gate voltage. It confirms the assumption of surface traps mentioned in the literature. The consequence is that it is difficult to estimate the power efficiency during the RF pulse with a technique based on average measurements. As observed, the quiescent current between two pulses is lower than the quiescent current without the RF

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signal. So for efficiency calculation, we subtract an incorrect quiescent value from the drain current absorbed during the RF pulse. The power efficiency is then overestimated. When the phenomenon is particularly important, the calculated power efficiency could even exceed 100%. To avoid this effect, we could operate in class-B with a null-quiescent current, or measure the quiescent current value between RF pulses. 8.5. Other results 8.5.1. Performance monitoring Contrary to base plate temperature, injected power in the amplifier is not regulated. We must be sure that it stays as constant as possible during the aging tests. Measurements show a small variation of ±5% in the worst case. Average variations are rather of ±2%. Measured variations of the amplifier characteristics (output power POUT, average drain current ID and average gate current IG), which affect each tested device, are summarized in Table 8.2. Bias conditions


ΔID/ID (%)

ΔIG/IG (%)

40 V–0 mA




40 V–600 mA




43 V–0 mA




45 V–0 mA




45 V–200 mA




Table 8.2. Evolution of amplifiers electrical performances during the test. Performances related to (45 V, 200 mA) were extrapolated to 800 h for information purpose only

The following conclusions could be drawn: – The stronger output power decrease preferentially affects the amplifiers operating with high dissipated power (45 V–200 mA, 45 V–0 mA and 43 V–0 mA). In both the first two cases, the output power decrease has a lower value than the case of 43 V and 0 mA. These cases have also the same dissipated power. Cases with (40 V,


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0 mA) and (40 V, 600 mA) present a similar power degradation. It means that quiescent current only has a small influence on the performance degradation. – There is a strong decrease in drain current in the case of 40 V and 600 mA. There is no evident correlation with the output power decrease. The latter is even similar to the case with 40 V and 0 A for which the drain current is almost constant. It means that the strong observed decrease in drain current is probably due to quiescent current ID0 decrease during the test. – There is a strong increase in the average drain current. The variation is close to 300 μA at the test beginning and increases to two or three times this value during the aging test. It must be noted that this gate current is not a leakage one and is essentially related to a light gate saturation (the gate to source junction becomes lightly passing). We observed that the input power remains constant during the test. So, the current increase is probably related to the drift of the junction threshold voltage. 8.5.2. RF characterizations POUT(PIN) and ID(PIN) characteristics of amplifiers are measured before and after each aging test. Power gain and efficiency are calculated with these measurement results. Table 8.3 presents variations, during the tests, of the power gain with low (30 dBm) and high (39 dBm) input power levels (respectively, named ΔGPOUT and ΔGC). Bias


ΔGC (dB)

40 V–0 mA



40 V–600 mA



43 V–0 mA



45 V–0 mA



45 V–200 mA



Table 8.3. Variation of amplifiers power gains. GPOUT is the low power gain and GC is the power gain in the compression zone

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The compression gain decreases for all tested amplifiers. This result is in agreement with the power decrease observed in the previous section. However, for some amplifiers, low power gain has increased. This probably means that the performance decreases occur especially for large VDS and ID swings. It should, therefore, be of interest to examine the transconductance gm and the RDSon resistance in the ohmic zone. Both elements are decisive for high power gain. Table 8.4 contains variations of high power efficiency (PIN=39 dBm), low power drain current (ΔID POUT) and high power drain current (ΔID comp). All tested amplifiers are subject to the drain current decrease at a high power level. This is also in agreement with the assumption of gm and RDSon degradation in the ohmic zone. Otherwise, it is clear that in all other cases, the drain current has increased at a low input power level. This is in correlation with low level power gain for 40 V–0 mA and 43 V–0 mA. In both cases, the amplifiers operate in class-B and consequently, pinch-off transconductance changes greatly with ID0. The latter depends on pinch-off voltage VP. This parameter seems to be essential. Nevertheless, the low level gain decrease for 45 V–0 mA and 45 V–200 mA probably occurs for another reason. Both transistors tested under 45 V come from a different production batch than the other three. We note that only the 40 V–600 mA test shows a small increase in the power efficiency. It confirms our previous assumption of correlation between ID decrease during the test and ID0 decrease. This is also confirmed by the simultaneous ID POUT and ID comp decrease. Contribution of ID0 to the efficiency is weak. So the latter is enhanced. Bias

ΔPAE (points)


ΔID comp (%)

40 V–0 mA




40 V–600 mA




43 V–0 mA




45 V–0 mA




45 V–200 mA




Table 8.4. Variations of maximal added power efficiency, and drain current at low and high power levels


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8.5.3. Direct current (DC) measurements Measurements of the output characteristics ID = f(VDS, VGS), the input characteristic IG = f(VGS) and the leakage characteristic IG = f(VDG) are performed. The objective is to find correlations between the variations of the transistor performances and its intrinsic behavior. To be synthetic, only pertinent parameters will be exposed. Figure 8.2 presents the DC network of the transistor tested under 45 V and 200 mA. The observed degradations are typically measured for the other components. As expected, and under low VDS, the output transistor characteristics show a transconductance gm decrease and an RDSon increase. Output power degradations previously observed are probably due to these variations. The conjunction of both elements induces a shift toward the right of the knee of (VDS, ID) DC characteristics. The VDS/ID swings thus have smaller amplitudes and the output power is lowered. However, under high VDS (greater than 15 V), the shift of pinch-off voltage VP to more negative values becomes a more influential parameter than the gm decrease. The results clearly show that for almost all transistors, pinch-off voltage VP and transconductance gm decrease. RDSon increases in all cases. Previous assumptions deduced from RF measurement are confirmed.

Figure 8.2. I(V) output characteristics for the test 45 V 200 mA: before aging (continuous line) and after aging (dotted line). –1.8 V