Electronic Circuits I
 9789339220891, 9339220897

Table of contents :
Title
Contents
1 BIASING OF DISCRETE BJT AND MOSFET
2 BJT AMPLIFIERS
3 JFET AND MOSFET AMPLIFIERS
4 FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS
5 IC MOSFET Amplifier

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Electronic Circuits I

About the Authors S Salivahanan is the Principal of SSN College of Engineering, Chennai. He obtained his B.E. degree in Electronics and Communication Engineering from PSG College of Technology, Coimbatore, M.E. degree in Communication Systems from NIT, Trichy, and Ph.D. in the area of Microwave Integrated Circuits from Madurai Kamaraj University. He has over three decades of teaching, research, administration and industrial experience, both in India and abroad, with stints at NIT, Trichy; A.C. College of Engineering and Technology, Karaikudi; R.V. College of Engineering, Bangalore; Dayananda Sagar College of Engineering, Bangalore; Mepco Schlenk Engineering College, Sivakasi; and Bannari Amman Institute of Technology, Sathyamangalam. Dr Salivahanan served as a mentor for the M.S. degree under the distance-learning programme offered by Birla Institute of Technology and Science, Pilani. He has industrial experience as Scientist/Engineer at Space Applications Centre, ISRO, Ahmedabad; Telecommunication Engineer at State Organisation of Electricity, Iraq; and Electronics Engineer at Electric Dar Establishment, Kingdom of Saudi Arabia. He is the author of 32 popular books some of which include Basic Electrical, Electronics and Computer Engineering; Electronic Devices and Circuits and Linear Integrated Circuits, all published by McGraw Hill Education, and Digital Signal Processing by McGraw Hill Education (India) and McGraw Hill International which has also been translated into Mandarin, the most popular version of the Chinese language. He has published several papers at national and international levels. Professor Salivahanan is the recipient of Bharatiya Vidya Bhavan National Award for Best Engineering College Principal for 2011 from ISTE, and IEEE Outstanding Branch Counsellor and Advisor Award in the Asia-Pacific region for 1996–97. He was the Chairman of IEEE Madras Section for two years, 2008 and 2009, and Syndicate Member of Anna University. He is a Senior Member of IEEE, Fellow of IETE, Fellow of Institution of Engineers (India), Life Member of ISTE and Life Member of Society for EMC Engineers. He is also a member of IEEE Societies in Microwave Theory and Techniques, Communications, Signal Processing, and Aerospace and Electronics.

N Suresh Kumar is the Principal of Velammal College of Engineering and Technology, Madurai. He received his B.E. degree in Electronics and Communication Engineering from Thiagarajar College of Engineering, Madurai; M.E. degree in Microwave and Optical Engineering from A.C. College of Engineering Technology, Karaikudi; and Ph.D. degree in the field of EMI/EMC from Madurai Kamaraj University. He has over two decades of teaching, administration and research experience and has authored 8 books, all published by McGraw Hill Education. He has published and presented many research papers in international journals and conferences. His areas of interest include Microwave Communication, Optical Communication and Electromagnetic Compatibility. He is a life member of IETE and ISTE.

Electronic Circuits I

S Salivahanan Principal SSN College of Engineering Chennai, Tamil Nadu, India

N Suresh Kumar Principal Velammal College of Engineering and Technology Madurai, Tamil Nadu, India

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Electronic Circuits I Copyright © 2015 by McGraw Hill Education (India) Private Limited. No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior written permission of the publishers. The program listings (if any) may be entered, stored and executed in a computer system, but they may not be reproduced for publication. This edition can be exported from India only by the publishers, McGraw Hill Education (India) Private Limited Print Edition ISBN-13: 978-93-392-2088-4 ISBN-10: 93-392-2088-9 eBook Edition e-ISBN-13: 978-93-392-2089-1 e-ISBN-10: 93-392-2089-7 Managing Director: Kaushik Bellani Head—Products (Higher Education and Professional): Vibha Mahajan Assistant Sponsoring Editor: Koyel Ghosh Editorial Executive: Piyali Chatterjee Manager—Production Systems: Satinder S Baveja Desk Editor: Jagriti Kundu Senior Graphic Designer—Cover: Meenu Raghav Senior Publishing Manager (SEM & Tech. Ed.): Shalini Jha Assistant Product Manager (SEM & Tech. Ed.): Tina Jajoriya General Manager—Production: Rajender P Ghansela Manager—Production: Reji Kumar Information contained in this work has been obtained by McGraw Hill Education (India), from sources believed to be reliable. However, neither McGraw Hill Education (India) nor its authors guarantee the accuracy or completeness of any information published herein, and neither McGraw Hill Education (India) nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that McGraw Hill Education (India) and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought. Typeset at The Composers, 260, C.A. Apt., Paschim Vihar, New Delhi 110 063 and printed at ** Cover Printer: ** ** Visit us at: www.meducation.co.in

Contents Preface Roadmap

vii xi

1.

Biasing of Discrete BJT and MOSFET 1.1 Introduction 1.1 1.2 Construction 1.1 1.3 Transistor Biasing 1.1 1.4 Operation of NPN and PNP Transistor 1.2 1.5 Types of Configuration 1.5 1.6 Bias Stability 1.12 1.7 Various Biasing Methods for BJT 1.19 1.8 Stability 1.45 1.9 Bias Compensation 1.47 1.10 Thermal Stability 1.49 1.11 Design of Biasing for JFET 1.49 1.12 Design of Biasing for MOSFET 1.54 Two Mark Question and Answers 1.64 Review Questions 1.66

1.1

2.

BJT Amplifiers 2.1 BJT Amplifier 2.1 2.2 Single Stage Amplifier 2.2 2.3 Small Signal Analysis of Single Stage BJT Amplifiers 2.9 2.4 AC Load Line 2.34 2.5 Voltage Swing Limitations 2.34 2.6 Differential Amplifier 2.35 2.7 Common Mode Rejection Ratio (CMRR) 2.41 2.8 Darlington Amplifier 2.44 2.9 Bootstrap Technique 2.47 2.10 Cascaded Stages 2.48 2.11 Cascode Amplifier 2.48 2.12 Large Signal Amplifiers 2.52 Two Mark Question and Answers 2.58 Review Questions 2.61

2.1

3.

JFET and MOSFET Amplifiers 3.1 JFET Amplifiers 3.1 3.2 Small Signal Analysis of JFET 3.2

3.1

vi

Contents

3.4 Small Signal Analysis of MOSFET Amplifier 3.9 3.5 Comparison of FET Model with h-Parameter Model of BJT 3.6 BiMOS Circuits 3.12 Two Mark Question and Answers 3.15 Review Questions 3.16

3.11

4

Frequency Analysis of BJT and MOSFET Amplifiers 4.1 Introduction 4.1 4.2 Logarithms 4.1 4.3 Decibels 4.2 4.4 General Shape of Frequency Response of Amplifiers 4.5 4.5 Low Frequency 4.7 4.6 Miller Effect 4.15 4.7 High Frequency Analysis of CE 4.17 4.8 High Frequency MOSFET Model 4.21 4.9 Short-circuit Current Gain 4.24 4.10 Cut Off Frequency—fa and fb Unity Gain 4.26 4.11 Determination of Bandwidth of Single Stage Amplifier 4.28 4.12 Determination of Bandwidth of Multistage Amplifiers 4.31 Two Mark Question and Answers 4.33 Review Questions 4.35

4.1

5.

IC MOSFET Amplifier 5.1 IC Biasing 5.1 5.2 The Basic MOSFET Current Source 5.1 5.3 MOS Current-Steering Circuits 5.3 5.4 Active Load 5.4 5.5 CMOS Common Source and Source Follower 5.8 5.6 CMOS Differential Amplifier 5.12 5.7 Differential Gain of the Active-loaded MOS Pair 5.13 5.8 CMOS Common Mode Rejection Ratio (CMRR) 5.15 Two Mark Question and Answers 5.17 Review Questions 5.18

5.1

Preface Electronic Circuits I is designed specifically to cater to the needs of third semester ECE students of Anna University. The book has a perfect blend of focused content coverage. Solved Anna University question papers which are tagged with specific topics will be extremely helpful to the students. Simple, easy-to-understand, and jargon-free, the book elucidates the concepts of electronics with the help of several solved examples, circuit diagrams and adequate questions helping students clearly understand the concepts of electronics.

SALIENT FEATURES ✓ Crisp content presentation strictly in line with the latest Anna University syllabus of Electronic Circuits I (Regulation 2013) ✓ Previous-year Anna University solved questions appropriately incorporated as: — Long Questions: Tagged within the text — Short Two-marks Questions: End of each chapter ✓ Rich exam-oriented pedagogy: ✓ Solved examples: 85 ✓ Solved two-marks questions: 52 ✓ Review questions: 111 ✓ Illustrations: 195

CHAPTER ORGANISATION The book is organised into 5 chapters. Chapter 1 deals with Biasing of Discrete BJT and MOSFET and includes DC load line, operating point, various biasing methods for BJT-Design-Stability-Bias compensation, thermal stability, design of biasing for JFET, design of biasing for MOSFET. Chapter 2 discusses BJT Amplifiers at length and covers the topics small signal analysis of common emitter, AC load line, voltage swing limitations, common collector and common base amplifiers, differential amplifiers, CMRR, Darlington amplifier, Bootstrap technique, Cascaded stages, Cascode amplifier. Chapter 3 covers JFET and MOSFET Amplifiers and includes small signal analysis of JFT amplifiers, small signal analysis of MOSFET and JFET, common source amplifier, voltage swing limitations, small signal analysis of MOSFET and JFET source follower and common gate amplifiers, BiMOS Cascode amplifier. Frequency Analysis of BJT and MOSFET Amplifiers is discussed in Chapter 4 with a detailed discussion on low frequency and Miller effect, high frequency analysis of CE and MOSFET CS amplifier, short circuit current gain, cut off frequency, fa and fb unity gain and determination of bandwidth of single stage and multistage amplifiers. Chapter 5 includes IC MOSFET Amplifier and discusses IC

viii Preface

Amplifiers, IC biasing current steering circuit using MOSFET, MOSFET current sources, PMOS and NMOS current sources, amplifier with active loads, enhancement load, depletion load and PMOS and NMOS current sources load, CMOS common source and source follower, CMOS differential amplifier, and CMRR.

ACKNOWLEDGEMENTS We would like to thank the editorial team of the publisher, McGraw Hill Education for their professional way of dealing with this project. S Salivahanan thanks his wife, Kalavathy, and his children for their enormous patience and cooperation. N Suresh Kumar thanks his wife, Andal, and his children for their encouragement and moral support during the writing of this book. Constructive suggestions and corrections for the improvement of the book would be most welcome and highly appreciated. A number of reviewers took pains to provide valuable feedback for the book. We are grateful to all of them and their names are mentioned as follows: P L Ramesh Shanmuganathan Engineering College, Pudukkottai, Tamil Nadu M Arankulavan Mahath Amma Institute of Engineering and Technology, Pudhukottai, Tamil Nadu N Nirmal Singh V V College of Engineering, Tirunelveli, Tamil Nadu A Gobinath Velammal College of Engineering and Technology, Madurai, Tamil Nadu N Umapathi GKM College of Engineering and Technology, Chennai, Tamil Nadu J Williams MAM College of Engineering, Trichy, Tamil Nadu We are also thankful to ECE students from V V College of Engineering, Tirunelveli, Tamil Nadu for reviewing the manuscript and providing their valuable feedback. Their names are mentioned as follows: Amali Theres Rinoba Amutha Ancy Steffina Angela Shajini Anith Sheeba Elizabeth Anto Jenisha Immastephy Anusha Sorna Chinnamalar Priyanka Christilda Jerlin Christy

Devisree Evangeline Jeeva Sudhana Gnanajesi Abiya Gracya Hemalatha Indumathi Jeron Jeyashree Kana Sheran Karthika

Preface ix

Kavitha Kousika Lydia Mathumathi Muhideen Fathima Byrose Nesa Stephila Mary Nisha Regina Sabana Sahaya Marsha Salini Ponmalar Saranya Narmatha Sharan Ebenezer Shilba Shunmuga Priya Sivasakthi Sneha Janet Suganya Uma Mageshwari Vijila

Vinitha Alagusundari Anitha Aswini Chitra Divya Femino Jebica Hannah Olive Jafny Moniza Lalitha Manoha Muthu Lakshmi Nisha Flora Boby Philomine Sony Prema Princiya Beulah Rani Revathy Sangeetha Selva Karthika Sujitha Sweety Julia

Publisher’s Note McGraw Hill Education (India) invites suggestions and comments from you, all of which can be sent to [email protected] (kindly mention the title and author name in the subject line). Piracy-related issues may also be reported.

Roadmap Electronic Circuits I Unit 1: Biasing of Discrete BJT and MOSFET DC Load line, operating point, various biasing methods for BJT-Design-Stability-Bias compensation, thermal stability, design of biasing for JFET, design of biasing for MOSFET

Go To

Chapter 1: Biasing of Discrete BJT and MOSFET

Unit 2: BJT Amplifiers Small signal analysis of common emitter, AC load line, voltage swing limitations, common collector and common base amplifiers, differential amplifiers, CMRR, Darlington amplifier, Bootstrap technique, Cascaded stages, Cascode amplifier.

Go To

Chapter 2: BJT Amplifiers

Unit 3: JFET and MOSFET Amplifiers Small signal analysis of JFT amplifiers, small signal analysis of MOSFET and JFET, common source amplifier, voltage swing limitations, small signal analysis of MOSFET and JFET source follower and common gate amplifiers, BiMOS Cascode amplifier.

Go To

Chapter 3: JFET and MOSFET Amplifiers

xii Roadmap

Unit 4: Frequency Analysis of BJT and MOSFET Amplifiers Low frequency and Miller effect, high frequency analysis of CE and MOSFET CS amplifier, short circuit current gain, cut off frequency, fa and fb unity gain and determination of bandwidth of single stage and multistage amplifiers.

Go To

Chapter 4: Frequency Analysis of BJT and MOSFET Amplifiers

Unit 5: IC MOSFET Amplifiers IC Amplifiers, IC biasing current steering circuit using MOSFET, MOSFET current sources, PMOS and NMOS current sources. Amplifier with active loads, enhancement load, depletion load and PMOS and NMOS current sources load, CMOS common source and source follower, CMOS differential amplifier, CMRR

Go To

Chapter 5: IC MOSFET Amplifiers

Biasing of Discrete BJT and MOSFET 1.1

1 1.1

BIASING OF DISCRETE BJT AND MOSFET

INTRODUCTION

A Bipolar Junction Transistor (BJT) is a three terminal semiconductor device in which the operation depends on the interaction of both majority and minority carriers and hence the name Bipolar. The BJT is analogous to a vacuum triode and is comparatively smaller in size. It is used in amplifier and oscillator circuits, and as a switch in digital circuits. It has wide applications in computers, satellites and other modern communication systems.

1.2 CONSTRUCTION The BJT consists of a silicon (or germanium) crystal in which a thin layer of N-type Silicon is sandwiched between two layers of P-type silicon. This transistor is referred to as PNP. Alternatively, in a NPN transistor, a layer of P-type material is sandwiched between two layers of N-type material. The two types of the BJT are represented in Fig. 1.1.

Fig. 1.1 Transistor (a) NPN and (b) PNP

The symbolic representation of the two types of the BJT is shown in Fig. 1.2. The three portions of the transistor are Emitter, Base and Collector, shown as E, B and C, respectively. The arrow on the emitter specifies the direction of current flow when the EB junction is forward biased. Emitter is heavily doped so that it can inject a large number of charge carriers into the base. Base is lightly doped and very thin. It passes most of the injected charge carriers from the emitter into the collector. Collector is moderately doped.

1.3 TRANSISTOR BIASING As shown in Fig. 1.3, usually the emitter-base junction is forward biased and collector-base junction is reverse biased. Due to the forward bias on the emitter-base junction an emitter current flows through the base into the collector. Though the, collector-base junction is reverse biased, almost the entire emitter current flows through the collector circuit.

1.2 Electronic Circuits I E E

C

C B

B

(b)

(a)

Fig. 1.2 Circuit symbol (a) NPN transistor and (b) PNP transistor

Fig. 1.3 Transistor biasing (a) NPN transistor and (b) PNP transistor

1.4 OPERATION OF NPN AND PNP TRANSISTOR 1.4.1

Operation of NPN Transistor

As shown in Fig. 1.4, the forward bias applied to the emitter base junction of an NPN transistor causes a lot of electrons from the emitter region to crossover to the base region. As the base is lightly doped with P-type impurity, the number of holes in the base region is very small and hence the number of electrons that combine with holes in the P-type base region is also very small. Hence a few electrons combine with holes to constitute a base current IB. The remaining electrons (more than 95%) crossover into the collector region to constitute a collector current IC. Thus the base and collector current summed up gives the emitter current, i.e. IE = – (IC + IB). In the external circuit of the NPN bipolar junction transistor, the magnitudes of the emitter current IE, the base current IB and the collector current IC are related by IE = IC + IB.

Fig. 1.4 Current in NPN transistor

Biasing of Discrete BJT and MOSFET 1.3

1.4.2

Operation of PNP Transistor

As shown in Fig. 1.5, the forward bias applied to the emitter-base junction of a PNP transistor causes a lot of holes from the emitter region to crossover to the base region as the base is lightly doped with N-types impurity. The number of electrons in the base region is very small and hence the number of holes combined with electrons in the N-type base region is also very small. Hence a few holes combined with electrons to constitute a base current IB. The remaining holes (more than 95%) crossover into the collector region to constitute a collector current IC. Thus the collector and base current when summed up gives the emitter current, i.e. IE = – (IC + IB). In the external circuit of the PNP bipolar junction transistor, the magnitudes of the emitter current IE, the base current IB and the collector current IC are related by IE = IC + IB

Fig. 1.5 Current in PNP transistor

(1.1)

This equation gives the fundamental relationship between the currents in a bipolar transistor circuit. Also, this fundamental equation shows that there are current amplification factors a and b in common base transistor configuration and common emitter transistor configuration respectively for the static (d.c.) currents, and for small changes in the currents.

Large-signal current gain ( ) The large signal current gain of a common base transistor is defined as the ratio of the negative of the collector-current increment to the emitter-current change from cut-off (IE = 0) to IE, i.e. (IC – ICBO) a = – __________ (1.2) IE – 0 where ICBO (or ICO) is the reverse saturation current flowing through the reverse biased collector-base junction, i.e. the collector to base leakage current with emitter open. As the magnitude of ICBO is negligible when compared to IE, the above expression can be written as IC a = __ IE

(1.3)

Since IC and IE are flowing in opposite directions, a is always positive. Typical value of a ranges from 0.90 to 0.995. Also, a is not a constant but varies with emitter current IE, collector voltage VCB and temperature.

General transistor equation In the active region of the transistor, the emitter is forward biased and the collector is reverse biased. The generalised expression for collector current IC for collector junction voltage VC and emitter current IE is given by IC = – a IE + ICBO (1 – eVc/VT)

(1.4)

1.4

Electronic Circuits I

If VC is negative and |Vc | is very large compared with VT , then the above equation reduces to IC = – a IE + ICBO

(1.5)

If VC, i.e. VCB, is few volts, IC is independent of VC. Hence the collector current IC is determined only by the fraction a of the current IE flowing in the emitter.

Relation among IC, IB and ICBO

From Eqn. (1.5), We have

IC = – a IE + ICBO Since IC and IE are flowing in opposite directions, IE = – (IC + IB) IC = – a [– (IC + IB)] + ICBO

Therefore,

IC – a IC = a IB + ICBO IC (1– a) = a IB + ICBO ICBO a IC = _____ IB + _____ 1–a 1–a a b = _____ , 1–a

Since

(1.6)

the above expression becomes IC = (1 + b) ICBO + b IB

(1.7)

Relation among IC, IB and ICEO In the common-emitter (CE) transistor circuit, IB is the input current and IC is the output current. If the base circuit is open, i.e, IB = 0, then a small collector current flows from the collector to emitter. This is denoted as ICEO, the collector-emitter current with base open. This current ICEO is also called the collector to emitter leakage current. In this CE configuration of the transistor, the emitter-base junction is forward-biased and collectorbase junction is reverse-biased and hence the collector current IC is the sum of the part of the emitter current IE that reaches the collector, and the collector-emitter leakage current ICEO. Therefore, the part of IE, which reaches collector is equal to (IC – ICEO). Hence, the large-signal current gain (b) is defined as,

From the equation, we have

(IC – ICEO) b = __________ IB

(1.8)

IC = bIB + ICEO

(1.9)

Relation between ICBO and ICEO Comparing Eqs. (1.7) and (1.9), we get the relationship between the leakage currents of transistor common-base (CB) and common-emitter (CE) configurations as ICEO = (1 + b) ICBO

(1.10)

From this equation, it is evident that the collector-emitter leakage current (ICEO) in CE configuration is (1 + b) times larger than that in CB configuration. As ICBO is temperature-dependent, ICEO varies by large amount when temperature of the junctions changes.

Biasing of Discrete BJT and MOSFET 1.5

Expression for emitter current The magnitude of emitter-current is IE = IC + IB Substituting Eqn. (1.7) in the above equation, we get IE = (1 + b) ICBO + (1 + b) IB

(1.11)

Substituting Eqn. (1.6) into Eqn. (1.11), we have 1 1 IE = _____ ICBO + _____ IB 1–a 1–a

DC current gain (

d.c.

(1.12)

or hFE) The d.c. current gain is defined as the ratio of the collector current IC

to the base current IB. That is, IC bd.c. = hFE = __ IB

(1.13)

As IC is large compared with ICEO, the large signal current gain (b) and the d.c. current gain (hFE) are approximately equal.

1.5 TYPES OF CONFIGURATION When a transistor is to be connected in a circuit, one terminal is used as an input terminal, the other terminal is used as an output terminal and the third terminal is common to the input and output. Depending upon the input, output and common terminal, a transistor can be connected in three configurations. They are: (i) Common base (CB) configuration, (ii) Common emitter (CE) configuration, and (iii) Common collector (CC) configuration.

(i) CB configuration This is also called grounded base configuration. In this configuration, emitter is the input terminal, collector is the output terminal and base is the common terminal.

(ii) CE configuration This is also called grounded emitter configuration. In this configuration, base is the input terminal, collector is the output terminal and emitter is the common terminal.

(iii) CC configuration This is also called grounded collector configuration. In this configuration, base is the input terminal, emitter is the output terminal and collector is the common terminal. The supply voltage connections for normal operation of an NPN transistor in the three configurations are shown in Fig. 1.6.

1.5.1

CB Configuration

The circuit diagram for determining the static characteristics curves of an NPN transistor in the common base configuration is shown in Fig. 1.7.

Input characteristics To determine the input characteristics, the collector-base voltage VCB is kept constant at zero volt and the emitter current IE is increased from zero in suitable equal steps by increasing VEB. This is repeated for higher fixed values of VCB. A curve is drawn between emitter current IE and emitter-base voltage VEB at constant collector-base voltage VCB. The input characteristics thus obtained are shown in Fig. 1.8.

1.6

Electronic Circuits I IC

IB

C

B

IE IE

+ –

E

IC

C

IB

E + –

E

B

– +

IE

+ –

IB

(a)

B

– +

C + –

IC

(b)

(c)

Fig. 1.6 Transistor configuration: (a) Common base (b) Common emitter and (c) Common collector IE

– –

– VEE

V

+

A VEB

+

IC C

E +

IC –

A

+

B IB

VCB

+ V –

+ V – cc

Fig. 1.7 Circuit to determine CB static characteristics IE (mA) VCB > 1 V VCB = 0 V

3.5 3 2.5 2 1.5 1 0.5 0.1 0.2 0.3 0.4 0.5 0.6

0.7 0.8 VEB (V)

Fig. 1.8 CB input characteristics

When VCB is equal to zero and the emitter-base junction is forward biased as shown in the characteristics, the junction behaves as a forward biased diode so that emitter current IE increases rapidly with small increase in emitter-base voltage VEB. When VCB is increased keeping VEB constant, the width of the base region will decrease. This effect results in an increase of IE. Therefore, the curves shift towards the left as VCB is increased.

Biasing of Discrete BJT and MOSFET 1.7

Output characteristics To determine the output characteristics, the emitter current IE is kept constant at a suitable value by adjusting the emitter-base voltage VEB. Then VCB is increased in suitable equal steps and the collector current IC is noted for each value of IE. This is repeated for different fixed values of IE. Now the curves of IC versus VCB are plotted for constant values of IE and the output characteristics thus obtained is shown in Fig. 1.9. IC (mA) Saturation region

Active region

IE = 5 mA

5 4 mA 4 3 mA 3 2 mA 2

1 mA

1

0 mA 1

–0.25

2

3

4

5

VCB (V )

Cut off region 0

Fig. 1.9 CB output characteristics

From the characteristics, it is seen that for a constant value of IE, IC is independent of VCB and the curves are parallel to the axis of VCB. Further, IC flows even when VCB is equal to zero. As the emitterbase junction is forward biased, the majority carriers, i.e. electrons, from the emitter are injected into the base region. Due to the action of the internal potential barrier at the reverse biased collector-base junction, they flow to the collector region and give rise to IC even when VCB is equal to zero.

Early effect or base-width modulation As the collector voltage VCC is made to increase the reverse bias, the space charge width between collector and base tends to increase, with the result that the effective width of the base decreases. This dependency of base-width on collector-to-emitter voltage is known as the Early effect. This decrease in effective base-width has three consequences: (i) There is less chance for recombination within the base region. Hence, a increases with increasing |VCB|. (ii) The charge gradient is increased within the base, and consequently, the current of minority carriers injected across the emitter junction increases. (iii) For extremely large voltages, the effective base-width may be reduced to zero, causing voltage breakdown in the transistor. This phenomenon is called the punch through. For higher values of VCB, due to Early effect, the value of a increases. For example, a changes, say from 0.98 to 0.985. Hence, there is a very small positive slope in the CB output characteristics and hence the output resistance is not zero.

Transistor parameters The slope of the CB characteristics will give the following four transistor parameters. Since these parameters have different dimensions, they are commonly known as common base hybrid parameters or h-parameters.

1.8

Electronic Circuits I

(a) Input impedance (hib ) It is defined as the ratio of the change in (input) emitter voltage to the change in (input) emitter current with the (output) collector voltage VCB kept constant. Therefore, DVEB hib = _____, VCB constant (1.14) DIE It is the slope of CB input characteristics IE versus VEB as shown in Fig. 1.8. The typical value of hib ranges from 20 W to 50 W. (b) Output admittance (hob ) It is defined as the ratio of change in the (output) collector current to the corresponding change in the (output) collector voltage with the (input) emitter current IE kept constant. Therefore, DIC hob = _____, IE constant (1.15) DVCB It is the slope of CB output characteristics IC versus VCB as shown in Fig. 1.9. The typical value of this parameter is of the order of 0.1 to 10 m mhos. (c) Forward current gain (hfb ) It is defined as a ratio of the change in the (output) collector current to the corresponding change in the (input) emitter current keeping the (output) collector voltage VCB constant. Hence, DIC hfb = ____ , VCB constant. (1.16) DIE It is the slope of IC versus IE curve. Its typical value varies from 0.9 to 1.0. (d) Reverse voltage gain (hrb) It is defined as the ratio of the change in the (input) emitter voltage and the corresponding change in (output) collector voltage with constant (input) emitter current, IE. Hence, DVEB hrb = _____ , IE constant (1.17) DVCB It is the slope of VEB versus VCB curve. Its typical value is of the order of 10 – 5 to 10 – 4.

1.5.2

CE Configuration

[AU Dec’13, 16 marks]

Input characteristics To determine the input characteristics, the collector to emitter voltage is kept constant at zero volt and base current is increased from zero in equal steps by increasing VBE in the circuit shown in Fig. 1.10.

Fig. 1.10 Circuit to determine CE static characteristics

Biasing of Discrete BJT and MOSFET 1.9

The value of VBE is noted for each setting of IB. This procedure is repeated for higher fixed values of VCE, and the curves of IB Vs. VBE are drawn. The input characteristics thus obtained are shown in Fig. 1.11.

IB (mA)

When VCE = 0, the emitter-base junction is forward biased and the junction behaves as a forward biased diode. Hence the input characteristic for VCE = 0 is similar to that of a forward-biased diode. When VCE is increased, the width of the depletion region at the reverse biased collectorbase junction will increase. Hence the effective width of the base will decrease. This effect causes a decrease in the base current IB. Hence, to get the same value of Ib as that for VCE = 0, VBE should be increased. Therefore, the curve shifts to the right as VCE increases.

150

250

VCE = 0V VCE > 0 V

200

100 50 0

0.2

0.4

0.6

0.8

VBE(V)

Fig. 1.11 CE input characteristics

Output characteristics To determine the output characteristics, the base current IB is kept constant at a suitable value by adjusting base-emitter voltage, VBE. The magnitude of collector-emitter voltage VCE is increased in suitable equal steps from zero and the collector current IC is noted for each setting VCE. Now the curves of IC versus VCE are plotted for different constant values of IB. The output characteristics thus obtained are shown in Fig. 1.12. From Eqs. (1.6) and (1.7), we have a b = _____ and IC = ( I + b) ICBO + b IB 1–a For larger values of VCE, due to Early effect, a very small change in a is reflected in a very large change in b. For exam-

Fig. 1.12 CB output characteristics

0.98 0.985 ple, when a = 0.98, b = _______ = 49. If a increases to 0.985, then b = ________ = 66. Here, a slight 1 – 0.98 1 – 0.985 increase in a by about 0.5% results in an increases in b by about 34%. Hence, the output characteristics of CE configuration show a larger slope when compared with CB configuration. The output characteristics have three regions, namely, saturation region, cut-off region and active region. The region of curves to the left of the line OA is called the saturation region (hatched), and the line OA is called the saturation line. In this region, both junctions are forward biased and an increase in the base current does not cause a corresponding large change in IC. The ratio of VCE(sat) to IC in this region is called saturation resistance. The region below the curve for IB = 0 is called the cut-off region (hatched). In this region, both junctions are reverse biased. When the operating point for the transistor enters the cut-off region, the transistor

1.10

Electronic Circuits I

is OFF. Hence, the collector current becomes almost zero and the collector voltage almost equals VCC, the collector supply voltage. The transistor is virtually an open circuit between collector and emitter. The central region where the curves are uniform in spacing and slope is called the active region (unhatched). In this region, emitter-base junction is forward biased and the collector-base junction is reverse biased. If the transistor is to be used as a linear amplifier, it should be operated in the active region. If the base current is subsequently driven large and positive, the transistor switches into the saturation region via the active region, which is traversed at a rate that is dependent on factors such as gain and frequency response. In this ON condition, large collector current flows and collector voltage falls to a very low value, called VCEsat, typically around 0.2 V for a silicon transistor. The transistor is virtually a short circuit in this state. High speed switching circuits are designed in such a way that transistors are not allowed to saturate, thus reducing switching times between ON and OFF times.

Transistor parameters The slope of the CE characteristics will give the following four transistor parameters. Since these parameters have different dimensions, they are commonly known as common emitter hybrid parameters or h-parameters. (a) Input impedance (hie) It is defined as the ratio of the change in (input) base voltage to the change in (input) base current with the (output) collector voltage VCE kept constant. Therefore, DVBE hie = _____, VCE constant (1.18) DIB It is the slope of CE input characteristics IB versus VBE as shown in Fig. 1.11. The typical value of hie ranges from 500 to 2000 W. (b) Output admittance (hoe) It is defined as the ratio of change in the (output) collector current to the corresponding change in the (output) collector voltage with the (input) base current IB kept constant. Therefore, DIC hoe = _____ , IB constant (1.19) DVCE It is the slope of CE output characteristic IC versus VCE as shown in Fig. 1.12. The typical value of this parameter is of the order of 0.1 to 10 m mhos. (c) Forward current gain (hfe) It is defined as a ratio of the change in the (output) collector current to the corresponding change in the (input) base current keeping the (output) collector voltage VCE constant. Hence, DIC hfe = ____, VCE constant (1.20) DIB It is the slope of IC versus IB curve. Its typical value varies from 20 to 200. (d) Reverse voltage gain (hre) It is defined as the ratio of the change in the (input) base voltage and the corresponding change in (output) collector voltage with constant (input) base current, IB. Hence, DVBE hre = _____ , IB constant (1.21) DVCE It is the slope of VBE versus VCE curve. Its typical value is of the order of 10–5 to 10–4.

Biasing of Discrete BJT and MOSFET 1.11

1.5.3

CC Configuration

The circuit diagram for determining the static characteristics of an NPN transistor in the common collector configuration is shown in Fig. 1.13.

Fig. 1.13 Circuit to determine CC static characteristics

Input characteristics To determine the input characteristics, VEC is kept at a suitable fixed value. The base-collector voltage VBC is increased in equal steps and the corresponding increase in IB is noted. This is repeated for different fixed values of VEC. Plots of VBC versus IB for different values of VEC shown in Fig. 1.14 are the input characteristics.

Fig. 1.14 CC input characteristics

Output characteristics The output characteristics shown in Fig. 1.15 are the same as those of the common emitter configuration.

Fig. 1.15 CC output characteristics

1.12 Electronic Circuits I

1.5.4

Comparison of Transistor Configuration

[AU Dec’09, 8 marks]

Table 1.1 A comparison of CB, CE and CC configurations Property

CB

CE

CC

Input resistance

Low (about 100 W)

Moderate (about 750 W)

High (about 750 kW)

Output resistance

High (about 450 kW)

Moderate (about 45 kW)

Low (about 25 W)

Current gain

1

High

High

Voltage gain

About 150

About 500

Less than 1

Phase shift between input & output voltages

0 or 360°

180°

0 or 360°

Applications

for high frequency circuits

for audio frequency circuits for impedance matching

1.6

BIAS STABILITY

[AU May’14, 6 marks]

The quiescent operating point of a transistor amplifier should be established in the active region of its characteristics. Since the transistor parameters such as b, ICO and VBE are functions of temperature, the operating point shifts with changes in temperature. The stability of different methods of biasing transistor (BJT, FET and MOSFET) circuits and compensation techniques for stabilizing the operating point are discussed in this chapter.

1.6.1

Need for Biasing—Operating Point

In order to produce distortion-free output in amplifier circuits, the supply voltages and resistances in the circuit must be suitably chosen. These voltages and resistances establish a set of d.c. voltage VCEQ and current ICQ to operate the transistor in the active region. These voltages and currents are called quiescent values which determine the operating point or Q-point for the transistor. The process of giving proper supply voltages and resistances for obtaining the desired Q-point is called biasing. The circuits used for getting the desired and proper operating point are known as biasing circuits. The collector current for common-emitter amplifier is expressed by IC = bIB + ICEO = bIB + (1 + b )ICO Here the three variables hFE, i.e., b, IB and ICO are found to increase with temperature. For every 10°C rise in temperature, ICO doubles itself. When ICO increases, IC increases significantly. This causes power dissipation to increase and hence to make ICO increase. This will cause IC to increase further and the process becomes cumulative which will lead to thermal runaway that will destroy the transistor. In addition, the quiescent operating point can shift due to temperature changes and the transistor can be driven into the region of saturation. The effect of b on the Q-point is shown in Fig. 1.16. One more source of bias instability to be considered is due to the variation of VBE with temperature. VBE is about 0.6 V for a silicon transistor and 0.2 V for a germanium transistor at room temperature. As the temperature increases, |VBE | decreases at the rate of 2.5 mV/°C for both silicon and germanium transistors. The transfer characteristic curve shifts to the left at the rate of 2.5 mV/°C (at constant IC) for increasing temperature and hence the operating point shifts accordingly. To establish the operating point in the active region, compensation techniques are needed.

Biasing of Discrete BJT and MOSFET 1.13

1.6.2

DC Load Line

Referring to the biasing circuit of Fig. 1.17(a), the values of VCC and RC are fixed and IC and VCE are dependent on RB. Applying Kirchhoff’s voltage law to the collector circuit in Fig. 1.17(a), we get VCC = IC RC + VCE. The straight line represented by AB in Fig. 1.17(b) is called the d.c. load line. The coordinates of the VCC end point A are obtained by substituting VCE = 0 in the above equation. Then IC = ____. Therefore, the RC VCC ____ coordinates of A are VCE = 0 and IC = . RC IC

IB4 IB3

VCC Rc

IB2 Q2 Q1 IB1

VCC

Fig. 1.16

IB = 0 VCE

Effect of b on Q-point IC 3.5 mA

C

3 mA

A

+VCC

IC RB CC

RC

CC

Q

1.5 mA

Vout RL

Vin

D 0 (a)

Fig. 1.17

12 V

B 21 V 24 V (b)

VCE

(a) Biasing circuit (b) CE output characteristics and load line

The coordinates of B are obtained by substituting IC = 0 in the above equation. Then VCE = VCC. Therefore, the coordinates of B are VCE = VCC and IC = 0. Thus, the d.c. load line AB can be drawn if the values of RC and VCC are known. As shown in Fig. 1.17(b), the optimum Q-point is located at the midpoint of the d.c. load line AB between the saturation and cut-off regions, i.e. Q is exactly midway between A and B. In order to get faithful amplification, the Q-point must be well within the active region of the transistor.

1.14 Electronic Circuits I

Even though the Q-point is fixed properly, it is very important to ensure that the operating point remains stable where it is originally fixed. If the Q-point shifts nearer to either A or B, the output voltage and current get clipped, thereby output signal is distorted. In practice, the Q-point tends to shift its position due to any or all of the following three main factors: (i) Reverse saturation current, ICO, which doubles for every 10 °C increase in temperature. (ii) Base-emitter voltage, VBE, which decreases by 2.5 mV per °C. (iii) Transistor current gain, b, i.e., hFE which increases with temperature. Referring to Fig. 1.17(a), the base current IB is kept constant since IB is approximately equal to VCC /RB. If the transistor is replaced by another one of the same type, one cannot ensure that the new transistor will have identical parameters as that of the first one. Parameters such as b vary over a range. This results in the variation of collector current IC for a given IB. Hence, in the output characteristics, the spacing between the curves might increase or decrease which leads to the shifting of the Q-point to a location which might be completely unsatisfactory.

AC load line After drawing the d.c. load line, the operating point Q is properly located at the center of the d.c. load line. This operating point is chosen under zero input signal condition of the circuit. Hence, the a.c. load line should also pass through the operating point Q. The effective a.c. load resistance, Ra.c., is the combination of RC parallel to RL, i.e. Ra.c. = RC || RL. So the slope of the a.c. load line 1 CQD will be – ____ . Ra.c.

(

)

To draw an a.c. load line, two end points, viz. maximum VCE and maximum IC when the signal is applied are required. Maximum VCE = VCEQ + ICQ Ra.c., which locates the point D (0D) on the VCE axis. VCEQ Maximum IC = ICQ + _____, which locates the point C (0C ) on the IC axis. Ra.c. By joining points C and D, a.c. load line CD is constructed. As RC > Ra.c., the d.c. load line is less steep than the a.c. load line. When the signal is zero, we have the exact d.c. conditions. From Fig. 1.17(b), it is clear that the intersection of d.c. and a.c. load lines is the operating point Q.

EXAMPLE 1.1 For the transistor circuit in Fig 1.18, find the Q-point, VCC = 15 V & b = 100, VEE = 0.7 V [AU Dec’09, 8 marks]

Solution VT =

R2Vcc R1 + R2

100 ¥ 103 ¥ 15 100 ¥ 103 + 100 ¥ 103 = 7.5 V =

RB = 100 K || 100 K = 50 K

Biasing of Discrete BJT and MOSFET 1.15

Apply KVL to base circuit VT – IBRB – VBE – (1 + b)IBRE = 0 IB =

VT - VBE = 9.23 mA (1 + b )RE + RB

IC = bIB = 100 ¥ 9.23 mA = 0.923 mA IE = 0.923 mA Apply KVL to collector circuit VCE = VCC – ICRC – IERE

Fig. 1.18

= 4.6935 V Q point, ICQ = 0.923 mA & VCEQ = 4.6935 V

EXAMPLE 1.2 For the circuit shown in Fig. 1.19 calculate the operating point

I BEQ =

Solution

=

[AU May’11, 8 marks]

VCC - VBE RB + (1 + b ) ( RC + RE ) 10 - 0.7 = 36.31 mA 200 ¥ 10 + (1 + 50) (1 ¥ 103 + 100) 3

ICQ = bIBQ = 50 ¥ 36.31 ¥ 10–6 = 18155 mA IEQ = IBQ + ICQ = 36.31 ¥ 10–6 + 1.8155 ¥ 10–3 = 1.85181 mA VCEQ = VCC – IE(RC + RE) Fig. 1.19

= 10 – 1.85181 ¥ 10–3 (1 ¥ 103 + 100) = 7.963 V

EXAMPLE 1.3 Locate the operating point of the circuit shown in Fig. 1.20 VCC = 15 V, hfe = 200

[AU Dec’10, 8 marks]

Solution I BQ = =

VCC - VBE RB + (1 + b ) ( RC + RE ) 15 - 0.7 3

630 ¥ 10 + (1 + 200) (4.7 ¥ 103 + 680)

= 8.36 mA

ICQ = IBQ = 200 ¥ 8.36 ¥ 10–6 = 1.672 mA IEQ = ICQ + IBQ Fig. 1.20

1.16

Electronic Circuits I

= 1.672 ¥ 10–3 + 8.36 ¥ 10–6 = 1.68 mA VCEQ = VCC – IE(RC + RE) = 15 – 1.68 ¥ 10–3 (4.7 ¥ 103 + 680) = 5.96 V

EXAMPLE 1.4 In the transistor amplifier shown in Fig. 1.17(a), RC = 8 k , RL = 24 k and VCC = 24 V. Draw the d.c. load line and determine the optimum operating point. Also draw the a.c. load line.

Solution (i) d.c. load line: Referring to Fig. 1.17(a), we have VCC = VCE + IC RC. For drawing d.c. load line, the two end points, viz. maximum VCE point (at IC = 0) and maximum IC point (at VCE = 0) are required. Maximum

VCE = VCC = 24 V VCC 24 Maximum IC = ____ = _______3 = 3 mA RC 8 × 10

Therefore, the d.c. load line AB is drawn with the point B (0B = 24 V) on the VCE axis and the point A (0A = 3 mA) on the IC axis, as shown in Fig. 1.17(b). (ii) For fixing the optimum operating point Q, mark the middle of the d.c. load line AB and the corresponding VCE and IC values can be found. VCC Here, VCEQ = ____ = 12 V and ICQ = 1.5 mA 2 (iii) a.c. load line: To draw an a.c. load line, two end points viz. maximum VCE and maximum IC when the signal is applied are required. The a.c. load, Maximum

8 × 24 Ra.c. = RC || RL = ______ = 6 kW 8 + 24 VCE = VCEQ + ICQ Ra.c. = 12 + 1.5 ¥ 10–3 ¥ 6 ¥ 103 = 21 V

This locates the point D (0D = 21 V) on the VCE axis. VCEQ Maximum collector current = ICQ + _____ Ra.c. 12 = 1.5 ¥ 10 – 3 + _______3 = 3.5 mA 6 × 10 This locates the point C (0C = 3.5 mA) on the IC axis. By joining points C and D, a.c. load line CD is constructed.

Biasing of Discrete BJT and MOSFET 1.17

EXAMPLE 1.5 For the transistor amplifier shown in Fig. 1.21(a), VCC = 12 V, R1 = 8 k , R2 = 4 k , RC = 1 k , RE = 1 k and RL = 1.5 k . Assume VBE = 0.7 V. (i) Draw the d.c. load line, (ii) determine the operating point, and (iii) draw the a.c. load line.

Solution (i) d.c. load line: Referring to Fig. 1.21(a), we have VCC = VCE + IC (RC + RE ). To draw the d.c. load line, we need two end points, viz. maximum VCE point (at IC = 0) and maximum IC point (at VCE = 0). Maximum VCE = VCC = 12 V, which locates the point B (0B = 12 V) of the d.c. load line. VCC 12 IC = ________ = ___________3 = 6 mA RC + RE (1 +1) × 10

Maximum

This locates the point A (0A = 6 mA) of the d.c. load line. Figure 1.21(b) shows the d.c. load line AB, with (12 V, 6 mA). IC (mA) D 12.3

+VCC (12 V)

8k

1k

R1

RC A 6

IC

IB

(5.4, 3.3)

Q 4k

R2

RE

1k

CE 0

(a)

(b)

Fig. 1.21

(ii) Operating point Q The voltage across Therefore,

R2 R2 is V2 = _______ VCC R1 + R2 4 × 103 V2 = ________3 × 12 = 4 V 12 × 10 V2 = VBE + IERE

Therefore,

C 7.38 VCE (V )

V2 – VBE 4 – 0.7 IE = ________ = _______3 = 3.3 mA RE 1 × 10

B 12

1.18 Electronic Circuits I

IC ª IE = 3.3 mA VCE = VCC – IC (RC + RE) = 12 – 3.3 ¥ 10 – 3 ¥ 2 ¥ 103 = 5.4 V Therefore, the operating point Q is at 5.4 V and 3.3 mA, which is shown on the d.c. load line. (iii) a.c. load line To draw the a.c. load line, we need two end points, viz. maximum VCE and maximum IC when signal is applied. 1 × 1.5 a.c. load, Ra.c = RC || RL = _______ = 0.6 kW 2.5 Therefore, maximum

VCE = VCEQ + ICQ Ra.c. = 5.4 + 3.3 ¥ 10 – 3 ¥ 0.6 ¥ 103 = 7.38 V

This locates the point C (0C = 6.24 V) on the VCE axis. Maximum

VCEQ IC = ICQ + _____ Ra.c. 5.4 = 3.3 ¥ 10 – 3 + ________3 = 12.3 mA 0.6 × 10

This locates the point D (0D = 12.3 mA) on the IC axis. By joining points C and D, a.c. load line CD is constructed.

EXAMPLE 1.6 Design the circuit shown in Fig. 1.22, given Q-point values are to be ICQ = 1 mA and VCEQ = 6 V. Assume that VCC = 10 V, = 100 and VBE (on) = 0.7 V.

Solution

The collector resistance is VCC – VCEQ 10 – 6 RC = ___________ = _______ = 4 kW ICQ 1 × 10–3

VCC

The base current is ICQ 1 × 10–3 IBQ = ____ = _______ = 10 mA 100 b The base resistance is VCC – VBE (on) 10 – 0.7 = 0.93 MW RB = _____________ = _________ IBQ 10 × 10 – 6

RB Vi

Fig. 1.22

EXAMPLE 1.7 Determine the characteristics of a circuit shown in Fig. 1.23. Assume that

Solution

Referring to Fig. 1.23, Kirchhoff’s voltage law equation is

= 100 and VBE (on) = 0.7 V.

RC

Biasing of Discrete BJT and MOSFET 1.19

VBB = IBRB + VBE (on) + IERE We know that IE = IB + IC = IB + bIB = (1 + b )IB VBB – VBE (on) The base current IB = ______________ RB + (1 + b) RE 5 – 0.7 = 53.34 mA = __________________ 20 × 103 + 101× 600 Therefore,

IC = bIB = 100 ¥ 53.34 ¥ 10–6

Fig. 1.23

= 5.334 mA IE = IC + IB = 5.334 ¥ 10 – 3 + 53.34 ¥ 10 – 6 = 5.38734 mA VCE = VCC – ICRC – IE RE = 10 – 5.334 ¥ 10 – 3 ¥ 400 – 5.38734 ¥ 10 – 3 ¥ 600 = 4.634 V The Q point is at VCEQ = 4.634 V and ICQ = 5.334 mA

1.7 VARIOUS BIASING METHODS FOR BJT [AU Dec’09, 16 marks, AU May’13, 8 marks, AU Dec’12, 16 marks] The stability factors for some commonly used biasing circuits are discussed below.

1.7.1

Fixed Bias or Base Resistor Method

[AU Dec’09, 8 marks, AU May’10, 8 marks]

A common emitter amplifier using fixed bias circuit is shown in Fig. 1.24. The d.c. analysis of the circuit yields the following equation. VCC = IBRB + VBE (1.22) – V V CC BE Therefore, IB = _________ RB Since this equation is independent of current IC, dIB/dIC = 0 and the stability factor given in Eq. (1.49) reduces to S =1+b Since b is a large quantity, this is a very poor bias stable circuit. Therefore, in practice, this circuit is not used for biasing the base. The advantage of this method are: (a) simplicity, (b) small number of components required, and (c) if the supply voltage is very large as compared to VBE of the transistor, then the base current becomes largely independent of the voltage VBE.

VCC RC

RB IB

IC Vout

Vin VBE

Fig. 1.24

Fixed bias circuit

1.20 Electronic Circuits I

EXAMPLE 1.8 In the fixed bias compensation method shown in Fig. 1.25 a silicon transistor with = 100 is used. VCC = 6 V, RC = 3 k . RB = 530 k . Draw the d.c. load line and determine the operating point. What is the stability factor?

(a) d.c. load line:

Solution

IC (mA)

VCE = VCC – ICRC When

IC = 0, VCE = VCC = 6 V

When

VCE

2

VCC 6 = 0, IC = ____ = _______3 = 2 mA RC 3 × 10

(b) Operating point Q:

Q

1

For silicon transistor, VBE = 0.7 V VCC = IBRB + VBE Therefore,

VCC – VBE 6 – 0.7 IB = _________ = _________ = 10 mA RB 530 × 103

Therefore,

IC = bIB = 100 × 10 × 10 – 6 = 1 mA

0

3

VCE (V )

6

Fig. 1.25

VCE = VCC – ICRC = 6 – 1 × 10 – 3 × 3 × 103 = 3 V Therefore operating point is VCEQ = 3 V and ICQ = 1 mA. (c) Stability factor: S = 1 + b = 1 + 100 = 101

EXAMPLE 1.9 Find the collector current and collector-to-emitter voltage for the given circuit as shown in Fig. 1.26.

Solution VCC = 9V

For a silicon transistor, VBE = 0.7 V Base current

VCC – VBE 9 – 0.7 IB = _________ = _________3 = 27.67 mA RB 300 × 10

RB 300 kW

RC = 2 kW

b = 50

Collector current IC = bIB = 50 × 27.67 × 10 – 6 = 1.38 mA Collector-to-emitter voltage VCE = VCC – ICRC = 9 – 1.38 × 10 – 3 × 2 × 103 = 6.24 V

Fig. 1.26

EXAMPLE 1.10 A Germanium transistor, in Fig. 1.27, having = 100 and VBE = 0.2 V is used in a fixed bias amplifier circuit where VCC = 16 V, RC = 5 k and RB = 790 k . Determine its operating point.

Biasing of Discrete BJT and MOSFET 1.21 VCC = 16 V

Solution For a Germanium transistor, VBE = 0.2 V Applying KVL to the base circuit, we have

RC = 5 kW RB = 790 kW

VCC – IBRB – VBE = 0

b = 100 VBE = 0.2 V

VCC – VBE 16 – 0.2 IB = _________ = _________3 = 20 mA RB 790 × 10

Therefore,

IC = bIB = 100 × 20 mA = 2 mA Fig. 1.27

Applying KVL to the collector circuit, we have VCC – ICRC – VCE = 0 VCE = VCC – ICRC = 16 – 2 × 10 – 3 × 5 × 103 = 6 V Hence, the operating point is IC = 2 mA and VCE = 6 V.

EXAMPLE 1.11 The circuit as shown in Fig. 1.28 has fixed bias using NPN transistor. Determine the value of base current, collector current and collector to emitter voltage.

Applying KVL to the base circuit, we have

Solution

VCC – IBRB – VBE = 0

RB 180 kW

VCC – VBE 25 – 0.7 IB = _________ = _________3 = 135 mA RB 180 × 10

Therefore,

VCC = 25 V RC 820 W Vo b = 80

IC = bIB = 80 × 135 × 10 – 6 = 10.8 mA Applying KVL to the collector circuit, we have Fig. 1.28

VCC – ICRC – VCE = 0 VCE = VCC – ICRC = 25 – 10.8 × 10 – 3 × 820 = 16.144 V

Therefore,

EXAMPLE 1.12 For a fixed bias configuration shown in Fig. 1.24, determine IC, RC, RB and VCE using the following specifications: VCC = 12 V, VC = 6 V, = 80 and IB = 40 A.

Solution

Assume VBE = 0.7 V for a silicon transistor. IC = bIB = 80 × 40 mA = 3.2 mA VCC – VC 12 – 6 RC = _________ = _________ = 1.875 kW IC 3.2 × 10 – 3 VCC – VBE 12 – 0.7 RB = _________ = _________ = 282.5 kW IB 40 × 10 – 6

Since emitter is grounded,

VE = 0. VCE = VC = 6 V

1.22 Electronic Circuits I

1.7.2

VCC

Emitter-Feedback Bias

The emitter-feedback bias network shown in Fig. 1.29 contains an emitter resistor for improving the stability level over that of the fixed-bias configuration. The analysis will be performed by first examining the base-emitter loop and then using the results to investigate the collector-emitter loop.

IC RC

RB IB

Vo

Vi C1

Base-emitter loop Applying Kirchhoff’s voltage law for

C2 IE RE

the base-feedback emitter loop, we get VCC – IBRB – VBE – IERE = 0

(1.23) Fig. 1.29

VCC – IBRB – VBE – (IB + IC) RE = 0

Emitter-feedback bias circuit

VCC – IB (RB + RE) – VBE – ICRE = 0 VCC – VBE = IB (RB + RE) + ICRE VCC – VBE RE IB = _________ – ________ IC RE + RB RE + RB

(

Therefore,

)

(1.24)

Here VBE is independent of IC.

(

dIB RE ___ = – ________ RE + RB dIC

Hence,

)

(1.25)

Substituting Eq. (1.25) in Eq. (1.49), we get the stability factor as 1+b S = ____________ RL 1+ b ________ RE + RB

(1.26)

bRE Since 1 + _________ > 1, S < (1 + b). Note that the value of the stability factor S is always lower in (RE + RB) emitter-feedback bias circuit than that of the fixed bias circuit. Hence it is clear that a better thermal stability can be achieved in emitter-feedback bias circuit than the fixed-bias circuit.

Collector-Emitter Loop Applying Kirchhoff’s voltage law for the collector-emitter loop, we get IE RE + VCE + IC RC – VCC = 0 Substituting IE = IC , we have VCE – VCC + IC (RC + RE) = 0 and

VCE = VCC – IC (RC + RE)

(1.27)

VE is the voltage from emitter to ground and is determined by VE = IERE

(1.28)

Biasing of Discrete BJT and MOSFET 1.23

The voltage from collector to ground can be determined from VCE = VC – VE and

VC = VCE + VE

(1.29)

or

VC = VCC – ICRC

(1.30)

The voltage at the base with respect to ground can be determined from or

VB = VCC – IBRE

(1.31)

VB = VBE + VE

(1.32)

EXAMPLE 1.13 For the emitter-feedback bias circuit, VCC = + 10 V, RC = 1.5 k , RB = 270 k and RE = 1 k . Assuming = 50, determine (a) Stability factor, S (b) IB (c) IC (d) VCE (e) VC (f) VE (g) VB and (h) VBC.

Solution

(a) The stability factor is 1+b 1 + 50 S = _____________ = _____________________ bR (50 × 1 × 103) E 1 + _________ 1 + _________________ (RE + RB) 1 × 103 + 270 × 103 51 51 = _________ = _____ = 43.04 1 + 0.185 1.185

(b)

VCC – VBE 9.3 10 – 0.7 = ____ = 28.97 mA IB = ______________ = _____________________ RB + (b + 1) RE 27 × 103 + (51) (1 × 103) 321 IC = bIB = (50) (28.97 × 10 – 6) = 1.45 mA

(c) (d)

VCE = VCC – IC (RC + RE) = 10 – 1.45 × 10 – 3 (1.5 × 103 + 1 × 103) = 10 – 3.62 = 6.38 V

(e)

VC = VCC – ICRC = 10 – 1.45 × 10 – 3 (1.5 × 103) = 7.825 V

(f)

VE = VC – VCE = 7.825 – 6.38 = 1.445 V or

(g) (h)

VE = IERE = ICRE = 1.45 × 10 – 3 × 1 × 103 = 1.45 V VB = VBE + VE = 0.7 + 1.45 = 2.15 V VBC = VB – VC = 2.15 – 7.825 = |5.675| V

(reverse bias as required)

1.24 Electronic Circuits I

EXAMPLE 1.14 Calculate d.c. bias voltage and currents in the circuit in Fig. 1.30. Neglect VBE of transistor.

Solution

Given: VCC = 20 V; RB = 400 kW, b = 100, RE = 1 kW; RC = 2 kW IBRB + VBE + IERE = VCC IC __ R + 0 + (IC + IB) RE = 20 b B RB RE IC ___ + RE + ___ = 20 b b

[

Therefore,

]

20 = 4 mA IC = _______________________ 3 400 × 10 _________ 3 + 1 × 10 + 10 100

[

]

Fig. 1.30

IC 4 × 10 – 3 IB = __ = ________ = 0.4 mA 100 b VB = VBE + IERE = 0 + 4 × 10 – 3 × 1 × 103 = 4 V, since IC ª IE

1.7.3 Collector-to-Base Bias or Collector-Feedback Bias

[AU May’11, 8 marks] + VCC

A common emitter amplifier using collector-to-base bias circuit is shown in Fig. 1.31. This circuit is the simplest way to provide some degree of stabilization to the amplifier operating point. If the collector current IC tends to increase due to either increase in temperature or the transistor has been replaced by the one with a higher b, the voltage drop across RC increases, thereby reducing the value or VCE. Therefore, IB decreases which, in turn, compensates the increase in IC. Thus, greater stability is obtained. The loop equation for this circuit is

Therefore,

RB

Vin

IB

IC Vout

VBE

Fig. 1.31 Collector-to-base bias circuit

VCC = (IB + IC) RC + IBRB + VBE i.e.

RC

VCC – VBE – ICRC IB = ________________ RC + RB RC dIB ________ ___ = dIC RC + RB

(1.33) (1.34)

(1.35)

Substituting Eq. (1.35) into Eq. (1.49), we get 1+b S = _______________ RC 1 + b ________ RC + RB

(

)

(1.36)

Biasing of Discrete BJT and MOSFET 1.25

As can be seen, this value of the stability factor is smaller than the value obtained by fixed bias circuit. Also, S can be made small and the stability can be improved by making RB small or RC large. If RC is very small, then S = (b + 1), i.e. stability is very poor. Hence, the value of RC must be quite large for good stabilization. Thus, collector-to-base bias arrangement is not satisfactory for the amplifier circuits like transformer coupled amplifier where the d.c. load resistance in collector circuit is very small. For such amplifiers, emitter bias or self bias will be the most satisfactory transistor biasing for stabilization.

EXAMPLE 1.15 In the biasing with feedback resistor method, a silicon transistor with feedback resistor is used. The operating point is at 7 V, 1 mA and VCC = 12 V. Assume = 100. Determine (a) the value of RB, (b) stability factor, and (c) what will be the new operating point if = 50 with all other circuit values are same.

Solution Refer to Fig. 1.24. We know that for a silicon transistor, VBE = 0.7 V. (a) To determine RB : The operating point is at Here,

VCE = 7 V and IC = 1 mA VCC – VCE 12 – 7 RC = __________ = ________ = 5 kW IC 1 × 10 – 3 IC 1 × 10 – 3 IB = __ = ________ = 10 mA 100 b

Using the relation, VCC – VBE – ICRC 12 – 0.7 – 1 × 10 – 3 × 5 × 103 RB = ________________ = _________________________ = 630 kW IB 10 × 10 – 6 (b) Stability factor,

1+b S = ______________ RC 1 + b ________ RC + RB

[

]

1 + 100 = 56.5 = ______________________ 5 × 103 _____________ 1 + 100 (5 + 630) × 103

[

]

(c) To determine new operating point when b = 50 VCC = bIBRC + IBRB + VBE = IB (bRC + RB) + VBE i.e.

12 = IB (50 × 5 × 103 + 630 × 103) + 0.7 11.3 IB = _________3 = 12.84 mA 880 × 10

1.26 Electronic Circuits I

IC = bIB = 50 × 12.84 × 10 – 6 = 0.642 mA

Therefore,

VCE = VCC – ICRC = 12 – 0.642 × 10 – 3 × 5 × 103 = 8.79 V Therefore, the coordinates of the new operating point are VCEQ = 8.79 V and ICQ = 0.642 mA.

EXAMPLE 1.16 An NPN transistor if = 50 is used in common emitter circuit with VCC = 10 V and RC = 2 k . The bias is obtained by connecting 100 k resistor from collector to base. Find the quiescent point and stability factor.

Solution

Given

VCC = 10 V, RC = 2 kW, b = 50 and collector to base resistor RB = 100 kW

To determine the quiescent point:

We know that for the collector to base bias transistor circuit,

VCC = bIBRC + IBRB + VBE Therefore,

VCC – VBE IB = __________ RB + b ◊ RC 10 – 0.7 = _______________________ = 46.5 mA 3 100 × 10 + 50 × 2 × 10 – 3

Hence,

IC = b ◊ IB = 50 × 46.5 × 10 – 6 = 2.325 mA VCE = VCC – ICRC = 10 – 2.325 × 10 – 3 × 2 × 103 = 5.35 V

Therefore, the co-ordinates of the new operating point are VCEQ = 5.35 V and ICQ = 2.325 mA To find the stability factor S: 1+b S = ______________ RC 1 + b ________ RC + RB

[

]

1 + 50 = 25.75 = _________________________ 2 × 103 _________________ 1 + 50 2 × 103 + 100 × 103

[

]

EXAMPLE 1.17 In a collector to base CE amplifier circuit of Fig. 1.24 having VCC = 12 V, RC = 250 k , IB = 0.25 mA, = 100 and VCEQ = 8 V, calculate RB and stability factor.

Solution

VCEQ 8 RB = _____ = __________ = 32 kW IB 0.25 × 10 – 3

Biasing of Discrete BJT and MOSFET 1.27

Stability factor,

1+b 101 S = _______________ = _________________ = 56.9 R 250 C 1 + 100 ________ 1 + b ________ 32 + 250 RC + RB

(

)

(

)

EXAMPLE 1.18 Calculate the quiescent current and voltage of collector to base bias arrangement using the following data (Fig. 1.32): VCC = 10 V, RB = 100 k , RC = 2 k , = 50 and also specify a value of RB so that VCE = 7 V.

Solution (a) Applying KVL to the base circuit, we have VCC – IB (1 + b) RC – IB RB – VBE = 0 Therefore,

VCC – VBE 10 – 0.7 = 46 mA IB = ______________ = __________________________ RB + (1 + b) RC 100 × 103 + (1 + 50) × 2 × 103 IC = bIB = 50 × 46 mA = 2.3 mA

Applying KVL to the collector circuit, we have

VCC = 10 V

VCC – (IB + IC) RC – VCE = 0 Therefore,

VCE = VCC – (IB + IC) RC = 10 – (46 × 10 – 6 + 2.3 × 10 – 3) × 2 × 103 = 5.308 V

Quiescent current, Quiescent voltage, (b) Given

RC = 2 KW RB = 100 KW IC + IB IB

b = 50

ICQ = 2.3 mA and VCEQ = 5.308 V VCE = 7 V

Fig. 1.32

(IB + IC) RC = VCC – VCE

We have,

(1 + b) IBRC = VCC – VCE VCC – VCE 10 – 7 IB = __________ = ________________3 = 29.41 mA (1 + b) RC (1 + 50) × 2 × 10 VCC = IBRB + VBE VCE – VBE 7 – 0.7 RB = _________ = ___________ = 214.2 kW IB 29.41 × 10 – 6

1.7.4 Collector-Emitter Feedback Bias Figure 1.33 shows the collector-emitter feedback bias circuit that can be obtained by applying both the collector-feedback and emitter-feedback. Here collector-feedback is provided by connecting a resistance RB from the collector to the base and emitter-feedback is provided by connection an emitter resistance RE from the emitter to ground. Both the feedbacks are used to control the collector current IC and the base current IB in the opposite direction to increase the stability as compared to the previous biasing circuits.

1.28 Electronic Circuits I + VCC

IC + I B RC

RB

Vo

IB

IC

Vi

VCE

C

VBE RE IE

Fig. 1.33 Collector-emitter feedback circuit

Applying Kirchhoff’s voltage law to the current, we get (IB + IC) RE + VBE + IBRB + (IB + IC) RC – VCC = 0 Therefore,

(

)

VCC – VBE RE + RC IB = _____________ – _____________ IC RE + RC + RB RE + RC + RB

Since VBE is independent of IC, RE + RC dIB ___ = – _____________ RE + RC + RB dIC

(

)

Substituting the above equation in Eq. (1.49), we get 1+b S = ________________ (1.37) b (RE + RC) _____________ 1+ RE + RC + RB From this, it is clear that the stability of the collector-emitter feedback bias circuit is always better than that of the collector-feedback and emitter feedback circuits.

1.7.5 Voltage Divider Bias, Self Bias or Emitter Bias

[AU May’14, 10 marks, AU Dec’13, 8 marks, AU May’10, 8 marks, AU Dec’10, 16 marks, AU May’13, 8 marks]

A simple circuit used to establish a stable operating point is the self biasing configuration. The self bias, also called as emitter bias, or emitter resistor and potential divider circuit, that can be used for low collector resistance, is shown in Fig. 1.34. The current in the emitter resistor RE causes a voltage drop which is in the direction to reverse bias the emitter junction. For the transistor to remain in the active region, the base-emitter junction has to be forward

+ VCC

IC R1

+ VCC

IC

RC IB

RC RB

Vout

VT VBE R2

IE = (IB + IC)

IB VT

RE

(a)

IE

RE

(b)

Fig. 1.34 (a) Self bias and (b) Thevenin’s equivalent circuit

Biasing of Discrete BJT and MOSFET 1.29

biased. The required base bias is obtained from the power supply through the potential divider network of the resistance R1 and R2.

Use of self bias circuit as a constant current circuit If IC tends to increase, say, due to increase in ICO with temperature, the current in RE increases. Hence, the voltage drop across RE increases thereby decreasing the base current. As a result, IC is maintained almost constant.

1.7.6 Stabilization Factors To determine stability factor, S Applying Thevenin’s Theorem to the circuit of Fig. 1.34, for finding the base current, we have, R2 VCC R1R2 VT = _______ and RB = _______ R1 + R2 R1 + R2 The loop equation around the base circuit can be written as VT = IBRB + VBE + (IB + IC) RE Differentiating this equation with respect to IC, we get RE dIB ________ ___ = dIC RE + RB Substituting this equation in Eq. (1.49), we get 1+b S = ______________ RE 1 + b ________ RE + RB

(

Therefore,

)

RB 1 + ___ RE S = (1 + b) __________ RB 1 + b + ___ RE

(1.38)

As can be seen, the value of S is equal to one if the ratio RB /RE is very small as compared to 1. As this ratio becomes comparable to unity, and beyond towards infinity, the value of the stability factor goes on increasing till S = 1 + b. This improvement in the stability up to a factor equal to 1 is achieved at the cost of power dissipation. To improve the stability, the equivalent resistance RB must be decreased, forcing more current in the voltage divider network of R1 and R2. Often, to prevent the loss of gain due to the negative feedback, RE is shunted by a capacitor CE. The capacitive reactance XCE must be equal to about one-tenth of the value of the resistance RE at the lowest operating frequency.

To determine the stability factor S' The stability factor S¢ is defined as the rate of change of IC with VBE, keeping ICO and b constant.

∂IC DIC S ¢ = _____ = _____ DV ∂VBE BE

From Fig. 1.34 (b), VT = IBRB + VBE + IERE = IB [RB + RE] + ICRE + VBE since [IE = IB + IC]

(1.39)

1.30

Electronic Circuits I

We have

IC – (1 + b) ICO IB = ______________ b

(1.40)

Substituting Eq. (1.39) in Eq. (1.40), we get IC ICO VT = __ (RB + RE) + VBE + ICRE + ____ (1 + b) {RB + RE} b b

(1.41)

Differentiating the above eq. w.r.t. VBE we get dIC RB + RE dIC 0 = _____ ________ + 1 + RE _____ + 0 dVBE dVBE b

(

)

[

dIC RB + RE – 1 = _____ RE + ________ dVBE b

[

]

dIC RB + (1 + b) RE – 1 = _____ ______________ dVBE b Therefore,

]

dIC –b S ¢ = _____ = ______________ dVBE RB + (1 + b) RE

(1.42)

To determine the stability of S¢¢ The stability factor S¢¢ is defined as the rate of change of IC w.r.t. to b, keeping ICO and VBE constant. Rearranging Eq. (1.41), we have

( )

1+b b _____ ICO (RB + RE) b b (VT – VBE) IC = ______________ + _____________________ RB + (1 + b) RE RB + (1 + b) RE

(1.43)

Since b >> 1, the numerator of the second term can be written as

( )

1+b (RB + RE) _____ ICO = (RB + RE) ICO b

(1.44)

Substituting Eq. 1.44 in Eq. 1.43, we have b (RB + RE) ICO b (VT – VBE) IC = ______________ + ______________ RE + (1 + b) RE RB + (1 + b) RE Therefore,

b [VT – VBE + (RB + RE) ICO] IC = _________________________ RB + (1 + b) RE

Let,

V ¢ = (RB + RE) ICO.

Therefore,

b [VT – VBE + V ¢] IC = _______________ RB + (1 + b) RE

(1.45)

Biasing of Discrete BJT and MOSFET 1.31

Differenting the above equation w.r.t. b and simplifying, we obtain IC dIC SIC S≤ = ___ = _________________ = ________ db b (1 + b) RE b 1 + b ________ RE + RB

[ (

EXAMPLE 1.19

)]

(1.46)

In a CE Germanium transistor amplifier circuit, the bias is provided by self bias, i.e. emitter resistor and potential divider arrangement (refer to Fig. 1.25). The various parameters are: VCC = 16 V, RC = 3 k , RE = 2 k , R1 = 56 k , R2 = 20 k and = 0.985. Determine (a) the coordinates of the operating point, and (b) the stability factor S.

Solution

For a Germanium transistor, VBE = 0.3 V. As a = 0.985,

a 0.985 b = _____ = ________ = 66 1 – a 1 – 0.985 (a) To find the coordinates of the operating point Referring to Fig. 1.34, we have Thevenin’s voltage,

R2 VT = _______ VCC R1 + R2 20 × 103 × 16 = 4.21 V = ________ 76 × 103

Thevenin’s resistance,

R1R2 20 × 103 × 56 × 103 RB = _______ = _________________ R1 + R2 76 × 103 = 14.737 kW

The loop equation around the base circuit is VT = IBRB + VBE + (IB + IC) RE

(

)

IC IC = __ RB + VBE + __ + IC RE b b IC 1 4.21 = ___ × 14.737 × 103 + 0.3 + IC ___ + 1 × 2 × 103 66 66 3.91 = IC [0.223 + 2.03] × 103 3.91 IC = __________3 = 1.73 mA 2.253 × 10 IC ª IE = 1.73 mA

(

Therefore, Since IB is very small, Therefore,

)

VCE = VCC – ICRC – IERE = VCC – IC [RC + RE] = 16 – 1.73 × 10 – 3 × 5 × 103 = 7.35 V

Therefore, the coordinates of the operating point are IC = 1.73 mA and VCE = 7.35 V.

1.32 Electronic Circuits I

(b) To find the stability factor S, RB 1 + ___ RE S = (1 + b) __________ RB 1 + b + ___ RE 14.737 1 + _______ 2 ______________ = (1 + 66) 14.737 ______ 1 + 66 + 2 8.3685 = 67 × _______ = 7.537 74.3685

EXAMPLE 1.20 Consider the self bias circuit where VCC = 22.5 Volts, RC = 5.6 k , R2 = 10 k and R1 = 90 k , hfe = 55, VBE = 0.6 V. The transistor operates in active region. Determine (a) operating point and (b) stability factor.

Solution For the given circuit, VBE = 0.6 V, hfe = 55 (a) To determine the operating point: Thevenin’s voltage,

Rz 10 × 103 VT = _______ VCC = _________3 × 22.5 = 2.25 V R1 + R2 100 × 10

Thevenin’s resistance,

R1R2 10 × 103 × 90 × 103 RB = _______ = _________________ = 9 kW R1 + R2 100 × 103

The loop equation around the base circuit is VB = IBRB + VBE + (IB + IC) RE

(

)

IC IC = ___ RB + VBE + ___ + IC RE hfe hfe IC 1 2.25 = ___ × 9 × 103 + 0.6 + ___ + 1 IC × 1 × 103 55 55

(

)

2.25 = IC × 0.16 × 103 + 0.6 + 1.01 × IC × 103 2.25 = IC × 1.17 × 103 + 0.6 Therefore, Since IB is very small, Therefore,

2.25 – 0.6 IC = _________3 = 1.41 mA 1.17 × 10 IC ª IE = 1.41 mA VCE = VCC – ICRC – IERE =VCC – IC (RC + RE) = 22.5 – 1.41 × 10 – 3 × 6.6 × 103 = 13.19 V

Biasing of Discrete BJT and MOSFET 1.33

Operating point coordinates are VCE = 13.19 V and IC = 1.41 mA (b) To find the stability factor, S RB 9 × 103 1 + _______3 1 + ___ RE 56 × 10 560 1 × 10 = _______ = ____ = 8.6 S = (1 + b) __________ = (1 + 55) _______________ 3 R 65 65 B 9 × 10 1 + b + ___ 1 + 55 + _______3 RE 1 × 10

EXAMPLE 1.21 The Fig. 1.35 shows that d.c. bias circuit of a common emitter transistor amplifier. Find the percentage change in collector current, if the transistor with hfe = 50 is replaced by another transistor with hfe = 150. It is given that the base emitter drop VBE = 0.6 V.

Solution

+12 V

(a) For the given circuit, VBE = 0.6 V, hfe = 50 Thevenin’s voltage,

R2 5 × 103 VT = ________ VCC = ________3 × 12 = 2 V R1 + R2 30 × 10

R1R2 25 × 103 × 5 × 103 Thevenin’s resistance, RB = _______ = ________________ = 4.16 kW R1 + R2 30 × 103

RC 1 kW

R1 25 kW V T = VB

RE 100 W

R2 5 kW

The loop equation around the base circuit is VT = VB = IBRB + VBE + (IB + IC) RE

(

)

IC IC = ___ RB + VBE + ___ + IC RE hfe hfe IC 1 2 = ___ × 4.6 × 103 + 0.6 + ___ + 1 × IC × 0.1 × 103 50 50

(

)

2 – 0.6 = IC × (0.08 + 0.102) × 103 Therefore,

14 IC = __________3 = 7.69 mA 0.182 × 10

(b) For the given circuit,VBE = 0.6 V, hfe = 150 The loop equation around the base circuit is VB = IBRB + VBE + (IB + IC) RE

(

)

IC IC = ___ RB + VBE + ___ + IC RE hfe hfe

Fig. 1.35

1.34 Electronic Circuits I

IC 1 2 = ___ × 4.6 × 103 + 0.6 + ___ + 1 × IC × 0.1 × 103 50 50

(

)

2 – 0.6 = IC × (0.028 + 0.1) × 103 Therefore, Change in collector current

1.4 IC = __________3 = 10.93 mA 0.128 × 10 10.93 – 7.69 = ___________ = 0.42 i.e. 42% 7.69

There is 42% change in IC when hfe changes from 50 to 150.

EXAMPLE 1.22 If the various parameters of a CE amplifier which uses the self bias method are VCC = 12 V, R1 = 10 k , R2 = 5 k , RC = 1 k , RE = 2 k and = 100, find (a) the coordinates of the operating point and (b) the stability factor, assuming the transistor to be silicon.

Solution (a) To find the coordinates of the operating point Refer to Fig. 1.34 Thevenin’s voltage,

R2 5 × 103 VT = _______ VCC = ________3 × 12 = 4 V R1 + R2 15 × 10

Thevenin’s resistance,

R1R2 5 × 103 × 10 × 103 RB = _________ = ________________ = 3.33 kW (R1 + R2) 15 × 103

The loop equation around the basic circuit is VT = IBRB + VBE + (IB + IC) RE

(

)

IC IC = __ RB + VBE + __ + IC RE b b IC 1 4 = ____ × 3.33 × 103 + 0.7 + IC ____ + 1 × 2 × 103 100 100

(

)

3.3 = (33.3 + 2020) IC 3.3 IC = ______ = 1.61 mA 2053.3 Since IB is very small, Therefore,

IC ª IE = 1.61 mA VCE = VCC – ICRC – IERE = VCC – IC [RC + RE] = 12 – 1.61 × 10 – 3 × 3 × 103

= 7.17 V Therefore, the coordinates of the operating point are IC = 1.61 mA and VCE = 7.17 V.

Biasing of Discrete BJT and MOSFET 1.35

(b) To find the stability factor S: RB 3.33 × 103 1 + _________ 1 + ___ RE 2 × 103 = 2.6 S = (1 + b) __________ = (1 + 100) ___________________ RB 3.33 × 103 ___ _________ 1+b+ 1 + 100 + RE 2 × 103

EXAMPLE 1.23 Determine the quiescent current and collector to emitter voltage for a Germanium transistor with = 50 in self biasing arrangement. Draw the circuit with a given component value with VCC = 20 V, RC = 2 k , RE = 100 , R1 = 100 k and R2 = 5 k . Also find the stability factor.

Solution

For a Germanium transistor, VBE = 0.3 V and b = 50

To find the coordinates of the operating point: Thevenin’s voltage,

R2 VT = _______ VCC R1 + R2 5 × 103 = _________3 × 20 = 0.95 V 105 × 10

Thevenin’s resistance,

R1R2 100 × 103 × 5 × 103 RB = _______ = _________________ = 4.76 kW R1 + R2 105 × 103

The loop equation around the base circuit is VT = IBRB + VBE + (IB + IC) RE

(

)

IC IC = __ RB + VBE + __ + IC RE b b IC 51 0.95 = ___ × 4.76 × 103 + 0.3 + IC × ___ × 100 50 50 0.65 = 197.2 IC Therefore,

0.65 IC = _____ = 3.296 mA 197.2

Since IB is very small,

IC = ª IE = 3.296 mA

Therefore,

VCE = VCC – ICRC – IERE = VCC – IC (RC + RE) = 20 – 3.296 × 10 – 3 × 2.01 × 103 = 13.375 V

Therefore, the coordinates of the operating point are IC = 3.296 mA and VCE = 13.375 V.

1.36

Electronic Circuits I

To find the stability factor S: RB 4.76 × 103 1 + ___ 1 + _________ R 100 E = 25.18 S = (1 + b) __________ = (1 + 50) __________________ R B 4.76 × 103 ___ _________ 1+b+ 1 + 50 + RE 100

EXAMPLE 1.24 A germanium transistor is used in a self biasing circuit configuration as shown below with VCC = 16 V, RC = 1.5 k and = 50. The operating point desired is VCE = 8V and IC = 4 mA. If a stability factor S = 10 is desired, calculate the values of R1 and R2 and RE of the circuit (Fig. 1.36). VCC = 16 V IC = 4 mA RC = 1.5 kW

R1 C

VCE = 8 V

B E R2

RE

IE

Fig. 1.36

Solution To determine RE : We know that,

VCC = VCE + IC (RC + RE) 16 = 8 + 4 × 10 – 3 (1.5 × 103 + RE)

Therefore,

RE = 500 W

To determine RTH: Given Stability factor

Upon solving, we get

S = 10 1+b 1 + 50 S = ______________ = _________________ R 500 E __________ 1 + b _________ 1 + 50 R + 500 RTH + RE TH

(

RTH = 5.58 kW

To determine R2: R2 = 0.1 b RE = 27.98 kW To determine R1: We know that,

R1R2 RTH = R1||R2 = _______ R1 + R2

)

Biasing of Discrete BJT and MOSFET 1.37

R1 × 27.98 × 103 _______________ 5.58 × 10 = R1 + 27.98 × 103 3

Therefore,

R1 = 6.97 kW

EXAMPLE 1.25 A CE transistor amplifier with voltage divider bias circuit of Fig. 1.34 is designed to establish the quiescent point at VCE = 12 V, IC = 2 mA and stability factor 5.1. If VCC = 24 V, VBE = 0.7 V, = 50 and RC = 4.7 k , determine the values of resistors RE, R1 and R2.

Solution (a) To determine RE: VCE = VCC – ICRC – IERE = VCC – IC [RC + RE], since IC ª IE 12 = 24 – 2 × 10 – 3 [4.7 × 103 + RE] Therefore,

RE = 1.3 kW

(b) To determine R1 and R2: Stability factor,

R1R2 1+b S = _______________, where RB = _________ RE (R1 + R2) 1 + b ________ RE + RB

(

)

51 5.1 = _____________________ 1.3 × 103 1 + 50 _____________ 1.3 × 103 + RB

( (

) )

i.e.

1.3 × 103 51 1 + 50 _____________ = ___ = 10 3 5.1 1.3 × 10 + RB

Therefore,

(

)

50 × 1.3 × 103 _____________ =9 1.3 × 103 + RB

50 × 1.3 × 103 1.3 × 103 + RB = _____________ = 7.2 kW 9 RB = 5.9 kW Also, we know that for a good voltage divider, the value of resistor R2 = 0.1 bRE Therefore,

R2 = 0.1 × 50 × 1.3 × 103 = 6.5 kW

1.38 Electronic Circuits I

R1R2 RB = _______ R1 + R2 R1 × 6.5 × 103 5.9 × 103 = _____________3 R1 + 6.5 × 10 Simplifying, we get

R1 = 64 kW

EXAMPLE 1.26 In the circuit shown in Fig. 1.37, if IC = 2 mA and VCE = 3 V, calculate R1 and R3.

Solution

Given: b = 100, IC = 2 mA, VCE = 3 V, VBE = 0.6 V,

+ VCC = 15 V

R2 = 10 kW and R4 = 500 W IC b = __ IB

We know that

I + IB

VCC = ICR3 + VCE + IER4 IE = IC + IB = 20 × 10 – 6 + 2 × 10 – 3 = 2.02 mA

R3 b = 100

IB

IC 2 × 10 – 3 IB = __ = ________ = 20 mA 100 b

Hence,

IC

R1

VBE (ac1) = 0.5 V VBE R2

10 kW

R4 = 500 W

Substituting the values, we get 15 = 2 × 10 – 3 × R3 + 3 × 2.02 × 10 –3 × 500 Therefore,

R3 = 5.495 kW

Fig. 1.37

VB = VBE + IER4 = 0.6 + 2.02 × 10 – 3 × 500 = 1.61 From the circuit,

R2VCC VB = _______ R1 + R2 10 × 103 × 15 1.61 = ____________3 R1 + 10 × 10

Therefore,

R1 = 83.17 kW

EXAMPLE 1.27 An NPN transistor if = 50 is used in common emitter circuit with VCC = 10 V and RC = 2 k . The bias is obtained by connecting 100 k resistor from collector to base. Find the quiescent point and stability factor.

Solution

Given

VCC = 10 V, RC = 2 kW, b = 50 and collector to base resistor, RB = 100 kW

To determine the quiescent point: We know that the collector to base bias transistor circuit

Biasing of Discrete BJT and MOSFET 1.39

VCC = bIBRC + IBRB + VBE VCC – VBE IB = __________ RB + b ◊ RC

Therefore,

10 – 0.7 = ______________________ = 46.5 mA 100 × 103 + 50 × 2 × 10+3 IC = bIB = 50 × 46.5 × 10 – 6 = 2.325 mA

Hence,

VCE = VCC – ICRC = 10 – 2.325 × 10 – 3 × 2 × 103 = 5.35 V Therefore, the co-ordinates of the new operating point are VCEQ = 5.35 V and ICQ = 2.325 mA To find the stability factor S:

1+b S = ______________ RC 1 + b ________ RC + RB

[

]

1 + 50 = 25.75 = _________________________ 2 × 103 _________________ 1 + 50 2 × 103 + 100 × 103

[

]

EXAMPLE 1.28 Design a voltage divider bias network using a supply of 24 V, VE = VCC / 8.

Solution

Given:

= 110 and ICQ = 4 mA VCEQ = 8 V. Choose

ICQ = 4 mA, VCEQ = 8 V, VE = VCC / 8, VCC = 24 V, b = 110

(a) To determine IB, IE and VE : ICQ 4 × 103 IB = ____ = _______ = 36.36 mA 110 b IE = IB + IC = 36.36 × 10 – 6 + 4 × 10 – 3 = 4.03636 mA VCC 24 VE = ____ = ___ = 3 V 8 8 (b) To determine RE and R2:

VE 0.3 RE = ___ = _____________ = 743.244 W IE 4.03636 × 10 – 3

Applying KVL to the collector circuit, VCC – ICRC – VCE – VE = 0 Therefore,

VCC – VCE – VE 24 – 8 – 3 RC = ______________ = _________ = 3.25 kW IC 4 × 10 – 3

1.40 Electronic Circuits I

(c) To determine R1 and R2 VB = VE + VBE = 3 + 0.7 = 3.7 V Referring to Fig. 1.34 consider the current through R1 be I + IB and that through R2 be I. Resistors R1 and R2 forms the potential divider. For proper operation of potential divider, current I should be atleast ten times the IB. i.e. I ≥ 10 IB. Therefore, I = 10 IB = 10 × 36.36 × 10 – 6 = 363.6 mA VB 3.7 R2 = ___ = ___________ = 10.176 kW I 363.6 × 10 – 6 VCC – VB 24 – 3.7 R1 = _________ = ____________________ = 50.755 kW I + IB (363.6 + 36.36) × 10 – 6

EXAMPLE 1.29 Determine the stability factor for the circuit shown in Fig. 1.38. VCC

Solution

(IC + I 1 )

VBE + (IC + IB) RE I2 = ________________ R2

RC R1

I1 = IB + I2

I1

VBE + (IC + IB) RE I1 = IB + ________________ R2

Therefore,

IBR2 + VBE + (IC + IB) RE = _______________________ R2

IC

IB R2

I2

(IC + IB)

RE

Applying KVL to the collector, base-emitter loop, we have Fig. 1.38

VCC = (IC + I1) RC – I1R1 – VBE – (IC + IB) RE = (IC + I1) RC + I1R1 + VBE + (IC + IB) RE = ICRC + I1RC + I1R1 + VBE + ICRE + IBRE = IC (RC + RE) + I1 (RC + R1) + VBE + IBRE Substituting the value of I1 from the equation determined above, we get

IBR2 + VBE + (IC + IB) RE VCC = IC (RC + RE) + _______________________ (RC + R1) + VBE + IBRE R2

[

] [

] [

]

(RC + R1) (RC + R1) (RE + R2) (RC + R1) = IC RC + RE + _________ + IB RE + __________________ + 1 + _________ VBE R2 R2 R2

Biasing of Discrete BJT and MOSFET 1.41

We know that IC = bIB + (1 + b) ICO Therefore,

IC – (1 + b) ICO IB = ______________ b

Substituting the value of IB, we get

[

]

RE (RC + R1) IC – (1 + b) ICO VCC = IC RC + RE + ____________ + ______________ × R2 b

[

] [

]

(RE + R2) (RC + R1) (RC + R1) RE + __________________ + 1 + _________ VBE R2 R2

dIC We know that S = _____ . Hence, differentiating the above equation and assuming VBE constant, we get dICO ∂IC RE (RC + R1) ∂IC (RE + R2) (RC + R1) 1 0 = _____ RC + RE + ____________ + _____ × __ RE + __________________ R2 R2 ∂ICO ∂ICO b

[

]

[

[

(RE + R2) (RC + R1) (1 + b) – ______ RE + __________________ R2 b

]

∂IC R2RC + R2RE + RERC + RER1 ∂IC 1 = _____ __________________________ + _____ × __ × R2 ∂ICO ∂ICO b

[

[

]

R2RE + RERC + RER1 + R2RC + R1R2 _________________________________ R2

]

[

1 + b R2 (RC + R1) + RE (R1 + R2 + RC) – _____ _____________________________ R2 b

]

∂IC ∂IC R2RC + RE (R1 + R2 + RC) 1 = _____ _______________________ + _____ × __ × R2 ∂ICO ∂ICO b

[

[

]

R2 (RC + R1) + RE (R1 + R2 + RC) _____________________________ R2

[

]

1 + b R2 (RC + R1) + RE (R1 + R2 + RC) – _____ _____________________________ R2 b

]

]

1.42 Electronic Circuits I

∂IC R2RC + RE (R1 + R2 + RC) R2 (RC + R1) + RE (R1 + R2 + RC) = _____ _______________________ + _____________________________ R2 bR2 ∂ICO

] [

[

]

1+b _____ [R2 (RC + R1) + RE (R1 + R2 + RC)] ∂IC b _____ _______________________________________________________ = R2 (RC + R1) + RE (R1 + R2 + RC) ∂ICO R2RC + RE (R1 + R2 + RC) + _____________________________ b 1+b _____ [R2 (RC + R1) + RE (R1 + R2 + RC)] b ________________________________________________________ = b(R2RC + RE (R1 + R2 + RC)) + R2 (RC + R1) + RE (R1 + R2 + RC) ________________________________________________________ b (1 + b) [R2 (RC + R1) + RE (R1 + R2 + RC)] ∂IC Stability factor, S = _____ = _____________________________________ ∂ICO R1R2 + (b + 1) [R2RC + RE (R1 + R2 + RC)]

1.7.7 Common Base Stability In a common base amplifier circuit, the equation for collector current IC is given by IC = aIE + ICO dI S ª _____ = 1 dICO Since this is highly stable, the common base amplifier circuit is not in need of bias stabilization.

1.7.8 Advantage of Self Bias (Voltage Divider Bias) Over Other Types of Biasing In fixed bias method discussed in Section 1.7.1, the stability factor is given by S =1+b Since b, is normally a large quantity, this circuit provides very poor stability. Therefore the fixed biasing technique is not preferred for biasing the base. In collector-to-base bias method, when RC is very small, S ª 1 + b, which is equal to that of fixed bias. Hence, collector-to-base bias method is also not preferable. In self bias method discussed in Section RB 1.7.5, when ___ is very small. S ª 1, which provides good stability. Hence, self bias method is the best RE one over other types of “biasing”.

EXAMPLE 1.30 The PNP transistor in the circuit of shown Fig. 1.39 has beta = 50. Find the values of RC to obtain VC = 5 V. What happens if the transistor is replaced with another beta = 100? [AU May’11, 8 marks]

Biasing of Discrete BJT and MOSFET 1.43

Solution VB = VCC – 0.7 = 10 – 0.7 = 9.3 V IB =

VB 9.3 = = 93 mA RB 100 K

For b = 50, IC = bIB = 50 ¥ 93 mA = 4.65 mA RC =

VC 5 = = 1075 W IC 4.65 ¥ 10 -3

Fig. 1.39

For b = 100, IC = bIB = 100 ¥ 93 mA = 9.3 mA RC =

VC 5 = = 537.6 W IC 9.3 ¥ 10 -3

EXAMPLE 1.31 Determine the value of RB and RC for a collector to base bias circuit for the specified condition: Vcc = 15 V, Vce = 5 V, Ic = 5 mA and beta = 100. [AU Dec’14, 2 marks]

Solution IB =

IC 5 mA = = 50 mA 100 b

RC =

VCC - VCE 15 - 5 = = 1.98 kW I B + IC 50 ¥ 10 -6 + 5 ¥ 10 -3

Apply KVL to the circuit VCE - I B RB - VBE = 0 RB =

VCE - VBE 5 - 0.7 = = 86 kW IB 50 ¥ 10 -6

EXAMPLE 1.32 Derive the stability factor of the voltage divider bias circuit. Compare the stability factor of fixed bias and voltage divider bias circuits with hFE = 100, RE = 1 kW, R1 = 33 kW, R2 = 12 kW [AU Dec’13, 4 marks]

Solution For fixed bias (i)

S=1+b = 1 + 100 S = 101 Æ fixed bias

1.44

Electronic Circuits I

For voltage divider bias: S=

1+ b where RE = 1 kW Ê RE ˆ 1+ bÁ Ë RE + RB ˜¯

R1R2 32 ¥ 103 ¥ 103 = = 8.727 kW R1 + R2 (32 ¥ 103 ) + (12 ¥ 103 ) RB = 8.727 kW RB =

S=

1 + 100 Ê ˆ 1 + 10 1 + 100 Á 3 3 ˜ Ë (1 + 10 ) + (8.727 + 10 ) ¯ 3

=

101 101 = 1 + (100 ¥ 0.1028) 1 + 10.28

S = 8.954

EXAMPLE 1.33 Design a voltage divider bias circuit for the specified conditions VCC = 12 V, VCE = 6 V, IC = 1 mA, S = 20, b = 100 and VE = 1 V [AU Dec’12, 6 marks]

Solution To find IB and IE IB =

IC 1 ¥ 10 -3 = 10 mA = 100 b

IE = IB + IC = 10 mA + 1 mA = 1.01 mA IE = 1.01 mA IB = 10 mA Find RE and RC RC =

VE 1V = = 990 W I E 1.01 mA

RC =

VCC - VCE - VE 12 - 6 - 1 = IC 1 ¥ 10 -3 A

RC = 5 kW Find R1 and R2 Stability factor S=

b +1 RE 1+ b RE + RB

Fig. 1.40

Biasing of Discrete BJT and MOSFET 1.45

20 =

(990 + RB ) 1 + 100 = 101 990 + RB + 99000 Ê 900 ˆ 1 + 100 Á Ë 990 + RB ˜¯

RB = 23.454 kW or 23454 W R1R2 = 23454 (1) R1 + R2 VB = VE + VEE = 1 + 0.7 = 1.7

RB =

R1 =

VCC - VB 12 - 1.7 10.3 = = I + IB I + IB I + IB

VB 1.7 = I I Substitute equation (2) & (3) in (1), R2 =

(2) (3)

10.3 1.7 17.51 ¥ 1 ( I + I B )I I + IB = RB = 23454 = 10.3 1.7 (10.3I + 1.7( I + IB )) + 1 ( I + I B )I I + IB =

17.51 10.3I + 1.7( I + I B )

241576.21 + 39871.81 + 39871.8IB = 17.51 Substitute IB in above equation, 281448I + 0.398718 = 17.51 I = 60.797 mA Substitute I & IB in equation(2) & (3), R1 =

10.3 10.3 = = 145.486 kW I + I B (60.797 + 10)10 -6

1.7 = 27961.9 W 60.797 ¥ 10 -6 R1 = 145.486 kW

R2 =

R2 = 27.962 kW

1.8 STABILITY The extent to which the collector current IC is stabilised with varying ICO is measured by a stability factor S. It is defined as the rate of change of collector current IC with respect to the collector–base leakage current ICO, keeping both the current IB and the current gain b constant ∂IC dIC DIC S = _____ ª _____ ª _____, b and IB constant ∂ICO dICO DICO

(1.47)

1.46

Electronic Circuits I

The collector current for a CE amplifier is given by IC = b IB + (b + 1)ICO

(1.48)

Differentiating the above equation with respect to IC, we get dICO dIB 1 = b ____ + (b + 1) _____ dIC dIC

(

Therefore,

(b + 1) dIB 1 – b ____ = ______ S dIC

)

1+b S = __________ dIB 1 – b ____ dIC

( )

(1.49)

From this equation, it is clear that this factor S should be as small as possible to have better thermal stability.

Stability factors S¢ and S¢¢ The stability factor S¢ is defined as the rate of change of IC with VBE, keeping ICO and b constant

∂IC DIC S ¢ = _____ ª _____ ∂VBE DVBE The stability factor S ¢¢ is defined as the rate of change of IC with respect to b, keeping ICO and VBE constant ∂IC DIC S¢¢ = ___ ª ____ ∂b Db

EXAMPLE 1.34 For a circuit shown in Fig. 1.41 VCC = 20 V, RC = 2 kW, b = 50, VBE = 0.2 V, R1 = 100 kW RE = 100 W calculate IB, VCE, IC and Stability factor S. [AU Dec’11, 8 marks]

VTH =

VCC R2 20 ¥ 10 = = 1.818 V R1 + R2 100 + 10

RB =

R1 ¥ R2 = 9.09 kW R1 + R2

IB =

VTH - VBE 1.818 - 0.2 = = 114 mA RB + (1 + b )RE 9.09 ¥ 103 + (1 + 50) ¥ 100

IC = bIB = 50 ¥ 114 ¥ 10–3 = 5.7 mA VCE = VCC – ICRC – (1 + b)IBRE = 20 – 5.7 ¥ 10–3 ¥ 2 ¥ 103 – (1 + 50) ¥ 114 ¥ 10–6 ¥ 100 = 8 V S=

1+ b 1 + 50 = = 33 100 Ê RE ˆ Ê ˆ 1+ bÁ Ë RE + RB ¯˜ ËÁ 100 + 9.09 ¥ 103 ¯˜

Fig. 1.41

Biasing of Discrete BJT and MOSFET 1.47

1.9

BIAS COMPENSATION [AU May’14, 6 marks, AU Dec’14, 8 marks, AU May’13, 8 marks]

The various biasing circuits considered in the previous sections used some types of negative feedback to stabilise the operation point. Also, diodes, thermistors and sensistors can be used to compensate for variations in current.

+ VCC

R1

RC IB

Vout

Vin

1.9.1 Thermistor and Sensistor Compensation

R2

[AU May’10, 4 marks]

RT RE

CE

Thermistor compensation In Fig. 1.42 a thermistor, RT, having a negative temperature coefficient is connected in parallel with R2. The resistance of thermistor decreases exponentially Fig. 1.42 Thermistor bias compensation with increase of temperature. An increase in temperature will de+ VCC crease the base voltage VBE, reducing IB and IC. Bias stabilization R1 Rs RC is also provided by RE and CE. Vout

Sensistor compensation In Fig. 1.43 a sensistor, RS, having a

Vin

positive temperature coefficient is connected across R1 (or RE). RS increase with temperature. As temperature increases, the equivalent resistance of the parallel combination of R1 and RS also increases and hence the base voltage VBE decrease, reducing IB and IC. This reduced IC compensates for the increased IC caused by the increase in ICO, VBE and b due to temperature rise.

R2 RE

Fig. 1.43 Sensistor bias compensation + VCC

1.9.2 Compensation Against Variation in VBE [AU May’10, 12 marks] and ICO Compensation for VBE

Rc Vout

RB Vin

(a) Diode compensation in emitter circuit Figure 1.44 shows the Thevenin’s equivalent circuit of the voltage divider bias with bias compensation technique. Here, VDD is separately used to keep diode in forward biased condition. If the diode is of same material and type as the transistor, the voltage across the diode VD will have the same temperature coefficient (2.5 m V/°C) as the base to emitter voltage VBE. If VBE changes by a small amount with change in temperature, then VD also changes by the same amount and therefore, the changes cancel each other.

VBE RE

RD

– VD D +

Fig. 1.44

Stabilization by voltage divider bias compensation

We know that,

[

]

[RB + (1 + b) RE] (RE + RB) (1 + b) VBE = VT – ________________ IC + _______________ ICO b b Rearranging, we have

– V + DD

1.48 Electronic Circuits I

[

]

[RB + (1 + b) RE] (RE + RB) (1 + b) _______________ IC = VT – VBE + _______________ ICO b IC b Hence,

b [VT – VBE] + (RE + RB) (1 + b) ICO IC = _______________________________ RB + (1 + b) RE

From KVL equation of the base circuit of Fig. 1.47, the above equation can be written as b [Vin – (VBE – VD)] + (RE + RB) (1 + b) ICO IC = _____________________________________ RB + (1 + b) RE Since variation of VD is same as VBE, the collector current IC will be insensitive to variation in VBE. (b) Diode compensation in voltage divider circuit Figure 1.45 shows the diode compensation technique used in voltage divider bias. Here, the diode is connected in series with resistance R2 and it is in forward biased condition. Therefore, VE VB – VBE IE = ___ = ________ RE RE and

IC ª IE

Hence,

IC ª IE

+ RC

R1

IC VCC VD1

D1

VD2

D2

VB

RE VE –

Fig. 1.45

Diode compensation in voltage divider bias circuit

When VBE changes with temperature, IC also changes. To cancel the change in IC, one diode is used to compensate the base terminal in VBE as shown in Fig. 1.45. The voltage at the base, VB, becomes VB = VR2 + VD Substituting in the above equation for IC, we get VR2 + VD – VBE IC ª ______________ RE If the diode is of the same material and type as the transistor, then the voltage across the diode will have the same temperature coefficient (2.5 mV/°C ) as the base to emitter voltage VBE. When VBE changes by a small amount with change in temperature, VD also changes by the same amount and thus they cancel each other and the collector current remains constant. Therefore, VR2 IC = ____ RE The change in VBE due to temperature is compensated by a change in the diode voltage that keeps IC stable at Q point.

Rs

RC IB

Diode compensation against variation in ICO Figure 1.46 shows a transistor amplifier with a diode D connected across the base– emitter junction for compensation of change in collector saturation current ICO. The diode is of the same material as the transistor and it is reverse biased by the base–emitter junction voltage VBE, allowing the diode reverse saturation current I0 to flow through diode D. The base current IB = I – Io.

+ VCC

I

IO

Fig. 1.46

Vout

D

Diode bias compensation

Biasing of Discrete BJT and MOSFET 1.49

As long as temperature is constant, diode D operates as a resistor. As the temperature increase, ICO of the transistor increases. Hence, to compensate for this, the base current IB should be decreased. The increase in temperature will also cause the keakage current Io through D to increase and thereby decreasing the base current IB The is the required action to keep IC constant. This method of bias compensation does not need a change in IC to effect the change in IB, as both Io and ICO can track almost equally according to the change in temperature.

1.10 THERMAL STABILITY The collector current for the CE circuit of Fig. 1.17 is given by IC = bIB + (1 + b) ICO. The three variables in the equation, b, IB and ICO increase with rise in temperature. In particular, the reverse saturation current or leakage current ICO changes greatly with temperature. Specifically, it doubles for every 10 °C rise in temperature. The collector current IC causes the collector–base junction temperature to rise which, in turn, increase ICO, as a result IC will increase still further, which will further rise the temperature at the collector–base junction. This process will become cumulative leading to “thermal runaway.” Consequently, the ratings of the transistor are exceeded which may destroy the transistor itself. The collector is normally made larger in size than the emitter in order to help dissipate the heat developed at the collector junction. However, if the circuit is designed such that the base current IB is made to decrease automatically with rise in temperature, then the decrease in b IB will compensate for the increase in (1 + b)ICO, keeping IC almost constant. In power transistors, the heat developed at the collector junction may be removed by the use of heat sink, which is a metal sheet fitted to the collector and whose surface radiates heat quickly.

1.11

DESIGN OF BIASING FOR JFET

[AU Dec’13, 8 marks]

For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q stable in the central portion of the pinch off region. The Q-point should be independent of device parameter variations and ambient temperature changes. This can be achieved by suitably selecting the gate to source voltage (Vgs) and drain current(ID) which is referred to as biasing.

1.11.1 Fixing the Q-point The Q-point, the quiescent point or operating point for a self-biased JFET is established by determining the value of drain current ID for a desired value of gate-to-source voltage, Vgs, or vice-versa. However, if the data sheet of JFET includes a transfer characteristics curve, then the Q-point may be determined by using the procedure given below. (i) Select a convenient value of drain current whose value is generally taken half of the maximum possible value of drain current, IDSS, Then find the voltage drop across source resistor, Rs, by Vs = ID Rs and the gate-to-source voltage from the equation Vgs = – Vs (ii) Plot the assumed value of drain current, ID, and the corresponding gate-to-source voltage, Vgs, on the transfer characteristics curve.

1.50

Electronic Circuits I

(iii) Draw a line through the plotted point and the origin. The point of intersection of the line and the curve gives the desired Q-point. Then, read the co-ordinates of Q-point. It is necessary to fix the Q-point near the mid-point of the transfer characteristic curve of a JFET. The mid-point bias allows a maximum amount of drain current swing between the values of IDSS and the origin. The following analytical method or graphical method can be used for the design of self bias circuit.

Analytical Method The values of the maximum drain current, IDSS, and the gate-to-source cut-off voltage, Vgs(off) are noted down from the data sheets of JFET. The value of the drain current is determined by

[

Vgs ID = 1 – ______ Vgs (off)

]

2

For example, if we select the gate-to-source voltage, Vgs = Vgs(off)/4, then the value of the drain current will be ID = IDSS {1 – 0.25}2 = IDSS (0.75)2 = 0.56 IDSS Here, the drain current is slightly more than one-half of IDSS. But it will bias the JFET close to the midpoint of the curve. The value of the drain resistor, RD, is selected in such a way that the drain voltage, VD, is equal to half the drain supply voltage, RD. The value of gate resistor, RG, is chosen arbitrarily large, so that it prevents loading on the driving stages.

Graphical Method A self-bias line is drawn such that it intersects the transfer characteristic curve near its mid-point gives the required Q-point. Then the co-ordinates of the Q-point are obtained. The value of source resistance, Rs, is expressed by the ratio of gate-to-source voltage, Vgs, to the drain current, ID. Therefore, the source resistance is given by Vgs Rs = ___ ID However, a more accurate method is to draw a self bias line through the co-ordinates of IDSS and Vgs(off) as shown in Fig. 1.47. Then the point of intersection of self-bias line and the transfer characteristic curve locates the Q-point. The value of the source resistor is expressed by the relation Vgs(off) RS =_______ IDSS

Fig. 1.47

Self-bias line through IDSS and Vgs (off)

The value of drain resistor, RD, and the gate resistor, RG, are selected in the same way as discussed above for the analytical method. An FET may have a combination of self bias and fixed bias to provide stability of the quiescent drain current against device and temperature variations.

Biasing of Discrete BJT and MOSFET 1.51

1.11.2 Self-bias Figure 1.48 shows the self-bias circuit for an N-channel FET. When the drain voltage VDD is applied, a drain current ID flows even in the absence of gate voltage (VG). The voltage drop across resistor Rs produced by the drain current is given by Vs = ID Rs. This voltage drop reduces the gate to source reverse voltage required for FET operation. The feedback resistor Rs prevents any variation in FET drain current. The drain voltage,

VD = VDD – ID RD Fig. 1.48

The drain-to-source voltage, VDS = VD – Vs = (VDD – ID RD) – ID Rs

Self-bias circuit for an N-channel JFET

= VDD – ID(RD + Rs) The gate-to-source voltage Vgs = VGG – Vs = 0 – ID Rs = – IDRs When drain current increases, the voltage drop across Rs increases. The increased voltage drop increases the reverse gate to source voltage, which decreases the effective width of the channel and hence, reduces the drain current. Now the reduced drain current decreases the gate to source voltage which, in turn, increases the effective width of channel thereby increasing the value of drain current.

1.11.3 Voltage Divider Bias Figure 1.49(a) shows the voltage divider bias circuit and its Thevenin’s equivalent is shown in Fig. 1.49(b). Resistors R1 and R2 connected on the gate side forms a voltage divider. The gate voltage,

(

)

R2 VGG = _______ VDD and R1 + R2

Fig. 1.49

R1R2 RG = _______ R1 + R2

(a) Voltage Divider Bias Circuit, and (b) Thevenin’s Equivalent Circuit

The bias satisfies the equation Vgs = VGG – IDRs.

1.52

Electronic Circuits I

The drain to ground voltage, VD = VDD – IDRD. If the gate voltage VGG is very large as compared to gate to source Vgs, the drain current is approximately constant. In practice, the voltage divider bias is less effective with JFET than BJT. This is because, in BJT, VBE ª 0.7 (silicon) with only minor variations from one transistor to another. But in a JFET, the Vgs can vary several volts from one JFET to another.

1.11.4

Fixed Bias

The FET device needs d.c. bias for setting the gate to source voltage Vgs to give desired drain-current ID. For a JFET, the drain current is limited by IDSS. Since the FET has a high input impedance, it does not allow the gate current to flow and the dc voltage of the gate set by a voltage divider or a fixed battery is not affected or loaded by the FET. The fixed bias circuit for an N-channel JFET shown in Fig. 1.50 is obtained by using a supply VGG. This supply ensures that the gate is always negative with respect to source and no current flows through resistor RG and gate terminal i.e. IG = 0. The VGG supply provides a voltage Vgs to bias the N-channel JFET, but no resulting current is drawn from the battery VGG. Resistor RG is included to allow any ac signal applied through capacitor C to develop across RG. While any ac signal will develop across RG, the d.c. voltage drop across RG is equal to IGRG which is equal to zero volt.

Fig. 1.50

Fixed bias circuit for an N-Channel JFET

Then, the gate to source voltage Vgs is Vgs = VG – Vs = –VGG – 0 = –VGG The drain-source current ID is then fixed by the gate-source voltage. This current will cause a voltage drop the drain resistor RD and is given as VDD = ID ◊ RD + VDS VDD – VDS ID = __________ RD

EXAMPLE 1.35 Calculate the value of feedback resistor (Rs) required to self bias an N-channel JFET with IDSS = 40 mA, Vp = –10 V and VGSQ = –5 V. [AU May’10, 2 marks]

Solution Given that

IDSS = 40 mA, VP = –10 V and VGSQ = –5 V, VGSQ = –IDQRS RS = –VGSQ/IDQ

Where

(1) 2

IDQ = IDSS(1 – VGTSQ/VP)

= (40 ¥ 10–3)[1 – (–5)/(–10)]2 = (40 ¥ 10–3)(1/4)

Biasing of Discrete BJT and MOSFET 1.53

IDQ = 10 mA From Equation 1 RS = –(–5)/(10 ¥ 10–3) = 500 W RS = 500 W

EXAMPLE 1.36 Determine IDQ, VGSQ, VD, VS, VDS and VDG for the network of Fig. 1.51 shown below [AU May’09, 16 marks]

Solution Calculate VG VG =

VDD R2 16 ¥ 270 K = = 1.823 V R1 + R2 2.1 M + 270 K

Obtain expression for VGS VGS = 1.823 – IDRS = 1.823 – 1.5 ¥ 103ID Calculate ID Ê V ˆ I D = I DSS Á1 - GS ˜ VP ¯ Ë

2

3 ˆ Ê = 8 ¥ 10 -3 Á1 - (1.823 - I D ¥ 1.5 ¥ 10 ) ˜ Ë ¯ -4

2

Fig. 1.51

= 8 ¥ 10–3(1 – [(0.456 + 375ID)])2 = 8 ¥ 10–3(1.456 – 375ID)2 = 8 ¥ 10–3(2.12 – 1092ID + 140625ID2) ID = 0.01696 – 9.736ID + 1125ID2 1125ID2 – 90736ID + 0.01696 = 0 Solving quadratic equation using formula

-b ± b2 - 4ac we get 2a

-( -9.736) ± ( -9.736)2 - 4 ¥ 1125 ¥ 0.01696 2 ¥ 1125 9.736 ± 4.2976 = 2 ¥ 1125 =

= 6.237 mA or 2.417 mA If we calculate value of VDS taking ID = 6.237 mA we get, VDS = VDD – ID(RD + RS) = 16 – 6.237 ¥ 10–3 (2.4 K + 1.5 K) = –8.3243 V Practically the value of VDS must be positive, hence ID = 6.237 mA is invalid ID = 2.417 mA

1.54

Electronic Circuits I

Step: 4 calculate VDS, VGS, VS, VD & VDG VDS = VDD – ID(RD + RS) = 16 – 2.417 ¥ 10–3 (2.4 K + 1.5 K) = 6.5737 V VGS = 1.823 – IDRS = 1.823 – (2.417 ¥ 10–3 ¥ 1.5 ¥ 103) = –1.8025 V VS = IDRS = 2.417 ¥ 10–3 ¥ 1.5 ¥ 103 = 3.6255 V VD = VDD – IDRD = 16 – (2.417 ¥ 10–3 ¥ 2.4 ¥ 103) = 10.2 V VDG = VD – VG = 10.2 – 1.823 = 8.377 V

1.12 1.12.1

DESIGN OF BIASING FOR MOSFET Biasing of Enhancement MOSFET

[AU Dec’13, 8 marks, AU Dec’14, 8 marks]

Figure 1.52 shows the drain-to-gate bias circuit for enhancement mode MOSFET. Here, the gate bias voltage is R1 Vgs = _______ VDS R1 + Rf

[

–VDD

]

This circuit offers the d.c. stabilisation through the feedback resistor Rf . However, the input resistance is reduced because of Miller effect. Also, the voltage divider biasing technique given for JFET can be used for the enhancement MOSFET. Here, the d.c. stability is accomplished by the d.c. feedback through Rs. But the self-bias technique given for JFET cannot be used for establishing an operating point for the enhancement MOSFET because the voltage drop across Rs is in a direction to reverse-bias the gate and it actually needs forward gate bias.

RD Rf

D

VGG G

R1

S

Fig. 1.52 Drain-to-gate bias circuit for enhancement MOSFET

Figure 1.53 shows an N-channel enhancement mode MOSFET common source circuit with source resistor. The gate voltage is R2 VG = VGS = _______ (VDD) R1 + R2

(

)

and the gate-to-source voltage is Vgs = VDD – VG Assuming that Vgs > VTN and the MOSFET is biased in the saturation region, the drain current is ID = KN(Vgs – VTN)2 Here the threshold voltage VTN and conduction parameter KN are functions of temperature. The drain-to-source voltage is VDS = VDD – IDRD

Fig. 1.53 N-channel enhancement mode MOSFET common source circuit with source resistor

Biasing of Discrete BJT and MOSFET 1.55

If VDS > VDS (sat) = Vgs – VTN, then the MOSFET is biased in the saturation region. If VDS < VDS (sat) = Vgs – VTN, then the MOSFET is biased in the non-saturation region, and the drain current is given by ID = KN [2(Vgs – VTN) VDS – V2DS]

1.12.2 Biasing of Depletion MOSFET Both the self-bias technique and voltage divider bias circuit given for JFET can be used to establish an operating point for the depletion mode MOSFET.

EXAMPLE 1.37 Calculate the operating point of the self biased JFET having the supply voltage VDD = 20 V, maximum value of drain current IDSS = 10 mA and Vgs = – 3 V at ID = 4 mA. Also, determine the values of resistors RD and Rs to obtain this bias condition.

Solution We know that the value of drain current at Q-point, IDSS 10 × 10–3 IDQ = ____ = ________ = 5 mA 2 2 and the value of drain-to-source voltage at Q-point, VDD 20 VDSQ = ____ = ___ = 10 V 2 2 Therefore, the operating point is at VDS = 10 V and ID = 5 mA. Also, we know that the drain-to-source voltage, VDS = VDD – IDRD 10 = 20 – (4 × 10–3) RD 20 – 10 RD = _______ = 2.5 kW 4 × 10–3 The source voltage or voltage across the source resistor Rs is Therefore,

Vs = –Vgs = –3 V i.e.

3 = ( 4 × 10–3) Rs

Also,

Vs = IDRs

Therefore,

3 Rs = _______ = 750 W 4 × 10–3

EXAMPLE 1.38 Calculate the values of Rs required to self bias an N-channel JFET with IDSS = 40 mA, VP = – 10 V and VGSQ = – 5 V.

[

Vgs Solution We know that ID = IDSS 1 – ___ VP

]

2

1.56 Electronic Circuits I

Substituting the given values, we get

[

]

(–5) 2 ID = 40 × 10–3 1 – _____ = 10 mA (–10)

| |

VDSQ 5 Rs = _____ = ________ = 500 W ID 10 × 10–3

Therefore,

EXAMPLE 1.39 A JFET amplifier with a voltage divider biasing circuit, shown in Fig. 1.54, has the following parameters: VP = – 2 V, IDSS = 4 mA, RD = 910 W, Rs = 3 kW, R1 = 12 MW, R2 = 8.57 MW and VDD = 24 V. Find the value of the drain current ID at the operating point. Verify whether the FET will operate in the pinch-off region.

Oxide Insulation Gate 1 Gate 2 (Metal) (Metal)

P

P

Drain 1 Source 2 N

Source 1 N

N

Substrate (Bulk)

Unit No. 1

P

P

Channel 2 (N)

Channel 1 (N)

Gate-protection Diodes

Drain 2 N

Unit No. 2

Source terminal

Drain terminal

Gate protection diodes

Fig. 1.54 Cross sectional view of the dual gate prortected N-channel depletion type MOSFET

Solution We obtain R2 8.57 × 106 VGG = VDD _______ = 24 _______________6 = 10 V R1 + R2 (12 + 8.57) × 10 We know that

(

Vgs ID = IDSS 1 – ___ VP

(

2

)

)

VGG – ID Rs = IDSS 1 – __________ , where Vgs = VGG – ID Rs VP

Biasing of Discrete BJT and MOSFET 1.57

Expressing ID and IDSS in mA, we have

(

i.e.,

10 – ID × 3 ID = 4 × 1 – __________ –2 2 9ID – 73ID + 144 = 0

Therefore,

2

)

ID = 3.39 mA or 4.72 mA

As ID = 4.72 mA > 4 mA = IDSS, this value is inappropriate. So, IDQ = 3.39 mA is selected. Therefore, VGSQ = VGG – IDQRs = 10 – (3.39 × 10–3 × 3 × 103) = – 0.17 V and

VDSQ = VDD – IDQ (RD + Rs) = 24 – 3.39 × 10–3 (0.91 + 3) × 103 = 10.745 V

Then

VDGQ = VDSQ – VGQS = 10.745 + 0.17 = 10.915 V

which is greater than |VP | = 2 V. Hence, the FET is in the pinch-off region.

EXAMPLE 1.40 A voltage divider bias is provided to an N-channel JFET circuit as shown in Fig. 1.55. To establish IDSS = 10 mA, VP = –3.5 V, R1 + R2 = 120 kW, ID = 5 mA and VDS = 5 V, determine the values of R1, R2 and RD.

Solution is given by

Let us assume that the JFET is biased in the saturation region. Then the d.c. drain current

(

Vgs ID = IDSS 1 – ___ VP

Therefore,

(

2

) )

Vgs 5 = 10 1 – ______ (–3.5)

2

By solving, we get Vgs = –1.008 V The voltage at the source terminal is Vs = IDRs – 5 = (5) (0.5) – 5 = –2.5 V The gate voltage is VG = Vgs + Vs = –1.008 – 2.5 = –3.508 V The gate voltage can be written as

(

)

R2 VG = _______ (10) – 5 R1 + R2 Therefore,

R2 –3.508 = ____ (10) – 5 120

i.e.,

R2 = 2.984 kW

and

R1 = 17.016 kW

The drain-to-source voltage is VDS = 5 – IDRD – IDRs – (–5)

Fig. 1.55

1.58 Electronic Circuits I

Substituting the specified values, we get 10 – VDS – ID Rs 10 – 5 – (5) (0.5) RD = ______________ = ______________ = 0.5 kW 5 Vgs – VP = –1.24 – (–3.5) = 2.26 V Here, since VDS > (Vgs – VP), the JFET is biased in the saturation region, which satisfies the initial assumption.

EXAMPLE 1.41 For the circuit shown in Fig. 1.56, find the values of VDS and Vgs. Given, ID = 5 mA, VDD = 10 V, RD = 1 KW and Rs = 500 W.

Solution

VGG = Vgs + IDRs

Since

VGG = 0, Vgs = – IDRs = – 5 × 10–3 × 500 = – 2.5 V

We know that VDD = ID(RD + Rs) + VDS Therefore,

VDS = VDD – ID(RD + Rs) = 10 – 5 × 10–3 (1500) = 2.5 V Fig. 1.56

EXAMPLE 1.42

For the common-source N-channel MOSFET circuit shown in Fig. 1.57 with the threshold voltage VTN = 1.5 V, conduction parameter KN = 1 mA/V2, the channel-length modulation parameter l = 0.01 V–1, Ri = R1 || R2 = 100 kW and the current at the transition point IDt = 4 mA. Design the MOSFET circuit with voltage divider bias such that IDQ = 1.5 mA and Q-point is in the middle of the saturation region.

Solution To determine VDSt : We know that IDt = 4 = KN (VGst – VTN)2 = 1 (VGSt – 1.5)2

VDD = 12 V

RD

where the subscript t indicates transition point values. Solving, we get Therefore,

VGSt = 3.5 V VDSt = VGSt – VTN = 3.5 – 1.5 = 2 V

If the Q-point is in the middle of the saturation region, then VDSQ = 7 V, which gives 10 V peak-to-peak symmetrical output voltage. From Fig. 1.55, Therefore, Then Therefore,

R1

V CC

Vi

±

R2

VDSQ = VDD – IDQRD VDD – VDSQ 12 – 7 RD = ___________ = ______ = 3.33 kW IDQ 1.5 2

IDQ = 1.5 = KN (VGSQ – VTN) VGSQ

= (1) (VGSQ – 1.5)2 = 2.73 V

ID = 2 mA

Fig. 1.57

Biasing of Discrete BJT and MOSFET 1.59

(

)

(V ( ) ( _______ R +R )

R2 1 VGSQ = 2.73 = _______ (VDD) = ___ R1 + R2 R1

Then,

R 1 R2 1

2

DD)

Ri (100 × 103) (12) 2.73 = ___ (VDD) = ______________ R1 R1 By solving, we get

R1 = 439.6 kW and R2 = 129.45 kW

EXAMPLE 1.43 For the N-channel depletion mode MOSFET circuit shown in Fig. 1.58. VTN = –2 V and KN = 0.1 mA/V2. Assume that VDD = 5 V and Rs = 5 kW. Determine ID and VDS.

Solution

Let us assume that the MOSFET is biased in the saturation region.

Then the d.c. drain current is ID = KN (Vgs – VTN)2 = KN (–VTN)2 = (0.1) (–(–2))2 = 0.4 mA The d.c. drain-to-source voltage is VDS = VDD – IDRs = 5 – (0.4)(5) = 3 V Then,

VDS(sat) = Vgs – VTN = 0 – (–2) = 2 V

Since VDS > VDS(sat), the MOSFET is biased in the saturation region. Fig. 1.58

EXAMPLE 1.44 Determine the following for the network shown in Fig. 1.59. (iv) VG (v) Vs (i) VGSQ (ii) VDS (iii) VD

35 V (VDD)

Solution (i) VGSQ = – VGG = – 3V (ii) IDQ = IDSS

[

]

2

RD

Vgs –3 1 – ___ = 12 × 10–3 1 – ___ VP –6

[ ( ) ] = 3 mA

3.5 kW

2

D IDSS = 12 mA VP = – 6V

G

VDS = VDSQ = VDD – IDQRD = 35 – 3 × 10–3 × 3.5 × 103 = 24.5 V (iii) VD = VDS + Vs = 24.5 + 0 = 24.5 V (v) VS = 0 V

(iv) VG = – 3V

2 MW

VGG

S

3V

Fig. 1.59

1.60 Electronic Circuits I

EXAMPLE 1.45 Determine IDQ, VGSQ, VD, VDS, and VDG for the given network shown in Fig. 1.60.

Solution

25 V

To find expression for VGS : R2 270 Vgs = ________ × VDD = ___________ × 20 = 2.28 V R1 + R2 (2100 + 270)

4.7 kW

Vs = 1.5 ID

2.1 MW

VD

Therefore, Vgs = VG – Vs = (2.28 – 1.5 ID)

10 mF

VG

To find ID :

[

]

Vs

Vgs 2 ID = IDSS 1 – ___ mA VP

[

IDSS = 8 mA VD = –4 V

270 kW 1.5 kW

20 mF

]

(2.28 – 1.5 ID) 2 ID = 8 1 – ____________ mA 4 8 ___ Therefore, ID = [4 + 2.28 – 1.5 ID]2 = 0.5 (6.28 – 1.5 ID)2 16 2ID = 39.44 – 18.84 ID + 2.25 I2D

Fig. 1.60

2.25 I2D – 20.84 ID + 39.44 = 0

________________________

20.84 ± ÷(20.84)2 – (4 × 2.25 × 39.44) ________________________________ Therefore, ID = = 6.6 mA or 2.6 mA 2 × 2.25 For ID = 6.6 mA, VDS is negative and hence this value may be neglected. Let us choose ID = 2.65 mA. Therefore, IDQ = 2.65 mA. To find VGSQ : VGSQ = 2.28 – 1.5 IDQ = 2.28 – (1.5 × 2.65) = – 1.695 V To find VDSQ : VDSQ = VDD – IDQ(RD + Rs) Therefore,

VDSQ = 20 – 2.65 × 10–3 (4.7 + 1.5) × 10–3 = 3.57 V

To find VD Vs and VDG : Vs = IDRs = 2.65 × 10–3 × 1.5 × 10–3 = 3.975 V Hence,

VD = Vs + VDS = 3.975 + 3.57 = 7.545 V VDG = VD – VG = 7.545 – 2.28 = 5.265 V

Biasing of Discrete BJT and MOSFET 1.61

EXAMPLE 1.46 For the given measurement Vs = 1.7 V for the network as shown in Fig. 1.61, determine (i) IDQ

(ii) VGSQ

(iii) IDSS

(iv) VD

(v) VDS

Solution (i)

Given Vs = 1.7 V Vs = IDRs Vs 1.7 IDQ = ___ = ____ = 3.33 mA Rs 510

(ii)

VGSQ = VG – Vs = – Vs = – 1.7 V

(

Vgs ID = IDSS 1 – ___ VP

(iii)

)

2

ID 3.33 × 10–5 IDSS = _________2 = ___________2 = 10 mA Vgs (–1.7) 1 – ______ 1 – ___ (–4) VP

(

)

VD = VDD – IDRD = 18 – 3.33 × 10–3 × 2 × 103 = 11.34 V

(iv) (v)

) (

Fig. 1.61

VDS = VD – Vs = 11.34 – 1.7 = 9.64 V

EXAMPLE 1.47 For a circuit shown in Fig. 1.62, calculate V0, Zi and Z0. Given input is V1 = 0.2 V(rms). IDSS = 9 mA and VP = – 4.5 V.

Solution

Zi = RG = 10 MW

(

Vgs ID = IDSS 1 – ___ VP

)

2

(

–IDRs = 9 × 10–3 1 – ______ VP

2

)

(–1000 ID) 2 = 9 × 10–3 1 – _________ – 4.5 = 9 × 10–3 (1 – 222.22 ID)2

(

)

= 9 × 10–3(1 – 444.44 ID + 49383I D2 ) ID = 9 × 10–3 – 4ID + 444.45 I2D Therefore, 444.45 I2D – 5ID + 9 × 10–3 = 0 Solving the quadratic equation, we get ID = 2.25 mA or 9 mA

Fig. 1.62

1.62 Electronic Circuits I

Since ID < IDSS, we take ID = 2.25 mA. Therefore, 2IDSS 2 × (9 × 10–3) gmo = _____ = ____________ = 4 mS 4.5 |VP|

(

VGSQ gm = gmo 1 – _____ VP

)

where VGSQ = – IDRs = – 2.25 × 10–3 1000 = – 2.25 V (2.25) gm = 4 × 10–3 1 – ______ = 2 mS (4.5)

(

)

1 1 _______ 3 Zo = ___ gm || Rs = 2 × 10–3 || 1 × 10 = 333.33W gm(rd || Rs) gm Rs 2 × 10–3 × 1 × 103 = 0.667 AV = _____________ = _________ = ____________________ 1 + gm(rd || Rs) 1 + gm Rs 1 + (2 × 10–3 × 1 × 103) Vo = Vi × AV = 0.2 × 0.667 = 0.133 V

EXAMPLE 1.48 An N-channel JFET having VP = – 4 V and VDSS = 10 mA is used in the circuit of Fig. 1.63. The parameter values are VDD = 18 V, Rs = 2kW, R1 = 450 kW, and R2 = 90 kW. Determine ID and VDS.

Solution

To find VGS : Vgs = VG – ID Rs R2 90 × 103 VG = _______ × VDD = ______________3 × 18 = 3 V R1 + R2 (450 + 90) × 10

Therefore,

Vgs = (3 – 2 × 103 ID)

To find ID :

[

]

[

Vgs 2 (3 – 2 × 103 ID) ID = IDSS 1 – ___ = 10 × 10–3 1 – _____________ VP –4

]

2

10 × 10–2 = ________ [4 + 3 – 2 × 103 ID]2 16 Therefore, 1.6 ID = 10–3 [7 – 2 × 103 ID]2 = 0.049 – 28 ID + 4 × 103 I2D 4 × 103 I2D – 29.6 ID + 0.049 = 0

_________________________

29.6 ± ÷(29.6)2 – 4 × 4 × 103 × 0.049 ID = ________________________________ 2 × 4 × 103 Therefore, ID = 4.9 mA or 2.5 mA If ID = 4.9 mA, then VDS would be negative and hence this is not acceptable.

Fig. 1.63

Biasing of Discrete BJT and MOSFET 1.63

Therefore,

IDQ = 2.5 mA

To find VDS : VDS = VDD – IDQ(RD + Rs) = 18 – 2.5 × 10–3 (2 + 2) × 103 = 8 V

EXAMPLE 1.49 Determine Vgs, ID, VDS , VD and VG for the circuit shown in Fig. 1.64.

Solution

To find VGSQ :

20 V 3

For a self bias circuit, VGSQ = – IDRs = – ID × 10

3.3 kW

To find ID : ID = IDSS

[

[

]

Vgs 2 (1 × 103 ID) 1 – ___ = 8 × 10–3 1 + __________ VP –6

[

1000 ID = 8 × 10–3 1 – _______ 6

]

]

D

2

IDSS = 3 mA VP = – 6 V

G

2

S 1 MW

1 kW

Therefore, 36 ID = 8 × 10–3 [6 – 1000 ID]2 = 8 × 10–3 [36 – 12 × 103 ID + 106 I2D] = 8 × 103 I2D – 132ID + 0.288 = 0

________________________

132 ± ÷(132)2 – 4 × 8 × 103 × 0.288 ______________________________ ID = 2 × 8 × 103 Therefore,

ID = 13.9 mA or 2.5 mA

But ID cannot be higher than IDSS, Therefore, ID = 4.225 mA To find VDS : VDS = VDD – ID(RD + Rs) = 20 – 2.5 × 10–3(3.3 + 1) × 103 = 9.25 V To find Vgs, VD and Vs : Vgs = 1 × 103 × ID = 1 × 103 × 2.5 × 10–3 = 2.5 V Vs = IDRs = 2.5 × 10–3 × 1 × 103 = 2.5 V VD = Vs + VDS = 2.5 + 9.25 = 11.75 V

EXAMPLE 1.50 Determine the following for the network shown in Fig. 1.65 – VGSQ, VDQ, VD, VG, Vs and VDS .

Solution

VG = 0, Vs = IDRs Vgs = VG – Vs = 0 – IDRs = – 680 ID

Fig. 1.64

1.64 Electronic Circuits I

To find ID :

12 V

We know that ID = IDSS

(

Vgs 1 – ___ VP

)

2

= 12 × 10–3

( (

–680 ID 1 – _______ –6

= 152.6 I2D – 2.7 ID + 0.01 _____________________

2.7 ± ÷(2.7)2 – 4 × 152.6 × 0.01 ___________________________ ID = 2 × 152.6

Therefore,

))

2

1.5 kW 10 mF

D G

Vo IDSS = 3 mA, VP = – 6V 10 mF

V1

S

= 12.4 mA or 5.28 mA

680 W

Since ID is less than IDSS, IDQ = 5.28 mA

Fig. 1.65

To find VGSQ : VGSQ = – 680 ID = – 680 × 5.28 × 10–3 = –3.6 V To find Vs :

Vs = IDRs = 5.28 × 10–3 × 680 = 3.6 V

To find VDS : VDS = VDD – ID(RD + Rs) = 12 – 5.28 × 10–3 ( 1.5 × 103 + 680 ) = 12 – 11.51 = 0.49 V To find VD : VD = Vs + VDS = 3.6 + 0.49 = 4.09 V

TWO MARK QUESTION AND ANSWERS 1. Define Stability Factors. [AU Dec’09, AU May’10] The stability factor is defined as the rate of change of collector current Ic with respect to the collector- base leakage current Ico, keeping both the current IB and the current gain b constant. S=

dI ∂IC DI ª C ª C , b and IB Constant ∂ICO dICO DICO

2. Draw the fixed bias single stage transistor circuit. Fixed bias single stage transistor circuit is shown in below

[AU Dec’09]

3. Derive for the stability factor S for a fixed bias circuit.

[AU Dec’10]

Biasing of Discrete BJT and MOSFET 1.65 A common emitter amplifier using fixed bias circuit is shown in fig. The d.c. analysis of the circuit yields the following equation

VCC = IBRB + VBE Therefore, IB =

VCC - VBE RB

Since this equation is independent of current IC, dIB/dIC = 0 and the stability factor is S = 1 + b 4. Draw a single stage self biased circuit using pnp transistor.

[AU May’11]

5. What is need for biasing in transistor amplifier? [AU May’11] When a transistor is biased properly, it works efficiently and produces no distortion in the output signal and thus operating point can be maintained stable. 6. Define three stability factors. [AU Dec’12] The stability factor is defined as the rate of change of collector current Ic with respect to the collector- base leakage current Ico, keeping both the current IB and the current gain b constant. S=

dI ∂IC DI ª C ª C , b and IB Constant ∂ICO dICO DICO

The Stability factor S¢ is defined as the rate of change of Ic with VBE keeping ICO and b constant. S¢ =

∂IC DI ª C ∂VBE DVBE

The Stability factor S≤ is defined as the rate of change of Ic with respect to b, keeping VBE and ICO constant. S ¢¢ =

∂IC DIC ª ∂b Db

7. Define the term biasing. [AU May’13] In order to produce distortion free output in amplifier circuits, the supply voltages and resistances in the circuit must be suitably chosen. These voltages and resistances establish a set of dc voltage VCEQ and current ICQ

1.66 Electronic Circuits I to operate the transistor in the active region. These voltages and currents are called quiescent values which determine the operating point for the transistor. The process of giving proper supply voltages and resistances for obtaining the desired Q point is called biasing. The circuits used for getting the desired and proper operating point are know as biasing circuits. 8. Write the conditions of thermal stability. [AU May’13] Condition for thermal stability is ∂PC ∂PD < ∂T j ∂T j 9. What is the function of Q point? [AU Dec’13] The function of Q point is to establish certain dc Current and voltage conditions to operate transistor in a particular operation region at zero signal level. 10. What is thermal runaway? [AU May’14] The continuous increase in collector current due to poor biasing cause the temperature at collector terminal to increase. If no stabilization is done, the collector leakage current also increases. This further increases the temperature. This action becomes cumulative and ultimately the transistor burns out. The self destruction of an unstabilised transistor is known as thermal runaway. 11. What are the factors against which an amplifier needs to be stabilized? [AU May’14] The stability factor indicates the degree of charge in operating point due to variation in b, ICO and VBE.

REVIEW QUESTIONS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

What is a Bipolar junction transistor? How are its terminals named? Explain the operation of NPN and PNP transistors. What are the different configurations of BJT? Explain the input and output characteristics of a transistor in CB configuration. Explain the early effect and its consequences. Derive the relationship between a and b. Why does the CE configuration provide large current amplification while the CB configuration does not? Draw the circuit diagram of an NPN junction transistor CE configuration and describe the static input and output characteristics. Also, define active, saturation and cut-off regions, and saturation resistance of a CE transistor. How will you determine h-parameters from the characteristics of CE configuration? Determine the h-parameters from the characteristics of CB configuration. What is the relation between IB, IE and IC in CB configuration? Explain the laboratory setup for obtaining the CC characteristics. Compare the performance of a transistor in different configurations. What is meant by Q-point? What is the need for biasing a transistor? What factors are to be considered for selecting the operating point Q for an amplifier? Distinguish between d.c. and a.c. load lines with suitable diagrams. Briefly explain the reasons for keeping the operating point of a transistor as fixed. What is thermal runaway? How can it be avoided? What three factors contribute to thermal instability? Define ‘stability factor.’ Why would it seem more reasonable to call this an instability factor?

Biasing of Discrete BJT and MOSFET 1.67 22. Draw a fixed bias circuit and derive an expression for the stability factor. 23. If the coordinates of the operating point of a CE amplifier using fixed bias or base resistor method of biasing are VCE = 6 V and IC = 1 mA, determine the value of RC and RB. [Ans. RC = 3 kW, RB = 300 kW] 24. Consider a common emitter NPN transistor with fixed bias as shown in Fig. 1.24. If b = 80, RB = 390 kW, RC = 1.5 kW and VCC = 30 V, find the coordinates of the Q-point. [Ans. 21 V, 6 mA] 25. A germanium transistor having b = 100 and VBE = 0.2 V is used in a fixed bias amplifier circuit where VCC = 16 V, RC = 5 kW and RB = 790 kW. Determine its operating point. 26. Derive an expression for the stability factor of a collector-to-base bias circuit. 27. Mention the disadvantages of collector-to-base bias. Can they be overcome? 28. In a germanium transistor CE amplifier biased by feedback resistor method, VCC = 20V, VBE = 0.2 V, b = 100 and the operating point is chosen such that VCE = 10.4 V and IC = 9.9 mA. Determine the values of RB and RC. [Ans. 100 kW, 1 kW] 29. Draw a circuit diagram of CE transistor amplifier using emitter biasing. Describe qualitatively the stability action of the circuit. 30. Draw a voltage divider bias circuit and derive an expression for its stability factor. 31. Why does potential divider method of biasing become universal? 32. If the various parameters of a CE amplifier which uses the self bias method are VCC = 12 V, R1 = 10 kW, R2 = 5 kW, RC = 1 kW, RE = 2 kW and b = 100, find (i) the coordinates of the operating point, and (ii) the stability factor, assuming the transistor to be of silicon. [Ans. VCE = 7.05 V, IC = 1.65 mA, S = 2.62] 33. In a CE germanium transistor amplifier using self bias circuit, RC = 2.2 kW, b = 50, VCC = 9 V and the operating point is required to be set at IC = 2 mA and VCE = 3V. Determine the values of R1, R2 and RE. [Ans. R1 = 17.75 kW, R2 = 4.75 kW, RE = 800 W] 34. Determine the operating point for the circuit of a potential divider bias arrangement with R2 = RC = 5 kW, RE = 1 kW and R1 = 40 kW. [Ans. VCE = 6 V, IC = 1 mA] 35. Calculate the values of R1 and RC in the voltage divider bias circuit so that Q-point is at VCE = 6 V and IC = 2 mA. Assume the transistor parameters are: a = 0.985, ICBO = 4 mA and VBE = 0.2 V. [Ans. RC = 3 kW, R1 = 5.54 kW] 36. Determine the stability factor for a CB amplifier circuit. 37. Draw a circuit which uses a diode to compensate for changes in ICO. Explain how stabilisation is achieved in the circuit. 38. How will you provide temperature compensation for the variations of VBE and stabilisation of the operating point? 39. What is the principle of providing thermal stabilisation by means of different methods of transistor biasing? How does this differ from the compensation techniques using a diode or thermistor or sensistor? 40. Draw two biasing circuits for a JFET or a depletion type MOSFET. 41. Determine the values of resistors RD and Rs for a self-biased P-channel JFET having the following parameters: VP = 5 V, IDSS = 12 mA, VDD = 12 V, ID = 5 mA and VDS = 6 V. [Ans. RD = 1.5 kW; Rs = 525W] 42. Determine the value of Rs required to self-bias an N-channel JFET with IDSS = 50 mA, VP = –10 V and VGSQ = – 5 V. [Ans. RS = 400 W] 43. In a self-bias N-channel JFET circuit, the operating point is to be set at ID = 1.5 mA and VDS = 10 V. The JFET parameters are IDSS = 5 mA and VP = – 2 V. Find the values of Rs and RD. Given that VDD = 20 V. [Ans. Rs = 0.6 kW, RD = 6 kW.] 44. In an N-channel JFET biased by potential divider method, it is desired to set the operating point at ID = 2.5 mA and VDS = 8V. If VDD = 30 V, R1 = 1 MW and R2 = 500 kW. Find the value of Rs. The parameters of JFET are IDSS = 10 mA and VP = –5V. [Ans. Rs = 5 kW]. 45. Draw two biasing circuits for an enhancement type MOSFET. 46. Explain how an FET is used as a voltage variable resistor.

2 2.1

BJT AMPLIFIERS

BJT AMPLIFIER

A circuit that increases the amplitude of the given input signal is an amplifier. A small a.c. signal fed to the amplifier is obtained as a larger a.c. signal of the same frequency at the output. Amplifiers constitute an essential part of radio, television and other communication circuits. In discrete circuits, Bipolar junction transistors and Field effect transistors are commonly used as amplifying elements. Depending on the nature and level of amplification and the impedance matching requirements different types of amplifiers can be considered and they are discussed in this chapter.

2.1.1 Classification of Amplifier Amplifiers can be classified as follows: 1. Based on the transistor configuration (a) Common emitter amplifier (b) Common collector amplifier (c) Common base amplifier 2. Based on the active device (a) BJT amplifier (b) FET amplifier 3. Based on the Q-point (operating condition) (a) Class A amplifier (b) Class B amplifier (c) Class AB amplifier (d) Class C amplifier 4. Based on the number of stages (a) Single stage amplifier (b) Multistage amplifier 5. Based on the output (a) Voltage amplifier (b) Power amplifier

2.2

Electronic Circuits I

6. Based on the frequency response (a) Audio frequency (AF) amplifier (b) Intermediate frequency (IF) amplifier (c) Radio frequency (RF) amplifier 7. Based on the bandwidth (a) Narrow band amplifier (normally RF amplifier) (b) Wide band amplifier (normally video amplifier)

2.2 SINGLE STAGE AMPLIFIER Single stage amplifiers have only one amplifying device, say, BJT in CE, CC or CB configuration or FET in CS, CD or CG configuration.

2.2.1 Common Emitter Amplifier

[AU May’13, 6 marks]

Figure 2.1 shows the circuit of a single stage CE amplifier using NPN transistor. The emitter-base junction is forward biased by power supply VBB and collector-base junction is reverse biased by power supply VCC, so that the transistor remains in the active region throughout its operation. The Quiescent (Q) point is determined by VCC, RB and RC. Input signal is applied to the base-emitter circuit and the amplified output signal is taken from the CE circuit. C1 and C2 are coupling capacitors to provide d.c. isolation at the input and output of the amplifier.

Fig. 2.1 Common emitter amplifier

Instead of using two power supplies, the same bias conditions can be set up in the CE amplifier circuit with a single power supply as shown in Fig. 2.2. Referring to Fig. 2.2, when no a.c. signal input is given, i.e. under d.c. conditions, VCC – VBE VCC IB = _________ ª ____ RB RB

(2.1)

2.3

Fig. 2.2 CE Amplifier with a single power supply

IC = b IB VCE = VCC – ICRC

(2.2) (2.3)

When a sinusoidal a.c. signal is applied at the input terminals of the circuit, during the positive half cycle the forward bias of the base-emitter junction VBE is increased, resulting in an increase in IB. The collector IC is increased by b times the increase in IB. From Eqn. 2.3, VCE is correspondingly decreased, i.e. the output voltage gets decreased as shown in Fig. 2.3.

Fig. 2.3 Input and output voltages of CE amplifier

Thus, in a CE amplifier, a positive going input signal is converted into a negative going output signal, i.e. a 180° phase shift is introduced between the output and input signal and further the output signal is an amplified version of the input signal.

2.4

Electronic Circuits I

Characteristics of CE amplifier (i) (ii) (iii) (iv) (v) (vi)

Large current gain (AI) Large voltage gain (AV) Large power gain (AP = AI ◊ AV) Voltage phase shift of 180° Moderate input impedance Moderate output impedance

EXAMPLE 2.1 For the circuit shown in Fig. 2.4 draw the dc circuit and find VCEQ, ICQ and hie. +20 V 10 KW = RL

RB = 1.8 MW

CL CL Re1 = 480 W

~

Re2 = 50 W

Fig. 2.4 Common emitter amplifier

Solution DC equivalent circuit I BQ = =

VCC - VBE RB + (1 + b )RE 20 - 0.7 6

1.8 ¥ 10 + (1 + 100) ¥ 1000

ICQ = b I BQ = 1.015 mA

I EQ = I BQ + ICQ = 1.025 mA I EQ = I BQ + ICQ = 1.025 mA VCEQ = VCC - IC RC - I E RE = 8.825 V hie = b re hie = 100 ¥ 25.362 = 2536.2 W

5 KW = RL

[AU Dec ’10, 6 marks]

2.5

EXAMPLE 2.2 For the same circuit shown in Fig. 2.4 draw the AC circuit and find AVC, Rin & RS. [AU Dec ’10, 10 marks]

Solution: Since hie & hfe are specified we use approximate analysis I Ai = - c = - h fe Current gain Ib Ri = hie + (1 + h fe )RE = 51K W

Input resistance

Avi =

Voltage gain

Ai RL¢ -100 * (10 K || 5 K) = = -6.536 Ri 51 KW

Rin = Ri RB = 51 K 1.8 KW = 49.59 KW RU = R1 = 10 K || 5 K = 3.33 KW RS = 0, AVS = AV = -6.536

EXAMPLE 2.3 Define h parameters of a CE transistor. A Transistor has following parameters hie = 800 W, hre = 10–4, hfe = 80, hoe = 10–7, for a load of 3K . Calculate the current gain ,voltage gain, power gain. [AU Dec’12, 16 marks]

Solution: Given data h fe = 80, hoe = 10 -7 , hre = 10 -4 , hie = 800, RL = 3 KW = 3 *103W (1)

Current gain Ai =

- h fe 1 + hoe RL

=

-80 1 + (1*10 -7 *3 *103 )

Ai = -79.976 A (2)

Voltage Gain Ri = hie + hre Ai RL = 800 + (1*10 -4 *( -79.976) *3 *103 ) Ri = 776W AV =

Ai RL -79.976 *3000 = Ri 776

AV = -309.186 V (3)

Power Gain Power gain = Av * Ai = -309.186 * -79.976 Power gain = 24727.4 W (or) 24.727 KWaH

2.6

Electronic Circuits I

Definitions of h-parameters of CE transistor: hie =

DVBE /VCE constant DI B

hre =

DVBE /I B constant DVCE

h fe =

DIC /VCE constant DI B

hoe =

DIC /I B constant DVC

2.2.2 Common Collector (CC) Amplifier Figure 2.5 shows the circuit of a single-stage CC amplifier using an NPN transistor. The emitter-base junction is forward biased by power supply VEE and collector-base junction is reverse biased by VCC, so that the transistor remains in the active region throughout its operation. Input signal is given to the base-collector circuit and the output signal is taken from the emittercollector circuit. C2

lE

Vout

C1

lB

Vin

RE lc

RB

+ + –

VCC

VEE –

Fig. 2.5 CC amplifier

Instead of using two power supplies, the required bias condition can be set up in a CC amplifier circuit with a single power supply as shown in Fig. 2.6. C1 and C2 are coupling capacitors to provide d.c. isolation at the input and output of the amplifier. From Fig. 2.6, Output voltage

Vo = IE RE = bIB RE

(2.4)

When a sinusoidal a.c. signal is applied at the input, during the positive half cycle of the signal applied, the base potential VB increases thereby increasing the base current IB. Hence, emitter current IE = IC + IB increases and voltage drop across RE, i.e. the output voltage increases. Thus, a positive going input signal results in a positive going output signal as shown in Fig. 2.7. Hence, in a CC amplifier, input and output signals are in phase with each other and further the voltage gain is approximately unity.

2.7

Fig. 2.6 CC amplifier with a single power supply

Fig. 2.7

Input and output voltages of CC amplifier

As the output signal taken at the emitter terminal almost follows the input signal, the CC amplifier is called as the Emitter Follower.

Characteristics of CC amplifier (i) High current gain (ii) Voltage gain of approximately unity (iii) Power gain approximately equal to current gain (iv) No current or voltage phase shift (v) Large input impedance (vi) Small output impedance.

2.8

Electronic Circuits I

2.2.3 Common Base (CB) Amplifier Figure 2.8 shows the circuit of a single stage CB amplifier using an NPN transistor. The emitter-base junction is forward biased by power supply VEE, whereas the collector-base junction is reverse biased by VCC, so that the transistor remains in the active region throughout its operation.

Fig. 2.8 Common base amplifier

Input signal applied to the emitter-base circuit and output signal is taken from collector-base circuit. The output voltage (= VCB) is given by the equation Vo = VCC – ICRC

(2.5)

When a sinusoidal a.c. signal is applied at the input, during the positive half cycle of the applied signal, the amount of forward bias to base-emitter junction is decreased, resulting in a decrease in IB. As a result IE (ª bIB) and hence, IC also decreases. From Eqn. (2.5), the drop ICRC decreases, hence Vo = VCB correspondingly increases. Thus, a positive half cycle appears at the output without any phase reversal as shown in Fig. 2.9.

Characteristics of CB amplifier (i) Current gain of less than unity (ii) High voltage gain (iii) Power gain approximately equal to voltage gain (iv) No phase shift for current or voltage (v) Small input impedance (vi) Large output impedance.

Fig. 2.9

Input and output voltage of CB amplifier

2.9

2.3 SMALL SIGNAL ANALYSIS OF SINGLE STAGE BJT AMPLIFIERS [AU May’10, 12 marks]

2.3.1 CE Amplifier with Fixed Bias The circuit of Fig. 2.10 shows a CE amplifier in fixed bias configuration. The a.c. equivalent circuit of the amplifier can be drawn by the steps mentioned as follows. (i) Remove the d.c. effects of power supply (VCC) by grounding them. (ii) Replace the capacitors (C1 and C2) by short circuits. Thus, the circuit of Fig. 2.10 reduces to the a.c. equivalent circuit of Fig. 2.11. Substituting the approximate hybrid model for the transistor in Fig. 2.11, the circuit reduces to that shown in Fig. 2.12. From the circuit of Fig. 2.12, the equations for input impedance, output impedance, voltage gain and current gain can be derived.

Fig. 2.11

Fig. 2.10 CE fixed bias configuration li

B

+

lc

lb

a.c. equivalent circuit of CE fixed bias amplifier

C

+

Io hfelb

Vi

RB

hie E



Zi

Vo

RC E

lL



Zo

Fig. 2.12 a.c. equivalent circuit of CE fixed bias amplifier using hybrid model

2.10

Electronic Circuits I

Input impedance Zi = RB || hie If

(2.6)

RB >> hie, Zi ª hie

(2.7)

Output impedance It is the impedance determined with Vi = 0. With Vi = 0, Ib = 0 and hfe Ib = 0 indicating an open circuit equivalence for the current source. Hence,

Voltage gain Voltage gain,

Zo = RL (= RC) Vo AV = ___ Vi Vo = – IoRC

Substituting

Io = hfe Ib Vo = –hfe IbRC

Assuming that

RB >> hie, Ii ª Ib and

Therefore,

Vi = Ib hie

– hfeIbRC AV = ________ Ib hie – hfeRC = _______ hie

(2.8)

As hfe and hie are positive, AV is negative. The negative sign indicates a 180° phase shift between input and output signals. IL Current gain AI = __ Ii – Io – hfeIb = ___ ª ______ = – hfe Ii Ib

(2.9)

Note: The sign for AI will be positive if AI is defined as the ratio of Io to Ii. Substituting the re model for the transistor in CE connection, the circuit of Fig. 2.11 reduces to that shown in Fig. 2.13.

Input impedance

Zi = RB || b re

If

RB >> b re Zi = b re

(2.10) (2.11)

Output impedance For similar reasons, Zo = RC

(2.12)

2.11 B

lb

C

+

+

Io blb

Vi

RB

E



Vo RL

bre

Zi



E Zo

Fig. 2.13 a.c. equivalent circuit of CE fixed bias amplifier using re model

Voltage gain

Vo AV = ___ Vi Vo = –IoRC Io = b Ib

Substituting

Vo = – (+ bIb)RC = – bIbRC RB >> b re

Assuming

Vi ª Ibb re – bIbRC AV = _______ Ibb re

Current gain

– RC = _____ re – I o AI = ____ Ii – Io = ____ Ib – bIb = _____ = –b Ib

(2.13)

(2.14)

EXAMPLE 2.4 Determine the input impedance, output impedance, voltage gain and current gain for the CE amplifier of Fig. 2.14. The h-parameters of the transistor of hfe = 60, hie = 500 at IC = 3 mA.

Solution

RB = 220 kW >> hie = 500 W

From h-parameter model Zi = hie = 500 W Zo = RC = 5.1 kW

2.12

Electronic Circuits I

– hfeRC – 60 (5.1 × 103) AV = ______ = _____________ 500 hie

12 V

= – 612 AI = – hfe = – 60 220 kW

5.1 kW 0.1 mF

From re model 26 mV Zi = b re where re = ______ Ie – V V CC BE From the circuit, Ib = _________ RB

Vo

0.1 mF

Vi

12 – 0.6 = _________3 = 51.8 mA 220 × 10

Fig. 2.14

Ie ª Ic = bIb = 60 × 51.8 × 10 –6 = 3.108 mA 26 × 10 –3 re = ___________ = 8.37 W 3.108 × 10 –3 Zi = b re = 60 × 8.37 = 502.2 W Zo = RC = 5.1 kW – RC AV = ____ re – (5.1 × 103) = ___________ = – 609 8.37 AI = – b = – 60 Note: Small differences in the calculation of amplifier parameters between the h-parameter and re models might arise due to the approximations made in the circuit design.

2.3.2 Common Emitter Amplifier with Emitter Resistor [AU Dec’09, 8 marks, AU Dec'14, 16 marks] A simple and effective way to provide voltage gain stabilisation in a CE amplifier is to add an emitter resistor RE which provides feedback as shown in Fig. 2.15. An approximate solution for this arrangement can be obtained by considering the simplified hybrid model equivalent circuit.

Current gain, AI Ic – hfe Ib AI = – __ = ______ = – hfe Ib Ib Thus, the current gain is equal to the short circuit current gain with RE = 0 and is unaffected by RE.

2.13 VCC

RL = (RC) Vo

C

B

lC

hie

C

B hfe lb

E E

Rs

Rs RE

RE

Vi +

+

Vs

RL Vc

(1 + hfe) lb

Vs –



Ri

N

(a)

Fig. 2.15

Input resistance, Ri

N (b)

(a) CE amplifier with emitter resistor (b) Approximate small-signal equivalent circuit

Vi [ hie + (1 + hfe) RE ]Ib Ri = __ = __________________ Ib Ib Ri = hie + (1 + hfe) RE

(2.15)

Comparing with Eqn. (9.38), the input resistance is augmented by (1 + hfe) RE and may be very much larger than hie. For example, with RE = 1 kW, hfe = 60, (1 + hfe) RE = 61 kW >> hie ª 1 kW. Hence, RE greatly increases the input resistance of the amplifier.

Voltage gain, AV From Eqn. (9.24), hfe RL RL AV = AI ___ = – _______________ Ri hie + (1 + hfe)

(2.16)

Thus, the addition of emitter resistor RE greatly reduces the voltage amplification as Ri has increased from hie to hie + (1 + hfe)RE. This reduction in gain is compensated by stability improvement. If (1 + hfe) RE >> hie and hfe >> 1 Then

hfe RL – RL AV ª – __________ ª _____ (1 + hfe) RE RE

(2.17)

2.14 Electronic Circuits I

Hence, under these approximations AV is completely stable and independent of all transistor parameters provided stable resistances are used for RL and RE.

Output resistance, Ro Output resistance Ro with RL excluded is infinite and with RL included, it is equal to RL and is independent of RE.

EXAMPLE 2.5 A CE amplifier uses load resistor RC = 2 k in the collector circuit and is given by the voltage source Vs of internal resistance 1000 . The h-parameters of the transistor are hie = 1300 , hre = 2 × 10–4, hfe = 55 and hoe = 22 mhos. Neglecting the biasing resistors, compute the current gain AI, input resistance Ri, voltage gain AV, output resistance Ro and output terminal resistance RoT for the following values of emitter resistor RE inserted in the emitter circuit: (i) 200 (ii) 400 and (iii) 1000 . Use the approximate model for the transistor if permissible.

Solution (i) For

RE = 200 W hoe × (RE + RC) = (2 × 103 + 200) × (22 × 10–6) = 0.0484

Since hoe × (RE + RC) < 0.1, the approximate model is permissible. AI = – hfe = –55 Ri = hie + (1 + hfe) RE = 12.5 kW RC AV = AI ___ 2000 = –55 × ______ = – 8.8 12,500 Output resistance, Ro = Output terminal resistance, ROT = Ro | | RC = 2 kW (ii) For RE = 400 W hoe × (RE + RC) = (2 × 103 + 400) × (22 × 10–6) = 0.0528 Since hoe × (RE + RC) < 0.1, approximate model is permissible. AI = – hfe = – 55 Ri = hie + (1 + hfe) RE = 23.7 kW RC AV = AI ___ Ri 2000 = – 55 × ______ = – 4.654 23,700 Output resistance, Ro = Output terminal resistance, ROT = Ro | | RC = 2 kW (iii) For

RE = 1000 W

Since hoe × (RE + RC) < 0.1, approximate model is permissible.

2.15

Al = –hfe = –55 Ri = hie + (1 + hfe) RE = 57.3 kW RC AV = AI ___ Ri 2000 = – 55 × ______ = –1.92 57,300 Output resistance, Ro = Output terminal resistance, ROT = Ro || RC = 2 kW

2.3.3 CE Amplifier with Unbypassed Emitter Resistor

[AU Dec’13, 16 marks]

The a.c. equivalent circuit for this amplifier shown in Fig. 2.16 can be drawn by following the steps mentioned earlier.

Fig. 2.16 CE amplifier with unbypassed emitter resistor

By substituting the hybrid equivalent circuit for the transistor of Fig. 2.17, the circuit reduces to that shown in Fig. 2.18.

Input impedance Current through the emitter resistor RE is Ie = Ib + hfe Ib = (1 + hfe)Ib From Fig. 2.18, Vi = Ibhie + (1 + hfe) IbRE Vi Zb = __ = hie + (1 + hfe)RE Ib

(2.18)

2.16

Electronic Circuits I

Fig. 2.17

Fig. 2.18

a.c. equivalent circuit for CE amplifier with unbypassed emitter resistor

a.c. equivalent circuit for CE amplifier with unbypassed emitter resistor using hybrid model

As hfe >> 1, Zb ª hie + hfeRE Normally,

(2.19)

hfeRE >> hie leading to Zb ª hfeRE

(2.20)

Zi = RB || Zb

(2.21)

From the circuit of Fig. 2.18,

Output impedance With Vi = 0, Ib = 0, hfeIb = 0 indicating open circuit for current source. Hence,

Zo = RC

Voltage gain

Vo AV = ___ Vi

From the circuit of Fig. 2.18, Vo = –IoRC

(2.22)

2.17

= – (hfeIb)RC

( )

Vi = – hfe ___ RC Zb Vo – hfeRC AV = ___ = ______ Vi Zb

(2.23)

Zb ª hfeRE,

With

– hfeRC AV = ______ hfeRE – RC = _____ RE

Current gain

(2.24)

– Io AI = ____ Ii Io = hfeIb

where

RB Ib = Ii ________ RB + Zb

Therefore,

RB Io = hfe Ii ________ RB + Zb – hfeRB – Io AI = ___ = ________ Ii RB + Zb

(2.25)

Substituting the RE model for the transistor of Fig. 2.17, the circuit reduces to that shown in Fig. 2.19.

Fig. 2.19

a.c. equivalent circuit for CE amplifier with unbypassed emitter resistor using re model

2.18 Electronic Circuits I

Input impedance

Vi = Ib(b re) + (1 + b ) IbRE Vi Zb = __ = bre + (1 + b ) RE Ib

As

b >> 1, Zb ª b (re + RE) ª b RE

(2.26)

Zi = RB || Zb

(2.27)

Output impedance For similar reasons, Zo = RC

Voltage gain

(2.28)

Vo AV = ___ Vi Vo = – IoRC = – b IbRC Vi = – b ___ RC Zb

Therefore, Substituting

Current gain

where Therefore,

Vo – bRC AV = ___ = _____ Vi Zb Zb ª bRE – RC AV = ____ RE Io AI = – __ Ii Io = b Ib

(2.29)

RB Ib = Ii ________ RB + Zb RB Io = bIi ________ RB + Zb – Io b RB AI = ___ = – ________ Ii RB + Zb

(2.30)

2.3.4 CE Amplifier with Voltage-Divider Bias Consider the CE amplifier of Fig. 2.20 in which the base bias is obtained by two resistors R1 and R2. By substituting the h-parameter equivalent for the transistor, the a.c. equivalent circuit can be obtained directly as shown in Fig. 2.21. As capacitor CE bypasses RE in the operating frequency range, RE is omitted in the equivalent circuit.

2.19

Fig. 2.20 CE amplifier with voltage-divider bias

Fig. 2.21

a.c. equivalent circuit of CE amplifier with voltage-divider bias using hybrid model

Input impedance R1R2 RB = R1 || R2 = _______ R1 + R2 Zi = RB || hie

(2.31)

Output impedance

Zo = RC

(2.32)

Voltage gain

Vo AV = ___ Vi

Substituting

Vo = – hfe Ib RC

Let

and Vi = Ib hie

2.20 Electronic Circuits I

– hfeIb RC AV = ________ Ib hie – hfeRC = ______ hie

(2.33)

Current gain

– Io AI = ___ Ii

Substituting

Io = – hfe Ib

where

RB Ib = Ii _______ RB + hie

Therefore,

RB Io = – hfe Ii _______ RB + hie

RB AI = – hfe _______ RB + hie Substituting the re model for the transistor, the a.c. equivalent circuit is as given in Fig. 2.22.

(2.34)

Input impedance Zi = RB || b re

(2.35)

lb

li +

lo Vi

R1

R2

bre

blb

RC

Vo



Zo

Zi

Fig. 2.22

a.c. equivalent circuit of CE amplifier with voltage-divider bias using re model

Output impedance

Zo = RC

Voltage gain

Vo AV = ___ Vi

where

Vo = – b IbRC Vi Ib = ____ b re

(2.36)

2.21

( )

Vi Vo = – b ____ RC b re

Therefore,

Vo – R C AV = ___ = ____ re Vi

(2.37)

– Io AI = ___ Ii

Current gain

From the circuit of Fig. 2.20, Io = – b Ib where

RB Ib = Ii ________ RB + b r e

Therefore,

RB Io = – b Ii ________ RB + bre Io RB AI = __ = – b ________ Ii RB + bre

(2.38)

EXAMPLE 2.6 Determine the input impedance, output impedance, voltage gain and current gain of the CE amplifier of Fig. 2.23 using h-parameter and re model equivalents for the transistor with hie = 3.2 k and hfe = 100 at the operating conditions. VCC = 16 V

RC 40 kW

4 kW

Vo 1 mF

1 mF

Vi

4.7 kW

R2

RE 1.2 kW

Fig. 2.23

Solution

h-Parameter analysis Zi = RB || hie RB = R1 || R2 = 40 kW || 4.7 kW = 4.2 kW

CE = 10 mF

2.22

Electronic Circuits I

Zi = 4.2 kW || 3.2 kW = 1.82 kW Zo = RC = 4 kW – hfeRC AV = ______ hie – 100 × 4 × 103 = _____________ = –125 3.2 × 103 – hfeRB AI = _______ RB + hie – 100 × 4.2 × 103 = _______________3 = –56.76 (4.2 + 3.2) × 10 Using re model To find IB, R2VCC VB = _______ R1 + R2 4.7 × 16 × 103 = _____________ = 1.682 V 44.7 × 103 Using Thevenin’s equivalent for input part, VB – VBE IB = ______________ RB + (1 + b) RE 1.682 – 0.6 = ____________________________ 3 4.2 × 10 + (1 + 100) (1.2 × 103) 1.082 = __________3 = 8.628 mA 125.4 × 10 IC = b IB = 100(8.628 × 10 –6) = 0.86 mA IE ª IC = 0.86 mA 26 mV 26 × 10 –3 re = ______ = __________ = 30.23 W IE 0.86 × 10 –3 Zi = RB ||b re = (4.2 × 103) || (100 × 30.23) = 4200 || 3023 = 1.76 kW

2.23

Zo = RC = 4 kW – RC AV = ____ re – 4000 = ______ = –132.3 30.23 – b RB AI = ________ RB + bre – 100 (4.2 × 103) = – 58.147 = _______________________ (4.2 × 103) + (100 × 30.23)

2.3.5 CB Amplifier Figure 2.24 shows the circuit of a CB amplifier. By applying the steps mentioned earlier to draw the a.c. equivalent circuit the circuit of Fig. 2.24 reduces to the circuit of Fig. 2.25.

Fig. 2.24 CB amplifier

Fig. 2.25

a.c. equivalent circuit of CB amplifier

Substituting the approximate hybrid model for the transistor in CB connection the circuit of Fig. 2.25 reduces to the circuit of Fig. 2.26.

Input impedance Output impedance Voltage gain

Zi = RE || hib Zo = RC Vo AV = ___ Vi Vo = – Io RC = – hfb Ie RC

(2.39) (2.40)

2.24

Electronic Circuits I

Fig. 2.26

a.c. equivalent circuit of CB amplifier using hybrid model

Assuming that RE >> hib, Ie ª Ii and Vi = Iehib Vo – hfb RC AV = ___ = _______ Vi hib – Io AI = ____ Ii – hfb Ie ª ______ Ie

Current gain

AI = – hfb Note:

(2.41)

(2.42)

As hfb is negative, AV and AI are positive for CB configuration.

For substituting the re model for the transistor, substitute hib = re and hfb = –1. Note the direction of IE reversed from the diagram of Fig. 2.26 and hence, the orientation of current source is also reversed. This results in the a.c. equivalent circuit for the CB amplifier using re model shown in Fig. 2.27.

Fig. 2.27

a.c. equivalent circuit for the CB amplifier using re model

2.25

Input impedance

Zi = RE || re

(2.43)

Output impedance

Zo = RC

(2.44)

Voltage gain

Vo – IoRC AV = ___ = ______ Vi Ie re (– Ie) RC = – ________ Ie re RC = ___ r

(2.45)

e

– Io (– IE) AI = ____ ª – _____ = 1 Ii IE

Current gain

(2.46)

EXAMPLE 2.7 Find the input impedance, output impedance, voltage gain and current gain for the CB circuit of Fig. 2.28. Assume VBE = 0.6 V.

Solution

VEE – VBE | IE | = _________ RE 8 – 0.6 = ______ = 1.85 mA 4000 26 mV re = ______ IE 26 = ____ = 14.05 W 1.85 Zi = RE || re Fig. 2.28

= 4000 || 14.05 = 14 W Zo = RC

VCC

= 3 kW RC _____ 3000 AV = ___ re = 14.05 = 213.52 AI = 1

2.3.6 CC Amplifier

R1 Rs

[AU Dec’09, 8 marks]

Figure 2.29 shows the Emitter Follower circuit in which the output is taken from the emitter terminal with respect to ground and the collector terminal is directly connected to VCC. Since VCC is at signal ground in the a.c. equivalent circuit as shown in Fig. 2.29, the emitter follower circuit is also called common collector amplifier.

CC Vo

Vs

+ –

R2

Fig. 2.29

RE

Emitter follower circuit

2.26 Electronic Circuits I

Current gain The small signal current gain, Ai, is defined as the ratio of output load current IL to input current Ib. IL Ie (1 + hfe)Ib Ai = __ = __ = _________ = 1 + hfe Ib Ib Ib where

Ie = –(1 + hfe)Ib

Input resistance From Fig. 2.30, the input resistance looking into the base is denoted as Ri, that is, Vb Ri = ___ = hie + (1 + hfe)RL Ib where

Vb = hie Ib + (1 + hfe)Ib RL

Therefore, the input resistance seen by the signal source R¢i is R¢i = Ri || R1 || R2 Ib

Ic

B

E

+

hie

IL

(1 + hfe)lb

Rs VI

+ Vc –

R1 || R2

hfe lb

RL



C R ¢i

C Ri

Ro

R o¢

Fig. 2.30 Simplified hybrid model for emitter follower circuit

Voltage gain The small signal voltage gain, AV, is defined as the ratio of output voltage, Vo, to input voltage, Vi. That is, Vo AiRL Ri – hie hie AV = ___ = _____ = ______ = 1 – ___ Vi Ri Ri Ri Therefore, AV ª 1 but always slightly less than one since Ri >> hie.

Output admittance From Fig. 2.30, the output admittance looking back into the emitter is denoted as Y0, that is, hfchrc Y0 = hoc – _______ hic + R¢S where

R¢s = Rs || R1 || R2

2.27

Neglecting hoc and assuming hrc = 1, hfc = – (1 + hfe), we get – hfc Y0 = _______ hic + R¢s – hic + R¢s hie + R¢s R0 = _________ = _______ hfc 1 + hfe Hence, the output resistance looking back into the output terminals, R¢o, is the load resistance, RL, in parallel with the resistance looking back into the emitter, Ro, that is, Therefore,

R¢o = Ro || RL The equations for input impedance, output impedance, voltage gain and current gain are given below: h-parameter model

re model

Zi = RB || Zb, where Zb = hie + hfe RE ª hfe RE

Zi = RB || Zb, where Zb = b (re + RE) ª b RE

hie Zo = RE || ______ 1 + hfe

bre Zo = RE || _____ 1+ b

RE AV = ____________ hie RE + ______ 1 + hfe

RE AV = _______ RE + re

(hfe) RB AI = ________ RB + Zb

bRB AI = ________ RB + Zb

[ ]

EXAMPLE 2.8 For the Emitter Follower shown in Fig. 2.29, the circuit parameters are Rs = 500 , R1 = R2 = 50 k , RL = 2 k , hfe = 100 and hie = 1.1 k . Determine the input resistance, output resistance, current gain and voltage gain.

Solution (a) To determine input resistance (Ri) Ri = hie + (1 + hfe)RL = 1.1 × 103 + (1 + 100) × 2 × 103 = 203.1 kW R¢i = Ri || R1 || R2 = 203.1 × 103 || 50 × 103 || 50 × 103 = 22.26 kW (b)To determine output resistance (R0) hie + R¢s 1.1 × 103 + (500 || 50 × 103 || 50 × 103) R0 = _______ = _________________________________ 1 + 100 1 + hfe 1.59 × 103 = _________ = 15.74 W 101 R¢o = Ro || RL = 15.74 || 2 × 103 = 15.62 W

2.28 Electronic Circuits I

(c) To determine current gain (Ai) Ai = 1 + hfe = 1 + 100 = 101 (d) To determine voltage gain (AV) hie 1.1 × 103 AV = 1 – ___ = 1 – __________3 = 0.9946 Ri 203.1 × 10

Example 2.9 Calculate the current gain AI, voltage gain AV, input resistance Ri and output resistance Ro for the common collector amplifier shown in Fig. 2.31. The transistor parameters are hic = 1.4 k , hfc = 100, hrc = 20 A/V and hoc = 20× 10–6. + VCC

R1

20 kW

C1 C2 Rs +

21 kW

R2

RE 20 kW

Vs

10 kW

RL 40 kW



Fig. 2.31

where

– hfc AI = _________ 1 + hoc R¢L R¢L = RE || RL = (40 || 10) kW = 8 kW – (–100) 100 A1 = _____________________ = ____ = 86.2 1 + (20) × 10–6 × 8 × 103 1.16

Input resistance

Ri = hic + hrcAIR¢L

Solution

Current gain

Voltage gain Output resistance,

where

= 1.4 × 103 + (1) (86.2) (8 × 103) = 691 kW AI R¢L _____________ (86.2)(8 × 103) _____ AV = = = 0.998 RI 691 × 103 1 Ro = ___ Yo hfc hrc Yo = hoc – _______ hic + R¢s R¢s = Rs || R1 || R2 = 1|| 20 || 20 kW = 0.9 kW

2.29

(– 100)(1) = 43478.26 × 106 Yo = 20 × 10–6 – _____________________ (1.4 × 103) + (0.9 × 103) Ro = 22.99 W R¢o = Ro || R¢L = (22.99) || (8 × 103) = 22.92 W

EXAMPLE 2.10 The common collector amplifier shown in Fig. 2.32 has VCC = 15 V, RB = 75 k and RE = 910 . The of the silicon transistor is 100. Find the input impedance of the amplifier stage (Zi) and voltage gain of the amplifier (AV). VCC = 15 V

75 KW

RB

Vo

+

Vs –

RE

910 W

Fig 2.32

Solution

We know that

Therefore,

VCC – VBE IB = ______________ RB + (1 + b) RE 15 – 0.7 = 85.7 mA IB = _____________________ 3 75 × 10 + (1 + 100) 910 IE = (1 + b)IB = 8.57 mA

The dynamic resistance is

0.026 0.026 re = _____ = __________ = 3.03 W IE 8.57 × 10–3 The input impedance of the amplifier is Zb = (1 + b)(re + RE) = 101 (3.03 + 910) = 92.2 kW [since hfc = 1 + hfe]

2.30

Electronic Circuits I

The input impedance of the amplifier stage is (75 × 103) (92.2 × 103) Zi = RB || Zb = ___________________ = 41.35 kW 75 × 103 + 92.2 × 103 The voltage gain of the amplifier is RE 910 AV = _______ = __________ = 0.997 re + RE 3.03 + 910

EXAMPLE 2.11 The common collector amplifier shown in Fig. 2.33 has VCC = 10 V, RB = 470 k and RE = 3.3 k . The of the silicon transistor is 100. Find the input impedance of the amplifier state (Zi) and overall voltage gain (VL/VS). VCC = 10 V

470 KW

Rs

RB

1 kW +

Vs

50 W

RE

RL

VL

3.3 kW –

Fig. 2.33

Solution

From Fig. 2.33,

VCC – VBE IB = ______________ RB + (1 + b) RE 10 – 0.7 = ________________________ = 11.58 mA 3 470 × 10 + 101 × 3.3 × 103 IE = (1 + b)IB = 101 × 11.58 × 10 – 6 = 1.16 mA

The load resistance of the emitter follower is rL = RE || RL = 3.3 kW || 50 W = 50 W Zi = RB || (1 + b)(re + rL) = 470 × 103 || (101)(22.4 + 50) = 7.13 kW

(

Zi VL ______ rL ___ = = _______ r + r Vs Rs + Zi e L

(

)

)

7.13 × 103 50 = __________ _________________ = 0.605 (22.4 + 50) 1 × 103 + 7.3 × 103

2.31

EXAMPLE 2.12 For the circuit shown in Fig 2.34, find the input impedance of the amplifier (Zb), input impedance of the amplifier stage Zi, voltage gain of the amplifier (AV), load voltage VL and load current iL, overall voltage gain (VL/Vs), and overall current gain iL is. VL

Rs

Vs

RE

500 ‡

Ro

2 k‡

1 k‡

4 k‡

+ 10 mV –

RL

(rms) –6V

6V

Fig. 2.34

Solution Therefore,

We know that

VEE – VBE IE = _________ RE 6 – 0.7 IE = _______3 = 2.65 mA 2 × 10 0.026 Zb = re = __________ = 9.81 W 2.65 × 10–3 Zi = re || RE = 9.81 W || 2 kW = 9.76 W RC _____ 1000 AV = ___ re = 9.81 = 101.9 re VL RL ___ = AV ______ ________ Vs re + Rs RL + RC

)(

(

(

9.81 = 101.9 _________ 9.81 + 50 Therefore,

)

4 × 10 ) ( _______________ ) = 13.37 4 × 10 + 1 × 10 3

3

3

VL = 13.37 ◊ Vs = 13.37 × 10 mV (rms) = 133.7 mV (rms) VL 133.7 × 10–3 iL = ___ = ___________ = 33.4 mA (rms) RL 4 × 103

(

Rs iL __ = a ______ iS Rs + re

(

)(

50 = 1 _________ 50 + 9.81

RC ________ RC + RL

)

1 × 10 ) ( ________________ ) = 0.167 1 × 10 + 4 × 10 3

3

3

2.32

Electronic Circuits I

EXAMPLE 2.13

()

( )

VL iL Find the voltage gain of the amplifier AV, overall voltage gain ___ and overall current gain __ of the comVs iS mon base amplifier as shown in Fig. 2.35. Assume the transistor used is Germanium.

Solution

The emitter current of the common base amplifier is

VEE – VBE 24 – 0.3 IE = _________ = ________3 = 1.077 × 10–3 A RE 22 × 10

– 24 V

VL RC

0.026 0.026 re = _____ = ___________ = 24.14 W IE 1.077 × 10–3

12 kW 15 kW

RC AV = ___ re = 497

RL

(

) ( ________ R +R )

(

)(

re VL ___ = AV ______ Vs re + Rs

RL

L

24.14 = 497 __________ 24.14 + 10

(

Rs iL __ = Ai ______ iS Rs + re

)(

10 W

C

)

15 × 103 _________________ = 195.156 12 × 103 + 15 × 103

Rs 22 kW

+

Vs

RE –

)

RC ________ = 0.444 RC + RL

+ 24 V

Fig. 2.35

EXAMPLE 2.14 The silicon transistor in the amplifier stage shown in Fig. 2.36 has a collector resistance of rc = 1.5 M . Find (i) the input resistance of the amplifier stage, (ii) the output resistance of the amplifier stage, and (iii) the rms load voltage VL. +9V

–9V

RE

4.7 kW

2.2 kW Ro

VL Rs

20 W

RL +

Vs

20 mV (rms) –

Fig. 2.36

10 kW

2.33

Solution VEE – VBE 9 – 0.7 IE = _________ = ________3 = 1.765 mA RE 4.7 × 10

We know that

0.026 re = _____ = 14.7 W IE Zi = RE || re = 4.7 kW || 14.7 W = 14.6 W Zo = RC || rc = 2.2 kW || 1.5 MW Zo RC || rc AV = ___ = ______ = 149.5 Zi RE || re

(

Zi VL ___ = AV _______ Vs Rs + Zi Therefore,

)(

)

RL ________ = 51.9 RL + Zo

VL(rms) = 51.9 × Vs (rms) = 1.038 V(rms)

EXAMPLE 2.15 Find the input impedance of the amplifier stage (Zi) and overall voltage gain (VL/Vs) for each of the amplifier shown in Fig. 2.37. Assume = 100. + 10 V

RC 3.3 kW

27 kW R1

Rs +

600 W

R2 4.7 kW

Vs

10 V

RE

R1 27 kW 3.3 kW 600 W

+ RL VL 15 kW –

+

Vs

680 W



+ VL 15 kW –

4.7 k

R2

680 W



(a)

(b)

Fig. 2.37

Solution

Referring to Fig 2.37 (a), we get R2 4.7 × 103 × 10 VB = _______ VCC = __________________ = 1.39 V R1 + R2 27 × 103 + 4.7 × 103 VE = (1.39 – 0.7) = 0.69 V VE 0.69 IE = ___ = ____ = 1 mA RE 680 0.026 re = _____ = 26 W IE

2.34

Electronic Circuits I

Zi = R1 || R2 || b (re + RE) = 3.79 kW

(

RC VL The overall voltage gain is ___ = – _______ Vs RE + re Referring to Fig 2.37(b)

)(

Zi _______ Rs + Zi

)(

)

RL ________ = – 3.3 RC + RL

Zi = R1 || R2 || bre = 1.58 kW Z R ________ = – 74.9 ( ) ( _______ R + Z ) (R + R )

RC VL ___ = – ___ re Vs

i

s

L

i

C

L

2.4 AC LOAD LINE After drawing the d.c. load line, the operating point Q is properly located at the center of the d.c. load line. This operating point is chosen under zero input signal condition of the circuit. Hence, the a.c. load line should also pass through the operating point Q. The effective a.c. load resistance, Ra.c., is the com1 bination of RC parallel to RL, i.e. Ra.c. = RC || RL. So the slope of the a.c. load line CQD will be – ____ . Ra.c.

(

)

To draw an a.c. load line, two end points, viz. maximum VCE and maximum IC when the signal is applied are required. Maximum VCE = VCEQ + ICQ Ra.c., which locates the point D (0D) on the VCE axis.

IC 3.5 mA

C

VCEQ Maximum IC = ICQ + _____, which locates the point C (0C ) Ra.c. on the IC axis.

3 mA

A

By joining points C and D, a.c. load line CD is constructed.

1.5 mA

Q

As RC > Ra.c., the d.c. load line is less steep than the a.c. load line. When the signal is zero, we have the exact d.c. conditions. From Fig. 2.38, it is clear that the intersection of d.c. and a.c. load lines is the operating point Q.

D 0

12 V

B 21 V 24 V

VCE

Fig. 2.38 CE output characteristics and load line

2.5 VOLTAGE SWING LIMITATIONS In a linear amplifier, symmetrical sinusoidal signals at the input gets amplified as sinusoidal signal at the output, without any clipping. The maximum output symmetrical swing provided by the amplifier can be obtained from the ac load line. Output signal will be clipped if it exceeds this limit, resulting in signal distortion.

EXAMPLE 2.16 Determine the maximum voltage swing at the output of common emitter amplifier in which quiescent point is ICQ = 0.9 mA and VCEQ = 9V. The ac resistance seen at the output terminal Rac (RC || RL) = 2K .

Solution The maximum symmetrical peak to peak AC collector current is DiC = 2ICQ = 2 ¥ 0.9 mA = 1.8 mA

2.35

The maximum symmetrical peak to peak output voltage is |DvEC | = |DiC |Rac = 1.8 ¥ 10–3 ¥ 2 ¥ 10–3 = 3.6 V

2.6

DIFFERENTIAL AMPLIFIER [AU Dec’10, 16 marks, AU Dec'13, 16 marks, AU May'14, 6 marks, AU May'10, 12 marks]

The differential amplifiers using BJT are broadly classified into two types namely (i) differential BJT amplifier with resistive loading and (ii) differential BJT amplifier with active loading.

Differential BJT amplifier with resistive load The emitter coupled or source coupled differential amplifier forms the input stage of most analog ICs. The Emitter-coupled differential amplifier circuit is shown in Fig. 2.39. It is important to note that the performance of a differential amplifier depends on the ideal matching of the transistor pair, Q1 and Q2.

Fig. 2.39 Circuit diagram of emitter-coupled differential amplifier

The amplifier uses both a positive power supply +VCC and a negative power supply –VEE. Though in practical situations the power supplies are equal in magnitude, it need not be the case always. It is to be mentioned that these amplifiers operate even at d.c., because appropriate d.c. level shifting could be obtained without the use of coupling capacitors.

d.c. analysis of an emitter coupled pair The d.c. analysis begins with the assumption that Q1 and Q2 are ideally matched, and the mismatching effects will be considered later. Here, we consider b >>1 so that – iE1 ª iC1 and hence

and –iE2 ª iC2

VI1 = VBE1 – VBE2 + VI2

2.36

Electronic Circuits I

In the d.c. analysis, the operating point values i.e. ICQ and VCEQ can be obtained for Q1 and Q2. The d.c. equivalent circuit can be derived by making a.c. inputs zero as shown in Fig. 2.40.

Fig. 2.40 d.c. equivalent circuit

For matched transistor pairs, we have RE1 = RE2, RE = RE1||RE2 RC1 = RC2 = RC VCC| = |VEE| For a symmetrical circuit with matched transistors, IC1Q = IC 2Q and VCE1Q = VCE2Q. Hence it is enough finding out operating point ICQ and VCEQ for any one of the two transistors. Any symmetrical circuit as shown in Fig. 2.41 will be suitable for a.c.-analysis. + VCC

+ VCC

RC

RC Vo

Vo

Q1 Rs

Q1 Rs

lb

lb

+ 2RE

Vs1

Vs 2

+ –



– VEE

Fig. 2.41

– VEE

Emitter-coupled pair (a) for Ac analysis and (b) for Ad analysis

2.37

Consider Fig. 2.40 for the d.c. analysis. Applying KVL to base-emitter loop of Q, we get IBRs + VBE + 2IERE = VEE

Therefore,

IC IE As b = __ for common emitter and IC ª IE, b = __ IB IB IE __ R + VBE + 2IERE = VEE b s

[

]

Rs IE ___ + 2 RE = VEE – VBE b VEE – VBE IE = __________ Rs ___ + 2RE b

(

)

Rs In practical conditions, ___ > 1 (typical value of m = 50) Fig. 3.6

rd 1 ___ Zo ª __ m || Rs = gm || Rs

EXAMPLE 3.3 In the CD amplifier of Fig. 3.6(b), let Rs = 4 k , RG = 10 M , gain AV, Input Impedance Zi and Output Impedance Zo.

Soution

= 50, and rd = 35 k . Evaluate the voltage

The voltage gain, Vo mRs AV = ___ = _____________ Vi (m + 1) Rs + rd 50 × 4 × 103 = _________________________ = 0.836 (50 + 1) × 4 × 103 + 35 × 103

The positive value indicates that Vo and Vi are in-phase and further note that AV < 1 for CD amplifier. Input Impedance Output Impedance

Zi = RG = 10 MW 1 Zo = ___ gm || Rs rd = __ m || Rs

( )

35 × 103 Zo = ________ || 4 × 103 = 595.7 W 50

3.2.3 Common Gate (CG) Amplifier A simple common-gate amplifier is shown in Fig. 3.7(a) and the associated small signal equivalent circuit using the current-source model of FET is shown in Fig. 3.7(b).

Voltage gain From the small signal equivalent circuit by applying KCL, ir = id – gm Vgs. Applying KVL around the outer loop gives Vo = (id – gmVgs) rd + Vgs

3.7

Fig. 3.7

– Vo Vsg = –Vgs = Vi and id = ____ RD – V o Vo = ____ + gmVi rd + Vi RD

But

(

Thus,

)

Hence, the voltage gain, Vo (gmrd + 1) RD AV = ___ = ____________ Vi RD + rd

(3.12)

Input impedance Figure 3.7(b) is modified for calculation of input impedance as shown in Fig. 3.7(c). Current through rd is given by Ird = –Ir = I1 + gmVgs I1 = Ird – gmVgs where

Vi – Vo Ird = _______ r d

Vi – IRD RD = __________ r

Fig. 3.7

d

Hence

Vi – IRD RD I1 = __________ – gmVgs r d

From Fig. 3.7(c), Vi = –Vgs Vi – IRD RD I1 = __________ + gmVi r d

Vi ______ IRDRD = __ + gmVi r – r d

d

3.8

Vi IRDRD __ I1 + ______ rd = rd + gmVi From Fig. 3.7(c), I1 = IRD

[

] [

rd + RD 1 I1 _______ = Vi __ rd rd + gm

Therefore,

]

Vi ________ rd + RD __ = = Zi¢ I1 1 + gm rd From Fig. 3.7(c), Zi = Rs || Zi¢ rd + RD = Rs || ________ 1 + gm rd In practice rd >>RD and gmrd >> 1 Therefore,

rd Zi = Rs || ____ gm rd

Therefore,

1 Zi = Rs || ___ g m

Output impedance It is the impedance seen from the output, terminals with input short circuited.

rd

From Fig. 3.7(c), when Vi = 0, Vsg = 0, the resultant equivalent circuit is shown in Fig. 3.7(d).

RD

Zo

Zo = rd || RD as

rd >> RD Zo ª RD

Fig. 3.7

EXAMPLE 3.4 In the CG amplifier of Fig. 3.7(b), let RD = 2 k , Rs = 1 k , gm = 1.43 × 10–3 mho, and rd = 35 k . Evaluate the voltage gain AV, input impedance Zi and output impedance Zo.

Solution

The voltage gain, Vo (gmrd + 1) RD AV = ___ = ____________ Vi RD + rd (1.43 × 10 – 3 × 35 × 103 + 1) 2 × 103 = _______________________________ = 2.75 2 × 103 + 35 × 103

3.9

Input Impedance

1 Zi = Rs || ___ g m

103 = 1 × 103 || ___ 1.4 = 0.41 kW Output Impedance

Zo ª RD = 2 kW

3.4 SMALL SIGNAL ANALYSIS OF MOSFET AMPLIFIER AC equivalent circuit for the NMOS amplifier circuit can be developed from small signal equivalent circuit for the transistor We assume that the signal frequency is sufficiently low so that any capacitance at the gate terminal can be neglected. The input to the gate thus appears as an open circuit, or an infinite resistance. Equations 1 relate the small signal drain current to the small signal input voltage, and equation 1 shows that the transconductance gm is a function of the Q point. The resulting simplified small signal equivalent circuit for the NMOS device is shown in Fig. 3.8. id = gmvgs

(3.13)

Fig. 3.8

This the finite output resistance of a MOSFET biased in the saturation region, as a result of the non zero slope in the iD versus vDS curve, can also be included in small signal equivalent circuit. We know that iD = K n [(vGs -VTN )2 (1 + lvDS )]

(3.14)

where l is the channel length modulation parameter and is a positive quantity the small signal output resistance, as previously defined, is Ê ∂i ˆ ro = Á D ˜ Ë ∂vDS ¯

-1

(3.15) vGS =VGSQ = Const.

ro = [ l K n (VGSQ - VTN )]-1 @ [ l I DQ ]-1 This small signal output resistance is also a function of the Q point parameters

(3.16)

3.10

The expanded small signal equivalent circuit of the n channel MOSFET is shown in Fig. 3.9 in phasor notation. This equivalent circuit is that of a transconductance amplifier in that the input signal is a voltage and output signal is a current. This equivalent circuit is inserted into the amplifier ac equivalent circuit in Fig. 3.8 to produce the circuit in Fig. 3.10.

Fig. 3.9

V From Fig 3.10 Voltage gain AV = o = - g m ( roRD ) Vi

MOSFET AC Analysis For linear amplifiers, superposition applies, so that dc and ac analyses can be done separately. The analysis of the MOSFET Amplifier proceeds as follows: 1. Analyze the circuit with only the dc sources present. This solution is the dc or quiescent solution. The transistor must be biased in the saturation region in order to produce a linear amplifier 2. Replace each element in the circuit with its small signal model, which means replacing the transistor by its small signal equivalent circuit 3. Analyse the small signal equivalent circuit setting dc source components equal to zero, to produce the response of the circuit to the time varying input

Fig. 3.10

The previous discussion was for an n channel MOSFET amplifier. The same basic analysis and equivalent circuit also applies to the p-channel device. Figure 3.11(a) shows a circuit containing a p channel MOSFET. Note that the Fig 3.11 power supply voltage VDD is connected to the source. Also note the change in current directions and voltage polarities compared to the circuit containing the NMOS transistor. Figure 3.11(b) shows the ac equivalent circuit with the dc voltage sources replaced by ac short circuits, all currents and voltages shown are the time varying components. The circuit of Fig. 3.12 for p channel MOSFET is the same as that of the n channel device, except that all current directions and voltage polarities are reversed. The final small signal equivalent circuit of the p channel MOSFET amplifier is shown in Fig. 3.13.

Fig 3.12

Fig. 3.13

3.11

The output voltage is Vo = gmVsg(ro||RD) The control voltage Vsg, given in terms of the input signal voltage, is Vsg = –Vi And the small signal voltage gain is Av =

Vo = - g m ( roRD ) Vi

This expression for the small signal voltage gain of the p channel MOSFET amplifier is exactly the same as that for the n channel MOSFET amplifier. The negative sign indicates that a 180 degree phase reversal between the output and input signals, for both PMOS and the NMOS circuit If the polarity of voltage and currents in the small signal equivalent circuit of the PMOS device is made exactly identical to that of the NMOS device, the equivalent circuit is the same as that of the NMOS transistor as shown in Fig 3.14.

Fig 3.14

3.5 COMPARISON OF FET MODEL WITH h The h-parameter model of a BJT in CE configuration is redrawn in Fig. 3.15 for comparison. B

lB

hie

lc

C +

+

+

Vb

hreVc

hfelb –

hoe

Vc





E

E

Fig. 3.15

3.12

Comparing circuits of Figs 3.4 and 3.15, the BJT also has a Norton’s output circuit, but the current generated depends on the input current and not on the input voltage as in FET. There is no feedback from output to input in the FET, whereas a feedback exist in the BJT through the parameter hre. The high (almost infinite) input resistance of the FET is replaced by an input resistance of about 1 kW for a CE amplifier.

Due to the high input impedance and the absence of feedback from output to input, FET is a much more ideal amplifier than the BJT at low frequencies. This becomes invalid beyond the audio range as the low frequency model of FET shown in Fig. 3.4 is not valid in the high frequency range.

Two basic amplifier design technologies are: (1) The bipolar technology, which uses npn and pnp bipolar junction transistors; (2) The MOS technology, that uses NMOS and PMOS field-effect transistors. Bipolar transistors have a larger transconductance than MOSFETs biased at the same current levels, and have larger voltage gains. MOSFET circuits have infinite input impedance at low frequencies, which implies a zero input bias current. These advantages of the two technologies can be combined by combining bipolar and MOS transistors in the same integrated circuit. Such a technology is called BiCMOS. BiCMOS technology is not only useful in digital circuit design, but also has applications in analog circuits. In this section, basic BiC-MOS analog circuit configurations are studied.

A bipolar multitransistor circuit is the Darlington pair configuration. A modified Darlington pair configuration is shown in Fig 3.16(a). The bias current Ibias is used to control the quiescent current in Q1. This Darlington pair circuit is used to improve the effective current gain of bipolar transistors. Equivalent FET circuits are not available. A BiCMOS circuit in which transistor Q1 in the Darlington pair is replaced with a MOSFET is shown in Fig 3.16(b). Infinite input resistance, due to MOSFET M1 and large transconductance due to bipolar transistor Q2 are the twin advantages.

Fig. 3.16

3.13

The small-signal equivalent circuit of Fig. 3.17 is used to analyze the BiCMOS Circuit Assume r0 =

in both MOSFET and BJT.

Using KCL output signal current is Io = gm1Vgs + gm2Vp

(3.17)

Vi = Vgs + Vp

(3.18)

where and Vp is the voltage drop across rp Hence

Vp = gm1Vgsrp

(3.19)

Fig. 3.17

Substituting equation 3.20 in 3.19 gives Vi = Vgs + gm1Vgsrp Hence

Vgs =

Vi 1 + g m1rp

(3.20)

Substituting equation 3.20 in equation 3.21 the output current becomes Io = gm1Vgs + gm2(gm1rp)Vgs = (gm1 + gm2gm1rp)Vgs

(3.21)

Substituting for Vgs from equation 3.22 into 3.23 we get Io =

g m1 (1 + g m 2 rp ) c ◊ Vi = g m ◊ Vi (1 + g m1rp )

c where gm is the composite transconductance. Since gm2 of the bipolar transistor is usually at least an order of magnitude greater than gm1 of the MOSFET, the composite transconductance is roughly an order of magnitude larger than the transconductance of the MOSFET alone. The resulting advantages are large transconductance and an infinite input resistance.

Figure 3.18(a) shows a basic bipolar cascode circuit. A corresponding BiCMOS configuration is shown in Fig. 3.18(b). The cascode circuit offers very high output resistance and the BiCMOS cascode amplifier offers wider frequency bandwidth than the common-emitter circuit, since the input resistance looking into the emitter of Q2 is very low. The advantage of the BiCMOS circuit is the infinite input resistance of M1.

Fig 3.18

3.14

The equivalent resistance looking into the emitter of a bipolar transistor is much less than the resistance looking into the source of a MOSFET; resulting in superior frequency response of a BiCMOS cascode circuit compared to that of all-MOSFET cascode circuit.

Biasing in integrated-circuit design is based on the use of constantcurrent sources. On an IC chip with a number of amplifier stages, a constant dc current (called a reference current) is generated at one location and is then replicated at various other locations for biasing the various amplifier stages through a process known as current steering. This is discussed in elaborate in chapter 5. The cascode current sources increase the output resistance, as well as the stability of the bias current. A BiCMOS double cascode constant-current source is shown in Fig. 3.19. The small-signal equivalent circuit for determining output resistance is shown in Fig. 3.20(a). The gate voltage to M6 and the base voltages to Q2 and Q4 are constants, equivalent to signal ground. As Vp2 = 0, then gm6Vp2 = 0, and the equivalent circuit can be rearranged as shown in Fig. 3.20(b).

Fig 3.20

Fig 3.19

3.15

The output resistance of this circuit is very high. Analysis shows that the output resistance is given approximately by Ro = (gm6ro6) (bro4) The output resistance is increased by a factor (gmro6) compared to the bipolar cascode circuit.

1. Draw the high frequency equivalent circuit of FET. G

D Cgd

gmVgs

Cgs

rd

Cds

S

S

2. Draw the small signal equivalent circuit of FET. id

G +

D +

rd

G +

id

D

+



Vgs

gmVgs

rd

Vds

Vgs

Vds

mVgs +









S

S

(a)

(b)

3. Give two advantages of common source FET amplifier? a. Good voltage gain b. High input impedance. 4. What is the use of source bypass capacitor in CS amplifier? Source bypass capacitor in CS amplifier is used for improving the voltage gain. 5. Draw the the circuit of Common source NMOS transistor with small signal parameters and Draw a Simplified small signal equivalent circuit for NMOS Transistor.

3.16 6. Draw the Small Signal equivalent circuit of PMOS Transistor.

7. Draw the Bipolar Darlington pair configuration.

1. Draw the small signal model of FET for low frequency and high frequency regions and compare them with the BJT models. 2. Draw the small signal equivalent circuit of FET amplifier in CS connection and derive the equations for voltage gain, Input impedance and Output Impedance. 3. In the CS amplifier of Fig. 3.5(a), let RD = 4 kW, R = 50 MW, m = 40, d = 40 kW. Evaluate AV, Zi and Z . [ AV = –3.64, Zi = 50 MW Z = 4 kW] 4. Draw the small signal equivalent circuit of FET amplifier in CD connection and derive the equation for voltage gain, Input impedance and Output impedance. 5. In the CD amplifier of Fig. 3.6(a), let R = 2 kW, R = 10 MW, m = 40, d = 40 kW. Calculate A , Zi and Z . [ AV = 0.66, Zi = 10 MW Z = 0.67 KW] 6. Draw the small signal equivalent circuit of FET amplifier in CG connection and derive the equation for voltage gain, Input impedance and Output impedance. 7. In the CG amplifier of Fig. 3.7(b), let RD = 4 kW, R = 2 kW, m = 2 × 10–3 mho, d = 40 kW. Calculate AV, Zi and Z . [ AV = 7.36, Zi = 0.4 kW, Z = 4 kW] 8. Draw and Explain the NMOS Common gate amplifier 9. Draw and explain the small signal equivalent circuit of MOSFET 10. What do you mean by BiCMOS technology? 11. Draw the BiCMOS Darlington pair configuration and derive the expression for Transconductance. 12. Draw the circuit diagram for BiCMOS double cascode constant current source and mention its advantages.

4 4.1

FREQUENCY ANALYSIS OF BJT AND MOSFET AMPLIFIERS

4.1

INTRODUCTION

The gain factors such as voltage, current, transconductance and transresistance of amplifiers are functions of signal frequency. In the amplifier gain versus frequency plot, the gain factor is plotted in terms of decibels and frequency in terms of Hertz on logarithmic scales. The main purpose is to determine the frequency response of amplifier circuits due to circuit capacitors and transistor capacitances. The frequency response will be useful to determine bandwidth of the circuit. The transfer function is derived by using the complex frequencys, of several passive circuits. With the help of Bode plots of the transfer function, the magnitude response, phase response, time constant and 3 dB cutoff frequencies are calculated. In this chapter, the frequency responses of transistor circuits including BJTs and FETs are studied. The effects due to circuit capacitors including coupling, bypass, and load capacitors and internal transistor capacitances are analysed. The RF amplifier and video amplifier circuits used in high frequency applications are discussed.

4.2

LOGARITHMS

The analysis of amplifiers normally extends over a wide frequency range. Use of logarithmic scale makes it comfortable plotting the response between wide limits. Logarithm taken to the base 10 is common logarithm. For example, logarithm of a variable “a” is log10 a. Logarithm taken to the base “e” is natural logarithm. For example, logarithm of a variable “a” is loge a. Common logarithm

:

u = log10 a

Natural logarithm

:

v = loge a

Natural logarithm can be written as ln a(= loge a). Numerically e = 2.71828 and loge a = 2.3 log10 a. In amplifier analysis, a frequency of 10,000 Hz becomes log10 104 = 4 log10 10 = 4 in logarithmic scale. Thus the frequency plot is compressed without major class of information and the problem of dealing with huge numbers is overcome.

4.2 Electronic Circuits I

In a semilog graph shown in Fig. 4.1 (a), only one of the two scales is a log-scale. In a double log graph shown in Fig. 4.1 (b), both the scales are log scales. Figure 4.2 indicates how a linear scale is converted into a log scale. Thus logarithmic scale helps to explain variations of parameters over a wide range by a simple graph. N

log10 10,000 = 4

log10 100,000 = 5

Linear scale

log10 1000 = 3

(b)

N

log10 100 = 2

Log scale

(a)

N 100

log10 10 = 1

Log scale

N 10

log10 1 = 0

Log scale

Linear scale

N 1

1000 10,000 100,000

0

1

2

3

4

5

Log scale

Fig. 4.1 (a) Semi log graph; (b) Double log graph

Fig. 4.2 Conversion from linear scale to logarithmic scale

Common mathematical equations 1. If a = b u, then u = logb a For example, if log10 1 = y, then 1 = 10y. Hence y = 0. u 2. log10 _v_ = log10 u – log10 v 3. log10 uv = log10 u + log10 v Table 4.1 clearly shows how the logarithm of number increases only as the exponent of the number. Table 4.1 Increase in the logarithm of a number log10 100 = 0 × log10 10 = 0 log10 101 = 1 × log10 10 = 1 log10 102 = 2 × log10 10 = 2 log10 103 = 3 × log10 10 = 3

and so on.

4.3

DECIBELS

Decibel is used to compare two power levels on a logarithmic basis. The term “bel” is derived from the name of telephone invention, Alexander Graham Bell. The unit “bel” (B) is defined relating two power levels P1 and P2 as P2 G = log10 ___ bel P1

( )

As “bel” was found to be a large unit for measurement, the “decibel” (dB) is defined where 10 decibels = 1 bel.

4.3

Hence,

( )

P2 GdB = 10 log10 ___ dB P1 The above equations indicate that dB is a measure of difference in magnitude between two power levels, say output power level and input power level (or some reference level). Quite often the input power level (or reference power level) is taken as 1 milliwatt in electronics. Then “decibel” symbol can be written as dBm, where P2 GdBm = 10 log10 ______ dBm 1 mW V21 V22 In terms of voltage P1 = ___ and P2 = ___ where Ri is input resistance of the system, where output Ri Ro resistance Ro is assumed to be equal to input resistance. V22/Ri P2 Hence, GdB = 10 log10 ___ = 10 log10 _____ P1 V21/Ri V2 2 = 10 log10 ___ V1

( ) ( )

V2 GdB = 20 log10 ___ dB V1 The advantage of logarithmic relationship is that the overall gain of a cascaded system is simply the sum of individual gains. Overall gain for a “n” stage system shown in Fig. 4.3 is given by G = G1 × G2 × G3 × ... × Gn – 1 × Gn

V1

1

V2

Vn – 1 n – 1

Fig. 4.3

V3

2

Vn

n

3

Vo/p

n-stage cascaded system

Vo/p Vo/p Vn V2 V3 V4 ____ = ___ × ___ × ___ × ... × ____ × ____ V1 V1 V2 V3 Vn – 1 Vn In logarithmic relationship

( )

Vo/p V3 V2 V4 GdB = 20 log10 ____ = 20 log10 ___ + 20 log10 ___ + 20 log10 ___ + º + V1 V1 V2 V3

( )

( )

( )

Vo/p Vn 20 log10 ____ + 20 log10 ____ Vn–1 Vn

( )

where

GdB = G1 + G2 + G3 + ... + Gn – 1 + Gn

and G1, G2, G3, … are voltage gains of stages 1, 2, 3, … respectively in decibels.

EXAMPLE 4.1 Calculate the magnitude gain corresponding to a voltage gain of 200 dB.

( )

Solution log10

V2 GdB = 20 log10 ___ = 200 dB V1 V ___2 = 10 V1

( )

( )

V4

4.4

Electronic Circuits I

V2 Gain = ___ = 1010 V1

EXAMPLE 4.2 A three-stage amplifier has a first stage-voltage gain of 30, second stage voltage gain of 200 and third stage gain of 400. Find the total voltage gain in dB.

Solution

First-stage voltage gain in dB, G1 = 20 log10 30 = 20 × 1.477 = 29.54

Second-stage voltage gain in dB, G2 = 20 log10 200 = 20 × 2.3 = 46 Third-stage voltage gain in dB, G3 = 20 log10 400 = 20 × 2.6 = 52 Therefore, the total voltage gain G = G1 + G2 + G3 = 29.54 + 46 + 52 = 127.54 dB

EXAMPLE 4.3 (a) A multistage amplifier employs five stages each of which has a power gain of 30. What is the total gain of the amplifier in dB? (b) If a negative feedback of 20 dB is employed, find the resultant gain.

Solution

Given, the gain of each stage = 30 and number of stages = 5

(a) Power gain of one stage = 10 log10 30 = 10 × 1.477 = 14.77 dB Total power gain = 5 × 14.77 = 73.85 dB (b) The resultant power gain with negative feedback = 73.85 – 20 = 63.85 dB

EXAMPLE 4.4 In an amplifier, the output power is 1.5 W at 2 kHz and 0.3 W at 20 Hz, while the input power is constant at 10 mW. Determine by how many decibels is the gain at 20 Hz below that at 2 kHz?

Solution

To determine power gain at 2 kHz

At 2 kHz, the output power is 1.5 W and input power is 10 mW. 1.5 Therefore, power gain in dB = 10 log10 ________ = 10 log10 150 = 21.76 10 × 10 – 3 To determine power gain in dB at 20 Hz At 20 Hz, the output power is 0.3 W and input power is 10 mW. 0.3 Therefore, power gain in dB = 10 log10 ________ = 10 log10 30 = 14.77 10 × 10 – 3 Fall in gain from 2 kHz to 20 Hz = 21.76 – 14.77 = 6.99 dB

4.5

EXAMPLE 4.5 An amplifier has a voltage gain of 15 dB. If the input signal voltage is 0.8 V, determine the output voltage.

Solution

Voltage gain in

dB = 20 log10 V2/V1

Therefore,

15 = 20 log10 V2/V1 15/20 = log10 V2/V1 0.75 = log10 V2/0.8

Taking antilogarithm, we get 100.75 = V2/0.8 V2 = 100.75 × 0.8 = 4.5 V

Hence,

4.4 GENERAL SHAPE OF FREQUENCY RESPONSE OF AMPLIFIERS The response of any single-stage (or) Multistage network is highly influenced by the frequency of the applied signal. At low frequencies, the effect of capacitors (coupling and bypass) cannot be neglected due to their high value of capacitive reactance under these conditions. Moreover, any fluctuations in the number of stages of a cascaded system will also affect the frequency response of that system. While plotting the frequency response of a circuit, it is conventional to use a logarithmic scale along the X-axis (horizontal axis), so as to permit a plot extending from low to the high frequency regions. In general, any frequency response curve can be splitted into three regions, namely. (a) Low frequency region (b) Mid frequency region and (c) High frequency region In general, the frequency response curve is a plot between magnitudes of gain and logarithmic frequencies. A typical frequency response curve of an RC-coupled amplifier is shown in Fig. 4.4. AV mid = Vout Vin

Bandwidth

AV mid 1 A 2 V mid Mid frequency region Low frequency region 10

f1 100

1000

10,000

100k

High frequency region

f2 1M 10M

Freq. (log scale)

Fig. 4.4 Gain vs frequency (logarithmic scale) of RC-coupled amplifier

The main reason for the drop in gain at the low frequency region and the high frequency is due to the increase in capacitive reactance in the low frequency region and due to the parasitic capacitive elements (or) the frequency dependence of the network’s gain on the active devices, in the high frequency region.

4.6

Electronic Circuits I

1__ The frequency boundaries of relatively high gain region is determined by choosing “___ AV mid” to be ÷2 the gain at the cut off levels. The frequencies corresponding to such values ( f1 and f2) are called cut-off frequencies (or) band frequencies (or) corner frequencies (or) half power frequencies. At cut-off frequencies, the output power is half the mid band power output. |V2out| Pout ( mid) = _____ Ro V out | Av | mid = ____ Vin

but Therefore,

(4.1)

| |

(4.2)

| AV mid Vin |2 Pout = ___________ Ro

(4.3)

at half power frequencies, f1 and f2 (Ref Fig. 4.1)

| 0.707 AV mid Vin |2 | AV mid Vin |2 Pout HPF = ________________ = 0.5 ___________ Ro Ro Comparing Eqs (4.1) and (4.4)

(4.4)

Pout HPF = 0.5 Pout (mid)

(4.5)

The bandwidth of each system is hence given by Bandwidth = f2 – f1

(4.6)

However, in most applications it is preferrable to have the plot of gains in (dB) and it is also conventional to use a normalized plot for such analysis as shown in Fig. 4.5. A normalized plot is a plot of gain Vs log frequencies, with the gain values divided by the gain in the mid frequency ranges (i.e., the maximum gain) AV AV mid

Normalized gain 1 0.707 × 1

f1 10

f2 100

1000

10,000

100k

f (log scale) 1M 10M

Fig. 4.5 Normalized plot for Fig. 4.4

A decibel plot can now be obtained by using the following transformation AV AV ______ = 20 log10 ______ AV mid dB AV mid

|

Hence, the gain at half power point becomes 1__ 20 log10 ___ = – 3 dB. ÷2

( )

The plot is as shown in Fig. 4.6.

(4.7)

4.7

AV AV mid

0 dB

10

f1

100

1000

10k

100k

f21M 10M

f (log)

dB

–3 –6 –9 – 12

Fig. 4.6

Note:

4.5

Decibel plot of the normalized gain versus frequency (logarithmic) of Fig. 4.6

Figs. (4.3 to 4.7), do not consider the 180° phase shift introduced by an RC coupled amplifier.

LOW FREQUENCY

The cut-off frequencies of single stage BJT/FET amplifiers are influenced by the RC combinations formed by the network capacitors CC, CE, etc. and the resistive parameters that are present in the network. For the purpose of analysis, each capacitive element can be modelled as one shown in Fig. 4.7 and its frequency response can be studied. Once the cut-off frequencies due to individual capacitors are studied, they can be compared to establish, which will determine the cut-off frequency (lower cut-off) for the system.

+

+

C Vin

R



Fig. 4.7

Vout –

Equivalent circuit for lower cut-off frequency analysis

In this section, a methodology for determining the lower cut-off frequency ( f1) will be presented. However, a straight forward mechanism can be employed to find the Upper cut-off frequency ( f2), with some extension in the frequency response region f1 and f2 are also referred to as a and b cut-off frequencies. It is to be recalled that 1 XC = ____ ª 0 W 2pfc

at High frequencies

1 XC = ____ ª W 2pfc Figure 4.7 can hence be approximated as shown in Fig. 4.8 and Fig. 4.9 for very high frequencies and at Low frequencies

very low frequencies respectively A typical frequency response between the above two extremes is as shown. Short +

Vin –

+

R

+

Vin

Vout –

Fig. 4.8 At Very high frequencies

+



R

Vout –

Fig. 4.9 At Very low frequencies

4.8

Electronic Circuits I

Applying the voltage divider rule in Fig. 4.7 RVin Vout = _______ R – jXC where, magnitude of Vout is given by RVin ________ |Vout | = _________ 2 2 ÷R + XC Case: When

(4.8)

(4.9)

XC = R RVin _______ |Vout | = _________ ÷R2 + R2 1__ |Vout | = ___ Vin ÷2

(4.10)

From Eq. (4.2),

1

Vout Vin 1__ ___ | AV | = ____ = ___ = 0.707 at XC = R Vin ÷2 Vin

(4.11)

AV = Vout/Vin

0.707

which is shown in Fig. 4.10. Now, as per the assumption

Therefore,

f (log)

f1

XC = R 1 ______ =R 2pf1C

Fig. 4.10 Av vs frequency of a typical RC network

1 f1 = ______ 2pRC

(4.12)

In terms of dBs, 0.707 corresponds to 3 dB from Eq. (4.8) Vout R AV = ____ = _______ Vin R – jXC

(4.13)

R 1 1 AV = ________ = ___________ = ____________ R – jXC 1 – j(XC /R) 1 1 – j ______ 2pfCR Substituting Eq. (4.12) into Eq. (4.14), we get

(

)

1 AV = _________ 1 – j(f1/ ) When

(4.14)

(4.15)

f = f1 1__ 1 _______ = ___ |AV | = ________ = 0.707, that corresponds to (–3 dB) 2 2 ÷ ÷1 + (1)

(4.16)

In general, “AV” can be written in magnitude and phase form. Vout __________ tan–1(f1/f ) ____ AV = = _________ Vin 1 + (f /f )2

÷

1

(4.17)

4.9

In the logarithmic form (dB), 1 _________ |AV | dB = 20 log10 __________ ÷1 + (f1/f)2

(4.18)

[ ( )]

f1 = – 10 log10 1 + __ f

2

(4.19)

If f1 >> f, ( f1/f )2 >> 1, 2

()

f1 |AV|dB = – 10 log10 __ f

(4.20)

f1 = – 20 log10 __ f Equation (4.20) can be used to find the future decibel plots, by ignoring the condition f > f1 a straight line is obtained only for the “0 dB” value, and hence it could be said that sloped line for such low frequency response can be obtained only when f > 1 Rs + hie

If

(1 + hfe) RE __________ Rs + hie fp ª __________ 2p CE RE

then

(4.29)

From Eqs (4.28) and (4.29) fp >> fo. AV(LF) If ______ at f = fp is considered, AV(MF)

f __p 1 + j AV(LF) fo Rs + hie ______ = __________ × _______ AV(MF) (1 + hfe) RE 1 + j1 fp j __ fo Rs + hie ª __________ × ______ 1 + j1 (1 + hfe) RE

The magnitude of this ratio is

|

AV(LF) Rs + hie ______ = __________ × __ AV(MF) (1 + hfe) RE ÷2 (1 + hfe) RE f __p ª __________ fo Rs + hie

But

Therefore,

|

f __p fo ___

|

|

AV(LF) 1__ ______ = ___ AV(MF) ÷2

(4.30)

1__ As the ratio of voltage gain has dropped by ___ , the power gain at this low frequency will be having a 2 ÷ 1_ _ drop of or 3 dB form the gain at mid frequency. 2

4.14 Electronic Circuits I

Thus, the lower 3 dB frequency is (1 + hfe) RE 1 + __________ Rs + hie f1 ª fp = ______________ 2p CERE (1 + hfe) RE ª ________________ (Rs + hie) 2p CERE (1 + hfe) = _____________ (Rs + hie) 2pCE

(4.31)

when fp = fo. If this condition is not met, f1 π fp and there may not be a 3-dB point. From Eq. (4.31), 1 + hfe CE = ____________ 2pf1 (Rs + hie)

(4.32)

Thus CE determines the lower 3-dB frequency f1. Further, the equation for f1 does not include RE so that the choice of CE for a given f1 is dependent only upon the transistor and the source resistance. Note: (i) The use of electrolytic capacitors for CE cause reduction in the lower 3-dB frequency and the mid frequency gain. If RCE represents the series resistance of CE, – hfe RL AV(MF) = ____________________ Rs + hie + (1 + hfe) RCE (ii) If the effect of biasing resistors R1 and R2 are taken into account, – hfe RL AV(MF) = ______________ hfe Rs Rs + hie + _____ RB where

(4.33)

(4.34)

RB = R1 || R2.

EXAMPLE 4.7 For the CE amplifier in Fig. 4.14, calculate the mid frequency voltage gain and lower 3-dB point. The transistor has h-parameters of hfe = 400 and hie = 10 k . The circuit details are Rs = 600 , RL = 5 k , RE = 1 k , VCC = 12 V, R1 = 15 k , R2 = 2.2 k and CE = 50 F.

Solution

– hfe RL AV(MF) = ______________ hfe Rs Rs + hie + _____ RB – 400 × 5 × 103 = ________________________________ = – 145.69 400 × 600 600 + 10 × 103 + _________________ 15 × 103 || 2.2 × 103

4.15

Lower 3-dB point, (1 + hfe) f1 = _____________ (Rs + hie) 2pCE 1 + 400 = ______________________________ (600 + 10 × 103) × 2p × 50 × 10 – 6 = 120 Hz

4.6

MILLER EFFECT

Miller’s theorem Miller’s theorem states that if an impedance Z is connected between the input and output terminals of a network which provides a voltage gain A, an equivalent circuit that gives the Z same effect can be drawn by removing Z and connecting an impedance Zi = _____ across the input and 1–A Z ZA Zo = _____ = _____ across the output as shown in Fig. 4.16. 1 A –1 1 – __ A

Fig. 4.16 Miller's theorem

Miller effect capacitance In inverting amplifiers, the capacitive element, Cf, is connected between input and output terminals of 1 the active device i.e., XC = _____. The large capacitors will control the low-frequency response due to f jw Cf their low reactance levels. Therefore, the Miller effect input capacitance CMi, is derived as Z Zi = ______ (1 – A) i.e. Therefore,

1 1 ______ = ___________ jw CMi jw Cf (1 – A) CMi = (1 – A)Cf.

Hence, it is evident that, in any inverting amplifier, the input capacitance will be increased by a Miller effect capacitance sensitive to the gain of the amplifier and the interelectrode capacitance, Cf, between the input and output terminals of the active device.

4.16

Electronic Circuits I

The Miller output capacitance, CMo is derived as Z Zo = _______ 1 1 – __ A

(

i.e.

Therefore, If

)

1 1 ______ = ____________ jw CMo 1 jw Cf 1 – __ A

(

(

)

)

1 CMo = 1 – __ Cf A A >> 1, CMo = Cf.

Dual of Miller’s theorem Dual of Miller’s theorem states that if an impedance Z connected as shunt element between input and output terminals, as shown in Fig. 4.17(a) can be replaced by an imped(AI – 1) 1 ance Zi = Z(1 – AI) at the input side and Z0 = Z 1 – ___ = Z _______ at the output side as shown in AI AI I__2 Fig. 4.17(b), where the current ratio, AI = . This can be verified by finding that the voltage across Zi I1 is I1Zi which is equal to the voltage drop (I1 + I2)Z across Z if Zi = Z(1 – AI). Hence the input voltage

(

)

Vi is the same in the two circuits in Fig. 4.17(a) and (b). Similarly the voltage V2 has the same value in the two circuits if the impedance Zo =

[

]

A______ I – 1 Z. AI

Therefore, the two networks are identical. This transformation is useful in the analysis of electric circuits.

Fig. 4.17

Dual of Miller's theorem

4.17

4.7

HIGH FREQUENCY ANALYSIS OF CE

4.7.1

[AU Dec’14, 16 marks]

High Frequency Model for a Transistor [AU Dec’10, 4 marks, AU Dec’13, 8 marks, AU May’14, 8 marks]

At high frequencies, the capacitive effects of the transistor junctions and the delay in response of the transistor caused by the process of diffusion of carriers should be taken into account in determining the high frequency model of a transistor. A high frequency-p or Giacoletto model for a transistor is shown in Fig. 4.18. rbb¢ —base spreading resistance between the actual base B and virtual base B¢. It represents the bulk resistance of the base. Its typical value is 100 W. rb¢e —resistance between the virtual base B¢ and the emitter terminal E. Typical value is 1 kW.

rb¢c rbb¢

Cb¢c



B

rb¢e

C

rce

Vb¢e

gm Vb¢e

Cb¢e E

E (a)

Fig. 4.18

(a) Hybrid p model for a transistor in the CE connection (b) Diagram showing virtual base B¢ and ohmic base-spreading resistance rbb¢

Input resistance from base to emitter with the output shorted is simply rbb¢ + rb¢e and this is the same as hie. Hence, hie = rbb¢ + rb¢e. rb¢c —resistance between the virtual base B¢ and the collector terminal C. It has a large value (typical value = 4 MW). Cb¢e — diffusion capacitance of the normally forward biased base-emitter junction. It has a typical value of 100 pF. Cb¢c — transistor capacitance of the normally reverse biased collector-base junction. It has a typical value of 3 pF. rce — output resistance with a typical value of 80 kW. Since rce >> RL, if a load RL is connected rce can be neglected. gmVb¢e — output current generator value where gm is the transconductance of the transistor.

4.18 Electronic Circuits I

4.7.2

Hybrid- Conductances

The hybrid p model for the CE transistor at low frequencies is shown in Fig. 4.19(a). The h-parameter model for the same is shown in Fig. 4.19(b). As the hybrid model is drawn for low frequencies, the capacitive elements are considered as open circuit. rbb¢

lb

B

lc

rbb =1/gb¢c



C

+

Vbe

rb¢e = 1/gb¢e

Vb¢e

rb¢e = 1/gb¢e

gmVb¢e

Vce



E

E

Fig. 4.19 (a) Hybrid-p model for a common-emitter transistor at low frequency

Base spreading resistance (rbb¢) In the circuit shown in Fig. 4.19(b), the value of input resistance is equal to hie when the output terminals are short circuited, i.e. Vce = 0. Under these conditions for the circuit in Fig. 4.19(a), the input resistance is given by

Ib

ic

B

C +

hie

+ Vbs hreVce

hfe Ib

hoe

Vce



Zi |V

ce

Therefore

=0

= rbb¢ + rb¢e || rb¢c E

hie = rbb¢ + rb¢e || rb¢c

As rb¢c >> rb¢e, the above equation can be written as hie = rbb¢ + rb¢e



Fig. 4.19

E

(b) h-parameter model for a common-emitter transistor at low frequency

Conductance between terminals B ¢ and C or the feedback conductance (gb¢c ) In the circuit shown in Fig. 4.19(b), if the input terminals are open-circuited, then the reverse voltage gain hre can be written in terms of the circuit in Fig. 4.19(a), and it is given by Vb¢e rb¢e hre = ____ = ________ Vce rb¢e + rb¢c Rearranging the above equation, we get rb¢e (1 – hre) = hre rb¢c As the value of hre is in the range of 10 – 4, the above equation can be approximated by rb¢e = hre rb¢c or

gb¢c = hre gb¢e

The equation also shows that the value of resistance rb¢c is much larger than resistance (rb¢e), i.e., rb¢c >> rb¢e.

Conductance between terminals C and E (gce) In the circuit shown in Fig. 4.19(b), if the input terminals are open circuited, then Vb¢e = hre Vce

4.19

For the circuit in Fig. 4.19(a), with the input terminals open, i.e, Ib = 0, then the collector current Ic is given by Vce ________ Vce Ic = ___ rce + rb¢e + rb¢c + gm Vb¢e The value of output admittance hoe is given by

|

Ic gm Vb¢e 1 1 hoe = ___ = ___ + ________ + ______ Vce Ib = 0 rce rb¢e + rb¢c Vce Substituting the value of Vbe in the above equation, we get Assuming that rb¢c >> rb¢e, the above equation can be rewritten in terms of conductance as gb¢c hoe = gce + gb¢c + gm ___ gb¢e Substituting gm = hfe gb¢e in the equation, we get hoe = gce + gb¢c + gb¢c hfe Rearranging the terms in the above equation, we get gce = hoe – (1 + hfe) gb¢c Since hfe >> 1, the above equation can be written as gce @ hoe – hfe gb¢c @ hoe – gm hre

Conductance between terminals B¢ and E or the input conductance (gb¢e) As the value of rb¢c is much greater than rb¢e, most of the current Ib flow through rb¢e in the circuit shown in Fig. 4.19(b) and the value of Vb¢e is given by Vb¢e @ Ib rb¢e The short-circuit collector current, Ic, is given by Ic = gm Vb¢e @ gm Ib rb¢e The short-circuit current gain, hfe is defined as Ic hfe = __ = gm rb¢e Ib Vce

|

Rearranging the above equation, we get gm rb¢e = hfe or gb¢e ___ hfe Transistor’s transconductance (gm) The transconductance of a transistor (gm) is defined as the ratio of change in Ic to change in Vb¢e for constant value of collector-emitter voltage. For common-emitter transistor configuration, the expression for collector current is given by Ic = ICO + a Ie The value of gm is given by

Ic gm = ____ Vb¢e

|

Ie Ie = constant = a ____ = a ___ V Ve VCE b¢e

4.20 Electronic Circuits I

(

)

Ve The partial derivative emitter voltage with respect to the emitter current i.e., ___ can be represented Ie as the emitter diode (re) and the dynamic resistance of a forward-biased (rd) is given as VT rd = ___ ID where VT is the volt equivalent of temperature and ID is the diode current. Therefore, the value of gm can be generalized as aIe Ic – ICO gm = ___ = _______ VT VT As Ic >> ICO, the value of gm for a NPN transistor is positive. For a PNP transistor, the analysis can be carried out on similar lines and the value of gm in the case of a PNP transistor is also positive. Therefore, the above expression for gm is written as |Ic| gm = ___ VT

4.7.3

Hybrid-p Capacitances

In the hybrid p model shown in Fig. 4.19(b), there are two capacitances namely the collector-junction barrier capacitance (Cc) and the emitter-junction diffusion capacitance (Ce).

Collector-junction capacitance (Cc) The capacitance Cc is the output capacitance of the commonbase transistor configuration with the input open (Ie = 0). As the collector-base junction is reverse-biased, Cc is the transition capacitance and it varies as (VCB)–n, where n is 1/2 for abrupt junction and 1/3 for a graded junction.

Emitter-junction capacitance (Ce) The capacitance Ce is the diffusion capacitance of the forwardbiased emitter junction and is proportional to the emitter current Ie and is almost independent of temperature. For a given collector current, the conductances and resistances of the hybrid p circuit calculated from the low frequency h-parameter values from the equations are given in Table 4.2. Table 4.2 Relationship between Low Frequency h-Parameters and High Frequency Parameters (i)

| | gm = ___ VT T where VT = ______ with T in K. At room temperature (300 K), VT = 0.026 V so that 11,600 IC (in mA) gm = _________ 26 mV

(ii)

hfe rb¢e = ___ gm

(iii)

rbb¢ = hie – rb¢e

(iv)

rb¢e 1 ___ rb¢c = ___ gb¢c = h re

(v)

gce

1 = ___ rce = hoe – (1 + hfe) gb¢c

4.21

EXAMPLE 4.8 A BJT has hie = 6 k and hfe = 224 at IC = 1 mA, with fT = 80 MHz and Cb¢c = 12 pF. Determine (a) gm (b)rb¢e (c) rbb¢ and (d) cb¢e at room temperature and a collector current of 1 mA. Determine the parameters, gm, rb¢e rbb¢ and Cb¢e of the small signal high frequency model of the BJT.

Solution IC (mA) 1 gm = _______ = ___ = 38.46 m mho 26 mV 26 hfe 224 ___________ rb¢e = ___ gm = 38.46 × 10 – 3 = 5.824 kW rbb¢ = hie – rb¢e = 6000 – 5824 = 176 W gm Cb¢e = ____ – Cb¢c 2p fT 38.46 × 10 – 3 = ____________6 – 12 × 10 – 12 2p × 80 × 10 = 76.5 × 10 – 12 – 12 × 10 – 12 = 64.5 pF

EXAMPLE 4.9 A certain BJT transistor has rp = 2 k and of fT, f and C .

Solution

We know that

= 100 at 1 MHz and

= 5 at 20 MHz. Determine the values

fT = bfb = bf f fT = 5 × 20 × 106 = 100 MHz

or

fT 100 × 106 fb = __ = _________ = 1 MHz 100 b We know that

1 fb = _______ 2pCp rp 1 1 × 106 = _____________3 2pCp × 2 × 10

Hence,

4.8

1 Cp = ____________________ = 80 2p × 2 × 103 × 1 × 106

HIGH FREQUENCY MOSFET MODEL

In the high frequency model of FET, the capacitances between nodes have to be added in the low frequency model. The resulting equivalent circuit is shown in Fig. 4.20. Cgs represents the barrier capacitance between gate and source. Cgd is the barrier capacitance between gate and drain. Cds is the drain to source capacitance of the channel. These interval capacitances leads to feedback from output to input and the voltage amplification decreases at higher frequencies.

4.22 Electronic Circuits I Cgd G

D Cds

rd

gm Vgs

Cgs

S

S

Fig. 4.20 The high frequency model of FET

The parameters of FET shown in Fig. 4.20 will have their magnitudes as given in Table 4.3. Table 4.3 Parameter Values of FET Parameter Range

4.8.1

rd

gm 0.1 – 10 mA/V

0.1 – 1 MW

Cgs , Cgd

cds 0.1 – 1 pF

rgs

rgd

8

>108 W

>10 W

1 – 10 pF

MOSFET CS Amplifier

The circuit of Fig. 4.21 shows the CS amplifier. The equivalent circuit at high frequencies is shown in Fig. 4.22. Cgd + VDD ZL

D G + –

Vi

G

+

+

Vi –

Vo S



Fig. 4.21 CS amplifier circuit

D +

Cgs

Cds

gmVi

rd

ZL

Vo

– S

S

Fig. 4.22 Small signal equivalent circuit of CS amplifier at high frequencies

The Norton’s equivalent circuit between D & S can be obtained by finding the short circuit current from D to S and impedance Z seen from output point with independent voltage sources short circuited and independent current sources open circuited. With Vi = 0, current gmvi = 0, the circuit of Fig. 4.22 reduces to circuit of Fig. 4.23.

D

Cgd

Hence admittance at the output point 1 Y = __ = YL + gd + Yds + Ygd Z

Cds

rd

ZL

Z

S

Fig. 4.23

Equivalent circuit to find Z

(4.35)

4.23

Where

1 YL = ___ is admittance corresponding to ZL ZL

Cgd D

1 gd = __ rd is conductance corresponding to rd

+

Vi

gmVi

I



Yds = jw Cds is admittance corresponding to Cds

S

Ygd = jw Cgd is admittance corresponding to Cgd. Fig. 4.24

The equivalent circuit to find the short circuit current from D to S is shown in Fig. 4.24. Hence, current

I = –gmVi + ViYgd

Equivalent circuit to find I

(4.36)

Voltage gain AV Voltage gain (amplification) AV with load ZL included is given by Vo IZ I AV = ___ = ___ = ____ Vi Vi Vi Y

From Eqs (4.35) and (4.36), – gm + Ygd AV = _________________ YL + gd + Yds + Ygd

(4.37)

At low frequencies, FET capacitances can be neglected and hence, Yds = Ygd = 0 Eq. (4.37) at low frequencies reduces to – gm – gm AV = ________ = _______ YL + gd ___ 1 1 + __ ZL rd – gm rd ZL AV = _________ = – gm Z¢L rd + ZL where

(4.38)

Z¢L = ZL || rd

Input admittance From Fig. 4.22, it is found that the Gate circuit is not isolated from drain circuit, but connected by Cgd . According to Miller’s theorem, an impedance Z ¢ connected between two points (1) & (2) of a circuit Z¢AV Z¢ can be replaced by Z1 = ______ from (1) to Ground and Z2 = _______ from (2) to Ground, where AV is 1 – AV AV – 1 the voltage gain V2 /V1. Applying Miller’s theorem to circuit of Fig. 4.22 the circuit of Fig. 4.25 is obtained, where capacitances are replaced by equivalent admittances. Hence the input admittance is given by Yi = Ygs + (1 – AV)Ygd

(4.39)

As Ygs = jwCds and Ygd = jw Cgd for an FET to possess negligible input admittance over a wide range of frequencies, the gate-source and gate-drain capacitances must be negligible.

4.24 Electronic Circuits I D

G Cds ZL

+

Vi –

Ygs

Ygd (1 – AV)

Ygd

1 1– A V

gmVi

rd

S

S

Fig. 4.25 CS amplifier equivalent circuit after applying Miller's theorem

Input capacitance (Miller effect) From Eq. (4.38), the voltage gain AV = – gm Z¢L where Z¢L = ZL || rd . For an FET with drain-circuit resistance Rd, the voltage gain AV = – gmR¢d where R¢d = Rd || rd. From Eq. (4.39) Yi = Ygs + (1 + gm R¢d) Ygd Yi = jw Cgs + (1 + gm R¢d) jw Cgd Yi ___ = Ci = Cgs + (1 + gm R¢d) Cgd jw

(4.40)

The increase in input capacitance Ci over the capacitance from gate to source is the Miller effect. In multistage (cascaded amplifiers) this input capacitance appears in shunt with output impedance of previous stage. As capacitive reactance decrease with increase in frequency, the resultant output impedance will be lower at higher frequencies, thereby reducing the gain.

Output admittance The output impedance for the CS amplifier of Fig. 4.23 is obtained by setting input voltage Vi = 0 and looking from the output point. The resulting Cgd equivalent circuit is shown in Fig. 4.26.

rd

The output admittance with ZL considered external to CS amplifier circuit is given by Yo = gd + Yds + Ygd

(4.41)

Cds

Fig. 4.26

Zo =

1 Yo

Calculation of output impedance

CURRENT GAIN The transistor’s high frequency capability can be known, if its CE short-circuit forward-current transfer ratio or current gain is found as a function of frequency. As RL is short circuited the approximate high frequency model becomes as shown in Fig. 4.27, where Cb¢e is in parallel with Cb¢c. The short circuit current gain is given by IL Ai = __ Ii From circuit of Fig. 4.27,

4.25 rbb¢

B

C +

rb¢e

Cb¢e + Cb¢c

Ii

Vb¢e

gm Vb¢e

IL



E

E

Fig. 4.27

Approximate high frequency circuit for determination of short circuit current gain

IL = – gmVb¢e Vb¢e Ii = _________ rb¢e || – jXC Vb¢e = _________________ –j rb¢e || ____________ w (Cb¢e + Cb¢c) Vb¢e _____ – jrb¢e ____________ w (Cb¢e + Cb¢c) = _________________ j rb¢e – ____________ w (Cb¢e + Cb¢c) Vb¢e _________ – j(rb¢e)2 fb _________ f = __________ jrb¢e fb rb¢e – ______ f

[

1 Let fb = ________________ 2p rb¢e (Cb¢e + Cb¢c)

Vb¢e = _______ – jrb¢e fb _______ f – j fb Current gain,

– gm Vb¢e jgmrb¢e fb AI = ________ = ________ Vb¢e f – j fb _______ –jrb¢e fb _______ f – j fb

]

4.26 Electronic Circuits I

jhfe fb = ______ f – j fb hfe fb = ________ – ( fb + jf) – hfe AI = _______ f 1 + j ___

(4.42)

b

where

1 fb = _______________ is the b cut-off frequency. 2prb¢e(Cb¢e + Cb¢c)

(4.43)

fa AND fb UNITY GAIN 4.10.1

Cut-off Frequency

The b cut-off frequency fb , also referred to as fhfe, is the CE short-circuit small signal forward-currenttransfer-ratio cut-off frequency. fb is the frequency at which a transistor’s CE short-circuit current gain drops 3-dB from its value at lower (mid) frequencies. fb represents the maximum attainable band width for the current gain of a CE amplifier with a given transistor.

4.10.2

Cut-Off Frequency

A CB amplifier has a much higher 3 dB frequency than a CE amplifier. The short-circuit current gain for CB amplifier which can be derived from the approximate high frequency circuit of the CB amplifier with output shorted is given by – hfb IL Ai = __ = _________ (4.44) Ii f __ 1+j fa

()

Where

hfe 1 fa = ________________ ª ________ 2prb¢e(1 + hfb) Cb¢e 2prb¢eCb¢e

(4.45)

Substituting Eq. (4.43) in Eq. (4.45), hfe fb (Cb¢e + Cb¢c) fa = _______________ Cb¢e

(4.46)

fa a’ (alpha) cut-off frequency at which the CB short-circuit small signal forward-current transfer ratio (Ai) drops 3 dB from its value at low frequencies (ª 1 kHz). Figure 4.28 shows the variation of Ai with frequency for CE and CB amplifiers and fa and fb

4.27 Ai 100 b (Common-emitter)

hfe 0.707 hfe 10

b cut-off Gain-bandwidth product

1 hfb hfb

0.707

a Cut-off a (Common base)

0.1 10

2

10

3

4

10

10

5

10

6

fT

10

7

fa

10

8

Frequency in Hz

Fig. 4.28 Variation of Ai with frequency for CE and CB amplifiers

EXAMPLE 4.10 For the Circuit shown in Fig. 4.29 find cut off frequencies due to C1, C2, C3 due to interelectrode capacitor Cgs and Cgd [AU Dec’10, 16 marks] Given gm = 0.49 mA/V Cgd = 9.38 pf Cgs = 1.8 pf rd = 40 K +VDD 2.3 MV

RD = 22 KV

1800 pF

C2 = 15 mF

C1

Vs

RL = 10 KV 1.5 MV

RS = 12 K

Fig. 4.29

Solution Cut off frequency due to C1 fC = 1/2pRinC1

CS = 56 mF

4.28 Electronic Circuits I

Assuming R in gate >> 0.908M fC = 97.378 Hz Cut off frequency due to C2 fC = 1/2p(RD + RL)C2 fC = 0.33 Hz Cut off frequency due to CS

Ê È 1 ˘ˆ fS = 1 / 2p Á RS Í ˙˜ CS Ë Î g m ˚¯ = 1.629 Hz

Cut off frequency due to interelectrode capacitors Cgs and Cgd AV = –gmRL¢ = –gm(RD||RL) = –3.369 Cin miller = Cgd(AV + 1) = 40.98 pF fC(input) =

1 ¥ [C gs + Cin miller ] 2p RS

= 310026 Hz Cout miller = Cgd(AV + 1)/AV = 12.116 pF fC(output) =

4.11

1 1 ¥ 2p ( RD + RL ) Cout miller

DETERMINATION OF BANDWIDTH OF SINGLE STAGE AMPLIFIER

fa and fb defined in the last section gives an idea about the high-frequency capability of a transistor. An even more important characteristic is fT, which is defined as the frequency at which the short-circuit common-emitter current gain has a magnitude of unity. From Eq. (4.36),

hfe _________ | Ai | = __________ 1 + (f/fb)2

and at f = fT,

| Ai | = 1

(4.47)

÷

( )

fT From Fig. 4.28 fT is less than fa but much greater than fb and __ fB Hence, Eq. (4.47) reduces to hfe 1 ª ___ fT __ fb

2

>> 1

4.29

Then

fT __ ª hfe fb

(4.48)

fT ª hfe fb

(4.49) hfe’ and b cut-off frequency, fb , or CE bandwidth.

fT Similarly, it can be proved that fT ª hf b fa

(4.50)

Value of fT range from 1 MHz for audio transistor up to 1 GHz for high frequency transistors. Typical values of fb , fa and fT are 0.36 MHz, 95.9 MHz and 80.63 MHz. Substituting for fb from Eq. (4.43) in (4.28), 1 fT = hfe ________________ 2p rb¢e (Cb¢e + Cb¢e) hfe 1 _____________ = ___ rb¢e × 2p (C + C ) b¢e

Since Cb¢c >> Cb¢e,

b¢c

gm = _____________ 2p (Cb¢e + Cb¢c) gm fT ª ______ 2pCb¢e

or

(4.51)

gm Cb¢e = _____ 2p fT

fT Substituting fb = ___ in Eq. (4.42) hfe

– hfe Ai = ___________ f 1 + jhfe __ fT

( )

(4.52)

This equation shows the dependence of transistor’s short circuit current gain on the transistor’s gain at low frequencies “hfe” and the high frequency characteristics “fT”.

EXAMPLE 4.11 A BJT has gm = 38 mhos, rb¢e = 5.9 k , hie = 6 k , rbb¢ = 100 , Cb¢c = 12 pF, Cb¢e = 63 pF, and hfe = 224 at 1 kHz. Calculate and cut-off frequencies and fT.

Solution

hfe fa ª _________ 2prb¢e Cb¢e 224 = ________________________ = 95.9 MHz 2p × 5.9 × 103 × 63 × 10 – 12 1 fb = ________________ 2prb¢e (Cb¢e + Cb¢c) 1 = ____________________________________ = 0.359 MHz 3 2p × 5.9 × 10 × (63 × 10 – 12 + 12 × 10 – 12)

4.30

Electronic Circuits I

gm fT = _____________ 2p (Cb¢e + Cb¢c) 38 × 10 0– 3 = _________________________ = 80.63 MHz 2p (63 × 10 – 12 + 12 × 10 – 12)

EXAMPLE 4.12 A certain BJT transistor has r = 2 k of fT, f , and C .

and

= 100 at 1 MHz and

= 5 at 20 MHz. Determine the value

Solution We know that fT = b fb = bf f or

fT = 5 × 20 × 106 = 100 MHz fT 100 × 106 fb = __ = _________ = 1 MHz 100 b

We know that

1 fb = _______ 2p Cp rp 1 1 × 106 = ______________3 2p Cp × 2 × 10

Hence,

1 Cp = ____________________ = 80 pF 2p × 2 × 103 × 1 × 106

EXAMPLE 4.13 Determine the bandwidth of the amplifier shown in Fig. 4.30.

[AU May'13, 16 marks]

20 V +VDD 100 K

9V

25 mF

25 mF C1 5K 10 K

2K

50 mF

Fig. 4.30

Solution hie = rb + rk = 1000 W + 1.1 K = 1.2 K fC = 1/2p(RS + R1||R2||hie)C1 =

1 = 6 Hz 2p [ 0 + (110 K||10 K||1.2 K)] ¥ 25 ¥ 10 -6

4.31

fc(output) = = fc(bypass) =

1 2p ( RC + RL )C2 1 = 0.454 Hz 2p (9 K + 5 K) ¥ 25 ¥ 10 -6 1 ÈÊ RTH + hie ˆ ˘ 2p ÍÁ ˜¯ ˙ CE b ÎË ˚

RTH = R1|| R2||RS = 0 W =

fH =

1 ÈÊ 1.2 ¥ 10 ˘ 3 -6 2p ÍÁ ˜¯ 2 ¥ 10 ˙ ¥ 50 ¥ 10 Ë 225 Î ˚ 3ˆ

= 598 Hz

1 2p rp [Cp + C m (1 + g m RL )]

Cp = 3 pF Cm = 100 pF gm = fH =

h fe rp

= 204.5 mA/V = 204.5 mA/V 1 3

2p ¥ 1.1 ¥ 10 [3 ¥ 10

-12

+ 100 ¥ 10 -12 (1 + 204.5 ¥ 10 -3 ¥ 5 ¥ 103 )]

= 1.4136 KHz Bandwidth is fH – fL Bandwidth = fH – fL = 1.4136 ¥ 103 – 0.454 = 1.4131 KHz

4.12

DETERMINATION OF BANDWIDTH OF MULTISTAGE AMPLIFIERS [AU Dec’12, 8 marks, AU Dec’14, 16 marks, AU Dec’9, 10 marks, AU May’13, 8 marks]

For a second transistor stage connected directly to the output of the first stage, there will be significant change in the overall frequency response. There will be additional low frequency cut-off levels due to the second stage that will further reduce the overall gain of the system in this region. For each additional stage, the upper cut-off frequency will be determined primarily by the stage having the lowest high frequency cut-off frequency. The low frequency cut-off is primarily determined by that stage having the highest low frequency cut-off frequency. Hence one poorly designed stage can off set an otherwise well designed cascaded system. The effect of increasing the number of identical stages, having the same lower and upper cut-off frequencies, can be clearly demonstrated by considering Fig. 4.31. For a single stage, the cut-off frequencies are f1 and f2 as indicated. For two identical stages in cascade, the drop off rate in the low and high frequency regions has increased to –12 dB/octave or – 40 dB per decade. At f1 and f2, therefore, the decibel drop is now –6 dB, rather than the defined band frequency gain level of

4.32 Electronic Circuits I AV 0

f (log scales)

–3 dB –6 dB –9 dB –12 dB

n=1 n=2 n=3

–15 dB –18 dB

f 2¢¢ f2¢ f2 (n = 3) (n = 2)(n = 1)

f ¢¢1 f1 f 1¢ (n = 1) (n = 2)(n = 3)

Fig. 4.31

Effect of an increased number of stages on the cut-off frequencies and bandwidth

–3 dB. The –3 dB point has shifted to f1¢ and f2¢ as indicated, with a resulting drop in the bandwidth. A –18 dB/octave or –60 dB/decade slope will result for a three stage system of identical stages with indicated reduction in bandwidth (f1≤ and f2≤). Assuming identical stages, an equation for each band frequency as a function of the number of the stages (n) can be determined in the following manner. For the low frequency region, AV low(overall) = AV1 low AV2 low AV3 low … AVn low As each stage is identical, AV1 low = AV2 low = … = Avn low AV low(overall) = (AV low)n

Therefore,

AV low/AV mid (overall) = (AV low/AV mid)n = 1/[1 – j( f1/f )]n __

Setting the magnitude of the result equal to 1/÷2 (–3 dB level) results in ___________

__

1/÷[1 + (f1/f1¢)2]n = 1/÷2 Rearranging the above we get

___________ – n

{ ÷[1 + (f1/f1¢)2] }

__

= 1/÷2

{[1 + ( f1/f1¢ )2]1/2}n = (2)1/2 {[1 + ( f1/f1¢ )2]}n = 2 1 + ( f1/f1¢ )2 = (2)1/n and hence we get

[

________

f1¢ = f1/ ÷(2)1/n – 1

]

4.33

In a similar manner, it can be shown that for the high frequency region. ________

f2¢ =

[ ÷(2)1/n – 1 ]

f2

________

The presence of

[ ÷(2)1/n – 1 ] is to be noted in both f1¢ and f2¢. The magnitude of this factor for various

values of n is listed below. ________

n

[ ÷(2)1/n – 1 ]

2

0.64

3

0.51

4

0.43

5

0.39

For n = 2, consider the upper cut-off frequency f2¢ = 0.64 f2 or 64% of the value obtained for a single stage, while f1¢ = (1/0.64) f1 = 1.56 f1. For n = 3, consider the upper cut-off frequency f2¢ = 0.51 f2 or approximately half the value of a single stage, while f1¢ = (1/ 0.51) f1 = 1.96 f1 or approximately twice the single stage value. A decrease in bandwidth is not always associated with an increase in the number of stages if the midband gain can remain fixed and independent of the number of stages.

TWO MARK QUESTION AND ANSWERS 1. Calculate the cut off frequency due to C1 and C2 in the circuit shown in figure.

Cut off frequency due to C1 fC = 1 / 2p RinC1 = 1 / 2p (R1 || R2 || hie )C1 = 1 / 2p (300 ¥ 103 || 150 ¥ 103 || 32 ¥ 103 ) ¥ 1 ¥ 10-6 = 6.56Hz

[AU Dec’10]

4.34 Electronic Circuits I Cut off frequency Due to C2 fC = 1 / 2p (RC + RL ) = 12732.4Hz 2. Define gain Bandwidth product. Gain bandwidth product for the current gain is given by AIm fH = h fe

[AU Dec’12]

RC 1 ◊ RC + Ri 2p Crb¢e

=

gmrb¢e RC ◊ 2p Crb¢e RC + Ri

=

RC gm ◊ 2p C RC + Ri

Similarly, the gain bandwidth product for the voltage gain is given by h fe 1 | AVm fH | = RCi ◊ 2p Crb¢e hie =

gm RCi 2p C hie

3. Define beta cutoff frequency. [AU Dec’14] The b cut off frequency fb, also referred to as fhfe, is the CE short circuit small signal forward current-transfer-ratio cutoff frequency. fb is the frequency at which a transistor’s CE short circuit current gain drops 3-dB from its value at lower (mid) frequencies. fb represents the maximum attainable bandwidth for the current gain of a CE amplifier with a given transistor. 4. Define rise time. Give the relation between bandwidth and rise time. [AU Dec’14, AU May’10] The rise time is the time required for a signal to change from 10% value to a 90% of its value. Relationship between bandwidth and rise time is given as Bandwidth = 0.35/tr 5. Give the expressions for gain bandwidth product for voltage and current. [AU May’10] Gain bandwidth product for the current gain is given by AIm fH = h fe

RC 1 ◊ RC + Ri 2p Crb¢e

=

gmrb¢e RC ◊ 2p Crb¢e RC + Ri

=

RC gm ◊ 2p C RC + Ri

Similarly, the gain bandwidth product for the voltage gain is given by h fe 1 | AVm fH | = RCi ◊ 2p Crb¢e hie =

gm RCi 2p C hie

4.35 7. Draw the hybrid pi equivalent circuit of BJT.

[AU May’11] rb¢c

rbb¢

Cb¢c



B

rb¢e

C

rce

Vb¢e

gm Vb¢e

Cb¢e E

E (a)

8. How do you calculate the bandwidth of a signal? [AU May’13] The bandwidth of a signal is defined as the ratio of lower cutoff frequency from upper cutoff frequency Bandwidth = f2 – f1

REVIEW QUESTIONS 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19.

What is the significance of logarithmic scale? Define “bel” and “decibel”. What is dBm? How is half-power bandwidth calculated? Explain in detail about logarithms and decibels. What are half-power frequencies? “The cut-off frequencies of single stage amplifiers are influenced by RC combinations”—Justify the statement. How does time constant ‘t ’ and rise time ‘tr’ influence the bandwidth of amplifiers. Discuss the effect of emitter bypass capacitor on low frequency response of BJT amplifiers. Explain the effect of coupling capacitor on low frequency response of BJT amplifiers. Draw the high frequency p model of a transistor and explain it. Derive the expression for CE short-circuit current gain as a function of frequency and hence define the a and b cut-off frequencies. Derive the expression for 3-dB upper cut-off frequency of emitter follower with the help of its equivalent circuit. Derive the relationship between low frequency h-parameters and high frequency hybrid p parameters for a transistor in CE configuration. Explain how the source resistance influence the frequency response of amplifiers. Draw the equivalent circuit of common-source amplifier at high frequencies and derive expressions for voltage gain, input admittance and output admittance. Draw the equivalent circuit of common-drain amplifier (source follower) at high frequencies and derive expressions for voltage gain, input admittance and output admittance. What are the parameters that will influence the frequency response of FET amplifiers? Justify your answer. Explain how the number of stages in a multistage amplifier influences the cut-off frequency and bandwidth.

5.1

5 5.1

IC MOSFET Amplifier

IC BIASING

Biasing in integrated-circuit design is based on the use of constant-current sources. On an IC chip with a number of amplifier stages, a constant dc current (called a reference current) is generated at one location and is then replicated at various other locations for biasing the various amplifier stages through a process known as current steering. Advantages of current steering 1. Effort expended on generating a predictable and stable reference current, usually utilizing a precision resistor external to the chip, need not be repeated for every amplifier stage. 2. The bias currents of the various stages track each other in case of changes in power-supply voltage or in temperature. The circuit building blocks and techniques employed in the bias design of IC amplifier is dealt in this chapter. These circuits are also utilized as amplifiers load elements.

5.2 THE BASIC MOSFET CURRENT SOURCE A simple MOS constant-current source circuit is shown in Fig 5.1. The important element of the circuit is transistor Q1 the drain of which is shorted to its gate, thereby forcing it to operate in the saturation mode with ID1 =

1 ÊW ˆ K n¢ Á ˜ (VGS - Vin ) 2 2 Ë L¯

(5.1)

where Kn’ is transconductance parameter, Vin is input voltage and W/L is width to length ratio for the MOSFET device. Here the channel-length modulation is neglected. The drain current of Ql is supplied by VDD through resistor R, which is housed outside the IC chip in most cases. Since the gate currents are zero,

Fig. 5.1

Basic MOSFET constant-

5.2

VDD - VGS R Here IREF is reference current of the current source ID1 = I REF =

(5.2)

VDD is power supply where the current through R is taken as the reference current of the current source and is denoted as IREF. The value of R can be determined by equations 5.1 and 5.2. Assuming Transistor Q2, has the same VGS as Q1, and operating in saturation, its drain current, which is the output current Io of the current source, will be I0 = ID2 =

1 ÊW ˆ K n¢ Á ˜ (VGS - Vin ) 2 2 Ë L ¯2

(5.3)

where once again channel-length modulation is neglected. The above two equations relates the output current Io to the reference current IREF given as I0 (W / L) 2 = I REF (W / L)1

(5.4)

This is a simple and yet powerful relationship: The unique connection of Ql and Q2 provides an output current Io related to the reference current IREF by the ratio of the aspect ratios of the transistors. To make it simple, the relationship between Io and IREF is solely determined by the geometries (W and L) of the two transistors. If the transistors are identical, I0 = IREF, and the circuit simply replicates or mirrors the reference current in the output terminal. Hence the circuit built with Ql and Q2 is the named as current mirror, which is applicable used irrespective of the ratio of device dimensions. Figure 5.2 shows the current mirror circuit in which the input reference current is depicted as being supplied by a current source for both simplicity and generality. The current gain or current transfer ratio of the current mirror is given by Eq. (5.4).

Fig. 5.2

Effect of Vo on I0 Transistor Q2 assumed to be operating in saturation for the operation of the current source of Fig. 5.1, which is essential for Q2 to supply a constant-current output. In order to ensure that Q2 is always saturated, the circuit to which the drain of Q2 is to be connected must maintain a drain voltage V0 that satisfies the relationship V0 ≥ VGS – Vt

(5.5)

where Vt is the threshold voltage The same can be expressed, in terms of the overdrive voltage Vov of Q1 and Q2 as V0 ≥ Vov Here Vov is override voltage

(5.6)

5.3

Thus the current source will give the desired operation with an output voltage V0 as low as Vov, which is a few tenths of a volt. Further channel-length modulation can have a significant effect on the operation of the current source. Assuming identical devices for Q1 and Q2, the drain current of Q2, Io, will equal the current in Q1, IREF, at the value of Vo that causes the two devices to have the same VDS, that is, at Vo = VGS. As Vo is increased above this value, I0 will increase according to the incremental output resistance ro2 of Q2.As shown in Fig. 5.3, as Io versus Vo. Since Q2 is operating at a constant VGS determined by IREF through the matched device Q1, Fig. 5.3 is simply the iD-vDS characteristic curve of Q2.

Fig 5.3

Thus, the current source of Fig. 5.4 and the current mirror of Fig. 5.5 have a finite output resistance R0 DVo V = ro 2 = A2 DI o Io

R0 ∫

(5.7)

where I0 is given by Eq. (5.3) and VA2 is the Early voltage of Q2. For a given process technology, VA is proportional to the transistor channel length. Hence to obtain high output-resistance values, current sources are designed using transistors with relatively long channels. To conclude the current Io can be expressed as I0 =

Ê V -V ˆ (W / L) 2 I REF Á1 + o GS ˜ VA2 ¯ (W / L)1 Ë

(5.8)

As discussed in the previous section, once a constant current is generated, it can be replicated to provide de bias currents for the various amplifier stages in an IC. Current mirrors are used to implement this current-steering function. Figure 5.4 shows one such a simple current-steering circuit.

Fig 5.4

5.4

Here Q1 and R determine the reference current IREF. Transistors Q1, Q2, and Q3 form a two-output current mirror given by

and

I2 = I REF =

(W / L) 2 (W / L)1

(5.9)

I3 = I REF =

(W / L)3 (W / L)1

(5.10)

For transistors Q2 and Q3 to operate in the saturation region, the voltages at the drains are constrained as follows VD2, VD3 ≥ – VSS + VGS1 – Vtn

(5.11)

Here Vtn is threshold voltage VD2 and VD3 is voltage drain VD2, VD3 ≥ – VSS + Vov1

(5.12)

where Vov1 is the overdrive voltage at which Q1, Q2, and Q3 are operating. Thus, the drains of Q2 and Q3 will have to remain higher than Vss by at least the overdrive voltage, which is usually a few tenths of a volt. Further from circuit of Fig. 5.4, current I3 is fed to the input side of a current mirror formed by PMOS transistors Q4 and Q5. This mirror provides I5 = I 4

(W / L)5 (W / L) 4

(5.13)

where I4 = I3. To keep Q5 in saturation, its drain voltage should be VDS £ VDD – |V0v5|

(5.14)

where V0V5 is the overdrive voltage at which Q5 is operating. It is important to note that as Q2 pulls its current I2 from a load (not shown in Fig. 5.5), Q5 pushes its current I5 into a load (not shown in Fig. 5.4). Hence Q5 is called a current source, and Q2 a current sink. Both current sources and current sinks are needed in an IC

5.4 ACTIVE LOAD The MOS transistor used as a load device is referred to as active load. Three types of load devices are n channel enhancement load device, n-channel depletion load device and p-channel enhancement load device. With an n channel enhancement mode driver transistor (inverter) all the three circuits can be used as amplifiers.

5.4.1

NMOS Amplifiers with Enhancement Load

Figure 5.5 (a) shows an NMOS enhancement load transistor, and Fig. 5.5 (b) shows the current-voltage characteristics. The threshold voltage is VTNL.

Fig 5.5

5.5

Fig. 5.5

An NMOS amplifier with enhancement load is shown in Fig 5.6a. The driver transistor is QD and the load transistor is QL. The characteristics of transistor QD and the load curve are shown in Fig. 5.6(b). The load curve is essentially the mirror image of the i-v characteristic of the load device. Since the i-v characteristics of the load device are nonlinear, the load curve is also nonlinear. The load curve intersects the voltage axis at VDD – VTNL, the point at which the current in the enhancement load device reduce to zero. The transition point is also shown in Fig. 5.6(b). The voltage transfer characteristic of Fig 5.6(c) useful in understanding the operation of the amplifier. When the enhancement-mode driver first begins to conduct, it is biased in the saturation region. For use as an amplifier, the circuit Q-point should be in this region, as shown in Fig. 5.6 b and c. The small-signal equivalent circuit of Fig. 5.7 is used to Fig. 5.6 find the voltage gain. The subscripts D and L refer to the driver and load transistors, respectively. In a source follower, the equivalent resistance looking into the source terminal (with Rs = ) is R0 = (1/gm||r0). Here the body effect of the load transistor is neglected. The small-signal voltage gain is Av =

Ê ˆ Vo 1 = - g mD Á roD r0 L ˜ Vi g Ë ¯ mL

(5.15)

Since, generally 1/gmL (1/gm3) reduces to vg3 = –(gm1/gm3)(vid/2)

(5.23)

This voltage controls the drain current of Q4 resulting in a current of gm4Vg3. Note that the ground at the output node causes the currents in ro2 and ro4 to be zero. Thus the output current

5.14

Fig. 5.15

m = i0

i0 will be i0 = –gm4vg3 + gm2(vid/2)

(5.24)

Substituting for vg3 from (5.23) gives I0 = gm1(gm4/gm3)(vid/2) + gm2(vid/2) Now, since gm3 = gm4 and gm1 = gm2 = gm the current i0 becomes i0 = gmvid from which Gm is found to be Gm = gm

(5.25)

Thus the short-circuit transconductance of the circuit is equal to gm of each of the two transistors of the differential pair. Here in the absence of the current-mirror action, Gm would be equal to gm/2. Determining the Output Resistance R0 The circuit for determining R0 is shown in Fig 5.16. The current i that enter Q2 must exit at its source. It then enters Q1, exiting at the drain to feed the Q3 – Q4 mirror. Since for the diode-connected transistor Q3, 1/gm3 is much smaller than ro3, most of the current i will flow into the drain of Q3. The mirror responds by providing an equal current i in the drain of Q4. To determine the relationship between i and vx from Fig. 5.16. i = vx/R02 where R02 is the output resistance of Q2. Now, Q2 is a CG transistor and has in its source lead the input resistance of Ql. The latter is connected in the CG configuration with a small resistance in the drain (approximately equal to 1/gm3), thus its input resistance is approximately 1/gml. R02 is obtained by substituting gmb = 0 and Rs = 1/gm1 as R02 = r02 + (l + gm2r02)(1/gm1) which for gm1 = gm2 = gm and gm2r02 >> 1 yields

5.15

R02 @ 2r02

(5.26)

From the circuit in Fig. 5.15, at the output node, using KCL ix = i + i + vx/r04 = 2i + vx/r04 = 2 vx/R02 + vx/r04 Substituting for R02 from Eq. (5.26) results in Thus, R0 = vx/ix = r02||r04

(5.27)

which is an attractive result. Equations (5.25) and (5.27) can be combined to obtain the differential gain Ad as Ad ∫ v0/vid = gm(r02||r04)

(5.28)

Ad = 1/2gmro = A0/2

(5.29)

For the case r02 = r04 = ro

1/gm3

ro3

ro4

Q4

Q3

i

i

ix Ro2

i

i Ro

Q1

ro1

ro2

+ –

Vx

Q2

i

Fig. 5.16

0

The active-loaded MOS differential amplifier has a low common-mode gain and a high CMRR, though its output is single-ended. Figure 5.17(a) shows the circuit with Vicm applied and with the power supplies removed. The output resistance Rss of the bias-current source I is included for analysis. Rss is split equally between Q1 and Q2 as shown in Fig. 5.17 (b). Both Q1 and Q2 are CS transistors with a large source degeneration resistance 2Rss. To determine the currents i1 and i2 due to input signal Vicm: Since 2Rss is usually much larger than l/gm of each of Q1 and Q2 the signals at the source terminals will be approximately equal to Vicm. Also, the effect of ro1 and ro2 are negligible. Hence

i1 = i2 @

Vicm 2 RSS

(5.30)

5.16

1/gm3

ro3

Q4

Q3

1/gm3

ro3

ro4

ro4

Q4

Q3

i4

i1

Vo

Ro1

i2

Ro2

Vo Vicm

Q1

ro1

ro2

Q2

Vicm

Q1

Vicm

ro1 ro2

2Rss

(a)

Q2

Vicm

2Rss

(b)

Fig. 5.17

Here Vicm is common mode voltage RSS output resistance The output resistance of each of Q1 and Q2 is given by Ro = ro + [1 + (gm + gmb)ro]RS which for RS = 2RSS and gmb = 0 yields R01 = R02 = r0 + 2RSS + 2gmr0RSS

(5.31)

where ro1 = ro2 = ro and gm1 = gm2 = gm. Note that Ro1 will be much greater than the parallel resistance È Ê 1 ˆ˘ introduced by Q3, Íro3 || Á ˙ Similarly, R02 will be much greater than ro4. Hence neglect Ro1 and Ro2 Ë g ms ˜¯ ˚˙ ÎÍ in finding the total resistance between each of the drain node and ground The current –i1 is passed through (1/gm3||ro3) and produces a voltage Vg3 Ê 1 ˆ Vg3 = -i1 Á ro3 ˜ Ë g ms ¯

(5.32)

Transistor Q4 senses this voltage and hence provides a drain current i4, i4 = –gm4vg3 Ê 1 ˆ = i1 g m 4 Á || ro3 ˜ Ë g ms ¯

(5.33)

Now, at the output node the current difference between i4 and i2 passes through ro4 (since Ro2 > ro4) to provide vo

5.17

V0 = (i4 – i2)r04 È ˘ Ê 1 ˆ = Íi1 g m 4 Á || ro3 ˜ - i2 ˙ ro 4 Ë g ms ¯ ÍÎ ˙˚ Substituting for i1 and i2 from Eq. (5.30) and setting gm3 = gm4 results in Common Mode gain Acm = As gm3r03 >> 1 & r03 = r04, Acm @

vo ro 4 -1 = vicm 2 RSS g m 2 ros + 1

-1 2 RSS g m3

(5.34)

(5.35)

(5.36)

Acm will be small since Rss is usually large, at least equal to ro. The common-mode rejection ratio (CMRR) can now be obtained CMRR =

| Ad | = [gm(r02||r04)] [2gm3RSS] | Acm |

(5.37)

which for r02 = r04 = r0 and gm = gm3 simplifies to CMRR = (gmr0) (RSSgm)

(5.38)

In order to obtain a large CMRR the biasing current source I should exhibit a high output resistance as found in cascode current source or Wilson current source.

TWO MARK QUESTION AND ANSWERS 1. Define Current steering. On an IC chip with a number of amplifier stages, a constant dc current (called a reference current) is generated at one location and is then replicated at various other locations for biasing the various amplifier stages through a process known as current steering. 2. State the Advantages of current steering. Advantages of current steering are: 1. Effort expended on generating a predictable and stable reference current, usually utilizing a precision resistor external to the chip, need not be repeated for every amplifier stage. 2. The bias currents of the various stages track each other in case of changes in power-supply voltage or in temperature. 3. Draw the Basic MOSFET constant-current source. See Fig. 5.1 on page 5.1. 4. Draw the MOSFET current mirror circuit. See Fig. 5.2 on page 5.2. 5. Define Active load and list the types of active load. The MOS transistor used as a load device is referred to as active load. Three types of load devices are n-channel enhancement load device, n-channel depletion load device and p-channel enhancement load device. 6. Draw the Current-voltage characteristics of NMOS enhancement load transistor See Fig. 5.5 on page 5.5.

5.18 7. Give the expression for small-signal voltage gain NMOS Amplifiers with Enhancement Load. The small-signal voltage gain is A = Since, generally 1/

Ê ˆ Vo 1 = - g mD Á roD roL ˜ Vi g mL Ë ¯

mL