Linear IC Applications 9789353161026, 9353161029

Table of contents :
Title
Contents
1 Circuit Configurations for Linear ICs
2 Operational Amplifiers
3 Linear and Non-Linear Applications of Op-Amps
4 Active Filters, Analog Multipliers and Modulators
5 Timers and Phase Locked Loops
6 D/A and A/D Converters
Question Paper

Citation preview

Linear iC appLiCations

About The Authors

S. Salivahanan is the Principal of SSN College of Engineering, Chennai. He obtained his B.E. degree in Electronics and Communication Engineering from PSG College of Technology, Coimbatore, M.E. degree in Communication Systems from NIT, Trichy and Ph.D. in the area of Microwave Integrated Circuits from Madurai Kamaraj University. He has four decades of teaching, research, administration and industrial experience both in India and abroad. He has taught at NIT, Trichy, A.C. College of Engineering and Technology, Karaikudi, RV College of Engineering, Bangalore, and Mepco Schlenk Engineering College, Sivakasi. He has industrial experience as Scientist/Engineer at Space Applications Centre, ISRO, Ahmedabad, Telecommunication Engineer at State Organization of Electricity, Iraq and Electronics Engineer at Electric Dar Establishment, Kingdom of Saudi Arabia. He is the author of 40 popular books which include all-time bestsellers such as Basic Electrical and Electronics Engineering, Electronic Devices and Circuits, Linear Integrated Circuits published by McGraw Hill Education, New Delhi, Digital Signal Processing by McGraw Hill International which has also been translated into Mandarin, the Chinese language. He has also authored the books on Digital Circuits and Design, Electromagnetic Field Theory, Circuit Theory, Network Analysis and Synthesis and Control Systems Engineering. He has published several papers at national and international levels. Professor Salivahanan is the recipient of Bharatiya Vidya Bhavan National Award for Best Engineering College Principal for 2011 from ISTE, and IEEE Outstanding Branch Counsellor and Advisor Award in the Asia-Pacific region for 1996-97. He was the Chairman of IEEE Madras Section for two years 2008 and 2009 and Syndicate Member of Anna University. He is a Senior Member of IEEE, Fellow of IETE, Fellow of Institution of Engineers (India), Life Member of ISTE and Life Member of Society for EMC Engineers. He is also a member of IEEE societies in Microwave Theory and Techniques, Communications, Signal Processing, and Aerospace and Electronics. V. S. Kanchana Bhaaskaran is a Professor in the School of Electronics Engineering and Dean of Academics at VIT University Chennai. She obtained her bachelor’s degree in Electronics and Communication Engineering from Institution of Engineers (India), Calcutta, MS degree in Systems and Information from Birla Institute of Technology and Sciences (BITS) Pilani and PhD from VIT University. With more than 38 years of industry, research and teaching experience, Professor Bhaaskaran served the Department of Employment and Training, Government of Tamil Nadu, IIT Madras, Salem Cooperative Sugar Mills’ Polytechnic College, SSN College of Engineering and VIT University Chennai. Her areas of specialization include Low Power VLSI Circuit Design, Microprocessor Architectures and Linear Integrated Circuits. She has published around 110 papers in international and national journals and conferences, has two patents published and one filed. She is a reviewer for peer reviewed international journals and conferences. Professor Bhaaskaran is the Fellow of the Institution of Engineers (India), Fellow of the Institution of Electronics and Telecommunication Engineers (India), Senior Member of the Institute of Electrical and Electronics Engineers Inc., USA and Life Member of the Indian Society for Technical Education.

Linear iC appLiCations

S Salivahanan Principal SSN College of Engineering Chennai

v S Kanchana BhaaSKaran Professor, School of Electronics Engineering and Dean (Academics) Vellore Institute of Technology Chennai

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Printed and bound in India. Director—Science & Engineering Portfolio: Vibha Mahajan Senior Portfolio Manager: Hemant K Jha Associate Portfolio Manager: Vaishali Thapliyal Production Head: Satinder S Baveja Manager—Production: Reji Kumar Information contained in this work has been obtained by McGraw Hill Education (India), from sources believed to be reliable. However, neither McGraw Hill Education (India) nor its authors guarantee the accuracy or completeness of any information published herein, and neither McGraw Hill Education (India) nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that McGraw Hill Education (India) and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought. Typeset at NuWave eSolutions Pvt. Ltd. and printed and bound in India at Cover Printer: Cover Designer: APS Compugraphics Cover Image Source: Shutterstock Visit us at: www.mheducation.co.in Write to us at: [email protected] CIN: U22200TN1970PTC111531 Toll Free Number: 1800 103 5875

Preface

This book is designed for the fifth semester Electronics and Communication Engineering students pursuing the course on Linear IC Applications. The book is written in a very simple yet elaborative, crisp and student-friendly lucid language, which helps students understand the basic concepts easily and intensely. The coverage of topics is focused and aligned to the latest syllabus. Various important terms and definitions related to integrated circuits, op-amps and linear IC applications are described. Typical applications of the ICs are well explained and are suitably supplemented with block diagrams, schematics, figures and transients. Pedagogical questions are well distributed and incorporated in each chapter. Multiple choice questions to probe the learning of the student form part of each chapter. Stepwise solution of solved examples has been provided within the text, which enables students to develop a logical approach to solving problems.

Chapter Organisation The text comprises of six chapters; the first two chapters cover the integrated circuits, the differential amplifier configurations and various stages of op-amp. The dc and ac characteristics of op-amp, specifications of op-amp 741 IC and its features followed by the op-amp parameters and their measurements, ideal and practical characteristics of op-amp, stages of a general op-amp, DC and AC performance characteristics, slew rate, open and closed loop configurations and frequency compensation techniques are dealt with in Chapter 2. Chapter 3 presents the linear and non-linear applications of op-amps, which include inverting and non-inverting amplifiers, Integrator, Differentiator, Difference Amplifier, Instrumentation amplifier, AC Amplifier, V-to-I and I-to-V Converters, Buffers, Non-Linear Function Generation, Comparators, Multivibrators, Triangular and Square Wave Generators, Logarithmic and Antilogarithmic amplifiers, and Precision rectifiers. Chapter 4 discusses the active filters with focus on design and analysis of Butterworth active filters of first and second order LPF, HPF, BPF and Band Reject filters along with All Pass Filters. This is followed by Analog Multipliers and Modulators in the same chapter with impetus on Analog Multiplier using Emitter Coupled Transistor Pair, Gilbert multiplier cell, Four Quadrant Multiplier, IC 1496 and, Sample and Hold circuits. Timer ICs and Phase Locked Loops form the fifth chapter. Timer IC 555 block diagram, its functional operation along with monostable and astable operations and their typical applications including Schmitt trigger form the first part of this chapter. Operation of the basic PLL with its block schematic, closed loop analysis of PLL, monolithic PLL IC–565, application of PLL for AM detection, FM detection, Frequency Translation, Frequency Multiplication, FSK modulation and Demodulation and Frequency Synthesizing are dealt with as part of the fifth Chapter. The Voltage Controlled Oscillator IC 566 and its applications are also dealt with. Chapter 6 delves in detail into the Analog and Digital Data Conversions, DAC Specifications, Weighted Resistor DAC, R-2R Ladder DAC, Inverted R-2R DAC, IC 1408 DAC. This is followed by different types of ADCs such as Parallel Comparator or Simultaneous Type (Flash Type) ADC, Counter

vi

Preface

Type A/D Converter, Successive Approximation Type A/D Converter, Dual Slope Type A/D Converter and specifications of the 12-bit A/D Converter IC AD574.

Highlights and Salient Features of the Book ● ● ●

Crisp content strictly as per the latest JNTU-K syllabus of Linear ICs Applications Comprehensive coverage with lucid presentation style Quality illustrations to aid better understanding of the subject

Acknowledgements We would like to thank the editorial and production team of the publisher, McGraw Hill Education (India), for their professional way of handling the project and bringing it out in such a short span of time. S. Salivahnan would like to thank his wife, Kalavathy and his sons Santhosh Kanna and Subadesh Kanna for their enormous patience and moral support during the course of writing this book. Dr. Bhaaskaran would like to express her heartfelt thanks to her husband, daughters and granddaughters, Gargi and Mythreyi, for their tremendous support. We are also thankful to Krishnanaik Vankdoth, Vaagdevi College of Engineering, Warangal and G. Sridevi, Aditya Engineering College, Surampalem, Andhra Pradesh for reviewing draft chapters of the book. S Salivahanan V S Kanchana Bhaaskaran

Publisher’s Note McGraw-Hill Education (India) invites suggestions and comments from you, all of which can be sent to [email protected] (kindly mention the title and author name in the subject line). Piracy-related issues may also be reported.

Contents

Preface Acknowledgements Roadmap to the Syllabus

1.

v vi xiv

Circuit Configurations for Linear ICs

1

1.1 1.2 1.3 1.4

Introduction 1 Differential Amplifiers 1 DC and AC analysis of Dual Input Balanced Output Configuration Differential Amplifiers with Active Loads 9 1.4.1 BJT Differential Amplifiers using Active Loads 10 1.5 Properties of Other Differential Amplifier Configurations 13 1.5.1 Dual input, unbalanced output differential amplifier 13 1.5.2 Single input, balanced output differential amplifier 14 1.5.3 Single input, unbalanced output differential amplifier 15 1.6 DC Coupling and Cascaded Differential Amplifier Stages 16 1.7 Level Translators or DC Level Shift Stages 20 Review Questions 22 Objective-Type Questions 23 Answers to Objective-Type Questions 23

2.

Operational Amplifiers 2.1 2.2 2.3 2.4 2.5

2.6 2.7 2.8 2.9

Introduction 24 Integrated Circuits 24 Classification, Package Types and Temperature ranges Circuit Symbol of an Operational Amplifier 28 Op-Amp Power Supplies 28 2.5.1 Dual Voltage Power Supplies 28 2.5.2 Single Voltage Power Supplies 29 Basic Block Diagram of an Op-Amp 31 Ideal Op-Amp Specifications 32 Practical Op-Amp Specifications 33 DC Characteristics of Op-Amp 34

2

24

25

viii

Contents

2.10

2.11

2.12

2.13

2.14

2.9.1 Input Bias Current 34 2.9.2 Input Offset Current 36 2.9.3 Input Offset Voltage 37 2.9.4 Total Output Offset Voltage 38 2.9.5 Offset Voltage Compensation 39 2.9.6 Thermal Drift 40 2.9.7 Power Supply Rejection Ratio (PSRR) or Supply Voltage Rejection Ratio (SVRR) 41 AC Characteristics of Op-Amp 42 2.10.1 Frequency Response 42 2.10.2 Open-loop Gain as a Function of Frequency 43 2.10.3 Bandwidth with Feedback 48 2.10.4 Closed-loop Frequency Response 49 2.10.5 Slew Rate 50 IC 741 Bipolar Operational Amplifier and its features 54 2.11.1 Bias Circuit 55 2.11.2 Input Stage 55 2.11.3 Gain Stage 56 2.11.4 Output Stage 56 2.11.5 DC Analysis of IC 741 56 2.11.6 Short-Circuit Protection 59 2.11.7 Small Signal Analysis 60 2.11.8 Frequency Response 63 General Description of the Op-Amp 741 63 2.12.1 General Description 64 2.12.2 Absolute Maximum Ratings 64 2.12.3 Packages 64 2.12.4 Op-amp Terminals 66 Op-Amp Parameters and Measurement 66 2.13.1 Offset Measurement 67 2.13.2 Bias Current Measurement 68 2.13.3 DC gain measurement 68 2.13.4 AC gain measurement 69 2.13.5 DC Common Mode Rejection Ratio (CMRR) measurement 70 2.13.6 DC Power Supply Rejection Ratio (PSRR) measurement 71 2.13.7 AC Common Mode Rejection Ratio (CMRR) measurement 71 2.13.8 Slew Rate measurement 72 Frequency Compensation 73 2.14.1 External Frequency Compensation 73 2.14.2 Internal Frequency Compensation 76

Contents

Review Questions 77 Objective-Type Questions 79 Answers to Objective-Type Questions

3.

81

Linear and Non-Linear Applications of Op-Amps 3.1 3.2

ix

Introduction 82 Open-Loop Op-Amp Configurations 82 3.2.1 Open-loop Differential Amplifier 83 3.2.2 Inverting Amplifier 83 3.2.3 Non-inverting Amplifier 83 3.2.4 Limitations of Open-loop Op-amp Configurations 84 3.3 Closed-Loop OP -AMP Configurations 84 3.3.1 Inverting Amplifier 86 3.3.2 Practical Inverting Amplifier 88 3.3.3 Non-inverting Amplifier 90 3.3.4 Practical Non-inverting Amplifier 93 3.4 Integrator 94 3.4.1 Ideal Integrator 94 3.4.2 Limitations of an Ideal Integrator 96 3.4.3 Summing Integrator 96 3.4.4 Practical Integrator Circuit (ac Integrator circuit) 97 3.4.5 Initial Condition 98 3.4.6 Applications of Integrators 98 3.5 Differentiator 100 3.5.1 Ideal Differentiator 100 3.5.2 Summing Differentiator 100 3.5.3 Limitations of Differentiators 101 3.5.4 Practical Differentiator 102 3.5.5 Applications of Differentiators 104 3.5.6 Comparison between an Integrator and a Differentiator 105 3.6 Differential Amplifier 105 3.6.1 Differential Amplifier with Single Op-amp 105 3.7 Instrumentation Amplifier 108 3.8 AC Amplifier 113 3.8.1 Inverting ac Amplifier 113 3.8.2 Non-inverting ac Amplifier 114 3.8.3 The ac Voltage Follower 114 3.9 Voltage to Current Converter (Transconductance Amplifier) 115 3.10 Current to Voltage Converter (Current-Controlled Voltage Sources) 117 3.11 Voltage Follower 119

82

x

Contents

3.12 OP-AMP Comparators 120 3.12.1 Zero Crossing Detector (Sine Wave to Square Wave Converter) 3.12.2 Amplitude Distribution Analyser 124 3.12.3 Pulse-time Modulator 124 3.12.4 Window Detector 124 3.12.5 Timing Marker Signal Generator 125 3.12.6 Phase Detector 126 3.13 Multivibrators 126 3.13.1 Astable (Free-running) Multivibrator 126 3.13.2 Monostable Multivibrator 130 3.14 Triangular Wave Generator 131 3.15 Square Wave Generator 134 3.16 Logarithmic Amplifier 134 3.17 Antilogarithmic Amplifier 137 3.18 Precision Rectifier 139 3.18.1 Precision Diodes 139 3.18.2 Half-wave Rectifier 141 3.18.3 Full-wave Rectifier 142 Review Questions 143 Objective-Type Questions 145 Answers to Objective-Type Questions 147

4.

Active Filters, Analog Multipliers and Modulators 4.1 4.2

4.3 4.4

4.5

4.6

Introduction 148 Types of filters 148 4.2.1 Low-pass Filter (LPF) 149 4.2.2 High-pass Filter (HPF) 149 4.2.3 Bandpass Filter (BPF) 149 4.2.4 Band-Reject Filter (BRF) or Band-Elimination Filter (BEF) 150 Design and Analysis of Butterworth Active Filters 150 Design of Low-Pass Filters 153 4.4.1 First Order Low-pass Filter with Unity Gain 153 4.4.2 First Order Low-pass Filter with Variable Gain 154 General Second-order Active Filter with Unity Gain 156 4.5.1 General Second-Order Active Filter with Variable Gain 157 4.5.2 Second-Order Low-pass Filter with Unity Gain 158 4.5.3 Second-Order Low-pass Filter with Variable Gain 160 Design of High-pass Filters 163 4.6.1 First-Order High-pass Filter with Unity Gain 163 4.6.2 First-Order High-pass Filter with Variable Gain 163 4.6.3 Second-Order High-Pass Filter with Unity Gain 166 4.6.4 Second-Order High-Pass Filter with Variable Gain 166

123

148

Contents

Bandpass Filters 169 4.7.1 Wideband Bandpass Filter 170 4.7.2 Narrowband Bandpass Filter 172 4.8 Band-Reject Filters 173 4.8.1 Wideband Band-reject Filter 173 4.8.2 Narrowband Band-reject Filter (Notch filter) 175 4.9 All-Pass Filters 178 4.9.1 All-Pass Filter using op-amp 178 4.10 Analog Multipliers 180 4.10.1 A Simple Multiplier using an Emitter Coupled Transistor Pair 4.10.2 Gilbert Multiplier Cell 182 4.11 Four-quadrant Analog Multiplier 186 4.12 Mc1496 Monolithic Double-Balanced Modulator/Demodulator 189 4.12.1 General Description 189 4.12.2 Device Operation 190 4.12.3 Balanced Modulator using MC1496 190 4.12.4 Amplitude Modulator 191 4.12.5 Product Detector 191 4.12.6 Double Balanced Mixer 192 4.12.7 Frequency Doubler 192 4.12.8 Phase Detection and FM Detection 193 4.13 Sample-and-Hold Circuits 194 4.13.1 Sampling 194 4.13.2 Sample-and-Hold Circuit 195 Review Questions 196 Objective-Type Questions 198 Answers to Objective-Type Questions 201

xi

4.7

5.

Timers and Phase Locked Loops 5.1 5.2 5.3 5.4

5.5 5.6

Introduction 202 Timer IC 555 202 5.2.1 Functional Diagram of the IC 555 202 Monostable Operation of Timer IC 555 204 Applications of Monostable Multivibrator 207 5.4.1 Ramp Generation 207 5.4.2 Frequency Divider 208 5.4.3 Pulse-width Modulation 209 Astable Operation of the Timer IC 555 210 Applications of Astable Multivibrator 213 5.6.1 FSK Generator 213 5.6.2 Pulse-position Modulator 214 5.6.3 Schmitt Trigger 215

181

202

xii

Contents

5.7 5.8 5.9

Introduction to PLL 216 Block Schematic and operation of the PLL 216 Principle and Description of Individual Blocks 221 5.9.1 Phase Detector/Phase Comparator 221 5.9.2 Voltage Controlled Oscillator (VCO) 223 5.9.3 Applications of IC Voltage Controlled Oscillator NE/SE566 225 5.9.4 Low-Pass Filter 228 5.10 LM 565 PLL 229 5.11 Applications of IC 565 PLL 237 5.11.1 Frequency Multiplication/Division 237 5.11.2 Frequency Translation 238 5.11.3 AM Demodulator 238 5.11.4 FM Demodulator 239 5.11.5 FSK Modulation/Demodulation 240 Review Questions 243 Objective-Type Questions 245 Answers to Objective-Type Questions 246

6.

D/A and A/D Converters 6.1 6.2 6.3 6.4

6.5 6.6 6.7 6.8

6.9

Introduction 247 Analog and Digital Data Conversions 247 Specifications of D/A Converter 248 Basic D/A Conversion Techniques 251 6.4.1 Weighted Resistor Type D/A Converter 251 6.4.2 R-2R Ladder D/A Converter 256 6.4.3 Inverted or Current-Mode R—2R Ladder D/A Converter 259 A Monolithic D/A Converter DAC 1508/1408 260 A/D Converters 264 Specifications of A/D Converter 266 Classification of A/D Converters 268 6.8.1 Parallel Comparator or Simultaneous Type (Flash Type) ADC 269 6.8.2 Counter Type A/D Converter 273 6.8.3 Successive Approximation Type A/D Converter 274 6.8.4 Dual Slope Type A/D Converter 277 Specifications of AD574 (12-Bit ADC ) 279 6.9.1 General Description 279 6.9.2 Functional Description 281 6.9.3 Unipolar Range Connections for the, AD574A 281 6.9.4 Bipolar Range Connections of AD574A 283 6.9.5 Operation of AD574A 283

247

Contents

6.9.6 Control Logic 283 6.9.7 Supply decoupling and Grounding Considerations Review Questions 285 Objective-Type Questions 286 Answers to Objective-Type Questions 287

Previous Year’s Solved JNTU Examination Questions

xiii

284

288

Roadmap to the Syllabus

Linear IC Applications JNTU–Kakinada Unit-I: INTEGRATED CIRCUITS: Differential Amplifier—DC and AC analysis of Dual input Balanced output Configuration, Properties of other differential amplifier configuration (Dual Input Unbalanced Output, Single Ended Input—Balanced/Unbalanced Output), DC Coupling and Cascade Differential Amplifier Stages, Level translator. GO TO

Chapter 1: Circuit Configurations for Linear ICs

Unit-II: Characteristics of OP-Amps, Integrated circuits-Types, Classification, Package Types and Temperature ranges, Power supplies, Op-amp Block Diagram, ideal and practical Op-amp Specifications, DC and AC characteristics, 741 Op-amp & its features, Op-amp parameters & Measurement, Input & Out put Off set voltages & currents, slew rate, CMRR, PSRR, drift, Frequency Compensation techniques. GO TO

Chapter 2: Operational Amplifiers

Unit-III: LINEAR and NON-LINEAR APPLICATIONS OF OP-AMPS: Inverting and Non-inverting amplifier, Integrator and differentiator, Difference amplifier, Instrumentation amplifier, AC amplifier, V to I, I to V converters, Buffers, Non-Linear function generation, Comparators, Multivibrators, Triangular and Square wave generators, Log and Anti log Amplifiers, Precision rectifiers. GO TO

Chapter 3: Linear and Non-Linear Applications of Op-Amps

Roadmap to the Syllabus

xv

Unit-IV: ACTIVE FILTERS, ANALOG MULTIPLIERS AND MODULATORS: Design & Analysis of Butterworth active filters—lst order, 2nd order LPF, HPF filters. Band pass, Band reject and all pass filters.Four Quadrant Multiplier, IC 1496, Sample & Hold circuits. GO TO

Chapter 4: Active Filters, Analogue Multipliers and Modulators

Unit-V: TIMERS & PHASE LOCKED LOOPS: Introduction to 555 timer, functional diagram, Monostable and Astable operations and applications, Schmitt Trigger; PLL—introduction, block schematic, principles and description of individual blocks, 565 PLL, Applications of PLL-frequency multiplication, frequency translation, AM, PM & FSK demodulators. Applications of VCO (566). GO TO

Chapter 5: Timers and Phase Locked Loops

Unit-VI: DIGITAL TO ANALOG AND ANALOG TO DIGITAL CONVERTERS: Introduction, basic DAC techniques, weighted resistor DAC, R-2R ladder DAC, inverted R-2R DAC, and IC 1408 DAC, Different types of ADCs–parallel Comparator type ADC, counter type ADC, successive approximation ADC and dual slope ADC.DAC and ADC Specifications, Specifications AD 574 (12 bit ADC). GO TO

Chapter 6: Digital to Analog and Analog to Digital Converters

Chapter

1 1.1

Circuit Configurations for Linear ICs

IntroductIon

Integrated circuit technology makes it possible to realise a large number of virtually identical transistors and the device characteristics can be matched to within 1 per cent of compatibility or less. Such an ability to build devices with nearly identical characteristics has led to the development of special circuit techniques for use in the operational amplifier (abbreviated ‘op-amp’), which is a fundamental building block of analogue circuit design. The op-amp is a direct-coupled, high-gain amplifier to which the feedback is externally connected to control its overall response characteristics. As it is mainly used to perform many linear operations as well as some non-linear functions, it is often called the analogue or linear integrated circuit. The name operational amplifier coins from the application of this type of amplifier for specific electronic circuit functions or operations such as summation, scaling, differentiation and integration and in the analogue computers. This chapter introduces the important circuit configurations of linear ICs and the basic concepts of their design and analysis. The dual input balanced output differential amplifier which forms the first stage of the op-amp followed by the other configurations such as dual input unbalanced output, single ended inputbalanced and unbalanced output are discussed. This chapter includes the basic concept of the cascaded differential amplifier stages for obtaining the desired gain values with direct coupling between stages. The level translator stage as used in op-amps gives an insight into the advantages derived by the IC through elimination of the coupling capacitors.

1.2

dIfferentIal amplIfIers

The function of a differential amplifier is to amplify the difference between two signals. The need for differential amplifier arises in many physical measurements where response from dc to many MHz of frequency is required. This forms the basic input stage of an integrated amplifier. The basic differential amplifier has the following important properties of (i) excellent stability (ii) high versatility (iii) high immunity to interference signals The differential amplifier as a building block of the op-amp has the advantages of (i) lower cost (ii) easier fabrication as IC component (iii) closely matched components Figure 1.1 shows the basic block diagram of a differential amplifier, with two input terminals and one output terminal.

Fig. 1.1

Block diagram of differential amplifier

2

Linear IC Applications

The output signal of the differential amplifier is proportional to the difference between the two input signals. That is, vo = Adm (v1 – v2) If v1 = v2, then the output voltage is zero. A non-zero output voltage vo is obtained when v1 and v2 are not equal. The difference mode input voltage is defined as vdm = v1 – v2 and the common-mode input voltage is defined as vcm =

(v1 + v2 ) 2

These equations show that if v1 = v2, then the differential mode input signal is zero and common-mode input signal is vcm = v1 = v2. For example, if v1 = +20 mV and v2 = –20 mV, then the differential mode voltage is vdm = +40 mV and the common voltage vcm = 0. However, if v1 = 120 mV and v2 = 80 mV, then the differential mode input signal is still vdm = +40 mV, but the common-mode input signal is vcm = 100 mV. For both the sets of input voltages, the output voltage of an ideal differential amplifier would be exactly the same. However, in practice, the common-mode input signal affects the output. Hence, in the design of a differential amplifier, the main aim is to minimise the effect of common-mode input signal.

1.3

dc

and

ac

analysIs of

dual Input Balanced output confIguratIon

The differential amplifiers using BJT are broadly classified into two types, namely, (i) differential BJT amplifier with resistive loading and (ii) differential BJT amplifier with active loading. Figure 1.2 shows the emitter-coupled or source-coupled differential amplifier which forms the input stage of most of the analogue ICs. It is also called the dual input and balanced output differential amplifier. The signals VS1 and VS2 are the two inputs of the differential amplifier, applied to the bases of Q1 and Q2. It is important to note that the performance of the differential amplifier depends on the ideal matching characteristics of the transistor pair Q1 and Q2. The configuration of Fig. 1.2 is called as the dual input balanced output differential amplifier, since 1) it uses two input signals and 2) the output voltage is measured between the two collectors. Note that the two collectors of the differential amplifier are at the same dc potential with respect to ground. The amplifier uses both a positive power supply +VCC and a negative power supply –VEE. Though in practical situations, the power supplies are equal in magnitude, it need not be the case always. It is to be mentioned that these amplifiers operate at dc because appropriate dc level shifting could be obtained without the use of coupling capacitors.

DC Analysis of the Dual Input Balanced Output Configuration The dc analysis begins with the assumption that Q1 and Q2 are ideally matched, and the mismatching effects will be considered later. Also, let us consider b >> 1 so that IE1 @ IC1 and hence,

and

–IE2 ª IC2

VI1 = VBE1 – VBE2 + VI2

In the dc analysis, the operating point values, i.e. VCQ and VCEQ can be obtained for Q1 and Q2. The dc equivalent circuit can be derived by making ac inputs zero as shown in Fig. 1.3.

Circuit Configurations for Linear ICs

Fig. 1.2

Circuit diagram of emitter-coupled differential amplifier

Fig. 1.3

Differential amplifier using BJt

3

4

Linear IC Applications

For matched or identical transistor pairs, we have ∑ RE = RE1˙˙RE2, since RE1 = RE2 ∑ RC1 = RC2 = RC ∑ ˙ VCC˙ = ˙ VEE˙ For a symmetrical circuit with matched transistors, IC1Q = IC2Q and VC1E1Q = VC2E2Q. Hence, the operating point ICQ and VCEQ for any one of the two transistors can be found out. Consider Fig. 1.3 for the dc analysis. Applying KVL to base-emitter loop of Q, we get IBRS + VBE + 2IE RE = VEE As b =

IC for common emitter configuration and IB

≈

Therefore,

IE =

In practical conditions, IE =

>IC Neglecting drop across and applying KVL to the collector-base loop, we get VC = VCC – ICRC and VCE = VC – VE = VCC – ICRC – VE But

VE = –VBE (voltage at the emitter of Q1).

Thus, VCE = VCC – ICRC + VBE The above equation gives VCEQ = VCE when IE @ IC = ICQ, for the given values of VCC and VEE.

AC Analysis of Dual Input Balanced Output Configuration The symmetrical circuit split into two equivalent circuits as shown in Fig. 1.4 will be suitable for ac analysis of an emitter-coupled pair. The differential mode gain Adm, common-mode gain Acm, input resistance Ri and output resistance Ro can be obtained using the h-parameter model of the transistors. Differential mode gain (Adm) For the analysis, assume that the two input signals have a magnitude of vS /2 and differ from each other by 180° phase shift as shown in Fig. 1.4(b). In Fig. 1.4(a), since IE1 = IE2

Circuit Configurations for Linear ICs

Fig. 1.4

5

emitter-coupled pair (a) for Acm analysis and (b) for Adm analysis

and they are out of phase by 180°, they cancel each other. The ac equivalent circuit of Fig. 1.4(b) is shown in Fig. 1.5 and a similar structure may be realised for Q2 also. Applying KVL to the input loop A1, we get

Ib =

vS 2 ( RS + hie )

Applying KVL to loop A2, the output voltage is vo = –hfe Ib RC Therefore, vo = –h fe RC

vS 2 ( RS + hie )

Fig. 1.5

approximate hybrid model neglecting hoe

- h fe RC vo = vS 2 ( RS + hie ) It should be noted that the minus sign in the above equation indicates 180° phase difference between the Êv ˆ input and the output. As the magnitude of the input signals are equal, viz. Á S ˜ and are out of phase by 180°, Ë 2¯ we have vS Ê vS ˆ vid = 2 - ÁË - 2 ˜¯ = vS Therefore, Adm =

- h fe RC vo v = o = vid vS 2 ( RS + hie )

where vs is the differential input voltage.

(1.1)

6

Linear IC Applications

When the output of a differential amplifier is measured with reference to the ground point, it is called an unbalanced output. However, Adm for a balanced case can be derived by considering the balanced output across the two collectors of Q1 and Q2, which are assumed to be perfectly matched. Adm for such a condition is twice the value of Adm obtained for an unbalanced output. Therefore, -2h fe RC - h fe RC = Adm = (1.2) 2 ( RS + hie ) ( RS + hie ) Common-mode gain (Acm) For common-mode analysis, consider that the input signals have the same magnitude vs and are in phase. Therefore, v + v2 v S + v S vic = 1 (1.3) = = vS 2 2 v We know that vo = AcmvS. Hence, Acm = o vS Unlike the previous case, the emitter current is considered for the analysis. The current through RE is 2IE and the source resistance RS is considered negligible.

1

Fig. 1.6

2

hybrid model for common-mode gain

Current through RC = IL (Load current) = – hfe Ib Current through RE = 2IE = 2 (Ib + IL) Applying Kirchhoff’s voltage law to the input side, we get hie + 2 (Ib + hfe Ib) RE = 0 2 vs Ib = hie + 2 (1 + h fe )RE

vs – 2Ib ¥ Therefore,

vo = ILRC = – hfe Ib RC

Circuit Configurations for Linear ICs

7

Substituting for Ib from the above equation, we get Acm =

- h fe RC v0 = vs hie + 2 (1 + h fe )RE

(1.4)

Hence, unlike Adm, Acm is the same for both balanced and unbalanced outputs.

Common-Mode Rejection Ratio (CMRR) The differential amplifier is set to be operating in common-mode configuration when the same voltage is applied to both the inputs, i.e. v1 = v2. One of the main requirements of the differential amplifier is to cancel or reject the noise signal that appears as a common input signal in both the input terminals of the differential amplifier. Hence a figure of merit called the Common-Mode Rejection Ratio (CMRR) is introduced to define the ability of a differential amplifier to reject the common-mode input signal. The CMRR is defined as the ratio of the differential voltage gain Adm to common-mode voltage gain Acm and is generally expressed in terms of decibels. Therefore, CMRR = 20 log10

Adm dB Acm

(1.5)

where Adm is the differential-mode voltage gain and Acm is the common-mode voltage gain. For an ideal differential amplifier, Acm = 0 and hence CMRR = •. In practical cases, since Adm >> Acm, CMRR is high, though finite. Therefore, vo = Adm vid + Acm vic È Acm vic ˘ = Adm vid Í1+ ˙ Î Adm vid ˚ È vic ˘ 1 = Adm vid Í1 + A / A v ˙ ÍÎ ( dm cm ) id ˙˚ È 1 vic ˘ That is, vo = Adm vid Í1 + ˙ Î CMRR vid ˚ where CMRR is not expressed in dB. As CMRR Æ •, the output voltage becomes vo = Admvid Here, the common-mode voltage is nullified to a greater extent. For a balanced case, substituting the results of Adm and Acm, we get RS + hie + 2 RE 1 + h fe CMRR = 20 log10 dB RS + hie

(

)

(

) dB

and for an unbalanced output, CMRR = 20 log10

RS + hie + 2 RE 1 + h fe 2 ( Rs + hie )

Input Impedance Ri The input impedance Ri is defined as the equivalent resistance existing between any one of the inputs and the ground, when the other input is grounded.

8

Linear IC Applications

From Fig. 1.5, Ri =

vS Ib

(1.6)

For a single input, Ri = RS + hie For dual input circuits, Ri = 2(RS + hie)

(1.7)

This input resistance is not dependent on whether the output is balanced or unbalanced.

Output Impedance Ro The output impedance Ro is defined as the equivalent resistance existing between any one of the outputs and ground. Therefore, from Fig. 1.6, it is found that Ro = RC. The common-mode gain decreases as Ro increases. Hence, the CMRR increases as Ro rises. Example 1.1 A differential amplifier has (i) CMRR=1000 and (ii) CMRR = 10000. The first set of inputs is v1 = +100 mV and v2 = –100 mV. The second set of inputs is v1 = 1100 mV and v2 = 900 mV. Calculate the percentage difference in output voltage obtained for the two sets of input voltages and also comment on the result. Solution

In the first set, vid = v1 – v2 =

200

vic =

=0

È 1 vic ˘ vo = Adm vid Í1 + ˙ Î CMRR vid ˚ (1.8) In the second set, vid = v1 - v2 = 1100 mV - 900 mV = 200 mV vic = Hence,

È 1 vic ˘ vo = Adm vid Í1 + ˙ Î CMRR vid ˚ (1.9)

Comparing Eqs (1.8) and (1.9), the output voltages for the two sets of input signals result in a 0.5% difference. Though the difference voltage vid = 200 mV in both the cases, the output is not the same and hence the effect of common-mode voltage vic has the same influence on the output voltage and it decreases with an increase in the CMRR.

Circuit Configurations for Linear ICs

9

When CMRR = 10000, a similar analysis as that of Set 1 gives vo = Set 2—Same as Set 1 Here the output voltages differ by 0.05%. Hence, as the CMRR increases, the difference between the output voltages decreases. Example 1.2 For a dual input, balanced output differential amplifier shown in Fig. 1.17, RC = 2.2 kW, RE = 4.7 kW, RS1 = RS2 = 50 W. The supply voltages are ± 10 V. The hfe for the transistor is 50. Assume silicon transistors and h ie = 1.4 kW. Determine the operating point values, differential gain, common-mode gain and CMRR. Solution

For silicon transistor, ICQ = IE =

VBE = 0.7 V

VEE - VBE 10 - 0.7 = RS 50 2 ¥ 4.7 ¥ 103 + 2 RE + 50 h fe = 0.9893 mA

Fig. 1.7

VCEQ = VCC + VBE – ICQ RC = 10 + 0.7 – 0.9893 ¥ 10–3 ¥ 2.2 ¥ 103 = 8.52 V The operating points VCEQ and ICQ are same for both the transistors. Differential gain

Ad =

Common-mode gain

Ac = =

h fe RC RS + hie

=

50 ¥ 2.2 ¥ 103 50 + 1.4 ¥ 103

= 75.86

h fe RC 2 RE (1 + h fe ) + RS + hie 50 ¥ 2.2 ¥ 103 2 ¥ 4.7 ¥ 103 (1 + 50) + 50 + 1.4 ¥ 103

CMRR =

= 0.22876

Ad 75.86 = = 331.61 Ac 0.22876

CMRR(dB) = 20 log 331.61 = 5.41 dB

1.4

dIfferentIal amplIfIers

wIth

actIve loads

Differential amplifiers are designed with active loads to increase the differential mode voltage gain. The open circuit voltage gain of an op-amp is needed to be as large as possible. This is achieved by cascading the gain stages which increases the phase shift and the amplifier also becomes vulnerable to oscillations. The gain can be increased by using large values of collector resistance.

10

Linear IC Applications

For such a circuit, the voltage gain is given by Adm = - g m RC = -

I C RC VT

To increase the gain, the ICRC product must be made very large. However, there are limitations in IC fabrication such as (i) a large value of resistance needs a large chip area (ii) for a large RC, the quiescent drop across the resistor increases and a large power supply will be required to maintain a given operating current (iii) large monolithic resistor introduces large parasitic capacitances which limits the frequency response of the amplifier (iv) for linear operation of the differential pair, the devices should not be allowed to enter into saturation. This limits the maximum input voltage that can be applied to the bases of transistors Q1 and Q2, the base-collector junction must be allowed to become forward-biased by more than 0.5 V. The large ÊI ˆ value of load resistance produces a large dc voltage drop Á EE ˜ RC , so that the collector voltage Ë 2 ¯ Ê I EE ˆ R and it will be substantially less than the supply voltage VCC. This will will be VC = VCC - Á Ë 2 ˜¯ C reduce the input voltage range of the differential amplifier. Due to the reasons cited above, an active load is preferred in the differential amplifier configurations.

1.4.1 BJT Differential Amplifiers using Active Loads A simple active load circuit for a differential amplifier is the current mirror active load shown in Fig. 1.8. The active load comprises transistors Q3 and Q4, with the transistor Q3 connected as a diode with its base and collector shorted. The circuit is shown to drive a load RL. When an ac input voltage is applied to the differential amplifier, the various currents of the circuit are given by I C 4 = I C 3 = I C1 = ( g mVid ) / 2 where I C4 = I C3 due to current mirror action. Here, IC2 is given by IC2 = - ( g mVid ) /2 We know that the load current IL entering the next stage is IL = IC2 – IC4 Therefore, IL = - ( g mVid ) / 2 - ( g mVid ) / 2 = - g mVid

Fig. 1.8

Bipolar differential amplifier with current mirror active load

Circuit Configurations for Linear ICs

11

Then, the output voltage from the differential amplifier is given by Vo = - I L RL = - ( - g mVid ) RL = g m RLVid The ac voltage gain of the circuit is given by AV =

Vo ( g m RLVid ) = = g m RL Vid Vid

(1.10)

The differential amplifier can amplify the differential input signals and it provides a single-ended output with a ground reference since the load RL is connected to only one output terminal. This is made possible by the use of the current mirror active load. The output resistance Ro of the circuit is that offered by the parallel combination of transistors Q2 (NPN) and Q4 (PNP). It is given by Ro = ro 2 | | ro 4

(1.11)

CMRR of the Differential Amplifier using Active Load The differential amplifier using active load provides high voltage gain to the differential input signal and a single-ended output that is referenced to the ground is obtained. The differential amplifier which provides conversion for a differential signal to a single-ended signal is necVCC essary in differential input and single-ended output amplifiers. The op-amp is one such circuit. Q5 Q4 Figure 1.9 shows the differential-to-single-ended conversion Rbias circuit. The changes in the input common-mode signal cause change IC4 in the bias current IEE due to the finite output resistance of the bias vo IC1 IC2 current source. This induces a change in IC2 and an identical change v1 v2 in IC1. The change in IC1 will then produce a change in the PNP Q2 Q1 load devices, and thereby a change in IC4, which is the collector current Q4. The current IC4 is in such a direction as to cancel the change in IC2. As a result of this, any common-mode input does Q3 Q6 not cause a change in output. The voltage gain of the differential amplifier is independent of the quiescent current IEE. This makes it possible to use very small –VEE value of IEE, as low as 20 mA, while still maintaining a large voltage gain. Small value of IEE is preferred since it results in a small value of bias current and a large value for the input resistance. A limitation Fig. 1.9 Differential to single ended conversion with active load in choosing a small IEE is, however, the fact that it will result in a poor frequency response of the amplifier. When a small value of bias current is required, the best approach is to use a JFET or MOSFET differential amplifier that is operated at comparatively higher values of IEE.

Differential Mode Signal Analysis The ac analysis of the differential amplifier can be made using the circuit model shown in Fig. 1.10. The differential input transistor pair produces equal and opposite currents whose amplitude is given by gm2vid/2 at

12

Linear IC Applications

Fig. 1.10

BJt differential amplifier with

differential mode input

Fig. 1.11

BJt differential amplifier with additional output stages

the collectors of Q1 and Q2. The collector current iC1 is fed by the transistor Q3 and it is mirrored at the output of Q4. Therefore, the total current io flowing through the load resistor RL is given by io = 2

g m 2vid = g m 2vid 2

Then, the output voltage is vo = io RL = ( g m 2 RL ) vid and the differential mode gain Add of the differential amplifier is given by Add =

vo = g m 2 RL vid

(1.12)

This current mirror provides a single-ended output which has a voltage equal to the maximum gain of the common emitter amplifier. The power of the current mirror can be increased by including additional common collector stages at the output of the differential input stage. A bipolar differential amplifier structure with additional stages is shown in Fig. 1.11. The resistance at the output of the differential stage is now given by the parallel combination of transistors Q2 and Q4 and the input resistance is offered by Q5. Then, the equivalent resistance is expressed by Req = ro 2  ro 4  ri 5 ª ri 5 The gain of the differential stage then becomes Adm = g m 2 Req = g m 2 ri 5 = bo5

IC 2 IC 5

(1.13)

Circuit Configurations for Linear ICs

13

Bipolar Differential Amplifier with Commonmode Input Signals Figure 1.12 shows the bipolar differential amplifier applied with a common-mode input signal. The common-mode input signal induces a common-mode current iic in each of the differential transistor pairs Q1 and Q2. The common current iic is given by iic =

gm2 v vic ª ic 1 + 2 g m 2 REE 2 REE

The current flow through transistor Q1 is supplied by the reference current of transistor Q3. This current is replicated or mirrored in transistor Q4 and it produces exactly the same current needed at the collector of Q2. Therefore, the output current and hence the output voltage and common-mode Fig. 1.12 BJt differential amplifier with common-mode input conversion gain Acd are all zero. However, for an actual amplifier, the common-mode gain is determined by small imbalances generated in the bipolar transistor fabrication and the overall asymmetry in the amplifier. One of the main factors is due to the current gain defect in the active load, and it can be minimised through the use of buffered current mirror using the transistor Q5 as shown in Fig. 1.12.

1.5

propertIes

of

other dIfferentIal amplIfIer confIguratIons

The differential amplifier which forms the main circuit configuration of an op-amp can be designed in four different configurations. If we use single input in place of dual input, the circuit is called as a single input configuration. When the output is measured at only one of the collectors of the differential amplifier, then it is called as unbalanced output configuration. This discussion, therefore, leads to the following four configurations of differential amplifiers— 1. 2. 3. 4.

Dual input, balanced output differential amplifier Dual input, unbalanced output differential amplifier Single input, balanced output differential amplifier Single input, unbalanced output differential amplifier

Of these four configurations, the dual input, balanced output configuration with its symmetric structure is the basic differential amplifier.

1.5.1

Dual input, unbalanced output differential amplifier

Taking the output of a differential amplifier as the differential voltage existing between the two collectors results in doubling of the differential gain. It also results in considerable reduction in common-mode gain. However, the possible mismatches between the devices may result in a small fraction of an input common mode signal appearing at the output terminals. A multistage amplifier as existing in an op-amp normally consists of a dual input and balanced output stage. However, the signal is converted to a single output or unbalanced output in the later stages of the cascaded amplifier stages.

14

Linear IC Applications + VCC

RC1

IC2

IC1

RC2 + VO –

RS1

RS2 +

+ VS1 –

Q1

Q2

VI1

+ VI2

–

+ V – S2

–

REE –VEE

Fig. 1.13

Dual input, unbalanced output differential amplifier

Figure 1.13 shows the dual input, unbalanced output differential amplifier with two input signals. However, the output is measured as the voltage at only one of the two collectors with respect to ground. The output is called unbalanced, since the collector at which the output voltage is observed is at some finite dc potential with respect to the ground. In other words, there is some dc potential existing at the collector output even when no input signals are applied. Since the output is measured with reference to the ground point, as an unbalanced output, the differential mode gain Adm for such a condition is half the value of Adm obtained for the dual input, balanced output differential amplifier, as given in Eq. 1.1.

1.5.2

Single input, balanced output differential amplifier

Figure 1.14 shows the single input, balanced output configuration of a differential amplifier. As shown in the figure below, the input is applied to the base of the transistor Q1. The output is measured between the two collectors as a balanced output, since the two collectors are at the same dc potential. The analyses are similar to the previous configuration, since all the configurations have the identical DC equivalent circuit.

Circuit Configurations for Linear ICs

15

+ VCC

RC1

IC2

IC1

RC2

+ V + V oD V + o1 o2 –

–

RS1 + VS1+ –

Q1

Q2

VI1 –

REE –VEE Fig. 1.14

Single input, balanced output differential amplifier

1.5.3 Single input, unbalanced output differential amplifier The configuration depicted in Fig. 1.15 is the single input, unbalanced output differential amplifier configuration. This is not commonly used, due to the fact that it not only requires more components due to the differential structure, but also due to the reason that it yields reduced voltage gain. Additionally, there exists a dc output voltage even without application of any input signal applied to the circuit. In this configuration, the input is applied to the base of one of the transistors and the output is taken from either of the two collectors.

16

Linear IC Applications

+ VCC

RC1

IC1

IC2

RC2 + VO –

RS1 Q1

+ + VS1 –

Q2

VI1 –

REE –VEE Fig. 1.15

1.6

Single input, balanced output differential amplifier

dc couplIng

and

cascaded dIfferentIal amplIfIer stages

When more gain values are required than what can be obtained from a single stage amplifier, many stages of amplifiers can be cascaded by connecting them in series. It is always preferred to have more number of stages with lower individual gain values rather than using a single stage with very high gain values. However, while connecting the output of one stage to the input of the cascading stage, it is vital to ensure that the operating bias conditions of the circuits remain unaffected. This is normally realized by using coupling capacitors between the stages. The coupling capacitors pass ac signals and prevent dc voltages from transferring to the next stage from the current stage. This avoids the dc voltages of the current stage upsetting the next stage. However, the capacitive coupling incurs two major limitations, viz. each coupling capacitor connected between stages produces a low frequency cut-off value, which curtails the low frequency response of the amplifier and secondly, the presence of an integrated capacitor in the IC is more expensive since it requires large amount of chip area, which makes the option not suitable for manufacturing of denser integrated circuits. Therefore, a multistage or cascaded differential amplifier with the desired gain values can be realized using direct connection between the successive stages of the differential amplifiers. The primary advantage of direct coupling between stages is that it alleviates the lower cut off frequency limits imposed by the coupling capacitors. Therefore such amplifiers are capable of amplifying signals of zero frequency or the dc, in addition to the amplification of ac input signals.

Circuit Configurations for Linear ICs

17

VCC = 10 V

RC1

RC2

2.2KΩ

2.2KΩ

RC3

1.2KΩ

RC4

1.2KΩ Singal ended output Vo

Noninverting input

Vo1 Q2

Q1

Vid Inverting input

RE1

Q4

Q3

4.7KΩ

R´E

R´E

100KΩ

100KΩ

15KΩ

RE2

–VEE = 10 V

Fig. 1.16

Cascaded Differential amplifier

Figure 1.16 shows a typical or cascaded two stage differential amplifier, which is commonly employed as the input stage of the BJT operational amplifiers. The differential amplifiers are direct connected in series. The first differential amplifier stage is a dual input, balanced output stage followed by the dual input, unbalanced output second differential amplifier stage. The two collector resistances, RC1 and RC2 of the first stage equal each other, with the emitter resistance RE1 connected to the negative power supply. Since the transistors, Q1 and Q2 are perfectly matched, the emitter resistance RE1 carries a current of 2IE1 with the emitter current of each transistor being IE1. The output of the balanced output stage is applied to the second stage. The second differential stage employs two swamping resistances R′E and an emitter resistance RE2, which carries a current of 2IE3. Since the transistors Q3 and Q4 are matched devices, the emitter currents can be considered equal. The unbalanced output is taken from the collector of the second stage as shown. The primary requirement while designing such cascaded amplifier stages is the perfect matching of the devices and the resistance values. To study the operation of the cascaded stage, typical parameters can be calculated as discussed below. Example 1.3 Let us consider hFE = 100 and VBE = 0.715V for the transistors used in the cascaded differential amplifier circuit shown in Fig. 1.16. Calculate the following:

(i). The collector current and collector to emitter voltage for the transistors (ii). The overall voltage gain of the circuit (iii).The input resistance (iv).The output resistance

18

Linear IC Applications

Solutions

(i).To find out the collector current and collector to emitter voltage of Q1 and Q2, let us consider that both the inverting and non-inverting inputs are grounded. The collector current IC ≈ IE and the currents can be calculated as given by IE1 = =

VEE – VBE 2RE1 + Rin/βdc 10 – 0.715 = 0.988 mA 2 × 4.7kΩ + 0

Therefore, IC1 = IC2 = 0.988 mA The voltage between the collector and emitter of Q1 and Q2 can be calculated as follows: VC1 = VCC = –RC1IC1 = 10 – (2.2KΩ) (0.988mA) = 7.83V and VC1 = VC2; Thus, VC2 = 7.83 V The voltage at the emitter of Q1 and Q2 is –0.715 V. Therefore, VCE1 = VCE 2 = VC1 – VE1 = 7.83 V + 0.715 V = 8.545 V. The collector current of transistors Q3 and Q4 can be found out using Kirchhoff’s voltage equation considering the base-emitter loop of transistor Q3. VCC – RC 2 IC 2 = VBE 3 – R′EIC 3 – RE2(2IE 3) + VBE = 0 10 – (2.2 kΩ) (0.988 mA) – 0.715 – (100) (IE 3) – (30 kΩ) IE 3 + 10 = 0 10 – 2.17 – 0.715 + 10 – 30.1kΩ) IE 3 = 0 IE3 =

17.12 = 0.569 mA = IE4 30.1 kΩ

Thus, the voltage at the collector terminal of Q3 and Q4 is given by VC3 = VC4 = VCC – RC 3 IC 3 = 10 – (1.2 kΩ) (0.569 mA) = 9.32 V Hence, we can find that VCE 3 = VVCE 4 = VC3 – VE 3 = 9.32 – 7.12 = 2.2 V Thus, for Q1 and Q2: ICQ = 0.988 mA VCEQ = 8.545 V and for Q3 and Q4: ICQ = 0.569 mA VCEQ = 2.2 V It may be noted that the output VC 4 is at 9.32 V.

Circuit Configurations for Linear ICs

19

(ii). To calculate the overall voltage gain of the circuit, let us first find out the ac emitter emitter resistance r′e of both the stages and then the overall voltage gain. re1′ =

25 mV 25 mV = = 25.3Ω = re2′ IE1 0.988 mA

re3′ =

25 mV 25 mV = = 43.94Ω = re4′ IE3 0.569 mA

The first differential amplifier stage being a dual input, balanced output type, its voltage gain is given by V R || R Ad1 = o1 = C1 i2 Vid re1 Here, Ri2 = input resistance of the second stage = 2βac (re3 + R′E) = (200)(143.94) = 28.79 kΩ Ad1 =

2.2 kΩ || 28.79 kΩ = 80.78 25.3

The second stage is a dual input, unbalanced output differential amplifier and it uses a swamping resistance R’E. Thus, its voltage gain is given by Ad2 =

Vo RC4 1.2 kΩ = = 4.14 Vo1 2(R′E + re4) 287.88

Therefore, the overall voltage gain of the cascaded differential amplifier stages is Ad = (Ad1) (Ad1) = (80.78) (4.17) 336.85 This proves the fact that the higher voltage gain values can be realized by cascading the differential amplifier stages. (iii).The input resistance of the cascaded differential amplifier stages is the input resistance of the first stage. In other words, Ri = 2βac (re1) = (200) (25.3) = 5.06 kΩ (iv).The output resistance of the cascaded differential amplifier is defined by the output resistance of the second differential amplifier stage. Therefore, RO = RC = 1.2 kΩ

20

Linear IC Applications Typical op-amp stages + VCC

non inv +

inv -

o/p

– VEE Input Stage

Intermediate Stage

Fig. 1.17

Level Translator

Output Stage

Stages of a typical op-amp

Figure 1.17 shows here a complete op-amp circuit having input from different amplifiers and with balanced output, intermediate stages with unbalanced output, level shifter and an output amplifier.

1.7

level translators

or

dc level shIft stages

Fabrication of large value coupling capacitors, such as those needed for dc coupling in broadband amplifiers is not easy in IC technology. The NPN common-emitter gain stage always produces a dc level that is higher than the dc level at the input. When a number of gain stages are cascaded for larger gain values, the dc level at the output rapidly builds up reaching the supply voltages. This results in poor linearity and amplitude limitation, or clipping of output voltage swing. This problem can be overcome by using a level shift stage between each of the gain stages so that the output dc level is shifted towards the negative supply. This circuit also helps in preventing inter-stage loading effects with its inherent characteristics of high input impedance and relatively low output impedance values. A typical dc level shift stage used in op-amp design is shown in Fig. 1.18, employing a common collector stage to buffer the input signal. This provides an easier means of shifting the input level Vi to a more negative dc level Vo.

+VCC Vi Q1 E I

R1 Vo R2

Fig. 1.18

a typical level shift stage circuit

Circuit Configurations for Linear ICs

21

To obtain the output value Vo , consider a current I flowing through the emitter branch of Q1 which is given by I=

VE R1 + R2

where VE is the voltage at the emitter of Q1 at node E. Therefore, the output voltage Vo = Here,

+VCC

VE ¥ R2 R1 + R2

Vi Q1

VE = Vi – VBE1

Hence, we have Vo =

DB Vo

(Vi - VBE2 ) R2 ( R1 + R2 )

R

This form of a level shift circuit has a main drawback. The ac gain of the circuit starts reducing as R2 is decreased for improving the net dc Fig. 1.19 Level shift stage using avalanche diode level shift. Moreover, its output impedance is also comparatively high. This limitation makes the level shift stage using avalanche diode an attractive alternative circuit for shifting the dc level. It is shown in Fig. 1.19. For this circuit, the net dc level shift is given by Vi – Vo = VBE + VB where VB is the breakdown voltage of the avalanche diode DB. This circuit may not be suitable for low level ac signals because of the excess noise generated by the diode DB. Further, the value of VB obtainable in ICs is limited. However, the voltage gain for the stage is nearly unity if the bulk resistance of DB is made negligible as compared with R. Another circuit for dc level shift applications is shown in Fig. 1.20. The transistor Q2 connected with resistors R1 and R2 form a VBE multiplier circuit. Therefore, the voltage between nodes E and F is given by

+VCC

Vi E R1

Q2 R2 F R3

R ˆ Ê R + R1 ˆ Ê = VBE Á1 + 1 ˜ VEF = VBE Á 2 ˜ R2 ¯ Ë R2 ¯ Ë However, it can be inferred from Fig. 1.20 that Vo = Vi – (VBE + VEF) È R ˆ˘ Ê Therefore, Vo = Vi - ÍVBE + VBE Á1 + 1 ˜ ˙ R Ë 2 ¯˚ Î or

Vi – Vo = VBE (2 + R1/R2)

Q1

Fig. 1.20

Vo

DC level shift circuit configuration

22

Linear IC Applications

Figure 1.21 shows another level shifter configuration using a lateral PNP and vertical NPN transistor configuration. The output dc voltage obtained by the level shift circuit is given by Vo =

R2 (VCC - VBE - Vi ) R1

where VBE is base to emitter voltage of the composite PNP-NPN transistor connection. The ac voltage gain of the circuit is given by Av @ –

R2 R1

Fig. 1.21

DC level stage using transistor arrangement

Review Questions 1.1 What are the basic building blocks of an A op-amp?

1.14 What is the main advantage of an active load?

1.2 List some important circuit configurations B used in linear ICs.

B 1.15 What is meant by matched transistors? 1.16 Explain how a differential mode output signal B is generated in a differential amplifier. 1.17 Explain how a common-mode output signal B is generated in a differential amplifier. A 1.18 Define CMRR. What is its ideal value?

1.3 Explain the operation of a Widlar current A source with a neat diagram. 1.4 With a circuit diagram, explain how dc level B shifting operation is performed. 1.5 What is a level shifter? Why is it needed? B 1.6 What is a level translator circuit? Why is it used with the cascaded differential amplifier B stages? A 1.7 What is a differential amplifier? 1.8 Draw the circuit of any one type of differential amplifier. Derive the expression for differential B voltage gain. 1.9 Draw the circuit diagram of an emittercoupled differential amplifier and explain the B operation. 1.10 Perform dc analysis and ac analysis of an B emitter-coupled pair. 1.11 State and explain common-mode rejection A ratio (CMRR). 1.12 Define the terms common-mode gain and A differential-mode gain. 1.13 Discuss the operation of a BJT, based active A load using a neat sketch.

B

1.19 Draw the dc transfer characteristics of a BJT differential amplifier and comment on it. B

1.20 Define common-mode and differential mode A input voltages. 1.21 Draw the half circuit models for an emittercoupled differential amplifier and explain. B 1.22 Find the Q-point for the differential amplifier C shown in Fig. 1.7. Assume b = 200. 1.23 A differential amplifier has (i) CMRR = 1000 and (ii) CMRR = 10000. The first set of inputs is v1 = +200 mV and v2 = –200 m V. The second set of inputs is v1 = 1200 mV and v2 = 800 mV. Compare the levels of output voltages obtained for the two sets of input voltages and comment on the performance of differential amplifier based on the results. C

Circuit Configurations for Linear ICs

23

Objective-Type Questions 1.1 In an NPN transistor, perfect biasing is achieved when (a) base is positive with respect to collector (b) base is positive with respect to emitter (c) base is positive with respect to both emitter and collector B (d) none of these 1.2 In a transistor, (a) collector is always reverse biased (b) collector is always forward biased (c) emitter is always reverse biased B (d) none of these 1.3 The amount of emitted current that forms the collector current is (a) IE – aIE (b) IE + aIE A (c) IE – bIB (d) aIE 1.4 The dynamic output conductance is given by DI o 1 (a) (b) ro DVo Io (c) (d) all of these B VA 1.5 The dc level shift stages are needed for (a) shifting the output dc level towards the positive supply (b) shifting the output dc level towards the negative supply (c) providing both positive and negative offsets B (d) none of these 1.6 A differential amplifier can be used as a limiter since (a) linear region of its transfer characteristics ends abruptly for a specific input value (b) gm is proportional to IE

(c) CMRR can be made very large (d) IE can be made constant

1.7 The CMRR of a differential amplifier defines the ability to (a) reject the noise signal appearing in both the input terminals (b) reject the common dc signal appearing in both the input terminals (c) reject the common ac signal appearing in both the input terminals C (d) all of these 1.8 In a difference amplifier, a large emitter resistance results in the reduction of (a) CMRR of the amplifier (b) differential mode gain (c) common-mode gain B (d) all of these 1.9 Active loads (a) increase the differential mode voltage gain (b) substitute the large value of resistances needed C (c) avoid parasitic capacitances (d) all of these 1.10 An op-amp is (a) a differential amplifier (b) a direct coupled amplifier (c) a low impedance amplifier B (d) a high gain push-pull amplifier 1.11 An op-amp can be used with (a) dc signals only (b) ac signals only (c) both ac and dc signals A (d) neither ac nor dc signals

Answers to Objective-Type Questions 1.1 (b) 1.6 (a) 1.11 (d)

1.2 (a) 1.7 (d)

1.3 (d) 1.8 (c)

C

1.4 (d) 1.9 (d)

1.5 (b) 1.10 (b)

Chapter

2 2.1

Operational Amplifiers

IntroductIon

Integrated circuit technology makes it possible to realise a large number of virtually identical transistors and the device characteristics can be matched to within 1% of compatibility or less. Such an ability to build devices with nearly identical characteristics has led to the development of special circuit techniques for use in the operational amplifier (abbreviated op-amp), which is a fundamental building block of analog circuit design. The op-amp is a direct-coupled high-gain amplifier to which the feedback is externally connected to control its overall response characteristics. Since it is mainly used to perform many linear operations as well as some non-linear functions, it is often called the analog or linear integrated circuit. The name operational amplifier coins from the application of this type of amplifier for specific electronic circuit functions or operations such as summation, scaling, differentiation and integration, and in analog computers. This chapter deals with op-amp specifications, DC and AC characteristics of op-amps, introduction to op-amp IC 741, measurement of op-amp parameters and frequency compensation techniques.

2.2

Integrated cIrcuIts

Integrated circuit (IC) is the result of relentless developments in the characteristics and miniaturisation of solid-state devices and components. When solid-state devices such as transistors and diodes were invented, they replaced vacuum tubes. Similarly, the new generation of solid-state electronics, i.e. integrated circuits replaced the discrete components, such as resistors, capacitors, diodes, transistors and FETs. In a discrete circuit, the components are separable, while the components of an integrated circuit are physically inseparable. Most of the ICs are silicon based chips with devices such as transistors, resistors and capacitors fabricated in them. A single silicon chip can contain a few devices or many millions of devices based on the application and its complexity. Large and complex circuits can be reduced to a small size through the IC technology, which has made the field of electronics ubiquitous across the wide spectrum of applications ranging from the satellites, communications and automobiles to the miniature wireless sensor nodes and networks. The following are the advantages of ICs over discrete components: (i) Small size (ii) Improved performance and more complex circuits (iii) Lower cost (iv) High reliability and ruggedness (v) Lower power consumption (vi) Less vulnerability to noise parameter variations (vii) Easy troubleshooting by replacement

Operational Amplifiers

25

(viii) Easier system design capability (ix) Standard packaging (x) Increased speed performance (xi) Low weight and portability (xii) Battery operation possible due to lower power supply requirement The limitations of integrated circuits are as follows: (i) As the IC is small in size, heat dissipation from the IC becomes difficult, which can hinder the operation of the IC at high frequencies. Increasing functionality and the current requirements can produce enough heat which may even destroy the device. (ii) At present, the coils, inductors and transformers cannot be produced in IC form.

2.3

classIfIcatIon, Package tyPes

and

temPerature

ranges

Classification based on complexity The IC technology has been advancing rapidly, resulting in increased complexity and more functionality of the circuits fabricated. The ICs can be categorised based on their complexity levels as shown in Table 2.1. Table 2.1

Classification of /Cs

Type of IC

No. of Logic Gates

No. of Transistors

Small Scale Integration (SSI)

3–30 per chip approx.

100

Medium Scale Integration (MSI)

30–300 per chip approx.

100–1,000

Large Scale Integration (LSI)

300–3,000 per chip approx.

1,000–20,000

Very Large Scale Integration (VLSI)

More than 3,000 per chip

20,000–10,00,000

Ultra Large Scale Integration (ULSI)

–

106–107

Giant Scale Integration (GSI)

–

More than 107

Integrated circuits are classified into two general categories: (i) Linear ICs and (ii) Digital ICs. The linear integrated circuits operate with continuous signals and are used to develop electronic circuits such as amplifiers, voltage comparators, etc. On the other hand, digital integrated circuits operate with binary signals and are invariably manufactured as integrated circuits.

Classification based on manufacturing process The ICs can be classified as shown in Fig. 1.1. On the basis of the fabrication process used, ICs can be classified as monolithic circuits and hybrid circuits. The word monolithic means single stone, and as the name implies, the entire circuit is fabricated on a single chip of semiconductor. In monolithic integrated circuits, the components like transistors, diodes, resistors and capacitors are formed simultaneously by diffusion process steps. Then, the process of metallisation is used in interconnecting these components to form the required circuit. The dielectric or PN junction is used to provide electrical isolation in monolithic ICs. The monolithic circuit technology is ideal for applications requiring identical characteristics of components in very large quantities. Therefore, they cost less and provide a higher order of reliability. A hybrid circuit contains individual component parts attached to a ceramic substrate. The components are interconnected by the use of either metallisation patterns or bonding wires. The hybrid circuits improve

26

Linear IC Applications

the circuit performance, since passive component values can be trimmed to precision at higher values. This technology is more suitable to custom-designed circuits of small volume fabrications. Hybrid ICs are categorised as thin film and thick film, based on the method used to form the resistors, capacitors, and related interconnections on the substrate. Integrated Circuits

Hybrid Circuits

Monolithic Circuits

Bipolar

PN junction isolation

Unipolar

Dielectric isolation Fig. 2.1

MOSFET

FinFET

JFET

Classification of ICs

Classification based on devices The Metal Oxide Semiconductor (MOS) IC families can be classified into the following based on the devices: (i) PMOS or P-channel MOSFETs (ii) NMOS or N-channel MOSFETs (iii) CMOS Complementary MOSFETs

Classification based on the type of signals processed The ICs can more relevantly be classified as (i) linear or analog ICs, (ii) digital ICs and (iii) mixed signal ICs based on the type and combinations of signals they process. The classification is made based on the treatment of the signal. An analog signal is the one that is defined over a continuous range of time, while, the digital signal is defined only at discrete points of time, by discrete values of amplitude. The linear ICs such as op-amps, voltage regulators, voltage comparators and timers are related to all the design phases of electronics in which signals are represented by continuous or analog quantities. The digital ICs, such as, the logic gates, flip-flops, counters, digital clock chips, calculator chips, memory chips and microprocessors deal with discrete quantities. In a digital IC, the information is represented by binary digits and involves logic and memory. The mixed signal ICs involve both the analog and the digital signal processing. Classification based on the types of packaging of the IC The ICs are manufactured and made available in the following types of packages based on the parameter requirements of the user. The generic shape and structure of some of the IC packages are shown in Figs. 2.2 (a) to (g). (i) Top-hat (TO) Package (ii) Dual-in-Line Package (DIP) (iii) Dual-in-Line Plastic Package

Operational Amplifiers

(iv) (v) (vi) (vii)

Leadless Chip Carrier (LCC) Plastic Leaded Chip Carrier (PLCC) Plastic Quad Flat Pack (PQFP) Plastic Pin Grid Array (PPGA) Package

(a)

(b) 8

7

6

5

(c)

4

9

3

10

2

11

1

12

20

13

19

14

15

16

17

18

(d)

(f)

Fig. 2.2

27

(e)

(g)

(a) Top-hat (TO) package, (b) Flat package, (c) Dual-in-Line package, (d) Leadless Chip Carrier package, (e) Plastic Leaded Chi Carrier, (f) Plastic Quad Flat package and (g) Plastic Pin Grid Array package

Classification based on temperature range of operation The integrated circuit grade or temperature grade is a method by which ICs are classified based on their operating temperature. It is typically based on the use of the particular chip in a certain environment. IC components usually fall into one of the four categories, namely, 1) Commercial Grade, 2) Industrial Grade, 3) Automotive Grade and 4) Military Grade. While commercial-grade are the most commonly used parts, the demand from the military, aerospace, automotive, and other applications like exploration of oil/ gas identified the requirement for additional grades to indicate the harsher operating conditions. Because of their limited availability, the military grade parts are usually much harder to purchase and bought based on the request and order to manufacturers.

28

Linear IC Applications

Table 2.2 below shows the temperature Grades and the temperature ranges. Table 2.2

Temperature Grades and Associated Temperature Ranges

Temperature Grade

Temperature Range

Commercial

0°C to 85°C

Industrial

−40°C to 100°C

Extended

−40°C to 125°C

Military

−55°C to 125°C

Automotive

−40°C to 125°C

cIrcuIt symbol

2.4

of an

oPeratIonal amPlIfIer

The circuit symbol of an op-amp is in the form of a triangle as shown in Fig. 2.3. The device has two input terminals and one output terminal. The terminal marked as (–) is called the inverting input terminal and the terminal marked as (+) is called as the non-inverting input terminal. Figure 2.4 shows the op-amp with positive voltage supply V + and a negative voltage supply V – terminals. Inverting input terminal

v+ –

Output terminal

Inverting input terminal

–

Output terminal

+ Non inverting input terminal

+ Non inverting input terminal

Fig. 2.3

2.5

Op-amp circuit symbol

Fig. 2.4

v–

Op-amp circuit symbol with positive and negative voltage supply terminals

oP-amP Power suPPlIes

The op-amps use a dc supply voltage, typically from a few volts up to 30 V. The circuits discussed in this text assume that all op-amps are powered from dual or split power supply sources. The power supplies are normally equal in magnitude with opposite polarity and the centre tap of the dual supplies is connected to ground terminal of the circuit. Thus, any input sources connected to ground become automatically referenced to the centre of the supply voltages, so that the output voltage is automatically referenced to ground. While using a perfect DC voltage source, the output of the op-amp is solely set by its inputs.

2.5.1

Dual Voltage Power Supplies

The power supply terminals of the IC are connected to two voltage sources of value ±5 V to ±22 V. The typical values of the power supply are normally ±15 V. The common terminal of the positive and negative voltage sources is connected to a common reference point or the ground terminal. The equivalent representation for the power supply connection with the op-amp is shown in Fig. 2.5(a). A single power supply can also be employed as shown in Fig. 2.5(b) through Fig. 2.5(d). The resistors R shown in Fig. 2.5(b) are chosen to be larger than 10 kW, so that, no appreciable current flows through them. The capacitors can be of any value in the range of 0.01 mF to 10 mF. They provide decoupling of the power supply noise.

Operational Amplifiers

Fig. 2.5

29

Power supply connections

The power supply circuit shown in Fig. 2.5(c) uses Zener diodes to provide symmetrical supply voltages. The value of Rs is selected so that, it provides enough current for the Zener diode to operate in its avalanche region of operation. A potentiometer is used in Fig. 2.5(d) to achieve the V + and V – voltages. The diodes D1 and D2 provide protection against any accidental reversal of power supply voltages.

2.5.2 Single Voltage Power Supplies Figure 2.6 below shows a single-supply op-amp circuit with its input voltage referenced to the ground. When the input is referenced to ground, the single supply op-amp circuits exhibit a large input common-mode voltage. The input voltage is referenced to the lower power supply rail rather than the midpoint of the dual supplies. This circuit does not operate when the input voltage is positive since the output voltage must go to a negative voltage, which is not possible with a positive supply. RG

RF +V

VIN _ +

Fig. 2.6

Single-supply op-amp circuit

VOUT

30

Linear IC Applications

The requirement of today’s world being portable and battery-powered equipments, the op-amps powered by single power supply is in practice. The single supply systems do not have the useful ground reference that the dual power supply systems have. Hence, right biasing must be employed to ensure that the output voltage swings between the appropriate voltage levels. This requirement for biasing the op-amp inputs to achieve the desired output voltage swing complicates single-supply designs. The op-amps, such as the IC 741 can be powered by single voltage power supply as shown in the next section. Sometimes, a situation may arise, where a small amount of analog circuit is used along with a predominantly Fig. 2.7 Non-inverting amplifier with single-supply digital circuit, which operates with a unipolar supply bias voltage. In such cases, the op-amp can be configured to operate with a +30 V unipolar supply, producing a similar performance. The basic idea of such a circuit is biasing the input at one-half of the total supply voltage, which can be done with a simple voltage divider. Fig. 2.7 shows a non-inverting voltage amplifier circuit using single-supply bias. A coupling capacitor C1 is used to isolate the dc biasing potential from the driving stage. The dc gain is set to unity without affecting the ac gain using capacitor C3, placed in series with resistor R4. Resistors R2 and R3 decide the 50 percent bias point and their parallel combination sets the input impedance also. Resistors R4 and R5 are used for preventing unwanted discharge of coupling capacitors C1 and C2 into the op-amp. The voltage gain of the circuit is given by Rf ˆ Ê ACL = Á1 + R1 ˜¯ Ë the same as that of dual supply circuit for the frequency range in which capacitive reactances can be neglected. Fig. 2.8 shows the single-supply inverting voltage amplifier. The input resistance is set by R1. The closedloop gain ACL is given by -Rf v ACL = o = vi R1

Fig. 2.8

Inverting amplifier with singlesupply bias

To achieve a relatively flat response over the desired frequency range, the reactances offered by the two capacitors C1 and C2 must be less than the respective series resistances R1 and RL at the lowest signal frequency. As the frequency reduces below a certain range, the series reactance of C1 increases and the effective gain reduces. At the same time, the series reactance of output capacitance C3 increases causing a further loss in gain. Hence, both the capacitors decide the low frequency roll-off of the gain. The lowest frequency fL is set 1 1 by f L £ and f L ≥ 2p R C . 2p R1C1 L 2

Operational Amplifiers

2.6

basIc block dIagram of

an

31

op-amP

The op-amp is a direct-coupled high-gain amplifier to which the feedback is externally connected to control its overall response characteristics. Since it is mainly used to perform many linear operations as well as some non-linear functions, it is often called the analog or linear integrated circuit. The name operational amplifier coins from the application of this type of amplifier for specific electronic circuit functions or operations such as summation, scaling, differentiation and integration, and in analog computers. Dual-input unbalanced output differential amplifier

Non-inverting input

Intermediate stage

Input stage

Complementary symmetry pushpull amplifier

Level shifting stage

Output stage

Output

Inverting input Dual-input balanced output differential amplifier

Fig. 2.9

Emitter follower with constant current source

Basic block diagram of operational amplifiers

Figure 2.9 shows the general block diagram of a typical op-amp. The major blocks are differential amplifiers, intermediate stages of differential or dual input and single output amplifiers, dc level shift circuits and output stages. The dual input balanced output differential amplifier stage provides most of the voltage gain of the amplifier and it defines the input resistance of the op-amp. Basic requirements of the input stage are as follows • Maximum input resistance (Typically more than 10 MΩ) • Low input bias current (Typically less than few 100s of mA) • Small input voltage offset (Typically less than few mV) • High Common Mode Rejection Ratio (CMRR) (Typically more than 70dB) • High differential input voltage range (Typically More than V+/2, where V+ is the positive supply voltage) • High Common mode voltage range (Typically more than V+/2) • High open-loop voltage gain value (Typically more than 104) The intermediate stage of op-amp is another differential amplifier which is driven by the output of the first stage. This is usually of dual input unbalanced output as shown in Fig. 2.9. The op-amps employs direct coupling for avoiding the use of coupling capacitors which necessitate huge silicon area during IC manufacturing. Hence, the DC voltage level at the output of the intermediate gain stage is well above the ground potential. This escalation in DC level inclines to shift the operating point of the successive stages. This limits the output voltage swing and may even distort the output signal. Thus, the level shifting circuit or level translator is employed to shift the DC level at the output down to zero with respect to the ground. An emitter follower with voltage divider is the simplest form of level translator. The output stage is generally a push pull complementary amplifier. This output stage increases the output voltage swing and it also raises the current sourcing capability of the op-amp. Additionally, it provides low output resistance required for the op-amp.

32

Linear IC Applications

Basic requirements of the output stage are as follows: • Large output voltage swing capability • Large output current swing capability • Low output resistance value • Minimum standby power • Short circuit protection

2.7

Ideal oP-amP sPecIfIcatIons

The ideal operational amplifier is a differential input and single-ended output device. The equivalent circuit and the transfer characteristics of an ideal op-amp are shown in Figs 2.10(a) and (b). The input impedance of an ideal op-amp is infinite and it means that input current is zero. The output terminal of the op-amp acts as the output of an ideal voltage source which means that its small signal output impedance is zero. As shown in Fig. 2.10(a), G represents the differential gain of the op-amp and the output voltage vo is given by vo = G(v1 – v2) = vid

(2.1)

where v1 is the input at the non-inverting input terminal, v2 is the input at the inverting input terminal and vid is the difference between v1 and v2.

G G

Fig. 2.10

Ideal op-amp: (a) Equivalent circuit (b) Transfer characteristics

Equation (2.1) identifies that the output is in phase with v1 and out of phase with v2. The transfer characteristics of an op-amp are shown in Fig. 2.10(b). The ideal op-amp produces an output in response only to the difference between the input signals v1 and v2. Thus, it maintains an ideal zero output signal for v1 = v2. When v1 π v2, there exists a common-mode input signal, in response to which the ideal op-amp produces a zero output signal. This characteristic is called the common-mode rejection. The op-amp consists of transistors biased in the active region with the voltages V + (or +VCC) and V– (or –VEE). Therefore, the output voltage is limited by these power supply voltage levels. When the output voltage vo reaches V+, it saturates and is nearly equal to V +. Similarly, when the output voltage vo approaches V –, it saturates at a voltage nearly equal to V–. The difference between the positive saturation level and positive supply voltage and the difference between the negative saturation level and the negative supply voltage is approximately 1 to 2 V as shown in Fig. 2.10(b). This concept is discussed in detail in Section 2.8. The ideal op-amp identifies the difference between two input signals that are applied at the inverting and non-inverting input terminals and amplifies the difference so obtained to produce an output signal. The output voltage is the voltage at the output terminal measured with respect to ground.

Operational Amplifiers

33

The characteristics of an ideal op-amp are (i) Infinite input resistance, Ri = • (ii) Zero output resistance, Ro = 0 (iii) Infinite voltage gain, G = • (iv) Infinite bandwidth, BW = • (v) Infinite common-mode rejection ratio, CMRR = • (vi) Infinite slew rate, SR = • (vii) Zero offset, i.e. when v1 = v2, vo = 0 (viii) Characteristics do not drift with temperature It can be observed that (i) An ideal op-amp allows zero current to enter into its input terminals, i.e. i1 = i2 = 0. Due to infinite input impedance, any signal with source impedance can drive the op-amp without getting inflicted with any loading effect. (ii) The gain of the ideal op-amp is infinite. Hence, the voltage between the inverting and non-inverting terminals is essentially zero for a finite output voltage. (iii) Since Ro = 0, the output voltage vo is independent of the output current drawn from the op-amp. This means that the output can drive an infinite number of output devices of any impedance value. If the input impedance is high and output impedance is low with respect to the feedback impedances connected externally, and if the voltage gain is sufficiently high, then the resulting amplifier performance becomes solely determined by the external feedback components.

2.8

PractIcal oP-amP sPecIfIcatIons

A practical op-amp is not ideal. The equivalent circuit of a practical op-amp is shown in Fig. 2.11. The equivalent circuit is useful in analyzing the operating principles of op-amps and in observing the effects of feedback. For the practical op-amp, the open-loop gain A0 π •, the input resistance Ri π • and the output resistance Ro π 0. It can be observed from Fig. 2.11 that the output is a voltage controlled voltage source, with vo = A0 vid as the equivalent Thevenin’s voltage source and Ro of Thevenin’s equivalent resistance looking back into the output terminal of the op-amp. The output voltage is given by vo = A0 vid = A0 (v1 – v2) where A0 is the large-signal voltage gain and vid is the difference between the input voltages v1 and v2. From the above equation, it is evident that the opamp amplifies the difference between the two input voltages and it does not amplify the input voltages themselves. The output voltage is directly proportional to the algebraic difference between the two input voltages. The polarity of the output voltage depends on the polarity of the difference between the input voltages. The use of an op-amp is greatly enhanced by the negative feedback. The feedback helps in avoiding saturation of the output and the circuit operates in a linear manner.

(2.2)

A0vid

Fig. 2.11

A0vid

Equivalent circuit of a practical op-amp

34

Linear IC Applications

Output Saturation The dual supply voltages V + and V – set the upper and lower bounds on the output characteristic of the op-amp. The input-output voltage transfer characteristics of Fig. 2.10(b) show the regions of operation and approximate model of op-amp in the respective regions. (i) In the linear region, the curve is approximately a straight line and its slope indicates the open-loop gain A0. When A0 is very large, the curve becomes steeper, and nearly aligns itself with the vertical axis. For a voltage of vid = 1 mV and A0 = 2 ¥ 105, vo = A0 ¥ vid = 2 ¥ 105 ¥ 1 ¥ 10–6 = 0.2 V. Hence, the op-amp is modelled with a dependent source of value A0vid as shown in Fig. 2.11. (ii) As vid increases, vo rises proportionally, until a point is reached when the internal transistors saturate that causes the characteristics to flatten out. This region is called the positive saturation region and in this region, vo no longer depends on vid. Then, the op-amp behaves as an independent source of value +Vsat. Similarly, the negative saturation occurs when vid rises in the negative direction resulting in the op-amp acting as an independent source of value –Vsat. For bipolar op-amps, such as IC 741, +Vsat and –Vsat are typically ±13 V which is about 2 V below VCC and VEE , of value ±15 V. When the op-amp is used with negative feedback, the operation must be confined within the linear region of operation.

2.9

dc characterIstIcs

of

oP-amP

An ideal operational amplifier draws no current from the signal source and its response is independent of the temperature variations. However, a practical op-amp gets affected by the environmental and process parameter variations. The current is indeed, taken from the source into the input of op-amp and the two inputs respond differently to the input voltage and current. This happens due to the inherent mismatch among the transistors. Therefore, the non-ideal dc performance characteristics of the op-amp are: (i) Input bias current (ii) Input offset current (iii) Input offset voltage (iv) Thermal drift

2.9.1

Input Bias Current

The input bias current is the average of the currents that flow into the inverting and non-inverting input terminals of an op-amp. The input bias current affects all applications of op-amps. For the op-amp to function, it is necessary to supply a small current, of the order of picoamperes for op-amps with FET inputs and microamperes for junction transistor type inputs. When reduced input bias currents are achieved, the possible imbalances in the circuit will be minimised. The IC 741 has an input bias current of 80 nA. The input of the op-amp is a differential amplifier comprising either BJT or FET. In both the cases, the input transistors are biased into their linear regions of operation by inducing current into the bases of BJTs or supplying voltages to the gates of FETs with the use of external circuitry. It is assumed that no current is drawn into the input terminals of an ideal op-amp. However, a small value of dc current does enter the input terminals to bias the input transistors. Figure 2.12(a) shows the currents IB1 and IB2 entering the input terminals of the op-amp. Though both the transistors are identical, the two currents IB1 and IB2 are not exactly equal. This is due to the internal imbalances created during the fabrication process. Therefore, the

Operational Amplifiers

35

manufacturers specify the input bias current IB as the average of the two base currents of the differential amplifier constituting the input stage of the op-amp. The input bias current IB is given by IB =

I B1 + I B 2 2

(2.3)

where IB1 is the dc bias current entering the non-inverting input and IB2 is the dc bias current entering the inverting input. Figure 2.12(a) shows that both the inputs are grounded, thus maintaining zero input voltage to the op-amp. It may be noted that the op-amp is powered by the dual voltage power supply, which is normally ±15 V.

Fig. 2.12

(a) Input bias currents (b) Inverting amplifier with bias currents

The basic inverting amplifier with the base currents IB1 and IB2 and the input voltage Vi = 0 is shown in Fig. 2.12(b). The non-inverting input terminal of the op-amp is grounded. For this circuit, the output voltage Vo must be 0 V. However, the output voltage is found to be offset by a value of Vo = IB 2Rf Assuming IC 741 op-amp with 500 nA of bias current (from datasheets), for Rf = 1 MW, the output becomes Vo = 500 ¥ 10–9 ¥ 1 ¥ 106 = 500 mV This indicates that for applications involving 500 mV of input voltage, this offset voltage is utterly unacceptable. This offset effect can be compensated using a compensation resistor Rcomp connected as shown in Fig. 2.12(c). The compensation resistor Rcomp is introduced in the nonFig. 2.12 (c) Bias current compensation inverting terminal path to ground. The current IB1 flowing through the compensating resistor Rcomp develops a voltage Vcomp across it. Then, applying Kirchhoff’s voltage law for the input circuit, we get -Vcomp + 0 + V2 - Vo = 0 or Vo = V2 - Vcomp (2.4) Choosing the proper value of Rcomp to get V2 = Vcomp cancels the offset effect, thus making the output Vo = 0. The value of Rcomp is calculated as shown below. V Rcomp = 2 I B2 and

IB1 =

Vcomp Rcomp

36

Linear IC Applications

At node a, with its voltage equal to –Vcomp as shown in Fig. 2.12(c), we get Vcomp I1 = R1 V2 and I2 = Rf

(2.5)

For offset compensation, it is known that Vo must be zero for Vi = 0. i.e., Using Eq. (2.4), Vcomp we get V2 = Vcomp and using Eq. (2.5), we get I2 = . Rf Applying Kirchhoff’s current law at node a, we get IB2 = I 2 + I1 =

Vcomp Rf

+

Ê R1 + R f ˆ = Vcomp Á ˜ Ë R1 R f ¯

Vcomp R1

Vcomp

Assuming IB1 = IB2, and using I B1 =

Rcomp

(2.6)

, we get

Ê R1 + R f ˆ Vcomp Vcomp Á ˜ = Ë R1 R f ¯ Rcomp or

Rcomp =

R1 R f R1 + R f

(2.7)

= R1 R f

Equation (2.7) shows that the compensating resistor Rcomp must be equal to the parallel combination of input and feedback resistors R1 and Rf connected at the inverting input terminal of the op-amp.

2.9.2

Input Offset Current

The circuit shown in Fig. 2.9(a) achieves bias current compensation, when the bias currents are equal, i.e., when IB1 = IB2. However, the input transistors cannot be made identical, and there always exists a small difference between the bias currents IB1 and IB2. The difference in magnitude between IB1 and IB2 is called input offset current IOS. I OS = I B1 - I B 2

(2.8) o

The manufacturers specify IOS for a circuit when the output Vo is zero and temperature is 25 C. IOS is typically less than 25% of IB for the average input bias current. It is 200 nA for BJT op-amp and 10 pA for FET op-amp. To find the effect of IOS on Vo, referring to Fig. 2.12(c), and assuming Vi = 0, we get, Vcomp = IB1 ¥ Rcomp and

I1 =

Vcomp

R1 Applying the two equations and using Kirchhoff’s current law at node a we get, R ˆ Ê I2 = I B 2 - I1 = I B 2 - Á I B1 comp ˜ R ¯ Ë 1

(2.9)

Operational Amplifiers

37

Using Fig. 2.12 (c), we get Vo = I2Rf – Vcomp = I2Rf – IB1Rcomp Substituting Eq. (2.9) in the above equation, we get Rcomp ˆ Ê R f - I B1 Rcomp Vo = Á I B 2 - I B1 R1 ˜¯ Ë

(2.10)

Using Eq. (2.7) for Rcomp and simplifying Eq. (2.10) we get Therefore,

Vo = Rf (IB2 – IB1) Vo = R f IOS

(2.11)

Equation (2.11) shows that the output voltage due to offset current IOS is dependent on the feedback resistor Rf, and it can be a positive or negative dc voltage with respect to ground. Since, normally IOS 0. This makes the closed-loop gain Av < A0 and the system becomes stable. Figure 2.21 shows the effect of feedback on open-loop gain with three corner frequencies and hence three RC pole pairs.

50

Linear IC Applications

Fig. 2.21

Effect of feedback on open-loop gain Vs frequency characteristics

Assuming a closed-loop gain of 80 dB is required, projecting the point horizontally to intersect on the openloop response curve at point A shows a closed-loop bandwidth of around 600 kHz. The –20 dB/decade rate of closure at A results in a maximum of –90o phase shift. If feedback resistors are chosen for 60 dB (or 1,000) gain, the bandwidth is 3.5 MHz as shown in Fig. 2.21. The 60 dB projection intersects the open-loop curve at –40 dB/decade rate of closure, and the maximum phase shift obtainable is (–90° –90°) = –180°. Hence, the circuit may be unstable. Similarly, a closed-loop gain of 20 dB results in a maximum of –270o phase shift creating instability. The transfer function of an op-amp with three corner frequencies is given by A=

A0 w1 w 2 w 3 ( s + w1 ) ( s + w 2 ) ( s + w 3 )

where 0 < w 1 < w2 < w3. The poles of the open-loop transfer function are at w1, w2 and w3. The poles of the closed-loop transfer function are given by the use of the equation 1+ Ab = 0. i.e.,

1+

2.10.5

b A0 w1 w 2 w 3 =0 s w + ( 1 ) (s + w 2 ) (s + w3 )

Slew Rate

Slew rate is an important parameter which limits the bandwidth for large signals and it indicates the rate of change output voltage. It is defined as the maximum rate of change of output voltage realised by a step input voltage, and it is usually specified in units of V/ms. The slew rate of the op-amp is related to its frequency response. The op-amps with wide bandwidth have better slew rates. Slew rate limiting affects all amplifiers where capacitance on internal nodes, or as part of the external load, has to be charged and discharged as voltage levels vary. The general purpose op-amps such as the IC 741 have a maximum slew rate of 0.5 V/ms, which means that the output voltage can change at a maximum of 0.5 V in 1 ms. The slew rate is usually specified at unity gain and no-load, and it improves with higher closed-loop gain and dc supply voltage.

Cause of slew rate limiting The slew rate is determined by a number of factors such as the amplifier gain, compensating capacitors and the change in polarity of output voltage. It is also a function of temperature and the slew rate generally reduces due to rise in the temperature.

Operational Amplifiers

51

The capacitor within or outside the op-amp is required to prevent oscillation and this capacitor restricts the response of op-amp to a rapidly changing input signal. The rate at which the voltage across the capacitor dv I Vc increases is given by c = where I is the current furnished by the internal circuit. This means that the dt C op-amp must have either a higher current or a small compensation capacitor. For example, the IC 741 can provide 15 mA of maximum current to its internal 30 pF capacitor. Therefore,

Slew rate =

Output voltage change d vc I max 15 m A = 0.5 V/ms = = = Time dt C 30 pF

If is to be noted that slew rates of value more than 100 V/ms are called as high-speed op-amps and are available for special applications such as video systems.

Slew rate limiting of sine-wave The slew rate limits the speed of response of all the large signal wave-shapes. Figure 2.22 shows Vi as a large amplitude, high frequency sine-wave with a peak amplitude of Vm. Let

Vi = Vm sin wt

Therefore, the output

Vo = Vm sin wt

The rate of change of output is given by d vo = Vmw cos w t dt

Fig. 2.22

Slew rate limiting of sine wave: (a) Voltage follower (b) Input and output waveforms

52

Linear IC Applications

The effect of slew rate limiting on a pulse input and a sine wave input is shown in Fig. 2.22(c) and (d).

Fig. 2.22

Effect of slew rate limiting: (c) pulse input and output (d) Sinusoidal input and output

The maximum rate of change of the output occurs when cos wt = 1. d vo Ωmax = Vmw dt

i.e.,

Slew rate =

or,

Slew rate = 2p f Vm V/ms

(2.24)

The maximum frequency fmax at which an undistorted output voltage with a peak value Vm is given by fmax =

Slew rate 2p Vm

(2.25)

The maximum peak sinusoidal output voltage Vm(max) that can be obtained at a frequency of f is given by Vm(max) =

Slew rate 2p f

(2.26)

Full Power Bandwidth The effect of slew rate limiting is the resulting distortion in the output signal, when the op-amp circuit is operated beyond its slew-rate capabilities. This is illustrated through Examples 2.10 to 2.15. To cite using an example and elaborate, consider a sinusoidal input Vi shown in Fig. 2.22(b). If the slew rate dv is high enough, the output would be Vo = Vm sin 2pft. The rate change of output o = 2pf Vm cos 2pft. Here, dt the peak amplitude is 2pf Vm. To realize an undistorted output, the slew rate must be equal to or greater than Slew rate Ê d vo ˆ . This shows that there is a tradeoff existing between ÁË dt ˜¯ , i.e., 2pf Vm £ Slew rate, or f Vm £ 2p max frequency f and amplitude Vm. In other words, Vm must be sufficiently small, to operate at higher frequencies. To operate the IC 741 at its full small-signal bandwidth of 1 MHz as a voltage follower, the maximum amplitude of Vm can be (0.5 V/ms)/(2p ¥ 1 MHz) @ 80 mV. Hence, the specification Full Power Bandwidth (FPB) of an op-amp is defined as the maximum frequency at which the op-amp can produce an undistorted output, with the Slew rate maximum possible amplitude. Thus, FPB = , where ±Vsat is the saturation voltage of op-amp chosen. 2pVsat

Operational Amplifiers

53

Example 2.9 Assume that an op-amp 741 connected as a unit gain inverting amplifier is applied with an input change of 10 V. Determine the time taken for the output to change by 10 V. Solution

Given, output voltage change = 10 V For the op-amp 741, slew rate = 0.5 V/ms We know that, Slew rate =

Output voltage change Time

Therefore,

Output voltage change 10 V = 20 ms = Slew rate 0.5 V/ms

Time =

Example 2.10 Assuming slew rate of IC 741 is 0.5 V/ms, what is the maximum undistorted sine-wave that can be obtained for (a) 12 V peak and (b) 2 V peak? Solution

Given the slew rate = 0.5 V/ms. (a) For the sine-wave of 12 V peak, fmax =

Slew rate 0.5 V / m s 0.5 = = = 6.63 kHz 2pVm 2p ¥ 12 � 2p ¥ 12 ¥ 10-6

(b) For the sine-wave of 2 V peak, fmax =

0.5V / ms 0.5 = = 39.8 kHz 2p ¥ 2V 2p ¥ 2 ¥ 10-6

Example 2.11 IC 741 is used as an inverting amplifier with a gain of 100. The voltage gain vs frequency characteristic is flat up to 10 kHz. Determine the maximum peak-to-peak input signal that can be applied without any distortion to the output. Solution

Slew rate of op-amp IC 741 = 0.5 V/ms We know that, Slew rate Vm(max) = 2p f =

0.5V / ms 0.5 = = 7.96 V 2p ¥ 10 kHz 2p ¥ 10 ¥ 103 ¥ 10-6

Example 2.12 Assuming the slew rate of op-amp is 0.5 V/ms, justify whether it is possible to amplify a square-wave of peak-to-peak value 500 mV, with a rise time of 4 ms or less, to a peak-to-peak amplitude of 5 V. Solution

The output voltage is greater than 1 V. dV Therefore, the required slew rate = o . dt The rise time is defined as the time needed for 10% to 90% of output transition. Therefore, the voltage swing value of 10% to 90% is (0.9 – 0.1) 5 V = 4 V.

54

Linear IC Applications

Then, the slew rate required =

4V 4 = = 1 V / m s. 4 ms 4 ¥ 10-6

Since the slew rate of op-amp 741 as given in the datasheet is 0.5 V/ms which is too slow when compared to the required slew rate of 1 V/ms, it is not possible to use op-amp 741 to amplify the given square wave. Example 2.13 Solution

The Slew rate =

The output voltage of a certain op-amp circuit changes by 20 V in 4 ms. What is its slew rate? dVo 20 V = = 5 V/ ms dt 4 ms

Example 2.14 An inverting amplifier using the 741C must have a flat response up to 40 kHz. The gain of the amplifier is 10. What maximum peak-to-peak input signal can be applied without distorting the output? Solution

The 741C has a typical slew rate of 0.5 V/ms. The slew rate is SR = The maximum output voltage, Vm = =

2p f Vm 106

= 0.5 V / m s

SR ¥ 106 2p f 0.5 ¥ 106

= 1.99 V peak 2p ¥ 40 ¥ 103 = 3.98 V (peak-to-peak) The maximum peak-to-peak input voltage for undistorted output is Vid =

Vm 3.98 = = 0.398 V (peak-to-peak) A 10

Example 2.15 An operational amplifier has a slew rate of 4 V/ms. Determine the maximum frequency of operation to produce a distortionless output swing of 12 V. Solution

Given Slew rate of the op-amp = 4 V/ms and Vm = 12 V f max =

2.11

4 Slew rate = 53.05 kHz = 2p Vm 2p ¥ 12 ¥ 10 - 6

Ic 741 bIPolar oPeratIonal amPlIfIer

and Its features

The IC 741 produced by several manufacturers since 1966 is widely used as a general purpose operational amplifier. Figure 2.23 shows the equivalent circuit of the IC 741 op-amp, divided into various individual stages. As discussed in the general op-amp structure, the circuit consists of three stages. (i) Input differential amplifier (ii) Gain stage (iii) Output stage

Operational Amplifiers

Fig. 2.23

55

Op-amp 741 equivalent circuit

A bias circuit is used to establish the bias current for whole of the circuit in the IC. The op-amp is supplied with positive and negative supply voltages of value ±15 V, and the supply voltages as low as ±5 V can also be used.

2.11.1

Bias Circuit

The reference bias current IREF for the IC 741 circuit is established by the bias circuit consisting of two diode-connected transistors Q11 and Q12 and resistor R5. The Widlar current source formed by Q11, Q10 and R4 provide bias current for the differential amplifier stage at the collector of Q10. Transistors Q8 and Q9 form another current mirror providing bias current for the differential amplifier. The reference bias current IREF also provides mirrored and proportional current at the collector of the double-collector lateral PNP transistor Q13. The transistor Q13 and Q12 thus form a two-output current mirror with Q13A providing bias current for output stage and Q13B providing bias current for Q17. The transistors Q18 and Q19 provide dc bias for the output stage formed by Q14 and Q20 and they establish two VBE drops of potential difference between the bases of Q14 and Q18.

2.11.2

Input Stage

The input differential amplifier stage consists of transistors Q1 through Q7, with biasing provided by Q8 through Q12. The transistors Q1 and Q2 form emitter-followers contributing to high differential input resistance, and whose output currents are inputs to the common base amplifier using Q3 and Q4 which offers a large voltage gain. The transistors Q5, Q6 and Q7 along with resistors R1, R2 and R3 form the active load for input stage. The single-ended output is available at the collector of Q6. The two null terminals in the input stage facilitate the null adjustment. The lateral PNP transistors Q3 and Q4 provide additional protection against voltage breakdown conditions. The emitter-base junction of NPN transistors breakdown at about 7 V whereas the PNP transistors Q3 and Q4 have higher emitter-base breakdown voltages of about 50 V. Therefore, placing PNP transistors in series with NPN transistors provide protection against accidental shorting of supply voltages to the input terminals.

56

Linear IC Applications

2.11.3

Gain Stage

The second or the gain stage consists of transistors Q 16 and Q 17, with Q 16 acting as an emitterfollower for achieving high input resistance. The transistor Q17 operates in common emitter configuration with its collector voltage applied as input to the output stage. Level shifting is done for this signal at this stage. Internal compensation through Miller compensation technique is achieved using the feedback capacitor C1 connected between the output and input terminals of the gain stage.

2.11.4

Output Stage

The output stage is a class AB circuit consisting of complementary emitter follower transistor pair Q14 and Q20. Hence, they provide an effective low output resistance and current gain. The output of the gain stage is connected at the base of Q 22, which is connected as an emitter-follower providing a very high input resistance, and it offers no appreciable loading effect on the gain stage. It is biased by transistor Q13A which also drives Q18 and Q19, which incidentally are used for establishing a quiescent bias current in the output transistors Q14 and Q20.

2.11.5

DC Analysis of IC 741

To perform dc analysis, both the inverting and non-inverting input terminals are assumed to be at ground potential and supply voltages of ±15 V are supplied to the op-amp.

lC10

Bias Circuit and Input Stage The bias circuit and input differential amplifier stage of IC 741 are shown in Fig. 2.24. The reference current IREF is given by V + - VEB12 - VBE11 - V IREF = R5

Fig. 2.24

Input stage with bias circuit

where VEB12 and VBE11 are the base-emitter voltages of Q12 and Q11. The transistors Q11 and Q10 with R4 form a Widlar current source, whose output current IC10 is determined using the relation given by ÊI ˆ IC10R4 = VT ln Á REF ˜ Ë I C10 ¯ where VT is the thermal voltage. Neglecting the base currents, we get IC8 = IC9 = IC10

Operational Amplifiers

57

Then, the quiescent collector currents in transistors Q1 through Q4 are equal and they are given by IC1 = IC2 = IC3 = IC4 =

I C10 2

Assuming exactly balanced dc currents in the input stage, the dc voltages at the collector of Q5 and Q6 are exactly the same. Therefore, it can be represented as VC6 = VC5 = VBE7 + VBE6 + IC6R2 + V – Thus, the dc level shifts through the op-amp. The current gain bp of PNP transistors Q3, Q4, Q8 and Q9 are relatively small, and hence, their base currents are not negligible. Figure 2.25 shows the detailed circuit of input stage of op-amp with the current components indicated. The base currents of NPN transistors Q1 and Q2 are assumed small and negligible. The current IC10 forms the base currents of Q3 and Q4, which in turn establish their emitter currents marked I in Fig. 2.21. The collector current of Q8 is given by 2I = I C 8 +

2 IC 9 bp

Since IC9 = IC8 in the current mirror, we get 2 ˆ Ê 2I = I C 9 1 + ÁË b p ˜¯ 2I

Therefore,

IC 9 =

Then,

IC10 = I C 9 +

(2.27)

2 1+ bp 2I 1 + bp

Fig. 2.25

Detailed circuit of input stage

Using Eq. (2.27), we get IC10 =

2I 1+

2 bp

+

È b 2p + 2 b p + 2 ˘ 2I ˙ = 2I Í 2 1+ bp ÍÎ b p + 3b p + 2 ˙˚

Assuming the base currents of NPN transistors Q1 and Q2 are negligible, the current I @

(2.28) I C10 . 2

Gain Stage The gain stage along with a part of the bias circuit showing IREF is shown in Fig. 2.26. The transistors Q12 and Q13 form a current mirror. The current IC13B is provided with a scale factor of 0.75 as given by IC13B = 0.75 IREF

(2.29)

58

Linear IC Applications

From Fig. 2.26, the emitter current of Q16 is given by IE16 @ IC16 = I B17 +

( I E17 ¥ R8 ) + VBE17 R9

(2.30)

considering that base current of Q16 is negligible.

Output Stage Figure 2.27 shows the basic output stage of op-amp IC 741 operating in class AB mode. The current source Q13A supplies a current of 0.25 IREF, to the combination of Q18, Q19 and R10. Assuming the base currents are negligible, IC13A is given by IC13A = 0.25 IREF = IBias (2.31)

Fig. 2.26

Gain stage of op-amp 741

Fig. 2.27

Output stage of op-amp

Neglecting the base current once again, the collector current of Q22 equals 0.25 IREF of IBias. The collector current of Q18 is then IC18 @

VBE19 R10

Therefore, IC19 = IBias – IC18

Operational Amplifiers

2.11.6

59

Short-Circuit Protection

The circuit of the output stage with short-circuit protection is shown in Fig. 2.28. The op-amp IC 741 contains a number of transistors that are OFF during its normal operation. When the output terminal gets shorted to the ground accidentally, while keeping a positive output voltage due to a certain input signal, a large current will get induced in the output transistor Q14. This can produce heat and cause burnout of the transistor. Therefore, when the current in Q14 reaches 20 mA, the voltage drop across R6 becomes 27 W ¥ 20 mA = 540 mV, which biases the transistor Q15 into conduction. Then, the excess current is shunted through the collector of Q15. Similarly, the maximum current in Q 20 is limited by R7, Q21 and Q24. When the current flow increases, the drop across R7 becomes sufficient to turn the transistor Q21 ON and the transistor Q21 and Q24 shunt the excess current away from the transistor Q20, thus protecting the output transistor.

Fig. 2.28

Short-circuit protection in IC 741 op-amp

Find the reference current IREF for the circuit shown in Fig. 2.24, assuming V + = 15 V, V = –15 V and VBE11 = VBE12 = 0.7 V. Example 2.16 –

Solution

Given V + = 15 V, V – = –15 V and VBE11 = VBE12 = 0.7 V From Fig. 2.25, R5 = 40 kW Therefore, IREF = = Example 2.17

V + - VBE12 - VBE11 - (- V - ) R5 15 - 0.7 - 0.7 - (-15) 40 ¥ 103

= 0.715 mA

Determine the bias currents in the gain stage of the op-amp shown in Fig. 2.26.

Solution

Assuming IREF to be 0.715 mA, the collector current IC17 of Q17 is given by IC17 = IC13B Since

IC13B = 0.75IREF, IC13B = IC17 ª IE17 = 0.75 ¥ 0.715 ¥ 10–3 = 0.536 mA

Using Eq. (2.31), we get IC16 @ IE16 = IB17 + =

I E17 R8 + VBE17 R9

I C17 I E17 R8 + VBE17 + b R9

60

Linear IC Applications

Assuming b = 150 and VBE17 = 0.7 V for NPN transistor, -3 -3 IC16 @ 0.536 ¥ 10 + 0.536 ¥ 10 ¥ 100 + 0.7 = 15.1 m A 150 50 ¥ 103

Determine the bias current in the output stage of Fig. 2.27 assuming IREF = 0.715 mA, VBE = 0.7 V and the saturation current for Q18 and Q19 are IS18 = IS19 = 10–14 A and IS14 = IS20 = 2 ¥ 10–14 A. Assume that the base currents are negligible. Example 2.18

Solution

IREF = 0.715 mA, VBE = 0.7 V, Is18 = Is19 = 10–14 A, Is14 = Is2 = 2 ¥ 10–14 A.

Given Thus,

IC13A = 0.25 ¥ IREF = 0.25 ¥ 0.715 ¥ 10–3 = 0.179 mA

Assuming

VBE19 = 0.7V, the current through R10 is given by IR10 =

VBE19 0.7 = = 0.014 mA R10 50 ¥ 103

IC19 @ IE19 = IC13A – IR10 = 0.179 – 0.014 = 0.165 mA

Therefore,

Then, VBE19 can be calculated as -3 ˆ Ê ˘ È VBE19 = VT ln Í I C19 ˙ = 26 ¥ 10-3 ¥ ln Á 0.165 ¥ 10 ˜ = 0.612 V Ë ¯ 10-14 Î IS ˚

b = 200, We get

Assuming

IB19 =

I C19 0.165 ¥ 10-3 = = 0.825 m A b 200

IC18 @ I E18 = I R10 + I B19 = (14 + 0.825) m A = 14.825 m A Ê 14.825 ¥ 10-6 ˆ ÊI ˆ VBE18 = VT ln C18 = 26 ¥ 10-3 ln Á ˜¯ = 0.549 V ÁË I ˜¯ Ë 10-14 S Therefore,

VBB = VBE18 + VBE19 = 0.549 + 0.612 = 1.161 V

Transistors Q14 and Q20 are identical with

IC14 = I C 20 = I S e

2.11.7

VBB 1 2 VT

VBB across their base-emitter junction. 2 = 2 ¥ 10-14 ¥ e

1.161 1 2 0.026

= 99.42 m A

Small Signal Analysis

Input Stage Figure 2.29 shows the ac equivalent circuit of the input stage. The differential voltage is vid between the two input terminals. The constant current biasing provides infinite impedance at the bases of Q3 and Q4. Reff 1 is the effective resistance offered by the active load, with Ri2 acting as the input resistance of the gain stage. The

Operational Amplifiers

vo 1 vid

small-signal differential voltage gain is given by Ad =

(

= – gm ro 4 Reff 1 Ri 2 =–

I CQ VT

(r

o4

)

Reff 1 Ri 2

61

)

(2.32)

where I CQ represents the quiescent collector current in transistors Q1, Q2, Q3 and Q4, ro4 is the resistance of Q4 looking into its collector. The negative sign denotes the change in signal polarity. The effective resistance of active load is Reff 1 = ro6(1 + gm6(R2 ΩΩrp 6)) which is the resistance of the Widlar current source. Input resistance Ri2 of the current stage is given by Ri2 = rp16 + (1 + bn)R ¢E

vid 2

Q2

Q1

+

ie

–

ie

–

+ Q3

vid 2

Q4 vo1

ai e Reff 1

Fig. 2.29

Ri 2

The ac equivalent circuit of input stage

where rp16 is the resistance through hybrid p model of Q16, and R¢E is the effective resistance of Q16 and in given by R¢E = R9 ( rp 17 + (1 + b n ) R8 ) (2.33) where rp17 is the resistance through hybrid p model of Q17.

Gain Stage Figure 2.30 shows the ac equivalent circuit of gain stage of IC 741 op-amp. The resistance Reff1 is the effective resistance of active load. Ri3 indicates the resistance offered by the output stage and Ri2 is the input resistance of the gain stage. The small signal voltage gain is determined as follows: The input base current of Q16 and Q17 are vo1 ib16 = Ri 2 ib17 = Then,

R9

(

R9 + rp 17 + (1 + b n ) R8

(

vo2 = -ic17 ¥ Reff 2 Ri 3

)

Q16

vo1

Q17

Ri3

ib17 R9 = 50 kW

) (

vo2

ib16

¥ ie16

Using the three equations above, we get

)

(1 + bn ) R9 Reff 2 Ri3 Ro17 v Av2 = o 2 = - b n vo1 Ri 2 R9 + ( rp 17 + (1 + b n ) R8 )

(

Reff 2 Ri2

Fig. 2.30

R8 = 0.1 kW

The ac equivalent circuit of gain stage

)

The effective resistance of the active load is the resistance seen into the collector of Q13B, that is given by Reff 2 = ro13 B =

VA I C13 B

62

Linear IC Applications

Figure 2.31(a) shows the ac equivalent circuit to determine the input resistance of the output stage. Consider that the PNP output transistor Q20 is active, the NPN output transistor Q14 is cut-off and the resistor RL is the load. Transistor Q22 acts as an emitter-follower and the input resistance is given by Ri3 = rp 22 + (1 + b p ) ÈÎ R19 R20 ˘˚

Q13A Rc13A Q13A Q18

Ro

R13A

Q19

Q18

R7 = 22 W

R10

Re20

vo Q19 R7

R10 = 50 kW

RL

Q13B

R20

Q22

vo2

Re22

Rc13B Q22

Q20

R19

Q20

Rc19

Rc17 Q17

Ri3

R8 = 100 W (a)

Fig. 2.31

(b)

The ac equivalent circuit of the output stage of op-amp 741 for calculating (a) input resistance, and (b) output resistance

The resistance R19 is the series combination of resistances seen looking into the emitters of Q18 and Q19 and collector of Q13A. The emitter resistances are small, compared to R13A. Hence, we have R19 @ R13 A = ro13 A =

VA I C13 A

The output transistor Q20 is also an emitter-follower. Therefore, R20 = rp 20 +(1 + bp)RL, considering that the resistor RL is larger than R7.

Overall Voltage Gain The overall voltage gain is the product of the individual gain factors, or we can write Av = Ad Av2 Av3

(2.34)

where Av3 is the voltage gain of the output stage. Typical voltage gain for IC 741 op-amp is in the range of 200,000.

Operational Amplifiers

63

Output Resistance The output resistance can be determined using the ac equivalent circuit shown in Fig. 2.31(b). Assuming the output transistor Q20 is conducting and Q14 is cut-off, the output resistance is given by Ro = R7 + Re20 where

Re 20 =

rp 20 + Re 22 Rc19

(1 + b p )

,

in which Rc19 @ Rc13A and the resistor Re22 is given by Re 22 =

rp 22 + Rc17 Rc13 B

and

(1 + b p )

, Rc13 B = ro13 B ,

Rc17 = ro17 È1 + g m17 ( R8 rp 17 )˘ . Î ˚ The output resistance of the op-amp can be determined by combining all the resistance terms.

2.11.8

Frequency Response

The IC 741 op-amp is internally frequency-compensated using Miller compensation technique by introducing a dominant low-frequency pole. Applying Miller’s theorem, the effective input capacitance of the second gain stage is Ci = C1 (1 + Av 2

)

(2.35)

The dominant low-frequency pole is given by f1 =

1 2p Req Ci

where Req is the equivalent resistance between the second stage input node and ground and is given by Req = Ro1 Ri 2 where Ri2 is the input resistance of the gain stage and Ro1 is the output resistance of the differential amplifier stage. Using Fig. 2.29, we observe that Ro1 = Reff 1 ro 4 The unity gain-bandwidth is given by fT = Ao f1

(2.36)

Typical unity gain-bandwidth value for the IC 741 op-amp is 1 MHz. If the frequencies of the other poles of the IC 741 op-amp are greater than 1.9 MHz, the phase margin is 90 degrees. This phase margin guarantees that any closed-loop amplifier circuit using op-amp IC 741 remain stable for any feedback transfer function.

2.12

general descrIPtIon

of the

oP-amP 741

Each integrated circuit manufacturer employs a specific code and allots a specific type number to the ICs, which they produce. For instance, the IC 741, which is an internally compensated and widely used op-amp originally manufactured by Fairchild as mA741 has the symbols mA representing the identifying initials used by Fairchild. The codes used by some of the well known manufacturers of linear ICs are: (i) Fairchild mA, mAF (ii) National Semiconductor LM, CH, LF, TBA

64

Linear IC Applications

(iii) (iv) (v) (vi) (vii)

2.12.1 (i) (ii) (iii) (iv) (v) (vi) (vii) (viii) (ix) (x)

Motorola RCA Texas Instruments Signetics Burr-Brown

MC, MFC CA, CD SN N/S, NE/SE BB

General Description mA741 is an internally frequency-compensated op-amp It is a monolithic IC, fabricated using planar epitaxial process It has internal short-circuit protection It has externally connected offset null capability It has large common-mode and differential voltage ranges It is useful in many applications such as integrator, differentiator, adder, subtractor, voltage follower or buffer and other feedback applications It consumes low power No latch-up occurs It is available in all the three types of packages, namely, 8-pin metal Can, 10-pin Flatpack and 8 or 14-pin dual-in-line package or DIP For 741C, two sets of electrical specifications are provided, where the first set is meant for operating characteristics at room temperature (25°C) and the other set applies to the commercial temperature range (0° to +70°C)

2.12.2 Absolute Maximum Ratings Supply voltage mA741A, mA741, mA741E mA741C Internal Power Dissipation Metal Can Moulded and Hermetic DIP Mini DIP Flatpack Differential Input Voltage Input Voltage Operating temperature range Military (mA741A, mA741) Commercial (mA741E, mA741C)

2.12.3

Packages

The normal packages available for the op-amps are (i) the metal Can (TO) package (ii) the dual in line (DIP) package (iii) the flat package

± 22 V ±18 V 500 mW 670 mW 310 mW 570 mW ±30 V ±15 V –55°C to 125°C 0°C to 70°C

Operational Amplifiers

65

The op-amp packages are available with single, dual or quad (four) op-amps contained in a single package. The typical packages have 8, 10 or 14 terminals for a single op-amp IC. The widely popular IC mA741 is a single op-amp available as an 8-pin DIP and TO package, a 10-pin Can or a 14-pin DIP. The mA747 is a chip containing two op-amps which comes as a 10-pin Can or a 14-pin DIP. The packages and the pin connections of IC 741 are shown in Fig. 2.32(a) through Fig. 2.32(d). Metal can package with straight leads Dual-in-line plastic package

Tab locates pin 8 N.C. Offset null

8

7

1

Inverting input

– 2

Offset null Output Inverting input Non-inverting 5 input Offset V– null 6

+

3 4

Non-inverting input

V+ 1 2 3

1

14

N.C.

2

13

N.C.

12

Offset N.C. null V+ Inverting input Output Offset Non-inverting input null V– N.C.

11 +

6

10 9

7

8 (c)

Fig. 2.32

V+

+

6

Output Offset null

Ceramic flat package

N.C.

5

7

(b)

N.C.

–

–

5

V– (a)

3 4

N.C.

4

Dual-in-line welded-seal ceramic package

Offset Null Inverting input Non-inverting input V– N.C.

8

N.C.

1 2 3

–

4

+

5

10

N.C.

9

N.C.

8 7

V+

6

Output Offset null

(d)

Packages of IC mA741 with pin diagrams: (a) 8-pin metal Can (b) 8-pin mini DIP (c) 14-pin DIP (d) 10-pin Flatpack

66

Linear IC Applications

2.12.4

Op-amp Terminals

The general purpose op-amp normally has five basic terminals, namely, two input terminals, one output terminal and two power supply terminals for positive and negative voltages. Referring to the top view of a metal can package of IC mA741 with 8 pins shown in Fig. 2.32(a), the pin number 8 is identified with a tab. The numbering for the IC is done counter clockwise starting from pin number 1 at the left towards 8 at the right. The pin number 2 forms the inverting terminal and pin 3 forms the non-inverting input terminal. The output is available at pin 6 and the terminal 1 and 5, called the null terminals are provided for dc offset null adjustment. The pins 7 and 4 form the positive and negative power supply terminals respectively, shown as V+ and V– in Fig. 2.32(a). The pin 8 is a no connection terminal. For the mini DIP and 14-pin DIP packages shown in Fig. 2.32(b) and Fig. 2.32(c) respectively, the top pin on the left hand side is identified as pin 1. For the flat pack type shown in Fig. 2.32(d), pin 1 is identified with a dot near pin 1. The remaining pins are counted counter-clockwise from pin 1.

2.13

oP-amP Parameters

and

measurement

Operational amplifiers are very high gain amplifiers provided with differential inputs and single-ended output. They are highly preferred in high precision analog circuit applications. Hence, it is imperative to measure, their performance through the defined set of parameters accurately. However, in open-loop measurements, due to their high open-loop gain of the order of 107 or more, it becomes very hard to avoid errors from very small voltages at the amplifier input due to spurious noise, stray currents, or the Seebeck (thermocouple) effect. There are several op-amp parameters which are needed to be measured while using them. This section discusses the measurement of most of the basic dc and ac parameters using simple circuits that can be easily constructed and clearly understand. The measurement of op-amp parameters can be easily carried out by using a servo loop as shown in Fig. 2.32 to force a null at the amplifier input, which allows the op-amp, which is the device under test (DUT) to essentially measure its own values and errors. The loop employs an auxiliary op-amp as an integrator to establish a stable loop with very high DC open-loop gain. The auxiliary op-amp connected in the loop is an op-amp with optimal performance with DC open-loop gain of 106 or more. When the offset of the DUT is expected to exceed a few millivolts, then the auxiliary op-amp must be operated using ±15 V power supplies. For DUTs with more than a few millivolts input offset, then the feedback resistor 99.9kΩ connected from auxiliary op-amp to input of DUT. The DUT is powered by positive and negative supply voltages of equal magnitude and opposite sign. The auxiliary amplifier, connected as an integrator with feedback capacitor is configured for open-loop with full gain at dc. However, the input resistor and the feedback capacitor curtail its bandwidth to a few Hz. In other words, the dc voltage at the output of the DUT is amplified by the full gain of the auxiliary amplifier and feedback through a 1000:1 attenuator, to the noninverting input of the DUT. The negative feedback pushes the output of DUT to ground potential. Hence, the voltage on the test point O1 is 1000 times the correction voltage or in other words, equal in magnitude to the error being applied to the input of the DUT. This will be tens of mV or more at the test point O1. Hence, it can be easily measured. An ideal op-amp has zero offset voltage (VOS). In other words, when both inputs are joined together and held at a voltage which is midway between the supply voltages, the output voltage must be midway between the supply voltages too. However, in practice, the op-amps incur offsets ranging from a few microvolts to a few millivolts. Hence, a voltage in this range must be applied to the input for bringing the output to the midway potential.

Operational Amplifiers

2.13.1

67

Offset Measurement

Figure 2.33 shows the test configuration for the measurement of offset parameters. The DUT output voltage is at ground when the voltage at test point output O1 is 1000 times its offset. C1 5mF

+V _ R4 110k

R1 100

DUT

Test Point O1

AUXILIARY OP AMP

+ R2 100

+15V

_

–V

+

R3 99.9k

–15V

Fig. 2.33

Offset measurement

The ideal op-amp has infinite input impedance and hence its inputs are supposed to have no input current flow. However, practically looking at it, small bias currents IB1 and IB2 are observed to flow in the inverting and noninverting inputs respectively. These currents can cause significant offsets in high-impedance circuits. These currents range from a few femto-amperes (1 fA = 10–15 A—one electron every few microseconds) to a few nano amperes depending on the op-amp type. In some of the high speed op-amps, it may reach even one or two microamperes. These currents can be measured using the circuit set-up shown in Fig. 2.33 with switches S1 and S2 closed. Fig. 2.34 shown. R1 100Ω

C1 5mF

S1 _ R3 110kΩ

RS R1 100Ω

DUT

S2

_ Test Point Vo

Auxiliary op-amp

+ RS

+ R2

RS >>100Ω (100kΩ TO 1GΩ) S1 CLOSED TO TEST IB2 S2 CLOSED TO TEST IB1 BOTH CLOSED TO TEST VOS BOTH OPEN TO TEST IOS

Fig. 2.34

Vo = 1+

R2 100

VOS

+ 1+

R2 IB+RS 100

– 1+

R2 IB–RS 100

Bias current measurement

68

Linear IC Applications

2.13.2

Bias Current Measurement

The circuit for measuring the offset circuit is the same as Figure 2.34, with the addition of two large resistors of value Rs connected in series with the DUT inputs. The two resistors of value RS create an additional offset voltage equal to IB × Rs. These resistors are set to be short circuited using switches S1 and S2. With both switches closed, the circuit is the same as Fig. 2.34 for measuring the offset. When S1 is open, the bias current from the inverting input flows into the inverting input, and the voltage difference adds to the offset, paving way for measuring IB1. In the same manner, by closing switch S1 and opening S2, the bias current IB2 can be measured. With the actual VOS previously measured and noted, the change in output Vo due to the change in RS can be determined and IB is then easily computed. This gives values of IB1 and IB2. The rated value of IB is the average of the two currents or in other words, IB = (IB1 + IB2)/2. Practical values of Rs vary from 100 kΩ for bipolar op-amps to 1000 MΩ for some FET input op-amps. When S1 and S2 are closed, Ios still flows in the 100-Ω resistors and introduces an error in Vos. However, unless Ios is large enough to produce an error greater than 1% of the measured Vos, it can usually be ignored in the calculation. Extremely low input bias currents can be measured by using integration techniques. The bias current under measurement is used to charge a capacitor, and the rate of voltage change across the capacitor is measured. If the capacitor and the general circuit leakage are negligible, the current may be calculated directly from the rate of change of the output of the test circuit. Figure 2.35 below demonstrates the general test concept. With one switch open and the other closed, either IB1 or IB2 can be measured. It can be noted that only capacitors with the most suitable dielectric can be employed in the process. S2 C

–

IB2

Vo

DUT IB1 + ∆ Vo C S1

=

∆t IB = C

IB C ∆ Vo ∆t

OPEN S1 TO MEASURE IB1 OPEN S2 TO MEASURE IB2 Fig. 2.35

2.13.3

Measuring Very Low Bias Currents

DC gain measurement

The open-loop DC gain of an op-amp is very high and op-amps with gain values greater than 107 are also being used. However, the op-amps with gain values between 250,000 and 2,000,000 are used widely. The dc gain of such op-amps can be measured by forcing the output of the DUT to move by a known amount by switching R5 between the DUT output and a 1 V reference with switch S1. The circuit arrangement shown in

Operational Amplifiers

69

Fig. 2.36 can be employed for this purpose. If R5 is at +1 V, then the DUT output must move to –1 V if the input of the auxiliary amplifier is to remain unchanged near zero. C1 5 mF

+V – R4 220kΩ

R1 100Ω

+

R5 220kΩ

S1

R2 100Ω

+15V –

DUT

Test Point Vo

AUXILIARY OP-AMP

–V R3 99.9kΩ

–1V

+ –15V

Fig. 2.36

DC gain measurement

The voltage change at test point Vo, attenuated by 1000:1 is the input to the DUT. This causes a 1V change in the output. It is simple to calculate the gain from this (= 1000 × 1V/Voltage Vo).

2.13.4 AC gain measurement In order to measure the open-loop AC gain of the op-amp, a small AC signal of the desired frequency is injected at the DUT input and the resulting output signal is measured at the output Vo as shown in Fig. 2.37. When this is being done, the auxiliary amplifier continues to stabilize the mean DC level at the DUT output. ac input signal

Test Point Vo

C3 1nF C1 5 mF

+V – R1 100Ω

R4||R5 110kΩ

AUXILIARY OP-AMP

+ R2 100Ω

+15V –

DUT

–V +

R3 99.9kΩ

–15V Fig. 2.37

AC gain measurement

As shown in Fig. 2.37, the AC signal is applied to the DUT input via a 10000:1 attenuator. This large value is required for low frequency measurements, where the open-loop gains may be very closer to the DC value. Hence, AC measurements are normally carried out at frequencies ranging from a few hundred Hertz to the frequency at which the open-loop gain has dropped to unity. It can be carried out meticulously with lower input amplitudes also, if low-frequency gain data is required. The simple attenuator shown in Fig. 2.38 is suitable only for frequencies up to around 100 kHz. For AC gain measurement at higher frequencies, a more complex circuit would be required.

70

Linear IC Applications

2.13.5

DC Common Mode Rejection Ratio (CMRR) measurement

The common-mode rejection ratio (CMRR) of an op-amp is defined as the ratio of the change of offset due to a change in common-mode voltage to the change in input common-mode voltage. It is normally found to be of the order of 80 dB to 120 dB at DC, and it however, remains low at higher frequencies. Figure 2.38 shows a simple CMRR test circuit, in which four precision resistors are used with the DUT. The op-amp is configured as a differential amplifier, however with the same signal applied to both the inputs. The change in the output is measured with 0V as input voltage and the Vin applied as input voltage. The limitation of this test circuit is that the ratio mismatch among the resistors is as important as the CMRR itself. R2 R1

–

Vin

Vout

DUT R1

+ ∆Vout = R2

Fig. 2.38

∆Vin CMRR

(1+ RR ) 2 1

Resistors must match within 1ppm (0.0001%) to measure CMRR > 100db

Simple Commom Mode Rejection Ratio (CMRR) Test Circuit

Figure 2.38 shows a more complex and intense test circuit to measure the CMRR. The common-mode voltage is not applied to the DUT input terminals, where low-level effects would be likely to disrupt the measurement, but the power-supply voltages are altered in the same direction, relative to the input. As shown in the circuit of Fig. 2.39, the offset is measured at Vo with supply voltages of, e.g. +2.5 V and – 2.5 V followed by power supply voltage with both voltages moved up by +1 V, i.e. +3.5 V and –1.5 V. The change of output voltage at test point Vo thus, corresponds to a change of common mode of 1 V, so that DC CMRR is the ratio of the offset change and 1 V. A

+V (+2.5V)

S1 B

+V + 1V (+3.5V) C1 5 mF

– R1 100Ω

R4 110kΩ

+15V –

DUT

AUXILIARY OP-AMP

+ R2 100Ω

+

R3 99.9kΩ

–15V

a –V (–2.5V)

S2 b

–(V – 1V) (–1.5V)

Fig. 2.39

DC CMRR measurement

Test Point Vo

Operational Amplifiers

2.13.6

71

DC Power Supply Rejection Ratio (PSRR) measurement

The parameter CMRR refers to the change of offset for a change in common mode voltage, while the total power supply voltage is kept unchanged. The power-supply rejection ratio (PSRR) is the ratio of the change on output voltage offset with respect to the change in total power supply voltage, with the common-mode voltage left unchanged at the midpoint of the supply as shown in Fig. 2.40. The circuit used for the PSRR measurement is exactly the same as that of the CMRR except that both the supply voltages of the DUT are changed, and the common level is unchanged. Note that the switch S makes the supply voltage of either +2.5 V and –2.5 V or to +3 V and –3 V is made available to the DUT. It means that the DUT is provided with a change of total supply voltage from 5 V to 6 V. The common-mode voltage remains at the midpoint. The calculation is thus given by (1000 × Voltage Vo/1 V). A

+V (+2.5V)

S2 B

+V + 0.5V (+3.0V) C1 5 mF

– R1 100Ω

R4 110kΩ

+15V –

DUT

Test Point Vo

AUXILIARY OP-AMP

+ R2 100Ω

+

R3 99.9kΩ

–15V

a –V (–2.5V)

S1 b

–(V + 0.5V) (–3.0V)

Fig. 2.40

DC PSRR measurement

2.13.7 AC Common Mode Rejection Ratio (CMRR) measurement In order to measure the ac CMRR and ac PSRR of opamp, the power supply voltages are modulated with AC signal voltages. Figure 2.41 shows the test circuit arrangement of ac CMRR measurement. The DUT is configured to operate in openloop at dc. And, the ac negative feedback defines an exact gain of (× 100) as in the diagrams. The positive and negative supplies to the DUT are modulated with AC signal voltages of amplitude 1V peakto-peak. The modulation of both power supplies is in the same

+V + 1V sinωt

C2 33 nF

R8 9.9kΩ

Test Point VO C1 5 µF

– R4 110kΩ

R1 100Ω DUT

+15V – AUXILIARY OP-AMP

+ R2 100Ω

+

R3 99.9kΩ

–15V

–V + 1V sinωt

Fig. 2.41

AC CMRR measurement

72

Linear IC Applications

phase, such that the actual supply voltage is made a steady dc, however with a sinusoidal common-mode of 2V Peak-to-Peak. This causes the DUT output to contain an ac voltage, which is measured at test point Vo. If the ac voltage at Vo has an amplitude of x volts peak (2x volts peak-to-peak), then the CMRR in reference to the DUT input, i.e., before the × 100 ac gain, is ×/100 V, and the CMRR is the ratio of this to 1V peak. The parameter ac PSRR is measured with the ac on the positive and negative supplies with 180° out of phase. This results in the amplitude of the supply voltages being modulated, for example, with 1V peak and 2 V p-p, while keeping the common-mode voltage steady at dc. The calculation is similar to the dc PSRR measurement. +V + 0.5Vsinωt

R8 9.9kΩ

C2 33 nF Test Point VO C1 5 µF

– R4 110kΩ

R1 100Ω

+15V –

DUT

AUXILIARY OP-AMP

+ R2 100Ω

+

R3 99.9kΩ

–15V

–V – 0.5 Vsinωt

Fig. 2.42

2.13.8

AC PSRR measurement

Slew Rate measurement

The maximum possible rate of change of the output voltage, while producing the rated output is defined as the slew rate. It is measured as a voltage change in a given time, typically V / µs or V / ms. The rate dVo / dt can thus be measured using the non-inverting op-amp configuration with R1 = • and R2 = •. While testing the Input op-amp which has a single ended input, the inverting mode square Output op-amp circuit can be used with R2 = 10kW. The input Vi to be wave limited applied can be a high frequency square wave and the slope by slew rate with respect to time of the leading and trailing edges of the output signals are measured. It is the common practice to specify the slower of the rising and falling rates as the slew rate of the op-amp DUT. Fig. 2.43 Illustration of the slew rate of op-amp

Operational Amplifiers

73

frequency comPensatIon

2.14

When wider bandwidth and limited closed-loop gain are required, suitable compensation techniques are employed. The two types of compensation techniques used in practice are: (i) External frequency compensation (ii) Internal frequency compensation

2.14.1

External Frequency Compensation

The compensating network is connected externally to the op-amp for modifying the response based on the requirements. The compensating network alters the response so that –20 dB/decade of roll-off rate is achieved over a broad range of frequency. The commonly used external compensation methods are: (i) Dominant-Pole compensation (ii) Pole-Zero (lag) compensation (iii) Miller effect compensation

Dominant-pole Compensation Let A be the uncompensated transfer function of an open-loop op-amp, whose transfer function is given by A=

A0w1 w 2 w 3 s + w ( 1 ) (s + w 2 ) (s + w3 )

(2.37)

where 0 < w 1 < w 2 < w 3. Figure 2.44(a) shows a dominant-pole compensation network by adding an RC network in series with an opamp, or it can be achieved by connecting a capacitor C at a suitable high resistance node with respect to ground. Then, the compensated transfer function A¢ after compensation is given by

1 ˆ Ê Á jw C ˜ vo A0 = A0 Á A¢ = ˜= 1 vi ˜ 1 + j ( f / fd ) ÁR+ ÁË jw C ˜¯ 1 is the break frequency of the compensating network. Using Eq. (2.37), we get the compensated 2p RC transfer function as where fd =

A¢ =

A0 f f f ˆÊ f ˆ Ê ˆÊ ˆÊ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ d 1 2 3

where fd < f1 < f2 < f3.

74

Linear IC Applications

The capacitance C is selected such that, the modified loop gain drops down to 0 dB with a roll-off rate as given by 20 dB/decade at a frequency, where the poles of the uncompensated system transfer function A contributes negligible phase shift. Normally, the break frequency w fd = d is selected so that, the transfer 2p function A¢ passes through 0 dB at the pole f1 of A. The uncompensated and compensated magnitude plots are shown in Fig. 2.44(b). The main disadvantage of this compensation technique is that, the bandwidth of the op-amp circuit reduces drastically from f1 to fd as shown in Fig. 2.44(b). However, the advantage derived from this method is the improved noise immunity of the system, since the noise components outside the reduced bandwidth are eliminated.

Pole-zero Compensation In this method, both a pole and a zero are added to the uncompensated transfer funcFig. 2.44 (a) Dominant-pole compensation (b) Gain Vs tion A. Figure 2.45(a) shows the circuit frequency characteristics for dominant pole arrangement of the pole-zero compensacompensation tion method. The zero is added at a higher frequency than the pole. The transfer function of the compensation network is given by

vo Z2 = = v2 Z1 + Z 2

1 jX C 2 1 R1 + R2 + jX C 2 R2 +

Fig. 2.45

(a) Pole–zero compensation

Operational Amplifiers

Fig. 2.45

where

Z1 = R1 and Z2 = R2 +

Therefore,

where and

75

(b) Its open-loop Vs frequency response

1 . jw C2

Ê fˆ 1+ Á j ˜ vo Ë f1 ¯ 1 + jw R2 C2 = = v2 1 + jw ( R1 + R2 ) C2 Ê f ˆ 1+ Á j ˜ Ë f0 ¯ 1 f1 = 2p R2 C2 f0 =

1 2p ( R1 + R2 ) C2

The compensating network introduces a zero at the first corner frequency f1 of uncompensated transfer function represented by A, which cancels the effect of pole at f1. The pole of the compensation network at w0 is selected such that the compensated transfer function A¢ passes through 0 dB at the second f0 given as 2p corner frequency f2 shown in the uncompensated transfer function A of Eq. (2.37). This is shown in Fig. 2.45(b) graphically by having A¢ passing through 0 dB at frequency f2 with a slope of –20 dB/decade. The overall transfer function of the amplifier with compensation network is given by fˆ Ê 1+ j ˜ Á f1 ¯ A0 vo vo v2 Ë ¥ = ¥ = A¢ = f f f ˆÊ f ˆ vi v2 vi Ê ˆ Ê ˆÊ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ 2 3 0 1 Therefore, A¢ =

A0 f f ˆÊ f ˆ Ê ˆÊ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ ÁË1 + j f ˜¯ 0 2 3

where 0 < f0 < f2 < f3.

(2.38)

76

Linear IC Applications

A comparison of the compensating techniques using dominant pole and pole-zero methods can be made using Fig. 2.45(a) and Fig. 2.45(b). The dominant pole is selected such that the compensated transfer function passes through 0 dB at f1 , which is the first pole of the uncompensated function, whereas the zero is chosen at f1 and pole is selected at f2. Therefore, the compensated transfer function passes through 0 dB at the second pole f2 of the uncompensated transfer function in the pole-zero compensation technique. Therefore, the resultant advantage is the improved bandwidth of value (f2 – f1). Since the size of the compensation capacitance is large, forbidding the integration of capacitor with the op-amp, normally standard IC op-amps have external pins provided to facilitate the external component connection. This drawback is eliminated in Miller effect compensation method, which employs the Miller effect.

Miller Effect Compensation Figure 2.46(a) shows the op-amp inverting amplifier with capacitor C1 connected in parallel with the feedback resistor R2. The combination of C1 and R1 behaves as phase-lead network in the feedback loop of op-amp as shown in Fig. 2.46(b). Thus, C1 and R1 introduce a phase lead to cancel some amount of phase lag in the loop. R2 C1

C1 R1

v2

–

vi

v1

R1

vo +

(a)

Fig. 2.46

2.14.2

(b)

Miller effect compensation: (a) Inverting amplifier with Miller capacitor (b) Phase lead network of the compensated op-amp

Internal Frequency Compensation

Broad bandwidth may not be the only criterion required in some applications like instrumentation. In such cases, internally compensated op-amps called compensated op-amps can be employed. They are found to be stable regardless of the value of closed-loop gain and without any external compensation methods. The frequency response of IC 741 op-amp which is internally compensated is shown in Fig. 2.47. The op-amp 741 internally contains a capacitance of 30 pF that shunts off the signal current at higher frequencies, leading to decrease in output signal. This internal compensating capacitor causes the open-loop gain to roll-off at –20 dB/decade rate that assures a stable characteristic for the circuit. The op-amp 741 has a gain-bandwidth (GBW) product of 1 MHz. This represents that the product of gain and frequency at any point on the open-loop gain versus frequency curve is 1MHz. If the op-amp is connected for a gain of 60 dB, or 10 3, then the bandwidth obtainable is 1 kHz. For a gain of 10, the bandwidth increases to 100 kHz.

Operational Amplifiers

Fig. 2.47

77

Frequency response of mA741 op-amp

Note that the gain bandwidth product is also identified normally as GBP. Some of the internally compensated op-amps are LM741, LM107 and LM112 from National SemiConductor, MC1558 from Motorola and mA741 from Fairchild.

Review Questions 2.1 What is an op-amp?

A

2.2 What are the basic building blocks of an opamp? What are the desirable characteristics of the individual blocks and why so? B 2.3 What are the characteristics of an ideal op-amp? B 2.4 An ideal op-amp has infinite input resistance B and zero gain (True/False). 2.5 Mention the characteristics of a practical B op-amp. 2.6 What are the non-ideal dc characteristics of B an op-amp? 2.7 Compare the ideal and practical characteristics of an op-amp. C 2.8 Draw the basic block diagram of a general op-amp and explain the operation of each B block.

2.9 Draw the circuit diagram of a general opamp, identify the stages in it and explain their function in detail. C 2.10 Draw the internal circuit diagram of the IC 741 operational amplifier and explain the function of each stage. C 2.11 Perform the dc analysis of op-amp 741. C 2.12 Perform the ac analysis of op-amp 741. C 2.13 Calculate the reference current IREF for Fig. 2.23, assuming VBE11 = VBE12 = 0.65 V and V + = +15 V and V – = –15 V. C 2.14 Calculate the bias current for the output stage of the op-amp shown in Fig. 2.25. Assume IREF = 0.7 mA,VBE = 0.65 V and saturation current for Q18 and Q19 is 10–14 A and IS14 and IS20 = 1.5 ¥ 10–14 A. Assume that the base currents are negligibly small. C

78

Linear IC Applications

2.15 How is Miller compensation achieved in opB amp 741? 2.16 Elaborate on the short circuit protection facility in IC 741. C 2.17 Comment on the frequency response of B IC 741. 2.18 How do you determine the overall gain of an op-amp? C 2.19 What is zero offset suppression in an opamp? B

2.29 2.30 2.31 2.32

2.33

2.20 List the dc and ac characteristics of an opA amp. 2.21 Lower bias current means higher input B impedance: (True/False). 2.22 Discuss the input offset current and input offset voltage of an operational amplifier. B A 2.23 Define offset voltage. 2.24 Assume for Fig. 2.12(c), IOS = 300 nA and R1 = 1.5 kW and Rf = 150 kW. Calculate the B maximum output offset voltage. 2.25 Define thermal drift. What are the parameters A that cause the thermal drift? 2.26 An op-amp has the drift specifications as given below: B DI OS = 0.4 nA / ∞C DT DVOS = 20 m V/∞C DT

and temperature span of variation = 25oC to 60oC. Rf = 2 MW R1 = 200 kW Assuming that after nulling at 25°C, the output voltage Vo = 0. At a temperature of 60oC, calculate what would be the maximum change in output voltage due to (a) drift in VOS and (b) drift in IOS. C 2.27 The frequency response plot of IC 741C is shown in Fig. 2.18(b). Find the gain that can be used to have a maximally flat response at B 100 kHz. 2.28 Define (a) bandwidth with feedback and A (b) unity gain-bandwidth.

2.34

2.35 2.36

2.37 2.38

2.39 2.40

2.41

2.42 2.43

A Define slew rate and what causes it? How is the slew rate measured? A What is meant by the roll-off rate? A A non-inverting amplifier has a gain of 200 and it is nulled at 25°C. What is the change in output voltage that can be expected at an increased temperature of 60°C for an offset B voltage drift of 0.2 mV/ °C ? Assume that an op-amp 741 connected as a unity gain inverting amplifier has an input change of 8 V. What is the time taken for the B output to change by 8 V? Assuming the slew rate for an op-amp is 0.6 V/ms, what is the maximum undistorted sine-wave that can be obtained for (a) 10 V peak and (b) 1 V peak? C Define full power bandwidth. How is it B related to the slew rate of the op-amp? The output voltage of a certain op-amp circuit changes by 10 V in 3 ms. What is its A slew rate? Explain the difference between slew rate and B transient response. Compare the frequency response of a compensated and an uncompensated op-amp. A Define Bode plot. What is the effect of the frequency of operation on the maximum unclipped output signal capability of an op-amp? B With a circuit diagram, explain how frequency compensation is obtained in an B operational amplifier. Briefly explain the need for compensating B networks in op-amps. What are the types of frequency compensation techniques used in op-amps? Explain in detail. A

2.44 What is the type of internal frequency compensation used in IC 741? Explain. A 2.45 What is the need for compensation? What are the effects of compensation on the response characteristics? C

Operational Amplifiers

79

2.46 Discuss the following with respect to an operational amplifier. (a) CMRR (b) Slew rate (c) Offset voltage (d) PSRR and A (e) Unity gain-bandwidth

2.58 Write the effect of variations in power supply B voltages on offset voltage. 2.59 The power supply rejection of an op-amp is 80 dB for a 1 V change in supply voltage. B Calculate the change in offset voltage.

2.47 Write the parameter values for an ideal op-amp: CMRR, offset current, output A impedance, input impedance. A 2.48 Define CMRR of an op-amp. 2.49 Briefly explain the need for compensating B network in op-amps. 2.50 Draw the voltage transfer characteristic of an B IC op-amp and explain. 2.51 Explain the principle of Miller compensation A technique.

2.60 What is the difference between compensated B and non-compensated op-amp? 2.61 Sketch the open-loop response of opamp and explain the same. What is the need for compensation? What are the effects of compensation on the response B characteristics? 2.62 What precautions must you take to ensure that your amplifier always operates in the linear region? C

2.52 Explain the Miller frequency compensation A technique employed in IC 741. 2.53 Name all the basic terminals of an op-amp. A

2.54 With the help of a block diagram explain the various stages present in an operational A amplifier. 2.55 An op-amp has a unity gain-bandwidth of 2 MHz for a signal of frequency 1 kHz. What A is the open-loop gain? 2.56 List the features of IC 741. A 2.57 Explain the following terms: (i) Offset current, (ii) Input capacitance and (iii) Large A signal voltage gain.

2.63 Draw the transfer characteristics of an operational amplifier and explain linear and B non-linear operation. 2.64 In response to a square wave input, the output of an op-amp changes from –3 V to + 3 V over a time interval of 0.25 ms. Determine the slew B rate of the op-amp. 2.65 What are the op-amp parameters? Why are B they needed to be measured? 2.66 Devise simple test circuits for the measurement of the following parameters and explain: i) Offset, ii) Bias current, iii) dc gain, iv) ac gain, v) dc CMRR, vi) dc PSRR, vii) ac B CMRR and viii) Slew rate

Objective-Type Questions 2.1 The operational amplifier consists of the three main stages, namely input stage, _________ A and output stage. 2.2 Feedback in an op-amp is provided for (a) Increasing the gain (b) Increasing the input impedance (c) Linear gain control B (d) To reduce the effect of offset

2.3 The high value of CMRR makes the output ________ when input signal with wide variation is applied (a) Low (b) High (c) Same B (d) Approximately the same

80

Linear IC Applications

2.4 The offset voltage occurs due to (a) Mismatched devices (b) Noise (c) Power supply B (d) All of these 2.5 The non-ideal dc characteristics of the opamp are (a) Input bias current (b) Input offset current (c) Input offset voltage A (d) All of these 2.6 The individual gain of the three stages of an op-amp are 1, 10 and 5. The overall gain is (a) 50 (b) 16 A (d) 15 (c) 11 5 2.7 Slew rate is an important parameter while working with (a) Low signal level (b) Medium signal level (c) Large signal level B (d) Any signal 2.8 The slew rate is identified with the unit (a) milliVolt/second (b) microVolt/second (c) Volt/millisecond A (d) Volt/microsecond 2.9 An op-amp for large signal and high frequency amplification requires primarily the specification namely, (a) PSRR (b) Slew rate (c) CMRR B (d) Frequency compensation 2.10 The closed loop gain of ________ amplifier is larger. (a) An inverting amplifier (b) A non-inverting amplifier (c) A voltage follower B (d) A current amplifier 2.11 The input resistance of the IC 741 is of the order of _______ (a) 1 to 10 kW (b) kW (c) Few tenths of MW (d) MW A

2.12 The ratio of change in input offset voltage with variation in supply voltage is called (a) Transient response (b) Input offset voltage stability (c) PSRR B (d) CMRR 2.13 A general purpose op-amp has a PSRR rating of 100 dB. This means that a 1 V change in the power supply produces an input offset voltage variation of (a) 1 mV (b) 1 mV (c) 10 mV (d) 10 mV C 2.14 The offset null terminals of IC 741 are (a) pins 1 and 5 (b) pins 2 and 6 (c) pins 1 and 4 (d) pins 4 and 5 A 2.15 The magnitude of open loop gain of an opamp is given by A0 (a) 1 + ( f / f1) 2 (b)

(c)

A0 1 + ( f1 / f ) 2 A0 1 - ( f / f1 ) 2

B (d) None of these 2.16 The compensating resistor Rcomp is given by

(a) R1 + Rf (c) R1 +

1 Rf

(b) R1 – Rf (d)

R1 R f

A

R1 + R f

2.17 The bandwidth of closed loop amplifier is given by A0 f1 AD AD (c) A0 f1 (a)

AD f1 A0 A0 AD (d) f1 (b)

B

2.18 The compensation method that leads to reduced bandwidth is (a) Phase lead compensation (b) Pole-zero compensation (c) Miller effect B (d) dominant pole

Operational Amplifiers

2.19 The full power bandwidth of an op-amp is (a) The maximum frequency of the output voltage with full swing achieved (b) Always zero (c) Always infinity (d) Always greater than the unity gain cross B over frequency 2.20 An ideal op-amp has ________ gain, _______ input impedance and _____ input impedance. (a) 0, 0, • (b) •, 0, 0 B (c) a, a, 0 (d) 0, a, 0

2.21 A virtual ground is the ground for (a) Voltage (b) Current (c) Voltage and current (d) None of these C 2.22 An op-amp with a common-mode gain of 1 dB and a differential gain of 100 dB will have CMRR of (a) 50 (b) 40 C (c) 100 (d) 1

Answers to Objective-Type Questions 2.1 2.6 2.11 2.16

(gain stage) (a) (c) (d)

2.2 2.7 2.12 2.17

(c) (c) (c) (a)

2.3 2.8 2.13 2.18

(b) (d) (d) (d)

81

2.4 2.9 2.14 2.19

(a) (b) (a) (a)

2.5 2.10 2.15 2.20

(d) (b) (a) (c)

Chapter

3 3.1

Linear and Non-Linear Applications of Op-Amps

IntroductIon

The op-amp originally developed to cater to the requirements of analog computer designers is a high gain, direct coupled amplifier. The voltage gain can be controlled by externally connected feedback components. It can be used in amplifier and signal processing applications involving dc to several MHz of frequency ranges. The operational amplifier circuits can be designed with various types of active devices. However, IC technology is remarkably successful in offering low-cost, high-performance and versatile op-amps in a monolithic form, and the op-amp became a widely accepted building block for circuit designers. The IC op-amps when operated in negative feedback configuration, find several applications in waveshaping, filtering and in solving mathematical operations. On the other hand, the operational amplifier when operated in open loop configuration exhibits non-linear characteristics. This feature finds use in many applications where the output needs to be switched between positive and negative saturation levels. Positive feedback can also be employed in these circuits to obtain hysteresis characteristics, i.e., to provide the upper and lower input voltage levels that trigger the output voltage to change from one saturation level to the other. Hence, this chapter discusses several applications of op-amp operating with negative feedback in closed loop configuration, followed by the non-linear circuits using op-amp in open-loop configuration.

3.2

open-Loop op-Amp confIgurAtIons

The term open-loop indicates that no feedback in any form is fed to the input from the output. When connected in open-loop, the op-amp functions as a very high gain amplifier. The three open-loop configurations of op-amp are: (i) Differential amplifier (ii) Inverting amplifier (iii) Non-inverting amplifier The above classification is made based on the number of inputs used and the terminal to which the input is applied. The op-amp amplifies both ac and dc input signals. Thus, the input signals can be either ac or dc voltages.

Linear and Non-Linear Applications of Op-Amps Vi 1

3.2.1 Open-loop Differential Amplifier In this configuration, the inputs are applied to the inverting and the non-inverting input terminals of the op-amp and it amplifies the difference between the two input voltages. Figure 3.1 shows the open-loop differential amplifier configuration. The input voltages are represented by Vi1 and Vi2. The source resistances Ri1 and Ri 2 are negligibly small in comparison with the very high input resistance offered by the op-amp, and thus the voltage drop across these source resistances is assumed to be zero. The output voltage Vo is given by Vo = A(Vi1 – Vi2)

(3.1)

83

+

b

Vo = A Vi 1 – Vi 2

g

Vi d – Vi 2 Ri1

Ri 2 +

+ Vi 2 Signal – source

Vi1

Signal source

RL

–

Fig. 3.1

Open-loop differential amplifier

where A is the large-signal voltage gain. Thus, the output voltage is equal to the voltage gain A times the difference between the two input voltages. Hence, this configuration is called a differential amplifier. In openloop configurations, the large-signal voltage gain A is also called open-loop gain A.

3.2.2

Inverting Amplifier

+ Vo = –AVi Vid

In this configuration, the input signal is applied to the inverting input terminal of the op-amp and the non-inverting input terminal is connected to the ground. Figure 3.2 shows the circuit of an open-loop inverting amplifier. The output voltage is 180° out-of-phase with respect to the input and hence, the output voltage Vo is given by

– RL Ri + Signal source

Vo = –AVi

Vi –

Thus, in an inverting amplifier, the input signal is amplified by the open-loop gain A and is phase-shifted by 180°. Fig. 3.2

3.2.3

Open-loop inverting amplifier

Non-inverting Amplifier

Figure 3.3 shows the open-loop non-inverting amplifier. The input signal is applied to the non-inverting input terminal of the op-amp and the inverting input terminal is connected to the ground. The input signal is amplified by the open-loop gain A and the output is in-phase with the input signal. Vo = AVi In all the above open-loop configurations, only very small values of input voltages can be applied. Even for voltage levels slightly greater than zero, the output is driven into saturation, which is observed from the ideal transfer characteristics of op-amp shown in Fig. 2.10(b). Thus, when operated in the open-loop

+ Vo = AVi Vid – RL Ri Signal source

+ Vi –

Fig. 3.3

Open-loop non-inverting amplifier

84

Linear IC Applications

configuration, the output of the op-amp is either in negative or positive saturation, or switches between positive and negative saturation levels. This prevents the use of open-loop configurations of op-amps in linear applications.

3.2.4

Limitations of Open-loop Op-amp Configurations

Firstly, in the open-loop configurations, clipping of the output waveform can occur when the output voltage exceeds the saturation level of op-amp. This is due to the very high open-loop gain of the op-amp. This feature actually makes it possible to amplify very low frequency signal of the order of microvolts or even less, and the amplification can be achieved accurately without any distortion. However, signals of such magnitudes are susceptible to noise and the amplification for those applications is almost impossible to obtain in the laboratory. Secondly, the open-loop gain of the op-amp is not a constant and it varies with changing temperature and variations in power supply. Also, the bandwidth of most of the open-loop op-amps is negligibly small. This makes the open-loop configuration of op-amp unsuitable for ac applications. The open-loop bandwidth of the widely used IC 741 is approximately 5 Hz. But in almost all ac applications, the bandwidth requirement is much larger than this. For the reasons stated, the open-loop op-amp is generally not used in linear applications. However, the open-loop op-amp configurations find use in certain non-linear applications such as comparators, square-wave generators and astable multivibrators.

3.3

cLosed-Loop op-Amp confIgurAtIons

The op-amp can be effectively utilised in linear applications by providing a feedback from the output to the input, either directly or through another network. If the signal feedback is out-of-phase by 180° with respect to the input, then the feedback is referred to as negative feedback or degenerative feedback. Conversely, if the feedback signal is in-phase with the input signal, then the feedback is referred to as positive feedback or regenerative feedback. The op-amps when used as a closed-loop amplifier may employ either active devices, passive components, or the combination of both. The intended application of the circuits decides the selection of components. In any case, the closed-loop amplifier can be represented using two functional blocks, one depicting the op-amp and the other showing the feedback circuit block. The main configurations of these circuits are decided by two factors, namely, (i) whether voltage or current is fedback to the input from the output and (ii) whether the feedback signal is connected in series or parallel. The four different basic types of configurations using an amplifier A and feedback circuit are shown in Figs. 3.4(a) to (d). Figures 3.4(a) and (b) illustrate the voltage output across load resistor feedback to the input in voltage series and voltage-shunt feedback configurations, respectively. Figures 3.4(c) and (d) show that the output current iL flowing through the load resistor is applied as input through the feedback circuit in series and parallel configurations, respectively. Figures 3.5(a) to (d) illustrate the corresponding four types of feedback configurations while using op-amps. The most commonly employed configurations are the voltage-series and voltage-shunt feedback types. The following sections discuss the voltage-shunt or the inverting amplifier and the voltage-series or the noninverting amplifier circuits using op-amps. An op-amp that uses feedback is called a closed-loop amplifier. The most commonly used closed-loop amplifier configurations are (i) Inverting amplifier (voltage-shunt feedback) and (ii) Non-inverting amplifier (voltage-series feedback).

Linear and Non-Linear Applications of Op-Amps

Fig. 3.4

Four types of feedback configurations: (a) Voltage-series, (b) Voltage-shunt (c) Current-series (d) Current-shunt

Fig. 3.5

Four types of feedback configurations for op-amps: (a) Voltage-series (b) Voltage-shunt

85

86

Linear IC Applications

Fig. 3.5

3.3.1

Four types of feedback configurations for op-amps: (c) Current-series (d) Current-shunt

Inverting Amplifier

The inverting amplifier is shown in Fig. 3.6(a), and its alternate circuit arrangement is shown in Fig. 3.6(b), with the circuit redrawn in a different way to illustrate how the voltage shunt feedback is achieved. The input signal drives the inverting input of the op-amp through resistor RL. The op-amp has an open-loop gain of A, so that the output signal is much larger than the error voltage. Because of the phase inversion, the output signal is 180° out-of-phase with the input signal. This means that the feedback signal opposes the input signal and the feedback is negative or degenerative.

Virtual Ground A virtual ground is a ground which acts like a ground. It may not have physical connection to ground. This property of an ideal op-amp indicates that the inverting and non-inverting terminals of the op-amp are at the same potential. The non-inverting input is grounded for the inverting amplifier circuit. This means that the inverting input of the op-amp is also at ground potential. Therefore, a virtual ground is a point that is at the fixed ground potential (0 V), even if it is not practically connected to the actual ground or common terminal of the circuit. The open-loop gain of an op-amp is extremely high, typically 2,00,000 for IC 741. For example, when the output voltage is 10 V, the input differential voltage Vid is given by Vid =

Vo 10 = = 0.05 mV A 200, 000

Furthermore, the open-loop input impedance of the IC 741 is around 2 MW. Therefore, for an input differential voltage of 0.05 mV, the input current is Ii =

Vid 0.05 mV = = 0.25 nA Ri 2 MW

Linear and Non-Linear Applications of Op-Amps

Fig. 3.6

87

Closed-loop inverting amplifier

Since the input current is so small compared to all other signal currents, it can be approximated as zero. For any input voltage applied at the inverting input, the input differential voltage Vid is negligibly small and the input current is ideally zero. Hence, the inverting input of Fig. 3.6(a) acts as a virtual ground. The term virtual ground signifies a point whose voltage with respect to ground is zero, and yet no current can flow into it. The expression for the closed-loop voltage gain of an inverting amplifier can be obtained from Fig. 3.6(a). Since the inverting input is at virtual ground, the input impedance is the resistance between the inverting input terminal and the ground. i.e., Zi = R1. Therefore, all of the input voltage appears across R1 and it sets up a current through R1 that equals V I1 = i (3.2) R1 This current must flow through Rf, because the virtual ground accepts negligible current. The left end of Rf is ideally grounded, and hence the output voltage appears only across the resistor Rf. Therefore, Vo =–I2Rf = –

Rf R1

Vi

(Since I2 = I1)

(3.3)

The closed-loop voltage gain Av is given by Av =

Vo - R f = Vi R1

(3.4)

The input impedance can be set by selecting the input resistor R1. Moreover, the above equation shows that the gain of the inverting amplifier is set by selecting a ratio of feedback resistor Rf to the input resistor R1. The ratio Rf /R1 can be set to any value less than or greater than unity. This feature of the gain equation makes the inverting amplifier with feedback very popular and it lends this configuration to a majority of applications.

88

Linear IC Applications

Example 3.1 For the closed-loop inverting amplifier shown in Fig. 3.6(a), Rf = 10 kW and R1 = 1 kW. Determine the closed-loop voltage gain Av . Solution

The closed-loop voltage gain is Av = –

Rf R1

=–

10 = - 10 1

The gain is 10 and the negative sign indicates the inverting mode or 180o phase-shift obtained at the output with respect to the input.

Practical Considerations (i) Setting the input resistance R1 to be too high will pose problems for the bias current, and hence it is usually restricted to 10 kW. (ii) The closed loop gain cannot be set very high due to the upper limit set by the gain-bandwidth (GBW = Av ¥ f ) product. The Av is normally below 100. (iii) The peak output of the op-amp is limited by the power supply voltages, and it is about 2 V less than the supply voltage, beyond which, the op-amp enters into saturation. (iv) The output current may not be short-circuit limited, and heavy loads may damage the op-amp. When short-circuit protection is provided, a heavy load may drastically distort the output voltage.

3.3.2

Practical Inverting Amplifier

The practical inverting amplifier has the following characteristics, namely, a finite value of input resistance and input current, its open loop voltage gain A is less than infinity and its output resistance Ro is not zero, as against the ideal inverting amplifier with infinite input resistance, infinite open-loop voltage gain and zero output resistance respectively. Figure 3.7(a) shows the low frequency equivalent circuit model of a practical inverting amplifier. This circuit can be simplified using the Thevenin’s equivalent circuit shown in Fig. 3.7(b). The signal source Vi and the resistors R1 and Ri are replaced by their Thevenin’s equivalent values. The closed-loop gain Av and the input resistance Rif are calculated as follows. The input impedance of the op-amp is normally much larger than the input resistance R1. Therefore, we can assume Veq @ Vi and Req @ R1. From Fig. 3.7(b), we get and

Vo = I1 Ro + AVid

(3.5)

Vid + I1Rf + Vo = 0

(3.6)

Rf R1

–

+ Ro

+

Vid

Vi –

Ri +

Fig. 3.7

Vo

+ AVid –

–

(a) equivalent circuit of a practical inverting amplifier

Fig. 3.7

(b) thevenin’s equivalent circuit

Linear and Non-Linear Applications of Op-Amps

89

Substituting the value of Vid from Eq. (3.6) in Eq. (3.5), we get Vo (1 + A) = I1(Ro – ARf)

(3.7)

Rf

Further, using the Kirchhoff’s voltage law, we get Vi = I1(R1 + Rf) + Vo (3.8) Substituting the value of I1 derived from Eq. (3.7) in Eq. (3.8) and solving for closedloop gain Av, we get Av =

Ro - AR f Vo = Vi Ro + R f + R1 (1 + A)

R1 –

I1

Vid

+ Ro

Veq = Vi

Isc

+ Io

AVid –

(3.9)

Rof

Fig. 3.7

(c) equivalent circuit to determine Ro

It can be observed from Eq. (3.9) that when A >> 1, Ro is negligibly small and the product AR1 >> Ro + Rf + R1, the closed-loop gain is given by Av @ –

Rf R1

which is of the same form as given in Eq. (3.4) for an ideal inverter.

Input Resistance Rif From Fig. 3.7(b), we get Rif =

Vid I1

Using Kirchhoff’s voltage law, we get, Vid + I1(Rif + Ro) + AVid = 0 which can be simplified for Rif as R f + Ro V Rif = id = I1 1+ A

(3.10)

Output Resistance Rof Figure 3.7(c) shows the equivalent circuit to determine Rof . The output impedance Rof without the load resistance factor RL is calculated from the open circuit output voltage Voc and the short circuit output current Isc. From Fig. 3.7(c), when the output is short circuited, we get

and

I1 =

Vi - 0 R1 + R f

(3.11)

Io =

AVid Ro

(3.12)

We know that Vid = – I1Rf. Therefore,

Io = –

AI1 R f Ro

(3.13)

90

Linear IC Applications

The short-circuit current is Isc = I1 + Io = Vi The output resistance Rof = Therefore, Rof =

( Ro - AR f ) Ro ( R1 + R f )

(3.14)

Voc V and the closed-loop gain Av = oc . I sc Vi

AvVi È ( Ro - AR f ) ˘ Vi Í ˙ ÍÎ Ro ( R1 + R f ) ˙˚

(3.15)

Substituting the value of Av from Eq. (3.9), we get Rof =

=

Ro R1 + R f

(

)

Ro ( R1 + R f

)

Ro + R f + R1 (1 + A) Ro + R1 + R f

È R1 A Í1 + Ro + R1 + R f ÍÎ

˘ ˙ ˙˚

(3.16)

In the above equation, the numerator contains the term Ro ΩΩ(R1 + Rf) and it is smaller than Ro. The output resistance Rof is therefore always smaller than Ro and for A Æ •, the output resistance Rof Æ 0.

3.3.3

Non-inverting Amplifier

The non-inverting amplifier with input signal applied to the non-inverting input and the output voltage fedback to the inverting input, i.e., in voltage-series mode is shown in Fig. 3.8(a). Figure 3.8(b) represents the simplified and usual circuit arrangement. The op-amp provides an internal gain A. The external resistors R1 and Rf form the feedback voltage divider circuit with an attenuation factor of b. Since the feedback voltage is at the inverting input, it opposes the input voltage at the non-inverting input terminal, and hence, the feedback is negative or degenerative. The differential voltage Vid at the input of the op-amp is zero, because node a is at the same voltage as that of the non-inverting input terminal. As shown in Fig. 3.8(a), Rf and R1 form a potential divider. R1 (3.17) Therefore, Vi = ¥ Vo R1 + R f Since no current flows into the op-amp, Equation (3.17) can be written as Rf Vo R1 + R f . = =1+ Vi R1 R1 Hence, the voltage gain for the non-inverting amplifier is given by Av =

Rf Vo =1+ Vi R1

Linear and Non-Linear Applications of Op-Amps

91

Using the alternate circuit arrangement shown in Fig. 3.8(b), the feedback factor of the feedback voltage divider network is R1 b= (3.18) R1 + R f Therefore, the closed-loop gain is 1 R1 + R f Av = = b R1 Rf =1+ R1

(3.19) (3.20)

From the above equation, it can be observed that the closed-loop gain is always greater than one and it depends on the ratio of the feedback resistors. If precision resistors are used in the feedback network, a precise value of closed-loop gain can be achieved. The closed-loop gain does not drift with temperature changes or op-amp replacements. The input resistance of the op-amp is extremely large (approximately infinity), since the op-amp draws negligible current from the input signal.

Fig. 3.8

(a) Closed-loop non-inverting amplifier (b) Its alternate circuit arrangement

Example 3.2 The variable resistance varies from zero to 100 kW. Find out the maximum and the minimum closed-loop voltage gain. Solution

Given circuit is a non-inverting amplifier (Fig. 3.9). Therefore, AVf = 1 + Here, When When

Rf R1

and R1 = 2 kW 0 =1 Rf = 0, AVf = 1 + 2 ¥ 103 100 ¥ 103 Rf = 100 kW, AVf = 1 + = 51 2 ¥ 103

Rf

Rf = 0 – 100 kW

R1

Fig. 3.9

92

Linear IC Applications

Example 3.3 Design a non-inverting amplifier circuit which is capable of providing a voltage gain of 15. Assume an ideal op-amp and the resistances used should not exceed 30 kW. Solution

Given

ACL = 15 ACL = 1 +

i.e., Therefore, i.e.,

15 = 1 + Rf R1

Rf R1 Rf

o

R1

= 14 Fig. 3.10

Rf = 14R1

Selecting R1 = 1 kW, we get Rf = 14 kW The designed circuit is shown in Fig. 3.10. Example 3.4

Determine the output voltage Vo for the non-inverting amplifier circuit shown in Fig. 3.11(a).

Solution

R This non-inverting amplifier will amplify Vi1 by 1 + f and not Vi. Since the op-amp input current is zero, a R1 part of the circuit is as shown in Fig. 3.11(b). Rf

R1

Fig. 3.11(a)

Therefore, I = and

1 1 ¥ 10 + 1 ¥ 103 3

= 0.5 mA

Vi1 = I ¥ (1 ¥ 103) = 0.5 ¥ 10–3 ¥ 103 = 0.5 V

Rf ˆ Ê Ê 50 ¥ 103 ˆ V + = 1 Therefore, Vo = Á1 + 1 i Á ˜ 0.5 = 3 V R1 ˜¯ Ë 10 ¥ 103 ¯ Ë

Fig. 3.11(b)

Linear and Non-Linear Applications of Op-Amps

Example 3.5

93

For a non-inverting amplifier shown in Fig. 3.12, determine (a) Av (b) Vo (c) IL and (d) Io.

Solution

The potential of the non-inverting input terminal is Vi. Therefore, Vi2 = Vi1 = Vi = 0.6 V I1 =

I1

Vi 2 Vi 0.6 = = = 60 m A R1 R1 10 ¥ 103

Since the input current into op-amp is zero, the current can flow only through Rf. (a) Av = 1 +

Rf R1

=1+

20 =3 10

(b) Vo = Av Vi = 3 ¥ 0.6 = 1.8 V Vo 1.8 = 0.9 mA (c) IL = R = 2 ¥ 103 L

Fig. 3.12

(d) Applying Kirchhoff’s current law at the output node, we get Io = I1 + IL = 60 ¥ 10–6 + 0.9 ¥ 10–3 = 0.96 mA The current Io flows from op-amp towards output terminal.

3.3.4

Practical Non-inverting Amplifier

The equivalent circuit of a non-inverting amplifier using the low frequency model is shown in Fig. 3.13.

Fig. 3.13

equivalent circuit of a non-inverting amplifier using low frequency model

Using Kirchhoff’s current law at node a, (Vi – Vid)Y1 – VidYi + (Vi – Vid – Vo)Yf = 0 i.e.,

– (Y1 + Yi + Yf)Vid + (Y1 + Yf)Vi = Yf Vo

(3.21)

Similarly, Kirchhoff’s current law at the output node gives (Vi – Vid – Vo)Yf + (AVid – Vo)Yo = 0 i.e.,

(

)

(

)

- Y f - AYo Vid + Y f Vi = Y f + Yo Vo

(3.22)

94

Linear IC Applications

Using Eqs (3.21) and (3.22), we get Av =

(

)

AYo Y1 + Y f + Y f Yi Vo = Vi ( A + 1) YoY f + (Y1 + Yi ) Y f + Yo

(

)

(3.23)

When the open-loop gain A approaches infinity, Eq. (3.23) becomes

(

AYo Y1 + Y f AYoY f

) = Y +Y 1

f

Yf

It can be written as Av = 1 +

=1+

Rf R1

Y1 Yf

, and it may be noted that it is of the form as given in Eq. (3.20).

IntegrAtor

3.4

A circuit in which the output voltage waveform is the time integral of the input voltage waveform is called integrator or integrating amplifier. Integrator produces a summing action over a required time interval and the circuit is based on the general parallel-inverting voltage feedback model.

3.4.1

Ideal Integrator

In order to achieve integration, the basic inverting amplifier configuration shown in Fig. 3.6 can be used with the feedback element Zf replaced by a capacitor Cf as shown in Fig. 3.14. The expression for the output voltage vo(t) can be obtained by applying Kirchhoff’s current law at node a as given by ii = iB + i f Since iB is negligibly small, i1 = if The current through the capacitor if (t ) = Cf Therefore,

vi (t ) - va (t ) R1

= Cf

d vc (t ) dt

Fig. 3.14

Integrator circuit

d (va (t ) - vo (t )) dt

However, vb (t ) = va (t ) = 0 because the gain of the op-amp Av is very large. Therefore, vi (t ) d = Cf ( -vo (t )) R1 dt Integrating both sides with respect to time, we get t

Ú 0

vi (t ) R1

t

dt = Ú C f 0

d ( - vo (t )) dt = - C f vo (t ) + vo (0) dt

Linear and Non-Linear Applications of Op-Amps

95

Therefore, vo (t ) = -

1 R1C f

t

Ú vi (t ) dt + vo (0)

(3.24)

0

where vo(0) is the integration constant and is proportional to the value of the output voltage vo(t) at t = 0. Equation (3.24) indicates that the output voltage is directly proportional to the negative integral of the input voltage and inversely proportional to the time constant R1Cf. In frequency domain, the above equation becomes Vo ( s ) = -

1 Vi ( s ) sR1C f

(3.25)

Letting s = jw in steady-state, we get Vo ( jw ) = -

1 Vi ( jw ) jw R1C f

(3.26)

Hence, the magnitude of the transfer function of the integrator is A=

Vo ( jw ) Vi ( jw )

=

(

j

w R1C f

)

=

1 w R1C f

(3.27)

At w = 0, the gain of the integrator is infinite. Also, the capacitor acts as an open circuit and hence, there is no negative feedback. Thus, the op-amp operates in open loop and hence the gain becomes infinite (or the op-amp saturates). In practice, the output will never become infinite. As the frequency increases, the gain of the integrator decreases. The input sinusoidal and square waveforms and the corresponding output waveforms of integrator circuit using op-amp are shown in Figs. 3.15(a) and (b).

wt

wt

Fig. 3.15

(a) Sine-wave input and its integrated cosine output and (b) Square-wave input and its triangular output

96

Linear IC Applications

3.4.2

Limitations of an Ideal Integrator

Even in the absence of input signal, the two components, namely, the offset voltage and the bias current contribute for an error voltage at the output. Thus, it is not possible to get a true integration of the input signal at the output. The output waveform is distorted due to this error voltage. Further, the bandwidth of an ideal integrator is very small. Hence, an ideal integrator can be used for very small ranges of input frequency only. In the ideal integrator circuit, a small dc offset at the input can force the output into saturation. To avoid this, a resistor is placed in parallel with the integrator capacitor to limit the low frequency gain. However, this has an undesirable side effect of limiting the useful integration range at higher frequencies. Due to the above limitations, an ideal integrator is not used in practice. A few additional components are used along with the ideal integrator circuit to minimise the effect of the error voltage. Such an integrator is called the practical integrator.

Integrator Errors The integrator errors are the deviations from the ideal behaviour found in a practical integrator circuit. The major sources of error are the offset and drift of the op-amp. The op-amp’s input offset voltage and bias current of an op-amp makes possible the continuous charging of feedback capacitor even in the absence of an input signal. As a result, the op-amp output can drift into the positive or negative saturation. The error component at the output due to the op-amp bias current can be compensated by connecting a resistor of the same value as the integrating resistor between the non-inverting input and ground. The drift error can be minimised by the use of a large value capacitor. This makes the bias current contribution to the drift negligibly small. However, a large value of C needs a smaller value of R. To avoid drift by the dielectric absorption of the capacitor, polypropylene or polystyrene dielectric capacitors can be used. The use of low current FET input op-amps make low drift integrators with long-term stability realisable. They also allow the bias current contribution to drift negligibly small. This can eliminate the need of excessively large capacitors also.

3.4.3

Summing Integrator

The circuit diagram of a summing integrator is shown in Fig. 3.16, which is derived from the simple integrator shown in Fig. 3.15(a). Using Eq. (3.24), the output voltage for the summing integrator can be written as t 1 Ê v1 (t ) v2 (t ) v3 (t ) ˆ vo (t ) = + + dt + vo (0) C Ú ÁË R R R ˜¯ f 0

1

2

3

Taking Laplace transform, we get Vo ( s ) = -

1 Ê V1 ( s ) V2 ( s ) V3 ( s ) ˆ + + sC f ÁË R1 R2 R3 ˜¯

Fig. 3.16

Summing integrator

Linear and Non-Linear Applications of Op-Amps

3.4.4

97

Practical Integrator Circuit (ac Integrator circuit)

The practical integrator circuit (lossy integrator) is shown in Fig. 3.17(a). Here, the feedback capacitor is shunted by a resistor Rf so that the gain of the integrator at low frequency is limited to avoid any saturation problem. Since the parallel combination of resistor Rf and capacitor Cf dissipates power, this circuit is called a lossy integrator. The resistor Rf provides the dc stabilisation, by limiting the low frequency gain to –Rf /R1. The resistor Rcomp is given by Rcomp = R1ΩΩRf and when Rf >> R1, Rcomp = R1. At the inverting input terminal of the op-amp, the nodal equation may be written as Vi ( s ) R1

+ sC f Vo ( s ) +

Vo ( s )

Fig. 3.17

(a) practical integrator circuit

=0

Rf

Rearranging the above equation, we get Vo ( s ) = -

1 Vi ( s ) sR1C f + R1 / R f

Substituting s = jw, we get the transfer function as expressed by A=

R f /R1 Vo ( jw ) 1 = = 2 2 2 2 2 Vi ( jw ) w R1 C f + R1 / R f 1 + w Rf C f

(

)

. 2

When Rf is very large, the lossy integrator will approximately become an ideal integrator. At low frequencies, assuming the low level frequency to be fa, the gain is approximately equal to Rf /R1. At 3 dB level, the gain is 0.707(Rf /R1). Therefore,

(

1 + wRf C f

)

2

= 2

Solving for f = fa, we get 2p fa Rf Cf = 1 Hence,

fa =

1 . 2p R f C f

The frequency responses of the ideal integrator and the lossy integrator are shown in Fig. 3.17(b). The ideal integrator of Fig. 3.14 exhibits a –6 dB/octave (–20 dB/decade) slope through the useful integration range. The frequency fb is the frequency at which the transfer function or gain of the integrator is 1 or 0 dB, i.e. 1 1 1= . When the . Hence, fb = 2p fb R1C f 2p R1Cf input frequency is less than fa, the circuit will

0,

Fig. 3.17

(b) Frequency responses of the ideal and lossy integrators

98

Linear IC Applications

not act as an integrator and it will only act as a simple inverting amplifier. When the input frequency is equal to fa, there will be 50 per cent accuracy. As a thumb rule, if the input frequency is 10 times fa, then it results in 99 per cent of accuracy.

3.4.5

Initial Condition

The circuit shown in Fig. 3.18 sets the initial condition for the integrator circuit as required for some applications. When the ganged switch S is turned ON or moved to position 1 initially before powering the op-amp, the capacitor Cf immediately charges to the voltage Vc of the battery. When the switch S is moved to position 2, the op-amp circuit with the feedback capacitor Cf and input resistor R1 acts as an integrator with the initial conditions as set by the battery Vc. Fig. 3.18 Integrator circuit with initial condition The capacitor is normally chosen to have very low leakage, such as Teflon, Polystyrene or Mylar dielectric capacitors are preferred.

3.4.6 Applications of Integrators Integrators may be used in combination with summers and amplifiers to form analog computers which are used to model a variety of physical systems in real time. The integrator circuits are used as waveshaping circuits and used to convert square-waves into triangular waves. Further they are used for solving differential equations in analog to digital converters and ramp generators. Example 3.6 Assuming R1 = 10 kW, Rf = 100 kW and Cf =10 nF in a practical integrator circuit of Fig. 3.17(a), determine the lower frequency limit of integration and the output response for the inputs (a) sine-wave (b) square-wave and (c) step input. Solution

Given R1 = 10 kW, R f = 100 kW and Cf = 10 nF . The lower frequency limit of integration is fa = =

1 2p R f C f 1

2p ¥ 100 ¥ 103 ¥ 10 ¥ 10-9

= 159 Hz

For accurate integration, the input frequency must be at least one decade above fa, i.e. 1590 Hz. (a) For the sine-wave input For an input of 1 V peak sine-wave at 2.5 kHz, the output vo is 1 vo (t ) = vi (t )dt R1C f Ú 1 1 sin (2p ¥ 2500t ) dt =3 10 ¥ 10 ¥ 10 ¥ 10- 9 Ú = -104 Ú sin (2p ¥ 2500t ) dt

Linear and Non-Linear Applications of Op-Amps

=-

99

104 [- cos(2p ¥ 2500t )] 2p ¥ 2500

= 0.637 cos(2p ¥ 2500t ) The output is a cosine wave with peak amplitude of 0.637 V only as shown in Fig. 3.19(a). (b) For the square-wave input The output waveform for an input of 2.5 kHz, 1V peak square-wave is shown in Fig. 3.19(b). It can be seen that the input is of constant amplitude of 1 V from 0 to 0.2 ms and –1 V from 0.2 ms to 0.4 ms. The output for each of these half periods will be ramps as seen above for step inputs. Thus, the expected output waveform will be a triangular wave. The peak value of the output for first half cycle is 0.2 ms 1 1 dt = –104 ¥ 0.2 ¥ 10–3 = –2 V vo = R1C f Ú0 This represents the total change in the output voltage over the first half cycle from 0 to 0.2 ms. Similarly, integration over the next half-cycle produces a positive change to reach 1 V. (c) For the step input If input is a step voltage V1 = 1 V for 0 £ t £ 0.6 ms, then the output voltage realised as shown in Fig. 3.19(c) is given by 1 vo = R1C f =-

0.6 ms

Ú

1 dt

0

1 10 ¥ 103 ¥ 10 ¥ 10-9

¥t

t = 0.6 ms t=0

= -104 ¥ 0.6 ¥ 10-3 = - 6 V

vi, vo vi 1V vo 0

0.2 ms

0.4 ms

t

–0.637 V

(a)

Fig. 3.19

Input and output waveforms for the integrator: (a) Sine-wave input, (b) Square-wave input (c) Step input

100

Linear IC Applications

dIfferentIAtor

3.5

The differentiator can perform the mathematical operation of differentiation, i.e. the output voltage is the differentiation of the input voltage. This operation is very useful to find the rate at which a signal varies with time.

3.5.1

Ideal Differentiator

The ideal differentiator is obtained by interchanging the position of the resistor and capacitor in the ideal integrator circuit, or it may be constructed from a basic inverting amplifier shown in Fig. 3.20, if the input resistor R1 is replaced by a capacitor C1. The ideal differentiator circuit is shown in Fig. 3.20.

Analysis The expression for the output voltage can be obtained from Kirchhoff’s Current Law applied at node a as follows: ic = I B + i f Since I B ª 0, ic = if That is,

C1

v - vo d (vi - va ) = a dt Rf

However, va= vb ª 0 V, since A is very large. Therefore, C1

or

d dt

Fig. 3.20

Differentiator

d vi v =- o dt Rf

vo = - R f C1

d vi dt

(3.28)

Thus, the output vo is equal to the RfC1 times the negative instantaneous rate of change of the input voltage vi with time. A differentiator performs the reverse of the integrator’s function. The upper cut-off frequency is given by fa =

1 2p R f C1

The input sinusoidal and square waveforms and the corresponding output waveforms of differentiator circuit using op-amp are shown in Figs 3.21(a) and (b).

3.5.2

Summing Differentiator

The circuit diagram of a summing differentiator is shown in Fig. 3.22, which is derived from the simple differentiator shown in Fig. 3.20. Using Eq. (3.28), the output voltage for the summing differentiator can be written as d v (t ) ˘ È d v (t ) vo (t ) = - R f ÍC1 1 + C2 2 ˙ dt dt ˚ Î È d v1 (t ) d v2 (t ) ˘ + For C1 = C2 , we get vo (t ) = - R f C1 Í dt ˙˚ Î dt

Linear and Non-Linear Applications of Op-Amps

101

wt

wt

Fig. 3.21

(a) Sine-wave input and its differentiated cosine output (b) Square-wave and its differentiated spike output

Fig. 3.22

Summing differentiator

Example 3.7 Design a differentiator to differentiate an input signal that varies in frequency from 10 Hz to about 1 kHz. Solution

The upper cut-off frequency fa = 1 kHz = Letting C1 = 1 m F, we have Rf =

3.5.3

1 2p R f C1

1 = 1.59 k W (2p )(103 )(10-6 )

Limitations of Differentiators

When compared to integrator circuits, the differentiator circuits are more susceptible to noise. The input noise fluctuations of small amplitudes will have large derivatives. When differentiated, these noise fluctuations will generate large noise signals at the output, which will introduce a poor signal-to-noise-ratio. This problem may be minimised by placing a resistor in series with the input capacitor. This modified circuit differentiates only low frequency signals with a constant high frequency gain.

102

Linear IC Applications

In a differentiator circuit, the limitations due to noise, stability and input impedance can pose problems. In order to minimise noise and aid in stability, a small capacitor may be placed in parallel with Rf, which will reduce the high frequency gain. In order to place a lower limit on the input impedance, a resistor may be connected in series with the differentiating capacitor. The addition of either component will limit the upper range of differentiation. As the frequency increases, the gain of the differentiator increases due to the reduction of input impedance 1 . Therefore, at high frequencies, the differentiator will become unstable due to very high gain X C1 = 2p fC1 and it may enter into saturation. This makes the circuit very sensitive to noise and the stability is affected. The noise component may override the signal also. These limitations are overcome using a practical differentiator circuit with additional components connected as discussed in the next section.

3.5.4

Practical Differentiator

A practical differentiator circuit is shown in Fig. 3.23. This eliminates the limitations of noise and stability. v -v v The effective current at the node a is zero. The input current iC = i a = i where Z1 = R1 in series with C1. Z1 Z1 Therefore, the input impedance Z1 = R1 + IC =

1 + sR1C1 1 = sC1 sC1

sC1Vi ( s )

(1 + sR1C1 )

The current if 1 flowing through Rf is given by if1 =

va - vo v =- o Rf Rf

Fig. 3.23

Taking Laplace transform, we get

if1 =

Vo ( s ) Rf

Similarly, the current if 2 flowing through Cf is given by d ( va - vo )

d vo = - Cf dt dt Taking Laplace transform, we get if 2 = Cf

i f 2 = - sC f Vo ( s ) Applying Kirchhoff’s Current Law at node a, we have IC = if1 + if2

practical differentiator

Linear and Non-Linear Applications of Op-Amps

Therefore,

sC1Vi ( s )

(1 + sR1C1 )

Simplifying, Vo ( s ) = -

=-

Vo ( s ) Rf

- sCf Vo ( s )

sR f C1Vi ( s )

(1 + sR C ) (1 + sR C ) f

103

f

(3.29)

1 1

The transfer function for the circuit is given by Vo ( s )

=

Zf

=-

sR f C1

(

)

Vi ( s ) Z i 1 + sR f C f (1 + sR1C1 ) Letting Rf Cf = R1C1, we get Vo ( s ) Vi ( s )

=-

sR f C1

(1 + sR1C1 )

2

=-

sR f C1 Ê f ˆ ÁË1 + j f ˜¯ b

2

(3.30)

(3.31)

1 . 2p R1C1 Eq. (3.31) shows that the gain increases at +20 dB/decade for frequency ranges of f < fb and decreases at the rate of –20 dB/decade for f > fb. It is shown as the gain characteristics in Fig. 3.24 in dotted lines. This 40 dB/decade variation in gain is due to the R1C1 and RfCf factors. For the ideal differentiator of Fig. 3.24, the frequency response would have steadily increased at 20 dB / decade even beyond fb, which could cause stability problems at high frequencies. The gain for the practical differentiator circuit is reduced significantly and this avoids the high frequency noise, and results in better stability. where fb =

Fig. 3.24

Frequency response of practical differentiator

The value fb is normally selected such that f a < fb < f c where fc denotes the unity gain-bandwidth of the op-amp in open loop configuration mode. For effective differentiation, the time period T of the input signal is given by T ≥ Rf C1 as indicated in Eq. (3.30).

104

Linear IC Applications

d vi . A compensation dt resistor Rcomp is normally connected at the non-inverting terminal of the op-amp to provide compensation for input bias current. When R1C1 and Rf Cf are much less than Rf C1, then Eq. (3.29) becomes, vo = - R f C1

3.5.5 Applications of Differentiators The differentiators can be used as waveshaping circuits. They can be used to convert triangular waves into square-waves. In fact, since differentiators tend to seek rapid changes in the input signal, they are quite useful as edge detectors in the FM demodulators. The integrators and differentiators may be used in combination with adders and amplifiers to form analog computers. Example 3.8 (a) Design a differentiator using op-amp to differentiate an input signal with fmax = 200 Hz. (b) Also draw the output waveforms for a sine-wave and a square-wave input of 1 V peak at 200 Hz. Solution

(a) Given f max = f a = 200 Hz fa =

1 2p R f C1

Assuming, C1 = 0.1 mF, we get Rf = Let us select

1 2p (200)(10-7 )

= 7.95 kW

fb = 10 f a = 2000 Hz

We know that fb = Therefore, R1 =

1 2p R1C1 1

2p (2000) (10-7 )

= 0.795 kW

Since R f C f = R1C1 , we get Cf =

0.795 ¥ 103 ¥ 10-7 7.95 ¥ 103

= 0.01 m F

(b) (i) For the sine-wave input, vi = 1 sin 2p (200)t We know that vo = - R f C1

d vi dt

= (7.95 kW) (0.1 m F)

d È(1 V ) sin(2 p ) (200)t ˘˚ dt Î

= (7.95 k W) (0.1 m F) (2p ) 200 cos ( 2p ¥ 200 t ) = - 1 cos (2p ¥ 200 t )

Linear and Non-Linear Applications of Op-Amps

105

The input and output waveforms are shown in Fig. 3.25(a). (ii) For the square-wave input with 1 V peak at 200 Hz, the output waveform will have positive and negative spikes of magnitude Vsat which is approximately ±13 V for ±15 V op-amp power supply. When the input is constant at ±1 V, the differentiated output will be zero. When the input transits between ±1 V level, the differentiated output will be infinite and gets clipped to about ±13 V for a ±15 V op-amp power supply as shown in Fig. 3.25(b).

0 wt

0 wt

Fig. 3.25

3.5.6

(a) Sine-wave input and its differentiated cosine output and (b) Square wave input and its differentiated spike output

Comparison between an Integrator and a Differentiator

Since the process of integration involves the accumulation of signal over time, sudden changes in the signal are suppressed. Therefore, an effective smoothing of the signal is achieved and integration can be viewed as low-pass filtering. Since the process of differentiation involves the identification of sudden changes in the input signal, constant and slowly changing signals are suppressed. Therefore, the differentiator can be viewed as a form of high-pass filtering.

3.6

dIfferentIAL AmpLIfIer

The differential amplifier, also called difference amplifier, can be constructed using a single op-amp or two op-amps with constant or variable gain in closed-loop configuration.

3.6.1

Differential Amplifier with Single Op-amp

The basic op-amp can be used as a differential amplifier as shown in Fig. 3.26(a). To analyse the operation of the circuit, assume that all resistors are equal of value R. The output voltage can be determined by using the superposition principle. It is assumed for analysis that R1 = R2 = R3 = Rf = R. Then, if Vi1 = 0 or grounded, then the output voltage Vo2 will be due to the input voltage Vi2 alone. Hence, the circuit shown in Fig. 3.26(a) becomes an inverting amplifier with the output voltage as given by Vo 2 = - [Vi 2 / 2] (1 + R / R ) = - Vi 2

106

Linear IC Applications

Similarly, if Vi2= 0, then the output voltage Vo1 will be due to Vi 1 alone. Hence, the circuit becomes a noninverting amplifier and the output voltage is given by Vo1 =

Vi1 Ê Rˆ Á1 + ˜¯ = Vi1 2 Ë R

(3.32) R1

Rf

+ Vi 2 – R2 = R1 Vid

– Vo +

+ Vi 1 –

R4 R 3 = Rf RP

Fig. 3.26

(a) Differential amplifier

Fig. 3.26

(b) Differential amplifier with variable gain

Now, considering that both the inputs are applied, the output voltage Vo is Vo = Vo1 + Vo 2 = Vi1 - Vi 2

(3.33)

Thus, the output voltage is proportional to the difference between the two input voltages. Hence, it acts as a difference amplifier and is also called differential amplifier. If the resistors are selected such that R f π ( R1 π R2 π R3), then the output voltage Vo is expressed by Rf Ê R f ˆ Ê R3 ˆ Vo = Á1 + Vi1 Vi 2 ˜ Á ˜ R1 ¯ Ë R3 + R2 ¯ R1 Ë

(3.34)

By changing the input resistors individually, difference amplifier for different strengths of input signals can be realized. Figure 3.26(b) shows the differential amplifier circuit with variable gain. This circuit has R1 = R2, R f = R4 and the potentiometer Rp = R4. Hence, based on the position of the variable terminal in RP, the voltage gain can be correspondingly varied.

Difference-mode Gain and Common-mode Gain For Eq. (3.34), if Rf = R and Vi2 = Vi1, then the output voltage Vo = 0. This means that the signal common to both the inputs compensate each other and produces no effective output voltage. This characteristic is true for an ideal op-amp based difference amplifier. However, a practical op-amp exhibits a small response to the common mode values of the input voltages also. The output voltage depends on the difference Vid between the input signals and it also depends on the common mode signal Vcm. This common mode signal Vcm is defined as V +V (3.35) Vcm = i1 i 2 2 Though the differential amplifier is symmetric, because of the mismatch between the circuit components, the gain at the output in response to the positive and negative terminal are found to be different in practice. Therefore, even with the same voltage applied at both the inputs, the output is not found to be zero.

Linear and Non-Linear Applications of Op-Amps

Then, the output can be expressed as Vo = A1Vo1 + A2Vo 2

107

(3.35a)

where A1 and A2 are the voltage amplification factors for the inputs Vi1 and Vi2 respectively, when the other input is grounded. Using Eq. (3.33) and the fact that Vid = (Vi1 - Vi 2 ), we get 1 Vi1 = Vcm + Vid 2 1 and Vi 2 = Vcm - Vid 2 Substituting the values of Vi1 and Vi2 from Eqs (3.36) and (3.37) in Eq. (3.35), we get Vo = AdmVid + AcmVcm where the difference mode gain Adm =

(3.36) (3.37)

(3.38) 1 ( A1 - A2 ) and the common mode gain Acm = A1 + A2. 2

Common-mode Rejection Ratio (CMRR) The common-mode rejection ratio is defined as the ratio of the differential mode gain Adm to the commonmode gain Acm. Adm (3.39) Acm This represents the figure of merit for the differential amplifier and it is usually represented in decibels (dB). For example, the IC mA 741 has a minimum CMRR of 70 dB and a precision op-amp such as mA 725 A has 120 dB for its CMRR. Higher the value of CMRR, better is the op-amp.

i.e.,

CMRR =

For a given op-amp, CMRR =105 and differential gain Adm = 105. Determine the commonmode gain Acm of the op-amp. Example 3.9

Solution

CMRR =

Adm = 105 Acm

Therefore, the common-mode gain Acm =

Adm 105 = 5 = 1. CMRR 10

Example 3.10 The two input terminals of an op-amp are connected to voltage signals of strengths 745 mV and 740 mV respectively. The gain of the op-amp in differential mode is 5 ¥ 105 and CMRR is 80 dB. Calculate the output voltage and % error due to common mode. Solution

Given CMRR = 80 dB, V1 = 745 mV, V2 = 740 mV, Ad = 5 ¥ 105 A CMRR in dB = 20 log dm Acm 5 ¥ 105 Therefore, 80 = 20 log Acm i.e.,

10000 =

5 ¥ 105 Acm

108

Linear IC Applications

Hence, common mode gain Acm = 50 Vo = Adm Vdm + Acm Vcm, where Vcm =

V1 + V2 and Vdm = V1 – V2 2

È 745 + 740 ˘ –6 = 5 ¥ 105 [745 – 740] ¥ 10 – 6 + 50 ¥ Í ˙ ¥ 10 = 2.5371 V 2 Î ˚ Ideal output Adm Vdm = 2.5 V Hence, % error =

2.5371 - 2.5 ¥ 100 = 1.484% 2.5

Example 3.11 A differential amplifier has a differential voltage gain of 2,000 and a common mode gain of 0.2. Determine the CMRR in dB. Solution

CMRR = Therefore,

Adm = 105 Acm

CMRR in dB = 20 log10

Adm 2000 dB = 20 log dB = 80 dB Acm 0.2

Limitations of the basic Differential Amplifier The two major limitations of the basic differential amplifier are (i) it has low input resistance and (ii) modifying the gain is cumbersome, since the resistor ratios must be closely matched. The first disadvantage can be eliminated by isolating or buffering the two inputs using voltage followers. This is realised by using two op-amps connected as voltage followers as discussed in the next subsection. The second limitation of the basic differential amplifier is the lack of adjustable gain feature. This can be eliminated by the use of three more resistors. This will be discussed as part of instrumentation amplifier circuit in the following section. The amplifier gain in such a circuit will be changed by only a single resistor.

3.7

InstrumentAtIon AmpLIfIer

Instrumentation amplifiers are used in monitoring and controlling of the physical quantities in the industrial processes for measurement and control of temperature, humidity, and light intensity. Normally, a transducer which can convert one form of energy into another is used to sense and deliver the required information in the form of an electrical quantity such as voltage, current or resistance. The signal is sent to the preamplifier stage for initial amplification and, after further amplification and processing, may be passed to the output stages such as meters, oscilloscopes, charts, memories and magnetic recorders. The major function of an instrumentation amplifier is precise amplification of low level output signal of the transducer, and the instrumentation amplifier is widely used in applications where low noise, low thermal and time drifts, high input impedance and accurate closed-loop gains are required. There are many commercially available instrumentation amplifier ICs, such as AD521, AD524 and AD624 manufactured by Analog Devices, and mA725, TCL7605 and LH0036. The requirements for instrumentation amplifiers are more rigid than that of general purpose amplifiers. The important features required for an instrumentation amplifier are: (i) high gain accuracy (ii) high CMRR (iii) high gain stability with low temperature coefficient (iv) low dc offset (v) low output impedance

Linear and Non-Linear Applications of Op-Amps

109

Consider a basic difference amplifier shown in Fig. 3.27. The output voltage Vo is given by Vo = -

R2 V2 + R1

Ê R ˆ 1 1 + 2 ˜ V1 Á R1 ¯ ÊR ˆË 1+ Á 3˜ Ë R4 ¯

˘ È Í ˙ Ê R R ˆ 1 Therefore, Vo = - 2 ÍV2 1 + 1 ˜ V1 ˙ Á Í R1 R2 ¯ ˙ ÊR ˆË 1+ Á 3˜ Í ˙ Ë R4 ¯ ÍÎ ˙˚ R1 R3 R2 If = , then Vo = (V1 - V2 ), i.e. the output voltage R2 R4 R1

Fig. 3.27

Differential amplifier using single op-amp

R2 . R1 The differential amplifier discussed above has its input impedance value limited by the value of resistor

Vo is the difference of the two input voltages with the gain of

R1. The gain of the differential amplifier is decided by the factor R2/R1, which restricts high gain values. This limitation is overcome by the use of a voltage follower between each signal input terminal and the difference amplifier. This has a disadvantage that the gain of the amplifier cannot easily be changed. Hence, a circuit with the possibility of gain adjustment by the use of a single resistor is preferable for instrumentation applications involving very low voltages of the order of microvolts and common-mode signals existing between the two input terminals. The instrumentation amplifier shown in Fig. 3.28 offers high input impedance and a high gain.

Fig. 3.28

Instrumentation amplifier

The op-amps A1 and A2 as shown in Fig. 3.28 are voltage follower or buffer circuits acting as the input stage for each of the inputs V1 and V2. They have zero differential input voltage, i.e. Vid = 0. Under such conditions, with common mode signal = 0 and V1 = V2, the voltage across the resistor R is zero. The voltages at the inverting terminals of the buffers are equal to the input voltages. Since no current flows through the resistors R and R¢, the output voltages are V 2¢ = V2 and V 1¢ = V1 respectively. However, if V1 > V2, then a current flows through

(

)

the resistors R and R¢, and V2¢ - V1¢ > (V2 - V1 ) . Therefore, this circuit will have more differential gain and CMRR compared to the single op-amp circuit shown in Fig. 3.28.

110

Linear IC Applications

The current flowing through the resistor R is I =

(V1 - V2 )

and the same current I will flow through the R R V¢ resistors R¢ in the direction shown. The voltage at the non-inverting terminal of op-amp A3 is 2 1 . R 1 + R2 By using superposition theorem, we get Vo = -

Ê R2 R ˆÊ R V¢ ˆ V2¢ + Á1 + 2 ˜ Á 2 1 ˜ R1 R1 ¯ Ë R1 + R2 ¯ Ë

Simplifying, we get Vo =

R2 (V1¢- V2¢) R1

(3.40)

Since there is no current entering the op-amp, the current I = V1¢ = R ¢I + V1 = and

(V1 - V2 ) , which flows through the resistor R¢. R

R¢ (V1 - V2 ) + V1 R

V2¢ = - R ¢ I + V2 = -

R¢ (V1 - V2 ) + V2 R

Substituting the values of V¢1 and V¢2 in Eq. (3.40), Vo is given by Vo =

That is, Vo =

R2 È 2 R ¢ ˘ (V1 - V2 ) + (V1 - V2 ) ˙ R1 ÍÎ R ˚ R2 R1

È 2R ¢ ˘ Í1 + R ˙ (V1 - V2 ) Î ˚

By using a variable resistor R, the gain of this instrumentation amplifier can be varied. When V1 = V2 = Vcm , V1¢ = V2¢ = Vcm, where Vcm is the common mode signal. The input stage thus passes the common mode signals with unity gain. On the other hand, when the input stage uses individually connected voltage follower circuits, they would allow both the common mode and the differential mode signals with the same gain. Therefore, the advantage of the coupled differential input stage is that it amplifies only the differential input signals with some voltage gain. The circuit, thus theoretically possesses an infinite CMRR, with the possibility of gain setting by the resistor R. Also, the circuit is not affected by resistor tolerance value of R. However, in practice, CMRR is not infinite due to the fact that the two op-amps inadvertently incur differences in internal common-mode errors. Use of dual op-amps in those cases is an ideal way to alleviate such errors. Figure 3.29 shows a differential instrumentation amplifier using transducer bridge. In a resistive transducer, the resistance of the transducer changes as a function of the physical quantity under measurement, which is connected as one arm of the bridge, with a small circle shown around as in Fig. 3.29. Due to the change in temperature, the effective resistance of the transducer changes and it is indicated by ( RT ± DR) , where RT is the resistance of the transducer and DR is the change in resistance RT.

Linear and Non-Linear Applications of Op-Amps

111

3.28

Fig. 3.29

Instrumentation amplifier using transducer bridge

The operation of the instrumentation amplifier using the transducer is explained as follows. The bridge is initially balanced with the use of a dc supply voltage Vdc, so that V1 = V2. That is,

RB (Vdc )

=

RB + RA

RC (Vdc ) RC + RT

Therefore,

RA RT = RB RC

or

ÊR ˆ RT = Á A ˜ RC Ë RB ¯

If the ratio of RA to RB, which is called the ratio arms of the bridge is assumed as constant k, then the value of the transducer resistance RT = kRC. As the physical quantity changes, the resistance value RT of the transducer changes, and this causes an imbalance in the bridge. That is, the output of the bridge V1 π V2. The three op-amp instrumentation amplifier shown in Fig. 3.29 amplifies this differential voltage. Let DR be the change in resistance of the transducer. As the resistors RB and RC are fixed resistors, the voltage V1 is constant. However, the voltage V2 varies as a function of the change in transducer resistance. Therefore, V2 =

V1 =

RC (Vdc ) RC + ( RT + DR) RB (Vdc ) RA + RB

Consequently, the voltage V12 across the output terminal of the bridge is V12 = V2 – V1. Therefore, V12 =

RC (Vdc ) RC + RT + DR

-

RB (Vdc ) RC + RB

If RA = RB = RC = RT = R, then the above equation becomes V12 = -

DR (Vdc ) 2(2 R + DR)

112

Linear IC Applications

The gain of the basic differential amplifier is –

R2 . Therefore, the output voltage Vo is R1

ÊR ˆ DR(Vdc ) R2 Vo = V12 Á 2 ˜ = Ë R1 ¯ 2 ( 2 R + DR ) R1 Since the change in resistance of a transducer is normally very small, (2 R + DR) @ 2 R. Hence, the output voltage Vo becomes Ê R ˆ DR(Vdc ) Vo = Á 2 ˜ Ë R1 ¯ 4 R Therefore, the output voltage is a function of the change in resistance of the transducer element, multiplied by the gain value of the op-amp A3 and it is also determined by the resistor R. Example 3.12

For the circuit shown in Fig. 3.30, show that the input resistance Ri =

Fig. 3.30

Solution

For op-amp A1, voltage at node a is zero. The current entering node a is given by Vi - 0 Vi ¢- 0 = R1 R2 For op-amp A2, with input V¢i at node b, the current entering node c is given by Vo - 0 Vi ¢- 0 = 2 R1 R2 Vi ¢ Vo Or, = R2 2 R1 Vi Vo = Therefore, or Vo = 2Vi R1 2 R1 The current Ii from source Vi is given by the sum of currents through R3 and R1. V -V V -0 Therefore, I i = i o + i R3 R1 Substituting Vo = 2Vi in the above equation, we get Ii =

Vi - 2Vi Vi -Vi R1 + Vi R3 Vi ( R3 - R1 ) + = = R3 R1 R1R3 R1R3

Hence, the input impedance of the circuit Ri =

Vi RR = 1 3 I i R3 - R1

Vi RR = 1 3 . I i R3 - R1

Linear and Non-Linear Applications of Op-Amps

113

Ac AmpLIfIer

3.8

The op-amps are fundamentally high-gain dc amplifiers. However, they can often be used for ac amplification also. This section highlights the inverting and non-inverting ac amplifier applications of the op-amp. The inverting and non-inverting amplifiers using op-amps can respond to both dc and ac signals. If a dc voltage is superimposed on an ac input signal, then it is necessary to block the dc component to obtain the ac frequency response of an op-amp. This can be achieved by using an ac amplifier with a coupling capacitor. These ac amplifiers can be realised in two configurations, namely, (i) inverting ac amplifier and (ii) non-inverting ac amplifier.

3.8.1

Inverting ac Amplifier

The inverting ac amplifier is shown in Fig. 3.31(a). The capacitor C connected in series with the resistor R1 blocks the dc component of the input. It sets the lower 3 dB frequency of the amplifier. To analyse the circuit in frequency domain: The node a is at virtual ground, and thus, the output voltage vo is given by vi vo = - iR f = Rf R1 + 1/sC

Fig. 3.31

(a) Inverting ac amplifier

Therefore, ACL =

Rf vo s =R1 s + 1/R1C vi

(3.41)

From the above equation, we get the lower 3 dB frequency as fL =

1 2p R1C

(3.42)

At higher frequencies, the capacitor C behaves like a short circuit and hence Eq. (3.41) becomes ACL = -

Rf R1

Peaking Amplifier The unit gain bandwidth (UGB) of the op-amp represents its operational bandwidth of the op-amp when the voltage gain is 1. It is also called closed-loop bandwidth and small-signal bandwidth. While the op-amp 741 has approximately 1 MHz of UGB, the newer op-amps such as LF351 and MC34001 have a gain-bandwidth product of 4 MHz. When an application requires amplification of signals of a particular frequency, the peak amplifier circuit shown in Fig. 3.31(b) with its frequency response shown in Fig. 3.31(c) can be employed. Here, the frequency under consideration must be less than the UGB of the op-amp.

114

Linear IC Applications

Fig. 3.31

3.8.2

(b) peaking amplifier and (c) its frequency response

Non-inverting ac Amplifier

The non-inverting ac amplifier is shown in Fig. 3.32(a). Here, a resistor R2 is included to provide a dc return to ground, which reduces the overall input impedance of the amplifier that is approximately equal to R2. A high input impedance for the non-inverting ac amplifier may be obtained by using the circuit shown in Fig. 3.32(b).

Fig. 3.32

Non-inverting ac amplifier: (a) With low input impedance (b) With high input impedance

3.8.3 The ac Voltage Follower The circuit of an ac voltage follower is shown in Fig. 3.33, which is used as a buffer to connect a high impedance input signal to a low impedance load. The capacitors C1 and C2 of larger values are selected so that they behave like a short circuit at any frequency. The resistors R1 and R2 provide a path for the flow of dc input current to the non-inverting terminal. The capacitor C2 acts as a bootstrapping capacitor which is connected to resistor R1 for ac operation. From Miller’s theorem, the input resistance is given by R1 Ri = 1- ACL

Fig. 3.33

aC voltage follower

Since the gain ACL of the voltage follower is close to unity, the input impedance is very high.

Linear and Non-Linear Applications of Op-Amps

VoLtAge

3.9

to

115

current conVerter (trAnsconductAnce AmpLIfIer)

An ideal voltage-controlled current source (VCCS) is the one that supplies (i) a current Io that equals a fixed constant k times the value of an independent controlling voltage Vi, or in other words, Io = kVi and (ii) a current which is independent of the load that it drives. The voltage to current converter accepts an input voltage Vi and gives an output current IL. For converting an input voltage to a proportional output current, there are two converting circuits, namely (i) voltage to current with floating load and (ii) voltage to current with grounded load. The voltage to current converter with floating load is shown in Fig. 3.34(a). The voltage at node a is Vi. Therefore, as Fig. 3.34 (a) Voltage to current converter with floating load I B = 0, Vi = I L R1 , i.e. I L = Vi / R1 , and the input voltage is converted into an output current IL. Since the same current flows through the signal source and load, the signal source provides this load current. The voltage to current converter with grounded load is shown in Fig. 3.34(b). Here, the voltage at node a is Va. Applying Kirchhoff’s Current Law at node a, and assuming R = R1 = Rf, we get I1 + I 2 = I L (Vi - Va ) (Vo - Va ) + = IL R R Vi + Vo - 2 Va = I L R (Vi + Vo - I L R) 2 R The gain of this non-inverting op-amp circuit is 1 + = 2. R Va =

Therefore, Vo = 2Va = Vi + Vo - I L R Vi = I L R Vi (3.43) R Hence, the load current is determined by the ratio of Vi and R. This circuit can also be called voltage to current transducer, since I 1 Transconductance ( g m ) = L = Vi R IL =

Therefore, the transconductance of the circuit is determined by the feedback resistor Rf = R. The circuits shown in Fig. 3.34(a) and (b) are also called voltagecontrolled current source (VCCS), since the load current is given by V (3.44) I L = i = Vi g m R

Fig. 3.34

(b) Voltage to current converter with grounded load

116

Linear IC Applications

where gm is the transconductance in Siemens. The load resistance RL does not appear in Eq. (3.44), and hence the load current IL is independent of the load resistance RL. The direction of the current through the load is controlled by the polarity of Vi. Figure 3.34(a) shows the floating load, that is so called, because neither terminal of RL is grounded. This circuit is preferred in applications, where the load cannot have the same ground reference as the input controlling voltage Vi. As the input impedance of this circuit is very high, it draws negligible current from the source. This converter is used in low voltage voltmeter, LED and Zener testers. Caution is to be exercised in the selection of Rf and RL due to the following reasons: (i) When Rf and RL are very small, the op-amp output current may be too high and the op-amp may be pushed into saturation. (ii) When Rf and RL are made very large, the output voltage may exceed the power supply voltage since the product of the values of two resistors and IL make the output voltage. Example 3.13 Assume that Rf = 10 kW, RL = 2 kW and Vi = 0.5 V for the circuit shown in Fig. 3.34(a). Determine the load current. Solution

Vi 0.5 = = 50 m A R f 10 ¥ 103 The op-amp will not be overloaded with the output current of 50 mA, since any commonly available op-amp such as 741 can produce an output current of 20 mA. To verify if the output voltage clipping would occur, The load current is I L =

(

)

(

)

Vmax = R f + RL I L = 10 ¥ 103 + 2 ¥ 103 ¥ 50 ¥ 10-6 = 0.6 V. The voltage level of 0.6 V is well below the clipping or saturation level of the op-amp. Example 3.14 Given a voltage-to-current converter as shown in Fig. 3.35, find the transconductance gm, of the circuit and calculate the maximum load current IL that could be drawn. Check whether overload can happen and calculate the output voltage Vo. Solution

From Fig. 3.35, I L = I R1 However,

I R1 =

Vi R1

Therefore,

IL =

Vi R1

i.e.,

IL 1 = Vi R1

Transconductance is given by gm =

IL 1 = Vi R1

Fig. 3.35

Linear and Non-Linear Applications of Op-Amps

Therefore, g m =

1 20 ¥ 103

117

= 50 m 6

Load current I L = g m  Vi = 50  10  0.5 = 25 m A Since the op-amp can operate with a current (max) of 25 mA, it will not be overloaded. Then, the output voltage Vo = ( RL + R1 ) I L = ( 20 + 10) ¥ 103 ¥ 25 ¥ 10- 6 = 0.75 V. This shows that the output voltage also is well below the saturation level of the op-amp.

3.10

current to VoLtAge conVerter (current-controLLed VoLtAge sources)

A current to voltage converter or an ideal currentcontrolled voltage source (CCVS), also called transresistance amplifier is the one, whose (i) output voltage is equal to a constant k times the magnitude of an independent input current Ii or in other words, Vo = kIi and (ii) output voltage is independent of the load connected to it. The constant k has the unit of ohms. These CCVS or current to voltage converters are required, since it is generally easier to measure voltages. For example, an output current proportional to an incident light energy is obtained from photo-devices such as a photocell and photo diode. This output current from the photo-devices can be converted to voltage by using this current to voltage converter shown in Fig. 3.36. Due to the virtual ground, Vb = Va = 0, the current through R1 is zero and Ii flows through the feedback resistor Rf . Thus, Va = - I i R f . In order to reduce the high frequency and possible oscillations, a capacitor C f is connected across Rf. Figure 3.37 shows a non-inverting current to voltage converter circuit. The input current Ii has a return path to ground. The voltage at the noninverting input is given by Vi = Ii Ri. Therefore, the voltage Vo at the output is given by Rf ˆ Rf ˆ Ê Ê Vi = Á1 + Vo = Á1 + I i Ri ˜ R1 ¯ R1 ˜¯ Ë Ë

Fig. 3.36

Fig. 3.37

Inverting current to voltage converter

Non-inverting current to voltage converter

(3.45)

118

Linear IC Applications

Example 3.15

For the circuit shown in Fig. 3.38(a), find output voltage Vo .

Solution

Va a b a

Vb

b

Fig. 3.38(a)

Fig. 3.38(b)

Assuming an ideal op-amp, the input current at the inverting input terminal is zero. From Fig. 3.38(b), we observe the following: V - Va V I1 = in = in R1 R1

4.46(a)

With no input current at the inverting terminal of op-amp, I1 =

Va - V1 V =- 1 R2 R2

V1 Vin Therefore, we have R = - R 2 1 R 2 Or, V1 = -Vin• R1 Also, we find from Fig. 3.38(b), Therefore, I2 =

3.46(b) V1 = -I2 R4

R V1 = -Vin 2 R1 R4 R4

3.46(c)

In order to find the output voltage Vo, we have from Fig. 3.38(b), (V1 - Vo) = (I1 - I2) R3

(3.47)

Substituting Equations 3.46(a) to 3.46 (c) in Equation 3.47, −Vin

 R2 R  1 − Vo =  Vin − Vin 2  R3 R1 R1 R1R4  

Simplifying Equation 3.48, Output voltage Vo =

Vin (R R + R2 R3 + R2 R4) R1 R4 4 3

(3.48)

Linear and Non-Linear Applications of Op-Amps

3.11

119

VoLtAge foLLower

If R1 = • and Rf = 0 in the non-inverting amplifier configuration, then the amplifier acts as a unity-gain amplifier or voltage follower as shown in Fig. 3.39. That is, Rf Av = 1 + R1 Rf Since = 0, we have Av = 1. R1

Fig. 3.39

Voltage follower

The circuit consists of an op-amp and a wire connecting the output voltage to the input, i.e. the output voltage is equal to the input voltage, both in magnitude and phase. In other words, Vo = Vi. Since the output voltage of this circuit follows the input voltage, the circuit is called voltage follower. It is also referred as a source follower, buffer amplifier, isolation amplifier or unity gain amplifier in practice. It offers very high input impedance of the order of MW and very low output impedance. Therefore, this circuit draws negligible current from the source. Thus, the voltage follower can be used as a buffer between a high impedance source and a low impedance load for impedance matching applications.

Example 3.16

Determine the output current IL for the circuit shown

in Fig. 3.40. Solution

The op-amp acts as a voltage follower with +5 V at the emitter of the transistor with VEE = +12 V. When the transistor is ON, the current through 1 kW resistor is

12 - 5 1 ¥ 103

= 7 mA.

Neglecting the base current, the current through RL is thus IL = 7 mA. Fig. 3.40

Example 3.17

Determine the current I in the circuit shown in Fig. 3.41.

Solution

The op-amp with 5 V at the non-inverting input drops 5 V across the 1 kW 5V resistance with a resulting current of = 5 mA. 1 kW Hence, the current I through R is 5 mA, since no current enters the inverting input terminal of op-amp. Fig. 3.41

120

Linear IC Applications

Example 3.18 Determine the current through RL in the circuit shown in Fig. 3.42. Solution

With 5 V at non-inverting terminal of op-amp A1, the voltage at E1 across 1 kW resistor is 5 V. Assuming negligible VCE drop across Q1, the voltage available at C1 is 5 V, which makes the voltage at E2 node also to be 5 V. Here, op-amps A1 and A2 act as voltage followers. Hence, the current through 1 kW resistor connected at E2 is VCC - VE 2 15 - 5 = = 10 mA RE 2 1 ¥ 103

Fig. 3.42

Assuming that the base current is negligible, the current through RL is 10 mA.

3.12

op-Amp compArAtors

An op-amp comparator compares an input voltage signal with a known voltage, called the reference voltage. In its simplest form, the comparator consists of an op-amp operated in open-loop, and when fed with two analog inputs, it produces one of the two saturation voltages ± Vsat (ª + VCC or - VEE ) at the output of the op-amp. The input-output transfer characteristics of an ideal comparator and a practical comparator using op amp are shown in Fig. 3.43(a) and 3.43(b) respectively. It can be seen from Fig. 3.43(b) that the output state of a practical comparator can change with an input increment of only 2 mV. This width of 2 mV is the region of uncertainty of a practical comparator. Two types of comparators, viz. (i) non-inverting comparator and (ii) inverting comparator can be constructed using op-amps.

Fig. 3.43

transfer characteristics of (a) ideal comparator, and (b) practical comparator

Linear and Non-Linear Applications of Op-Amps

121

Figure 3.44(a) shows an op-amp configured for use as a non-inverting comparator. A fixed reference voltage Vref is applied to (–) input and a time-varying signal vi is applied to (+) input. When the non-inverting input vi is less than the reference voltage Vref, i.e. vi < Vref, the output voltage vo is at -Vsat @ - VEE . On the other hand, when vi is greater than Vref , i.e. vi > Vref, the output voltage vo is at + V @ + V . Thus, sat CC Fig. 3.44 (a) Non-inverting comparator the output vo changes from one saturation level to another depending on the voltage difference between vi and Vref. Figures 3.44(b) and (c) show the input and output waveforms of the comparator when Vref is positive and negative respectively. The diodes D1 and D2 are connected to protect the op-amp from excessive input voltages of Vref as shown in Fig. 3.44(a). In practical circuits, Vref can be obtained by the use of a 10 kW potentiometer forming a voltage divider with the use of supply voltages +VCC and –VEE , and the wiper connected to (–) input terminal of op-amp as shown in Fig. 3.44(d).

Fig. 3.44

(b) Input and output waveforms when Vref is +ve (c) Input and output waveforms, when Vref is –ve

122

Linear IC Applications

Fig. 3.44

(d) Comparator with variable Vref and (e) Comparator with Zener diode at the output

Output voltage level other than ±Vsat at the output can be obtained by using a resistor R and back-to-back Zener diodes connected at the output of op-amp as shown in Fig. 3.44(e). Then, the limiting values of voltage vo becomes (VZ1 + VD) and –(VZ2 + VD), where VD ª 0.7V, and VZ1 and VZ2 are the Zener voltages. Figure 3.45(a) shows a practical inverting comparator with the reference voltage Vref applied to (+) input and the voltage signal vi applied to the (–) input. For a sinusoidal input signal vi and for positive and negative Vref, the input and output waveforms are as shown in Fig. 3.45(b) and (c) respectively. Fig. 3.45 vi

vi

Vp

Vp +Vref 0

t

–Vp

0 –Vref

t

–Vp

vo

vo

+Vout

+Vout t

0 –Vout

t

0 –Vout

vi < Vref (b)

Fig. 3.45

(a) Inverting comparator

vi > –Vref (c)

(b) Input and output Waveforms, when Vref is +ve (c) Input and output Waveforms, when Vref is -ve

Linear and Non-Linear Applications of Op-Amps

123

Example 3.19 Draw the transfer characteristics of the comparator circuit shown in Fig. 3.46(a), when (a) op-amp is ideal and (b) open-loop gain of op-amp is 100000. Assume VZ1 = VZ2 = 5.5 V. Solution

(a) Since the op-amp is ideal, the open-loop gain AOL = •. Therefore, a very small positive or negative voltage at the input results in ±Vsat at the output. This causes VZ1 or VZ2 to breakdown, driving the output vo to ±(VZ + VD) = ±(5.5 V + 0.7 V) = ±6.2 V. The curve shown in Fig. 3.46(b) shows the transfer characteristics of the ideal op-amp.

Fig. 3.46

(a) Circuit of comparator (b) transfer characteristics for ideal op-amp, (c) transfer characteristics for op-amp with open loop gain = 100000

(b) Given, AOL = 1,00,000 v 6.2 Therefore, Dvi = o = = 0.062 mV AOL 100000 That is, the Zener diodes break down at ±0.062 mV. The transfer characteristic of such an arrangement is shown in Fig. 3.46(c).

Applications of Comparator The important applications of a comparator are: (i) (ii) (iii) (iv) (v) (vi)

Zero crossing detector (sine wave to square wave converter) Amplitude distribution analyser Pulse-time modulator Window detector Timing marker signal generator Phase detector

The circuit arrangement and operation of these systems are discussed briefly in the following sections.

3.12.1

Zero Crossing Detector (Sine Wave to Square Wave Converter)

The comparator connected as a zero crossing detector is shown in Fig. 3.47(a). The reference voltage input Vref is set to zero and the sinusoidal input vi is applied to (–) input. The output waveform vo switches between positive and negative saturation levels as shown in Fig. 3.47(b), when the input signal vi passes through zero in the negative and the positive directions respectively.

124

Linear IC Applications

Fig. 3.47

(a) Zero crossing detector (b) Input and output waveforms

In some applications, the input vi may be a slowly varying signal, consuming more time to cross 0 V. Thus, the switching of vo between saturation voltages may take longer time. Conversely, due to noise at the input terminals of op-amp, output vo may unnecessarily switch between the saturation voltages +Vsat and –Vsat. Both these problems are overcome with the use of regenerative or positive feedback introduced in the circuit of a Schmitt trigger.

3.12.2 Amplitude Distribution Analyser The comparator can be used to analyse the amplitude distribution of the noise that is developed in an active device. Figure 3.47(a) can be employed for amplitude distribution analysis with the positive and negative saturation output voltage levels set for +12 V and 0 V. The voltage spectrum of the noise pulses can be produced by connecting the reference voltage Vref with a set value and the noise signal is connected as input vi to the inverting input of the comparator. When vi > Vref, the output reaches the negative saturation of 0 V and when vi < Vref, the output reaches the positive saturation of +12 V. A dc meter can be used to measure the average value of the output square voltage. For any other reference voltage Vref , the dc meter reading indicates the probability that the amplitude of the noise is greater than Vref . In this manner, the cumulative amplitude probability distribution of the noise can be obtained by recording the meter readings against the Vref voltage levels.

3.12.3

Pulse-time Modulator

A pulse-time modulator for a communication system can be constructed by connecting the modulating pulse signal as Vref and a periodic sweep waveform applied to the other input as vi in Fig. 3.47(a). The relative spacing between the successive output pulses indicates the input information.

3.12.4 Window Detector The window detector, also called a window comparator identifies an unknown input voltage falling within two threshold voltage levels. The span of threshold voltage difference is called the window. Figure 3.48(a) shows a set of voltage comparators connected to form a window detector. The threshold voltage levels are

Linear and Non-Linear Applications of Op-Amps

125

VTH and VTL for the upper limit and lower limit of the window respectively. Referring to Fig. 3.48(a), when VTL < vi < VTH, both the transistors Q1 and Q2 are OFF, and the pull-up resistor RC pulls the output high, thus producing a high output voltage. When the voltage vi falls outside the range, that is when vi > VTH, Q1 is ON and if vi < VTL, Q2 is ON. Either of these conditions makes the output zero. If the resistor RC is replaced by an LED in series with current limiting resistors, the LED will glow when the input voltage vi falls outside the windows. Figure 3.48(b) shows the voltage transfer characterFig. 3.48 (a) Window detector (b) Its voltage transfer istics of the window detector circuit. characteristics A three level detector/comparator with LED indicators is shown in Fig. 3.49. The three LEDs are connected to the output of comparators in series with appropriate current limiting resistors. The LEDs will glow when the input vi falls within the respective windows. Alternately, placing an inverter between the comparator and LED-resistor combination makes the LEDs glow when vi falls outside the corresponding windows. Table 3.1 shows the status of LEDs for different input voltage ranges with 6 V connected as +VCC . Table 3.1

Three level comparator

Input (Volts) Less than 2 V Less than 4 V and more than 2 V More than 4 V

LED3 ON OFF OFF

LED2 OFF ON OFF

LED1 OFF OFF ON

The window detectors find applications in production line testing for sorting-out circuits, raising industrial alarms and level detectors. They are available as individual IC modules, such as 4115/04 of Burr-Brown and LTC1040 of Linear technology.

Fig. 3.49

three level comparator

3.12.5 Timing Marker Signal Generator A timing marker signal generator using a sine wave is shown in Fig. 3.50(a). The input signal vi and the output signal of the zero crossing detector are shown in Fig. 3.50(b) and (c). The output vo of the zero crossing detector circuit is applied to the differentiator formed by an RC circuit. The differentiated signal v¢o is shown in Fig. 3.50(d). The value of RC is made much less than the time period T of the input signal vi. This helps in generating steep pulse spikes which can act as time markers. The diode DC clips off the negative portion of the waveform. The time marking signal output vL is shown in Fig. 3.50(e). The frequency of the sinusoidal signal vi determines the pulse spacing interval T and the frequency of time marking.

126

Linear IC Applications

Fig. 3.50

(a) time marker signal generator circuit (b) Input waveform (c) Output vo of op-amp (d) Differentiated output v o¢ (e) pulses across R, vL

The time marker signal is used as trigger signals for monoshot multivibrator, SCR circuit and sweep voltage generator of CRT.

3.12.6

Phase Detector

The phase angle between two time varying voltages can be measured using the circuit of Fig. 3.50(a). The two voltages are converted into spikes using the time marker circuit shown in Fig. 3.50(e). The time interval between the pulse spikes is measured, and it is an indication of the phase difference between the two signals. The phase angle difference from 0° to 360° can be detected using such a circuit.

3.13

muLtIVIbrAtors

Multivibrators are regenerative circuits, which are mainly used in timing applications. Based on their operational characteristics, they can be classified into three categories, namely, (i) Astable multivibrator (ii) Monostable multivibrator (iii) Bistable multivibrator The astable multivibrator toggles between one state and the other without the influence of any other external control signal. It is also called a free-running multivibrator. The monostable multivibrator or one-shot requires an external signal called a trigger to force the circuit into a quasi-stable state for a particular time duration or delay. A suitable timing network determines the time delay and it returns to the stable state at the end of the delay time.

3.13.1 Astable (Free-running) Multivibrator An astable multivibrator is a square-wave generator. Figure 3.51(a) shows the circuit of an astable multivibrator with the output of op-amp fedback to the (+) input terminal. The resistors R1 and R2 form a voltage divider R2 of the output is fed back to the input. The output can take values of network, and a fraction b = R1 + R2 +bVsat or –bVsat. The voltage ± bVsat acts as Vref at the (+) input terminal. The output is also connected to the (–) input terminal through an integrating low-pass RC network. When the voltage vc across capacitor C just exceeds Vref , switching takes place resulting in a square-wave output.

Linear and Non-Linear Applications of Op-Amps

127

To understand the operation of the circuit, let us consider that initially the output is at +Vsat as shown in Fig. 3.51(b). The capacitor C with its voltage shown as vc starts charging through resistor R towards +Vsat. The voltage at (+) input terminal is held at +bVsat as indicated by the use of R1 – R2 potential divider network. The charging of C continues until the voltage vc at the (–) input terminal is just greater than the voltage at the (+) input terminal, +b Vsat. When this happens as shown at point b of Fig. 3.51(b), the output is switched down to –Vsat. The voltage +bvo across the capacitor now starts discharging through resistance R and charging towards –Vsat. The capacitor voltage vc now becomes increasingly more and more negative and at point c just exceeds –b Vsat. The output now switches back to +Vsat, and the cycle repeats. Summarising, (i) when vo = +Vsat, C charges from –bVsat to +bVsat and switches vo to –Vsat (ii) when vo = –Vsat, C charges from +bVsat to –bVsat and switches vo to +Vsat.

Period and Frequency of Oscillation The frequency of the free running multivibrator is determined by the charging and discharging time of the capacitor between the voltage levels –bVsat and +bVsat and vice versa. The voltage across the capacitor as a function of time can be represented as

(

)

-t

vc(t) = V + V - V e RC f in ini f in where V fin is the final value of the voltage and Vini is the initial voltage.

128

Linear IC Applications

Fig. 3.51

Square-wave generator using op-amp: (a) Circuit diagram (b) Waveforms at output and capacitor terminals (c) Use of Zener diodes for different peak-to-peak voltages (d) asymmetric square-wave generator

Considering the charging of the capacitor from point a towards +Vsat, -t

vc(t) = +V sat + (- b Vsat - Vsat ) e RC -t

= Vsat - Vsat (1 + b ) e RC

(3.49)

At t = T1, the voltage across the capacitor reaches +bVsat and switches at point b. -T1 ˆ Ê Therefore, bVsat = Vsat Á1 - (1 + b ) e RC ˜ Ë ¯ -T1

That is,

(1 – b) = (1 + b ) e RC

1+ b = RC ln R1 + 2R2 1- b R1 As shown in Fig. 3.51(b), the total time period is given by

and

T1 = RC ln

T = 2T1 = 2RC ln

1+ b 1- b

(3.50)

That is, T = 2 RC ln Ê R1 + 2R2 ˆ ÁË R ˜¯ 1 and the output is a symmetrical waveform. Hence, the frequency of oscillation is fo = Considering R1 = R2, we have b=

R = 0.5, T = 2RC ln 3 2R

(3.51)

1 = T

1 Ê1 + b ˆ 2 RC ln Á Ë 1 - b ˜¯

(3.52)

Linear and Non-Linear Applications of Op-Amps

fo =

1 1 = 2 RC ln 3 2.2 RC

129

(3.53)

Equation (3.50) shows that the period is directly proportional to the time constant RC. Thus, varying either R or C changes the period correspondingly. Therefore, providing a tunable resistance R paves the way for a continuously tunable square-wave generator. The output peak amplitudes can be varied by the use of Zener diodes connected back to back as shown in Fig. 3.51(c). The output voltage is then regulated to ±(Vz + VD) where Vz is the Zener voltage. Then, the peak-topeak output voltage is given by vo (peak-to-peak) = 2(Vz + VD). To generate an asymmetric square-wave, a variable voltage source V can be introduced as shown in Fig. 3.51(d). For the circuit shown in Fig. 3.51(d), assuming that R1 = 116 kW, R2 = 100 kW, and

Example 3.19

±Vsat = ±14 V, find (i) the time constant to produce 1 kHz output (ii) the resistance R (iii) the maximum value of differential input voltage. Solution

(a) From Eq. (3.51), the time period T = 2 RC ln

R1 + 2R2 R1

Ê 116 ¥ 103 + 2 ¥ 100 ¥ 103 ˆ T = 2 RC ln Á ˜ ¯ Ë 116 ¥ 103 Ê 316 ¥ 103 ˆ = 2 RC ln Á ˜ Ë 116 ¥ 103 ¯

Ê 316 ¥ 103 ˆ = 2 RC since ln Á ˜ ª1 Ë 116 ¥ 103 ¯ 1 1 = = 1 ms f 1 ¥ 103

Given

f = 1 kHz, T =

That is,

2 RC = 1 ¥ 10–3 sec

Therefore, the time constant RC = 0.5 ¥ 10–3 sec (b) With C = 0.01 m F,

R=

0.5 ¥ 10-3 0.01 ¥ 10-6

= 50 kW

(c) Maximum value of differential input voltage is Ê R2 ˆ 100 ¥ 103 = 2 ¥ 14 ¥ 2Vsat Á = 12.96 V. Ë R1 + R2 ˜¯ (100 + 116) ¥ 103 Therefore, the peak values for the differential input voltage just exceed ±2 ¥ 6.48 V. Example 3.20

voltage of ± 12 V.

Design a square wave oscillator for fo = 1 kHz using 741 op-amp and DC supply

130

Linear IC Applications

Solution

Given frequency of oscillation fo = 1 kHz. For designing a square wave oscillator, the op-amp based astable multivibrator, shown in Fig. 3.51(a) may be used with the assumption of R1 = R2 = 10 kW. Referring to Eq. (3.53), we have fo =

1 2.2 RC

Assuming C = 0.1 mF, we get R =

3.13.2

1 1 = = 4.545 kW 2.2 Cfo 2.2 ¥ 0.1 ¥ 10-6 ¥ 1 ¥ 103

Monostable Multivibrator

The circuit diagram of a monostable multivibrator, also called a one-shot multivibrator is shown in Fig. 3.52(a). This has a stable state and a quasi-stable state. Single output pulse of adjustable time duration in response to a triggering signal can be generated using the monostable multivibrator. The time duration for the output pulse is achieved by connecting the required external components to the op-amp.

Fig. 3.52

Monostable multivibrator: (a) Circuit diagram (b) Negative polarity triggering signal, (c) Voltage across the capacitor (d) Output voltage waveform

When the output Vo is at positive saturation, the diode D1 clamps the capacitor (C) voltage to VD(0.7 V). This is the stable state of the circuit. In this state, the inverting terminal b is clamped to ground by diode D1. This results in preventing the inverting input terminal going more positive than VD (0.7 V). This makes terminal a also positive by the same voltage VD. A negative-going narrow trigger pulse is passed through differentiator R3CT and diode D2, and connected to the non-inverting input terminal of op-amp. R3 is made much larger than R1, so that its loading effect may be minimised. The diode D2 prevents positive spikes arriving from the triggering circuit. Let us assume that in the stable state, the output Vo of op-amp is at +Vsat, the voltage at inverting terminal is VD and the voltage at (+) terminal through the potential divider R1 – R2 is +bVsat, where R1 . When a negative trigger signal V T is applied to the (+) terminal through the trigger line, the b= R1 + R2 effective signal is less than 0.7 V. That is, voltage at (+) terminal is [bVsat + (–V T)] < 0.7 V. Then, the op-amp output switches from +Vsat to –V sat. The diode D1 is now reverse-biased and the capacitor C starts

Linear and Non-Linear Applications of Op-Amps

131

charging exponentially to –Vsat through the resistance R in the closed loop. In this condition, the voltage at positive input terminal is –bVsat. While charging exponentially, just as the capacitor voltage vc becomes slightly more than –bVsat, the voltage at (–) terminal becomes more negative than that at (+) terminal. Then, the op-amp output switches back to +Vsat. The capacitor C now starts charging towards +Vsat through the resistance R. This continues only until the voltage at (–) terminal becomes VD (0.7 V) and then it clamps the capacitor C to VD . The waveforms of the negative polarity triggering signal, voltage across the capacitor and output of op-amp are shown in Fig. 3.52 (b), (c) and (d) respectively.

To Determine the Pulse Width T For a low-pass RC circuit, the general solution is v o = Vfin + (Vini – Vfin) e–t /RC where V ini is the initial voltage value and Vfin is the final voltage value. For the circuit explained above, Vfin = –Vsat and Vini = V D (diode forward voltage). The output v c is then given by v c = –Vsat +(VD + V sat)e–t/RC

(3.54)

At the end of time t = T as shown in Fig. 3.51(c), vc = –b Vsat. Thus, –bVsat = –Vsat + (V D + Vsat)e–T/RC Simplifying for the pulse width, we get T = RC ln Ê 1 + VD /Vsat ˆ ÁË 1 - b ˜¯ where b =

R2 R1 + R2

(3.55)

When V sat >> VD (0.7 V ) and R1 = R2 with b = 0.5, T = 0.693 RC (3.56) Understandably, the trigger pulse width should be less than the pulse width T. The monostable multivibrator circuit can generate a fast transition after a calculated time T equal to the pulse width in response to the application of the input trigger pulse. Therefore, it can be used as a time-delay circuit. The rectangular waveform can be used as a gating signal in counters and analog-to-digital converters.

3.14

trIAnguLAr wAVe generAtor

Figure 3.53(a) shows the circuit of a triangular wave generator. It consists of two op-amps and several passive components. The op-amp A1 forms a non-inverting comparator with hysteresis, which is a Schmitt Trigger. The op-amp A2 forms an integrator which integrates the output obtained from the Schmitt trigger. The op-amp A1 is a two level comparator whose outputs are determined by ±Vsat. The square-wave output from A1 is applied to the (–) input terminal of the op-amp A2. The output of A2 is a triangular wave and it is fedback as an input to the comparator A1 through a voltage divider network formed by R2 and R3.

132

Linear IC Applications

Loop Analysis Let us consider that the output v′o of comparator A1 is +Vsat initially. The integrator integrates +Vsat and produces a negative going ramp at its output as shown in Fig. 3.52(b). Hence, the voltages at the two ends of the voltage divider formed by R2 – R3 are +Vsat at the output of A1 and –Vramp at the output of A2. At t = T1, when the negative going ramp reaches a value of –Vramp, represented as point a in Fig. 3.53(b), the effective value at the point P becomes slightly less than 0 V. This switches the op-amp A1 to its negative saturation level –Vsat. Voltage v¢o

+Vsat

b

+Vramp

vo vo

T1

–Vramp

a

–Vsat

T2

t

T/2

(b) Waveform at v ¢o and vo

triangular waveform generator: (a) Circuit diagram (b) Waveforms at v o¢ and vo

Fig. 3.53

With the output of A1 at –V sat, the op-amp A2 starts integrating and increases its output in the positive direction. At t = T2, shown as point b in Fig. 3.53(b), the voltage at P becomes just more than 0 V. This switches the output of op-amp A1 from –Vsat to +Vsat. This cycle repeats itself, and generates a triangular waveform. The frequency of the waveform is determined by the RC value of the integrator formed by op-amp A2 and the saturation voltage levels ±Vsat of comparator op-amp A1.

To Determine the Amplitude and Frequency of the Triangular Waveform When the comparator output is at +Vsat, the effective voltage at the point P is –Vramp +

R2 [+Vsat – (–Vramp)] = 0 R2 + R3

Simplifying, we get -R2 –Vramp = (+Vsat) R3 Similarly, at t = T2 , when the output of A1 switches from –Vsat to +Vsat , Vramp = -R2 (–Vsat) = R2 Vsat R3 R3

(3.57)

Thus, the peak-to-peak amplitude of the triangular wave is vo(pp) = +Vramp – (–Vramp) = 2

R2 Vsat R3

(3.58)

The time taken for the output of A2 to switch from –Vramp to +Vramp is half of the time period, i.e. T/2. From the basic integrator output equation, vo = –

1 R1C1

T/2

Ú 0

(–Vsat)dt =

Vsat Ê T ˆ Á ˜ R1C1 Ë 2 ¯

Linear and Non-Linear Applications of Op-Amps

Then, T = 2

133

R1C1 vo(pp) Vsat

Substituting the value of vo(pp) from Eq. (3.58) in the above equation, we get T=

4 R1C1 R2 R3

(3.59)

Therefore, the frequency of oscillation is R3 fo = 1 = T 4 R1C1 R2

(3.60)

A triangular waveform generator can also be constructed by a simple alternate arrangement of a squarewave generator connected to an integrator as shown in Fig. 3.54(a).

Fig. 3.54

alternate triangular waveform generator circuit: (a) Circuit diagram (b) Waveforms at the output of op-amps

Let us assume that the voltage v¢o is high at +Vsat. This forces a current of +Vsat/R3 through capacitor Cf of the integrator, producing a negative ramp at the output of the integrator. When v¢o is low at voltage –Vsat , the output of integrator ramps up linearly. This cycle repeats itself and hence the frequency of the triangular wave is the same as that of the square-wave. Hence, the value of resistor R connected in the square-wave generator part of the circuit determines the frequency of the triangular wave. The amplitude of the triangular wave decreases with an increase in frequency value. This is due to the fact that the capacitive reactance decreases at high frequencies and increases at low frequencies. The square waveform and triangular waveform of the circuit are shown in Fig. 3.54(b). A stable triangular wave can be obtained by maintaining 5R3C2 > T /2, where T is the period of the squarewave input. A resistance R4 is normally connected across Cf to avoid saturation problems occurring at low frequencies. Example 3.21 Assume that for the circuit shown in Fig. 3.54(a), R1 = 100 kW, R2 = 10 kW, R3 = 20 kW, C1 = 0.01 mF and ±Vsat = ±14 V for the op-amps. Determine the (a) period, (b) frequency, (c) peak value of square-wave and (d) peak value of triangular wave. Solution

(a) From Eq. (3.59),

134

Linear IC Applications

Time period T = = (b) Frequency fo =

4 R1C1 R2 R3 4 (100 ¥ 103) (0.01 ¥ 10-6 ) (10 ¥ 103) 20 ¥ 103

= 2 ms

1 1 = = 500 Hz T 2 ¥ 10-3

(c) The peak value of the op-amp is simply the saturation voltage levels, i.e. +14 V and –14 V. (d) Peak value of the triangular wave from Eq. (3.57) is Vp =

10 ¥ 103 R2 ¥ 14 = 7 V Vsat = 20 ¥ 103 R3

Therefore, the triangular wave oscillates between +7 V and –7 V.

3.15

squAre wAVe generAtor

Please refer to the subsection Astable (Free-running) Multivibrator using op-amp, which is otherwise called as a Square Wave Generator.

3.16

LogArIthmIc AmpLIfIer

The response of the op-amp circuit is determined by the choice of elements used in the feedback network of op-amp. When resistors are used, which have a linear relation between the voltage and current, the resulting circuit shows a linear response for the input. On the other hand, when a logarithmic PN junction obtained from a transistor is used, the circuit results in a log or antilog response. The log and antilog responses can be derived from the popular log/antilog ICs such as 755 and 759 from Analog Devices and IC 4127 from Burr-Brown, which are monolithic devices. These logarithmic amplifiers can also be used in applications where significant rise in the dynamic range of certain signal processing systems are desired. There will be no loss in accuracy and resolution, even when the input signal is very small in comparison with the full dynamic range. A typical situation is when the instrument can display a pulse voltage of 10 mV or 10 V with visible precision on the same scale for both the extremes of voltages.

Basic Log Circuit The logarithmic amplifier, called a log-amp or a logger, is basically a current to voltage converter with the transfer characteristics of Ê If ˆ Vo = Vi ln Á ˜ ËI ¯ i

Linear and Non-Linear Applications of Op-Amps

135

(lf /Ii)

Fig. 3.55

Logarithmic amplifier (a) Fundamental circuit and (b) Its logarithmic characteristics

The transistor Q with its base grounded and its collector at virtual ground is connected in a transdiode configuration as shown in Figs. 3.55(a) and (b). Its voltage-current relationship is thus defined by I E = I S ÈÎe qVBE / kT - 1˘˚ For the transdiode or grounded base transistor configuration, IE = IC and hence, I C = I S ÈÎe qVBE / kT - 1˘˚

(3.61)

where IS is the emitter saturation current and kT/q is the volt-temperature equivalent. From Eq. (3.61), IC I + 1 @ C , since I C >> I S IS IS Applying natural log on both sides and rearranging, we get e qVBE / kT =

VBE =

kT Ê I C ˆ ln q ÁË I S ˜¯

From the Fig. 3.55(a), I1 = Therefore, Vo = -

Vi and VBE = –Vo Ri

kT Ê Vi ˆ kT Ê Vi ˆ ln =ln q ÁË R1 I S ˜¯ q ÁË VR ˜¯

(3.62)

where VR = R1 IS Hence, the output voltage is found to be the logarithmic equivalent of input voltage. The emitter saturation current IS of the transistor widely varies from one transistor to the other. This problem could be eliminated by employing two transistors Q1 and Q2 shown in Fig. 3.56, manufactured under the same process conditions on a single silicon wafer. The input conversion is applied to one log amp and an external reference voltage VR is applied to another. By this arrangement, close matching of VR and good thermal tracking are achieved. That is, IS1 = IS2 = IS

136

Linear IC Applications

Fig. 3.56

Logarithmic amplifier with compensation of emitter saturation current

From Fig. 3.56, the output Vo1 is found as kT Ê Vi ˆ ln q ÁË R1 I S ˜¯

Vol = -

and the output Vo2 is Vo 2 = -

kT Ê VR ˆ ln q ÁË R1 I S ˜¯

The op-amp A3 configured as a subtractor will subtract the two inputs, thus providing at the output, Vo = -

=

kT Ê VR ˆ Ê kT Ê Vi ˆ ˆ ln - ln q ÁË R1 I S ˜¯ ÁË q ÁË R1 I S ˜¯ ˜¯

kT Ê Vi ˆ ln q ÁË VR ˜¯

(3.63)

The VR is thus set with a single external voltage source. Therefore, the dependence of the circuit on the device and temperature has been removed. The op-amp A4 configured as the fourth stage compensates for the effects of temperature with the inclusion of the temperature sensitive resistor RTC with positive temperature coefficient. The overall output voltage VL is thus Ê R ˆ kT Ê Vi ˆ VL = Á1 + 2 ˜ ln RTC ¯ q ÁË VR ˜¯ Ë

(3.64)

Negligible variation in VL is achieved with matched coefficients and resistor values. Figure 3.57 shows a logarithmic amplifier using only two op-amps.

Linear and Non-Linear Applications of Op-Amps

Fig. 3.57

3.17

Logarithmic amplifier using two op-amps

AntILogArIthmIc AmpLIfIer

Basic Antilog Circuit Antilog amplifier is a decoding circuitry to convert the logarithmically encoded signal back to the real world signal levels. A decade change in the input of the logarithmic amplifier causes a one volt change in its output, and conversely, the antilog amplifier creates a decade change in output with respect to a unit change in the input signal. A basic antilog amplifier circuit is shown in Fig. 3.58. The transistor is connected at the inverting input terminal with its base grounded. It is used to convert the input voltage into an input current, with a log function. Due to the virtual ground at the inverting input terminal, the log function of input voltage passes through the feedback resistor Rf. The drop across Rf produces the output voltage.

Fig. 3.58

Basic antilog amplifier circuit

The output voltage is derived as Vo = – Rf Ii . Using Eq. (3.61),

(

Ii = I C = I S e qVBE / kT

)

Fig. 3.59

antilogarithmic amplifier

137

138

Linear IC Applications

(

Vo = - R f I S e qVBE / kT

Therefore,

)

The schematic arrangement for the antilog amplifier is shown in Fig. 3.59. The input for the antilog is fed through the potential divider R2 and RTC, to the base of transistor Q2. The output of op-amp A2 is fed back to R1 at the inverting input of op-amp A1. The non-inverting inputs are connected to ground. From Fig. 3.59,

and

V1BE =

kT Ê VL ˆ ln q ÁË R1 I S ˜¯

(3.65)

V2 BE =

kT Ê VR ˆ ln q ÁË R1 I S ˜¯

(3.66)

Since the base of Q1 is connected to ground, VA = - V1BE = -

kT Ê VL ˆ ln q ÁË R1 I S ˜¯

(3.67)

The base voltage of Q2 is the drop across RTC , and therefore, VB =

RTC R2 + RTC

Vi

(3.68)

The emitter voltage of Q2 is VQ 2 E = VB + V2 BE Substituting Eqs (3.66) and (3.68) in Eq. (3.69), we get VQ 2 E =

RTC kT Ê VR ˆ Vi ln R2 + RTC q ÁË R1 I S ˜¯

From Fig. 3.59, we see that VQ 2 E = VA Therefore, -

RTC kT Ê VL ˆ kT Ê VR ˆ ln Á = Vi ln ˜ q Ë R1 I S ¯ R2 + RTC q ÁË R1 I S ˜¯

Rearranging, we get RTC kT Ê VL ˆ kT Ê VR ˆ Vi = ln + ln R2 + RTC q ÁË R1 I S ˜¯ q ÁË R1 I S ˜¯ =-

kT Ê VL ˆ ln q ÁË VR ˜¯

(3.69)

Linear and Non-Linear Applications of Op-Amps

139

We know that log10 x = 0.4343 ln c . ÊV ˆ Ê q ˆ Ê RTC ˆ V = 0.4343 ln Á L ˜ Therefore, - 0.4343 Á ˜ Á Ë kT ¯ Ë R2 + RTC ˜¯ i Ë VR ¯ That is,

ÊV ˆ Ê q ˆ Ê RTC ˆ - 0.4343 Á ˜ Á V = log10 Á L ˜ Ë kT ¯ Ë R2 + RTC ˜¯ i Ë VR ¯

ÊV ˆ - KVi = log Á L ˜ Ë VR ¯ Ê q ˆ Ê RTC ˆ where K = 0.4343 Á ˜ Á Ë kT ¯ Ë R2 + RTC ˜¯ or

Hence, VL = VR 10- KVi The IC manufacturers provide log/antilog circuits in IC form. A typical device is IC 4127 from Burr-Brown which is a hybrid IC using matched transistors to improve the circuit accuracy.

3.18

precIsIon rectIfIer

The signal processing applications with very low voltage, current and power levels require rectifier circuits. The ordinary diodes cannot rectify voltages below the cut-in voltage of the diode. A circuit which can act as an ideal diode for rectifying voltages, which are below the level of cut-in voltage of the diode can be designed by placing the diode in the feedback loop of an op-amp. Such a rectifier can be called as precision rectifier.

3.18.1

Precision Diodes

Figure 3.60(a) shows the arrangement of a precision diode. It is a single diode arrangement and functions as a non-inverting precision half-wave rectifier circuit. It is called super diode, since it provides a nearly perfect rectifier. If vi in the circuit of Fig. 3.60(b) is positive, the op-amp output VOA also becomes positive. Then the closed loop condition is achieved for the op-amp and the output voltage vo = vi. When vi < 0, the voltage VOA becomes negative and the diode is reverse biased. The loop is then broken and the output vo = 0. Consider the open loop gain AOL of the op-amp is approximately 104 and the cut-in voltage Vg for silicon V diode is ª 0.7 V. When the input voltage vi > g , the output of the op-amp VoA exceeds Vg and the diode AOL V D conducts. Then, the circuit acts like a voltage follower for input voltage level vi > g i.e. when vi > AOL 0.7 = 70m V and the output voltage vo follows the input voltage during the positive half cycle for input 104 V voltages higher than 70 mV as shown in Fig. 3.60(c). When vi is negative or less than g , the output of opAOL

(

)

amp VOA becomes negative and the diode becomes reverse biased. The loop is then broken and the op-amp swings down to negative saturation. However, the output terminal is now isolated from both the input signal and the output of the op-amp and thus vo = 0. No current is then delivered to the load RL except for the small bias current of the op-amp and the reverse saturation current of the diode.

140

Linear IC Applications

Fig. 3.60

(a) precision diode (b) equivalent circuit (c) Input and output waveforms

From the equivalent circuit shown in Fig. 3.60(b), we have vo + 0.7 - A (vi - vo ) = 0 vo + Avo = Avi - 0.7 A 0.7 Therefore, vo = 1 + A vi - 1 + A As A is large, vo ª vi . This circuit is an example of a non-linear circuit, in which linear operation is achieved over the region (vi > 0) and non-linear operation is achieved over the remaining region (vi < 0). Since the output swings to negative saturation level when vi < 0, the circuit is basically of saturating form. Thus, the frequency response is also limited. The precision diodes are used in Half-wave rectifier, Full-wave rectifier, Peak value detector, Clipper and Clamper circuits. It can be observed that the precision diode shown in Fig. 3.60(a) operates in the first quadrant with vi > 0 and vo > 0. The operation in third quadrant can be achieved by connecting the diode in reverse direction.

Linear and Non-Linear Applications of Op-Amps

3.18.2

141

Half-wave Rectifier

A non-saturating half-wave precision rectifier circuit is shown in Fig. 3.61(a). When vi > 0, the voltage at the inverting input becomes positive, forcing the output VOA to go negative. This results in forward biasing the diode D1 and the op-amp output drops only by ª 0.7 V below the inverting input voltage. Diode D2 becomes reverse-biased. The output voltage vo is zero since no current flows in the feedback circuit through Rf. Hence, the output vo is zero when the input is positive. When vi < 0, the op-amp output VOA becomes positive, forward biasing the diode D2 and reverse biasing the diode D1. The circuit then acts like an inverting amplifier circuit with a non-linear diode in the forward path. The gain of the circuit is unity when Rf = Ri.

Fig. 3.61

(a) Non-saturating half-wave precision rectifier circuit (b) Input and output waveforms

The circuit operation can mathematically be expressed as

and

vo = 0 when vi > 0 Rf vo = vi for vi < 0 Ri

The voltage VOA at the op-amp output is

and

VOA ª – 0.7 V for vi > 0 Rf VOA ª vi + 0.7 V for vi < 0. Ri

The input and output waveforms are shown in Fig. 3.61(b). The op-amp shown in the circuit must be a high-speed op-amp. This accommodates the abrupt changes in the value of VoA when vi changes sign and improves the frequency response characteristics of the circuit. The advantages of half-wave rectifier are (i) it is a precision half-wave rectifier and (ii) it is a non-saturating one. The inverting characteristics of the output vo can be circumvented by the use of an additional inversion or sign changer using one op-amp for achieving a positive output.

142

Linear IC Applications

3.18.3

Full-wave Rectifier

The full-wave rectifier circuit commonly called an absolute value circuit is shown in Fig. 3.62(a). The first part of the total circuit is a half-wave rectifier circuit considered earlier in Fig. 3.61(a). The second part of the circuit is an inverting summing circuit.

Fig. 3.62

(a) active non-saturation full-wave rectifier circuit

For positive input voltage vi > 0 V and assuming that Rf = Ri = R, the output voltage Vo¢= –vi. The voltage Vo¢ appears as (–) input to the summing -R op-amp circuit formed by A2. The gain for the input Vo¢ is as shown ( R/2) in Fig. 3.62(a). The input vi also appears as an input to the summing

vi t Vo t

amplifier. Then, the net output is Vo = - vi - 2Vo¢

Fig. 3.62

(b) Input and output waveforms

= - vi - 2 ( - vi ) = vi Since vi > 0 V, Vo will be positive, with its input-output characteristics in first quadrant. For negative input vi < 0 V, the output Vo¢ of the first part of rectifier circuit is zero. Thus, one input to the summing circuit has a value of zero. However, vi is also applied as an input to the summer circuit formed by the op-amp A2. R The gain for this input is ÊÁ - ˆ˜ = - 1, and hence the output is Vo = –vi. Since vi is negative, Vo will be Ë R¯ inverted and will thus be positive. This corresponds to the second half cycle operation of the circuit. To summarise the operation of the circuit, Vo = vi when vi < 0 V Vo = vi for vi > 0 V, and hence, Vo = ˙ vi˙ It can be observed that this circuit is of non-saturating form. The input and output waveforms are shown in Fig. 3.62(b).

Linear and Non-Linear Applications of Op-Amps

143

Review Questions 3.1 For a non-inverting amplifier using op-amp, determine the output voltage and voltage gain. Assume R1 = 2 kW, Rf = 10 kW and B Vi = 5 mV. 3.2 What is a dc voltage follower? How will you B simulate such a device using op-amp? 3.3 Why is the voltage follower called the buffer C amplifier and an isolation amplifier? 3.4 An input of 3 V is fed to the noninverting terminal of an operational amplifier. The amplifier has R1 of 10 kW and Rf of 10 kW. B Find the output voltage. 3.5 What is the effect of saturation during C amplification process using op-amp? 3.6 Draw the circuit of a voltage to current converter if the load is (i) floating and (ii) grounded. Is there any limitation on the size C of the load when grounded? 3.7 Explain with a circuit the working of V to I converter with floating load. Where can it be B used? 3.8 With a circuit diagram explain the working of A a current to voltage converter. 3.9 What is an instrumentation amplifier? Draw a system whose gain is controlled by a variable C resistance? 3.10 What are the desirable characteristics of an B instrumentation amplifier? 3.11 What is the advantage of having a coupled differential input stage in the instrumentation C amplifier? 3.12 What is the ideal CMRR value of the instrumentation amplifier? Justify your C answer. 3.13 Explain the difference between the dc and ac B amplifiers. 3.14 Explain the operation of inverting and nonA inverting amplifiers. 3.15 How can the input impedance of a noninverting ac amplifier be varied? What are C the salient features of the circuit?

3.16 Draw and explain the operations of an ac voltage follower having very high input B resistance. 3.17 What is the basic function of an integrator? A

3.18 Draw the circuit of an ideal integrator and A explain its operation. 3.19 Explain the summing integrator and double integrator. Derive for their output voltages. B

3.20 Explain and draw the output waveforms of the ideal integrator circuit when the input is (i) sine wave, (ii) square-wave and (iii) step B input. 3.21 What are the limitations of an ideal integrator? A

3.22 Explain various errors in an ideal integrator circuit. How are these errors minimised? B 3.23 What practical modifications are needed to be done to the basic integrator and why? C 3.24 How are the initial conditions introduced in C an integrator? 3.25 Explain the practical integrator circuit. B Explain its advantages. 3.26 Derive the frequency response of a practical B integrator. 3.27 Show the response of an integrator for the following inputs: (a) sine wave input and B (b) square wave input. 3.28 For performing differentiation, an integrator is preferred to a differentiator. Reason out. C 3.29 What is the basic function of a differentiator? A

3.30 What are the limitations of an ideal A differentiator? 3.31 Design a differentiator to differentiate an input signal that varies in frequency from B 10 Hz to about 10 kHz. 3.32 What is the function of the capacitors used in C the basic integrator and differentiator?

144

Linear IC Applications

3.33 What is the principle of a differentiator using C op-amp? What are its drawbacks? 3.34 What are the practical modifications needed to be done to the basic differentiator and C why? 3.35 Explain the design procedure of a practical B differentiator. 3.36 Draw the circuit diagram of an op-amp differentiator and derive an expression for B the output in terms of the input. 3.37 Show the response of a differentiator for the following inputs: (a) Sine wave input and B (b) square wave input. 3.38 Derive the output voltage equation for the following: (i) Integrator B (ii) Differentiator 3.39 Design a differentiator using op-amp to differentiate an input signal with fa = 1 kHz. B

3.40 Design a differentiator to produce an output of 6 V when the input changes by 2 V in C 100 ms. 3.41 Explain the difference between integrator and differentiator. List one application of each. A 3.42 Reason out why an integrator can be considered as low pass filter and the C differentiator a high pass filter? 3.43 A signal Vi is applied to the inverting terminal of an op-amp through Zi and to the noninverting terminal through Z2. From inverting terminal to ground is an impedance Z3 and between non-inverting terminal and the output is Z4. Derive the expression for the gain. C 3.44 Assuming R1 = 1 kW, Rf = 10 kW and Cf = 0.1 mF in a practical integrator circuit of Fig. 4.34, determine the lower frequency limit of integration and the output response for a sine-wave input of 0.5 V peak at 5 kHz. C

3.45 Using a differential amplifier, explain how to C multiply two analog voltages. 3.46 What are the uses of log and antilog A amplifiers?

3.47 Explain the principle of a basic logarithmic A amplifier circuit. 3.48 How is the current characteristic of a PN B junction employed in a log amplifier? 3.49 Draw the circuit diagram of a logarithmic amplifier using op-amps and explain its B operation. 3.50 Explain a basic antilogarithmic amplifier B using op-amp. 3.51 Compare the transfer characteristics of an B ideal and a practical comparator? 3.52 List different types of comparator circuits. A 3.53 Design an op-amp based comparator circuit B and explain its operating features. 3.54 List the applications of comparator circuits. A

3.55 An op-amp comparator circuit connected with two Zener diodes of rating VZ1 = VZ2 = 6.3 V is operated by ±15 V power supply. Determine the output voltage levels in saturation conditions assuming (i) an ideal op-amp and (ii) open-loop gain of op-amp is 50000. C

3.56 What is a zero crossing detector? How can it be employed to wave shape a sine wave into B a square wave? 3.57 What is a window detector? Explain its operation in the use of voltage level B indicators. 3.58 Design a phase difference measurement circuit using op-amp based comparator. Show typical output with transients. C 3.59 For the circuit of Fig. 3.46(a), assume vi = 120 mV peak sine-wave of 200 Hz frequency, R = 1 kW and VZ1 = VZ2 = 6.2 V. Assume supply voltages of ±15 V. Draw the transfer characteristics of the circuit for (a) an ideal op-amp and (b) an op-amp with an open-loop gain of 60000. C 3.60 What is a precision diode? Why is it called so? And what is the minimum ac voltage that can be rectified using the circuit? C

Linear and Non-Linear Applications of Op-Amps

3.61 Draw a precision half-wave rectifier circuit B and explain its operation. 3.62 Draw a half-wave rectifier circuit to rectify an ac voltage of 0.2 V. Draw the typical input-output transients. C 3.63 Draw the circuit of a full-wave rectifier circuit and explain its operation with necessary A transients. 3.64 Sketch a precision rectifier peak-to-peak detector circuit. Draw the input and output waveforms and explain the circuit operation. B

3.65 How will you realise a peak detector using a precision rectifier? B

145

3.66 Design a nonsaturating precision half-wave rectifier of Fig. 3.54(a) to produce 4 V peak output using sinewave input of peak amplitude 0.5 V. The frequency of sine wave B signal is 2 MHz. 3.67 An application requires diodes with accurately same forward voltage drops at specific value of output current. Devise a circuit for the same using op-amp and explain. C 3.68 Construct a zener diode tester using op-amp A and explain its operation. 3.69 Construct an LED tester using op-amp and explain its operation. What is the use of the B BJT booster transistor at the output?

Objective-Type Questions 3.1 The ratio between the feedback and input resistors of an inverting scale changer circuit A is called ____________. 3.2 The voltage follower circuit produces 180o phase shift at its output. (True / False) 3.3 The voltage follower circuit act as _________. (a) an amplifier (b) a multiplier (c) an impedance matching circuit A (d) all of these 3.4 The current source of Fig. 3.34(a) can drive the __________ loads. (a) capacitive (b) inductive (c) resistive (d) all of these B 3.5 The voltage to current transducer circuit is transconductance amplifier. (True/False) A

3.6 The transresistance amplifier is a (a) current to voltage converter (b) voltage to current converter (c) current controlled current source B (d) voltage controlled current source 3.7 __________ is not an instrumentation amplifier IC. (a) AD521 (b) AD524 A (c) AD624 (d) LM324

3.8 Refer to practical integrator circuit of Fig. 3.17(a). The use of resistance Rf helps in (a) linearizing the output waveform when the input is square (b) better dc stability by providing a finite dc gain (c) overcoming the offset current and voltage effects C (d) reducing the transients 3.9 Design an Adder-Subtractor circuit for input voltages V1, V2 and V3 for achieving Vo = 2V1 + 2V2 + 2V3, the value of resistances required are (a) R1 = R2 = R3 = Rf (b) 2R1 = 2R2 = 2R3 = Rf (c) R1 = R2 = R3 = 2Rf C (d) none of these 3.10 For achieving (V1 + V2) – (V3 – V4) (a) two adders and one subtractors are needed (b) adder-subtractor is needed (c) adder is needed B (d) subtractor is needed 3.11 Current to Voltage converter can be used with (a) a photo cell (b) nuclear detector (c) load cell B (d) none of these

146

Linear IC Applications

3.12 The voltage follower circuit can be used as a buffer between ____ and _____ in that order. (a) low impedance load, high impedance source (b) high impedance source, a low impedance load C (c) none of these 3.13 Transconductance amplifier is a (a) current to voltage converter (b) current amplifier (c) voltage amplifier A (d) voltage to current converter 3.14 Transresistance amplifier is (a) voltage to current converter (b) voltage multiplier (c) voltage controlled current source A (d) current controlled voltage source 3.15 A voltage follower circuit with a slew rate of 1V/ms is applied with a unit step of voltage applied at time t = 0. The output magnitude at time t = 300 ns will be (a) 1 V (b) 0.3333 V C (c) 0.3 V (d) zero 3.16 The output of an integrator when applied A with a step input is (a) impulse (b) step (c) ramp (d) none of these 3.17 The output of a differentiator when applied B with a step input is (a) an impulse (b) a step (c) a ramp (d) none of these 3.18 The output voltage of a non-inverting current to voltage converter is Rf ˆ Ê (a) Vo = Á1 + I i R1 R1 ˜¯ Ë ÊR ˆ (b) Vo = Á f ˜ I i R1 Ë R1 ¯

3.22 For the differentiator circuit of Fig. 3.20, the output vo is given by (a) - R f C1 (b) R f C1 (c) -

dvi dt

dvi dt

1 dvi R f C1 dt

dvi A dt 3.23 A simple comparator circuit operates with a loop gain of (a) –1 (b) +1 (c) • (d) none of these (d)

A

Ê R ˆ (c) Vo = Á1 + 1 ˜ I i R1 Rf ¯ Ë (d) Vo = IiR1

3.19 A positive level shifter circuit for an ac signal can be realized by using a two input summing circuit with (a) a dc value applied to the inverting input along with ac signal (b) a dc value applied to the non-inverting input (c) a dc value applied to both the inputs C (d) none of these 3.20 For rectifying voltages less than 0.6 V, ___________ can be used with op-amp. (a) tunnel diode (b) precision diode (c) Zener diode B (d) none of these 3.21 The integrator circuit of Fig. 3.17(a) will have a dc gain of (a) zero (b) infinity (c) value equal to open loop gain of the op-amp B (d) none of these

B

3.24 Timing marker signal generator uses a ___________ circuit to generate the marking signal. (a) differentiator (b) integrator (c) Adder (d) subtractor B

Linear and Non-Linear Applications of Op-Amps

3.25 Timing marker signal generator employs (a) an op-amp (b) two op-amps (c) no op-amp (d) all of these

3.28 Precision rectifiers are used for rectifying voltages which is (a) equal to 0.6 V (b) more than 0.6 V (c) less than 0.6 V (d) none of these

A

3.26 Phase detector using comparator can measure phase differences of value (a) 0° to 90° (b) 0° to 180° (c) 90° to 270° (d) 0° to 360° B 3.27 Precision diode is (a) a half wave rectifier (b) a full wave rectifier (c) an accurate diode A (d) none of these

A

Answers to Objective-Type Questions 3.1 3.2 3.7 3.12 3.17 3.22 3.27

voltage gain False (d) (b) (a) (a) (a)

3.3 3.8 3.13 3.18 3.23 3.28

(c) (b) (d) (a) (c) (c)

3.4 3.9 3.14 3.19 3.24

147

(d) (c) (d) (a) (a)

3.5 3.10 3.15 3.20 3.25

True (b) (c) (b) (a)

3.6 3.11 3.16 3.21 3.26

(a) (a) (c) (c) (d)

Chapter

Active Filters, Analog Multipliers and Modulators

4 4.1

IntroductIon

The filter is an electric network which is used to change either the phase or the amplitude of signal with respect to its frequency. Ideally, this will not include any new frequency to the input and it will alter the frequency component of that signal. An active filter utilizes an op-amp along with resistors and capacitors for the filtering. The filters are widely used in communication, signal processing and sophisticated electronic instruments. The applications of filters also include the suppression of power-line hum, reduction of very low or high-frequency interference and noise, bandwidth limiting and specialised spectral shaping. This chapter provides the reader the insight into the design of various types of filters and their features. This is followed by the discussion on the analog multipliers and modulator. The balanced modulator-demodulator IC LM_1496 is introduced and application circuits using the IC LM1496 are discussed. Finally, the sample-and-hold circuits using op-amp are discussed.

4.2

types

of fIlters

A filter is a frequency selective circuit that allows only a certain band of the desired frequency components of an input signal to pass through and attenuates the signals of undesired frequency components. The filters are of two types, namely (i) analog filters and (ii) digital filters. The analog filters are further classified as passive filters and active filters. The passive filters utilise only resistors, inductors and capacitors. An active network is a circuit obtained by interconnecting passive elements (resistors and capacitors) and active elements (transistors, tunnel diodes and operational amplifiers). An active filter uses an op-amp in order to minimise the effect of loading on the frequency characteristics of the filter. The filters are widely used in communication, signal processing and sophisticated electronic instruments. The applications of filters also include the suppression of power-line hum, reduction of very low or highfrequency interference and noise, bandwidth limiting and specialised spectral shaping. A filter is a circuit that processes the signals based on the frequency dependency characteristics. The manner in which the behaviour of the filter varies with frequency is called its frequency response and it is expressed in terms of the transfer function H(jw), where w = 2pf is the angular frequency in radians per second (rad/s) and j is the imaginary unit. A filter is a linear two-port network with a transfer function H(s) = Vo(s)/Vi(s). Here, Vo(s) is the output response and Vi(s) is the input response This response is also expressed as H(jw) = |H(jw)| e jf(w) where |H(jw)| is the magnitude response and f(w) is the phase response. A filter can be realised in any one of the following four basic response types: (i) Low-pass filter (LPF) (ii) High-pass filter (HPF) (iii) Bandpass filter (BPF) (iv) Band-reject filter (BRF), Bandstop or Band elimination filter (BEF)

Active Filters, Analog Multipliers and Modulators

4.2.1

149

Low-pass Filter (LPF)

A low-pass filter allows only low frequency signals up to a certain break-point fH to pass through, while suppressing high frequency components as shown in Fig. 4.1(a). The range of frequencies from 0 to higher cut-off frequency fH is called passband and the range of frequencies beyond fH is called stopband.

Fig. 4.1

4.2.2

the ideal and practical characteristics of (a) Low-pass Filter, (b) high-pass Filter, (c) Band-pass Filter and (d) Band-reject Filter

High-pass Filter (HPF)

A high-pass filter allows only frequencies above a certain break-point fL to pass through and attenuates the low frequency components as shown in Fig. 4.1(b). The range of frequencies beyond its lower cut-off frequency fL is called passband and the range of frequencies from 0 to fL is called stopband.

4.2.3

Bandpass Filter (BPF)

The bandpass filter is the combination of high and low-pass filters, and this allows a specified range of frequencies to pass through. The ideal and practical characteristics of the bandpass filter are shown in

150

Linear IC Applications

Fig. 4.1(c). It has two stopbands in the range of frequencies between 0 and fL and beyond fH. The band between fL and fH is called passband. Hence, its bandwidth is ( fH - fL ).

4.2.4

Band-Reject Filter (BRF) or Band-Elimination Filter (BEF)

The band-reject filter is the logical inverse of bandpass filter, which does not allow a specified range of frequencies to pass through. The ideal and practical characteristics of the band-reject filter are shown in Fig. 4.1(d). It has two passbands in the range of frequencies between 0 and fL and beyond fH. The band between fL and fH is called stopband.

desIgn

4.3

and

analysIs

of

Butterworth actIve fIlters

The rate at which the response of a filter falls in the transition band is determined by the order of the filter. When the order of the filter is higher, the roll-off rate becomes faster. The order of the filter is derived from the transfer function of the filter. Besides the order, the type of filter determines the shape of the transition band. This is reflected by its damping factor. The popular alignment types are Chebyshev, Butterworth, Elliptic and Bessel approximations. The Chebyshev approximation provides a low-pass response that is equiripple in the passband with the transmission decreasing monotonically in the stopband. All the transmission zeros are at s = •. The Butterworth approximation provides a low-pass response that is maximally flat at w = 0 and it is characterised by its moderate amplitude and phase response. The transmission decreases monotonically as w increases, reaching 0 (infinite attenuation) at w = •, where all N transmission zeros lie. It exhibits the fastest roll-off of any monotonic or smooth filter. This is the only filter whose 3dB frequency equals its critical frequency ( f3dB = fc). Hence, the Butterworth approximation is widely used in the design of active filters. The magnitude response of Butterworth low-pass filter has a is given by A (4.1) H ( jw ) = 2N Êwˆ 1+ Á ˜ Ë wc ¯ where A is the filter gain and wc is the 3 dB cut-off frequency and N is the order of the filter. The magnitude response of the Butterworth filter is shown in Fig. 4.2. The magnitude response has a maximally flat passband and stopband. It can be seen that by increasing the filter order N, the Butter-worth filter response approximates the ideal response. However, the phase response of the Butterworth filter becomes increasingly non-linear with higher values of N. |H(jw)|

|H(jw)|

A

1 0.707A

a p (in dB)

d1 (N1 < N2)

a s (in dB)

N3 wc

0

(a) Fig. 4.2

(N2 < N3) w

d2

0

w1

w2

(b)

Butterworth low-pass filter (a) Magnitude response and (b) Design specification

w

Active Filters, Analog Multipliers and Modulators

151

The design parameters of the Butterworth filter are obtained by considering the low-pass filter with the desired specifications as given below. d1 £ H (e jw ) £ 1 , H (e

jw

0 £ w £ w1

) £ d2 ,

w2 £ w £ p

The corresponding analog magnitude response is to be obtained in the design process. Using the above equations and if A = 1, we get 1 d12 £ £1 1 + (w1/w c ) 2 N 1 £ d 22 1 + (w 2 /w c ) 2 N This equation can be written in the form 1 (w1/w c ) 2 N £ 2 - 1 d1 1 (w 2 /w c ) 2 N ≥ 2 - 1 d2

(4.2a) (4.2b)

Equality is assumed in Eqs (4.2a and b) in order to obtain the filter order N and the 3dB cut-off frequency wc. Dividing Eq. (4.2b) by Eq. (4.2a), we get

(

)(

)

(w 2 /w1) 2N = 1 /d 22 - 1 / 1/d12 - 1

From the above equation, the order of the filter N is given by

{(

)(

)}

2 2 È ˘ 1 log Î 1/d 2 - 1 / 1/d1 - 1 ˚ N= log (w 2 /w1 ) 2

(4.3)

The value of N is chosen to be the next nearest integer to the value of N as given by Eq. (4.3). Using Eq. (4.2a), we get w1 wc = 1/ 2 N 2 È ˘ Î 1/d1 - 1˚

(

)

(4.4)

The transfer function of the Butterworth filter is usually written in the factored form as given below. N /2

H(s) =

or

H(s) =

’

k =1 s

Bk w c2 2

N = 2, 4, 6, …

+ bk w c s + ck w c2

B0 w c s + c0 w c

( N - 1) /2

Bk w c2

k =1

s 2 + bk w c s + ck w c2

’

The coefficients bk and ck are given by bk = 2 sin[(2k - 1)p / 2N] and ck = 1 The parameter Bk can be obtained from N /2

A=

’ Bk ,

for even N

k =1

( N -1) / 2

and

A=

’ Bk , for odd N k =1

N = 3, 5, 7, …

(4.5)

152

Linear IC Applications

Note: If the passband attenuation a p and the stopband attenuation as are specified in dBs, then they can be related with d1 and d2 respectively, as follows: 1 1 0.1a ap= 20 log , i.e. 2 = 10 p (4.6) d1 d1 as= 20 log

1 1 , i.e. 2 = 100.1a s d2 d2

(4.7)

Poles of a Normalised Butterworth Filter The magnitude squared response of Butterworth low-pass filter given by 1

H ( jw ) = 2

1 + (w /w c ) For a normalised filter, w c = 1. Thus,

H ( jw ) = 2

2N

1 1 + w 2N

The normalised poles in the s-domain can be obtained by substituting w = s/j and equating the denominator polynomial to zero, 2N

Ê sˆ 1 + Á ˜ = 0, or 1 + (-s2)N = 0 Ë j¯ The solution to the above expression gives us the poles of the filter. The above expression can be written as

i.e.,

(- 1)N s 2 N

= -1 Expressing -1 in the polar form,

(- 1)N s 2 N

j ( 2 n - 1)p = e , n = 1, 2, …, N

The poles in the left-half of the s-plane are given by sn = s n + j w n = e j ( 2 n + N - 1)p /2 N = je j ( 2 n - 1)p /2 N Using the polar to rectangular conversion, e jq = cos q + j sin q, the normalised poles are obtained as Ê 2n - 1ˆ Ê 2n - 1ˆ sn = - sin Á p + j cos Á p Ë 2 N ˜¯ Ë 2 N ˜¯ Ï1, 2,.....( N + 1) /2, for N odd where n = Ì for N eveen Ó1, 2,......N /2, The un-normalised poles s¢n, can also be obtained from the normalised poles as shown below, s¢n = sn (w c ) - 1/N The normalised poles lie on the unit circle spaced p /N apart.

Active Filters, Analog Multipliers and Modulators

153

Butterworth Polynomials The Butterworth polynomials are given in Table 4.1. Table 4.1

Butterworth polynomials

N

Factors

Polynomial

1

s+1

s+1

2

s 2 + 2s + 1

s 2 + 2s + 1

3

( s + 1), ( s 2 + s + 1)

s3 + 2s 2 + 2s + 1

4

( s 2 + 0.765s + 1), ( s 2 + 1.848s + 1)

s 4 + 2.613s 3 + 3.414 s 2 + 2.613s + 1

5

( s + 1),( s 2 + 0.618s + 1), ( s 2 + 1.618s + 1)

s 5 + 3.236 s 4 + 5.236 s 3 + 5.236 s 2 + 3.236 s + 1

6

( s 2 + 0.518s + 1), ( s 2 + 2 s + 1), ( s 2 + 1.932 s + 1)

s 6 + 3.864 s 5 + 7.464 s 4 + 9.142 s 3 + 7.464 s 2 + 3.864 s + 1

7

( s + 1),( s 2 + 0.44 s + 1),

s 7 + 4.494 s 6 + 10.098s 5 + 14.592 s 4 +

( s 2 + 1.247 s + 1), ( s 2 + 1.802 s + 1)

14.592 s 3 + 10.098s 2 + 4.494 s + 1

( s 2 + 0.3s + 1), ( s 2 + 1.111s + 1),

s8 + 5.126 s 7 + 13.137 s 6 + 21.846 s 5 +

( s 2 + 1.166 s + 1), ( s 2 + 1.962 s + 1)

25.688s 4 + 21.846 s 3 + 13.137 s 2 + 5.1126 s + 1

( s + 1), ( s 2 + 0.347 s + 1),( s 2 + s + 1),

s 9 + 5.759 s8 + 16.582 s 7 + 31.163s 6 + 41.986 s 5

( s 2 + 1.532 s + 1), ( s 2 + 1.879 s + 1)

+ 41.986 s 4 + 31.163s 3 + 16.582 s 2 + 5.757 s + 1

( s 2 + 0.313s + 1), ( s 2 + 0.908s + 1),

s10 + 6.393s 9 + 20.432 s8 + 42.802 s 7 +

( s 2 + 2 s + 1), ( s 2 + 1.792 s + 1),

64.882 s 6 + 74.233s 5 + 64.882 s 4 + 42.802 s 3 +

( s 2 + 1.975s + 1)

20.432 s 2 + 6.393s + 1

8

9

10

4.4

desIgn

of

low-pass fIlters

In order to improve the response of the filter, a higher order filter can be used. A second order low-pass filter consists of two RC pairs and has a roll-off rate of -40dB/decade.

4.4.1

First Order Low-pass Filter with Unity Gain

The first order (one-pole) active low-pass filter with unity gain, i.e., with voltage follower is shown in Fig. 4.3(a). The voltage transfer function for the circuit is 1 Vo ( s ) 1 sC = = H(s) = 1 Vi ( s ) 1 + sRC +R sC 1 H ( jw ) = w 1+ j wH

154

Linear IC Applications

wH =

where

1 RC

H ( jw ) =

Therefore,

1 Ê w ˆ 1+ Á Ë w H ˜¯

2

or H ( jf ) =

1 Ê f ˆ 1+ Á Ë f H ˜¯

2

vo vi

Fig. 4.3

(a) First order low-pass filter with voltage follower (unity gain) and (b) Bode plot of low-pass filter with voltage follower (unity gain)

The Bode plot of the voltage gain magnitude curve is shown in Fig. 4.3(b). The slope of the voltage gain magnitude curve outside the passband is 6 dB/octave or 20 dB/decade. This characteristic is called the roll-off. The roll-off becomes sharper or steeper with higher-order filters. Example 4.1 A first order low-pass Butterworth active filter has a cut-off frequency of 10 kHz and unity gain at low frequency. Find the voltage transfer function magnitude in dB at 12 kHz for the filter. Solution

The voltage transfer function magnitude of the first order low-pass Butterworth filter is given by H ( jf ) =

1

=

Ê f ˆ 1+ Á Ë f H ˜¯

2

1 Ê 12 ¥ 103 ˆ 1+ Á ˜ Ë 10 ¥ 103 ¯

2

= 0.64, i.e., 20 log 0.64 = - 3.87 dB

4.4.2

First Order Low-pass Filter with Variable Gain

Figure 4.4(a) is an active low-pass filter with single RC network connected to the non-inverting terminal of op-amp. The input resistor Ri and feedback resistor Rf are used to determine the gain of the filter in the passband. At low frequencies, the capacitor appears open. And the circuit acts like a non-inverting amplifier Rf ˆ Ê with a voltage gain of Á1 + . As the frequency increases, the capacitive reactance decreases, causing the R ˜¯ Ë i

voltage gain to drop off.

Active Filters, Analog Multipliers and Modulators

155

Referring to Fig. 4.4(a), the voltage V1 across the capacitor is vi v1 = 1 + j 2 p f RC The output voltage V o for noninverting amplifier is Rf ˆ Ê v1 vo = Á 1 + Ri ˜¯ Ë By substituting V1 in the above equation, the output voltage Vo becomes Rf ˆ Ê vi vo = Á 1 + ˜ R ¯ 1 + j 2p f RC Ë i

vo = vi

or

A Ê f ˆ 1+ jÁ Ë f H ˜¯

vo is the gain of the low-pass filter vi which is a function of frequency,

where

Fig. 4.4

(a) First order low-pass filter with variable gain and (b) Its frequency response

Ê Rf ˆ A=1+ Á is the maximum passband gain of the filter, Ë Ri ˜¯ f is the frequency of the input signal 1 fH = is the higher cut-off frequency of the filter. 2p RC The frequency response of the filter can be determined by using the magnitude of the gain of the low-pass filter, which is expressed as vo A = (4.8) 2 vi Ê f ˆ 1+ Á Ë f H ˜¯ At very low frequencies, i.e., f < fH, the gain is approximately equal to A. When the frequency reaches the cut-off frequency, i.e., f = fH, the gain falls to 0.707 times the maximum gain A. The frequency from 0 to fH is called the passband. At high frequencies, i.e., f > fH, the gain decreases at a constant rate of –20 dB/decade. The frequency range beyond fH is called stopband. The frequency response of the active low-pass filter (nonideal) is shown in Fig. 4.4(b).

Low-pass Filter Design The following steps are used for the design of an active low-pass filter: (i) Choose the value of higher cut-off frequency fH (ii) Select the value of capacitor C such that its value is £ 1 mF (iii) When the values fH and C are known, the value of R can be calculated by using fH =

1 2p RC

156

Linear IC Applications

(iv) Finally, select the values of R i and R f depending on the desired passband gain by using Ê Rf ˆ A=1+ Á Ë R ˜¯ i

Example 4.2

Design a first order low-pass filter at a cut-off frequency of 2 kHz with a passband gain

of 2. Solution

Refer to Fig. 4.4(a) Given Let

fH = 2 kHz and A = 2 C = 0.01 mF

We know that

fH =

1 2p RC 1 1 R= = = 7.95 kW 2p f H C 2p 2 ¥ 103 ¥ 10-8 Rf A =1+ =2 Ri

Therefore,

(

We know that Therefore,

4.5

)

Rf = Ri = 10 kW (say)

general second-order actIve fIlter

Figure 4.5 shows a general second order (two-pole) active filter, also called Sallen-Key filter, with admittances Y 1 through Y 4 and an ideal voltage follower. The loading effect will be eliminated by using a voltage follower which has high input impedance and low output impedance. Further, a non-inverting amplifier configuration can be incorporated to increase the gain and to eliminate the loading effects. The transfer function for the general network is derived and then the specific admittance is applied to obtain the characteristics of the particular filter. Applying Kirchhoff’s current law equation at node Va, we get

wIth

unIty gaIn Y3

– Vb Vi

Y1

Y2

Vo +

Va Y4

Fig. 4.5

General second order active filter with unity gain

(Vi - Va )Y1 = (Va - Vb )Y2 + (Va - Vo )Y3

(4.9)

Applying Kirchhoff’s current law equation at node Vb, we get

(Va - Vb )Y2

= Vb Y4

(4.10)

According to voltage follower characteristics, Vb = Vo. Therefore, the above equation becomes Ê Y + Y4 ˆ Ê Y + Y4 ˆ Va = Vb Á 2 = Vo Á 2 ˜ Ë Y2 ¯ Ë Y2 ˜¯

(4.11)

Active Filters, Analog Multipliers and Modulators

157

Substituting the above equation into Eq. (4.9) and using the relation Vb = Vo, we get Vi Y1 + Vo (Y2 + Y3 ) = Va (Y1 + Y2 + Y3 ) Ê Y + Y4 ˆ = Vo Á 2 (Y1 + Y2 + Y3 ) Ë Y2 ˜¯

(4.12)

Multiplying the above equation by Y2, we get [ViY1 + Vo (Y2 + Y3)]Y2 = Vo (Y2 + Y4) (Y1 + Y2 + Y3) ViY1Y2 = Vo [Y1Y2 + Y 22 + Y2Y3 + Y4(Y1 + Y2 + Y3) – Y 22 – Y2Y3] = Vo [Y1Y2 + Y4(Y1 + Y2 + Y3)] Therefore,

H(s)=

Vo ( s ) Y1 Y2 = Vi ( s ) Y1 Y2 + Y4 (Y1 + Y2 + Y3 )

(4.13)

For obtaining a low-pass filter, both Y1 and Y2 should be conductances, i.e. Y1 = 1/R1 and Y2 = 1/R2, which will permit the signal to pass into the voltage follower at lower frequencies. If Y4 is a capacitor, then the output will roll-off at high frequencies. For producing a two-pole function, Y3 should also be a capacitor. If both Y1 and Y2 are capacitors, then the signal will be blocked at low frequencies but will be passed into the voltage follower at high frequencies, which results in a high-pass filter. Hence, both the admittances Y3 and Y4 should be conductances to produce a second order high-pass transfer function.

4.5.1

General Second-Order Active Filter with Variable Gain

A general second-order active filter with variable gain is shown in Fig. 4.6. Here, the op-amp is connected in non-inverting amplifier configuration. The results thus obtained can be used for the analyses of low-pass and high-pass filters. Therefore, Rf ˆ Ê Vo = Á 1 + Vb = AVb Ri ˜¯ Ë

(4.14)

Ri

Va Vi

Y1

Rf

Vb

Y3

Vo +

Y2 Y4

Rf ˘ È where A = Í1 + (4.15) Fig. 4.6 General second-order active filter ˙ Ri ˚ Î (Sallen-key filter) Applying Kirchhoff’s current law at node Va and using Eq. (4.14), we get ViY1 = Va (Y1 + Y2 + Y3 ) - Vo Y3 - Vb Y2

Vo Y2 A Applying Kirchhoff’s current law at node Vb and using Eq. (4.14), we get = Va (Y1 + Y2 + Y3 ) - Vo Y3 -

VaY2 = Vb (Y2 + Y4 ) =

Vo (Y2 + Y4 ) A

(4.16)

158

i.e.,

Linear IC Applications

Va =

Vo (Y2 + Y4 )

(4.17)

AY2

Substituting the above equation into Eq. (4.16), we get ViY1 =

Vo (Y2 + Y4 ) VY [Y1 + Y2 + Y3] – VoY3 – o 2 AY2 A

Vi (AY1Y2) = Vo [Y1Y2 + Y 22 + Y2Y3 + Y4(Y1 + Y2 + Y3) – Y2Y3A – Y 22] Therefore,

4.5.2

Vo ( s )

H(s) =

Vi ( s )

=

AY1 Y2 Y1 Y2 + Y4 (Y1 + Y2 + Y3 ) + Y2 Y3 (1 - A)

(4.18)

Second-Order Low-pass Filter with Unity Gain

The transfer function of a general second order low-pass active filter given in Eq. (4.13) can be used to analyse the second order low-pass and high-pass filters. A Butterworth filter is a maximally flat magnitude filter. The transfer function of the filter is designed in such a way that its magnitude is as flat as possible in the passband. Let Y1 = Y2 = 1/R, Y3 = sC3 and Y4 = sC4. Then, the transfer function is 1 1 R2 = H(s) = 1 Ê2 ˆ 1 + sRC4 ( 2 + sRC3 ) + sC4 Á + sC3 ˜ 2 Ë ¯ R R Let the time constant t1 = RC3 and t2 = RC4. Substituting s = jw, we get 1 1 H(jw) = = 2 1 + j wt 2 ( 2 + j wt 1 ) 1 - w t 1t 2 + j ( 2 wt 2 ) Therefore, its magnitude is

(

(

)

-1 / 2

)

2 2 H ( jw ) = ÈÍ 1 - w 2t 1t 2 + ( 2 wt 2 ) ˘˙ Î ˚ A maximally flat Butterworth filter will have a minimum rate of change. Therefore,

d H ( jw ) =0 dw Differentiating H ( jw ) , we obtain d H ( jw ) 1 =dw 2

(

È 1 - w 2t t 1 2 ÍÎ

)

2

2 + ( 2 wt 2 ) ˘˙ ˚

Letting the derivative to zero, we get d H ( jw ) =0 dw i.e.,

(

)

È- 4 wt 1t 2 1 - w 2t 1t 2 + 8 wt 22 ˘ = 0 Î ˚

(

)

= 4 wt 2 È- t 1 1 - w 2t 1t 2 + 2t 2 ˘ = 0 Î ˚

-3 / 2

(

)

È-4 wt 1t 2 1 - w 2t 1t 2 + 8 w t 22 ˘ Î ˚

Active Filters, Analog Multipliers and Modulators

159

The above equation is satisfied when 2t2 = t1 (1− w 2 t1t2 ). That is, C3 = 2C4. Therefore, the magnitude of the transfer function becomes 1 |H(jw)| = 1/ 2 È1 + 4 (wt )4 ˘ 2 Î ˚ The cut-off frequency occurs when H ( jw ) =

1 2

, or 4 (w 3dBt 2 ) = 1. 4

Therefore, w3dB = 2 p f3dB =

1

=

t2 2

1 2 RC4

1 We know that the cut-off frequency of a low-pass filter is wH = w3dB = . RC Comparing the above equations, we get C4 = 0.707C C3 = 1.414C The magnitude of the voltage transfer function for the second order low-pass Butterworth filter is H ( jf ) =

1 Ê f ˆ 1+ Á Ë f H ˜¯

4

The second order low-pass Butterworth filter is shown in Fig. 4.7(a). The Bode plot of the transfer function magnitude is shown in Fig. 4.7(b).

Fig. 4.7

(a) Second order low-pass Butterworth filter with unity gain (b) Its Bode plot of the transfer function magnitude

Example 4.3 Design a second-order low-pass Butterworth filter with a cut-off frequency of 10 kHz and unity gain at low frequency. Also determine the voltage transfer function magnitude in dB at 12 kHz for the filter. Solution

Refer to Fig. 4.7(a). We know that

fH =

1 2p RC

160

Linear IC Applications

Therefore,

RC =

Letting

1 1 = = 15.92 ¥ 10-6 2 p f H 2p ¥ 10 ¥ 103

R = 200 kW, results in C = 79.6 pF

Therefore,

C3 = 1.414C = 113 pF and C4 = 0.707C = 56.3 pF

The voltage transfer function is 1

H ( jf ) =

Ê f ˆ 1+ Á Ë f H ˜¯

1

= 4

= 0.5704 i.e.,

Ê 12 ¥ 103 ˆ 1+ Á ˜ Ë 10 ¥ 103 ¯

4

20 log 0.5704 = -4.88 dB

4.5.3 Second-Order Low-pass Filter with Variable Gain To form a low-pass filter, we choose Y1 = Y2 = 1/R and Y3 = Y4 = sC as shown in Fig. 4.8(a). Here, equal value of components is used for simplicity. Therefore, the transfer function H(s) of a second order low-pass filter with variable gain becomes H (s) =

Vo ( s ) Vi ( s )

A =

Ri

R

Rf +

R

Vi

+ C

Fig. 4.8

Vo

C

(a) a second-order low-pass filter with variable gain

1 R2

1 Ê1 1 ˆ sC + sC Á + + sC ˜ + (1 - A) 2 ËR R ¯ R R A = Ê2 ˆ 1 + sCR 2 Á + sC ˜ + sCR (1 - A) ËR ¯ A = 1 + s 2 C 2 R 2 + 3sCR - AsCR A H(s) = 2 2 2 (4.19) s C R + sCR (3 - A) + 1 When s = 0, H(0) = A ; when s = •, H(•) = 0, which indicates that this configuration is for low-pass active filters. For second order physical systems such as electrical, mechanical, chemical and hydraulic, the transfer function can be generally expressed as H(s) =

A w H2 s 2 + aw H s + w H2

(4.20)

161

Active Filters, Analog Multipliers and Modulators

where A is the gain of the system, wH is the higher cut-off frequency in rad/sec and a is the damping coefficient. Comparing Eq. (4.19) and Eq. (4.20), we obtain 1 wH = (4.21) RC a = (3 - A) (4.22) Substituting s = jw in Eq. (4.20), we get A H(jw) = (4.23) 2 ( j w /w H ) + j a (w /w H ) + 1 The normalised expression for low-pass filter is given by A H(jw) = 2 s + as + 1

(4.24)

Ê w ˆ where normalised frequency s = j Á Ë w H ˜¯ The expression of magnitude in dB of the transfer function is 20 log H ( j w ) = 20 log

A 1 + j a (w /w H ) + ( j w /w H )

2

È ˘ Í ˙ Í ˙ A ˙ = 20 log Í 2 2 ˙ Í Ê 2 ˆ Ê w ˆ ˙ Í 1- w + Áa 2 ˜ Í ÁË Ë w H ˜¯ ˙˚ wH ¯ Î

(4.25)

Figure 4.8(b) shows the frequency response for different values of damping coefficient a. For a heavily damped filter, the response is stable. However, the roll-off to the passband starts very early. For lower values of a, the response overshoots and ripple appears at the early stages of passband. If a is very low, then the filter becomes oscillatory. The flattest passband occurs when a = 2 = 1.414 , which is called Butterworth filter response. Therefore, 20 log H ( j w ) = 20 log

A Ê w ˆ 1+ Á Ë w H ˜¯

4

(4.26)

Therefore, for the generalised Nth order low-pass Butterworth filter, the normalised transfer function is H ( jw) A

=

1 Ê w ˆ 1+ Á Ë w H ˜¯

2N

(4.27)

162

Linear IC Applications

For the unity gain system, the above equation becomes 1 H ( jw) = 2N Ê w ˆ 1+ Á Ë w H ˜¯ +10

(4.28)

0.5

0.866

0.766

|H ( jw)| dB

0 1.06 Chebyshev –10 1.414 Butterworth 1.73 Bessel

–20 –30 –40 0.1

Fig. 4.8

0.2

0.3

w wH

1

2

3

10

(b) Frequency response of second order low-pass filter for different damping with unity gain (a = 1)

Example 4.4

Design a second order Butterworth low-pass filter having upper cut-off frequency of 2 kHz.

Solution

Refer to Fig. 4.8(a). Given N = 2 and fH = 2 kHz = 1/2 pRC. 1 1 = = 79.58 ¥ 10-6 Therefore, RC = 2p f H 2p ¥ 2 ¥ 103 Letting

4 5

C = 0.1 mF, we get R = 0.8 kW

The order of the filter N = 2. From the Table 4.2, we get a = 2 = 1.414. The passband gain A = 3 - a = 3 - 1.414 = 1.586 Hence, the transfer function of second order low-pass Butterworth filter is 1.586 A = 2 H(s) = 2 s + 1.414 s + 1 s + 1.414 s + 1 Here, A = 1 + Rf/Ri = 1.586 R Therefore, f = 0.586 Ri Let Rf = 5.86 kW. Hence, Ri = 10kW

Active Filters, Analog Multipliers and Modulators

desIgn

4.6

163

hIgh-pass fIlters

of

The high-pass filter is the complement of the low-pass filter. Hence the high-pass filter can be obtained by simply interchanging R and C in the circuit of low-pass configuration.

4.6.1

First-Order High-pass Filter with Unity Gain

The first order active high-pass filter with unity gain, i.e., with voltage follower is shown in Fig. 4.9(a). The voltage transfer function for this circuit is H(s) =

Therefore,

Vo ( s ) Vi ( s )

=

R 1 R+ sC

=

1

1 sRC 1 1 where w L = H(jw) = RC Ê wL ˆ 1+ jÁ Ë w ˜¯ 1 1 H ( jw ) = or H ( jf ) = 2 2 Êw ˆ Ê f ˆ 1+ Á L ˜ 1+ Á L ˜ Ë w ¯ Ë f ¯ 1+

The Bode plot of the voltage gain magnitude curve is shown in Fig. 4.9(b). The slope of the voltage gain magnitude curve outside the passband is 6 dB/octave or 20 dB/decade. This characteristic is called the roll-off. The roll-off becomes sharper or steeper with higher-order filters.

Fig. 4.9

4.6.2

(a) First-order high-pass filter with voltage follower (unity gain) (b) Bode plot of high-pass filter with voltage follower (unity gain)

First-Order High-pass Filter with Variable Gain

The active high-pass filter with a single RC network connected to non-inverting terminal of the op-amp is shown in Fig. 4.10(a). The input resistor Ri and feedback resistor Rf are used to determine the gain of the filter in the passband. At low frequencies, the capacitor appears open, and the voltage gain approaches zero. At high frequencies, the capacitor appears shorted, and the circuit becomes a non-inverting amplifier with a Rf ˆ Ê voltage gain of Á1 + . R ˜¯ Ë i

164

Linear IC Applications

Fig. 4.10

(a) First-order active high-pass filter with variable gain (b) Frequency response of an active high-pass filter

The output voltage Vo of the first order active high-pass filter is R f ˆ j 2 p fRC Ê Vo = Á 1 + Vi R ˜¯ 1 + j 2 p fRC Ë i

Therefore, the gain of the filter becomes Ê Ê f ˆ ˆ jÁ ˜ ˜ Á Ë fL ¯ ˜ Vo = AÁ (4.29) Á Vi Ê f ˆ˜ j 1 + Á ÁË f ˜¯ ˜¯ Ë L Ê Rf ˆ , the frequency of the input signal is f and the lower cut-off where passband gain of the filter is A = 1 + Á Ë Ri ˜¯ 1 . frequency of the filter is fL = 2p RC The frequency response of the filter is obtained from the magnitude of the filter. Ê f ˆ AÁ ˜ Ë fL ¯ V A That is, (4.30) H ( jf ) = o = = 2 2 Vi Ê f ˆ Ê f ˆ 1+ Á L ˜ 1+ Á ˜ Ë f ¯ Ë fL ¯ At very high frequencies, i.e., f > fL, the gain is approximately A. At frequency f = fL, the gain falls to 0.707 times the maximum gain A. The range of frequency above fL is called the passband. For frequency f < fL, the gain decreases at a constant rate of –20 dB/decade. The frequency range below the cut-off frequency is called stop band. The frequency response of the first order active high-pass filter is shown in Fig. 4.10(b). It is to be noted that the high-pass second order filter is obtained from the low-pass second order filter by applying the transformation, w s = 0 w 0 low- pass s high - pass Hence, the resistors R and capacitors C are interchanged in a low-pass active filter to get a high-pass active filter.

Active Filters, Analog Multipliers and Modulators

165

Example 4.5 Design a first order high-pass filter at a cut-off frequency of 2 kHz with a passband gain of 2. Also, plot its frequency response. Solution

Refer to Fig. 4.10(a). Given fL = 2 kHz Let C = 0.01 mF 1 2p RC

We know that fL =

1 1 = = 7.95 kW 2 p f L C 2 p 2 ¥ 103 ¥ 10-8 Rf Rf Also, A = 1+ = 2 i.e., =1 Ri Ri Therefore, Rf = Ri = 10 kW (say) The frequency response data for the first order high-pass filter of this example are given in Table 4.2. The plot of the resulting frequency response is shown in Fig. 4.11. Therefore,

Table 4.2

R=

(

)

Frequency response data for the first order high-pass filter of Example 4.5

Frequency, f (Hz)

Gain, |Vo/Vi|

100

0.10

-20.01

200

0.20

-14.02

400

0.39

-8.13

700

0.66

-3.60

1000

0.89

2000 3000 7000 10000 13000 100000

1.414 1.66 1.92 1.96 1.98 2.00

-0.97 3.01 4.42 5.68 5.85 5.92 6.02

Fig. 4.11

Gain in dB, 20 log|Vo/Vi|

Frequency response of first-order high-pass filter

166

4.6.3

Linear IC Applications

Second-Order High-Pass Filter with Unity Gain

A second order high-pass Butterworth filter is shown in Fig. 4.12(a). The analysis can be done exactly the same way as for the low-pass filters except that the derivative is set equal to zero at s = jw = • . Also, the two capacitors are assumed equal. The 3 dB cut-off frequency is 1 fL = 2p RC Here, we find that R3 = 0.707R and R4 = 1.414R. The magnitude of the transfer function for the second order high-pass Butterworth filter is 1 H ( jf ) = 4 Ê f ˆ 1+ Á L ˜ Ë f ¯ The Bode plot of the transfer function magnitude for the second order high-pass Butterworth filter is shown in Fig. 4.12(b).

Fig. 4.12

4.6.4

(a) Second order high-pass Butterworth filter with unity gain (b) Its Bode plot of the transfer function magnitude

Second-Order High-Pass Filter with Variable Gain

To form a high-pass filter, using Eq. (4.13) we choose Y1 =Y2 = sC and Y3 =Y4 =1/R as shown in Fig. 4.13. Here, equal value of components is used for simplicity. Therefore, the transfer function H(s) of a second order high-pass filter becomes H (s) =

=

As 2 C 2 1Ê 1 ˆ sC s 2 C 2 + Á 2 sC + ˜ + (1 - A) RË R¯ R As 2 2s 1 s s2 + + 2 2+ (1 - A) RC R C RC As 2

= s2 +

1 1 (3 - A ) s + 2 2 RC R C

Fig. 4.13

Second-order high-pass filter with variable gain

Active Filters, Analog Multipliers and Modulators

A s2

H(s) =

s 2 + (3 - A) w L s + w L2 1 where wL = RC A H(s) = 2 w Êw ˆ 1 + L (3 - A ) + Á L ˜ Ë s ¯ s

167

(4.31)

(4.32)

When s = 0, H(0) = 0, and when s = •, H(•) = A. It is obvious that this configuration is for high-pass active filters. Therefore, the lower cut-off frequency is 1 fL = f3dB = (4.33) 2 p RC Letting s = jw in Eq. (4.32) and (3 - A) = a = 2 = 1.414, the transfer function of second order Butterworth high-pass filter becomes A (4.34) H ( jw ) = 4 Ê wL ˆ 1+ Á Ë w ˜¯ A or, H ( jf ) = (4.35) 4 Ê fL ˆ 1+ Á ˜ Ë f ¯ Therefore, for the generalised Nth order high-pass Butterworth filter, the normalised transfer function is H ( jw ) A

=

1 Êw ˆ 1+ Á L ˜ Ë w ¯

2N

For the unity gain system, the above equation becomes 1 H ( jw ) = 2N Êw ˆ 1+ Á L ˜ Ë w ¯

(4.36)

(4.37)

Example 4.6 (a) Find the lower cut-off frequency fL for the second order high-pass Butterworth filter shown in Fig. 4.14. (b) Also, find the passband gain of the filter and (c) plot the frequency response of the filter.

Fig. 4.14

Second order high-pass Butterworth filter with variable gain

168

Linear IC Applications

Solution

(a) Given R2 = R3 = 16 kW and C2 = C3 = 0.01 mF Therefore, the lower cut-off frequency is 1 1 = fL = 2p RC 2 p R2 R3C2C3 1

= 2p

(16 ¥ 10 ) (0.01 ¥ 10 ) 3 2

-6 2

ª 1 kHz

(b) The passband gain of the filter is Rf 15.8 ¥ 103 =1+ = 1.586 A = 1+ Ri 27 ¥ 103 The voltage gain magnitude is H ( jf ) =

Vo A = 4 Vi 1 + ( fL / f )

(c) The frequency response data for the second order high-pass filter of this example are given in Table 4.3. The plot of the resulting frequency response is shown in Fig. 4.15. Table 4.3

Frequency response data for the second order high-pass filter of Example 4.6 Gain, |Vo /Vi | 0.02 0.06 0.70 1.12 1.58 1.59 1.59 1.59 1.59

Frequency, f (Hz) 100 200 700 1000 3000 7000 10000 30000 100000

Gain in dB, 20 log |Vo /Vi | -35.99 -23.96 -3.12 1.00 3.95 4.00 4.01 4.01 4.01

+10

Voltage gain in dB

+4.006 0 dB

3 dB { 40 dB/decade

–10 –20 –30

–35.39

Stopband

100 kHz

Fig. 4.15

fL = 1 kHz

Passband 10 kHz

100 kHz

Frequency response of second order high-pass filter

1 MHz f

Active Filters, Analog Multipliers and Modulators

169

Bandpass fIlters

4.7

A bandpass filter passes a particular band of frequencies and attenuates any input frequency outside this passband. The bandpass filter has a passband between higher cut-off frequency fH and lower cut-off frequency fL, such that fH > fL. This filter has a maximum gain at the resonant frequency ( fr), which is defined as fr =

fH fL

The figure of merit or quality factor Q is given by fr f = r Q= fH - fL B where B is the bandwidth. A filter with high Q selects a smaller band of frequencies (more selective). If the resonant frequency fr and Bandwidth B are known, then the cut-off frequencies can be determined from B2 B + f r2 fL = 4 2 and fH = fL + B The bandpass filters can be classified as (i) wideband bandpass filter and (ii) narrowband bandpass filter. Example 4.7 If a bandpass filter has a lower cut-off frequency fL = 250 Hz and a higher cut-off frequency fH = 2500 Hz, then find its bandwidth and the resonant frequency. Solution

The bandwidth of the bandpass filter is B = fH - fL = 2500 - 250 = 2250 Hz The resonant frequency of the bandpass filter is fr =

f H f L = 2500 ¥ 250 = 790.56 Hz

Here, the centre frequency is (250 + 2500)/2 = 1375 Hz. Hence, it proves that the resonant frequency is always less than the centre frequency. Example 4.8 Given a bandpass filter with resonant frequency fr of 1000 Hz and a bandwidth B of 3000 Hz, find its (a) quality factor, (b) lower cut-off frequency and (c) higher cut-off frequency. Solution

(a) The figure of merit or quality factor Q is given by Q=

fr f 1000 = r = = 0.33 fH - fL B 3000

(b) The lower cut-off frequency of the bandpass filter is fL =

B2 B + f r2 - = 4 2

(3000)2 4

+ (1000) 2 -

(c) The upper cut-off frequency is fH = fL + B = 302.77 + 3000 = 3302.77 Hz

3000 = 302.77 Hz 2

170

Linear IC Applications

4.7.1 Wideband Bandpass Filter A bandpass filter can be constructed simply by connecting the low-pass and high-pass filters in cascade as shown in Fig. 4.16(a). Here, the low-pass circuit will pass all frequencies up to its cut-off frequency fH, while the high-pass circuit will block all frequencies below its cut-off frequency fL, provided fH > fL, i.e., fH must be at least 10 times fL. The cut-off frequencies of the low and high-pass sections must have the equal passband gain. Hence, the combination enables the filter acquire the passband from fL to fH as shown in Fig. 4.16(b). Low-pass response

Vo /Vi Vi

High-pass response

1 Low-pass filter

High-pass filter

Vo

–3 dB

fL

fH f

(a)

(b)

Fig. 4.16

(a) Cascaded low-pass and high-pass filters acting as bandpass filter (b) Frequency response of the bandpass filter

Fig. 4.17

(a) ±20 dB/decade-wide bandpass filter (b) Its frequency response

Active Filters, Analog Multipliers and Modulators

171

For realising a ±20 dB/decade bandpass filter, first-order high-pass and first-order low-pass sections are cascaded as shown in Fig. 4.17(a), in which A1 and A2 are dual op-amps. Its frequency response is shown in Fig. 4.17(b). Here, the total gain of the wide band-pass filter is A1 A2. For realising a ±40 dB/decade bandpass filter, second-order high-pass and second-order low-pass sections can be cascaded and so on. Example 4.9 Design a wide band-pass filter having fL = 400 Hz, fH = 2 kHz and pass band gain of 4. Find the value of Q of the filter. Solution

Given pass band gain A = 4. Let the gain of the high-pass section be A1 = 2. For the first order high-pass section, fL = 400 Hz. Let C = 0.1 mF. Therefore,

R =

1 1 = = 3.98 kW 2p f LC 2p ¥ 400 ¥ 0.1 ¥ 10 - 6 Rf

A1 = 1 + Therefore, Hence, let

R1

Rf R1

=2

=2–1=1

Rf = R1 = 3.98 kW

For the first order low pass section, let fH = 2 kHz and C ¢ = 0.01 mF. Here,

A2 =

A 4 = =2 A1 2

R¢ =

1 1 = = 7.96 kW 3 2p f H C ¢ 2p ¥ 2 ¥ 10 ¥ 0.01 ¥ 10 - 6

A2 = 1 +

R¢f R1¢

=2

i.e.,

R¢f = R¢1

Therefore,

R¢f = R¢1 = 7.96 kW

Resonant frequency

fr =

Bandwidth

f L ¥ f H = 400 ¥ 2 ¥ 103 = 894.427 Hz

BW = fH – fL = 2 ¥ 103 – 400 = 1600 Hz Q=

fr 894.427 = 0.559 = Bandwidth 1600

172

4.7.2

Linear IC Applications

Narrowband Bandpass Filter

The narrowband bandpass filter using one inverting mode op-amp with two feedback paths is shown in Fig. 4.18(a) and its frequency response is shown in Fig. 4.18(b). The resonant frequency can be changed by adjusting Rr without changing the bandwidth or gain. The bandwidth B is determined by resistor R and the two matched capacitors C as given by B=

0.1591 RC

where B = fr /Q. The adjustable resistor Rr is determined by Rr =

R 2Q 2 - 1

Fig. 4.18

(a) Narrowband bandpass filter circuit (b) Its frequency response

Its resonant frequency fr is determined from fr =

0.1125 R 1+ RC Rr

Example 4.10 Given a bandpass filter with the component values shown in Fig. 4.19, find its (a) resonant frequency and (b) bandwidth.

Fig. 4.19

Narrowband bandpass filter

Active Filters, Analog Multipliers and Modulators

173

Solution

(a) The resonant frequency of the bandpass filter is fr =

=

0.1125 R 1+ RC Rr 0.1125

(20 ¥ 10 ) (0.01 ¥ 10 ) -6

3

1+

20 ¥ 103 2.7 ¥ 103

ª 1631 Hz

(b) The bandwidth of the bandpass filter is B=

0.1591 0.1591 = = 795.5 Hz 3 RC 20 ¥ 10 0.01 ¥ 10 - 6

(

)(

)

Design a narrowband bandpass filter with a resonant frequency of 200 Hz and a

Example 4.11

bandwidth of 20 Hz. Solution

f r 200 = = 10 20 B

Here

Q=

Let

C = 0.33mF

We know that

R=

Therefore,

Rr =

4.8

0.1591 0.1591 = = 24.1 k W BC 20 0.33 ¥ 10 - 6

(

R 2Q 2 - 1

=

24.1 ¥ 103 2 ¥ 102 - 1

)

= 121.1 W

Band-reject fIlters

The band-reject filter, often called the band-elimination or band-stop filter attenuates the frequencies in the stopband and passes them outside this band. The band-reject filter can be classified as (i) wideband band-reject filter and (ii) narrowband band-reject filter.

4.8.1 Wideband Band-reject Filter A band-reject filter or bandstop filter can be constructed by parallel connecting a low-pass filter and a highpass filter as shown in Fig. 4.20(a). The inputs are connected in parallel, and the outputs should be applied to a summing circuit in order to avoid one input overloading the other. Here, the low-pass circuit will block all frequencies above its cut-off frequency fH, while the high-pass circuit will block frequencies below its cut-off frequency fL, provided fL > fH. The result is a stopband of fL to fH as shown in Fig. 4.20(b) and (c).

174

Linear IC Applications |H( f )| Low-pass High-pass filter Vi

f

fH

|H(f )|

High-pass

Vo

Summing circuit

fL

|H(f )|

f

Bandreject

Low-pass filter

fH (a)

fL

f

(b) Vo Vi

High-pass response

Low-pass response

1 –3 dB

fH

fL

f

(c)

Fig. 4.20

(a) parallel combination of low-pass and high-pass filters results in a band-reject filter, (b) Ideal band-reject filter frequency response (c) practical frequency response of the band-reject filter

Figure 4.21(a) shows a wideband band-reject filter that is obtained by paralleling a high-pass filter with a cut-off frequency of fL with a low-pass filter with cut-off frequency of fH, provided fL > fH and a summing amplifier connected in series to add the filtered individual passband components. The passband gains of both the high-pass and low-pass sections must be equal i.e., A1 = A2. The frequency response characteristic of the wideband band-reject filter is shown in Fig. 4.21(b). The amplifiers A1, A2 and A3 can be obtained by using the quad op-amp such as mAF774 or MC34004. The design of the filter is based on the design of individual sections of the circuit. The passband gain can also be suitably selected. If the gain is set at 1, then R2 = R3 = R4. The value of Ro is parallel combination of R2, R3 and R4.

Active Filters, Analog Multipliers and Modulators

Fig. 4.21

4.8.2

175

(a) Circuit of a wideband band-reject filter (b) Its frequency response

Narrowband Band-reject Filter (Notch filter)

The narrowband band-reject filter, often called the notch filter is the twin-t network cascaded with the voltage follower as shown in Fig. 4.22(a). By using the Star-Delta conversion formulae, the Twin-T network shown in Fig. 4.22(b) can be modified as equivalent delta network shown in Fig. 4.22(c). The impedance of the delta network equivalent to the twin-T network is Z1 = Z3 = Z2 =

sCR + 1 2 sC

2 R ( sCR + 1)

(s R C + 1) 2

2

2

176

Linear IC Applications

Fig. 4.22

(a) Circuit of a narrowband band-reject (notch) filter (b) twin-t network, (c) equivalent Delta network (d) Its frequency response

From Fig. 4.22(c), we get s 2C 2 R 2 + 1 V2 = 2 2 2 s C R + 4 sCR + 1 V1 Substituting s = jw, the above equation becomes 1 - w 2C 2 R 2 V2 = 1 - w 2 C 2 R 2 + j 4 w RC V1 Setting the real part to be zero, we get the notch-out frequency fo , at which the maximum attenuation occurs as given by 1 fo = 2p RC Applying Kirchhoff’s current law at node Va in Fig. 4.22(a), we get

(Vi - Va ) sC + (Vo - Va ) sC + ( KVo - Va ) 2G = 0 or

sCVi + ( sC + 2 KG )Vo = 2 ( sC + G )Va

where K =

R2 1 and G = R ( R1 + R2 )

Active Filters, Analog Multipliers and Modulators

177

Applying Kirchhoff’s current law at node Vb, we get

(Vi - Vb ) G + (Vo - Vb ) G + 2 ( KVo - Vb ) sC

=0

GVi + (G + 2 KsC )Vo = 2 (G + sC )Vb

or

Applying Kirchoff's Current law at node Vp, we get

(Va - Vo ) sC + (Vb - Vo ) G = 0 sCVa + GVb = (G + sC )Vo

or

Using the above three node current equations, the transfer function can be written as H(s) =

=

Vo ( s ) Vi ( s )

=

G 2 + s 2C 2 G 2 + s 2 C 2 + 4 (1 - K ) sCG Ê Gˆ s2 + Á ˜ Ë C¯

2

2

Ê Gˆ Ê Gˆ s 2 + Á ˜ + 4 (1 - K ) s Á ˜ Ë C¯ Ë C¯

In the steady-state, with s = jw , we get H(jw) = where wo =

w 2 - w o2

w 2 - w o2 - j 4 (1 - K ) ww o

G 1 1 or fo = = C RC 2p RC

From the above equation H(jw) becomes zero for w = wo and approaches unity as w > wo. In practice, the high frequency response will be limited by the high frequency response characteristics 1 of the op-amp. At 3dB cut-off frequency, H ( jw ) = 2 Therefore,

w 2 - w o2 = ± 4 (1 - K ) ww o

or

Êwˆ Êwˆ ÁË w ˜¯ ± 4 (1 - K ) ÁË w ˜¯ -1 = 0 o o

2

Upon solving the above quadratic equation, we obtain the upper and lower half power frequencies as, 2 fH= f o ÈÍ 1 + 4 (1 - K ) + 2 (1 - K )˘˙ Î ˚

and The 3 dB bandwidth is

The Quality factor

2 fL= f o ÈÍ 1 + 4 (1 - K ) - 2 (1 - K )˘˙ Î ˚

B= f H - f L = 4 (1 - K ) f o Q=

fo 1 = B 4 (1 - K )

178

Linear IC Applications

As K approaches unity, Q factor becomes very large and B approaches zero. In fact, mismatches between resistors and capacitors limit the Q factor and bandwidth B to a practically realisable value. The frequency response of the active notch filter is shown in Fig. 4.22(d). These notch filters are used in communications and bio-medical instrumentation applications to eliminate the undesired frequencies. They are also useful for the rejection of a single frequency, such as 50 or 60 Hz power line frequency hum.

all-pass fIlters

4.9

An all-pass filter allows all the frequency components of the input signal to pass without attenuation, while providing the required phase shift at a given frequency of the input signal. The phase shift circuits, namely, phase lag and phase lead circuits fall into the category of all-pass filters, wherein Rf = R1. They pass all frequencies but delay the signal by a predictable time. The all-pass filters are also called delay equalisers, phase correctors, or constant delay filters. All-pass filters provide a delay without varying the amplitude response. Some analog computational functions provide a delay, i.e. inverting amplifiers give a constant 180o phase shift, differentiators give a 90o phase lead and integrators give a 90o phase lag. All-pass filter provides an adjustable phase shift. The phase of the signals may change when transmitted over telephone wires. Hence, all-pass filters are required to correct these phase changes. Furthermore, the all-pass filters are used (i) to prevent aliasing, (ii) to reject high-frequency interference such as that from the power line frequency and harmonics, and ripples from isolation amplifiers and (iii) to limit bandwidth.

4.9.1 All-Pass Filter using op-amp The phase shift circuits produce phase shifts that depend on the frequency and maintain a constant gain. These circuits are also called constant-delay filters or all-pass filters. The constant-delay refers to the fact that the time difference between input and output remains constant when frequency is changed over a range of operating frequencies. This is also called all-pass because normally a constant gain is maintained for all the frequencies within the operating range. Figure 4.23(a) shows the all-pass filter circuit constructed using an op-amp, connected in both inverting and noninverting modes. To analyse the circuit operation, it is assumed that the input voltage vi drives a simple inverting amplifier with input applied at (–) and (+) terminals of opamp. It is also assumed that inverting gain is –1 and nonRf inverting gain after the low-pass circuit is 1 + = 1 + 1 = 2, R1 since Rf = R1. Fig. 4.23 vo vi 1 f (log)

Fig. 4.23

(b) Bode plot for the all-pass Filter circuit

(a) all-pass Filter circuit

Active Filters, Analog Multipliers and Modulators

Voltage Vin

179

Vo

0 Phase Angle in Degrees

φ Lagging Phase Angle Fig. 4.23

(c) Input-output waveform for theta=90°

For the circuit shown in Fig. 4.23(a), it can be written as Vo ( jw ) = -Vi ( jw ) + 2

1 Vi ( jw ) 1 + jw RC

(4.38)

ˆ Ê Ê 1 - jw RC ˆ 1 Therefore, Vo ( jw ) = Vi ( jw ) Á -1 + 2 = Vi ( jw ) Á ˜ 1 + jw RC ¯ Ë Ë 1 + jw RC ˜¯ The relationship between output and input can be expressed by Vo ( jw )

Ê 1 - jw RC ˆ =Á Vi ( jw ) Ë 1 + jw RC ˜¯

(4.39)

The relationship is complex as defined by Eq. (4.39), and it shows that it has both magnitude and phase. Since the numerator and denominator are complex conjugates, their magnitudes are identical and the overall phase angle is equal to the angle of numerator minus the angle of the denominator. The phase angle is then given by q = - tan -1 (w RC ) - tan -1 (w RC ) = - 2 tan -1 (w RC )

(4.40)

Here, when w = 0, the phase angle approaches zero. When w = •, the phase angle approaches –180°. Then Eq. (4.40) can be written as q = - 2tan -1 ( f / f o ) (4.41) where the frequency fo is given by 1 fo = 2p RC

(4.42)

Here, when f = fo in Eq. (4.41), the phase angle q = –90°. The Bode plot for the all-pass filter circuit is shown in Fig. 4.23(b). The output voltage vo will have the same frequency as the input, however lagging vi by 90o as shown in Fig. 4.23(c). Example 4.12 Determine the phase angle and the time delay for the circuit shown in Fig. 4.23(a) for a frequency of 2 kHz, assuming R1 = 20 kW, R = 39 kW, Rf = R1 and C = 1 nF. Solution

The circuit is a phase-lag network. Therefore, f o =

1 1 = = 4081 Hz . 2p RC È2 ¥ p ¥ 39 ¥ 103 ¥ 1 ¥ 10-9 ˘ Î ˚

180

Linear IC Applications

The phase angle for frequency of 2 kHz is given by, Ê 2 ¥ 103 ˆ q = - 2tan -1 Á ˜ = - 52.2∞ Ë 4081 ¯ The phase angle is directly proportional to delay, and 360° of delay corresponds to one period. Therefore,

t q = d which gives 360∞ T

td =

1 q 1 -52.2∞ = = - 72.5 ms . 3 f 360∞ 2 ¥ 10 360∞

analog MultIplIers

4.10

A multiplier produces an output Vo , which is proportional to the product of two inputs Vx and Vy . That is,

Vo = KVxVy

(4.43) –1

where K is the scaling factor that is usually maintained as (1/10) V . There are various methods available for performing analog multiplication. Five of such techniques, namely, (i) logarithmic summing technique, (ii) pulse height/width modulation technique, (iii) variable transconductance technique, (iv) multiplication using Gilbert cell and (v) multiplication using variable transconductance technique are discussed in the next section. An actual multiplier has its output voltage Vo defined by Vo =

(Vx + j x ) (Vy + j y ) 10 (1 + e )

+ jo

(4.44)

where jx and jy are the offsets associated with signals Vx and Vy , e is the error signal associated with K and jo is the offset voltage of the multiplier output.

Commonly used Terminologies Associated with Multiplier Characteristics Accuracy This specifies the deviation of the actual output from the ideal output, for any combination of X and Y inputs falling within the permissible operating range of the multiplier. Linearity This defines the accuracy of the multiplier. Figure 4.24 shows the response of the output as a function of one input voltage Vx when the other voltage Vy is assumed constant. It represents the maximum percentage deviation from the ideal straight line output. An error surface is formed by plotting the output for different combinations of X and Y inputs. The linearity error can be defined as the maximum absolute deviation of the error surface. This linearity error imposes a lower limit on the multiplier accuracy. Squaring mode accuracy The square-law curve is obtained with both the X and Y inputs connected together and applied with the same input signal. The Fig. 4.24 Linearity of the multiplier maximum deviation of the output voltage from an ideal

Active Filters, Analog Multipliers and Modulators

181

square-law curve expresses the squaring mode accuracy. This is shown in Fig. 4.25. Bandwidth The bandwidth indicates the operating capability of an analog multiplier at higher frequency values. Small signal 3 dB bandwidth defines the frequency fo at which the output reduces by 3 dB from its low frequency value for a constant input voltage. This is identified individually for the X and Y input channels normally. The transconductance bandwidth represents the frequency at which the transconductance of the multiplier drops by 3 dB Fig. 4.25 Squaring mode accuracy of the multiplier of its low frequency value. This characteristic defines the application frequency ranges when used for phase detection or AM detection. Quadrant The quadrant defines the applicability of the circuit for bipolar signals at its inputs. One-quadrant device accepts only positive input signals, the two quadrant device accepts one bipolar signal and one unipolar signal and the four-quadrant device accepts two bipolar signals.

4.10.1 A Simple Multiplier using an Emitter Coupled Transistor Pair A circuit using an emitter coupled pair is shown in Fig. 4.26. The output currents IC1 and IC2 are related to the differential input voltage V1 by IC1 =

and IC2 =

I EE 1 + e -V1 VT I EE 1 + eV1 VT

(4.45)

(4.46)

where VT is the thermal voltage and the base currents have been Fig. 4.26 emitter coupled transistor pair neglected. Combining Eqs (4.45) and (4.46), we have the difference between the two output currents as DIC = IC1 – IC2

DIC

ˆ Ê 1 1 = IEE Á -V1 VT V1 VT ˜ 1+ e ¯ Ë1 + e Ê V ˆ = IEE tanh Á 1 ˜ Ë 2VT ¯

IEE

(4.47)

The dc transfer characteristic of the emitter-coupled pair is shown in Fig. 4.27. It shows that the emitter-coupled pair can be used as a simple multiplier using this configuration. When the differential input voltage V1 2fi Hz For example, an audio signal ranging from dc to 20 kHz could theoretically be reconstructed by taking uniformly spaced samples at a rate of 40,000 samples/second. In practice, the sampling rate is always preferred to be higher than the theoretical minimum value and normally, 3 to 4 times the highest frequency of the signal. Example 4.13 A system employs a 16-bit word for representing the input signal. If the maximum output voltage is set to 2 V, calculate the resolution of the system and its dynamic range. Solution

A 16-bit word represents 216 or 65,536 levels. These levels are equally spaced across the 2 V range. Then, each step is given by

Active Filters, Analog Multipliers and Modulators

195

2 = 30.52 mV 65536 Therefore, the system can resolve voltage changes as low as 30.52 mV. The dynamic range of a system represents the ratio of the largest value obtainable to the smallest value. Therefore, 2 = 65536, i.e. 20 log10 65536 @ 96 dB Dynamic range = 30.52 ¥ 10 - 6 The dynamic range may also be calculated using the formula, Dynamic range ª 6 dB ¥ Number of bits = 6 dB ¥ 16 bits = 96 dB. Step size =

4.13.2

Sample-and-Hold Circuit

Figure 4.44(a) shows a Sample-and-Hold circuit for high speed of operation. The MOS transistor M shown is an analog switch capable of switching by logic levels, such as that from TTL. It alternately connects and disconnects the capacitor C1 to the output of op-amp A1. Diodes D1 and D2 are inverse-parallel connected. They prevent op-amp A1 from getting into saturation when the transistor M is OFF. This makes the operation of the circuit faster. Hence, the output of op-amp A1 will be v o¢ (t) ª vi (t) – 0.7 V when vi (t) < vo (t), and v o¢ (t) ª vi (t) + 0.7 V when vi (t) > vo (t). When transistor M is ON, the op-amps A1 and A2 act as voltage followers. The waveforms shown in Fig. 4.44(b) illustrate the operation of the circuit. The transistor M is alternately switched ON and OFF by the control voltage vs at its gate terminal. Note that the voltage vs is to be higher than the threshold voltage of the FET. When the transistor switch M is ON for a short interval of time, the capacitor C1 quickly charges or discharges to the value of the analog signal at that instant. In other words, when input vi is larger than capacitor voltage vc and the transistor M is OFF, it rapidly charges to the level of vi the instant M switches ON. Similarly, if vc is initially greater than vi, then C1 rapidly discharges to the level of vi when M becomes ON. When M is OFF, only the input bias current of op-amp A2 and the gate – source reverse leakage current of FET are effective in discharging the capacitor. Hence, the sampled voltage is held constant by C1 until the next sampling instant or acquisition time. Figure 4.44(c) shows the sampling or acquisition time t1 and holding time t2. During the sampling time t1, C1 is charged through the FET channel resistance RDS(ON), and the charging time t1 = 5RDS(ON) C1 when the capacitor charges to 0.993 of input voltage. During the hold time t2, the capacitor partially discharges. This is called hold-mode droop. To avoid this, the op-amp A2 must have very low input bias current, the capacitor should have a low leakage dielectric and M must have very low reverse leakage current between its gate and source terminals. The low channel resistance RDS(ON) is desirable for the FET to achieve faster charging and discharging of C1.

Fig. 4.44

(a) Sample-and-hold circuit

196

Linear IC Applications

Fig. 4.44

(b) Signal voltage, control voltage and output voltage waveforms (c) Capacitor voltage waveform

Review Questions 4.1 What is meant by a filter and classify them based on the components used in designing. B

4.2 What is meant by a filter and classify them B based on their frequency response. 4.3 What are the four main types of filters? A 4.4 What do the terms order and poles indicate as C related to filters? 4.5 What type of filter has a constant output response for voltage from dc up to the cut-off B frequency? Where is it employed? 4.6 What type of filter has a constant output response for voltage over a band of frequencies while attenuating all frequencies outside the band? Identify a typical application of such a C filter. 4.7 Define low-pass and high-pass filters with necessary frequency response characteristics. A

4.8 How can you realise a low-pass filter using op-amp? What are the advantages of active A filters? 4.9 Draw a circuit for a first order active highA pass filter. 4.10 First order active LPF can also act as an A integrator (True/False). 4.11 Define passband and stopband of a filter. A 4.12 What is the roll-off rate of first order filter? A

4.13 What are the factors determining the shape of B the transition band? 4.14 What is the influence of the damping factor in the frequency response characteristics of a C filter? Explain with examples. 4.15 What is meant by Butterworth response? A 4.16 Draw the characteristics of first order A Butterworth filter.

Active Filters, Analog Multipliers and Modulators

4.17 Explain  from  first  principles  how  a  second  order Butterworth low-pass filter can be B designed. 4.18 Compare the frequency response characteristics of first order and second order B Butterworth filters. 4.19 It is desired to have an amplifier which has such a response that it gives zero amplification (orminimal level of output) at a frequency of 1 kHz and maximum amplification at all other frequencies. Suggest a circuit with opB amp and explain its operation. A 4.20 Explain a band-reject filter. 4.21 Draw the characteristics of a first order active A notch filter. 4.22 Define an all-pass filter. How can it be justifiably called as phase shift circuits? C 4.23 Design a first order low-pass filter at a cut-off frequency of 2.5 kHz with a passband gain of B 1.5. 4.24 Design a second order Butterworth high-pass active filter with the following specifications: (i) Voltage gain = 2.5 and (ii) Cut-off B frequency = 5 kHz. 4.25 Design a second order low-pass Butterworth filter with a cut-off frequency of 12 kHz and unity gain at low frequency. Also determine the voltage transfer function magnitude in dB C at 15 Hz for the filter. 4.26 Design a second order Butterworth lowpass filter having upper cut-off frequency of B 2.5 kHz. 4.27 Design a first order high-pass filter at a cutoff frequency of 2.5 kHz with a passband gain of 1.5. Also, plot its frequency response. C

4.28 If a bandpass filter has a lower cut-off frequency fL = 200 Hz and a higher cut-off frequency fH = 2000 Hz, find its bandwidth C and the resonant frequency.

197

4.29 Given a bandpass filter with resonant frequency fr of 1 kHz and a bandwidth B of 4 kHz, find its (a) quality factor, (b) lower cutoff frequency and (c) higher cut-off frequency. C

4.30 If a bandpass filter has a resonant frequency of 1200 Hz and a bandwidth of 3000 Hz, find the lower and upper cut-off frequencies. C 4.31 Given a bandpass filter with lower and higher cut-off frequencies of 50 Hz and 60 Hz respectively, find its (a) quality factor, (b) resonant frequency and (c) bandwidth. B 4.32 Design a narrowband bandpass filter using an op-amp. The resonant frequency is 100 Hz B and Q = 2. Assume C = 0.1 m F. 4.33 Design a narrowband bandpass filter with a resonant frequency of 300 Hz and a B bandwidth of 30 Hz. 4.34 Design a wideband bandpass filterwith fL = 200 Hz and fH = 1 kHz and calculate the B value of Q for the filter. 4.35 Design an active bandpass filter for a B passband of 500 Hz with fL= 1 kHz. 4.36 Define the process of sampling. What is its A use? 4.37 Write a note on Shannon’s sampling theorem. A

4.38 Draw a fundamental Sample-and-Hold circuit. What factors contribute to the hold B mode droop in this circuit? 4.39 What are the general applications of analog A multipliers? 4.40 What are the basic characteristic parameters of an analog multiplier? Comment on the performance parameters of a multiplier. B 4.41 Define (i) Linearity, (ii) Accuracy, (iii) Squaring mode accuracy and (iv) Bandwidth as relevant A to the analog multiplier.

198

Linear IC Applications

4.42 Using Eq. (4.44), show that the circuit can perform the multiplication of two analog B input signals.

4.52 Explain how to convert a simple emitter coupled pair into a two quadrant multiplier.

4.43 What is the relevance of the term Quadrant of B Operation as applied to a multiplier? 4.44 What are the one, two and four quadrant multipliers? Briefly explain. Which is C preferred for what applications? 4.45 What are the typical multiplication techniques used for monolithic realisation of C a multiplier? Compare them. 4.46 Explain an emitter-coupled transistor pair for use as a simple multiplier. Why is it called a B modulator? 4.47 Explain the basic Gilbert cell with a neat diagram. How does it overcome the limitations of the emitter-coupled transistor B pair?

4.53 You are given with an analog multiplier. Conceive practical applications and implementation for the desired performance. B Explain briefly. 4.54 Define modulators. How can the multiplier B be used as modulator? 4.55 Draw the circuit of a four quadrant analog multiplier used for frequency multiplication.

4.48 What are the limitations of a simple Gilbert cell? How do you overcome the limitations? C

4.49 Perform the dc analysis of Gilbert multiplier cell. Comment on linearity of the output C obtained from Gilbert multiplier cell. 4.50 Why do you need predistortion circuits in Gilbert analog multiplier and how do you configure a Gilbert multiplier with B predistortion circuits?

C

C

4.56 You are allowed to use only single quadrant multipliers of any numbers as you desire. Explain how a four quadrant multiplier be obtained from the given single quadrant C multipliers. 4.57 Discuss the general features and operation of the double balanced modulator/demodulator A IC LM1496. 4.58 Explain the use of balanced modulator/ demodulator IC LM1496 as a (a) Balanced Modulator (b) Amplitude Modulator (c) Product Detector (d) Double Balanced Mixer (e) Frequency Doubler (f) Phase Detection and FM Detection B

4.51 Derive a circuit arrangement for implementing an inverse hyperbolic tangent function and C explain the operation of the circuit.

Objective-Type Questions 4.1 The active filter networks do not require (a) capacitors (b) resistors A (c) power supplies (d) inductors 4.2 The active RC networks are more sensitive than passive RLC networks. (True/False) B 4.3 Micro miniaturisation is possible in active A RC networks. (True/False)

4.4 A low pass filter allows (a) beyond lower cut-off frequency (b) 0 to higher cut-off frequency (c) the band between lower and upper cutoff frequencies A (d) all frequencies

Active Filters, Analog Multipliers and Modulators

4.5 A high pass filter allows (a) beyond lower cut-off frequency (b) 0 to higher cut-off frequency (c) the band between lower and upper cutoff frequencies A (d) all frequencies 4.6 A bandpass filter allows (a) beyond lower cut-off frequency (b) 0 to higher cut-off frequency (c) the band between lower and upper cutoff frequencies A (d) all frequencies 4.7 A band-reject filter eliminates (a) beyond lower cut-off frequency (b) 0 to higher cut-off frequency (c) the band upto lower and beyond upper cut-off frequencies (d) the band between lower and upper cutA off frequencies 4.8 An active filter employs (a) transistor in its active region (b) operational amplifier (c) MOSFET in its active region (d) none of these

B

4.9 A low pass filter can function as (a) a differentiator (b) an integrator (c) both integrator and differentiator (d) none of these

B

4.10 A high pass filter can function as (a) a differentiator (b) an integrator (c) both integrator and differentiator B (d) none of these 4.11 An all pass filter allows (a) all frequency components greater than a particular frequency (b) all frequency components less than a particular frequency (c) all frequency components A (d) none of these 4.12 The magnitude response of Butterworth filter is given by

(a) | H ( jw )| =

A Êw ˆ 1+ Á c ˜ Ëw¯

(b) | H ( jw )| =

2N

A Êwˆ 1+ Á ˜ Ë wc ¯

(c) | H ( jw )| =

2N

A Ê 1ˆ w +Á ˜ Ë wc ¯

(d) | H ( jw )| =

199

2N

A

C

Ê 1ˆ wc + Á ˜ Ëw ¯

2N

4.13 The gain of a second order Butterworth filter is (a) 1.414 (b) 1.586 A (c) 1.732 (d) 2.108 4.14 It is possible to achieve Q values of IC filters equal to (a) 10 (b) 30 B (c) 100 (d) 60 4.15 The band pass filter with a –40 dB/decade roll-off rate will need (a) first order HPF and first order LPF in cascade (b) first order HPF and second order LPF in cascade (c) second order HPF and first order LPF in cascade (d) second order HPF and second order LPF B in cascade 4.16 The resonant frequency of a bandpass filter is (a) f r =

fH fL

(b) fr = fHfL

(c) f r =

f H /f L

(d) f r =

fH + fL C

4.17 The quality factor Q is determined by fr BW (c) fr ¥ BW (a)

BW fr (d) none of these

(b)

B

200

Linear IC Applications

4.18 If the central frequency is 40 kHz and the lower and higher cutoff frequencies are 30 kHz and 50 kHz, then the Q-factor is (a) 0.5 (b) 2 C (c) 20 (d) 40

4.26 Aliasing error occurs when a signal fi is sampled at a rate _________. (a) 2 fi (b) lower than 2 fi (c) greater than 2 fi (d) none of these

4.19 Notch filter is a (a) wide-band pass filter (b) wide-band reject filter (c) narrow-band pass filter A (d) narrow -band reject filter 4.20 Notch filters are used to nullify the effect of ______ of electrical line noise (a) fundamental frequency (b) second harmonic (c) all harmonics B (d) none of these 4.21 Band-pass filters are easily achievable using a cascade of high-pass and low-pass filters for relatively _____ Q applications (a) low (b) high (c) low and high (d) none of these

4.27 ______________ of a multiplier is formed by plotting the output for different combination B of X and Y inputs.

B

4.22 Order of filter determines (a) shape of the filter response (b) steepness of the attenuation slope (c) minimum number of reactive elements needed to realize the filter B (d) (b) and (c) 4.23 The process of transforming an analog signal into digital representation is called (a) quantization (b) digitizing (c) sampling (d) all of these B 4.24 The minimum sampling rate of an input signal of frequency fi is (a) greater than 2 fi (b) 2 fi (c) less than 2 fi (d) none of these A

4.25 The Nyquist frequency is _____________ the sampling frequency (a) twice (b) greater than A (c) less than (d) one-half

A

4.28 The maximum deviation of the output voltage of a multiplier from an ideal squareB law curve expresses __________. 4.29 The two quadrant device accepts __________ signals. (a) 1 bipolar and 1 unipolar (b) 2 unipolar (c) 2 bipolar B (d) all of these 4.30 An analog multiplier produces an output that is given by (a) KVxVy (b) VxVy (c) Vx + Vy (d) none of these B

4.31 Four-quadrant multiplier can multiply a positive and a negative signal. (True/False) A

4.32 ___________ multiplier cell forms the basis A of most of the balanced multiplier ICs. 4.33 When larger voltage signals are to be multiplied, ___________ function can be used to ____________ the input signals. B 4.34 The predistortion circuits are used in compensating for the _________ transfer characteristic of the basic Gilbert multiplier B cell. 4.35 The scaling factor K of a four-quadrant variable transconductance multiplier is RL 2 RL I1 (a) (b) Rx Ry 2 I1Rx Ry (c)

2 Rx Ry RL I1

(d)

2 RL I1Rx Ry

C

Active Filters, Analog Multipliers and Modulators

201

Answers to Objective-Type Questions 4.1 4.4 4.7 4.10 4.13 4.16 4.19 4.22 4.25 4.28 4.31 4.34

(d) (b) (d) (a) (b) (a) (d) (d) (d) the squaring mode accuracy True inverse hyperbolic tangent

4.2 4.5 4.8 4.11 4.14 4.17 4.20 4.23 4.26 4.29 4.32 4.35

True (a) (b) (c) (c) (a) (a) (d) (b) (a) Gilbert (d)

4.3 4.6 6.9 4.12 4.15 4.18 4.21 4.24 4.27 4.30 4.33

True (c) (b) (b) (d) (b) (a) (b) Error surface (a) a nonlinearity, predistort

Chapter

5 5.1

Timers and Phase Locked Loops

IntroductIon

The 555 timer IC introduced in 1972 by Signetics is an integrated circuit which is one of the most popular ICs ever manufactured. It is presently manufactured by many companies in bipolar and in low-power Complementary Metal Oxide Semiconductor (CMOS) technologies. The IC555 is used in a multitude of timer, pulse generation and oscillator applications. It can be used to generate time delays, as an oscillator and as a flip-flop element. The other advanced derivatives such as IC556, IC7555 and IC7556 are introduced in the chapter. The phase locked loop, universally called as PLL, is a control system which generates an output signal whose phase is related to the phase of an input signal. The phase locked loop can track the input signal frequency, and it can generate output frequency that is a multiple of the input frequency or translated input frequency. The realisation of PLL had been very costly in most industrial and consumer applications. However, the evolution achieved in monolithic IC technology has made the fabrication of IC PLL inexpensive and consequently, the uses, of PLL are constantly expanding in many applications, such as, the satellite communication systems, FM demodulators, stereo demodulators, tone detectors and frequency synthesisers. This chapter uncovers the operating principle of PLL, introduces the reader to the popular IC565 for various applications.

5.2

tImer Ic 555

The 555 integrated circuit timer was first introduced by Signetics Corporation as Type SE555/NE555. It is available in 8-pin circular style TO-99 Can, 8-pin mini-DIP and 14-pin DIP as shown in Fig. 5.1. The 555 IC is widely popular and various manufacturers provide the IC. The IC 556 contains two 555 timers in a 14-pin DIP package and Exar’s XR-2240 contains a 555 timer with a programmable binary counter in a single 16-pin package. The 555 timer can be operated with a dc supply voltage ranging from +5 V to +18 V. This feature makes the IC compatible to TTL/CMOS logic circuits and op-amp based circuits. The IC 555 timer is very versatile and its applications include oscillator, pulse generator, square and ramp wave generator, one-shot multivibrator, safety alarm and timer circuits, traffic light controllers, etc. The 555 timer can provide time delay, ranging from microseconds to hours.

5.2.1

Functional Diagram of the IC 555

Figure 5.2 shows the functional block diagram of 555 IC timer. The positive dc power supply terminal is connected to pin 8(VCC) and negative terminal is connected to pin 1(Gnd). The ground pin acts as a common ground for all voltage references while using the IC. The output (pin 3) can assume a HIGH level (typically 0.5 V less than VCC) or a LOW level (approximately 0.1 V).

Timers and Phase Locked Loops H Package VCC Ground

1

8

Discharge

7

Trigger 2 IC 555 6 Output

3

4 Reset

5

N Package

Threshold

Ground Trigger

1

8

VCC

2

7

Discharge

Output

3

6

Reset

4

Threshold Control voltage

Control voltage

IC 555 555 IC

5

(a) F.N-14 package Gnd 1 NC 2 Trigger 3 Output 4

14 V CC 13 NC 12 Discharge IC 555

NC 5 Reset 6

11 NC 10 Threshold 9 NC

NC 7

8 Control voltage (b)

Fig. 5.1

Fig. 5.2

pin configurations of IC 555 timer

Functional block diagram of IC 555 timer

203

204

Linear IC Applications

Two comparators, namely, upper comparator (UC) and lower comparator (LC) are used in the circuit. Three 5 kW internal resistors provide a potential divider arrangement. It provides a voltage of (2/3)VCC to the (–) terminal of the upper comparator and (1/3)VCC to the (+) input terminal of the lower comparator. A control voltage input terminal (pin 5) accepts a modulation control input voltage applied externally. Pin 5 is connected to ground through a bypassing capacitor of 0.1 mF. It bypasses the noise or ripple from the supply. The (+) input terminal of the UC is called the threshold terminal (pin 6) and the (–) input terminal of the LC is the trigger terminal (pin 2). The operation of the IC can be summarised as shown in Table 5.1. Table 5.1

States of operation of IC 555

Sl. No.

Trigger (pin 2)

Threshold (pin 6)

Output state (pin 3)

Discharge state (pin 7)

1

Below (1/3)VCC

Below (2/3)VCC

High

Open

2

Below (1/3)VCC

Above (2/3)VCC

Last state remains

Last state remains

3

Above (1/3)VCC

Below (2/3)VCC

Last state remains

Last state remains

4

Above (1/3)VCC

Above (2/3)VCC

Low

Ground

The standby (stable) state makes the output Q of flip-flop (FF) HIGH. This makes the output of inverting power amplifier LOW. When a negative going trigger pulse is applied to pin 2, as the negative edge of the 1 trigger passes through VCC, the output of the lower comparator becomes HIGH and it sets the control FF 3 2 making Q = 1 and Q = 0. When the threshold voltage at pin 6 exceeds VCC, the output of upper comparator 3 goes HIGH. This action resets the control FF with Q = 0 and Q = 1. The reset terminal (pin 4) allows the resetting of the timer by grounding the pin 4 or reducing its voltage level below 0.4 V. This makes the output (pin 3) low overriding the operation of lower comparator. When not used, the reset terminal is connected to V CC. Transistor Q2 isolates the reset input from the FF and transistor Q1. The reference voltage Vref is made available internally from VCC. Transistor Q1 acts as a discharge transistor. When output (pin 3) is high, Q1 is OFF making the discharge terminal (pin 7) open. When the output is low, Q1 is forward-biased to ON condition. Then, the Discharge terminal appears as a short circuit to ground.

5.3

monostable operatIon

of

tImer Ic 555

Monostable multivibrator has one stable state and one quasi-stable state. It is also known as monoshot or one-shot multivibrator or uni-vibrator. It remains in its stable state until an input pulse triggers it into its quasi-stable state. It stays in quasi-stable state for a time duration determined by an RC timing circuit. The output returns to its original stable state automatically at the end of the time and stays there until the next trigger pulse is applied. Therefore, a monostable multivibrator cannot generate square-waves on its own like an astable multivibrator. Only external trigger pulses will cause it to generate the rectangular pulses. The functional block diagram and connection diagram of a monostable multivibrator using 555 timer are shown in Fig. 5.3 (a) and (b) respectively. In the standby mode, the control flip-flop FF holds Q1 ON, thus clamping the external timing capacitor C to ground. The output (pin 3) during this time is at ground

Timers and Phase Locked Loops

Trigger

205

Additional pulse has no effect on output

1 VCC 3 2 V 3 CC

Capacitor Voltage vc

0V +VCC

Output

T

0V +VCC

Reset 0V

Discharge

Reset pulse applied +VCC Output after reset pulse applied (c)

Fig. 5.3

V

Monostable multivibrator: (a) Functional diagram (b) Connection diagram (c) timing pulses

206

Linear IC Applications

potential, or LOW. The three 5 kW internal resistors act as voltage dividers providing bias voltages of (2/3)VCC and (1/3)VCC, respectively. Since these two voltages fix the necessary comparator threshold voltages, they aid in determining the timing interval. The lower comparator (LC) is biased at (1/3)VCC and it remains in the standby state as long as the trigger (pin 2) input is held above (1/3)VCC. When triggered by a negative going pulse, the output of the lower comparator goes HIGH setting the flip-flop FF with Q = 1 and Q = 0. This turns the transistor Q1 OFF, and the output goes HIGH (approximately equal to VCC). Since the timing capacitor is now unclamped, the voltage across the capacitor now rises exponentially through R towards VCC with a time constant RC. After a period of time, the capacitor voltage will equal (2/3)VCC and the upper comparator (UC) resets the internal flip-flop. This makes Q = 1 and the transistor Q1 is ON. This in turn discharges the capacitor rapidly to ground potential. As a consequence, the output now returns to the standby state or ground. The timing sequence of 555 monostable multivibrator is shown in Fig. 5.3(c). The circuit triggers only on a negative going pulse, when the level is less than (1/3)VCC. Once triggered, the output will remain HIGH until the set time has elapsed, even if it is triggered again during this interval which is indicated in Fig. 5.3(c). Since the external capacitor voltage charges exponentially from 0 to (2/3)VCC, the voltage across the capacitor vc is given by v c = VCC (1- e - t /RC )

(5.1)

At time t = T, v c = (2/ 3)V CC That is,

2 VCC = VCC(1 – e–T /RC) 3

Ê 1ˆ Therefore, T = –RC ln Á ˜ = 1.1 RC (seconds) Ë 3¯

(5.2)

Figure 5.4 shows a graph of various combinations of R and C necessary to produce a given time delay. Since the charging rate and comparator thresholds are both directly proportional to the supply voltage, the timing interval given by Eq. (5.2) is independent of the supply voltage. For proper monostable operation with the 555 timer, the negative-going trigger pulse width should be kept shorter compared to the desired output pulse width. The values of external timing resistor and capacitor can be determined either from Eq. (5.2) or from the graph given in Fig. 5.4. To prevent mistriggering on positive pulse edges, an R1–C1 combination with a diode D can Fig. 5.4 Graph of rC combinations for different time be connected between pin 2 and pin 8 as shown delays in Fig. 5.5. The value of R1 and C1 should be such that R1C1 is smaller than the required pulse width. During the positive edge of the trigger pulse, the diode D gets forward-biased and it limits the amplitude of the positive spike to 0.7 V, which is less than (1/3)VCC to trigger the lower comparator LC ON.

Timers and Phase Locked Loops

Fig. 5.5

207

Waveshaping circuit to avoid positive pulse triggering

Design a monostable multivibrator using 555 timer for a pulse period of 1 ms.

Example 5.1 Solution

The period of pulse is t = 1.1 RC Letting C = 0.1 mF, –3 1 ¥ 10 = 1.1 ¥ 10–7 R Therefore, R = 8.2 kW

applIcatIons

5.4

of

monostable multIvIbrator

The important applications of monostable multivibrator are (i) Ramp generation, (ii) Frequency division, and (iii) Pulse-width modulation.

5.4.1

Ramp Generation

Linear ramp signal can be generated using the circuit shown in Fig. 5.6(a). The timing capacitor C is charged by constant current source instead of charging by a resistor. The transistor QL forms a constant current source. Assuming that i is the current supplied by a constant current source, the capacitor voltage vc is given by t

1 vc = Ú idt C0

(5.3)

Referring to Fig. 5.6(a) and employing KVL, R1 VCC - VBE = ( b + 1) I B RE R1 + R2

(5.4)

b IB RE = IC RE = iRE where IB and IC are the base and collector currents of transistor QL and b is the current gain in CE mode. From Eq. (5.4), i=

R1VCC - VBE ( R1 + R2 ) RE ( R1 + R2 )

(5.5)

208

Linear IC Applications

Fig. 5.6

ramp Generator: (a) Circuit diagram (b) Waveforms

Substituting Eq. (5.5) in Eq. (5.3), we get vc =

Therefore, vc =

1 C

t

Ú

R1VCC - VBE ( R1 + R2 )

0

RE ( R1 + R2 )

R1VCC - VBE ( R1 + R2 ) CRE ( R1 + R2 )

dt

¥t

(5.6)

At the instant of time t = T, v c becomes (2/3)VCC. Then, (2 / 3)V CC =

R1VCC - VBE ( R1 + R2 ) CRE ( R1 + R2 )

¥T

That is, the time period T of linear ramp generator is given by T=

(2 /3)VCC CRE ( R1 + R2 ) R1VCC - VBE ( R1 + R2 )

(5.7)

When the capacitor voltage v c just goes above (2/3)VCC the upper comparator triggers, thereby resetting the flip-flop. This discharges the capacitor C, and the output remains at zero until another trigger pulse is applied. The various waveforms of the circuit are shown in Fig. 5.6(b).

5.4.2

Frequency Divider

The monostable multivibrator, when continuously triggered by a square-wave signal can be used as a frequency divider, if the timing interval T of the monostable multivibrator is designed to be longer than the period of the triggering square-wave signal. The one-shot is triggered by the first negative edge of the

Timers and Phase Locked Loops

square-wave input. During the second negative edge of the square-wave, the output of monostable multivibrator remains HIGH. However, during the third negative edge of the square-wave signal, the mono-shot once again triggers ON. In this manner, the output pulse can be made any integral fraction of the input triggering square-wave signal. The waveform of the input square-wave and output of monoshot are shown in Fig. 5.7 for a frequency divided-by-two operation.

5.4.3

Input trigger at pin 2 Output triggers

No change

209

Output triggers again

VCC 3 t Output

T

t

Pulse-width Modulation Fig. 5.7

the input and output waveforms of frequency divider circuit

The monostable multivibrator, when applied with a modulating control input signal at pin 5 can act as a pulse width modulator. The circuit of the mono-shot with modulating input signal at pin 5 is shown in Fig. 5.8(a). The series of trigger pulses at pin 2 generates a series of output pulses. The duration of the output pulses are determined by the triggering of the upper comparator, which in turn depends on the modulating signal input at pin 5. This is due to the fact that, the modulating signal is superimposed upon the voltage (2/3)VCC obtained through voltage divider circuit. The threshold level of the upper comparator thus changes and the output pulse modulation occurs. The modulating control input signal and the output waveforms are shown in Fig. 5.8(b).

Fig. 5.8 pulse width modulator using monostable multivibrator: (a) Circuit diagram (b) Input and output waveforms

It can be seen that, the frequency of the output remains the same, with the duty cycle of the output varying in response to the modulating input.

210

5.5

Linear IC Applications

astable operatIon

of the

tImer Ic 555

The functional diagram of the IC 555 connected for astable operation is shown in Fig. 5.9. The device connection diagram with external components is shown in Fig. 5.10. Resistors RA and RB form the timing resistors. The discharge (pin 7) terminal is connected to the junction of RA and RB. Threshold (pin 6) and trigger (pin 2) terminals are connected to the v c terminal, and control (pin 5) terminal is by-passed to ground through a 0.01 mF capacitor.

Fig. 5.9

Functional diagram of astable multivibrator using IC 555 timer

Fig. 5.10

Connection diagram of astable multivibrator

When the power supply VCC is connected to the circuit, the capacitor C charges towards VCC. The charging rate is determined by the time constant (RA + RB)C. During this period, the output (pin 3) is high, since R = 0, S = 1 and thus Q = 0. When the capacitor voltage reaches and rises just above (2/3)VCC, the upper comparator triggers, and resets the flip-flop (FF). This makes internal discharge transistor Q1 ON, resulting in the capacitor

Timers and Phase Locked Loops

211

C discharging towards ground through the resistance RB and Q1. The time constant for discharging is RBC. Since current can also flow through RA into Q1, the resistance RA and RB are to be made large enough to limit this current. A maximum current of 0.2 A can be allowed to flow through the ON transistor Q1. When the timing capacitor C discharges, as it reaches and goes just less than (1/3)VCC, the lower comparator gets triggered. This sets the flip-flop making Q = 0. This results in unclamping the external timing capacitor by switching Q1 OFF. This cycle of charging to (2/3)VCC and discharging to (1/3)VCC repeats. Figure 5.11 shows the timing sequence and capacitor voltage waveform during the astable operation. The output (pin 3) is high during the internal charging of the capacitor from (1/ 3)V CC to (2/3)VCC. The capacitor voltage vc for a low pass RC circuit is given by v c = VCC(1 – et/RC)

TON TOFF

Fig. 5.11

the timing waveform of astable multivibrator

Here, we assume a step input of VCC volt. If t1 is the time taken by the capacitor to charge from 0 to (2 / 3)VCC, then (2 / 3)VCC = VCC(1 – e–t1/RC) Therefore,

t1 = 1.098 RC

If t2 is the time taken by the capacitor to charge from 0 to (1 / 3)VCC, then (1 / 3)VCC = VCC(1 – e–t2/RC) Therefore, t2 = 0.405 RC Then, the time taken by the capacitor to charge from (1 /3)VCC to (2 / 3)VCC is given by tON = t1 – t2 = 1.098 RC – 0.405 RC ª 0.693 RC Thus, tON for the circuit is tON = 0.693(RA + RB)C where RA and RB form the charging path. The output is in LOW level during the period of discharging from (2 / 3)VCC to (1/3)VCC and the voltage across the capacitor in such a condition is expressed by (1 / 3)VCC = (2/3)VCCe –t/RC Hence, t = 0.693 RC Therefore, for the astable circuit, tOFF = 0.693 RBC where RB forms the discharging path for the current.

212

Linear IC Applications

Thus, total time

T = TON + TOFF or T = 0.693(RA + 2RB)C

and

f=

1 1.45 = T ( RA + 2 RB ) C

Figure 5.12 shows the various combinations of (RA + 2RB) and C needed to obtain a stable output frequency. The duty cycle D of any pulse generator circuit is D=

T high (ON) interval ¥ 100% = ON ¥ 100% period T

D=

RA + RB ¥ 100% RA + 2 RB

Capacitance in mF

1 MW

0.1 MW

10 kW

1 kW

10 MW 0.1 (RA + 2RB) 0.01

0.001 1

10

100

1k

10 k

100 k

Astable Frequency in Hz

Fig. 5.12

RA, RB and RC combinations for different frequencies

Defining the duty cycle in this manner always makes D greater than 50% since TON > TOFF. An alternative way of defining the duty cycle for this circuit is D=

TOFF RB ¥ 100% = ¥ 100% T RA + 2 RB

It can be noted that the later definition takes into account the time when Q1 is ON as TON. The resulting duty cycle value is less than 50%. Example 5.2

Determine the frequency of oscillation if the duty cycle D = 20% and the ON period

T1 = 1 ms. Solution

The duty cycle is

Therefore,

D=

TON ¥ 100% TON + TOFF

20 1 ¥ 10-3 = 100 TON + TOFF

Timers and Phase Locked Loops

Here the total period,

T = TON + TOFF = 5 ms

Therefore, the frequency of oscillation

f=

213

1 = 200 Hz. T

Design an astable multivibrator using 555 timer for a frequency of 1 kHz and a duty cycle of 70%. Assume C = 0.1 mF. Example 5.3

Solution

The ON period TON = 0.693(RA + RB)C1. Similarly, the OFF period TOFF = 0.693 RB C1 The total period T is given by T = TON + TOFF = 0.693(RA + 2RB)C1 Therefore, the duty cycle D is given by D=

0.693 ( RA + RB ) C1 TON T R + RB = ON = = A TON + TOFF T 0.693 ( RA + 2 RB ) C1 RA + 2 RB

D=

RA + RB 7 = RA + 2 RB 10

RA =

4 RB 3

Given D = 0.7, we have

Therefore,

10 RB ¥ 10 – 7 3 Substituting the value of T and solving, we get The period of oscillation T = 0.693 ¥

1 ¥ 104 = 4.7 kW 10 0.693 ¥ 3 4 RA = ¥ 4700 ª 6.8 kW. 3

RB =

Therefore,

5.6

applIcatIons

of

astable multIvIbrator

The important applications of the astable multivibrator are FSK generator, Pulse position modulator and Schmitt trigger.

5.6.1

FSK Generator

A timer IC 555 connected for FSK (Frequency-Shift-Keying) generation is shown in Fig. 5.13. The FSK method transmits data by identifying the logic 0 and 1 by means of two preset frequencies. The digital data input frequency is normally 150 Hz. Here, when the input is HIGH, QM is OFF. This makes the timer work in normal astable mode with the preset frequency defined by f1 =

1.45 R + ( A 2 RB ) C

214

Linear IC Applications

Fig. 5.13

FSK generator connection diagram

When the input goes LOW, QM is ON and it connects resistance RC across RA. The effective resistance RA || RC in series with RB now forms the charging path. Therefore, the output frequency f2 is 1.45 f2 = RA RC + 2 RB C

(

)

Example 5.4 The teletypewriter uses the frequencies 1070 Hz and 1270 Hz for its MODEM. Design the FSK generator circuit shown in Fig. 5.13 for this application. Solution

The components RA, RB and C can be selected so that f1 = 1070 Hz. 1.45 That is, f 1 = 1070 = ( RA + 2 RB ) C Assuming We know that, Then, for output frequency,

RA = 50 kW and C = 0.01 mF, RB = 42.77 kW 1.45 f2 = ( RA  RC + 2 RB ) C f2 = 1270 Hz 1270 =

Thus,

5.6.2

1.45 (50 ¥ 10 || RC + 2 (42.77 ¥ 103 )) ¥ 0.01 ¥ 10 - 6

RC ª 76 W

3

(Standard value)

Pulse-position Modulator

The timer IC 555 connected for pulse-position modulation is shown in Fig. 5.14(a). The modulating signal is applied to the modulating control input (pin 5). This changes the threshold voltage condition for the upper comparator. Therefore, the output pulse position varies due to the modulating signal. Figure 5.14(b) shows

Timers and Phase Locked Loops

215

the output waveform obtained for an input triangular wave modulating signal. It can be seen that the output frequency changes with respect to the modulating signal leading to pulse position modulation.

Fig. 5.14

5.6.3

pulse-position modulator using astable operation of IC timer: (a) the connection diagram (b) Modulating signal and output waveforms

Schmitt Trigger

The timer IC 555 can be used to function as a Schmitt trigger with variable threshold voltage levels. The use of timer IC 555 connected as a Schmitt trigger circuit in astable mode of operation is shown in Fig. 5.15(a). The two internal comparator inputs (pins 2 and 6) are connected together and externally biased with a voltage VCC /2 through R1 and R2 potential divider network. Since the voltage at pins 6 and 2 will trigger the upper comparator (UC) at (2/3)VCC and the lower comparator (LC) at (1/3)VCC , the bias provided by R1 and R2 is centered within these two threshold levels. The input and output waveforms are shown in Fig. 5.15(b).

Fig. 5.15

Schmitt trigger using IC 555 timer: (a) Connection diagram, (b) Input and output waveforms

216

Linear IC Applications

When a sine wave input of sufficient amplitude (vi), where vi is greater than [(2/3)VCC – (1/3)VCC], is applied to the circuit, it causes the internal flip-flop to alternatively Set and Reset generating a square wave output. Unlike a conventional multivibrator type of square wave generator that divides the input frequency by 2, the main advantage of Schmitt trigger is that it simply converts the sine-wave signal into square-wave signal of the same frequency. Hence, this circuit can be used as a wave shaper.

5.7

IntroductIon

to

pll

The phase locked loop is a closed loop feedback system, whose output frequency and phase are in lock with the frequency and phase of the input signal. In analogue TV receivers since late 1930s, the phase locked loop horizontal and vertical sweep circuits are locked to the synchronization pulses of the broadcast signal. When Signetics introduced the monolithic integrated circuit NE565 in 1969, which were the complete phase locked loop on a single chip, applications for the technique multiplied. The PLL is an important building block of a linear system, which can detect the phases of two signals and reduce the difference in the presence of a phase difference. The PLL mechanisms can be implemented as either analogue or digital circuits. Both implementations use the same basic structure involving the phase detector, filter, error amplifier and voltage controlled oscillator. The analogue and digital PLL circuits include the four basic elements in their own analogue or digital forms. This chapter presents the analogue PLL to the reader. The availability of IC565 as an integrated phase locked loop provides a complete phase locked loop building block, around which carious application circuits can be developed. These PLLs are widely used in radio, telecommunications, computers and other electronic applications. The IC565 can be used to demodulate a signal, recover and retrieve a signal from a noisy communication channel, produce a stable frequency which is a multiple of the input frequency, or having translated from its original frequency. It is also widely used in distributing precisely timed clock pulses in digital systems such as microprocessors.

5.8

block schematIc

and operatIon of the

pll

The basic block diagram of a phase locked loop is shown in Fig. 5.16. The main elements of the PLL are a phase detector/comparator, a low-pass filter, an error amplifier (A) and a voltage controlled oscillator (VCO). The phase detector is fundamentally a multiplier, which generates the sum and difference of two input signals.

Fig. 5.16

Basic block diagram of pLL

The free running frequency fo of the VCO is determined by an externally connected resistor and a timing capacitor. When the loop is locked, the frequency fo is directly proportional to an externally applied voltage vc, called the dc control voltage. When an input periodic signal vi of frequency fi and VCO output signal vo

Timers and Phase Locked Loops

217

of frequency fo are applied to the PLL, the phase detector produces a dc or low frequency signal ve which is proportional to the phase difference between the input signal vi and the VCO output signal vo. When the phase sensitive signal from the phase detector is passed through the low-pass filter F(s), the high frequency sum component is filtered out. The low frequency difference component passes out of the filter and then amplified by the error amplifier A. This amplified signal is applied to the input of VCO as control voltage vc, which changes the VCO frequency fo in such a way that the difference between fo and fi is reduced. If the two frequencies are brought almost identical by this feedback action, then the circuit is said to be locked. Once the lock is achieved, the VCO frequency fo becomes equal to the input signal frequency fi with a finite phase difference f.

Process of Capture It is an important aspect of PLL, by which the loop achieves the condition of being in-lock with a signal from a free-running and unlocked condition. In the unlocked condition of the PLL, the VCO operates at a frequency fc, called centre frequency or free running frequency. This corresponds to an applied voltage of 0 V dc at its control input. The capture process is inherently non-linear and starts occurring as described below. Let us assume that the feedback loop of the PLL is initially open between the loop-filter and VCO control input. An input signal of frequency fi , which is assumed to be closer to the VCO centre frequency fc applied to the input of the phase detector. The phase detector is usually an analog multiplier that multiplies the two sinusoids together, and it produces the sum and difference of the two signals at its output. Since the high frequency sum component is filtered out by the low-pass filter, the output of the LPF is a sinusoid, whose frequency is equal to the difference between the VCO centre frequency fc and incoming signal frequency fi . Considering that the loop is suddenly closed, the difference frequency sinusoid is applied to the VCO input as the control voltage vc . Thus, this will make the VCO frequency fo , a sinusoidal function of time. Therefore, it alternately moves closer and farther away from fi . The output frequency of the phase detector, being the difference between fo and fi, moves to a higher frequency when fo moves away from fi, and moves to a lower frequency when fo moves closer to fi. This fact is reflected in the phase detector output having an asymmetrical wave shape during the capture process as shown in Fig. 5.17. This asymmetry in the waveform produces a dc component in the phase detector output. This dc component shifts the VCO frequency fo towards fi and the frequency difference gradually diminishes. When the loop is locked, the frequency difference becomes zero, and a dc voltage remains at the loop-filter output. ve

Free running dc output dc output in locked condition

t Loop closed at this point

Fig. 5.17

Output of phase detector during capture process

The low-pass loop-filter filters out the difference frequency components resulting from interfering signals, which are far away from the centre frequency. It also acts as a memory for the loop, when the lock is momentarily

218

Linear IC Applications

lost due to a large interfering transient signal. Therefore, the capture-range and pull-in time are dependent on the amount of gain in the loop and the bandwidth of the filter. The signal will be out of capture range when the beat frequency is too high due to the VCO frequency which is far away from the centre frequency. Once lock is achieved, the VCO can track the signal well beyond the capture-range. Reducing the bandwidth of the filter thus improves the rejectivity of out-of-band signals. However, it reduces the capture range, the pull-in time increases and loop phase margin become less. The capture range of a PLL is defined as the range of input frequencies around the centre frequency within which the loop can get locked from an unlocked condition. The pull-in time is the total time required for the loop to get captured with the input signal. An important feature of PLL is its ability to suppress the noise such as those superimposed on the input signal and the noise generated by the VCO.

Closed Loop Analysis of PLL To study the closed loop analysis of PLL, a more detailed block diagram is used as shown in Fig. 5.18. Assume that the PLL is initially in locked condition. Also assume that the gain of the phase detector is Kd Volt/rad of phase difference, the transfer function of the loop-filter is F(s) and the gain in the forward loop is A. The input sinusoidal signal vi is represented by vi = Vp sin (w t + qi)

(5.8)

Fig. 5.18

Detailed block diagram of pLL

If the phase shift of the signal at the VCO output is qOSC, then the average value of the output of the phase detector is ve = Kd (qi – qOSC)

(5.9)

where qi and qOSC are phase shifts with respect to an arbitrarily assumed reference. The phase of the signal at the output of VCO as a function of time is equal to the integral of the VCO output frequency, and it can be expressed as d q OSC (t ) dt

wOSC (t) = t

Thus, qOSC (t) = Ú w OSC (t ) dt + q OSC 0

t =0

Timers and Phase Locked Loops

219

Therefore, the integral component is represented as 1/s inside the VCO block of Fig. 5.18. The oscillator frequency wOSC and the dc control voltage vc are actually related by wOSC = wc + Ko vc

(5.10)

where wc is the centre or free-running angular frequency that results when vc = 0 and Ko is the VCO gain in rad/s per volt. Then, the closed-loop transfer function of the PLL becomes Vc ( s ) = qi (s) =

K d F (s) A 1 + K d A F ( s)

Ko s

s K d F (s) A s + K d Ko A F (s)

(5.11)

To study the response of the loop to frequency variations at the input rather than phase, the above equation can be represented as Vc ( s ) V (s) K d F (s) A = = c w i ( s) s qi ( s) s + K d Ko A F ( s)

(5.12)

since wi = dqi /dt and wi (s) = sqi (s). Considering F(s) = 1 with the loop having a first order low-pass frequency response, we have Vc ( s ) Kv 1 ¥ = w i (s) s + Kv Ko

(5.13)

where Kv the loop bandwidth is given by Kv = Ko Kd A. Then, the loop bandwidth Kv, is the effective bandwidth, and the loop and capture ranges are very much dependent on Kv. If Kv decreases, the capture time rises, and the capture-range reduces. Therefore, the property of interference rejection improves.

Second Order PLL The first order loop without loop-filter has several limitations such as (i) both the sum and difference frequency components are fed to the output from the phase detector and (ii) all out-of-band interfering signals from the input will appear shifted in frequency at the output. Therefore, a loop-filter is highly desirable in applications where interfering signals are present. The most common configuration of monolithic PLL is the second-order loop with a loop-filter F(s) of a simple single-pole, lowpass filter realised with a resistor R and a capacitor C as shown in Fig. 5.19. Then, F (s) = where w =

1 1 = 1 + s /w 1 + st

1 1 = . RC t

R

C

Fig. 5.19

Single-pole loopfilter (lag filter)

(5.14)

220

Linear IC Applications

The resulting block diagram of the second order PLL using single-pole loop-filter is shown in Fig. 5.20. The various dynamic performance requirements of PLL are achieved by the use of different types of filters. vi , qi

+

ve Kd

F(s) = (1 + s/w)–1

vc A

– vo, qo Ko/s

Fig. 5.20

Block diagram of second-order pLL using single-pole loop filter

Loop Lock-range and Capture-range The loop lock-range is represented as the range of frequencies about wo for which the PLL maintains the relationship wi = wOSC. If the phase detector can determine the phase difference between qi and qOSC over a ±p/2 range, then the lock-range is defined as wL = ± D w OSC = K d A K o (± p / 2) = ±KV (p / 2)

(5.15)

The capture-range is the range of input frequencies within which an initially unlocked loop will get locked 1 , then the with an input signal. When F(s) = 1, the capture-range equals the lock-range. If F ( s ) = (1 + s /w i ) capture-range is smaller than the lock-range. The lock-range and capture-range for such a loop are shown in Fig. 5.21.

Fig. 5.21

Lock and capture processes of pLL

Timers and Phase Locked Loops

5.9

prIncIple

and

descrIptIon

of IndIvIdual

221

blocks

The main reason that the PLL has been widely used as an integrated system component is its feasibility of getting fabricated on a single chip for all the individual PLL components. The various component blocks of PLL are discussed in this section.

5.9.1

Phase Detector/Phase Comparator

The analog phase detector realised by using an electronic switch is shown in Figs. 5.22(a) and (b). Assuming that the signal from VCO operates the electronic switch, the input sinusoid vi is chopped by the VCO frequency. The input sinusoid and the VCO output square wave produce different values of filtered error voltages with respect to various values of phase error ve, which is shown as cross-hatched area in the waveform of Fig. 5.22(b). The output of the phase detector when passed through the filter gives out an average error signal shown as dotted line. The error voltage is zero when the phase difference between the two inputs equals 90°. The error voltage is positive for a phase difference of 0° and negative for a phase difference of 180°. In a PLL system configured by this type of phase detector, the PLL achieves a perfect lock when VCO output is in phase quadrature or 90° out of phase with the input. VCO Output ve Positive error voltage

0°

ve Zero error voltage

90° Switch Output

Input signal vi

ve

Negative error voltage

180° Drive from VCO (a) Electronic switch arrangement

Fig. 5.22

(b) Typical waveforms

analog phase detector using electronic switch

Considering the input signal vi = Vi sin wi t and VCO output vo = Vo sin (wot + f), the phase detector output ve becomes ve = K vi vo = K Vi Vo sin (w i t ) sin (w o t + f )

222

Linear IC Applications

where K is the gain of the phase comparator and f is the phase difference between input signal vi and VCO output vo. Then, KViVo (cos (w i t - w o t - f ) - cos (w i t + w o t + f )) 2 When locked, wi = wo ve =

KViVo (cos(- f ) - cos( 2 w o t + f )) (5.16) 2 The double frequency term is eliminated by low-pass filter and the dc error voltage is due to the term cos f. It can be observed that when f = 90∞, perfect lock is achieved and hence the error voltage ve = 0. From the above equation, it is clear that the output error voltage ve is dependent on (i) the input signal amplitude Vi, which makes the phase detector gain and loop gain also dependent on Vi (ii) cos f, that makes the response non-linear. Hence, ve =

Phase Detector Using Gilbert Multiplier Cell The problem of non-linearity is eliminated in the Gilbert multiplier circuit shown in Fig. 5.23(a). The input signal vi is applied to the differential pair Q1 – Q2. The VCO output vo is connected to the pairs Q3 – Q4 and Q5 – Q6 which act as Single-Pole Double-Throw (SPDT) switches. It is assumed that both the phase detector inputs vi and vo have large amplitudes and that all the transistors behave like switches. vi

f 2p

p

3p

wot

4p

vo

p

2p

3p

4p

5p

wot

Output voltage ve f +IEERC A2 –IEERC

Fig. 5.23

(a) analog phase detector using Gilbert multiplier cell

Fig. 5.23

A1

p

2p

3p

4p

5p

w ot

(b) typical input and output waveforms of the analog phase detector

The typical input and output waveforms of the analog phase detector using Gilbert multiplier cell is shown in Fig. 5.23(b). During the interval from 0 to (p – f), both vi and vo are high. Then, the transistors Q1 and Q3 are ON and current IEE flows through Q3 and Q1 providing an output voltage ve = – IEE RC. During the period from (p – f) to p, when vi is HIGH and vo is LOW, transistors Q1 and Q4 are ON resulting in an output voltage, ve = IEE RC as shown in the waveform of Fig. 5.23(c).

Timers and Phase Locked Loops

Fig. 5.23

223

(c) phase detector output ve versus the phase difference f

The average value or the dc component found from the area A1 and A2 of the waveform of ve is given by ve = -

1 [ A1 - A2 ] p

È I R (p - f ) I EE RC f ˘ = - Í EE C ˙ p p Î ˚ Ê 2f ˆ = I EE RC Á - 1˜ Ëp ¯ =

2 I EE RC p

pˆ Ê ÁË f - ˜¯ 2

pˆ Ê = Kf Á f - ˜ Ë 2¯ where the phase-angle to voltage conversion ratio Kf = is shown in Fig. 5.23(c).

(5.17) 2I EE RC . The linear relationship between ve and f p

5.9.2 Voltage Controlled Oscillator (VCO) The generation of signals is a basic requirement for a wide variety of applications. Hence, a number of manufacturers fabricate a selection of integrated circuit oscillators and function generators on single chips. Two of the popular ICs are the voltage controlled oscillator and phase locked loop ICs. The voltage controlled oscillator (VCO) is an oscillator whose oscillating frequency varies in response to a control voltage vc. It is designed to produce fo = K vc, where vc > 0 and K is defined as the sensitivity of VCO in rad/volt. The VCO being the most important building block of a monolithic PLL, its desirable properties are: (i) Linearity in voltage-to-frequency conversion (ii) Frequency stability against temperature changes and drift characteristics (iii) High operating frequency and wide tracking range of frequencies and (iv) High modulation sensitivity Ko and ease of tuning. An emitter coupled multivibrator is shown in Fig. 5.24(a). Let us consider that initially Q1 is OFF and Q2 is ON as shown in Fig. 5.24(b). The drop across resistor R2 is assumed large enough to turn the diode D2 ON. Then, the base of Q4 is one diode drop less than VCC, and the emitter of Q4 and the base of Q1 are two diode drops less than VCC. Since Q1 is OFF, Q3 has its base at VCC and its emitter at one diode drop below VCC.

224

Linear IC Applications

(a)

Fig. 5.24

(b)

(a) Voltage-controlled, emitter-coupled multivibrator circuit (b) equivalent circuit during one half-cycle

The current I1 now charges the capacitor C with emitter of Q1 becoming more negative than that of Q2. The transistor Q1 will be ON when its emitter voltage becomes equal to three diode drops below VCC, and the resulting collector current of Q1 due to voltage drop across resistor R1 turns D1 ON. As a result, the base voltage of Q3 moves in the negative direction by one diode drop. Therefore, the base voltage of Q2 also moves in the negative direction by one diode drop. The transistor Q2 will now be turned OFF. Then, the current I1 charges the capacitor voltage in the opposite direction for an amount of two diode drops and hence Q2 will be switched ON again. Thus the cycle repeats. As the circuit is symmetrical, the time required to charge the capacitor is half of the time period. That is, T Q C DV 2CVBE (on ) = = = 2 I1 I1 I1 Thus, the frequency of oscillation becomes f=

I1 1 = T 4CVBE (on )

(5.18)

The voltage waveforms at various nodes of the circuit are shown in Fig. 5.24(c). This emitter-coupled VCO is non-saturating and the voltage swings within the circuit are maintained small. Therefore, the circuit operates up to 100 MHz for typical integrated circuit environments. One of the most commonly used VCO is NE/SE566.

Timers and Phase Locked Loops

225

Voltage at base of Q2 (VB2)

VCC VCC

Q2 on

VCC 0.6 1.2

Q1 on

t Voltage at emitter of Q2 (VE2) VCC VCC

1.2

VCC

.8 t Capacitor voltage (Vc) +0.6 t

Vo VCC VCC

Q2 on Q1 on

0.6

t

Fig. 5.24

(c) Voltage waveforms at various nodes

5.9.3 Applications of IC Voltage Controlled Oscillator NE/SE566 The pin configuration and the basic block diagram of IC 566 VCO are shown in Figs. 5.25(a) and (b) respectively. The frequency of oscillation is determined by an externally connected resistor R1 and a capacitor C1. The control voltage or the modulating input vc is applied at the control terminal (pin 5) as shown in Fig. 5.25(c). The triangular voltage obtained at pin 4 is shown in Fig. 5.25(d). It is generated by alternately charging the capacitor C1 by one current source, and discharging it linearly through another current source. The amount of charge and discharge voltage swing is determined by the Schmitt trigger. The Schmitt trigger also provides the square-wave output at pin 3 through the power amplifier A3 and the triangular output is available at pin 4 from the buffer amplifier A1.

Operation of VCO The output voltage swing of the Schmitt trigger is set to the levels VCC and 0.5VCC. Referring to Fig. 5.25(b), if Ra = Rb in the positive feedback path, the voltage at the non-inverting terminal of op-amp A2 swings from 0.5VCC to 0.25VCC. During charging of C1, when the voltage across C1 just exceeds 0.5VCC, the Schmitt

226

Linear IC Applications

trigger switches to LOW (0.5VCC) and the capacitor starts discharging. When the voltage across C1 reduces to 0.25VCC, the Schmitt trigger switches to HIGH (VCC) and C1 starts charging. By maintaining the source current and sink current of the two current sources equal, a uniform triangular voltage with equal positive and negative slopes is obtained at pin 4. The square-wave output of Schmitt trigger, inverted and buffered is available at pin 3. The waveforms at the output pins 3 and 4 are shown in Fig. 5.25(d).

Ground

1

NC

2

Square wave output Triangular wave output

3

8 +VCC NE/SE566 VCO

7 C1 6 R1 Modulation 5 input

4 (a) Pin diagram

Fig. 5.25

Voltage-controlled oscillator

Timers and Phase Locked Loops

227

Calculation of the Free-running Frequency fo of VCO The voltage change across the capacitor C1 is DV = 0.25VCC. Since constant current sources are used, the rate of change of voltage across the capacitor is given by i DV = Dt C1 i.e. or

0.25VCC i = Dt C1

0.25VCC C1 i The time period T of the triangular waveform is 2Dt. Therefore, the frequency of oscillation fo is 1 1 i fo = = = T 2 Dt 0.5VCC C1

and

Dt =

i =

Thus, fo =

VCC - vc , R1

(5.19)

(5.20)

where vc is the voltage at pin 5.

2(VCC - vc ) C1R1VCC

(5.21)

Therefore, output frequency of VCO can be varied by (i) the external resistor R1, (ii) the external capacitor C1, or (iii) the control voltage vc applied at pin 5. Figure 5.25(c) shows a typical connection diagram for a VCO with modulating input applied at pin 5. The voltage vc at pin 5 is set by the voltage divider circuit consisting 7 of R2 and R3. If vc is initially set to VCC , then 8 2(VCC - (7 / 8) VCC ) 1 (5.22) fo = = C1 R1 VCC 4 R1C1

Voltage-to-frequency Conversion Factor

Df o , where Dvc is the change in Dvc modulating signal required to produce a corresponding shift D fo in frequency. Assuming the centre frequency is fo and the new frequency is f1 Df = f1 – fo

The voltage-to-frequency conversion factor is determined by Kv =

2(VCC - vc + Dvc ) 2(VCC - vc ) C1R1VCC C1R1VCC 2 Dvc = C1 R1VCC Df 2 Therefore, = Kv = Dvc C1 R1 VCC 1 , the above equation becomes Since fo = 4 R1C1 8 fo Kv = VCC =

(5.23)

228

Linear IC Applications

The triangular and square-waveforms are buffered so that their output impedance is 50 W, and the typical amplitude swing of the triangular wave is 2.4 V and that of the square-wave is 5.4 V. A low value capacitor of 0.001 mF is normally connected between pins 5 and 6 to eliminate any possible oscillations produced in the current sources. NE/SE566 is employed for the frequency range of 500 KHz to 1 MHz, and MC4324/4024 and MC1648 are employed for higher frequency ranges beyond 1 MHz. Example 5.5 Determine the change in dc control voltage vc during lock, if input signal frequency fs = 20 kHz, the free running frequency is 21 kHz and the V/F transfer coefficient of VCO is 4 kHz/V. Solution

The VCO frequency is given by

Df 21 ¥ 103 - 20 ¥ 103 = Kv = Dvc Dvc

1000 = 4000 Hz/V Dvc 1000 Therefore, the change in dc control voltage Dvc = = 0.25 V. 4000 or

Example 5.6 For the VCO circuit shown in Fig. 5.25(c), assume R2 = 2.2 kW, R1 = R3 = 15 kW and C1 = 0.001 mF. Assume VCC = 12 V. Determine (a) the output frequency and (b) the change in output frequency if modulating input vc is varied from 7 V to 8 V. Solution

(a) As shown in Fig. 5.25(c), R2 and R3 form a potential divider. R3 15 ¥ 103 Therefore, vc = VCC ¥ = 12 ¥ = 10.465 � R2 + R3 (2.2 + 15) ¥ 103 Therefore, the output frequency is fo = (b) For vc = 7 V, fo = For vc = 8 V,

2 (VCC - vc ) 2 (12 - 10.465) = = 17.06 kHz C1R1VCC 0.001 ¥ 10-6 ¥ 15 ¥ 103 ¥ 12 2 (VCC - vc )

=

C1R1VCC 2 (VCC - vc )

2 (12 - 7 )

0.001 ¥ 10- 6 ¥ 15 ¥ 103 ¥ 12

= 55.556 kHz

2 (12 - 8)

= 44.444 kHz 0.001 ¥ 10- 6 ¥ 15 ¥ 103 ¥ 12 Hence, the change in output frequency = (55.556 – 44.444) 103 = 11.112 kHz. fo =

5.9.4

=

C1R1VCC

Low-Pass Filter

The main function of the low-pass filter in PLL is to remove the high frequency components generated in the output of the phase detector. This filter is also used to eliminate high frequency noise signals and to control the dynamic characteristics such as the capture and lock ranges, bandwidth and transient response of the PLL. If the bandwidth of the filter is reduced, its response time increases at the cost of reduced capture range. The filter also serves another important purpose by acting as a short time memory when momentary losses of signal occur, with the dc voltage on the capacitor continuing to shift the frequency of VCO until the signal is picked up again.

Timers and Phase Locked Loops

229

The loop-filter employed in PLL may be one of the three types shown in Figs. 5.26(a), (b) and (c). An amplifier is generally added for the passive filters shown in Figs. 5.26(a) and (b). The active filter shown in Fig. 5.26(c) includes gain in its design.

Fig. 5.26

5.10

Low-pass Filters (a) and (b) passive filters and (c) active filter

lm565 pll

The first practical monolithic PLLs developed were 560/561/562 series. Some of the important monolithic PLLs are the SE/NE560 series from Signetics and the LM560 series from National Semiconductor Corp. The SE/NE560, 561, 562, 564, 565 and 567 series differ mainly with respect to their operating frequency range, power supply requirement and bandwidth adjustment ranges. The LM565 being the most commonly used PLL is discussed in this section. These PLL circuits consist of a Gilbert type phase detector, a temperaturecompensated VCO and facility for connecting an external RC circuit to perform the loop-filter function. Figure 5.27 shows the internal circuit diagram of LM565. The analog phase detector circuit of PLL comprises Q1 – Q2, Q3 – Q4 and Q5 – Q6 differential amplifier pairs. Q37 and R3 serve as current-sink bias source. Resistors R1 and R2 serve as loads for the phase detector. The diode-connected transistors Q7 and Q3 reduce the voltage swing to ± 0.7 V, and thus the conversion ratio of the PLL becomes 0.7 – (–0.7) 1.4 = π (5.24) Kd = π The balanced output from the phase detector is supplied to the differential transistor pair Q10 – Q11 biased by Q39 which acts as the current sink. This stage works for a gain of 1.4 and a single ended output from this stage is taken across R12. Resistor R12 in combination with the external capacitor connected between pin 7 and ground form the loop-filter. The transistors Q12 through Q23 form the voltage controlled current source for the VCO. Equal charging and discharging currents are supplied to the external capacitor C1 connected at pin 9. Resistor R1 is connected between pin 8 and +VCC. The Schmitt trigger formed by Q25 through Q36 with the differential amplifier output circuit consisting of Q33 and Q34 form part of VCO. The charging and discharging cycles through the current source are determined by switching the transistors Q23 and Q24 ON or OFF. The transistors Q14, Q26, Q30 and Q35 connected as diodes generate the desired level shifting. The pin diagram and block diagram of IC 565 are shown in Figs. 5.28(a) and (b) respectively. The IC 565 is available in 14-pin DIP package and 10-pin Metal Can package. The output of the phase detector is applied to a differential amplifier as shown in Fig. 5.28(b). A single ended output dropped across R is connected internally

Linear IC Applications

Fig. 5.27

Internal Circuit diagram of IC pLL LM565

230

to VCO. It is also available as demodulated output at pin 7 of PLL. The resistor R is part of the low-pass filter. The capacitor C between pins 7 and 10 along with the internal resistor, R of 3.6 kΩ forms the low-pass-filter. The capacitor C should be large enough to eliminate variations in the demodulated output voltage at pin 7. When dual power supplies are used, the power supply requirement for the 565 is any value in the range from ± 6 V to ± 12 V. When a single power supply is used, the supply voltage can be between + 12 V and + 24 V.

Timers and Phase Locked Loops

231

The important operating characteristics of LM565 as observed at an operating voltage range of ±6 V and TA = + 25°C are given below: Maximum power dissipation Phase Detector Input impedance Input level for limiting Output resistance Output common mode voltage Offset voltage between pins 6 and 7 Sensitivity Kd

:

300 mW

: : : : : :

5 kW 10 mV 3.6 k W 4.5 V 100 mV 0.68 V/rad

Voltage Controlled Oscillator Temperature stability Square-wave output at pin 4 Triangular wave output at pin 9 Maximum operating frequency Sensitivity Ko

: : : : :

200 ppm/°C 5.2 V (p-p) 2.4 V (p-p) 500 kHz 4.1 fo rad/sec/V

Demodulated Output Characteristics Output Voltage level at Pin 7 Maximum Voltage Swing Offset Voltage (V6–V7) Offset Voltage Vs Temperature (Drift)

: : : :

4.5 V 2 V (p-p) 50 mV 100 mV/°C

Closed-loop Performance Loop gain Ko Kd

:

2.79 fc/sec.

A 0.001 mF capacitor is connected between pins 7 and 8 to avoid oscillations due to parasitic effects. The free running or centre frequency of VCO is fo @

1.2 4R1 C1

where R1 and C1 are the external resistor connected to pin 8 and the external capacitor connected to pin 9 respectively as shown in Fig. 5.28(b).

Fig. 5.28

Ne/Se565 pLL (a) 10 pin and 14 pin diagrams

232

Linear IC Applications

Fig. 5.28

(b) Block diagram of IC LM565

The values of R1 and C1 determine the centre frequency of VCO. The value of R1 is chosen between 2 k W and 20 k W. The device can achieve lock with an input signal over ± 60% of bandwidth with respect to the centre frequency. Pins 2 and 3 form the two input terminals of IC565. The input signal can also be direct-coupled without any dc voltage difference between the pins, and the dc resistances seen from pins 2 and 3 being equal.

Derivation of Lock-in Range Assume f radians is the phase difference between the input signal and the VCO voltage. Then, the output voltage ve of the analog phase detector is given by pˆ Ê ve = K d Á f - ˜ Ë 2¯

(5.25)

where Kd is the phase angle-to-voltage transfer coefficient of the phase detector. Therefore, the control voltage to VCO is pˆ Ê vc = AK d Á f - ˜ (5.26) Ë 2¯ where A is the voltage gain of the amplifier. This control voltage vc shifts VCO frequency from its free running frequency fo to a frequency f represented by f = f o + K ov c where Ko is the voltage to frequency transfer coefficient of the VCO. When PLL achieves lock with signal frequency fi , we have f = f i = f o + K ov c From Eqs (5.26) and (5.27), we get ( fi - fo ) = AK Ê f - p ˆ vc = d Á ˜ Ë Ko 2¯ Therefore, f =

p ( fi - f o ) + 2 Ko K d A

(5.27)

(5.28) (5.29)

Timers and Phase Locked Loops

233

The maximum output voltage magnitude available from the phase detector occurs for f = p and 0 radian p as shown in Fig. 5.29 and ve (max) = ±Kd from Eq. (5.17). Then, the corresponding value of the maximum 2 control voltage available to drive the VCO is given by p vc(max) = ± ÊÁ ˆ˜ KdA Ë 2¯

(5.30)

The maximum VCO swing in frequency that can be achieved is given by p ( f – fo) max= Kovc(max) = KdKo A ÊÁ ˆ˜ Ë 2¯

(5.31)

Therefore, the maximum range of signal frequencies over which the PLL can remain locked will be fi = fo ± ( f – fo)max Êpˆ = fo ± KdKo A Á ˜ = fo ± DfL Ë 2¯ The lock-in frequency range is 2DfL and from Eq. (5.32) it is given by Lock-in-range = 2DfL = KdKo Ap = Kvp where KdKoA = Kv is the loop bandwidth. Êpˆ Êpˆ or, DfL = KdKo A Á ˜ = Kv Á ˜ Ë 2¯ Ë 2¯

(5.32)

(5.33)

(5.34)

The lock-in range is symmetrically located with respect to the free running frequency fo of VCO. For IC PLL 565, using Eq. (5.23), we have 8 fo V V = + VCC – (–VCC )

Ko = where

From Eq. (5.24),

Kd =

1.4 p

and A = 1.4 Hence, from Eq. (5.34), the lock-in range becomes DfL = ±

7.8 f o V

(5.35)

Derivation of Capture Range The frequency of VCO will be in its free running frequency fo until PLL is locked to the signal. The phase angle difference between the input signal and the VCO output voltage is f = (w i t + qi) – (wo t + qo) = (w i – wo) t + Dq

(5.36)

Thus the phase angle difference does not remain constant. Using Eq. (5.36), it will change with time at a rate given by df = wi – wo dt

(5.37)

234

Linear IC Applications

The phase detector output voltage will therefore not have a dc component but will produce a triangular ac Êpˆ voltage of peak amplitude Kd Á ˜ and a fundamental frequency ( fi – fo ) = D f. Ë 2¯ The low pass filter (LPF) is a simple RC network having the transfer function T( f) =

1 1 + j ( f / f1)

(5.38)

The fundamental frequency term supplied to the LPF by the phase detector will be the frequency difference Df = fi – fo. If Df > 3 f1, the LPF transfer function will be approximately, f1 f1 = D f ( fi - f o) The voltage vc to drive the VCO is vc = ve ¥ T( f) ¥ A or, vc (max) = ve (max) ¥ T(D f) ¥ A T(Df ) =

(5.39) (5.40)

È f1 ˘ ÍD f ˙A Î ˚ Then, the maximum VCO frequency shift is

From Eq. (5.30),

Êpˆ vc (max) = ±Kd Á ˜ Ë 2¯

Êpˆ È f ˘ ( f – fo) max = Kovc(max) = Kd Kv Á ˜ Í 1 ˙ A (5.41) Ë 2¯ ÎDf ˚ Letting f = fi for the acquisition of signal frequency, the maximum signal frequency range that can be acquired by PLL is Êpˆ È f ˘ ( fi – fo)max = ±KdKo Á ˜ A Í 1 ˙ (5.42) Ë 2 ¯ Î D fC ˚ Now DfC = ( fi – fo)max Therefore, using Eq. (5.42), p ( DfC )2 = K d Ko ÊÁË 2 ˆ˜¯ Af1 Since

Êpˆ DfL = ± K d K o Á ˜ A , we get Ë 2¯

( DfC )

ª ±

f1 Df L

(5.43)

Therefore, the total capture range is 2DfC ª 2 f1Df L where the lock-in range = 2DfL = KdKoAp = Kvp. In the case of PLL IC 565, R = 3.6 kW. Hence, the capture range is given by 1

È Df L ˘ 2 DfC = ± Í ˙ Î 2p RC ˚ where C is in Farads.

(5.44)

Timers and Phase Locked Loops

235

The capture-range is symmetrically located with respect to free running frequency fo of VCO as shown in Fig. 5.29. The PLL cannot acquire lock outside the capture-range. Once captured, it will hold-on until the signal frequency goes beyond the lock-in range. Therefore, in order to increase the lock-in range, larger capture-range is required. However, increasing the capture-range makes the PLL susceptible to noise. Hence, optimisation is to be reached. In practice, the LPF bandwidth is first set for a large value for initial acquisition of signal. When the signal is captured, the bandwidth of LPF is reduced substantially. This will minimise the interference of undesirable signals and noise. (p /2) Kf A (VCO control voltage)

Slope = 1/KV

VC fo – DfL

fo – DfC fo

fo + DfC

fo + DfL

fs

2DfC = Capture range – p /2) Kf A 2DfL = Lock in range

Fig. 5.29

Lock-in and capture ranges of pLL

Example 5.7 For PLL 565, given the free-running frequency as 100 kHz, the demodulation capacitor of 2 mF and supply voltage is ± 6 V, determine the lock and capture frequencies and identify the component values. Solution

Given fo = 100 kHz, C = 2 mF and VCC = ± 6 V We know that 7.8 f o 7.8 f o 7.8 ¥ 100 ¥ 103 DfL = ± =± =± = ± 65 kHz V + VCC - ( - VCC ) + 6 - ( - 6) Therefore, the lock range = 2DfL = 2 ¥ 65 kHz = 130 kHz DfC = ±

Df L 65 ¥ 103 ± = 2p ¥ 3.6 ¥ 103 ¥ C 2p ¥ 3.6 ¥ 103 ¥ 2 ¥ 10- 6

= ±1.199 kHz The capture range = 2D fC = 2 ¥ 1.199 kHz = 2.397 kHz The free-running frequency of VCO in the PLL IC 565 is f o = Assuming R1 = 12 kW, a standard value, we have 100 ¥ 103 =

1.2 4 ¥ 12 ¥ 103 ¥ C1

Therefore, C1 =

1.2 4 ¥ 12 ¥ 103 ¥ 100 ¥ 103

1.2 4 R1C1

= 2.5 ¥ 10-10 F = 250 pF .

236

Linear IC Applications

Determine the output frequency fo , lock range DfL and capture range Dfc of IC 565. Assume R1 = 15 kW, C1 = 0.01 mF, C = 1 mF and the supply voltage is +12 V. Example 5.8

Solution

Given R1 = 15 kW, C1 = 0.01 mF and C = 1 mF. The free running or centre frequency of VCO is 1.2 1.2 = = 2 kHz 4 R1C1 4 ¥ 15 ¥ 103 ¥ 0.01 ¥ 10- 6

fo @

The lock range is given by DfL = ±7.8 fo /V = ±7.8 ¥ 2000 /12 = ±1.3 kHz The capture range is given by 1

1

˘2 È ˘2 È Df L 1.3 ¥ 103 DfC = ± Í = ± Í 3 ˙ 3 -6 ˙ Î 2p ¥ 3.6 ¥ 10 C ˚ Î 2p ¥ 3.6 ¥ 10 ¥ 1 ¥ 10 ˚ = ± 239.73 Hz Example 5.9 Assuming C1 = 470 pF and C = 20 mF in Example 5.7, calculate the lock in range and capture range of PLL. Solution

The free running or centre frequency of VCO is fo @

1.2 1.2 = = 42.553 kHz 4 R1C1 4 ¥ 15 ¥ 103 ¥ 470 ¥ 10-12

The lock range is given by DfL = ±

7.8 f o 7.8 ¥ 42.553 ¥ 103 =± = ± 27.66 kHz V 12

The capture range is given by 1

1

˘2 È È ˘2 Df L 27.66 ¥ 103 DfC = ± Í = ± Í ˙ 3 3 -6 ˙ Î 2p ¥ 3.6 ¥ 10 C ˚ Î 2p ¥ 3.6 ¥ 10 ¥ 20 ¥ 10 ˚ = ± 247.27 kHz Example 5.10 A PLL has a free running frequency of 300 kHz and the bandwidth of the low pass filter is 50 kHz. Check whether the loop acquires lock for an input signal of 320 kHz. Solution

The sum frequency of phase detector output = (300 + 320) kHz = 620 kHz and the difference frequency of phase detector output = (320 – 300) kHz = 20 kHz. Given the bandwidth of the low pass filter as 50 kHz which is greater than the difference frequency of 20 kHz, the PLL can acquire lock.

Timers and Phase Locked Loops

5.11

applIcatIons

of

237

Ic 565 pll

The IC 565 PLL is used for applications such as (i) Frequency Multiplication/Division, (ii) AM Detection, (iii) FM Detection, (iv) FSK Modulation/Demodulation and (v) Frequency Synthesising.

5.11.1

Frequency Multiplication/Division

Figure 5.30(a) shows the block diagram of PLL used for frequency multiplication. A divide-by-N network (frequency divider) is inserted between the VCO and the phase detector. When the PLL is in locked condition, the output of the frequency divider network is the same as the input frequency fi. Therefore, the VCO actually provides the multiple of the input frequency. The desired multiplication factor is achieved by inserting suitable divide-by-N network, where N is an integer. Thus, in locked condition, fo = Nfi. As an example, a divide-by-5 network can be inserted to achieve the frequency 5fi. The frequency multiplication can also be obtained by operating the PLL in harmonic locking mode for input signals, which are rich in harmonics such as a square-wave. Then, the VCO can get directly locked-on to the nth harmonic of the input signal without the use of a frequency divider network. The value of n is normally limited to 10 since the amplitude of higher order harmonics decreases as the order increases. Therefore, effective locking may become difficult to achieve. The circuit shown in Fig. 5.30(a) can also be used for frequency division by locking the mth harmonic f of the square-wave output of VCO with the input signal. Then, the output of VCO is given by fd = i . m Figure 5.30(b) shows the output waveform of the frequency divider for a divide-by-5 circuit.

F

Fig. 5.30

Frequency multiplier using IC 565 (a) Block connection diagram and (b) Input and output waveforms

238

Linear IC Applications

5.11.2

Frequency Translation

Figure 5.31 depicts the block diagram of a frequency translator using IC565. The circuit can be employed when the input signal frequency, fi, is to be shifted by a small frequency difference. As shown in the figure, the multiplier and low pass filter (LPF) are connected externally with the PLL structure. The input signal, fi, which is to be shifted and the output frequency fo of VCO are applied as input to the multiplier. The output of the multiplier is the sum and difference frequency components of fs and fo, viz. fs ± fo. This is applied to the LPF, which allows only the difference component fi – fo. This component is applied to the phase comparator as one the two inputs. The offset frequency ft (ft < fi) is applied as the second input to the phase detector. When the Phase-Locked Loop (PLL) realizes the locked state, fo – fi = ft Or

fo = fi + ft Thus, the output frequency is a shifted or translated version of the input frequency. The offset frequency ft can be varied to translate the input signal frequency to the desired value. Offset Frequency fo ± fi

fi

Multiplier

fo – fi

LPF

ft

PLL

Phase detector

LPF

Amplifier

VCO

Output fo = fi + ft

PLL Fig. 5.31

the phase-Locked Loop (pLL) used as a Frequency translator

5.11.3 AM Demodulator The PLL can be used as an AM detector for demodulating the amplitude-modulated signals. Assume the AM signal is given by vm(t) = V p [1 + m(t ) ] sin w c t Here, m (t) is the modulation index or the modulation depth of the modulation scheme. The signal vm(t) can be demodulated by multiplying the signal with a local oscillator signal of the same carrier frequency fc, as shown in Fig. 5.32.

(5.45) v(t) vm(t)

LPF

A sin (wct + q)

Fig. 5.32

Simple aM detector

vo(t)

Timers and Phase Locked Loops

239

Then, the multiplier output is given by vo (t) = AV p [1 + m(t ) ]sin w ct sin (w c t + q ) = AV p [1 + m(t ) ]

cos q - cos (2w c t + q ) 2

The high-frequency second term can be removed by a low-pass filter, and hence the filter output becomes vo (t) = V [1 + m(t ) ] cosq

(5.46)

where V = AVP . This application can be implemented using the PLL as shown in Fig. 5.33. Here, the local oscillator signal generated in the PLL is phase-locked with the input signal. vm(t) AM input

90° Phase shift

Multiplier

LPF

vo(t) Demodulated output

PLL VCO output

Fig. 5.33

aM detector using pLL

The PLL is locked to the carrier frequency of amplitude-modulated signal. The VCO output of the PLL, which has the same frequency value as the carrier, but unmodulated, is applied as one input to the multiplier. It is to be recalled that under locked condition, the VCO output signal of PLL is 90° out of phase with the input signal. Hence, the AM input signal is phase-shifted by 90° before being applied to the multiplier. The two signals applied to the multiplier, namely, the amplitude-modulated signal and the carrier signal generated in the PLL are now in phase. The output of the multiplier is then passed through the LPF for the removal of the high frequency components. The average value of the output Vo(t) is thus directly proportional to the amplitude of the input signal. This AM detector exhibits a high degree of selectivity due to the fact that the PLL responds selectively to the carrier frequencies, which are very close to the VCO output. Due to coherent detection, higher degree of noise immunity is also achieved.

5.11.4

FM Demodulator

Figure 5.34 shows the PLL employed for FM detection. The PLL is set locked with the input FM signal. Then, the VCO frequency will be equal to the instantaneous frequency of FM signal fi (t) such that, fi (t) = fc + Kovc

(5.47)

240

Linear IC Applications

FM signal vi, fi

Phase detector Ko

LPF F (fm)

VCO Ko, fc

Fig. 5.34

A

Cc

vc(t)

vc

FM detector using pLL

fi (t ) - f c . This error voltage controls Ko the VCO to maintain lock with the input signal. The instantaneous frequency of the FM signal is given by The VCO control voltage vc is the demodulated FM output and vc = fi(t) = f c + Dfc sinw m t where fc is the carrier frequency, Dfc is the peak frequency deviation and wm is the angular frequency of the modulating signal. The ac component of vc(t) after the capacitor Cc is vc(t) =

fi (t ) - f c f + Df c sinw m t - f c = c Ko Ko

Df c sinw m t (5.48) Ko This gives the modulating signal voltage applied to the FM carrier at the transmitter. The control voltage of VCO is a linear function of the instantaneous frequency deviation. Hence, the FM signal is demodulated almost without any distortion. Therefore, the PLL can be employed for detection of wideband or narrowband FM signals with a higher degree of linearity, which cannot be achieved by any other detection methods. The centre frequency fo should be set as close as possible to the FM carrier frequency fc to achieve maximum symmetrical lock-range.

Therefore, vc(t) =

Example 5.11 A PLL IC 565 connected as an FM demodulator has R1 = 10 kW, C1 = 0.01 mF and C = 0.04 mF. The supply voltage is +12 V. Determine (a) Free-running frequency, (b) Lock-range and (c) Capture-range. Solution

The free running or centre frequency of VCO is 1.2 1.2 = = 300 kHz 4 R1C1 4 ¥ 10 ¥ 103 ¥ 0.01 ¥ 10-6 The lock range is given by fo @

È 7.5 f o ˘ 7.8 ¥ 300 ¥ 103 = 195 kHz DfL = ± Í = 12 Î V ˙˚ The capture range is given by 1

1

˘2 È ˘2 È Df L 195 ¥ 103 DfC = ± Í = ± Í ˙ 3 3 -6 ˙ Î 2p ¥ 3.6 ¥ 10 C ˚ Î 2p ¥ 3.6 ¥ 10 ¥ 0.04 ¥ 10 ˚ = 14.68 kHz

Timers and Phase Locked Loops

5.11.5

241

FSK Modulation/Demodulation

The Frequency Shift Keying (FSK) is a type of frequency modulation, in which the binary data or code is transmitted by means of a carrier frequency that is shifted between two fixed frequency values, namely, f1 representing logic 0 and f2 representing logic 1. The frequencies corresponding to logic 1 and logic 0 are called mark and space respectively. The block diagram of Fig. 5.35 shows the schematic arrangement for FSK demodulation using PLL. The PLL is designed to remain in-lock with the FSK signal for both the frequencies f1 and f2. Then, the VCO control voltage fed to the comparator is given by

and

Vf 1 =

f1 - f o Ko

(5.49)

Vf 2 =

f 2 - fo Ko

(5.50)

Fig. 5.35

FSK demodulator using pLL

The difference between the two control voltage levels is DVf =

f 2 - f1 Ko

(5.51)

Two inputs Vf1 and Vf2 are applied to the comparator. One of the inputs passes through a second low-pass filter (LPF-2). The filter is designed for a time constant which is longer than the FSK pulse duration to obtain a dc voltage. This dc voltage will have a value midway between Vf1 and Vf2. When the FSK signal vi is applied to the input, the loop gets locked to the input frequency and tracks it in between the two frequencies f1 and f2. The corresponding dc shift at the output is made logic compatible by adjusting the saturation voltages of the voltage comparator. A typical and simple circuit diagram for FSK generation and FSK demodulation is shown in Fig. 5.36. The FSK generation is done by an IC 555 timer operated in astable mode, whose frequency at the output is controlled by ON/OFF state of transistor Q1. The transistor Q1 in turn is switched ON by the input digital data applied at its base.

Fig. 5.36

a practical circuit for FSK generation and FSK demodulation

242 Linear IC Applications

Timers and Phase Locked Loops

243

The frequency values f1 and f2, as determined by the circuit shown in Fig. 5.36 are f1 =

and

f2 =

1.45 = 1270 Hz ( RA  RC + 2 RB ) C 1.45

( RA + 2 RB ) C

= 1070 Hz

The output from the FSK generator is applied to FSK demodulator designed using IC 565. The three stage RC ladder forms the LPF–2 shown in the block diagram of Fig. 5.36 for removing the carrier component.

Review Questions 5.1 Define a multivibrator.

A

5.2 What is timer IC 555? Draw the internal B structure of IC555 Timer.

5.12 Write notes on voltage multivibrator using IC 555.

controlled

5.13 List various applications of 555 timer.

A A

5.3 Define (a) an astable multivibrator, and (b) a A monostable multivibrator.

5.14 Explain the operation of a Schmitt trigger B using IC 555.

5.4 Derive the expression for the period of a pulse generated when 555 Timer is used as a B monostable multivibrator.

5.15 Design a circuit to produce a 120 ms output B pulse using the IC 555.

5.5 Design a monostable multivibrator using 555 B timer for a pulse period of 2 ms. 5.6 Differentiate an astable multivibrator from a A monostable multivibrator. 5.7 Define the duty cycle of an astable A multivibrator. 5.8 Design a square-wave generator using 555 timer for a frequency of 150 Hz and 70% duty C cycle. Assume C = 0.1 mF. 5.9 Determine the frequency of oscillation if the duty cycle D = 25% and the ON period T1 = C 1 ms. 5.10 Design a dual frequency generator circuit for C the frequencies 1200 Hz and 1000 Hz. 5.11 Give the advantages of the op-amp based astable multivibrator over the BJT based B multivibrator.

5.16 What are the important features of IC 7555? A

5.17 What are the general applications of IC 7555? A

5.18 What are the features of IC 7555 which B makes it superior to IC 555? Elaborate. 5.19 Draw the internal architecture of IC 7555 and explain the difference in structure against IC C 555 and its advantages 5.20 Design an astable multivibrator using IC 7555 and explain the operation. Choose component values for generating a frequency of 2 kHz and duty cycle of 50%. Assume C suitable capacitance value. 5.21 Design a monostable mutivibrator using IC 7555 for generating a pulse train of 3 ms C pulse period. A 5.22 What is PLL?

244

Linear IC Applications

5.23 Draw the basic block diagram of a PLL and A explain. 5.24 Define capture-range, lock-range and pull-in A time of PLL. 5.25 Why is capture-range always smaller than the B lock-range? B 5.26 Briefly explain the role of LPF in PLL. A 5.27 List the applications of PLL. 5.28 Explain an analog phase detector with a suitable circuit diagram. Also draw the input B and output waveforms. 5.29 What are the desirable properties for a VCO? A

5.30 Draw the circuit diagram of a VCO and A explain its operation. 5.31 Draw the block diagram of IC 566 VCO and A explain its operation. 5.32 In a VCO, there is a change in frequency for A a change in ______. 5.33 Determine the change in dc control voltage vc at lock, if signal frequency fs = 10 kHz, the free running frequency is 10.5 kHz and the V/F transfer coefficient of VCO is 5 kHz/V. C

5.34 Perform the closed loop analysis of PLL and C derive the transfer function of PLL. 5.35 Derive the expressions for the lock-in and C capture ranges of IC 565 PLL. 5.36 Calculate the output frequency fo, lock-range fL and capture-range fc of IC 565. Assume R1 = 10 W, C1 = 0.01 mF and C = 20 mF. C 5.37 Assuming C1 = 560 pF in the previous problem, calculate the output frequency. C 5.38 A PLL IC 565 connected for FM detection has R1 = 8.3 kW, C1 = 0.001 mF and Cc = 0.02 mF. The supply voltage is +12 V. Determine the (a) Free-running frequency, (b) CaptureC range and (c) Lock-range 5.39 A PLL has a free running frequency of 500 kHz and the bandwidth of the low-pass filter is 10 kHz. Will the loop acquire lock for an input

signal of 600 kHz? Justify your answer. Assume that the phase detector produces sum C and difference frequency components. A 5.40 What are the applications of PLL? 5.41 Discuss the application of PLL IC for frequency multiplication. Differentiate between frequency multiplication and frequency B translation. 5.42 Using neat sketches, explain how a PLL can B be used as frequency translator. B 5.43 Define modulation and demodulation. 5.44 Draw the circuit diagram of AM detector using B PLL and explain its operation. 5.45 FM detection can be done using PLL A (True/False). 5.46 Briefly explain the use of PLL for FM A detection. 5.47 Explain the process of FSK demodulation B using PLL. 5.48 What is the use of demodulator in a communication system? What is the advantage of B FSK? 5.49 How is frequency stability obtained in a PLL B by the use of VCO? 5.50 The PLL can be used as a programmable A frequency generator (True/False). 5.51 Find the lock and capture frequencies for PLL 565, with free-running frequency of 120 kHz, demodulation capacitor of 1 mF and C supply voltage of ±5 V. 5.52 For the VCO circuit shown in Fig. 5.25(c), assume R2 = 1.5 kW, R1 = R3 = 12 kW, C2 = 0.001 mF and VCC =10 V. Calculate the output frequency and the change in output frequency if modulating input vC is varied C from 7 V to 8 V. 5.53 Derive the expression for free running B frequency of VCO. 5.54 Define voltage-to-frequency conversion A factor of VCO.

Timers and Phase Locked Loops

245

Objective-Type Questions 5.1 In a monostable multivibrator, the trigger pulse width must be (a) less than pulse width T (b) greater than pulse width T (c) pulse width T B (d) none of these 5.2 Astable multivibrator can be used as a timeA delay circuit (True/False) 5.3 Monostable operation of 555 timer has (a) one stable state and one quasi stable state (b) two stable state (c) Two quasi stable state A (d) none of these 5.4 For an astable multivibrator using IC 555 1 (a) f = 1.45C ( RA + 2 RB ) (b) f =

1.45 ( RA + 2 RB )C

(c) f =

1.45C RA + 2 RB

(d)

1.45 2C ( RA + RB )

5.7 Low pass filter in a PLL controls the (a) lock range (b) capture range (c) error voltage (d) centre frequency fo

B

5.8 Reducing the filter bandwidth of a PLL (a) improves the rejectivity of out-of-bandsignals (b) reduces the capture range (c) increases the pull-in time C (d) all of these 5.9 Lock range of a PLL is _________ less than the capture range. B (a) larger (b) smaller 5.10 In perfect locked state, the phase difference between the input signal and VCO frequency is (a) 0° (b) 180° A (c) 270° (d) 90° 5.11 The phase angle to voltage conversion ratio Kj is given by

C

5.5 PLL can detect the ________ of two signals and _______________ the difference in the presence of a phase difference. (a) phase, reduce (b) phase, increase (c) amplitude, reduce B (d) amplitude, increase 5.6 While in lock, the two input ___________ of a PLL are almost identical and the phase difference between them is ________ (a) frequencies, 90° (b) amplitudes, 90° (c) phases, 90° B (d) frequencies, 180°

(a)

2 I EE RC p

(b)

2 I EE p RC

(c)

2 I EE p RC

(d)

2 RC I EE p

C

5.12 Voltage to frequency transfer coefficient is given by (a)

VCC 8f

(b)

8 fo VCC

(c)

8VCC f - fo

(d)

f - fo 8VCC

B

5.13 A PLL is a feedback loop consisting of a phase detector, _________, amplifier and VCO. (a) low-pass filter (b) band-pass filter (c) notch filter (d) all pass filter A

246

Linear IC Applications

5.14 The lock range of a PLL is given by (a) 2 fo(max) (b) 2D fC (c) Kv Kjp (d) Kd Ko Ap 5.15 Capture range of a PLL is given by (a) (f – fo)max (b) 2(f – fo)max (c) 2 f1Df L

5.21 The advantages of the use of PLL as an AM detector are (a) it avoids the use of IF filter and the need for additional oscillators (b) it avoids complete IF section (c) it avoids complete RF section B (d) none of these

B

(d) none of these B

5.22 While using the PLL for FM detection, the VCO control voltage vc is given by (a) D f sin wmt/Ko (b) D f/Ko sin wmt (c) sin wmt/Ko D f (d) Dsin wmt/Ko f

5.16 The loop bandwidth is given by (a) K v =

Ko A Kd

(b) Kv = Ko Kd A

C

K K (c) K v = o d A

(d) none of these B

5.17 The _______ term in analog phase detector non-linear. (a) cos j (c) tan j

the response of an makes the response (b) sin j (d) none of these B

5.18 Digital phase detector can be constructed by using (a) IC7400 (b) IC7410 A (c) CD4070 (d) IC7420 5.19 IC 566 is a phase locked loop (True/False) A 5.20 The PLL can be employed as a ___________ filter. (a) high-pass (b) low-pass B (c) band-pass (d) tracking

5.23 The PLL can be employed for FSK modulation and demodulation using (a) FM detector configuration (b) AM detector configuration (c) frequency shift keying B (d) Frequency synthesizer 5.24 The output frequency fo of a VCO is given by (a)

1.2 4R1C1

(b)

4 1.2R1C1

(c)

1.2C1 4 R1

(d)

4 R1 1.2 R1C1

5.25 The most suitable IC for the application of tone decoder is (a) NE565 (b) NE567 B (c) NE564 (d) NE566

Answers to Objective-Type Questions 5.1 5.6 5.11 5.16 5.21

(b) (a) (a) (b) (a)

5.2 5.7 5.12 5.17 5.22

(a) (b) (b) (a) (a)

5.3 5.8 5.13 5.18 5.23

(a) (d) (a) (c) (c)

C

5.4 5.9 5.14 5.19 5.24

(c) (a) (d) False (a)

5.5 5.10 5.15 5.20 5.25

(a) (d) (c) (d) (a)

Chapter

6 6.1

D/A and A/D Converters

IntroductIon

The data converters convert one form of data into another. Real world processes produce the analog signals which carry information pertaining to process variables, such as, voltage, current, charge, temperature and pressure. The rate of flow of such information may be very slow or very fast. It is difficult to store, manipulate, compare, calculate and retrieve such data with good accuracy using purely analog technology. Computers can perform these operations quickly and efficiently using digital techniques. Therefore, it is necessary to convert the analog signals from various transducers into its equivalent digital data, which in turn acts as the input for digital systems. Thus, the requirement for converting analog signal into digital data emerges. The computers also need to communicate with people and physical processes through the use of analog signals, which necessitate the process of digital to analog conversion. This chapter discusses the most common D/A and A/D conversion techniques, D/A converter and A/D converter. The ICs, delta modulators and demodulators are followed by sigma-delta converters and widely used ICs for D/A and A/D conversions.

6.2

AnAlog

And

dIgItAl dAtA conversIons

In the application of signal processing, the measurement and analysis of signals are very important to identify their characteristics. If the signal is unknown, the process of analysis begins with the acquisition of the signal. The most common technique of acquiring signals is by sampling. Sampling a signal is the process of acquiring its values only at discrete points in time. The definitions related to the process of sampling and the subsequent analog and digital conversion processes are: (i) an analog signal is a signal that is defined over a continuous period of time in which the amplitude may assume a continuous range of values. (ii) the term quantisation refers to the process of representing a variable by a finite set of discrete values. (iii) a quantised variable is the signal variable that can assume only finite distinct values. (iv) a discrete time signal is the one that is defined at particular points of time only. Therefore, the independent time variable is quantised. When the amplitude of a discrete-time signal is allowed to assume a continuous range of values, the function is called a sampled-data signal. A sampled data signal could result from sampling an analog signal at discrete points of time. (v) a digital signal is a function, in which the time and amplitude are quantised. A digital signal is always represented by a sequence of words, where each word can contain a finite number of bits (binary digits). A D/A converter (DAC) converts digital data into its equivalent analog data. The analog data is required to drive motors and other analog devices. An A/D converter (ADC) converts analog data into its equivalent

248

Linear IC Applications

digital data, i.e. binary data. The A/D converter and D/A converter are also called data converters and they are also available as monolithic integrated circuits. Figure 6.1 shows a typical application in which A/D and D/A conversions are employed. An analog input signal from a transducer is band-limited by anti-aliasing filter. The signal is then sampled at a frequency rate higher than twice the maximum frequency of the band-limited input signal. That is, when the A/D converter is operated at a rate of fs samples/second, the highest frequency component of the input signal can be less than fs/2. The A/D converters normally require the input to be held constant during the conversion process. Hence, a Sample-and-Hold Amplifier (SHA) is introduced in the loop as shown in Fig. 6.1 before A/D converter. The SHA freezes the band-limited signal just before the start of each conversion. The digital signal from A/D converter may be processed, transmitted and recorded in digital form by the digital signal processor (DSP) block. Then, the digital signal is converted into analog signal by D/A converter for use in analog form. The D/A converter is usually operated at the same frequency fs as that of A/D converter. The output of D/A converter is commonly a staircase signal, which is passed through a smoothing filter to eliminate the quantisation noise effects. A deglitcher may be introduced in the loop before the smoothing process, to remove any output glitches generated during input code variations.

Vi

Antialiasing filter

Fig. 6.1

SHA

ADC

DSP

DAC

Deglitcher

Smoothing filter

Vo

Sampled data system using a/D and D/a converters

The schematic structure shown in Fig. 6.1 is prevalent either in full or in part in numerous applications such as digital signal processing, direct signal control, digital audio mixing, music and video synthesis, pulsecode modulation (PCM) communication, data acquisition and digital microprocessor based instrumentation.

6.3

specIfIcAtIons

of

d/A converter

The important specifications, namely, accuracy, offset voltage, monotonicity, resolution and settling time of D/A converter are discussed below.

Accuracy The components in D/A converter circuits are prone to mismatches, drift, ageing, noise and other sources of errors. These factors lead to degradation in conversion performance. Absolute accuracy defines the maximum deviation of the output from the ideal value and it is expressed in fractions of 1 LSB. The D/A converter manufacturers follow different ways of specifying accuracy. The D/A converter errors are classified as static and dynamic errors.

Offset Voltage The simplest kind of static errors are offset error and gain error. Ideally, the output of a D/A converter is 0V when all the bits of binary input word are 0s. In practice, however, there is a very small output voltage called

D/A and A/D Converters

VFS

VFS Gain error

vo

Ideal

vo

Ideal

Offset error

249

0 000

111

b1b2b3 (a)

Fig. 6.2

0 000

b1b2b3

111

(b)

D/a Converter (a) Offset error (b) Gain error

offset voltage or offset error as depicted in Fig. 6.2(a). The offset error is nullified by translating the actual A/D converter characteristics up or down so that it goes through the origin as shown in Fig. 6.2(a). The gain error shown in Fig. 6.2(b) is compensated by adjusting the scale factor K.

Linearity

Analog signal

The most common dynamic errors are fullscale error and linearity error or the gain 7/8 VFS error. Full-scale error is the maximum 3/4 VFS deviation of the output value from its D 5/8 VFS expected or ideal value, expressed in 1/2 VFS percentage of full-scale. Linearity error is Œ the maximum deviation in step size from 3/8 VFS the ideal step size. More expensive D/A 1/4 VFS converters have full-scale and linearity 1/8 VFS errors as low as 0.001% of full-scale. General purpose D/A converters have 000 001 010 011 100 101 110 111 accuracies in the range of 0.01 to 0.1%. Digital word The linearity of a D/A converter is defined as the precision with which the Fig. 6.3 Linearity error of a 3-bit D/a converter digital input is converted into analog output. An ideal D/A converter produces equal increments in analog output for equal increments in digital input as shown in dotted line curve of the transfer characteristics of Fig. 6.3. However, in an actual D/A converter, the gain and offset errors due to resistors introduce non-linearity as shown by the solid line of the transfer characteristics of Fig. 6.3. The linearity error measures the deviation of the output from the fitted straight line which passes through the measured output points. It is represented by Œ/D as shown in Fig. 6.3. Commonly, the linearity of 1 1 D/A converter is specified as less than ± LSB meaning that |Œ| < D. 2 2

250

Linear IC Applications

Differential Nonlinearity (DNL) Error For a D/A converter, the DNL error is the difference between the ideal and the measured output responses for successive D/A converter codes. An ideal D/A converter response would have analog output values exactly one code (1 LSB) apart (DNL = 0). A DNL specification of greater than or equal to 1 LSB guarantees monotonicity.

Integral Nonlinearity (INL) Error For data converters, INL is the deviation of an actual transfer function from a straight line. After nullifying offset and gain errors, the straight line is either a best-fit straight line or a line drawn between the end points of the transfer function. The INL is often called relative accuracy.

Monotonicity A D/A converter is monotonic if its output value increases as the binary inputs are incremented from one value to the next. That is, the staircase output can have no downward step as the binary input is incremented. Figure 6.3 shows the transfer curve for a non-monotonic D/A converter. The output decreases when the input word changes from 011 to 100. The monotonic characteristic is important in control applications, without which, oscillations will result. 1 If a D/A converter is identified to be monotonic, the error must be less than ± LSB at each output level. 2 1 Hence, all the D/A converter ICs are designed to have linearity error of less than ± LSB. 2

Resolution (step size) Resolution of D/A converter is defined as the smallest change that can occur in the analog output as a result of a change in the digital input. The resolution is always equal to the weight of the LSB and is also known as the step size, since it is the amount of Vo that will change when the digital input data goes from one step to the next. Although resolution can be expressed as the amount of voltage or current per step, it is more useful to express it as a percentage of the full-scale output. The percentage resolution is given by step size % Resolution = full scale ¥ 100

(6.1)

Percentage resolution can also be calculated as 1 % Resolultion = total number of steps ¥ 100

(6.2)

For an n-bit digital input, the total number of steps is (2n – 1). Then, % Resolultion =

1 (2n - 1)

¥ 100

This means that it is the number of bits which determines the percentage resolution of an A/D converter.

D/A and A/D Converters

251

Settling Time or Conversion Time The time required for the output of a D/A converter to settle down to within ±(1/2) LSB of the final value for a given digital input is known as settling time. It depends on the switching time of the logic circuits, which in turn depends on the inevitable stray capacitances and inductances present in the converter circuit. The settling time normally ranges from 100 ns to 10 ms based on the word length and the conversion technique employed.

Temperature Sensitivity For a fixed digital input, the analog output varies with temperature, normally from ±50 ppm/oC to ±1.5 ppm/oC. This is introduced due to the temperature sensitivity of the reference voltages, the resistors used in the converters, the op-amp and its offset voltage. Therefore, this factor determines the stability of D/A converter. There are various types of D/A converters, namely, (i) weighted resistor type, (ii) R-2R ladder type, (iii) voltage mode R-2R ladder type and (iv) inverted or current mode R-2R ladder type.

6.4

BAsIc d/A conversIon technIques

The D/A converter converts digital or binary data into its equivalent analog value. The input digital data for a D/A converter is an n-bit binary word D. The bit b1 is called the most significant bit (MSB) and bit bn the least significant bit (LSB). Then, the quantity D can be represented by D = b12–1 + b22–2 + b32–3 + .... + bn2–n. The D/A converter accepts the binary input D and produces an analog output, which is proportional to D using a reference voltage VR. The converted analog value is either in voltage or current form. For a voltage output D/A converter, the conversion characteristic may be expressed as

(

Vo = KVFS b1 2-1 + b2 2-2 + b3 2-3 + ... + bn 2- n where

)

(6.3)

Vo VFS K b1 ... bn

= output voltage = full-scale range of voltage = scaling factor, usually unity = n-bit binary fractional word with binary point located at the left b1 = most significant bit (MSB) of weight VFS/2 bn = least significant bit (LSB) of weight VFS/2n

The symbolic representation of an n-bit D/A converter is shown in Fig. 6.4.

Fig. 6.4

n-bit D/a converter

6.4.1 Weighted Resistor Type D/A Converter In the weighted resistor type D/A converter, each digital level is converted into an equivalent analog voltage or current. In a 4-bit D/A converter which accepts data from 0000 to 1111, there are 15 discrete levels of input above the zero level, and hence it is convenient to divide the output analog signal into 15 levels above zero.

252

Linear IC Applications

The LSB of the digital data causes a change in the analog output that is equal to 1/15th of the full-scale analog output voltage (VR). Therefore, the weighted resistor network is designed in such a way that a 1 in LSB (20) position results in VR ¥ 1/15 at the output. A 1 in the 21 bit position must cause a change in the analog output voltage that is equal to 2/15th of VR (i.e. twice the size of the LSB). Similarly, a 1 in 22 and 23 bit positions must cause a change of VR ¥ 4/15V and VR ¥ 8/15V respectively as the analog output. It is important to note that the sum of the weights assigned to various bit positions of a 4-bit D/A converter must be equal to 1, i.e. (1/15 + 2/15 + 4/15 + 8/15 = 15/15) VR = VFS. In general, the weight assigned to the LSB is 1/(2n – 1), where n is the number of bits in the digital input. Thus, the 4-bit weighted resistor network shown in Fig. 6.5(a) performs the following D/A conversion: 1. The 20 bit is changed to 1/15th of VR, 21 bit to 2/15th of VR, 22 bit to 4/15th of VR and 23 bit to 8/15th of VR. 2. These four voltages are added together to form the analog output voltage using an op-amp summer circuit. The resistor R0, R1, R2 and R3 form the voltage divider network connected with the op-amp and RL is the load resistor which should be large enough so as not to load the divider network. The LSB should be connected with the highest input resistance R0 while the 21 bit is connected with a resistance of half the value of LSB resistor, i.e. R0/2. Therefore, its current contribution at the summing junction of op-amp will be twice that of LSB. The 22 bit is connected with a 1/4th of LSB resistance, i.e. R0/4. Similarly, the MSB is connected with 1/8th of the LSB resistance, i.e. R0/8. The output is the sum of these four attenuated voltages. The operating principle of the circuit is explained with the following illustration.

Illustration The equivalent circuit of Fig. 6.5(a), when applied with the digital data of 0001, is shown in Fig. 6.5(b). The analog output voltage Vo can be calculated using Millman’s theorem, which states that the voltage at any node in a resistive network is equal to the sum of the currents entering the node divided by the sum of the conductance connected at the node. Assume VR to be the reference voltage which provides current to the resistive network, based on the presence or absence of logic 1 in a particular bit position. Then, the output voltage is expressed as

Fig. 6.5

VR VR VR VR + + + R0 R1 R2 R3 Vo = 1 1 1 1 + + + R0 R1 R2 R3

(a) Four-bit weighted resistor D/a converter

(6.4)

D/A and A/D Converters

Fig. 6.5

253

(b) equivalent circuit of a 4-bit weighted resistor D/a converter for input 0001

For the weighted resistor network, assuming R1 = R, R2 = R/2, R3 = R/4 and R4 = R/8, and applying the Millman’s theorem to the circuit of Fig. 6.5(b), we get VR V V V + R + R + R R R / 2 R /4 R /8 Vo = 1 1 1 1 + + + R R / 2 R / 4 R /8

(6.5)

Figure 6.6(a) shows the circuit of an n-bit D/A converter using op-amp as a summing amplifier. It employs a binary-weighted resistor network to generate the terms bi2–i where i = 1, 2, … n. The circuit also uses n-electronic switches controlled by the binary input word b1, b2, ... bn and a reference voltage –VR. The switches are of single pole double throw (SPDT) type. If the binary input to a switch is 1, then the switch connects the resistance to the reference voltage –VR. When the input bit to the switch is 0, it connects the resistor to ground.

Fig. 6.6

an n-bit weighted resistor D/a converter: (a) Circuit diagram

Considering an ideal op-amp A, the output current Io is given by Io = I1 + I 2 + ... + I n =

VR 1

2 R

b1 +

VR 2

2 R

b2 + º +

VR 2n R

bn

VR [b1 2-1 + b2 2-2 + º + bn 2- n ] R V Then, the output voltage Vo = I o R f = R [b1 2-1 + b2 2-2 + º + bn 2- n ] R =

(6.6)

254

Linear IC Applications

Using Eqs (6.3) and (6.6), it can be seen that if Rf = R, then K = 1 and VFS = VR. The n-bit D/A converter circuit shown in Fig. 6.6(a) uses a negative reference voltage, thus producing a positive staircase voltage. The analog output voltage waveform for 3-bit weighted resistor D/A converter is shown in the transfer characteristics of Fig. 6.6(b) for input binary words 000, 001, … 111.

code

Fig. 6.6

an n-bit weighted resistor D/a converter: (b) transfer characteristic

It can be noted that (i) The D/A converter output is the result of multiplying the analog signal VR by the signal data. Therefore, if VR is made variable, then the D/A converter is called a multiplying D/A converter [MDAC]. (ii) Higher the value of n, finer is the resolution of conversion, and closer is the staircase to a continuous ramp waveform. DACs are available for word lengths ranging from 6 bits to 20 bits or more with 6, 8, 10, 12 and 14 bits being common. (iii) The op-amp in Fig. 6.6(a) can be connected in non-inverting mode also. (iv) The op-amp is operated as a current-to-voltage converter. (v) Polarity of VR is chosen depending on the switches to be operated. (vi) The accuracy and stability of D/A converter are based on the accuracy of resistors and their temperature dependence and the resistors have to handle varying currents based on bit values. (vii) The switches are in series with resistors, and therefore the finite ON resistance of the switch must be very low. The bipolar transistor does not perform well as voltage switches due to the voltage offset when it is in saturation. Therefore, MOSFET devices are preferred as efficient electronic switches. The main disadvantage of binary weighted D/A converter is the requirement of wide range of resistor values. As the length of the binary word is increased, the range of resistor values needed also increases. For an 8-bit D/A converter, the resistor values to be connected with the bits are 20R + 21R + ... + 27R. Therefore, the largest resistor corresponding to bit b8 is 128 times the value of the smallest resistor corresponding to bit b1. The fabrication of such large value of resistors of the order of MW is not practically possible in monolithic

D/A and A/D Converters

255

circuit fabrication. In addition, the voltage drop variations across such high value resistors due to the bias currents affect the accuracy. Therefore, the limitations in achieving and maintaining resistor ratios restrict the use of weighted resistor D/A converters to below 8-bits of word length. The R-2R ladder type D/A converter is a better choice for practical applications and it overcomes such drawbacks. A system uses a 12-bit word to represent the input signal. If the maximum peak-to-peak voltage at the output is set to 4 V, find the resolution of the system and the dynamic range. Example 6.1

Solution

The 12-bit word can represent 212 or 4096 levels, which are equally spaced across the 4 V range. Then, the 4 step size = = 976 mV. Therefore, the system can identify input changes as low as 976 mV. 4096 The dynamic range gives the ratio of the largest value to the smallest value which can be converted. Therefore, 4 the dynamic range = 4096. The dynamic range in dB is given by 20 log10 4096 = 72 dB. 976 ¥ 10 - 6 Example 6.2

An 8-bit D/A converter has an output voltage of range 0 to 2.55 V. Find the resolution of

the system. Solution

An 8-bit D/A converter can identify 28 or 256 levels. Therefore, the output can have 256 different values starting from 00000000. 2.55 2.55 = = 10mV. Then, the step size = n 2 - 1 255 Therefore, the system can produce output changes as low as 10 mV. Example 6.3 A 4-bit R-2R ladder type D/A converter having resistor values of R = 10 kW and 2R = 20 kW, uses VR of 10 V. Find (a) the resolution of the D/A converter (b) Io for a digital input of 1101. Solution

Given n = 4, R = 10 kW and VR = 10 V. (a) Resolution of 1 LSB =

1 n

¥

1 10 VR = 4 ¥ 2 10 ¥ 103 R

2 1 ¥ 1 mA = 62.5 mA. = 16 (b) The output Io for a digital input of 1101 is Io = 62.5 mA ¥ 13 = 0.8125 mA (since binary 1101 = decimal 13)

256

Linear IC Applications

Example 6.4 An 8-bit D/A converter has a resolution of 10 mV/bit. Find the analog output voltage for the inputs (a) 10001010 and (b) 00010000. Solution

The decimal equivalent value D = b827 + b726 + b625 + ... + b120 (a) For input = 10001010, D = (1)27 + 0 + 0 + 0 + (1)23 + 0 + (1)21 + 0 = 128 + 8 + 2 = 138 Therefore, Vo = 138 ¥ 10 mV/bit = 1.38 V (b) For output = 00010000, D = 0 + 0 + 0 + (1)25 + 0 + 0 + 0 + 0 + = 32 Therefore, Vo = 32 ¥ 10 mV/bit = 0.32 V

6.4.2

R-2R Ladder D/A Converter

A wide range of resistor values is required in the design of binary weighted resistor D/A converter. In R-2R ladder D/A converter, resistors of only two values, i.e. R and 2R are used. Hence, it is suitable for integrated circuit fabrication. The typical values of R used vary from 2.5 kW to 10 kW. The principle of operation of a ladder type network for 4-bit D/A conversion is shown in Fig. 6.7(a), with 4-bit binary input b1 b2 b3 b4, analog output Vo and one terminating resistor 2R. In this ladder circuit, the output voltage is a weighted sum of digital inputs. For example, if the 4-bit binary input, b1 b2 b3 b4 is 1000, i.e. if MSB is 1, while the other three inputs are 0, the circuit shown in Fig. 6.7(a) can be modified as shown in Fig. 6.7(b). Here, the terminating resistor (2R) and the resistor connected to b4 input (2R) are combined at node N1 to form an equivalent resistor (R) as shown in the equivalent circuit of 1st stage in Fig. 6.7(c). Then, at node N2, the resistor connected with b3 input (2R) can be combined with the resistor (R + R = 2R) to form the 2nd stage of equivalent circuit as shown in Fig. 6.7(d). Similarly, at Node N3, the equivalent resistor is R as shown in the equivalent circuit of stage 3 in Fig. 6.7(e). Then, the analog output voltage Vo is given by Vo =

VR ¥ 2 R V = R R + R + 2R 2

(6.7)

Fig. 6.7

(a) Four-bit r-2r ladder type D/a converter

Fig. 6.7

Fig. 6.7

(b) equivalent circuits for binary input b1 b2 b3 b4 =1000

(c) equivalent circuit of 1st stage

257

D/A and A/D Converters

Fig. 6.7

(d) equivalent circuit of 2nd stage

Fig. 6.7

(e) equivalent circuit of 3rd stage

Thus, for digital input b1 b2 b3 b4 = 1000, i.e. when MSB = 1, the output is VR/2. Similarly, it can be found that for digital input b1 b2 b3 b4 = 0100, i.e. when second MSB = 1, the output is VR/4; for b1 b2 b3 b4 = 0010, the output is VR/8 and for b1 b2 b3 b4 = 0001, i.e., when LSB = 1, the output becomes VR/16. Since the resistive ladder is a linear network, the principle of superposition can be used to find the total analog output voltage for a particular digital input by adding the output voltages caused by the individual digital inputs. This can be represented for an n-bit D/A converter as follows: Vo =

VR 1

+

VR 2

+

VR 3

++

VR

2 2 2 2n where n is the total number of bits at the input.

Fig. 6.8

(6.8)

Four-bit r-2r ladder D/a converter

Figure 6.8 shows a practical circuit arrangement of a 4-bit D/A converter using an op-amp. The inverting input terminal of the op-amp acts as summing junction for the ladder inputs. Using Eq. (6.8) the output voltage Vo is expressed by R f Ê b1 b2 b3 b4 ˆ Vo = –VR + + + R ÁË 21 22 23 24 ˜¯ = –VR

Rf R ¥ 24

(b1 23 + b2 22 + b3 21 + b4 20 )

(6.9)

258

Linear IC Applications

Or, more generally for an n-bit input signal, assuming Rf = R Vo = –

VR 2n

(b1 2n -1 + b2 2n - 2 + ... + bn 20 )

The resolution of the R-2R ladder type D/A converter with current output is given by 1

Resolution I =

2

¥

n

VR R

(6.10)

The resolution of the R-2R ladder type D/A converter with voltage output is given by 1

Resolution V =

2

n

¥

VR ¥ Rf R

(6.11)

where Rf is the feedback resistance of the op-amp. Consider the R – 2R 4-bit converter of Fig. 6.8 and assume that feedback resistance Rf of the op-amp is variable, the resistance R = 10 kW and VR = 10 V. Determine the value of Rf that should be connected to achieve the following output conditions. Example 6.5

(a) (b) (c) (d)

The value of 1 LSB at the output is 0.5 V. An analog output of 6 V for a binary input of 1000. The full-scale output voltage of 12 V. The actual maximum output voltage of 10 V.

Solution

(a) Given R = 10 kW, VR = 10 V and n = 4. Using Eq. (6.11), for a value of 1 LSB = 0.5 V, we have R f ¥ 10 104 ¥ 24

= 0.5 or

Rf =

104 ¥ 24 ¥ 0.5 = 8 kW 10

(b) For binary value of 1000, using Eq. (6.9) and setting b1 = 1 and b2 = b3 = b4 = 0, we get 6=

R f ¥ 10 ¥ 2-1 104

104

¥ 6 = 12 kW

or

Rf =

Rf =

104 ¥ 12 = 12 kW 10

10 ¥ 2-1

(c) For VFS = 12 V, we get R f ¥ 10 104

= 12 or

(d) Let b1 = b2 = b3 = b4 = 1. Thus, for getting a full scale voltage of 10 V, R f ¥ 10 104 That is, Rf =

(2-1 + 2-2 + 2-3 + 2-4 ) = 10

104 ¥ 10 = 10.667 kW 10 ¥ 0.9375

D/A and A/D Converters

6.4.3

259

Inverted or Current-Mode R—2R Ladder D/A Converter

In weighted resistor and R–2R ladder types of D/A converters, the current flowing through the resistors changes as the input data changes. Power dissipation causes heating, and non-linearity of D/A conversion arises due to varying power dissipation values corresponding to bit patterns. This becomes a serious limitation as the word length increases. This is eliminated in the inverted R–2R ladder type of D/A converter shown in Fig. 6.9.

Fig. 6.9

Inverted or current-mode R–2R ladder D/a converter

The bit position of each of the subsequent MSBs and LSBs are interchanged. Each binary input is connected through the switch to either ground or to the inverting input terminal of op-amp, which is at virtual ground. Since both the positions of switch bi are at ground potential, i.e. the actual or virtual ground, the current flow through any resistor is constant and it is independent of the input binary bit value. These currents can be represented as V I1 = R (6.12) 2R

and

I2 =

(VR /2) = VR

I3 =

(VR /4) = VR

In =

2R

2R

(V

R /2

=

I1 2

(6.13)

=

I1 4

(6.14)

4R

8R n -1

)=

I1

(6.15)

2R 2n -1 The output voltage Vo is given by Vo = –Io ¥ Rf = –Rf (I1 + I2 + I3 + ... + In) = -

When Rf = R,

VR R f R

(

(b1 2-1 + b2 2- 2 + ... + bn 2- n )

Vo = - VR b1 2-1 + b2 2-2 + ... + bn 2- n

)

(6.16)

260

Linear IC Applications

The circuit operates on the principle of summation of the currents. Hence, it is called R – 2R current mode type of D/A converter. The current divides equally in successive nodes as indicated in Eqs (6.12) to (6.15) and the current flow in individual arms of the network remains the same irrespective of the binary bit pattern. Therefore, currents are maintained constant in all the branches and the ladder node voltages also remain constant at VR/20, VR/21, VR/22 ... VR/2n–1. The op-amp is used as a current-to-voltage converter and the total current Io is determined by the binary word. The most important advantage of the current mode or inverted ladder type of D/A converter is that the stray capacitances do not affect the speed of response of the circuit due to the constant ladder node voltages. Hence, the speed performance is improved. The advantage of this type of D/A converter is their capability of using any two voltage levels for the bit switching, neither of which need necessarily be zero. Example 6.6 The inverted R–2R ladder shown in Fig. 6.9 has R = Rf = 10 kW and VR = 10 V. Calculate the total current delivered to the op-amp and the output voltage when the binary input is 1110. Solution

Using Eqs (6.12) through (6.15), we get I1 =

VR 10 = = 0.5 mA 2 R 2 ¥ 10 ¥ 103

I2 =

I1 I 0.5 ¥ 10 - 3 0.5 ¥ 10 - 3 = = 0.25 mA and I3 = 1 = = 0.125 mA 2 2 4 4

Therefore, the current Io is given by Io = I1 + I2 + I3 = 0.5 + 0.25 + 0.125 = 0.875 mA. The output voltage Vo = –0.875 ¥ 10–3 ¥ 10 ¥ 103 = –8.75 V

6.5

A MonolIthIc d/A converter dAc 1508/1408

Monolithic D/A converters consisting of R–2R ladder network with switches and the feedback resistors are available for binary word lengths of 8, 10, 12, 14 and 16. Hybrid D/A converters are available from DATEL Inc. for current and voltage outputs. The MC1508/MC1408 series of 8-bit monolithic D/A converters provide high-speed performance with low cost. They are designed for use when the output current is required to be a linear product of an 8-bit digital word and an analog reference voltage. The important features of these ICs are their fast settling time of the order of 70ns (typ), a relative accuracy of ±0.19% (max error), an output voltage swing from +5 V to –5 V and high multiplying speeds of 4 mA/ms (input slew). The inputs are non-inverting and TTL and CMOS compatible with settling time of 300ns. The ICs operate with standard supply voltages of +5 V and –5 V to –15 V. These ICs find applications in tracking A/D converters, Digital Panel Meters (DPM) and Digital Voltmeters (DVM), waveform synthesising circuits, Sample-and-Hold and peak detector circuits, CRT character generation circuits, audio digitising and decoding, programmable power supplies, analog and digital arithmetic operations, speech compression and expansion, stepping motor drive modems and servo motor and pen drivers. Figures 6.10(a) and (b) show two different pin configurations of the IC 1408. The internal block diagram of the IC MC1508/MC1408 is shown in Fig. 6.11. It consists of a reference current amplifier, an R–2R ladder and 8 high-speed current switches. For many applications, only an external reference resistor and the reference

D/A and A/D Converters

Fig. 6.10

Fig. 6.11

261

(a) and (b) pin configurations of IC 1408

Internal block diagram of IC MC1508/MC1408

voltage need to be added. The switches are non-inverting in operation and hence, a high state on the input turns ON the specified output current component. The switch uses current steering for high speed and a termination amplifier consisting of an active load gain stage with unity gain feedback. The termination amplifier holds the parasitic capacitance of the ladder at a constant voltage during switching, and provides a low impedance termination for all legs of the ladder. The R–2R ladder network divides the reference amplifier current into binary-weighted components. The maximum output current obtainable for the highest binary input is 255/256 of the reference amplifier current, or 1.992 mA for a 2.0 mA reference amplifier current. Figure 6.12(a) shows an eight bit D/A converter circuit for unipolar output with 8 input data lines b1(MSB) through b8(LSB). The reference current of 2mA for full-scale is provided by two power supplies of values

262

Linear IC Applications

Fig. 6.12

MC1408 D/a converter circuit diagram for (a) Unipolar output and (b) Bipolar output

VCC = +5 V and VEE = –5 V. The resistor R14 with the voltage reference VR derive a total reference current, as given by IR =

VR 5 = 2 mA = R14 2.5 ¥ 103

The resistors R14 and R15 are selected such that their values match the input impedance of the reference source. The output current is given by

D/A and A/D Converters

ˆ VR Ê 8 bi 2- i ˜ , where b1 = 0 or 1. Â Á R14 Ë i =1 ¯ Then, the output voltage Vo becomes Io =

Vo =

b b ˘ VR Èb b R f Í 1 + 2 + 3 + ... + 8 ˙ R14 8 256 ˚ Î2 4

263

(6.17)

(6.18)

For input b8, ... b1 = 11111111, the output current Io is given by Io =

Ê 8 ˆ 255 = 1.992 mA b ¥ 2 - i ˜ = (2 ¥ 10 - 3 ) ¥ 3 ÁÂ i 256 2.5 ¥ 10 Ë i =1 ¯ 5

(6.19)

Therefore, the current output is 1 LSB value less than the full-scale reference current of 2 mA. Then, the output voltage Vo for the full-scale input of 11111111 is Ê 255 ˆ Vo = (2 ¥ 10 - 3 ) ¥ Á ¥ (5 ¥ 103 ) = 9.961 V Ë 256 ˜¯ The IC 1408 can also be calibrated for operating with bipolar output voltage levels from –5 V to +5 V as shown in Fig. 6.12(b). This is achieved by connecting resistor RB between VR and output pin 4. V The resistor RB provides a current of R = 1 mA to the output. This is in the direction opposite to that of the RB current generated by the input signal. Therefore, the output current for bipolar operation becomes 8 ÊV ˆ Ê V ˆ Ê ÊV ˆ -i ˆ I¢o = Io – Á R ˜ = Á R ˜ Á  bi ¥ 2 ˜ - Á R ˜ Ë RB ¯ Ë R14 ¯ Ë i =1 ¯ Ë RB ¯

When the binary input word is 00000000, the output is given by È ÊV ˆ˘ Ê 0-5 ˆ Vo = I o¢ ¥ R f = Í I o - Á R ˜ ˙ R f = Á ¥ 5 ¥ 103 = –5 V 3˜ R Ë ¯ ¥ 5 10 Ë ¯ B Î ˚ For the binary input word 10000000, the output Vo becomes È ÈÊ V ˆ Ê d ˆ Ê V ˆ ˘ ÊV ˆ˘ Vo = I o¢ ¥ R f = Í I o - Á R ˜ ˙ R f = ÍÁ R ˜ Á 1 ˜ - Á R ˜ ˙ R f Ë ¯ Ë RB ¯ Ë RB ¯ ˚ Î ÎË R14 ¯ 2 ˚ ÈÊ 5 ˆ Ê 1ˆ Ê 5 ˆ ˘ = ÍÁ ¥ 5 ¥ 103 = (1 - 1)¥ 10 - 3 ¥ 5 ¥ 103 = 0 3˜ Á Ë 2 ˜¯ ÁË 5 ¥ 103 ˜¯ ˙ . ¥ 2 5 10 Ë ¯ ˚ Î Similarly, for the binary input word of 11111111, the output Vo is given by ÈÊ V ˆ Ê 255 ˆ Ê VR ˆ ˘ -3 3 Vo = Í Á R ˜ Á ˜¯ - Á ˜ ˙ R f = (1.992 - 1) ¥ 10 ¥ 5 ¥ 10 Ë Ë RB ¯ ˚ ÎË R14 ¯ 256 = 0.992 ¥ 10–3 ¥ 5 ¥ 103 = 4.96 V

264

Linear IC Applications

Example 6.7

(i) (ii) (iii) (iv)

For the circuit of Fig. 6.12(a), calculate the output voltage Vo for digital input word of

00000000 01111111 10000000 11111111

Solution

The value of current for 1 LSB is 8 mA. Then, the full-scale current IFS = 8 ¥ 10– 6 ¥ 255 = 2.04 mA. (i) For digital input of 00000000, Io = 8 ¥ 10– 6 ¥ 0 = 0 I o¢ = 2.040 ¥ 10–3 – 0 = 2.04 mA Therefore, Vo = (2.040 ¥ 10–3) (5 ¥ 103) = –10.20 V Similarly, the values of Io, I o¢ and Vo calculated for (ii), (iii) and (iv) are summarised in Table 6.1. Table 6.1

Analog outputs for Example 6.7 (ii) to (iv) Digital Inputs

6.6

Analog Outputs

b8

b7

b6

b5

b4

b3

b2

b1

Negative full-scale

0

0

0

0

0

0

0

Negative zero

0

1

1

1

1

1

Positive zero

1

0

0

0

0

Positive full-scale

1

1

1

1

1

Vo (V)

Io (mA)

I¢o (mA)

0

0

2.040

1

1

1.016

1.024

–0.040

0

0

0

1.024

1.016

0.040

1

1

1

2.040

0

–10.20

10.20

A/d converters

An A/D converter does the inverse function of a D/A converter. It converts an analog signal into its equivalent n-bit binary coded digital output signal. The analog input is sampled at a frequency much higher than the maximum frequency component of the input signal. The digital output from an A/D converter can be in serial or parallel form. The A/D converter accepts an analog input vi and produces an output binary word b1, b2 ... bn of fractional value D such that D = b1 2-1 + b2 2-2 + ... + bn 2- n

(6.20)

where b1 is the MSB and bn is the LSB. The symbolic representation of an n-bit A/D converter is shown in Fig. 6.13(a). Two additional control pins START input and End of Conversion (EOC) output are provided with A/D converters. The START input initiates the conversion and the EOC announces when the conversion is complete. The output can be of parallel or serial form. Usually latches, control logic and buffers are provided to enable interfacing of the A/D converter to microprocessors or LCD/LED displays directly. Figure 6.13(b) shows the ideal characteristics of a 3-bit A/D converter with VFS = 1.0 V where VFS is the full-scale analog voltage. The A/D conversion process divides the analog input into 2n intervals. These intervals are called code ranges and all the values of vi falling within a code range are represented by the

D/A and A/D Converters

265

6 6 particular code. For instance, the code 110 corresponding to vi = V represents all inputs of value ± 8 8 1 1 V. Hence, the output can err by ± LSB. 16 2

Fig. 6.13

a/D converter (a) Symbolic representation (b) Ideal transfer characteristics and quantisation noise for a 3-bit a/D converter

The general block diagram of an A/D converter is shown in Fig. 6.14. It consists of an antialiasing filter or prefilter, Sample-and-Hold amplifier, a quantiser and an encoder. The prefilter avoids the aliasing of high frequency signals. The Sample-and-Hold circuit holds the input analog signal into the A/D converter at a constant value during the conversion time. The quantiser segments the reference voltage signal into subranges. Typically, for an n-bit digital output code, there are 2n subranges. The digital processor forms the encoder circuit which encodes the subrange into the corresponding digital bits. Therefore, the analog input signal is converted into an equivalent digital output code within the conversion time.

Fig. 6.14

General block diagram of an a/D converter

266

Linear IC Applications

specIfIcAtIons

6.7

of

A/d converter

Some important specifications, namely, accuracy, differential linearity, conversion time, input voltage range and resolution of A/D converters are discussed below.

Resolution The resolution refers to the finest minimum change in the signal which is accepted for conversion, and it is decided with respect to the number of bits. It can be defined as resolution = 1/2n, where n is the number of digital output word bits. The ratio of the full-scale input voltage range VFS to the resolution gives the minimum change of input voltage which can cause a change of 1 LSB at the output. This can be expressed as Dvi for 1 LSB =

VFS

(6.21) 2n where VFS is the full-scale input voltage range. If the number of bits used to represent a signal is larger, then the resolution improves. For example, if an 8-bit word is used, a maximum of 256 distinct values are available. If a maximum analog signal amplitude of 1V is used, then each step in the word represents

1V = 3.9 mV. If 16 bits are used for the same 1 V range, 256

then each step would produce 1 V/65536 = 15.26 mV. The digital output starts at 0 for an A/D converter. Therefore, the maximum full-scale input voltage which will cause the output to be all logic 1’s is 1 LSB less than the full-scale voltage range. viFS = VFS – 1 LSB

(6.22)

where viFS is the maximum input voltage which can produce all 1’s at the output. Example 6.8

An 8-bit A/D converter accepts an input voltage signal of range 0 to 10 V.

(a) What is the minimum value of the input voltage required to generate a change of 1 LSB? (b) What input voltage will generate all 1’s at the A/D converter output? (c) What is the digital output for an input voltage of 4.8 V? Solution

(a) From Eq. (6.21), 1 LSB =

10 28

= 39.1 mV

(b) From Eq. (6.22), viFS = 10V – 39.1 mV = 9.961 V. (c) The digital output for an applied input voltage of 4.8V is given by 4.8 V = 122.76 ª 123 39.1 mV Converting this to binary gives the digital output for an 8-bit A/D converter to be 01111011. D=

Quantisation Error A digital error in an A/D converter is based on the resolution of the digital system. In A/D conversion, a continuous analog voltage is represented by an equivalent set of digital numbers. When the digital numbers are converted back to analog voltage by a D/A converter, the output is a staircase waveform, which is a

D/A and A/D Converters

267

discontinuous signal composed of a number of discrete steps. The smallest digital step is due to the LSB and it can be made smaller only by increasing the number of bits in the digital representation. This error is called quantisation error, or digitizing error and it is commonly the bit. As shown in Fig. 6.13(b), the digital output 3 1 is 011 for all values of V ± LSB. Therefore, there is an uncertainty about the exact value of vi when the 8 2 1 output is 011. This uncertainty is called the quantisation error and its value is ± LSB. 2 Increasing the number of bits of A/D converter results in finer resolution and smaller quantisation error.

Analog Error Analog error in an A/D converter is mainly due to variations in the dc switching point of the comparator. The variations in switching are mainly due to offset, gain and linearity error of the operational amplifier used in the comparator. The other sources of analog error are the resistors in the A/D converter, the reference voltage source and the ripple and noise introduced by the circuit components.

Linearity Error This is an important measure of A/D converter performance. It is defined as a measure of the variation in voltage step size. This indicates the difference between the transitions for a minimum step of input voltage change. This is normally specified as a fraction of 1 LSB.

Differential Nonlinearity (DNL) Error The analog input levels that trigger any two successive output codes should differ by 1 LSB (DNL = 0) for an A/D converter. Any deviation from 1 LSB value is defined as DNL error. The counter type and continuous type A/D converters normally have better differential linearity than successive approximation type A/D converters.

Integral Nonlinearity (INL) Error

Dither The performance of A/D converters can be improved using dither. This is a very small amount of random noise (white noise) which is added to the input before A/D conversion. Its amplitude is set to half of the LSB value. Its effect is to cause the state of the LSB to randomly oscillate between 0 and 1 in the presence of very low levels of input, rather than sticking

111 110 101

b1b2b3

Figure 6.15 shows an actual A/D converter characteristic with a missing code. The dotted curve represents the locus of the midpoints of the actual input step voltage ranges. This line is called the code centre line. The maximum deviation of the code centre line from the straight line passing through the end points of the ideal characteristics after nulling the offset and gain errors is called Integral Nonlinearity error (INL).

Missing code

100 1 LSB

011 010 001 000 0

Fig. 6.15

1 8

2 8

3 4 8 8 vi (V)

5 8

6 8

7 8

a/D converter characteristic with a missing code

268

Linear IC Applications

at a fixed value. Instead of the signal simply getting cut-off altogether at this low level (which is only being quantised to a resolution of 1 bit), it extends the effective range of signals that the A/D converter can convert, at the expense of a slight increase in noise. Thus, the quantisation error is diffused across a series of noise values which is far less objectionable than a hard cut-off. The result is an accurate representation of the signal over time. A suitable filter at the output of the system can recover this small signal variation.

Conversion Time The time required for an A/D converter to convert an analog input value into its equivalent digital data is called the conversion time.

Input Voltage Range It is the range of voltage that an A/D converter can accept as its input without causing any overflow in the digital output.

6.8

clAssIfIcAtIon

of

A/d converters

The A/D converters (ADC) can be classified based on their operational features as follows.

Type I The A/D converters can be classified into two groups as (a) Programmed A/D converters (b) Non-programmed A/D converters In programmed A/D converters, the conversion is made in a fixed number of steps, with equal time intervals. For example, successive approximation type of A/D converter is a typical example of the programmed type of A/D converter. The non-programmed A/D converters may require a sequence of steps initially, and the time interval of the sequence of steps depends only on the response time of the conversion circuitry. The integrating type A/D converters fall in this category.

Type II The A/D converters are classified into two groups as (a) Closed-loop or feedback type A/D converters (b) Open-loop type A/D converters In closed-loop or the feedback type A/D converters, the analog voltage generated internally as a function of digital input is fed back to one input of the comparator. This voltage is compared with the analog voltage under conversion. When the input voltage and the feedback voltages are equal, the conversion is said to be complete. All D/A converter based A/D converters belong to this category. In open-loop converters, a direct comparison is made between the analog input voltage and a set of reference analog voltages. The result of the comparison forms a digital word at the output. The flash type A/D converters are typical examples of open-loop converters.

D/A and A/D Converters

269

Type III The A/D converters are classified into two groups as (a) Capacitor – charging type A/D converters (b) Discrete voltage comparison type A/D converters The capacitor charge-balancing type of A/D converter operates on the principle of charging the capacitor at a rate proportional to the input voltage, while simultaneously pulling out discrete charge packets out of the capacitor at a rate such that the net charge flow is always zero. The capacitor balancing integrating type of A/D converters belong to this category. Discrete voltage comparison type employs the principle of generation of discrete voltages whose levels are equivalent to digital words. The comparison for these discrete voltage levels is then made with the analog input voltage to determine the equivalent digital word. A/D converters based on weighted capacitor of D/A converters fall under this category.

Type IV The A/D converters are classified into two groups based on their conversion techniques as (a) Direct type A/D converters (b) Integrating type A/D converters. The direct type A/D converters compare a given analog signal with an internally generated equivalent analog signal. Flash (comparator) type A/D converter, Counter type A/D converter, Tracking or Servo operated A/D converter and Successive approximation A/D converter are direct type of A/D converters. The integrating type of A/D converters performs the A/D conversion in an indirect manner. It is a special class of converter which uses either a reference voltage, or integrates the signal during the conversion process. Therefore, they do not require S/H circuit at the input. The process of integrating the signals also improves the signal-to-noise ratio for certain type of analog signals. The integrating A/D converters are suitable only for very low frequency signals. For example, many of the digital voltmeters employ an integrating A/D converter in the circuit. The charge balancing type and dual slope A/D converters fall in this category.

6.8.1

Parallel Comparator or Simultaneous Type (Flash Type) ADC

The simultaneous type A/D converter is based on comparing an unknown analog input voltage with a set of reference voltages. To convert an analog signal into a digital signal of n output bits (2n – 1) number of comparators are required. For example, a 2-bit A/D converter requires 3 or (22 – 1) comparators, while a 3-bit converter needs 7 or (23 – 1) comparators. The block diagram of a 2-bit simultaneous type A/D converter is shown in Fig. 6.16. As shown in Fig. 6.16, the three op-amps are used as comparators. The non-inverting inputs of all the three comparators are connected to the analog input voltage. The inverting input terminal of the op-amps are connected to a set of reference voltages V/4, 2V/4 and 3V/4 respectively, which are obtained using a resistive divider network and power supply +V. The output of a comparator is in positive saturation state when the voltage at the non-inverting input terminal is more than the voltage at the inverting terminal and it is in negative saturation state otherwise. When the analog input voltage is less than V/4, the voltage at the non-inverting terminals of the three comparators is less than their respective inverting input voltages, and hence, the comparator outputs are C1 C2 C3 = 000.

270

Linear IC Applications

Fig. 6.16

Block diagram of 2-bit simultaneous type a/D converter

When the analog input is between V/4 and V/2, the comparator outputs are C1 C2 C3 = 100. Table 6.2 shows the comparator outputs for different ranges of analog voltage and their corresponding digital outputs. Table 6.2

Comparator and digital outputs for a 2-bit simultaneous type A/D converter

Analog Input Voltage ( Vi )

Comparator Outputs C1

C2

Digital Outputs C3

b2

b1

0 £ Vi £ V/4

0

0

0

0

0

V/4 £ Vi £ V/2

1

0

0

0

1

V/2 £ Vi £ 3V/4

1

1

0

1

0

3V/4 £ Vi £ V

1

1

1

1

1

Since there are four ranges of analog input voltages, this can be coded using a 2 bit digital output (b2, b1) as shown in Table 6.2. The coding circuit for encoding the three comparator outputs into two digital outputs is shown inside the dotted square of Fig. 6.16 using the simplified expressions for b1 and b2 as discussed below. From Table 6.2, logic expressions for b2 and b1 can be written as

(

)

b2 = C1C2 C3 + C1C2 C3 = C1C2 C3 + C3 = C1C2

(

b1 = C1 C2 C3 + C1C2 C3 = C1 C2 ≈ C3

)

(6.23) (6.24)

Similarly, a 3-bit A/D converter can be constructed using seven (23 – 1) comparators as shown in Fig. 6.17. The comparator and digital outputs for eight different ranges of analog input voltage are given in Table 6.3.

271

D/A and A/D Converters

Fig. 6.17

Table 6.3

Block diagram of 3-bit simultaneous type a/D converter

Comparator and digital outputs for 3-bit simultaneous type A/D converter

Analog Input Voltage ( V) 0 £ Vi £ V/8 V/8 £ Vi £ 2V/8 V/8 £ Vi £ 3V/8 V/8 £ Vi £ 4V/8 V/8 £ Vi £ 5V/8 V/8 £ Vi £ 6V/8 V/8 £ Vi £ 7V/8 V/8 £ Vi £ V

Comparator Outputs C1 0 1 1 1 1 1 1 1

C2 0 0 1 1 1 1 1 1

C3 0 0 0 1 1 1 1 1

C4 0 0 0 0 1 1 1 1

C5 0 0 0 0 0 1 1 1

Digital Outputs C6 0 0 0 0 0 0 1 1

C7 0 0 0 0 0 0 0 1

b3 0 0 0 0 1 1 1 1

b2 0 0 1 1 0 0 1 1

b1 0 1 0 1 0 1 0 1

272

Linear IC Applications

From Table 6.3, it is clear that the logic expressions for (b3, b2 and b1) are complex due to their dependence on seven input variables (C1, C2, ... C7). Hence, the coding circuit is implemented using a priority encoder. The IC 74148 is an 8 to 3 priority encoder with active LOW inputs and outputs. Since the comparator outputs are active HIGH, they are connected to the inputs of encoder through inverters and the outputs of encoder are inverted once again to get active HIGH digital outputs b3, b2 and b1 as shown in Fig. 6.18. The El and Eo signals are the Enable Input and Enable Output active Low signals for the IC.

Eo

Fig. 6.18

Output Enable

Logic diagram of 3-bit simultaneous type a/D converter

Advantages (i) Simultaneous type A/D converter is the fastest because A/D conversion is performed simultaneously through a set of comparators. Hence, it is also called flash type A/D converter. Typical conversion time is 100 ns or less. (ii) The construction is simple and easier to design.

Disadvantages The simultaneous type A/D converter is not suitable for A/D conversion with more than 3 or 4 digital output bits. It is because of the fact that (2n – 1) comparators are required for an n-bit A/D converter and the number of comparators required doubles for each added bit.

D/A and A/D Converters

6.8.2

273

Counter Type A/D Converter

The counter type A/D converter is constructed using only one comparator with a variable reference voltage. The variable reference voltage can be obtained by a sequence counter and a D/A converter. The block diagram for an n-bit counter type A/D converter is shown in Fig. 6.19(a).

Fig. 6.19

Counter type a/D converter (a) Block diagram

Vd Volts

Va

Counter stops

0

1

2

3

4

5

6

7

8

9 10

0

1

2

Clock Reset

End reset

Fig. 6.19

Begin reset

End reset

(b) Counter type a/D converter (b) Output staircase waveform

The operation of the counter type A/D converter is as follows. The n-bit binary counter is initially set to 0 by the Reset switch which is normally active LOW. Therefore, the digital output is zero and the analog equivalent Vr is also 0. When Reset signal is released (HIGH), the clock pulses gated through the AND gate are counted by the binary counter. The D/A converter converts the digital output to an analog voltage and supplies it as the inverting input to the comparator. The output of the comparator enables the AND gate to pass the clock. The number of counted pulses increases with time and the analog input Vr is a rising staircase waveform as shown in Fig. 6.19(b).

274

Linear IC Applications

The counting will continue until the reference voltage Vr equals and just rises more than Vi . Then the comparator output becomes LOW and this disables the AND gate from passing the clock. The counting stops at the instance Vi > Vr and at that instant the digital output of the comparator represents the analog input voltage Vi . Then the clock is inhibited, the counter stops its progress and the conversion is said to be complete. The numbers stored in the n-bit counter is the equivalent n-bit digital data for the given analog input voltage. In this A/D converter, the counter advances by one count for every clock pulse, and therefore, the clock speed decides the conversion speed. For example, if a 100 kHz clock is used in an 8-bit A/D converter, the 1 = 2.56 ms to reach the full-scale counter advances for every step and it will take 2.56 ms i.e. 28 ¥ 100 kHz digital output (i.e. 28 ¥ 10 ms = 256 ms). Normally, the time required to reach one half of the full-scale voltage is called average conversion time. Hence, the average conversion time of the above A/D converter is 1.28 ms.

(

)

Advantages (i) The counter type A/D converter is very simple and needs less hardware compared to the simultaneous type A/D converter. (ii) This is suitable for digitising applications with high resolution.

Disadvantages In counter type A/D converter, the conversion time is very long, variable and proportional to the amplitude of the analog input voltage. Since the counter always counts from 0 through a normal sequence, a maximum of 2n counts are required to convert a full-scale analog input voltage. Hence, for an n-bit A/D converter, the average conversion time is 2n /2 = 2n–1 times the clock period, which can be very long for large value of n.

6.8.3

Successive Approximation Type A/D Converter

The conversion time is maintained constant in successive approximation type A/D converter, and it is proportional to the number of bits in the digital output, unlike the counter and continuous type A/D converters. The basic principle of this A/D converter is that the unknown analog input voltage is approximated against an n-bit digital value by trying one bit at a time, beginning with the MSB. The principle of successive approximation process for a 4-bit conversion is shown in Fig. 6.20. This type of A/D converter operates by successively dividing the voltage range by half, as explained in the following steps. (i) The MSB is initially set to 1 with the remaining three bits set as 0. The digital equivalent is compared with the unknown analog input voltage. (ii) If the analog input voltage is higher than the digital equivalent, the MSB is retained as 1 and the second MSB is set to 1. Otherwise, the MSB is reset to 0 and the second MSB is set to 1. (iii) Comparison is made as given in step 1 to decide whether to retain or reset the second MSB. The third MSB is set to 1 and the operation is repeated down to LSB and by this time, the converted digital value is available in the SAR. From Fig. 6.20, it can be seen that the conversion time is constant (i.e., four cycles for 4-bit A/D converter) for various digital outputs. This method uses a very efficient search strategy to complete an n-bit conversion in just n-clock periods. Therefore, for an 8-bit successive approximation type A/D converter, the conversion requires only 8 cycles, irrespective of the amplitude of analog input voltage.

D/A and A/D Converters

Fig. 6.20

275

Successive approximation principle for 4-bit digital output

The functional block diagram of successive approximation type A/D converter is shown in Fig. 6.21. The circuit employs a successive approximation register (SAR) which finds the required value of each successive bit by trial and error method. The output of the SAR is fed to an n-bit D/A converter. The analog output equivalent of the D/A converter is applied to the non-inverting input of the comparator, while the other input of the comparator is connected with an unknown analog input voltage V i under conversion. The comparator output is used to activate the successive approximation logic of SAR. When the START command is applied, the SAR sets the MSB (b1) of the digital signal, while the other bits are made zero, so that the Fig. 6.21 Functional block diagram of successive approximation type a/D converter trial code becomes 1 followed by zeros. For example, for an 8-bit A/D converter the trial code is 10000000. The output of the SAR is converted into analog equivalent Vr and gets compared with the input signal Vi. If Vi is greater than the D/A converter output, then the trial code 10000000 is less than the correct digital value. The MSB is retained as 1 and the next significant bit is made 1 and the testing is repeated. If the analog input Vi is now less than the D/A converter output, then the value 11000000 is

276

Linear IC Applications

greater than the exact digital equivalent. Therefore, the comparator resets the second MSB to 0 and proceeds to the next most significant bit. This process is repeated for all the remaining lower bits in sequence until all the bit positions are tested. The EOC signal is sent out when all the bits are scanned and the value of D/A converter output just crosses Vi. Table 6.4 shows the flow of conversion sequence and Fig. 6.22 shows the output response with the associated waveforms. It can be observed that the D/A converter output voltage gets successively closer to the analog input voltage Vi. For an 8-bit A/D converter, it requires 8 pulses to compute the output irrespective of the value of Fig. 6.22 Output response for an analog input the analog input. Table 6.4

Successive approximation conversion sequence

Correct Digital Representation

Successive Approximation Register (SAR) Output Vi at Different Stages in the Conversion

Comparator Output

11010100

10000000

1 (initial output)

11000000

1

11100000

0

11010000

1

11011000

0

11010100

1

11010110

0

11010101

0

11010100 Example 6.9 An 8-bit successive approximation A/D converter is driven by a 2 MHz clock signal. Find the conversion time required. Solution

1 = 0.5 ms. 2 MHz The time required to perform the calculation is the sum of (i) the time required for resetting SAR before performing the conversion, and (ii) the time required for performing the conversion. Therefore, the total number of clock pulses required for the conversion is given by

The time for one clock pulse =

(8 + 1 = 9 ) clock cycles = 9 ¥ 0.5 ms = 4.5 ms

Advantages of Successive Approximation Type ADC A comparison between an 8-bit continuous type A/D converter and an 8-bit successive approximation A/D converter is shown in Fig. 6.23. Generally the successive approximation technique is more versatile and superior. Only n number of comparisons are needed for an A/D conversion process for an n-bit digital output.

D/A and A/D Converters

Fig. 6.23

277

Speed comparison of successive approximation and tracking a/D converters

Successive approximation ICs are available as monolithic circuits. The AD7582 from Analog Devices Corporation provides a 28-pin DIP CMOS package for 12-bit A/D conversion using successive approximation technique.

6.8.4

Dual Slope Type A/D Converter

In dual slope type A/D converter, the integrator generates two different ramps, one with the unknown analog input voltage Vi as the input, and another with a known reference voltage (–VR) as the input. Hence, it is called dual slope type A/D converter. Its logic diagram is shown in Fig. 6.24(a) and the dual ramp output waveform in Fig. 6.24(b).

Fig. 6.24

(a) Logic diagram of dual slope type a/D converter

278

Linear IC Applications

The operation of dual slope type A/D converter is explained as follows. Assume that the 4-digit decade counter is initially reset to 0000, the ramp output Vs is reset to 0 V, analog input voltage is positive, and the input to the ramp generator or integrator is switched to the unknown analog input voltage. Since the positive analog input voltage is connected to the inverting input of the integrator, – the integrator output Vs is a negative ramp while the comparator output Vg is positive, and the CLK is passed through the AND gate. This results in counting-up of the 4-digit decade counter. The negative ramp will proceed for a fixed time period Fig. 6.24 (b) Dual ramp output waveform T1, which is determined by a count detector for the time period T1. At the end of fixed time period T1, the ramp voltage is given by Vi ¥ T1 (6.25) RC where RC is the time constant of the ramp generator circuit. When the counter reaches the fixed count at time period T 1, the count detector gives a signal to the control circuit which in turn resets the counter to 0 and switches the integrator input to a negative reference voltage (–VR). Now, the ramp generator begins at –Vs and increases upward until it reaches 0 V. During this time, the counter gets advanced. When Vs reaches 0 V, the comparator output will become 0 and the CLK is inhibited from passing through the AND gate. Now, the conversion cycle is said to be completed and the positive ramp voltage is given by –Vs =

Ê -V ˆ Vs = - Á R ¥ T2 ˜ Ë RC ¯

(6.26)

where VR and RC are constants and the time period T2 is variable. Since the ramp generator voltage starts at 0 V, decreasing down to –Vs and then increasing up to 0 V, the amplitude of negative and positive ramp voltages can be equated as follows: V – Vi ¥ T1 = R ¥ T2 RC RC T Therefore, –Vi = VR ¥ 2 T1

(6.27) (6.28)

From the above equation, it is clear that the unknown analog input voltage is proportional to the time period T2, because VR is a known reference voltage and T1 is the predetermined time period. Also, the contents of the 4-digit decade counter at the end of conversion reflect the variable time period T2. For example, consider the frequency of CLK is 1 MHz, the reference voltage is –1.0 V, the fixed time period T1 is 1 ms and the RC time constant is set at RC = 1 ms. Assuming the unknown analog input voltage amplitude as Vi = 5 V, during the fixed time period T1, the integrator output Vs will go down to Vs =

-5 - Vi ¥ 1 ms = –5 V ¥ T1 = 1 ms RC

D/A and A/D Converters

279

Then, during the time period T2, Vs will integrate all the way back to 0 V. That is,

T2 =

Vs 5 ¥ RC = ¥ 1 ms = 5 ms = 5000 ms VR 1

Hence, the 4-digit counter value is 5000, and by activating the decimal point of MSD seven segment displays, the display can directly read as 5 V. Example 6.10 For a particular dual slope ADC, T1 = 83.33 ms and the reference voltage is 100 mV. Calculate T2 if (a) V1 = 100 mV and (b) V1 = 200 mV. Solution

The reference voltage is 100 mV and T1 = 83.33 ms. (a) The analog input voltage amplitude is Vi = 100 mV. –Vi = Vr ¥ (T2/T1) –100 mV = 100 mV ¥ (T2/83.33 ms) Hence, T2 = 83.33 ms (b) –Vi = Vr ¥ (T2/T1) –200 mV = 100 mV ¥ (T2/83.33 ms) Hence, T2 = 166.66 ms

6.9 6.9.1

specIfIcAtIons

of

Ad574 (12-BIt Adc)

General Description

The AD574A is a complete 12-bit successive-approximation analog-to-digital converter with tri-state output buffer circuitry for direct interface to an 8 or 16-bit microprocessor bus. A high precision voltage reference and clock are included on-chip, and the circuit guarantees full-rated performance without external circuitry or clock signals. The AD574A design is implemented using Bipolar/I2L process from Analog Devices. It integrates all analog and digital functions on one chip. Offset, linearity and scaling errors are minimized by active lasertrimming of thin-film resistors at the wafer stage. The voltage reference uses an implanted buried Zener for low noise and low drift. On the digital side, I2L logic is used for the successive-approximation register, control circuitry and tristate output buffers. The AD574A is available in six different grades. The AD574AJ, K, and L grades are specified for operation over the 0°C to +70°C temperature range. The AD574AS, T and U are specified for the -55°C to + 125°C range. The IC is available in 28-Pin ceramic and Plastic DIP packages, 28-terminal PLCC and LCC Packages. The important features of this IC are (i) The AD574A interfaces to most 8- or 16-bit microprocessors. Multiple-mode tristate output buffers connect directly to the data bus while the read and convert commands are taken from the control bus. (ii) The 12 bits of output data can be read either as one 12-bit word or as two 8-bit bytes (one with 8 data bits, the other with 4 data bits and 4 trailing zeros). (iii) The precision, laser-trimmed scaling and bipolar offset resistors provide four calibrated ranges: 0 volts to + 10V and 0 volts to +20V unipolar, –5 volts to +5 volts and –10V to +10V bipolar. (iv) The internal buried Zener reference is trimmed to 10V. The reference is available externally and can drive up to 1.5 mA. (v) AD674B and AD774B provide higher speed and pin compatible alternative choices.

Linear IC Applications

+5V

1

12/8

2

28 STS

MSB

27 DB11

Nibble A

280

26 DB10

Control CS

3

AO

4 Clock

SAR

25 DB9

12 3

R/C 5

24 DB8

12

VCC

7

Ref out

8

Analog common

9

3K

23 DB7

– + COMP

10 V Ref

IDAC = 4 × N × Iref

Nibble B

6

State Output Buffers

CE

22 DB6

21 DB5

20 DB4 19.95 K Iref

19 DB3

8K

–12/–15 V VEE 11 + 9.95 K

–

BIP OFF 12

Nibble C

Ref in 10

18 DB2

LSB

16 DB0

17 DB1

5K VEE

DAC

10 Vin 13

12

5K 20 Vin 14

15

Fig. 6.25

Functional Block Diagram and pin Configuration

Digital common

D/A and A/D Converters

281

ABSOLUTE MAXIMUM RATINGS (Taken from Data Sheet from Analog Devices®.) VCC to Digital Common VEE to Digital Common VLOGIC to Digital Common Analog Common to Digital Common Control Inputs (CE, CS, AO 12/8, R/C) to Digital Common Analog Inputs (REF IN, BIP OFF, 10 VIN) to Analog Common 20 VIN to Analog Common REF OUT Chip Temperature Power Dissipation Lead Temperature (Soldering, 10 sec). Storage Temperature (Ceramic)

6.9.2

0 V to +16.5 V 0 V to –16.5 V 0 V to +7 V ±1V –0.5 V to VLOGIC + 0.5 V VEE to VCC ± 24 V Indefinite Short to Common Momentary Short to VCC 175°C 825 mW +300°C –65°C to +150°C (Plastic) –25°C to +100°C

Functional Description

The AD574A requires no additional components to provide the complete successive approximation A/D conversion function. The block diagram of AD574A is shown in Fig. 6.25. When the control section starts a conversion, it enables the clock and resets the SAR to all zeros. Once a conversion cycle has begun, it cannot be paused or restarted, and data is not available from the output buffers. The SAR, timed by the clock, will sequence through the conversion cycle and return an end-of-convert flag to the control section. The control section will then disable the clock, bring the output status flag low, and enable control functions to allow data read functions by external command. During the conversion cycle, the internal 12-bit current output DAC is sequenced by the SAR from the most significant bit (MSB) to least significant bit (LSB) to provide an output current which accurately balances the input signal current through the 5 kΩ or 10 kΩ input resistor. The comparator determines whether the addition of each successively weighted bit current causes the DAC current sum to be greater or less than the input current; if the sum is less, the bit is left on; if more, the bit is turned off. After testing all the bits, the SAR contains a 12-bit binary code which accurately represents the input signal to within ±1/2 LSB. The temperature-compensated buried–Zener reference provides the primary voltage reference to the DAC and guarantees excellent stability with both time and temperature. The reference is trimmed to 10V ± 0.2. The thin-film application resistors are trimmed to match the full-scale output current of the DAC. The ADC is operated using either 10V or 20V range. Analog input is connected between pins 13 and 9 for 10V range and between the terminal pins 14 and 9 for operating in 20V range. Figures 6.26 and 6.27 show the input connections for unipolar and bipolar modes of operation of the IC. In the unipolar mode, the range of operation is 0 to 10V in 10V range or 0 to 20V in 20V range. The tristate buffer circuits at the output provide means of interfacing the ADC to 8-bit or 16-bit data bus. The high precision reference and clock are provided in the IC.

6.9.3

Unipolar Range Connections for the, AD574A

The analog input is connected between Pin 13 and Pin 9 for a 0 V to +10 V input range, between 14 and Pin 9 for a 0 V to +20 V input range. The LSB has a nominal value of 2.44mV for the 10V span input and it is 4.88mV for the 20V span input. The AD574A is intended to have a nominal 1/2 LSB offset so that the exact analog input for a given code will be in the middle of that code (halfway between the transitions to the

282

Linear IC Applications

2 12/8 OFFSET R1 100k

STS 28

3 CS 4 AO

–12V/–15V

+12V/+15V

HIGH 27 BIT 24

5 R/C

MIDDLE 23 BITS 20 AD574A LOW 19 BITS 16 10 REF IN 6 CE

GAIN 100k R2 100Ω

8 REF OUT

100Ω 12 BIP OFF +5V 1

0 TO + 10 V 13 10VIN

ANALOG INPUTS

+15V 7 14 20VIN

–15V 11

0 TO + 20 V 9 ANA COM DIG COM 15

Fig. 6.26

Unipolar Operation of aD574a

2 12/8

STS 28

3 CS 4 Ao

HIGH 27 BITS 24

5 R/C

MIDDLE 23 BITS 20 AD574A LOW 19 BITS 16 10 REF IN 6 CE

R2 100Ω GAIN

8 REF OUT OFFSET

12 BIP OFF R1 100Ω

+5V 1

± 5V 13 10VIN

ANALOG INPUTS

14 20VIN

+15V 7 –15V 11

± 10V 9 ANA COM DIG COM 15

Fig. 6.27

Bipolar Operation of aD574a

D/A and A/D Converters

283

codes above and below it). Thus, the first transition (from 0000 0000 0000 to 0000 0000 0001) will occur for an input level of +1/2 LSB which is 1.22 mV for 10 V range. Figure 6.26 shows the unipolar operation with the IC 574.

6.9.4

Bipolar Range Connections of AD574A

The connections for bipolar ranges are shown in Figure 6.27. As for the unipolar ranges, if the offset and gain specifications are sufficient, one or both of the trimmers shown can be replaced by a 50 Ω ± 1% fixed resistor. Bipolar calibration is similar to unipolar calibration.

6.9.5

Operation of AD574A

The control signals Chip Enable (CE), Chip Select (CS) and read/convert (R/(C ¯) control the operation of ADC. Inputs A0 and 12/8¯ control the conversion length and the data output format. When the analog to digital conversion starts with A0 low, a full 12-bit conversion is initiated and with A0 in logic High, the 8-bit conversion is initiated. If the input at 12/8¯ is Low when the conversion is complete, the tristate buffer contains the 8 bit MSBs when A0 is Low, or 4 LSBs of the 12-bit data when A0 is High. This in effect facilitates interfacing the ADC to 8-bit data bus of a digital system. If the 12/8¯ input is High when the conversion is over, the tristate output buffer contains the full 12-bit data. It enables the interfacing of the ADC to 16-bit data bus. The status of the converter is indicated by the STS output signal. STS goes High at the beginning of a conversion process and returns to Low when the conversion cycle is complete. The timing diagram is shown in Fig. 6.28. R/C

tc

STS D11-D0

High impedance

Data valid Fig. 6.28

6.9.6

Data valid

timing diagram

Control Logic

The AD574A contains on-chip logic to provide conversion initiation and data read operations from signals commonly available in microprocessor systems. Table 6.5 shows the control signals and the operation details of AD574A. Table 6.5

AD574A Truth Table CE

CS

R/C

12/8

Ao

Operation

0

X

X

X

X

None

X

1

X

X

X

None

1

0

0

X

0

Initiate 12-Bit Conversion

1

0

0

X

1

Initiate 8-Bit Conversion

1

0

1

Pin 1

X

Enable 12-Bit Parallel Output

1

0

1

Pin 15

0

Enable 8 Most Significant Bits

1

0

1

Pin 15

1

Enable 4 LSBs + 4 Trailing Zeroes

284

Linear IC Applications

6.9.7

Supply decoupling and Grounding Considerations

Filtered, well regulated and high frequency noise free power supplies need to power the IC 574, since a few millivolts of noise represents several counts of error in a 12-bit ADC. Decoupling capacitors are to be used on all power supply pins. The analog common at Pin 9 is the ground reference point for the internal reference and is thus the high quality ground for the AD574A. The analog and digital commons should be connected together at the package.

Interfacing AD574A to Digital Systems The AD574A is microprocessor compatible and it can be interfaced to a wide variety of microprocessors and other digital systems. AD574A can be interfaced to the system bus directly. The ADC can be used in a stand-alone mode, which is useful in systems made available with dedicated input ports. Hence, full bus interface capability will not be required in such conditions. The typical A/D conversion routine involves the following steps: 1. The control logic of the AD574A makes direct connection to most microprocessor systems busses. 2. A write to the ADC initiates a conversion process. 3. The processor then waits for the conversion cycle to complete, since the conversion process may take more than one instruction cycle to complete. 4. Valid data can be read after the conversion is complete. 5. The ADC provides an output signal STS which indicates when a conversion is in progress. This signal can be polled by the processor by reading through an external tristate buffer, or any other designated input port. 6. The STS signal can also be connected to an interrupt routine. 7. Once it is established that the conversion is complete, the data can be read. In case of converters with more data bits than are available on the bus, multiple read operations may be required by following a choice of data format.

D/A and A/D Converters

285

Review Questions 6.1 What do you mean by data converters?

B

6.2 Define D/A conversion.

A

6.3 Distinguish full-scale error and linearity error B of a D/A converter. 6.4 Describe the various specifications of a D/A B converter. 6.5 What do you understand by offset error in a A D/A converter? 6.6 Define (i) Monotonicity and (ii) Settling time A of a D/A converter. 6.7 What is meant by the resolution of a D/A A converter? 6.8 A system uses a 16-bit word to represent the input signal. If the maximum peak-to-peak voltage at the output is set for 5V, find the resolution of the system and the dynamic B range. 6.9 A 16-bit D/A converter has an output of voltage range from 0 to 2.55 V. Find the B resolution of the system. 6.10 A 4-bit D/A converter has a resolution of 10 mV/bit. Find the analog output voltage C for the inputs (i) 1010 and (ii) 0001. 6.11 How many bits are required to design a D/A converter, that can have a resolution of 5 mV? C The ladder has +8V full scale. 6.12 Determine the output voltage produced by a 4-bit DAC whose output voltage range is 0 to 10 V, when the input binary number is 0110. C

6.13 List the essential parts of a D/A converter. A 6.14 Explain the 4-bit weighted resistor type D/A A converter in detail. 6.15 What are the limitations of weighted resistor A type D/A converter? 6.16 How many resistors are required for an 8-bit weighted resistor D/A converter? What are those resistance values, assuming the C smallest resistance is R?

6.17 What are the advantages of R–2R ladder type D/A converter over weighted resistor type? B 6.18 Explain a 4-bit R–2R ladder type D/A B converter in detail. 6.19 What is the advantage of inverted R–2R ladder network D/A converter over R–2R B ladder D/A converter? 6.20 The inverted R–2R ladder shown in Fig. 6.10 has R = R f = 22 kW and VR = 12 V. Calculate the total current delivered to the op-amp and the output voltage when the binary input is C 1110. 6.21 Differentiate between current-mode and voltage-mode R–2R ladder D/A converters. C Explain. 6.22 Explain the functional diagram and operating A principle of a D/A converter IC. B 6.23 What is the need for A/D converter? 6.24 What are the different types of A/D A converters? 6.25 How do you classify the A/D converters A based on their operational features? 6.26 Describe various specifications of an A/D A converter. 6.27 Determine the resolution of an 8-bit A/D B converter for a 10V input range. 6.28 What do you mean by quantisation error in an ? A/D converter? 6.29 Define aliasing error. A 6.30 What are the sources of analog error in an A A/D converter? 6.31 What is meant by differential linearity of an A A/D converter? 6.32 Define the conversion time of an A/D A converter. 6.33 What is the resolution of an A/D converter? A

6.34 What is the minimum quantisation error that B can be achieved in an A/D converter?

286

Linear IC Applications

6.35 An 8-bit A/D converter accepts an input voltage signal of range 0 to 12 V. (i) What is the minimum value of the input voltage required to generate a change of 1 LSB? (ii) What input voltage will generate all 1s at the A/D converter output? (iii) What is the digital output for an input C voltage of 6 V? 6.36 Explain a typical simultaneous type A/D A converter in detail. 6.37 Design a 3-bit simultaneous type A/D B converter. 6.38 What are the limitations of simultaneous type B A/D converter? 6.39 Which type of A/D converter is faster? Why? B

6.40 What is Flash type A/D converter? Why is it B called so? 6.41 Describe the successive approximation A/D A conversion principle.

6.42 With a neat block diagram, explain successive approximation type A/D converter in detail. A

6.43 Describe the operation of dual slope A/D A converter with necessary diagrams. 6.44 Explain the principle of operation and functional diagram of any one A/D converter A IC. 6.45 Explain a microprocessor compatible ADC A IC with its functional diagram. 6.46 An 8-bit D/A converter has a resolution of 10 mV. Find the full-scale voltage and the output voltage when the input is 1100000. C 6.47 What is the maximum resistor ratio used in a 12-bit binary-weighted D/A converter C circuit? 6.48 For a 4-bit R–2R ladder D/A converter assume that the full-scale voltage is 10 V. Calculate the step change in output voltage when the input changes from 1001 to 1110. C

Objective-Type Questions 6.1 The process of transforming an analog signal into digital representation is called (a) quantization (b) digitizing (c) sampling (d) all of these B 6.2 Resolution of n-bit word analog to digital converter is 1 1 (a) (b) n n 2 (2 - 1) 1 1 C (c) (d) n-1 n-1 (2 ) (2 - 1) 6.3 The minimum sampling rate of an input signal of frequency fi is (a) greater than 2 fi (b) 2 fi (c) less than 2 fi (d) none of these A

6.4 The Nyquist frequency is _____________ the sampling frequency (a) twice (b) greater than A (c) less than (d) one-half 6.5 The fastest analog to digital converter is _____ type. (a) successive approximation (b) flash (c) counter type A (d) dual-slope 6.6 The smoothing filter contains (a) high-pass filter (b) all stop filter (c) all pass filter (d) low-pass filter B

6.7 Successive approximation ADC does not A require an internal DAC. (True/False)

D/A and A/D Converters

6.8 Quantization error of ADC and DAC is given by 1 1 (a) ± LSP (b) ± Vin 2 2 1 1 C (c) ± VLSB (d) ± vo 2 2 6.9 Weighted resistor D/A converter consists of (a) decade weighted resistor network (b) binary-weighted resistor network B (c) none of these 6.10 The resolution of a 4-bit R-2R ladder D/A converter with a reference voltage of 5 V and R = 10 kW is (a) 62.5 mA (b) 31.25 mA (c) 125 mA (d) none of these C

6.11 The resolution of the R/2R ladder type D/A converter with voltage output is given by (a)

(c)

VR 2 RR f

(b)

n

Rf R

(d)

VR ¥ Rf 2n R C

V R 2n VR 6.12 Current-mode R-2R ladder D/A converter has the advantage of (a) avoiding power dissipation (b) maintaining constant power dissipation and stray capacitances do not affect the circuit operation

(c) reducing power dissipation B (d) none of these 6.13 Differential nonlinearity error (DNL) defines the (a) deviation from 1 MSB (b) deviation from 1 LSB (c) deviation between two steps A (d) none of these 6.14 Open-loop A/D converters use D/A converter. A (True/False) 6.15 Closed-loop A/D converters use D/A A converter. (True/False) 6.16 Dual-slope A/D converters belong to integrating type A/D converters. (True/False) B

6.17 Dual-slope A/D converters belong to direct B type A/D converters. (True/False) 6.18 Successive approximation type A/D converter processes the bits starting from (a) MSB (b) LSB (c) the first 1 bit (d) any of these B 6.19 Fastest A/D converter is successive B approximation type. (True/False)

Answers to Objective-Type Questions 6.1 6.6 6.11 6.16

(d) (d) (b) (b)

6.2 6.7 6.12 6.17

(a) False (b) (b)

6.3 6.8 6.13 6.18

(b) (c) (a) (b)

287

6.4 6.9 6.14 6.19

(d) (b) (a) (b)

6.5 (b) 6.10 (b) 6.15 (a)

288

Linear and IC Application

SET – 1 III B. Tech I Semester Supplementary Examinations, May – 2017 LINEAR IC APPLICATIONS (Common to Electronics and Communication Engineering, Electronics and Instrumentation Engineering and Electronics and Computer Engineering)

1. The LSB of 10 bit DAC is 20 mV. Calculate output voltage for an input 1011001101. Solution The decimal equivalent value D = b10 29 + b9 28 + b8 27 +  + b1 20 For input = 1011001101, D = (1) 29 + ( 0) 28 + (1) 27 + (1) 26 + 0 + 0 + (1) 23 + (1) 22 + 0 + (1) 20 = 512 + 128 + 64 + 8 + 4 + 1 = 717 1 LSB = 20 mV . Output voltage Vo = 717 3 20 mV = 14.34 V 2. For a dual input balanced output differential amplifier, RC = 47kW, RS 1 = RS 2 = 20kW, R1 = 43kW, hfe = 75, hie = 20k, Vce = 9V, VEE = –9V and VBE 0.7V. Calculate the operating point values. Solution (i) To determine the operating point: I CQ = I E =

VEE − VBE R 2 RE + S h fe

=

(

−9.7 −9 − 0.7 = = −10 m A 3 96266 .67 20 × 10 2.453 × 103 + 75

)

(

)

−6 3 VCEQ = VCE + VBE − I CQ Rc = 9 + 0.7 − −10 × 10 × 47 × 10 = 10.17 V

h R 75 × 47 × 103 (ii) Ad = Vo = 1 fe c = 1 = 44.0625 2 Rs + hie Vs 2 20 × 103 + 20 × 103 (iii) Ac =

− h fe Rc

(

)

R3 + hie + 1 + h fe 2 RE

(iv) CMRR =

=

−75 × 47 × 103 = −0.480 20 × 103 + 20 × 103 + (1 + 75) 2 × 43 × 103

Ad 44.0625 = = 91.796 0.480 Ac

LIC A JNTU K Solved Questions

4. Design a practical integrator circuit with dc gain of 20 to integrate a square wave of 25 KHz. Rf

V

Cf

R1 – +

Rcmp = R, II R f

Fig. 1 Solution Given

Rf

= 20

Ri We know that

R f /R i

A =

(

1 + w Rf Cf

)

2

3

At w = 2p f = 5 0 × 10 p rad/sec, the gain drops by i.e.,

A=

1  Rf  2  R1 

Substituting, we get

Rf 1

Rf

R1

=

2 R1

1 + w 2 Rf 2 C f2

1+ w 2 Rf 2 C f2 = 2 1 + w 2 Rf 2 C f 2 = 2

w 2 C f 2 Rf 2 = 1 Let

C f = 0.01m F 2

−6 2

(50 × 10 p ) × (0.01 × 10 ) 3

× Rf 2 = 1

R f ≅ 0.64 MΩ i.e.

R f ≅1MΩ (select)

Therefore,

R1 =

Rf 20

=

1 × 103 = 50kΩ 20

1 times from its peak value of 20. 2

289

290

Linear and IC Application 1 MW

0.01 mF

50 KW – +

Rcmp ≅ 50 KW

Fig. 2 5. Design a multiple feedback narrow band pass filter with fr = 1kHz, Q = 3 and Af = 10 C = 0.01 m F

C 2R

95.4 KW 47.7 KW

R V1

– C

+

V0

C = 0.01 m F –

V2 2.8 KW

Rv

Fig. 3 Solution Given f r = 1 kHz , Q = 3 and Af = 10 BW =

f r 1 × 103 = = 333.3 Hz Q 3

Let C = 0.01mF We know that BW = Therefore, R =

0.1591 RC

0.159 = 47.7 kΩ 333.3 × 0.01 × 10-6

Hence, 2 R = 95.4 kΩ Here, Rr =

R 47.7 × 103 = 2.8kΩ = 2Q 2 − 1 2 × (3)2 − 1

Fig. 4

+

V0

LIC A JNTU K Solved Questions

291

SET – 4 III B. Tech I Semester Regular/Supplementary Examinations, October/Novemeber – 2017 LINEAR IC APPLICATIONS (Common to Electronics and Communication Engineering, Electronics and Instrumentation Engineering and Electronics and Computer Engineering)

3 (b) An op-amp has a slew rate of 2 V/ms. What is maximum frequency of an output sinusoid of peak value 5V which will not be affected by the slew rate limitation. Solution Given

SR = 2V/ m s and Vm = 5V

We know that Slew Rate S R = 2p fm VmV/s Therefore, f max =

SR × 10 6 2p Vm

2 × 10 6

= 2p × 5

= 64kHz