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Table of contents :
Cover
Contents
Chapter 1: NUMBER SYSTEM
1.1 Introduction
1.2 Analog Systems
1.3 Digital Systems
1.4 Limitations of Digital Systems
1.5 Digital Number Systems
1.6 Binary Arithmetics
1.7 Signed Magnitude
1.8 One’s Complement
1.9 Two’s Complement
1.10 Subtraction by using Two’s Complement
1.11 Overfl ow
1.12 Binary Coded Decimal (BCD) Number System
1.13 Packed BCD
1.14 Gray Code (Refl ected Code)
1.15 Gray Code to Binary Conversion
1.16 Binary to Gray Code Conversion
1.17 Excess3 (XS3) Code
1.18 Decimal to Excess3 (XS3) Conversions
1.19 Weighted BCD Codes
1.20 ASCII Code
1.21 EBCDIC
1.22 Parity Bit
1.23 Error Correcting Code: Hamming Code
Summary
Multiple Choice Questions
Review Questions
Chapter 2: BOOLEAN ALGEBRA AND LOGIC GATES
2.1 Introduction
2.2 Boolean Algebra
2.3 Boolean Laws
2.4 De Morgan’s Theorem
2.5 Logic Gates
2.6 Universal Gate
2.7 Simplifi cation of Logic Circuits
2.8 Consensus Theorem
2.9 Positive Logic and Negative Logic
Summary
Multiple Choice Questions
Review Questions
Chapter 3: DIGITAL LOGIC FAMILY
3.1 Introduction
3.2 Classifi cation of Digital Logic Family
3.3 Characteristics of Digital Logic Family
3.4 BJT Characteristics
3.5 Direct Coupled Transistor Logic (DCTL)
3.6 Resistor Transistor Logic (RTL)
3.7 Diode Transistor Logic (DTL)
3.8 TransistorTransistor Logic (TTL)
3.9 Emitter Coupled Logic (ECL)
3.10 Schottky TTL
3.11 High Threshold Logic (HTL)
3.12 Integrated Injection Logic (IIL)
3.13 TTL Logic Gates
3.14 Characteristics of TTL
3.15 Metal Oxide Semiconductor FETs (MOSFET) Characteristics
3.16 MOS Characteristics
3.17 CMOS Gates
3.18 CMOS Characteristics
3.19 Interfacing TTL and CMOS Logic Family
3.20 Advantages and Disadvantages of CMOS Over TTL
Summary
Multiple Choice Questions
Review Questions
Chapter 4: COMBINATIONAL LOGIC
4.1 Introduction
4.2 Elements of Combinational Logic
4.3 Boolean Equation
4.4 Canonical Sum of Product (SOP)/Minterm Representation
4.5 Canonical Product of Sum (POS)/Maxterm Representation
4.6 Minterm vs. Maxterm
4.7 Conversion between Canonical SOP and Canonical POS Forms
4.8 Development of Truth Table from Logic Expression
4.9 Logic Simplifi cation using Boolean Algebra
4.10 Karnaugh Maps
4.11 Construction of Karnaugh Maps from Logic Expression
4.12 Logic Simplifi cation using Karnaugh Maps
4.13 Product of Sums Simplifi cation using Karnaugh Maps
4.14 Don’t Cares
4.15 Minimisation of Simultaneous Functions
4.16 Variable Mapping
4.17 Tabular Method of Minimisation
Summary
Multiple Choice Questions
Review Questions
Chapter 5: COMBINATIONAL LOGIC DESIGN
5.1 Introduction
5.2 Combinational Logic Design
5.3 Decoders
5.4 Encoders
5.5 Priority Encoders
5.6 Multiplexers
5.7 Demultiplexer
5.8 Code Conversion using Logic Gates and MSI ICs
5.9 Hazards
5.10 Fault Detection of Combinational Logic Circuit
Summary
Multiple Choice Questions
Review Questions
Chapter 6: ARITHMETIC LOGIC CIRCUITS
6.1 Introduction
6.2 Binary Addition
6.3 Binary Subtraction
6.4 Carry LookAhead Addition
6.5 Serial Adder
6.6 Parallel Addition
6.7 Binary Multiplier
6.8 Binary Division
6.9 Arithmetic Logic Units (ALU)
6.10 Digital Comparators
Summary
Multiple Choice Questions
Review Questions
Chapter 7: FLIPFLOPS
7.1 Introduction
7.2 Inverter with Feedback
7.3 Two Inverters form a Memory Cell
7.4 Memory Cell using NAND and NOR Gates
7.5 Latch
7.6 SR Latch using NOR Gates
7.7 SR Latch using NAND Gate
7.8 SR Latch with Enable
7.9 The D Latch
7.10 D Latch with Enable
7.11 FlipFlops
7.12 Edgetriggered SR Flip Flop
7.13 Cascading SR FlipFlops
7.14 SR FlipFlop with Asynchronous Inputs
7.15 EdgeTriggered D FlipFlops
7.16 D FlipFlop with Asynchronous Inputs
7.17 The JK FlipFlop
7.18 T FlipFlop
7.19 Conversion from One Type of FlipFlop to Another Type
7.20 Operating Characteristics of FlipFlops
7.21 Applications of FlipFlops
7.22 FlipFlop ICs
Summary
Multiple Choice Questions
Review Questions
Chapter 8: SEQUENTIAL CIRCUITS 3
8.1 Introduction
8.2 Register
8.3 Shift Register
8.4 Classifi cation of Shift Register
8.5 Unidirectional Shift Registers
8.6 Bidirectional Shift Registers
8.7 Serial InParallel Out (SIPO) Shift Registers
8.8 Serial InSerial Out Shift Registers
8.9 Parallel InParallel Out Shift Registers
8.10 Parallel InSerial Out Shift Registers
8.11 Buffer Register
8.12 Universal Shift Register
8.13 Universal Shift Register using MUX
8.14 Applications of Shift Registers
8.15 Counter
8.16 Classifi cation of Counter
8.17 Asynchronous (Ripple) Counters
8.18 Asynchronous Decade Counters
8.19 Simultaneous Updown Counter
8.20 Asynchronous Updown Counters
8.21 Propagation Delay in Asynchronous Counter
8.22 Asynchronous Counter ICs
8.23 Synchronous Counters
8.24 Synchronous Down Counter
8.25 Synchronous Updown Counters
8.26 Synchronous Decade Counters
8.27 Propagation Delay in Synchronous Counter
8.28 Synchronous Counter ICs
8.29 MOD n Counter
8.30 Synchronous Counter Design Steps
8.31 Cascade Counters
8.32 Programmable or Presettable Counters
8.33 Self Starting and Self Correcting Counters
8.34 Counter Applications
Summary
Multiple Choice Questions
Review Questions
Chapter 9: SEQUENTIAL CIRCUITS DESIGN
9.1 Introduction
9.2 Sequential Circuit Model
9.3 Classifi cation of Sequential Circuits
9.4 State Table
9.5 State Diagram
9.6 State Equation
9.7 Design Procedure of Synchronous Sequential Circuits
9.8 State Reduction of Synchronous Sequential Circuits
9.9 Asynchronous Sequential Circuits
9.10 Design Procedure of Asynchronous Sequential Circuits
9.11 Algorithmic State Machines (ASM)
Summary
Multiple Choice Questions
Review Questions
Chapter 10: MULTIVIBRATORS
10.1 Introduction
10.2 Classifi cation of Multivibrators
10.3 Clock Oscillator using BJTs
10.4 Monostable Multivibrator using BJTs
10.5 Bistable Multivibrator using BJTs
10.6 Astable Multrivibrator using NOT Gates
10.7 Monostable Multrivibrator using NAND Gates
10.8 Multivibrator using OP AMPs
10.9 555 Timer
10.10 Applications of 555 Timer
10.11 556 Timer
10.12 74121 Monostable Multivibrator
10.13 74122 Retriggerable Monostable Multivibrator
10.14 Retriggerable Monostable Multivibrator IC 74123
Summary
Multiple Choice Questions
Review Questions
Chapter 11: ANALOG DIGITAL CONVERSION
11.1 Introduction
11.2 Sample and Hold Circuit
11.3 Quantisation
11.4 Binary Digit Weight
11.5 Operational Amplifi ers
11.6 Digital to Analog Converters (DAC)
11.7 Extended Capacity of DAC
11.8 Current Mode DAC
11.9 Switched Capacitor DAC
11.10 D/A Converter Specifi cation
11.11 DAC ICs
11.12 ADC Converter
11.13 Medium Speed Analog to Digital Converters
11.14 High Speed Analog to Digital Converters
11.15 Specifi cation of ADC
11.16 ADC ICs
11.17 Bipolar DAC and ADC
11.18 Applications of DAC and ADC
Summary
Multiple Choice Questions
Review Questions
Chapter 12: SEMICONDUCTOR MEMORIES
12.1 Introduction
12.2 Classifi cation of Memory
12.3 Memory Organisation
12.4 Memory Operation
12.5 Semiconductor ReadOnly Memories
12.6 RandomAccess Memory (RAM)
12.7 Sequential Memory
12.8 ChargeCoupled Device (CCD)
12.9 Magnetic Disks Memory
12.10 ContentAddressable Memory (CAM)
12.11 Advance Memory
Summary
Multiple Choice Questions
Review Questions
Chapter 13: PROGRAMMABLE LOGIC DEVICES
13.1 Introduction
13.2 Programmable Read Only Memory (PROM) Devices
13.3 Programmable Logic
13.4 Programmable Logic Array (PLA)
13.5 Programmable Array Logic (PAL)
13.6 Comparison between PROM, PAL, and PLA
13.7 Simple Programmable Logic Devices (SPLDs)
13.8 Complex Programmable Logic Device (CPLDs)
13.9 Field Programmable Gate Array (FPGA)
Summary
Multiple Choice Questions
Review Questions
Chapter 14: COMPUTER AIDED DIGITAL SYSTEM DESIGN
14.1 Introduction
14.2 Computer Aided Digital System Design
14.3 Computer Aided Design (CAD) Tools
14.4 Hardware Description Language (HDL)
14.5 Very High Speed Integrated Circuit Hardware Description Languages (VHDL)
14.6 Verilog HDL
Summary
Multiple Choice Questions
Review Questions
Chapter 15: LABORATORY EXPERIMENTS
15.1 Introduction
15.2 Development of Instruction Manual for Laboratory Experiments
15.3 Experiment on Basic Logic Circuits using Diodes and Transistors
15.4 Experiment on Basic Logic Circuits using Logic Gates
15.5 Experiment on Combinational Logic Circuits using Logic Gates
15.6 Experiment on FlipFlops
15.7 Experiment on Register
15.8 Experiment on Seven Segment Display and Decoder Driver
15.9 Experiment on Counters
15.10 Experiment on Cascade Counters
15.11 Experiment on Self Starting and Self Correcting Counters
15.12 Experiment on Sequence Generator
15.13 Experiment on Updown Counter
15.14 Experiment on Multivibrators
15.15 Experiments on DAC
15.16 Experiment on ADC
15.17 Experiment on VHDL Simulation of Digital System
Summary
Review Questions
Appendix A: IEEE Standard Symbols
Appendix B: Pin Diagram of Logic Gates
Appendix C: Glossary
Appendix D: Answers of Multiple Choice Questions
Index
DIGITAL ELECTRONICS: PRINCIPLES
AND
APPLICATIONS
The Author Soumitra Kumar Mandal has completed BE (Electrical Engineering) from Bengal Engineering College, Shibpur, Calcutta University; MTech (Electrical Engineering) with specialisation in Power Electronics from Institute of Technology, Banaras Hindu University, Varanasi and PhD from Punjab University, Chandigarh. He began his academic career as a lecturer of Electrical Engineering at S.S.G.M. College of Engineering, Shegaon. Subsequently, he joined Punjab Engineering College, Chandigarh, as a lecturer (Mar 1999 to Jan 2004). Presently, he is an Assistant Professor of Electrical Engineering at National Institute of Technical Teachers’ Training and Research, Kolkata. Dr Mandal is also a life member of ISTE as well as a member of IE. Twenty of his research papers have been published in National and International Journals. He has also presented several papers at National and International Conferences. His research interests are in computer controlled drives, microprocessor and microcontrollerbased system design, embedded system design and neurofuzzy computing.
DIGITAL ELECTRONICS: PRINCIPLES
AND
APPLICATIONS
Soumitra Kumar Mandal Assistant Professor Department of Electrical Engineering National Institute of Technical Teachers’ Training and Research, Kolkata
Tata McGraw Hill Education Private Limited NEW DELHI McGrawHill Ofﬁces New Delhi New York St Louis San Francisco Auckland Bogotá Caracas Kuala Lumpur Lisbon London Madrid Mexico City Milan Montreal San Juan Santiago Singapore Sydney Tokyo Toronto
Published by Tata McGraw Hill Education Private Limited, 7 West Patel Nagar, New Delhi 110 008 Copyright © 2010, by Tata McGraw Hill Education Private Limited No part of this publication may be reproduced or distributed in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise or stored in a database or retrieval system without the prior written permission of the publishers. The program listings (if any) may be entered, stored and executed in a computer system, but they may not be reproduced for publication. This edition can be exported from India only by the publishers, Tata McGrawHill Education Private Limited. ISBN (13): 9780070153820 ISBN (10): 0070153825 Managing Director: Ajay Shukla Head—Higher Education Publishing: Vibha Mahajan Manager: Sponsoring—SEM & Tech Ed: Shalini Jha Editorial Executive: Surabhi Shukla Development Editor: Surbhi Suman Jr Executive—Editorial Services: Dipika Dey Jr Manager—Production: Anjali Razdan General Manager: Marketing—Higher Education: Michael J Cruz Sr Product Manager—SEM & Tech Ed.: Biju Ganesan Asst Product Manager—SEM & Tech Ed.: Amit Paranjpe General Manager—Production: Rajender P Ghansela Asst General Manager—Production: B L Dogra Information contained in this work has been obtained by Tata McGraw Hill, from sources believed to be reliable. However, neither Tata McGraw Hill nor its authors guarantee the accuracy or completeness of any information published herein, and neither Tata McGraw Hill nor its authors shall be responsible for any errors, omissions, or damages arising out of use of this information. This work is published with the understanding that Tata McGrawHill and its authors are supplying information but are not attempting to render engineering or other professional services. If such services are required, the assistance of an appropriate professional should be sought.
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Dedication In the memory of my youngest son —Late Gajanan Mandal and to my parents — Smt. Arati Mandal and Shri Prokash Mandal my wife — Malvika and my children — Om and Puja.
CONTENTS Preface 1.
2.
xi
NUMBER SYSTEM 1 1.1 Introduction 1 1.2 Analog Systems 2 1.3 Digital Systems 2 1.4 Limitations of Digital Systems 4 1.5 Digital Number Systems 4 1.6 Binary Arithmetics 20 1.7 Signed Magnitude 24 1.8 One’s Complement 25 1.9 Two’s Complement 25 1.10 Subtraction by using Two’s Complement 26 1.11 Overﬂow 27 1.12 Binary Coded Decimal (BCD) Number System 29 1.13 Packed BCD 29 1.14 Gray Code (Reﬂected Code) 30 1.15 Gray Code to Binary Conversion 31 1.16 Binary to Gray Code Conversion 31 1.17 Excess3 (XS3) Code 32 1.18 Decimal to Excess3 (XS3) Conversions 32 1.19 Weighted BCD Codes 32 1.20 ASCII Code 35 1.21 EBCDIC 37 1.22 Parity Bit 38 1.23 Error Correcting Code: Hamming Code 40 Summary 42 Multiple Choice Questions 42 Review Questions 44 BOOLEAN ALGEBRA AND LOGIC GATES 2.1 Introduction 46 2.2 Boolean Algebra 47 2.3 Boolean Laws 49 2.4 De Morgan’s Theorem 53
46
2.5 2.6 2.7 2.8 2.9
3.
Logic Gates 55 Universal Gate 61 Simpliﬁcation of Logic Circuits 64 Consensus Theorem 69 Positive Logic and Negative Logic 70 Summary 71 Multiple Choice Questions 72 Review Questions 74
76 DIGITAL LOGIC FAMILY 3.1 Introduction 76 3.2 Classiﬁcation of Digital Logic Family 76 3.3 Characteristics of Digital Logic Family 77 3.4 BJT Characteristics 81 3.5 Direct Coupled Transistor Logic (DCTL) 82 3.6 Resistor Transistor Logic (RTL) 82 3.7 Diode Transistor Logic (DTL) 83 3.8 TransistorTransistor Logic (TTL) 83 3.9 Emitter Coupled Logic (ECL) 85 3.10 Schottky TTL 85 3.11 High Threshold Logic (HTL) 86 3.12 Integrated Injection Logic (IIL) 86 3.13 TTL Logic Gates 88 3.14 Characteristics of TTL 96 3.15 Metal Oxide Semiconductor FETs (MOSFET) Characteristics 102 3.16 MOS Characteristics 107 3.17 CMOS Gates 107 3.18 CMOS Characteristics 111 3.19 Interfacing TTL and CMOS Logic Family 113 3.20 Advantages and Disadvantages of CMOS Over TTL 116 Summary 117 Multiple Choice Questions 117 Review Questions 119
viii 4.
5.
Contents
COMBINATIONAL LOGIC 122 4.1 Introduction 122 4.2 Elements of Combinational Logic 122 4.3 Boolean Equation 123 4.4 Canonical Sum of Product (SOP)/Minterm Representation 124 4.5 Canonical Product of Sum (POS)/Maxterm Representation 126 4.6 Minterm vs. Maxterm 128 4.7 Conversion between Canonical SOP and Canonical POS Forms 129 4.8 Development of Truth Table from Logic Expression 130 4.9 Logic Simpliﬁcation using Boolean Algebra 132 4.10 Karnaugh Maps 137 4.11 Construction of Karnaugh Maps from Logic Expression 144 4.12 Logic Simpliﬁcation using Karnaugh Maps 146 4.13 Product of Sums Simpliﬁcation using Karnaugh Maps 148 4.14 Don’t Cares 150 4.15 Minimisation of Simultaneous Functions 154 4.16 Variable Mapping 157 4.17 Tabular Method of Minimisation 159 Summary 168 Multiple Choice Questions 168 Review Questions 169 COMBINATIONAL LOGIC DESIGN 172 5.1 Introduction 172 5.2 Combinational Logic Design 172 5.3 Decoders 174 5.4 Encoders 183 5.5 Priority Encoders 186 5.6 Multiplexers 190 5.7 Demultiplexer 201 5.8 Code Conversion using Logic Gates and MSI ICs 209 5.9 Hazards 220 5.10 Fault Detection of Combinational Logic Circuit 226 Summary 231 Multiple Choice Questions 231 Review Questions 232
6. ARITHMETIC LOGIC CIRCUITS 6.1 Introduction 234 6.2 Binary Addition 234
234
6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10
7.
8.
Binary Subtraction 238 Carry LookAhead Addition 244 Serial Adder 245 Parallel Addition 246 Binary Multiplier 247 Binary Division 250 Arithmetic Logic Units (ALU) 251 Digital Comparators 255 Summary 258 Multiple Choice Questions 258 Review Questions 260
262 FLIPFLOPS 7.1 Introduction 262 7.2 Inverter with Feedback 263 7.3 Two Inverters form a Memory Cell 263 7.4 Memory Cell using NAND and NOR Gates 263 7.5 Latch 264 7.6 SR Latch using NOR Gates 265 7.7 SR Latch using NAND Gate 266 7.8 SR Latch with Enable 268 7.9 The D Latch 269 7.10 D Latch with Enable 269 7.11 FlipFlops 271 7.12 Edgetriggered SR Flip Flop 271 7.13 Cascading SR FlipFlops 272 7.14 SR FlipFlop with Asynchronous Inputs 273 7.15 EdgeTriggered D FlipFlops 275 7.16 D FlipFlop with Asynchronous Inputs 276 7.17 The JK FlipFlop 277 7.18 T FlipFlop 280 7.19 Conversion from One Type of FlipFlop to Another Type 283 7.20 Operating Characteristics of FlipFlops 287 7.21 Applications of FlipFlops 289 7.22 FlipFlop ICs 292 Summary 297 Multiple Choice Questions 297 Review Questions 298 SEQUENTIAL CIRCUITS 8.1 Introduction 302 8.2 Register 302 8.3 Shift Register 303 8.4 Classiﬁcation of Shift Register 303 8.5 Unidirectional Shift Registers 304 8.6 Bidirectional Shift Registers 304 8.7 Serial InParallel Out (SIPO) Shift
302
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Contents
8.8 8.9 8.10 8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 8.22 8.23 8.24 8.25 8.26 8.27 8.28 8.29 8.30 8.31 8.32 8.33 8.34
9.
Registers 305 Serial InSerial Out Shift Registers 307 Parallel InParallel Out Shift Registers 309 Parallel InSerial Out Shift Registers 309 Buffer Register 310 Universal Shift Register 311 Universal Shift Register using MUX 314 Applications of Shift Registers 315 Counter 318 Classiﬁcation of Counter 318 Asynchronous (Ripple) Counters 319 Asynchronous Decade Counters 323 Simultaneous Updown Counter 324 Asynchronous Updown Counters 324 Propagation Delay in Asynchronous Counter 325 Asynchronous Counter ICs 326 Synchronous Counters 328 Synchronous Down Counter 330 Synchronous Updown Counters 330 Synchronous Decade Counters 331 Propagation Delay in Synchronous Counter 332 Synchronous Counter ICs 333 MOD n Counter 335 Synchronous Counter Design Steps 337 Cascade Counters 340 Programmable or Presettable Counters 342 Self Starting and Self Correcting Counters 342 Counter Applications 344 Summary 347 Multiple Choice Questions 347 Review Questions 351
SEQUENTIAL CIRCUITS DESIGN 356 9.1 Introduction 356 9.2 Sequential Circuit Model 357 9.3 Classiﬁcation of Sequential Circuits 357 9.4 State Table 359 9.5 State Diagram 359 9.6 State Equation 361 9.7 Design Procedure of Synchronous Sequential Circuits 361 9.8 State Reduction of Synchronous Sequential Circuits 374 9.9 Asynchronous Sequential Circuits 378 9.10 Design Procedure of Asynchronous Sequential Circuits 379 9.11 Algorithmic State Machines (ASM) 384 Summary 392
Multiple Choice Questions Review Questions 394
392
10. MULTIVIBRATORS 397 10.1 Introduction 397 10.2 Classiﬁcation of Multivibrators 397 10.3 Clock Oscillator using BJTs 398 10.4 Monostable Multivibrator using BJTs 400 10.5 Bistable Multivibrator using BJTs 401 10.6 Astable Multrivibrator using NOT Gates 402 10.7 Monostable Multrivibrator using NAND Gates 405 10.8 Multivibrator using OP AMPs 405 10.9 555 Timer 415 10.10 Applications of 555 Timer 422 10.11 556 Timer 424 10.12 74121 Monostable Multivibrator 426 10.13 74122 Retriggerable Monostable Multivibrator 428 10.14 Retriggerable Monostable Multivibrator IC 74123 431 Summary 433 Multiple Choice Questions 433 Review Questions 435 437 11. ANALOG DIGITAL CONVERSION 11.1 Introduction 437 11.2 Sample and Hold Circuit 438 11.3 Quantisation 441 11.4 Binary Digit Weight 442 11.5 Operational Ampliﬁers 443 11.6 Digital to Analog Converters (DAC) 443 11.7 Extended Capacity of DAC 454 11.8 Current Mode DAC 455 11.9 Switched Capacitor DAC 456 11.10 D/A Converter Speciﬁcation 457 11.11 DAC ICs 459 11.12 ADC Converter 461 11.13 Medium Speed Analog to Digital Converters 470 11.14 High Speed Analog to Digital Converters 472 11.15 Speciﬁcation of ADC 474 11.16 ADC ICs 476 11.17 Bipolar DAC and ADC 478 11.18 Applications of DAC and ADC 481 Summary 481 Multiple Choice Questions 481 Review Questions 483
x
Contents
12. SEMICONDUCTOR MEMORIES 485 12.1 Introduction 485 12.2 Classiﬁcation of Memory 486 12.3 Memory Organisation 488 12.4 Memory Operation 488 12.5 Semiconductor ReadOnly Memories 490 12.6 RandomAccess Memory (RAM) 506 12.7 Sequential Memory 520 12.8 ChargeCoupled Device (CCD) 527 12.9 Magnetic Disks Memory 530 12.10 ContentAddressable Memory (CAM) 536 12.11 Advance Memory 540 Summary 542 Multiple Choice Questions 542 Review Questions 544 546 13. PROGRAMMABLE LOGIC DEVICES 13.1 Introduction 546 13.2 Programmable Read Only Memory (PROM) Devices 548 13.3 Programmable Logic 558 13.4 Programmable Logic Array (PLA) 558 13.5 Programmable Array Logic (PAL) 568 13.6 Comparison between PROM, PAL, and PLA 579 13.7 Simple Programmable Logic Devices (SPLDs) 582 13.8 Complex Programmable Logic Device (CPLDs) 583 13.9 Field Programmable Gate Array (FPGA) 585 Summary 589 Multiple Choice Questions 589 Review Questions 590 592 14. COMPUTER AIDED DIGITAL SYSTEM DESIGN 14.1 Introduction 592 14.2 Computer Aided Digital System Design 592 14.3 Computer Aided Design (CAD) Tools 594 14.4 Hardware Description Language (HDL) 595 14.5 Very High Speed Integrated Circuit Hardware Description Languages (VHDL) 597 14.6 Verilog HDL 629 Summary 639 Multiple Choice Questions 640 Review Questions 640
643 15. LABORATORY EXPERIMENTS 15.1 Introduction 643 15.2 Development of Instruction Manual for Laboratory Experiments 644 15.3 Experiment on Basic Logic Circuits using Diodes and Transistors 646 15.4 Experiment on Basic Logic Circuits using Logic Gates 649 15.5 Experiment on Combinational Logic Circuits using Logic Gates 651 15.6 Experiment on FlipFlops 654 15.7 Experiment on Register 656 15.8 Experiment on Seven Segment Display and Decoder Driver 658 15.9 Experiment on Counters 659 15.10 Experiment on Cascade Counters 662 15.11 Experiment on Self Starting and Self Correcting Counters 664 15.12 Experiment on Sequence Generator 666 15.13 Experiment on Updown Counter 667 15.14 Experiment on Multivibrators 669 15.15 Experiments on DAC 672 15.16 Experiment on ADC 673 15.17 Experiment on VHDL Simulation of Digital System 675 Summary 678 Review Questions 678 Appendix A: IEEE Standard Symbols 681 Appendix B: Pin Diagram of Logic Gates 692 Appendix C: Glossary 693 Appendix D: Answers of Multiple Choice Questions 701 Index 703
PREFACE Digital technology has a wide range of applications today and is witnessing tremendous advancement from simple logic gates to Field Programmable Gates Arrays (FPGAs). Due to its growing importance, this subject has been incorporated in undergraduate courses of Electrical, Instrumentation, Electronics, Computer Science & Engineering, and Information Technology. Rationale It has been observed that majority of the books available on the subject cover only digital electronics principles without any focus on the practical applications. Since almost none of the reference books have syllabus compatibility and right pedagogy, many students ﬁnd it difﬁcult to conceptualise the subject. Feedback received from students and teachers have strongly recommended the need for a single book that would cover all topics as per the university curriculum. This book—an outcome of my vast experience of teaching digital electronics at S.S.G.M. College of Engineering, Shegaon and Punjab Engineering College, Chandigarh—abridges the gap between the principles and its practices followed in digital electronics. Here, I must particularly mention Prof. Kanchandhani of S.S.G.M. College of Engineering, Shegaon (author of Power Electronics) for inspiring me to write a book that would deal with digital electronics principles and practical experiments using hardware as well as software, thereby providing the requisite foundation in the subject to our students. Users This text is particularly well suited for the undergraduate students of CSE, IT, ECE, EEE, and Electronics & Instrumentation Engineering. It will also be a useful reference for students of BSc and MSc (Computer Science/IT/Electronics), BCA/ MCA, polytechnics, diploma and DOEACC courses in Computer Sciences. Prerequistes This book is intended for undergraduate and postgraduate students in electrical engineering, researchers, hardware designers and teachers. This subject requires no prerequisites other than a basic understanding of analog electronics and algebra. Undergraduate and polytechnic students without prior knowledge of digital electronics can also grasp the subject due to lucid and stepbystep explanation of concepts throughout the book. Principles of operation are explained using examples and solved problems that range from simple to complex. After studying this book, students will be thoroughly equipped to excel in semester as well as competitive examinations. Goals and Coverage This book has been designed to provide working knowledge about digital logic elements and develop any digital system with logic elements. It covers the following areas—number system, boolean algebra, logic gates, digital logic family, combinational logic circuits design, arithmetic logic unit, ﬂipﬂops, sequential circuits and their design, multivibrators, DAC and ADC, digital memory, fundamental knowledge of VLSI, PLDs, CPLDs and FPGAs, computeraided digital system design, programming in VHDL and Verilog, and experiments on digital electronics using hardware and software. Handson practice with hardware and computeraided design tools for digital system design will enhance the skills of students. Features The book begins with a discussion on the fundamental concepts of digital electronics such as number systems, boolean algebra, logic families followed by topics (like combinational and sequential logic, multivibrators, A/D conversion and memories) related to design and analysis of digital systems and ﬁnally, covers basics of digital design using VHDL and Verilog HDL.
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The features of the book are given below: ã Instructional objectives of each chapter have been written in a very speciﬁc manner. ã The concepts are concisely explained and supported with numerous examples, illustrations, equations, tables and circuit diagrams. ã Stepwise methodology for explaining solved examples. ã A brief summary of topics has been presented at the end of each chapter. ã The language used is simple and coherent. ã Handson practice with hardware, ICs, CAD tools and VHDL for designing a digital system. ã The book provides objective, theoretical and numerical problems for testing and enhancing one’s subjectrelated knowledge and understanding. ã This book contains multiple choice questions and review questions at the end of each chapter. The objective questions would be helpful in the preparation of competitive examinations. ã References and website addresses provide pointers to further indepth information. ã Alphabetical glossary with explanation of key terms has been provided in Appendix C. ã Strong pedagogy includes: • Solved examples : 179 • Multiple choice questions : 278 • Review questions (theoretical and numerical): 352 • Laboratory experiments: 15 Organisation This book is organised into 15 chapters and 4 appendices. Chapters 1 to 6 are devoted to combinational logic design whereas Chapters 7 to 14 cover sequential logic circuit design. Electrical engineering students usually follow these courses within one semester dealing with Chapters 1 to 5, Chapters 7 to 9, Chapter 11 and Chapter 14. This book can also be used in a Master’s course on Digital System Design and as a reference text for graduate engineers working in their ﬁelds. Chapter 1 presents the basic concepts of number system, analog and digital systems with their limitations. This chapter provides binary arithmetic, signed magnitude, one’s complement, two’s complement, various codes such as BCD, packed BCD, gray code, XS3 code, ASCII code, EBCDIC code, parity bit, error detecting code and code conversion along with their applications in detail. Chapter 2 describes the basic postulates and theorems of boolean algebra and various logic operations. The correlation between boolean expression and implementation using logic gates has been explained. The operation of logic gates with logic diagram, positive logic and negative logic, DeMorgan’s theorem, consensus theorem and simpliﬁcation of logic circuits are also incorporated. Chapter 3 deals with various digital logic families and their characteristics. The TTL logic gates, characteristics of TTL, MOS logic gates, MOS characteristics, CMOS gates, CMOS characteristics, interfacing of TTL and CMOS logic family, and comparison between CMOS over TTL are explained elaborately. Chapter 4 explains combinational logic circuit. The different elements of combinational logic, SOP and POS representation, conversion between SOP and POS forms are discussed. The various methods of minimisation and simpliﬁcation of Boolean expression, karnaugh maps, minimisation of simultaneous functions, variable mapping and tabular method of minimisation are elaborately explained. Chapter 5 deals with design and implementation of combinational logic circuits such as decoder encoders, priority encoders, multiplexers, and demultiplexers. The code conversion using logic gates and MSI ICs, hazards and fault detection of combinational logic circuit are highlighted.
Preface
xiii
Chapter 6 gives a detailed exposition of arithmetic and logic circuits such as binary addition, subtraction, carry lookahead addition, serial and parallel adder, binary multiplier, binary division, Arithmetic Logic Units (ALU), and digital comparators. Chapter 7 elucidates various types of latches and ﬂipﬂops such as SR Latch using gates, D latch, edge  triggered SR, D, T, and JK ﬂipﬂop, ﬂipﬂop with asynchronous inputs, conversion from one type of ﬂipﬂop to another type, operating characteristics and applications of ﬂipﬂops. The structures of ﬂipﬂops are discussed highlighting the difference between latch and ﬂipﬂops with leveltriggered and edgetriggered. Chapter 8 covers sequential circuits such as register, shift register, buffer register, universal shift register, applications of shift registers, asynchronous (Ripple) and synchronous counters, propagation delay in counter, modn counter, counter design steps, cascade counters, programmable or presettable counters, selfstarting and selfcorrecting counters, and counter applications. Chapter 9 deals with sequential circuits design. The sequential circuit model, state table, state diagram, state equation, design procedure of sequential circuits, state reduction of synchronous sequential circuits, and asynchronous sequential circuits are discussed. The Algorithmic State Machines (ASM), ASM Chart, difference between conventional ﬂow chart and ASM Chart are discussed in this chapter. Abundant examples of sequential circuits design are incorporated. Chapter 10 gives the basic concept of multivibrators and types of multivibrators such as monostable, bistable, and astable multivibrators. The 555 timer and its applications, 556 timer, 74121 monostable multivibrator, 74122 and 74123 retriggerable monostable multivibrators are explained. Chapter 11 covers various methods of Digital to Analog Converters (DAC) and Analog to Digital Converters (ADC), speciﬁcation of ADC and DAC and applications of ADC and DAC. Chapter 12 describes the fundamental concept of semiconductor memories, classiﬁcation of memory, memory organisation and its operation. Read Only Memory (ROM), Random Access Memory (RAM), sequential memory, Charge Coupled Device (CCD), magnetic disk memory, and Content Addressesable Memory (CAM) are explained. Chapter 13 covers the various programmable logic devices such as PROM, PLA and PAL. The comparison between PROM, PAL and PLA is highlighted, and fundamental knowledge of Simple Programmable Logic Devices (SPLDs), Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Array (FPGA) are discussed. Chapter 14 deals with computer aided digital systems design. The basic concept of Computer Aided Design (CAD), CAD tools, Hardware Description Language (HDL), Very high speed integrated circuit Hardware Description Language (VHDL) and Verilog HDL are elaborately discussed. Chapter 15 presents laboratory experiments that can be performed with hardware and be simulated with software. Experiments on basic logic circuits using diodes, transistors and logic gates, combinational logic circuits, ﬂipﬂops, registers, sevensegment display and decoder driver, counters, cascade counters, selfstarting and selfcorrecting counters, sequence generator, updown counter, multivibrators, DAC and ADC are presented with their required formal information. Experiments on VHDL simulation of digital systems are also incorporated. Appendix A is a discussion on the IEEE standard graphic symbols for logic functions. Appendix B provides the pin diagram of logic gates. Appendix C contains glossary with explanation of important terms. Appendix D includes answers of multiple choice questions. Web Resources This book is accompanied with an exhaustive online learning centre designed to provide valuable resources for instructors and students. For Instructors: For Students: • Solutions Manual • Test Bank (includes Additional Questions for Practice) • PowerPoint Slides • Tutorials on Digital Electronics • Lab Assignments • Solutions to Selected Questions • Chapterwise Objectives • References and Website Addresses
xiv
Preface
Acknowledgements The author has received inspiration and cooperation for completion of this book from Dr Gurnam Singh, PEC, Chandigarh; Dr S Chatterjee, NITTTR, Chandigarh; Dr S K Bhattachariya, Former Director, NITTTR, Kolkata; Prof Amitabha Sinha, Director School of Information Technology, WBUT; Dr C K Chanda and Dr P Shyam, Bengal Engineering College, Shibpur; Dr P Sarkar, Professor and Head Electrical, Dr S Chattopadhay, Assistant Professor, and Dr S Pal, Senior Lecturer, NITTTR, Kolkata. The author is thankful to the Electrical Engineering staff, specially A K Das, N K Sarkar, S Roy Choudhury, and Surojit Mallick for their valuable assistance. Special thanks go to the Tata McGraw Hill team, namely, Vibha Mahajan, Shalini Jha, Surabhi Shukla, Surbhi Suman, Dipika Dey, Anjali Razdan and Baldev Raj for their excellent publishing initiatives. A note of acknowledgement is due to the following reviewers for their valuable suggestions. Arvind Rajawat Maulana Azad National Institute of Technology (MANIT) Bhopal, Madhya Pradesh Rakesh K Sarin Dr B R Ambedkar National Institute of Technology, Jalandhar, Punjab Pradeep Kumar Amity School of Engineering & Technology, Noida, Uttar Pradesh Sampath Kumar JSS Academy of Technical Education, Noida, Uttar Pradesh Sangeeta Shukla Sagar Institute of Research and Technology, Bhopal, Madhya Pradesh Sunil Mathur Maharaja Agrasen Institute of Technology, New Delhi
B Chakraborty National Institute of Technology, Durgapur, West Bengal Kanak Saxena Samrat Ashok Technological Institute (SATI), Vidisha, Madhya Pradesh Bijoy Bandyopadhyay University of Calcutta, Kolkata, West Bengal Abir Chattopadhyay Camellia School of Engineering and Technology, West Bengal V J Dongre Government Polytechnic, Nagpur, Maharashtra M G Sumithra Bannari Amman Institute of Technology, Erode, Tamil Nadu Thimmarayaswamy K B M Sreenivasaiah College of Engineering, Bangalore, Karnataka
The readers of the book are encouraged to send their comments, queries and suggestions at the following email id—[email protected] (kindly mention the title and author name in the subject line).
SOUMITRA KUMAR MANDAL
CHAPTER
1 NUMBER SYSTEM 1.1
INTRODUCTION
In science, technology, business, and all other ﬁelds, we always deal with quantities. Quantities can be measured, monitored, recorded, manipulated arithmetically, observed, or in some other way utilised in most physical systems. It is necessary to represent their values efﬁciently and accurately. Quantities are represented by two ways: analog and digital. In analog representation, a quantity is represented by a voltage or current. Analog quantities have an important characteristic: they are continuous and can vary in wide range of values. Figure 1.1 shows the analog voltage variation with time. In digital representation, the quantities are represented by symbols called digits. In a digital watch, the time of day is represented in the form of decimal digits which stand for hours, minutes and seconds. Though the time of day changes continuously, the digital watch reading does not change continuously. It changes in steps of one per minute or per second. Therefore, this digital representation changes in discrete steps, as compared to an analog watch, where the dial reading changes continuously. The analog voltage is digitalised and represented by discrete steps as shown in Fig. 1.2. The major difference between analog and digital quantities can be simply stated that analog signal is continuous and digital signal is discrete one.
Fig. 1.1 Analog voltage variation
Fig. 1.2 Digital voltage represented by sampled or quantised levels
2
1.2
Digital Electronics: Principles and Applications
ANALOG SYSTEMS
Any analog system consists of integrated circuits of transistors to perform different operations on any physical quantity which is represented in analog form. In an analog circuit, transistors operate in between blocked and saturated states, and an analog datum is represented by a continuous signal. This continuous analog signal is either voltage or current. When it is voltage, the amplitude of voltage can be varied in between the ground and power supply voltages (+VCC or –VCC). Consequently, the output signal can be varied from zero to maximum positive or negative value of analog system. Examples of analog systems are measurement of voltage, current, power, energy and any physical quantity (force, displacement, and speed, etc.), audio ampliﬁer, magnetic tape recording, cell phones, data transmission, and video recording. Since nineteenth century, we are using radio but the normal radio still uses analog transmission. Analog system is also very popular for video recording. In video recording system, information is video and audio. When information is recorded by an analog system, the recording has a very high quality. To transmit the recorded information from one place to other, initially it is modulated directly with a carrier wave and then it is transmitted through air, cable, and satellite. During this transmission, the carrier and modulated signal will loose amplitude and some noise is also introduced to the carrier and its modulated signal due to interference. Therefore, receiving end signal always has a lower quality than the transmitted signal and the modulated signal will also be of lower quality than the original signal. In this way, analog transmission system is unable to maintain the quality. The original cell phone technology is analog, but analog cell phones are obsolete due to lot of disadvantages and presently it is replaced by digital cell phone. The disadvantages of analog cell phone are as follows: (i) the battery life is about one fourth of that of a digital phone, (ii) they are more susceptible to noise and disturbance, (iii) the voice quality is not clear, (iv) new features, namely date, time, text messaging, internet are not available on analog cell phones, (v) they need more power and thus can potentially disturb other electronics equipments. From the above discussion, it is very clear that analog systems have a lot of disadvantages. Nowadays, digital systems are used due to greater ﬂexibility, high accuracy, more generality, and the design itself is technology independent.
1.3 DIGITAL SYSTEMS
Fig. 1.3
(a) Voltage representation of binary ‘1’ and binary ‘0’ (b) A digital signal
In digital systems, signals are represented in binary form. As a binary quantity can be represented by two operating states called ‘0’ and ‘1’, it may be transmitted in the form of electronic OFF and ON pulses respectively. ON means binary ‘1’ and OFF means binary ‘0’. When these pulses are received by any digital system, they are processed. The typical representation of voltage is shown in Fig. 1.3. Binary ‘1’ means any voltage between 2V to 5V and binary ‘0’ states
Number System
3
any voltage between 0V to 0.8V. It will be noted that voltage between 0.8V to 2V is not used and this may create error in a digital circuit. In a digital system, all communication within the system are carried out in a digital manner. Usually, the digital communication means that all signals within the system can have only two possible states of OFF and ON or ‘0’ and ‘1’. Digital electronics is the branch of electronics and these electronic systems are composed of elements that exhibit this digital behavior. As a digital system can only exhibit one of two possible states, they are usually easier to understand than analog systems, which can have an inﬁnite number of states. The ﬁeld of digital electronics is very exciting, and fast changing. Advances in digital electronics make it possible to do very complex system in a simple manner. Digital electronics are a key element of many products, namely personal computers, sophisticated sewing machines, microwave ovens, compact disc players, and video cassette players, etc. The brains of all of these products and many parts of these products are composed of digital electronics. Presently, it is very difﬁcult to survive in this world without digital electronics.
1.3.1
Advantages of Digital Systems
In analog systems, the noise is transmitted from one component to the next and it increases with the number of interconnected hardware elements between inputs and outputs. So very careful design and manufacturing procedures are required for the analog system, thus increasing the price of the product. If digital system replace the analog system, the following advantages are possible: •
It is simple to design. Exact values of voltage or current are not important, but only the range, HIGH or LOW in which they fall.
•
The storage of digital information is easy.
•
Accuracy and precision are better than analog signals.
•
Operation of digital system can be programmed and variety of operation can be done. The analog system can also be programmed, but the variety and complexity of the available operations is very limited.
•
Digital circuits are less affected by noise. We can easily distinguish the binary ‘0’ and binary ‘1’ signal, though there are some noises in signal.
•
In digital ICs, a large number of digital circuits can be incorporated compared to analog ICs.
•
Simple, inexpensive and safe implementation of complex data processing algorithms.
•
Simple design and implementation procedures.
•
High immunity to noise (virtually no loss of information due to noise). Each digital component behaves as a ﬁlter eliminating the noise on its inputs.
1.3.2
Disadvantages of Digital Systems
Every system has some disadvantages and few drawbacks. Similarly, the disadvantages of digital systems are as follows:
4
Digital Electronics: Principles and Applications
Large numbers of transistors are required for performing some operations that can be implemented using simpler analog hardware. For instance, additions and multiplications by constants can be easily implemented using analog circuits based on operational ampliﬁers. In some situations, the operation speed is lower than the speed offered by equivalent analog circuits.
•
•
1.4
LIMITATIONS OF DIGITAL SYSTEMS
In real world, all physical quantities are analog in nature. These quantities are used as input signals of system and monitored for controlling the system. To take advantage of digital electronics, the following steps are followed: Step 1
Convert the analog inputs to digital form by using analog to digital converter, ADC.
Step 2
Process the digital information.
Step 3
Convert the digital outputs back to analog form by digital to analog converter, DAC.
The block diagram of speed control system is shown in Fig.1.4 and this speed control system requires analog to digital converter for converting analog signals to digital form. Firstly, the speed is measured in analog form and then converted into digital form by using analog to digital converter. This digital speed signal is used as input of digital signal processor. After that digital signal is processed by digital signal processor circuit, its digital output is fed to digital to analog converter. The digital to analog converter converts the digital signal to analog form. This analog output is used as an input of the controller and controller’s output takes necessary action to adjust the speed. Therefore, it is conﬁrmed from the above system that the data conversion is the major drawback of application of digital electronics.
Fig. 1.4
1.5
Block diagram of speed control system that requires analog to digital converter
DIGITAL NUMBER SYSTEMS
In general, numbers are represented using ‘10’ symbols or ﬁgures. These ‘10’ symbols or ﬁgures are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. The signiﬁcance of each ﬁgure depends on its position inside the string of ﬁgures used to represent the number. These are numbers represented in “base 10”. In digital system, there are many number systems but most commonly used number systems are the decimal, binary, octal, and
5
Number System
hexadecimal systems. The decimal system is the most familiar number system that we commonly use in everyday life.
1.5.1
Decimal Number
The decimal number is composed of ‘10’ symbols. These ‘10’ symbols are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9. By using these symbols we can write any quantity. The decimal system is also called the base ‘10’ system as it has ‘10’ digits. The representation of decimal number is shown in Table 1.1. Table 1.1 103 = 1000
102 = 100
101 = 10
Representation of decimal number 100 = 1
. Decimal point
Most Signiﬁcant Digit (MSD)
10–1 = 0.1
10–2 = 0.01
10–3 = 0.001 Least Signiﬁcant Digit (LSD)
The example of decimal numbers are 6897 and 27.95. The decimal number (6897)10 can be written as (6897)10 = 6 × 103 + 8 × 102 + 9 × 101 + 7 × 10° and the number (27.95)10 can be represented as (27.95)10 = 2 × 101 + 7 × 10° + 9 × 10–1 + 5 × 10–2. Any positive integer can be represented by symbol or digits in a positional number system. The number N can be represented in the equation form N = dn dn–1 dn–2 …….. d3 d2 d1 d0 . d–1 d–2 d–3 . . . d–n–1 d–n
(1.1)
Ø Decimal Point The di represents the digits, which have ten values ranging from 0 to 9. The value of ‘n’ may be any real integer to express the number N. The digit on the extreme right is called the least signiﬁcant digit (LSD) because it has the lowest positional value of 1 for integers. The next digit to the left of this least signiﬁcant digit has the positional value of 10; the next, 100; and so on. The digit on the extreme left is called the most signiﬁcant digit (MSD) as it has the highest positional value. The use of positional numbers can be extended to fractions by adding a decimal point and letting digits to the right of the decimal represent 1/10ths, 1/100ths, and so on, depending on position. The number N can be determined from equation (1.2). N = dn × 10n + dn–1 × 10n–1 + . . . . . . . + d1 × 101 + d0 × 100 + d–1 × 10–1 + d–2 × 10–2 . . .
1.5.2
(1.2)
General Positional Numbers
Generally, we use ‘base 10’ in decimal system to represent a number, but a number system can have any base. The base of a number system is also called the radix. The rules concerning the decimal number
6
Digital Electronics: Principles and Applications
representation in “base 10” can be extended to 2 (binary), 8 (octal), and 16 (hexadecimal) based number system. The generalised representation of a positional number to any base b is given by equation (1.3) and (1.4). Nb = dn dn–1 dn–2 . . . . . . d3 d2 d1 d0 . d–1 d–2 d–3 . . . d–n–1 d–n …… ↑
(1.3)
Radix Point The equation (1.3) means Nb = dn × bn + . . . + d0 × b0 + d–1, × b–1 + d–2 × b–2 …… + d–n × b–n …… where, the di represents the digits, b is the base or radix, and the “.” represents the radix point .
(1.4)
The notation of generalised positional number system is Nb. Here the subscript denotes the base.
1.5.3
Fig. 1.5 Representation of binary by switch ON and OFF
Binary Number
The simplest information is either TRUE or FALSE. This can be represented by two voltage levels: 5 Volts for TRUE and 0 Volts for FALSE or Switch is ON and switch is OFF as shown in Fig. 1.5. A voltage signal, which has only two possibilities, is represented by a BIT. BIT stands for Binary Digit. Binary means: only 2 possible values. Advantages of using binary representation are simple to implement in electronic hardware (switch) and good tolerance to noise. FALSE means ‘0’ and TRUE means ‘1’. Electronic storage devices are used two distinct different states: ‘0’ and ‘1’. So, these electronic storage devices use a number system based on only two digits. In binary number system, the digits are zero (0) and one (1) and the radix/base is two (2). The example of an binary number is
N = 10101010112 = (1010101011)2 where,
the subscript ‘2’ denoting the base of binary number system.
By using the formula of the general position number system, the number N can be presented in terms of base 10 or decimal numbers. N = 1 × 29 + 0 × 28 + 1 × 27 + 0 × 26 + 1 × 25 + 0 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 1 × 20 = 512 + 0 +128 + 0 + 32 + 16 + 8 + 2 + 1 = (699)10 It is very convenient to determine the equivalent decimal number if we represent the positional value of each of the digits existing in binary. After that, we add the positional values corresponding to nonzero digits ‘1’. The positional value of each digit is given below: 512 256 128 64 32 16 8 4 2 1
7
Number System
In the binary system, there are only two symbols or possible digit values, ‘0’ and ‘1’. This base2 system can be used to represent any quantity that can be represented in decimal. Table 1.2 shows the representation of binary number. Table 1.2 23 = 8
22 = 4
21 = 2
Representation of binary number 20 = 1
2–1 = 1/2
.
2–2 = 1/4
Binary point
Most Signiﬁcant Bit (MSB)
2–3 = 1/8
Least Signiﬁcant Bit (LSB)
The four bit binary number with different possibilities is represented by decimal equivalent as shown in Table 1.3.
1.5.4
Table 1.3
Four bit binary numbers and it’s decimal equivalent
23=8
22=4
21=2
20=1
Decimal Equivalent
0
0
0
0
0
0
0
0
1
1
0
0
1
0
2
0
0
1
1
3
0
1
0
0
4
0
1
0
1
5
0
1
1
0
6
0
1
1
1
7
1
0
0
0
8
1
0
0
1
9
1
0
1
0
10
1
0
1
1
11
1
1
0
0
12
1
1
0
1
13
1
1
1
0
14
1
1
1
1
15
BinarytoDecimal Conversion
Any binary number can be converted to its decimal equivalent simply by summing together the weights of the various positions in the binary number, which contain 1. The decimal equivalent of binary number (111011)2 is (59)10 as shown below:
8
Digital Electronics: Principles and Applications
(1 1 1 0 1 1) 2
(binary)
25 + 24 + 23 + 0 + 21 + 20
= 32 + 16 + 8 + 0 + 2 + 1 = 5910 (decimal)
and similarly, the binary number (110110101)2 is converted into decimal number (437)10. 11 0 1 1 0 1 0 1 2 8
7
5
4
2
(binary) 0
2 +2 +0+2 +2 +0+2 + 0+2
= 256 + 128 + 0 + 32 + 16 + 0 + 4 + 0 + 1 = 43710 (decimal)
It should be noticed that this method is to ﬁnd the weights (i.e., powers of 2) for each bit position that contains a 1, and then to add them up.
1.5.5 DecimaltoBinary Conversion There are 2 methods namely reverse of binary to decimal and repetitive division. Each method is represented in this section.
Reverse of BinarytoDecimal Method The decimal number (45)10 can be represented as sum of 32, 8, ,4, and 1. So, the binary equivalent of (45)10 is (101101)2. 45 10 = 32 + 0 + 8 + 4 + 0 + 1 (decimal) = 25 + 0 + 23 + 22 + 0 + 20 = 1 0 1 1 0 12 (binary) Repetitive Division This method uses repeated division by 2. The ﬂow chart for converting decimal number into binary by repeated division is shown in Fig. 1.6. For example, to convert 2510 to binary is given below: 25/2 = 12 + remainder 1 12/2 6/2 3/2 1/2
= = = =
6 3 1 0
+ + + +
1 LSB
Least Signiﬁcant Bit) remainder 0 0 remainder 0 0 remainder 1 1 remainder 1 1 MSB (Most Signiﬁcant Bit)
Result 2510 = 1 1 0 0 12
Fig. 1.6 Flow chart for converting decimal number into binary by repeated division
The repetitive division method of conversion of decimal number to binary number can also be represented as shown below:
9
Number System 600 / 2 = 300 remainder 0 300 / 2 = 150 remainder 0 150 / 2 = 75 remainder 0 75 / 2 = 37 remainder 1 37 / 2 = 18 remainder 1 18 / 2 =
9 remainder 0
9 /2=
4 remainder 1
4 /2=
2 remainder 0
2 /2=
1 remainder 0
1 /2=
0 remainder 1 1 0 0 1 0 1 1 0 0 MSB
0 LSB
All of the remainders from the division are then arranged in reverse order, from MSB to LSB to form the correct binary sequence. Therefore, the binary equivalent of decimal number (600)10 is (1001011000)2. The binary equivalent values for 015 are presented in Table1.4. Table 1.4 The binary equivalent values for 0–15
Decimal 102 101 100
1.5.6
Binary 23 22 21 20
Decimal 102 101 100
Binary 23 22 21 20
0
0
0
0
0
0
0
0
0
8
1
0
0
0
0
0
1
0
0
0
1
0
0
9
1 0
0
1
0
0
2
0
0
1
0
0
1
0
1
0
1
0
0
0
3
0
0
1
1
0
1
1
1
0
1
1
0
0
4
0
1
0
0
0
1
2
1
1
0
0
0
0
5
0
1
0
1
0
1
3
1
1
0
1
0
0
6
0
1
1
0
0
1
4
1
1
1
0
0
0
7
0
1
1
1
0
1
5
1
1
1
1
Conversion of Fractional Decimal Number into Binary
To convert a fractional decimal number to a binary number, we multiply the fractional part of the number repeatedly by base 2. The integer part obtained after multiplication is noted separately and the fractional part is again considered for further multiplication. This process will continue till a zero fractional part has been obtained. In this conversion method, the ﬁrst integer is Most Signiﬁcant Bit (MSB) and the last integer is the Least Signiﬁcant Bit (LSB) of the fractional decimal number. The ﬂow chart of conversion of fractional decimal number into binary is depicted in Fig. 1.7. For example, the conversion of (0.625)10 into binary is explained below: To convert 0.625 decimal to binary, the computation uses repeated multiplication by 2. The integer part and fractional part of the product are separated after each multiplication.
10
Digital Electronics: Principles and Applications Fraction Number
Product
Fractional part
Integer Part
.625
.625 × 2 = 1.25
.25
1 MSB
.25
.25 × 2 = .5
.5
0
.5
.5 × 2 = 1
0
1 LSB
The binary equivalent of (.625)10 is (.101)2. Similarly, the binary equivalent of .475 is given below:
Fig. 1.7 Flow chart for conversion of fractional decimal number into binary
Example 1.1
�
Fraction Number
Product
Fractional part
Integer Part
.475
.475 × 2 = .95
.95
0 MSB
.95
.95 × 2 = 1.9
.9
1
.9
.9 × 2 = 1.8
.8
1
.8
.8 × 2 = 1.6
.6
1
.6
.6 × 2 = 1.2
.2
1
.2
.2 × 2 = .4
.4
0
.4
.4 × 2 = .8
.8
0
.8
.8 × 2 = 1.6
.6
1
.
.
.
.
.
.
The binary equivalent of (.475)10 is (.01111001100…)2.
Convert the following binary numbers to decimal numbers (a) 1110011 (b) 1101.11
Solution (a) (1110011)2 = 1 × 26 + 1 × 25 + 1 × 24 + 0 × 23 + 0 × 22 + 1 × 21 + 1 × 20 = 1 × 64 + 1 × 32 + 1 × 16 + 0 × 8 + 0 × 4 + 1 × 2 + 1 × 1 = 64 + 32 + 16 + 2 + 1 = 115 (b)
(1101.11)2 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 1 × 2–1 + 1 × 22 = 1 × 8 + 1 × 4 + 0 × 2 + 1 × 1 + 1 × 0.5 + 1 × 0.25 = 8 + 4 + 1 + 0.5 + 0.25 = 13.75
11
Number System
Convert the following decimal numbers to binary numbers
Example 1.2
(a) 11
(b) 255
� Solution (a) Conversion of (11)10 to binary 11/2 5/2 2/2 1/2 Result
= 5 + = 2 + = 1 + = 0 + (11)10
remainder remainder remainder remainder =
of of of of
1 1 0 1
1 (Least Signiﬁcant Bit) 1 0 1(Most Signiﬁcant Bit) 1 0 1 12
(b) Conversion of (255)10 to binary 255/2 127/2 63/2 31/2 15/2 7/2 3/2 1/2 Result
= 127 + remainder of 1 = 63 + remainder of 1 = 31 + remainder of 1 = 15 + remainder of 1 = 7 + remainder of 1 = 3 + remainder of 1 = 1 + remainder of 1 = 0 + remainder of 1 25510 =
Example 1.3
1(Least Signiﬁcant Bit) 1 1 1 1 1 1 1(Most Signiﬁcant Bit) 1 1 1 1 1 1 1 12
Convert the following decimal numbers to binary numbers (a) 0.72 (b) 24. 625
� Solution (a) Conversion of (0.72)10 to binary Fraction Number
Product
Fractional part
Integer Part
0.72
.72 × 2 = 1.44
.44
1 MSB
.44
.44 × 2 = .88
.88
0
.88
.88 × 2 = 1.76
.76
1
.76
.76 × 2 = 1.52
.52
1
.52
.52 × 2 = 1.04
.04
1
.04
.04 × 2 = .08
.08
0
.08
.08 × 2 = .16
.16
0
.16
.16 × 2 = .32
.32
0
.32
.32 × 2 = .64
.64
0
.64
.64 × 2 = 1.28
.28
1
.28
.28 × 2 = .56
.56
0
.56
.56 × 2=1.12
.12
1 LSB
(.72)10 is equal to (0.101110000101)2
12
Digital Electronics: Principles and Applications
(b) Conversion of (24.625)10 to binary 24/ 2 12/ 2 6 / 2 3 / 2 1 / 2 Result
= 12+ = 6 + = 3 + = 1 + = 0 + 2410 =
remainder remainder remainder remainder remainder
0 0 0 1 1
0 (Least Signiﬁcant Bit) 0 0 1 1 (Most Signiﬁcant Bit) 1 1 0 0 02
Fraction Number
Product
Fractional part
Integer Part
.625
.625 × 2 = 1.25
.25
1 MSB
.25
.25 × 2 = .5
.5
0
.5
.5 × 2 = 1
0
1 LSB
(24.625)10 is equal to (11000.101)2
1.5.7 Octal Number The octal number system has a base of eight, meaning that it has eight possible digits: 0,1,2,3,4,5,6, and 7. The octal number system is shown in Table 1.5. Table 1.5 83 = 512
82 = 64
81 = 8
Octal number system
80 = 1
Most Signiﬁcant Digit (MSD)
. Octal Point
8–1 = 1/8
8–2 = 1/64
8–3 = 1/512 Least Signiﬁcant Digit (LSD)
1.5.8 DecimaltoOctal Conversion Generally, decimal to octal conversion is done by using reverse octal to decimal and repetitive division method. Both methods are presented below:
Reverse of OctaltoDecimal Method The decimal number (20.75)10 can be written as summation of 16 , 4 and 6/8. The decimal number can be represented by using Table 1.5 as given below: 20.7510 = 2 × (81) + 4 × (80) + 6 × (8–1) = 24.68
Repetitive Division This method uses repeated division by 8. Figure 1.8 depicted the ﬂow chart for converting decimal number into by repeated division. The example is converting 17810 to octal: 178/8 22/ 8 2 / 8
= 22+ remainder 2 2 = 2 + remainder 6 6 = 0 + remainder 2 2 (Most Signiﬁcant Digit) Result 17810 = 2628
(Least Signiﬁcant Digit)
13
Number System
The repetitive division method of conversion of decimal number to octal number is also presented into 602 / 8 = 75 remainder 2 75 / 8 = 9 remainder 3 9 / 8 = 1 remainder 1 1 / 8 = 0 remainder 1 1
1 3 2
MSD
LSD
All of the remainders from the division are then arranged in reverse order, from MSD to LSD to form the correct octal sequence. Therefore the octal equivalent of decimal number (602)10 is (1132)8.
1.5.9
BinarytoOctal/OctaltoBinary Conversion
The binary equivalent of octal digits 0 to 7 are presented in Table 1.6. Table 1.6 Octal Digit Binary Equivalent
Fig. 1.8 Flow chart for converting decimal number into octal by repeated division
Binary equivalent of octal digit
0
1
2
3
4
5
6
7
000
001
010
011
100
101
110
111
It is clear from Table 1.6 that each octal digit is represented by three bits of binary digit. The example of binary to octal conversion is (111 100 111 010)2 = (111) (100) (111) (010)2 =(7 4 7 2 )8. Similarly, the octal number (24657)8 can represented by binary number (010) (100) (110) (101) (111)2= (010100110101111)2. Example 1.4
Convert the following octal numbers to decimal numbers (a) 416
(b) 360.15
� Solution (a) (416)8 = 4 × 82 + 1 × 81 + 6 × 80 = 4 × 64 + 1 × 8 + 6 × 1 = 256 + 8 + 6 = 270 (b) (360.15)8 = 3 × 82 + 6 × 81 + 0 × 80 + 1 × 8–1 + 5 × 8–2 = 3 × 64 + 6 × 8 + 0 × 1 + 1 × 0.125 + 5 × 0.0156 = 192 + 48 + 0.125 + 0.0781 = 240.2031 Example 1.5
Convert the following decimal numbers to octal numbers (a) 234
(b) 2988.6875
14
Digital Electronics: Principles and Applications
� Solution (a) Conversion of (234)10 to octal 234/ 8 29 / 8 3 / 8 Result
= 29+ remainder of 2 = 3 + remainder of 5 = 0 + remainder of 3 23410 = (352)8
2 (Least Signiﬁcant Digit) 5 3 (Most Signiﬁcant Digit)
(b) Conversion of (2988.6875)10 to octal 2988/ 8 373/ 8 46 / 8 5/8
= = = =
373 + remainder of 4 46 + remainder of 5 5 + remainder of 6 0 + remainder of 5
Result
298810 = (5154)8
4 (Least Signiﬁcant Digit) 5 1 5(Most Signiﬁcant Digit)
Conversion of (0.6875)10 to octal
Fraction Number
Product
Fractional part
Integer Part
0.6875
.6875 × 8 = 5.5
.5
5 MSD
.5
.5 × 8 = 4
.0
4 LSD
(2988.6875)10 is equal to (5104.54)8
Example 1.6
Convert the following octal numbers to binary numbers (a) 370.526
�
(b) 2702
Solution (a) Conversion of (370.526)8 to binary (370.526)8 = 011 111 000.101 010 110 (b) Conversion of (2702)8 to binary
Example 1.7
(2702)8 = 010 111 000 010
Convert the following binary numbers to octal numbers (a) 101111001110.001 100
�
(b).111001111
Solution (a) Conversion of (101111001110.001 100)2 to octal (101111001110.001 100)2 = (101) (111) (001) (110). (001) (100) = (5716.14)8 (b) Conversion of (.111001111)2 to octal (.111001111)2 = (.111) (001) (111) = (.717)8
1.5.10
Hexadecimal Number
In hexadecimal system, the base is 16. So, this system has 16 possible digit symbols. It uses the digits 0 through 9 and the letters A, B, C, D, E, and F as the 16 digit symbols. The letters A to F are used for the values of 10–15. This hexadecimal system is also used extensively in computing. The hexadecimal equivalent of decimal numbers 0 to 15 is presented in Table 1.7. Table 1.8 shows the hexadecimal number system.
15
Number System Table 1.7
Represent the decimal number into hexadecimal
Decimal Base 10
Hexadecimal Base 16
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
A
11
B
12
C
13
D
14
E
15
F
Table 1.8 163 = 4096 Most Signiﬁcant Digit (MSD)
1.5.11
162 = 256
161 = 16
Hexadecimal number system
160 = 1
.
16–1 = 1/16
Hexadecimal Point
16–2 = 1/256
16–3 = 1/4096 Least Signiﬁcant Digit (LSD)
Decimal to Hexadecimal Conversion
Decimal to Hexadecimal conversion can be done by two methods, namely reverse hexadecimal to decimal and repetitive division. These methods are explained below:
Reverse of Hexadecimal to Decimal Conversion The conversion of decimal number into hexadecimal number by using Table 1.8 is explained below: The decimal number (687)10 can be written as summation of 512 (2 × 256), 160 (10 × 16) ñnd 15 (15 × 1). Therefore, hexadecimal equivalent of decimal number can be represented by (687)10 = 2 × (162) + 10 × (161) + 15 × (160) = (2AF)16
Repetitive Division Method For converting decimal to hexadecimal, repeated division method uses successive division by 16. The ﬂowchart for converting decimal number into hexadecimal by repeated division is depicted in Fig.1.9. The example of converting 37810 to hexadecimal is given below:
16
Digital Electronics: Principles and Applications 378/16 = 23+ remainder (Least Signiﬁcant 23/ 16 = 1 + remainder 1 / 16 = 0 + remainder (Most Signiﬁcant Result (378)10 =
10 A Digit) 7 7 1 1 Digit) (17A)16
To convert a decimal number into hexadecimal, a similar process is performed as described in binary and octal. The example is given here the numbers are successively divided by 16: (5789)10 / 16 = 361 remainder 13(D) (361)10 / 16 = 22
remainder 9 (9)
(22)10 / 16 = 1
remainder 6 (6)
(1)10 / 16 = 0
remainder 1 (1) 1 6 9 MSD
Fig. 1.9
1.5.12
D LSD
All of the remainders from the division are then arranged in reverse order, from MSD to LSD to form the Flow chart for converting decimal correct hexadecimal sequence. Therefore, the hexanumber into hexadecimal by decimal equivalent of decimal number (5789)10 is repeated division (169D)16.
Binary to Hexadecimal and Hexadecimal to Binary Conversion
Binary equivalent of hexadecimal digits (0 to F) are shown in Table 1.9. It is depicted in this table that each group of 4 binary digits (bits) is 1 hexadecimal digit. The example of binary to hexadecimal conversion is given below: (1111 1011 0011)2 = (1111) (1011) (0011) = (F B 3)16 . The Hexadecimal number (24657A)16 can be represented by binary number (0010) (0100) (0110) (0101) (0111) (1010)2 = (0010 0100 0110 0101 0111 1010)2. Table 1.9
Binary equivalent of hexadecimal digit
Binary Equivalent
Hexadecimal Digit
0000
0
0001
1
0010
2
0011
3
0100
4
0101
5
0110
6
0111
7 (Contd.)
17
Number System Table 1.9
(Contd.)
1000
1.5.13
8
1001
9
1010
A
1011
B
1100
C
1101
D
1110
E
1111
F
OctaltoHexadecimal and HexadecimaltoOctal Conversion
OctaltoHexadecimal To convert an octal number to hexadecimal number, the following steps are required: In ﬁrst step, the octal number is converted into binary. The second step is regrouping the binary number in 4 bits and a group starts from the LSB. In third step, the 4 bits group binary number can be represented by hexadecimal number. The example is given below. To convert octal number (547)8 to hexadecimal number, step 1, step 2 and step 3 have been presented in tabular form. (547)8 = (101 100 111)2 (Binary) Step 1 = (0001) (0110) (0111)
Step 2
= (167)16 (Hexadecimal )
Step 3
HexadecimaltoOctal Conversion In hexadecimal to binary conversion, three steps are required. The ﬁrst step is to convert hexadecimal to binary. The second step is regrouping the binary number in 3 bits a group which starts from the LSB. In third step, the groups of 3 bits binary number can be represented by octal numbers. One example is the conversion of (5A8)16 to Octal number as follows: To convert hexadecimal number (5A8)16 to octal number, all the three steps are presented below: 5A816
= (0101 1010 1000)2 (Binary)
Step 1
= (010) (110) (101) (000)
Step 2
= (2 6 5 0)8 (Octal)
Step 3
Example 1.8
Convert the following hexadecimal numbers to decimal numbers (a) F2C
� Solution (a) (F2C)16
(b) DF8.28
= F × 162 + 2 × 161 + C × 160 = 15 × 256 + 2 × 16 + 12 × 1 = 3840 + 32 + 12 = 3884
18
Digital Electronics: Principles and Applications
(b)
(DF8.28)16
Example 1.9
= D × 162 + F × 161 + 8 × 160 + 2 × 16–1 + 8 × 16–2 = 13 × 256 + 15 × 16 + 8 × 1 + 2 × 0.0625 + 8 × 0.0039 = 3328 + 240 + 8 + 0.125 + 0.0312 = 3576.1562 Convert the following decimal numbers to hexadecimal numbers (a) 905
(b) 6786
� Solution (a) Conversion of (905)10 to hexadecimal 905/ 16 56/ 16 3/16 Result
= 56+ remainder of 9 = 3 + remainder of 8 = 0 + remainder of 3 (905)10 =
9(Least Signiﬁcant Digit) 8 3(Most Signiﬁcant Digit) 38916
(b) Conversion of (6786)10 to hexadecimal 6786/ 16 424/ 16 26 /16 1/16
= = = =
424+ remainder of 2 26 + remainder of 8 1 + remainder of 10 0 + remainder of 1
Result
(6786)10 =
Example 1.10
2 (Least Signiﬁcant Digit) 8 A 1(Most Signiﬁcant Digit) 1A8216
Convert the following decimal numbers to hexadecimal numbers (a) 0.625
(b) 2824.5
� Solution (a) Conversion of (0.625)10 to hexadecimal Fraction Number
Product
Fractional part
Integer Part
0.625
.625 × 16 = 10
.0
A
(.625)10 is equal to (0.A)16 (b) Conversion of (2824.725)10 to hexadecimal 2824/16 176/ 16 11 /16 Result
= 176+ remainder of 8 = 11 + remainder of 0 = 0 + remainder of 11 282410 =
Fraction Number
Product
.725
8(Least Signiﬁcant Digit) 0 B (Most Signiﬁcant Digit) B 0 816
Fractional part
Integer Part
.725 × 16 = 11.6
.6
B MSD
.6
.6 × 16 = 9.6
.6
9
.6
.6 × 16 = 9.6
.6
9 LSD
(.725)10 is equal to (.B99)16 Therefore, (2824.725)10 is equivalent to (B08.B99)16
Number System Example 1.11
Convert the following hexadecimal numbers to binary numbers (a) A4C
(b) 3E7.DA
� Solution (a) Conversion of (A4C)16 to binary (b) Conversion of (3E7.DA)16 to binary Example 1.12
(A4C)16 = (1010 0100 1100)2 (3E7.DA)16 = (0011 1110 0111.1101 1010)2
Convert the following binary numbers to hexadecimal numbers (a) 101111001011
(b) 1011110011.00110010
� Solution (a) Conversion of (101111001011)2 to hexadecimal (101111001011)2 = (1011) (1100) (1011) = (BCB)16 (b) Conversion of (1011110011.00110010)2 to hexadecimal (1011 1100 1101.00110010)2 = (1011) (1100) (1101) . (0011) (0010) = (BCD.32)16 Example 1.13
Convert the following octal number to hexadecimal number (a) 744 (b) 3472.56
� Solution (a) Conversion of (744)8 to hexadecimal (744)8 = (111 100 100)2 Forming into groups of 4 bits = (0001 1110 0100)2 = (1E4)16 (b) Conversion of (3472.56)8 to hexadecimal (3472.56)8 = (011 100 111 010.101 110)2 Forming into groups of 4 bits = (0111 0011 1010.1011 1000)2 = (73A.B8)16 Example 1.14
Convert the following hexadecimal number to octal number (a) B7A4
(b) D43E.5A
� Solution (a) Conversion of (B7A4)16 to octal (B7A4)16 = (1011 0111 1010 0100)2 Forming into groups of 3 bits = (001 011 011 110 100 100)2 = (133644)8 (b) Conversion of (D43E.5A)16 to octal (D43E.5A)16 = ( 1101 0100 0011 1110 . 0101 1010)2 Forming into groups of 3 bits = (001 101 010 000 111 110 . 010 110 100)2 = (152076.264)8
19
20
1.6
Digital Electronics: Principles and Applications
BINARY ARITHMETICS
In numerical system, the most common arithmetical operations are addition, subtraction, multiplication, division, roots, powers, and logarithms, etc. If we perform one plus one operation, we get two by using simple arithmetic operation of addition. But computers perform arithmetic operations on binary numbers only. In binary arithmetics, the output of one plus one is 0. So, this binary operation of addition can be confusing to a person accustomed to work with decimal arithmetic operation only. In this section, the four basic operations of binary arithmetic are explained.
1.6.1
Binary Addition
It is a very simple task to add two binary numbers and it is very similar to the addition of decimal numbers. In decimal numbers, we start by adding the bits one 0+0=0 column at a time, from right to left. Unlike decimal 1+0=1 addition, there is little to memorise the rules for the 0+1=1 binary addition of bits. The rules of binary addition is 1 + 1 = 0 and a carry 1 ( i.e. 10 in binary) given in Table 1.10. 1 + 1 + 1 = 1 and carry 1 ( i.e. 11 in binary) If the sum in one column is a twobit number, the least signiﬁcant bit is written as part of the total sum and the most signiﬁcant bit is “carried” to the next left column as carry. The following examples of binary addition are given below : Addition of two binary number (1 0 0 1 1 0 1)2 and (0 0 1 0 0 1 0)2 is Table 1.10
Rules of binary addition
1001101 + 0010010 1011111 Similarly, addition of (1 0 0 1 0 0 1)2 and (0 0 1 1 0 0 1)2 is 11 1 1 1 1000111 +0010110 1011101 In the ﬁrst problem of addition, there is no bit to be carried, since the sum of bits in each column was 1 or 0, not 10 or 11. In the other two problems, there are deﬁnitely bits to be carried, but the process of addition is still quite simple.
21
Number System
1.6.2
Binary Subtraction
Table 1.11
To subtract one binary number from another, we use the standard techniques, which are adopted for decimal numbers. The subtraction of each bit pair, from right to left, borrowing as needed from bits to the left. The rules of binary subtraction are shown in Table 1.11. The examples of binary subtractions are given below: The subtraction of 1001 from 101 is 100 and 110.001 from 101.110 is 10.011
Rules of binary subtraction
0–0=0 1–0=1 1–1=0 0 – 1 = 1 with a borrow of 1
1 Borrow bits 1001 –101 100 11 1 1 0 .0 0 1 – 1 0 1 .1 1 0
Borrow bits
0 1 0. 0 1 1 By using rules of binary subtraction, we will be able to subtract two binary numbers as shown above. But there is another method for binary subtraction, i.e., two’s complement. This method is better than conventional method and explained latter on.
1.6.3
Binary Multiplication
Binary multiplication is the same as in realnumber algebra, i.e., anything multiplied by 0 is 0, and anything multiplied by 1 remains unchanged. The rules of binary multiplication are given in Table 1.12. The examples of binary multiplication are given below: The ﬁrst example is the multiplication of (1011010)2 and (11011)2 1011010 ×11011 1011010 1011010× 0000000×× 1011010××× 1011010××××
Table 1.12 Rules of binary multiplication 0×0=0 1×0=0 0×1=0 1×1=1
100101111110 The result of the multiplication of (1011010)2 and (11011)2 is (10 0 1 0 1 1 1 1 1 10)2. The second example to perform (1100)2 ¥ (1010)2 is
22
Digital Electronics: Principles and Applications
1100 ×1010 0000 1100× 0000×× 1100××× 1111000 The result of the multiplication of (1100)2 and (1010)2 is (11110000)2. The third example is multiplication between (1.01)2 and (10.1)2 1.01 ×10.1 101 000× 101×× 1 1. 0 0 1 The result of the multiplication of (1.01)2 and (10.1)2 is (1 1 . 0 0 1)2.
1.6.4 Binary Division Division can be performed by repetitive subtraction. The rules of binary division are given below: The example of binary division is presented below: Table 1.13
Rules of binary The division of (1100010)2 by (111)2 is (1110)2 as calculated division below
0/0 = Undeﬁned
111) 1100010 (1110 111
1/0 = Undeﬁned 0/1 = 0
01010 111
1/1 = 1
00111 111 000 Example 1.15
Add the following binary numbers (a) 10101 11010
(b) 1001 0011
Number System � Solution a) 1 0 1 0 1 11010 101111 Carry 11 (b) 1 0 0 1 0011
Carry
1100
Example 1.16
Subtract the following binary numbers (a) 101010 – 100
(b)
1110010 – 0000110
Solution 1 Borrow (a) 101010 –100
�
100110 (b)
1110010 – 0000110 1101100
Example 1.17
�
Multiply the following binary numbers (a) 10101
(b) 1111
× 101
× 1100
Solution (a)
10101
×101 10101 00000× 10101×× (b)
1101001 1111 ×1100
23
24
Digital Electronics: Principles and Applications 0000 0000× 1111×× 1111××× 10110100
Example 1.18
Divide the following binary numbers (a) 110)100001
(b) 111)1011011
� Solution (a) 1 1 0 ) 1 0 0 0 0 1 ( 1 0 1.1 110 1001 110 110 110 (b)
1 1 1 ) 1 0 1 1 0 1 1 (1101 111 1000 111 111 111
1.7
SIGNED MAGNITUDE
This is one of the simplest codes. In this code, initially the decimal number is converted from base 10 into base 2 and then an additional bit is added to code the sign of the number. The ﬁrst bit of binary number is dedicated to represent positive or negative sign—sign ‘0’ for positive ‘+’ and sign ‘ 1’ for negative ‘–’. The rest represent the absolute value of magnitude. The sign magnitude numbers from –7 to +7 are depicted in Fig. 1.10. The example of 8 bit signed magnitude numbers are given below: +3 = 00000011 –3 = 10000011 +15 = 00001111 +30 = 00011110 –30 = 10011110 +50 = 00110010 –50 = 10110010
25
Number System
1.8
ONE’S COMPLEMENT
The one’s complement of a binary number can be obtained by substituting each ‘1’ by ‘0’ and ‘0’ by ‘1’. The example of one’s complement is shown in Table 1.14. From Table 1.14, it is very clear that ﬁrst bit is sign bit and +3 is complement of –3 as shown below: +3 = 00000011 –3 = 11111100 Fig. 1.10 Table 1.14
Signmagnitude number
One’s complement number
Positive Decimal Number
Binary Equivalent
Negative Decimal Number
One’s Complement of Binary Equivalent
+0
0000
–0
1111
+1
0001
–1
1110
+2
0010
–2
1101
+3
0011
–3
1100
+4
0100
–4
1011
+5
0101
–5
1010
+6
0110
–6
1001
+7
0111
–7
1000
The positive number +0 to +7 can be represented by Table 1.14 and negative number – 0 to –7 are also shown in Table 1.14. The range for n bit number is +/(2n–1–1).
1.9
TWO’S COMPLEMENT
The two’s complement of a binary number can be obtained from the following steps: Step1: Firstly, complement each bit of binary number i.e. ‘1’ is replaced by ‘0’ and ‘0’ is replaced by ‘1’ to get one’s complement. Step2: Add 1 to this one’s complement to obtain two’s complement. By using a general representation, two’s complement can be written as 2’s complement = Bit wise complement +1 Let us take an example of two’s complement of a binary number (0100)2 or (+4)10. One’s complement is 1011 and after adding 1 with this number we get (1100) – 4. Therefore two’s complement represents the magnitude of a number. Figure 1.11 shows the two’s complement of number and Table 1.15 also depicts the two’s complement of numbers.
Fig. 1.11
Two’s complement of numbers
26
Digital Electronics: Principles and Applications Table 1.15 Two’s complement numbers Zero
positive one positive two positive three positive four positive ﬁve positive six positive seven
0000
0001 0010 0011 0100 0101 0110 0111
negative one negative two negative three negative four negative ﬁve negative six negative seven negative eight
1111 1110 1101 1100 1011 1010 1001 1000
Two’s complement is the code used by microprocessors to represent integer numbers. Two’s complement is preferred over other codes because it simpliﬁes the structure of the hardware required to implement arithmetical operations, such as additions and subtractions.
1.10
SUBTRACTION BY USING TWO’S COMPLEMENT
The negative binary numbers can be represented by the two’s complement. Here, we will use the negative binary number to subtract through addition. The example is subtraction of 810 – 510. This is actually addition of 810 + (–510). For addition of 810 + (–510), it is required to represent eight and negative ﬁve in binary. The positive eight is equivalent to (1000)2. Negative ﬁve is represented by two’s complemented form as given below: Negative ﬁve is equivalent to 10112. Then addition of positive eight 10002 and negative ﬁve, 10112 is as follows 1 Carry bits 1000 +1011 10011 Discard extra bit After discarding the ﬁfth bit (extra bit) in the answer, the correct answer is 00112 or positive three. Another example is to perform (14)10 – (11)10. The number (14)10 is equivalent to (00001110)2 and –(11)10 is represented by 11110101 in two’s complement form. The addition of two numbers is shown below: 14 = 0 0 0 0 1 1 1 0 – 11 = + 1 1 1 1 0 1 0 1 3
00000011
Here, an additional example of subtraction with larger numbers. If we would like to add 2510 to 1810, ﬁrstly we represent 2510 and 1810 in binary form. Initially, represent negative twentyﬁve, then ﬁnding the two’s complement. Five bits are required to represent twenty ﬁve and one extra bit is also required for the negative weight bit. In this way, six bits are used for binary representation of 2510 .
Number System
27
Positive twenty ﬁve, +2510 = 0110012 One’s complement of (11001)2 = (100110)2 Two’s complement of (11001)2 = One’s complement + 1 = (100111)2 . Therefore, –2510 is equivalent to (100111)2. Positive eighteen in binary form is 1810 = 0100102 Then add these two binary numbers Carry bits
11 100111 +010010
111001 As there are no extra bits, no bits will be discarded. The leftmost bit is 1 and the answer should be negative in two’s complement form. Initially, the result will be converted into decimal by summing all the bits respective weight; we obtain the ﬁnal result as given below: 1 × (–32) + 1 × 16 + 1 × 8 + 1 × 1 = –7. Example 1.19
Perform the following operations (a) (–15)10 + (–22)10
(b) (22)10 –(15)10
� Solution (a) 15 = 0000 1111 in 8 bit notation one’s complement of 15 = 1111 0000 In two’s complement form, –15= 1111 0000 + 1 = 1111 0001. 22 = 0001 0110 in 8 bit notation one’s complement of 22 = 1110 1001 In two’s complement form, –22 = 1110 1001 + 1 = 1110 1010. 11110001 –15 11101010 –22 111011011 (b)
22 = 0001 0110 –15 = 1111 0001 00010110 11110001
–37
22 –15
100000111
7
Discard extra bit
1.11 OVERFLOW In digital system, the size of the word is ﬁxed. If the magnitude of the number after addition or subtraction operation exceeds the allotted number of bits, an overﬂow occurs. Therefore, errors are generated. With
28
Digital Electronics: Principles and Applications
eight bits, we can represent one hundred twenty eight steps from zero to one hundred twenty seven (0 to +127) or (0 to –127). This means that maximum number is +127 (0111 1111) and lowest number is –128 (1000 0000). In this case, the eighth binary digit is used to represent sign. During addition of two binary numbers, if the result is more than +127, over ﬂow exists. Consider two numbers (64)10 and (75)10. The binary representation of (64)10 and (75)10 are (64)10 = (0100 0000)2 and (75)10= (0100 1011)2 respectively. The addition of two binary numbers (0100 0000)2 and (0100 1011)2 is shown below: 0100 0000 0100 1011
(64)10 (75)10
1000 1011
(–11)10
The result is (1000 1011)2. After discarding the left most bit, the result will be incorrect as it is negative number (–11)10 in place of (139)10. Another example is addition of two negative numbers (–64)10 and (–75)10. (–64)10 = 1111 1110 (–75)10 = 1011 0101 11011 0011 The result of addition of (–64)10 and (–75)10 is equal to (11011 0011)2. After discarding the extra bit, the result is (–41)10, but the correct answer is (–139)10 . Therefore, to get the correct results bit ﬁelds must be sufﬁciently large. Presently, consider nine bits to represent numbers and the ninth bit (most signiﬁcant bit) can be used as sign bit. Then the addition of (+64)10 & (+75)10 and (–64)10 & (–75)10 are given below : Addition of (+64)10 & (+75)10 0 0100 0000 0 0100 1011
(+64)10 (+75)10
0 1000 1011
(+139)10
Addition of (–64)10 & (–75)10 (–64)10 = 1 1111 1110 (–75)10 = 1 1011 0101 (–139)10 = 11 1011 0011 Discard Form the above examples; we get correct answers by using sufﬁciently large bit ﬁelds to handle the magnitude of the sums. The overﬂow can be detected after decimal addition and compare the result with binary answers. After addition (+64)10 and (+75)10 we are supposed to get (+139)10, but binary sum checked out to be (–11)10. Therefore, we can say that something has to be wrong. Actually overﬂow is the reason for wrongness. Auspiciously, overﬂow detection is easily implemented in electronic circuits and it is a standard feature in digital adder circuits.
29
Number System
1.12 BINARY CODED DECIMAL (BCD) NUMBER SYSTEM We are already familiar with the Binary, Decimal and Hexadecimal Number System. If we represent single digit values for hex, the numbers 0  F, and then these numbers can represent the values 0 – 15 in decimal, and occupy a nibble. Often, we wish to use a binary equivalent of the decimal system. This system is called Binary Coded Decimal or BCD, which also occupies a nibble. In BCD, the binary patterns 1010 through 1111 do not represent valid BCD numbers, and cannot be used. Table 1.16 shows the BCD equivalent of decimal number from 0 to 9. This Code is called as 8421 BCD code. This code replaces each decimal ﬁgure with a group of 4 bits in binary form. The conversion from Decimal to BCD is performed according to Table 1.16. Table 1.16
Decimal Number
BCD code
Binary Coded Decimal Number 8
4
2
1
0
0
0
0
0
1
0
0
0
1
2
0
0
1
0
3
0
0
1
1
4
0
1
0
0
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
8
1
0
0
0
9
1
0
0
1
Conversion from Decimal to BCD is very simple as shown in Table 1.16. Each digit of the decimal number can be represented by a byte. Then we can convert 0 through 9 to 0000 0000 through 0000 1001. The BCD equivalent value for the decimal number 5,219 is shown below. Since there are four digits in our decimal number, there are four bytes in our BCD number. Thousands
Hundreds
Tens
Units
5
2
1
9
00000101
00000010
00000001
00001001
In computer, the minimum of 1 byte is required for storage of a number. Therefore, we can say that the upper nibble of each BCD number is wasting storage space. BCD is still a weighted position number system so we can perform mathematics, but we must use special techniques in order to obtain a correct answer.
1.13
PACKED BCD
The storage data on disk and in RAM is so valuable, we would like to eliminate this wasted storage. This may be accomplished by packing the BCD numbers. In a packed BCD number, each nibble has a weighted position starting from the decimal point. Therefore, instead of requiring 4 bytes to store the BCD number 5219, we can represent it by using 2 bytes, i.e., half the storage. The upper nibble of the upper byte of the
30
Digital Electronics: Principles and Applications
number will be stored as the THOUSANDS value and the lower nibble of the upper byte can be stored as the HUNDREDS value. Similarly, the lower byte would store the TENS value in the upper nibble and the UNITS digit in the lower nibble. Therefore, 5219 can be represented by 2 bytes as shown below: Thousands  Hundreds Tens  Units 5
2
0101
1
0010
9
0001
1001
The example of conversion from decimal to BCD is illustrated below: Decimal Number
1.14
BCD equivalent
123
0001 0010 0011
99
1001 1001
255
0010 0101 0101
5487
0101 0100 1000 0111
GRAY CODE (REFLECTED CODE)
The BCD code is a weighted code and each bit position has been assigned a deﬁnite weight. But the Gray code is a nonweighted code. In this code, weights are not assigned to the bit positions. Actually, Gray code is ordering of 2n binary numbers such that only one bit changes from one entry to the next. On the other hand, we can say that in this code successive numbers differ by only one digit. This code is very useful in mechanical encoders since a slight change in position only affects one bit. This is useful in avoiding erroneous counts and in designing reliable sequential control modules. Using a typical binary code, up to ‘n’ bits could change, and slight misalignments between reading elements could cause wildly incorrect readings. In 1878, French Engineer Emile Baudot used Gray code in telegraph. Frank Gray ﬁrst patented the codes in 1953. To construct a Gray code for ‘n’ bits, we take a Gray code for ‘n1’ bits with each code preﬁxed by 0 and append the ‘n1’ Gray code reversed with each code preﬁxed by 1. This is called a Binaryreﬂected Gray code. The example of creating a 3bit Gray code from a 2bit Gray code is given in Table 1.17. According to this table, 3bit Gray code is (000, 001, 011, 010, 110, 111, 101, 100). Another 3 bit Gray code is (000, 010, 011, 001, 101, 111, 110, 100). Table 1.18 shows the Gray code of 4 bit binary number. Table 1.17
A 3bit Gray code from a 2bit Gray code
00
01
11
10
A Gray code for 2 bits
000
001
011
010
The 2bit code with ‘0’ preﬁxes
10
11
01
00
The 2bit code in reverse order
110
111
101
100
The reversed code with ‘1’ preﬁxes
000
001
011
010
110
111
101
100
A Gray code for 3 bits
Table 1.18 Four bit Gray code
Decimal Number Binary Number Gray Code Decimal Number
Binary Number
Gray Code
0
0000
0000
8
1000
1100
1
0001
0001
9
1001
1101
2
0010
0011
10
1010
1111
3
0011
0010
11
1011
1110 (Contd...)
31
Number System Table 1.18
(Contd...)
4
0100
0110
12
1100
5 6 7
1010
0101
0111
13
1101
1011
0110
0101
14
1110
1001
0111
0100
15
1111
1000
Consider the binary numbers for decimal numbers 3 and 4. We can see that there is a change in three bit positions. So the chance of error increases in binary numbers. In the Gray code, since only onebit position changes between decimal numbers 3 and 4, the chances of errors are reduced. As less number of bit changes are required for two numbers and a ﬁnite time is also required for each bit change, the Gray code circuit can operate at higher speed. The disadvantage of the Gray code is that it cannot be used in arithmetic operations. If addition, subtract, etc operations are necessary, the Gray code is converted into binary and then arithmetic operations will be performed using binary data.
1.15 GRAY CODE TO BINARY CONVERSION Using simple arithmetic method, we can do the conversion from Gray code to binary. The rules of arithmetic method for Gray code to binary conversion is as given below: Rule1 The most signiﬁcant bit (MSB) of the Gray code can be used as most signiﬁcant bit (MSB) in the binary. Rule2 The most signiﬁcant bit (MSB) of binary will be added with the next bit immediately on its right. Determine the sum and carry should be ignored. Rule3 Continuously add bits to bits immediately to their right until adding of all bits are completed. Rule4 The binary equivalent of Gray code is the result and the number of bits will be same as the Gray code. This method has been explained with Fig. 1.12. Consider a Gray code 1000 and it can be converted into its binary. According to rule 1, there is no change in the most signiﬁcant bit (MSB) of Gray code and binary. Hence MSB of binary is 1. Then apply rule 2. So, MSB of the binary number can be added with the next bit of Gray Fig. 1.12 Gray code to binary conversion code immediately on its right. Determine the sum and carry should be ignored. The result of addition 1 and 0 is 1 and it can be considered as the next bit of the binary number. According to rule 3, this bit is added with the next bit that is 0. The result of operation 1 + 0 is 1. So 1 is added to 0 of the LSB and the sum is 1. The ﬁnal result is 1111, which is the binary equivalent of Gray code.
1.16 BINARY TO GRAY CODE CONVERSION The binary to Gray code conversion rules are similar with the Gray code to binary conversion. In this case also the MSB of binary can be used as the MSB of the Gray code. The MSB of the binary number is then added to the next bit to its right. The sum can represent the next bit of the Gray code. The
32
Digital Electronics: Principles and Applications
process can be repeated upto the LSB. The binary to Gray code conversion of binary number 1010 is shown in Fig. 1.13. The Gray code 1111 is the equivalent of the binary number 1010.
1.17
EXCESS3 (XS3) CODE
The Excess3 (XS3) code is a nonweighted code and it is used with binary coded decimal (BCD) numbers. This code is an Fig. 1.13 Binary to Gray code important 4bit code and each 4bit code represents a speciﬁc conversion decimal digit. Table 1.19 shows the BCD code and the XS3 code for decimal digits from 0 through 9. It is very clear from the above table that the Excess 3 (XS3) code number is three graters than BCD equivalent. The example is that the BCD code for decimal digit 7 is 0111 but the said number in Excess 3 (XS3) code is 1010. This code simpliﬁes the BCD addition and other arithmetic operations. Therefore, the Excess3 (XS3) code has been used in arithmetic operations. Table 1.19
1.18
Excess3 code
Decimal Digit
BCD Code
XS3 Code
0 1 2 3 4 5 6 7 8 9
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001
0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
DECIMAL TO EXCESS3 (XS3) CONVERSIONS
To convert any decimal number into it’s XS3 form, we add 3 to the decimal number and then the sum is converted into BCD number. The example is conversion of decimal number 5 into XS3 code. Initially, we add 3 with the decimal number 5: Decimal number 5 Add 3 3 Sum 8 Then we convert the sum to BCD form. So the decimal number 5 represents 1000 in Excess 3 (XS3) code.
1.19
WEIGHTED BCD CODES
We are already familiar with the binary code. It is a weighted code as it is represented by the 8421 BCD code. There are also some weighted codes namely 4221, 2421, and 5211. The numbers 8, 4, 2 and 1 represent the weights of the bit positions. Similarly, weighted codes 4221, 2421, and 5211 are also used to represent the weight of the bit position. Table 1.20 shows the weighted BCD code.
33
Number System Table 1.20
Decimal Digit
The weighted BCD code
8421
Weighted BCD Codes 4221 2421
0 1 2 3 4 5 6 7
0000 0001 0010 0011 0100 0101 0110 0111
0000 0001 0010 0011 1000 0111 1100 1101
0000 0001 0010 0011 0100 1011 1100 1101
0000 0001 0011 0101 0111 1000 1010 1100
8 9
1000 1001
1110 1111
1110 1111
1110 1111
Example 1.20
Determine the decimal equivalent of the following BCD numbers (a) 0011 1001 0101 0001
(b) 1001 0111 0011 0101
� Solution (a) BCD number is 0011 1001 0101 0001. The BCD number is divided into 4bit groups and then converted into decimal equivalent 0011 1001 0101 0001 = (0011) (1001) (0101) (0001) = 3951 (b)
BCD number is 1001 0111 0011 0101. The BCD number is divided into 4bit groups and then converted into decimal equivalent 1001 0111 0011 0101 = (1001) (0111) (0011) (0101) = 9735
Example 1.21
Determine the XS3 equivalent of the following decimal numbers (a) 345
(b) 698
� Solution (a) Firstly, add 3 to each decimal digit. Then convert into BCD form Decimal number 345 Add 3 333
(b)
678 The XS3 equivalent of 345 is 0110 0111 1000. Firstly, add 3 to each decimal digit. Then convert into BCD form Decimal number 698 Add 3 333
9 12 11 The XS3 equivalent of 698 is 1001 1100 1011.
5211
34
Digital Electronics: Principles and Applications
Example 1.22
Convert the following XS3 numbers into decimal numbers (a) 1011 (b) 1001 0011 0111
� Solution (a) Subtract 3 from XS3 number and then convert into decimal form XS3 number 1011 Subtract 3 0011 1000 The decimal equivalent of XS3 number 1011 is 8 . (b)
Subtract 3 from XS3 number and then convert into decimal form XS3 number 1001 0011 0111 Subtract 3 0011 0011 0011 0110 0000 0100 The decimal equivalent of XS3 number 1001 0011 0111 is 604 .
Example 1.23
Convert the following binary numbers into Gray code number (a) 1010 (b) 1101
� Solution (a) 1 0 1 0 Add 1 + 0 = 1, Add 0 + 1 = 1, Add 1 + 0 = 1 1111 (b) 1 1 0 1 Add 1 + 1 = 0, Add 1 + 0 = 1, Add 0 + 1 = 1 1011
Example 1.24
Convert the following decimal numbers into 4221 BCD code (a) 575
(b) 945
� Solution (a) 5 represent 1001 7 represent 1101 5 represent 1001 Therefore, 4221 BCD representation of 575 is 1001 1101 1001. (b)
9 represent 1111 4 represent 1000 5 represent 1001 Hence, 4221 BCD representation of 945 is 1111 1000 1001.
Number System
35
1.20 ASCII CODE A computer handles numerical and nonnumerical data for communication with environment. So, computer should recognise the characters, numbers, symbols, punctuations, etc. by using alphanumeric Fig. 1.14 7 bit ASCII code codes. Most commonly used alphanumeric code is ASCII code. ASCII code stands for American Standard Code for Information Interchange. ASCII is pronounced as “Askee”. This code is extensively used for digital data communication, and digital computers. It is a 7bit code. This code is used to represent each small and capital letter, numerical digits (0 to 9) and punctuation characters. This 7bit code is made up of a 3bit group followed by a 4bit group as shown in Fig.1.14. For example, if we want to represent A, the 3bit group is 010 and 0001 stands for 4bit group. Therefore, the 7bit code for A is 0100001. Computers process data in byte form. So ASCII is also used to represent data in byte form and this representation is called Extended ASCII. The Extended ASCII set uses 8bits codes and comprises special symbols for generating tables and other simple graphical elements. Extended ASCII code for A is 10100001. There are 128 characters in ASCII. The ASCII character set except the extended characters is divided into four groups of 32 characters. All four groups of ASCII codes are represented in combined form as shown in Table 1.21 and all four groups are explained below:
ASCII Code  Group I The ﬁrst 32 characters of ASCII codes represented by 00H through 1FH are called the control characters. This group of codes is formed for a special set of nonprinting characters and these characters are used to perform various printers and display control operations. Table 1.21 shows the data representation of the ASCII code for the characters 00H through 01FH. The examples of common control characters are given here. For example, ASCII code for carriage return operation is 0DH. This changes the position of the cursor to the left side of the current line of characters. Similarly in line feed operation the ASCII code is 0AH, which moves the cursor down one line on the output device. Another example is backspace, which moves the cursor back one position to the left. For this operation ASCII code is 08H. ASCII Code  Group II The second group of 32 ASCII character codes is used for various punctuation symbols, special characters, and the numeric digits. The data representation of the ASCII code for the characters 20H through 3FH is depicted in Table 1.21. The examples of the second group of ASCII code are space character and numeric digits 0 to 9. For space character, ASCII code is 20H and numeric digits 0 through 9 can be represented by ASCII codes 30H through 39H. ASCII Code  Group III The 32 characters of ASCII code group III are reserved for the upper case alphabetic characters and six special symbols. Table 1.21 shows the data representation of the ASCII code for the characters 040H through 05FH. The ASCII codes for the characters “A” through “Z” lie in the range 41H through 5AH. In view of the fact that there are only 26 different alphabetic characters and the remaining six codes hold various special symbols. ASCII Code  Group IV The fourth and last group of 32 ASCII character codes is reserved for the lower case alphabetic symbols, ﬁve additional special symbols, and the control character namely delete. Table 1.21 shows the data representation of the ASCII code for the characters 60H through 7FH.
36
Digital Electronics: Principles and Applications
Table 1.21
ASCII Code – Group I HEX DEC CHR CTRL
ASCII code chart
ASCII Code – Group I I HEX DEC CHR
ASCII Code – Group III HEX DEC CHR
ASCII Code – Group IV HEX DEC CHR
00
0
NUL
^@
20
32
SP
40
64
@
60
96
‘
01
1
SOH
^A
21
33
!
41
65
A
61
97
a
02
2
STX
^B
22
34
“
42
66
B
62
98
b
03
3
ETX
^C
23
35
#
43
67
C
63
99
c
04
4
EOT
^D
24
36
$
44
68
D
64
100
d
05
5
ENQ
^E
25
37
%
45
69
E
65
101
e
06
6
ACK
^F
26
38
&
46
70
F
66
102
f
07
7
BEL
^G
27
39
‘
47
71
G
67
103
g
08
8
BS
^H
28
40
(
48
72
H
68
104
h
09
9
HT
^I
29
41
)
49
73
I
69
105
i
0A
10
LF
^J
2A
42
*
4A
74
J
6A
106
j
0B
11
VT
^K
2B
43
+
4B
75
K
6B
107
k
0C
12
FF
^L
2C
44
,
4C
76
L
6C
108
l
0D
13
CR
^M
2D
45
−
4D
77
M
6D
109
m
0E
14
SO
^N
2E
46
.
4E
78
N
6E
110
n
0F
15
SI
^O
2F
47
/
4F
79
O
6F
111
o
10
16
DLE
^P
30
48
0
50
80
P
70
112
p
11
17
DC1
^Q
31
49
1
51
81
Q
71
113
q
12
18
DC2
^R
32
50
2
52
82
R
72
114
r
13
19
DC3
^S
33
51
3
53
83
S
73
115
s
14
20
DC4
^T
34
52
4
54
84
T
74
116
t
15
21
NAK
^U
35
53
5
55
85
U
75
117
u
16
22
SYN
^V
36
54
6
56
86
V
76
118
v
17
23
ETB
^W
37
55
7
57
87
W
77
119
w
18
24
CAN
^X
38
56
8
58
88
X
78
120
x
19
25
EM
^Y
39
57
9
59
89
Y
79
121
y
1A
26
SUB
^Z
3A
58
:
5A
90
Z
7A
122
z
1B
27
ESC
3B
59
;
5B
91
[
7B
123
{
1C
28
FS
3C
60
5E
94
^
7E
126
~
1F
31
US
3F
63
?
5F
95

7F
127
DEL
37
Number System
The lower case character symbols use the ASCII codes 61H through 7AH. The upper case and lower case characters differ from their lower case equivalents in exactly one bit position that is bit ﬁve. Upper case characters always contain a zero in bit ﬁve but lower case alphabetic characters always contain a one in bit ﬁve. Example 1.25
What is the ASCII code of message “MAY I HELP YOU”?
� Solution Using the Table1.21, the message can be represented in the hex code and 7bit ASCII code Character Hex Code ASCII Code MAY 4D 41 59 100 1101 100 0001 101 1001 I 49 100 1001 HELP 48 45 4C 50 100 1000 100 0101 100 1100 101 0000 YOU 49 4F 55 100 1001 100 1111 101 0101
Example 1.26
The ASCII code message, 100 0111 100 1111 100 0100 is stored in memory of a computer. What is the message?
� Solution Using the Table1.21, the ASCII code message can be represented by characters ASCII Code Character 100 0111 G 100 1111 O 100 0100 D
1.21 EBCDIC The EBCDIC is an 8bit code primarily used by IBM and IBM compatible computer systems. It is known as Extended Binary Coded Decimal Interchange Code. Like ASCII code, it is also widely used in digital data communication of large computers. It is an 8bit code. This 8bit code is made up of two groups. Group  I represents the zone and Group  II stands for numeric data as depicted in Fig. 1.15. This code is used to represent the various characters, printable special characters and nonprintable control characters. The printable control characters are printer vertical spacing, and movement of cursor, etc. The Extended Binary Coded Decimal Interchange Code (EBCDIC) for representing characters (A to Z), digits (0 to 9) and a few special characters are shown in Table 1.22. It is observed that this code is similar, to punch card codes.
Fig. 1.15
8 bit EBCDIC
38
Digital Electronics: Principles and Applications Table 1.22 EBCDIC
Character
Zone
Numeric
Hexadecimal
Character
Zone
Numeric
Hexadecimal
A.
1100
0001
C1
0
1111
0000
F0
B.
1100
0010
C2
1
1111
0001
F1
C.
1100
0011
C3
2
1111
0010
F2
D.
1100
0100
C4
3
1111
0011
F3
E.
1100
0101
C5
4
1111
0100
F4
F.
1100
0110
C6
5
1111
0101
F5
G.
1100
0111
C7
6
1111
0110
F6
H.
1100
1000
C8
7
1111
0111
F7
I.
1100
1001
C9
8
1111
1000
F8
J.
1101
0001
D1
9
1111
1001
F9
K.
1101
0010
D2
Blank
0100
0000
40
L.
1101
0011
D3
.
0100
1011
4B
M.
1101
0100
D4
0110
1110
6E
Z.
1110
1001
E9
?
0110
1111
6F
:
0111
1010
7A
#
0111
1011
7B
@
0111
1100
7C
=
0111
1110
7E
1.22
PARITY BIT
During transmitting data from one system to another system, if one bit of 8 bit data is lost; an incorrect code will be received at receiving end. This data lost may occur due to electrical disturbance during data transmission, unacceptable humidity level and dust particle on storage media. To overcome this
39
Number System
problem, an extra bit is added with data for detecting errors. This extra bit is called as parity bit. There are two types of parity bit, namely even parity and odd parity. In even parity, the parity bit is selected in such a way that even numbers of ones are in word. In case of odd parity, the parity bit is selected so that total numbers of ones is an odd number. When even number of ones is present in a word, this is known as even parity word. Similarly, if odd numbers of ones are present in a word, the word is called odd parity word. The example of even parity word and odd parity word are given below: Even parity word
1001 1111
Odd parity word
1000 1001
ASCII code information is actually 7bit code. During communications, 8bit information (7 bit for ASCII code and one extra bit for parity) has been transmitted accurately. The extra bit or parity bit can be generated by parity generator. The circuit diagram of odd parity bit generator is shown in Fig. 1.16. Exclusive OR gate is used to generate the parity bit as output of this gate is 1 when only one input is 1 and other is 0. Seven input Exclusive – OR gate has been depicted in Fig. 1.16 Odd parity bit generation the ﬁgure for generating parity bit. When ASCII code is 100 1111, a parity bit 1 is added with data to make it even number of ones. Then the new code after addition of parity bit is 1100 1111. ASCII Code
1001111
Data
11001111
Parity bit In another example, the ASCII code is 100 0100, a parity bit 0 is added with data as even number of ones are already present in data. After addition of parity bit, the code has been changed to 0100 0100. Table 1.23 and Table 1.24 represent the even parity and odd parity respectively. ASCII Code 100 0100 Data
0 1000100
Parity bit Table 1.23 Even parity
ASCII Code
Parity bit
Word transmitted
Word received
100 0001 100 0010 100 0011 100 0100
0 0 1 0
0 100 0001 0 100 0010 1 100 0011 0 100 0100
0 100 0001 0 100 0010 1 100 0011 0 100 0100
40
Digital Electronics: Principles and Applications Table 1.24
Odd parity
ASCII Code
Parity bit
Word transmitted
Word received
100 0001 100 0010 100 0011 100 0100
1 1 0 1
1 100 0001 1 100 0010 0 100 0011 1 100 0100
1 100 0001 1 100 0010 0 100 0011 1 100 0100
Figure 1.17 shows the block diagram of digital data transmission. Here, two devices, namely transmitter and receiver are communicating with even parity. In this digital data transmission, parity generator is used at the side of transmission and parity checker is also required at receiving end. The transmitting device sends data and parity generator counts the number of set bits in each group of seven bits. When the number of set bits is even, parFig. 1.17 Digital data transmission ity generator sets the parity bit to 0. If the number of set bits is odd, parity generator sets the parity bit to 1. As a result, every byte has an even number of set bits. At the receiving end, the receiver receives transmitted data. Then parity checker checks each byte to make sure that it has an even number of set bits. When parity checker ﬁnds an odd number of set bits, the receiver knows that there was an error during transmission. Therefore, during digital data transmission, the sender and receiver must both agree to use parity checking and there will be advanced agreement whether parity is to be odd or even. If sender and receiver are not conﬁgured with the same parity, communication will be impossible. Parity checking is most commonly used in communications and testing memory storage devices. Generally, computers perform parity check on memory when each byte of data is read from memory.
1.23
ERROR CORRECTING CODE: HAMMING CODE
Binary data can be transmitted through any communication medium such as optical ﬁber cables or radio waves. If any noise is introduced in a communication system, there will be some error between the transmitted and received data. Therefore, an error detecting code should be used to detect errors during data transmission. Parity bit checking is commonly used to detect error, but it cannot correct the errors (discussed in Section 1.22). The errors can be corrected by error correcting code which is known as hamming code.
41
Number System
The hamming code was developed by R.W. Hamming. In this code, one or more parity bits are added to the data in such a way that error can be detected and corrected. The number of bits changed from one code word to another code word is called as hamming distance. Now consider Ai and Aj are to be any two code words. The hamming distance dij between two different codewords Ai and Aj is deﬁned by the number of components in which they differ. Assuming that dij is determined for each pair of code words, the minimum value of dij is known as the minimum hamming distance dmin. 7
6
5
4
3
2
1
¨
Bit Position
1
0
0
1
0
1
1
¨
Ai
1
¨
Aj
Ø 1
0
1
Ø 1
0
0
In the above example, the code words differ in the second and ﬁfth bit positions from the right. Therefore Dij is 3. The important properties of hamming code distance is that— i. To detect single error, dmin should be at least two. ii. For single error correction, dmin should be at least three. The relationship between number of errors and minimum hamming distance dmin is E £ (dmin – 1)/2. iii. When the values of dmin is greater than 3, more number of errors will be detected and corrected. This code should have a minimum distance of three between two code words, in order to achieve single bit error detection and correction. The code word consists of parity check bits and message bits. When ‘r’ represents the number of parity check bits, the codeword must be 2r – 1 bits. The number of message bits are determined from m = 2r – 1 – r. For example, if r = 3, the maximum number of message bits are four as m = 2r – 1 – r = 23 – 1 – 3 = 4. The bit positions in the code word are numbered from 1 to 2r – 1 and the position of parity bit in the code word is a power of 2. In a 7bit codeword, the format of the transmitted codeword (TC) bits position are 7, 6, 5, 4, 3, 2, and 1, and the parity bits occupy position 1, 2 and 4. Assume TC = b3 b2 b1 r3 b0 r2 r1. The 7bit hamming (7,4) code word is b3 b2 b1 r3 b0 r2 r1 which is associated with binary message bits b3 b2 b1 b0. In the above TC = b3 b2 b1 r3 b0 r2 r1, the positions occupied by the parity bits 100 (4), 010(2) and 001(1). The message bits occupy the bit positions 011(3), 101(5) 110(6) and 111(7). The parity bit r1 can be determined by EXORing the message bits in bit positions 7, 5, and 3. Therefore, r1 = b3 ≈ b1 ≈ b0 The parity bit r2 is obtained by EXORing the message bits in position 7, 6 and 3 so that r2 = b3 ≈ b2 ≈ b0 Lastly r3 is expressed by EXORing the message bits in bit positions 7, 6 and 5 r3 = b3 ≈ b2 ≈ b1
42
Digital Electronics: Principles and Applications
For example, when the message bits b3 b2 b1 b0 = 1011, the parity check bits are determined from r1 = b3 ≈ b1 ≈ b0, r2 = b3 ≈ b2 ≈ b0, and r3 = b3 ≈ b2 ≈ b1. Here the parity check bits are r1s, r2s, r3s and which are transmitted with message bits. r1s = 1 ≈ 1 ≈ 1 = 1;
r2s = 1 ≈ 0 ≈ 1 = 0;
r3s = 1 ≈ 0 ≈ 1 = 0
Then, the transmitted codeword or Hamming code is TC = b3 b2 b1 r3 b0 r2 r1 = 1010101 If the code word is transmitted, the message is received at the receiving end and we ﬁnd an error in bit b0. Then the received codeword is RC= b3 b2 b1 r3 b0 r2 r1 =1010001 To determine the error in the received codeword, the parity bits at the receiving end must be determined as follows: r1r = 1 ≈ 1 ≈ 0 = 0;
r2r = 1 ≈ 0 ≈ 0 = 1;
r3r = 1 ≈ 0 ≈ 1 = 0
The position of the error can be determined by EXORing the transmitted and received parity bits. r1s ≈ r1r = 1 ≈ 0 = 1; r2s ≈ r2r = 0 ≈ 1 = 0; r3s ≈ r3r = 0 ≈ 0 = 0 Then error can be indicated by code 011 which indicates that there is an error in the third bit position of codeword.
SUMMARY Decimal, binary, octal and hexadecimal number systems are explained briefly. The conversions from one number system to others are incorporated in this chapter. The rules of binary arithmetic operations, namely addition, subtraction, multiplication and division are discussed with examples. The signed numbers, one’s complement and two’s complement of numbers are discussed in detail. The application of two’s complement in binary subtraction is also included with examples. To represent numbers, alphabets and special symbols, different codes are used. In this chapter, BCD, Packed BCD, Gray code, Excess 3 code, weighted BCD code, ASCII code and EBCDIC are explained properly. The conversion from one code to other is also discussed. The ASCII code is an alphanumeric code and it is commonly used in computer for digital data transmission. During the digital data transmission from one computer to other, there may be some error due to the presence of electrical noise. To detect error, parity bit is used. The error detection and correction technique is also explained.
MULTIPLE CHOICE QUESTIONS 1.
Which of the following is the limitation of analog electronics? (a) Slow speed (c) Combination of (a) and (b) (b) High speed (d) None of these
Number System 2.
3. 4. 5.
6. 7. 8.
9. 10. 11. 12. 13. 14. 15.
43
Why digital electronics are more widely used as compared to analog electronics? Select one reason from the following. (a) They are easier to maintain (b) They are less expensive (c) They are useful over wider ranges of problem types (d) They are always more accurate and faster The number of nibbles, which make up one byte, is (a) 2 (b) 16 (c) 4 (d) None of these The decimal equivalent of the hexadecimal number E5 is (a) 229 (b) 279 (c) 327 (d) None of these Which of the following statements is correct? (a) Decimal 10 is presented as 10101 in binary code (b) Decimal 9 is presented as 1011 in Excess 3 code (c) Decimal 9 is presented as 1010 in BCD code (d) Decimal 10 is presented as 1100 in Gray code (1111.01) is (a) (15.25)10 (b) (12.25)10 (c) (23)10 (d) (12)10 In the 8421 BCD code, the decimal number 125 is written as (a) 1111101 (b) 000111 (c) 7D (d) None of these Indicate which of the following binary additions is correct (a)10101 + 1111= 111101 (b) 1010 +1101=1111 (c)1010+1110=11000 (d) 1010 + 1001=1111 The binary equivalent of decimal number 13 is (a) 1001 (b) 1100 (c) 1010 (d) 1101 The decimal number 422 is equal to which of the following hexadecimal number? (a) 229 (b) 279 (c) 327 (d) 1A6 The binary number 101011 is equivalent to (a) 229 (b) 279 (c) 327 (d) None of these The decimal equivalent of 101.101 is (a) 5.29 (b) 5.625 (c) 327 (d) None of these Convert (11001.1)2 into octal (a) (31.4)8 (b) (32.4)8 (c) (35.4)8 (d) None of these Convert (347)8 into base 2 (a) 011100111 (b) 11100111 (c) 11101011 (d) None of these Parity bit for error detection doses not imply (a) Automatic error correction (c) Odd number of error detection (b) Increase in the hardware in the system (d) Increase in the length of code
44
Digital Electronics: Principles and Applications
REVIEW QUESTIONS 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
1.9. 1.10
1.11
1.12
1.13
1.14
1.15
1.16 1.17 1.18
What is the difference between analog and digital quantities? Explain advantages of digital system over analog system. What is overﬂow in digital computer? Discuss weighted code with examples. What is the difference between ASCII code and EDCDIC code? What is parity bit?. Explain brieﬂy applications of parity bit. Convert the following binary numbers to decimal numbers. (a) 1100111 (b) 111010101 (c) 101.11011 (d) 10111.011011 Convert the following decimal numbers to binary numbers. (a) 5635 (b) 256 (c) 100.425 (d) 0.625 (e) 100.25 (f) 37 Convert the following binary numbers to octal, and hexadecimal number. (a) 101111010111111 (b) 110110110111 (c) 1111100111110 (d) 11101010110 Convert the following octal numbers to binary numbers. (a) 57.35 (b) 222 (c) 50.25 (d) 2765 (e) 2567 (f) 67 Convert the following hexadecimal numbers to binary numbers. (a) FFAF (b) 9BCD6 (c) CF (d) AA2 (e) 87D4 (f) AE0F Convert the following decimal numbers to octal and hexadecimal number. (a) 546 (b) 2777 (c) 5235 (d) 46 (e) 9898 (f) 65 Add the following binary numbers. (a) 10110111 (b) 11111101 (c) 11010011 10100110 10101100 11110110 Subtract the following binary numbers (a) 11111011 (b) 00011011 (c) 11110011 – 01110001 –10000011 – 01110111 Divide the following binary numbers (a) ( 10001110 ) 1001011011110111 (b) ( 10110110 ) 1101100000101001 (c) ( 11010011 ) 11001100111011111 Determine the 2’s complement of following numbers (a) 01101101 (b) 11101111 (c) 10000011 Convert the following 2’s complement numbers into decimal (a) 10001101101 (b) 101101111 (c) 111000011 Convert the following decimal numbers into 2’s complement numbers (a) 599 (b) –77 (c) 365
Number System 1.19 1.20 1.21 1.22
1.23
1.24
1.25 1.26
Convert the following decimal numbers to 8 bit, 2’s complement numbers, (a) 256 (b) 56 (c) –106 Convert the following decimal numbers to BCD (a) 298 (b) 25 (c) 56 (d) 86 (e) 99 Convert the following BCD numbers into decimal numbers (a) 0011 0111 1001 (b) 1001 0101 0110 1000 (c) 0111 1001 1001 0011 1001 Add the following BCD numbers (a) 1001 0111 1001 (b) 1001 0101 0110 0001 (c) 0111 1001 1001 0011 1001 0011 1001 0011 1001 1001 0100 1001 1000 0100 0011 1001 1001 Subtract the following BCD numbers (a) 1001 0111 1001 (b) 1001 0101 0110 1001 (c) 0111 1001 1001 0011 1001 – 0011 1001 0011 – 0011 0110 0100 1001 0011 0100 0011 1001 0011 Determine characters of the following ASCII code (a) 101 0100 100 1000 100 0101 100 0101 100 0001 101 0010 101 0100 100 1000 (b) 100 1101 100 1111 100 1111 100 1110 (c) 101 0011 (d) 101 0101 100 1110 Deﬁne Parity bit. What are the types of parity bit?. Explain applications of parity bit. Explain Hamming Code with an example.
45
CHAPTER
2
BOOLEAN ALGEBRA AND LOGIC GATES 2.1
INTRODUCTION
Boolean algebra has been introduced by the mathematician, George Boole in 1854. It is a two state algebra to solve logic problems and used the logical and arithmetic calculations for digital equipments. This operates with logic variables, namely ‘0’ and ‘1’. The logic variables can also be represented by logical TRUE (T) and logical FALSE (F). Any statement can be represented by logic variable. One example is “The Sun rises in the east” (TRUE). In this way, any statement can be model as logic variable. In the other way, new statements can be built based on existing statements using logic variables and logic operators. The new statements may be false or true. Consider X= “The Sun rises in the east” then NOT X = Y= “The Sun does not rises in the east” (FALSE). Boolean logic variable “0” or “1” is not used to represent actual numbers but it is used to represent the state of voltage variable called logic level. Commonly used representation of logic levels are shown in Table 2.1. Transistors can be operated at two different states namely saturation and cutoff. Figure 2.1 shows the saturation operation of transistor. In this circuit, 5 volt is applied through the twoposition switch to operate in saturation. When the transistor is in saturation region, the voltage between collector and emitter is very small. So, the output voltage is 0 volts. Therefore, this circuit can be used to represent binary bits. The input signal is a logic ‘1’ and the output signal is a logic ‘0’. These voltage levels can also be represented by logic level HIGH and LOW respectively as depicted in Table 2.1. Similarly, due to change the position 0V (logic 0) is used as input and transistor operates in cutoff region and output voltage will be 5V or logic ‘1’ as shown in Fig. 2.2. Table 2.1
Representation of logic level
Logic 0
Fig. 2.1
Transistor in saturation
Logic 1
False
True
Open Switch
Close Switch
Low
High
No
Yes
Off
On
Boolean Algebra and Logic Gates
47
In this way, a single transistor can be used as a logic gate or gate. A gate is a electronic circuit which is designed to receive and generate voltage signals into binary form. Figures 2.1 and 2.2 can implement the NOT gate or inverter. Generally, gate circuits are represented by symbols. The symbol of NOT gate is presented in proper place.
2.2
BOOLEAN ALGEBRA
The English mathematician, George Boole (1815–1864) is Fig. 2.2 Transistor in cutoff known as the father of Boolean Algebra. His work namely “An Investigation of the Laws of Thought, on Which Are Founded the Mathematical Theories of Logic and Probabilities” was published in 1854. Actually, this consists of several rules of relationship between mathematical quantities namely true or false, ‘1’ or ‘0’. This mathematical system is called as Boolean algebra. This is a twostate algebra to solve logic problems. This new algebra had no practical use until Shanon applied it to telephone switching circuits. Presently, Boolean algebra is the backbone of computer and it is also used to analyse and design of digital circuits. Boolean algebra uses alphabetical letters to denote variables same as normal algebra. Boolean variables are always CAPITAL letters, never lowercase, as these variables are allowed to possess only one of two possible values, either ‘1’ or ‘0’. The inversion, AND and OR operation of Boolean algebra are explained as follows.
2.2.1
Inversion Operation
Each variable has a complement means the opposite of its value. If we consider variable A has a value of ‘0’, then the complement of A has a value of ‘1’. Boolean notation uses a bar above this variable character to denote complementation as given below: – – If A = 0 then A = 1 or If A = 1 then A = 0 The complement of A is denoted as Anot or Abar. The prime symbol is also used to represent complementation. For an example, the complement of A will be A¢. For inversion operation, NOT gate is used as depicted in Fig.2.3. This gate has one input and an output. When input is A, output, O is always complement of A due to inversion. The equation for this is O = NOT A If A is 0, O = NOT 0 = 1 On the other hand, if A is 1, Fig. 2.3
Inversion operation
O = NOT 1 = 0 In Boolean algebra, the NOT operation is denoted by the overbar and the equation for NOT operation can be written as – O=A The above equation can be interpret as “ output, O equals NOT A” or “output O equals the complement of A”.
48
Digital Electronics: Principles and Applications
2.2.2 OR Operation In mathematics, the sum of any number and zero is the same as the original number. This algebraic identity can be written as X + 0 = X, where X is any number. Similar to ordinary algebra, Boolean algebra has its individual identities based on the bivalent states of Boolean variables. In Boolean algebra, the sum of anything (1 or 0) and zero(0) is the same as anything (1 or 0). This logical function is known as OR operation. The equation for OR operation is O = A OR B With given the inputs, we can ﬁnd the output. If A = 0 and B = 0,then output O = 0 OR 0 = 0 So, output of an OR gate is zero when both inputs are 0s. But, when A = 0 and B = 1, the output is 1 O = 0 OR 1 = 1 Therefore, it is clear that output of an OR gate is 1 when either input is 1. Similarly, if A = 1 and B = 0, output is 1 O = 1 OR 0 = 1 In Boolean algebra, the ‘+’ sign stands for the OR operation and the equation for OR operation is O = A + B. Figure 2.4 shows the relationship between inputs and output for OR operation.
Fig. 2.4 OR operation
2.2.3 AND Operation The multiplication is also valid in Boolean algebra and it is the same as in realnumber algebra. Anything multiplied by 0 is 0, and anything multiplied by 1 output is 1. This is nothing but the truth table for an AND gate. In other words, Boolean multiplication corresponds to the logical function of an AND gate. The equation for AND operation is O = A. B In Boolean algebra, the multiplication sign “.” stands for AND operation. The above equation can be written simply O = AB. This equation can be interpreted as “ output, O equals as A AND B”. If both the inputs are low, output is low, O = 0.0 = 0 In fact, the output will be 1 only in one case when both the inputs are high. That is O = 1. 1 = 1.
Boolean Algebra and Logic Gates
49
Figure 2.5 shows the AND operation.
Fig. 2.5 AND operation
2.3
BOOLEAN LAWS
Boolean laws have been derived by using Boolean postulates. These laws are used to design and analyse logic circuit mathematically. The Table 2.2 shows the Boolean laws. In this section, all these laws are explained below: Table 2.2
The Boolean laws
Laws of Union Law 1 A+0=A Law 2 A+1=1 Laws of Intersection Law 3 A.0 = 0 Law 4 A.1 = A Laws Tautology Law 5 A+A=A Law 6 AA = A Laws of Complements – Law 7 A+A =1 Law 8 A.A = 0 Laws of Double Complements = Law 9 A =A Laws of Commutation Law 10 A+B=B+A Law 11 AB = BA Laws of Association Law 12 A + (B + C) = (A + B) + C Law 13 A(BC) = (AB)C Laws of Distribution Law 14 A(B + C) = AB + AC Law 15 (A + B)(C + D) = AC + AD + BC + BD Laws of Absorption Law 16 A (A + B) = A Law 17 A + AB = A – Law 18 A(A + B) = AB – – Law 19 AB + B = A + B – Law 20 AB + B = A + B DE Morgans Theorem —–— – – Law 21 A + B = A. B –—– – – Law 22 A. B = A + B
2.3.1
Laws of Union
This is the ﬁrst Boolean identity. It means that the sum of anything (1 or 0) and zero (0) is the same as the anything (1 or 0). There is no difference between the Boolean identity, laws of union and real number
50
Digital Electronics: Principles and Applications
algebra. Law 1 and Law 2 of Laws of Union are shown in Fig 2.6(a) and (b) respectively and their operations are explained as follows:
Law 1 A+0=A Fig. 2.6 When A = 0, A + 0 = 0 When A = 1, A + 1 = 1 Law 1 means that the output is always A and depends on the value of A. When A = 1, the output will be 1. If A = 0, output will be 0. Law 2 A+1=1 When A = 0, A + 1 = 1, When A = 1, A + 1 = 1 It means that output is independent of A and it will be always the same when A = 1 or A = 0. This identity is different from any seen in normal algebra. Here, we can see that the sum of anything and ‘1’ is ‘1’.
2.3.2 Laws of Intersection There are two intersection identities: A.0, and A.1. These two laws are stated below with the help of Fig. 2.7 (a) and (b):
Fig. 2.7
Law 3 A.0 = 0 When A = 0, A.0 = 1, When A = 1, A.0 = 0 This law states that if one of two inputs AND gate is logic zero (0) and other input is connected with signal A, the output will be logic zero (0). Law 4 Α.1 = A When A = 0, A.1 = 0, When A = 1, A.1 = 1 It is depicted in Fig. 2.7(b) that if one of two inputs AND gate is logic 1 and other input is connected with signal A, the output will be A.
2.3.3 Laws of Tautology Law 5 A+A=A The output of adding A and A together is A as shown in Fig. 2.8 (a). When both inputs of an OR gate are connected to each other, output will be A same as input. Law 6 A.A = A In normal algebra, the product of a variable and itself is the square of that variable. But, in Boolean algebra, A.A is equal to A as depicted in Fig.2.8(b). The equation, A.A = A means that the product of a Boolean quantity and itself is the original quantity like 0 ¥ 0 = 0 and 1 ¥ 1 = 1. If both inputs of a AND gate are connected to each other and output will be A same as input.
Fig. 2.8
51
Boolean Algebra and Logic Gates
2.3.4
Laws of Complements
– Law 7 A + A = 1 In laws of complement of Boolean algebra, the output of OR operation of any variable and it’s complement is always ‘1’. So, the sum of any Boolean quantity and its complement must be ‘1’ as shown in Fig. 2.9 (a). – Law 8 A.A = 0 In Boolean mathematics, the AND operation output between a variable A and its complement, A– is 0. Therefore, the output must be ‘0’ for AND operation between any variable and its complement. As the product of any Boolean quantity and ‘0’ is ‘0’, the product of a variable and its complement must be ‘0’ as shown in Fig. 2.9 (b).
2.3.5
Fig. 2.9
Laws of Double Complements
= Law 9 A = A There is also one identity with complementation that is known as double complements. Double complement means that a variable inverted twice. It simply states that it is actually complement of the complement of a variable. After complementing a variable twice, we get the original Boolean value as shown in Fig. 2.10. – ==0=A If A = 0, A = 1 and A
2.3.6
Fig. 2.10
Laws of Commutation
Law 10 A+B = B+A Law 11 AB = BA The Commutative Law is also applicable for Boolean algebra, and it applies equally to addition and multiplication. From this commutative property, we can say that we can reverse the order of variables in addition or multiplication as shown in Fig.2.11 (a) and (b).
2.3.7
Fig. 2.11
Laws of Association
Law 12 A+(B+C) = (A+B)+C Law 13 A(BC) = (AB)C Laws of Association of Boolean algebra are same as for conventional algebra. So associative property can be applied in addition and multiplication of variables as depicted in law 12 and law 13. Using this property, we can able to add or multiply between associate groups with parentheses as depicted in Fig. 2.12(a) and (b). In this case, the truth table will not be changed.
Fig. 2.12
52
Digital Electronics: Principles and Applications
2.3.8 Laws of Distribution Law 14 A(B+C) = AB+AC Law 15 (A+B)(A+C) = A+BC The laws of distribution are used to expand any Boolean expression. The law 14 and law 15 show the product of a sum and in reverse how all terms can be factored out of Boolean sumsofproducts as depicted in Fig. 2.13 (a) and (b) respectively.
2.3.9
Laws of Absorption
Law 16 Law 17 Law 18 Law 19 Law 20
A (A + B) = A A + AB = A – A (A + B) = AB – – AB + B = A+ B – A + AB = A + B
Fig. 2.13
There are ﬁve laws of absorption in Boolean algebra as given above. These laws are used in the simpliﬁcation of logic circuits. When logic circuits are represented by most simpliﬁed Boolean form, the logic circuit can able to perform the same function with fewer logic gates. As a result, reliability of logic circuit will be increased and cost of manufacture will be decreased. The law 16 can be proved by using Boolean identity. Consider the Boolean expression A(A+B) A(A+B) = AA + AB = A + AB applying AA = A Factoring A out of both terms, we get A(1 + B) We already know that B + 1 = 1. Then apply this in the above equation, we get A.1 Applying identity 1.A = A, we ﬁnally get A. – Similarly, we can prove that A + A B = A + B – Applying the rule A + AB = A, the Boolean expression A + A B can – be written as A + AB + A B – Factoring out of second and third terms A + B(A+ A ) – Applying (A+ A ) =1, we get A + B.1 Applying 1. A = A, we ﬁnally get A + B Fig. 2.14
Example 2.1
Figure 2.14(a) and (b) show logical implementation of law 16 and law 20 using logic gates respectively. In the same way, we can be able to prove other laws and to implement using logic gates. Prove A(A + B) = A
Boolean Algebra and Logic Gates �
Solution A(A + B) = AA + AB = A + AB = A.1 + AB = A(1 + B) = A.1 =A
Example 2.2 �
Applying distributive property Applying identity AA = A Factoring out A Apply identity 1 + A = 1 Apply identity A.1 = A
Prove (A + B) (B + C) = B + AC
Solution (A + B) (B + C) = AB + AC + BB + BC = AB + AC + B + BC = B + AB + AC + BC = B + AC + BC = B + BC + AC = B + AC
2.4
53
Applying distributive property Applying identity AA = A Apply B + AB = B Apply B + AB = B
DE MORGAN’S THEOREM
De Morgan was developed two important rules for group complementation in Boolean algebra. These two rules are: De Morgan’s First Theorem —— ——— — – – A +B = A . B
De Morgan’s Second Theorem ––– – – A .B = A + B De Morgan’s First Theorem Break
De Morgan’s Second Theorem Break
—— ——— —
——— — —
A +B
A ·B
— —
—
A.B
2.4.1
—
A+ B
De Morgan’s First Theorem
According to De Morgan’s ﬁrst theorem, when a long bar is broken, the operation directly under the break changes from addition to multiplication as given below —— ——— — – – A +B = A . B Both sides of Boolean expression can be represented by logic circuits.
Fig. 2.15
54
Digital Electronics: Principles and Applications
Figure 2.15 (a) is a 2 input NOR gate —— and Fig.2.15 (b) is the substitute of NOR gate using OR and ——— — inverter. Here the output is equal to O = A + B . Figure 2.15(c) has inverted inputs before they reach the AND gate. Therefore, the Boolean equation – – of output is O = A . B After comparing Table 2.3 and Table 2.4, we can say that they are identical. This means the two circuits are logically equivalent; given the same inputs, the outputs are same. In other words, the circuits shown are interTable 2.4 Truth table Table 2.3 Truth table changeable. Therefore, Inputs Output Inputs Output De Morgan’s ﬁrst the– – –––– A B O=A +B A B O = A+B orem is proved from 0 0 1 0 0 1 truth tables. 0 1 0 0 1 0 When three inputs 1 0 0 1 0 0 are involved, De Mor1 1 0 1 1 0 gan’s ﬁrst theorem is written as —— ——— — ——— — – – – A + B +C = A . B . C Similarly, for 4 inputs it will be ——— — —— ————— —— – – – – A +B+ C + D = A . B . C . D
2.4.2
Fig. 2.16
Table 2.5
Inputs
De Morgan’s Second Theorem
According to De Morgan’s second theorem, when a long bar is broken, the operation directly under the break changes from multiplication to addition as given below: ––– – – A .B = A + B Both sides of the above Boolean equation can be implemented by logic circuits as shown in ﬁgures below. Figure 2.16 (a) is a 2 input NAND gate. Therefore, the Boolean equation –––– of output is O = A . B Figure 2.16 (b) has inverted inputs before they reach the OR gate. Therefore – – the Boolean equation of output is O = A + B Truth table We can say that Table 2.5 and Table 2.6 are identical. This means that the two circuits are logically equivalent; given the Output same inputs, the outputs are same. In other words, the circuits –––– O = A. B shown are interchangeable. 1 Thus, the De Morgan’s second theorem is proved.
A
B
0
0
0
1
1
1
0
1
1
1
0
When three inputs are involved, De Morgan’s second theorem is written as ——— – – – A . B. C = A + B + C For 4 inputs,
———— – – – – A . B.C. D = A + B + C + D
55
Boolean Algebra and Logic Gates
If multiple layers of bars exist in a Boolean expression, we can only break one bar at a time, and it is usually easier to begin simpliﬁcation by breaking the longest bar ﬁrst. For an example, –— consider the Boolean expression is AB + CD . The expression –— AB + CD can be reduced using DeMorgan’s Theorems. Firstly, –— –— break the longest bar and we get A B .CD. Then we break A B . – – So, ﬁnally we ﬁnd A CD + B CD. Example 2.3
Table 2.6
Inputs
Truth table
Output
A
B
– – O=A+B
0
0
1
0
1
1
1
0
1
1
1
0
Prove A + B + C + D + ABCD = 1
� Solution – – – – A + B + C + D + ABCD = A + B + C + D + A + B + C + D – – – – =A+A +B+B +C+C +D+D =1+1+1+1=1
Breaking long bar in ABCD – Apply identity A + A = 1
2.5 LOGIC GATES Logic gates are electronic circuits with a number of inputs and one output. The output voltage depends on the input voltages. Logic gate circuits are most commonly represented in a schematic by symbols in place of constituent transistors and resistors. The digital systems can be made by using three basic logic gates. These are AND gate, OR gate and NOT gate. The AND gate is an electronic circuit whose output is high when it’s all inputs are high. The OR gate is also an electronic circuit which gives a high output if one or more of it’s inputs are high. The NOT gate generates an inverted version of the input logic at it’s output. The most commonly used other logic gates are NAND, NOR, XOR, INV, and BUF. The term INV stand for “inverter” and BUF stand for “buffer”. In this section, function of all logic gates have explained elaborately.
2.5.1
Truth Table
The truth table describes the output of a logic circuit, which depends on the inputs of the logic circuit. Figure 2.17 shows the block diagram of two inputs logic circuit and it’s output is shown in Table 2.7. The relationship between input and output should be expressed by Boolean logic function that is unknown (?). Similarly, three inputs and one output logic circuit represented by Fig.2.18 and the output for different values of inputs are depicted in Table 2.8. The correlation between inputs and output should be expressed by Boolean function. Therefore, the “?” in the box as shown in Fig. 2.17 and Fig.2.18 will be replaced by logic gates. The two inputs AND gate is required for Fig.2.17 and a three inputs OR gate can able to represent the Fig. 2.18.
Fig. 2.17
Two inputs and one output
Fig. 2.18
Three inputs and one output
56
Digital Electronics: Principles and Applications Table 2.7
Two inputs and one output
Inputs A B 0 0 1 1
Table 2.8
Output O
0 1 0 1
Three inputs and one output
A
Inputs B
C
Output O
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 1 1 1 1 0
0 0 0 1
2.5.2 AND Gate The expression O = A.B means output “O” equals A AND B. The “.” sign stands for the AND operation and actually it is same as ordinary multiplication of 1s and 0s. The AND operation produces a result of ‘1’, when all input variables are ‘1’. But the output is ‘0’ when one or more inputs are ‘0’. Figure 2.19 shows the two inputs AND gate and truth table is given in Table 2.9. Table 2.9
Truth table of two inputs AND gate
Inputs
Fig. 2.19
A
B
Output O = A.B
0 0 1 1
0 1 0 1
0 0 0 1
Two inputs AND gate
An example of three inputs AND gate and its truth table are shown in Fig. 2.20 and Table 2.10 respectively. It is also depicted in truth table that output is ‘1’ when all inputs are ‘1’ and otherwise output is ‘0’. Table 2.10
Truth table of three inputs AND gate
Inputs
Fig. 2.20 Three inputs AND gate
A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Output C 0 1 0 1 0 1 0 1
O = A.B.C 0 0 0 0 0 0 0 1
The three inputs and four inputs AND gate using two input AND gates are depicted in Fig. 2.21(a) and Fig. 2.21(b) repectively.
57
Boolean Algebra and Logic Gates
2.5.3 OR Gate The expression O = A + B deﬁned as output “O” equals A OR B. The “+” sign stands for the OR operation and it is not for arithmetic addition. When any of the inputs of OR gate is ‘1’ the output of the OR gate will be ‘1’. But, the output of OR gate is ‘0’ only when all the input variables are ‘0’. The symbol of two inputs OR gate is shown in Fig. 2.22 and truth table is also given in Table 2.11.
Fig. 2.21 Table 2.11
Truth table of two inputs OR gate
Inputs A 0 0 1 1
Output B 0 1 0 1
O=A+B 0 1 1 1
Fig. 2.22 Two input OR gate
Figure 2.23 shows the three inputs OR gate and its truth table is given in Table 2.12. It is depicted in this table that the output of the OR gate is ‘1’ when any of the inputs of OR gate is ‘1’ and output is ‘0’ only when all the input variables are ‘0’. Table 2.12
Truth table of three inputs OR gate
Inputs A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Output C 0 1 0 1 0 1 0 1
O=A+B+C 0 1 1 1 1 1 1 1
Fig. 2.23
Three inputs OR gate
Three inputs and four inputs OR gate can be designed by using two inputs OR gates as shown in Fig. 2.24 (a) and (b) respectively.
2.5.4 NOT Gate The circuit which is shown in Fig. 2.1 as given in Section 2.1, is known as an inverter or NOT gate. This inverter circuit is also represented by symbol as given in Fig. 2.25. An alternative symbol for an inverter is shown in Fig. 2.26. The NOT Gate has one input signal and one output signal. When the input signal A is subjected to the NOT operation, the output O can be expressed as
58
Digital Electronics: Principles and Applications
– O = A or O = A¢ Here, ‘ – ’ or ( ¢ ) represents the NOT operation. This expression means output ‘O’ equals NOT A or O equals the inverse of A or O equals the complement of A. The truth table of the NOT gate is shown in Table 2. 13. The NOT gate operations can be referred as inversion or complementation. Table 2.13
Truth table of NOT gate
Input
Fig. 2.24
Output
A
– O = A = A′
0 1
1 0
The NOT operation is also referred as inversion or complementation, and these terms are used interchangeably.
2.5.5 NOR Gate Fig. 2.25
NOT gate
Fig. 2.26
NOT gate
NOR gate is extensively used in digital electronic circuit. This gate is the combination of the basic gates AND, OR and NOT. NOR is the same as the inverted OR gate and its symbol is shown in Fig. 2.27. This gate has a small circle on the output. This small circle represents the inversion operation and the output expression of the two inputs NOR gate is —— O = A + B = (A + B)¢. The truth table of the NOR gate is shown in Table 2. 14. An three inputs OR gate can be designed by using a NOR gate and a NOT gate as shown in Fig. 2.28. Table 2.14
Truth table of two inputs NOR gate
Inputs
Fig. 2.27
Two inputs NOR gate
Output
A
B
O = A + B = (A + B)′
0 0 1 1
0 1 0 1
1 0 0 0
2.5.6 NAND Gate
Fig. 2.28 The three inputs OR gate
The inverted operation of AND gate is the NAND gate and its symbol is depicted in Fig. 2.29. There is a small circle on the output. This small circle represents the inversion operation. The output of the two inputs NAND gate can be expressed as
59
Boolean Algebra and Logic Gates
–— O = A B = ( AB )¢. The truth table of two inputs NAND gate is given in Table 2.15. Table 2.15
Truth table of two inputs NAND gate
Inputs
Output
A
B
–— O = A B = (AB)¢
0 0 1 1
0 1 0 1
1 1 1 0
Fig. 2.29
Two inputs NAND gate
Digital logic can be described in terms of standard logic symbols and their corresponding truth tables. The transistor based digital ICs (Integrated chips) have been manufactured by using the function of all gates. The horizontal lines represent inputs or outputs of the gates and the small circle at the outputs means inverted operation of output. A three input NAND gate and four input NAND gate can be designed by using two inputs AND and NAND gates as shown in Fig. 2.30 (a) and (b).
Fig. 2.30
2.5.7
ExclusiveOR Gate
The operation of ExclusiveOR gate is something quite different from OR gate. When the inputs of ExclusiveOR gate are at different logic levels either ‘0’ and ‘1’ or ‘1’ and ‘0’, its output is “high”. On the other hand, output of ExclusiveOR gate is “low” logic level if the inputs are at the same logic levels. The ExclusiveOR gate can be written as XOR or ExOR gate. Figure 2.31 shows the two inputs ExOR gate and truth table is given in Table 2.16. Table 2.16
Truth table of XOR gate
Inputs
Output
A
B
O=A⊕B
0 0 1 1
0 1 0 1
0 1 1 0
Fig. 2.31
ExOR gate
60
Digital Electronics: Principles and Applications
An ExclusiveOR gate can be build up by using NAND, AND, and OR gates. The equivalent circuit of ExOR gate is shown in Fig. 2.32. In this circuit, the output of NAND gate and OR gate are fed to AND gate for ﬁnal output. Here, AND gate acts as a buffer. For the ﬁrst three input combinations (00, 01, and 10) the output of NAND gate is Fig. 2.32 Equivalent circuit of Exhigh. When the NAND gate’s output is high, the output of OR gate AND gate is equal to the OR gate’s output. When inputs are “high”, the output of NAND gate outputs a “low” and the output of AND gate is “low”. Figure 2.33 shows the alternative equivalent circuit of the ExclusiveOR gate. This circuit uses two AND gates with inverters and an OR gate. The output of AND gates can be “high” for input conditions 01 and 10. Then OR gate allows either of the AND gates’ “high” outputs to create a ﬁFig. 2.33 Equivalent circuit of ExOR nal “high” output. ExclusiveOR gates are used to compare gate binary numbers. This gate is also used for error detection, parity check and code conversion, like binary to Grey. The three inputs ExOR and four inputs ExOR gates can be developed by using two inputs ExOR gate as shown in Fig. 2.34(a) and (b) respectively. The truth table of three inputs ExOR gate is shown in Table 2.17. Table 2.17
Truth table of three inputs ExOR gate
Inputs
Fig. 2.34
A 0 0 0 0 1 1 1 1
Output
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
O = A⊕B⊕C 0 1 1 0 1 0 0 1
2.5.8 ExclusiveNOR gate The last gate for analysis is the ExclusiveNOR gate and it is known as the XNOR gate. It is equivalent to an ExclusiveOR gate with an inverted output. The truth table for this gate is absolutely opposite of the ExclusiveOR gate as given in Table 2.18. Figure 2.35 shows the two inputs ExNOR gate and its equivalent is depicted in Fig.2.36. From the truth table, it is very clear that the purpose of an ExclusiveNOR gate is to output a ‘high’ when both inputs are at the same logic levels.
Table 2.18
Truth table of XNOR gate
Inputs
Output
A
B
——– O = A⊕B
0 0 1 1
0 1 0 1
1 0 0 1
61
Boolean Algebra and Logic Gates
Fig. 2.35
2.6
ExNOR gate
Fig. 2.36
Equivalent circuit of ExNOR gate
UNIVERSAL GATE
NAND and NOR gates have a unique property that they are universal. It means that universal gates are able to mimic the operation of any other gates. For an example, the interconnected NAND gates can generate the OR function. Similarly, any gates can be replaced by the NAND and NOR gates. The construction of NOT, Buffer, AND, OR, NOR gate using NAND and NOR gates are explained below:
2.6.1
The NOT Gate Using NAND and NOR
It is depicted in Fig. 2.37 that there are two ways to construct a NOT gate or an inverter using NAND and NOR gates. The ﬁrst method is that both input terminals of NAND and NOR gates will be interconnected and it will be same as inverter input terminal. In Fig. 2.37 (a) and Fig. 2.37(c), both terminals are interconnected and used as an inverter input terminal. In the other method, one terminal is used as input and the unused terminal is connected with +Vcc for NAND gate and ground for NOR gate as shown in Fig. 2.37 (b) and Fig. 2.37(d) respectively.
2.6.2
Fig. 2.37 (a) NOT gate using NAND, (b) NOT gate using NAND, (c) NOT gate using NOR, (d) NOT gate using NOR
The Buffer Using NAND and NOR Gate
Figure 2.38 shows the symbol of buffer. The buffer gate construction using NAND and NOR gates is very simple and two NAND or NOR gates are used for this purpose as given in Fig 2.39 and Fig. 2.40. Actually, two inverters connected in cascade form behaves as buffer. The output of buffer is same as the input.
Fig. 2.39
2.6.3
(a) and (b) Buffer using NAND gate
Fig. 2.40
Fig. 2.38
Buffer
(a) and (b) Buffer using NOR gate
The AND Gate Using NAND Gate
To construct an AND gate from NAND gates, an inverter or a NOT gate is required to invert the output of a NAND gate. This inversion cancels out the ﬁrst inverted operation of NAND gate and the ﬁnal result will be AND function as depicted in Fig.2.41. The same function can also be implemented using NOR gates. Initially all of the inputs are inverted using NOR gates as inverter and then fed to another NOR gate. So, three NOR gates are required to build up a AND gate as shown in Fig. 2.42.
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Digital Electronics: Principles and Applications
Fig. 2.41
Fig. 2.42 AND gate using NOR gate
AND gate using NAND gate
2.6.4 The NAND Gate Using NOR Gate
Fig. 2.43
NAND gate using NOR gate
The NAND gate construction using NOR gate is shown in Fig. 2.43. Here, ﬁrstly all inputs are inverted by using NOR gates and fed to another NOR gate. The NOR gate’s output is inverted by another NOR gate. Therefore, four NOR gates can implement a NAND gate.
2.6.5 The OR Gate Using NAND and NOR Figure 2.44 shows the construction of OR gate using NAND gates. Initially, all inputs are inverted by using NAND gates and then results are fed to another NAND gate for getting OR function. In this way, an OR gate can developed using three NAND gates. On the other hand, an OR gate can be created by inverting the output of a NOR gate as shown in Fig. 2.45.
Fig. 2.44
OR gate using NAND gate
2.6.6
Fig. 2.46
NOR gate using NAND gate
Fig. 2.45
OR gate using NOR gate
The NOR Gate Using NAND Gate
The procedure for making NOR gate using NAND gate is same as construction of OR gate using NAND gate. All inputs are inverted and used as inputs of a NAND gate. After that, NAND gate’s output is inverted by another NAND gate. So, the NOR gate function can be developed by using four NAND gates as depicted in Fig. 2.46.
63
Boolean Algebra and Logic Gates
Example 2.4
Write the truth table of the logic circuit as shown in Fig. 2.47.
Fig. 2.47
� Solution Truth table of the logic circuit expression A + B + CD is given below: Table 2.19 Truth table for A + B + CD
Inputs A
B
C
D
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A+B
CD
A + B + CD
A + B + CD
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 0 0 1 1 1 0 1 1 1 0 1 1 1 0
Example 2.5 Draw the circuit diagram of the logic expression ——— O = A + BC + ACD � Solution The logic circuit diagram of Boolean expression is shown in Fig. 2.48. It is clear from this ﬁgure that two AND gates, one NOR gate and one OR gate are required to implement the logical equation ——— O = A + BC + ACD Example 2.6
Fig. 2.48
Draw the circuit diagram of the logic expression
O = AB + BC + AC + BD
�
Solution
Figure 2.49 shows the logic circuit diagram for the logic expression O = AB + BC + AC + BD. The AND gates, two inverters, one NOR, and two OR gates are used to implement the above logical equation.
Fig. 2.49
64
Digital Electronics: Principles and Applications
Example 2.7
Draw the output of the two input ExNOR gate with the given inputs A and B.
Fig. 2.50
� Solution The A waveform can be read as 10101 and B waveform can be represented as 11011. The digital output of OR gate will be 10000. The waveform of output is given below:
Fig. 2.51
2.7
SIMPLIFICATION OF LOGIC CIRCUITS
The logic circuit is deﬁned as a circuit, which is developed, by combinations of logic gates. The outputs of the logic circuit at any given time depends on the logic inputs at that instance. Therefore, due to change in input combinations, output will be changed. During the logic implementation, we can use the original Boolean expression directly or we can use Boolean laws for simpliﬁcation of the logic expression to reduce number of gates in logic circuit. Consider a Boolean expression O = AB + BC (B+C). This expression can be implemented by using three AND gates and two OR gates as shown in Fig. 2.52. Now, the task is circuit simpliﬁcation by using Boolean Laws. The stepbystep procedure is explained here. Fig. 2.52
The original expression O is equal to AB + BC(B + C). O = AB + BC(B + C).
After distributing terms, we get AB + BBC + BCC Then apply Boolean law AA = A to second and third term, we ﬁnd AB + BC + BC We apply A + A = A, we get AB + BC Taking common B from both terms, we determine B(A + C)
65
Boolean Algebra and Logic Gates
So, after using Boolean laws in original expression, we get the simpliﬁed expression O = B(A + C). To implement this logic expression, one OR gate and one AND gate are required as shown in Fig. 2.53. It is very clear from Fig. 2.52 and Fig. 2.53 that the second implemented logic circuit is most simple from the original one. Here, only two logic gates are used instead of ﬁve. As a result, this circuit has the following advantages: higher operating speed, less power Fig. 2.53 consumption, less cost, and more reliability. Another Boolean expression is O = A + B(A + C) + AC. We apply Boolean Laws to reduce this expression to its simplest form. O = A + B (A + C) + AC After distributing terms, we ﬁnd O = A + AB + BC + AC Apply Boolean law A + AB = A in ﬁrst and second terms, we get O = A + BC + AC Then apply A + AB = A in ﬁrst and third terms, we obtain O = A + BC The simpliﬁed form of the expression, O = A + B(A + C) + AC is O = A + BC. Simpliﬁcation of Boolean expression by using De Morgan’s laws. Consider the expression A + BC . The digital implementation of this logic expression is given in Fig. 2.54. Fig. 2.54
By using the De Morgan’s laws, we break the bar covering the entire expression as
A + BC = A . BC = – – Applying double complements identity, A = A we get A BC Therefore, the original circuit can be implemented by using a threeinput AND gate and a inverter as shown in Fig. 2.55. Simpliﬁcation of logic expression O = A + BC + AB
Fig. 2.55
To represent this logic expression, we apply two NOR, one AND, one NAND and one Inverter as depicted in Fig. 2.56.
Fig. 2.56
To reduce the above logic expression, Boolean identities and De Morgan’s theorems are used as follows: After breaking the longest Bar of logic expression O = A + BC + AB , we get
(A + BC) (AB)
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Digital Electronics: Principles and Applications
= – Applying double complements A = A, we get (A + BC) (AB ) – – Then applying distribution law, we obtain AAB + BCAB – – Applying Boolean identity AA = A and AA = 0, we get AB + 0 – After applying identity A + 0 = A, we ﬁnally get AB – The simpliﬁed logic expression AB can be implemented by using logic gates. Figure 2.57 shows the equivalent circuit of the expression. This ﬁgure consists of one inverter and one AND gate. Another logic expression is considered for circuit simpliﬁcation task. The equation is – – – O = A BC + AB C + ABC + ABC.
Fig. 2.57
The logic circuit based on this expression can be designed by using four three input AND gates, three Inverters and one four input OR gate as shown in Fig. 2.58. The above circuit is quite complex. The expression can be signiﬁcantly simpliﬁed by using Boolean laws. The steps of simpliﬁcation are given below: – – – O = A BC + AB C + ABC + ABC
Fig. 2.58
– – – Factoring BC of the ﬁrst and forth terms, we get O = BC(A + A) + AB C + ABC – – – Applying identity A +A = 1, we ﬁnd BC + AB C + ABC – – Factoring B from ﬁrst and third term, B(C + AC ) + AB C – – Apply Boolean identity A + A B = A + B, we get B(C + A) + AB C – After applying distribution law, we obtain BC + AB + AB C – Taking common A from second and third terms, we get BC + A(B + B C) – Then apply Boolean identity A + A B = A + B and we ﬁnd BC + A(B + C) After distributing, we ﬁnally get BC + AB + AC
Fig. 2.59
Therefore, the simpliﬁed logic circuit can be developed by using logic expression BC + AB + AC. Figure 2.59 shows the logic circuit for BC + AB + AC which is consists of three two inputs AND gates and three inputs OR gate.
Boolean Algebra and Logic Gates
Example 2.8 (a) (b) (c)
�
O= O= O=
Simplify the following logic expressions.
–– – – –– – – –– ABC D + AB C D + ABC D –– – – – – – –– ––– ABC D + A BC D + ABC D + ABC D – – – (A + B + C ) + (A + B + C )
Solution –– – – –– – – –– (a) O = ABC D + AB C D + ABC D –– –– – – = AC (BD + B D + BD)
(b)
67
–– – – – = AC (B(D + D) + BD) –– – – = AC (B + BD) –– – – – – – –– ––– O = ABC D + ABC D + ABC D + ABC D ––– – –– – = AC D(B + B) + AC D(B + B) ––– –– = AC D + AC D – –– = (A + A)C D –– = CD
–– Factoring out AC – Factoring out B from ﬁrst and –– – – second terms of (BD + B D + BD) – Applying D + D = 1)
––– Factoring out AC D from ﬁrst and second terms –– – – – – – –– ––– of O = ABC D + ABC D + ABC D + ABC D –– and AC D from third and fourth terms – Applying (A + A) = 1
– – – (c) O = (A + B + C ) (A + B + C ) Applying distribution identity – – –– – – –– – = AA + AB + AC + AB + BB + B C + AC + C B + C C) – Applying AA = A and C C = 0 – – – – – –– = A + AB + AC + AB + B + B C + AC + C B + 0) Factoring out A from ﬁrst to fourth terms – and seventh term and B from ﬁfth, sixth – – – – – – = A (1 + B + C + B + C ) + B (1 + C + C ) = A + B and eighth terms.
Example 2.9
Simplify the following logic expressions using DeMorgan’s Theorem.
– (a) O = (A + B + C) (A + B– + C) (b) O = A + BCD (c) O = (A + B + CD–)AB
� Solution –– – – – – (a) O = (A + B + C) (A + B + C) = A + B + C + A + B + C = A B C + ABC – – – – (b) O = A + BCD = A · BCD = A (B + C + D) –– – – – – –– – – –– (c) O = (A + B + C D)AB = (A + B + CD) + AB = ABC D + A + B = A B (C + D) + A + B
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Digital Electronics: Principles and Applications
Example 2.10
Make truth table of the binary expression O = A + B + C.D
� Solution The truth table of the binary expression O = A + B + C.D is given in Table 2.20. Table 2.20 Truth table for O = A + B + C.D
Inputs A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Example 2.11
B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Output C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
A+B 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
C.D 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
A + B + C.D 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Derive the logic expression from the truth table and implements the logic circuit using NAND gates. Table 2.21
Inputs A 0 0 0 0 1 1 1 1
B 0 0 1 1 0 0 1 1
Output C 0 1 0 1 0 1 0 1
O 1 0 1 0 0 0 1 1 Fig. 2.60
� Solution – – –– – – The logic expression of the above truth table is O = A BC + A BC + ABC + ABC and it can be simpliﬁed by using Boolean laws as given below. The ﬁnal result is A.C AB and hardware implementation with the help of NAND gates is depicted in Fig. 2.60. – – –– – – –– – – O = A BC + A B C + ABC + ABC = A C (B + B ) + AB(C + C) –– = A C + AB = A.C AB
Boolean Algebra and Logic Gates
69
2.8 CONSENSUS THEOREM – – (a) AC + BC + AB = AC + BC
– – (b) (A + C)(B + C ) (A + B) = (A + C)(B + C ) – Assume a three variables logic function F = AC + BC in which variable C is present in one of the – terms and the complement of C, (C ) is present in the other term. An extra product term of the remaining – two variables, AB is added in the logic function and it becomes F = AC + BC + AB. This extra product term, AB is known as consensus term. It can be proved that the output of F is equal to the output of as fol lows: – F = AC + BC + AB – – – = AC + BC + AB(C + C ) Applying (C + C ) = 1 – – – – – = AC + BC + ABC + ABC = AC + ABC + BC + ABC = AC(1 + B) + BC (1 + A) – = AC + BC Applying (1 + B) = 1 and (1 + A) = 1 Hence, the presence of consensus term in a Boolean function does not change the value of function and the optional product term AB is redundant. But sometimes, the consensus term may eliminates other terms and simplify the original Boolean equation. For example, assume a Boolean function F 1 = C + – ABC . For this function, the consensus term is AB which is added to the Boolean function F 1 and the new Boolean function is F 2 . – – – – F 2 = C + ABC + AB = C + ABC + AB(C + C ) Applying (C + C ) = 1 – – – = C + ABC + ABC + ABC = C + AB(C + C) = C + AB – Now, the original term ABC has been eliminated from original Boolean function and the consensus term AB becomes essential. The technique of forming consensus terms and add them to a Boolean function without changing its value is known as consensus theorem. The duality principle is that a theorem can be obtained from another theorem by interchanging binary operators ‘+’ and ‘.’ and the identity elements ‘0’ and ‘1’. For example, ‘A + 1 = 1’ is given as a theorem, we can obtain its dual by interchanging ‘+’ with ‘.’. Then the new theorem is ‘A.0 = 0’. In the same way, if ‘A.0’ is given as a theorem, we can obtain‘A + 1 = 1’ as dual. By using the duality principle, we can – – – prove that (A + C)(B + C ) (A + B) = (A + C)(B + C ) as this Boolean function is the duel of AC + BC + – AB = AC + BC by changing ‘+’ with ‘.’ and ‘.’ with ‘+’. Example 2.12
– – Prove that ABC + DC + ABD = ABC + DC using consensus theorem.
� Solution – Consider F = ABC + DC – = ABC + DC + ABD – – = ABC + DC + ABD(C + C ) – – = ABC + DC + ABDC + ABDC – = ABC (1 + D) + DC (1 + AB) – = ABC + DC
Add the consensus term ABD – Applying (C + C ) = 1
As (1 + D) = 1 and (1 + AB) = 1
70
2.9
Digital Electronics: Principles and Applications
POSITIVE LOGIC AND NEGATIVE LOGIC
The Binary input – output signals have always one of two values: logic ‘0’ and logic ‘1’. There are two different ways to assign a signal value to logic level such as positive logic Fig. 2.61 Positive logic and negative logic. Figure 2.61 shows the representation of positive logic and negative logic representation is illustrated in Fig. 2.62. In this ﬁgures, H stands for higher signal level when signal value is high. Similarly, L stands for lower signal level when signal value is low. Fig. 2.62 Negative logic When high level signal H represents logic ‘1’ and low level signal L corresponds to logic ‘0’, this signal representation is known as positive logic. If signal level H represents logic level ‘0’ and signal level L stands for logic ‘1’, this method of signal representation is called as negative logic. Therefore, positive and negative logic levels are not actual signal values, but they are different types of logic. Integrated circuit manufactures always mention the logic level of digital gates in their data sheet. For example, the representation of positive logic AND and OR gates and negative logic AND and OR gates are illustrated in Fig. 2.63 (a), (b), (c) and (d) respectively. The truth table of positive as well negative logic AND and OR gates are given in Fig. 2.63(e), (f), (g) and (h) correspondingly. The small triangle in the input and output terminals of negative logic AND or OR gate or any other gates stand for polarity indicator. When the polarity indicator is absent in a logic symbol of gates, the logic gates operate in positive logic. In the same way, when the polarity indicator is present in a logic symbol of gates, the logic gates operate in negative logic. During design of logic circuit, sometimes it is necessary to convert positive logic to negative logic or vice versa. When we convert positive logic to negative logic, logic level ‘1’ changes to logic level ‘0’ and logic level ‘0’ changes to logic level ‘1’. Figure 2.63(d) shows the negative logic OR gate and its truth table is Fig. 2.63(h). If AND operation is compared with the truth table of negative OR gate, we ﬁnd that the negative logic OR gate is equivalent to positive logic AND gate. Similarly, negative AND gate can represent an positive logic OR gate when we convert positive logic to negative logic. Therefore, if any logic circuit represented by AND and OR gates and the logic level changed from positive to negative, all AND gates will be replaced by negative OR gate and all OR gates will be substituted by negative AND gate to maintain the same output functions.
Fig. 2.63
(a) Positive logic AND gate (b) Negative logic AND gate (c) Positive logic OR gate (d) Negative logic OR gate (e) Truth table of positive logic AND gate (f) Truth table of negative logic AND gate (g) Truth table of positive logic OR gate (h) Truth table of negative logic OR gate
71
Boolean Algebra and Logic Gates
SUMMARY In this chapter, the operation, symbol and truth table of logic gates are conferred. The summary of logic gates is represented in Table 2.22. The universal gates and their applications to form any gates are incorporated. A brief introduction to Boolean laws, De Morgan’s theorem, Consensus theorem and positive and negative logic are also discussed. The simplification of logic expressions using Boolean laws and De Morgan’s theorem explained with examples. The implementation of logic functions using logic gates is also given. Table 2.22
Gate Buffer
Inverter
AND
NAND
OR
Summary of logic gates
Logic Symbol
Truth Table Input
Output
A
O=A
0
0
1
1
Input
Output
A
– O=A
0
1
1
0
Inputs
Output
A
B
O = A.B
0
0
0
0
1
0
1
0
0
1
1
1
Inputs
Output
A
B
—— O = A.B
0
0
1
0
1
1
1
0
1
1
1
0
Inputs
Output
A
B
O=A+B
0
0
0
0
1
1
1
0
1
1
1
1 (Contd.)
72
Digital Electronics: Principles and Applications Table 2.22 (Contd.) NOR
XOR
XNOR
Inputs
Output
A
B
—–— O = A +B
0
0
1
0
1
0
1
0
0
1
1
0
Inputs
Output
A
B
O=A
0
0
0
0
1
1
1
0
1
1
1
0
Inputs
B
Output
A
B
——— O=A B
0
0
1
0
1
0
1
0
0
1
1
1
MULTIPLE CHOICE QUESTIONS 1.
2.
3.
4.
In a positive logic circuit, (a) Logic 0 and 1 represented by 0V(ground) and positive voltage(+VCC) respectively (b) Logic 0 and 1 represented by negative and positive voltages respectively (c) Logic 0 voltage level is higher than logic 1 voltage level (d) Logic 0 voltage level is lower than logic 1 voltage level In negative logic, the logic 1 state corresponds to (a) Ground level (c) High voltage level (b) Negative voltage level (d) Low voltage level A NAND gate is called a universal logic element because (a) All digital computers use NAND gates (b) All the minimisation techniques are applicable for optimum NAND gate realisation (c) Everybody use this gate (d) Any logic function can be realised by NAND gates alone If a input signal A=11100 is applied to a NOT gate, its output signal is (a) 00011 (b) 01001 (c) 00011 (d) 1000
73
Boolean Algebra and Logic Gates 5. 6. 7.
8.
9.
10. 11. 12.
13. 14. 15.
A 3 inputs logic gate has its three inputs: A = 1, B = 0 and C = 1. If its output O = 1, the gate is (a) NOR (b) NAND (c) AND (d) OR When A and B represent the inputs of an Exclusive OR logic gate, its output O will be – – –— (a) O = AB + A B (b) O = AB + A + B (c) O = A + B + A B (d) None of these In positive logic, the logic 0 state corresponds to (a) Zero voltage (c) High voltage level (b) Any positive voltage (d) Low voltage level A two input OR gate is designed for positive logic. Consider that this gate is operated with negative logic. Then the logic operation will be (a) OR (b) AND (c) NOR (d) ExOR The following equation corresponds to De Morgan’s theorem in Boolean algebra –— – – (a) (A + B)(A + B) = A + AB + B (c) A B = A + B (b) (A + B)(A + B) = AA + AB + BB + BA (d) None of these A 2 input logic gate has its inputs A = 0, and B = 1. If its output O = 1, the gate would be (a) NOT (b) OR (c) AND (d) NOR The NOT symbol at the output of an OR gate converts it intogate (a) OR (b) NAND (c) AND (d) NOR The Boolean algebra is based on the premise that (a) Differential equations can be solved by analog circuits (b) There are two states (c) Data can be stored and retrieved (d) None of these Which of the following functions is referred as complementary? (a) NAND (b) NOR (c) OR (d) NOT What are the values of the inputs for a NAND gate if output is 1? (a) A = 0, B = 0 (b) A = 1, B = 0 (c) A = 0, B = 1 (d) A = 1, B = 1 What is the output function of the circuit shown in Fig. 2.64?
Fig. 2.64
16.
(a) O = ABCD (b) O = AB + CD (c) O = AB + CD Which function is implemented by the circuit as shown in Fig. 2.65?
(d) None of these
Fig. 2.65
(a) O = ABC 17.
(b) O = A + B + C
(c) O = AB + C
(d) None of these
Boolean algebra is different from ordinary algebra in which way? (a) Boolean algebra can represent more than 1 discrete level between 0 and 1.
74
18. 19. 20.
Digital Electronics: Principles and Applications (b) Boolean algebra have only 2 discrete levels: 0 and 1. (c) Boolean algebra can describe up to levels of logic levels. (d) They are actually the same. If output of a three inputs OR gate is ‘0’, what are the conditions of inputs A, B, and C ? (a) A = 0, B = 0, C = 0 (b) A = 1, B = 0, C = 0 (c) A = 0, B = 1, C = 0 (d) A = 1, B = 1, C = 1 What is the output of the circuit shown in Fig. 2.65 if A = 0, B = 1 and C = 0 (a) 0 (b) 1 (c) High impedance (d) None of these DeMorgan’s law converts (a) OR to NOR (b) NOR to NAND (c) NOR to AND (d) None of these
REVIEW QUESTIONS 2.1 2.2 2.3
Draw the logic symbol of four input AND gate and write the truth table of four input AND gate. Draw the circuit diagram of ExOR gate using NAND and NOR gates. Write the truth table of the logic circuit as given below:
Fig. 2.66
2.4
Derive the logic expression of the logic circuit as given below and also write the truth table.
2.5
Draw the output of the two input NAND gate with the given inputs A and B.
Fig. 2.67
Fig. 2.68
2.6
Draw the output of the two input AND gate with the given inputs A and B.
Fig. 2.69
2.7
Draw the output of the three input NAND gate with the given inputs A, B and C.
Fig. 2.70
Boolean Algebra and Logic Gates 2.8
75
Draw the output of the three inputs ExOR gate with the given inputs A, B and C.
Fig. 2.71
2.9.
Prove the following identities of Boolean algebra – – (a) A + A = A (b) A. A = 0 (c) A + A = 1 (d) A.A = A 2. 10 Prove the commutative law (a) A + B = B + A (b) AB = BA 2.11 Prove the distributive law (a) A + (BC) = (A + B)(A + C) (b) A(B + C) = (AB) + (AC) 2.12 Prove the following relationship (a) AB + AC + BC = AB + AC (b) (A + B)(A + C)(B + C) = (A + B)(A + C) 2.13 Simplify the following logic expressions. –– – – –– – –– – –– (a) O = A B C D + A B C D + A B CD + A B CD –– – – (b) O = A B D + AB D + ABD + B CD –– – –– – (c) O = ABC + ABD + A B C + A B D 2.14. Simplify the following logic expressions using De Morgan’s Theorem –– (a) O = (A + BC) (A B + C) (c) O = AB + CD –– (b) O = A + B + CD (d) O = (AB + CD) 2.15 Make truth tables for each of the following 1bit binary expressions. – (a) O = A B + C (c) O = ABC + D – –— (b) O = A + BC (d) O = AB + CD – (e) O = BC + AD 2.16 Derive the logic expression from the truth table as given in Table 2.23 and implements the logic circuit using NAND or NOR gates. Table 2.23
Inputs
Output
A
B
C
O
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 1 0 1 1
CHAPTER
3 DIGITAL LOGIC FAMILY 3.1
INTRODUCTION
The logic gates are discussed in Chapter 2. Presently, these gates are available in integrated form and the digital Integrated Circuits (ICs) are most commonly used in complicated digital circuits design. The logic gates can be designed in different methods. Therefore, there are different types of logic family, but unipolar and bipolar logic family are the main logic family. Transistors, diodes and resistors are main elements of bipolar logic family, but MOSFETs are used in unipolar logic family. In this section, bipolar and unipolar logic families are discussed brieﬂy.
3.2
CLASSIFICATION OF DIGITAL LOGIC FAMILY
The digital logic family has broadly twocategories, namely bipolar logic and unipolar logic. The bipolar logic families are classiﬁed as saturated and unsaturated types. In saturated type of bipolar logic family, transistors are operated in between cutoff and saturation. Resistor transistor logic (RTL), Direct coupled transistor logic (DCTL), Integrated injection logic (IIL or I2L), Diode transistor logic (DTL), Transistor transistor logic (TTL), and High threshold logic (HTL) are commonly used bipolar logic families. In unsaturated bipolar logic family, the transistors are operated in between cutoff and nonsaturation. Schotty TTL and Emitter coupled logic (ECL) are examples, of unsaturated bipolar logic family. There are two types of unipolar logic family, namely pchannel MOS (PMOS) and nchannel MOS (NMOS) and complementary MOS Fig. 3.1 Classiﬁcation of digital logic family (CMOS). The classiﬁcation of digital logic family is shown in Fig. 3.1. The logic family can also be classiﬁed into four groups depending on the number of transistors in an IC. Table 3.1 shows all four groups. The various logic types of logic families are explained in this chapter.
77
Digital Logic Family
Table 3.1 Classiﬁcation of logic family based on complexity measured by number of transistors
Name of Group
No of Transistors
Applications
Small scale integration (SSI)
Less than 100
SSI circuits are used for educational purposes, and interface complex digital devices.
Medium scale integration(MSI)
Above 100 but below 1000
MSI circuits used in multiplexers, demultiplexers, registers, and counters, etc.
Large scale integration(LSI)
Above1000 but below 10000
LSI circuits are used in small memory chips, and programmable logic devices.
Very large scale integration(VLSI)
More than 10000
VLSI are applied in large computer memories, microprocessors, microcontrollers, and digital signal processors
3.3
CHARACTERISTICS OF DIGITAL LOGIC FAMILY
Before discussion on various types of logic families, the performance parameters of a logic family are explained for better understanding. The most important performance parameters are given below: ∑ Speed of operation ∑ Power dissipation ∑ Voltage parameters ∑ Current parameters ∑ Noise immunity ∑ Fan in ∑ Fan out ∑ Cost ∑ Availability The designer should select a particular logic family for any application based on the actual requirement. To design a efﬁcient logic circuit, the designer should study the performance parameters from IC manuals in detail. Speed of Operation The operating speed of a logic family is determined from the propagation delay. If a square wave is applied to the input of an inverter, output of the inverter will be a square wave as shown in Fig. 3.2. It is very clear from Fig. 3.2 that the propagation delay is measured from the time difference between 50% logic transition of input from its initial value and 50% logic transition of output. There are two types of Fig. 3.2 Input and output waveform of an propagation delay times, namely tPHL and tPLH. inverter The propagation delay tPHL is the delay time when output changes from HIGH to LOW due to change in input. Similarly, tPLH is the propagation delay for output changes from LOW to HIGH. Generally, tPHL and tPLH are very close to each other. Actually, we consider the average value of tPHL and tPLH. The propagation delay varies in between 1 to 20 nano seconds. For proper operation of a logic gate, the time period of input signal must be more than propagation delay time. If input frequency is very high, and cycle time is less than propagation delay, the switch starts malfunctioning.
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Digital Electronics: Principles and Applications
Power Dissipation Power dissipation is the amount of power drawn from supply during static and dynamic condition. In static condition, the power dissipated in a logic gate is called static power consumption and similarly, the dynamic power consumption takes place in dynamic condition or switching transitions. The static power consumption is the power dissipated in logic gate when the device is either ON or OFF. During the transition from OFF to ON or ON to OFF, the power consumed in a gate is called dynamic power consumption. The voltage and current waveforms of logic gate are depicted in Fig. 3.3. The power dissipation is directly proportional to switching frequency and inversely proportional with cycle time. CMOS ICs have very low power consumption at low frequency. If frequency Fig. 3.3 Voltage and current wave form of a logic gate increases, power dissipation increases. The average power dissipation is determined by the simplest expression VCCIC, where IC is the average value of current. Generally, the power dissipation varies in the range of milliwatts (mW). Voltage Parameters High level input voltage (VIH ): VIH is the minimum input voltage guaranteed to be recognised as logic 1 or HIGH. VIH is 2 V for TTL and 3.5 V for CMOS. If input voltage is less than VIH, it will not be accepted as logic 1 or HIGH. Low level input voltage ( VIL ): VIL is the maximum input voltage guaranteed to be recognised as logic 0 or LOW. VIL is 0.8 V for TTL and 1.5 V for CMOS. When input voltage is greater than VIL, it will not be accepted as logic 0 or LOW. High level output voltage (VOH ): VOH is the minimum output voltage for HIGH state or logic1 under deﬁned load conditions. VOH is 2.4 V for TTL and 4.9 V for CMOS. Low level output voltage (VOL): VOL is the maximum output voltage for LOW state or logic 0. VOL is 0.4V for TTL and 0.1V for CMOS. Current Parameters High level input current (IIH): IIH is the current that ﬂows into an input when a high level or logic ‘1’ voltage is applied to that input. Low level input current (IIL): IIL is the current that ﬂows into an input when a low level or logic ‘0’ voltage is applied to that input. High level output current (IOH): IOH is the maximum current that ﬂows from an output and the output can source in HIGH state or logic ‘1’ while still maintaining the output voltage above VOH. Low level output current (IOL): IOL is the maximum current that the output can sink in LOW state or logic ‘0’ while still maintaining the output voltage below VOL. Noise Immunity Noise is always present in electronics circuits due to stray electric and magnetic ﬁelds. This signal is unwanted and spurious. Sometimes, the noise signal distorts the output voltage of the gate. Noise immunity of a logic gate means the circuit’s ability to tolerate noise. In order to correctly recognise logic ‘0’ and logic ‘1’ states, noise immunity is measured quantitatively which is
Digital Logic Family
79
known as noise margin (NM). There are two types of noise margin such as low noise margin and high noise margin. Low noise margin (LNM), VNL: VNL is the largest noise amplitude that is guaranteed for no change of the output voltage level when the input voltage of the logic gate is in the LOW interval. The low noise margin is measured by the expression as given below: VNL =VIL– VOL.
High noise margin (HNM), VNH : VNH is the largest noise amplitude that is guaranteed for no change of the output voltage level when the input voltage of the logic gate is in the HIGH interval. It is measured by VNH = VOH – VIH. Fan In Fan in is the maximum number of inputs for a logic gate in a particular logic family. This number is limited due to delay time. For example, a two inputs AND gate has fanin of two, a three inputs OR gate as a fanin of three and a NOT gate or an inverter has a fanin of one. Generally, delay of operation of any gate increases with increasing fanin quadratically. Gate delay is the delay offered by a gate for the signal applied at input terminals, before it reaches the gate output. Gate delay is also known as propagation delay. Fan Out Fan out is deﬁned as the number of similar logic gates driven by a single logic gate. While a logic gate has high fan out, it is advantageous to design integrated chips, as less number of driving circuits are required. The fanout depends on the amount of source or sinks current of a gate while the gate drives other gates. When a logic gate output with more than its rated fanout, the logic gate has the following effects: ∑ The operating temperature of the device will be increased. Hence, reliability of the device will be reduced and eventually the device may fail. ∑ Propagation delay will be increased and it may be above speciﬁed value. ∑ The output rise and fall times may be increased beyond speciﬁcation. ∑ In the low state, the output voltage VOL may increase above maximum value of VOL . ∑ In the high state, the output voltage VOH may decrease below the minimum value of VOH . The factors that limit the fanout of a gate are the output current capacity as speciﬁed by the parameters IOH and IOL, and the input current requirements of the driven gates as speciﬁed by their parameters IIH and IIL. Certainly, the sum of the currents IIH for all the gates driven by a gate must be less than the current IOH of the driving gate. In the same way, the sum of the IIL current parameters must be less than IOL for these gates. When all of the gates have the same current parameter values, then the fanout due to current considerations can be expressed by a constant integer which is the maximum number of gate inputs that can be connected to a single gate output. The fanout can be deﬁned as the largest integer less than or equal to minimum of (IOH/IIH, IOL/IIL), where IOH/IIH is the number of gates that can be driven by a single gate when output signal is high, and IOL/IIL is the maximum number if the output signal is low. Figure 3.4 shows a TTL AND gate drives ‘N’ numbers of similar AND gates for high level output and low level output. Here, N is the fan out of the gate and it can be determined from current driving capability of output and the current requirement of input. If maximum current driving capability IOH and maximum current requirement of each input IIH are known, the fan out of the gate will be
80
Digital Electronics: Principles and Applications
N=
I OH I IH
For example, consider IOH is equal to 500µA and IIH is 25µA. The fan out is I 500 N = OH = = 20. I IH 25
Fig. 3.4 (a) Fan out computation for high level output (b) Fan out computation for low level output
Cost The cost of a digital IC depends on the quantity manufactured. The designer always tries to design low cost ICs though the quantity of ICs used is large.
Availability To choose a logic family for particular applications, availability is an important parameter. Availability can be considered in to different ways as given below: The popularity of the logic family: The popularity of a particular logic family depends upon the users and digital circuit designers. If application of a logic family is more, a large number of ICs of that logic family will be manufactured. Therefore, the cost per IC will be very small and easily available in the market. The breadth of the logic family: The breadth of the logic family means to the number of different logic functions, ICs available. The complex functions would have to be constructed using basic ICs. For example, the TTL logic family has very good popularity and high breadth over other logic families. Wired logic capability: Due to wiredlogic capability, the outputs may be connected jointly to achieve extra logic without additional hardware. Various ﬂexibilities are available in different IC logic families and these must be considered while selecting a logic family. Availability of complement outputs: If the complement of outputs is available in ICs, the additional inverter is not required to invert the output. Example 3.1
Calculate the fan out of a NAND gate which drives NAND gates.
Assume IOH = 0.4 mA, IOL = 16 mA, IIH = 0.1 mA, and IIL = 0.4 mA.
�
Solution
Fan out at high level output, N =
I OH 0.4 = = 20 I IH 0.02
Fan out at low level output, N =
I OL 16 = = 40 I IL 0.4
The fanout of the gate is minimum of (
I OH I OL , ) = minimum of (20, 40) = 20 I IH I IL
Digital Logic Family
3.4
81
BJT CHARACTERISTICS
The characteristic of bipolar junction transistor (BJT), which is used in internal structural design of digital circuits has been discussed in this section. Bipolar transistors are npn and pnp type and they are constructed either with germanium or silicon semiconductor material. Generally, IC transistors are made with silicon and they are usually npn type. The schematic symbol of npn and pnp transistors with base (B), emitter (E) and collector (C) terminals are shown in Fig. 3.5(a) and (b) respectively. The information about the characteristic curves of a common emitter Fig. 3.5 Schematic symbols npn silicon transistor as shown in Fig.3.6 are required for the analysis of (a) npn BJT and (b) pnp BJT of digital circuits. Figure 3.6 (a) is a simple inverter circuit which is consists of two resistors RC and RB and a transistor. The current IC ﬂows through the resistor RC and the collector of the transistor. This current is known as collector current. The current IB ﬂows through the resistor RB and the base of the transistor. This current is called as base current. The emitter terminal is grounded and the current ﬂows through emitter IE = IC + IB. The VCE stands for the collector to emitter voltage and VBE stands for base emitter voltage.
Fig. 3.6
(a) Inverter circuit (b) Base characteristics of npn transistor (c ) Collector characteristics of npn transistor
The base–emitter characteristic of npn BJT is illustrated in Fig. 3.6(b). This is the plot of base current variation with respect to VBE. For silicon made transistor, when the base emitter voltage VBE is less than 0.6V, the transistor is said to be cutoff. Consequently, base current IB = 0 and very small current ﬂows in the collector. Then collector to emitter circuit behaves as an open circuit. When the baseemitter junction is forward biased and is greater than 0.6V, the transistors starts to conduct and the base current IB increases rapidly as shown in Fig. 3.6(b) and the voltage across baseemitter junction is about 0.8V. The collector emitter characteristics with a typical load line are shown in Fig. 3.6( c). When VBE is less than 0.6V, the transistor is at cutoff and no base current ﬂows, but negligible current ﬂows in the collector. The collector to emitter circuit behaves like an open circuit. In active region, the collector to emitter voltage VCE can be varied from about 0.8V to VCC. The collector current in this region is approximately hfe IB, where hfe is the dc current gain of the transistor. It should be noted that the maximum collector current does not depend on the IB, but on the external resistance RC. Therefore, VCE is always positive and its lowest possible value is 0V. After assuming VCE = 0, the maximum IC current can be determined from IC = VCC/RC.
82
Digital Electronics: Principles and Applications
The relationship between collector current and base current IC = hfe IB is Operating VBE (V) Current relaVCE (V) valid only when the transistor operates region tionship at active region. The parameter hfe Cutoff 0.2V IC = hfe IB of the transistor, but it is very useful to Saturation 0.7 to 0.8V 0.2 V consider an average value for the shake I ≥ I hfe B CS of analysis of transistor. In a typical operating range, hfe is about 50 and it may be varied up to 20. It can be observed that the base current may be increased to any desirable value, but the collector current is limited by the external resistance RC. As a consequence, a situation can be reached when hfe IB is greater than IC. When this condition arises, the transistor is said to be in saturation region. Thus, the condition for saturation is determined from the relation hfe IB ≥ ICS, where ICS is the maximum collector current ﬂow during saturation. VCE is not zero in the saturation region, but it is approximately 0.2V. The typical values of basic parameters of the transistor characteristics are listed in Table 3.2. The above information will be used for better understanding of circuits operation and the analysis of basic circuits of all bipolar logic families which are discussed in this chapter. Table 3.2
Parameters of the typical npn silicon transistor
3.5 DIRECTCOUPLED TRANSISTOR LOGIC (DCTL)
Fig. 3.7
Directcoupled transistor logic (DCTL)
Figure 3.7 shows the Direct–coupled Transistor Logic (DCTL) for a three inputs NOR gate. The input voltage is applied to the base of transistors and the output is taken from the collector of transistor. When logic 1 or + VCC is input to A, B, and C, transistors saturate, the output voltage drops to its saturation voltage or OV. The operation of DCTL is highly affected due to change in slight differences in characteristics of transistors. If the base emitter of one transistor is slightly less than other transistors, then transistor draws most of the current and proper operation of DCTL circuit will be disturbed. This phenomena is called current hogging. This current hogging can be reduced if resistances are connected in series with base of transistor and then base current is less depended on base emitter characteristics. Then the circuit is called Resistor Transistor logic (RTL).
3.6
Fig. 3.8
Resistor transistor logic (RTL)
RESISTOR TRANSISTOR LOGIC (RTL)
A Resistor Transistor Logic (RTL) circuit of a three inputs NOR gate is shown in Fig. 3.8. In this circuit, resistance is connected in series with the base of each transistor to reduce the hogging current effect. Actually, the input capacitance has been charged and discharged through this additional resistance and time constant will be increased. Therefore, the switching speed becomes slower. The fanout of RTL is four or ﬁve and time delay is approximately 50 ns.
Digital Logic Family
83
If inputs A, B and C are LOW, transistors T1, T2 and T3 are cutoff and the output is HIGH or + VCC. When any one of the inputs A, B and C is HIGH, the corresponding transistor operates in saturation and the output will be LOW or 0.2 V approximately. Thus NOR logic is satisﬁed.
3.7
DIODE TRANSISTOR LOGIC (DTL)
Diode Transistor Logic (DTL) circuit is most commonly used in logic family. Figure 3.9 shows a DTL logic circuit. This circuit is actually a NAND gate. To perform logical operation, inputs are given at the terminals A, B, and C of the diodes D1, D2 and D3 respectively. Then the signal is coupled with a diode D and an inverter, which consists of a transistor and a load resistance. When all inputs are logical 1 or + VCC, diodes D1, D2, D3 are reversed biased and no current passes through diodes. The diode D is forward biased and current will ﬂow through Resistance RB, Diode D and base of the Fig. 3.9 Diode transistor logic (DTL) transistor T. Then transistor T operates at saturation. The output voltage of the transistor is logic 0. When any one input signal is low (A = logical 0, B and C are logical 1), diode D1 is forward bias and current will ﬂow through RB and D1. Then diode D is not conducting and current will not ﬂow through D and base of Transistor T. Hence T is in cutoff and output will be high or logic level 1. As the signal passes through the forward bias diodes to transistor, the switching speed of DTL is faster than RTL. Fan out is also increased due to high input impedance. The switching delay is approximately 25 ns and fan out is 8. Therefore, DTL integrated circuits are economical.
3.8
TRANSISTORTRANSISTOR LOGIC (TTL)
In Transistor Transistor logic (TTL), logic gates are built only around transistors. TTL was developed in 1965. All TTL families are available in small scale integration (SSI) package and in more complex forms as MSI and LSI packages. The differences in the TTL series are not in the digital functions that they perform but rather in the values of resistances and different type transistors which are used to develop basic gates. There are many versions or families of TTL, such as Standard TTL, High Speed TTL, Low Power TTL and Schhottky TTL. TTL gates in all the versions come in three different types of output conﬁguration such as ∑ Totem pole output conﬁguration ∑ Open collector output conﬁguration ∑ Tristate or three states output conﬁguration TTL circuit is most popular in bipolar logic family as it is the fastest saturating logic family Figure 3.10 shows the basic TTL circuit for a two inputs NAND gate. A single multiemitter transistor replaces input diodes and the series diode of DTL. Each emitterbase diode serves Fig. 3.10 Transistortransistor logic as one input, and the basecollector diode functions as the (TTL) series diode. The multiemitter transistor is economically fabricated in monolithic form. In a multiemitter transistor, a single isolated collector region is dif
84
Digital Electronics: Principles and Applications
fused, a single base region is diffused and formed in the collector region, and the several emitter regions are diffused as separate areas into the base region. An output stage using an active pullup transistor is added to the basic logic circuit to give currentgain drive for switching in both directions. This output conﬁguration results in faster switching speed and higher fanout capability. The TTL circuit is adaptable to virtually all forms of IC logic and produces the highest performancetocost ratio of all logic types. TTL circuits for all gates have been discussed later in detail. The different series of TTL circuits are presently available. All these circuits are based on the same basic circuit, but some of their properties have been optimised based on special applications. These devices in the standard TTL series are designated with a number preﬁxed by a 74. For example, 7400 stands for a NAND gate, and 7404 stands for an inverter, etc. If the resistor values in the TTL circuit are increased, its average power dissipation can be reduced. On the other hand, propagation delay will be increased. This low power TTL series are designated as 74LXX (74L00, 74L04, etc) and the typical power dissipation range is 1mW to 10mW for any standard gate. Typical propagation delays are 33ns for 74L circuits as compared to 9ns for 74 series circuits. The high speed TTL series are designated as 74HXX (74H00, 74H04, etc). The typical power dissipation of a 74H00 NAND gate is 22.5mW, but its propagation delay is about 6ns. The 74XX, 74LXX, and 74HXX TTL series are the early logic families. In these circuits, some of their transistors operate into saturation. Therefore, there is an excess of charge in base region and limits the speed at which the transistor can switch from the saturated to the cutoff mode. Then the standard TTL circuit is modiﬁed by using a special type of diode called a Schottkybarrier diode to prevent the transistors from going into saturation. This series is known as Schottky TTL and is designated as 74SXX (74S00, 74S04, etc.). This series has a typical power dissipation of 18.75mW and a typical propagation delay of about 3ns. Though 74SXX series use a more complicated circuit than the other series, but due to high speed, the circuit is more susceptible to noise. The lowpower Schottky TTL series is developed by reducing the resistor values in a Schottky circuit in order to minimise power dissipation. This series Series Propagation Power is designated as 74LSXX (74LS00, 74LS04, etc.). Delay Dissipation The propagation delay of 74LSXX series is about 74XX 10ns 10mW 9.5ns and power dissipation is approximately 2mW. 74LXX 33ns 1mW Consequently, 74LSXX series has about the same 74SXX 3ns 19mW speed as a standard 74XX series, but the power 74LSXX 9.5ns 2mW dissipation is about one ﬁfth power dissipation of 74HXX 6ns 22mW 74XX series. 74ASXX 1.5ns 10mW The other members of TTL family are the Advanced Schottky and Advanced Low Power Schott74ALSXX 4ns 1mW ky series. The Advanced Schottky is represented by 74AS and the Advanced Low Power Schottky series is designated as 74ALS. These TTL series have signiﬁcant improvements in speed and power dissipation over Schottky and Low Power Schottky. The typical power dissipations of 74AS series gates are about 10mW and 1mW for ALS parts. Due to high speed and low power consumption, the 74ALS and 74AS series are very popular in design of TTL gates. The comparison of different TTL family based on speed and power consumption is given in Table 3.3. Table 3.3
Comparison of different TTL family
Digital Logic Family
3.9
85
EMITTERCOUPLED LOGIC (ECL)
The emittercoupled logic circuit is shown in Fig. 3.11. The emitters of transistors T1, and T3 are coupled with the emitter of a reference transistor T2. The commonemitter resistor of transistors T1, T2, and T3 is very high so that it behaves as a constantcurrent source. Figure 3.11 depicts a constant current source in place of the commonemitter resistor of transistors T1, T2, and T3. A reference voltage VR is connected to the base of transistor T2. When the inputs A and B are logical ‘0’ or ground potential, T1 and T3 are in cutoff. Current will not ﬂow Fig. 3.11 Emittercoupled logic (ECL) through RC, and the output Y1 will be logical high, +Vcc. If one of the inputs or both inputs are logical ‘1’ and greater than the reference voltage VR, transistor T1 or T3 or both transistors conduct. As current ﬂows through the corresponding transistors and RC, the collector potential becomes low. Then output Y1 is logical ‘0’. When current through the transistors T1 or T3 increases, current through the reference transistor T2 decreases. The threshold voltage of T1 or T3 is equal to the reference voltage VR. As Emitter coupling is present in the circuit, it does not allow transistors to operate in saturation. Therefore, the switching speed of ECL is very fast and it is approximately few nanoseconds. Power dissipation of ECL is comparatively high and its value is about 50 mW. As output impedance of ECL circuit is very low, fanout of this logic family is very high approximately 25. Table 3.4 Comparison of logic family The standard digital circuits of DCTL, RTL, DTL, TTL and ECL are explained above. The Logic Power Propagation Fan out family dissipation delay designer chooses a particular logic family for a speciﬁc application after reading all RTL 24mW 50ns 5 performance parameters of each logic family DTL 10mW 30ns 8 from their data sheet. Table 3.4 shows the TTL 10mW 10ns 10 comparison between RTL, DTL, TTL and ECL ECL 40mW 2ns 25 logic families based on power dissipation, propagation delay and fanout.
3.10
SCHOTTKY TTL
The Schottky TTL is a unsaturated logic family and this TTL series is actually known on the name of Schottky diode inverter. In Schottky TTL circuit, transistors are prevented from saturation by using Schottky transistors. These transistors are obtained when a Schottky diode is connected between the base and the collector of a normal transistor as shown in Fig. 3.12(a). Figure 3.12(b) shows the symbol of Schottky transistors. Schottky diodes have different characteristic from normal pn junction diodes and these diodes have very low saturation voltage of the order of 0.4V. In case of normal pn junction diodes, the saturation voltage is about 0.6V. In TTL logic family, transistors operate in saturation. When a silicon transistor operates in saturation, the base to emitter voltage (VBE) is about 0.7V and the collector to emitter voltage (VCE) is about 0.1V. If a Schottky diode is connected with normal transistor, the collector to emitter voltage (VCE) voltage will be more than 0.4V but less than the base to emitter voltage (VBE). Conse
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Digital Electronics: Principles and Applications
quently, the Schottky diode holds the collector to a voltage, which prevents the transistor to operate in fully saturation. So, the diffusion capacitance and propagation delay are reduced. Therefore, Schottky transistors can operate at very high switching speeds and perform consistently up to about 100MHz. A Schottky TTL NAND is shown in Fig. 3.13. Transistors T2 to T6 are Schottky transistors and diodes D1 to D5 are Schottky diodes in Fig. 3.13. All resistances (R1 to R6) are high value compared to TTL logic family. Four different types Schottky TTL, namely SchottFig. 3.12 Schottky transistor Fig. 3.13 Schottky TTL NAND gate ky TTL, low power Schottky TTL, advanced Schottky TTL and advanced low power Schottky TTL are available. Table 3.5 shows the comparison between Schottky TTLs based on power dissipation, propagation delay and fanout. Table 3.5 Comparison of logic family
Logic family Schottky TTL
Power dissipation
Propagation delay
Fanout
20mW
3 ns
10
Low power Schottky TTL
2mW
10 ns
20
Advanced Schottky TTL
17mW
1.5 ns
40
Advanced low power Schottky TTL
1mW
4 ns
20
3.11
HIGH THRESHOLD LOGIC (HTL)
This logic is particularly designed to work in industrial environments, where the noise level is quite high. The principle of operation is the same as that of DTL, but the voltage level used is 15V. The noise margin obtained by HTL is around 7V.
3.12
INTEGRATED INJECTION LOGIC (IIL)
This logic family uses a combination of pnp and npn transistors. In an IC, it is always easier to make pnp and npn pair, and such a pair occupies less space. Thus, the packing density on the chip is improved. Therefore, the gate size is very small. Example 3.2
Determine the fan out of the DTL circuit as shown in Fig. 3.14.
Assume R = 5KΩ, R1 = R2 =… RN = 10 KΩ, VCE(sat) = 0.2V, VD = 0.7V and IC = 1.8mA.
87
Digital Logic Family � Solution Consider input at terminal A is logic level 1 and other terminals are in logic level 0. Therefore, transistor T1 operates in saturation. The current ﬂow through diodes D1, D2 …. DN is IL and it is calculated by VCC  VD  VCE (sat) 5  .7  .2 IL = = mA = 0.41mA R1 10 The current ﬂow through the resistance R is I1 VCC  VCE (sat ) 5  .2 I1 = mA = 0.96mA = R1 5 The collector current of transistor T1 is IC1 = N IL + I1 where, N is the fan out I  I 1.8  .96 = 2.04 = 2 So, the fan out N = C 1 = IL .41
Example 3.3
Fig. 3.14
Calculate fan out and average power dissipation of DTL circuit as shown in Fig. 3.15.
Assume Vd = 0.7V, VBE = 0.75V, VCE sat = 0.2V, hfe = 50, R1 = 4.7K, R2 = 4.7K, R3 = 3.3K
�
Solution
Consider A, B, and C are high and diodes D1, D2 and D3 are reverse biased. Diode D4 is conducting and transistor T1 is in saturation, the voltage at P1 is VP1 = on state voltage of D4 +on state voltage of D5 + VBE sat = 0.7 + 0.7 + 0.75 = 2.15 V Current ﬂow through D4 is V  VP1 5  2.15 I1 = CC = mA = 0.606 mA 4.7 R1 Current ﬂow through R2 is 0.75 V I 2 = CE = mA = 0.16 mA 4.7 R2 Applying KCL at P2, the base current of transistor T1 IB = I1 – I2 = (0.606 – 0.16) mA = 0.446 mA The collector current V  VCE 5  0.2 I C = CC = mA = 1.45 mA 3.3 R3
Fig. 3.15
The hfe IB = 50 ¥ 0.446 mA = 22.3 mA. As hfe IB is grater than IC, the transistor T1 operates in saturation. The output of the transistor will be low. To determine the fan out, consider load current IL = 0.9 mA.
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Digital Electronics: Principles and Applications IL N + IC £ 22.3 mA 0.9N + 1.45 £ 22.3 mA 22.3  1.45 N= = 23.1 .9
The fan out of the transistor T1 is 23. The power dissipation in transistor T1 when output is Low P1 = VCC (I1 + IC) = 5(0.606 + 1.45)mW = 10.28 mW The power dissipation in transistor when output is High P2 = VCC I1 = 5 ¥ 0.606 = 0.303 mW Average power dissipation is P + P2 10.28 + 0.303 Pav = 1 = mW = 5.29 mW 2 2
Example 3.4
Determine the voltages at P1, and P2 of TTL circuit as shown in Fig. 3.16. Assume VA= 1.1V, VB = 4.5V, VBE = 0.7V, VCC = 5V, R1 = 4.7K, R2 = 4.7K, R3 = 2.2K
�
Fig. 3.16 Transistortransistor logic (TTL)
Solution
The input voltages at A, B are VA = 1.1V, and VB = 4.5V respectively. As VA is 1.1V, emitter base junction of T1 to input terminal A is conduction state. Consequently, the VP1 = VA + VBE = 1.1V + .7V = 1.8V The base emitter junction of T2 will be saturate when VP1 = 0.7 + 0.7 + 0.8 = 2.2V. As VP1 is 1.8 V, T2 will be OFF but transistor T1 conducts to input terminal A. Therefore, IB2 = 0 and the output voltage is equal to 5V. So VP2 = 5V.
3.13
TTL LOGIC GATES
The TTL logic based Inverter, buffer, NAND, AND, OR and NOR gates are explained below:
3.13.1
Fig. 3.17
Practical inverter circuit
The NOT Gate with Totem– Pole Output
The singletransistor inverter circuit is already explained in Chapter 2 and this is not most commonly used. Actually, all practical inverter circuits contain more than one transistor for improving voltage gain and transistors operate in full cutoff or full saturation. Other components of inverter circuit are used to reduce the possibility of damage. Figure 3.17 shows the practical inverter circuit.
Digital Logic Family
89
In the circuit as shown in Fig. 3.18, diode D1 will be reversebiased. As diode D1 is not conducting, no current will ﬂow through it. Actually, D1 is used in the circuit to protect transistor when a negative voltage is impressed on the input. With no voltage between the base and emitter of transistor T1, no current will ﬂow through transistor. A backtoback pair of diodes can replace T1 as shown in Fig. 3.19. Depending on the logic level of the input, the function of diodes is to steer current to or away from the base of transistor T2. When the input is Vcc, no current will ﬂow through the left steering diode of T1. But, there will be current through the right steering diode of T1 through resistor R1, as well as through baseemitter diode junction of T2 and T4. So, transistors T2 and T4 will have base current, and T2 and T4 will be turn on. The voltage between the base of T1 and ground will be approximately 2.1 volts. This voltage drop is equal to the combined voltage drops of three pn junctions, namely the right steering diode of T1, baseemitter diode of T2, and baseemitter diode of T4.
Fig. 3.18
Practical inverter circuit with input Vcc
Fig. 3.19
Practical inverter circuit with input VCC
As base current is ﬂow through transistor T2, it will be turned on and it also be saturated. When T2 is saturated, the voltage drop across resistor R3 will be enough to forwardbias the baseemitter junction of transistor T4. Therefore, transistor T4 will operate in saturation. As T4 is saturated, the output voltage will be almost 0 volts or a binary ‘0’ or logic level low. The voltage between the base of T3 and its emitter is not enough to turn on it due to diode D2. So, T3 remains in cutoff. If input is connected with ground as shown in Fig. 3.20, all of the current goes through the left steering diode of T1 and none of it through the right diode. We know that pn junction diodes are very nonlinear devices. If the forward biased voltage is more than threshold voltage, it conducts. When diodes begin to conduct, the voltage drop across diodes are not more than 0.7 volts. In this circuit, the left diode of the steering diode pair is fully conducting, and the voltage drop across it is approximately about 0.7 volts. This eliminates current through the base of T2, thus turning it off. When T2 is off, there is no longer a path for T4 base Fig. 3.20 Practical inverter circuit with input ground current. So T4 goes into cutoff. On the other hand, T3 has
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Digital Electronics: Principles and Applications
sufﬁcient voltage dropped between its base and ground to forwardbias its baseemitter junction and saturate it. Accordingly, the output terminal voltage will be logical high. In actuality, the output voltage will be somewhere around 4 volts depending on the degree of saturation and any load current, but still high enough to be considered a high logic level. Now, we can say that the circuit behave as inverter. When input is binary ‘1’ and output is ‘0’. If input is binary ‘0’ output will be ‘1’. Table 3.6 shows the truth table of inverter. Table 3.6
Truth table of inverter
Input A
T1
T2
Transistor T3
T4
Output O
Low High
Saturation Cutoff
Cutoff Saturation
Saturation Cutoff
Cutoff Saturation
High Low
The advantage of totempole output circuits is that there is always one of the totempole transistors is cutoff, except during the transition from one output state to the other output state. Therefore, the required pullup resistor R4 should be much smaller than the simple passive pullup circuit resistance. Since RC time constant reduces, the time required to charge the input capacitance of gates which is connected to a totempole output decreases. There are some disadvantages of the totempole output circuit as follows. When the circuit output changes from one state to the other, the two transistors (T3 and T4) must both change modes, and they will not change at exactly the same time, so that there is a very short interval when both are conducting and the current through R3 will be larger during this interval than when one of the transistors is cutoff. As a result, a surge of current is generated and a noise voltage “spike” can be detected on the power supply line. The magnitude of this voltage spike is proportional to the resistance of the supply line. Accordingly, TTL gates generate noise themselves, and extra precautions should be taken to eliminate its adverse effect and use bypass capacitors throughout the system built with TTL gates to reduce the magnitude of the noise spikes.
3.13.2
The Buffer Gate with Open Collector Output
When the outputs of gates are connected together as shown in Fig. 3.21 (a), the load resistors in the gates are connected in parallel. Therefore, the total load resistance is reduced and the current ﬂowing through the switches is increased. While only one switch is closed, all of this current will ﬂow through that switch. If this current is large, it could damage the switch. Hence the number of outputs that can be connected together becomes limited. To provide the logic designer more ﬂexibility in connecting gate outputs, circuits are designed without an internal pullup resistor. This type of circuit is called opencollector gates for the bipolar transistors or opendrain gates for the unipolar transistors. In open collector, the collector of the output transistor is brought directly to the gate output terminal. To use this gate, an external load resistor must be connected between the output terminal and a positive voltage supply. Generally, the outputs of open collector TTL gates are tried together with a single external resistor and a wiredAND logic is performed. Figure 3.21.(c) shows the wired – logic graphic symbol to denote wired AND connections on logic diagram.
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Digital Logic Family
Fig. 3.21 (a) The output of connected inverter (b) Equivalent logic diagram (c) Wired – logic graphic symbol
While two inverter gates are connected together like the output of one inverter is used as the input of another, the circuit can be worked as a buffer. Due to the two stage inversion, ﬁnal output of buffer is same as input. The buffer circuits are used as signal ampliﬁers. A weak signal source may be boosted by means of two inverters connected in cascade. The logic level is unchanged, but the full currentsourcing or currentsinking capability of buffer is available to drive a load. An opencollector type buffer circuit is shown in Fig. 3.22. This circuit is similar with inverter. Only one difference is that it has one additional commonemitter transistor, which can reinvert the output signal.
Fig. 3.22
Buffer with open collector output
Fig. 3.23
Buffer with open collector output when input is VCC
When input is high +VCC as depicted in Fig. 3.23, no current ﬂow through the left steering diode of T1. The current ﬂows through resistance R1 and the base of transistor T2 so that transistor T2 operates in saturation. As T2 is saturated, T3 will also be saturated. Therefore, the voltage between the base and emitter of the transistor T4 is very small. Then transistor T4 operate in cutoff. The output of transistor T4 is high or +VCC. Thus, in buffer circuit, when the input voltage is high, output will be high. Similarly with a low input voltage, the output will be low. When input is low as shown in Fig. 3.24, current ﬂow through switch base emitter junction of transistor T1 and resistance R1. Consequently, no current will ﬂow through the base of T2 and transistor T2 operate in cutoff. Hence, no base current goes through T3 and T3 is also in cutoff condition. As T3 in cutoff, a current ﬂow through resistance R4 and base emitter junction of transistor T4. The output of transistor T4 is low. A buffer circuit with totem pole output transistor is shown in Fig. 3.25. The circuit operation is same as open collector circuit. Table 3.7 shows the truth table of buffer.
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Digital Electronics: Principles and Applications
Fig. 3.24
Buffer with open collector output when input is ground Table 3.7
Fig. 3.25
Buffer circuit with totem pole output
Truth table for buffer
Input A
T1
T2
T3
T4
Output O
Low
Saturation
Cutoff
Cutoff
Saturation
Low
High
Cutoff
Saturation
Saturation
Cutoff
High
3.13.3
Transistor
TTL NAND and AND Gates with Open Collector Output
Figure 3.26 shows the two inputs inverter circuit. The steering diodes marked as T1 is actually a transistor. The three pn junction diodes cannot be replaced by a simple npn transistor. Therefore, a different transistor is required. This transistor should have two emitters with one base and one collector. Figure 3.27 shows the multi emitter transistor based NAND gate. When both inputs are grounded as shown in Fig. 3.28(a), transistor T2 will be operated in cutoff mode. Then T3 is forced to operate in cutoff. The output of the transistor T3 is high. If one input terminal is grounded other terminal is connected with +VCC, transistor T2 is in cutoff. Then transistor T3 is also in cutoff and output will be high. But output is low when all inputs are high. Transistor T2 is turned on and operate in saturation. Then T3 is forced to operate in saturation. The truth table of two inputs NAND gate is given in Table 3.8.
Fig. 3.26
The two inputs inverter circuit
Fig. 3.27
The multiemitter transistor based NAND gate
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Digital Logic Family Table 3.8
Truth table for NAND gate
Input A
Transistor T2
Output O
B
T1
Low
Low
Saturation
Cutoff
Cutoff
High
Low
High
Saturation
Cutoff
Cutoff
High
High
Low
Saturation
Cutoff
Cutoff
High
High
High
Cutoff
Saturation
Saturation
Low
T3
Fig. 3.28 (a) The multiemitter transistor based NAND gate with both inputs grounded (b) The multiemitter transistor based NAND gate with one input high and other grounded
Fig. 3.28 (c) The multiemitter transistor based NAND gate with one input high and other grounded (d) The multiemitter transistor based NAND gate with both inputs high
An AND gate can be developed by using an NAND gate and an inverter to the output as shown in Fig. 3.29. However, the NAND function is actually the simplest, most natural mode of operation for this TTL design. To create an AND function using TTL circuitry, we should add an inverter at the output of TTL NAND gate and the complexity of the circuit increases. Table 3.9 shows the truth table of two inputs AND gate.
Fig. 3.29 AND gate with opencollector output
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Digital Electronics: Principles and Applications Table 3.9
Truth table for AND gate
Inputs A
Transistor B
T1
T2
T3
T4
Output O
Low
Low
Saturation
Cutoff
Cutoff
Saturation
Low
Low
High
Saturation
Cutoff
Cutoff
Saturation
Low
High
Low
Saturation
Cutoff
Cutoff
Saturation
Low
High
High
Cutoff
Saturation
Saturation
Cutoff
High
3.13.4
TTL NOR and OR Gates with Open Collector Output
Figure 3.30 shows a two inputs TTL NOR gate. Here, transistors T1 and T2 are connected in same manner. In this circuit both transistors T1 and T2 are used as two steering diode as shown in Fig. 3.31. When input A is connected with +Vcc, current will ﬂow through the base of transistor T3 with right steering diode of T1 and resistance R1. Then T3 is turned on and operate in saturating condition. Similarly, if input B is ground potential, current will ﬂow through left steering diode of T2 and resistance R2, no current will go through base of transistor T4. Therefore, transistor T4 is in cut off. In this circuit Transistors T3 and T4 are connected in parallel through resistance R3 and R4. If any one of the two transistors T3 and T4 is operated in saturation mode, current will ﬂow through resistance R3 and R4. As input A is high and input B is low, T3 is turned on and T4 is cutoff, current passes through resistance R3 and R4. A positive voltage is applied across the base of transistor T5 and a current a current ﬂow through base emitter junction of transistor T5. Hence, T5 is turned on and operate in saturation. Consequently the output of transistor T5 is low.
Fig. 3.30
NOR gate with open collector
Fig. 3.31
NOR gate with open collector
In the same way, if both inputs A and B are high, transistor T3 and T4 will be in saturation, and transistor T5 is also in saturation. Then output will be low. But the output of transistor T5 is only high when both inputs A and B are low. In this case, left steering diodes of T1 and T2 are conducting through resistance R1 and R2 respectively. No current goes through base of transistor T3 and T4. So T3 and T4 are in cutoff. Hence, no voltage is applied across base emitter junction of T5 and T5 is in cutoff. As a result, output will be high. Therefore, we can say that this circuit behaves as NOR gate. Table 3.10 shows the truth table of two inputs NOR gate.
95
Digital Logic Family Table 3.10 Truth table for NOR gate
Inputs
Transistor
Output
A
B
T1
T2
T3
T4
T5
O
Low
Low
Saturation
Saturation
Cutoff
Cutoff
Cutoff
High
Low
High
Saturation
Cutoff
Cutoff
Saturation
Saturation
Low
High
Low
Cutoff
Saturation
Saturation
Cutoff
Saturation
Low
High
High
Cutoff
Cutoff
Saturation
Saturation
Saturation
Low
An OR gate can be developed by adding an inverter to the output of the NOR gate as shown in Fig. 3.32. In this circuit, the output of 2 inputs NOR gate is inverted by using transistor T6. The truth table of two inputs OR gate is depicted in Table 3.11. The totempole output stages are also possible in both NOR and OR TTL logic circuits. But the outputswitching time will be increased in proportion to the number of load being driven.
Fig. 3.32 OR gate with open collector Table 3.11
Input
Truth table for OR gate
A
B
T1
T2
T5
T6
Output O
Low
Low
Saturation
Saturation
Cutoff
Cutoff
Cutoff
Saturation
Low
Low
High
Saturation
Cutoff
Cutoff
Saturation
Saturation
Cutoff
High
High
Low
Cutoff
Saturation
Saturation
Cutoff
Saturation
Cutoff
High
High
High
Cutoff
Cutoff
Saturation
Saturation
Saturation
Cutoff
High
3.13.5
Transistor T3 T4
TTL Gate with Tristate Output
All TTL gates have two output states: logic ‘0’ and logic ‘1’, but the tristate logic gates have three output states as given below: ∑ Low level state or logic ‘0’ state ∑ High level state or logic ‘1’ state ∑ High impedance state (Z). The graphic symbol of tristate logic gates are shown in Fig. 3.33. The tristate gate consists of an extra input terminal called enable or control input (C). When the control input is at logic ‘0’, the gate performs its normal Fig. 3.33 Gate symbols of tristate gates
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Digital Electronics: Principles and Applications
operation. If the control input is at logic ‘1’, the output of gate becomes tristate or high impedance state irrespective of inputs. In high impedance state, the gate is physically disconnected from its output terminal when C is at logic ‘1’ and the output appears as an open circuit.
Fig. 3.34
Tristate NAND gate
Table 3.12 Truth table for tristate NAND gate
Control input C 0 0 0 0 1
Fig. 3.35
3.14
Data input A
B
0 0 1 1 x
0 1 0 1 x
Output (O) 1 1 1 0 High impedance(Z)
Bus realisation using tristate gates
Figure 3.34 shows the tristate two inputs NAND gate. In this circuit, A and B are the inputs and C is used as control input. When control input (C) is HIGH or logic ‘1’, it works like any other NAND gate. But when control input (C) is LOW or logic ‘0’, T1 conducts, and the diode connecting between T1 emitter and T2 collector starts to conduct and driving T3 into cutoff. As T2 is not conducting, T4 is also at cutoff. When both pullup and pulldown transistors are not conducting, the output (O) is in highimpedance state (Z). The circuit operation is given in tabular form as depicted in Table 3.12. The outputs of two or more tristate gates can be directly wired together as illustrated in Fig. 3.35. In this circuit, C1 C2 …. CN are control inputs and D1 D2….. DN are data inputs and output is O. Assume that during operation at most one of them is not in the high impedance state. Certainly those gates are in the highimpedance state, they are effectively disconnected from the common point and they cannot affect the operation of any of the others in any way. Consequently, the activated gate controls the value of the common output line. Hence, tristate gates with their outputs wired together can be used as a bus. In fact, tristate gates were developed and are used almost exclusively for this application. The advantages of using tristate gates instead of opencollector gates are that more gates outputs can be wired together and bigger busses can be built. The tristate gates are faster as they have lower propagation delay.
CHARACTERISTICS OF TTL
Transistors are used to design TTL gates. During design of gates the limitations of transistors are considered to get proper performance. The performance parameters of TTL logic family are logic levels, source current, sink current, noisemargin, voltage transfer characteristics, fanin, fanout, power dissipation, and propagation delay. All these parameters are explained below:
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Digital Logic Family
3.14.1
Logic Levels
Figure 3.36 shows the inverter circuit. The output of an Inverter is logic ‘0’ when input voltage is low and logic ‘1’ if input voltage is high. According to manufacturers speciﬁcations of TTL ICs, low input voltage is varied between 0V and 0.8V. While input voltage is in this range, output of the inverter will be high, logical ‘1’. The low input voltage can be any value up to 0.8 V. In the data sheet of TTL ICs, the worstcase low input voltage is denoted as VILmax = 0.8 V. Figure 3.37 shows the positive logic level of TTL transistor. VILmax is the maximum allowable input voltage for a logic low level. Similarly, VIH is also the minimum allowable input voltage for a logic high level. If the input voltage exceeds VILmax, the output will be random value. In the same way, the input voltage between 5.0V to 2.0V is considered as high input voltage, VIH. When input voltage is varied in the above range, output will be low. The worstcase high input voltage is denoted as VIHmin = 2V.
Fig. 3.36
Inverter transistor circuit
Between the two levels, VIL and VIH, the transistor operates in the active region, output level is not specially determined. In this condition, the control on the transistor parameters is lost. This is called forbidden region. The difference between VIHmin and VILmax is called the Transition Width (TW). TW = VIHmin – VILmax = 2.0 – 0.8 = 1.2V In the same way, the output voltage of TTL ICs is not possible practically to achieve zero output voltage, 0V for the low output voltage Fig. 3.37 Input and output voltage proﬁle of TTL and 5.0V for the high output voltage. As per data sheet of TTL ICs, the low output voltage, VOL = 0.4V. VOH represent the high state output voltage and lies between 2.4V and 5V. The worstcase high output voltage is listed in data sheets as VOH = 2.4V. The worst case input and output voltages have been listed below: Maximum low input voltage Minimum high input voltage
VIL max VIH min
Maximum low output voltage
VOL max 0.4 V
Minimum high output voltage
VOH min 2.4 V
0.8 V 2.0 V
Logic Swing is deﬁned as the difference between the two output voltage levels. LS = VOH min – VOL max = 2.4 – 0.4 = 2.0V
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Digital Electronics: Principles and Applications
3.14.2
Voltage Transfer Characteristic
The voltagetransfer characteristic is one of the important properties of TTL devices. It is actually the relation between output voltage and input voltage under steady state conditions. Figure 3.38 shows the voltage transfer characteristics of TTL devices. The BP1 means breakpoint one and the BP2 means breakpoint two. At breakpoint BP1, input voltage is just at the point of turning on the transistor. But output voltage is still very close to the cutoff value and collector current is very small. At breakpoint, BP2, input voltage is sufﬁcient so that the transistor is at the edge of saturation region and collector current nearly at maximum value. Since any further increase in the input voltage results in hardly any change the output voltage. These breakpoints separate the following three regions of operation, namely Cutoff, AcFig. 3.38 Voltage transfer characteristive and Saturation. The coordinates of BP1 and BP2 are tics of TTL as follows BP1 Æ (VIL, VOH) and BP2 Æ (VIH, VOL) where,VIL input low voltage, maximum value of VIN to guarantee that VOUT = VOH VIH input high voltage, minimum value of VIN to guarantee that VOUT = VOL The TTL inverter circuit as shown in Fig. 3.36 has R1 = 10K, R2 = 1K, VBE(ON) = 0.7 V, VBE(SAT) = 0.8, and VCE(SAT) = 0.1 V. VOH is equivalent to VCE with the transistor at edge of cutoff region, and VOH is equal to VCC. VOL is equivalent to VCE with transistor at the edge of saturation region. In this example VCE(SAT) = 0.1V, and VOL = VCE(SAT). VIL is the input voltage at which transistor will be just turn on. In this example, VBE(ON) = 0.7 V, and VIL = VBE(ON). VIH is the input voltage, which is just sufﬁcient to saturate the transistor. When the transistor just at the Edge of Saturation (EOS), the collector current is given below: VCC  VCE (SAT ) I C ( EOS ) = R2 But also at the edge of the active region, IC = IC(EOS) IC(EOS) = hfeIB(EOS) The input VIH is determined by the following steps as given below: VIH  VBE (SAT ) I B ( EOS ) = R1 R VCC  VCE (SAT ) VIH = VBE (SAT ) + 1 ◊ R2 h fe VIH = 0.8 +
10 5  0.1 ◊ = 1.5V 1 70
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Digital Logic Family
The coordinates of BP1 and BP2 are VIN = 0.7V, VOUT = 5.0V and VIN = 1.5V, VOUT = 0.1V respectively.
3.14.3
Noise Margins
Various kinds of noise are always present in electronic circuits, which distort the output voltage of the gate. When output of one gate is used as input to another gate, it is very required to recognise ‘0’ and ‘1’ logic states, immunity to unwanted signal must be built into each gate in the form of noise margin. The noise margin low level (NML) is the difference between VOHmin and VIHmin and noise margin high level (NMH) is the difference between VILmax and VOLmax as given below: NML = VIL max – VOL max NMH = VOH min – VIH min = 2.4 – 2.0 = 0.4 V
3.14.4
= 0.8 – 0.4 = 0.4 V
FanOut
Fanout is the maximum number of TTL loads that can be connected to the output of a TTL driver circuit. Figure 3.39 shows that only one TTL load gate is connected to the output of a TTL transistor. Since the fan out of the driver T0 is one, 1. If there is no load at output of inverter, VOH of the inverter is VCC = + 5V and the High noise margin NMH = 3.5V. Figure 3.39 shows that only one load is present. VOH at VOUT is due to voltage divider action of R2 and R1. R1 VOH = VBE (SAT ) + (VCC  VBE (SAT ) ) R2 + R1 = 0.8 +
Fig. 3.39
Fanout of TTL circuit
10 (5.0  0.8) = 4.6V 1 + 10
In this way, when one load is connected to the TTL drive; VOH has been reduced from 5.0V to 4.6V. Therefore, NMH is also reduced and its value is NMH = VOH – VIH = 4.6 – 1.5 = 3.1V Subsequently, we can determine the maximum number of TTL load that can connect to the output of a TTL driver. To ﬁnd out the fan out, NMH is equal to 0. NMH = 0 ﬁVOH = VIH While T0 is off and N number of TTL load is connected with the TTL driver as depicted in Fig. 3.40. There are N base resistors R1 and all are connected in parallel to VBE(SAT). So we can write the expression for N number of TTL load.
Fig. 3.40
Fanout of TTL circuit
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Digital Electronics: Principles and Applications
VBE (SAT ) +
R1 N R (VCC  VBE (SAT ) ) = VBE (SAT ) + 1 R2 + R1 N R2
Ê VCC  VCE (SAT ) ˆ ˜ Á h fe Ë
After solving the above equation, the fan out can be determined. After substituting all know parameters in the above equation, we get N which may be integer or real number. As fractional loads are unfeasible, fanout always will be in round ﬁgure. To determine the maximum number of TTL load gates for the fanout, we always consider NMH = 0 and NMH is equal to NML.
3.14.5
Propagation Delay
When input to a gate changes suddenly, TTL gates response to the input signal and it takes ﬁnite time to change the output state. This is due to change the switch from cutoff state to saturation state or vice versa. This time delay is called the propagation delay. On the other hand, the switching times of the bipolar junction transistor is also known as propagation delay. This is calculated by carrying out analysis of the chargecontrol model of the BJT. The analysis of the switching sequences is explained here. While the input voltage is a rectangular pulse at time t0, it is considered that the input voltage changes suddenly from 0 to 5V. Initially, transistor was in the cutoff and output voltage is VCC, 5V.
Delay time(td ) When the input voltage suddenly changes at time t0, there is no change at the output until time t1. Here t1 is the time when output voltage start to decrease due to changes collector current. The delay is generated as the voltage across the emitter and collector junctions do not change instantaneously due to the junction capacitances at the depletion regions. The delay time (td) is determined from the difference between t1 and t0. It is (t1 – t0) as depicted in Fig. 3.41. Fall Time (tf ) Due to the junction capacitance effects, the output voltage decreases as depicted in Fig. 3.42. At time t2, the transistor is at the edge of saturation and output voltage of transistor is about VCE(sat) = 0.1V. The fall time can be determined from (t2 – t1).
Fig. 3.41 N TTL load connected to a TTL driver circuit
Fig. 3.42 Rise time, fall time, delay time and saturation time
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101
Saturation Time(ts ) It is clear from Fig. 3.42 that there is another step change in the input voltage from 5V to 0V at time t3. Though input voltage changes suddenly, output voltage does not change till t4 due to the removal of the overdrive charge from the base, or the base and collector regions. The saturation time is computed as (t4 – t3). Rise Time (tr ) Due to junction capacitance effects output voltage rises similar to fall time, and the transistor is now turning off. At time t5, the transistor is at the edge of cutoff. Consequently the output is VCC, 5V. The rise time is the difference between t5 and t4. The switching times namely delay, fall, saturation and rise time are required for digital circuit designer. But propagation delay is most important for designers. In a inverter circuit, the turnon delay time tPHL is calculated as the output is changing from a high voltage level to a low voltage level. t PHL = td +
tf 2
The turnoff delay time tPLH is computed as the output is changing from a low voltage level to a high voltage level. t PLH = ts +
tr 2
Thus, the average propagation delay time is deﬁned as tp =
3.14.6
t PHL + t PLH 2
Power Dissipation
In the data sheet of transistor, the speciﬁcation of power dissipation is represented by average power dissipation. The power dissipation rating of TTL gate is 10 mW per gate. In the active state, the output is continuously changing, power dissipation increases and it must be taken into account where heat dissipation and power supply ratings gets importance. Consider that the power dissipation is constant at constant output. When the output is low, T1 conducts. When the output is high, T1 does not conduct. This causes more current drain from the power supply per gate, when the output is low than when it is high. The power dissipation per gate is given below In the low state, 5V ¥ 3mA = 15 mW In the high state, 5V ¥ 1mA = 5mW If we assume that the gate is on and off for equal time periods, the total dissipation per gate will be as follows: Total dissipation: (15 + 5)/2 = 10mW.
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Digital Electronics: Principles and Applications
3.14.7
Fig. 3.43
The simpliﬁed gate circuit source current
Sourcing and Sinking Current
A TTL logic gate circuit has the ability to handle output current in two directions, namely in and out. Technically, this is called as sourcing and sinking current respectively. When the gate output is high, current will ﬂow through ground, load and VCC. This is represented in simpliﬁed form in Fig. 3.43.
In simpliﬁed form, the output of a gate circuit as being a doublethrow switch, capable of connecting the output terminal either to VCC or ground, depending on its state. For a gate outputting a high logic level, a doublethrow switch is in the VCC position, providing a path for current through a grounded load. A TTL logic gate is said to be sourcing current when it provides a path for current between the output terminal and the positive side of the DC power supply (VCC). In other words, it is connecting the output terminal to the power source (+V). Consequently, when a gate circuit is outputting a low logic level to a load, it is analogous to the doublethrow switch being set in the “ground” position. Current will then be going the other way if the load resistance connects to VCC.. In this condition, the gate is said to be sinking current as depicted in Fig. 3.44. A gate is said to be sinking current when it provides a path for current between the output terminal and ground. In other words, it is grounding (sinking) the Fig. 3.44 nchannel depletion–mode MOSFET output terminal. Table 3.13 shows the characteristics of a TTL. Table 3.13
Characteristics of TTL
Parameter
Value
VIH min
2.0V
VIL max
0.8V
VOH min
2.4
VOH max
0.4V
IIH
0.02mA
IIL
0.4mA
IOH
4mA
IOL
8mA
tPHL
10ns
tPLH
10ns
Pd
10mW
3.15 METAL OXIDE SEMICONDUCTOR FETS (MOSFET) CHARACTERISTICS The Field–Effect Transistor (FET) is a three terminal voltage controlled semiconductor device. The three leads of the FET are drain (D), source (S) and gate (G). The gate is used as input. The operation of FET depends on the ﬂow of only one type of carrier–either holes or electrons. The current ﬂow in the FET occurs between the source and drain. The path connection between the source and drain is called the channel. The FETs are classiﬁed into two categories: Junction FieldEffect Transistors (JFETs) and Metal Oxide Semiconductor FieldEffect Transistors (MOSFETs). The JFETs are used in linear circuits but the MOSFETs are employed in digital circuits.
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103
There are two types of MOSFETs : nchannel and pchannel. MOSFETs are also classiﬁed by the conducting state: depletion mode and enhancement mode. Actually the mode of operation depends on bias voltage. When the MOSFET is conducting with zero bias voltage, it is said to be a depletion mode device. If the device is not conducting with zero bias, the device will be known as enhancement–mode MOSFET. The name enhancement MOSFET is derived from the fact that a voltage is required on the gate to enhance or increase the current ﬂow in the channel. Similarly, the depletion MOSFET derives from the fact that a voltage on the gate is used to deplete or reduce the current ﬂow in the channel.
Fig. 3.45
The simpliﬁed gate circuit sinking current
The basic structure of an nchannel depletion–mode MOSFET is shown in Fig. 3.45. This device consists of two ntype regions diffused on a ptype substrate. The two heavily doped n–type regions are called the source and drain. The moderately doped ntype channel runs between source and drain. This channel is insulated from the gate by a layer of silicon oxide SiO2. Generally, the gate is constructed by a thin layer of aluminium located in the centre of the channel. When a positive voltage is applied to the drain and a negative voltage is applied to the gate, the channel will be appeared as shown in Fig. 3.46. The negative potential will attract holes from the ptype substrate and repel or neutralise the electrons in the moderately doped ntype channel. As the channel being depleted of carriers, subsequently the drain current will decrease.
As the gate of the MOSFET is electrically isolated from the channel, the device Fig. 3.46 Biasing of nchannel depletion–mode MOSFET can be able to operate with a positive gate to source voltage. If VGS increases, the number of free electrons ﬂowing through the channel increases. Consequently, the current ﬂow increases with increasing VGS. The drain curves of a typical nchannel depletion mode MOSFET are depicted in Fig. 3.47. These curves are formed by varying VGS to various positive as well as negative values and observing the relationship between VDS and ID for each value of VGS. The construction of an nchannel enhancement type MOSFET is shown in Fig. 3.48(a). The main difference between depletion and enhancement type MOSFET is that there is no channel in enhancement type MOSFET. The biasing arrangement of this MOSFET is given in Fig. 3.48(b). When VGS is increased, the conductivity of the
Fig. 3.47
Drain curves of nchannel depletion– mode MOSFET
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Digital Electronics: Principles and Applications
channel is enhanced and electrons are pulled into the substrate just below the layer of insulation under the gate. Ultimately, a channel is formed between the source and drain as the minority electron carriers are drawn from the substrate to the positive gate voltage. The amount of gate voltage required to develop a channel is called the threshold voltage (VTH). When the bias voltage is below the threshold voltage, current ﬂow stops. A negative bias voltage can generate cutoff in an enhancement–mode MOSFET. The schematic symbols of all MOS transistors are shown in Fig. 3.49.
Fig. 3.48 (a) nchannel enhancement –mode MOSFET (b) Biasing of nchannel enhancement –mode MOSFET
Fig. 3.49
Symbols of MOS transistors (a) nchannel depletion type (b) pchannel depletion type (c) nchannel enhancement type (d) pchannel enhancement type
MetalOxideSemiconductors (MOS) are extensively used in digital electronics circuits due to the following advantages: (i) MOS requires less space than BJT for fabrication a silicon chip (ii) High input resistance (iii) Very low power consumption (iv) MOS logic family is compatible with BJT due to matching voltage levels. (v) Very economical (vi) Few steps are required for MOS fabrication process (vii) MOS circuit’s speed is very high due to reduction of internal dimension of devices (viii) Dynamic circuit techniques are used in MOS technology. Therefore less number of transistors is required to implement a given circuit. (ix) Presently local oxidation technique is used to increase circuit density and to improve circuit performance. The MOS logic has three categories such as
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105
P Channel MOSFETs , PMOS N Channel MOSFETs, NMOS Complementary MOSFETs, CMOS Pchannel MOSFET becomes obsolete. Nowadays, N channel MOSFETs are very popular due to high speed. An nchannel MOS consists of a lightly doped ntype silicon substrate . The source and drain are formed by diffusion with ptype impurities. The region between two ptype impurities namely source and drain acts as a channel. This device operates in enhanced and depletion mode. The mode of operation depends on the state of the channel region. An nchannel enhancement MOSFET requires a positive gate voltage for conduction. Figure 3.50 shows the symbols of MOS devices. If VGS and VGD are less than threshold voltage, VTH, the Fig. 3.50 (a) pchannel MOS and device operates in cutoff and no current ﬂows from drain (b) nchannel MOS to source as depicted in Fig. 3.51(a). When VGS is greater than threshold voltage, VTH, the device is ON and operates in saturation. Therefore, current ﬂows from Drain to Source as shown in Fig. 3.51(b).
Fig. 3.51 (a) MOS in cutoff (b) MOS in saturation
3.15.1
MOS Inverter
The MOS inverter circuit can be classiﬁed into static and dynamic circuits. This classiﬁcation depends on the requirement of periodic clock pulse. If there is no requirement of periodic clock pulse for operating a combinational logic circuit, this circuit is called static circuit. On the other hand, dynamic circuits require periodic clock pulse for operation in combinational logic circuits. Figure 3.52 shows a MOSFET inverter circuit with a passive resistive load RD. If the input voltage is HIGH, MOSFET will be ON and output voltage will be LOW. Similarly if input is reversed, output will be HIGH. In contrast to TTL technology, linear resistors are used as pullup element in an inverter. In MOSFET technology, MOSFET fabrication is easier than a resistor and it requires twenty times less space. Therefore, another MOSFET can be used in place of load resistance as shown in Fig. 3.53. As gate of the MOSFET, T2 is connected with the drain, the MOSFET, T2 is always conducting and it acts as a resistance. During design process, the resistance of MOSFET, T2 is ten times greater than MOSFET, T1. Consequently,
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Digital Electronics: Principles and Applications
MOSFET, T2 behaves as a resistance and MOSFET, T1 acts as a switch. To provide greater current, the pulldown devices are ﬁrst turned off and a capacitive load must be charged as shown in Fig. 3.52(b).
Fig. 3.52
Fig. 3.53
MOS Inverter
3.15.2
MOS Inverter
NMOS NAND Gate
Figure 3.54 shows the two inputs MOS NAND gate. If one input or both inputs are LOW, the corresponding MOS is OFF. Then voltage across T3 is zero and output is Vdd. If both inputs are high, T1 and T2 are ON and output will be low. Table 3.14 shows the truth table of a NAND gate. Table 3.14
Truth table for two inputs MOS NAND gate
Inputs A Fig. 3.54
3.15.3
Two inputs NAND gate
Transistors T1 T2
B
Output O
Low
Low
Cutoff
Cutoff
High
Low
High
Cutoff
Saturation
High
High
Low
Saturation
Cutoff
High
High
High
Saturation
Saturation
Low
NMOS NOR Gate
The two inputs NOR gate is depicted in Fig. 3.55. If any one input is HIGH or both inputs are HIGH, the corresponding transistors are ON and output is LOW. When both transistors T1 and T2 are OFF, output is low. The truth table of NOR gate is shown in Table 3.15. Table 3.15
Truth table for two inputs MOS NOR gate
Inputs
Fig. 3.55 Two Inputs NOR gate
Transistors T1 T2
Output O
A
B
Low
Low
Cutoff
Cutoff
High
Low High High
High Low High
Cutoff Saturation Saturation
Saturation Cutoff Saturation
Low Low Low
Digital Logic Family
107
3.16 MOS CHARACTERISTICS The MOS logic families have slow operating speed; have a better noise margin, a greater supply voltage range, and a higher fanout compared to the TTL logic families. The MOS devices require less space in ICs and consume small power with respect to TTL. The some basic characteristics are explained below:
Fan Out Due to very high input impedance, MOS devices have large fan out. But increasing with no of MOS gates, the capacitance will be increased at the output. Therefore, the speed of MOS is reduced. NMOS devices are directly interfaceable with TTL devices as voltage and current parameters of MOS are similar with TTL. Operating Speed The MOS devices have relatively high output resistance and the capacitive loading is also present when the inputs of the logic circuits drive the devices. MOS logic inputs have very high input resistance, subsequently, this logic inputs have a reasonably high input capacitance called MOS capacitor. The MOS capacitor varies in between 2 to 5 picofarads. Actually, capacitance is charged and discharged through resistance. The switching speed of MOS devices depends on the rate of charge and discharge of capacitance. Therefore, switching time increases due to large output resistance and large capacitance. Power Dissipation The power dissipation of MOS logic circuits is very small. So this logic circuit can be very useful for LargeScale Integration (LSI) and Very Large Scale Integration (VLSI) ICs. During the design of ICs, the power consumption should be minimum. As 10,000 or more gates can be easily placed in a LSI IC, average power consumption per gate of LSI IC should be less than 100mW. Propagation Delay A large capacitance is present at input and output of MOS devices. The propagation delay is large due to capacitance. For a NMOS NAND gate, the propagation delay time is approximately 50 ns. Noise Margin Typically, NMOS noise margins are around 1.5V when operated from Vdd = 5 V and will be proportionally higher for larger values of Vdd.
3.17 CMOS GATES CMOS is most widely used digital circuit technology in comparison to other logic families. This logic family has the following advantages: lowest power dissipation and highest packing density. Virtually, allmodern microprocessors are manufactured in CMOS and older versions are now reprocessed in CMOS technology. Complementary MOS (CMOS) Inverter analysis makes use of both NMOS and PMOS transistors in the same logic gate. All static parameters of CMOS inverters are superior to those of NMOS inverters. Price paid for these substantial improvements and increased process complexity to provide isolated transistors of both polarity types. The logic level operation of NMOS and PMOS are given below: logic 1(Positive VGS)
turns on an NMOS turns off a PMOS
logic 0
turns off an NMOS turns on a PMOS
Thus, for the output high and low states both devices are never ON simultaneously. NMOS acts as the output transistor and the PMOS acts as the load transistor. The output pullup and pulldown paths never conﬂict during operation of the CMOS inverter. By connecting, the complementary transistors as shown in Fig. 3.56, can work as an inverter. VGS is needed to enable the DrainSource current channel.
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Digital Electronics: Principles and Applications
NMOS enhancementmode transistor is the lower T1 and PMOS enhancementmode transistor is the upper T2. Gates of both NMOS and PMOS are connected together. Drains are also connected together. One transistor can be considered as load for the other. Here, T1 will be act as the load for T2 in the PMOS inverter. Similarly, T2 can be considered as the load on the NMOS inverting transistor. The operation of T1 and T2 is complementing each other. The output of a CMOS inverter does reduce all the way to 0V. Since output can range from 0 volts to VDD, output is said to railtorail.
3.17.1
CMOS Inverter
Two complementary MOSFETs, namely, pchannel MOSFET (PMOS) and nchannel MOSFET (NMOS) are connected in such a way that the circuit behaves as inverter. Figure 3.56 shows the complementary CMOS inverter. The drains are joined together. Vdd is connected with source of PMOS and source of NMOS is also connected with ground. Figure 3.57(a) shows the operation of CMOS inverter when input is connected with low voltage (logic 0). Fig. 3.57 (a) Complementary CMOS When input voltage is low, Fig. 3.56 Complementary inverter circuit with input ground the NMOS will be cutoff MOS inverter and PMOS will be operTable 3.16 The truth table of CMOS ating in saturation mode. inverter Then output will be Vdd. Similarly, when input voltage is Input Transistor Output high, PMOS will be in cutoff and NMOS operate in saturation. Therefore, the output voltage will be almost zero volt. In A T1 T2 O this way, this circuit beLow Cutoff Saturation High haves as inverter. Table High Saturation Cutoff low 3.16 shows the truth table of CMOS inverter. The transistor T2 is a Pchannel MOSFET. When the channel is more positive than the gate, the channel is enhanced and current is allowed between source and drain. Therefore, the upper transistor T2 is turned on. The transistor T1, having zero voltage between gate and source, is in its cutoff mode. Thus, the actions of these two transistors are such that the output terminal of the gate circuit has a solid connection to Vdd and a very high resistance connection to ground. This makes the output high or logic 1 for the low or logic 0 state of the input. Similarly, when the input is +VCC, the operation of the circuit is depicted in Fig. 3.57(b). The transistor T1 is saturated as it has
Fig. 3.57 (b) Complementary CMOS inverter circuit when input connected to VCC
Digital Logic Family
109
sufﬁcient voltage of the correct polarity applied between gate and substrate to turn it on due to positive on gate, and negative on the channel. The transistor T2, having zero voltage applied between its gate and substrate, is in its cutoff mode. Thus, the output of this gate circuit is now “low” or logical ‘0’. Clearly, this circuit exhibits the behaviour of an inverter, or NOT gate. The multipleinput CMOS gates such as AND, NAND, OR, and NOR are also explained in the next section.
3.17.2
CMOS NAND and AND GATE
Figure 3.58 shows the two inputs CMOS NAND gate. The two pchannel MOSFETs namely T1 and T2 are connected in parallel. Two nchannel MOSFETs T3 and T4 are connected in series. It can be noticed that transistors T1 and T3 are in series connected complementary pair and form an inverter circuit. These transistors are controlled by input signal A. When the input Fig. 3.58 CMOS NAND is high, the transistor T1 is cutoff and transistor T3 is ON. On the other gate hand, when input is low, T1 is ON and T3 is OFF. Similarly, transistors T2 and T4 are controlled by the same input signal (input B), and they will also exhibit the same ON/OFF behaviour for the same input logic levels. The following sequence of switching shows the behaviour of this NAND gate for all four possibilities of input logic levels (00, 01, 10, and 11) in Fig. 3.59 (a), (b), (c) and (d) respectively. Table 3.17 shows the truth table for two inputs CMOS NAND gate.
Fig. 3.59
(a) CMOS NAND gate with both inputs grounded (b) CMOS NAND gate when one input grounded and other connected with Vdd (c) CMOS NAND gate when one input grounded and other connected with Vdd (d ) CMOS NAND gate when both inputs connected with Vdd
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Digital Electronics: Principles and Applications
The CMOS NAND gate circuit can be used as an AND gate by inverting the output of NAND gate. For this, one inverter circuit is connected after NAND gate. Figure 3.59 shows the two input CMOS AND gate and the truth table of CMOS AND gate is illustrated in Table 3.18.
3.17.3
CMOS NOR and OR GATE
Figure 3.61 shows two inputs CMOS NOR gate. Transistors T1 and T3 work as a complementary pair, as do transistors T2 and T4. Each pair is controlled by a single input signal. When input A or input B are high (1), at least one of the transistors (T3 or T4) will be saturated, thus the output will Fig. 3.60 CMOS AND gate be low (0). Only in the event of both inputs being low (0), both lower transistors will be in cutoff mode and both upper transistors be saturated, the conditions necessary for the output to go high (1). This behaviour, of course, deﬁnes the NOR logic function. Table 3.19 shows the truth table of two inputs CMOS NOR gate. Table 3.17
Inputs A B
Fig. 3.61
Two inputs CMOS NOR gate
Truth table for two inputs CMOS NAND gate
Transistors T2 T3
T1
Low Low Saturation Saturation Low High Saturation Cutoff High Low Cutoff Saturation High High Cutoff Cutoff
Cutoff Cutoff Saturation Saturation
T4
Output O
Cutoff Saturation Cutoff Saturation
High High High Low
Table 3.18 Truth table for two input CMOS AND gate
Inputs A B Low Low High High
T1
T2
Transistors T3 T4
Low Saturation Saturation Cutoff High Saturation Cutoff Cutoff Low Cutoff Saturation Saturation High Cutoff Cutoff Saturation
Cutoff Saturation Cutoff Saturation
T5
T6
Cutoff Saturation Cutoff Saturation Cutoff Saturation Saturation Cutoff
Output O Low Low Low High
Table 3.19 Truth table for two inputs CMOS NOR gate
Inputs
Transistors T3
A
B
T1
T2
Low Low High High
Low High Low High
Cutoff Cutoff Saturation Saturation
Cutoff Saturation Cutoff Saturation
Cutoff Cutoff Saturation Saturation
T4
Output O
Cutoff Saturation Cutoff Saturation
High Low Low Low
The OR function can be built up from the basic NOR gate and an inverter on the output of NOR gate. Figure 3.62 shows the two inputs CMOS OR gate. The truth table of two inputs CMOS OR gate is depicted in Table 3.20.
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Digital Logic Family
Fig. 3.62 Two inputs CMOS OR gate Table 3.20
Truth table for two inputs CMOS OR gate
Inputs
Transistors T3 T4
A
B
T1
T2
T5
T6
Output O
Low
Low
Cutoff
Cutoff
Cutoff
Cutoff
Cutoff
Saturation
Low
Low
High
Cutoff
Saturation
Cutoff
Saturation
Saturation
Cutoff
High
High
Low
Saturation
Cutoff
Saturation
Cutoff
Saturation
Cutoff
High
High
High
Saturation
Saturation
Saturation
Saturation
Saturation
Cutoff
High
3.18 CMOS CHARACTERISTICS The basic performance parameters are same for TTL and CMOS. So, the CMOS parameters are logic levels, source current and sink current, noisemargin, fanin, Table 3.21 Characteristics of CMOS fanout, power dissipation, and propagation delay. Table 3.21 shows the CMOS characteristics. The characteristics of CMOS Parameter Value are different from TTL as values of parameters are different. 3.5V VIH min All these parameters are explained in this section. 1.5V V IL max
3.18.1
Logic Levels
According to manufacturers speciﬁcations of CMOS ICs, low input voltage is varied between 0V and 1.5V. In the data sheet of CMOS ICs, the worstcase low input voltage is denoted as VIL max =1.5V. VIL max is the maximum allowable input voltage for low logic level. In the same way, VIH min is also the minimum allowable input voltage for high logic level. The worstcase high input voltage is denoted as VIH min = 3.5V. The high input voltage of CMOS varies in the range 3.5V to 5V.
VOH min
4.9V
VOH max
0.1V
IIH
1µA
IIL
–1µA
IOH
–100µA
IOL
360µA
tPHL
60ns
tPLH
45ns
Pd
10nW
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Digital Electronics: Principles and Applications
When input voltage varies in between the two levels VIL max and VIH min, the CMOS transistor operates in the active region and output level is not specially determined. In this case, there is no control on the transistor parameters. The difference between VIH min and VIL max is called the Transition Width (TW). TW = VIH min – VIL max = 3.5 – 1.5 = 2V On the other hand, the low output voltage of CMOS, VOL varies in 0 to 0.1V, and the maximum low state output voltage is VOL max= 0.1 V. VOH represent the high state output voltage and lies between 4.9 V and 5 V. The worstcase high output voltage, VOH min =4.9 V according to data sheet of CMOS. Figure 3.62 shows the input and output voltage proﬁle of CMOS. The worst case input and output voltages have been listed below: Maximum low input voltage
VILmax
1.5 V
Minimum high input voltage
VIH min
3.5 V
Maximum low output voltage
VOL max
0.1 V
Minimum high output voltage
VOH min
4.9 V
The Logic Swing (LS) of CMOS can be determined from the difference between the two output voltage levels as given below LS = VOH min – VOL max = 4.9 – 0.1 = 4.8V
3.18.2
Noise Margins
The low level noise margin (NML) is the difference between VOH max and VIH min and high level noise margin (NMH) is the difference between VIL min and VOL min as given below: NMH = VOH min – VH min = 4.9 – 3.5 = 1.4 V
NML = VIL max – VOL max = 1.5 – 0.1 = 1.4 V
In general, the CMOS devices have greater noise margins than TTL. The noise margin would be more if the CMOS devices were operated at a supply voltage greater than 5V.
3.18.3
FanOut and Fan In
Fanout is the maximum number of CMOS logic gates that can be driven by a single CMOS logic gate. The fanout of CMOS varies in the range of 20 to 50 depending upon the operating condition. Fanin means the maximum number of inputs for a CMOS gate and this is limited by technological factors. The fanin of CMOS lies between 2 to 8.
3.18.4
Propagation Delay
The propagation delay of CMOS ICs generally varies in between about 20ns to 100ns. As compared to TTL ICs, CMOS ICs have more propagation delay. When CMOS ICs are connected in cascade form, the propagation delay will be increased. If the CMOS operates at high supply voltage and low load capacitance, switching speed of CMOS increases signiﬁcantly.
3.18.5
Power Dissipation
In the data sheet of CMOS transistor, the speciﬁcation of power dissipation is represented by average power dissipation. The power dissipation of a CMOS gate is about 10nW. When the frequency
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Digital Logic Family
of input signal increases, CMOS gate dissipates more power. However, CMOS gates draw transient current during every change of output state, from low to high and high to low. Therefore, CMOS ICs have greater power dissipation at greater frequencies. At 1 MHZ, the power dissipation is approximately 1mW.
3.18.6
Sourcing and Sinking Current
Just like TTL ICs, CMOS ICs also have source and sink current. The source and sink current of CMOS are very small compared to TTL. Figure 3.63 illustrates a CMOS driver interface with a CMOS inverter load. While the output of CMOS driver is low, the driver sinks a current about 1µA. The CMOS driver can source a current Fig. 3.63 Input and output voltage proﬁle of CMOS about 1µA when the output of CMOS driver is high as depicted in Fig. 3.65. IILmax is the current, which is ﬂowing out of the load when the driver output is low and it has a negative sign. Similarly, if the driver output is high, IIH max is the current, which is ﬂowing into the load and it has positive sign.
Fig. 3.64
CMOS driver sinks a current from a CMOS load
Fig. 3.65
CMOS driver source a current to a CMOS load
3.19 INTERFACING TTL AND CMOS LOGIC FAMILY To design a complex digital electronics circuit, designer use devices of two different logic families or same logic family. Therefore, there are two types of devices namely driving and loading devices existing in any circuit. The driving device is connected to the loading device. For proper interface, the output characteristic of the driving device should match with the input characteristic of loading device. If they are not properly matched, an interfacing problem will arise between driving and loading devices. So output will not be the desired output. To get desired output, some external circuit is connected in between two devices. TTL and CMOS logic families are most commonly used in digital circuits. Therefore, interfacing on TTL to TTL, CMOS to CMOS, TTL to CMOS and CMOS to TTL are given below.
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Digital Electronics: Principles and Applications
3.19.1 TTL to TTL The output and input voltage proﬁles of TTL devices are shown in Fig. 3.66. The output and input voltage levels of TTL are VOH min= 2.4V, VOL max = 0.4V, VIH min = 2V, and VIL max = 0.8V. The VOH min is greater than VIL min and VOLmax is less than VIL max. Therefore, output voltage levels VOH V fall within the acceptable input voltage levels min, OL max VIH min and VIL max. Consequently, there is no interfacing problem between two TTL devices and a TTL driver can be connected directly with a TTL load. Fig. 3.66 (a) Output voltage proﬁle of TTL (b) Input voltage proﬁle of TTL
3.19.2
CMOS to CMOS
Figure 3.67 shows the output and input voltage proﬁles of CMOS devices. The output and input voltage levels of CMOS are VOH min = 4.9V, VOL max = 0.1V, VIH min = 3.5V, and VIL max = 1.5V. In CMOS the VOH min is greater than VIL min and VOL max is less than VIL max. So, CMOS output voltage levels (VOH min, VOL ) fall within the acceptable input voltage levels max (VIH min ,VIL max) of CMOS. Accordingly, there will not be any interfacing problem between two CMOS ICs. Therefore, a CMOS driver can be connected directly Fig. 3.67 (a) Output voltage proﬁle of CMOS (b) Input voltage proﬁle of CMOS with a CMOS load.
3.19.3
TTL to CMOS
The output voltage proﬁles of TTL and input voltage proﬁles of CMOS devices are depicted in Fig. 3.68. The output and input voltage levels of TTL and CMOS are VOH min = 2.4V, VOL max = 0.4V, VIH min = 3.5V, and VIL max = 1.5V repectively. If the TTL output is low, the maximum output voltage of TTL, VOL max is 0.4V. As VOL max is less than VIL max, it is suitable for a CMOS load. When the TTL output is high, the maximum output voltage of TTL, VOH min is 2.4V, which is not acceptable for a CMOS load as VOH min is less than VIH min. Therefore, high state output voltage level of a TTL is not sufﬁcient/compatible to drive a CMOS load. Consequently, there is an interfacing problem between TTL and CMOS ICs , when two types Fig. 3.68 (a) Output voltage proﬁle of TTL of ICs are used in same system. (b) Input voltage proﬁle of CMOS
115
Digital Logic Family
For example a TTL NAND gate output is fetched to a CMOS Inverter as shown in Fig. 3.69. Both gates are powered by the 5V power supply. When TTL gate output is low (0 to 0.4V), it will be accurately recognised by the CMOS gate as a low (0 to 1.5V). If the TTL gate output is high (2.4 to 5V), it will not be accurately recognised by the CMOS gate as a high (3.5 to 5V). Due to different voltage levels, there is some mismatch. Therefore, the output of a TTL falls with in the unacceptable range of the CMOS input and it will be accepted as low. The problem can be solved by connecting a pullup resistance at output of TTL as shown in Fig. 3.70 and Fig. 3.71. Fig. 3.69 Interfacing a TTL driver Sometimes, it is required to interface a TTL IC with a CMOS IC when CMOS IC is powered by a greater voltage as depicted
Fig. 3.70
Interfacing a TTL driver and a CMOS load with pullup resistance
Fig. 3.71
and a CMOS load
(a) Output voltage proﬁle of TTL with pullup resistance (b) Input voltage proﬁle of CMOS
in Fig. 3.72. In this case, the CMOS can able to recognise the both low and high output as low because the high state output voltage level (2.4V to 5V) is less than the high state input voltage of CMOS (7V to 10V). So, a pullup resistance is connected in between output of TTL and Vdd as shown in Fig. 3.73 to increase the TTL high state output voltage to full power supply voltage.
Fig. 3.72
Interfacing a TTL driver and a CMOS load at different power supply
Fig. 3.73
Interfacing a TTL driver and a CMOS load with pullup resistance at different power supply
116
3.19.4
Digital Electronics: Principles and Applications
CMOS to TTL
During interfacing between CMOS andTTLdevices, we take into account the limiting values of output voltage and current of CMOS (VOH min, VOL max, IOH max, IOL min) and the input voltage and current of TTL (VOH min, VOL max, IOH max, IOL min). The voltage and current proﬁles of CMOS are VOH min = 4.9V, VOL max = 0.1V, IOH max = –360µA, and IOL min = 360µA. Similarly, limiting values of voltage and current of TTL are VOH min= 2V, VOL max = 0.8V, IOH max= 40µA, and IOL min = –1.6mA. Figure 3.74 shows the output and input voltage proﬁle of CMOS and TTL respectively. As output voltage levels of CMOS driver (VOH min, VOL max ) fall within the acceptable range of TTL input voltage levels (VIH min and VIL max), there is no interfacing problem connecting a CMOS output to a TTL load input. But the only signiﬁcant issue is that the current loading of TTL inputs is present and the CMOS output must sink current for each of the TTL inputs in the low state. CMOS gate gives better performance, when it is operated at voltage around 9 to 12V. Therefore, to get best performance CMOS operates in at 10V but TTL operates at 5V. When CMOS gate is connected with 10V power supply, the interfacing problem will arise. The high output state of CMOS gate is greater than 5V, which exceed the acceptable high input voltage level of TTL. This problem can be solved by adding an open collector inverter using NPN transistor at the output of CMOS as depicted in Fig. 3.75. The Rpullup resistance is optional, as TTL inputs presume a high state. But one important fact that inverted output of CMOS is used as input of TTL. When the CMOS output is low, the TTL gets a high input signal. While the CMOS output is high, the TTL gets a low input signal.
3.20
ADVANTAGES AND DISADVANTAGES OF CMOS OVER TTL
Since it appears that any gate possible to construct using TTL technology can be duplicated in CMOS, why do these two “families” of logic design still coexist? The answer is that both TTL and CMOS have their own unique advantages. A CMOS consist of a NMOS and a PMOS transistor. The complementary P and N channel MOSFET pairs of a CMOS are never conduct simultaneously. So, the CMOS gate draws very little current from the Vdd power supply. Therefore, power dissipation of CMOS is very small in the range of nW. On the other hand, TTL always draw some current from supply, as the bias current is required to operate the bipolar transistors. The range of power dissipation of TTL is mW.
Fig. 3.74 (a) Output voltage proﬁle of CMOS (b) Input voltage proﬁle of TTL
Fig. 3.75 Interfacing a CMOS driver and a TTL load at different power supply
Digital Logic Family
117
The power dissipation of a TTL device remains somewhat constant at different operating conditions. However, the power dissipation of a CMOS device depends on the operating frequency. If the frequency of input signal increases, the CMOS devices dissipate more power. When a CMOS operates in a static condition, it dissipates approximately zero power. As a CMOS gate also draws much less current from a driving gate output than a TTL gate because MOSFETs are voltagecontrolled, not currentcontrolled, devices; this means that one gate can drive many more CMOS inputs than TTL inputs. The measure of how many gate inputs a single gate output can drive is called fanout. Another advantage of CMOS is that CMOS ICs can operate in wide range of power supply voltages than TTL gate. The disadvantage of CMOS is slow speed, as compared to TTL. As the input capacitances of a CMOS gate are greater than the input capacitances of TTL, the RC time constant developed by CMOS logic circuit resistances will be more. As a result, CMOS ICs are operated in slow speed.
SUMMARY In this chapter, the classification of digital logic family is explained. The operation of different logic families, namely DTL, TTL, ECL, and CMOS are discussed with circuit diagrams. The characteristics of digital logic family are incorporated for better understanding of TTL, MOS and CMOS logic gates. TTL inverter, buffer, NAND, AND, NOR and OR gates are explained with the help of truth table and circuit diagrams. An inverter is one that output is the opposite of input. If input is ‘low’ output is ‘high’. When two inverter gates connected in ‘series’, input is inverted two times, so that buffer output is same as input. Buffer gates are commonly used to amplify weak signal before driving a load. Taking a TTL inverter circuit and adding another input we could build a TTL NAND gate. An AND gate may be developed by adding an inverter gate to the output of the NAND gate. An OR gate can also be formed after addition of an inverter at the output of the NOR gate. The MOS inverter, NAND and NOR gate are explained in this chapter. CMOS logic gates are made using complementary transistors namely NMOS and PMOS. CMOS inverter, NAND, AND, NOR and OR gates are also discussed in this chapter. The characteristics of TTL, MOS and CMOS are explained briefly to understand the applications of TTL, MOS, and CMOS logic families in digital systems. The interfacing of TTL and CMOS is also enlightened in this chapter.
MULTIPLE CHOICE QUESTIONS 1. 2. 3. 4. 5.
Which of the following range is used as low level (logic 0) input voltage in TTL circuit? (a) 0.4V – 1.2V (b) 0V – 0.8V (c) 0.8V – 2.4V (d) 1V – 2.4V Which of the following range is used as high level (logic 1) input voltage in TTL circuit? (a) 2V – 5V (b) 0.8V – 5V (c) 0.8V – 2.4V (d) 1V – 5V Which of the following range is used as low level (logic 0) input voltage in CMOS circuit? (a) 0V – 1.5V (b) 0.8V – 2V (c) 0.8V – 2.4V (d) 1V – 2.4V Which of the following logic family is fastest of all? (a) TTL (b) RTL (c) DCTL (d) ECL Which of the following technology is used for microprocessors? (a) CMOS (b) NMOS (c) PMOS (d) None of these
118 6. 7. 8. 9. 10. 11. 12. 13.
14. 15.
16. 17.
18. 19. 20. 21.
Digital Electronics: Principles and Applications Which of the following logic family is most widely used? (a) TTL (b) DTL (c) ECL (d) None of these Which of the following logic family consumed least power? (a) TTL (b) RTL (c) DCTL (d) ECL Which of the following MOS logic family is used in LSI technology? (a) NMOS (b) PMOS (c) CMOS (d) None of these The propagation delay of TTL is (a) 10ns (b) 120ns (c) 200ns (d) None of these What is the fanout of TTL devices? (a) 2 (b) 4 (c) 6 (d) 10 Which of the following devices have 200 gates (a) SSI (b) MSI (c) LSI (d) VLSI A gate can drive the number of similar gates that is known as (a) Fan in (b) Fan out (c) Shinking current (d) Propagation delay CMOS stands for (a) Charged Metal Oxide Switch (b) Complementary Metal Oxide Semiconductor (c) Complementary Metal Oxide Switch (d) None of these What will be the power consumption of CMOS circuits if frequency increases? (a) Increases (b) Decreases (c) Same (d) None of these A tristate logic gate has three output states. They are (a) High, Low, Open circuit (high impedance) (c) High, Low, Saturated (b) High, Low, Short circuit (d) None of these Which of the following logic family consumes the least power in static state? (a) TTL (b) ECL (c) CMOS (d) I2L What are the three basic modes of operation of a transistor? (a) Saturated, cutoff, active (c) open, closed, off (b) High, low, opencircuit (d) None of these Noise margin of TTL is (a) 0.4V (b) 2V (c) 3V (d) 1.5V Noise margin of CMOS is (a) 1.4V (b) 2.4V (c) 3.4V (d) 4.4V The power dissipation of a CMOS is approximately (a) 10nW (b) 20nW (c) 30nw (d) None of these What are the three basic parameters for selecting digital logic family? (a) Speed, cost, power consumption (b) Speed, size, power consumption (c) Speed, size, propagation delay (d) None of these
Digital Logic Family
119
REVIEW QUESTIONS 3.1 3.2 3.3
What are the types of digital logic family? Explain brieﬂy any one logic family with circuit diagram. Draw the circuit diagram of DCTL to perform logical AND and explain brieﬂy the operation of circuit. Determine fan out of transistor T0 as shown in Fig. 3.76. Consider VCC = 5V, R = 12K, IB = 0.15mA for saturation.
Fig. 3.76
3.4.
Determine IB1, IB2, IC1 and IC2 for the transistor T1 and T2 as depicted in Fig. 3.77. Consider R1 = R2 = 1.5, R = 4.7K, VCC = 5V, hfe = 50, and VCE = 0.2V.
3.5.
Determine the rise time of a RTL circuit as depicted in Fig. 3.78. Consider R1 = 450 ohms , R = 640 ohms, C = 5pF, N = 10.
Fig. 3.77
Fig. 3.78
120 3.6.
Digital Electronics: Principles and Applications Determine the current through diode D1 as shown in Fig. 3.79. Consider RB = RC = 1.5K, R = 4.7K V1 = 0.2V and VD1 = 0.7V.
Fig. 3.79
3.7.
Write the truth table of the DTL circuit as depicted in Fig. 3.80.
Fig. 3.80
3.8.
Determine the voltage V1 in a HTL NAND gate for the following conditions: i. ii.
T1 begins to come out of cutoff T2 operates at the edge of saturation
Consider R1 = 3K, R2 = 10K, R3 = 5K, R4 = 10K, VZ = 6.8V, VCC = 12V. Assume all necessary parameters.
Digital Logic Family
Fig. 3.81
3.9. 3.10. 3.11. 3.12. 3.13. 3.14. 3.15.
3.16. 3.17.
3.18. 3.19.
3.20.
HTL NAND Gate
Explain the operation CMOS NAND gate with circuit diagram. Give a list for the characteristics of TTL logic family. Give a list for the characteristics of CMOS logic family and compare with TTL logic family. Draw a circuit diagram of TTL NAND gate and explain its operation. Deﬁne propagation delay, noise margin and fanout. Draw the circuit diagram CMOS NOR gate and explain with truth table. Explain interfacing of two logic families for the following conditions: i. TTL driving CMOS logic family ii. CMOS driving TTL logic family Table 3.22 What is noise margin? Explain the effect of noise margin in operation of logic family. Parameter Value How a TTL device can interface with CMOS device 2.0V VIH min when TTL is connected with 5V and CMOS is con0.7V VIL max nected with 12V? 2.4V V The speciﬁcation of TTL gate is given in Table 3.22. OH min 0.4V VOH max Determine noise margin and propagation delay. 0.02mA I Calculate the value of pullup resistance for an open IH collector TTL gate with a fanout of 10. 0.4mA IIL Consider VIH min = 2.0V, IOH = 20mA and the leakage 4mA IOH current ﬂows through the collector of TTL output 8mA IOL transistor is 40 mA. 10ns tPHL Draw the circuit diagram of Schottky NAND gate 10ns tPLH and explain its operation brieﬂy.
121
CHAPTER
4 COMBINATIONAL LOGIC 4.1
INTRODUCTION
A digital circuit is combinational if its output is depending on inputs. The combinational logic circuit is memory less. This logic circuit deals with the method of combining basic gates to get desired solution. Combinational logic circuits can be constructed using logic gates and without feedback from output to input. A simple mathematical model of combinational logic functions is a unit with inputs and outputs as shown in Fig. 4.1. X is the set of input variables X0, X1, X2, …………. to Xn and Y is the set of output variables Y0, Y1, Y2 ……………… Yn. The combinational function operates on the input variables X0, X1, X2, …………. to Xn and the output variables Y0, Y1, Y2 ……………… Yn. The output Y0 is a function of X0, X1, X2, …………. to Xn and it is mathematically written Fig. 4.1 Combination logic functions as Y0 = F(X0, X1, X2, …………. to Xn). Similarly, Y2, Y3 … Yn are also functions of X0, X1, X2, …………. to Xn. The combination logic circuit can be designed by the following steps: Step 1  Select the problem. Step 2  Construct the truth table. Step 3  Write switching functions. Step 4 – Simplify switching functions. Step 5  Draw logic diagram. Step 6  Develop logic circuit using gates.
4.2
ELEMENTS OF COMBINATIONAL LOGIC
Literal, Product Term, Sum Term, Sum of Products, Product of Sum, Maxterm, Minterm are related with combinational logic circuits. The deﬁnations of all these terms are explained below:
Literal: It is a Boolean variable. It will be either primed or unprimed state in the logic expression. – – – As for example, X and X are both literals. Similarly, ABCD consists of four literals A, B, C and D . – Product Term: A product term is the logical product (AND) of literals. For example, X, XY , XYZ are the product of terms when X, Y, Z are Boolean variables. But X + Y + Z is not a product term due to presence of plus (+) sign in the expression.
123
Combinational Logic
– Sum Term: A sum term is sum of literals or the logical OR of literals. For example, X+Y and X + – Y + Z are sum terms, when X, Y, Z are Boolean variables. X(Y + Z) is not a sum term as the logical AND operation is present. Sum of Products: Sum of product (SOP) is the logical expression in which OR of multiple product terms are present. Each product term is the logical AND of literals. The example of SOP expression is – Y + X Y + XYZ. Products of Sums: Product of Sum (POS) is the logical expression in which AND of multiple – – OR terms are present. Each sum term is the OR of literals. The expression (X + X Y ) (XY + Z) (Y + Z) is an example of POS. Minterms: It is a special type of product (AND) term. It is a product term which contains all the input variables that make up a Boolean expression. Maxterm: A maxterm is a special type (OR) term. A maxterm is a sum term that contains all the input variables that make up a Boolean expression. Canonical Forms: Canonical is deﬁned as “conforming to a general rule”. The rule for boolean logic is that each term used in a boolean equation must contain all of the variables. Canonical Sum of Products: A canonical Sum of Products (SOP) is a complete set of minterms that deﬁnes when an output variable is a logical ‘1’. Each minterm corresponds to the row in the truth table when the output function is 1. Canonical Product of Sums: A canonical Product of Sums (POS) is a complete set of maxterms that deﬁnes when an output variable is a logical ‘0’. Each maxterm corresponds to the row in the truth table when the output function is 0. Sum of Minterms: Sum of minterms is the logical expression in which OR of multiple product terms are present. Each product term is the logical AND of literals. Product of Maxterms: Product of maxterms is the logical expression in which AND of multiple product terms are present. Each sum term is the logical OR of literals. Any logic expression can be implemented by logic gates. Then we use Boolean algebra to simplify the expressions by eliminating redundancy at low cost logic circuit. In design, it is required to realise logic expression in one form to another form by converting. There are two useful techniques for reducing combinational logic equations and logic diagrams to the fewest possible elements, namely mapping and tabular minimisation.
4.3
BOOLEAN EQUATION
Logic can be described by truth table, logic diagram and boolean equation. There are sixteen possible logic functions for two inputs variable and one output. Figure 4.2 shows the logic function and all possible outputs, namely F0 to Fig. 4.2 Combinational logic function F15 are depicted in Table 4.1. The output function, F is a function of X and Y. Table 4.1
X
Y
0 0 1 1
0 1 0 1
All possible output functions of two input variables
F0
F1
F2
F3
F4
All possible output functions F5 F6 F7 F8 F9 F10
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
F11 F12 1 0 1 1
1 1 0 0
F13
F14
F15
1 1 0 1
1 1 1 0
1 1 1 1
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Digital Electronics: Principles and Applications
– The output function F0 = 0, F1 = X.Y, F3 = X, F4 = X Y, F5 = Y, F6 = X ≈ Y, ——– — —– – –– – – F7 = X + Y, F8 = X + Y , F9 = X ≈ Y , F10 = Y , F11 = X Y + XY + XY, F12 = X , – – – – – Fig. 4.3 Logic dia F13 = X Y + X Y + XY, F14 = X .Y and F15 = 1. These output functions can be gram of function F1 represented by NOT, AND, NAND, OR, NOR and ExOR and ExNOR logic gates. The logic diagram for switching function F1 is shown in Fig. 4.3. Similarly, truth table, logic diagram and Boolean equations for two, three and four input variables are also explained in this chapter.
4.4
CANONICAL SUM OF PRODUCT (SOP)/MINTERM REPRESENTATION
A truth table is a table that shows all the inputoutput possibilities of any logic circuit. A map is visual display of fundamental products needed for sum of products solution. Two, three and four variables, truth tables are explained below:
4.4.1
Two Variables
A truth table for two variables A and B is depicted in Table 4.2. It is clear from this truth table that there are four possible combinations of the variables and corresponding to these four combinations of the variables there are four possible minterms m0, m1, m2 and m3. Minterm0 (m0) occurs when the variable A –– is ‘0’ and the variable B is ‘0’ and then m0 is represented by A B . Assume that the variable A will always be represented as the most signiﬁcant bit and the variable B will be represented as the least signiﬁcant – bit. Similarly, Minterm1(m1) occurs when A is ‘0’ and B is ‘1’ . Consequently, m1 is represented by A B. In the same way, the other two minterms m2 and m3 can be obtained as given in Table 4.2. Table 4.2 Truth Table and minterms representation for twovariables
A
Inputs B
Output O
0
0
0
0 1 1
1 0 1
1 1 0
Minterms M –– m0 = A B – m1 = A B – m2 = AB m3 = AB
Numerical Representation 0 1 2 3
It can be seen that each row of the truth table represents a minterm. Below the output (O), 1’s are placed to indicate that output contains a particular minterm in its sum and 0’s when that term is excluded from the sum. According to the truth table, the output (O) contains minterm 1 and 2 only. Then the output can be expressed as – – O = A B + AB Another way of representing this relationship is to use the Greek letters sigma, S and an ‘m’ to represent “the sum of minterms”. Applying these notations, we can represent Table 4.2 as O = S m(1, 2). The expression O = S m(1,2) should – – be read as “O is the sum of minterms 1 and 2”. The logic Fig. 4.4 Logic diagram of O = AB + AB diagram of O = S m(1,2) is shown in Fig. 4.4
4.4.2 Three Variables Table 4.3 shows the truth table for a three variables function with minterms. According to the truth table –– – – the output (O) contains minterm 1, 2, 6 and 7. Consequently the output expression is O = A B C + A BC + – ABC + ABC. By using sigma notation, this can be expressed as O = S m(1, 2, 6, 7). The logic diagram –– – – – of O = A B C + A BC + ABC + ABC is shown in Fig. 4.5.
125
Combinational Logic Table 4.3
Truth table for three variables and minterms
Inputs
Output
A
B
C
O
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 0 0 1 1
4.4.3
Minterms M
–– – m0 = A B C –– m1 = A B C – – m2 = A BC – m3 = A BC –– m4 = AB C – m5 = AB C – m6 = ABC m7 = ABC
Numerical Representation 0 1 2 3 4 5 6 7
Four Variables
The truth table of a four variables function is depicted in Table 4.4. It is clear from the truth table that the output, O contains minterms 1, 2, 6, 7, 11, 12, 14 and 15. –– – –– – The expression is O = A B C D + A B CD – – – – –– + A BCD + A BCD + AB CD + ABC D + – ABCD + ABCD. Using sigma notation, –– – – – this can be expressed as O = S m (1, 2, 6, Fig. 4.5 Logic diagram of O = AB C + ABC + ABC + ABC –– – –– – – – – – –– 7, 11, 12, 14, 15). The logic diagram of O = A B C D + A B CD + A BCD + A BCD + AB CD + ABC D + – ABCD + ABCD is shown in Fig. 4.6. Table 4.4
Truth table of four variables
A
B
Inputs C
D
Output O
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1
Minterms M
–––– m0 = A B C D ––– m1 = A B C D –– – m2 = A B CD –– m3 = A B CD – –– m4 = A BC D – – m5 = A BC D – – m6 = A BCD – m7 = A BCD ––– m8 = AB C D –– m9 = AB C D – – m10 = AB CD – m11 = ABCD –– m12 = ABC D – m13 = ABC D – m14 = ABCD m15 = ABCD
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Digital Electronics: Principles and Applications
4.5 CANONICAL PRODUCT OF SUM (POS)/MAXTERM REPRESENTATION 4.5.1 Two Variables The truth table for a two variables function can also be represented in maxterm as shown in Table 4.5. To ﬁnd the maxtern from minterm, all minterms will be complemented. For — example, the complement of minterm m3 is A – – – B = A + B = M3. The maxterm are represented as M0, M1, M2 and M3 for two input variables. The truth Table 4.5 can be expressed in terms of maxterms as follows. – – ––– –– – O = (A + B )(A + B). Fig. 4.6 of O =– –A B C D +–A B C D + – – –Logic diagram – A BC D + A BC D + AB C D + ABC D + ABCD + ABCD This can also be represented as O = ∏(1, 2). The logic circuit diagram is also shown in Fig. 4.7. Table 4.5 Twovariable truth table and maxterm representation
A
Inputs B
Output O
Maxterms M
Numerical Representation
0 0 1 1
0 1 0 1
1 0 0 1
M0 = A + B – M1 = A + B – M2 = A + B – – M3 = A + B
0 1 2 3
4.5.2 Three Variables Table 4.6 shows the truth table of the three variables A, B and C and their maxterm representation are also given in this table. As per truth table, the output consists of four maxterms M1, M2, M6 and M7. The maxterm expression of output is – – – – – – – O = (A + B + C )(A + B + C)(A + B + C)(A + B + C ). The above expression can also be represented as O = ∏(1, Fig. 4.7 Logic diagram of O = (A + B–)(A– + B) 2, 6, 7). The logic circuit diagram is also shown in Fig. 4.8. Table 4.6
Truth table for three variables and maxterms
A
Inputs B
C
Output O
Maxterms M
Numerical Representation
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 0 0 1 1 1 0 0
M0 = A + B + C – M1 = A + B + C – M2 = A + B + C – – M3 = A + B + C – M4 = A + B + C – – M5 = A + B + C – – M6 = A + B + C – – – M7 = A + B + C
0 1 2 3 4 5 6 7
127
Combinational Logic
4.5.3
Four Variables
The truth table of four logic variables function and their maxterm representation are also given in Table 4.7. The max term expression of the given logic function is – – – O – = (A + B +–C + –D)(A– + –B + C + D)(A–+ B + C + D)(A + B + C + D)(A + B + C + D) This is can also represented as O = ∏(1, 2, 6, 7, 9). The logic circuit diagram is depicted in Fig. 4.9. Table 4.7
Truth table of four variables
A
Inputs B C
D
Output O
Maxterms M
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 0 1 1 1 0 0 1 0 1 1 1 1 1 1
M0 = A + B + C + D – M1 = A + B + C + D – M2 = A + B + C + D – – M3 = A + B + C + D – M4 = A + B + C + D – – M5 = A + B + C + D – – M6 = A + B + C + D – – – M7 = A + B + C + D – M8 = A + B + C + D – – M9 = A + B + C + D – – M10 = A + B + C + D – – – M11 = A + B + C + D – – M12 = A + B + C + D – – – M13 = A + B + C + D – – – M14 = A + B + C + D – – – – M15 = A + B + C + D
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Example 4.1
– Fig. 4.8 –Logic diagram – – of O – = (A – +B – + C) (A + B + C)(A + B + C)(A + B + C )
Fig. 4.9
Logic diagram of O = P(1, 2, 6, 7, 9)
Determine the boolean function of the truth Table 4.8 in terms of minterms and draw the logic diagram.
� Solution The truth Table 4.8 can be represented in terms of minterms 0, 1, 4 & 5 and it can be expressed as – – – –– –– – O = ∏ m (0,1, 4, 5) = A B C + A B C + AB C + AB C . Figure 4.10 shows the logic circuit diagram. Table 4.8
Fig. 4.10
Logic diagram of O = S m(0, 1, 4, 5)
A
Inputs B
C
Output O
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 1 0 0 1 1 0 0
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Example 4.2
Determine the boolean function of the truth Table 4.9 in terms of maxterms and draw the logic diagram. Table 4.9
�
A
B
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
Inputs
C
D
Output O
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0
Solution
The Table 4.9 consists of the following maxterms 0, 1, 2, 3 &15 and it can be represented by O = ∏(0,1,2,3,15). This function can be expressed as
– – – – – – – – O = (A + B + C + D)(A + B + C + D)(A + B + C + D) (A + B + C + D) (A + B + C + D ) and its logic diagram is depicted in Fig. 4.11.
Fig. 4.11
–
Logic Diagram of O = (A + B + C + D)(A + B + C + D)
– – – – – – – (A + B + C + D) (A + B + C + D) (A + B + C + D )
4.6
MINTERM VS. MAXTERM
Any Boolean function can be written either as sum of minterms or product of maxterms. When the function is represented by minterms, the function is easily formed by ORING together the minterms for which the function is true (1). This form of representation is called Canonical sum of product (SOP)
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Combinational Logic
representation. Similarly, in the maxterm expressions, the function is formed by ANDING together the maxterms for which the function is false (0). This form of the function is called the Canonical Product of Sums (POS) representation. Minterms and maxterms can be formed for any number of variables. We can form the minterm for any row of truth table by ANDING together all the variables that are true (1) in that row and the complements of all the variables that are false (0) in that row. In the same way, we can also form the maxterm for any row by ORING together all the variables that are false (0) in that row and the complements of all the variables that are true (1) in that row.
4.7 CONVERSION BETWEEN CANONICAL SOP AND CANONICAL POS FORMS The Canonical SOP and Canonical POS forms representation of a Boolean function are complementary. The numbers, which are existing in SOP representation, do not appear in POS representation. Similarly all the numbers which are exist in POS representation, do not appear in SOP representation. To convert from one Canonical form to other Canonical form, the symbols S and P will be interchanged and the list of numbers will be present in new form which is actually missing from original form. If “n” is the number of variables of the function, there will be 2n number of minterms and maxterms. When “m” number minterms are present in original expression, then its maxterm representation consists of (2n – m) maxterms. The conversion from Canonical SOP to Canonical POS Form and Canonical POS to Canonical SOP form are explained below:
4.7.1 Canonical SOP to Canonical POS Form The complement of a function which is expressed as the Canonical sum of products (SOP) is equal to the Canonical product of sum (POS). Table 4.10 shows the truth table of a typical Boolean function. The original function can be expressed by the minterms which make the function equal to ‘1’. When we take complement of minterms, we can represent the same function in maxterms which make the function equal to ‘0’. Table 4.10
A 0 0 0 0 1 1 1 1
Inputs B 0 0 1 1 0 0 1 1
Truth table for three variables and maxterms
C
Output O
0 1 0 1 0 1 0 1
0 1 1 0 0 0 1 1
Minterms M –– – m0 = A B C –– m1 = A B C – – m2 = A BC – m3 = A BC –– m4 = ABC – m5 = ABC – m6 = ABC m7 = ABC
Maxterms M M0 = A + B + C – M1 = A + B + C – M2 = A + B + C – – M3 = A + B + C – M4 = A + B + C – – M5 = A + B + C – – M6 = A + B + C – – – M7 = A + B + C
According to the truth table as given in Table 4.10, the Boolean function in minterms is –– – – – F(A, B, C) = S m(1,2,6,7) = m1 + m2 + m6 + m7 = A B C + A BC + ABC + ABC After incorporating the missing minterm numbers in original function, we can get the complement of function F(A, B, C) is F¢(A, B, C) = S m(0, 3, 4, 5) . –– – – –– – Therefore, F¢(A, B, C) = S m(0, 3, 4, 5) = m0 + m3 + m4 + m5 = A B C + A BC + AB C + ABC
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– ◊ m– ◊ m – ◊ m– The complement of the function F¢(A, B, C) = F(A, B, C) = m0 + m3 + m4 + m5 = m 0 3 4 5 Applying DeMorgans theorem, we ﬁnd that –– – – –– – F(A, B, C) = m0 + m3 + m4 + m5 = A B C + A BC + AB C + ABC = A–B–C– ◊ A–BC ◊ AB–C– ◊ AB–C – – – – – = (A + B + C) (A + B + C )(A + B + C)(A + B + C ) = M0 M3 M4 M5 = P (0,3,4,5) It can be stated that minterms complement is the maxterm and it can be expressed as m¢j = Mj , where M = maxterm, m = minterm and j = 0, 1, 2 …..(2n – 1).
4.7.2 Canonical POS to Canonical SOP Form The complement of a function which is expressed as the Canonical product of sum (POS) is equal to the Canonical sum of products (SOP). The original function can be expressed by the maxterms which make the function equal to ‘0’. When we takes complement of maxterms, we can represent the same function in minterms which make the function equal to ‘1’ . According to the truth table as given in Table 4.10, the Boolean function in maxterms is – – – – – F1(A, B, C) = P (0, 3, 4, 5) = M0 M3 M4 M5 = (A + B + C) (A + B + C )(A + B + C)(A + B + C ) The complement of function F1(A, B, C) is F1¢(A, B, C) = P (1, 2, 6, 7) Therefore, – – – – – – – F1¢(A, B, C) = P (1, 2, 6, 7) = M1 M2 M6 M7 = (A + B + C ) (A + B + C) (A + B + C) (A + B + C ) The complement of the function F1¢(A, B, C) = F1(A, B, C) = M1 M2 M6 M7 Applying DeMorgans theorem, we ﬁnd that — — — — F1(A, B, C) = M 1 + M 2 + M 6 + M 7 – – – – – – – =A+B+C +A+B+C+A+B+C+A+B+C –– – – – = A B C + A BC + ABC + ABC = m1 + m2 + m6 + m7 = S m(1,2,6,7) It can be stated that maxterm complement is the minterms and it can be expressed as M¢j = mj , where M = maxterm, m = minterm and j = 0, 1, 2 … (2n – 1).
4.8
DEVELOPMENT OF TRUTH TABLE FROM LOGIC EXPRESSION
Sometimes, we have a Boolean expression and we want to ﬁnd its truth table. The Boolean expression can be written in minterms or maxterms. For example, we consider that the Boolean logic function is O = P(0, 1, 4, 5, 10, 11, 14, 15). The logic expression for the function O = P(0, 1, 4, 5, 10, 11, 14, 15) is – – – – – – O = (A + B + C + D)(A + B + C + D)(A + B + C + D)(A + B + C + D )(A + B + C + D) – – – – – – – – – – (A + B + C + D)(A + B + C + D)(A + B + C + D ) In this logic expression, the equation is written in the form of maxterms. The truth table for the above Boolean expression is shown in Table 4.11, where we have placed a ‘0’ in each row that corresponds
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Combinational Logic
to a maxterm in the function and a ‘1’ in all other rows at output column. To form a truth table for any function written in maxterms, the process is almost identical. The logic circuit diagram of O = ∏(0, 1, 4, 5, 10, 11, 14, 15) is depicted in Fig. 4.12. Table 4.11
Inputs A
B
C
D
Output O
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0
Fig. 4.12
Maxterms M M0 = A + B + C + D – M1 = A + B + C– + D M2 = A + B + C– + D – M3 = A + B– + C + D M4 = A + B– + C + D– M5 = A + B– + C– + D M6 = A + B– + C– + D – M7 = A– + B + C + D M8 = A– + B + C + D– M9 = A– + B + C–+ D M10 = A– + B + C– + D – M11 = A– + B– + C + D M12 = A– + B– + C + D– M13 = A– + B– + C– + D M14 = A– + B– + C– + D– M15 = A + B + C + D
Logic diagram of O = P(0,1,4,5,10,11,14,15)
To develop a logic expression written in minterm from the truth Table 4.12, the procedure is same. Consider the logic function is O =∑ m (1, 3, 5, 7, 8, 9, 12, 13) and it can be expressed as ––– –– – – – ––– –– –– – O = A B C D + A B CD + A BCD + A BCD + AB C D + AB C D + ABCD + ABC D. The truth table of the logic function is illustrated in Table 4.12 and the logic circuit diagram is depicted in Fig. 4.13.
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Digital Electronics: Principles and Applications Table 4.12
A
B
Inputs C
D
Output O
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 1 1 0 0 1 1 0 0
Fig. 4.13
4.9
Minterms M– – – –
m0 = A – –B C –D m1 = A–B–C D – m2 = A–B–CD m3 = A– B CD –– m4 = A– BC– D m5 = A–BC D – m6 = A–BCD m7 = A BCD ––– m8 = AB– C– D m9 = AB–C D– m10 = AB–CD m11 = AB CD –– m12 = ABC– D m13 = ABC D – m14 = ABCD m15 = ABCD
Logic diagram of O = Sm (1, 3, 5, 7, 8, 9, 12, 13)
LOGIC SIMPLIFICATION USING BOOLEAN ALGEBRA
The maxterm and minterm expressions can be simpliﬁed by using Boolean algebra. The procedure is given below for both expressions. For example, the maxterm expression is – – – – O = (A + B + C + D)(A + B + C + D)(A + B + C + D)(A + B + C + D ) – – – – – – – – – – – – (A + B + C + D) (A + B + C + D)(A + B + C + D)(A + B + C + D )
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Combinational Logic
– The product of sum expression can be simpliﬁed by using logic adjacency D + D = 1 = (A + B + C) (A + B + C)(A– + B + C–)(A– + B– + C–) – – = (A + C) (A + C ) – – Thus, the simpliﬁed expression is O = (A + C) (A + C ) and Fig. 4.14 shows the logic circuit diagram. ––– –– – – – Similarly, we consider that the minterm expression is O = A B C D + A B CD + A BCD + A BCD ––– –– –– – + AB C D + AB C D + ABCD + ABC D and apply Boolean algebra to simplify it. Therefore, the simpliﬁed form of minterm expression is given below: –– – – – –– – – – = A B D(C + C) + A BD(C + C) + AB C (D + D) + ABC (D + D) –– – –– – – – = A B D + A BD + AB C + ABC , where (C + C) = 1 and D + D = 1 – – – – – – = A D(B + B) + AC (B + B) = A D + AC Figure 4.12 represents the logic diagram of the Boolean expression O = (A + B + C + D)(A + B + C + – – – – – – – – – – – – – – – – D)(A + B + C + D)(A + B + C + D ) (A + B + C + D) (A + B + C + D)(A + B + C + D)(A + B + C + D ) us– – ing gates before simpliﬁcation. After simpliﬁcation we get the simpliﬁed expression O = (A + C) (A + C ) and the logic diagram of this simpliﬁed expression using logic gates is depicted in Fig. 4.14. Similarly, ––– –– – – – ––– –– the logic diagram of the Boolean expression O = A B C D + A B CD + A BCD + A BCD + AB C D + AB C D –– – + ABCD + ABC D is shown in Fig. 4.13 using gates before simpliﬁcation. After simpliﬁcation, we obtain – – the simpliﬁed expression of O = A D + AC and Fig. 4.15 represents the logic diagram of the simpliﬁed – – expression of O = A D + AC . Consequently, it is very clear, from the circuit diagrams that we can be able to represent the same logic function by different circuit diagrams and also in most simpliﬁed form. The simpliﬁed representation of a logic function using logic gates has the following advantages: less cost, reduce number of logic gates, reduce complexity, simple circuit, and reduce delay and ﬁrst logic output.
Fig. 4.14
– – Logic diagram of O = (A + C) (A + C )
Example 4.3
Fig. 4.15
– – Logic diagram of O = A D + AC
Develop the truth table of the logic expression O = P(0,1,2,4,5,7).
� Solution Table 4.13 shows the truth table of the logic function O = P(0,1,2,4,5,7). Table 4.13
A
Inputs B
C
Output O
Maxterms M
Numerical Representation
0
0
0
0
M0 = A + B + C
0 (Contd...)
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Digital Electronics: Principles and Applications
(Contd...) 0 0 0 1 1 1 1
0 1 1 0 0 1 1
Example 4.4
1 0 1 0 1 0 1
0 0 1 0 0 1 0
– M1 = A + B + C – M2 = A + B + C – – M3 = A + B + C – M4 = A + B + C – – M5 = A + B + C – – M6 = A + B + C – – – M7 = A + B + C
1 2 3 4 5 6 7
Develop the truth table of the logic expression O =∑m(1,2,3,4,6,7).
� Solution Table 4.14 shows the truth table of the logic function O = ∑m(1, 2, 3, 4, 6, 7) Table 4.14
A 0 0 0 0 1 1 1 1
Example 4.5
Inputs B 0 0 1 1 0 0 1 1
C
Output O
0 1 0 1 0 1 0 1
0 1 1 1 1 0 1 1
Minterms M ––– m0 = A B C –– m1 = A B C – – m 2 = A BC – m 3 = A BC –– m 4 = AB C – m 5 = AB C – m 6 = ABC m 7 = ABC
Numerical Representation 0 1 2 3 4 5 6 7
Simplify the logic expression using Boolean algebra and draw the logic circuit for O = Σ(0, 1, 2, 6, 10, 11).
� Solution The logic function O = Σ(0, 1, 2, 6, 10, 11) contains four variables. Table 4.15 shows the truth table of the logic function and this function can be expressed in standard SOP form as given below: –––– ––– –– – – – – – O = A B C D + A B C D + A B CD + A BCD + AB CD + – AB CD. Then Boolean algebra is used to simplify the function. ––– – – – – – – O = A B C (D + D) + A CD (B + B) + AB C(D + D) ––– – – – – = A B C + A CD + AB C where, A + A = 1 ––– Therefore, the simpliﬁed logic expression is O = A B C + – – – A CD + AB C and the logic circuit diagram is shown in Fig. 4.16.
Fig. 4.16 Logic diagram of ––– – – – O = A B C + A CD + AB C
135
Combinational Logic Table 4.15
Inputs
Output
A
B
C
D
O
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 0 0 0 1 0 0 0 1 1 0 0 0 0
Example 4.6
Minterms m
–––– m 0 = AB CD ––– m 1 = AB CD –– – m 2 = A B CD –– m 3= A B CD – –– m 4= A BC D – – m 5 = A BC D – – m 6 = A BCD – m 7 = A BCD ––– m 8 = AB C D –– m 9 = AB C D – – m 10 = AB CD – m 11 = AB CD –– m 12 = ABC D – m 13 = ABC D – m 14 = ABCD m 15 = ABCD
Simplify the logic expression using Boolean algebra and draw the logic circuit for O = ∏ (4, 5, 8, 9, 10, 11)
� Solution Table 4.16 shows the truth table of logic function O = ∏ (4,5, 8, 9, 10,11) and the standard POS representation of the function is – – – – – – – – – – – O = (A + B + C + D) (A + B + C + D ) (A + B + C + D) (A + B + C + D ) (A + B + C + D) (A + B + C + D ) The above expression can also be simpliﬁed using logic adjacency of Boolean algebra and the simpliﬁed of the function is given below: – – – – – – O = (A + B + C) (A + B + C) (A + B + C ) = (A + B + C) (A + B) – – The logic circuit diagram of this simpliﬁed logic expression O = (A + B + C) (A + B) is depicted in Fig. 4.17. Table 4.16
A
B
Inputs C
D
Output O
Maxterms M
0 0
0 0
0 0
0 1
1 1
0 0 0 0 0 0
0 0 1 1 1 1
1 1 0 0 1 1
0 1 0 1 0 1
1 1 0 0 1 1
1
0
0
0
0
M0 = A + B + C + D – M1= A + B + C + D – M2= A + B + C + D – – M3= A + B + C + D – M4 = A + B + C + D – M5= A + B + C + D – – M6= A + B + C + D – – – M7 = A + B + C + D – M8 = A + B + C + D (Contd...)
136 (Contd...) 1 1 1 1 1 1 1
Digital Electronics: Principles and Applications
0 0 0 1 1 1 1
0 1 1 0 0 1 1
1 0 1 0 1 0 1
– – M9= A + B + C + D – – M10= A + B + C + D – – – M11= A + B + C + D – – M12 = A + B + C + D – – – M13= A + B + C + D – – – M14= A + B + C + D – – – – M15= A + B + C + D
0 0 0 1 1 1 1
–
–
Fig. 4.17 Logic diagram of O = (A + B + C) (A + B)
Example 4.7
—– —– Simplify the logic expression (AB(C + BD) + A B ) CD.
� Solution —– —– (AB(C + BD) + A B ) CD – – – – = (AB(C + B + D) + A + B )CD – – – – = (ABC + ABB + ABD + A + B )CD – – – = (ABC + ABD + A + B )CD – – – = ABCD + ABDCD + A CD + B CD – – = ABCD + A CD + B CD – – = CD(AB + A + B ) —– = CD(AB + A B ) = CD Example 4.8
Applying DeMorgan After distribute – As ABB = 0 After distribute – As ABDCD = 0 Distribute Applying DeMorgan —– As AB + A B = 1
Simplify the logic diagram as given below:
� Solution The output Y of the logic diagram as shown in Fig. 4.18 is Y = AB BC BC CD = (AB + BC)(BC + CD) = (ABBC + ABCD) + (BCBC + BCCD) = ABC + ABCD + BC + BCD = ABC (1 + D) + BC(1 + D) —– = ABC + BC = BC(A + 1) = B C
Applying DeMorgan After distribute Remove repeated variables Apply absorption Fig. 4.18
Combinational Logic
137
4.10 KARNAUGH MAPS M. Karnaugh published his work in 1953 with the title “The map method for synthesis of combinational logic circuits”. Actually, this map method is graphical representation of Boolean functions and is used to simplify Boolean functions considering the idea of an array of next neighbor, and logic adjacent minterms. In place of writing all the minterms, M. Karnaugh represented the Boolean functions using minterm relations. This map method is known as a Karnaugh map or Kmap. A Karnaugh map is a matrix of squares and each square represents a minterm or maxterm from of a Boolean expression. A Karnaugh map is used to ﬁnd input variable redundancies and to reduce output Boolean equation. Each map lists the 2n product terms that can be formed from ‘n’ variables, each in a different square. A product term in ‘n’ variables is called a minterm. For 3 variables, 23=8 minterms and for 4 variables, 24=16 minterms..The Karnaugh map for two, three, four, ﬁve and six variables are explained below:
4.10.1
Two Variables Karnaugh Map
Figure 4.19 shows the Karnaugh map for a two variable function. Each square or cell in the map represents a minterm in terms of variables A and B. The value of one of the variables associated with the cell is given above the cell and the value of the other variable associated with the same cell is given to the left of the cell. At the upper left corner of the Kmap, variable names A and B are shown above and below a diagonal line respectively. In this ﬁgure, the column variable is A and the row variable is B. The minterm indices associated with a cell is given in the lower right corner of the cell. For example, in this map the minterm associated with the lower right cell is m3 = AB, this minterm is true if A = 1, and B = 1 as depicted in Fig. 4.19(c).
Fig. 4.19 (a), (b) and (c) Two variables map
Figure 4.19 (a), (b) and (c) are alternatively used in Karnaugh map representation. The names of the variables are listed on both sides of the diagonal line. The ‘A’ above the diagonal indicates that the – variable A is assigned to the columns. The ‘0’ is a substitute for A , and the ‘1’ substitutes for A. Below – the diagonal ‘B’ is associated with the rows: ‘0’ stands for B , and ‘1’ stands for B. Table 4.17 shows the truth table of a two variables function. The outputs of the truth table correspond on an onetoone basis are entered into Karnaugh map as depicted in Fig. 4.20. For example, enter “0” –– in cell0 corresponding to Boolean expression A B . Similarly, enter “1” in cell1, 2 and 3 corresponding
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– – to Boolean expressions A B, AB and AB respectively. The minterm relationship of the function as given in the Karnaugh map (Kmap) – – is O = A B + AB + AB.
Fig. 4.20 Two variable map
This map has two grouping of two minterms because of the logic adjacency of 2 adjacent cell regions in the Kmap. The shaded rectangle region corresponds to A and another shaded rectangle encloses the region corresponding to B. So the simpliﬁed function
is O = A + B . Figure 4. 21 (a), (b), and (c ) show the different adjacent 2cell regions in the 2variable Kmap. Table 4.17
Inputs
Twovariables truth table and minterm representation
A
B
Output O
0 0 1 1
0 1 0 1
0 1 1 1
Minterms m –– m0 = A B – m 1 = AB – m 2 = AB m 3 = AB
Numerical Representation 0 1 2 3
Fig. 4.21 The adjacent 2 cell regions of two variable K map
Example 4.9
Figure 4.22 (a) and 4.22(b) are given. Determine the Boolean expression.
Fig. 4.22 Two variables Karnaugh map
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Combinational Logic
� Solution Kmap is used to simplify the boolean expression based on adjacent cells. Actually, cells make one or more variables common in boolean expression. The procedure of determining the boolean expression as follows: Step1 Group the two 1s in the column of Kmap; Step2 Determine the variables top and/or side, which are the same for the group; Step3 Write the Boolean expression. Here the Boolean – expression of the function of Fig. 4.22(a) is B. The procedure of determining the Boolean expression for Fig. 4.22 (b) is given below: Step1 Group the two 1’s in the row of Kmap; Step2 Determine the variables top and/or side, which are the same for the group; Step3 Write the Boolean expression. At this time, the boolean expression of the function of Fig. 4.22 (b) is A. Fig. 4.22
(a) and (b)
Example 4.10 �
Table 4.18 shows the truth table of a function. Transfer the outputs to the Karnaugh and write the Boolean expression.
Solution
Transfer the 1s from the locations in the Truth table to the corresponding locations in the Kmap. Fig. 4. 23 shows the Kmap for the truth table 4.18. A B Output Then the following procedure is done to determine the Boolean function 0 0 0 Step – 1 Group rectangle the two 0 1 1 1’s in the column under B 1 0 1 1 1 1 Step – 2 Group rectangle the two 1’s in the row right of A Step – 3 The product term for ﬁrst group is B Step – 4 The product term for second group is A Step – 5 The sumofproducts of above two terms is O = A + B Table 4.18
Fig. 4.23
Example 4.11
Simplify the logic diagram as shown in Fig. 4.24.
Fig. 4.24
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Digital Electronics: Principles and Applications
� Solution The logic diagram as shown in Fig. 4.24 can be simpliﬁed in the following steps as given below: Step – 1 The Boolean expression for the logic diagram as shown in Fig. 4.24 can be written as – – O = A B + AB + AB Step – 2 Relocate the product terms to the Karnaugh map as depicted in Fig. 4.25. Step – 3 Form groups of adjacent cells. Step – 4 The Boolean expressions for groups can be written. Step – 5 The sumofproducts of above two terms is O = A + B. Step – 6 The simpliﬁed logic diagram can be drawn as shown in Fig. 4.26. Example 4.12
Fig. 4.25
Fig. 4.26
Simplify the logic diagram as shown in Fig. 4.27.
Fig. 4.27
� Solution The logic diagram as shown in Fig. 4.26 can be simpliﬁed in the following steps as given below: Step – 1 The Boolean expression for the logic diagram as shown in Fig. – – 4.27 can written and it is O = A B + AB Step – 2 Relocate the product terms to the Karnaugh map as depicted in Fig. 4.28.
Fig. 4.28
Step – 3 The grouping of adjacent cells is not possible as only diagonal cells are present. Hence simpliﬁcation is not possible. Step – 4 The simpliﬁed logic diagram can be drawn using Exclusive OR gate as shown in Fig. 4.29.
4.10.2
Fig. 4.29
Three Variables Karnaugh Map
Table 4.19 shows the truth table of a three variable function and the 3variable Karnaugh map can be used to represent the same as illustrated in Fig. 4.30. This 3variable Karnaugh map has 23 = 8 cells, the small squares within the map. Each individual cell is exclusively identiﬁed by the three Boolean variables A, –– B, C. It is depicted in Fig. 4.30 that A B C distinctively selects Fig. 4.30
Three variable maps
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Combinational Logic
the lower left most cell m1 or 1. Similarly, each cell can be uniquely identiﬁed by a 3variable product term, a – Boolean AND expression. For example, AB C following – the C row across to the right and the AB column down, – both intersecting at the lower right most cell AB C. The sequence of numbers across the top of the map is not a binary sequence and it should be 00, 01, 11, 10. Actually, 00, 01, 11, 10 is Gray code sequence as only one binary bit changes during one number to the next number in Gray code sequence. As adjacent cells are always varied by one bit, we use Gray code in Kmap representation. For this, it is required to organise the outputs of a logic function in such a way so that we can visualise all at a time. Therefore, the column and row headings of a Karnaugh map must be in Gray code order. Three variable Karnaugh map with adjacent cells combinations is given in Fig. 4.31(a), (b), (c) and (d). Table 4.19
A
Fig. 4.31 Three variable Karnaugh map with adjacent cells combinations (a) four cells (b) four cells (c) four cells (d) eight cells
4.10.3
0 0 0 0 1 1 1 1
Inputs B C 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Output Minterms Numerical O M Representation 0 1 1 0 0 0 1 1
–– – m0= A BC –– m 1= A B C – – m 2= A BC – m 3= A BC –– m 4= AB C – m 5= AB C – m 6= ABC m 7= ABC
0 1 2 3 4 5 6 7
Four Variables Karnaugh Map
The truth table of a function of four variables is illustrated in Table 4.20. Since 24 is 16, there are 16 combinations of variables labeled 0 through 15. Figure 4.32 shows the Karnaugh map for four variables. This map has four rows and four columns. The columns are assigned to variables A and B, but rows for variables C and D. All variables are follows the gray code for shifting from one cell to next cell. All product terms of four variables as shown in Table 4.20 can be placed in all 16 cells of
Fig. 4.32
Four variables K map
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map. In minimisation of a four variables function, initially, we ﬁnd out the most distinguished 1 cells, which lead to essential prime implicants. After that, the rest ‘1’ cells are grouped to provide the minimal form of the function. The simpliﬁcation procedure of Boolean function using Kmap is explained later in detail. Table 4.20
Truth table of four variables
Inputs
4.10.4
A
B
C
D
Output O
Minterms M
0
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
1
0
1
1
1
1
1
0
0
0
0
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
–– – – m0 = A BCD –– – m1 = A BCD –– – m2 = A BCD –– m3 = AB CD – –– m4 = ABC D – – m 5 = ABC D – – m 6 = A BCD – m 7 = A BCD ––– m 8 = ABCD –– m 9 = ABCD – – m 10 = ABCD – m 11 = ABCD –– m 12 = ABCD – m 13 = ABC D – m 14 = ABCD
1
1
1
1
1
m 15 = ABCD
Five Variables Karnaugh Map
Karnaugh maps can be extended to ﬁve variables by using a three dimensional array of cells. In threedimensional representation all next neighbour cells are logic adjacent. But it is little bit difﬁcult to represent in a two dimensional Karnaugh map. In this two dimensional representation, each section of map are placed side by side sequentially according to their sequence in three dimensional form. To represent ﬁve variables Kmap, 25=32 cells are required to accommodate all the product terms and two blocks of sixteen cells are required. Figure 4.33 shows the ﬁve variables Kmap. In this ﬁgure, the left block is used for minterms from m0 to m15 where most signiﬁcant variable A=0 and the right block can be used minterms for m16 to m31 where A=1. The most signiﬁcant variable is shown as the mapheading Fig. 4.33 Five variables Karnaugh map variable. During visualisation of the map,
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Combinational Logic
we consider the block of the map is stacked on the top of the right block. Therefore, cell 0 is logic adjacent to cell 16, cell 2 is logic adjacent to cell 18, cell 8 is logic adjacent to cell 24, cell 10 is logic adjacent to cell 26 and so on. Table 4.21 shows the truth table for a function of ﬁve variables and a ﬁve variable map can be accommodated from this table as shown in Fig. 4.33. The minterm representation of Table 4.21 is O = Σ(m0, m1, m2, m3, m8, m16, m17, m18, m19, m24) To simplify this function, we try to make group all entries of Kmap cells. When left block lies above the right block, all cells that are neighbours sidetoside and top to bottom. Cell 2 is logic adjacent to cell 18 and cell 8 is logic adjacent to cell 24 and so on. So cells 0, 1, 2, 3 and cells 16, 17, 18, 19 are logic adjacent and makes a group of eight cells. Similarly, the group of two cells consists of cell 8 and 24. In normal minimisation of a ﬁve variables, we may not be able to ﬁnd out the minimum numbers of terms or literals. The better approach is to ﬁnd the most distinguished –‘1’ cells which lead to essential prime implicants. After that the rest 1’s are grouped to provide the minimal from of the function. Table 4.21 Truth table of ﬁve variables A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
B 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Inputs C 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
D 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
E 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Output O 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0
Minterms M m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 m16 m17 m18 m19 m20 m21 m22 m23 m24 m25 m26 m27 m28 m 29 m 30 m 31
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4.10.5
Digital Electronics: Principles and Applications
Six Variables Karnaugh Map
The six variables Karnaugh map can be developed based on the method of ﬁve variables Karnaugh map. Figure 4.34 shows the six variables map. In this map, four blocks of 16 cells are required and four variables C, D, E, and F are used. The other two variables are the two most signiﬁcant variables that can be used as map headings for each four variables block of the map. During threedimensional representation of six variables Karnaugh map, the four blocks of four variables are stacked one on top of another according to variation of two most signiﬁcant bits A and B. The sequence is started with 00 and others will be 01, 11 and 10. According to sequence of stack, subsequent elements at the top and bottom of the stack are logic adjacent. Consequently, cell 0 is logic adjacent to cell 16, cell 16 is logic adjacent to cell 48, cell 48 is logic adjacent to cell 32 , and so on.
Fig. 4.34
4.11
Six variables Karnaugh map
CONSTRUCTION OF KARNAUGH MAPS FROM LOGIC EXPRESSION
The Karnaugh map for a given Boolean expression can be constructed by the following steps: Step – 1 Find out the size of the Kmap. Actually the number of variables in the function can determine the size of the Kmap. If the function has ‘n’ variables, then Kmap of the said function consists of 2n cells. Step – 2 Assemble all 2n cells in the form of m ¥ n matrix. Generally, m is equal to n. Here m = number of rows and n = number of columns. Step – 3 Locate the decimal number to each cell according to gray code sequence. Step – 4 Enter a ‘1’ in each cell subsequent to each decimal number of the minterms expression, SOP and enter a ‘0” in each square corresponding to each decimal number of the maxterms, POS.
Combinational Logic Example 4.13
145
– Construct a Karnaugh Map for the Boolean function O = AB + CD
� Solution – The expression O = AB + CD is a four variables function. So the Kmap of the said function consists of 4 2 = 16 cells. The Kmap can be represented by 4 ¥ 4 matrix as shown in Fig. 4.35. The ﬁrst term of the – expression is AB, we put 1s in all the cells of the map where A = 1 and B = 1. Then the second term is CD, we also locate 1’s in all the cells, where C = 1and D = 0.
Fig. 4.35 Four variable map
Example 4.14
Construct a Karnaugh map for the function O = ABC + BC
� Solution The expression O = ABC + BC is a three variables function. So the Kmap of the said function consists of 23 =8 cells. The Kmap can be represented by 4 ¥ 2 matrix as shown in Fig. 4.36. The ﬁrst term of the expression is ABC, we put 1s in all the cells of the map where A = 1, B = 1 and C = 1. Then the second term is BC, we also locate 1s in all the cells, where B = 1and C = 1.
Fig. 4.36 Three variable maps
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4.12
Digital Electronics: Principles and Applications
LOGIC SIMPLIFICATION USING KARNAUGH MAPS
In general, Karnaugh map is used to ﬁnd the simplest form of logic expression. The Karnaugh map can reduce any logic function very rapidly and easily compared to Boolean algebra. As the logic expression is simpliﬁed, the number of gates and inputs will be reduced. Hence, the logic circuit will be cheap due to elimination of components. Therefore, to design a low cost and efﬁcient logic circuit, designer should choose the lowest number of gates with the lowest number of inputs per gate. The minimisation procedure using Karnaugh map is explained below: Step – 1 Initially, truth table or Boolean expression of a logic function is converted into corresponding K  map. Step – 2 Start groupings of 1’s in all the entries of the Kmap. Actually, consider groupings of two terms, then four terms, then eight terms and so on. After that choose minimum number of groupings to cover all the entries in the map. In this step, we always try to avoid forming groupings, which are already covered by larger groupings. Step – 3 Find all the single entries which can not be covered by any grouping. Step – 4 When steps from 1 to 3 are completed, write the minimum expression corresponding to groupings so that every 1s of the Kmap is covered by at least one grouping. For example, consider a logic expression –– – – –– – – – – – O = ABC D + ABC D + ABCD + ABCD + A B CD + A BCD + AB CD . This is a four variables function. Therefore, a four variables Karnaugh map is required to represent the logic function. Fig. 4.37 shows the Karnaugh map of this logic function. The above Boolean expression has seven product terms. They are mapped top to bottom and left to right on the Kmap as given in Fig. 4.37. For example, the –– ﬁrst Pterm ABC D is ﬁrst row 3rd cell, corresponding to map location A = 1, B = 1, C = 0, D = 0. Then other product terms are placed in a similar manner. After that, start groupings of 1s in all the entries of the Kmap. It is very clear from the Fig. 4.37 that there are only two groups of four terms to cover all the entries in the map. The dashed horizontal group corresponds Fig. 4.37 – the simpliﬁed product term CD . The vertical group corresponds to Boolean expression AB. Representing two groups, we ﬁnd the minimum expression in – the sumofproducts form O = AB + CD . The four variables logic function can also be reduced by Boolean algebra but it is very tedious as given below: –– – – –– – – – – – O = ABC D + ABC D + ABCD + ABCD + A B CD + A BCD + AB CD . – – – – – – – – = ABC (D + D) + ABC(D + D) + BCD(A + A) + B CD(A + A) – – – – – – – – = ABC + ABC + BCD + B CD = AB(C + C) + CD (B + B) = AB + CD As the Karnaugh map reduction process is faster and easier than Boolean algebra, we commonly used Kmap specially if there are many logic reductions to do.
Combinational Logic
147
– –– – The Kmap for logic expression O = A BC D + A – – – – –– – – BC D + A BCD + A BCD + ABC D + ABCD + ABCD + ABCD is shown in Fig. 4.38 and we can determine its simpliﬁed form using Kmap that is O=B.
Fig. 4.38
––– – – Similarly, the logic expression O = A B C D + A BC D –– – –– – – + AB C D + ABCD + A B CD + A BCD + AB CD + ABCD can simpliﬁed using Kmap and it is O = D as depicted Fig. 4.39 in Fig. 4.39. When we fold up the corners of the map, it is a napkin to make the four cells physically adjacent as shown in Fig. 4.40, The four cells of the above Kmap are a group of four – – as the Boolean variables B and D are in common. The logic –– – – –– – –– – – – expression O = A B C D + A B CD + AB C D + ABCD can be –– represented in the simpliﬁed form that is O = B D . In the Kmap as shown in Fig. 4. 41, if we roll the top and bottom edges of Kmap, a cylinder is formed with eight adjacent cells. This group of eight adjacent cells has one common Fig. 4.40 Boolean variable D = 0. Consequently, the logic expression –––– – – O = A B C D + A BC – –– – –– D + ABCD + ABC D –– – – – Fig. 4.41 + A BCD + A BCD + – – – – ABCD + ABCD can be represented by one product term, D. The – original eight term Boolean expression simpliﬁes to O = D. To simplify the Karnaugh map as given in Fig. 4.42, we can sketch out two groups of eight cells. A group of – eight cells can be represented by B and another group – of eight cells represents D . Therefore, the simpliﬁed Fig. 4.42 –––– – –– –– – –– output of O = A B C D + A BC D + AB C D + ABC D –– – – – – – – –– – –– –– – – – + A B CD + A BCD + AB CD + ABCD + A B C D + A B CD + AB C D + AB CD is O = B + D . Similarly,
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Digital Electronics: Principles and Applications
–– – Fig. 4.43 can be represented by O = A C + BC + D. Figure 4.44 can also be represent by grouping 2n of –– – cells and can be represented by O = A B + AB + A CD.
Fig. 4.43
4.13
Fig. 4.44
PRODUCT OF SUMS SIMPLIFICATION USING KARNAUGH MAPS
We are already familiar with SumofProduct (SOP) solutions to simplify Boolean function using Karnaugh map. But there is also a ProductofSums (POS) solution for each SOP solution, which sometimes be more useful depending on the application. In this simpliﬁcation, we use the maxterms of the function. A maxterm is a Boolean expression resulting in a ‘0’ for the output of a single cell expression, and 1s for all other cells in the Karnaugh map. Figure 4.45 shows the three variables Kmap. There is a single ‘0’ in a map and other cells are 1s. Therefore, 1s covers maximum area of Kmap. The maxterm is a ‘0’, not a ‘1’ in the – Karnaugh map. The maxterm is a sum term, A + B + C. The – equation of the map is O = A + B + C. The procedure for placing a maxterm in the Kmap is given below: Step1 Identify the sum term to be mapped. Step2 Write corresponding binary numeric value. Fig. 4.45 Three variables Kmap Step3 Form the complement Step4 Use the complement as an address to place a 0 in the Kmap Step5 Repeat for other maxterms – – – Consider a maxterm A + B + C. Numeric value 000 corre– – – sponds to A + B + C. The complement of 000 is 111. Then Place – – – a 0 for maxterm A + B + C in this cell (1, 1, 1) of the Kmap as – – – shown in Fig. 4.46. When A + B + C is (1¢ + 1¢ + 1¢), all 1s in, which is (0+0+0) after taking complements, we have the only condition that will give us a 0. All the 1s are complemented to Fig. 4.46 Three variables Kmap all 0s, which is 0 when OR operation is done.
Combinational Logic
Fig. 4.47 Three variables Kmap
149
A Boolean productofsums expression is multiple of – – – – – maxterms like O = (A + B + C) (A + B + C ). The maxterm – – (A + B + C) stands for numeric 001 and its complements is 110, – – – placing a 0 in cell (1,1,0). Similarly the maxterm ((A + B + C )) yields numeric 000 which complements to 111, placing a 0 in cell (1,1,1) as depicted in Fig. 4.47. At present, we are truly interested to simplify productofsums expression. Therefore, form the 0s into groups. According to Kmap as shown in Fig. 4.48, this can be a group of two cells. The binary value corresponding to the sumterm is (1, 1, X). In this case, both A and B are 1 for the group although C is both 0 and 1. Therefore, we can write an X as a place holder for C. Then we can write – – the sumterm (A + B) discarding the C and the X, which held its’ place.
The procedure for writing the productofsums simpliﬁcationusing Kmap Step1 Form largest groups of 0s possible, covering all maxterms. Groups must be a power of 2. Step2 Write binary numeric value for group. Fig. 4.48 Three variables Kmap Step3 Complement binary numeric value for group. Step4 Convert complement value to a sumterm. Step5 Repeat steps for other groups. Each group yields a sumterm within a productofsums result. Example 4.15
Simplify the productofsums Boolean expression using Kmap – – – – – – – – – – – O = (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D) (A + B + C + D)
� Solution Firstly, transfer the six maxterms to the Kmap as 0s. It is very clear from map that the ‘0’ entries in the map covering minimum area. To ﬁnd the proper cell location in the Kmap, it is required to complement the input variables. Once the cells are in proper place, form groups of cells as shown in Fig. 4.49. Larger groups will give a sumterm with fewer inputs. Fewer groups will yield fewer sumterms in the result. We have two groups. Therefore, POS expression has two sumterms. The group of 4cells yields a 2variable sumterm. The second group of 2cells give us two 3variable sumterms. The simpliﬁed function of the – – Fig. 4.49 Boolean expression is O = (A + C + D) (C + D). The ﬁnal result is product of the two sums.
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Digital Electronics: Principles and Applications
Example 4.16
Simplify the productofsums Boolean function as shown in Kmap
� Solution The minimal covering for the ‘0’ entries in the Kmap is shown in Fig. 4.50(a). After grouping we get the – simpliﬁed expression is O = (C + D)A .
Fig. 4.50
Fig. 4.50 (a)
The ﬁrst factor in the expression is form the grouping of entries in cells 2,6,10 and 14. The second factor is form the grouping of entries in cells 0, 1, 2, 3, 4, 5, 6, 7. Table 4.22
4.14 DON’T CARES
Truth table with don’t care state
Inputs Output A B C D O We know that output of a function is depends on input 0 0 0 0 0 variables. But in some cases, output does not matter on 0 0 0 1 1 combination of input variables. This is happened as input 0 0 1 0 1 0 0 1 1 0 combinations are invalid and the outputs corresponding 0 1 0 0 0 to these input combinations have no importance. These 0 1 0 1 0 types of input combinations are called, as don’t cares 0 1 1 0 1 and are shown in the truth Table 4.22. We use the symbol 0 1 1 1 1 1 0 0 0 0 ‘X’ in a cell that can be either 1 or 0. The same notation 1 0 0 1 1 is also used in Kmap. Figure 4.51 shows the Karnaugh 1 0 1 0 1 map with don’t care. Actually, don’t cares increase the 1 0 1 1 x versatility of the 1 1 0 0 x designer. In the K1 1 0 1 x 1 1 1 0 x map, ‘X’ entries are 1 1 1 1 x the don’t care entries. It may be either 1 or 0. Always designer chooses the value, which will make the simplest expression in both SOP and POS forms.
Fig. 4.51
Combinational Logic Example 4.17
151
Simplify the logic function F(A, B, C, D) = Sm (0, 1, 2, 5, 6, 8) + d(3, 4, 7, 14) using Kmap in SOP and POS form.
� Solution (a) SOP Expression The minimal covering for the 1 entries is shown in Fig. 4.52. We consider the don’t cares in cells 3, 4, 7, 14 as 1s and used in grouping of 1 entries. – –– – – The simpliﬁed SOP expression is F(A, B, C, D) = F1 + F2 + F3 = O = A + BCD + BCD.
Fig. 4.52
(b) POS Expression The minimal covering for the 0 entries is shown in Fig. 4.53. We consider the don’t cares in cells 3, 4, 7, 14 as 0’s and used in grouping of 0 entries. The simpliﬁed POS expression is F(A, B, C, D) = F1. F2 . F3 . F4 = O – – – – – – – = (C + D) (A + C ) (A + D) (B + C + D)
Fig. 4.53
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Digital Electronics: Principles and Applications
Figure 4.54 and 4.55 show the logic diagram of SOP and POS solution respectively. Now, we can compare between the productofsums solution and the sumofproducts solution. The SOP uses one three inputs OR gate and two three input AND gate, while the POS uses three two inputs OR gates, one three inputs OR gate, and one four input AND gate. For minimal cost solution, the SOP solution is simpler.
Fig. 4.54
Fig. 4.55
Example 4.18
Simplify the logic function F(A, B, C, D) = P (3, 5, 6, 11, 13, 14, 15) + d(4, 9, 10) using KMap in SOP and POS form.
� Solution (a) SOP Expression The minimal covering for the ‘1’ entries is shown in Fig. 4.56. We consider the don’t cares in cells 4,9,10 as 1s and used in grouping of ‘1’ entries. The simpliﬁed SOP expression is F(A, B, C, D) = F1 + F2 + F3 + F4 = –– –– – ––– – O = CD + A B C + A B D + A BCD.
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Combinational Logic
Fig. 4.56
(b) POS Expression The minimal covering for the ‘0’ entries is shown in Fig. 4.57. We consider the don’t cares in cells 4,9,10 as 0s and used in grouping of ‘0’ entries. The simpliﬁed POS expression is F(A, B, C, D) – – = F1. F2 . F3 . F4 . F5 = O = (A + B + C)(B + – – – – – – – C + D) (B + C + D) (A + D) (A + C ). Three – – – different group expressions, (A + B + C), (A + D) – – and (A + C ) are depicted in Fig. 4.57. When two – adjacent cells 6 and 14 are grouped, we get (B + – C + D). Similarly, if two adjacent cells 3 and 11 – – are grouped, we ﬁnd (B + C + D). Figure 4.58 and 4.59 show the logic diagram of SOP and POS solution respectively. Now, we
Fig. 4.58
Fig. 4.57
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Digital Electronics: Principles and Applications
can compare between the productofsums solution and the sumofproducts solution. The SOP uses one four inputs OR gate, one four inputs AND gate, two three inputs AND gate and one two inputs AND gate, while the POS uses three three inputs OR gates, two two inputs OR gate, and one ﬁve input AND gate. Therefore, the SOP solution becomes simpler.
Fig. 4.59
4.15
MINIMISATION OF SIMULTANEOUS FUNCTIONS
Figure 4.60 shows the block diagram of simultaneous function. It is a combinational logic circuit, which has multi inputs and multi outputs. X is the set of input variables X0, X1, X2, … to Xn and Y is the set of output variables F0, F1, F2 … Fn. The combinational logic circuit operates on the input variables X0, X1, X2, … to Xn and the output variables F0, F1, F2 … Fn. Here, the electronic circuit of combinational logic shown as the black box has ‘n’ different outputs F0, F1, F2 … Fn for the same Fig. 4.60 Simultaneous functions combination of inputs. Such circuits are called as multiple output circuits and the functions corresponding to the outputs (F0, F1, F2, … Fn) are called simultaneous functions. At this instant, the designer works on implementation of simultaneous functions with minimum hardware. Actually the designer reduces the output functions to their minimal forms, and then each output function will require minimum hardware. Though, there is a possibility of the hardware duplicity as some output functions have similar terms. In that case, all common terms of the output functions can be shared. Therefore, all common terms are detected and shared during hardware implementation of simultaneous functions. To minimise multioutput functions, essential prime implicants from the Kmap of the product of 2 functions at a time, then 3 functions at a time etc. should be taken into account depending on the number of functions.
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Combinational Logic
The example of simultaneous output function is given below: Two simultaneous output function are F1(A, B, C, D) = Sm(0, 1, 2, 3, 4) and F2(A, B, C, D) = Sm (1, 2, 3, 7, 14, 15). Figure 4.61 and 4.62 show the Karnaugh map for F1(A, B, C, D) = Sm (0, 1, 2, 3, 4) and F2(A, B, C, D) = Sm (1, 2, 3, 7, 14, 15) respectively. The functions F1 and F2 can be reduced to SOP –– ––– –– – –– forms using Karnaugh maps as F1 = A B + A C D and F2 = A B D + A B C + BCD + ABC
Fig. 4.61
Karnaugh map for F1
From the minimal expressions F1 and F2, we can say that two functions F1 and F2 should be implemented independently as there is no common term between F1 and F2. Luckily, the function F1 can also be expressed by one more minimal expression as given below: – –– –– ––– F1 (A, B, C, D) = A B C + A B C + A C D In this minimal expression of F1, it is very clear that there is a common expression in F1 and F2. During implementation of F1 and F2, the common term will be shared. In this way, the designer always ﬁnd out the common terms and able to design in most simple way. There are different methods to detect the sharing possibilities. The most common method is the construction of a map in which each output minterm F1 and F2 is AND operated with the corresponding minterms and the results placed on the third map. The third map represents all the minterms, which are common to the F1 and F2 functions. This shared term Kmap be able to draw using Table 4.23.
Fig. 4.62
Karnaugh map for F2
Table 4.23
The shared term
F1
F2
F1.F2
1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
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Digital Electronics: Principles and Applications
Example 4.19
Simplify the following simultaneous equations F1(A, B, C, D) = Σm(1, 2, 3, 4) and F2(A, B, C, D) = Σm (1, 2, 3, 7).
� Solution The Kmaps for F1, F2 and F1.F2 are depicted in Fig. 4.63(a), (b) and (c) respectively.
Fig. 4.63
(a) Karnaugh map for F1
Fig. 4.63 (b) Karnaugh map for F2
It is very clear from Kmap of F1.F2, the following terms: –– –– A B D and A B C are common to both F1 and F2 . Therefore, during deriving the minimal expressions of F1 and F2, these common terms are included as far as possible. The sub cubes of F1 and F2 are shown in Fig. 4.63. Then output functions for F1 and F2 are given below: –– –– – –– F1= A B D + A B C + A BCD –– –– – F2= A B D + A B C + A CD Unfortunately, the other common term could not be retained in the minimal expressions for F1 and F2 because if we would have tried to retain, the functions would not been minimal. Fig. 4.63 (c) Karnaugh map for F1.F2 The incompletely speciﬁed (with don’t cares) multiple output functions (simultaneous functions) can also be solved by the above method. However, solving of more than two incompletely speciﬁed functions becomes difﬁcult.
Example 4.20
Simplify the following simultaneous equations F1(A, B, C, D) = Σm(1, 2, 3, 4) + d(10, 11, 12) and F2(A, B, C, D) = Σm (1, 2, 3, 7) + d(8, 9, 10)
157
Combinational Logic � Solution The Kmaps for F1, F2 and F1.F2 are depicted in Fig. 4.64(a), (b) and (c) respectively.
Fig. 4.64 (a) Karnaugh map for F1
Fig. 4.64 (b)
Karnaugh map for F2
Table 4.24
Fig. 4.64 (c)
Karnaugh map for F1.F2
The Kmap for F1.F2 is drawn based on the Table 4.24 with shared terms. From the shared Kmap of –– –– F1.F2, the following common terms: A B D and A B C are obtained. When we write the function for F1 and F2, we have to keep in mind to include all common terms. The output functions are written as –– –– –– F1= A B D + A B C + BCD –– –– – F2= A B D + A B C + A CD
The shared term
F1
F2
F1.F2
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
X
0
0
X
0
X
X
X
X
0
0
X
0
0
0
0
0
0
0
0
0
0
0
4.16 VARIABLE MAPPING Variable mapping is a technique, which is used to achieve the minimal expression of the output function for large number of variables without Kmap. Consider the Boolean expression
158
Digital Electronics: Principles and Applications –– –
––
– –
–
F(ABCK) = A B C + A B C + A BC + A BC + ABCK. The above Boolean expression is a function of four variables A, B, C, and K. Hence a four variables Kmap can be used for reducing the function. But we interested to represent the said function using three variables Kmap. Therefore the above function can be mapped into three variables Kmap as shown in Fig. 4.65 which is based on Table 4.25. Table 4.25 Represent cell value and cell No.
Cell Value
Fig. 4.65
Three variable Kmap
–– – A BC –– ABC – – A BC – A BC –– AB C – AB C – ABC ABC
Cell No. 0 1 2 3 4 5 6 7
From the Kmap as shown in Fig. 4.65, we ﬁnd a 2 cell sub cube F1 and a 4 cell sub cube F2. Then the minimal expression is – F(ABCD) = K. F1 + F2 where F1 = BC and F2 = A – – = K. BC + A = A + K. BC Example 4.21 Simplify the following expression –– – – – – –– ABC D + ABC D + ABCD + A BCD + A B CD + ABCD � Solution The three variables KMap of the Boolean function –– – – – – –– ABC D + ABC D + ABCD + A BCD + A B CD + ABCD is shown in Fig. 4.66 and selection of the subcubes are also indicated in the same ﬁgure. The simpliﬁed from of this Boolean function is as follows –– – – – – –– ABC D + ABC D + ABCD + A BCD + A B CD + ABCD –– – – – – Fig. 4.66 Three variable Kmap of ABC D + = ABC (D + D) + ABC(D + D) + A (B – – – – – – – – – ABC D + ABCD + A BCD + A B CD + ABCD + B )CD (As D + D = B + B = 1) – – – – – – = ABC + ABC + A CD = AB(C + C) + A CD = AB + A CD ( As C + C = 1) The minimal expression from Kmap is – – F(ABCD) = F1 + F2 = AB + A CD where F1 = AB and F2 = A CD
159
Combinational Logic
4.17 TABULAR METHOD OF MINIMISATION The graphical method or Karnaugh map method is very convenient to obtain the minimal expression of a Boolean function relating with 3 or 4 variables only. But the difﬁculty arises with increasing the number of variables. When the number of variables increases, the visualisation of adjacent cells of the Karnaugh maps is very difﬁcult. Although, Karnaugh map method can also be used for 5 to 6 variables function. To overcome the visualisation difﬁculty, the tabular method is used for minimisation of a Boolean function of any number of variables. W.V.Quine and E.J.Mc Clusky developed the tabular method of minimisation and this method is known as Quine Mc Clusky method of minimisation. The tabular method depends upon combining adjacent cells. The procedure is in combining two adjacent cells, four adjacent cells and eight adjacent cells combination. This procedure is also applicable to search out combinations as big as possible. So a designer can develop a logic function using tabular method. Some deﬁnitions related with the Quine McClusky method of minimisation are discussed below:
Implicant An implicant is a simpliﬁed expression and can be obtained after combining the adjacent minterms of the set of minterms. There are two types implicants, namely, Prime implicants and Essential prime implicants. Prime implicant is an implicant when it is not a subset of another implicant of the function. A Prime implicants is called as essential prime implicants if it includes a cell, which is not incorporated in any other prime implicant. The logical function is ––– –– – – – – – – – F(ABCD) = AB C D + AB C D + AB CD + AB CD + A BC D + A BCD + ABCD + ABCD and the Kmap for this function is shown in Fig. 4.67. The logical expression of the said function is F (A, B, C, D) = F1 – – + F2 + F3 + F4 , where F1 = AB , F2 = A BD, F3 = BCD and F4 = AC. Here F1, F2, F3, and F4 are the prime implicants of the function F(ABCD). In this example, prime implicant F3 is not essential. Minimal SOP Form The minimal SOP form representation of a Boolean function is that the prime implicants can covered all 1’s in the Karnaugh map. When we want to choice one prime implicant from the two prime implicants, the simplest one should be selected. The set of prime implicants of the Karnaugh map as shown in Fig. 4.67 are F1, F2, F3, and F4. All prime implicants are unnecessary to represent function and some prime implicants are eliminated. The minimal function is now the sum of these selected prime implicants. Therefore, the procedure results in a minimal SOP form. But the minimal SOP expression is F(ABCD) = F1 + F2 + F3 + F4. The same method can be used for POS form using maxterms. The procedure of Quine McClusky Method is given below:
Fig. 4.67
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Digital Electronics: Principles and Applications
Step 1 i. ii.
Represent each minterms of the Standard SOP form of logic function by a binary code and its decimal equivalent. Form the groups containing the number of 1s in the binary code. Each group should have speciﬁed group number known as index number. In group0 of minterms, number of 1’s is zero; in group 1 minterms have a single 1; in group2, minterms have two 1’s; in group3, minterms have three 1s; and in group4, minterms have four 1s. Arrange all the minterms according to groups with ascending order of decimal number. For example, Table 4.26 shows the minterms with number of 1’s in binary code, group and variables.
Step 2 – iii. Apply the theorem, A + A = 1 in two minterms from adjacent groups. Here, two minterms are combined together if their binary representations differ by just a single bit. The combined term consists of the original binary representation, with the difference bit replaced by (–). Table 4.27 shows the combination of two minterms. The check mark (÷) is placed just after the each minterm, which has been combined with at least one term as depicted in Table 4.26. Step 3 iv. Four minterms of adjacent groups are combined if possibilities exist. In this case, dashes (–) exist in same position of two groups and only one position will be different. Table 4.28 shows the combination of four minterms. v. Combine eight minterms of adjacent groups if possibilities exist. For this case, position of two dashes (–) will be same and only one position will be different. Step 4 vi. Construct the table of prime implicants in which each column has a decimal number at the top in ascending order which corresponds to the minterms in the standard SOP form and each row represents the prime implicant. vii. Use a trick mark (÷) under each decimal number, which means the particular minterm is contained in the prime implicants represented by the row. viii. Find out all the columns, which contain a single trick mark (÷) and give a star mark (*) at the left of the rows. The star marked rows are called essential prime implicants. ix. Derive the minimal SOP logic function incorporating all essential prime implicants. x. Find out all prime implicants, which covers the maximum number of minterms and also include the prime implicants in the minimal SOP logic function. The examples of QuineMcClusky procedure are given below. Example 4.22
Simplify the Boolean function F = Sm (0, 1, 2, 7, 8, 9, 10, 11, 14, 15) using Quine McClusky method.
161
Combinational Logic �
Solution
Step1 The highest minterm is 15; therefore the function is a four variables function. Initially, the table is created representing all minterms, group and variables of the function. All the minterms are arranged ascending order considering numbers of 1’s in binary representation of minterms as shown in Table 4.26. Table 4.26
No. of 1’s
Group
Minterms A
Variables B C
0
0
0
÷
D
0
0
0
0
1
I
1 2 8
÷ ÷ ÷
0 0 1
0 0 0
0 1 0
1 0 0
2
II
9 ÷ 10 ÷
1 1
0 0
0 1
1 0
3
III
7 ÷ 11 ÷ 14 ÷
0 1 1
1 0 1
1 1 1
1 1 0
4
IV
15 ÷
1
1
1
1
Step2 The combinations of two minterms are shown in Table 4.27. The minterms, which are combined with other minterms, are tick (÷) marked in the Table 4.26. After the combinations of two minterms, the results consist of the original binary representation with different bit placed by ‘–’ as depicted in Table 4.27. Table 4.27
Combination 0,1 0,2 0,8
÷
1,9 2,10 8,9 8,10 9,11 10,14 7,15 11,15 14,15
÷
÷
÷ ÷ ÷ ÷ ÷ ÷
The combinations of two minterms
A
Binary Code B C
D
0 0 
0 0 0
0 0
0 0
1 1 1 1 1 1
0 0 0 0 0 1 1
0 1 0 1 1 1 1
1 0 0 1 0 1 1 
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Digital Electronics: Principles and Applications
Step3 Table 4.28 shows the possible combinations of four minterms. In four minterms, combination, two different combinations of two minterms are combined. Give the tick marked in Table 4.27 for two combinational minterms that are covered in combinations of four minterms. Some terms of Table 4.27 are not tick marked and these nontick marked terms are known as prime implicants. Table 4.28
The combinations of four minterms
Combination A
Binary Code B C
0,1,8,9

0
0

8,9,10,11 10,11,14,15
1 1
0 
1

D
Step4 The table of prime implicants is constructed for ﬁnding out the essential implicants. Table 4.29 shows the table of prime implicants. Table 4.29 Table of Prime Implicants
Prime Implicants 0,1
Minterms 0
1
÷
÷
2
7
8
÷
1,9
9
11
÷
÷
7,15*
÷
14,15 8,9,10,11* 10,11,14,15*
÷
÷
15
÷ ÷
8,9
0,1,8,9*
14
÷ ÷
2,10*
10
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
÷
To select the essential prime implicants, Table 4.29 is scanned all minterms in column wise. All the minterms, which have only one tick mark, contribute one essential prime implicants. In this table minterms 2, and 7 are essential prime implicants and put star (*) on these prime implicants. Then prime implicants are to be selected for the remaining minterms. The procedure is that select prime minterms, which cover maximum number of unaccounted minterms. There are three prime implicants which take care of these minterms are (0, 1, 8, 9); (8, 9, 10, 11) and (10, 11, 14, 15). Again put star marks at the proper places. The essential prime implicants are selected the star marked terms from Table. Hence the minimal form of the logic function is –– – – – F = B C + AB + AC + BCD + B CD
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Combinational Logic
Step5 The result can be veriﬁed by the help of Karnaugh map, Fig. 4.68. The simpliﬁed expression is F = F1 + F2 + –– – – – –– – – – F3 + F4 + F5 = B C + AB + AC + BCD + B CD, where F1 = B C, F2 = AB , F3 = AC, F4 = BCD and F5 = B CD.
Fig. 4.68 Karnaugh map for F
Simplify the function F = S(0, 1, 2, 3, 5, 9, 11) +d (4, 7, 15) using Quine Mclusky
Example 4.23
method and verify the result by Karnaugh map.
� Solution It is clear from the logic function that the highest minterm is 15. So, the function is a four variable function. This logic function has three don’t care entries. To derive the logic expression the procedure is same, but the last step is different one. In the last step the essential prime implicants are selected for compulsory terms.
Step1 Initially, the table is created representing all minterms and variables of the function. All the minterms are arranged increasing order considering numbers of 1’s in binary representation of minterms as given in Table 4.30. Table 4.30
No. of 1’s
Group
Minterms A
Variables B C
0
0
D
÷
0
0
0
0
0
1
I
1 2 4
÷ ÷ ÷
0 0 0
0 0 1
0 1 0
1 0 0
2
II
3 5 9
÷ ÷ ÷
0 0 1
0 1 0
1 0 0
1 1 1
3
III
7 ÷ 11 ÷
0 1
1 0
1 1
1 1
4
IV
15 ÷
1
1
1
1
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Digital Electronics: Principles and Applications
Step2 Table 4.31 shows the allpossible two minterms combinations. The result of combinations of two minterms consists of the original binary representation with different bit placed by ‘–’ as depicted in the same table. The minterms, which are combined with other minterms, are tick marked in the Table 4.30. Table 4.31
Combinations of two minterms
Combination A
B
Binary Code C
0 0 
0 0
0 0
0 0 0 1 0 1 0 1
0 0 1 0 1 1 1 1
1 1 1 1 1 1 1 1 1 1
0,1 0,2 0,4
÷ ÷ ÷
0 0 0
1,3 1,5 1,9 2,3 4,5 3,11 3,7 5,7 9,11 11,15 7,15
÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷
0 0 0 0 0 0 1 1 
D
Step3 Table 4.32 gives possible combinations of four minterms. There is no possibility of combinations of eight minterms. Table 4.32 Combinations of four minterms
Combination
Binary Code A
B
C
D
0,1,2,3 0,1,4,5
0 0
0 
0

1,5,3,7 1,3,9,11 3,7,11,15
0 
0 
1
1 1 1
Step4 Table 4.33 is constructed to ﬁnd out the essential implicants.
165
Combinational Logic Table 4.33
Prime Implicants
0 ÷
0,1, 2,3*
Table of prime implicants
1
2
Minterms 3
÷
÷
÷
5
0,1,4,5*
÷
÷
÷
0,1,5,7
÷
÷
÷
1,3,9,11* 3,7,11,15
÷
÷
9
11
÷
÷
÷
÷ ÷
9,11
÷ ÷
11,15
The procedure of selection prime minterms is to cover maximum number of minterms. There are three prime implicants (1, 3, 9, 11); (0, 1, 2, 3) and (0, 1, 4, 5) which cover all compulsory minterms (0, 1, 2, 3, 5, 9, 11). Then put star marks at the proper places of the three prime implicants. Hence the minimal form of the logic function is –– – –– F = AB + BD + A C
Step  5 The result can be veriﬁed by the help of Karnaugh map, Fig. 4.69. The simpliﬁed expression is F = F1 + F2 –– – –– –– – –– + F3 = A B + B D + A C , where F1 = A B , F2 = B D and = F3 = A C .
Fig. 4.69 Karnaugh map for F
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Digital Electronics: Principles and Applications
Example 4.24
Simplify the function F = S(1, 2, 3, 6, 7, 8, 10, 11, 12, 14, 17, 18, 20, 21, 22, 24, 28, 29, 31) using Quine Mclusky method
�
Solution
In the logic function, the highest minterm is 31. Therefore, the logic function is a ﬁve variables function. To derive the logic expression, the procedure is same as given below:
Step1 Initially, the table is created representing all minterms and variables of the function. All the minterms are arranged increasing order considering numbers of 1’s in binary representation of minterms as illustrated in Table 4.34. Table 4.34
No. of 1’s
Group
Minterms A
Variables B C D
1
I
1 2 8
÷ ÷ ÷
E
0 0 0
0 0 1
0 0 0
0 1 0
1 0 0
2
II
3 6 10 12 17 18 20 24
÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷
0 0 0 0 1 1 1 1
0 0 1 1 0 0 0 1
0 1 0 1 0 0 1 0
1 1 1 0 0 1 0 0
1 0 0 0 1 0 0 0
3
III
7 11 14 21 22 28
÷ ÷ ÷ ÷ ÷ ÷
0 0 0 1 1 1
0 1 1 0 0 1
1 0 1 1 1 1
1 1 1 0 1 0
1 1 0 1 0 0
4
IV
29
÷
1
1
1
0
1
4
IV
31
1
1
1
÷
Step2 Table 4.35 shows the combinations of two minterms. The minterms, which are combined with other minterms, are tick marked in the Table 4.34.
167
Combinational Logic Table 4.35
Combinations of two minterms
Combinations 1,3 2,3 2,6 3,7 8,10 8,12 10,11 10,14 18,22 20,21 20,22 24,28 28,29 29,31 1,17 8,24 12,28 2,18 6,22
÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷ ÷
÷ ÷ ÷ ÷
A
B
0 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
1 1 1 1 1 1 
Binary Code C
D
E
0 0 0 0 
1 1 1 0 1 1
1 0 1 0 0 0
0 0 0 1 1 1
1 1 1 1
1 0 0 0 
0 0 0 1
0 1 1 0 0
0 0 1 0 1
0 0 0 1 1
1 0 0 0 0
Step3 All possible combinations of four minterms are shown in Table 4.36. There is no possibility of an eightcell combination. Table 4.36 Combinations of four minterms
Combinations 2,3,6,7 2,6,10,14 8,10,12,14 20,21,28,29 8,12,24,28 2,6,18,22
A
B
Binary Code C
0 0 0 1 
0 1 1 0
1 
Step4 To choose the essential implicant Table 4.37 is constructed
D
E
1 1 0 0 1
0 0 0 0
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Digital Electronics: Principles and Applications Table 4.37
Prime Implicants
1
2,3,6,7*
2
3
6
7
÷
÷
÷
÷
8
÷
2,6,10,14*
Table of prime implicants
10 11
Minterms 12 14 17 18 20 21 22 24 28 29 31
÷
÷
÷ 8,10,12,14 20,21,28,29* 8,12,24,28* 2,6,18,22* 1,17* 10,11* 29,31*
÷
÷
÷
÷ ÷
÷ ÷
÷
÷
÷
÷
÷
÷
÷ ÷
÷
÷
÷ ÷
÷ ÷
÷
In this table, minterms 1, 11, 17, and 31 are essential prime implicants and put star (*) on these prime implicants. Then prime implicants are also be selected for the remaining minterms. The procedure is that select prime minterms, which cover maximum number of unaccounted minterms. There are ﬁve prime implicants which take care of these minterms are (2, 3, 6, 7), (2, 6, 18, 22), (2, 6, 10, 14), (8, 12, 24, 28) and (20, 21, 28, 29). Then put star marks at the proper places. The essential prime implicants are selected from the star marked terms of the Table 4.37. Hence, the minimal form of the logic function is ––– – – –– – – – – – –– F = B C DE + A BC D + ABCE + A B D + B DE + A DE + ACD + BD E
SUMMARY In this chapter, the basic combinational logic function and its element are discussed. The circuit development of combinational logic function is explained. The logic circuit can be designed by the Canonical sum of product (SOP) and Canonical product of sum (POS) methods. The Canonical sum of products (SOP) represent in AND – OR circuit but Canonical product of sums (POS) can be represented in OR – AND circuit. The sum of product and product of sum expressions of any truth table have been explained. These SOP and POS expressions can be simplified by using Boolean algebra as designer select the simplest circuit for low cost and high reliability. To design a most simplified logic circuit using Boolean algebra is a tedious work. The Karnaugh method is substitute of logic simplification by converting a truth table into a Karnaugh map. The greatest simplified Boolean expression of a truth table is possible in this case. Sum of product form and product of sum expressions of a truth able using Karnaugh map are possible. Three, four, five and six variables Karnaugh maps are illustrated in this chapter. It is very inconvenient to use Karnaugh map to simplify logic function if number of variables are more than six. Then QuineMcCluskey method used for large number of variables and this method has been explained with examples. The simultaneous functions are also incorporated in this chapter.
MULTIPLE CHOICE QUESTIONS 1.
2.
A Karnaugh map is used for (a) Minimising Boolean expressions (c) Develop digital circuits (b) Computer interface (d) None of these Which of the following could be used to detect a potential static hazard when designing a combinational logic circuit? (a) Karnaugh map (b) Truth table (c) State table (d) None of these
Combinational Logic 3.
4. 5. 6. 7. 8. 9.
In addition to minimising logic expressions, a Karnaugh map can also be used for (a) Static hazard detection (c) Synchronous circuit design (b) Sequential logic circuit design (d) None of these A four variables Karnaugh map contains (a) 4 cells (b) 8 cells (c) 16 cells (d) 32 cells A ﬁve variable Karnaugh map contains (a) 4 cells (b) 8 cells (c) 16 cells (d) 32 cells Quine McCluskey method uses (a) Tabular Method (b) Karnaugh map (c) Boolean Algebra (d) None of these AND –OR realisation is equivalent to (a) SOP (b) POS (c) Kmap (d) None of these OR  AND realisation is equivalent to (a) SOP (b) POS (c) Kmap (d) None of these What is the simpliﬁed Boolean expression for Kmap (Fig.4.70) in SOP?
Fig. 4.70
10. 11.
12. 13.
– (a) AB (b) BC (c) A C (d) None of these What is the simpliﬁed Boolean expression for Kmap (Fig.4.70) in POS? – – (a) B + C (b) A + C (c) C(A + B) (d) None of these The minimisation of logic expression is done due to (a) Reduce space (c) Reduce number of gates (b) Reduce cost (d) All of these – –– – The simpliﬁed form of logic expression AB + A B + A B + AB is (a) 1 (b) A (c) AB (d) None of these – – – – The simpliﬁed form of logic expression A BC + ABC + A BC + ABC is (a) B (b) A + BC (c) C (d) None of these
REVIEW QUESTIONS 4.1. 4.2. 4.3.
Deﬁne SOP and POS. What is the difference between SOP and POS? Write the standard SOP form for the following logic functions given below: –– – ––– –– – – a) AB + BC b) C D + A B c) A B C + ABCD + BC d) A B D + A D + B D Write the standard POS form for the following logic functions given below: – – – – a) (A + B) (B + C) (c) (A + B + C) (B + C + D) (B + C ) – – – – – – – – – – b) (A + B+ C) (A + B + D) (B + C) d) (A + C + D) (B + C + D) (A + C )
169
170 4.4
Digital Electronics: Principles and Applications Determine Boolean function of the truth table 4.38 in terms of minterms and draw logic diagram using NAND gate. Table 4.38
4.5.
A
B
Inputs C
D
Output O
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1
Determine Boolean function of Table 4.39 in terms of maxterms and draw logic diagram using NOR gate. Table 4.39
4.6.
4.7.
4.8.
A
Inputs B
C
Output O
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 1 0 0 1 1 0 0
Make truth table for the following logic functions: a) F1(A, B, C, D) = Sm(0, 1, 2, 3, 5, 7, 11, 15) b) F1(A, B, C, D) = Sm(1, 3, 5, 11, 15) + d(0, 1, 4, 7) c) F1(A, B, C, D) = P( 2, 3, 5, 6, 13, 14) d) F1(A, B, C, D) = P( 5, 6, 11,12,13, 14) + d(7,15) Simplify the following logic expression using Boolean algebra: (a) F1(ABCD) = Sm(0, 2, 3, 4, 8, 9, 11, 15) (b) F1(ABCD) = Sm(1, 3, 5, 8, 9, 11, 15) + d( 7, 13) (c) F1(ABCD) = P( 2, 4, 10, 12, 13, 14) (d) F1(ABCD) = P( 1, 2, 6, 7,13, 14, 15) +d(0, 3, 5) Explain the two, three and four variables Kmap and their applications to reduce logic functions with examples.
Combinational Logic
171
4.9. 4.10.
What are the advantages of Kmap method reduction? Draw the Karnaugh map for the following logic functions: (a) F1(A, B, C, D) = Sm( 1, 2, 3, 5, 11, 15) (b) F1(A, B, C, D) = Sm(1, 5, 9, 11, 13, 15) + d(3, 7) (c) F1(A, B, C, D) = P( 0, 2, 3, 4, 5, 6, 13, 14) (d) F1(A, B, C, D) = P( 0, 4,6, 11,12,13) + d(7, 14, 15) 4.11. Make a Karnaugh map of the following functions and derive the expression in SOP form: (a) F1(A, B, C, D) = Sm(0, 1, 2, 4, 5, 6, 13, 15) (b) F1(A, B, C, D) = Sm( 5, 8, 9, 11, 13,15) + d( 7,12) (c) F1(A, B, C, D) = P( 2, 3, 5, 6, 10, 11, 13, 15) (d) F1(A, B, C, D) = P( 1,5, 8, 9, 10,11 ) + d(0,4) 4.12. Make a Karnaugh map of the following functions and derive the expression in POS form: a) F1(A, B, C, D) = Sm(0, 2,3, 4, 8, 9, 10, 11, 13, 15) b) F1(A, B, C, D) = Sm( 5, 8, 9, 11, 12, 13,15) + d( 0, 1, 3, 7) c) F1(A, B, C, D) = P( 0, 1, 2, 3, 5, 6, 10, 11, 13, 15) d) F1(A, B, C, D) = P( 0, 1,5, 8, 9, 10,11 ) + d(2,4) 4.13. What are simultaneous functions? Why simultaneous functions are used in digital systems?. 4.14.
4.15.
Minimise the following simultaneous functions: (a) F1 (A, B, C, D) = Sm(0, 2,3, 4, 8, 9, 10, 11, 13, 15) F2 (A, B, C, D) = Sm(5, 8, 9, 11, 12, 13,15) + d( 0, 1, 3, 7) (b) F1 (A, B, C, D) = P(0, 1, 2, 3, 5, 6, 10, 11, 13, 15) F2 (A, B, C, D) = P(0, 1,5, 8, 9, 10, 11 ) + d(2,4) (c) F1 (A, B, C, D) = Sm(1, 2, 3, 5, 11, 15) F2 (A, B, C, D) = Sm(1, 5, 9, 11, 13, 15) + d(3, 7) d) F1 (A, B, C, D) = P( 0, 1, 2, 3, 5, 6, 10, 11, 13, 15) F2 (A, B, C, D) = P( 0, 1,5, 8, 9, 10,11 ) + d(2,4) Explain variable mapping with examples.
4.16.
Simplify the following expressions using variable map: – –– – – – – – – (a) AB D + A BC + ABD + A BC (c) (A + B + D ) (A + B + D) (A + B + C) – –– –– – – – (b) ABC + ABD + C D + ABC D (d) D(A + B + C) (A + B + C)
4.17.
What are the advantages of Tabular method over Kmap method in minimisation of logic functions?
4.18.
Minimise the following functions using QuineMcClusky tabular method: (a) F1(A, B, C, D) = Sm( 1, 2, 3, 5, 11, 15) (b) F1 (A, B, C, D) = Sm(5, 8, 9, 11, 12, 13,15) + d( 0, 1, 3, 7) (c) F1 (A, B, C, D) = Sm(1,2, 3, 4, 5,6, 7, 10, 11, 15, 18, 19, 20, 21, 22, 23, 25, 26, 27) (d) F1 (A, B, C, D) = Sm(1, 2, 3, 5,6, 10, 11, 15, 18, 19, 20, 21, 22, 23, 25, 26, 27, 31) + d(4, 7, 30)
CHAPTER
5 COMBINATIONAL LOGIC DESIGN 5.1
INTRODUCTION
The general logic gates AND, OR, NAND, NOR and NOT are commonly used in combinational logic circuit design using Karnaugh map and QuineMc Cluskey minimisation method. But practically, NOR and NAND universal gates are used to implement combinational logic circuits. SmallScale Integration (SSI) circuits are available to implement logic circuits. As medium and largescale integrated circuits are introduced, the conventional logic circuits designs have been changed. Traditionally, the design engineer has developed a Boolean equation to solve a particular problem. Then this function has been minimised and implemented using SSI ICs. If combinational logic circuits may have a large number of inputs and outputs, the use of truth tables in the design of such circuits is impractical. Furthermore, it is not economical to provide sufﬁcient pins on an IC package to allow access to each of the gates. Many functions, such as counting, addition, parity checking are common in a large number of designs and a useful library of digital circuits for implementing these functions has been developed. As a fabrication techniques improved daybyday, it became possible to implement these functions on a single chip. There is an array of devices, such as multiplexers, demultiplexers, adders, parity generators and checkers, decoders, and comparators. These devices signiﬁcantly reduce the number of ICs and the system cost. Therefore, the system design becomes simpliﬁed. This improves the reliability of the system by reducing of external wired connections. The development of MSI circuits has led to the technique of splitting complex design into a number of subsystems. The designer has the task of interconnecting available MSI circuits in such a way that satisﬁes the design speciﬁcation.
5.2
COMBINATIONAL LOGIC DESIGN
In the combinational logic circuit design process, the logic designer initially deﬁnes the input variables for representing all conditions. The system may be single output or multioutputs. Consequently, the designer must assign the output variables. After assigning the input variables and output variables, the designer writes the truth table to represent all combinations of input and output variables. The designer builds up the Boolean expressions in canonical sum of product (SOP) or Fig. 5.1 Block diagram of a canonical product of sum (POS) form. The written Boolean expression combinational logic circuit may be or may not be minimised form. Therefore, the equations should
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Combinational Logic Design
be expressed in the minimum SOP and POS form. Finally, the designer implement the logic expressions by electronics circuits, namely AND, NAND, OR, NOR and NOT gates; MSI chips explicitly decoders, encoders, multiplexers and demultiplexers. Figure 5.1 shows the block diagram of a typical combinational logic circuit with three inputs A0 , A1 , A2 and one output O. Example 5.1
Design a fulladder circuit using gates.
� Solution Step  1: The block diagram of fulladder is shown in Fig. 5.2. The two inputs A and B will be added with the carry from previous stage CIN. Therefore, three input variables A, B and CIN are considered for combinational logic circuit. There are two outputs sum(S) and carry output (COUT). Fig. 5.2
Step  2: The truth table of full adder is shown in Table 5.1 Table 5.1
Block diagram of full adder circuit design
Truth table of full adder
CIN
Inputs B
A
Outputs S COUT
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
Step  3: The outputs S and COUT can be expressed in SOP and POS form respectively as given below: S = F(A, B, CIN) = S(1, 2, 4, 7) = ’(0, 3, 5, 6) COUT = F(A, B, CIN)=Σ(3, 5, 6, 7) = ’(0, 1, 2, 4) The above Boolean expressions can be minimised by using Kmap. Figure 5.3 shows the Kmap for sum(S) COUT).
Fig. 5.3 Kmap for sum (S)
Fig. 5.4
Kmap for carry output (COUT)
– – —— – – S = F(A, B, CIN) = CIN A B + CIN AB + CIN AB + CIN AB –– – – – = CIN (AB + A B ) + CIN (A B + AB ) ——— – = CIN (A ≈ B ) + CIN (A ≈ B) = C ≈ B ≈ A COUT = F(A, B, CIN) = AB + CINB + CINA Step  4 : Implementation of the circuit using logic gates. Figure 5.5 shows the implementation of full adder using EXOR, AND and OR gates.
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Digital Electronics: Principles and Applications
Fig. 5.5
5.3
Implementation of full adder using gates
Fig. 5.6
Block diagram of 2 line to 4 line decoder
DECODERS
Decoder is a combinational logic circuit which has ‘n’ inputs and one output out of 2n outputs. For example, if there are two inputs, the decoder asserts one of the four outputs depending upon inputs. Figure 5.6 shows the block diagram of 2 to 4 line decoder. Here, A and B are two inputs and E stands for chip enable. O0, O1, O2 and O3 are the outputs of decoder.
5.3.1
Fig. 5.7
Basic structure of a 2 to 4 line decoder
2:4 Decoder
The structure of 2 to 4 line decoder is depicted in Fig. 5.7. Four NAND gates are used for this decoder. If the input is 00 (A=0 and B=0), output O0 will be asserted; if input is 01(A=0 and B=1), output O1 will be asserted and so on. Table 5.2 shows the truth table of 2:4 decoder. For any combination of inputs, only one output will be low and other outputs will be high. Therefore, decoder selects only one output at a time. Similarly, 3:8, 4:16 and 5:32 decoder can be made using logic gates and also in terms of ICs.
5.3.2 3:8 Decoder The IC 74138 is 3 to 8 line decoder. When this IC is enable, the selected output then depends upon the input combination of A, B and C. For example, when Table 5.2 Truth table of 2 to 4 line decoder C=0 and B=A=1, output O6=0 and all the other outputs Inputs Outputs are 1 as depicted in Table 5.3. Table 5.4 can also be E A B O0 O1 O2 O3 used as 3:8 decoder, if the output O6=1 and all the other 0 0 0 0 1 1 1 outputs are 0 for the same input combination C=0 and 0 0 1 1 0 1 1 B=A=1. The equations for each output of the decoder 0 1 0 1 1 0 1 can be represented by minterms and maxterms. The 0 1 1 1 1 1 0 truth tables of 3:8 decoder for minterm and maxterm 1 x x 1 1 1 1 representation are shown in Table 5.5 and Table 5.6 respectively. The structure of 3 to 8 line decoder using NAND is depicted in Fig. 5.8. Eight NAND gates are used for this decoder. If the input is 001, output O1 will be asserted. Similarly, if input is 101, output O5 will be asserted and so on. The implementation 3 to 8 line decoder using AND is given in Fig. 5.9.
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Combinational Logic Design
Fig. 5.9 3 line to 8 line decoder using AND gates
Fig. 5.8 3 line to 8 line decoder using NAND gates Table 5.3
Truth table of 3 to 8 line decoder using NAND gates
A
Inputs B
C
O0
O1
O2
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1
1 1 0 1 1 1 1 1
Table 5.4
Inputs A B C 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0
A
Inputs B
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Product term –– – A BC –– A BC – – A BC – ABC –– ABC
Outputs O3 O4 1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 1
O5
O6
O7
1 1 1 1 1 0 1 1
1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 0
Truth table of 3 to 8 line decoder using AND gates
C
O0
O1
O2
Outputs O3 O4
0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Table 5.5 Minterms of three variables
Symbol m0 m1 m2 m3 m4
m0
m1
m2
1 0 0 0 0
0 1 0 0 0
0 0 1 0 0
O5
O6
O7
0 0 0 0 0 1 0 0
0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 1
Minterms m3 m4 0 0 0 1 0
0 0 0 0 1
m5
m6
m7
0 0 0 0 0
0 0 0 0 0
0 0 0 0 0 (Contd...)
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Digital Electronics: Principles and Applications
Table 5.5 1 0 1 1 1 0 1 1 1
(Contd...) – AB C – ABC ABC
m5 m6 m7
0 0 0
0 0 0
Table 5.6
Inputs ABC
Sum Term
Symbol
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
A+B+C – A+B+C – A+B+C – – A+B+C – A +B+C – – A +B+C – – A +B+C – – – A +B+C
M0 M1 M2 M3 M4 M5 M6 M7
0 0 0
0 0 0
0 0 0
1 0 0
0 1 0
0 0 1
M5
M6
M7
1 1 1 1 1 0 1 1
1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 0
Maxterms of three variables
M0
M1
M2
0 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1
1 1 0 1 1 1 1 1
5.3.3
Maxterms M3 M4 1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 1
4:16 Decoder
4:16 decoder can be implemented similar to 3:8 decoders. Figure 5.10 shows the 4:16 decoder. This has 4 inputs and 16 outputs. In this decoder also, only one output will be low at a time. For example, if input is 1000, output O8 will be low and other outputs will be high. The truth table of 4:16 decoder is shown in Table 5.7. This 4 : 16 decoder can be used for converting any 4bit code, which is used to represent the decimal digits to give decimal output. Fig. 5.10 4 line to 16 line decoder Table 5.7
Inputs A B C D 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Truth table of 4 to 16 line decoder
O0
O1
O2
O3
O4
O5
O6
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
Outputs O7 O 8 O 9 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
O10 O11 O12 O13 O14 O15 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Combinational Logic Design
177
The IC 74154 is a 4 line to 16line decoder. The PIN conﬁguration and logic diagram of IC74154 are shown in Fig. 5.11 and 5.12 respectively. The 74154 decoder has four address inputs (A0, A1, A2, A3) and gives 16 mutually exclusive active low outputs (Q–0, Q–1 …… Q–15). The 2inputs Enable (E0, E1) gate can be used to strobe the decoder to eliminate the normal decoding “glitches” on the outputs, or it can be used for expansion of the decoder. The enable gate has two AND’ed inputs, which must be Low to enable the outputs. In 74154, one of the Enable inputs is used as the data input and the other Enable is Low, the addressed output will follow the state of the applied data.
5.3.4
Cascading Decoders
Two or more decoders can be combined to produce a decoder with large number of input bits by using the enable bit of decoder. The cascade Fig. 5.11 Pin conﬁguration combination of two 2 line to 4 line decoder to develop a 3 to 8 line decoder is of IC 74154 shown in Fig. 5.13. An input variable is used as an enable input of the ﬁrst decoder and the complement of the same input variable is attached to the enable input of the second decoder. The most signiﬁcant input variable can be used to select which decoder is enabled and lower input variables are fed to each decoder. It is depicted in Fig. 5.13 that E is enable input and A, B are lower input variables. A block diagram of a 4 line to 16 line decoder is also depicted in Fig. 5.14 and it consists of ﬁve 2 to 4 line decoders. Fig. 5.12 Logic Diagram of IC 74154
Fig. 5.13 3 line to 8 line decoder using two 2 line to 4 line decoders.
Fig. 5.14 4 line to 16 line decoder using ﬁve 2 line to 4 line decoders
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Digital Electronics: Principles and Applications
Example 5.2
Design a 4 line to 16 line decoder using 3 line to 8 line decoder.
� Solution Figure 5.15 shows the implementation of a 4 line to 16 line decoder using 3 line to 8 line decoder where four inputs are A,B, C and Enable(E) and 16 outputs D0 to D15.
Fig. 5.15 4 line to 16 line decoder using 3 line to 8 line decoder
5.3.5 Applications of Decoders Decoders can produce either all the minterms or maxterms for ‘n’ input variables. A decoder can be used to realise any Boolean function of ‘n’ input variables with the help of an OR gate in sum of product (SOP) representation or a AND gate in product of sum (POS) representation. For example, consider a four variable Boolean function F(A, B, C, D) = Sm(0, 1, 2, 3, 4, 5, 7). The Boolean function can be expressed by F = m0+m1+m2+m3+m4+m5+m7 The inversion of the above Boolean function is F¢ = m0 + m1 + m2 + m3 + m4 + m5 + m7 – m – m – m – m – m – m – =m 0 1 2 3 4 5 7 The IC74154 can be used to implement the above logic using a NAND gate as shown in Fig. 5.16.
Fig. 5.16 Combinational logic circuit implementation for Σm(0,1,2,3,4,5,7)
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Combinational Logic Design
Example 5.3
Design combinational logic circuits for the logic functions F1, F2 and F3 as given below using 4:16 decoder IC 74514.
F1=Sm(1,2,3,4,5,7);
F2=Sm(2,4,7,9,11); F3=Sm(10,12,14,15)
� Solution The IC 74514 has an enable terminal, E. When E is low logic level, the IC is active and A, B, C and D input variables are used for addressing the output terminal. The logic function F1=Sm(1,2,3,4,5,7) can be written in minterm representation as F1= m1 + m2 + m3 + m4 + m5 + m7 and its complement – m – m – m – m – m –. F1¢= m 1 2 3 4 5 7 This logic function can be implemented using an IC74154 and a six inputs NAND gate as depicted in Fig. 5.17. Similarly, F2 and F3 are also represented by minterm equations and implementation circuits are also illustrated in Fig. 5.17.
Fig. 5.17 Implementation of combinational logic circuits of F1=Σm(1,2,3,4,5,7),
F2=Σm(2,4,7,9,11) and F3=Σm(10,12,14,15)
5.3.6
Binary Adder Using Decoder
Figure 5.18 shows the block diagram of full adder circuit. In the full adder circuit there are three inputs A, B, and CIN, where A and B are two inputs which are added and CIN is the carry from the previous stage. The sum (S) and carry output (COUT) are obtained from the addition of A,B and CIN. The truth table of summation of two numbers with carry is shown in Table 5.8. The sums and COUT can be Fig. 5.18 Block diagram of full adder circuit represented by minterm functions as given below: S=F(A,B,CIN)=Sm(1,2,4,7) and COUT=F(A,B,CIN)=Sm(3,5,6,7). Figure 5.19 shows the implementation of full adder using decoder. Table 5.8 Truth table for binary adder
CIN
A
B
COUT
S
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 0 1 1 1
0 1 1 0 1 0 0 1
Fig. 5.19
Binary adder using decoder
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Digital Electronics: Principles and Applications
5.3.7
BCD to 7 Segment Display
The seven segment display widely used in calculators, digital watches, and measuring instruments, etc. Generally light emitting diode (LED), liquid crystal display (LCD) segments provide Fig. 5.20 (a) Segment identiﬁcation and (b) numerical displays the display output of numerical numbers and characters. To display any number and character, sevensegment display is most commonly used. Figure 5.20(a) shows the segment identiﬁcation and display of decimal numbers 0 to 9 is given in Fig.5.20(b). The light emitting diodes emit light when anode is positive with respect to cathode. There are two possible connections of light emitting diodes namely common anode and common cathode. In common anode connection, seven anodes are connected to a common voltage and cathode will be controlled individually to get the proper display. But in common cathode connection, anodes can be controlled individually for display when all cathodes are connected to a common supply. Fig. 5.21 Block diagram of seven Figure 5.21 shows the block diagram of 7segment display. segment display The decimal number 0 to 9 can be displayed by the binary coded decimal input. For example, the segments a, b, c, d, e, and f will be bright for decimal number 0.Table 5.9 shows the different segments will be bright for decimal number 0 to 9. Using the truth table, the Kmap for each segment is drawn and derives the minimised Boolean expression. Then the circuit is implemented by using decoder circuit. The Boolean expressions of each output functions can be written as given below: Table 5.9
Truth table for seven segment display
Decimal Number
Inputs A
B
C
D
a
b
c
Outputs d
e
f
g
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 1 1 0 1 0 1 1 1 x x x x x x
1 1 1 1 1 0 0 1 1 1 x x x x x x
1 1 0 1 1 1 1 1 1 1 x x x x x x
1 0 1 1 0 1 1 0 1 0 x x x x x x
1 0 1 0 0 0 1 0 1 0 x x x x x x
1 0 0 0 1 1 1 0 1 1 x x x x x x
0 0 1 1 1 1 1 0 1 1 x x x x x x
Combinational Logic Design
181
a=F1(A,B,C.D)=Sm(0,2,3,5,7,8,9) b=F2(A,B,C.D)=Sm(0,1,2,3,4,7,8,9) c=F3(A,B,C.D)=Sm(0,1,3,4,5,6,7,8,9) d=F4(A,B,C.D)=Sm(0,2,3,5,6,8) e=F5(A,B,C.D)=Sm(0,2,6,8) f=F6(A,B,C.D)=Sm(0,4,5,6,8,9) g=F7(A,B,C.D)=Sm(2,3,4,5,6,8,9) Figure 5.22 shows the pin conﬁguration of IC 7447 and logic diagram of IC 7447 is depicted in Fig. 5.23. The pin description of IC Fig. 5.22 Pin conﬁguration of 7447 is given below: IC 7447 A0 – A3 BCD inputs — Ripple blanking RB 1 — LT Lamp test input — —— BI /RBO Blanking input/Ripple blanking output Segment outputs a– – – The IC 7447 decodes the input data given in the truth Table 5.9. IC 7447 is BCD to 7Segment Decoder with opencollector outputs. The 74LS47 has four input lines of BCD(8421) data, and it generates their complements internally. Then decoder decodes the data with seven AND/OR gates having opencollector outputs to drive indicator segments directly. Each segment output sinks about 24 mA in the ON/LOW state and can withstand up to 15V in the OFF/HIGH state. Some auxiliary inputs namely ripple Fig. 5.23 Logic diagram of IC 7447 blanking, lamp test and cascadable zerosuppression functions are also provided in IC 7447. Zero suppression logic is very useful in multi seven segment decoders. Zero suppression is possible in different ways, namely leading zero suppression and trailing zero suppression. Leading zero suppression is blanking of zeros on the front of the number and trailing zero suppression is blanking of the zeros after the number. Figure 5.24 shows the block diagram Fig. 5.24 Block diagram of 4digit display of of fourdigit display. The most signiﬁcant leading zero suppression
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Digital Electronics: Principles and Applications
digit (MSD) is always blank if BCD inputs are zero and the blanking input is HIGH. The next higher order digit is also blank as blanking output is HIGH. The ripple blanking output indicates that it has BCD inputs 0 and higher order digits are 0. The blanking output is connected to the blanking input of the next decoder. Then other two digits are displayed. To display the digits of the right side of decimal point, trailing zero suppression is used. The lowest order digit will be blank when BCD input 0. Figure 5.25 shows the block diagram Fig. 5.25 Block diagram of 4digit display of trailing of 4 digit display for trailing zero zero suppression suppression. The blanking output of one decoder is connected to the blanking input of the next decoder. Here, the lowest order digit is blanked, as its BCD input is 0. The next digit is also blanked, as blanking input is HIGH and BCD input is 0. Subsequently remaining two bits are displayed.
5.3.8 BCD to Decimal Decoder The BCD to decimal decoder converts BCD (8421) code into one of the decimal digits 0 to 9. It is also called as 4 line to 10 line decoder. Truth table of BCD to decimal decoder is shown in Table 5.10 and it is implemented by using BCD to decimal decoder IC 7442.The 74HC/HCT42 are highspeed Sigate CMOS devices and are pin compatible with low power Schottky TTL. Figure.5.26(a) shows the pin conﬁguration of IC 7442 and logic symbol of IC 7442 is depicted in Figure.5.26(b). The pin description of IC 7442 is given below: A0 to A3 data inputs data outputs Y0 to Y9 positive supply voltage VCC GND ground The 74HC/HCT42 decoders have four active BCD inputs and provide ten mutually exclusive active outputs. The logic design of the IC 7442 is such that all outputs are HIGH when binary codes greater than nine are applied to the inputs. Figure 5.27 shows the logic diagram of BCD to decimal decoder. The most signiﬁcant input(A3) generates an useful inhibit function when the IC7442 is used as a 1of8 decoder. Table 5.10
A3 0 0 0 0 0
Inputs A2 A1 0 0 0 0 1
0 0 1 1 0
Truth table of BCD to decimal converter
A0
Y0
Y1
Y2
Y3
0 1 0 1 0
0 1 1 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 1
Outputs Y4 Y5 1 1 1 1 0
1 1 1 1 1
Y6
Y7
Y8
Y9
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1
1 1 1 1 1 (Contd...)
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Combinational Logic Design Table 5.10 0 0 0 1 1 1 1 1 1 1 1
1 1 1 0 0 0 0 1 1 1 1
(Contd...) 0 1 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1 0 1
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
Fig. 5.26 (a) Pin conﬁguration of IC 7442, and (b) logic symbol of IC 7442
5.4
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1
Fig. 5.27 Logic diagram of BCD to decimal converter
ENCODERS
The operation of encoders is the opposite of decoders. Encoders have 2n inputs and encode them into ‘n’ outputs. When ‘n’ is equal to two, there are four input lines and two output lines. The operation of 4:2, 8:3 and 16:4 encoders are explained in article 5.4.1, 5.4.2 and 5.4.3 respectively.
5.4.1
4:2 Encoder
The block diagram of a four inputs encoder is depicted in Fig. 5.28. Table 5.11 shows the truth table of 4 line to 2line decoder. If the line 0 is selected, output will be 00; if line 2 is selected, output will be 10 and so on. The encoder truth table allocates one of the
Fig. 5.28 Block diagram of 4 line to 2 line encoder
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Digital Electronics: Principles and Applications
Table 5.11
Fig. 5.29
Implementation of 4:2 encoders
Truth table of 4 line to 2 line encoder
F0
Inputs F1 F2
F3
Outputs A B
0 1 0 0 0
0 0 1 0 0
0 0 0 0 1
0 0 0 1 1
0 0 0 1 0
0 0 1 0 1
four combinations of the address variables A and B to each of the inputs. The outputs of encoder can be expressed by Boolean expression as given below: A=F2 +F3 B=F1 + F3 Implementation of 4 line to 2 line encoder is shown in Fig. 5.29.
5.4.2 8:3 Encoder The block diagram of a eight inputs and three outputs encoder is depicted in Fig. 5.30. Table 5.12 shows the truth table of 8 lines to 3line decoder. The outputs of encoder can be expressed by Boolean expression as given below: A=D4+D5+ D 6+ D 7; B= D 2+ D 3+ D 6+ D 7 C= D 1+ D 3+ D 5+ D 7
Fig. 5.30
Block diagram of 8 line to 3 line encoder
The limitation of above decoder is that if all inputs D 0 to D 7 are 0, all outputs will be equal to 0. Therefore, one additional output is sometimes incorporated to point out this state. Another limitation is that only one of the encoder’s inputs must be asserted at a time; otherwise the output will be illogical. Table 5.12
D7
D6
D5
0 0 0 0 0 0 0 1
0 0 0 0 0 0 1 0
0 0 0 0 0 1 0 0
Truth table for 8 line to 3 line encoder
Inputs D4 D3 0 0 0 0 1 0 0 0
0 0 0 1 0 0 0 0
D2
D1
D0
A
Outputs B
C
0 0 1 0 0 0 0 0
0 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
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Combinational Logic Design
5.4.3
16:4 Encoder
The block diagram of a sixteen inputs and four outputs encoder is depicted in Fig. 5.31. Table 5.13 shows the truth table of 16 line to 4line decoder. The outputs of encoder can be expressed by Boolean expressions as given below:
A = D8+ D9+ D10+ D11+ D12+ D13+ D14+ D15 B = D4+ D5+ D6+ D7+ D12+ D13+ D14+ D15 C = D 2+D3+D6+ D7+ D10+ D11+ D14+ D15 D = D1+ D3+ D5+ D7+ D9+ D11+ D13+ D15 Fig. 5.31
Table 5.13
D15 D14 D13 D12 D11 D10
D9
Block diagram of 16 line to 4 line encoder
Truth table of 16:4 encoder
Inputs D8 D7
D6
D5
D4
D3
D2
D1
D0
A
Outputs B C D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
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1
1
0
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0
0
0
0
0
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0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
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0
1
0
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0
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0
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0
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1
1
1
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0
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0
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0
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1
1
1
1
186
Digital Electronics: Principles and Applications
Example 5.4
Design an encoder for the truth table 5.14 given below: Table 5.14
8 line to 3 line encoder
I7
I6
I5
Input I4 I3
I2
I1
I0
B2
x x x x x x x 1
0 0 0 x 0 x 1 x
0 0 0 x 0 1 x x
0 0 0 0 1 0 0 x
0 0 1 0 0 0 0 x
0 1 0 0 0 0 0 x
1 0 0 0 0 0 0 0
0 0 0 0 1 1 1 1
0 0 0 1 0 x x x
Output B1 B0 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
� Solution The outputs of encoder can be expressed by Boolean expressions as given below:
B0= I1+I3+I5+I7 B1= I2+ I3+ I6+ I7 B2= I4+ I5+ I6+I7 Fig. 5.32
8:3 binary encoder
The implementation of above Boolean expressions using OR gates is given in Fig. 5.32.
5.5
PRIORITY ENCODERS
The priority encoder can perform the basic operation of encoder but it has some additional ﬂexibility. The additional feature is priority detection. The priority detection is that can produce BCD output according to highest order decimal number. For example, when decimal number inputs 9 and 6 both are high, the output will be 1001. The operation of most commonly used 4 line to 2 line, 8 line to 3 line and 10 line to 4 line priority encoders are explained below:
5.5.1
4 line to 2 line Priority Encoder
In a 4 line to 2 line encoder, when one input line is selected, according to that, output lines A and B will be set. But there is no way when two or more inputs are requested for servicing at the same time. In this situation priorities of inputs will be considered as Table 5.15 Truth table of 4: 2 priority encoder parameter to control the output of encoder. A truth Inputs Outputs table for 4:2 priority encoder is shown in Table, F0 F1 F2 F3 A B 5.15. In this table priority is assigned to highest 0 0 0 0 x x asserted input. For example, when inputs F0 and x x x 1 1 1 F1 are asserted, the output should be 01 as the x x 1 0 1 0 input F1 has highest priority. From the truth table x 1 0 0 0 1 1 0 0 0 0 0 5.15, the following equations are obtained
187
Combinational Logic Design
– A = F3 + F 3F2 = F3 + F2 – – – B = F3 + F 3F 2F1 = F3 + F 2F1 The implementation of above equations is shown in Fig. 5.33
5.5.2
8: 3 Priority Encoder
The 8 line to 3 line priority encoder generates a 3 bit binary output depending on input lines. When line 0 is selected, the encoder output will be 000. If line 1 is selected, the encoder output is 001. In this priority encoder, priority has assigned to the highest output. Truth table of 8 lines to 3line priority encoder is depicted in Table 5.16. Table 5.16
EI
I0
I1
I2
1 0 0 0 0 0 0 0 0 0
X 1 X X X X X X X 0
X 1 X X X X X X 0 1
X 1 X X X X X 0 1 1
Fig. 5.33
4:2 priority encoder
Truth table for 8 line to 3 line priority encoder
Inputs I3 X 1 X X X X 0 1 1 1
I4
I5
I6
I7
A2
A1
X 1 X X X 0 1 1 1 1
X 1 X X 0 1 1 1 1 1
X 1 X 0 1 1 1 1 1 1
X 1 0 1 1 1 1 1 1 1
1 1 0 0 0 0 1 1 1 1
1 1 0 0 1 1 0 0 1 1
Outputs A0 GS 1 1 0 1 0 1 0 1 0 1
1 1 0 0 0 0 0 0 0 0
EO 1 0 1 1 1 1 1 1 1 1
To create a priority encoder it is ﬁrst useful to create functions that are true only if their corresponding input lines are true. For a 8 to 3 encoder these functions will be: H7=I7 – H6 = I6 I 7 – – H5= I5 I 6 I 7 – – – H4= I4 I 5 I 6 I 7 – – – – H3= I3 I 4 I 5 I 6 I 7 – – – – – H2= I2 I 3 I 4 I 5 I 6 I 7 – – – – – – H1= I1 I 2 I 3 I 4 I 5 I 6 I 7 – – – – – – – H0= I0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 where, H stands for highest priority, and I stands for inputs. Then H0, H1 …… H7 functions are used to create the outputs A0 to A2 as follows
188
Digital Electronics: Principles and Applications
A0= H1 + H3 + H5 + H7 A1= H2+ H3+ H6+ H7 A2= H4+ H5+ H6+ H7 IC74148 is an MSI encoding circuit for the 8 to 3 line priority encoder. The features of IC 74148 are code conversions, decimaltoBCD converter, cascading for priority encoding of ‘n’ bits, input enable capability, priority encoding of highest priority input line, output enableactive Low when all inputs are high, group signal outputactive when any input is Low. The 8input priority encoder IC 74148 acknowledges data from eight activelow inputs and provides a binary representation on the three active low outputs. A priority is assigned to each input so that when two or more Fig. 5.34 Pin diagram of IC 74148 inputs are simultaneously active. The input with the highest priority is represented on the output, with input line I7 having the highest priority. The pin diagram of IC74148 is given in Fig. 5.34 and the pin description as follows: I 1 – I7 I0 EI EO GS A0 – A2
Priority inputs (active Low) Priority input (active Low) Enable input (active Low) Enable output (active Low) Group select output (active Low) Address outputs (active Low)
The logic circuit diagram of IC74148 is shown in Fig. 5.35. When enable input signal EI is active low, the IC will be enable. The high EI signal will force all outputs to the inactive or high state and allow new data to settle without producing erroneous information at the outputs. When the numbers of input signals to be encoded are more than eight, two or more encoders are connected in cascade. To operate in combination with other encoders, the group select signal (GS) and enable output signal (EO) are provided in encoder. The GS is activelow when any input is low. The EO is activelow when all inputs are high. If EO and GS are activehigh, when the enable input is high. The enable output and group select signals can be expressed as — EO = EI I0I1I2I3I4I5I6I7 — GS = EI + I0I1I2I3I4I5I6I7EI
Fig. 5.35
Logic diagram of IC 74148
Priority encoders are commonly used in microprocessor, microcontroller and computer to handle interrupt signals and the processor should response to the highest priority pending interrupt request.
189
Combinational Logic Design
5.5.3
10 Line to 4 Line Priority Encoder
IC 74147 is a 10line to 4line priority encoder and encodes 10line decimal to 4line BCD. The pin diagram of IC 74147 is depicted in Fig. 5.36 and the pin description as follows: Y0 to Y3 A0 to A8 VCC GND n.c.
BCD address outputs (active LOW) decimal data inputs (active LOW) positive supply voltage ground (0 V) not connected
The 9input priority encoders IC74147 accept data from nine active low inputs (A0 to A8) and provide a binary representation on the four active low outputs (Y0 to Y3). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with the highest priority is represented on the output. The input line A8 has the highest priority. The IC 74147 provides the 10line to 4line priority encoding function by use of the implied decimal ‘0’. The ‘0’ is encoded when all nine data inputs are high and all four outputs are high. The logic diagram of 74147 is shown in Fig. 5.37 and the truth able for IC 74147priority encoder is given in Table 5.17. Table 5.17
Fig. 5.36 (a) Pin conﬁguration of IC74147 and (b) Logic symbol of IC 74147
Fig. 5.37
Logic diagram of IC 74147priority encoder
Truth table for 74147priority encoder
A0
A1
A2
A3
Inputs A4
A5
A6
A7
A8
Y3
Outputs Y2 Y1
Y0
1 X X X X X X X X 0
1 X X X X X X X 0 1
1 X X X X X X 0 1 1
1 X X X X X 0 1 1 1
1 X X X X 0 1 1 1 1
1 X X X 0 1 1 1 1 1
1 X X 0 1 1 1 1 1 1
1 X 0 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1
1 0 0 1 1 1 1 1 1 1
1 1 1 0 0 0 0 1 1 1
1 0 1 0 1 0 1 0 1 0
1 1 1 0 0 1 1 0 0 1
190
Digital Electronics: Principles and Applications
5.5.4 Cascading Priority Encoders By cascade connection of several priority encoders, we can create a larger priority encoder. In an encoder IC, EI is enable input. This input enables the priority encoder. EO is enable output. This output is asserted only when EI is asserted and none of the other inputs are asserted. This output is used to enable other lower priority encoders. Figure 5.38 shows the cascade connection of two 74148 ICs to form a 16 line to 4 line encoder. The enable input EI of the IC2 is connected to ground. If any input of IC2 goes low, its EO goes high. As EO of IC2 is connected to the enable input, EI of the IC1, IC1 will be disabled. If IC2 is enabled, the GS output of the IC2 goes low when any of its input becomes low. But the GS outputs of both the ICs will be high, while no input of any of the ICs is low. This 16 line to 4 line encoder can be used for converting hexadecimal number to binary form. In hexadecimal to binary conversion, hexadecimal inputs 0 to 7 are connected to the input lines of encoder IC1 and hexadecimal inputs 8 to F are connected to the input lines of encoder IC2.
Fig. 5.38 16 inputs priority encoder
5.6
MULTIPLEXERS
The multiplexer is a combinational logic circuit, which operates as controlled switch with ‘n’ inputs and one single data output. It selects one of the inputs according to Table 5.18 Multiplexer ICs binary signals applied on select pins of combinational circuit and passes the information of the selected line to the common output. IC NO. Description 74157 Quad 2:1 Multiplexer Therefore multiplexer is also called as data selector. Generally 74158 Quad 2:1 Multiplexer the number of data inputs is a power of two (2, 4, 8, 16 etc). The 74153 Dual 4:1 Multiplexer operation of 2:1, 4:1, 8:1 and 16:1 multiplexers are explained in 74352 Dual 4:1 Multiplexer article 5.6.1, 5.6.2, 5.6.3 and 5.6.4 respectively. Table 5.18 shows the 74152 8:1 Multiplexer available multiplexer ICs. 74150 16:1 Multiplexer
191
Combinational Logic Design
5.6.1
2:1 Multiplexer
Figure 5.39 shows the block diagram of 2:1 multiplexer and the multiplexer has two inputs (D0 & D1), one select input (S) and one output (F). The switch connects the output to the one input or the other depending on a select signal. Since there are only two possible ways to connect the input lines, only one select signal is needed. If the select line is high, the output will be switched to D1 and if the select line is low, the output will be switched to input D0. Figure 5.40 shows the actual 2:1 analog multiplexer. In analog multiplexer, the output Fig. 5.39 Block diagram of 2:1 multiplexer is literally equal to the input signal. In a digital multiplexer, the output will be high if input is high and output will be low if input is low. The truth table of 2:1 multiplexer is shown in Table 5.19. Table 5.19
Fig. 5.40
Truth table of 2:1 multiplexer
Select S
Inputs D1
D0
Output F
0
0
0
0
0
0
1
1
1
1
0
1
1
1
1
1
2: 1 analog multiplexer
Figure 5.41 shows logic circuit of 2:1 multiplexer using logic gates. When S=0, output of lower AND gate D0, but output of upper AND gate is 0. Therefore, output generated by OR gate is equal to D0. Similarly, when S=1, output of upper AND gate is D1 and output of lower AND gate is 0. Consequently, output of OR gate is D1. – Then output expression is O = S D0 + SD1. Simple logic gates can implement multiplexers and Fig. 5.41 Logic circuit of 2:1 multiplexer these gates can be fabricated in a IC. Usually four 2 line to 1 line multiplexers are fabricated in a single IC. IC 74157 and IC 74158 are the examples of 2:1 multiplexer. The connection diagram and logic circuit diagram of IC 74157 and IC 74158 are shown in Figs 5.42 and 5.43 respectively. Strobe and select signals are common to all four 2 line to 1 line multiplexer. When strobe is low, multiplexer is enable and data can pass from selected input line to output line. When strobe is high, multiplexer is disable and no data can pass from input to output. The selected signal is used to select one of the 2 inputs.
192
Digital Electronics: Principles and Applications
Fig. 5.42 (a) Connection diagram of IC 74157 and (b) Logic diagram of quad 2 line to 1 line multiplexers IC 74157
Fig. 5.43
(a) Connection diagram of IC 74158 and (b) Logic diagram of quad 2 line to 1 line multiplexer IC 74158
5.6.2 4:1 Multiplexer Figure 5.44 shows the block diagram of a multiplexer with four inputs, D0, D1, D2 and D3. There are two select lines S0 and S1 and an enable line, E. The multiplexer decodes the input through select line. Table 5.20 shows the truth table of 4:1 multiplexer. When select inputs S1=0 and S0=0, the data output Y is equal to D0. The data output Y is equal to D1, if select inputs S1=0 and S0=1. If select inputs S1=1 and S0=0, the data output Y is equal to D2. The data output Y is equal to D3, if select inputs S1=1 and S0=1. The output expression is Fig. 5.44 Block diagram of 4:1 multiplexer
193
Combinational Logic Design
– — – – Y = DO S 1 S 0 + D1S 1S0 + D2S1S 0 + D3S1S0 Figure 5.45 shows the implementation of 4 line to single line multiplexer using gates. The inputs of the multiplexer are D0, D1, D2 and D3 and two select lines S0 and S1. Four 3 inputs AND gates and one four inputs OR gate are used for implementation of a 4:1 multiplexer. Table 5.20
Truth table for 4:1 Muxtiplexer
Selects Data Inputs S1 S0 0 0 1 1
0 1 0 1
Output Y D0 D1 D2 D3 Fig. 5.45
4:1 multiplexer
Generally, dual 4 line to 1 line multiplexers ICs are available. IC74153 is a dual 4 line to 1 line multiplexer and its logic symbol and circuit diagram are shown in Fig. 5.46 (a) and (b) respectively. This multiplexer has two select input lines (A and B). When AB = 00, the D0 input line is selected. If AB = 11 the D3 input line is selected. Like quad 2 line to 1 line multiplexer, dual 4 line to 1 line multiplexers have two strobe which are used to switch on and off the multiplexers. The functional table of IC74153 is given in Table 5.21.
Fig. 5.46
(a) Logic symbol of dual 4:1 multiplexers and (b) Logic diagram of dual 4 line to 1 line multiplexer IC 74153
194
Digital Electronics: Principles and Applications Table 5.21
Functional table of dual 4 line to 1 line multiplexer IC 74153
Select Inputs B A
C0
C1
C2
C3
Strobe – G
Output Y
x 0 0 0 0 1 1 1 1
x 0 1 x x x x x x
x x x 0 1 x x x x
x x x x x 0 1 x x
x x x x x x x 0 1
0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 1
x 0 0 1 1 0 0 1 1
Inputs
5.6.3 8line to 1line Multiplexer The block diagram of 8:1 multiplexer is shown in Fig. 5.47. This multiplexer has eight input lines D0 to D7 and three select inputs S0 to S2. The multiplexer decodes the inputs through select lines. Table 5.22 shows the truth table of 8:1 multiplexer. If select inputs S2 = 1, S1 = 0 and S0 = 0, the data output Y is equal to D4. Similarly the data outputs D0 to D7 will selected through S2 , S1 and S0 as shown in Table 5.22. The output Y can be expressed as Table 5.22
Fig. 5.47
Block diagram of 8:1 multiplexer
– – – – – – – – Y = D0S 2S 1S 0 + D1S 2S 1S0 + D2S 2S1S 0 + D3S 2S1S0 – – – – + D4S2S 1S 0 + D5S2S 1S0 + D6S2S1S 0 + D7S2S1S0
Truth table of 8:1 multiplexer
Selects Data Inputs S2 S1 S0 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Output Y D0 D1 D2 D3 D4 D5 D6 D7
The multiplexer IC 74151A has eight input lines from D0 to D7 and three select inputs A, B and C. There is also provision for a strobe, which is active low. If strobe is low, the multiplexer is enabled. When strobe is held high, IC is disabled. The data output and its complement are available at output pins. Figure 5.48 shows the pin conﬁguration of this multiplexer and the logic diagram for this multiplexer is in Fig. 5.49.
Fig. 5.48 Pin diagram of 74151A
IC 74151A is a 8 line to 1 line multiplexer and its circuit diagram is shown in Fig.5.49. This multiplexer has three select lines A, B and C. Every time one of the inputs will be selected through select
Combinational Logic Design
195
lines and send the data of the selected line to output line. In this multiplexer, strobe signal is used as a switch to turn on and off the multiplexer. Table 5.23 shows the functional table of 8 lines to 1 line multiplexer. Table 5.23
Functional table of 8 lines to 1 line multiplexer
Inputs Select inputs C B A
Outputs Store – G
Y
W 1 – D0 – D1 – D2 – D3 – D4 – D5 – D6 – D7
X 0
X 0
X 0
1 0
0 D0
0
0
1
0
D1
0 0
1 1
0 1
0 0
D2 D3
1
0
0
0
D4
1 1
0 1
1 0
0 0
D5 D6
1
1
1
0
D7
5.6.4
Fig. 5.49
Logic diagram for multiplexer 1C 74151
16line to 1line Multiplexer
This multiplexer has 16 input lines, four select lines and one output. Figure 5.50 shows the block diagram of 16 lines to 1 line multiplexer. The multiplexer select one out of 16 inputs D0 to D15 through four select lines S0 to S3 and send information to output. Table 5.24 shows the truth table of 16 lines to 1 line multiplexer. The 16:1 data selectors/multiplexers contain full onchip decoding to select the desired data source. The IC 74150 is a 16:1 multiplexer and is used to select oneofsixteen data sources. Pin connections of multiplexer IC 74150 are given in Fig. 5.51(a) and its logic symbol is also shown in Fig. 5.51(b). The bubble at the output point out that the output is active low if the selected data bit is high. So, the output is always the complement of the selected data bit. The 74150 have a strobe input, which must Fig. 5.50 Block diagram of 16:1 multiplexer be at a LOW logic level to enable these devices. A HIGH level at the strobe forces the W output HIGH and the Y output LOW. The 74150 features an inverted (W) output only. The logic circuit diagram of IC 74150 is shown in Fig. 5.52.
196
Digital Electronics: Principles and Applications Table 5.24
S3
Truth table of 16:1 multiplexer
Selects Data Inputs S2 S1
S0
Strobe – G
Output Y
0
0
0
0
0
D0
0
0
0
1
0
D1
0
0
1
0
0
D2
0
0
1
1
0
D3
0
1
0
0
0
D4
0
1
0
1
0
D5
0
1
1
0
0
D6
0
1
1
1
0
D7
1
0
0
0
0
D8
1
0
0
1
0
D9
1
0
1
0
0
D10
1
0
1
1
0
D11
1
1
0
0
0
D12
1
1
0
1
0
D13
1
1
1
0
0
D14
1
1
1
1
0
D15
Fig. 5.51 (a) Pin diagram of 74150 and (b) Logic symbol of 74150
Combinational Logic Design
Fig. 5.52
5.6.5
197
Logic diagram of 74150
Cascading Multiplexers
One can connect two or more multiplexers in cascade by using the enable input on a multiplexer and an OR gate to construct a larger multiplexer. The example is that two 4 line to 1 line multiplexers are combined to create one 8 to 1 multiplexer. Three select lines are required for a 8 to 1 multiplexer. 2 of the three lines are directly connected to the select inputs of each 4:1 multiplexer. The other select line is connected to enable one of the two multiplexers and inverted enable is connected to other 4:1 multiplexer. The outputs of two 4:1 multiplexers are combined by using an external OR gate to develop 8:1 multiplexers. Figure 5.53 shows the 8:1 multiplexer using two 4:1 multiplexers.
Fig. 5.53 8:1 multiplexer using two 4:1 multiplexers
198
Example 5.5
Digital Electronics: Principles and Applications Design a 32:1 multiplexer using two 16:1 multiplexers.
� Solution The 16:1 multiplexers are the largest available ICs. Therefore, 32:1 multiplexer can be designed by using two 16:1 multiplexers with the help of enable/strobe inputs. Figure 5.54 shows the 32 line to 1 line multiplexer using two 16:1 multiplexers and an OR gate.
Fig. 5.54 32:1 multiplexer using two 16:1 multiplexers
5.6.6 Applications of Multiplexers Multiplexers are used in ∑ Boolean function implementation ∑ Pulse train generator ∑ Register to register data transfer ∑ Encoders ∑ Combinational logic circuit design. The example of Boolean function implementation and pulse train generator are given below.
199
Combinational Logic Design
Example 5.6
Implement the Boolean function F(A,B,C,D)=Sm(1,2,4,5,7,9,11,12) using a multiplexer.
� Solution As there are four variables, a four select lines multiplexer is required to implement the Boolean function F(A,B,C,D)=Sm(1,2,4,5,7,9,11,12) . So, 16:1 multiplexer IC74150 will be selected. The circuit diagram for implementation of above Boolean function is shown in Fig. 5.55.
Fig. 5.55
Example 5.7
Implement the Boolean function F(X,Y,Z)=Σm(1,2,6,7) using 4:1 multiplexer.
� Solution As 4:1 multiplexer is used to implement the Boolean function F(X,Y,Z)=Σm(1,2,6,7) , two select inputs can be used for selecting the 4 input address lines. Since the output is depends on the value Z, the output F will Table 5.25
Truth table of 4: 1 multiplexer
X
Inputs Y
Output F
Z
0
0
0
0
F=Z
0
0
1
1
0
1
0
1
0
1
1
0
F=Z – F=Z – F=
1
0
0
0
F=0
1
0
1
0
F=0
1
1
0
1
F=1
1
1
1
1
F=1
Fig. 5.56
200
Digital Electronics: Principles and Applications
– be derived from Z, Z , 1, and 0. The relation between Z and F is depicted in Table 5.25. Figure 5.56 shows the implementation of Boolean function F(X,Y,Z)=Σm(1,2,6,7) using 4:1 multiplexer.
Example 5.8
Implement the Boolean function F(A,B,C,D) =Σm(1,3,4,11,12,13,14,15) using 8:1 multiplexer.
� Solution Create truth table for F as shown in Table 5.26. A, B, and C are used as variables to the selection inputs. The last input variable D can be considered as input data and the values of F to select the inputs for each of the – multiplexer’s data input lines are D, D , 0 or 1. Figure 5.57 shows the implementation of Table 5.26, which represents the Boolean function F(A,B,C,D) = Sm(1,3,4,11,12,13,14,15). Table 5.26
A
Truth table of 4: 1 multiplexer
Select Data B C
D
Output F
0
0
0
0
0
F=D
0
0
0
1
1
F=D
0
0
1
0
0
F=D
0
0
1
1
1
0
1
0
0
1
0
1
0
1
0
F=D – F=D – F=D
0
1
1
0
0
F=0
0
1
1
1
0
F=0
1
0
0
0
0
F=0
1
0
0
1
0
F=0
1
0
1
0
0
F=D
1
0
1
1
1
F=D
1
1
0
0
1
F=1
1
1
0
1
1
F=1
1
1
1
0
1
F=1
1
1
1
1
1
F=1
Example 5.9
Fig. 5.57
Design a circuit for a pulse train 10101011 using a multiplexer.
� Solution As the length of the pulse train is 8 bits, 8:1 multiplexer and MOD 8 counter will be used to generate the pulse 10101011. Figure. 5.58 shows the implementation of pulse train.
201
Combinational Logic Design
Fig. 5.58
5.7
Table 5.27
DEMULTIPLEXER
Demultiplexer is the inverse of the multiplexing. A demultiplexer bypass the binary input data to one of it’s many output lines. The selection of which output line receives the information can be determined by the binary input on the select lines. Commonly available demultiplexers are 1:4, 1:8 and 1:16. Table 5.27 shows the available demultiplexer ICs.
5.7.1
Demultiplexer ICs
IC NO.
Description
74139
Dual 1:4 Demultiplexer
74136
1:8 Demultiplexer
74154
1:16 Demultiplexer
1:2 DEMULTIPLEXER
Figure 5.59 shows the 1:2 demultiplexer, which has one input and two outputs. The switch connects the input to one of the output depending on a select signal. Since there are only two possible ways to connect the input and output lines, only one select signal is required. If the select line is low, the input will be switched to D0 and if the select line is high, the input will be switched to D1. Fig. 5.59 Table 5.28
Truth table of 2:1 multiplexer
Select S
Input F
D1
D0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
1
0
Block diagram of 1:2 demultiplexer
Outputs
Figure 5.60 shows the actual 1:2 analog demultiplexer. In analog demultiplexer, the output is literally equal to the input for all values of input. In a digital demultiplexer, the output will be high if input is high and output will be low if input is low. The truth table of 1:2 demultiplexer is shown in Table 5.28.
202
Digital Electronics: Principles and Applications
5.7.2 1:4 Demultiplexer 1:2 demultiplexer can be extended to 1:4 demultiplexer by increasing the number of select lines. 1:4 demutiplexer has four output lines and two select inputs. If the select input lines are 00, the input is connected to output line D0; if the select lines are 01, then input is connected to output line D1. Table 5.29 shows the truth table of 1:4 demultiplexer. Figure 5.61 shows the circuit for 1:4 demultiplexer. The output logic can be expressed by meanterms as given below: – – D0 = ES 1S 0 – D1 = ES 1S0 – D2 = ES1S 0 D3 = ES1S0 where, E is as input data, S0 and S1 are select lines and output lines are D0 to D4. Table 5.29
Fig. 5.60 1 : 2 analog demultiplexer
Fig. 5.61
Logic diagram of 1 line to 4 line demultiplexer
Truth table of 1 line to 4 line demultiplexer
E
Inputs S1
Output S0
D0
D1
D2
D3
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
1
1
1
1
0
1
x
x
1
1
1
1
The IC74139 is a dual 1of4 demultiplexer. The pin conﬁguration of 1:4 demultiplexer is shown in Fig. 5.62 and pins description of IC 74139 is given below: A0n, A1n
Address inputs
Ea, Eb
Enable inputs (activeLow)
Q0n, Q3n
Data outputs
This IC has two independent demultiplexers. Each demultiplexer can accept two binary weighted inputs (A0n, A1n) and provides four mutually exclusive activelow outputs (Q0n – Q3n). Each demultiplexer has an activelow enable (E). When E is high, all outputs are high. The enable can be used as the data input for a 1of4 demultiplexer application. The functional table for one of demultiplexer is given in Table 5.30. Logic diagram of dual 1 line to 4 line demultiplexer is depicted in Fig. 5.63.
203
Combinational Logic Design
Fig. 5.62
(a) Pin conﬁguration of 1:4 demultiplexer, (b)Logic symbol of dual 1:4 line demultiplexer
Fig. 5.63 Logic diagram of dual 1:4 line demultiplexer Table 5.30
Functional table of 1:4 demultiplexer
Inputs Enable
Output
Select
– Q0
– Q1
– Q2
– Q3
E
A0
A1
1
x
x
1
1
1
1
0
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
1
1
1
0
0
1
1
1
1
1
0
204
Digital Electronics: Principles and Applications
5.7.3 1:8 Demultiplexer The IC74237 is a 3to8 line decoder/ 1:8 demultiplexer with latches at the three address inputs (A0 to A2). Pin conﬁguration of IC 74237 is shown in Fig. 5.64 and pin description is given below: A0 to A2
data inputs
Y0 to Y7
demultiplexer outputs
LE
latch enable input (active LOW)
E1
data enable input (active LOW)
E2
data enable input (active HIGH)
GND
ground (0 V)
VCC
positive supply voltage.
Figure 5.65 shows the functional diagram of demultiplexer IC Fig. 5.64 Pin conﬁguration of 1:8 demultiplexer 74237 and its functional table is Table 5.31. This demultiplexer has three enable inputs LE, E1 and E2, which can be used to extend the higher demultiplexers. The IC74237combines the 3to8 decoder function with a 3bit storage latch. When the latch is enabled (LE = low), the IC74237 acts as a 3to8 active low decoder. When the latch enable (LE) changes from lowtohigh, the last data present at the inputs before this transition, is stored in the latches. Further address changes are ignored as long as LE remains high. The output enable input (E1 and E2) controls the state of the outputs independent of the address inputs or latch operation. All outputs are high unless E1 is low and E2 is high. The logic circuit diagram of demultiplexer IC 74237 is depicted in Fig. 5.66. Table 5.31
Functional table of 1:8 demultiplexer IC 74237
Inputs Output Enable Select Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 –— – – LE E1 E2 A0 A1 A2 x
1
x
x
x
x
0
0
0
0
0
0
0
0
x
x
0
x
x
x
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
0
0
0
0
0
0
1
Fig. 5.65 Functional diagram of 1:8 demultiplexer
Combinational Logic Design
205
Fig. 5.66 Logic diagram of 1:8 demultiplexer
5.7.4
1:16 Demultiplexer
The 4to16 line decoders/ 1 : 16 demultiplexers IC74514 are having four binary weighted address inputs (A0 to A3), with latches, a latch enable input (LE), and an active LOW enable input (E). The 16 outputs (Q0 to Q15) are mutually exclusive active HIGH. When LE is HIGH, the selected output is determined by the data on An. When LE goes LOW, the last data present at An are stored in the latches and the outputs remain stable. When E is LOW, the selected output, determined by the contents of the latch, is HIGH. At E HIGH, all outputs are LOW. The enable input (E) does not affect the state of the latch. When the IC74514 is used as a demultiplexer, E is the data input and A0 to A3 are the address inputs. Pin conﬁguration and logic symbol of IC 74514 are shown in Fig. 5.67 (a) and (b) respectively. The functional diagram of 1:16 demultiplexer IC 74514 is illustrated in Fig. 5.68 and functional table of 1:16 demultiplexer is given in Table 5.32. Figure 5.69 shows the logic diagram of 1:16 demultiplexer IC 74514. The pin description of IC 74514 is given below: LE
latch enable input (active HIGH).
A0 to A3
address inputs
Q0 to Q15
demultiplexer outputs (active HIGH)
GND
ground (0 V)
n
enable input (active LOW)
VCC
positive supply voltage
206
Digital Electronics: Principles and Applications
Fig. 5.67 (a) Pin conﬁguration 1:16 demultiplexer IC 74514 and (b) Logic symbol 1:16 demultiplexer Table 5.32 Functional table of 1:16 demultiplexer
– E
Inputs A0 A1 A2
A3
1
x
x
x
x
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Q0 Q1 Q2 Q3 Q 4 Q5
Q6
Outputs Q7 Q8 Q9 Q10 Q11 Q12 Q13 Q14 Q15
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Combinational Logic Design
Fig. 5.68 Functional diagram of 1:16 demultiplexer IC 74514
Fig. 5.69
Logic diagram of 1:16 demultiplexer IC 74514
207
208
Digital Electronics: Principles and Applications
5.7.5 Cascade Demultiplexer 1:16 demultiplexer is the largest available ICs. When large demultiplexer is required, we can not implemented by using single MSI ICs. Therefore, two or more demultiplexers are connected in cascade to fulﬁll the requirement. The expansion of 1:16 demultiplexer to 1:32 demultiplexer is possible using enable input terminals. The Enable E is the most signiﬁcant bit and A will be least signiﬁcant bit. Figure 5.70 shows the 1:32 demultiplexer.
Fig. 5.70 Logic diagram of 1:32 demultiplexer
5.7.6 Applications of Demultiplexers Demultiplexers are used in • Boolean function implementation • Data transmission • Combinational logic circuit design. • Generate enable signals (enable one out of many). The application of enable signals in microprocessor systems are: i. Selecting different banks of memory ii. Selecting different input/output devices for data transfer iii. Enabling different functional units iv. Enabling different rows of memory chips depending on address Generally, demultiplexers are used to implement multiple Boolean functions and decoder circuits. The application of demultiplexer in multiple Boolean functions implementation is given in Example 5.10.
Combinational Logic Design
Example 5.10
209
Design a circuit using multiplexer for the following Boolean functions:
F1(A,B,C,D)=S (1,2,3,4,5,7) F2(A,B,C,D)=S (2,4,7,9,11) F3(A,B,C,D)=S (10,12,14,15) Solution As there are four variables, 1: 16 demultiplexer can be used with four select lines. Figure 5.71 shows the implementations of above Boolean functions using demultiplexer and OR gates.
�
Fig. 5.71
5.8 CODE CONVERSION USING LOGIC GATES AND MSI ICs In digital system, most commonly used codes are Binary, BCD, Excess3, Gray code, 9’s complement and 10’s complement of decimal number. In different applications, different codes are used. For example, BCD data must be converted to sevensegment code, which is incorporated in article 5.3.7 to display BCD numbers in sevensegment display form. Therefore, BCD to Excess3, BCD to Binary, Binary to Gray, Gray to Binary, 9’s complement and 10’s complement of Decimal number conversions using logic gates and MSI ICs are explained in this section
5.8.1
BCD to Excess–3 Decoder
In Excess3 code, each decimal digit is represented by it’s binary code plus 3. Truth table for BCD to Excess3 decoder is given in Table 5.33. The Kmap of the corresponding truth table and reduction of all the output functions are shown in Fig. 5.72.
210
Digital Electronics: Principles and Applications Table 5.33 Truth table for BCD to excess3 decoder
Decimal Numbers
BCD Inputs
Excess3 Output
A
B
C
D
O3
O2
O1
O0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
1
0
0
2
0
0
1
0
0
1
0
1
3
0
0
1
1
0
1
1
0
4
0
1
0
0
0
1
1
1
5
0
1
0
1
1
0
0
0
6
0
1
1
0
1
0
0
1
7
0
1
1
1
1
0
1
0
8
1
0
0
0
1
0
1
1
9
1
0
0
1
1
1
0
0
10
1
0
1
0
x
x
x
x
11
1
0
1
1
x
x
x
x
12
1
1
0
0
x
x
x
x
13
1
1
0
1
x
x
x
x
14
1
1
1
0
x
x
x
x
15
1
1
1
1
x
x
x
x
The minimal SOP functions for the outputs are – O0 = D –– O1 = CD + C D –– – – O2 = BC D + BC + BD O3 = A + BC + BD These expressions can be implemented using AND, OR and NOR gates as depicted in Fig. 5.73. The outputs O0, O1, O2 and O3 can be expressed in minterms as given below: O0=Σm(0,2,4,6,8) O1=Σm(0,3,4,7,8) O2=Σm(1,2,3,4,9) O3=Σm(5,6,7,8,9) The implementation of O0, O1, O2 and O3 using 4 line to 16 line decoder IC is given in Fig. 5.74.
Combinational Logic Design
Fig. 5.72 (a) Kmap for O3; (b) Kmap for O2; (c) Kmap for O1; (d) Kmap for O0
Fig. 5.73
Binary to Excess 3 converter using logic gates
211
212
Digital Electronics: Principles and Applications
Fig. 5.74
Binary to Excess 3 converter using decoder
5.8.2 Gray Code to Binary Code Table 5.34 shows the Gray code and it’s equivalent decimal number. From this table, the binary code A,B,C and D are expressed in terms of G0,G1, G2 and G3 as given below. A = F1 ( G0, G1, G2, G3) = Sm(8,9,10,11,12,13,14,15) B = F2 ( G0, G1, G2, G3) = Sm(4,5,6,7,8,9,10,11) C = F3 ( G0, G1, G2, G3) = Sm(2,3,4,5,8,9,14,15) D = F4 ( G0, G1, G2, G3) = Sm(1,2,4,7,8,11,13,14) Kmaps can be constructed for these expressions for getting the minimal SOP form for them. The corresponding Kmaps are shown in Fig. 5.75 (a), (b), (c) and (d). Table 5.34 Truth table for Gray code to binary code
Decimal Numbers
G3
Gray Code G2 G1
G0
A
Binary Code B C
D
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
2
0
0
1
1
0
0
1
0
3
0
0
1
0
0
0
1
1
4
0
1
1
0
0
1
0
0
5
0
1
1
1
0
1
0
1
6
0
1
0
1
0
1
1
0
7
0
1
0
0
0
1
1
1
8
1
1
0
0
1
0
0
0 (Contd.)
213
Combinational Logic Design Table 5.34 (Contd.) 9
1
1
0
1
1
0
0
1
10
1
1
1
1
1
0
1
0
11
1
1
1
0
1
0
1
1
12
1
0
1
0
1
1
0
0
13
1
0
1
1
1
1
0
1
14
1
0
0
1
1
1
1
0
15
1
0
0
0
1
1
1
1
Fig. 5.75
(a) Kmap for A; (b) Kmap for B; (c) Kmap for C; (d) Kmap for D
The minimal SOP functions for the outputs are given below. A=G3 B=G3≈G2 C=G3≈G2≈G1 D=G3≈G2≈G1≈G0
214
Digital Electronics: Principles and Applications
These expressions can be implemented using XOR gates as shown in Fig. 5.76. IC 7486 IC can be used as a binary to Gray converter based on XOR logic gates. These logic expressions can also be implemented by using 4 line to 16line decoder.
5.8.3 Binary Code to Gray Code Table 5.35 shows the binary code and it’s equivalent Gray code. From the table, the Gray code G0, G1, G2 and G3 can be expressed in terms of A,B,C and D as given below.
Fig. 5.76
Gray to Binary converter using XOr gates
G0 = F1 (A, B, C, D) = Sm(1,2,5,6,9,10,13,14) G1 = F2 (A, B, C, D) = Sm(2,3,4,5,10,11,12,13) G2 = F3 (A, B, C, D) = Sm(4,5,6,7,8,9,10,11) G3 = F4 (A, B, C, D) = Sm(8,9,10,11,12,13,14,15) Table 5.35 Truth table for binary code to Gray code
Decimal Numbers
A
Binary Code B C
Gray Code G2 G1
D
G3
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
2
0
0
1
0
0
0
1
1
3
0
0
1
1
0
0
1
0
4
0
1
0
0
0
1
1
0
5
0
1
0
1
0
1
1
1
6
0
1
1
0
0
1
0
1
7
0
1
1
1
0
1
0
0
8
1
0
0
0
1
1
0
0
9
1
0
0
1
1
1
0
1
10
1
0
1
0
1
1
1
1
11
1
0
1
1
1
1
1
0
12
1
1
0
0
1
0
1
0
13
1
1
0
1
1
0
1
1
14
1
1
1
0
1
0
0
1
15
1
1
1
1
1
0
0
0
G0
The binary to Gray converter can also implemented by XOR gates. It is depicted from the Table 5.35 that the most signiﬁcant bits of binary and Gray codes are the same. Consequently, the most signiﬁcant bits does not require any conversion. Figure 5.77 shows the circuit of binary to Gray code conversion. The Boolean expressions of binary to Gray code are given below:
215
Combinational Logic Design
G3=A G2=A≈B G1=A≈B≈C G0=A≈B≈C≈D Fig. 5.77
5.8.4
Binary to Gray converter
9’s Complements of Decimal Number
Table 5.36 shows the truth table of IC 74184 to convert BCD number into 9’s complement. Here, ABCD are BCD inputs and 9’s complement output are NA, NB, NC and ND. Figure 5.78 shows the circuit diagram for converting BCD numbers into 9’s complement numbers. Table 5.36 9’s complement of decimal number
Decimal Numbers
G
Inputs D C
E
0
0
1
B
A
Y8
0
0
0
0
0
1
0
1
1
0
0
1
0
0
0
0
0
1
1
0
0
1
0
0
0
2
0
0
0
0
1
0
0
1
1
0
1
1
1
3
0
0
0
0
1
1
0
1
0
0
1
1
0
4
0
0
0
1
0
0
0
1
1
0
1
0
1
5
0
0
0
1
0
1
0
1
0
0
1
0
0
6
0
0
0
1
1
0
0
0
1
0
0
1
1
7
0
0
0
1
1
1
0
0
0
0
0
1
0
8
0
0
1
0
0
0
0
0
1
0
0
0
1
9
0
0
1
0
0
1
0
0
0
0
0
0
0
Fig. 5.78
Outputs Y7 Y6
BCD to 9’s complement converter
9’s complement ND NC NB NA
216
Digital Electronics: Principles and Applications
5.8.5 10’s Complements of Decimal Number The truth table of IC 74184 to convert BCD number into 10’s complement is depicted in Table 5.37 where BCD inputs are A, B, C, and D and 10’s complement output are TA, TB, TC and TD. Figure 5.79 shows the circuit diagram for converting BCD numbers into 10’s complement numbers. Table 5.37
Decimal Numbers
E
0
1
1 2
10’s complement of decimal number
G
Inputs D C
Outputs Y7 Y6
10’s complement TD TC TB TA
B
A
Y8
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
1
1
0
0
0
1
0
1
0
0
1
0
0
0
3
1
0
0
0
1
1
0
1
1
0
1
1
1
4
1
0
0
1
0
0
0
1
1
0
1
1
0
5
1
0
0
1
0
1
0
1
0
0
1
0
1
6
1
0
0
1
1
0
0
1
0
0
1
0
0
7
1
0
0
1
1
1
0
0
1
0
0
1
1
8
1
0
1
0
0
0
0
0
1
0
0
1
0
9
1
0
1
0
0
1
0
0
0
0
0
0
1
Fig. 5.79 BCD to 10’s complement converter
5.8.6
BCD to Binary Converter
Figure 5.80 shows the logic symbol of BCD to binary converter IC 74184. In six bit BCD to binary conversion, the LSB of BCD inputs is connected to output Y0 and other BCD inputs are applied to pins A through E. The binary outputs are obtained from Y1 to Y5 and Y6, Y7, & Y8 are not used for this BCD to binary conversion as depicted in Fig. 5.81. The truth table of six bit BCD to binary conversion is given in Table 5.38. The LSB of the BCD inputs, A0 and LSB of the binary outputs are not included in this table. To convert a two decade BCD number into binary form, two 74184 ICs are required as depicted in Fig. 5.82. Figure 5.83 shows the conversion of three decades BCD number into binary form using six 74184 ICs.
217
Combinational Logic Design
Fig. 5.81 Six bit BCD to binary converter using IC 74184
Fig. 5.80 Logic symbol of BCD binary converter IC 74184
Table 5.38 Truth table of six bit BCD to binary converter
Enable G
Decimal Equivalent
E B1
BCD Inputs D C B B0 A3 A2
Y5
Binary Outputs Y4 Y3 Y2
A A1
Y1
0 0
01
0
0
0
0
23
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
45
0
0
0
0
67
0
0
0
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
89
0
0
0
1011
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
1
0
1213
0
0
1415
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1617
0
1819
0
1
0
1
1
0
1
0
0
0
0
1
1
0
0
0
1
0
0
1
0 0
2021
1
0
0
0
0
0
1
0
1
0
2223
1
0
0
0
1
0
1
0
1
1
0
2425
1
0
0
1
0
0
1
1
0
0
0
2627
1
0
0
1
1
0
1
1
0
1
0
2829
1
0
1
0
0
0
1
1
1
0
0
3031
1
1
0
0
0
0
1
1
1
1
0
3233
1
1
0
0
1
1
0
0
0
0
0
3435
1
1
0
1
0
1
0
0
0
1
0
3637
1
1
0
1
1
1
0
0
1
0
0
3839
1
1
1
0
0
1
0
0
1
1
218
Digital Electronics: Principles and Applications
Fig. 5.82 Eight bit BCD to to binary converter for two decades using IC 74184
Fig. 5.83 BCD to to binary converter for three decades using IC 74184
5.8.7 Binary to BCD Converter IC 74185 is used to convert binary to BCD form. Figure 5.84 shows the six bit binary to BCD conversion. The LSB of binary inputs, B0 is directly connected with output Y0 and other binary inputs (B1, B2, B3, B4, B5) are applied to pins A through E of IC 74185. The BCD outputs are obtained from Y1 to Y5. The truth table of six bit binary to BCD conversion is given in Table 5.39. The LSB of the binary inputs, B0 and LSB of the BCD outputs are not included in this table. Larger binary numbers can be converted to BCD form by using more 74185 ICs. Figure 5.85 shows the conversion of eight bit binary number into BCD form using three 74185 ICs. Fig. 5.84 Six bit binary to BCD converter using IC 74185
219
Combinational Logic Design Table 5.39 Truth table of six bit binary to BCD converter
Enable
Decimal Equivalent
G
E
Binary Inputs D C B
A
BCD Outputs
B5
B4
B3
B2
B1
Y6
Y5
Y4
Y3
Y2
Y1
0
01
0
0
0
0
0
0
0
0
0
0
0
0
23
0
0
0
0
1
0
0
0
0
0
1
0
45
0
0
0
1
0
0
0
0
0
1
0
0
67
0
0
0
1
1
0
0
0
0
1
1
0
89
0
0
1
0
0
0
0
0
1
0
0
0
1011
0
0
1
0
1
0
0
1
0
0
0
0
1213
0
0
1
1
0
0
0
1
0
0
1
0
1415
0
0
1
1
1
0
0
1
0
1
0
0
1617
0
1
0
0
0
0
0
1
0
1
1
0
1819
0
1
0
0
1
0
0
1
1
0
0
0
2021
0
1
0
1
0
0
1
0
0
0
0
0
2223
0
1
0
1
1
0
1
0
0
0
1
0
2425
0
1
1
0
0
0
1
0
0
1
0
0
2627
0
1
1
0
1
0
1
0
0
1
1
0
2829
0
1
1
1
0
0
1
0
1
0
0
0
3031
0
1
1
1
1
0
1
1
0
0
0
0
3233
1
0
0
0
0
0
1
1
0
0
1
0
3435
1
0
0
0
1
0
1
1
0
1
0
0
3637
1
0
0
1
0
0
1
1
0
1
1
0
3839
1
0
0
1
1
0
1
1
1
0
0
0
4041
1
0
1
0
0
1
0
0
0
0
0
0
4243
1
0
1
0
1
1
0
0
0
0
1
0
4445
1
0
1
1
0
1
0
0
0
1
0
0
4647
1
0
1
1
1
1
0
0
0
1
1
0
4849
1
1
0
0
0
1
0
0
1
0
0
0
5051
1
1
0
0
1
1
0
1
0
0
0
0
5253
1
1
0
1
0
1
0
1
0
0
1
0
5455
1
1
0
1
1
1
0
1
0
1
0
0
5657
1
1
1
0
0
1
0
1
0
1
1
0
5859
1
1
1
0
1
1
0
1
1
0
0
0
6061
1
1
1
1
0
1
1
0
0
0
0
0
6263
1
1
1
1
1
1
1
0
0
0
1
220
Digital Electronics: Principles and Applications
Fig. 5.85
5.9
Eight bit binary to BCD converter using IC 74185
HAZARDS
When the designer designs any combinational and sequential logic circuits, the designer should take certain restrictions and precautions to ensure proper operation of the circuits and to get proper result. Consequently, the designer should have a clear understanding of the mechanism, which produces any malfunction in combinational and sequential circuits, called as hazards. When an input changes from ‘0’ to ‘1’ or ‘1’ to ‘0’, there is a momentary unexpected transient output change due to propagation delay of logic gates. This momentary unexpected transient output change is known as output glitch. A hazard always exists in a combinational circuit when it produces an output glitch while one or more inputs change. There are two types of hazard which generally occur in digital systems: ∑ Static hazards ∑ Dynamic hazards A Static hazard is a momentary change in output when an input signal undergoes a momentary transition, but there will be no effect on steady state output. This type of hazard is present in combinational circuits as well as gateimplemented asynchronous circuits. There are two types of static hazard namely static 0 hazard and static  1 hazard. In static 0 hazard, the output should be ‘0’ but goes momentary to ‘1’ as a result of an input change as shown in Fig. 5.86(a). But in static  1 hazard, the output should be ‘1’ but goes momentary to ‘0’ as a result of an input change as illustrated in Fig. 5.86(b). The Static 1 hazard present in 2level ANDOR circuits and the static 0 hazard present in 2level Fig. 5.86 (a) Static 0hazard and (b) Static 1hazard ORAND circuits. These hazards can be detected and eliminated
221
Combinational Logic Design
for 2level circuits using Kmaps. Dynamic hazards occur when the output changes several times before reaching its steady state value as a result of a single change in input as depicted in Fig. 5.87.
5.9.1
Propagation Delay
Fig. 5.87
Dynamic hazards
When a twoinputs NAND gate or a NOT gate acts as an inverter, there will be a ﬁnite time delay between an input change and the corresponding change of the output. This time delay is called as propagation delay of gate, which is depicted in the timing diagram. In Fig. 5.88, the change in A from – ‘0’ to ‘1’ is followed by a change in A from ‘1’ to ‘0’ with a propagation delay, Dt1 seconds. Similarly – while A changes from ‘1’ to ‘0’ followed by a change in A from ‘0’ to ‘1’ with a propagation delay, Dt2 seconds. So far the combinational circuit analyses have discussed in this chapter ignoring propagation delays and consider only steadystate output. To study the hazard of any combinational and sequential logic circuits, we should consider the propagation delays of all circuit gates.
Fig. 5.88
5.9.2
Propagation delay of gates
Generation of Static 1 Hazards in Combinational Circuit
When an input to a combinational circuit, which is implemented by AND and OR gates is changing, Static1 hazard may be generated at the output of the circuit. The static1 hazard occurs due to different path lengths in the combinational network which introduce different time delays. For example, the – Boolean function O = AC + BC may be implemented by using inverter, AND and OR gates as shown in Fig. 5.89(a) and Kmap of this function is illustrated in Fig. 5.89 (b). A static 1 hazard exists in the following ANDOR circuit when A=1, B=1 and C changes from ‘1’ to ‘0’. The timing diagram of the Boolean function is shown in Fig. 5.90. Assume all gates have same propagation delay Dt. In this circuit there are two paths, the ﬁrst path via G1, G2 and G4 and the second path via G3 and G4. As all gates have the same time delay, it is evident that the delay through the ﬁrst path is greater than the delay through the second path.
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Digital Electronics: Principles and Applications
Fig. 5.89
(a) Logic diagram of O = AC + BC and (b) Three variables Kmap
For the change in C from ‘1’ to ‘0’ and there is a change in the output of G1 from ‘0’ to ‘1’ with a propagation delay Dt followed by the output of G2 changing from ‘0’ to ‘1’. For the other path of the circuit, the output of G3 ﬁrst changes from ‘1’ to ‘0’ with a propagation delay Dt. As the G3, G4 path has the shorter time delay; it is clear from Fig. 5.90 that the change in output propagated along this path occurs earlier in time than the change propagated along the G1, G2 and G4 path. Hence, for a short period of time, the output signal is low or logic level ‘0’ when A = 1, B = 1 and C changes from‘1’ to ‘0’.
5.9.3 Elimination of Static 1 Hazards A static1 hazard occurs in ANDOR circuits Fig. 5.90 Timing diagram of O =AC– + BC when A=1 and B=1 and C changes from 1 to 0. when an input variable and its complement are connected to two different AND gates. Static 1 hazards can be found using Kmaps by ﬁnding adjacent ‘1’ cells that are covered by different product terms. To eliminate static1 hazards, additional product terms or prime implicants are required to cover such cells, which covering the transition of the variable causing the hazard. For the previous example, the static1 hazard can be eliminated by including the additional product term AB. – The consensus product term for the Boolean equation O = AC + BC is AB, and this can be added to the – – original equation O = AC + BC without altering its value. Then output equation will be O = AC + BC + – AB . For the condition A=1 and B=1, the equation reduces to O = C + C +1 and the value of the function – O remains at ‘1’ even if C and C are simultaneously equal to ‘0’ for a very short period of time. The effect of adding the consensus product term can be studied by examining the Kmap plot of the function before and after the addition of the consensus product term. The Kmap of original Boolean function is shown in Fig. 5.89(a). The Kmap plot of the function, after the inclusion of the consensus
Combinational Logic Design
223
product term is shown in Fig. 5.91(a). The comparison of the two Kmap plots is that before the addition of the consensus product, there are two l’s in adjacent cells not covered by the same prime implicant. On covering these two adjacent l’s by the same prime implicant, as in Fig. 5.91(b), the hazard is removed – from the circuit. The hazardfree circuit for the Boolean function O =AC + BC + AB is shown in Fig. 5.91(b), and it will be observed that an additional AND gate has been introduced for generating the required consensus product term AB.
Fig. 5.91
5.9.4
– (a) Three variables Kmap; (b) Implementation of hazardfree function O = AC + BC + AB
Elimination of Static0 Hazards
A static0 hazard occurs in ORAND circuits when an input variable and its complement are connected to different OR gates. The static0 hazards can be determined using Kmaps by ﬁnding adjacent ‘0’ cells that are covered by different sum terms. To eliminate static0 hazards, additional sum terms or prime implicants are needed to cover such cells , which covering the transition of the variable causing the hazard. Figures 5.92 (a) and (b) show the Kmap of three variables function with and without hazard respectively.
Fig. 5.92
(a) Three variables Kmap and (b) Three variables Kmap hazard free
The logic diagram of the OR AND circuit – – of O =(B + C)( A + C ) is shown in Fig. 5.93. – The consensus term for this equation is (A + B) and this can be included in the above equation without altering its value, so that the output – – – function will be O = (B + C)( A + C )(A + B). The – logic diagram of the Boolean function O = (B + – – C)( A + C )(A + B) is illustrated in Fig. 5.94. Fig. 5.93
– – Logic diagram of O = (B + C)( A + C )
224
Digital Electronics: Principles and Applications
Fig. 5.94
– – – Logic diagram of O = (B + C)( A + C )(A + B ) hazardfree
– – – – – When A = 0 B = 0, then the Boolean function O = (B + C)( A + C )(A + B) becomes O = C.C .0 = 0. With the inclusion of the consensus term, the value of the function is always ‘0’ irrespective of whether – C and C are simultaneously equal to ‘1’. – The static0 hazard can be eliminated by the inclusion of the consensus term (A + B). The consequential hazardfree circuit is shown in Fig. 5.94. Elimination of the hazard requires the inclusion of an additional gate which generates the required consensus term. When we want to ﬁnd a static0 hazard, we use the Kmap plot of the function which identiﬁes those combinations of the variables that cause the function value to be ‘0’. To obtain a plot of the 0terms, the inverse of the original function O must be plotted.Consider the equation of the original Boolean function is: – – O = (B + C)( A + C ) – – After inverting of O = (B + C)( A + C ), we ﬁnd – – – O = BC + A C Then inverse function is plotted as shown in Fig. 5.92(a). It is clear from this ﬁgure that the two 0’s in the adjacent cells 010 and 011 are not covered by the same prime implicant. Subsequently the additional – prime implicant A B must be added with the original function, we get – – – – O = BC + A C + A B. – – – – Again inverting O = BC + A C + A B , we obtain the hazardfree function after incorporating the consensus term to the function equation. Therefore the static 0 hazardfree function is – – – O = (B + C)( A + C )(A + B). The algorithm for ﬁnding static 0hazards are given below: Step1: Plot Kmap of the inverse function as shown in Fig. 5.95 after 0s are replaced by 1s and 1s are replaced by 0s in Fig. 5.92. Step2: Look for adjacent 1s not covered by the same prime implicant. Step3: Introduce additional prime implicants to cover all adjacent 1’s that are not covered by the same prime implicant. Step4: Alter the inverse equation by incorporating the additional prime implicants. Step5: Invert the modiﬁed equation to get the hazardfree structure of the function.
Combinational Logic Design
5.9.5
225
Dynamic Hazards
Dynamic hazards occur in combinational logic circuits when the output changes several times before reaching its steady state value as a result of a single change in input. Generally, it is expected by the circuit designer that the output changes either 0 Æ 1 or 1Æ 0. But in practice, when the output transitions are 0 Æ 1 Æ 0 Æ 1 then a dynamic hazard has occurred. Similarly, if an output changes from 1Æ 0 Æ 1 Æ 0 in place of expected change 1Æ 0, then a dynamic hazard is present in the circuit.
Fig. 5.95 Three variables Kmap hazard free
In the above cases, there is a minimum of three changes which is appeared at the output as shown in Fig. 5.87. The dynamic hazard occurs due to the factorisation of a Boolean function. If the function has different fanin, there will be different path lengths through a circuit to obtain a output for speciﬁed inputs. On the other hand, the gates which are used in the circuit may have different time delays. Due to different path lengths and different time delays, there is some possibility to exist a dynamic hazard in the combinational logic circuit. Consider the typical Boolean function: – – O = (AC + BC )(A + C ) Figure 5.96 shows the implementa– – tion of function O = (AC + BC )(A + C) with AND and OR gates. There are three different paths through this circuit for the variable C and consequently, there is a possibility that a dynamic hazard exists in the circuit. The three paths of the circuit are as follows: 1. Through gates G4, G7 and G8 2. Through gates G3, G5, G7 and G8, and 3. Through gates G1, G6 and G8.
Fig. 5.96
Logic circuit of dynamic hazard
As there three variables A, B, and C, there are eight possible combinations of A, B, and C. Because of multiple paths taken by the signal variable C in this circuit, the dynamic hazard is preset. Fig. 5.97 shows the timing diagram of the circuit when A=1, B=1, and C changes from 0 to 1. It is depicted in this ﬁgure that the output of G3 gate has a time delay Dt1 and the output of G6 gate has a time delay Dt2 . The output of G5 and G4 gates have a time delay Dt3 and Dt4 respectively. As ∆t4 > ∆t3 , a static 1 hazard will be present at the output of G7 gate. In case Dt4> Dt3> Dt2 there will be a dynamic hazard at the output of G8 gate as shown in Fig. 5.97. If the designer is designed the circuit either sum of products form (AND OR) or product of sum form (OR AND), in such a way that there are no static hazards present in the circuit. When there will be no static hazards, then the circuit will also be dynamic hazards free. To design a dynamic hazards free circuit of four or more variable Boolean functions, the same procedure can also be followed.
226
Digital Electronics: Principles and Applications
Fig. 5.97
5.10
Timing diagram of dynamic hazard when A = 1 and B = 1 and C changes from 1 to 0
FAULT DETECTION OF COMBINATIONAL LOGIC CIRCUIT
The simplest method of detecting faults in a combinational logic circuit is to apply every possible input combination and compare the circuit response with the known truth table of the circuit. If there is any fault in the circuit, there will be some mismatch between the response of the circuit and truth table and it is known as faulty response of the circuit. But this method has certain limitations as the numbern of input variables ‘n’ increases, the number of tests required increases exponentially and is equal to 2 in case of a combinational circuit. Figure 5.98 shows a typical combinational logic diagram and its response with fault and without fault is given in Table 5.40. F1 is the response, when there is no fault and F2 response can be obtained, if there is a fault present in the circuit. The faulty response F2 is obtained, whenever A = B = C = 0. When input line ‘m’ is held permanently and erroneously at ‘0’, the output of G1 is then ‘0’ whenever B = 1 or 0. If the input line ‘n’ is also held permanently and erroneously at ‘0’, the output of G2 is then ‘0’ whenever A = 1 or 0. The fault F2 is revealed by applying A = 0, B = 0 C = 0 and examining the output. Therefore, this fault is occurred while two input lines ‘m’ and ‘n’ are erroneously low. An examination of the circuit in conjunction with the expected circuit response can revel the nature of the fault. This informal fault analysis of the circuit has been carried out only by inspection. Although it is desirable that more formal techniques for testing should be developed. In this section fault analysis of combinational logic circuits are explained.
Combinational Logic Design
227
Table 5.40
Inputs
Response Response without fault without fault A B C F1 F2
0 0 0 0 1 1 1 1
1. 2. 3.
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
1 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1
Fig. 5.98
–– Logic diagram of F = AB + A C
Generally, unskilled instructors and engineers always faced problems with a combinational logic circuit which contains a unknown fault. To ﬁnd the fault, they often resort to remove semiconductor components at random and attempting to test them. Sometimes, they replace the components with new components without testing the old one. This is not a right method of fault detection and location for the following reasons: When a typical digital system has many components, any fault component will be chosen at random for removal. Due to remove components by inexperienced engineers and their replacement can damage absolutely good components and the circuit board. In digital systems, the most common faults are mechanical failure of switches and faults in soldering connection such as open circuit resistors and open circuit capacitors. Sometimes ICs and other devices are also unlikely malfunction.
In good practice that no component should be removed or replaced until it has been proven faulty. To prove that a component in the combinational logic circuit is faulty, it requires that voltage and continuity checks should be performed upon the circuit while it is powered and the component should be subjected to typical signals. The output is examined for the correct output signals. Suppose a typical system consists of ‘n’ components connected in sequence, we want to locate a fault in the circuit. Then signal tracing will be employed in situations where the intermediate signals are accessible at each point in the chain. Using this technique, the signals at the outputs of the components are examined and compared with the expected response. When correct signals are observed at the input to a certain component but not at its output, then it is clear that the fault must be associated closely with the component. This does not mean that this particular component is faulty. It is also possible that the power supply to this component may be failed. Generally, there are two types of test which are carried out on any combinational logic circuits. 1. Fault detection test, that is used to detect if there any fault in the system. 2. Fault location test, which is used to locate and identify faults. To locate the fault as well as faulty component, assume that the fault is equally likely to occur in any of the ‘n’ links of the chain. The correct procedure is not to trace the signal in turn through each component in the signal chain, for this method requires, on average n/2 tests before the faulty stage
228
Digital Electronics: Principles and Applications
is located. The more efﬁcient method is binary division, where ﬁrstly the presence or absence of the correct signal is established halfway through the chain of ‘n’ stages. Depending upon the result of the single test, either the entire ﬁrst half or the entire last half of the circuit can therefore be eliminated from further attention and subsequent tests conﬁned to the faulty half. The same principle can then be applied to this half of the circuit and so on. By successive binary divisions, the fault can be isolated to one single stage. With a large number of stages, this procedure requires only log2(n) tests to locate the faulty stage. Therefore, signiﬁcantly less than the average of n/2 tests are required for tracing the signal in turn through each stage. For example, if n = 64 sequential signal tracing requires 32 tests on average, where as binary division signal tracing require 8 tests. All faults are either stuckat 0 (sa0) or stuckat1 (sa1) in any combination logic circuit. Stuckat0 means that the line is permanently at logic level ‘0’ and stuckat1 means that the line is permanently at logic level ‘1’ irrespective of logic level that is actually supposed to be present on that line. This widely used fault model does not cover all possible faults. For example, a short circuit of any line to ground fault can be represented by a sa0 fault. While an open circuit on an input line to a TTL gate will cause that input to ﬂoat at a voltage corresponding to an unreliable and noise logic level ‘1’, causing an sa1 fault. When any two paths of combinational logic circuit are inadvertently connected together, the bridging or short circuit fault occurs. In this section, different faults of a 2inputs AND gate and a typical combinational logic circuit are discussed.
5.10.1
Faults of a 2–inputs AND Gate
Figure 5.99(a) shows a 2inputs AND gate and it has two input lines, levelled ‘m’ and ‘n’ respectively, and one output line labelled, o. When there is no fault, the inputoutput relationship of AND gate is shown Table 5.41(a).There are six possible single faults such as any one of m, n and o paths are either sa1 fault or sa0 fault. When the line ‘m’ has a sa0 fault as depicted in Fig. 5.99 (b), it is required to determine the test that will detect this fault. If input B is at logic level ‘1’ level or at logic level ‘0’, the gate output will be permanently held at ‘0’ while the other input A may be at logic level ‘1’ or at logic level ‘0’.The test result is given in Table 5.41(b). Similarly, while the line ‘m’ has a sa1 fault as shown in Fig.5.99(c), input B is at logic level ‘1’ or at logic level ‘0’, the gates output will be ‘1’ or ‘0’ although the other input A may be at logic level ‘1’ or at logic level ‘0’. The test result is illustrated in Table 5.41(c) For a sa1 fault on ‘n’ path as shown in Fig. 5.99(d), input A=1 is the gate enabling signal while the complement of the stuckat fault value must be applied at input B, giving B = 0. Therefore the required test is A = 1 and B=0 and the possible test results are shown in Fig. 5.99 (a) 2inputs AND gate and (b) 2inputs AND gate with sa0 at m and (c) 2inputs AND gate with Table 5.41(d). sa1 at m and (d) 2inputs AND gate with sa1 at n
229
Combinational Logic Design Table 5.41(a)
Remarks
Input A Input B Output O 0
0
0
0
1
0
1
0
0
1
1
1
Normal output. There is no fault
Table 5.41(b)
Remarks
Input A Input B Output O 0
0
0
0
1
0
1
0
0
1
1
0
As m line at sa0 fault, output is always 0
Table 5.41(c)
Input A Input B
Output O
Remarks As m line at sa1fault, output is 1 when A = 0, B = 1 and A = B = 1
0
0
0
0
1
1
1
0
0
1
1
1
Table 5.41(d)
Input A
Input B Output O
0
0
0
0
1
0
1
0
1
1
1
1
5.10.2
Remarks As n line at sa1 fault, output is 1 when A = 1, B = 0 and A = B = 1 Fig. 5.100
Path sensitisation when sa0 fault at m
Faults of a Combinational Logic Circuit
The determination of a test set for a single gate, where there is direct access to the input and output, is achieved by enabling or sensitising the gate. Figure 5.100 shows path sensitisation for testing sa0 fault on line ‘m’. Assume gates G1 and G2 are present inside the IC and their outputs are not accessible. When a sa0 fault occurs at line ‘m’, the sensitisation of two gates G1 and G3 are required to detect the said fault. Here a sensitised path from input A to the output F is considered and detected by thick line. Generally, any combinational logic circuit consists of many gates which are connected in network. Figure 5.100 shows a typical combinational logic circuit and a sa0 fault at ‘m’ path. The output of D and E paths are not directly accessible as D and E paths in side the IC. So that output must be detected
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Digital Electronics: Principles and Applications
at output F. Therefore, the sensitisation of G1 and G2 gates are required. A sensitised path from A to F is shown in Fig. 5.100. When B = 0 and C = 0, point D must be set at 0. The sensitivity of gate G2, point E must be set at A and the normal output F = A. Consequently, there is no difference between normal output and fault output at B = 0 and C = 0. Similarly, the fault can not be detected at B = 0 and C = 1. When B = 1, C = 0 and A = 1, the normal output is 1, but the response of the circuit is 0 due to sa0 fault at m. In the same way, if B = 1, C = 1 and A = 1, the normal output is ‘1’, but the response of the circuit is ‘0’. The results of combinational logic circuit are summarised in Table 5.42. Some times faults are undetectable, when circuit malfunction sa0 and sa1 faults. During design of combinational logic circuit, the design will develop the hazard free circuit to avoid undetectable fault. Table 5.42
Path Gate sensitisation input signals Fault test condition
5.10.3
ADF and sa0 fault at m B = C =0
B=0C=1
B=1C=0
A=0 A=1 A=0 A=1 A=0
B=1C=1
A=1 A=0
A=1
Normal output F
1
0
0
0
1
1
0
1
Faulty output F
1
0
0
0
1
0
0
0
Bridge Faults
When any two lines of a combinational logic circuit is shorted, there is a short circuit fault in the circuit. This type of faults occur due to careless soldering that leaves some soldering materials between two adjacent lines and subsequently these lines are connected. This short circuit fault is known as bridge fault. Figure 5.101 (a) shows the bridge fault mpo path and Fig. 5.101 (b) shows the bridge fault nqo path. The test results of bridge fault are given in Table 5.43. – – – While inputs B and A have same logic values (B = 0 = A or B = A = 1) and though ‘m’ and ‘n’ paths are interconnected, no faults can be detected as inputs of gates G1 and G2 are held at their correct val– ues. But when B and A inputs are driven to complementary – logic levels means B = 0, A = – 1 or B = 1, A = 0, the circuit will be different from actual required output. Then there are different possibilities of output Fig. 5.101 Bridge fault (a) mpo path (b) nqo path as follows: 1. When the input signal is supposed to be set at 1 may be pulled down to 0, if the circuit is made with TTL gates. 2. When input signal is supposed to be set at 0 may be pulled up to 1, if the circuit is made with ECL gates. 3. Both inputs may be pulled to an indeterminate voltage level, which cannot be interpreted as either logic level ‘1’ or logic level ‘0’. The driving gates may fail to operate properly and consequently some stuck at faults occur on gates.
231
Combinational Logic Design Table 5.43
Path
mpo path
nqo path
Input signals
A = 0, B = 0, C = 0
A = 1, B = 1,C = 1
Normal path signals
p = 0, q = 1, and o = 1
p = 1, q = 0 and o = 1
Fault
mn bridge fault
Test signals
– (A , B) = (1,0), p = 0, q = 0 and o = 0
mn bridge fault – ( A , B ) = (0,1), p = 0, q = 0 and o = 0
Normal output
1
1
Faulty output
0
0
SUMMARY Combinational logic circuits can be used to design any type of logic operations. Some of these logic operations are multiplexing, demultiplexing, encoding, decoding and arithmetic operations of binary numbers. In this chapter, the working principle of multiplexers, demultiplexers, decoders and encoders are explained and their applications are also incorporated. Commonly used MSI ICs –7447 BCD to seven segment decoder, 7442 BCD to Decimal decoder, 74154, 74148, 74147, 74157, 74158, 74150, 74151A, 74237 are discussed. When MSI ICs are used to design combinational logic circuits, digital system design will be simplified and efficient. In this chapter, hazards and fault detection of combinational logic circuits are explained.
MULTIPLE CHOICE QUESTIONS 1.
2.
3. 4. 5.
6.
A multiplexer has (a) One data input and two or more than two data outputs (b) One data output and two or more than two data inputs (c) One data output and a number of data input and a number of select inputs (d) One data output and a number of select inputs A multiplexer can be used as (a) Counter (b) Shift register (c) Combinational circuit (d) 7  segment display A multiplexer, with 3bit data select inputs, is a (a) 4:1 multiplexer (b) 8:1 multiplexer (c) 16:1 multiplexer (d) 32:1 multiplexer. A two variable Boolean logic function can be implemented by (a) 4:1 multiplexer, (b) 1:4 demultiplexer, (c) NAND gate (d) NOR gate A demultiplexer has (a) One data input and two or more than two data outputs (b) One data output and two or more than two data inputs (c) One data output and a number of data input and a number of select inputs (d) One data output and a number of select inputs A demultiplexer can be used as (a) A counter (b) A ﬂipﬂop (c) A combinational circuit (d) A 7  segment display
232 7. 8. 9. 10.
11. 12.
13. 14. 15.
Digital Electronics: Principles and Applications The output of a 2inputs gate is ‘1’ and its inputs are unequal. This is a (a) EXOR gate (b) AND gate (c) NOR gate (d) ANDgate The ————— gate is used as two bits comparator. (a) AND ( b) OR (c) NAND (d) EXOR Multi channel signals can be transmitted through a single channel by using _________. (a) Demultiplexers (b) Encoder (c) Decoder (d) Multiplexer Minimisation of Boolean logical expressions helps to reduce (a) Space (b) Number of gates (c) Cost (d) Space, number of gates and cost The number of 2lineto4line decoders are used to design a 4line to 16line decoder is (a) 2 (b) 4 (c) 5 (d) 6 In 7segment display system, zero blanking is used to blankout (a) All the leading zeros ( b) All the trailing zero (c) The zero in the MSB (location) (d) a and b In 8:3 priority encoder, highest priority is given on (a) 7 (b) 0 (c) 9 (d) F In 16:4 priority encoder, lowest priority is given on (a) 7 (b) 0 (c) 9 (d) F In binary to Gray converter, _______ gate is used (a) AND ( b) OR (c) NAND (d) EXOR
REVIEW QUESTIONS 5.1. 5.2. 5.3.
5.4.
5.5.
5.6. 5.7.
(a) Deﬁne decoder. (b) Design a decoder circuit to convert binary numbers to decimal. (a) Explain cascade decoder with example (b) Design a 5to32 line decoder using 2to4 line decoder and 3to8 line decoder. A combinational circuit is deﬁned by the following equations F1 = AB+ABC; F2 = A+B+C; F3 = AB Design a circuit that can implement the above equations using a decoder and NAND gates. A combinational circuit is deﬁned by the following equations – – – F1=ABC+ABC ; F2=A+B+C+D; F3=A+B+CD+AD; F4=ACD+A CD+BCD+BCD Design a circuit that can implement the above equations using a decoder with NAND gates. Implement the following 4 variables functions using a decoder having active low outputs and NAND gates. F1=S (0,1,3,9,12,14); F2=S(5,9,10,12,13,15) F3=P (0,3,8,11,12,15); F4=P(1,2,7,8,11,12,14) Design a 3 to 8 line decoder using NOR gates only and draw its circuit. What will be the output of decoder 74154, if the enable is low, the data input low and the select inputs are as follows? (a) 1110 (b) 1001 (c) 0101 (d) 0000
Combinational Logic Design 5.8. 5.9. 5.10.
5.11.
5.12.
5.13.
5.14.
5.15.
5.16. 5.17. 5.18. 5.19. 5.20. 5.21. 5.22. 5.23. 5.24. 5.25.
233
Draw a diagram for 7segment LED display driver and explain its operating principle. (a) Deﬁne encoder. Distinguish between encoder and decoder. (b) Design a encoder circuit for 10 line to 4 line priority encoder. (a) Describe the operation of a multiplexer using functional block diagram. (b) Enumerate some of the applications of multiplexers. (c) Explain how Boolean functions will be implemented using multiplexers. (a) What is demultiplexers? Distinguish between (i) A multiplexer and demultiplexer (ii) Decoder and demultiplexer (b) Draw the logic diagram of a one line to four line demultiplexers. Implement the following 3variable Boolean functions using 4:1 multiplexers: (a) F1= Sm(0,2,3,5,7) (b) F2=Sm( 1,3,4,6,7) (c) F3=Sm( 0,2,4,5,6,7). Implement the following 4variable Boolean functions using 8:1 multiplexers (a) F1=Sm(0,1,3,5,6,8,9,11,12,13) (b) F2=Sm( 0,7,8,9,10,11,15) (d) F3=Sm(0,1,3,5,9,10,11,13,14,15) Implement the 6variables Boolean functions f = Sm( 0,1,3,5,7,12,14,16,18,20,22,26,28,30,32,34,37,39,41,43,45,50,51,53,60,61,62,63) using eightinput multiplexers and 4input multiplexers Design a BCD to 7 segment decoder using (a) Dual 4:1 multiplexers (b) 1;16 demultiplexer (c) BCD to decimal decoder Design a 32:1 multiplexers using two 16:1 multiplexers. Design a 1:32 demultiplexer using 1:8 and 1:16 demultiplexer. Design a logic circuit for converting Excess3 to 8421 code. Design a GREY to BCDcode converter using MSI ICs and logic gates. Design a pulse train 11011001 using MSI ICs. Draw a connection diagram to show how multiplexer 74151 should be used to implement the Boolean – – – function F = A BC + AB C + ABC + ABC Draw a diagram to show how IC 74237 can be used as an 8output data distributor. Design a four digit 7 segment display system. Design a 5¥3 dot matrix display system to display alphanumeric character E. Design a 64:1 multiplexer using 8:1 and 16:1 multiplexers.
CHAPTER
6 ARITHMETIC LOGIC CIRCUITS 6.1
INTRODUCTION
The arithmetic and logical operation of digital circuits are already explained in combinational logic chapter. The design and implementation of arithmetic and logic circuits using gates are also explained in that chapter. Nowa days, Medium Scale Integrated (MSI) circuits are used in multibit addition, multibit subtraction, and all arithmetic logic operations. Presently, MSI ICs are available in market. But all arithmetic functions are not available in a standard MSI IC. The designer should select a particular ALU IC and can modify its operation as per requirement. In this chapter, arithmetic and logic operations such as addition, subtraction, multiplication and division are explained with the help of logic gates and integrated circuits.
6.2
BINARY ADDITION
To design binary adder circuits, the basic knowledge of arithmetical operations in base 2 is required. Figure 6.1 shows the governing rules of addition of two binary numbers. When two ones are added, then sum is zero and a carry bit is generated. Then the carry bit is added to the next pair of bits. In this section, half adder, full adder and Fig. 6.1 Addition of two binary numbers 4bit adder circuits are explained.
6.2.1 Table 6.1
Truth table of half adder
Inputs Addend Augend (A) (B) 0 0 0 1 1 0 1 1
Outputs Sum Carry (S) (C) 0 0 1 0 1 0 0 1
The Half Adder
A half adder is the simplest digital adder and it is used to add two binary digits, an addend (A) and an augend (B). After addition of two binary digits A and B, the sum (S) and carry (C) are generated. This carry signal may be used to the next stage of the addition. Table 6.1 shows the truth table for adding two binary digits A and B. The Boolean expressions of the sum (S) and carry (C) are – – Sum S = A⊕B = AB + A B Carry C = A.B
235
Arithmetic Logic Circuits
The sum can be implemented by using an ExclusiveOR gate and an AND gate can be used for carry generation as shown in Fig. 6.2(a). Figure 6.2(b) shows the implementation of the sum and carry functions using AND and OR gates. A block diagram representation of a half adder (HA) is also depicted in Fig. 6.3.
Fig. 6.2 Implementation of half adder (a) Using EXOR and AND logic gates (b) Using AND and OR logic gates
Fig. 6.3 Block diagram of half adder
6.2.2
The Full Adder
A halfadder only adds the two input bits, but a full adder can add three input bits, an addend (A), an augend (B) and carry input (Cin) generated by the previous stage addition. It has two outputs, sum (S) and carry out (Cout). Table 6.2 shows the truth table of full adder. K  maps and logic gates are generally used to implement the sum (S) and carry out (Cout). Table 6.2
Truth table of full adder
Inputs
Outputs
Carry in (Cin)
Addend (A)
Augend (B)
Sum (S)
Carry out ( Cout)
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
0 0 0 1 0 1 1 1
The block diagram of full adder is shown in Fig. 6.4. In this ﬁgure, inputs are the two binary bits A and B and the carry input (Cin) and outputs are the sum output (S) and the carryout (Cout). The sum (S) and carryout ( Cout) can be expressed in Boolean equations from the truth table as follows:
Fig. 6.4 Block diagram of Full adder
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Digital Electronics: Principles and Applications
–– – — –— Sum S = A B Cin + A BCin + AB Cin + ABCin – – — Carry C = A BCin + AB Cin + ABCin + ABCin The sum can also be expressed as – – — –— – ——— S = A (B Cin + BCin) + A(B Cin + BCin) = A (B ⊕ Cin) + A B ⊕ Cin ) Finally, sum is S = A⊕B⊕Cin and can be implemented using an three inputs EXOR gate. The carry out may be rewritten as – – — C = (A B + AB )Cin + AB(Cin + Cin) = (A⊕B)Cin+ AB The Kmaps for sum and carry out are shown in Fig. 6.5(a) and (b) respectively. The carryout equation may be written in simpliﬁed form using Kmap as given below: Cout = AB + BCin+ ACin = (A⊕B)Cin+ AB
Fig. 6.5
Kmap of Full adder (a) for sum (b) for carry out
Implementation of full adder circuits using AND, OR and EXOR gates are depicted in Fig. 6.6(a) and Fig. 6.6(b). Full adder circuit can also be implemented with the help of two halfadder circuits as shown in Fig. 6.7. The ﬁrst half adder is used to add two inputs A and B and generate sum S′ and carry output C′. Then second half adder combines the sum (S′) and carry input (Cin) and generate ﬁnal sum S and carry out C′′. The ﬁnal carry can be produced by using OR operation between C′ and C′′.
Fig. 6.6(a)
Implementation of full adder using AND and OR gates (b) der using EXOR, AND and OR gates
Implementation of full ad
Arithmetic Logic Circuits
237
Fig. 6.7 Block diagram of full adder using half adders
6.2.3
The 4 Bit Binary Full Adder
The addition of two 4bit digit binary numbers, A = A3 A2 A1A0 and B=B3B2B1B0 is shown in Fig. 6.8. Initially, the lest signiﬁcant bits A0 and B0 are added with carry input Cin and generate a sum S0 and a carry C0. If there is no carry input (Cin=0), only two lest signiﬁcant bits A0 and B0 will be added. The carry output Fig. 6.8 Addition of two 4 bit numbers of adder C0 can be used as carry input of the next adder operation. Then A1, B1 and carry C0 are added to generate a sum S1 and a carry C1. Similarly, A2, B2 and carry C1 are added to produce S2 and a carry C2 , which is used as carry input of the next adder. In the same way, A3, B3 and carry C2 are added to generate a sum S3 and a carry C3. After completion of addition, the sum is S3S2S1S0 and carry output is C3. The addition of two 4bit numbers Fig. 6.9 Block diagram of 4 bit adder using full adders and an half adder can be implemented by using full adder and half adder circuits. When initial carry input Cin=0, the full adders and one half adders can be used to implement addition of two 4bit numbers as depicted in Fig. 6.9. The above operation can be done using four full adder circuits as shown in Fig. 6.10 when carry input (Cin) of ﬁrst full adder is grounded. These circuits are also known as ripple through adder for the reason that carries from one stage Fig. 6.10 Block diagram of 4bit adder using full adders of the adder may be ripple through a
238
Digital Electronics: Principles and Applications
number of the subsequent stages. In this case, carry generated form ﬁrst full adder is ripple through all the full adders and ﬁnally the carryout is generated from the last stage of addition. Similarly, an ‘n’ bit adder can be build by connecting proper number of full adders as shown in Fig. 6.11. In this case, the carry Fig. 6.11 Block diagram of ‘n’ bit adder using full adders output are passed from one full adder to the next full adder but last carry out put will be the ﬁnal carry output of the addition. The ﬁnal result of ‘n’ bit adder is the sum S = SN1 SN2….S1 S0 and carry out Cout=CN1. Commonly used MSI ICs for addition are IC74181, IC74182 and IC74183. The four full adders are available in a single IC. There are eight inputs (four for A and four for B), four pins for the sum outputs, one pin for the carry in and one for carryout and two pins for Fig. 6.12 8 bit addition using two 74283 ICs the supply voltage. The example of a 8 bit adder using two 74283 ICs is shown in Fig. 6.12. Similarly, two or more number of ICs can be connected to implement an ‘n’ bit adder circuit.
6.3
Fig. 6.13 Subtraction of two binary numbers
6.3.1
BINARY SUBTRACTION
Figure 6.13 shows the governing rules of subtraction of two binary numbers. The binary subtraction of two binary numbers has the four possible combinations. After performing the subtraction 01, the result difference, D = 1 and borrow, Bout = 1. This borrow (Bout) will be used as borrow input Bin for the next stage. In this section, half subtractor, full subtractor, 4bit subtractor and half adder/subtractor circuits are explained.
Half Subtractor
A half subtractor is used to subtract two binary digits, the minuend (A) and the subtrahend (B). After subtraction of two binary digits A and B, the difference, D = A – B and the borrow, Bout are generated. This borrow signal may be transferred to the next stage of subtraction. Table 6.3 shows the truth table for subtraction two binary digits A and B. The Boolean expressions of the difference (D = A – B) and the borrow (Bout) are
239
Arithmetic Logic Circuits
– – Difference D = A⊕B = AB + A B – Borrow Bout = A B Figure 6.14 shows the implementation of the difference (D) and the borrow (Bout) functions using AND and OR gates. The block diagram representation of a half subtractor (HS) is also shown in Fig. 6.15.
Fig. 6.14
6.3.2
Table 6.3
Inputs
Outputs
Minuend Subtracted (A) (B) 0 0 0 1 1 0 1 1
Fig. 6.15
Implementation of half subtractor using logic gates
Truth table of Half subtractor Difference (D) 0 1 1 0
Borrow (Bout) 0 1 0 0
Block diagram of half subtractor
The Full Subtractor
A full – subtractor (FS) has three input bits, the minuend (A), the subtrahend (B) and the borrow (Bin). The FS performs twosubtraction operations. In ﬁrst subtraction, (A–B) is done and in second subtraction, (ABBin) is completed. After ﬁnal subtraction of three binary digits A, B and Bin, the difference (D) and the borrow output (Bout) are generated. Then borrow, Bout will be transferred to the next stage of subtraction. Table 6.4 shows the truth table of full subtacter. Kmaps and logic gates are used to implement the difference (D) and the borrow output (Bout) of full subtractor. Table 6.4 Truth table of full subtractor
Borrow
Inputs Minuend
Outputs Difference Borrow
Subtracted
(Bin)
(A)
(B)
(D)
(Bout)
0
0
0
0
0
0
0
1
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
1
1
1
1
1
The block diagram of full subtractor is shown in Fig. 6.16. The difference (D) and the borrow output (Bout) can be expressed in Boolean equations from the truth table as follows:
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Digital Electronics: Principles and Applications
Fig. 6.16
Block diagram of full subtractor
–– – — –— difference D = A B Bin + A BBin + AB Bin + ABBin –– – — – borrow output B out = A B Bin + A BBin + A BBin + ABBin The simpliﬁed expression of difference is — –— – – – + BBin) + A(B Bin + BBin) = A (B ≈ D = A (B— Bin—– Bin) + A B ≈ Bin = A ≈ B ≈ Bin
The borrow out may be rewritten as – — –– – –— —– Bout = A B(Bin + Bin) + (A B + AB)Bin = A B + A ≈ B Bin The Kmaps of difference (D) and the borrow output (Bout) are shown in Fig. 6.17 (a) and Fig. 6.17 (b) respectively. From Kmap, the simpliﬁed Boolean expression of borrow output is – – Bout = AB + ABin + BBin
Fig. 6.17 Kmap of full subtractor (a) for difference (b) for borrow output
Figure 6.18 shows the implementation of full subtractor circuits using EXOR, AND, and OR gates. Full subtractor circuit can also be implemented with the help of two half subtractor circuits as shown in Fig. 6.19. The ﬁrst half subtractor is used to subtract two inputs, A and B, and generate difference (D) and the borrow output (Bout)¢ or B¢. Then the second half subtractor can be used to subtract the borrow Bin from difference Fig. 6.18 Implementation of full subtractor using (D) and generate ﬁnal difference (D) and the logic gates borrow output (Bout)¢¢ or B¢¢. The ﬁnal borrow output can be produced by using OR operation between B¢ and B¢¢. Two 4bit numbers can be subtracted by using an array of full subtractor (FS) and half subtractor (HS) circuits as depicted in Fig. 6.20 and Fig. 6.21. Similarly, two ‘N’bit numbers can also be Fig. 6.19 Block diagram of full subtractor subtracted by using an array of full subtractors as shown in Fig. 6.22. The number B=BN1 BN2…..B1 B0 is subtracted from A=AN1 AN2……A1 A0. If initial borrow input is not present, in least signiﬁcant bit subtraction, one half subtractor can be used and for all other bits full subtractors are used. The above operation can be implemented by using four full subtractor circuits. In this case borrow input of ﬁrst full subtractor is grounded. The borrow output is passed from one full subtractor to the next full subtractor but last borrow output will be the
241
Arithmetic Logic Circuits
ﬁnal borrow output of the subtraction. The ﬁnal result of ‘N ’ bit subtraction is the difference (D) =DN1 DN2 ….D1 D0 and the borrow output Bout=BN1.
Fig. 6.20 Four bit subtractor using FS
Fig. 6.22
6.3.3
Fig. 6.21 Four bit subtractor using FS and HS
Four bit subtractor using FS
Half Adder/Subtractor
Figure 6.23 shows the half adder/subtractor circuit. In this circuit, a controlled XOR gate is used to control addition as well as subtraction operations. When mode control M=0, the output is sum S = A ≈ B and carry C = AB and the circuit behaves as adder. When mode control M=1, the output is difference D = – A ≈ B and borrowoutput B = A B. Therefore, the circuit works as a subtractor.
6.3.4
2’s Complement Adder/Subtractor
The XOR gate can be used, as an inverter when it’s one input is high. Figure 6.24 shows the one’s complement of a 4bit number. When input B=B3B2B1B0 and mode control M=1, the output will be – –– – B 3B2B1B 0. 4bit adder/subtractor using 2’s complement is shown in Fig. 6.25. Input A = A3A2A1A0 is directly connected with full adders but input B=B3B2B1B0 is fed to XOR gate and gates output are connected with full adders. If mode control M = 0, output of XOR gates are same as inputs. Therefore, two four bit numbers A= A3A2A1A0 and B = B3B2B1B0 are added. During subtraction, mode control M = 0, output of XOR gates are complements of – –– – inputs B 3B2B1B 0. If Cin = 1, the addition of two 4bit inputs A = – –– – A3A2A1A0 and B = B 3B2B1B 0 with carry as follows.
Fig. 6.23 Half adder/subtractor
Fig. 6.24
one’s complement of a 4 bit number
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Digital Electronics: Principles and Applications
– –– – B 3B2B1B 0 1’s complement 1 Cin = 1
+
B¢3 B¢2 B¢1 B¢0 2’s complement of B3B2B1B0 A3 A2 A1 A0 Minuend + B¢3 B¢2 B¢1 B¢0 2’s complement of B3B2B1B0 S3 S2 S1 S0 Difference Fig. 6.25
4 bit adder/subtractor
Hence, the ﬁnal result S3 S2 S1 S0 will
be the difference between A – B. The addition/ subtraction can be implemented by using 4 bit adder MSI IC 74283 and a quad XOR gate IC 7486 as depicted in Fig. 6.26. The mode control signal is used to select addition and subtraction operations. If M = 0 and Cin = 0, the least signiﬁcant stage of the adder acts as a half adder. Then IC 74283 acts as adder. When M = 1 and Cin = 1, the adder IC performs the subtraction operation. In this case, 7486 act as an inverter and the least signiﬁcant stage of the adder acts as 2’s complement subtraction. Figure 6.27 shows the 1’s complement addition/subtraction operation. In this case, the end about carry (EAC) is connected with Cin of the adder.
Fig. 6.26
Addition/subtraction using 2’s complement
Fig. 6.27
Addition/subtraction using 1’s complement
6.3.5 Sign Magnitude Binary Subtractor The two’s complement of a binary number is generally used to represent a negative number. The negative number is derived from the following expression as given below: 2’s complement of a number = 1’s complement of number +1 The sign binary equivalent of decimal number +1 is 0 001 Sign
Magnitude
Arithmetic Logic Circuits
243
The ﬁrst bit, 0 stands for positive sign and the Table 6.5 4 bit signed binary number next three bits are used to represent the magnitude Decimal number Signed binary number of the number. The 1’s complement of 0001 is 1110. Sign Magnitude Then 2’s complement is 1110 +1= 1111 which rep+7 0 1 1 1 resents decimal number, –1. Here the ﬁrst bit, 1 +6 0 1 1 0 stands for negative sign. Table 6.5 shows the 4 bit +5 0 1 0 1 signed binary number. +4 0 1 0 0 Figure 6.28 shows the 4bit sign magnitude bi+3 0 0 1 1 nary subtraction. During subtraction, the 4 bit sign +2 0 0 1 0 subtracted B is converted into two’s complement to +1 0 0 0 1 change the sign of number. It is depicted in Fig. 6.28 0 0 0 0 0 that the 4 bit sign magnitude binary number A (A0, –1 1 1 1 1 A1, A2, A3) is directly fed to ﬁrst 4 bit adder IC 74283 –2 1 1 1 0 and the other number B (B0, B1, B2, B3) is inverted –3 1 1 0 1 using quad EXOR gates and fed to the 4 bit adder. –4 1 1 0 0 When Cin is 1, the two’s complement of the 4 bit –5 1 0 1 1 sign number B is added with A and the difference of –6 1 0 1 0 the two 4 bit sign magnitude binary numbers can be –7 1 0 0 1 ﬁnd at the outputs S¢3 S¢2 S¢1 S¢0 of IC 74283. If S¢3 = –8 1 0 0 0 0, output will be S¢2 S¢1 S¢0. When S¢3 = 1, output will be two’s complement of S¢2 S¢1 S¢0. Therefore the second 74283IC is used to generate the 2’s complement of the output S¢2 S¢1 S¢0 and ﬁnal output can be obtained at S2 S1 S0. The ﬁnal output of the two 4 bit sign magnitude binary subtraction is the sign bit and the magnitude of the result of subtraction as given in Fig. 6.28.
6.3.6
BCD Adder
Figure 6.29 shows the one digit BCD adder circuit. Two BCD inputs are applied at inputs A and B of 4 bit binary adder IC 74283. The sum output of two BCD inputs is obtained from S3 S2 S1 S0 of IC 1. If the output is less than equal to 1001(9), there is no requirement of decimal adjustment. When output is greater than 1001(9) or any value from 1010 to 1111, the output must be converted into decimal form. Therefore, 0110(6) will be added with S3 S2 S1 S0 to generate units and tens. For this, output of IC1 is directly fed to the B inputs of IC2. The carry output and the sum outputs S3, S2 and S1 of IC1 are connected through an inverter and two NAND gates to a 3inputs NAND gate. The output of NAND gate is connected with A2 and A 1 input terminals of IC2. A0 and A3 input terminals of IC2 are
Fig. 6.28 4 bit sign magnitude binary subtraction
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Digital Electronics: Principles and Applications
grounded. The final result will be obtained from the output of IC2 after decimal adjustment as depicted in Fig. 6.29.
6.4
Fig. 6.29 BCD adder
CARRY LOOKAHEAD ADDITION
In the 4bit adder, the carry signals have to propagate from one fulladder to the next full adder. The delay generated to produce carry output is 4d, where d = propagation delay of each stage. This propagation delay can be increased with number of bits. The circuit performance can be improved by increasing the speed of operation. Reducing the propagation delay, we can increase the speed. Generally, lookahead carry generator technique is used for this operation. The lookahead carry generator involves two Boolean functions namely Generate (G) and the Propagate (P). For input bits Ai and Bi, Generate (Gi) and the Propagate (Pi) functions are deﬁned as: Gi = AiBi Pi = Ai ≈ Bi The carry output equation will be Cout=(Ai≈Bi)Cin+ AiBi and the above equation can be rewritten in terms of Generate (Gi) and the Propagate (Pi) Cout=PiCin+Gi For a 4bit adder, the generation and propagation terms for each stage are as follows
G0=A0B0 P0=A0≈B0 G1=A1B1 P1=A1≈B1 G2=A2B2 P2=A2≈B2 G3=A3B3 P3=A3≈B3 The carry outputs for the different stages are C0= P0Cin + G0 C1= P1C0 + G1 = P1 (P0Cin +G0) + G1 = P1 P0Cin + P1G0 + G1 C2= P2 C1 + G2= P2(P1 P0 Cin + P1 G0 + G1)+ G2= P2 P1 P0 Cin + P2 P1 G0+ P2 G1+ G2 C3= P3C2 + G3 = P3 P2 P1 P0Cin+ P3 P2 P1 G0+ P3 P2 G1+ P3 G2+ G3 The ﬁnal carryout equation can be rewritten as C3=PCin+ G where G = P3 P2 P1G0+ P3 P2 G1+ P3 G2+ G3 and P = P3 P2 P1 P0 This carry look ahead generator can be implemented using AND, OR and XOR gates as shown in Fig. 6.30. IC 74283 performs the addition of two 4bit binary numbers with full internal carry look ahead facility.
Arithmetic Logic Circuits
Fig. 6.30
Carry look ahead generator
Fig. 6.31
245
Pin diagram of IC 74283
The pin diagram and logic symbol of IC 74283 are illustrated in Fig. 6.31 and Fig. 6.32 respectively. The sum outputs are provided for each bit (S3 S2 S1 and S0) and the resultant carry (C4) is obtained from the fourth bit. These adders feature full internal look ahead across all four bits. This provides the system designer with partial look  ahead performance at the economy and reduced package count of a ripplecarry implementation. The features of IC 74283 are given below: ∑ Fullcarry lookahead across the four bits ∑ Systems achieve partial lookahead performance with the economy of ripple carry ∑ Typical add times: two 4bit words 15 ns; two 8bit words 25 ns; two 16bit words 45 ns ∑ Typical power dissipation per 4bit adder is 95 mW. For 8 bit addition, two 74283 IC are connected in cascade and typical delay time is about 25ns. A 16 bit addition can be implemented by cascade connection of four 74283 ICs and delay time to get the ﬁnal result will be approximately 45ns.
6.5
SERIAL ADDER
Figure 6.33 shows the serial addition of two N  bit numbers A = AN1 AN2 …. A1 A0 and B= BN1, BN2… B1 B0. This circuit Fig. 6.32 The IC 74283 4 bit carry look ahead adder consists of three shift registers, a full adder and a D ﬂipﬂop. In serial adder, addition is started from the least signiﬁcant bit. Initially, the full adder inputs are Ai=A0, Bi=B0 and Ci–1=0. The outputs are sum Si=S0=A0≈B0 and carry Ci = C0= A0B0. When the ﬁrst clock pulse is applied, S0 is loaded into the SUM register. Carry out Ci=C0 is connected with the D ﬂipﬂop. Therefore, ﬂipﬂop output Q = D after ﬁrst clock pulse and is fed
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Digital Electronics: Principles and Applications
into full adder as carry input. In the mean time, the next addend A1 and augend B1 are input into the full adder from register A and B respectively as shift registers are shifted to the right by one bit. Then the full adder inputs are Ai=A1, Bi=B1 and Ci1=C0. The outputs are sum Si=S1=A1≈B1 and carry Ci=C1=A1.B1 Just after the application of second Fig. 6.33 Two N bit serial adder clock pulse, S1 is loaded into the sum register, and S0 shifted by one bit right. The carry Ci=C1 is also fed the input terminal Ci1 of full adder. Then the addend A2 and augend B2 are input into the full adder from registers A and B due to right shifting. Therefore, the full adder inputs are Ai= A2, Bi=B2 and Ci1=C1. The outputs are Sum Si=S2=A2≈B2 and carry Ci=C2=A2.B2. When the next clock pulse is applied, the sum S1 is loaded into SUM register and S1 and S0 are shifted by one bit right. The similar operation will be repeated on each clock pulse. Hence, after N clock pulses, the content of A and B registers are zeros and Ai = 0, Bi = 0. When Ai = Bi = 0, the ﬁnal carry out will be available at the sum output of full adder and loaded into the sum register after N+1 clock pulse. Consequently, ﬁnal sum S = SN1 SN2 ……S1 S0 and carry C = CN1 are stored in the sum register.
6.6
PARALLEL ADDITION
Figure 6.34 shows the ‘N’ bit parallel adder circuit. It consists of addend register, augend register, full adders and sum register. In parallel addition, the addend (A) and augend (B) are added simultaneously and it is faster than serial adder but less economical. Before addition, the addend and augend are stored in addend register and augend register respectively. These registers are not shift registers but used as storage registers and it is not required to shift bits serially. The register is a set of D ﬂipﬂops Fig. 6.34 Parallel addition and number of ﬂipﬂops actually depends upon the number of bits of addend and augend. The ﬂipﬂops in the addend register and augend register are completely independent of each other but a common clock pulse operates the ﬂipﬂops. Initial addend (A = AN1 AN2 …. A1 A0) and augend (B = BN1, BN2… B1 B0) are applied to the input terminals of respective ﬂipﬂops. Just after application of clock pulses, the addend (A = AN1 AN2 …. A1 A0) and augend (B = BN1, BN2… B1 B0) are loaded into registers and available at the output terminals of corresponding ﬂipﬂops. Then addend (A = AN1 AN2 …. A1 A0) and augend (B = BN1, BN2… B1 B0) are added with carry input Cin in full adders. After addition the sum (S = SN1,SN2… S1 S0) and carry (CN) are
Arithmetic Logic Circuits
247
available from full adders and fed to the ﬂipﬂops of sum register. When the clock pulse is applied, these results will be stored in sum register. The parallel addition has speed limitation. The carry generated of full adder must be ripple through from one full adder to next full adder. For example, carry output of ﬁrst full adder C0 will be obtainable after a time equal to the propagation delay time of the full adder. Then this carry C0 will be used as carry input of next full adder and generates a carry C1 after a second propagation delay. This process will continue till the additions of all bits are completed. The sum of the propagation delays of all full adders is actually the total delay time of operation. To reduce the total delay time, the fast adder circuits are incorporated the carry look ahead (CLA) to ripple through carry of adders. The addition of K Nbit numbers is S = X(1) +X(2) + X(3) +….+ X(K). When more than two Nbit numbers are added, the Fig. 6.34 must be modiﬁed into Fig. 6.35. This adder circuit consists of Nbit augend register, N bit full adder and N+1 bit accumulator register. Actually, the N bit full adder is the cascade connection of N full adders. Initially, all ﬂipﬂops of augend register and accumulator register are in reset condition and the ﬁrst number X(1) [ XN1(1)………. X2(1) X1(1) X0(1) ] is fed to the input terminals of D ﬂipﬂops of the augend register. After application of clock pulse, the number X (1) is input to the BN1 ……B2 B1 B0 terminals of N bit full adder and other terminals of N bit full adder AN1 ……A2 A1 A0 are 0 as the outputs of N–bit accumulator are 0. Then N bit full adder circuit added two N bit number AN1 =0 ……A2 =0 A1 =0 A0=0 and BN1 = XN1(1) ……B2= X2(1) B1= X1(1) B0 = X0(1) Fig. 6.35 Parallel addition of K N  bit numbers with carry input Cin=0. After addition, the output of N bit full adder will be XN1(1)………. X2(1) X1(1) X0(1). Therefore, the X(1) will be stored in the accumulator register when the second clock pulse is applied and fed into the input terminals AN1 ……A2 A1 A0 of Nbit full adder and the next number X(2) [ XN1(2)………. X2(2) X1(2) X0(2) ] is also loaded in augend register. Now A = X(1) and B = X(2). The output of Nbit full adder is the sum of X(1) and X(2). When the third clock pulse is applied, S = X(1)+ X(2) will be loaded in accumulator register and X(3) [ XN1(3)………. X2(3) X1(3) X0(3) ] number will be loaded into augend register. Then above process will continue until addition of all Nbit numbers are completed. So, after Kth clock pulse the content of accumulator register is the ﬁnal sum of K Nbit numbers.
6.7
BINARY MULTIPLIER
A binary multiplier is an electronic device which is used in digital electronics for multiplication of two binary numbers. Table 6.6 shows the rules of binary multiplication. Here, A is the multiplicand and B is the multiplier. When the multiplicand is 0 or 1 and the multiplier is 0, the product output is 0. If the
248 Table 6.6
Digital Electronics: Principles and Applications
multiplier digit is 1, the partial product is equal to the multiplicand. Therefore, the AND operation is Inputs Output equivalent to multiplication of two bits. Multiplicand Multiplier (A.B) The process of two bit multiplication is (A) (B) shown in Fig. 6.36. The multiplicand A (A1 A0) is 0 0 0 multiplied in turn by each digit of the multiplier B (B1B0). Intially, B0 is multiplied with A1 and A0 0 1 0 and generates partial product A1B0, A0 B0. Then 1 0 0 B is multiplied with A1 and A0 and generates 1 1 1 1 partial product A1 B1 , A0 B1 which are shifted by one bit left. Then sum of threse partial products produce the result of multiplication using AND gates and adders as depicted in Fig. 6.37. Each partial product is either 0 or 1 depending upon the multiplicand and multiplier. The AND gates produce the partial products. In a 2bit by 2bit multiplier, two half adders are used to sum the partial products, but generally full adders are used Fig. 6.36 Process of 2 bit multiplication in multiplication. Here P3 – P0 are the product output. Table 6.7 shows the product output of 2 two bit binary numbers. The product output has more digits than the multiplicand and multiplier. If two N bit binary numbers are multiplied, the product output will be as many as 2N bits. Truth Table of binary multiplication
Table 6.7
Truth table 2×2 multiplier
Inputs Multiplicand Multiplier
Fig. 6.37
2  bit by 2 bit multiplication
A1
A0
B1
B0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
P3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Output P2 P1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0
0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0
P0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 1
Arithmetic Logic Circuits
249
Figure 6.38 shows the process of 4bit by 4bit multiplication. Here, the 4bit binary number A (A3 A2 A1 A0) is multiplied by another 4bit number B (B3 B2 B1 B0). The ﬁrst row of multiplication is that the least signiﬁcant bit of multiplier is multiplied with each bit of multiplicand and four partial products A3 Fig. 6.38 4bit by 4bit multiplication B0, A2 B0, A1 B0, A0 B0 are produced. Then the second row of multiplication is obtained by multiplying each bit in the multiplicand by the B1 and generates four partial products A3 B1, A2 B1, A1 B1, A0 B1, which are shifted by one bit. Similarly, other two rows of partial products are produced. Then the columns of partial products are added to get the ﬁnal product. The basic implementation of 4bit by 4bit array multiplication is depicted in Fig. 6.39. It consists of full adders and AND gates.
Fig. 6.39 4 bit by 4 bit array multiplication
Logical AND operation each of the bits of the multiplicand (A3 A2 A1 A0) with the ﬁrst bit of the multiplier (B0) can generate A3 B0, A2 B0, A1B0, A0B0. The output of A0 AND B0 is the ﬁrst bit of the product output  P0. After that, AND each of the bits of the multiplicand (A3 A2 A1 A0) with the ﬁrst bit of the multiplier (B1) and generates A3B1, A2 B1, A1 B1, A0 B1. Then partial product A3B0, A2B0, A1B0 now will be added with A3B1, A2 B1, A1 B1, A0 B1 using full adders. In this addition process, the carry is generated and it is forwarded to the next column of partial products. Product P1 is obtained from ﬁrst full adder. The above process will continue till all multiplication and addition process are completed. The carry output from the last adder becomes the ﬁnal bit in the product. The ﬁnal product of this 4 bit multiplier is an 8 bit result P7 P6 P5 P4 P3 P2 P1 P0. In this way, combinational logic circuit (AND gates and full adders) is used to implement 4 bit multiplication. This operation can also be implemented by 4 bit adders and AND gates as shown in Fig. 6.40.
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Digital Electronics: Principles and Applications
Fig. 6.40
Fig. 6.41
6.8
4bit by 4bit multiplication
4bit by 4bit multiplication using IC 74284 and IC 74285
Actually, digital multiplications are very complex circuits. In general, when multiplying an mbit number by an nbit number, there are m × n partial products. If n = 32 and m = 64, the multiplication circuit requires huge number of gates and full adders. Actually, the required combinational logic gates and full adders increase with number of bits in the multiplier and multiplicand and a register is required to store the product. Nowadays LSI circuits are available as fast multiplier chips. The IC 74284 and IC 74285 are commonly used in 4bit by 4bit multiplication as given in Fig. 6.41.
BINARY DIVISION
Binary division is basically the reverse operation of the binary multiplication by shift and Add or repetitive addition. Division can be performed by repeated subtraction. Until dividend is less than the divisor, the subtraction is continuing. Figure 6.42 shows the schematic diagram of dividing a four bit number A= A 3 A2 A1 A 0 by a divisor B= B3 B2 B1 B0 using repeated subtraction method. This circuit consists of a 4bit adder, a register and a counter. Initially, all ﬂipﬂops of dividend register are reset. Then the dividend A is loaded into the register. The outputs of dividend register are connected as inputs of the adder. The one’s complement of – – – – divisor B, B 3 B 2 B 1 B 0 is also connected other input terminals of 4 bit adder. The carry output C3 must be connected to the carry input Cin. Consider Cin =1 and the counter is initially reset at zero.
Arithmetic Logic Circuits
251
After subtraction the difference, AB appears at S3 S2 S1 S0. When A>B and C3=1, the AND gate is enabled. If the clock pulse is applied, the difference AB will be loaded into the dividend register and the counter value incremented by one. The register contents again are used as input to the 4 bit adder. Then B is subtracted from AB, if AB>B. After subtraction the difference, ABB=A2B will appear at S3 S2 S1 S0. As the AND gate will be enabled and after application of the second clock pulse A2B will be loaded two 4bit binary numbers by reinto the register and the counter is also in Fig. 6.42 Division peated subtraction cremented by one. If after N clock pulses the remainder becomes less than B, C3=becomes 0 and the AND gate will now be disabled. Then the counter will stop counting. Therefore, the quotient is stored in the counter and the remainder will be available at S3 S2 S1 S0.
6.9
ARITHMETIC LOGIC UNITS (ALU)
Arithmetic logic units (ALU) perform arithmetic and logic operations (add, subtract, OR, AND….) on binary inputs data. Figure 6.43 shows the block diagram of an N bit ALU. This ALU has two N bit inputs A = AN1 AN2 ..…. A1 A0 and B = BN1 BN2 ..….B1 B0 , one N bit select inputs S = SN1 SN2 ..….S1 S0 and output function FN1 FN2 ..….F1 F0 . The select inputs actually select the output function. If there are three select variables in an ALU, there will be eight output functions as shown in Table 6.8. Arithmetic logic units are available in a variety of medium scale integrated (MSI) circuit package Fig. 6.43 Block diagram of an N bit ALU types and with different numbers of pins. Generally, the ALU is divided into two units: an arithmetic unit (AU) and a logic unit (LU). In some processors with multiple arithmetic units, one AU may be used for ﬁxedpoint operations while other arithmetic units AUs are used for ﬂoatingpoint operations. In general, arithmetic logic units have direct input and output access to the processor controller, main memory and input/output (I/O) devices. Each input consists of an operation code (one or more operands). The operation code determines actually which operation will be performed. After performing the operation ALU outputs are loaded into a storage register. Figure 6.44 shows the general structure of a simple arithmetic logic unit. Here, two multiFig. 6.44 General structure of a simple ALU bit data inputs A and B are applied to ALU.
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Digital Electronics: Principles and Applications
Function indicates the action like add, subtract, AND, etc. Data outputs have same bit width as multibit data inputs A and B and conditions indicates special conditions of arithmetic activity like overﬂow. Arithmetic logic units may vary in terms of number of bits, supply voltage, operating current, propagation delay, power dissipation, and operating temperature etc. The number of bits equals to the width of the two input words on which the ALU perform arithmetic and logical operations. Common conﬁgurations of ALU are 2bit, 4bit, 8bit, 16bit, 32bit and 64bit ALUs. Supply voltages varies from –5 V to +5 V. Power dissipation of ALU is in some milliwatts (mW). TransistorTransistor Logic (TTL), Fairchild Advanced Schottky TTL (FAST), Emitter Coupled Logic (ECL), Complementary MetalOxide Semiconductor (CMOS) logic families are used to develop ALU ICs. Arithmetic Logic Units are available in a variety of integrated circuit (IC) package types and with different numbers of pins. Basic IC package types for ALUs are Ball Grid Array (BGA), Quad Flat Package (QFP), Single InLine Package (SIP), and Dual InLine Package (DIP). IC74382 is an ALU IC and its logic symbol is depicted in Fig. 6.45. It is a 4bit device and performs eight functions as shown in Table 6.8. Three select lines S2 S1 S0 are used to select output functions. Multibit ALU can be created by connecting the carry output of lower order IC to carry in of higher order IC as shown in Fig. 6.46. Table 6.8 Function table
Select inputs Logic function Comments S2 S1 S0 0 0 0 CLEAR F3F2F1F0=0000 0
0
1
B Minus A
0
1
0
A Minus B
CN=1
0
1
1
A Plus B
CN=0
1
0
0
A≈B
Exclusive OR
1
0
1
A+B
OR
1
1
0
AB
AND
1
1
1
PRESET
F3F2F1F0=1111
Fig. 6.45
Logic symbol of ALU IC 74382
Fig. 6.46 8 bit ALU using two 4 bit ALUs
253
Arithmetic Logic Circuits
The IC 74LS181 and IC 74S181 are also arithmetic logic units (ALU). Figure 6.47 shows the pin diagram of IC 74181. The logic diagram of IC 74181 is depicted in Fig. 6.48. These circuits perform 16 binary arithmetic operations on two 4bit words as shown in Table 6.9. These operations are selected by the four functionselect lines (S0, S1, S2, S3) and include addition, subtraction, decrement, and straight transfer. When performing arithmetic manipulations, the internal carries must be enabled by applying a lowlevel voltage to the mode control input (M). A full carry lookahead scheme is made available in these devices for fast, simultaneous carry generation by means of two cascadeoutputs (pins 15 and 17) for the four bits in the package. When used in conjunction with the SN54S182 or SN74S182 full carry lookahead circuits, highspeed arithmetic operations can be performed. The method of cascading ‘S182 circuits with these ALUs
Fig. 6.47 Pin diagram of ALU IC 74181
Fig. 6.48 Logic diagram of ALU IC 74181
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Digital Electronics: Principles and Applications
to provide multilevel full carry lookahead is illustrated in Fig. 6.49. If high speed is not of importance, a ripplecarry input (Cn) and a ripplecarry output (Cn+4) are available. However, the ripplecarry delay has also been minimised so that arithmetic manipulations for small word lengths can be performed without external circuitry.
Fig. 6.49
Cascade connection of 74LS181 and 74S182
The ‘LS181 or ‘S181 can also be utilised as a comparator. The A = B output is internally decoded from the function outputs (F0, F1, F2, F3) so that when two words of equal magnitude are applied at the A and B inputs. Assumption is that a high level is used to indicate equality (A = B). The ALU must be in the subtract mode with Cn = H when performing this comparison. The A = B output is opencollector so that it can be wireAND connected to give a comparison for more than four bits. The carry output (Cn+4) can also be used to supply relative magnitude information. After this operation, the ALU may be placed in the subtract mode by placing the function select inputs S3, S2, S1, S0. These circuits have been designed to not only incorporate all of the designer’s requirements for arithmetic operations, but also to provide 16 possible functions of two Boolean variables without the use of external circuitry. These logic functions are selected by use of the four functionselect inputs (S0, S1, S2, S3) with the modecontrol input (M) at a high level to disable the internal carry. The 16 logic functions are detailed in Table 6.9, which is included exclusiveOR, NAND, AND, NOR, and OR functions. Series 54, 54LS, and 54S devices are characterised for operation in the temperature range of –55°C to 125°C; and Series 74LS and 74S devices are characterised for operation from 0°C to 70°C. Table 6.9
Select inputs S3 0 0 0 0 0 0 0
S2 0 0 0 0 1 1 1
S1 0 0 1 1 0 0 1
S0 0 1 0 1 0 1 0
Logic function M=1 – F
F = A— F = AB – F=A+B F = 1——– F = A– + B F=B ——– F = A≈ B
Functional table of ALU IC 74181
Arithmetic and logic functions (Active low data) M=0 Cn=L No carry M=0, Cn=H with carry F F F = A Minus 1 F = AB – Minus 1 F = AB Minus 1 F = Minus 1(2’s complement) – F = A Plus (A + B )– F = AB Plus (A + B ) F = A Minus B Minus 1
F=A F = AB – F= AB F = Zero – F = A Plus (A + B )–Plus 1 F = AB Plus (A + B )Plus 1 F = A Minus B
255
Arithmetic Logic Circuits Table 6.9 0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 1 1 1
(Contd...) 1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
– F = A– + B F = AB F=A≈B F=B F=A+B F=0 – F = AB F = AB F=A
– F=A+B F = A Plus (A+B) F = A Plus B – F = AB Plus (A+B) F = (A+B) F = A Plus At F = AB– Plus A F = AB Plus A F=A
– F = (A + B ) Plus 1 F = A Plus (A+B) Plus 1 F = A Plus B Plus 1 – F = AB Plus (A+B) Plus 1 F = (A+B) Plus 1 F = A Plus A Plus 1 F = AB– Plus A Plus 1 F = AB Plus A Plus 1 F = A Plus 1
6.10 DIGITAL COMPARATORS The comparator is a device which compares two binary numbers and also produces some results. There are two different types of comparators such as identity comparator and magnitude comparator. An identity comparator is a device that makes a bitbybit comparisons of two binary numbers and asserts an output when the two numbers are bitbybit equal. When a comparator compares two binary numbers and takes a decision whether one of the inputs is larger (L) than, or smaller (S) than or equal (E) to the other inputs and generates one of the three outputs L, S and E. This comparator is more complicated than identity comparator and is known as magnitude comparator.
6.10.1
1bit Digital Comparator
Consider two one bit numbers A and B and compare them to ﬁnd out the relative magnitude of L, S and E. After comparison, the result will be whether A>B, AB or A=1 and B=0, the output L =1 which implies that A>B. Similarly, output S=1 when AB, AB (L)
Output AB1, then A>B; if A1B; if A0B1. The second term E1A0B 0 = 1 if A1=B1 and A0>B0. If those two conditions are satisﬁed, then A>B. — — The equation for determining whether AB0. If the above four conditions are satisﬁed, then A>B. The equation for determining whether AB and AB outputs to the inputs of a NAND gate. Open–collector and totempole outputs are also available in the comparators group and some chips such as the IC 74886 have either one or two enable pins.
258
Digital Electronics: Principles and Applications
Fig. 6.52 4bits comparator
SUMMARY In this chapter, the arithmetic operations: addition, subtraction, 2’s complement adder/subtractor, sign magnitude binary subtraction carry look ahead adder, serial adder, parallel adder, BCD addition, multiplication and division using combinational logic circuits are explained. Some MSI ICs are also incorporated to perform addition and multiplication. The operation of arithmetic logic unit (ALU) is also explained with 74382 and 74181 MSI ICs. The operation of 1 bit, 2 bit and 4 bit comparators are discussed in this chapter.
MULTIPLE CHOICE QUESTIONS 1.
2.
In digital system, subtraction is performed using (a) Half adders (b) Half subtractors (c) Adders with ones complement representation of negative numbers (d) None of these In digital electronics addition is performed using (a) Half adders (b) Half subtractors (c) Adders with ones complement representation of negative numbers (d) None of these
Arithmetic Logic Circuits 3.
4.
5.
6. 7. 8.
9.
10.
11.
12.
13.
14. 15.
A half adder consists of (a) AND gate (c) NAND (b) EXOR gate and AND gate (d) None of these A full adder consists of (a) AND gate (c) NAND (b) EXOR gate and AND gate (d) None of these A full adder can be designed (a) Using 2 half adders (c) Using 4 half adders (b) Using 3 half adders (d) Using 5 half adders An N bit adder consists of (a) 2 full adders (b) N full adders (c) 4 full adder (d) N1 full adders IC 74181 is an N bit adder which consists of (a) Full adder adder (b) Half adder adder (c) Multiplier (d) None of these BCD arithmetic is preferred over binary arithmetic due to (a) BCD arithmetic circuits are simpler than binary arithmetic circuits (b) BCD arithmetic circuits are faster than binary arithmetic circuits (c) BCD arithmetic circuits are less expensive than binary arithmetic circuits (d) Easy operation and output display In BCD addition, 0110 is required to be added to the sum for getting the correct result, if (a) The sum of two BCD numbers is not a valid BCD number (b) The sum of two BCD numbers is not a valid BCD number or a carry is produced (c) A carry is produced (d) None of these BCD subtraction is performed by using (a) One’s complement representation (c) Nine’s complement representation (b) Two’s complement representation (d) None of these The ALU is used to perform (a) Only logical operation (c) Arithmetic and logical operation (b) Only arithmetic operations (d) Control operations A multiplier circuit consists of (a) AND gate and Full adders (c) NAND (b) OR gate and EXOR gates (d) None of these 2’s complement of a number is (a) 1’s complement of a number + 1 (c) 1’s complement of a number + 10 (b) 1’s complement of a number –1 (d) None of these The ﬁnal carry output equation of carry look ahead addition is (a) C3 = PCin + G (b) C3 = P + Cin +G (c) C3 = P = GCin (d) None of these 74283 is a (a) 4 bit adder (c) 4 bit subtractor (b) 4 bit carry look ahead adder (d) None of these
259
260 16.
Digital Electronics: Principles and Applications Serial adder is (a) Faster than parallel adder (b) Slower than parallel adder
(c) (d)
Costly with respect to parallel adder None of these
REVIEW QUESTIONS 6.1 6.2 6.3 6.4
6.5
6.6
6.7 6.8 6.9 6.10 6.11
6.12
6.13 6.14 6.15 6.16 6.17
Draw a half adder circuit using NAND gates and explain its operation. Draw a full adder circuit using NAND gates and explain its operation. Write some applications of full adders. What is the difference between half adder and full adder? Design a 4 bit divider circuit using repeated subtraction. Draw a 8 bit serial adder and explain it operation brieﬂy. When serial input data’s are 1111 1001 and 1000 1000, ﬁnd the output of serial adder after eight clock pulses. What are the advantages and disadvantages of serial adder? Design a 4 bit parallel adder circuit. Explain how 1010 and 1111 will be added in parallel adder. What are advantages of parallel adder? If the propagation delay time of 1 bit full adder is 100ns, determine the total delay time to get ﬁnal result. Draw a 4 bit by 4 bit array multiplication circuit and explain its operation. What will be total delay time to get ﬁnal product output? Consider AND gate delay time 100ns and full adder delay time 200ns. Design a circuit to convert 4 bit binary number into one’s complement form. Design a circuit to convert 4 bit binary number into two’s complement form. Determine the maximum propagation delay time between Cin and Cout of a 4 bit CLA adder. Assume the propagation delay in each full adder is Tf and in gates is Tg. Design the combinational logic circuits to perform the following operations: (a) A+B (b) AB (c) A¥B where A=A5A4A3A2A1A0 and B= B 5 B 4 B 3 B 2 B 1 B 0 Deﬁne ALU. Explain the operation of 74LS382 ALU IC with diagram. Show the following operation using 74LS382 ALU IC: (a) A PLUS B (b) A+ B (c) A MINUS B Design a 8 bit ALU using two 4 bit 74LS382 ALU IC. Show the following operation using 74181 IC: (a) A PLUS B (b) A ≈ B where A=1111 1111 and B =1000 0111. Show the following operation using 74LS181 IC: (a) A PLUS B (b) AB Plus A Design a combinational logic circuit to perform the arithmetic operation B =A+2, where A= A4A 3A 2A1A 0. Draw the connection diagram of 74283 and 7486 to perform a 8 bit parallel adder/subtractor. Draw the 4 bit multiplication circuit and explain brieﬂy. Write most commonly used multiplication ICs in digital electronics. An arithmetic circuit has two selection signals, S0 and S1. The circuit is required to perform the following operations (a) F = A + B (b) F = A + B + 1 (c) F = A (d) F = B
261
Arithmetic Logic Circuits
6.18 6.19 6.20 6.21
Design the ALU circuit using a 4 bit adder and logic gates. Design a binary multiplier which multiplies a 4 bit number B3 B2 B1 B0 by a number A= A2 A1 A0. Design a circuit that adds two binary bits a carry input (Cin). What is the difference between a parallel adder and a carry lookahead adder?. Explain the operation of carry lookahead adder with diagram. Compare the following two circuits as shown in Fig. 6.53 and Fig. 6.54.
Fig. 6.53
6.22 6.23 6.24 6.25
Digital summer
Fig. 6.54
Analog summer
What is the advantage of lookahead carry? When should it be used? If an ‘M’ bit number is multiplied by an ‘N’ bit number, what will be the length of the product register? Design an 8 bit adder using two 4 bit adders. Design a 4 bit subtraction using 4 bit adders and minimum number of ExOR gates.
CHAPTER
7 FLIPFLOPS 7.1
INTRODUCTION
The combinational logic circuits are a part of digital systems and they have many applications such as decoder, encoder, adder, subtracter, multiplexer, demultiplexer, etc. But when the circuit output not only depends on the present state but also the previous state, the circuit is known as sequential logic circuit. The basic block diagram of a sequential circuit is shown in Fig.7.1. This circuit consists of a combinational logic circuit and a memory element. The output of combinational logic circuit is stored in memory elements. Memory elements output entered into combinational logic circuit and used as input variables. The output of combinational logic circuit depends upon the external inputs and input from memory elements. A memory element is a device which can store information in terms of 1 or 0 and its state can be modiﬁed by clock signal and data inputs A ﬂipﬂop is one bit memory element which can store 1 or 0. Flipﬂop is an electronic circuit or device which is used to store a data in binary form. Actually, ﬂipﬂop is an onebit memory device and it can store either 1 or 0. This device has twostate characteristics. Therefore, this device is known as two state machines as shown in Fig.7.2. There are four conditions of transition of ﬂipﬂops due to change in input and clock signals. Condition1, condition2, condition3 and condition4 are the four different logic conditions related with input and clock signals. If the initial state of ﬂipﬂop is 0 in condition1, when input x = 0 and clock is applied, ﬂipﬂop output state will not be changed and its output should retain at logic level 0. In condition2, while ﬂipﬂop is in 0 state and input x=1 and clock is applied, there will be transition in ﬂipﬂop’s output as its state is changed from logic level 0 to logic level 1. Similarly, in condition3, when ﬂipﬂop is in 1 state, input x = 1 and clock is applied, output will not be changed and output should maintain logic level 1. But, in condition4, ﬂipﬂop is in 1 state, input=0 and clock signal is applied, and then output will be changed from logic level 1 to logic level 0. Flipﬂop can be constructed using inverter, NOR and NAND gates which are discussed in this chapter.
Fig. 7.1
Block diagram of sequential logic circuit
Fig. 7.2
Two state machine
FlipFlops
7.2
263
INVERTER WITH FEEDBACK
Figure 7.3 shows the inverter with feedback. The basic operation of this circuit is explained here. When the input is logic level 0, the output switches to logic level 1 after a small propagation delay. Logic level 1 output gets fed back to the input as logic level 1. When the input is logic level 1, the output switches to logic level 0 after a small propagation delay. Logic level 0 outputs gets fed back to the input as logic level 0 and the cycle repeats itself. The result is a high frequency oscillator, if implemented with an inverter gate. The propagation delay of Fig. 7.3 Inverter with feedback inverter varies in between 4ns to 60ns. When the propagation delay of a TTL NOT gate is about 25ns, the time period will be 50ns and oscillator frequency will be about 20MHz.
7.3
TWO INVERTERS FORM A MEMORY CELL
Two inverters are connected in cascade with feedback as shown in Fig. 7.4. This circuit behaves as a static memory cell. This circuit hold value as long as power is applied. We can also change the value of the memory cell as shown in Fig. 7.5. Fig. 7.4 Two inverter form a memory cell Initially, break the feedback path named remember switch and data is loaded by load switch. Then the output is data. When load switch is open and remember switch is closed, data will be stored. Similar to inverter pair circuit, crosscoupled NAND and NOR gates have capability to generate output 0 (reset) or 1 (set). On the other hand, we can say inverter form a memory cell with that two NAND or NOR gates connected in such Fig. 7.5 Two remember and load switch a way that output of one NAND gate is used input of another NAND gate or output of one NOR gate is used input of another NOR gate.
7.4
MEMORY CELL USING NAND AND NOR GATES
The memory cell can be implemented using NOR or NAND gates. Figure 7.6 shows the basic memory cell using two NAND gates. The relationship between input and output is – – – Q = A2 = A 1; Q = A1 = A 2 – The outputs Q and Q are complements of each other. This circuit has two stable states: Set and Reset. In set state, Q is – – 1 and Q is 0. In reset state Q is 0 and Q is 1. If the circuit is in 1 state, this memory cell remains in this state. Similarly, if it is in 0 state, the circuit continuously to remain in this state. Fig. 7.6 One bit memory cell using This property of the circuit is called as memory cell and it NAND gates
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Digital Electronics: Principles and Applications
Table 7.1 Truth table of one bit memory cell using NAND gates
Inputs A1 A2
Outputs – Q Q
0
1
1
0
1
0
0
1
can store one bit information either 1 or 0. The operation of one bit memory cell using NAND gates is represented by Table 7.1. Figure 7.7 shows the circuit diagram of 1 bit memory cell using NOR gates and its truth table is depicted in Table 7.2. The correlation between input and output is – – – Q = A2 = A 1 , and Q = A1 = A 2 Table 7.2
Truth table of one bit memory cell using NOR gates
Inputs
Fig. 7.7
7.5
One bit memory cell using NOR gates
Outputs
A1
A2
Q
– Q
0
1
1
0
1
0
0
1
LATCH
Latch is a bistable device capable of staying in either of two states: Set and Reset for an indeﬁnite time period. Latches are basically similar to ﬂipﬂops as they have two states. But the difference between latches and ﬂipﬂops is in the method of changing their states. When the Enable input of Latch is high, the output of Latch changes depending upon inputs. If the Enable input of Latch is low, the output of Latch should hold its previous state. The ﬂipﬂop is triggered by either positive edge or negative edge of clock signal for changing their output states. When the clock signal changes from low to high state and the output changes due to the inputs, it is called positive edge triggering ﬂipﬂop. If the clock signals change from high to low state and the output changes due to the inputs, this condition is known as negative edge triggering ﬂipﬂop. The difference between latch and ﬂipﬂop is illustrated in Table 7.3. Different types of latches are SR latch and D latch. The operation of SR latch and D latch is explained in Section 7.6 to 7.10. Table 7.3 Difference between Latch and ﬂipﬂop
Latch
Flipﬂop
A latch is an electronic sequential logic circuit used to store A ﬂipﬂop is an electronic sequential logic circuit used to information in an asynchronous arrangement. store information in an synchronous arrangement. It has two stable states and maintains its states for an indeﬁnite period until a trigger pulse is applied. One latch can store one bit information, but output state One ﬂipﬂop can store one bit data, but output state changes changes only in response to data input. with trigger pulse only. Latch is an asynchronous device and it has no clock Flipﬂop has clock input and its output is synchronised input. with clock pulse. Latch holds a bit value and it remains constant until new Flipﬂop holds a bit value and it remains constant until a inputs force it to change. trigger pulse is received. Latches are levelsensitive and the output tracks the input Flipﬂops are edgesensitive. They can store the input only when the level is high. Therefore as long as the level is logic when there is either a rising or falling edge of the clock. level 1, the output can change if the input changes.
265
FlipFlops
7.6
SR LATCH USING NOR GATES
Figure 7.8 shows the two crosscoupled NOR gates. The NOR gates are connected in such a way that the output of one feeds back to the input of another. S and R are two inputs of SR latch. S is stands for set, it means that when S is 1, it stores 1. Similarly, R stands for reset and if R=1, ﬂipﬂop reset and it’s output will be 0. This circuit is called as NOR gate Latch or SR Latch. The functional table of SR latch using NOR gate is depicted in Table 7.4. The analysis of Table 7.4 is discussed with the help of Fig. 7.9 (a), (b), (c) and (d). Table 7.4
Fig. 7.8
Crosscoupled NOR gates
Truth table of SR latch using crosscoupled NOR gates
Inputs
Outputs
S
R
Q
– Q
0 0 1 1
0 1 0 1
Latch 0 1 0
Latch 1 0 0
Comments Hold Reset Set Not used(Invalid)
S=0, R=0: The normal resting state of SR Latch is S=0, and R=0. In this condition there is no effect on – output. Consequently, the state of Q and Q will not be changed. This is hold operation of SR latch.
Fig. 7.9
(a) NOR Latch with R = 0 and S = 0 (b) NOR Latch with R = 1 and S = 0 (c) NOR Latch with R = 0 and S = 1 (d) NOR Latch with R = 1 and S = 1(Invalid)
– S=1, R=0: When S=1, and R=0, the output Q will be 1 and Q is equal to 0. This is called set operation of SR Latch.
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Digital Electronics: Principles and Applications
– S=0, R=1: If S=0, and R=1, Latch reset the output. Accordingly output Q=0 and Q =1. This is known as reset operation of SR Latch. – S=1, R=1: If S=1 and R=1, latch is set and reset at the same time. The output will be Q=0 and Q =0. – But practically both outputs zero have no use. Therefore, this condition is invalid as the Q and Q outputs must be complement of each other. Therefore, this is called an invalid or illegal state for the SR latch. Table 7.5 Truth table of NOR gate SR latch Table 7.5 shows the truth table of SR latch where Qn is the present state and Qn1 is the next state. Figure 7.10 Inputs Present state Next state shows the state transition diagram of SR latch. 0Æ0 S R Qn Qn+1 transition occurs when S = 0 and R=0 or S=0 and R=1. 0 0 0 0 Since R can be either 0 or 1, it may be indicated as don’t 0 0 1 1 care state represented by X symbol. Then 0Æ0 transition 0 1 0 0 0 1 1 0 is possible only when S=0 and R=X. The 0Æ1 transition 1 0 0 1 is generated if S=1 and R=0. Similarly, 1Æ0 transition 1 0 1 1 occurs when S=0 and R=1. The 1Æ1 transition is gener1 1 0 x ated if S=X and R=0. 1 1 1 x The timing diagram of a NOR latch for different SR inputs is depicted in Fig. 7.11. Initially, R=1 and S=0, the output of SR latch – Q is 0 and Q =0. After that R=0 and S=0, the output of SR latch does not changed and it should retain its previous output. Therefore S– R latch output Q is 0 and Q = 0. Then R=0 and Fig. 7.10 State transition diagram of SR Latch – S=1, the output of SR latch Q is 1 and Q =0 as – the latch is set. Afterwards R=1 and S=1, the output of SR latch Q is 0 and Q =0 as this state is invalid – due to R=S=1. Then R=1 and S=0, the output of SR latch Q is 0 and Q =1 as the latch is reset. Similarly, other logic operations can be justiﬁed using Table 7.5.
Fig. 7.12 K map of SR latch Fig. 7.11 Timing diagram of SR latch
The Kmap of SR latch with three inputs namely S, R, Qn and one output Qn+1 is given in Fig. 7.12. The relationship between inputs and output can be expressed by characteristic equation – Qn+1 = S + R Qn.
7.7
SR LATCH USING NAND GATE
The SR Latch can be constructed from two NAND gates as shown in Fig. 7.13. Two NAND gates are crosscoupled. Output of one NAND
Fig. 7.13
NAND latch
267
FlipFlops
– gate is connected with the one input of the other NAND gate. Therefore, the output of gates Q and Q are the latched outputs. In general, outputs are complement of each other. In latch, there are two inputs namely Set (S) and Reset (R). Initially, S and R both inputs are 1 state. Then any one input will be changed to 0 (logic 0) for changing output. Truth table for operation of SR latch using NAND gates is given in Table 7.6. The four possible states of SR latch are shown in Fig. 7.14 (a), (b), (c) (d) and (e) and operation detail is given below: Table 7.6 Truth table of crosscoupled NAND gates
Fig. 7.14
S
R
Q
– Q
Comments
0
0
1
1
Not used
0
1
0
1
Reset
1
0
1
0
Set
1
1
Latch
Latch
Hold
(a) NAND latch with R=0 and S=0 (Invalid) (b) NAND latch with R=1 and S=0 (c) NAND latch with R=0 and S=1 (d) NAND latch with R=1 and S=1 (e) NAND latch with R=1 and S=1
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Digital Electronics: Principles and Applications
– S=0, R=0: When S=0, R=0, the output of latch will be Q=1 and Q =1. But practically both outputs high will not be allowed; therefore this state is called invalid state of latch. – S=1, R=0: When S=1, and R=0, the output Q will be 1 and Q =0. This is known as set operation of SR latch. S=0, R=1: If S=0, and R=1, ﬂip ﬂop reset the output. Therefore, – the output Q will be 0 and Q =1. This is called reset operation of SR latch. Fig. 7.15
Symbol of SR latch
S=1, R=1: This is the normal resting state of SR Latch when S=1, R=1 and in this condition there is no effect on output. Consequently, – the state of Q and Q will not be changed. This is the holding state of latch. Figure 7.15 shows the logic symbol of SR latch.
7.8
SR LATCH WITH ENABLE
In SR latch using NOR or NAND gates, the output will be changed depending upon S and R inputs. But sometimes output of SR latch changes when only some conditions are satisﬁed. This means that output is dependent on conditional input called enable (E). When E=0, the devices are disable and output has no change. But when E=1, the device is enable and output depends on S and R inputs. Figure 7.16 shows the SR latch with enable. While the enable E is 0, the outputs of AND gates will be 0. Accordingly, S and R both will be 0, NOR gates outputs cannot be changed and latching the – Q and Q outputs. If the enable input (E) is 1, the SR latch reacts with S and R inputs. The truth table of enabled SR latch is shown in Table 7.7. Figure 7.17 shows waveform SR latch with enable. It is depicted in Fig. 7.17 that anytime S is 1 and R is 0, a logic level 1 on the E input sets the latch. Anytime S is 0 and R is 1, a logic level 1 on the E input resets the latch. The symbol of SR latch with enable is depicted in Fig. 7.16 SR latch with enable Fig. 7.18. Table 7.7
Inputs
Truth table of SR latch with enable
Enable E
S
R
Outputs – Q Q
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Q Q Q Q Q 0 1 0
– Q – Q – Q – Q – Q 1 0 0
Comments
Remarks
Hold Hold Hold Hold Hold Reset Set Invalid/not used
SR inputs are disabled
SR inputs are enabled
269
FlipFlops
Fig. 7.17
7.9
Waveform of SR Latch with enable
Fig. 7.18
Symbol of SR Latch with enable
THE D LATCH
In a cross coupled NAND gates as shown in Fig. 7.19, input D is connected with S and its complement – D is connected with R. If input D is 0, S=0 and R=1 and latch reset means Q=0, Q =1. When input D=1, – then S=1 and R=0 latch output Q=1 and Q =0. Table 7.8 shows the truth table of D latch. In a D latch,
Fig. 7.19 D Latch
7.10
Table 7.8
Truth table of D latch
Input D
Output – Q Q
0
0
1
1
1
0
the output follows the input. When D=0, output Q=0 and if D=1, output Q=1.
D LATCH WITH ENABLE
The D latch with enable has two inputs: one enable input (E) and other D input and one output Q as shown in Fig. 7.20. When the enable (E) is high, the D latch changes its states to whatever in D input. If the enable (E) is low, the latch does not change its state. Therefore, D latches can be used as 1bit memory device to store logic level 1, high or logic level 0, low when enable E is disabled. Hence, read new data from the D input when enable E is enabled. Figure 7.21 shows the state transition diagram of the D latch. The enable input is not shown Fig. 7.20 D latch with enable in diagram as transitions occur only when the enable is high. Table 7.9(b) shows the truth table of D latch representing present sate and next state
270
Digital Electronics: Principles and Applications
Fig. 7.21
Table 7.9
State diagram of D latch
(a) Truth table of D latch
E
D
Q
– Q
0 0 1 1
0 1 0 1
Latch Latch 0 1
Latch Latch 1 0
Fig. 7. 22 Kmap of D latch
Table 7.9
(b) Truth table of D latch with E, D, Qn and Qn+1
ENABLE
D
E 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
Present State
Next State
Qn
Qn+1
0 1 0 1 0 1 0 1
0 1 0 1 0 0 1 1
and the Karnaugh map for the next step of D latch from enable, D and present state Qn is depicted in Fig.7.22. The expression for the next state output Qn+1 from the Karnaugh map is – Qn+1 = ED + E .Qn As there are two 1’s in adjacent cells on the Kmap, a static hazard is present in Kmap. To eliminate the static hazard, another term DQn will be added. Then static hazard free characteristic equation is – Qn+1 = ED + E .Qn + DQn It is clear from this expression that the state of D latch does not change until the enable is high. If the enable is asserted, the logic expression can be simpliﬁed as Qn+1 = D. Logic symbol of D ﬂipﬂop is shown in Fig. 7.23. Figure 7.24 shows the timing diagram of D latch. The outputs respond to input D when the enable (E) input is high. When the enable signal becomes low, the circuit remains latched. Any time D is high and enable E is high, the output Q is high. Any time D is low and enable E input is high, Q becomes low. When the enable E input is low, the state of latch does not affected by the D input. The advantages of enabled D latch is that it has only one data input and when only output is required make the enable signal logic 1. The transition of D latch does not occur until E Fig. 7.23 Logic symbol of D latch with enable makes a 0Æ1.
FlipFlops
271
The operation of D latch can be understood from a time delay block diagram as depicted in Fig. 7.25. The data input will be available at the output only after propagation time delay, td. Therefore, this circuit also works as delay circuit.
7.11 FLIPFLOPS A ﬂipﬂop is a device which changes its state at the times Fig. 7.24 Timing diagram of D Latch with enable when a change is taking place in the clock signal. The ﬂipﬂop is triggered by either positive (leading) edge or negative (trailing) edge of clock signal. In edge triggering, the output of ﬂipﬂop can be changed only when the Fig. 7.25 clock pulse is applied. If the clock signal changes from low to high state and the output changes due to the inputs, it is called positive edge triggering. When the clock signal changes from high to low state and the output changes due to the inputs, this condition is called negative edge triggering. Most commonly used ﬂipﬂops are SR, D, JK and T ﬂipﬂops. In this chapter, the operation of SR, D, JK and T ﬂipﬂops are discussed.
7.12 EDGETRIGGERED SR FLIP FLOP An edgetriggered ﬂipﬂop changes outputs either at the positive edge or negative edge of the clock pulse. Figures 7.26 (a) and (b) show the clocked RS ﬂipﬂop using NAND and NOR gates respectively and this ﬂipﬂop is triggered on the positive edge of clock. The output of ﬂip ﬂop can be changed when clock is applied and transition takes place 0 to 1. Therefore, S and R are the inputs of ﬂipﬂop and clock pulse is applied for changing the state of ﬂipﬂop. Truth table of clocked SR ﬂipﬂop is illustrated in Table 7.10. This is explained the operation of SR ﬂipﬂop with inputs and clock. The operation of S
Fig. 7.26
(a) Clocked SR ﬂipﬂop using NAND gates (b) Clocked SR ﬂipﬂop using NOR gates
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Digital Electronics: Principles and Applications
R ﬂip ﬂop can be analysis by waveform. Generally 50% duty cycle clock pulse is used for clocked SR ﬂipﬂop, so that inputs S and R gets enough time to settle the effect on to change output. Figure 7.27 shows the controlling of SR ﬂipﬂop with a clock and it has two states: stable state and changing state. In stable state, clock is low and inputs S and R cannot change the output of ﬂipﬂop. S and R inputs only change output in half of clock period when Fig. 7.27 The controlling of SR ﬂipﬂop clock signal transition is 0Æ1 called changing state. At with a clock the positive edge of clock pulse (CLK)  1, S=1 and R=0, Q changes from logic level 0 to logic level 1. Similarly, at the positive edge of clock pulse (CLK) – 2, S=0 and R=1, Q changes from logic level 1 to logic level 0. Symbols of positive edgetriggered without bubble at clock input and negative edgetriggered with bubble at clock input are shown in Fig. 7.28 (a) and (b) respectively.
Fig. 7.28
(a) Positive edge triggered SR ﬂipﬂop (b) Negative edge triggered SR ﬂipﬂop
The truth table of positive edge triggered SR ﬂipﬂop is given in Table 7.10. When S = 1 and R = 0, ﬂipﬂop sets on the rising clock edge. If S = 0 and R = 1, ﬂipﬂop resets on the rising clock edge. The S and R inputs can be changed at any time when the clock input is low or high. It is depicted in Fig. 7.27 that output changes at the transition of clock from low to high. The operation and truth table of negative edgetriggered ﬂipﬂop are the same as positive edge triggered ﬂipﬂop but only difference is trigger edge that will be negative or falling edge of the clock pulse. Therefore, ﬂipﬂop will be set or reset at the negative or falling edge of the clock pulse. Table 7.10
Clock
Truth table of positive edge triggered SR ﬂipﬂop
Inputs S
R
Outputs – Q Q
0 0 1 1
0 1 0 1
Q 0 1 ?
(CLK) Ø Ø Ø Ø
7.13
– Q 1 0 ?
Comments
No change Reset Set Invalid
CASCADING SR FLIPFLOPS
Flipﬂops are the building block of sequential circuits. In sequential circuits, data can ﬂow from one ﬂipﬂop to other on each successive clock pulse. Therefore, ﬂipﬂops are connected in cascade means
FlipFlops
273
connect output of one ﬂipﬂop to input of another. Figure 7.29 shows cascaded SR ﬂipﬂops in master slave form. When the clock changes low to high, the output of master ﬂipﬂop changes and input to the slave ﬂipﬂop. The output of Fig. 7.29 Masterslave SR ﬂipﬂop slave ﬂipﬂop is not affecting as inverted clock pulse is applied to slave ﬂipﬂop. Maser ﬂipﬂop’s output can be transferred to slave ﬂipﬂop when clock changes high to low. So, at the end of each clock pulse, the output of salve ﬂipﬂop changes and shifting of data in cascaded maserslave ﬂipﬂop. Waveform of masterslave SR ﬂipﬂop is depicted in Fig. 7.30. At the instant of ﬁrst positive edge clock pulse S=1 and R=0, the output of master ﬂipﬂop – is P = 1 and P = 0. As inverted clock pulse is applied to the slave ﬂipﬂop, when the clock Fig. 7.30 Waveform of masterslave SR ﬂipﬂop pulse changes from 1 to 0, the ﬁrst positive edge – clock pulse is applied to the slave ﬂipﬂop. Therefore, the output of slave ﬂipﬂop will be Q=1 and Q = 0. Similarly, other operations of master slave SR ﬂipﬂop can be justiﬁed using truth table.
7.14
SR FLIPFLOP WITH ASYNCHRONOUS INPUTS
– In normal SR ﬂipﬂop, output Q and Q will be depends upon synchronous inputs S, R and clock – signal. Outputs Q and Q are also synchronised with clock signal. In asynchronous SR ﬂipﬂop with asynchronous inputs, the ﬂipﬂop can be set or reset regardless of S, R and clock signal. These inputs are called preset (PRE) and clear (CLR). Figure 7.31 shows the logic symbol of asynchronous SR ﬂipﬂop. Implementation of asynchronous SR ﬂipﬂop using NAND gates is given in Fig.7.32. While the preset input (PRE) is high and clear input – Fig. 7.31 (a) Logic symbol of Asynchronous (CLR) is low, the ﬂipﬂop will be Q=0, Q = 1 despite SR ﬂipﬂop with preset and clear (b) Logic the consequences of synchronous inputs and the clock symbol of Asynchronous SR ﬂipﬂop with inverted preset and clear signal. So, the ﬂipﬂop is in reset state or cleared. If the clear input (CLR) is high and the preset input – (PRE) is low, the ﬂipﬂop will be set as Q = 1, Q = 0. But, if both preset (PRE) and clear inputs (CLR) – are low, both Q and Q will be 1. This condition is an invalid state of the ﬂipﬂop and PRE=CLR=0 is not allowed. Truth table of asynchronous SR ﬂipﬂop is shown in Table 7.11. Preset (PRE) and clear (CLR) inputs will be used when multiple ﬂipﬂops are connected in a group to achieve a function on a
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Digital Electronics: Principles and Applications
multibit binary word and a single line is required to set or reset all ﬂipﬂops at a time. Asynchronous inputs may be activehigh or activelow. If inputs are activelow, there will be an inverting bubble at that input on the block symbol same as the negative edgetriggered clock inputs. Table 7.11 Truth table of asynchronous SR ﬂipﬂop
Fig. 7.32 Logic diagram of SR ﬂipﬂop with preset and clear
Example 7.1
Clock (CLK)
Clear (CLR)
1 0 0 0
0 0 1 0
Preset Output (PRE) 0 1 0 0
Comments
Qn+1 Normal ﬂipﬂop 0 Clear 1 Preset Not allowed
Determine the output waveform when of SR latch when the inputs as shown in Fig. 7.33 are applied. Consider initial output of SR Latch is low and enable is always high.
Fig. 7.33
� Solution The output waveform of SR Latch is illustrated in Fig. 7.34. Initial output of SR latch Q is 0. When S=1, R=1, this is the invalid state of SR Latch and output Q is 0. After that S=0 and R=1, the latch is reset. So the output Q has not changed and it retain at 0. Then S=1 R=0, latch is set. So the output Q changes from 0 to 1. Similarly, other outputs of SR latch can be justiﬁed. Example 7.2
Fig. 7.34
Write the output of a clocked SR ﬂipﬂop when the inputs are R=011001 and S = 101100. Assume initially Q is low.
Solution Table 7.12
CLK
Inputs S
R
Ø Ø Ø Ø Ø Ø
�
1 0 1 1 0 0
0 1 1 0 0 1
Outputs Qn Qn+1 0 1 0 0 1 1
1 0 0 1 1 0
The output of SR ﬂipﬂop Qn+1 is shown in Table 7.12. Initial output Qn is 0. If S=1, R=0, Qn=0 and ﬁrst clock pulse is applied, the next state output Qn+1 will be 1. When S=0, R=1, Qn=1 and second clock pulse is applied, the next state output will be 0. In the same way, remaining next state outputs with respect to clock pulse can be justiﬁed using truth table of SR ﬂipﬂop.
275
FlipFlops Example 7.3
Draw the output waveform of a positive edge triggered SR ﬂipﬂop when the inputs are given in Fig. 7.35. Assume initially ﬂipﬂop output is low.
� Solution The output waveform is shown in Fig. 7.36. If S=1, R=0 and positive edge triggers applied, the ﬂipﬂop will be set. If S=0, R=1 ﬂip ﬂop will be reset when positive edge triggered applied. At the instant of ﬁrst clock pulse, S=0 and R=1, ﬂipﬂop will be reset and output Q is 0. During the second clock pulse, S=0 and R=0 and ﬂipﬂop should retain its previous state and there will be no change in output. So the output Q = 0. Subsequently, S=1 and R=1, ﬂipﬂop operates in invalid state and output Q=0. At the instant of fourth clock pulse, S=0 and R=0, the output of the ﬂipﬂop Q is =0. During the ﬁfth clock pulse, S=1 and R=0, ﬂipﬂop is set and output Q =1.
Fig. 7.35
Fig. 7.36
7.15 EDGETRIGGERED D FLIPFLOPS
The operation of D latch is already discussed in Section 7.9 and 7.10. It responds to the data inputs D only when the enable input is high. But, the edge triggered D ﬂipﬂops responds on either the rising or falling edge of a clock pulse when a clock signal is applied. In edge triggered D ﬂipﬂop, data can be transmitted from inputs to outputs on the rising (positive) or falling (negative) edge of clock pulse. The clocked D ﬂipﬂop has two inputs: a clock input and D input. At the instant when clock changes from low to high or from high to low, the ﬂipﬂop changes its states to whatever in D input. If the clock is disabled, the ﬂipﬂop does not change its state. Consequently, D ﬂipﬂops can be used as 1bit memory device to store either 1, high Fig. 7.37 Positive edge triggered D ﬂipﬂop or 0, low state when clock is disabled, and Table 7.13 Truth table of D ﬂipﬂop read new data from the D input when clock is enabled. Figure 7.37 shows the positive Clock D Present State Next State edge triggered D ﬂipﬂop. Table 7.13 shows (CLK) Qn Qn+1 the truth table of D ﬂip ﬂop representing 0 0 0 0 0 0 1 1 present sate and next state and the Kar0 0 Ø Ø Ø Ø Fig. 7.38
K map of D ﬂipﬂop
1 1 0 0 1 1
0 1 0 1 0 1
0 1 0 0 1 1
naugh map for the next state output of D ﬂipﬂop Qn + 1 from clock CLK, data input D and present state Qn is depicted in Fig.7.38. The expression for Qn + 1 from the Karnaugh map is ——— Qn + 1 = CLK.D + C L K . Qn
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Digital Electronics: Principles and Applications
It is clear from this expression that the state of D ﬂipﬂop does not change until the clock is enabled. The timing diagram for a positive edgetriggered D ﬂipﬂop is depicted in Fig. 7.39. The outputs respond to input D at the positive edge of clock input only. In this timing diagram, output only responds to the D input due to transitions of the clock signal from low to high. In negative edge triggering, output only responds to the D input when the clock signal changes from Fig. 7.39 Response of positive edge triggered D ﬂipﬂop high to low. The negative edge triggered ﬂipﬂop produces the following response as given in Fig. 7.40. At the instant of ﬁrst negative edge of clock pulse, D=0, the output of D ﬂipﬂop Q=0. During the second negative edge of clock pulse, D=1, the output of D ﬂipﬂop Q changes from 0 to 1. Logic symbol of positive edge triggered and of negative edge triggered D ﬂipﬂops are shown in Fig. 7.41(a) and Fig. 7.41(b) respectively.
Fig. 7.40
7.16
Response of negative edge triggered D ﬂipﬂop
Fig. 7.41
(a) Logic symbol of positive edge triggered D ﬂipﬂop (b) Logic symbol of negative edge triggered D ﬂipﬂop
D FLIPFLOP WITH ASYNCHRONOUS INPUTS
Fig. 7.42 (a) Logic symbol of asynchronous D ﬂipﬂop with preset and clear (b) Logic symbol asynchronous D ﬂipﬂop with inverted preset and clear
– In D ﬂipﬂop, outputs, Q and Q will depend on synchro– nous input D and outputs Q and Q are synchronised with clock signal. In asynchronous D ﬂipﬂop, asynchronous inputs can set or reset the ﬂipﬂop regardless of D and clock signal. These inputs are called preset (PRE) and clear (CLR). Figure 7.42 shows the asynchronous D ﬂipﬂop. When the preset input (PRE) is high and the clear input (CLR) is low, the D ﬂipﬂop will be cleared or – reset (Q=0, Q=1) despite the consequences of synchronous inputs or the clock signal. If the preset input (PRE) is low and the clear input (CLR) is high, the D ﬂipﬂop – will be set (Q=1, Q= 0). Preset (PRE) and clear (CLR) inputs will be used when multiple D ﬂipﬂops are connected in a group. Asynchronous inputs may be activehigh or activelow. If inputs are activelow, there will be an inverting bubble at that input on the block symbol same as the negative edgetriggered clock inputs.
277
FlipFlops Example 7.4
Determine the output waveform of level triggered D ﬂipﬂop if the inputs waveform is shown Fig. 7.43(a) as given below:
Fig. 7.43(a)
Fig. 7.43(b)
� Solution A level triggered D ﬂipﬂop is nothing but a D ﬂipﬂop with enable input E. When enable input E =0, the D ﬂipﬂop should hold its previous output. If enable input E = 1, the output of D ﬂipﬂop will be the data input D. Assume initial output of D ﬂipﬂop is 0. The output waveform of level triggered D ﬂipﬂop is shown in Fig. 7.43(b). Example 7.5
What is race around condition of data transfer using negative edge triggered D ﬂipﬂops? How can it be removed?
� Solution Figure 7.44 shows the race around condition of data transfer using negative edge triggered D ﬂipﬂops. At the instant of negative edge of the ﬁrst clock pulse, Q0 becomes high or logic 1 after a propagation delay tPLH. At the negative edge of the second clock pulse, Q0 becomes logic level 0 after a time delay tPLH. The ﬂipﬂop FF1 is also clocked and its input is 1. Then output of FF1 is Q1=1 which creates a race condition. Actually, a marginal condition becomes arise as Q0 does not remain in high or logic 1 after the second negative triggering edge of the clock. Therefore, logic level 1 may not be transferred. To transfer data, Q0 must be remaining high for time equal to the hold time thold. The data can only be transferred if tPHL> thold. If thold > tPHL, a unreliable data transfer is created. This condition is known as race around condition of data transfer using D ﬂipﬂops. To remove this condition, the master slave ﬂipﬂops will be used.
Fig. 7.44
7.17
Data transfer using negative edge triggered D ﬂipﬂops
THE JK FLIPFLOP
In SR ﬂipﬂop, when S=1, R=1, output of ﬂipﬂop is invalid. To eliminate the invalid condition, an feedback is added with SR ﬂipﬂop. This feedback selectively enables set and reset inputs. This modiﬁed SR ﬂipﬂop is called JK ﬂipﬂop as shown in Fig. 7.45. The operation of JK ﬂipﬂop is – shown in Table 7.14. When both J and K inputs are logic 0, the outputs Q and Q will not change and ﬂipﬂop stores the information like a latch. If J=0 and K=1, the ﬂipﬂop reset and the output Q = 0 and
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Digital Electronics: Principles and Applications
– – Q =1. When J=1, K=0, the ﬂipﬂop set and the output Q=1 and Q = 0. While both J and K inputs activated (J=1, K=1), the outputs Q and – Q will swap states. If the ﬂipﬂop is in set state, it will be changed to reset state. On the other hand, reset ﬂipﬂop will be changed to set state. Therefore, the JK ﬂipﬂop will toggle from a set state to a reset state, or visaversa. It is depicted in Table 7.14 that the SR ﬂipﬂop’s invalid state is eliminated and the additional feature, ability to toggle between the two stable output states is incorporated.
Fig. 7.45 JK ﬂipﬂop
Table 7.14 Truth table of JK ﬂipﬂop
Inputs
7.17.1
Outputs
J
K
Q
– Q
0 0 1 1
0 1 0 1
Latch 0 1 Toggle
Latch 1 0 Toggle
Clocked JK FlipFlop
Figure 7.46 shows the clocked JK ﬂipﬂop. The clocked JK ﬂipﬂop has three inputs: a clock input and other two inputs called as J and K. Figure 7.47 shows the state transition diagram of JK ﬂipﬂop. When the clock is asserted, the state of ﬂipﬂop can be changed depending on the condition of J and K. When
Fig. 7.46
Clocked JK ﬂipﬂop Fig. 7.47
the clock is not asserted, the output of JK ﬂipﬂop is same as the previous sate output. When J=0, K=1 and clock is asserted, the next state output is the complement of K. If J=1, K=0 and clock is asserted, the next state output is J. When J=1, K=1 and clock is asserted, the next state output is the complement of previous state and ﬂipﬂop operates as toggle switch. The truth table of JK ﬂipﬂop for present state and next stable state is depicted in Table 7.15. Karnaugh map for the next state output is shown in Fig. 7.48. The logical expression — – of Qn+1 is Qn+1 = JQn + K Qn
State transition diagram of JK ﬂipﬂop
Table 7.15
Truth table of JK ﬂipﬂop
Clock
J
K
Present State Qn
Next State Qn+1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 0
FlipFlops
7.17.2
279
EdgeTriggered JK FlipFlops
The JK ﬂipﬂop will continuously toggle between two output states when both J and K are in high state and the edge triggering of the clock input is not applied. Then JK ﬂipﬂop operates as an astable device. To operate as a bistable device, edge triggering is used so that it toggles only when the clock is asserted on either the rising or falling edge of a clock pulse. The positive and negative edgetriggered JK ﬂipﬂops are depicted in Fig. 7.49 (a) and Fig. 7.49 (b) respectively.
Fig. 7.48 Karnaugh map of JK ﬂipﬂop
7.17.3
Fig. 7.49 (a) Logic symbol of positive edge triggered JK ﬂipﬂop (b) Logic symbol of negative edge triggered JK ﬂipﬂop
JK FlipFlop with Asynchronous Inputs
Asynchronous inputs on a JK ﬂipﬂop have control over – the Q and Q outputs. These inputs are called the preset, PRE and clear, CLR. The preset input drives the ﬂipﬂop to a clear or reset state whereas the clear input drives it to a set state. Figure 7.50 shows the asynchronous JK ﬂipﬂop. If the preset input is high and the clear input is low, the JK – ﬂipﬂop will be cleared and outputs will be Q= 0 and Q =1 despite the consequences of synchronous inputs and the clock signal. If the clear input is high and the preset input – is low, the JK ﬂipﬂop will be set (Q=1, Q=0). The preset (PRE) and clear (CLR) inputs will be used when multiple JK ﬂipﬂops are connected in a group. Asynchronous inputs Fig. 7.50 (a) Logic symbol of asynchronous JK ﬂipﬂop with reset and clear may be activehigh or activelow. If inputs are activelow, (b) Logic symbol of asynchronous JK there will be an inverting bubble at that input on the block ﬂipﬂop with inverted reset and clear symbol just like the negative edgetrigger clock inputs.
7.17.4
JK Master Slave FlipFlop
It is clear from Table 7.15 that the ﬂipﬂop is disabled when clock (CLK) =0 and ﬂipﬂop is active when clock (CLK) = 1. Figure 7.46 exhibits instability when J=1, K=1 and CLK=1 due to the feedback of the complementary output signals to input. In this condition the output Q is oscillatory and will stay in this state until clock changes from 1 to 0. To overcome these difﬁculties, a JK master slave ﬂipﬂop is used. In JK ﬂipﬂop, if J=1, K=1, Q=0 and when clock pulse is applied then output Q=1. This change in output takes place after a propagation delay time tPLH. Now J=1, K=1 and Q=1 and if the clock pulse is still present, Q changes back to 0. So for the certain duration of the clock pulse tP, the output will oscillate between 0 and 1. The output Q is ambiguous. This situation is called as racearound condition. To eliminate the racearound condition, tPHL must be grater than clock pulse tP. Therefore, JK master slave ﬂipﬂops are introduced to solve this problem.
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Digital Electronics: Principles and Applications
Figure 7.51 shows the diagram of JK master slave ﬂipﬂop. This is the cascade connection of two JK ﬂipﬂops. The ﬁrst ﬂipﬂop is called master and other one is called as slave. The master is clocked in the normal way but the inverted clock is applied to slave. It is assumed that the changes in J and K inputs does not effect on output when clock is low and master ﬂipﬂop is disabled. When the clock changes low – to high, the output of master ﬂipﬂop (Qm and Q m) changes and these changes are fed to the input of the – slave ﬂipﬂop. But there is no change at the output of slave ﬂipﬂop (Q and Q ) as inverted clock pulse is – applied to slave ﬂipﬂop. Consequently, feedback inputs Q and Q will not effect due to no change. When clock changes high to low, master’s output can be transferred to slave ﬂipﬂop. Therefore, the output of slave ﬂipﬂop changes by shifting data from maser to slave ﬂipﬂop at the end of each clock pulse. The timing diagram of JK master slave ﬂipﬂop is shown in Fig. 7.52.
Fig. 7.51
Example 7.6
JK Master slave ﬂipﬂop
Fig. 7.52
Waveform of JK ﬂipﬂop
Draw the output waveform of JK master slave ﬂipﬂop with the following inputs as shown Fig. 7.53.
� Solution Figure 7.54 shows the output waveform of JK master slave ﬂipﬂop, where – Qm and Q m are outputs of master ﬂipﬂop and slave ﬂipﬂops outputs are Q – and Q . The master ﬂipﬂop is positive edge triggered but the slave ﬂipﬂop is negative edge triggered. Initially, J=1 and K=0 and output of the master – ﬂipﬂop will be Qm =1 and Q m= 0 just after the positive edge of ﬁrst clock pulse. Before the negative edge of ﬁrst clock pulse, inputs of slave ﬂipﬂop – are J = Qm =1 and K= Q m= 0. After the negative edge of ﬁrst clock pulse, – outputs of slave ﬂipﬂops are Q = 1 and Q = 0. Thus, we can also justify the other outputs of JK master slave ﬂipﬂop for remaining clock pulses.
7.18
T FLIPFLOP
Fig. 7.53
Fig. 7.54
Figure 7.55 shows the symbol of T ﬂipﬂop and table of operation is given in Table 7.16. When T=0, output of T ﬂipﬂop Qn+1= Qn. When T=1, output of T ﬂipﬂop Qn+1 is complement of Qn. As output of — ﬂipﬂop is complement of Qn , Qn this circuit is known as toggle circuit.
281
FlipFlops Table 7.16
Input T 0 0 1 1
7.18.1
Truth table of T ﬂipﬂop
Present State Qn
Output Next State Qn+1
0 1 0 1
0 1 1 0
Remarks Latch Toggle
Fig. 7.55 Symbol of T ﬂipﬂop
T Latch with Enable
A T latch with Enable has two inputs namely a enable input, E and data input, T. When enable input E is asserted, the state of T ﬂipﬂop changes. Figure 7.56 shows the state transition diagram of the T latch. The truth table of T latch with present state and next state is depicted in Table 7.17. Figure 7.57 shows the Karnaugh map for next state transition Qn+1 of T latch with enable and present state as inputs. The logic expression of the next state is – — Qn+1 = T Qn + T Q n .
Fig. 7.56
T Latch
The logic symbol is depicted in Fig. 7.58. Table 7.17
Fig. 7.57 Karnaugh map of T latch
Truth table of T Latch
Enable
T
Present State Qn
Next State Qn+1
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 1 0 1 0 1 1 0
7.18.2
Edgetriggered T FlipFlops
Fig. 7.58 Logic symbol of T latch with enable
The edge triggered T ﬂipﬂop reacts to the data input T only when the clock input is activated. The clock is asserted on either the rising or falling edge of a clock pulse. The positive and negative edgetriggered D ﬂipﬂops are depicted in Fig. 7.59 (a) and Fig. 7.59(b) respectively.
7.18.3
T FlipFlop With Asynchronous Inputs
Fig. 7.59 (a) Logic symbol of positive edge triggered T ﬂipﬂop (b) Logic symbol of negative edge triggered T ﬂipﬂop
Figure 7.60 shows the asynchronous T ﬂipﬂop. If – the preset input is high and the clear input is low, the T ﬂipﬂop will be clear (Q=0, Q =1) despite the
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Digital Electronics: Principles and Applications
consequences of synchronous inputs or the clock signal. If the preset input is low and the clear input is high, the T ﬂipﬂop will be set – (Q=1, Q =0). Preset (PRE) and clear (CLR) inputs will be used when multiple T ﬂipﬂops are connected in a group. Asynchronous inputs may be activehigh or activelow. If inputs are activelow, there will be an inverting bubble Fig. 7.60 at that input on the block symbol same as the negative edgetriggered clock inputs. Example 7.7
(a) Logic symbol of asynchronous T ﬂipﬂop with reset and clear (b) Logic symbol of asynchronous T ﬂipﬂop with inverted reset and clear
The waveforms as depicted in Fig. 7.61 are applied to a T ﬂipﬂop. Draw the output waveform of the clocked T ﬂipﬂop.
� Solution The output waveform of clocked T ﬂipﬂop is shown in Fig. 7.62. Assume the initial state of T ﬂipﬂop Q is 0. During the ﬁrst clock pulse T=0, then output Q will be 0. At the instant of second clock pulse, T=1, the output will be the complement of previous state. So, the output Q is 1. Similarly, we can determine the output of T ﬂipﬂop for remaining clock signal and T input.
Fig. 7.61
Fig. 7.62
Example 7.8
A positive edge triggered T ﬂip ﬂop with PRE and CLR inputs is shown in Fig. 7.63. Draw the output waveform. Consider initial output is low.
� Solution Figure 7.64 shows the output waveform and its explanation is given below: v
During the ﬁrst clock pulse, the preset (PRE) and clear (CLR) are low and T is high. The ﬂipﬂop operates in toggle mode.
v
In second, third and fourth clock pulse preset (PRE) is high and clear (CLR) is low, ﬂip ﬂop is reset and output does not depend on input.
v
During the ﬁfth clock pulse, both preset (PRE) and clear (CLR) are low and T is high. Then ﬂipﬂop again operates in toggle mode.
v
For sixth and seventh clock pulse, preset (PRE) is low and clear (CLR) is high, ﬂip ﬂop is set regardless of synchronous input.
Fig. 7.63
Fig. 7.64
283
FlipFlops
7.19 CONVERSION FROM ONE TYPE OF FLIPFLOP TO ANOTHER TYPE The circuit diagram, logic symbol and working principle of SR, JK, D and T ﬂipﬂops are already incorporated in this chapter. Presently, the conversion from one type of ﬂipﬂop to another type by using a formal technique is explained in this section. The problem of changing from one type ﬂipﬂop to another type is the design of second type of ﬂipﬂop using the ﬁrst ﬂipﬂop as a memory element. This conversion is very useful in the design of clocked sequential circuits. Figure 7.65 shows the bock diagram for conversion from one type ﬂip Fig. 7.65 Block diagram of conversion of one type of ﬂipﬂop to another ﬂop to another type. In this conversion process, some steps are followed. The ﬁrst step of conversion is that write the present and next state truth table of ﬂipﬂops. The next step is to design a combinational logic circuit to produce the next state output from inputs and present output state using Karnaugh map. The ﬁnal step is implementation of combinational logic circuit using logic gates. The conversion of SR to JK, JK to SR, JK to D, JK to T, SR to T and D to T are explained in this section.
7.19.1
Conversion of SR FLIPFLOP to JK FLIPFLOP
The truth tables of SR and JK FLIPFLOP are depicted in Table 7.18, which will be used for conversion from SR ﬂipﬂop to JK ﬂipﬂop. Figures 7.66 (a) and 7.66(b) show the Karnaugh map for S and R with J, K and Qn inputs. From these Kmaps the logic expressions for S and R are derived as follows: – S = J.Qn and R = K.Qn. The implementation of JK ﬂipﬂop using SR ﬂipﬂop and logic gates is shown in Fig. 7.67. Table 7.18
JK FLIPFLOP inputs J K
Truth table of JK and SR ﬂipﬂop
Output Qn
SR FLIPFLOP inputs Qn+1 S R
0
0
0
0
0
x
0
1
0
0
0
x
1
0
0
1
1
0
1
1
0
1
1
0
0
0
1
1
x
0
0
1
1
0
0
1
1
0
1
1
x
0
1
1
1
0
0
1
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Digital Electronics: Principles and Applications
Fig. 7.66 (a) Kmap for S (b) Kmap for R
7.19.2
Conversion of JK FLIPFLOP to SR FLIPFLOP
The truth table for conversion from JK to SR ﬂipﬂop is shown in Table 7.19. Figure 7.68 shows the Karnaugh map for J and K with S, R and Qn inputs. From these Kmaps the logic expressions for J and K are derived as follows: – J = SR and K = RQn
Fig. 7.67 Conversion from SR ﬂipﬂop to JK ﬂipﬂop
Figure 7.69 shows the conversion of JK ﬂipﬂop to SR ﬂipﬂop by using a additional circuit consists of one NOT and two AND gates Table 7.19 Truth table of JK and SR ﬂipﬂop
SR FLIPFLOP inputs S R 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Output Qn 0 0 0 0 1 1 1 1
Qn+1 0 0 1 0 1 0 1 0
JK FLIPFLOP inputs J K 0 0 1 0 x 0 x 0
Fig. 7.68 (a) Kmap for J (b) Kmap for K
x x 0 0 0 1 0 1
285
FlipFlops
Fig. 7.69 Conversion of JK ﬂipﬂop to SR ﬂipﬂop
7.19.3
Conversion of JK FLIPFLOP to T FLIPFLOP
Truth table of conversion from JK to T ﬂipﬂop is given in Table 7.20. It is clear from table that when J and K inputs of JK ﬂipﬂop are connected, it behaves as a T ﬂipﬂop. The logical expression for T is J=K=T. Figure 7.70 shows the conversion of JK ﬂipﬂop to T ﬂipﬂop. Table 7.20
Truth table of conversion from JK to T ﬂipﬂop
T ﬂipﬂop inputs T
Qn
0
0
0
0
0
0
1
1
0
0
1
0
1
1
1
1
1
0
1
1
7.19.4
Output Qn+1
JK ﬂipﬂop inputs J K
Fig. 7.70 Conversion from JK to T ﬂipﬂop
Conversion of D FLIPFLOP to T FLIPFLOP
Table 7.21 shows the truth table of conversion from D to T ﬂipﬂop. Using this table, the logical – — expression of D can be derived as a function of T and Qn. So D (T, Qn) = Qn.T + QnT = Qn≈T. The implementation conversion of D ﬂipﬂop to T ﬂipﬂop using logic expression D(T,Qn)= Qn≈T is shown in Fig. 7.71. Table 2.21
Truth table of conversion from D to T ﬂipﬂop
T ﬂipﬂop inputs
7.19.5
Output
D ﬂipﬂop inputs
T
Qn
Qn+1
D
0
0
0
0
0
1
1
1
1
0
1
1
1
1
0
0
Fig. 7.71
Conversion of D ﬂipﬂop to T ﬂipﬂop
Conversion of SR FLIPFLOP to T FLIPFLOP
The truth table of conversion from SR to T ﬂipﬂop is shown in Table 7.22. Using this table, the logical — expressions S(T,Qn) and R(T,Qn) are derived as S(T,Qn) = TQn and R(T,Qn) = TQn. The implementation — conversion of SR to T ﬂipﬂop using logic expressions S(T,Qn) = TQn and R(T,Qn) = TQn is shown in Fig. 7.72.
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Digital Electronics: Principles and Applications
Table 7.22
Truth table of conversion from SR to T ﬂipﬂop
T ﬂipﬂop inputs T
Output Qn Qn+1
SR ﬂipﬂop inputs S R
0
0
0
0
x
0 1 1
1 0 1
1 1 0
0 1 0
0 0 1
Fig. 7.72 Conversion of SR ﬂip ﬂop to T ﬂipﬂop
7.19.6 Conversion of JK FLIPFLOP to D FLIPFLOP JK ﬂipﬂop can be operate as a D ﬂipﬂop as shown in Fig. 7.73. The truth table of conversion from JK to D ﬂipﬂop is shown in Table 7.23. It is depicted in table that the input data will be transferred at the output when – clock is applied. Using this table, the logical expressions for J and K is derived as J=D, K = D. Table 7.23 Truth table of conversion from JK to T ﬂipﬂop
D ﬂipﬂop inputs D
Qn
Qn+1
0
0
0
0
1
0
0
1
1
0
1
1
0
1
1
1
0
0
Example 7.9
Output
JK ﬂipﬂop inputs J K 0
0 Fig. 7.73 Conversion JK ﬂipﬂop to D ﬂipﬂop
Convert T ﬂipﬂop into JK ﬂipﬂop
� Solution The truth table of conversion from T ﬂipﬂop to JK ﬂipﬂop is shown in Table 7.24. Using this table, the — logical expression of T(J, K, Qn) can be derived from Kmap as given in Fig. 7.74. Here, T is T(J,K,Qn) = J Qn — + KQn. The implementation conversion of T to JK ﬂipﬂop using logic expression T(J,K,Qn) = JQ n+KQn is shown in Fig. 7.75. Table 7.24 Truth table of conversion from T to JK ﬂip ﬂop
JK FLIPFLOP inputs J K 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Qn 0 0 0 0 1 1 1 1
Output Qn+1 0 0 1 1 1 0 1 0
T FLIPFLOP input T 0 0 1 1 0 1 0 1
287
FlipFlops
Fig. 7.74 Kmap for T
Fig. 7.75
7.20 OPERATING CHARACTERISTICS OF FLIPFLOPS In the application of ﬂipﬂops, the following parameters are always speciﬁed by the manufacturers v Propagation Delay Time —–– —–– tPLH(CLK to Q), tPHL(CLK to Q), tPLH(PRE to Q), and tPHL(CRE to Q) v v v v v
Set up time Hold time Maximum clock frequency Pulse width Power dissipation
Propagation Delay Time Propagation delay time means that the required interval times to change the output after applying the input signal. The performance of ﬂipﬂop can be measured by different propagation delays: Propagation delay tPLH (CLK to Q) is measured from the 50% triggering edge point of the clock pulse to the 50% transition of the output from Low to High. This time delay is shown in Fig.7.76
Fig. 7.76
Propagation delays tPLH clock to output
Propagation delay tPHL (CLK to Q) is measured from the 50% triggering edge of the clock pulse to the High to Low transition of the output as depicted in Fig. 7.77.
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Digital Electronics: Principles and Applications
—–– Propagation dealy tPLH (PRE to Q) is measured from the 50% preset input to the Low to High transition of th e output. This delay is shown in Fig. 7.78.
Fig. 7.77 Propagation delays tPHL clock to output
Fig. 7.78 Propagation delays tPLH preset to output
— –– Propagation dealy tPHL (CLR to Q) is measured from the 50% clear input to the High to Low transition of the output as depicted in Fig. 7.79
Maximum clock frequency ( fmax ) Maximum clock frequency is the highest clock frequency at which the ﬂipﬂop can be triggered. If the clock frequency is above maximum, the ﬂipﬂop will not be able to respond properly. Setup time (tset up ) Set up time is the minimum time that input signal must be present on input terminal prior to the triggering edge of the clock pulse as depicted in Fig. 7.80. tset up is approximately 20ns for TTL ICs. Therefore, the input of a D FF must be held constant for at least 20ns before applying a positive edgetriggering clock into the ﬂipﬂop.
Fig. 7.79 Propagation delays tPHL clear to output
Fig. 7.80
Setup time
Hold time (thold ) The hold time is the minimum time interval that signal must remain at the terminal after the triggering edge of the clock pulse. thold is approximately 5ns. Therefore, the input signal of D ﬂipﬂop will be removed at about 5ns after the positive edge of the clock has applied. Figure.7.81 shows the hold time of a D ﬂipﬂop.
289
FlipFlops
Pulse width Generally, the manufacturer speciﬁes the minimum pulse widths for the clock, preset, and clear inputs to operate ﬂipﬂop adequately. Typically, the clock is speciﬁed by its minimum high pulse width and minimum low pulse width. Clock high pulse width This is the minimum time that clock must remain in its high state for reliable operation. It is approximately 15ns.
Fig. 7.81
Hold time
Clock low pulse width This is the minimum time that clock must remain low for reliable operation. This time is approximately 30ns. Power dissipation The power dissipation is one of the important characteristics of ﬂipﬂops. It is actually the total power consumption on the device and measured from P=Vcc Icc. If the ﬂipﬂop operates on a 5V dc supply and draws 25 mA current, the power dissipation will be P=Vcc Icc=5V×25mA=125mW. The comparison of operating performance of different ﬂipﬂop ICs is given in Table 7.25. Table 7.25
Flipﬂop parameters
Comparison of operating performance of ﬂipﬂops
7474(TTL)
7476(TTL)
Flipﬂop ICs 7471(TTL)
74107(TTL)
74112(CMOS)
fmax MHz
15
45
3
20
20
tPHL(CLK to Q)
40
20
150
40
31
tPLH(CLK to Q)
25
20
75
25
31
——– tPHL(C L R to Q) —— tPLH(PRE to Q)
40
20
200
40
41
25
20
75
25
41
ts(setup)
20
20
0
0
25
th(hold)
5
0
0
0
0
Tw(clock High)
30
20
200
20
25
Tw(clock Low)
37
25
200
47
25
Power (mW)
43
10
3.8
25
0.12
7.21 APPLICATIONS OF FLIPFLOPS The basic applications of ﬂipﬂops are v Latch v Frequency division v Memory v Glitch generators
v Registers v Counters v Bounce elimination switch
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Digital Electronics: Principles and Applications
In this section, applications of ﬂipﬂop as registers, frequency division, counters, memory and bounce elimination switch are explained.
7.21.1
Registers
Shift register is one type of sequential logic circuit. This circuit is most commonly used to store digital data. Shift register can be constructed by a group of ﬂipﬂops. The output of one ﬂipﬂop is fed to the next ﬂipﬂop as input. A common clock drives all these ﬂipﬂops and they are set or reset simultaneously. Therefore, data process sequentially. There are four basic types of shift registers namely Serial In  Serial Out, Serial In  Parallel Out, Parallel In  Serial Out, and Parallel In Parallel Out. In Serial In  Parallel Out Shift Fig. 7.82 4 bit register using ﬂipﬂop Registers, data bits are entered serially but the data bits are taken out of the register in parallel. Once the data are stored in the register, each bit appears on its respective output line, and all bits are available simultaneously. A construction of a fourbit serial in  parallel out register is shown below. A 4 bit register using 7474 positive edge triggered ﬂip ﬂop is shown in Fig.7.82. The bits to be stored are applied at the D inputs, which are clocked in at the leading edge of the clock pulse. In this register, the data to be entered must be available in parallel form. The detail operations of registers are incorporated in next chapter.
7.21.2
Frequency Division
The ﬂipﬂop can also be used in frequency division. If a waveform is applied to the clock input of JK ﬂipﬂop, which operates in toggle mode, the frequency of output waveform is half of the input frequency as shown in Fig. 7.83. Therefore, ﬂipﬂop is called as divide by 2 device.
Fig. 7.83
7.21.3
Flipﬂop as divide by 2 device
Counters
Flipﬂops are most commonly used for counting purpose. A 2bit counter consists of two ﬂipﬂops as shown in Fig. 7.84. The ﬂipﬂop used is 74107 JK master slave ﬂipﬂops, which is used as T type. The pulses to be counted are connected at the clock input of FF0. The Q0 output of FF0 is connected to the
291
FlipFlops
Fig. 7.84 2 bit binary upcounter
clock input FF1. The ﬂipﬂops are cleared by applying logic 0 at the clear input terminal momentarily. For normal counting operation, it is to be maintained at logic 1. The pulses and the output waveforms are depicted in Fig. 7.84. The output Q0 of the leastsigniﬁcant stage changes at the negative edge of each pulse. The output Q1 changes at the negative edge of each Q0 pulse. At any time, the decimal equivalent of the binary number Q1 Q0 is the number of pulses counted till that time. For example, at the count is 01 decimal 1. The circuit resets after counting four pulses. The different types of counters are discussed extensively in Chapter 8.
7.21.4
Memory
In digital systems, digital data stored and retrieved whenever required. Flipﬂop can be used to store data for any desired length of time and then read out whenever required. In this memory, data can be written into memory and data can also be read from memory. A 1bit read/write memory is shown in Fig.7.85. It has the three terminal namely data inputs D, an Write/Read and an output Q.
Fig. 7.85
One bit memory cell
In this one bit memory, D Flip Flop has Q Table 7.26 Modes of operation of one bit Memory cell output that follows the D input when E terInputs Mode minal is at logic 1. When the E input changes D from logic 1 to logic 0, the Q output does not Write/Read change and it is retained though the D input Hold, Q=D ¥ ¥ changes. Therefore, E enables the memory 1 0 Write 0 into memory, Q=0 cell for reading or writing operation. If E= 1 1 Write 1 into memory, Q=1 Write/Read is at logic 1 writing operation 0 Read , Q ¥ can be performed. When Write/Read is at logic 0, reading operation is done. The modes of operation are given in Table 7.26. The detailed operations of memory are explained in Chapter 12.
7.21.5
Contact Bounce Elimination
Pushbutton type mechanical switches are usually used in digital instrument as input devices by which digital information is entered into the system. For making a proper electrical contact, the switch open and close several times within a few milliseconds. When the pushbutton switch is released, the discon
292
Digital Electronics: Principles and Applications
nection is not immediate. The switch opens and closes several times before ﬁnal disconnection. So, it is virtually impossible to obtain a clean voltage transition from +Vcc to 0V if a mechanical switch position changes from 1 to 2. The reason for this is the phenomena of contact bounce as shown in Fig. 7.86. It is clear from Fig. 7.86 that the movement of the switch from contact position 1 to 2 produces several output voltage transitions as the switch bounces many times before coming to rest on contact 2. Generally, the multiple output voltage transitions will stay on the output for few milliseconds. This type of output voltage transition is not acceptable in many applications. Therefore, NAND or NOR latch can be used to prevent the presence of switch bounce.
Fig. 7.86
Contact bounces
Fig. 7.87
Contact bounces elimination using SR latch
Figure 7.87 shows the contact bounce elimination using SR latch. Initially, consider switch in position 1, S is low and the Q output is low. When switch position moved to position 2, S is high, R is low and the Q output is high. If the connection with position 2 has been broken due to contact bounce, S is high, R is high. In this condition, the output voltage Q will not be changed. The converse action takes place when the switch is moved to position 1. In this way, bounceelimination circuits can eliminate the contact bounce.
7.22
FLIPFLOP ICS
Most commonly used ﬂipﬂop ICs are edge triggered D and JK ﬂipﬂops, which are available in market. T ﬂipﬂops are not available, but JK ﬂipﬂops can be converted into T ﬂipﬂops. An example of D latch is the 7474 and its pin diagram is depicted in Fig. 7.88. The pin description is given in Table 7.27. The 7474 is highspeed Sigate CMOS devices which are pin compatible with low power Schottky TTL. The 7474 IC is dual positiveedge triggered, Dtype ﬂipﬂops with individual data (D) inputs, clock (CP) inputs, set – (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOWtoHIGH transition of the clock pulse. Figure 7.89 (a) and 7.89 (b) stand for the logic symbol of individual ﬂipﬂops within IC and single block representation of IC respectively. Table 7.28 shows the functional table of 7474. Figure 7.90 shows the timing diagram of D ﬂipﬂop.
Fig. 7.88 Pin diagram of 7474 duel positive edge triggered D ﬂipﬂop
293
FlipFlops Table 7.27
Pin description
Symbol
Name and Function
— — 1R D, 2RD
Asynchronous resetdirect input
1D, 2D
Data inputs
1CP, 2CP Clock input(positive edge, Low to High triggered) – – 1SD, 2SD Asynchronous setdirect input Flipﬂop outputs
1Q, 2Q – – 1Q, 2Q
Complement outputs
GND
Ground
Vcc
Positive suppy voltage
Table 7.28
Function table
Inputs Outputs — — – nSD nRD nCP nD nQ nQ
(a) Individual logic symbol
Fig. 7.89
L
H
x
x
H
L
H
L
x
x
L
H
x
L
L
x
H
H
H
H
L
L
H
H
H
H
H
L
(b) Single block logic symbol
Logic symbol of 7474 duel positive edge triggered D ﬂipﬂop
74LS174 Hex D ﬂipﬂops with Clear 74LS174 IC is a positiveedgetriggered ﬂipﬂop using TTL circuitry to implement Dtype ﬂipﬂop logic. This device has six latches on a single chip with direct clear input. Pin diagram of 74LS174 IC is shown in Fig. 7.91. Data at the D inputs is transferred to the Q outputs on the positivegoing edge of the clock pulse. Clock triggering occurs at a particular voltage level. While the clock input is at either the high or low level, the D input signal has no effect at the output. Logic symbol of 74LS174 Hex D ﬂipﬂops with Clear input is given in Fig. 7.92.
294
Digital Electronics: Principles and Applications
Fig. 7.90
Fig. 7.91
Timing diagram of D ﬂipﬂop
Pin diagram and logic symbol of 74LS174
74LS175 quad D flipflops with Clear Figure 7.93 shows an example of a 74LS175 quad ﬂipﬂop. This device consists of four ﬂipﬂops. The logic symbol of 74LS175 IC is shown in Fig. 7.94. This device has common clears, but no presets.
Fig. 7.92
Logic symbol of 74LS174 Hex D ﬂipﬂops with clear
295
FlipFlops
Fig. 7.93
Fig. 7.95
Pin diagram of 74LS175
Table 7.29
Pin diagram of 74LS273
Pin description of 74273
Pin
Fig. 7.94
Logic symbol of 74LS175 IC
Function
CP
Clock pulse input
D 0 D7 —— MR
Data inputs
Q0 – Q7
Flipﬂop outputs
Asynchronous master reset input
IC 74LS273 The 74LS273 is a highspeed 8bit register, consisting of eight Dtype ﬂipﬂops with a common clock and an asynchronous active LOW master reset. Pin diagram is shown in Fig. 7.95 and logic symbol is depicted in Fig. 7.96. Table 7.29 shows the pin description of 74LS273.
296
Digital Electronics: Principles and Applications
Fig. 7.96
Logic symbol octal D ﬂipﬂop with buffer
74LS73A JK Flipﬂops IC74LS73A is dual negativeedgetriggered master slave JK ﬂipﬂops with clear and complementary outputs. This device contains two independent negativeedgetriggered JK ﬂipﬂops with complementary outputs. The J and K data are processed by the ﬂipﬂops on the falling edge of the clock pulse. The data on the J and K inputs is allowed to change when the clock is high to low. A low logic level on the clear input will reset the outputs regardless of the levels of the other inputs. Pin diagram and logic symbol of IC74LS73A is shown in Fig.7.97 Table 7.30 shows the function table of IC74LS73A. Table 7.30 Function table
K
Outputs – Q Q
x
x
L
H
L
L
Q0
H — Q0
H
H
L
H
L
H
L
H
L
H
H
H
H
x
x
CLR L
H
Inputs CLK J x
H
Fig. 7.97
Pin diagram and logic symbol of IC74LS73A
Toggle Q0
— Q0
74LS279 Quad SR latches Figure 7.98 shows the quad SR latches. The 74LS279 consists of four individual and independent SetReset latches with active low inputs. Two of the four latches have an additional S input ANDed with the primary S input. A low on any S input while the R input is high will be stored in the latch and appear on the corresponding Q output as a high. A low on the R input while the S input is high will clear the Q output to a low. Simultaneous transition of the R and S inputs from low to high will cause the Q output to be indeterminate.
Fig. 7.98
Quad SR Latches
297
FlipFlops
Table 7.31 shows the function table of SR Latch where Q0= the level of Q before the indicated input conditions were established. Table 7.31
Function table of SR Latches
– R
Output Q
L
L
H
– S
Inputs
L
H
H
H
L
L
H
H
Q0
SUMMARY In this chapter, the basic element of sequential circuits, flipflops has been introduced as a basic memory element. This device can be used to store 1 bit of digital information. There are four types of flipflops, namely SR, JK, T type, and D type. All four flipflops have been explained in detail, including their design using logic gates. The triggering systems of flipflops have also been incorporated in this chapter. Flipflops are converted from one type to others. Therefore, conversions of flipflops are also discussed here. Applications of flipflops in registers, frequency division, counters, memory elements, contact bounce elimination, etc. have been included in this chapter.
MULTIPLE CHOICE QUESTIONS 1. 2. 3. 4. 5. 6.
7.
A ﬂipﬂop has two outputs which are – – – (a) Q=0, Q =0 (b) Q=1, Q =1 (c) Q=1, Q =0 A ﬂipﬂop can be built by using (a) NAND gates (b) AND gates (c) AND or OR gates The invalid state of SR ﬂipﬂop is (a) S=1, R=1 (b) S=0, R=0 (c) S=0, R=1 IF a JK ﬂip ﬂop is in reset condition, its output will be – – – (a) Q=0, Q =1 (b) Q=0, Q =0 (c) Q=1, Q =1 When a T ﬂip ﬂop is set, its output will be – – – (a) Q=0, Q =1 (b) Q=0, Q =0 (c) Q=1, Q =1 A JK ﬂipﬂop can be built up using (a) AND gates and clocked SR ﬂipﬂop (c) NOR gates (b) OR gates and D ﬂipﬂop (d) None of these JK ﬂipﬂop can be used as Toggle switch when (a) J and K connected to ground (b) J connected to ground and K connected to + VCC (c) J and K connected to +VCC (d) None of these
(d) None of these (d) None of these (d) S=1, R=0 – (d) Q=1, Q =0 – (d) Q=1, Q =0
298 8. 9. 10. 11.
12.
13. 14.
15.
16.
17.
18. 19. 20.
Digital Electronics: Principles and Applications In a clocked SR ﬂip, R is connected with S through an inverter, the circuit is called (a) JK ﬂipﬂop (b) T ﬂipﬂop (c) D ﬂipﬂop (d) None of these – In a JK ﬂipﬂop, if J=K=1 and clock is applied, the output Q will be (a) 0 (b) No change (c) 1 (d) None of these Race around condition occurs in JK ﬂipﬂop if (a) J=1, K=1 (b) J=0, K=0 (c) J=0, K=1 (d) J=1, K=0 In a ﬂipﬂop with Preset and Clear terminals, (a) Preset and clear operation perform separately (b) In preset operation, clear is disabled (c) In clear operation, preset is disabled (d) None of these Master salve is used to (a) Improve its reliability (c) Eliminate race condition (b) Reduce power dissipation (d) Increase its clock frequency A transparent latch is a (a) D ﬂipﬂop (b) T ﬂipﬂop (c) T or D ﬂipﬂop (d) T and D ﬂipﬂops The initial output of JK ﬂipﬂop Q is 1. It changes to 0, when a clock pulse is applied. The input J and K will be (a) J=1, K=1 (b) J=0, K=0 (c) J=0, K=1 (d) J=1, K=0 The initial output of JK ﬂipﬂop Q is 0. It changes to 1, when a clock pulse is applied. The input J and K will be (a) J=1, K=1 (b) J=0, K=0 (c) J=0, K=1 (d) J=1, K=0 The initial output of SR ﬂipﬂop Q is 0. It changes to 1, when a clock pulse is applied. The input S and R will be (a) S=1, R=1 (b) S=0, R=0 (c) S=0, R=1 (d) S=1, R=0 The initial output of SR ﬂipﬂop Q is 1. It changes to 0, when a clock pulse is applied. The input S and R will be (a) S=1, R=1 (b) S=0, R=0 (c) S=0, R=1 (d) S=1, R=0 Flipﬂops can be used as (a) Latches (b) Registers (c) Counters (d) All of these The digital memory element consists of (a) Flipﬂops (b) NAND gates (c) NOR gates (d) Shift registers Flipﬂops can be used to store (a) One bit data (b) Two bit data (c) One byte data (d) Two byte data
REVIEW QUESTIONS 7.1 7.2
What will be the output of a NAND latch as shown in Fig. 7.13 for the following cases? (a) S=0, R=1 (b) S=1, R=0; Deﬁne ﬂipﬂop. Explain the principle of operation of SR ﬂipﬂop with truth table. Draw the output waveform of SR ﬂipﬂop.
FlipFlops 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14
7.15
299
Design a SR ﬂipﬂops using NOR gates and draw the output waveform. Why S=1 R=1 condition is invalid in SR ﬂipﬂop? What is a clocked ﬂipﬂop? Explain the principle of operation of clocked SR ﬂipﬂop with truth table. Draw the output waveform. Explain the function preset and clear inputs of SR ﬂipﬂop. Explain the principle of operation of clocked maser slave SR ﬂipﬂop with output waveform. Draw the circuit diagram of positive edge triggered D ﬂipﬂop. Explain its operation using truth table and waveform. Why is it called as delay ﬂipﬂop? Explain the principle of operation of clocked T ﬂipﬂop with truth table and output waveform. Why it is called as toggle switch? Write the truth table of JK ﬂipﬂop and explain the principle of operation of clocked JK ﬂipﬂop with output waveform. What is race condition in ﬂipﬂop? What will be the state of JK ﬂipﬂop in the following cases? (a) J=1; K=1; Qn=0 (b) J=0; K=1; Clear low Explain JK master slave ﬂipﬂop with output waveform. What are the different forms of triggering in ﬂipﬂops? Explain any one with example. Difference between level, negative edge tiggered and master slave ﬂipﬂop. What is the conversion of one type of ﬂipﬂop to other type? Explain the following ﬂipﬂop conversions (a) SR to JK (b) JK to SR (c) JK to T (d) JK to D Draw the output waveform of a clocked SR latch, when the inputs are as shown in Fig. 7.99.
Fig. 7.99
7.16 7.17
What is edge triggering and level triggering? Explain edge triggering SR ﬂipﬂop with waveforms. Draw the output waveform of a clocked D latch, when the inputs are as given in Fig. 7.100
Fig. 7.100
7.18
Draw the output waveform of a clocked T latch, when the inputs are as given in Fig .7.101
300
Digital Electronics: Principles and Applications
Fig. 7.101
7.19
Draw the output waveform of a clocked J K latch, when the inputs are as depicted in Fig. 7.102.
Fig. 7.102
7.20
7.21
Show the output for the changes of input (a) S=1, R=0 to S=R=0 , and (b) S=0, R=1 to S=R=0 Write the truth table of ﬂipﬂop as shown in Fig. 7.103. Sketch the waveforms of input clock and output when J=1010 1100 and K=0110 0101.
Fig. 7.103
7.22
If the waveforms as shown in Fig. 7.102 is applied to the JK master slave ﬂipﬂop as given in Fig. 7.104, draw the output waveform.
Fig. 7.104
7.23
Deﬁne D and T ﬂipﬂop. Write the truth table and draw waveform. Design the D and T ﬂipﬂop using JK ﬂip ﬂop.
FlipFlops 7.24
7.25
301
Carry out the following conversions i) SR to D, ii) JK to D, iii) D to JK, iv) SR to T, v) JK to T, vi) T to JK, vii) T to D, viii) D to SR, ix) D to T, x) T to SR, xi) JK to SR Proof that the circuit as shown in Fig. 7.105(a) and (b) behave as a toggle switch.
Fig. 7.105 (a) and (b)
7.26
Draw the output of ﬂipﬂop FF0 and FF1 with respect to clock signal. Assume all Flipﬂops are initially reset. What is the condition for proper operation of the circuit as shown in Fig. 7.106?. How we remove race around condition of data transfer using negative edge triggered D ﬂipﬂops.
Fig. 7.106
7.27
Draw the output of Q0 and Q1 of ﬂipﬂop, FF0 and FF1 when the clock signal is applied as per Fig.7.107. Assume all ﬂipﬂops are initially reset.
Fig. 7.107
CHAPTER
8 SEQUENTIAL CIRCUITS 8.1
INTRODUCTION
A sequential circuit consists of memory elements, such as ﬂipﬂops and combinational logic circuits. Figure 8.1 shows the basic block diagram of a sequential circuit. The sequential circuit is a feedback system as the present state of the circuit is fed back to the input decoder and is used to determine the next state of the machine. The next state of the machine can be determined by the present state of the circuit and inputs. The input decoder performs the logic operations based on the present state of the circuit and inputs and generates Fig. 8.1 Basic block diagram of sequential circuit next state code of the circuit. Then the next state code is stored in the memory. In sequential circuit, the output depends on the immediate input to the circuit and also the present state of the circuit. The present state of the circuit is also stored in the memory element. There are two types of sequential circuits, such as synchronous sequential circuit and asynchronous sequential circuit. In synchronous sequential circuit, state changes are synchronised to the periodic clock pulses but state changes of asynchronous sequential circuit are not synchronised with clock signal. Most commonly used sequential circuits are registers and counters. In this chapter, operating principles and applications of registers and counters are discussed in detail.
8.2
REGISTER
Registers are digital circuits which are used to store ‘n’ bits information in the same time and each bit is stored in a ﬂipﬂop. Generally, registers are building with D ﬂipﬂops. Registers can also be designed using SR and JK ﬂipﬂops and presently, they are available in MSI ICs. In a register, data can be entered in serial form and data can also be output in serial form. Then this register is called as shiftregister since data bits are shifted in the ﬂipﬂops with each clock pulse. Data can be shifted either in right direction or left direction or bidirectional. When the data is shifted from left to right, it is known as right shift register. If data is shifted right to left, it is called as left shift register. In bidirectional shift register, data can be shifted either left to right or right to left, depending upon the mode control signal.
303
Sequential Circuits
8.3
SHIFT REGISTER
Shift register is an example of sequential logic circuit. This logic circuit is most commonly used to store digital data during arithmetic and logical operations. Shift register can be constructed by a group of ﬂipﬂops. Each ﬂipﬂop can store one bit, so a register composed of ‘n’ ﬂipﬂops can store a ‘n’ bit number. The output of one ﬂipﬂop is fed to the next ﬂipﬂop as input. All these ﬂipﬂops are driven by a common clock and they are set or reset simultaneously. Therefore, the data process sequentially. The storing of one bit data using D ﬂipﬂop is shown in Fig. 8.2. It is depicted in Fig. 8.2(a) that data input D is 1 and clock is applied. Then input data ‘1’ is stored in ﬂipﬂop as output of D ﬂipﬂop is 1. If input is removed, Fig. 8.2 D ﬂipﬂop as one bit storage element output will be remaining same. Similarly, ‘0’ can be stored in D ﬂipﬂop as shown in Fig. 8.2(b). In this chapter, the operation of different types of shiftregisters and their applications have been discussed. The operation of bidirectional type shift register is also explained.
8.4
CLASSIFICATION OF SHIFT REGISTER
There are four basic types of shift registers, namely Serial In  Serial Out (SISO), Serial In  Parallel Out (SIPO), Parallel In  Serial Out (PISO), and Parallel In  Parallel Out (PIPO). In this chapter, all four types shift registers are explained brieﬂy.
8.4.1
Serial InParallel Out (SIPO) Shift Registers
In Serial In – Parallel Out (SIPO), data is applied at the input of register in serial form and the output can be obtained in parallel form after the completely shifting of data in register.Figure 8.3 Fig. 8.3 Serial data input and parshows the serial input data, and then parallel output. allel data output in SIPO
8.4.2
Serial InSerial Out (SISO) Shift Registers
shift register
In Serial In – Serial Out shift register, data input is in serial form and clock pulses are applied to each ﬂipﬂop. After each clock pulse, data moves by one position. The output can be obtained in serial form. In this type of shift register, data moves either in left or right direction. Fig. 8.4 Serial data input and serial data output in SISO shift register It is depicted in Fig. 8.4 that data inputs in the shift register are serially 1001 and data output from shift register is also serially.
8.4.3
Parallel InSerial Out (PISO) Shift Registers
In Parallel In – Serial Out shift register, data is loaded into shift register in parallel form and the data output obtained will be serial form as illustrated in Fig. 8.5.
Fig. 8.5 Parallel data input and serial data output in PISO shift register
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Digital Electronics: Principles and Applications
8.4.4
Parallel InParallel Out (PIPO) Shift Registers
In Parallel In – Parallel out shift register, data is loaded in parallel form and the data output will be in parallel. In Fig. 8.6, data input is in parallel form but data output from shift register is also in parallel form.
8.5 UNIDIRECTIONAL SHIFT REGISTERS Fig. 8.6 Parallel data input and parallel data output in PIPO shift register
The shift registers generally perform data shifting operation from left to right. In unidirectional shift register, data can be shifted in left or right direction. When the data movement is in left direction, the register is called as left shift register. If the data movement is in right direction, the register is called as right shift register.
8.5.1
Fig. 8.7 (a) and (b) 4 bit left shift register
Left Shift Registers
The left shift register is shown in Fig. 8.7(a) and (b). In this shift register, data is entered in serial form and data output is also in serial form and data moves right to left. If the serial data input is 1001, after fourth clock pulse, 1001 data will be loaded into a 4bit shift register. After ﬁfth clock pulse, MSB ‘1’ will be output as serial data output terminal. Just after sixth clock pulse, the next bit ‘0’ will be the output. Similarly, on the seventh clock pulse, the next bit ‘0’ will be out. After eight clock pulse, last bit ‘1’ will be the output.
8.5.2
Right Shift Registers
The right shift register is shown in Fig. 8.8 (a) and (b). In right shift register, data is entered in serial form and data output is also in serial form. Data moves left to right. Its operation is similar with left shift register but only difference is the Fig. 8.8 (a) and (b) 4 bit right shift register direction of data movement. After four clock pulses, four bit data will be loaded completely into shift register. From ﬁfth to eighth clock pulse, data will be output serially at output terminal.
8.6
BIDIRECTIONAL SHIFT REGISTERS
Sometimes, the same shift register can be used as left shift or right shift with some additional circuits. We can multiply a binary number by 2, just simply placing the binary number in a shift register and shifting the number by one bit to the left. Only care has to be taken that a ‘1’ is not shifted out of the most signiﬁcant stage of the register. Similarly, a binary number can be divided by ‘2’ when we simply shift the number to the right by one stage or one bit. The operation of bidirectional shift register can be explained using Fig. 8.9.
Sequential Circuits
305
The bidirectional shift register is one in which the data can be shifted either left or right. A three bit bidirectional shift register using D ﬂipﬂops is shown in Fig. 8.9. Here a set of NAND gates are used to select data inputs from the right or left adjacent ﬂipﬂops, as selected by the —— — LEFT/RIGHT control line. The serial left shift and right shift Fig. 8.9 Bidirectional shift register operation of register can be per—— — —— — formed by using LEFT/RIGHT control signal. When the mode control signal LEFT/RIGHT=1, the data will —— — be shifted to the right when clock pulses are applied. In the mode control signal LEFT/RIGHT=0, the input —— — data will be shifted to the left when clock pulses are applied. The mode control signal LEFT/RIGHT should be changed only when CLK = 0, otherwise the data stored in the shift register may be changed.
8.7 SERIAL INPARALLEL OUT (SIPO) SHIFT REGISTERS 8.7.1 4 bit SIPO Shift Register using D ﬂipﬂop In SIPO shift register, data bits are entered in shift register serially and the data bits are taken out of the register in parallel. When the data are stored in shift register, each bit appears on its respective output line. Therefore, all output bits are available simultaneously. The construction of a fourbit Serial In  Parallel Out shift register is shown in Fig. 8.10. Figure 8.10 is a 4bit shift register using D ﬂipﬂops. The serial data is fed to the input Fig. 8.10 Four bit serial in  parallel out shift register D of ﬂipﬂop, FF0 and output is obtained in parallel form at the output of ﬂipﬂops, FF0, FF1, FF2 and FF3. In this shift register, positive edge triggered ﬂipﬂops are used. So the data are transferred on the positive edge of the clock pulse. The clear signal is applied to all four ﬂipﬂops. The waveform of 4 bit serial input parallel output shift register is shown in Fig. 8.11. The truth table of this shift register is also depicted in Table 8.1. Table 8.1
Truth table of 4 bit SIPO shift register
Clear Input before L H H H H
clock pulse
Clock pulse
x 1 0 0 1
0 1 2 3 4
Output Q 0 Q1 Q2 Q3 0 1 0 0 1
0 0 1 0 0
0 0 0 1 0
0 0 0 0 1
Fig. 8.11 Waveform of 4bit serial input and parallel output shift register
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Digital Electronics: Principles and Applications
Table 8.1 gives details of the operation of SIPO shift register. At the start clear input is low, and all ﬂipﬂops will be reset. So the output of all ﬂipﬂops is low and Q0 = 0, Q1 = 0, Q2 = 0, and Q3= 0. The serial input data is marked as x. It means that the input has no effect on output. Before applying the next clock pulses, clear input terminal is high and data input is in serial form. Data ‘1’ has been applied to the FF0 of shift register; Fig. 8.12 Logic symbol of 4bit shift register input data ‘1’ has to be transferred to the output of FF0 on positive edge of clock pulse. Therefore, after the ﬁrst clock pulse Q0 is 1 and other outputs are low means Q1 = 0, Q2 = 0, and Q3= 0. Now, input of FF0 is 0 and input of FF1 is Q0 =1. When the next positive edge clock pulse occurs, the output of ﬂipﬂop FF0 has been transferred to next ﬂipﬂop FF1 and the output of ﬂipﬂop FF1 has been transferred to next ﬂipﬂop FF2. As input to the Flip ﬂop FF0 is low, output of FF0 will be 0. Similarly, output of FF1 is Q1= 1. Therefore, after application of second clock pulse, the output of ﬂipﬂops are Q0 = 0, Q1 = 1, Q2 = 0, and Q3= 0. Before applying the third clock pulse, input of FF0 is 0, but inputs of FF1 and FF2 are Q0=0, and Q1=1 respectively. When the third clock pulse applied, data is shifted from FF0 to FF1, FF1 to FF2 and the output of ﬂipﬂops are Q0 = 0, Q1 = 0, Q2 = 1, Q3= 0. When the last bit ‘1’ is applied to the data input and the fourth clock pulse is applied, the ‘1’ is entered into FF0 and stored in this ﬂipﬂop. But data is shifted from FF0 to FF1, FF1 to FF2 and FF2 to FF3. After fourclock pulse, the output of ﬂipﬂops are Q0 = 1, Q1 = 0, Q2 = 0, Q3 = 1. Consequently, the digital output will be 1001 and this output data are in parallel form. Timing diagram of 4 bit SIPO shift register is shown in Fig. 8.11 and it’s logic symbol is given in Fig. 8.12.
8.7.2 SIPO Shift Register using JK ﬂipﬂop Figure 8.13 shows the serial input parallel output shift register using JK ﬂipﬂops. The serial input data is connected to the J input of ﬂipﬂop FF0 and its complement to the K input. The normal and complement outputs of each ﬂipﬂop are connected to the J and K inputs of the next ﬂipﬂop respectively. The clear inputs of all the ﬂipﬂops are commonly connected. When clear input is low, all the ﬂipﬂops will be reset. The clock inputs of all the ﬂipﬂops are also connected to a common line, so that clock pulse can be applied to all ﬂipﬂops simultaneously in the register and all the ﬂipﬂops are toggled simultaneously. This shift register is also operates according to Table 8.1 and its wave form will Fig. 8.13 Four bit serial in – parallel out shift register using JK ﬂipﬂops be same as Fig. 8.11. Example 8.1
Draw the waveform of 4bit SIPO register, when input data is 1010.
� Solution The logic symbol of 4bit SIPO shift register is shown in Fig. 8.14(a). Here serial data input is 1010. Initial data input is ‘1’, when clock pulse is applied, data ‘1’ is stored in Q0 and other ﬂipﬂops are in reset condition.
307
Sequential Circuits
During second clock pulse, input data is ‘0’. Just after application of second clock pulse, Q0 becomes ‘0’ and previous state of Q0 is shifted to Q1. At this instant Q1=1, and Q2=Q3=0. At the instant of third clock pulse, input data is 1, so after third clock pulse Q0=1, Q1=0 and Q2=1. Then at fourth clock pulse, input data is 0, output will be Q0=0, Q1=1, Q2=0 and Q3=1. As it is a four bit register, after the four clock pulse, data input
Fig. 8.14(a)
Logic symbol of 4 bit SIPO shift register
Fig. 8.14(b)
Waveform of 4 bit SIPO register
operation will be completed and data will be available at output terminals. The register output after four clock pulses is 1010 as shown in Fig. 8.14(b).
8.8
SERIAL INSERIAL OUT SHIFT REGISTERS
A basic fourbit serial in –serial out shift register can be constructed using four D ﬂipﬂops, as shown in Fig. 8.15. The operation of the circuit is as follows. In this shift register, data inputs serially means one bit at a time on a single line and data outs in Fig. 8.15 Four bit serial in – serial out shift register using serial form. When clear input is D ﬂipﬂops low, the register is ﬁrst cleared and the output of all four ﬂipﬂops will be zero. After that clear input is in high state and the input data is applied sequentially to the D input of the ﬁrst ﬂipﬂop (FF0). As soon as clock pulse is applied, input data has to be transferred to the output of FF0 on positive edge of clock pulse. If the clock pulse is applied sequentially, one bit is transmitted from left to right on each clock pulse. Fig. 8.16 Data inputs and Therefore, data is shifted from FF0 to FF1, FF1 to FF2 and FF2 to clock waveform of shift register FF3 respectively. If a data word to be 1101, after fourclock pulse the least signiﬁcant bit of the data has to be shifted through the register from FF0 to FF3 and 1101 data will be stored in register. Accordingly, the data input operation completes. Timing diagram of shift register output is given in Fig. 8.16. In order to get the data out of the register, data must be shifted serially and taken out from FF3. After fourth clock pulse, the least signiﬁcant bit of the data appears on FF3. When the next clock pulse is applied, the second bit data comes out on FF3. Similarly, the third bit and fourth bit appear on FF3 sequentially after applying corresponding clock pulses. While the original four bit are being shifted completely, a new four bit number can be entered in the shift register.
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Digital Electronics: Principles and Applications
The data out of shift register can be done destructively or nondestructively. In destructive readout, the original data is lost and at the end of the read cycle, all ﬂipﬂops are reset to zero. To avoid the loss of data, an arrangement for a nondestructive reading can be possible Fig. 8.17 Nondestructive reading of SISO shift register by adding two AND gates, an OR gate and an inverter to the shift register. The construction of this circuit is shown in Fig. 8.17 When the R/W control line is high; the data is loaded to the shift register. If the R/W control line is low, the data can be shifted out of the Fig. 8.18 Four bit Serial In – Serial Out shift register using JK ﬂipﬂops register. The implementation of SISO shift register using JK ﬂipﬂops is shown in Fig. 8.18. Example 8.2
Draw the waveform of 4 bit register as shown in Fig. 8.19 for four clock pulses, when input data is 1001. Assume that initially the register content is 0000.
�
Solution
Fig. 8.19 Four bit serial in – serial out shift register using D ﬂipﬂops
Fig. 8.20
Four bit serial in–serial out shift register using D ﬂipﬂops
As initially the register content is 0000, Q0=Q1= Q2= Q3= 0. During first clock pulse, data input is 1. Consequently, after first clock pulse, data ‘1’ is stored in Q0 and other flipflops are in reset conditions. At the instant of second clock pulse, data is 0. Just after application of second clock pulse, Q0 becomes 0 and Q1=1 as Q0 is shifted to Q1. Similarly after third clock pulse, Q0=0, Q1=0 and Q2=1. At fourth clock pulse, data is 1, then output will be Q0=1, Q1=0, Q2=0 and Q3=1. As a result, after application of four clock pulses, ‘1’ will be output at output data terminal Q3 of shift register. Figure 8.20 shows the waveform of 4 bit register for four clock pulses.
Sequential Circuits
8.9
309
PARALLEL INPARALLEL OUT SHIFT REGISTERS
In Parallel In  Parallel Out shift registers, all data bits are entered simultaneously on the parallel input lines rather than on a bit by bit basis on serial data inputs. After simultaneously entry of all data bits, the data bits are available on the output lines immediately. Figure 8.21 shows a fourbit Parallel In  Parallel Out shift register constructed by D ﬂipﬂops. The D0, D1, D2, D3 are the parallel inputs and the Q0, Q1, Q2, Q3 are the parallel outputs. When Fig. 8.21 Parallel In – Parallel Out shift register a common clock is applied to all ﬂipﬂops of this register, all the data at the D inputs D0, D1, D2, D3 should appear at the corresponding Q outputs simultaneously.
8.10 PARALLEL INSERIAL OUT SHIFT REGISTERS A fourbit Parallel InSerial Out shift register is shown in Fig. 8.22. The circuit uses D ﬂipﬂops and logic gates for entering/loading data to the register. D0, D1, D2 and D3 are the four parallel input lines, where D0 is the most signiﬁcant bit and D3 is the least signiﬁcant bit. The SHIFT/ ——— LOAD input used for entering four bits of data into the register. When the mode control line, SHIFT/ ——— LOAD is LOW, the Fig. 8.22 Logic diagram of four bit Parallel In – Serial Out shift register data is applied to the D input of respective ﬂipﬂops. After application of a clock pulse, the ﬂipﬂop will be set if its D input is 1 and the ﬂipﬂop will be reset if its D input is 0. Therefore, all four bits will be stored simultaneously in the register. When the mode control line is HIGH or SHIFT is active high and a clock pulse is applied, the data can be shifted right from one ﬂipﬂop to the next ﬂipﬂop. Figure 8.23 shows the logic symbol of four Fig. 8.23 Logic symbol of 4bit Parallel In –Serial Out shift register bit parallel in serial out shift register.
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Digital Electronics: Principles and Applications
Figure. 8.24 shows the waveform of four bit Parallel In  Serial Out shift register. If the data input D0=1, D1=1, D2=0, D3=0; after application of ﬁrst clock pulse the parallel data 1100 are loaded into the register and data output Q3 is 0. When the second clock pulse is applied, data shifted right means Q0 shifted to Q1, Q1 shifted Fig. 8.24 Waveform of PISO shift register to Q2, and Q2 shifted to Q3. On the application of third clock pulse Q1 data appears on Q3 and on the fourth clock pulse, Q0 data appears on Q3. Therefore, all four bits will be shifted out sequentially. Example 8.3
Draw the timing diagram of data output of a four bit shift register with parallel input data 1011.
� Solution ——— When SHIFT/LOAD is low and clock pulse is applied, the parallel data 1011 are loaded into register. The output at Q3 is 1. On the second clock pulse, the data ‘1’ at Q2 is shifted into Q3. At third clock pulse, the ‘0’ is shifted into Q3. When the fourth clock pulse is applied, the output at Q3 is 1. Figure 8.25 (b) shows the timing diagram of PISO shift register.
Fig. 8.25
8.11
(a) Block diagram of PISO shift register and (b) Timing diagram of PISO shift register
BUFFER REGISTER
Generally, these registers are known as Tristate Buffer Registers. In microprocessor system, the data transfer with in the system takes place over a common set of interconnecting lines which is known as data bus. As different devices may be connected to the single data bus, those devices need to be connected through tristate buffers. Therefore, bus organisation systems of microprocessor require a tristate buffers which operate on tristate logic such as low, high and high impedance state or highZstate. IC 74374 is an 8 bit tristate buffer register which consists of D ﬂipﬂops and tristate gates. Figure 8.26 shows the logic diagram of 8 bit buffer register IC 74374. The pin diagram representation of IC 74374 is also shown in Fig. 8.26. The data inputs are 1D, 2D… 8D and data outputs are 1Q 2Q …8Q. Buffer register operates just like a PIPO register. When data inputs are given to D ﬂipﬂops and clock is applied, input data will be loaded to ﬂipﬂops and available at output of the ﬂipﬂops but not available
Sequential Circuits
311
Fig. 8.26 Pin diagram and logic diagram of 8 bit tristate buffer register IC 74374
at output bus as output bus is in highZ state. Whenever the output is required, output enable (OE) signal makes low and the ﬂipﬂops output available at the output terminals.
8.12 UNIVERSAL SHIFT REGISTER The 4bit universal shift registers features are parallel and serial inputs, parallel outputs, mode control, and two clock inputs. These registers operate in different modes, namely serial inputs, parallel load, shift right, and shift left. Pin diagram and logic symbol of 4bit universal shift register IC 7495A are depicted in Fig. 8.27(a) and (b) respectively. Logic diagram of IC 7495A is illustrated in Fig. 8.28. The mode control signal controls the serial and parallel inputs. Applying the four bits of data and taking the mode control input high, we can achieve Fig. 8.27 Pin diagram and logic symbol of 7495A parallel loading. Then the data is loaded into
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Digital Electronics: Principles and Applications
Fig. 8.28
Logic diagram of 7495A
the associated ﬂipﬂops and appears at the outputs after the high to low transition of the clock2 input. During parallel loading, the entry of serial data is inhibited. When mode control is low, data is serially entered into shift register. Shift right takes place on the high to low transition of clock1 when the mode control is low; shift left takes place on the high to low transition of clock2 when the mode control is high by connecting the output of each ﬂipﬂop to the parallel input of the previous ﬂipﬂop. The functional table of 7495A is given in Table 8.2. Table 8.2
Functional Table of 7495A
Inputs Clocks Mode control Serial 2(L) 1(R ) H H H L L L ↑ ↓ ↓ ↑ ↑
H ↓ ↓ L X X L L L H H
x x x H ↓ ↓ L L H L H
x x x x H L x x x x x
Outputs A x a QB↑ x x x x x x x x
Parallel B C
D
QA
QB
QC
QD
x b QC↑ x x x x x x x x
x d d x x x x x x x x
QA0 a QBn QA0 H L QA0 QA0 QA0 QA0 QA0
QB0 b QCn QB0 QAn QAn QB0 QB0 QB0 QB0 QB0
QC0 c QDn QC0 QCn QCn QC0 QC0 QC0 QC0 QC0
QD0 d d QD0 QCn QCn QD0 QD0 QD0 QD0 QD0
x c QD↑ x x x x x x x x
↑ shifting left requires external connection of QB to A, QC to B and QD to C. Serial data is entered at input D. H = High level, L =Low level, x = irrelevant ↓ = transition from high to low level, ↑ = transition from low to high level a,b,c,d = the level of steady state input at inputs A, B, C, or D, respectively. QA0, QB0, QC0, QD0 = the level of QA, QB, QC or QD respectively, before the indicated steady state input conditions were established.QAn, QBn, QCn, QDn = the level of QA, QB, QC or QD respectively, before the most recent transition of the clock.
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Sequential Circuits
Fig. 8.29
Pin diagram and logic symbol of 74194
The IC 74194 is a 4bit bidirectional universal shift register and it has shiftleft and shiftright capability, synchronous parallel and serial data transfer, asynchronous master reset and can easily expand for both serial and parallel operation. Pin diagram and logic symbol of IC 74194 are depicted in Fig.8.29 (a) and (b) respectively. The functional characteristics are indicated in the logic diagram as shown in Fig.8.30 and function table as illustrated in Table 8.3. The registers are fully synchronous. The synchronous operation of the IC is determined by the mode select inputs (S0, S1). It is clear from the mode select table that data can be entered and shifted from left to right (Q0 → Q1→ Q2, etc.) or, right to left (Q3→ Q2→ Q1, etc.) or parallel data can be entered, loading all 4 bits of the register simultaneously.
When both S0 and S1 are LOW, existing data is retained in a hold mode. The ﬁrst and last stages provide Dtype serial data inputs (DSR, DSL) to allow multistage shift right or shift left data transfers without interfering with parallel load operation. Mode select and data inputs are edgetriggered and operate in the LOWtoHIGH transition of the clock pulse. The four bit parallel data inputs D0 to D3 are Dtype inputs. When S0 and S1 are high, data D0 Fig. 8.30 Logic diagram of 74194 to D3 will be transferred to the Q0 to Q3 outputs respectively after the transition of the clock from LOWtoHIGH. Figure 8.31 shows the timing sequences of clear, clearload, shiftright, shiftleft, inhibit and clear operation of 74194. Table 8.3
Operating Modes Reset Hold Shift left Shift right Parallel load
—R – CP M x x ↑ ↑ ↑ ↑ ↑
L H H H H H H
Functional table of IC 74194
S1 x l h h l l h
Inputs S0 DSR DSL x l l l h h h
x x x x l h x
x x l h x x x
Dn
Q0
x x x x x x dn
L q0 q1 q1 L H d0
Outputs Q1 Q2 L q1 q2 q2 q0 q0 d1
L q2 q3 q3 q1 q1 d2
Q3 L q3 L H q2 q2 d3
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Digital Electronics: Principles and Applications
H = High voltage level, h = High voltage level one setup time prior to the low to high CP transition L = low voltage level, l = Low voltage level one setup time prior to the low to high CP transition q, d = lower case letters indicate the state of the referenced input one setup time prior to the low to high CP transition x=don’t care , ↑ = Low to high clock pulse transition
Fig. 8.31
8.13
Timing sequences of clear, clearload, shiftright, shiftleft, inhibit and clear of 74194
UNIVERSAL SHIFT REGISTER USING MUX
A universal shift register using multiplexer is shown in Fig. 8.32. It has the capability of shift left, shift right, load and hold. It consists of D ﬂipﬂops and 4:1 multiplexers. The multiplexer is used to select mode of operation such as hold, shift left, shift right and load. The multiplexer has two common selection variables S0 and S1. When S1=0 and S0=0, hold is selected. L is selected when S1=0 and S0=1, R is selected when S1=1 and S0=0. The Load operation is performed when S1=1 and S0=1. The mode of operation of the universal register with respect to mode inputs Fig. 8.32 Two bit universal shift register using 4:1MUX is given in Table 8.4.
Sequential Circuits Table 8.4
Activity
Mode S1 S0
Hold Shift left Shift right Load
0 0 1 1
Clock
Mux gate
↑ ↑ ↑ ↑
Hold L R Load
0 1 0 1
Actually, the mode select inputs S1 and S0 select shift left, shift right, and load with enabling multiplexer gates L, R, and Load respectively. This register has tristate outputs. The tristate buffers must be disabled by S1=1 S0=1 to ﬂoat the I/O bus for use as inputs. A bus is a collection of similar signals. The inputs are applied to A, and B through pins QA and QB, and routed to the Load gate in the multiplexers, and on the D inputs of the FFs. Data is parallel load on application of a clock pulse.
Fig. 8.33 Logical symbol of IC 7491 8 bit shift register Table 8.5
S1
—— —— S0 OE2 OE1
x x 0 0 1 1
x x 0 1 0 1
x 1 0 0 0 x
1 x 0 0 0 x
Tristate gate Disable Disable Enable Enable Enable Disable
315
When S1=0 S0=0, the hold gate enables a path from the Q output of the ﬂipﬂop back to the hold gate, to the D input of the same ﬂipﬂop. As a result, the output is continuously reloaded with each new clock pulse when S1=0, S0=0. In this way, data is hold.
To read data from outputs QA and QB, the tri—E2 — = 0, O —E1 — =0 state buffers must be enabled by O and mode S1 S0 = 00, or S1 S0 = 01, or S1 S0 = 10. So that mode is anything except load for data output as shown in Table 8.5. For right shifting operation of data, shift right (SR) input signal is used. Any data shifted out to the right from stage QA to QB via QA and QB. This output is unaffected by the tristate buffers. The shift right sequence for S1 S0 = 10 is: SR → QA → QB
Similarly, the left shift operation of data is possible with shift left (SL) input signal. Any data shifted out to the left from stage QB to QA via QB and QA. This is also unaffected by the tristate buffers. The shift left sequence for S1 S0 = 01 is: SL → QB → QA —E2 — or O —E1 —. During Shifting of data may take place with the tristate buffers disabled by one of O shifting operation, the register contents outputs will not be accessible. The IC 74ALS299 is universal shift register with tristate outputs which is commonly used in digital systems.
8.14 APPLICATIONS OF SHIFT REGISTERS Shift registers can be found in many applications. The list of shift register applications are as follows: Timing circuits to produce time delay, Shift register counters: Ring counter and Johnson counter, Serial to parallel converters, Parallel to serial converters, Sequence generators
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Digital Electronics: Principles and Applications
In this section, time delay generation, Ring counter, Johnson counter and Serial to parallel converters are explained.
8.14.1
Time Delay
The Serial InSerial Out shift register can be used to produce time delay as shown in Fig. 8.33. The number of stages in the register and the clock frequency can control the amount of time delay. If a data ‘1’ is applied to A and B terminals of eight bit register IC 7491 for clock pulse duration, it appears on the output of ﬁrst stage after applying triggering pulse. Then this data can be shifted from one stage to other on the each positive edge triggering of clock pulse. Therefore, after the eighth clock pulse, data will appears on output as depicted in Fig. Fig. 8.34 Waveform of shift registers as time delay 8.34. If the clock frequency is 1 KHz, one cycle time is 1ms. Consequently, 8ms time delay can be generated by this circuit.
8.14.2
Shift Register Counters
Two of the most common types of shift register counters are introduced here: the Ring counter and the Johnson counter. They are basically shift registers with the serial outputs connected back to the serial inputs in order to produce particular sequences. These registers are classiﬁed as counters because they exhibit a speciﬁed sequence of states.
Ring Counters A Ring counter is a circulating shift register in which the output of the most signiﬁcant stage is fed back to the input of the least signiﬁcant stage. The 4bit ring counter can be constructed using D ﬂipﬂops as shown in Fig. 8.35. The sequence table of ring counter is given in Table 8.6. It is clear from this table that the output of each stage is shifted into the next stage on the positive Fig. 8.35 Ring counter edge of a clock pulse. Initially, FF0 is set and all other ﬂipﬂops, FF1, FF2 and FF3, are reset. Therefore, Q0 is 1 and Q1, Q2, and Q3 are 0. After application of clock pulse, output Q0 will be shifted to Q1 and Q1 will Table 8.6 Counting sequence of be 1. Similarly, just after the clock pulse2, output Q2 will be 1 and 4bit Ring counter Q3 will be 1 after third clock Clock Q0 Q1 Q2 Q3 pulse. The waveform of four 0 1 0 0 0 bit Ring counter is shown in 1 0 1 0 0 Fig. 8.36. 2 0 0 1 0 As the count sequence has 3 0 0 0 1 4 different states, the counter can be considered as a mod4 counter. The Ring counter utilizes Fig. 8.36 Timing diagram of ring counter only four of the maximum sixteen states; therefore, Ring counters
317
Sequential Circuits
are very inefﬁcient in terms of state usage. But the most advantage of a Ring counter over a binary counter is that it is selfdecoding.
Johnson Counters
In a Johnson counter, inverted output of the last stage ﬂopﬂop is fed back to the input of the ﬁrst stage ﬂipﬂop. Then a unique sequence is Table 8.7 Counting sequence of generated due to feedback. Table 8.7 shows the sequence table 4bit Johnson counter of four bit Johnson counter. A four bit Johnson counter has eight Clock Q0 Q1 Q2 Q3 0 1 2 3 4 5 6 7
0 1 1 1 1 0 0 0
0 0 1 1 1 1 0 0
0 0 0 1 1 1 1 0
0 0 0 0 1 1 1 1 Fig. 8.37 Four bit Johnson counter
counting sequence and ﬁve bit Johnson counter has ten counting sequence. Therefore ‘n’ bit/stage Johnson counter should have a count sequence of length ‘2n’ and it may be called as mod2n counter. These counters are also known as twisted ring counters. Figure 8.37 shows the circuit diagram of a four bit Johnson counter. The timing diagram of four bit Johnson counter is depicted in Fig. 8.38 Fig. 8.38 Waveform of four bit Johnson counter The disadvantage of this counter is that the maximum available states are not fully utilized and only eight states out of the sixteen states are being used.
8.14.3
Serial Data to Parallel Data Conversion
Serial data transmission is commonly used to transmit data one digital system to other through single line. If parallel data transmission is used, eight lines are required for this. The microprocessor or computerbased systems require parallel data. When these systems communicate with external devices, then these devices send or receive serial data. Therefore, the commonly required incoming data to be converted into parallel format. Therefore, serialtoparallel conversion is required. A Serial In  Parallel Out shift register can be used in serialtoparallel conversion. Example 8.4
Draw the logic circuit and waveform of 5 bit Ring counter
�
Fig. 8.39
Five bit Ring counter
Solution
The logic circuit diagram of 5 bit ring counter is shown in Fig. 8.39 and its timing diagram is depicted in Fig. 8.40. Initially, ﬁrst D ﬂipﬂop FF0 is reset and rest of the ﬂipﬂops are cleared. So Q0 is 1 and Q1=Q2=Q3=Q4=0 after
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Digital Electronics: Principles and Applications
the ﬁrst clock pulse. When the second clock pulse is applied, Q1 becomes 1 and outputs of other ﬂipﬂops are 0. On the application of third clock pulse, Q2 is 1 and Q0=Q1=Q3=Q4=0. Similarly, Q3=1 when fourth clock pulse is applied and Q0=Q1=Q2=Q4=0. So that we can verify that ‘1’ is always retained in the counter but simply shifting around the ring after application Fig. 8.40 Timing diagram ﬁvebit Ring counter of each clock pulse.
8.15
COUNTER
When a group of ﬂipﬂops are connected in cascade, the counting operation is performed. Then, this sequential circuit is most commonly used for counting purpose, and this circuit is called as counter. The counter is also a memory system as any counter circuit must remember its past states and it possesses data in memory. In this chapter, the connections of ﬂipﬂops to make any type of counter and their operations have been explained. Counters are mostly used in digital computers, digital telephone and digital instruments. A number of ﬂipﬂops are required for different asynchronous and synchronous counters, divide by ‘n’ counters, and their connection diagram and the numbers of sequential states are explained. The design of synchronous counters, cascade counters and selfstarting and selfcorrecting counters are also discussed in this chapter.
8.16
CLASSIFICATION OF COUNTER
There are several types of counters, which are able to count binary numbers. Counters can be classiﬁed based on application of clock, number of ﬂipﬂops (stages) and sequential states. According to application of clock to ﬂipﬂops, counter is divided into two broad categories namely asynchronous and synchronous counters. As per number of ﬂipﬂops (stages) counters are 2 bit, 3 bit, 4 bit and n bit. Counters can also be used as count up or count down based on sequential states. Asynchronous (Ripple) Counters In asynchronous counter, the external clock pulse clocks the ﬁrst ﬂipﬂop. Then, the output of ﬁrst ﬂipﬂop (Q or Q–) is connected as clock of the next ﬂipﬂop. – Similarly, each successive ﬂipﬂop is clocked by the Q or Q of the previous one. All ﬂipﬂops do not change states in exact synchronism with the applied clock pulses. There is some propagation delay between responses of successive ﬂipﬂops. The asynchronous counter is also called as ripple counter due to the way of ﬂipﬂop response one after another in a kind of rippling effect. The maximum clock frequency of an asynchronous counter decreases with the increase of number of ﬂipﬂops or bits. Asynchronous counter can generate glitches in decoding gates due to propagation delays. Therefore, strobing technique should be used for eliminating the effects of glitches.
Synchronous Counters In synchronous counter, the clock input terminals of all ﬂipﬂops are commonly connected. Therefore, the same clock pulse simultaneously triggers all ﬂipﬂops of the counters and the problem caused by the ﬂipﬂop propagation delay has been eliminated in these counters. For a synchronous counter, the maximum frequency remains same, regardless of the number of bits. Count Down Counter Synchronous and asynchronous counters are able to count either in increasing or decreasing order. In count down counter, the counter value sequentially decreases. In a three stage down counter, the counting sequence is 7, 6, 5, 4, 3, 2, 1, and 0. This counter can be made by JK or T or D ﬂipﬂops. Count Up Counter In count up counter, the counter value sequentially increases. The counting sequence of threestage counter is 0, 1, 2, 3, 4, 5, 6, and 7. This counter can also be designed by JK or T or D ﬂipﬂops.
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319
8.17 ASYNCHRONOUS (RIPPLE) COUNTERS The sequence of binary counter follows a dividebytwo pattern. This means that the frequency for each bit, from least signiﬁcant bit (LSB) to most signiﬁcant bit (MSB), follows a dividebytwo pattern. Therefore, the LSB is half of the clock frequency and the highest frequency among all stages. The frequency of the next bit is onehalf the LSB’s frequency. The counter circuit can be designed using T ﬂipﬂops or JK ﬂipﬂops when operate in the toggle mode to count in a binary sequence.
8.17.1
Fig. 8.41 One bit asynchronous counter
Fig. 8.42
8.17.2
1 bit Ripple Counter
One bit ripple counter using JK ﬂipﬂops is shown in Fig. 8.41. When J and K inputs are made high, JK ﬂipﬂop is operating in toggle mode. As a result, after each positive edge clock pulse, output of ﬂip ﬂop is changed. Here, the signal A is clock pulse and B represents the output of JK ﬂipﬂop. The count sequence is from 0 to 1 and 1 to 0. Timing diagram of one bit asynchronous counter is depicted in Fig. 8.42.
Timing diagram of one bit asynchronous counter
2bit Ripple Up Counter
A twobit asynchronous counter is shown in Fig. 8.43. Usually, all the CLEAR inputs are connected together, so that a single pulse can clear all the ﬂipﬂops before counting starts. The external clock is connected to the clock input of the ﬁrst ﬂipﬂop (FF0) only. So, FF0 changes state at the negative edge of each clock pulse, but FF1 changes only when triggered by the falling edge of the Q output of FF0. Due to propagation delay the transition of the input clock pulse and a Fig. 8.43 2bit ripple counter transition of the Q output of FF0 can never occur at exactly the same time. Therefore, all ﬂipﬂops cannot be triggered simultaneously and an asynchronous operation is performed. The transitions of CLK, Q0, and Q1 are shown in the timing diagram as shown in Fig. 8.44. Truly, there is some small delay between the CLK, Q0 and Q1 transitions. The 2bit ripple cou Table 8.8 State sequence for 2bit Fig. 8.44 Timing diagram of 2bit ripple up counter Binary up counter nter circuit has four different states as depicted in Table 8.8. The relationship between Clock pulse Q1 Q0 number of bits (ﬂipﬂops) and number of states is that a coun0 0 0 ter with n ﬂipﬂops can have 2n states. The number of states 1 0 1 in a counter is known as its modulo number or mod number. 2 1 0 3 1 1 Accordingly, a 2bit counter is a mod4 counter. The timing
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diagram of two bit asynchronous counter is illustrated in Fig. 8.44 and state transition diagram of 2bit counter is depicted in Fig. 8.45.
8.17.3
Fig. 8.45
2bit Ripple Down Counter
State transition diagram of 2bit upcounter binary
A twobit ripple down counter is shown in Fig. 8.46. The external clock is applied to the clock input of the ﬂipﬂop, FF0 only. The output of FF0 is used as clock of FF1. In count down counter, outputs Q0 and Q1 are taken from complement output of FF0 and FF1 respectively. Timing diagram of twobit ripple down counter is depicted in Fig. 8.47. The state sequence of counting is 3, 2, 1, and 0 is given in Table 8.9. Figure 8.48 shows the state transition of 2bit ripple down counter.
Fig. 8.47
Timing own counter diagram 2bit ripple Table 8.9
8.17.4
Fig. 8.48
State transition diagram of 2bit binary down counter
State sequence for 2bit ripple down counter
Clock pulse
Q1
Q0
0 1 2 3
1 1 0 0
1 0 1 0
3bit Ripple Up Counter
Figure 8.49 shows the 3bit ripple counter, which is implemented using three JK ﬂipﬂops. The counter is capable to count up to 23=8. This counter is also called as module 8 or divide by 8 counters. The truth table of 3bit counter is given in Table 8.10. When the clock pulse is applied to the counter, the counter value Fig. 8.49 3bit ripple up counter sequentially increases state by state and the output of ﬂipﬂops indicates the count of pulses in counter. Waveform of threebit binary ripple counter is shown in Fig. 8.50. At the positive edge of the ﬁrst clock pulse, ﬂipﬂop FF0 sets and the output Q0 becomes 1 and this output does not affect on the output of FF1. So the counter output will be updated to 001 Fig. 8.50 Timing of 3bit ripple up from 000 as shown in row 2 of Table 8.10. When the second counter
Sequential Circuits
321
clock pulse, is applied, ﬂipﬂop FF0 is reset and the output of FF0 changes from 1 to 0. After the second clock pulse, ﬂipﬂop FF1 is set and the output of FF1 changes from 0 to 1. Then counter output State Q2 Q1 Q0 will be 010 as depicted in third row. When the third clock pulse is 0 0 0 0 applied, FF0 ﬂipﬂop sets and output becomes 1. At this time, the 1 0 0 1 2 0 1 0 state of FF1 and FF2 do not change. At that moment, the output of 3 0 1 1 the counter is 011. If the fourth clock pulse is applied, ﬂipﬂop FF0 4 1 0 0 resets and the output of FF0 changes from 1 to 0. In this time ﬂip5 1 0 1 ﬂop FF1 resets and the output of FF1, Q1 will be 0, which changes 6 1 1 0 the ﬂipﬂop FF2 to 1. 7 1 1 1 As soon as the ﬁfth clock pulse given in FF0, the said ﬂipﬂop sets and output Q0 becomes 1, while the output of ﬂipﬂop FF1 and FF2 are not affected. After ﬁfth pulse, the counter output is 101. In the next pulse, ﬂipﬂop FF0 resets and ﬂipﬂop FF1 and FF2 are set. During the 7th pulse, all ﬂipﬂops, FF0, FF1, and FF2, are set and the counter output will be 111. When the eighth pulse is applied, all ﬂipﬂops are reset and then counter output is 000. In this way, the counter counts 0 to 7 sequentially.
Table 8.10
8.17.5
Truth table of 3bit ripple up counter
3bit Ripple Down Counter
Figure 8.51 shows the circuit diagram of 3bit down counter. In up counter, the output Q0, Q1 and Q2 are taken from output Q of ﬂipﬂops FF0, FF1, and FF2 respectively, – but in down counter, the complement output Q of ﬂipﬂop FF0, FF1, and FF2 are connected to Q0, Q1 and Q2. Truth table of 3bit ripple down counter is shown in Table 8.11. Initially, consider that all ﬂipﬂops are reset and the counter output will be 111. As soon as the ﬁrst clock pulse is applied to the ﬂipﬂop FF0, it will be set. The complement output of Fig. 8.51 3bit ripple down counter FF0 is 0. The output of FF1 will be 0 and it complement is 1. The output of FF2 will also be 0 and its complement is 1. Table 8.11 Truth table of 3bit ripple Therefore, the counter output is 110. down counter After application of second clock pulse, FF0 ﬂipﬂop will State Q 2 Q1 Q 0 be reset. The complement output of FF0 is 1, which affects the 0 1 1 1 FF1ﬂipﬂop. So the counter output is 101. Similarly, it is de1 1 1 0 picted from table that the counter sequentially decreases one 2 1 0 1 by one after applying each clock pulse. After applying sixth 3 1 0 0 clock pulse counter value is 001 and at the end of seventh 4 0 1 1 clock pulse the 5 0 1 0 6 0 0 1 output of coun7 0 0 0 ter is 000. Figure 8.52 shows the waveform of 3bit ripple down counter.
8.17.6
4bit Ripple Up Counter
Figure 8.53 shows the circuit diagram of 4bit ripple up Fig. 8.52 Timing diagram of 3bit ripple down counter counter, which is made by four JK ﬂipﬂops. Truth table
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Digital Electronics: Principles and Applications
Fig. 8.53
Fig. 8.54
4 bit ripple up counter
Fig. 8.55
Waveform of 4bit ripple up counter Table 8.12
8.17.7
of 4bit ripple up counter is depicted in Table 8.12. This counter counts sequentially from 0000 to 1111 like three bit ripple up counter. The state transition diagram is given in Fig. 8.54. Figure 8.55 shows the waveform of 4bit ripple up counter. It can be viewed that the output of each ﬂipﬂop divides the input clock frequency by 2.
State transition diagram of 4bit ripple up counter
Truth table of 4bit ripple up counter
State
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
4bit Ripple Down Counter
Figure 8.56 shows the circuit diagram of 4bit ripple down counter, which is made by four JK ﬂipﬂops. Truth table of 4bit down counter is depicted in Table 8.13. This counter counts sequentially from 1111 to 0000. The state transition diagram is given in Figure 8.57. Figure 8.58 shows the waveform of 4bit ripple down counter.
Fig. 8.56 4bit ripple down counter
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Sequential Circuits Table 8.13
Fig. 8.57
State transition of 4bit ripple down counter
Fig. 8.58
Timing diagram of 4bit ripple down counter
Truth table of 4bit ripple down counter
State
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
8.18 ASYNCHRONOUS DECADE COUNTERS The n bit binary counter has two to the power n states. But counter with states less than the number, 2n is also possible. The counter is designed with ﬂipﬂops and logical gates to have the number of states in sequences. This sequence is called as truncated sequences. These sequences can be achieved by using logic gates, which can force the counter to recycle from any count value. A decade counter has ten truncated sequences. As there are ten states from 0 to 9, four ﬂipﬂops are required for decade counter. An implementation of a decade counter is Fig. 8.59 Decade counter shown in Fig. 8.59. Once the counter counts to ten (1010), all four ﬂipﬂops will Table 8.14 The sequence of the be cleared. Therefore, Q1 and Q3 are used to decode the count decade counter of ten. Table 8.14 shows the truth table of decade counter. As State Q3 Q2 Q1 Q0 the decade counter has ten states, it is also called as MOD10 0 0 0 0 0 counter. This counter can be used to divide the external clock 1 0 0 0 1 input frequency by ten and the output will be available after every 2 0 0 1 0 tenclock pulses. State transition of decade counter is depicted in 3 0 0 1 1 4 0 1 0 0 Fig. 8.60. Recycling of decade counter after counting 9 is possible 5 0 1 0 1 to decode count value (10)10 or (1010)2 using an AND gate and 6 0 1 1 0 the AND gate output is connected with the clear (CLR) inputs of 7 0 1 1 1 the ﬂipﬂops. Therefore, all ﬂipﬂops are reset and the counter 8 1 0 0 0 state becomes 0000. Figure 8.61 shows the timing diagram of 9 1 0 0 1 asynchronous decade counter.
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Digital Electronics: Principles and Applications
It is depicted in Fig. 8.61 that there is a glitch on the output waveform of Q1. Before decoding the count value (10)10 or (1010)2, Q1 must be high ﬁrst. The counter should stay at count 10 state for several nanoseconds as the decoding gate requires several nanoseconds propagation delay to generate output F. Therefore, the counter should be in 1010 state for a very short time before return back to 0000 state. In this way, the glitch is generated on Q1 waveform. Fig. 8.60 State transition of decade counter
Fig. 8.61
8.19
Timing diagram of decade counter
Fig. 8.62
Simultaneous updown counter
SIMULTANEOUS UPDOWN COUNTER
Figure 8.62 shows a 4bit simultaneous updown counter. When output is taken from Q3, Q2, Q1 and Q0, it generates a upcounting sequence. If output is taken from Q–3, Q–2, Q–1 and Q–0, it behaves as a downcounting sequence. In this way the same circuit has the capabilities to operate either up or down counter – when outputs taken from Q and Q. Waveforms of four bit updown counter are depicted in Fig. 8.63 (a) and (b) respectively.
Fig. 8.63
8.20
(a) Wave form of four bit up counter and (b) Waveform of four bit down counter
ASYNCHRONOUS UPDOWN COUNTERS
In certain applications, a counter must be able to count both up and down. Fig. 8.64 shows the 3bit updown counter. It counts up or down depending on the status of the control signals UP and DOWN. When the UP input is at 1 and the DOWN input is at 0, the NAND network between FF0 and FF1 will gate the noninverted output (Q) of FF0 into the clock input of FF1. Similarly, Q of FF1 will be gated through the
325
Sequential Circuits
Fig. 8.64
3bit asynchronous UPDOWN counter
other NAND network into the clock input of FF2. Thus, the counter will count in UP direction. The functional table of 3bit up counter is shown in Table 8.15. Table 8.15 Functional table of up counter When the control input UP is at 0 and DOWN is at 1, UP Down State FF2 FF1 FF0 the inverted outputs of FF0 and FF1 are gated into the 1 0 0 0 0 0 clock inputs of FF1 and FF2 respectively. If the ﬂipﬂops 1 0 1 0 0 1 are initially reset to 0’s, then the counter will go through 1 0 2 0 1 0 the following sequence as given in Table 8.16 when 1 0 3 0 1 1 clock pulses are applied. Then the counter behaves as 1 0 4 1 0 0 DOWN counter. An asynchronous updown counter is 1 0 5 1 0 1 slower than an up counter or a down counter because 1 0 6 1 1 0 1 0 7 1 1 1 of the additional propagation delay introduced by the NAND networks. Table 8.16
Functional table of down counting
UP
Down
State
FF2
FF1
FF0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 1 2 3 4 5 6 7
0 1 1 1 1 0 0 0
0 1 1 0 0 1 1 0
0 1 0 1 0 1 0 1
8.21 PROPAGATION DELAY IN ASYNCHRONOUS COUNTER The operations of asynchronous counters have been discussed in previous sections. The main disadvantage of these counters is that they are slow. Asynchronous counters are not very useful at very high frequencies, particularly for large number of bits. In these counters, each ﬂipﬂop is triggered by the transition of the output of the preceding ﬂipﬂop. Due to the inherent propagation delay time tpd, the ﬁrst ﬂipﬂop output, Q0 will be available after a period of propagation delay tpd when clock pulse is applied as shown in Fig. 8.65. The second ﬂipﬂop responds after 2 tpd. If the counter consists of ‘n’ ﬂipﬂops, then nth ﬂipﬂop changes state after n tpd time delay from the input clock pulse. Therefore, the proper operation of nbit counter, the time period of clock signal should be greater than n tpd.
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Digital Electronics: Principles and Applications
So Tclock > n tpd where, Tclock is the time period of clock, n is the number of bits or stages and tpd is propagation delay. Then the clock frequency of asynchronous counters for reliable operation is 1 1 > n · t pd or > f clock . Therefore, f clock n · t pd 1 . So the maximum frequency is f max = n · t pd the maximum clock frequency for an asynchronous counter fmax decreases as number of bits increases. For example, in a four stage asynchronous of a 3bit asynchronous counter counter, the propagation delay of each ﬂip Fig. 8.65 Waveform with propagation delay tpd=50 ns ﬂop is 50ns, then the maximum frequency at which the counter operate properly is 1 1 f max = = = 5 MHz. n · t pd 4 · 50ns
8.22 ASYNCHRONOUS COUNTER ICS The operation of asynchronous counters using their proper circuits and waveforms have been explained in previous section. These counters are designed using ﬂipﬂops. Now a days, some asynchronous counters are available in MSI ICs as shown in Table 8.17. Depending upon the features of counters, ICs are divided into three different groups A, B and C. All these ICs consist of four master slave ﬂipﬂops and the set, rest and load operations are independent of clock pulse or asynchronous. Before use any counter ICs, designer should study the manufacturer data sheet of ICs. Table 8.17 Asynchronous counter ICs
Example 8.5
IC Numbers
Description
Features
Group
7490, 74290 7492 7493, 74293 74176, 74196 74177, 74197 74390 74393 74490
BCD counter Divide by 12 counter 4 bit binary counter Presettable BCD counter Presettable 4bit binary counter Dual decade counters Dual 4 bit binary counter Dual BCD counters
Set, reset Reset Reset Reset, Load Reset, Load Reset Reset Set, reset
A B B C C B B A
Each ﬂipﬂop of a 3bit asynchronous counter is positive edge triggered and has a propagation delay of 10µs. Draw the timing diagram of the counter and determine the delay time of Q2 after 4th clock pulse.
Sequential Circuits �
327
Solution
Fig. 8.66
3 bit asynchronous counter
Figure 8.66 shows the positive edge triggered 3bit asynchronous counter and it has propagation delay of 10µs. Figure 8.67 shows the timing diagram of this counter. The output Q0 has 10µs delay from clock input and output Q1 has – delay 10µs from Q0 and 20 µs from clock. The output Q2 has – also 10µs delay from Q1. Therefore Q2 has 30µs delay from clock.
Fig. 8.67 Timing diagram of asynchronous counter
Example 8.6 �
How a 4bit asynchronous counter can count 0000 to 1100?
Solution Figure 8.68 shows the 4bit asynchronous counter to count 0000 to 1100 and its timing diagram is depicted in Fig. 8.69. When the counter has reached 1100, the output of AND gate reset all ﬂipﬂops. Therefore, the counter again starts counting from 0000. Fig. 8.68
4bit asynchronous counter to count 0000 to 1100
Fig. 8.69 Timing diagram of asynchronous counter to count 0000 to 1100
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Digital Electronics: Principles and Applications
8.23 SYNCHRONOUS COUNTERS The synchronous counter is clocked in such way that all ﬂipﬂops in the counter are triggered simultaneously and all output bits also change state simultaneously. This operation can be performed when the clock is connected to clock input of all ﬂipﬂops so that all ﬂipﬂops receive the same clock pulse at the same time. Figure 8.70 shows that clock inputs of four ﬂipﬂops Fig. 8.70 Four ﬂipﬂops with same clock signal are connected together and both JK inputs are high. Therefore JK ﬂipﬂops operate in toggle mode and the dividebytwo frequency pattern can be obtained from the output of each ﬂipﬂop. So this circuit cannot function as a counter. To achieve binary sequence, JK inputs of ﬂipﬂops will be connected to previous stage output directly or with some special arrangement. In this section, the 2bit, 3bit and 4bit synchronous counters are explained with circuit diagrams and timing diagrams.
8.23.1
2bit Synchronous Counter
Figure 8.71 shows the circuit diagram of two bit synchronous counter. The operation of two bit counter is given below: Initially, both ﬂipﬂops are in reset condition and the counter is in the binary 0 state. Therefore, the counter output is 00. At the positive edge of the ﬁrst clock pulse, FF0 operates in toggle mode and Q0, output of FF0 is high or 1. But at the positive edge of ﬁrst clock pulse CLK1, J and K are both low as Q0 is connected with J and K inputs of FF1. As a Fig. 8.71 Two bit synchronous counter result J=0 and K=0 and there is no change in output of FF1. Hence the output of counter is 01 after CLK1. At the second clock pulse (CLK2), both FF0 and FF1 operate in toggle mode as J and K inputs of ﬂipﬂops are high. After the positive triggering edge of CLK2, Q0=0 and Q1=1 and the output of counter is 10. At the leading edge of CLK3, FF0 will operate in toggle mode and FF1 remains Fig. 8.72 Timing diagram of 2bit set, as its J and K inputs are low. Therefore after the third synchronous counter clock pulse, counter output Q0=1 and Q1=1. In the forth clock pulse, again both FF0 and FF1 are in toggle condition. After the leading edge of forth clock pulse CLK4, Q0=0 and Q1=0. The timing diagram of 2bit synchronous counter is shown in Fig. 8.72.
8.23.2
3bit Synchronous Counter
Figure 8.73 shows a three bit synchronous counter. In this counter, the clock inputs of all three ﬂipﬂops are connected together. Therefore, all the ﬂipﬂops change state simultaneously. The J and K inputs of FF0 are connected to +V. The output of FF0 has connected
Fig. 8.73 Three bit synchronous counter
Sequential Circuits
329
with J and K inputs of FF1. The J and K inputs of FF2 are connected to the output of an AND gate which has two inputs Q0 and Q1. The timing diagram of 3bit synchronous counter is shown in Fig. 8.74. The sequence of states is also depicted in Table 8.18.
Fig. 8.74 Timing diagram of 3 bit synchronous counter Table 8.18
State sequence for 3bit synchronous counter
Clock pulse
Q2
Q1
Q0
0 1 2 3 4 5 6 7
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
J and K inputs of FF0 are always high and this ﬂipﬂop operates in toggle mode. The Q0 output changes on each clock pulse from initial state to ﬁnal state. FF1 will operate in the toggle mode when the output of FF0 is high. At CLK2, CLK4, CLK6 and CLK8, FF1operates in toggle mode and will change state. In CLK1, CLK3, CLK5 and CLK7, Q0 is a 0 and FF1 is in the nochange mode. Therefore, the output of FF1 will remain in its present state. The output FF2 will change when both Q0 and Q1 are high state. This condition is generated by the AND gate and applied to the J and K inputs of FF2.
8.23.3 4 bit Synchronous Counter
Figure 8.75 shows the four bit synchronous counter and all four ﬂipﬂops are connected with a common positive edge triggered clock pulse. Therefore, all ﬂipﬂops will be triggered simultaneously. As J and K inputs of FF0 are connected to high, FF0 ﬂipﬂip will operate in toggle mode on each clock pulse. FF1 ﬂipﬂop toggles when Q0 is high. If Q0 and Q1 are high, FF2 ﬂipﬂop toggles. When Q0, Q1 and Q2 are high, FF3 ﬂipﬂop also operates in toggle mode. The timing diagram of 4bit synchronous counter is depicted in Fig. 8.76 and sequence of state of four bit synchronous counter is given in Table 8.19. Fig. 8.75 Four bit synchronous up counter This counter is implemented with positive edge triggered ﬂipﬂops. The operation of ﬁrst three ﬂipﬂops is same as the threestage counter. The fourth stage, FF3 changes only twice in the sequence. The transitions of FF3 occur only when Q0, Q1 and Q2 are high. This condition is decoded by AND gates as shown in Fig. 8.75.
Fig. 8.76 Timing diagram of 4bit synchronous up counter
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Digital Electronics: Principles and Applications Table 8.19 Truth table of 4bit synchronous up counter
State
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
8.24 SYNCHRONOUS DOWN COUNTER Figure 8.77 shows the four bit synchronous down counter. FF0 toggles on every clock pulse. FF1 ﬂip– ﬂop toggles only if Q 0 is high. FF2 ﬂipﬂop toggles – – only if Q 0 and Q 1 are high. FF3 ﬂipﬂop toggles only – – – if, Q 0, Q 1 and Q 2 are high. The timing diagram of 4 Fig. 8.77 Four bit synchronous down counter bit synchronous counter is depicted in Fig. 8.78.
Fig. 8.78
Timing diagram of 4bit synchronous
8.25 SYNCHRONOUS UPDOWN COUNTERS 8.25.1
3bit Synchronous Updown Counter
Figure 8.79 shows the circuit of a 3bit synchronous updown counter. Similar to an asynchronous updown counter, a synchronous updown counter also has an up  down control input, which is used to control the di Fig. 8.79 Three bit UP/DOWN synchronous down counter counter
Sequential Circuits Table 8.20(a)
1 1 1 1 1 1 1 1 Table 8.20(b)
0 1 2 3 4 5 6 7
8.25.2
Q2
Q1
Q0
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
It is depicted in the sequence table of three bit UP/DOWN synchronous counter that Q0 toggles on every clock pulse for both the UP and DOWN sequences. In the UP counter, Q1 changes state on the next clock pulse when Q0=1. But in the DOWN counting sequence, Q1 changes state on the next clock pulse when Q0=0. Q2 changes state on the next clock pulse when Q0=Q1=1 for the UP sequence. In the DOWN sequence, Q2 changes state on the next clock pulse when Q0=Q1=0. These characteristics can be implemented using AND, OR and NOT logic gates as given in Fig. 8.79.
State sequence for 3bit synchronous binary down counter
——— UP/DOWN Clock pulse 0 0 0 0 0 0 0 0
rection of the counter. State sequence of 3bit synchronous up  down counter is given in Table 8.20 (a) and (b) respectively.
State sequence for 3bit synchronous binary up counter
——— UP/DOWN Clock pulse
0 1 2 3 4 5 6 7
Q2
Q1
Q0
1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
331
4bit Synchronous Updown Counter
——–— Figure 8.80 shows the four bit synchronous updown counter. The UP/DOW N control input is used to enable the counter for counting either upward direction or downward direction with the help of AND – ——–— gates to pass the Q/Q outputs to the succeeding stages of ﬂipﬂops. When the UP/DOW N control line is in high state, the top AND gates become enabled, and the circuit behaves as synchronous up counter. If the UP/ ——–— DOW N control line is “low,” the bottom AND gates become enabled, and the circuit works as synchronous down counter. Fig. 8.80
Four bit synchronous updown counter
8.26 SYNCHRONOUS DECADE COUNTERS The synchronous decade counter counts from 0 to 9 and also operates in a truncated sequence. It does not count 1010 state, but this 1010 state force the counter to back 0000 state. For this, the synchronous decade counter operates in truncated
Fig. 8.81
Synchronous decade counter
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Digital Electronics: Principles and Applications
sequence. Figure 8.81 shows the 4bit synchronous decade counter. State sequence of decade counter is given in Table 8.21. It is very clear form the Table 8.21 that Q0 toggles on each clock pulse. Consequently the logic equation for J and K inputs of FF0 is J=K=1. When Q0=1 and Q3=0, Q1 changes on the next clock pulse every time. So the logic equation for J and K inputs of FF1 is – J=K=Q0 Q3. But Q2 changes on the next clock pulse each time when Q0=Q1=1. The logic expression for J and K inputs of FF2 is J=K=Q0Q1. Q3 changes on the next clock pulse each time when Q0=1 and Q3=1 for count 9 and Q0=Q1=Q2=1 for count 7. Therefore the logic expression for JK inputs of FF3 is J=K=Q0Q1Q2+Q0Q3. These characteristics can be implemented by using AND, and AND and OR logic gates as depicted in Fig. 8.81. The timing diagram of a synchronous decade counter is shown in Fig. 8.82.
8.27
PROPAGATION DELAY IN SYNCHRONOUS COUNTER
Table 8.21
State sequence of a synchronous decade counter
Clock Pulse
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
Fig. 8.82
Timing diagram of synchronous decade counter
The propagation delay of asynchronous counters has been discussed in Section 8.21. The delay time response of a synchronous counter is the time taken by one ﬂipﬂop to toggle and the time for new logic levels to propagate through AND gate to reach the JK inputs of the ﬂipﬂops. The total delay time of a synchronous counter can be expressed as Total delay time = Propagation delay of one ﬂipﬂop (tpd) + propagation delay of AND gate (tg) The propagation delay is always constant and it is independent of the total number of ﬂipﬂops. Usually, it will be much lower than propagation delay in asynchronous counters with the same number of ﬂipﬂops. Hence, the speed of operation of synchronous counters is limited by the propagation delays of AND gates and a single ﬂipﬂop. In a there bit synchronous counter, only one AND gate is used. Therefore, the maximum clock frequency of a there bit synchronous counter for reliable operation is 1 f max = t pd + t g where, tpd is propagation delay and tg is the propagation delay of AND gate. As all three ﬂipﬂops of a there bit synchronous counter are connected to a common clock pulse, glitches can be avoided completely in this counter. A four bit synchronous counter is known as synchronous counter with parallel carry. In this counter, the number of stages is four and the number of AND gates also increases to two along with the number of inputs for the AND gates. This is the disadvantages of this circuit. Then the maximum clock frequency of a four bit synchronous counter for reliable operation is 1 1 = f max = t pd + 2 · t g t pd + (n  2) · t g
333
Sequential Circuits
where, tpd is propagation delay , tg is the propagation delay of AND gate and n is number of stages or bits. For an n bit synchronous counter, the maximum clock frequency can be determined by 1 . f max = t pd + (n  2) · t g For example, in a seven stage synchronous counter, the propagation delay of each ﬂipﬂop is 50ns and propagation delay of AND gate is 10ns, then the maximum clock frequency at which the counter operate properly is 1 1 = f max = = 50MHz as tpd = 50ns , tg =10ns and n =7. t pd + (n  2) · t g 50ns + (7  2)10ns
8.28 SYNCHRONOUS COUNTER ICs The operations of synchronous counters with circuits and waveforms have been explained in previous sections. Generally, these counters are designed using ﬂipﬂops. Presently, some synchronous counters are available in MSI ICs as shown in Table 8.22. Depending upon the features of counters, ICs are divided into four different groups A, B, C and D. All these ICs are positive edge triggered and loading, clearing and change of states take place on the positive edge of input clock pulse. Table 8.22 shows the synchronous counter ICs and designer should study the manufacturer data sheet of counter ICs before application of any counter ICs. Table 8.22
Synchronous counter ICs
IC Numbers
Description
Features
Group
74160 74161 74162 74163 74168 74169 74190 74191 74192 74193
Decade UP counter 4 bit binary UP counter Decade UP counter 4bit binary UP counter Decade UP/Down counter 4bit binary UP counter Decade UP/Down counter 4bit binary UP counter Decade UP/Down counter 4bit binary UP counter
Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear Synchronous preset and asynchronous clear
A A A A B B C C D D
Example 8.7
Figure 8.83 shows the 4bit synchronous counter. Determine the sequence of counter.
� Solution Table 8.23 shows the sequence of counter as illustrated in Fig. 8.83.
Fig. 8.83
4bit synchronous counter
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Digital Electronics: Principles and Applications Table 8.23 Sequence of counter
Fig. 8.84
State
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Waveform of 3bit sequence counters
Example 8.8 The waveform of 3bit synchronous binary UP/DOWN counter is shown in Fig. 8.84. Determine the sequence of counter. � Solution Table 8.24 shows the sequence of 3bit synchronous binary UP/DOWN counters. Table 8.24 State sequence for 3 bit synchronous binary UP/DOWN counters
——— UP/DOWN Clock pulse 1 1 1 1 0 0 0 0 1 1 1 1
0 1 2 3 4 5 6 7 8 9 10 11
Q2
Q1
Q0
0 0 0 1 0 0 0 0 0 0 0 1
0 1 1 0 1 1 0 0 0 1 1 0
1 0 1 0 1 0 1 0 1 0 1 0
Example 8.9 The sequence of 3bit synchronous binary UP/DOWN counter is shown in Table 8.25. Draw the timing diagram of counter. Table 8.25
State sequence for 3 bit synchronous UP/DOWN counter
——— UP/DOWN Clock pulse 1 1 1 1
0 1 2 3
2
0 0 0 1
Q1
Q0
0 1 1 0 1 1 0 0 (Contd...)
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Sequential Circuits Table 8.25 1 1 0 0 0 0 1 1
(Contd...) 4 5 6 7 8 9 10 11
1 1 1 1 0 0 0 1
0 1 0 0 1 1 1 0
1 0 1 0 1 0 1 0
� Solution Figure 8.85 shows the timing diagram of Table 8.25 for 3bit synchronous UP/DOWN counters.
Fig. 8.85 Waveform of 3bit synchronous UP/DOWN counters
8.29 MOD n COUNTER The counter can be designed in such a way that the counter starts counting any preset value to any required value. The modulus of counter with four ﬂipﬂops in up counting mode for any preset value is 24N1. If the preset state, N is =3, the modulus of counter is 1631=12. In down counting operation, the counter starts count down from preset state. When the preset state of down counter is (11)10 or 1011, the counter sequentially counts down from 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, and 0. So the modulus of down counter is Nmax+1 where, Nmax is the maximum count value which equal to (11)10. If the counter maximum value is 12, the counter will be mod 13. The mod ‘n’ counters can be designed by the counter reset, logic gates and interconnection of counters. In counter reset method, when the counter completes the desired count, all ﬂipﬂops of counter will be reset and counter start counting from reset state. In some cases, logic gates are used to generate the counting sequence without the resetting the counter. Counters may also be connected in cascade to implement a counter. When mod 2 and mod 8 counters are connected in cascade, the counter circuit behaves as mod 16 counters. Figure 8.86 shows the cascade connection of mod2 and mod8 counters. The timing diagram is shown in Figure 8.87. It is clear from timing diagram that ﬁnal output can be obtained after 16 clock Fig. 8.86 Cascade connection of mod2 and mod8 counters pulses. Hence the overall modulus of
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Digital Electronics: Principles and Applications
the cascaded counters is 2 × 8 =16. This also called as divide by16 counter.
Fig. 8.87
8.29.1
Timing diagram of mod16 counter
Mod3 Counter
Figure 8.88 shows the state transition diagram of mod three counters. As there are three states, two ﬂipﬂops are required to implement it. Table 8.26 shows the truth table of mod3 counter. The counter counts 0, 1, 2 sequentially. After counting 2 it returns to 0. This is possible, Table 8.26 Truth table of when a combinational logic circuit reset all ﬂipﬂops at the counter Mod3 counter state 3. Figure 8.89 shows the circuit diagram of mod3 counter. It is Count Q1 Q0 depicted in ﬁgure that output of ﬂipﬂop FF0 and FF1 are connected 0 0 0 into an NAND gate and output of NAND gate can be used to reset or 1 0 1 clear ﬂipﬂops FF0 and FF1. At the counter state 3, FF0 and FF1 will be 2 1 0 1 and NAND gates output is 0 which reset ﬂipﬂops. Then the counter sequentially counts 0, 1, and 2. The waveform of mod3 counter is given in Fig. 8.90.
Fig. 8.88
State transition diagram of mod3 counter
8.29.2
Mod5 Counter
Fig. 8.89
Circuit diagram of mod3 counter
The state transition diagram of mod5 counter is shown in Fig. 8.91. Three ﬂipﬂops are required to implement it. Table 8.27 shows the truth table of mod5 counter. The counter counts 0, 1, 2, 3, and 4 sequentially. After counting 4, it returns to 0. Therefore a combinational logic circuit is required to reset all ﬂipﬂops at the counter state 5. The circuit diagram of mod5 counter is depicted in Fig. 8.92. The waveform of mod5 counter is given in Fig. 8.93.
Fig. 8.90
Waveform of mod3 counter
Fig. 8.91 State transition diagram of mod5 counter
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Sequential Circuits
Fig. 8.92
Table 8.27
Count
Circuit diagram of mod5 counter
8.29.3
Truth table of mod5 counter 0 0 0 0 1
Table 8.28
0 0 1 1 0
Waveform of mod5 counter
Mod12 Counter
The state transition diagram of mod12 counter is shown in Fig. 8.94. Four ﬂipﬂops are required to implement it. Table 8.28 shows the truth table of mod 12 counter. The counter counts 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 and 11 sequentially. After counting 11 it returns to 0. Therefore a combinational logic circuit is required to reset all ﬂipﬂops at the counter state 12. The circuit diagram of mod12 counter is depicted in Fig. 8.95. The waveform of mod12 counter is given in Fig. 8.96.
Q2 Q1 Q0
0 1 2 3 4
Fig. 8.93
0 1 0 1 0
Truth table of Mod12 counter
Count
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9 10 11
0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1
Fig. 8.94 State transition diagram of mod 12 counter
8.30 SYNCHRONOUS COUNTER DESIGN STEPS The basic operation of synchronous counters is already explained in this chapter. In this section, the design of synchronous counter is explained below sequentially: Step1 Deﬁne the counting sequence of counter and draw the state diagram of the counter. Fig. 8.95
Circuit diagram of of mod 12 counter
Step2 Develop a truth table of the counter with present sate and next state.
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Digital Electronics: Principles and Applications
Step3
The unused state of the counter should be tabulated in the present state and the next state should be initial count value. But, in practice, the unused states of the counter do not shown in ﬂipﬂop excitation table. Step4 Select T or D or JK or RS ﬂipﬂops for design a counter and ﬁnd the number of ﬂipﬂops considering the expression 2n ≥ m, where n is the number of ﬂipﬂops and m is the number of counting sequence. Step5 Draw the Kmaps for all ﬂipﬂop inputs. Step6 Derive the simpliﬁed expression for all Fig. 8.96 Waveform of mod12 counter ﬂipﬂop inputs. Step7 The implementation circuit diagram of counter with ﬂipﬂops and logic gates. By using above steps, mod5 synchronous counter and mod10 synchronous counter design are explained in this section.
8.30.1
Mod5 Synchronous Counter
The counting sequence of mod5 counter is 0, 1, 2, 3, 4, 0, 1, 2… and Table 8.29 shows the counting sequence of Table 8.29 Sequence of mod5 counter mod5 counter. The state diagram of mod5 counter is Clock pulse Q2 Q1 Q0 given in Section 8.29.2. To design this counter, three ﬂip0 0 0 0 ﬂops are required and all ﬂipﬂops are connected with a 1 0 0 1 2 0 1 0 common clock pulse. To generate the counting sequence, 3 0 1 1 ﬂipﬂop inputs are given in ﬂipﬂop excitation table as per 4 1 0 0 Table 8.30. The initial state of ﬂipﬂop FF0 is 0 and its output will be changed to 1 after applying clock pulse. For that reason, J0 must be 1 and K0 must be 0 or 1 (X). The initial state of ﬂipﬂop FF1 is 0 and it’s output will not be unchanged after the clock pulse and consequently J1 will be 0 and K1 will be 0 or 1 (X). The state of FF2 does not changed after the ﬁrst clock pulse and therefore, J2 will be 0 and K2 will be 0 or 1 (X). The other input states of FF0, FF1 and FF2 to develop the sequence are depicted in Table 8.30. The Karnaugh map for J0, K0, J1, K1, J2, and K2 are shown in Fig. 8.97(a) to Fig. 8.97(f) respectively. The simpliﬁed expressions for all ﬂipﬂops inputs are – J0 = A , K0 =1, J1=C, K1=C, J2=BC, and K2=1. Figure 8.98 shows the implementation of mod5 counter using ﬂipﬂops and logic gates. Table 8.30 Flipﬂop excitation table of mod5 counter
Clock pulse
Preset state
Next state
CLK
Q2 A
Q1 B
Q0 C
Q2 A
Q1 B
Q0 C
0 1 2 3 4
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 0 0 1 0
0 1 1 0 0
1 0 1 0 0
FF2 J2 K2 0 0 0 1 x
x x x x 1
Flipﬂop inputs FF1 FF0 J1 K1 J0 K0 0 1 x x 0
x x 0 1 x
1 x 1 x 0
x 1 x 1 x
339
Sequential Circuits
Fig. 8.97
– (a) Kmap for J0= A
and (d) Kmap for K1 (K1= C)
(b) Kmap for K0 ( K0= 1)
(c) Kmap for J1 (J1= C)
(e) K map for J2 (J2=BC) and
(f ) K map for K2 (K2=1)
Fig. 8.98 Mod5 counter
8.30.2
Mod10 Synchronous Counter
In mod10 counters the counting sequences are 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0….. The state diagram and sequence table of mod10 counter are given in Section 8.18. To design this counter, four ﬂipﬂops are required and all ﬂipﬂops are connected with a common clock pulse. Assume that JK ﬂipﬂips are used to design mod10 counter. To produce the above counting sequence, all ﬂipﬂop inputs are given in ﬂipﬂop excitation Table 8.31. The Karnaugh map for J0, K0, J1, K1, J2, K2, J3, and K3 are shown in – Fig. 8.99(a) to Fig. 8.99(h) respectively. The simpliﬁed expressions for all ﬂipﬂops inputs are J0 = Q3 – – – – – – – – – – – – – – + Q2 Q1, K 0 = Q3 + Q2 Q1, J1 = Q3 Q0, K1 = Q3 Q0, J2 = Q3Q1Q0, K2 = Q3Q1Q0, J3 = Q3 Q2 Q1 Q0 and K3 = Q2 Q–1Q0. The implementation of mod10 counter using ﬂipﬂops and logic gates is shown in Fig. 8.100. Table 8.31 Flipﬂop excitation table for mod 10 counter
Clock pulse CLK
Preset state Q3
Q2
Q1
Q0
Q3
Q2
Q1
Q0
0 1 2 3 4 5 6 7 8 9
0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 1 1 1 0 0
0 0 1 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1 0 1
0 0 0 0 0 0 0 1 1 0
0 0 0 1 1 1 1 0 0 0
0 1 1 0 0 1 1 0 0 0
1 0 1 0 1 0 1 0 1 0
Next state
FF3 J3 K3 0 0 0 0 0 0 0 1 x x
x x x x x x x x 0 1
Flipﬂop inputs FF2 FF1 K2 J1 K1 2 0 0 0 1 x x x x 0 0
x x x x 0 0 0 1 x x
0 1 x x 0 1 x x 0 0
x x 0 1 x x 0 1 x x
FF0 J0 K0 1 x 1 x 1 x 1 x 1 0
x 1 x 1 x 1 x 1 x x
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Digital Electronics: Principles and Applications
Fig. 8.99
– – – (a) K map J0 = Q3 + Q2Q1 and
– (d) K map K1 = Q3Q0
and
8.31
– – – – (b) K map K0 = Q3 + Q2Q (c ) K map J1 = Q3Q0 and
– (e) K map J2 = Q3Q1Q0 and
– (g) K map J3 = Q3Q2Q1Q0
– (f) K map K2 = Q3Q1Q
– – (h) K map K3 = Q2Q1Q0
CASCADE COUNTERS
Counters are connected in cascade to construct higher mod counters with smaller mod counters. In this counters, the last stage output of one counter is fed to another counter. Figure 8.101 shows the cascade connection of two counters: one is mod4 counter and other is mod8 Fig. 8.100 Mod10 counter counter. The output of mod4 counter is connected with input of clock of mod8 counter. The overall mod value of counter is determined after multiplication of individual mod value of counters. So, the mod value is 4 × 8=32. Figure 8.102 shows the timing diagram of mod32 counter.
Fig. 8.101 Cascade connection of mod4 and mod8 counters
Fig. 8.102
Waveform of mod32 counter due connection of mod4 and mod8 counters to cascade
341
Sequential Circuits
Synchronous counters can be connected in cascade from. For this count enable (CE) and terminal count (TC) are used for higher mod counter. Figure 8.103 shows the cascade connection of two mod10 counters. When count enable (CE) signal is high, counters start counting. Here, terminal count of counter 1 is connected to count enable (CE) terminal of counter2. When counter1 does not reach its last count state, the TC signal of counter1 is low and counter2 is inhibited. After completion of ﬁrst cycle counting of counter1, TC signal of counter1 becomes high. This high enables counter2 and the counter2 starts to count and changes to next state. When the ﬁrst clock pulse is applied to counter1, this counter should reaches its last stage of count or terminal count at 10th clock pulse (CLK10) and counter2 starts counting from its initial state to next state. After completion of the second cycle of counter1, TC of counter 1 is again high and counter2 is again enabled and its state changes to next state. This operation continues for ten cycles. After the ten cycle operations, the counter2 generates terminal count TC. Therefore, counter1 generates TC after ten clock cycles but counter2 generates TC after 10 × 10=100 clock cycles. In this way, counter2 will complete one cycle after 100 clock pulses and the overall mod value of two cascaded Mod10 counters is 100. This circuit can be used as frequency divider. When input frequency of clock signal (CLK) is fin, the frequency of TC of counter1 is fin/10 and the frequency of TC of counter2 is fin /100 as shown in Fig. 8.103. When the mod10 counters are connected in cascade, the output frequency will be fin/10, where fin is the input frequency. Figure 8.104 shows the cascade connection of three counters and a 10 MHz clock frequency has been applied to counter1. Then output frequencies of three counters are 1 MHz, 100 KHz and 10 KHz respectively.
Fig. 8.103
Fig. 8.104
Example 8.10
Cascade connection of two mod10 counters
Cascade connection of three mod10 counters
Determine the mod value of counter as shown in Fig. 8.105(a) and (b).
Fig. 8.105(a)
Fig. 8.105(b)
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Digital Electronics: Principles and Applications
� Solution (a) The mod value of two cascade counters as shown in Fig. 8.105(a) is 2×10=20 (b) In Fig. 8.105(b), three different counter are connected in cascade. The mod value of three cascade counters is 10×5×8=400
8.32
PROGRAMMABLE OR PRESETTABLE COUNTERS
Generally the up counters start the count sequence from 000..0, but the down counters start counting from 111…1 state. This is done when all the ﬂipﬂops are reset or set after completion of each counting cycle. A counter can also be made to start counting in any desired state using combinational logic circuits. Programmable counters have the capability to start counting from any desired state. The Programmable counters are known as Presettable counters, which can be preset to any desired starting count. Presettable counters are two types, such as asynchronous presetting and synchronous presetting counters. Asynchronous presetting is independent of the clock input, while synchronous presetting occurs on the active edge of the clock signal. Figure 8.106 shows a three bit synchronous presetting counter. In this counter, apply the desired count value to P2, P1 and P0 inputs. When the preset load (PL) is low, the count value is loaded into the counter ﬂipﬂops. After that the preset load (PL) input becomes high, the NAND gates are disabled and the counter is free to count input clock Fig. 8.106 Three bit programmable or presettable pulses starting from the newly entered count counter value which has been preset into the ﬂipﬂops. Most commonly used Presettable counters ICs are 74ALS190, 74ALS191, 74ALS192, 74ALS193, 74HC190, 74HC191, 74HC192 and 74HC193.
8.33
SELF STARTING AND SELF CORRECTING COUNTERS
The counter already explained in previous sections always starts counting sequence from either 000 or 111. In real working environment, we can not able to assume that the counter will always start from this predeﬁned count value. As soon as the power switch is ON, the states of the ﬂipﬂops is undeﬁned, they will be set or reset at random. Therefore, the counter should not be able to start Fig. 8.107 (a) State transition diagram of selfstart counter and from any predeﬁned state and the (b) State transition diagram of selfstart counter
Sequential Circuits
343
counting states will not be correct. This problem can be eliminated by self starting and self correcting counters. In any modn counter, all possible states are not present but only required states are present. But in a selfstarting counter each possible state are present through some states which are not desired –– –– –– Fig. 8.108 (a) K map for (D0 = A B + BC + C A ) and (b) K map for –– – – – –– count sequence. (D1 = A B C + A BC ) and (c) K map for D3 = (D3 = A BC + ABC ) The selfstarting and selfcorrecting counters should have a sequence of transitions that eventually leads to a valid counter state. It is not a matter how the counter starts up, but it eventually enters the proper counter sequence after very short time. Figure 8.107(a) shows the state transition diagram of a typical selfstarting counter. In this state transition diagram, the counter should be in sequence after one transition. Fig. 8.107(b) shows the alternative state transition diagram. In this diagram, counter may require either two transitions or one transition before entering into the correct sequence. During design, it is necessary to select the counter sequence as few transitions as possible. Therefore, Fig. 8.107(a) is used for hardware implementation. As shown in Fig. 8.107(a), the counting sequence is 000→001→011→100→101→000. If at starting initial count value is either 111 or 110 or 010, then self correcting capability has been added after incorporating the unused states in counter design. If present state is 111 or 110 then, next transition will be 000. When present state is 010 then next state transition is 011. When this counter is designed with D ﬂipﬂops, the excitation of D ﬂipfops will be the next state. Flipﬂops excitation for selfstart counter is given in Table 8.32. The state transition Table 8.32 is represented by Kmaps as shown in Fig. 8.108(a), (b) and (c). The excitation function of D –– – – ﬂipﬂops are D0 = A B + B C + –– –– – – A C , D1 = A B C + A BC , and D3 = – –– A BC + AB C where A=Q2, B=Q1, C=Q0. The implementation of the selfstart and selfcorrecting counter is shown in Fig. 8.109. In some applications of counFig. 8.109 Selfstarting counter ters, self initialisation is an advantage. It eliminates the need for complex initialisation and guarantees the return to the original state sequence after a temporary wrong state. The low operating frequency and large areas of the available selfcorrecting counters have limitations. Due to the additional hardware required to change state transitions, the ﬁnal circuit tends to be slow and large. The selfstarting and selfcorrecting counters have maximum 10 stages.
344
Digital Electronics: Principles and Applications Table 8.32
Clock pulse CLK
Flipﬂops excitation for self start counter
0 1 2 3 4
Preset state
8.34
Next state
Q2 A
Q1 B
Q0 C
Q2 A
Q1 B
Q0 C
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
0 0 0 1 1 0 0 0
0 1 1 0 0 0 0 0
1 1 1 0 1 0 0 0
FF2 D2 0 0 0 1 1 0 0 0
Flipﬂop inputs FF1 FF0 D1 D0 0 1 1 0 0 0 0 0
1 1 1 0 1 0 0 0
COUNTER APPLICATIONS
Digital counters are very useful and versatile devices. These devices have many applications such as frequency measurement, time period measurement, digital clocks, decimal counter, electric organ, rhythm generators, Atomic clocks, master clocks and world clocks, etc. In this section, only application of counters in frequency measurement, time period measurement, digital clocks are discussed.
8.34.1
Frequency Measurement Using Counter
The basic block diagram of frequency measurement using counter is shown in Fig. 8.110. The counter is driven by the output of an AND gate. The AND gate inputs are a known frequency sample pulse and an unknown frequency signal whose frequency will be measured. When the sample pulse is high, then only unknown frequency signal are allowed to pass through the AND gate and output of AND gate is fed into the counter. Then counter counts number of pulses during time interval t1 to t2 as shown in Fig. 8.111.
Fig. 8.110
Frequency measurement using counter
Fig. 8.111 Principle of frequency measurement using counter
The counter starts counting at t1 time and the counter stops counting at t2. Thus, the counter counts the number of pulses that occur during the sampling interval. This is a direct measure of the frequency of the pulse waveform. Usually, the counter is made by cascaded BCD counters, the decoder and seven segment display units. The decoder converts the BCD outputs into seven segment form and display in
345
Sequential Circuits
segment display units. In this way, the frequency of a signal is measured. In this method, frequency measurement is not accurate as accuracy depends almost entirely on the duration of the sampling interval, which must be very accurately controlled. The most commonly used frequency measurement scheme Fig. 8.112 Frequency measurement scheme using accurate sam is shown in Fig. 8.112. This pling intervals and counter scheme is very accurate as crystal controlled oscillator is used to generate a very accurate 100 kHz waveform, which is shaped into square pulses and fed to a series of decade counters that are being used to successively divide this 100 kHz frequency by 10. The frequencies at the output of each decade counter are as accurate as the crystal frequency. These decade counters are usually binary counters. The switch is used to select one of the decade counter output frequencies to be fed to the clock input of a single ﬂipﬂop to be divided by 2.
8.34.2
Measurement of Time Period
Using the principle of frequency measurement using counter, the time period of any signal can be measured. Fig. 8.113 shows the basic block diagram of time period measurement using counter. The most accurate crystal controlled oscillator 1 MHz reference frequency is applied the AND gate through a pulse shaper circuit. Input signal is also applied to clock terminal of JK ﬂipﬂops. The output of JK ﬂipﬂop is for a clock period of input signal. Then known ﬁxed frequency signal passes through AND gate for time interval Tx only. The output of AND gate is connected with a counter. The counter counts the ﬁxed frequency signal for the time interval. Then the time period can be measured in terms of count value and display it in seven segment display section.
Fig. 8.113
8.34.3
Time period measurement using counter
Digital Clocks
The most common application of counters is digital clock. Any digital clock displays the time of day in hours, minutes and seconds. To construct an accurate digital clock, a very highly controlled basic clock frequency is required. Generally, a quartzcrystal oscillator is used to generate the basic frequency for batteryoperated digital clocks. Digital Clocks operated from the ac power supply, and then the 50 Hz
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power frequency is uses as the basic clock frequency. In both case, the basic frequency has to be divided down to a frequency of 1 Hz or pulse of 1 second (pps). The basic block diagram for a digital clock is shown in Fig. 8.114. The 50 Hz signal is passes through a pulse shaper circuit to produce square pulses at the rate of 50 pps. Then, 50 pps square waveform is fed into a MOD50 counter to generate a 1 pps signal. The 1pps signal is then fed into the SECONDS section. In this section, BCD and MOD6 counters are used to count seconds and display seconds from 00 to 59. After counting 60 seconds, the MOD6 counter generates 1 pulse/minutes and again starts second cycle counting. In minutes section, BCD and MOD6 counters are used to count minutes and display seconds from 00 to 59. After counting 60 minutes, MOD6 counter of minute section sends a pulse, i.e., 1pulse/hour to the hour section. The Hour section BCD and MOD2 counters count hours and display 00 to 12. After complete one cycle operation, the next cycle operation will be started. Hence, Hours, Minutes and Seconds are displayed in Hour section, Minutes section and Seconds section respectively.
Fig. 8.114 Block diagram of Digital Clocks
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347
SUMMARY Shift registers are storage devices and used for storing binary data. JK, D and SR flipflops can construct shift registers. In shift register, several flipflops can be cascaded together and are driven by a common clock. In ‘n’ bit shift register, ‘n’ flipflops are required. In this chapter, four basic types of shift registers: Serial InParallel Out, Serial In Serial Out, Parallel InParallel Out, Serial In Parallel Out are discussed with examples and ICs. A bidirectional shift register can move data internally in either left or right direction. In a universal shift register, data can be entered/loaded in serial and parallel, and data can also be out in serial and parallel. The bidirectional and universal shift register ICs are also incorporated in this chapter. The Ring and Johnson shift counters are two specialized shift registers used to create sequential outputs. The Ring counter has ‘n’ states in its sequence but the Johnson counter has ‘2n’ states, where n is the number of stages. Counter is a sequential circuit and it can be developed by using flipflops. Generally, counter has a 2n counter states, where ‘n’ is the number of flipflops used in the counter. Counter of any value can be designed by skipping some states from the natural count. For this feedback signals are taken from some flipflops and then reset or clear all flipflops. In this chapter, operations of asynchronous (ripple) and synchronous counters are explained in detail. The design of synchronous counters, modn counters, and cascade connection of counter are also incorporated. Some asynchronous and synchronous counters ICs are also included for practical implementation. Cascaded counters, programmable counters, selfstarting and selfcorrecting counters and applications of counters are also discussed in this chapter.
MULTIPLE CHOICE QUESTIONS 1.
2.
3.
4.
5.
6. 7.
Left shifting the contents of a shift register by one bit is equivalent to (a) dividing the content by 2 (b) dividing the content by 10 (b) multiplying the content by 2 (d) multiplying the content by 10 Right shifting the contents of a shift register by one bit is equivalent to (a) dividing the content by 2 (b) dividing the content by 10 (c) multiplying the content by 2 (d) multiplying the content by 10 A 4bit PISO shift register will receive 4 bits of _____ data and data will shift by _____ position(s) for each clock pulse. (a) parallel, one (b) parallel, two (c) serial, one (d) serial, two Parallel loading of the 4bit register means (a) left shifting the data in all four ﬂipﬂops simultaneously (b) right shifting the data in all four ﬂipﬂops simultaneously (c) loading data in two of the ﬂipﬂops (d) loading data in all four ﬂipﬂops at the same time A n bit shift register can not be used as (a) module n counter (b) module 2n counter (c) serial to parallel conversion (d) parallel to serial conversion Generally shift register is constructed by using (a) T ﬂipﬂops (b) D ﬂipﬂops (c) J K ﬂipﬂips (d) S R ﬂipﬂips How many clock pulses are required to completely load serially a 8bit shift register?
348
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
Digital Electronics: Principles and Applications (a) 8 (b) 7 (c) 4 (d) 5 The universal shift register can be used as (a) serial to parallel conversion (b) parallel to serial conversion (c) serial to serial conversion (d) a, b and c In a ________ shift register data is entered into register one bet at a time and all data outs at a time (a) SIPO (b) SISO (c) PISO (d) PIPO – In a 4bit shift register, Q of the last ﬂipﬂop is connected with the J terminal of ﬁrst ﬂipﬂop and Q of the last ﬂipﬂop is connected with the J terminal of ﬁrst ﬂipﬂop. The shift register acts as (a) Ring counter (b) Binary counter (c) Shift register (d) None of these. The data can be taken out of a SISO shift register from (a) the Q output of the ﬁrst FF. (b) the Q output of the last FF. (c) all of the Q outputs together. (d) None of these The data can be taken out of a PIPO shift register from (a) the Q output of the ﬁrst FF. (b) the Q output of the last FF. (c) all of the Q outputs together. (d) None of these By adding recirculating lines to a 4bit ParallelIn, SerialOut shift register, it becomes (a) a ParallelIn, Serial and Parallel Out (b) a SerialIn, Parallel and Serial Out (c) a SeriesParallelIn, Series and Parallel Out (d) a bidirectional In, Parallel and Series Out The _________registers have a data is entered in one bit at a time and have all the stored bits shifted out one bit at a time. (a) ParallelIn and ParallelOut (b) ParallelIn and SerialOut (c) SerialIn and ParallelOut (d) SerialIn and SerialOut A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit? (a) Ring shift (b) clock (c) Johnson (d) binary Ring shift and Johnson counters are: (a) synchronous counters (b) asynchronous counters (c) binary counters (d) a and c What is the function of preset of a Ring shift counter? (a) all FFs set to 1 (b) all FFs reset to 0 (c) one FF set to 1, others reset to 0 (d) one FF reset to 0, others set to 1 The difference between a Ring counter and a Johnson counter is (a) Ring counter is faster. (b) The feedback is reversed. (c) Johnson is faster (d) None of these What is the name of shift register that will accept parallel or a bidirectional serial load and will out data in parallel or bidirectional serial form? (a) universal (b) SIPO (c) PISO (d) tristate
Sequential Circuits 20.
21. 22. 23. 24. 25. 26.
27.
28. 29.
30.
31.
Why stepper motors are very popular in digital systems?. (a) low cost (b) driven by sequential digital signals (c) can be able to provide repetitive mechanical movement (d) b and c The number of ﬂipﬂops are required for mod5 counter (a) 1 (b) 2 (c) 3 (d) 4 In design a counter circuit, the most commonly used ﬂipﬂop is (a) D type (b) RS ﬂipﬂop (c) Latch (d) JK type The minimum number of ﬂipﬂops required for a synchronous decade counter is (a) 1 (b) 2 (c) 4 (d) 10 What is the modulus of 5bit ripple counter (a) 16 (b) 32 (c) 5 (d) 64 A twisted ring counter consisting of 6 ﬂipﬂops, will have (a) 6 states (b) 12 states (c) 64 states (d) 128 states A mod2 counter, followed by a mod5 counter is (a) mod5 counter followed by a mod2 counter (b) mod11 counter (c) mod9 counter (d) decade counter A decade counter can be designed by (a) 4 ﬂipﬂop and by pass 6 states (b) 10 ﬂipﬂops and by pass 10 states ( c) 4 ﬂipﬂop and by pass 5 states (d) 4 ﬂipﬂop and by pass 4 states Three mod5 counters are connected in cascaded. The overall modulus of circuit will be (a) Mod10 counter (b) mod15 counter (c) Mod125 counter (d) None of these A 3bit ripple counter will have the counting sequence as (a) 000,001,010,011,100,101, 110, 111 (b) 000, 001, 011, 111 (c) 111, 110, 101, 100, 011,010, 001, 000 (d) none of these Any sequential logic circuit consist of (a) only ﬂipﬂops (b) only gates (c) ﬂipﬂops and combinational logic circuits (d) only combinational logic circuits The waveforms of a counter are shown in Fig. 8.115. This is a (a) Ring counter (b) twisted ring counter (c) ripple counter (d) synchronous BCD counter
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Digital Electronics: Principles and Applications
Fig. 8.115
32. 33. 34.
35.
36.
The preset input of a 4bit preset able UP counter has 1010. The modulus of this counter is (a) 5 (b) 10 (c) 11 (d) 15 The preset input of a 4bit preset able DOWN counter has 1001. The modulus of this counter is (a) 11 (b) 10 (c) 9 (d) 8 If 100KHz clock pulse is applied to mod2 counter, the output frequency of symmetrical square wave will be (a) 200KHz (b) 100KHz (c) 50KHz (d) None of these If time period of input clock pulse is 10µs, 50µs times period symmetrical square wave can be generated from (a) divide by 5 (b) divide by 10 (c) 3bit binary counter (d) cascade connection of mod2 and mod5 The waveforms of a counter are shown in Fig. 8.116. This is a (a) Asynchronous counter (b) Johnson counter (c) Ring (d) None of these
Fig. 8.116
37.
The waveforms of a counter are shown in Fig. 8.117. This is a (a) Asynchronous counter (b) Johnson counter (c) Ring (d) None of these
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Sequential Circuits
Fig. 8.117
38. 39. 40.
A 4bit ripple counter requires (a) 3 (b) 4 (c) 5 (d) The minimum propagation delay is possible in (a) Synchronous counter (b) Asynchronous counter The maximum number of states of 4bit synchronous counters (a) 16 (b) 10 (c) 8 (d)
6 ﬂipﬂops
4
REVIEW QUESTIONS 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 8.11 8.12 8.13
What is shift register? What are the types of registers? Explain any oneshift register with example. Explain the operation of bidirectional shift register with circuit diagram and waveforms. What is universal register? Explain its operation. Explain the operation of Ring counter with state diagram and waveforms. Explain the operation of Johnson counter with state diagram and waveforms. What is difference between Johnson and Ring counter. Write the applications of shift register brieﬂy. What is serial data transfer and parallel data transfer? Explain the serial to parallel and parallel to serial data conversion with circuit diagram. Explain the operation of four stages and ﬁve stages twisted ring counter with circuit diagram, truth table and timing diagram. Draw the waveforms to enter a serial data 11101into a SIPO shift register. Draw the logic circuit diagram of universal shift register and explain its operation with functional table. What is the largest hexadecimal number that can be stored in a ten ﬂipﬂops shift register?. Draw a PIPO shift register which consists of six ﬂipﬂops. Draw a logic circuit diagram of shift register to produce a 50µs delay and explain brieﬂy. Draw the waveform for 4bit SIPO shift register as shown in Fig .8.118, when data input is 1101.
Fig. 8.118
352 8.14
Digital Electronics: Principles and Applications — —— Draw the timing diagram of the shift register as shown in Fig. 8.119, when LEF T /RIGHT signal is low for three clock pulses and high for three clock pulses. Consider QA=1, QB=0, and QC=1.
Fig. 8.119
8.15
Draw the output waveform of SISO shift register as shown in Fig. 8.120, serial data 10101011 applied in A and B is high.
Fig. 8.120
8.16
Show the timing diagram of 4bit PISO shift register as depicted in Fig. 8.121, if input data is 1101.
Fig. 8.121
8.17
Explain the operation of counter circuit as shown in Fig. 8.122 with truth table and timing diagram.
Fig. 8.122
Sequential Circuits
353
8.18
Explain the operation of counter circuit as shown in Fig. 8.123 with truth table and timing diagram.
8.19
Draw the logic circuit diagram of a ten bit Ring counter. Show the timing diagram and explain brieﬂy. Figure 8.124 shows the logic diagram of 74194. Explain how it will be used in (i) Serial Input Parallel Output (ii) Parallel In Parallel Out (iii) shift left and (iv) shift right operation.
Fig. 8.123
8.20
Fig. 8.124
8.21 8.22 8.23 8.24 8.25
Deﬁne counter. Explain classiﬁcation of counter with example. Write the count sequence of 3bit binary ripple counter. Design a 3bit ripple counter using JK ﬂipﬂops. Draw the timing diagram of 4bit asynchronous counter and explain brieﬂy. Design a 4bit binary UP/DOWN ripple counter with a control input for UP/DOWN counting. Figure 8.125 shows a ripple counter. Draw the timing diagram for ﬁrst ten clock pulses.
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Fig. 8.125
8.26 8.27 8.28
Design a 4bit asynchronous decade counter and draw the timing diagram. Draw a logic diagram of 4bit ripple counter and explain its operation with timing diagram and sequence table. What modiﬁcation is required to use as a decade counter.? Figure 8.126 shows a asynchronous counter. Draw the waveform of output Q0, Q1 and Q2 outputs with respect to clock.
Fig. 8.126
8.29 8.30 8.31 8.32 (a) (b) (c) (d) 8.33 8.34
Design the following counters using 7493A. (a) Divide by 2 (b) Divide by 8 (c) Divide by 16 (d) Divide by 10 Draw the timing diagram for the following asynchronous counters (a) 4bit binary up counter (b) 6 stage binary counter What are the disadvantages of ripple counter? How these disadvantages are overcome in synchronous counter? Write the difference between the following counters Synchronous counter and asynchronous counter Binary UP and binary DOWN counter Decade counter and ripple counter Mod5 and divide by 5 counters Draw the timing diagram of 4bit synchronous counter and explain with sequence table and logic diagram. Design a 4bit synchronous UP/DOWN counter.
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Figure 8.127 shows a synchronous counter. Draw the timing diagram for ﬁrst eight clock pulses.
Fig. 8.127
8.36 8.37 8.38 8.39 8.40
Design a 4bit synchronous decade counter and draw the timing diagram. Design a 4bit synchronous decade counter to count Excess3 code sequence. Design a synchronous decade counter using 74160. Deﬁne mod ‘n’ counter. Design the following mod counters (a) mod5 (b) mod10 (c) mod15 (d) mod12 Design a counter using JK ﬂipﬂops to generate the sequence as shown in Table 8.33. Table 8.33
Clock pulse
Q3
Q2
Q1
Q0
0
0
0
0
1
1
0
0
1
0
2
0
1
0
0
3
1
0
0
0
8.41
Determine the overall modulus of cascade connection of counters as given in (a), (b) & (c ) and also determine the output frequency. Consider clock frequency is 10KHz
8.42
What is the difference between register and counter? Explain how shift register can be used as a counter. Design a synchronous mod6 counter using JK ﬂipﬂops and draw the timing diagram of this counter. Design the following synchronous counter (a) divide by 7, (b) divide by 9, (c) divide by 11 A synchronous counter using JK ﬂipﬂops has the following connections – (ii) In FF1, J = K = Q0Q 3 (i) In FF0, J = K = HIGH (iii) In FF2, J = K = Q0 Q1 (iv) In FF3, J = K = Q0 Q1 Q2 + Q0Q3
8.43 8.44 8.45
Draw the above synchronous counter and determine its modulus and the count sequence.
CHAPTER
9 SEQUENTIAL CIRCUITS DESIGN 9.1
INTRODUCTION
The combinational logic circuits are a part of digital systems and they have many applications such as decoder, encoder, adder, subtracter, multiplexer, demultiplexer, etc. But when the circuit output not only depends on the present state but also the previous state, the circuit is known as sequential logic circuit. Any sequential circuit consists of a combinational logic circuit and memory elements. The output of combinational logic circuit is stored in memory elements. Memory elements output feedback into combinational logic circuit and used as input variables. The output of combinational logic circuit depends upon the external inputs and input from memory elements. A memory element is a device which can store information in terms of ‘1’ or ‘0’ and its state can be modiﬁed by clock signal and data inputs. A ﬂipﬂop is an one bit memory element, which can store ‘1’ or ‘0’. To store ‘n’ bit information, ‘n’ ﬂipﬂops are required. Generally, JK, D and T ﬂipﬂops are used in memory elements. In this chapter, different kinds of sequential logic circuits: synchronous sequential circuits and asynchronous sequential circuits are discussed. In fact, a sequential logic circuit is one way of building block of a sequential machine. In any sequential machine, the output not only depends on the present input to the machine, but also it always depends on the previous condition of the machine. Sequential machines can be considered as machines, which have a well organised set of conditions. The conditions are called as states. Therefore, sequential machines are also called as state machines. The transitions of the machine from one state to the next are most frequently driven by a clock signal. When the machine is driven by clock signal, it is known as a synchronous machine. If the machine is not clocked driven, the transitions from one state to the next state can be decided by the change in input to the machine and it is known as asynchronous machine. As input changes sequentially, the output of sequential machines may be repeated cyclically through a ﬁnite set of states. Consequently, sequential machines are also called as ﬁnite state machines. A ﬁnite state machine is the most general type of digital circuit whose outputs depend upon both on the present input signals and on the previous input signals. Though the previous inputs of a ﬁnite state machine control the present outputs indirectly by determining the internal state of the machine. The internal state and the present inputs ﬁnd out the present output signals. The examples of ﬁnite state machines are latches and ﬂipﬂops, which are the simplest types of ﬁnite state machines and counters. The sequential circuits have many applications in digital system design which consists of combinational
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357
logic circuits as well as memory elements. Any logic family can be used in combinational logic circuit and the memory element may be either D ﬂipﬂops or JK ﬂipﬂops or T ﬂipﬂops. Generally, JK ﬂipﬂops are used for simpler circuit implementation. In this chapter, the design procedure of sequential circuits has been discussed with examples.
9.2
SEQUENTIAL CIRCUIT MODEL
Figure 9.1 shows the model for a general sequential circuit which consists of combinational logic circuit and memory elements. The combinational logic circuit has ‘n’ inputs I1 – In and ‘m’ outputs O1Om. The edge triggered ﬂipﬂops are used in memory elements. This sequential circuit is driven by a clock signal and the output can be changed on either positive or negative edge of the clock pulse only.
Fig. 9.1 Block diagram of a general sequential circuit
The present state of the sequential circuit or ﬁnite state machine (FSM) is always stored in the memory elements. Therefore, memory elements must be capable to store the information and to specify the states of the machine. For example, a sequential circuit or a ﬁnite state machine might have four states speciﬁed by the S0, S1, S2, and S3. S0 represents 00, S1 represents 01, S2 represents 10, and S3 represents 11. So that the memory elements can store codes 00, 01, 10 and 11 representing the four states S0, S1, S2, and S3. The next state of the ﬁnite state machine can be determined by the present state of the machine and by the inputs. The combinational logic circuit is used to perform the logic operations based on the present state of the machine and the input to the machine. Then the combinational logic circuit generates the next state of the machine and fed into the memory. Then next state variables become present state variables and stored in the memory. This method of changing states is known as a state change. The sequential machine is a feedback system as the present state of the machine is fed back to the combinational logic circuit. If there are ‘n’ ﬂipﬂops in the memory to store present state, there are 2n possible states. All 2n state are stored or store only speciﬁed states which are needed and used in the design of the circuit. The state of the circuit can only change on a transition of the clock signal either positive edge or negative edge only. The output of the machine is determined by the present state of the machine and possibly by the input to the machine. The output decoder performs the logic operations on the state of the machine and the input to the machine to generate the output. In some cases, the output is simply the state of the machine when there is no output decoder. But often the state must be converted into output signal using output decoder. When the output is a function of the input signals, the input signals will certainly be converted differently if different output decoder circuits are used for this purpose.
9.3
CLASSIFICATION OF SEQUENTIAL CIRCUITS
The sequential circuits or ﬁnite state machines (FSM) are classiﬁed depending upon the presence or absence of a clock signal such as synchronous sequential circuit and asynchronous sequential circuit.
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When a sequential circuit is driven by a clock signal, it is called as synchronous sequential circuit. If the circuit perform operations with out a clock signal, it is known as asynchronous sequential circuit. This circuit can also be classiﬁed depending on the effect of the present inputs on the present outputs, such as Moore machine and Melay machine. In Moore machine, the outputs depend directly only on the state information. But in Melay machine, the outputs directly depend both on the preset inputs and on the state information. Based on presence or absence of clock, the Moore machine is classiﬁed as synchronous and asynchronous Moore machine. Similarly, the Melay machine is also classiﬁed as synchronous and asynchronous Melay machine. The behaviour of Moore machine is deﬁned by the equations Next state = F (Present state, Inputs) Output = G (Present state) The conﬁguration of synchronous and asynchronous Moore machine is shown in Fig. 9.2 and Fig. 9.3 respectively. Similarly, the behaviour of Mealy machine is deﬁned Fig. 9.2 Synchronous Moore machine by the following equations. Next state = F (Present state, Inputs) Output = G (Present state, inputs) The general structures of synchronous and asynchronous Melay machine are shown in Fig. 9.4 and 9.5 Fig. 9.3 Asynchronous Moore machine respectively.
Fig. 9.4
Synchronous Melay machine
Fig. 9.5 Asynchronous Melay machine
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Sequential Circuits Design
9.4
STATE TABLE
The time diagram of inputs, outputs and ﬂipﬂops states of sequence circuits may be listed in a state table. For the analysis and design of sequential circuits, it is necessary to describe the state transitions of a state machine in a present state, next state and output table. In this table all possible combinations of inputs and present states, and the corresponding next state and output for each combination are listed in tabular form. The state table for a typical sequence circuit is shown in Table 9.1. Assume the following four states S0→00, S1→01, S2→10, and S3→11. After substituting the states, we obtain the state transition Table 9.2. It is depicted in Table 9.1 that there are three sections designated as present state, next state and output. The present state assigns the states of the ﬂipﬂops before the applying a clock pulse. The next state assigns the states of the ﬂipﬂops after the application of the clock pulse. The output section shows the values of the output variables for each combination inputs, present states and next states. The output and the next state sections have two columns: one for X=0 and the other for X=1. Table 9.1 State table
Present state Q 1 Q0
X=0 Q1 Q0
S0 S1 S2 S3
S0 S1 S2 S2
Next State X=1 Q1 Q 0
Table 9.2
Present state Q 1 Q0 00 01 10 11
S1 S3 S0 S3
X=1 O
0 0 0 0
0 0 1 0
State transition table
Next State X=0 X=1 Q1 Q0 Q1 Q0 00 01 10 10
Output X=0 O
01 11 00 11
Output X=0 O
X=1 O
0 0 0 0
0 0 1 0
The analysis of the state table of a typical sequential circuit can be started from any arbitrary state. Suppose we assume that the initial state is 00. When the present state is S0 or 00 (Q1= 0 and Q0= 0). When X = 0, the next state output is unchanged means it is S0 state. Similarly, with Q1= 0, Q0= 0 and X = 1, we ﬁnd that the next state is S1 or 01(Q1= 0 and Q0= 1). The information about state changes is given in the ﬁrst row of the state table. When the present state is S1 or 01, Q1= 0 and Q0=1. If X = 0, the next state out remain unchanged means next state is in S1 state. But if X = 1, the next state output is S3 or 11(Q1 = 1 and Q0= 1). The information is listed in the second row of the state table. In the same way, we can explain the other state conditions of the state table. The state table of any sequential circuit can be written by the same procedure. In general, if a sequential circuit consists of ‘n’ ﬂipﬂops and ‘m’ input variables, there will be 2n rows, one for each state. The next state and output sections should have 2m columns, one for each combination.
9.5
STATE DIAGRAM
The most convenient method to describe any sequential circuit or ﬁnite state machine is a state transition diagram. This is a graphical approach of representing how the ﬁnite state machine changes from one
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Digital Electronics: Principles and Applications
state to another state. This is also used to depict the output generated by the ﬁnite state machine. When the information available in the state table is represented by graphical form, the diagram is known as state diagram or state transition diagram. The state transition diagram contains the same information about the transitions of a state machine which is represented in tabular form. Each row of the table is directly represented in the state diagram by considering the inputs and present state to determine the next state and output. Figure 9.6 is an example of a state transition diagram for a synchronous machine in which the transitions are controlled by a clock. The circle represents the states of the sequential circuit. The state identiﬁcation is written within each circle. In this diagram, there are four states, which are levelled S0, S1, S2 and S3. Assume the following four states represented by Fig. 9.6 State diagram binary code S0→00, S1→01, S2→10, and S3→11 respectively. The transitions between the states are represented by lines with arrows to indicate their directions. Some of the transitions do not change the states, such as the ones above state S0, above state S1, above state S2 and also above state S3. All of the transitions in this synchronous machine are controlled by clock pulse and are written next to the direct arrows representing the transition. The direct arrows are labelled with two binary numbers, which are separated by a ‘/’. The number before the ‘/’ stands for the value of the input which changes the state transition. The number after the ‘/’ represents the value of the output during the present state. For example, the direct arrow from the state 00 to 01 represents that the state of sequential circuit changes from 00 state to the next state 01 while X/Y=1/0. Here X stands for input and Y represents output. When X=1 and after application of the clock pulse, the state of sequential circuit changes to the next state 01 and output will be 0. Consequently, if the state of a sequential circuit is known at a time t0, and the inputs are known from time t0 to time t1, then the state of the sequential circuit can be found at a time t1 from state diagram directly. Actually, there is no difference between a state table and a state diagram except the way of representation. When a state diagram of any sequential circuit is given, we can easily develop the state table from the given state logic diagram. Therefore state diagram directly follows the state table as illustrated in Table 9.3. The state diagram represents the practical form of the state transitions and so it is very easy to understand the state diagram. Table 9.3
Present state AB
X=0 AB
00 01 10 11
00 10 11 11
State table of state diagram
Next State X=1 AB 01 01 10 00
Output, Y X=0 X=1 O O 0 0 1 0
0 0 0 0
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361
9.6 STATE EQUATION The state equation of a sequential circuit is a boolean expression which represents the conditions of ﬂipﬂop state transition. The state equation can be derived directly from the state table. For example, to design the sequential circuit as per Table 9.3, the next state of the ﬂipﬂop must be derived from inputs, and present state. From the next state columns of State Table 9.3, we observe that the ﬂipﬂop A changes its state four times: when X = 0 and AB = 01 or 10 or 11 and when X = 1 and AB = 10. Assume the state of a sequential circuit is known at a time t0, and the inputs are known from time t0 to time t1, then the state of the sequential circuit can be derived at t1. The change of state can be expressed algebraically in a state equation as follows: – – –– – – – – – – – A(t1) = A BX + AB X + ABX + AB X = A BX + AB (X + X) + ABX – – – – – – – – = (A + A)BX + AB (X + X) = BX + AB As (A + A) = (X + X) = 1 Similarly, we ﬁnd that the ﬂipﬂop B goes to 1 state four times: when X = 0 and AB = 10 or AB = 11 and when X = 1 and AB = 00 or AB=01. This change can also be expressed algebraically in a state equation as follows: –– – –– – – – – –– B(t1) = AB X + ABX + A B X + AB X = AB (X + X) + ABX + A B X – – –– – = AB + ABX + A B X As (X + X) = 1
9.7
DESIGN PROCEDURE OF SYNCHRONOUS SEQUENTIAL CIRCUITS
For the design of a sequential circuit having limited number of inputs and outputs, the analysis of sequential circuit is required. The analysis of sequential circuits, such as operation of different types of counters is already explained in Chapter 8. The design procedure of any sequential circuit follows the steps given below: Step1 Deﬁne the problem with speciﬁcation. Step 2 Draw a block diagram for the proposed design with all the inputs and the required outputs. Step3 Make a state transition diagram from the speciﬁcation. Generally, this is the most difﬁcult part of any sequential circuit design. Setp4 Using the state diagram, construct a state table and check for redundant states. Step5 Rebuild the state diagram if redundancy has occurred. Step6 Make a state assignment. Step7 Draw a new state table after removing all redundancies and using the state assignment. Step8 Select the ﬂipﬂops D or T or JK which one will be used in memory elements. Step9 Derive the excitation equations for the next state inputs to the selected ﬂipﬂops with the help of the reduced state table. Derive the output equations of sequential circuit. Step10 Implement the excitation equations and the output equations with the help of logic gates and ﬂipﬂops. Speciﬁcation of Sequential Circuit The speciﬁcation of any sequential circuit consists of some verbal statements of the problem which is the detailed information about the inputs available and the required outputs. The speciﬁcation of the problem is an unambiguous term as it does not state the very simple relationship between inputs and outputs. Before design a circuit, several discussions between designer and user are required to resolve the ambiguities. After getting the complete information about the circuit, designer should start the process of design and implement the circuit properly.
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Block Diagram and Timing Diagram of Sequential Circuit After the detailed study of the problem speciﬁcation, designer should construct a block diagram showing all the inputs and the required outputs. In addition, draw a timing diagram of sequential circuit which represents the outputs of the speciﬁed problem. The State Diagram The verbal statements of the problem should be expressed in terms of the internal states of the circuit and draw a state diagram representing all internal states. There are no deﬁned rules for constructing state diagrams, but it is the ability of the designer which can only be acquired by experience. For example, we assume the following verbal statements of the problem: “A sequential logic circuit receives input data serially on an input line. The input data is synchronised with an external clock signal. When the following combinations 010, 011, 110 and 111 are detected, a 1 will appear at the output. The output must occur when the third bit of the string is present and the third clock pulse is high”. Generally, the innovative and inexperienced designer can develop the treelike structure of the states as shown in Fig.9.7. Here, the method of approach is that the designer selected a state S0 arbitrarily. This internal state of the circuit may have a pair of transition paths: one in the left side and other in the right side. The left side movement or right side movement is selected by the transition signal X. When the transition signal X=1, internal state change from S0 to S1. If the transition signal X=0, internal state change from S0 to S2. Again each of the states S1 and S2 may have a pair of transition paths: one in the left side and other in the right side. Depending upon the value of the transition signal X, there will be four paths lead to the four different states S3, S4, S5 and S6 as depicted in Fig. 9.7. In the same way, each of these four states S3, S4, S5 and S6 has two different paths, but the next transition is that all left and right exist paths return back to the starting state.
Fig. 9.7
State diagram
The combinations 111 and 110 follow the path S0 S1 S3 S0 through the state diagram as shown in Fig. 9.7 and the output O=1 in state S3. In the same way, the combinations 010 and 011 follow the path S0 S2 S5 S0 through the state diagram and the output O=1 in the state S5. Then remaining two paths of the state diagram are related with those combinations which are not required to detect. State Table Corresponding to the state diagram as shown in Fig. 9.7, the state table is developed and it is depicted in Table 9.4. In this table, each row represents the state of the circuit and each column stands for every combination of the input signals. Here, there is only one input signal X. Therefore, there are only two columns in the next state: one for X = 1 and other for X = 0. The next state of the circuit is
363
Sequential Circuits Design Table 9.4
Present state S0 S1 S2 S3 S4 S5
State table of Fig. 9.7
Next state X=0
X=1
S2 Output O = 0 S4 Output O = 0 S6 Output O = 0 S0 Output O = 1 S0 Output O = 0 S0 Output O = 1 S0 Output O = 0
S1 Output O = 0 S3 Output O = 0 S5 Output O = 0 S0 Output O = 1 S0 Output O = 0 S0 Output O = 1 S0 Output O = 0
Table 9.5
Present state S0 S1 S2 S35 S46
Reduced state table
Next state X= 0
X=1
S2 Output O = 0 S46 Output O = 0 S46 Output O = 0 S0 Output O = 1 S0 Output O = 0
S1 Output O = 0 S35 Output O = 0 S35 Output O = 0 S0 Output O = 1 S0 Output O = 0
entered in the each of the cells which are produced by the intersection of the rows and columns. The output O of S6 each state is also entered into the cell. For example, when X = 0 and present is S0, the next state is S2 and output is 0. Similarly, if X = 1 when present state is S0, the next state is S1 and output is 0. In the same way, other states and outputs are entered in the cells. State Reduction When large numbers of states are present in the state diagram, the more hardware is required for the circuit implementation. Therefore, it is required to reduce the number of states if posTable 9.6 Minimal state table sible. The process of the state reduction in sequential circuit design means that the process which can be used Present Next state to minimise the combinational logic circuit design. X=0 X=1 state Usually, the state reduction is done by using Caldwell’s S0 S12 S12 merging procedure which depends upon two equivalent Output O = 0 Output O = 0 S46 S12 S35 states. Equivalence of states can be deﬁned by the folOutput O = 0 Output O = 0 lowing statements: S0 S35 S0 “Two states Sp and Sq are equivalent if both have Output O = 1 Output O = 1 the same next states and both have equal outputs”. It is S0 S46 S0 depicted in Table 9.4 that the rows headed S4 and S6 and Output O = 0 Output O = 0 the rows headed S3 and S5 satisfy the above deﬁnition of equivalence of states. Consequently, states S4 and S6 have been merged, the state formed is represented by S46. Whenever S4 and S6 appear in the table, they are replaced by S46. In the same way, S3 and S5 are merged and from an equivalent state S35 which replaces S3 and S5 wherever S3 and S5 appear in the state table. The reduced state table is shown in Table 9.5. After getting the reduced table, the designer should try to ﬁnd out the minimal state table. For this, again use Caldwell’s merging procedure in the reduced stable table. It is clear from Table 9.5 that the two rows S1 and S2 are equivalent and can be merged to form the equivalent S12. Then S12 replaces S1 and S2 wherever S1 and S2 appear in Table 9.6. After Fig. 9.8 Reduced state diagram that no further reduction is possible. Then the reduced state diagram can be constructed from the minimal reduced state table. Figure 9.8 shows the reduced state diagram.
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Digital Electronics: Principles and Applications
State Assignment After getting the minimum state table, the next step is that the designer should choose secondary variables properly to locate the variables states. The required numbers of secondary variables are determined by the total number of states in the reduced state diagram. It is depicted in Fig. 9.8 that there are four states. Therefore, two secondary variables are required to deﬁne each state uniquely. The number of secondary variables which are used to deﬁne all states of reduced state diagram is equal to the number of ﬂipﬂops required to implement the sequential circuit. As there are four states and two secondary variables A and B are required to describe all four states, only two ﬂipﬂops are required to implement the circuit. Table 9.7 Revised state table of state diagram Revised State Table Table 9.7 shows Present Next State FlipFlop inputs Output the revised state table of reduced state diagram X=0 X=1 state X = 0 X = 1 O as shown in Fig. 9.8 in terms of the secondary AB AB AB D1 D 0 D1 D0 variables A and B. In this table, every possible 00 01 01 0 1 0 1 0 transition of the secondary variables for both 01 10 11 1 0 1 1 0 X = 0 and X = 1 is presented. 10 00 00 0 0 0 0 0 11
00
00
0
0
0
0
1
FlipFlop Selection To implement the sequential circuit, the designer should choose any one of the following ﬂipﬂops: D, JK and T ﬂipﬂops. Here, D ﬂipﬂops have been selected to implement the next state equations. The Next State Equations To determine the next state equations, initially we represent the required inputs of D ﬂipﬂops for every transition in the state table. After that, the Dinputs for the various transitions are mapped on the K  map and ﬁnd the simpliﬁed boolean functions. Figures 9.9(a) and.9.9(b) show the Kmap of D1 and D0 ﬂipﬂops respectively. From the Kmap for D1 and D0, the next state equations are derived as follows:
Fig. 9.9
– D1 = A B
(a) – (a) Three variables Kmap D1 = A B
– D1 = A B
(b) –– – (b) Three variables Kmap D0 = A B + XA
–– – D0 = A B + XA
Output Equations A last column in the state table as shown in Table 9.7 is the output O. The output O=1, when A=1 B=1. Then the output equation is O = AB. If the entry in the state depends on clock pulse then the output should be written as O=A.B.CLOCK. The implementation of sequential circuit using D ﬂipﬂops is shown in Fig. 9.10.
Fig. 9.10
Implementation of sequential circuit using logic gates and D ﬂifﬂops
365
Sequential Circuits Design Example 9.1
Design a sequential circuit (ﬁnite state machine) for Table 9.8 using D ﬂipﬂops. Assume two inputs are A and B, outputs of the sequential circuit are outputs of D ﬂipﬂops, present state =S, Next State=S*. Consider the four states of the sequential circuit are S0=00, S1=01, S2=10 and S3=11. Table 9.8
� Solution After substituting the following four states S0→00, S1→01, S2→10, and S3→11 in Table 9.8, we get the state transition Table 9.9. As the state information is two bits, Present two ﬂipﬂops are required. Q1 and Q0 are the output signals of two ﬂipﬂops. Then state (S) present state of ﬂipﬂops are Q1 and Q0 and the next state of ﬂipﬂops are Q1* and S0 S1 Q0*. When the memory element of the sequential circuit (ﬁnite state machine) is S2 implemented with Dtype ﬂipﬂops, then the excitation table of the D ﬂipﬂops is S3 shown in Table 9.10. Table 9.9 The state transition table
Present state 00 (Q1Q0)
Inputs (AB) 01 10 11
Table 9.10
Inputs (AB) 00 01 10 11 S1 S0 S0 S1 S2 S0 S0 S2 S3 S0 S0 S3 S1 S0 S0 S1 Next State (S*)
The excitation table of D ﬂipﬂops
Present state (Q1Q0)
00
Inputs (AB) 01 10 11
00
01
00
00
01
00
01
00
00
01
01
10
00
00
10
01
10
00
00
10
10
11
00
00
11
10
11
00
00
11
11
01 00 00 01 Next State (Q1* Q0*)
11
01 00 00 01 Inputs of ﬂipﬂops D1 D0
Two Kmaps can be drawn from the excitation Table 9.10. Figure 9.11 shows the Kmap for D1 and D0. Based on the Kmap as shown in Fig. 9.11, the following excitation equations can be derived.
Fig. 9.11 Kmap for D1 and D0
—–– — –– — — –—— D1 = Q1* = QQ0A B + Q1Q0A B + Q1Q0AB + Q1Q0AB = (A B ) (Q1 Q0) –– ––— — –—— — D0 = Q0* = A B Q1 + ABQ1 + A B Q0 + ABQ0 = (A B ) (Q1 Q 0) The implementation of the sequential circuit using D ﬂipﬂops and combinational logic circuit elements is shown in Fig. 9.12.
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Fig. 9.12 Implementation of sequential circuit using Dﬂipﬂops
Example 9.2
The state diagram of a sequential circuit is given in Fig. 9.13. Draw the state table for Fig. 9.13. Assume two inputs are A and B, output is O.
Fig. 9.13
State diagram of a typical sequential circuit
� Solution It is depicted in Fig.9.13 that there are four states of the sequential circuit S0, S1, S2 and S3, and two inputs A and B. The state table of state diagram as depicted in Fig. 9.13 is shown in Table 9.11 representing present state, next state and inputs. When S0= 00, S1= 01, S2= 10 and S3= 11 are inserted in the Table 9.11 and output is also incorporated in this table, we get the complete state transition table as shown in Table 9.12. Table 9.11
Present state (S) S0 S1 S2 S3
State table
Inputs (AB) 00 01 10 11 S1 S2 S3 S1
S0 S0 S1 S0 S0 S2 S0 S0 S3 S0 S0 S1 Next State ( S*)
Table 9.12
Present state (Q1Q0) 00 01 10 11
State table with output
00
Inputs (AB) 01 10
11
01/1 00/1 00/1 01/1 10/0 00/0 00/0 10/0 11/0 00/0 00/0 11/0 01/1 00/1 00/1 01/1 Next State (Q1* Q0*)/Output(O)
367
Sequential Circuits Design Example 9.3
Design a sequential circuit for the state Table 9.13 using D ﬂipﬂops. Assume two inputs are A and B, output of the sequential circuit is O, present state of D ﬂipﬂops = Q1 Q0, Next State of D ﬂipﬂops = (Q1* Q0*). Table 9.13
�
Present state(Q1Q0)
00
00 01 10 11
01/0 10/1 11/0 01/1
01
Inputs (AB) 10
00/0 00/0 00/1 00/1 00/0 00/0 00/1 00/1 Next State (Q1* Q0*)/Output(O)
11 01/0 10/1 11/0 01/1
Solution As the memory element of the sequential circuit is implemented with Dtype ﬂipﬂops, then the excitation table of the D ﬂipﬂops is given in Table 9.14. The Kmap for D1 and D0 is shown in Fig. 9.11. Based on the Kmap as shown in Fig. 9.11, the excitation equations of D1 and D0 ﬂipﬂops can be derived as given below: —–– — –– — — –—— D1 = Q1* = QQ0A B + Q1Q0A B + Q1Q0AB + Q1Q0AB = (A B ) (Q1 Q0) –– ––— — –—— – D0 = Q0* = A B Q1 + ABQ1 + A B Q0 + ABQ0 = (A B ) (Q1 + Q0) As output depends on the current state only, this sequential circuit is a synchronous Moore machine. The — output function O can be easily determined as Q1Q0 + Q1Q0. The implementation of the sequential circuit using D ﬂipﬂops and combinational logic circuit elements is shown in Fig. 9.14. Table 9.14
Present state (Q1Q0) 00 01 10 11
Fig. 9.14
00 01/0 10/1 11/0 01/1
The excitation table of D ﬂipﬂops
Inputs (AB) 01 10 00/0 00/0 00/1 00/1 00/0 00/0 00/1 00/1 Inputs of ﬂipﬂops (D1 D0 )/ Output(O)
11 01/0 10/1 11/0 01/1
Implementation of sequential circuit using D ﬂipﬂops
368
Example 9.4
Digital Electronics: Principles and Applications Design a ﬁnite state machine for the state Table 9.15 using T ﬂipﬂops.
Table 9.15 The state table � Solution Inputs (AB) When Table 9.15 is implemented by T ﬂipﬂops instead of Present state 00 01 10 11 D ﬂipﬂops, the excitation table will be different. Table 9.16 (Q1Q0) shows the excitation table when the ﬁnite state machine is 00 01 00 00 01 implemented by using two T ﬂipﬂops. Construct the K01 10 00 00 10 map for the excitation Table 9.16 and derive the minimised 10 11 00 00 11 boolean function from the Kmap as shown in Fig. 9.15. The 11 01 00 00 01 minimised Boolean excitation functions of T ﬂipﬂops are Next State (Q1* Q0*) as follows: Table 9.16 The excitation table of T –– – – T1= Q1Q0 + A B Q0 + A BQ1 + ABQ0 + AB Q1 ﬂipﬂops –– = Q1Q0 + A B Q0 + (A B)Q1 + ABQ0 Inputs (AB) — – – — –– — — — – – T0= Q1Q0 + A B Q 1 + A B Q 0 + ABQ 1 + ABQ 0 + A BQ0 + AB Q0 Present state 00 01 10 11 — ––— — –– — — – – = Q1Q0 + A B Q 1 + ABQ 1 + A B Q 0 + ABQ 0 + A BQ0 + AB Q0 (Q Q ) 1 0 — –– — –– — – – = Q1Q0 + (A B + AB)Q 1 + (A B + AB)Q 0 + (A B + AB )Q0 00 01 00 00 01 — –—— — –—— — = Q1Q0 + (A B ) Q 1 + (A B ) Q 0 + (A B)Q0 01 11 01 01 11 — –—— — — 10 01 10 10 01 = Q1Q0 + (A B ) (Q 1 + Q 0) + (A B)Q0 11 10 11 11 10 The implementation of the sequential circuit using T ﬂipﬂops Inputs of Flipﬂops T1 T0 and combinational logic circuit elements is shown in Fig. 9.16.
Fig. 9.15
K map of the transition Table.5.16 for T1 and T0
Fig. 9.16 Implementation of sequential circuit using T ﬂipﬂops
369
Sequential Circuits Design Example 9.5
Design a ﬁnite state machine for the state Table 9.17 using JK ﬂipﬂops.
� Solution When JK ﬂip ﬂops are used to implement the Table 9.17, the excitation table consists of four bits in each cell as there are two inputs of each JK ﬂipﬂops. Table 9.18 shows the excitation table when the ﬁnite state machine is implemented by using two JK ﬂipﬂops. Construct the Kmap for the excitation table as shown in Fig. 9.17 and derive the minimised excitation function. The excitation functions of the sequential circuit are as follows: –—— J1 = A B Q0 K1 = (A B) + Q0 — –—— J0 = (A B ) K0 = A B + Q1 The implementation of the sequential circuit using JK ﬂipﬂops and combinational logic circuit elements is shown in Fig. 9.18. Table 9.17
Present state (Q1Q0) 00 01 10 11
00
Table 9.18
The state table
Inputs (AB) 01 10
11
01 00 00 01 10 00 00 10 11 00 00 11 01 00 00 01 Next State (Q1* Q0*)
The excitation table of JK ﬂipﬂops
Present state (Q1Q0) 00 01 10 11
00
Inputs (AB) 01 10
11
0X 1X 0X 0X 0X 0X 0X 1X 1X X1 0X X1 0X X1 1X X1 X0 1X X1 0X X1 0X X0 1X X1 X0 X1 X1 X1 X1 X1 X0 Inputs of ﬂipﬂops J1 K1 J0 K0
Fig. 9.17 Kmap of the transition Table.5.18
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Digital Electronics: Principles and Applications
Fig. 9.18
Example 9.6
Implementation of sequential circuit JK ﬂipﬂops
Design a updown counter for the State diagram 9.19 using Tﬂipﬂops. Assume ‘En’ stands for counter enable and ‘dir’ represents direction of updown counter. Consider four states S0=00, S1=01, S2=10 and S3=11 and two outputs O1 and O0.
Fig. 9.19
� Solution Consider A=‘En’ stands for counter enable and B=‘dir’ represents direction of updown counter. The memory element of sequential circuit consists of two T ﬂipﬂops and the sate transition table is given in Table 9.19. The excitation Table is illustrated in Table 9.20. The Kmap for the excitation table is shown in Fig. 9.20. Then the excitation functions are as follows –— –— T1 = ABQ0 + AB Q0 = A(BQ0 + B Q0) = A B Q0 T0 = A Based on the output table as given in Table 9.21, the output functions are O1 = AQ1 O0 = AQ0 The implementation of the sequential circuit using Tﬂipﬂops and combinational logic circuit elements is shown in Fig. 9.21.
371
Sequential Circuits Design Table 9.19 The state table
Present state (Q1Q0)
00
00 01 10 11
00 01 10 11
Table 9.20
Inputs (AB) 01 10
11
00 11 01 00 10 01 11 10 Next State (Q1* Q0*)
The excitation table of Tﬂipﬂops
Inputs (AB) 01 10
Present state (Q1Q0)
00
00
00
00
11
01
01
00
00
01
11
10
00
00
11
01
11
00
00
01
11
01 10 11 00
11
Inputs of ﬂipﬂops T1 T0
Fig. 9.20
Table 9.21
Kmap of the transition Table.5.20 for T1 and T0
State transition table with outputs
Present state (Q1Q0) 00 01 10 11
00
Inputs (AB) 01 10
11
00/00 00/00 11/11 01/01 01/00 01/00 00/00 10/10 10/00 10/00 01/01 11/11 11/00 11/00 10/10 00/00 Next State(Q1* Q0*)/Output(O1,O0) Fig. 9.21
Example 9.7
Implementation of sequential circuit JK ﬂipﬂops
Implement the State Table 9.22 using D ﬂip ﬂops Table 9.22
Present state AB 00 01 10 11
Next state X=0 X=1 AB AB 01 10 00 00
01 11 00 00
Flipﬂop inputs X=0 X=1 D1 D0 D1 D0 0 1 0 0
1 0 0 0
0 1 0 0
1 1 0 0
Output O 1 1 1 0
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Digital Electronics: Principles and Applications
� Solution Initially we construct the Kmap of Table 9.22 and derive the excitation functions of D ﬂipﬂop inputs D1 and D0. Fig.9.22 shows the Kmap of the excitation Table 9.22. The minimised Boolean functions are obtained form Fig.9.22 as follows – D1 = A B –– – D0 = A B + XA –– The output equation is A B . The implementation of the sequential circuit using D ﬂipﬂops and combinational logic circuit elements is shown in Fig. 9.23.
(a)
(b) – –– – Fig. 9.22 (a) Three variables Kmap D1 = AB (b) Three variables Kmap D0 = AB + XA
Fig. 9.23 Implementation of sequential circuit using D ﬂipﬂops
Example 9.8
Design a sequence detector as per State Table 9.23 and implement using D ﬂip ﬂops. Table 9.23
Present state AB
Next state X=0 X=1 AB AB
State Table
Flipﬂop inputs X=0 X=1 D1 D0 D1 D0
Output X=0 X=1 O1 O0
00
00
01
0
0
0
1
1
0
01
11
01
1
1
0
1
0
0
10
11
01
1
1
0
1
0
0
11
00
10
0
0
1
0
0
1
373
Sequential Circuits Design
� Solution Draw the Kmap of Table 9.23 and derive the excitation function of D ﬂipﬂop inputs D1 and D0. Fig. 9.24 shows the Kmap of the excitation Table 9.23. The minimised Boolean functions are obtained as follows –– – – D1 = X A B + X AB + XAB – – – D0 = XA + AB + AB –– The output equations are O1 = A B and O0 = AB. The implementation of the sequence detector circuit using D ﬂipﬂops and combinational logic circuit elements is shown in Fig.9.25.
Fig. 9.24 (a) Three variables Kmap –– – – D1 = X A B + X AB + XAB
Fig. 9.24 (b)
Three variables Kmap – – – D0 = XA + AB + AB
Fig. 9.25 Implementation of sequence detector circuit using D ﬂipﬂops
374
9.8
Digital Electronics: Principles and Applications
STATE REDUCTION OF SYNCHRONOUS SEQUENTIAL CIRCUITS
Usually synchronous sequential circuits are represented by state table and state diagram. When the state table is directly used to implement the sequential circuit, more hardware is required. To reduce the hardware requirement, the sequential circuit must be optimised by state reduction. There are three different methods of state reduction to ﬁnd equivalent states of any speciﬁed state table. These methods are inspection, partitioning and implication table. The method of state reducing using inspection is already explained in Section 9.7. In this method, the two states Sm and Sn will be equivalent if and only if, each possible input sequence produces identical output sequence irrespective of initial state whether Sm or Sn. For this, all possible input sequences are represented in tabular from incorporating all corresponding output sequences of the sequential circuit. This method will be very tedious when the circuit consists of large number of input signals and very large number of states. Consequently, the other two methods, such as partitioning and implication table are used as these methods are simple and nontedious for state reduction. In this section, portioning and implication table methods of state reduction are discussed with examples.
9.8.1 Partitioning
Table 9.24
State table
Table 9.24 shows a typical state table of a state Present Next state diagram mentioning all states and a single input X X=0 X=1 state and a single output O. Initially, the ﬁrst partition S0 S5 S4 Output O = 1 Output O = 0 can be made by placing all those present states in S0 S1 S2 the same section of partition, when the outputs Output O = 0 Output O = 1 are identical for all possible inputs. It is depicted S0 S2 S3 in Table 9.24 that the present state S0, the two Output O = 0 Output O = 0 possible inputs X=0 and X=1 and the corresponding S5 S3 S6 outputs are O = 1 and O = 0. In the same way, if Output O = 0 Output O = 1 S4 S4 S2 the present state is, either S4 or S5, the output O = 1, Output O = 1 Output O=0 when input X = 0 and the output O=0, while input S5 S5 S4 X = 1. As the outputs are identical, the three states Output O = 1 Output O = 0 S0, S4 and S5 are equivalent states. Similarly, S1 and S0 S6 S3 S3 are equivalent and S2, S6 are also equivalent. Output O = 0 Output O = 0 Therefore, the ﬁrst partition is P1= (S0, S4, S5)(S1, S3)(S2, S6) Table 9.25 Reduced state table In the ﬁrst partition, when X = 0, the next states for Present Next state S0, S4 and S5 are all in the same section of P1. While X=1, X=0 X=1 state the next states for S0, S4, S5 are S4, S2 and S4 respectively. S05 S05 S4 As next state of S4 is different from others, the state S4 Output O = 1 Output O = 0 lies in a different section of partition. Therefore, ﬁrst S05 S13 S26 section of partition P1 can be divided into two different Output O = 0 Output O = 1 sections. The ﬁrst section consists of S0 and S5, and S05 S26 S13 Output O = 0 the second section has only one state S4. Then the new Output O = 0 S4 S4 S26 partition is P2 = (S0, S5) (S4) (S1, S3) (S2, S 6). Output O = 1 Output O = 0 After that, we again try to ﬁnd out the existence of new partition using the same procedure. As there is no further partition, the reduced state table is shown in Table 9.25.
Sequential Circuits Design
Table 9.26
Present state S0 S1 S2 S3 S4 S5 S6 S7
State table
Next state X=0
X=1
S0 Output O = 0 S3 Output O = 1 S5 Output O = 0 S4 Output O = 1 S6 Output O = 1 S2 Output O = 0 S1 Output O = 1 S7 Output O = 0
S2 Output O = 1 S0 Output O = 1 S5 Output O = 1 S1 Output O = 1 S4 Output O = 1 S2 Output O = 1 S7 Output O = 1 S2 Output O = 1
Fig. 9.26
9.8.2
Implication Table
The last method of state reduction is implication table. Table 9.26 shows a state table of a typical sequential circuit. The implication table may be constructed by listing all the states vertically except the ﬁrst one and all the states horizontally except the last one. Figure 9.26 shows the implication table of state Table 9.26. The implication table represents all possible combinations of state pairs and each cell of implication table is used as the testing ground for equivalent of a state pair. For example, the ﬁrst down lefthand cell at the intersection of S0 and S7 is the place where these two states are test for equivalence. For testing the equivalence, there are two different conditions. The ﬁrst condition is that the next state outputs of a pair of states must be identical. Applying this condition, all the cells which can not be equivalent should be cross marked on the implication table. For example, S0 and S1 may not be equivalent as the next states outputs are 0, 1 and 1, 1 respectively. Consequently, the cell at the intersection of S0 and S1 are cross marked. In the same way, all nonequivalent states pairs are cross marked as shown in Fig. 9.27. After that, place all implied pairs of equivalent states in all empty cells of Fig. 9.27. For example, the cell at the intersection S0 and S7 should consist of the implication of both S0 and S7 as S0 and S7 are equivalent states. Similarly, other equivalent implications must be entered in the other empty cells as depicted in Fig. 9.28.
Implication table
Fig. 9.27 Elimination of nonequivalent states pair
375
Fig. 9.28
Insertion of all implied pairs
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When the next states of the two states are the same state for a given input, then the two states are equivalent and put a trick mark inside the cell which represents the said states. For example, at the intersection of S0 and S7, and at the intersection of S2 and S5, we can apply this rule and put a tick mark on these two cells. It is clear from the state Table 9.26 that S2 and S5 states are a pair of lock –in states. S5 can be entered from S2 after receiving a clock pulse. Similarly, S2 can be entered from S5 on the receipt of clock pulse. But, there is no way to exist from these states. Therefore, these two states may be merged and after receiving a clock pulse the sequential circuit must Fig. 9.29 The complete implication table after inserting tick and cross marked be stay in the merged state. This is called lockin states. To leave these lockin states, a reset signal is required. After that, we start testing the implication table row by row, starting from the bottom right hand cell. A cross mark may be entered into a cell which contains implied pairs when either of the implied pairs have already crossed. The cell at the intersection of S4 and S6 should be cross marked as the cell associated with the implied pairs S6 and S7, which are already cross marked. This process will be repeated until no other cells can be crossed out and ﬁnally we can get the ﬁnal from of the implication table as depicted in Fig. 9.29. Figure 9.30 shows the partition listing. Then implication table Fig. 9.30 Partition listing should be examined column by column from right Table 9.27 Redusced state table to left to ﬁnd if there any cells which have not been crossed out. Present Next state In the ﬁrst column of the implication table, the state X=0 X=1 ﬁrst single cell at the intersection of S6 and S7 is S0257 S0257 S0257 crossed out. Therefore, there will be no entry in Output O = 0 Output O = 1 the partition listing of S6. In the second column, the S1 S3 S0257 state pair at the intersection of S5 and S7 have not Output O = 1 Output O = 1 cross marked. Therefore, they are equivalent states S3 S4 S1 and are entered in partition listing of S5. As there Output O = 1 Output O = 1 is no uncrossed entries in the Column 3 and 4, the S4 S6 S4 entry S5, S7 will be repeated for partition listing S3 Output O = 1 Output O = 1 and S4. S6 S1 S0257 We can see in the ﬁfth column that there are Output O = 1 Output O = 1 two uncrossed cells which are intersection of S2, S7
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377
and S2, S5 respectively. These two cells are equivalent. In the last column, we ﬁnd that there are three uncrossed cells S0, S7; S0, S5; and S0, S2. These three cells are also equivalent. Therefore, the ﬁnal partition listing will be P = (S0 S2 S5 S7) (S6) (S4) (S3) (S1). Table 9.27 shows the reduced state table. Determine the minimal state table for a synchronous sequential circuits as given in Table 9.28 using (a) Caldwell’s merging rules and (b) Partitioning
Example 9.9
Table 9.28
Present state S0 S1 S2 S3 S4 S5 S6
Next state X=0
X=1
S1 Output O = 1 S3 Output O = 1 S5 Output O = 1 S0 Output O = 1 S0 Output O = 1 S0 Output O = 1 S0 Output O = 0
S2 Output O = 1 S4 Output O = 1 S6 Output O = 1 S0 Output O = 0 S0 Output O = 1 S0 Output O = 1 S0 Output O = 1
� Table 9.29
Present state S0 S1 S2 S3 S45 S6
Minimal State Table
X=0
Next state X=1
S1 Output O = 1 S3 Output O = 1 S45 Output O = 1 S0 Output O = 1 S0 Output O = 1 S0 Output O = 0
State table
S2 Output O = 1 S45 Output O = 1 S6 Output O = 1 S0 Output O = 0 S0 Output O = 1 S0 Output O = 1
Solution
(a) In Caldwell’s merging rules, the equivalence of states can be deﬁned by the statement that “Two states Sm and Sn are equivalent if both have the same next states and also both have equal outputs”. It is depicted in Table 9.28 that states outputs for S0, S1, S2, S4 and S5 are equal but the next states are unequal. Consequently, S0, S1, S2, S4 and S5 can not be merged together. But, only states S4 and S5 can be merged as both have the same next states and also both have equal outputs. After merging S4 and S5 states, we ﬁnd the minimal state table as shown in Table 9.29. (b) In partitioning method, the ﬁrst partition is made by placing all those present states in the same section of partition, when the outputs are identical for all possible inputs. The states outputs for S0, S1, S2, S4 and S5 are equal and these states are put in the same section. Outputs of state S3 and S6 are different and they are placed in two different sections of partition.
Therefore, the ﬁrst partition is P1= (S0, S1, S2, S4, S5) (S3) (S6) In the ﬁrst partition, when X = 0 or X = 1, the next states for S4, and S5 are all in the same section of P1. But when X = 0, the next states for S0, S1, S2 are S1, S3 and S5 respectively. As next states are different, the state S0,
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S1, and S2 must be in a different section of partition. Then the ﬁnal partition is P2 = (S0) (S1) (S2) (S4, S5) (S3) (S6) and the minimal state table is shown in Table 9.29.
9.9 ASYNCHRONOUS SEQUENTIAL CIRCUITS Just like synchronous sequential circuits, the asynchronous sequential circuits are also feedback circuits. The difference between synchronous and asynchronous sequential circuits is that there is no memory element in the asynchronous sequential circuits and they are not clock driven. Due to the absence of memory element, the implementation of the excitation Boolean function must be hazard free. If the designer design the circuit based on the minimised Boolean functions, there will be some possibility of static hazard in the circuit. Therefore, during the implementation of any asynchronous sequential circuit, the designer should design the circuit in hazardfree form. The block diagram of asynchronous sequential circuit is shown in Fig. 9.31. This block diagram consists of a combinational logic circuit, n input variables X1 X2 …..Xn, m output variables O1 O2…Om, k internal states y1 y2 …yk, and delay elements on feedback paths. The delay element is a gate circuit which can provide propagation delay. The present state and next state variables in asynchronous sequential circuit are known as secondary variables and excitation variables respectively. y1 y2 …yk are present state (secondary) variables and Y1 Y2 ….Yk are next state (excitation) variables.
Fig. 9.31 Block diagram of asynchronous sequential circuit
The main characteristic of asynchronous sequential circuit is that only one input is allowed to change at any particular instant. Simultaneous changes of two or more input variables are prohibited. This is obviously different from the behaviour of a synchronous sequential circuit, where the change of input variables are allowed arbitrarily and state changes are activated by the repetitive clock pulse. There are two different conditions of any asynchronous sequential circuit, namely stable and unstable states. At any instant, the state of the circuit is deﬁned by the logical values of the input variables and the present state of the circuit. When the next state is same as the present state, the circuit is in a stable state. For a set of input variables, the circuit will be in stable state, if yi = Yi , where i = 1, 2…..k. Therefore, circuit is stable only when the present state is equivalent to the next state. When the circuit is in stable state, there is a change in the input variable which forces the combinational logic circuit to generate the new set of next variables. Hence, yi ≠ Yi and the circuit operate in unstable state for time being. After certain time delay, yi becomes Yi and the circuit again operates in the next stable state.
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Therefore, due to change an input variable, the circuit, can move to an unstable sate and after some time, the state variables are updated with their new values so that the next state has become the present state and stability must be restored. Consequently, transition of asynchronous sequential circuit from one state to next state takes place only in response to the change in input signals one at a time and only when the circuit operate in stable state. This type of operation is called as fundamental mode. During design of asynchronous sequential circuits, the designer should take care of static hazards, dynamic hazards, and races, in order to avoid circuit malfunction.
9.10 DESIGN PROCEDURE OF ASYNCHRONOUS SEQUENTIAL CIRCUITS The design procedure of asynchronous sequential circuits is difﬁcult than that of synchronous sequential circuits as the timing problems are involved in the feedback (delay) path. In any synchronous sequential circuit, timing problems are eliminated by triggering all ﬂipﬂops with the positive edge or negative edge of clock pulse. The asynchronous sequential circuits are not clock driven and the state of asynchronous sequential circuits is allowed to change instantaneously after the input changes. Therefore, during deign of asynchronous sequential circuits, the designer should take care of that the input signals change one at a time when the circuit in a stable state only. The main aim of design is that to develop hazardfree next state functions and output equations. The design steps of asynchronous sequential circuits are given below: Step1 Deﬁne the problem with proper speciﬁcation. Step2 Draw a block diagram for the proposed design with mention all the inputs and outputs. Step3 Draw a state transition diagram from the speciﬁcation. Step4 Draw state table and state transition table. Step5 Plot the K map for next state variables and outputs using present state variables and other inputs. Step6 Derive the Boolean expressions for the excitation variables and outputs as a function of the input and secondary variables. Step7 Implement the excitation equations and the output equations with the help of logic gates. For example, consider a D latch with two inputs: one is DATA and other is LOAD. The D latch has also one output O. Figure 9.32 shows the state diagram of D latch. Table 9.30 is state table of Fig. 9.32. After substituting the following two states S0→0, and S1→1 in Table 9.30, we obtain the transition Table 9.31. The Kmap of the excitation Table 9.31 is shown in Fig. 9.33. Based on the Kmap as shown in Fig. 9.33, we can ﬁnd the excitation equation and output equation. The excitation equation is Q* = LOAD.Q + DATA.Q + LOAD.DATA and the output equation is O=Q. The implementation of D latch is illustrated in Fig. 9.34. Table 9.30
Present state (S) S0 S1
State table of D latch
Inputs (LOAD, DATA) 00 01 10 11 S0 S1
S0 S0 S1 S0 Next State (S*)
S1 S1
Table 9.31
Present state (Q) 0 1
Excitation table of D latch
Inputs (LOAD, DATA) 00 01 10 11 0 1
0 1
0 0
Next State (Q*)
1 1
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Fig. 9.32 The state diagram of D latch
Fig. 9.33
Example 9.10
Kmap of Table 9.31
Fig. 9.34
D latch
Design an asynchronous sequential circuit as shown in Fig. 9.35. The circuit has two inputs A B, present state Q, next state Q* and one output O. The excitation table of the circuit is illustrated in Table 9.32.
Fig. 9.35
Block diagram of asynchronous sequential circuit
� Solution The Kmap for next state Q* and output O are depicted in Fig. 9.36 (a) and (b) respectively. Based on the – Kmaps, we can ﬁnd the excitation function and output equation. The excitation equation is Q* = AB + A Q – – and the output equation is O = A B + A Q. The implementation of excitation function and output equation is shown in Fig. 9.37.
(a)
(b) Fig. 9.36
(a) Kmap for Q* (b) Kmap for O
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Fig. 9.37
Logic diagram of asynchronous sequential circuit
Example 9.11 Design an asynchronous sequential circuit for the following behaviour The circuit has two inputs A and B and two outputs O0 and O1. When both inputs are 0, outputs O0, O1 are 0 and Q* = Q. When both inputs are 1, outputs O0, O1 are 1 and Q* = Q. If Q = 0, either A = 1 or B = 1, output O0= – – 0 and O1= 1 and Q* = Q. If Q = 1, either A = 1 or B = 1, output O0= 1 and O1= 0 and Q*= Q. �
Solution
Fig. 9.38 Table 9.32
Present state (Q) 0 1
The block diagram of asynchronous sequential circuit is shown in Fig. 9.38. Table 9.33 shows the present state, next state and outputs of the asynchronous sequential circuit according to circuit behaviour. The Kmap for next state Q* , outputs O1 and O0 are depicted in Fig. 9.39 (a), (b) and (c) respectively. The excitation function and output equations can be obtained from the Kmap. The – – – excitation function is Q* = BQ + B Q, output equations are O1= AB – – + BQ, and O0 = AB + BQ. Figure 9.40 shows the implementation of asynchronous sequential circuit by using logic gates.
Block diagram
The state table with output
00
Table 9.33
Inputs (A, B) 01 10 11
The state transition table with outputs
Present state (Q)
0/0 0/1 0/0 1/0 1/1 1/1 0/0 1/0 Next State/Output (Q*/O)
00 01
00
Inputs (AB)
00 01 10 11
00
01
10
11
0/00 1/10 01/0 10/0 1/00 0/01 0/01 1/11 Next State(Q1* Q0*)/Output(O)
Table 9.34 The state table with output
Present state (Q1Q0)
Inputs (AB) 01 10
11
00/0 00/0 01/0 10/0 01/1 11/1 01/1 11/1 00/1 00/1 XX/1 11/1 10/0 10/0 11/0 11/0 Next State(Q1* Q0*)/Output(O)
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Fig. 9.39 (a) Kmap for Q*
(b) Kmap for O1
(c)K map for O0
Fig. 9.40 Logic diagram
Example 9.12
Design an asynchronous sequential circuit for the state diagram as shown in Fig. 9.41.
Consider four states S0=00, S1=01, S2=10 and S3=11. Assume two inputs A and B and one output O.
Sequential Circuits Design
Fig. 9.41
383
State diagram
� Solution The state table of state diagram as shown in Fig. 9.41 is given in Table 9.34. The Kmap the state table is shown in Fig. 9.42. Then derive the excitation functions and output equation are as follows Q*1 = AB + Q1Q0 + BQ0 – — Q*0 = AB + Q1Q0 + AQ1 + AQ0 — — O = Q1Q0 + Q1Q0 = Q1 Q0 The implementation of the asynchronous sequential circuit using combinational logic circuit elements is shown in Fig. 9.43.
Fig. 9.42 K Map of the transition Table 9.32
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Fig. 9.43 Implementation of asynchronous sequential circuit
9.11
ALGORITHMIC STATE MACHINES (ASM)
In any digital system, digital data are manipulated to perform arithmetic and logic operations, shifting, counting and other data processing operations. Generally, these operations are practically implemented using adders, decoders, multiplexers, registers, shift registers and counters ICs. The logic design of digital circuits consists of controller and datapath. The datapath is related with the design of digital circuits which performs the dataprocessing operations. The controller design is also related with control circuit which generate control command signals as per requirement of digital circuit. Figure 9.44 shows the block diagram of a digital system which indicates the relationship between controller and datapath. Usually the control logic generates the signals for sequencing the operations in the datapath, where data is processed sequentially. Initialisation commands are generated from controller to reset the digital system. After that, when external input and status control signals are applied, the digital system changes its present state to next state and perform other speciﬁed operations. The operations of controller and data processing unit (datapath) of any digital system can be represented by algorithm. Any algorithm should have ﬁnite number of procedural steps through which the problem will be implemented using digital ICs. A ﬂow chart of any algorithm Fig. 9.44 Controller and datapath interaction for hardware implementation can convert the
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statement into an information diagram which speciﬁes the sequence of operations incorporating with all necessary conditions for excitation. The special ﬂow chart which can be developed speciﬁcally to explain algorithms of digital system for hardware implementation is called an algorithmic state machine. Hence, the alternative method of sequential circuit design is known as the algorithmic state machine (ASM). While this technique is used to design any digital electronics circuit, the state diagram is constructed in the form of a ﬂow chart. In this section ASM can be explained with a sequence of actions which are designed to initiate a set of state transitions and outputs for speciﬁed data inputs.
9.11.1
ASM Chart
Usually the ﬂow chart is the simplest way to represent the sequence of operations and necessary conditions for an algorithm graphically. A conventional ﬂow chart explains the sequence of procedural steps and decision paths for an algorithm without concern for their relationship but the ASM chart describes the sequence of events. The ASM chart is adapted to specify the control sequence and data processing operations in a digital system. If we compare between state diagram and ASM chart, we ﬁnd that ASM charts are slightly longer than state diagram. State diagrams are compact but difﬁcult to understand. Actually, ASM charts describe the sequential operations simply compared to state diagrams. As the structured approach is followed in the construction of ASM chart, it is very easy to represent the complex digital systems compared to state diagram representation. The three basic elements of the ASM chart are state box, decision box and conditional output box as depicted in Fig. 9.45. The operation of state box, decision box and conditional output box are explained in this section.
State Box In ASM, the rectangular box is used to represent each state for a period of one state time which may be for one clock period or for an integral number of clock periods in a clock driven machine. The state is identiﬁed by a binary code which is a unique combination of the state variables. Each state should have a name or number for proper identiﬁcation. There is one entry path and one exit path for each state. The exit path may be connected directly to another state box or to one or more decision boxes. The output is independent of the inputs and simply depends on the present state of the circuit. The outputs are indicated in the rectangular box. The state output is active while the machine remains in the state, and is present for the period of the state time. Figure 9.46 (a) shows an example of state box. This state has a symbolic name S1 and the binary code is assigned to it is 001. Inside the box, it is written R ←0 which represents the register R will be cleared to 0. The START_OP name inside the Box represents an output signal which starts any speciﬁed operation. The register performs storage data, shift registers, counters, increment, set and reset ﬂipﬂop, clear, 3 decrement, addition, and data transfer operations. The symbolic notation of register operations is depicted in Table 9.35. Table 9.35
Different register operations
Description Clear register R Transfer the content of register A into Register B Increment register A by 1 Decrement register A by 1 Addition of resister A and B Subtract the content of B from A Set ﬂipﬂop F to1
Symbolic Notation R←0 B←A A ←A+1 A ←A–1 A ←A+B A ←A–B F ←1
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Decision Box The decision box consists of a Boolean expression which generates a conditional output based on the machine inputs. The ASM decision box is illustrated in Fig. 9.45(b) which has one input path and three exit paths which will link to other state boxes. When the logical value of the condition is 1, the true exit path is followed by ASM as shown in Fig. 9.46(b). If the logical value of the condition is 0, the false exit path is followed. These two paths can be identiﬁed by 1 and 0 as shown in Fig. 9.46(b). The exit paths of decision box can lead directly to another state box or to one or more decision boxes.
Fig. 9.45
ASM chart (a) state box (b) decision box (c) condition box
Fig. 9.46 Example of ASM chart (a) state box (b) decision box (c) condition box
Conditional Output Box The output depends on the present state of the circuit and the input signals. This is represented by roundended rectangle boxes. Actually, the round corners can differentiate the conditional output box from the state box. The input path to a conditional output box is always comes from the output of a decision box and the condition required to generate an active output must be speciﬁed. The example of conditional output box is depicted in Fig. 9.46(c). If A is 0, register R will be cleared. While A = 1, R will be unchanged. Either A = 0 or A = 1, the next state is S2 which is represented by binary code 010 and the content register B will be transferred to register C.
9.11.2
ASM Block
The ASM block consists of at least one state box, and one or more decision boxes and conditional output boxes which are connected with the exit path of decision box. Each ASM block should have one entry path and more number of exit paths which are represented by the structure of the decision boxes. Figure 9.47 shows a typical ASM chart which consists of one state box, two decision boxes and one conditional output box.
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Initially, the ASM will stay at state S1 and it is represented by binary code 001. The output in this state is A=A+1. The output of state box is associated with two decision boxes and one conditional output box as depicted in Fig. 9.47. Any ASM block without any decision or conditional output boxes can form a simple block. The operations within the state, decision boxes and conditional output boxes are executed with in a clock pulse while the system is in S1 state. After the clock pulse, the system controller transfers the sate S1 to any one of the next states such as S2, S3, and S4. The binary code of states S2, S3, and S4 are represented by 010, 011, and 100. When B = 0, the register C will be cleared and the state of system will be 100. If B = 1 and D = 0, the system operates in S3 state other wise output state will be S2.
Fig. 9.47
9.11.3
ASM block
Algorithmic State Machines Design
Any algorithm state machine should have ﬁnite number of steps and each step must be properly deﬁned. All steps should be represented in such a order that the sequential machine ﬂow chart states the overall behaviour of sequential machine. The ASM design of any digital problem can be done by the following steps: • Write the design speciﬁcation. • Convert the problem statement into algorithmic ﬂow chart. • Draw Kmap. • Find minimised next state and output functions. • Implementation of digital circuit. Example 9.13
Design a mod7 counter using ASM.
� Solution The counting sequence of mod7 counter is 000, 001, 010, 011, 100, 101 and 110. The ASM chart for mod7 counter is shown in Fig. 9.48. There are seven steps assigned by state names S0, S1, S2, S3, S4, S5 and S6
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respectively. Table 9.36 shows the present state and next state of mod7 counter. Assume that the present state variables are A, B, and C and the next state variables are Z3, Z2 and Z1. Figure 9.49 shows the Kmap which is used to derive the next state functions. The expressions for Z1, Z2 and Z3 are Z1 = –– –– – – – – – A C + BC , Z2 = A BC + BC and Z3 = AB + A BC. The implementation of mod7 counter using ASM is illustrated in Fig. 9.50.
Table 9.36
Present state and next state of mod7 counter
A
Present state B
C
Z3
Next state Z2
Z1
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 0
0 0 0 1 1 1 0
0 1 1 0 0 1 0
1 0 1 0 1 0 0 Fig. 9.48 ASM chart of mod7 counter
Fig. 9. 49 (a) Kmap for Z1
(b) Kmap for Z2 (c) Kmap for Z3
Sequential Circuits Design
Fig. 9.50
Example 9.14
389
Logic diagram of mod7 counter
Design a 2bit synchronous up/down counter
� Solution It can be assumed that initial count value of the counter is 00. When the 2bit synchronous UP/Down counter control input (UP) is high, the counter should count upward direction on every clock pulse and the counting sequence will be 00, 01, 10, 11, and 00. If the UP/Down counter control input (UP) is low, the counter starts counting in down ward direction on every clock pulse such as 00, 11, 10, 01,00. To develop the ASM chart, the detail sequence of counter operations must be represented sequentially. Figure 9.51 shows the ASM chart for 2bit synchronous UP/Down counters. Present state and next state of 2bit UP/Down counter are illustrated in Table 9.37 where the present state variables are A and B, and the next state variables are Z2 and Z1. Figure 9.52(a) and (b) show the Kmap for Z1 and Z2 respectively. The expressions for Z1 and Z2 are as follows – Z1 = B and – – —– –– – – –– –— – – Z2 = A B U P + ABUP + A BUP + ABUP = (A B + AB)UP + (A B + AB)UP = ––—– — — A B UP + (A B)UP. The implementation of 2bit synchronous Up/Down counter using ASM is illustrated in Fig. 9.53. Table 9.37
Present state and next state of 2bit UP/Down counter
Present State A B 0 0 1 1
0 1 0 1
Next State when UP=1 Next State when UP=0 Z2 Z1 Z2 Z1 0 1 1 0
1 0 1 0
1 0 0 1
1 0 1 0
Fig. 9.51 ASM chart for 2bit UP/Down counter
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Fig. 9.52
(a) Kmap for Z1
(b) Kmap for Z2
Fig. 9.53 2bit synchronous UP/Down counter
Example 9.15
Draw ASM chart of a 4:1 multiplexer.
� Solution Figure 9.54 shows the symbolic representation of 4:1 multiplexer, which has two select lines S1 and S0 and four inputs X1, X2, X3 and X4 and one output F. The functional table of 4:1 Mux is illustrated in Table 9.38. When S1= 0 and S0 = 0, output F = X1. Similarly, depending upon the select inputs, output is available at output F. The ASM chart of 4:1 multiplexer is depicted in Fig. 9.55. Table 9.38 Functional Table of 4:1 MUX
S1
S0
Output
0 0 1 1
0 1 0 1
F=X1 F=X2 F=X3 F=X4
Fig. 9.54
Symbol of 4:1 MUX
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391
Fig. 9.55 ASM chart for 4:1 MUX
Example 9.16
Draw ASM chart of full adder.
Table 9.39
A 0 0 0 0 1 1 1 1
Inputs B 0 0 1 1 0 0 1 1
� Solution
Full adder
Cin
F
0 1 0 1 0 1 0 1
0 1 1 0 1 0 0 1
Outputs Cout
Fig. 9.56
0 0 0 1 0 1 1 1
The full adder is used for adding two binary digits A and B with carry input Cin. There are eight combinations of A, B and Cin as given in Table 9.39. After addition, the outputs are sum F and carry output Cout. Figure 9.56 shows the ASM chart of full adder.
ASM chart of full adder
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Example 9.17 Develop ASM chart for the following conditions of a digital circuit: The output of digital circuit depends upon the trigger pulse as well as inputs X1 and X2. Assume that after application of ﬁrst trigger pulse, output =1 which is independent of inputs X1 and X2. If X1 X2 = 00, 01, and 10, output = 0 after application of second positive edge trigger pulse. When X1 X2 = 11 and second positive edge trigger pulse is applied, output =1. � Solution The transition from one state to the other state takes place at rising or positive edge of the clock pulse. After the ﬁrst rising edge of the clock pulse, the output is high. As the output does not depend on input signals, the ﬁrst rectanglebox has a value Z=1. The output is low after the second rising edge of the clock pulse when X1 X2 = 00, 01, and 10 and the output is high for the condition X1 X2 = Fig. 9.57 ASM chart 11. The ASM chart for the above operations is shown in Fig. 9.57. This block diagram can be represented in the ASM chart by drawing a decision box which ANDs both the inputs. When the result of ANDing X1 and X2 is 1, the output is high and rectanglebox contains Z=1. If ANDing X1 and X2 is 0, output is low and rectanglebox contains Z=0.
SUMMARY Generally, any sequential circuit consists of a combinational logic circuit and memory elements. The output of combinational logic circuit is stored in memory elements. Memory elements output feedback into combinational logic circuit and used as input variables. The output of combinational logic circuit is function of the external inputs and inputs from memory elements. In this chapter, the modeling and classification of sequential circuits has been discussed. The operation of Mealy machines and Moore machines, function of state table, state diagram and state equations are also incorporated. Designs of synchronous and asynchronous sequential circuits with examples are discussed elaborately. In this chapter, the operation of algorithmic state machines (ASM) are also incorporated with some examples.
MULTIPLE CHOICE QUESTIONS 1.
2.
The sequential circuits consists of combinational logic as well as memory elements (a) Combinational logic as well as memory elements (b) Combinational logic only (c) Memory elements only (d) None of these The example of sequential circuit is
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Sequential Circuits Design (a) (b) 3.
4.
5.
Counter Shift register
The sequential machine is a (a) Feedback system (b) Nonfeedback system
(c) (d)
Combinational logic circuit 7 segment display
(c) (d)
Feedback and nonfeedback system None of these
The Moore machine is deﬁned by the equations (a) Next state = F (Present state, Inputs) and Output = G (Present state) (b) Next state = F (Inputs) and Output = G (Present state) (c) Next state = F (Present state) and Output = G (Present state) (d) Next state = F (Present state, Inputs) The Mealy machine is deﬁned by the following equations. (a) Next state = F (Present state, Inputs) and Output = G (Present state, inputs) (b) Next state = F (Present state) and Output = G (Present state, inputs) (c) Next state = F (Present state, Inputs) and Output = G (inputs) (d) Next state = F (Inputs) and Output = G (Present state, inputs)
6.
A synchronous Melay machine has (a) An input decoder, memory elements and an output decoder (b) An memory elements and an output decoder (c) An input decoder and an output decoder (d) An input decoder and memory elements
7.
The asynchronous Melay machine consists of (a) An input decoder and an output decoder (b) An input decoder, memory elements and an output decoder (c) Memory elements and an output decoder (d) An input decoder and memory elements
8.
A synchronous Moore machine has (a) An input decoder, memory elements and an output decoder (b) A memory elements and an output decoder (c) An input decoder and an output decoder (d) An input decoder and memory elements
9.
The asynchronous Moore machine consists of (a) An input decoder and an output decoder (b) An input decoder, memory elements and an output decoder (c) Memory elements and an output decoder (d) An input decoder and memory elements
10. 11.
Reduced state diagram of any state table can obtained from (a) Inspection (b) partitioning (c) implication table
(d) all of these
A sequential circuit can be designed with the help of (a) State Table (b) State diagram (c) Kmaps
(d) all of these
394 12.
Digital Electronics: Principles and Applications When the output of a sequential circuit depends on the present input as well as previous output states, the circuit is called (a) Moore machine (b) Mealey machine (c) Sequential circuit (d) all of these
REVIEW QUESTIONS 9.1
9.2 9.3 9.4
9.5
(a) Deﬁne sequential circuit. (b) Discuss the classiﬁcation of sequential circuit with examples (c ) Write difference between synchronous and asynchronous sequential circuit (a) Explain Mealy and Moore machines. (b) Write difference between Mealy and Moore machines (a) Discuss state table, state diagram and state equations of a ﬁnite state machine with example. (b) Write design procedure of a ﬁnite state machine. A sequential circuit has two inputs X and CLOCK and one output O. Incoming data are examined in consecutive groups of three digits and the output O=1 for the following three input sequences 000, 010 and 111. Draw a state diagram and implement the sequential circuit using D, T and JK ﬂipﬂops. Find the minimal state table for sequential machines as given in Table 9.40. Table 9.40
State Table
Present state X=0 S0 S1 S2 S3 S4 S5 S6
9.6
Design a sequential circuit for the state Table 9.41 using JK ﬂipﬂops. Assume two inputs are A and B, output of the sequential circuit is O, present state of JK ﬂipﬂops = Q1Q0 , Next State of JK ﬂipﬂops = Q1* Q0*.
Next state X=1
S0 Output O = 0 S3 Output O = 0 S0 Output O = 0 S5 Output O = 0 S1 Output O = 1 S5 Output O = 0 S0 Output O = 0
S1 Output O = 0 S2 Output O = 1 S3 Output O = 0 S4 Output O = 1 S2 Output O = 0 S4 Output O = 1 S1 Output O = 0 Table 9.41
Present state (Q1Q0)
00
Inputs (AB) 01 10
00
01/1
01 10 11
10/1 00/1 00/0 10/1 11/0 00/0 00/1 11/0 01/0 00/1 00/1 01/1 Next State (Q1* Q0*)/Output(O)
00/0
00/1
11 01/0
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Sequential Circuits Design 9.7
The state diagram of a sequential circuit is given in Fig. 9.58. Draw the state table for Fig. 9.58 and implement using T ﬂipﬂops. Assume two inputs are A and B, output is O.
Fig. 9.58
9.8
The state diagrams of sequential circuits are given in Fig. 9.59 and Fig. 9.60. Design the sequential circuits using ﬂipﬂops and combinational logic circuit.
Fig. 9.59
9.9 9.10
Fig. 9.60
Draw the state diagram and state table of a updown counter. Design the UpDown counter using T ﬂipﬂops. A sequential circuit has one input and one output. The state diagram is shown in Fig. 9.61. Design the circuit with JK, D and T ﬂipﬂops.
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Fig. 9.61
9.11 9.12 9.13
9.14
9.15
Design a 5 state sequential machine whose sequential states are: 000, 001, 010, 110, 111, 000….. Assume initial state is 000. Why state reduction is necessary in sequential circuit design? What are the different methods of state reduction? Explain implication table method of state reduction with an example. Explain algorithmic state machines with examples. Discuss how the ASM chart differs from a conventional ﬂow chart. Draw the ASM chart of (a) 8:1 Multiplexer and (b) 4bit synchronous Up/Down counter. A synchronous counter is controlled by two input signals A and B. The counter does not operate, if A = 0 and B = 0. When A = 0 and B = 1, the counter operates as a mod four counter. If A=1 and B=0 the counter operates as a mod eight counter. Draw an ASM chart and design a circuit using D ﬂipﬂops and NAND gates to satisfy the above speciﬁcation. A sequential circuit waveform generator generates four output waveforms which are controlled by input signals X1 and X2. If X1= 0 and X2= 0, the output wave form is high for a period of three clock cycles and low for a period of one clock cycle. When X1= 1 and X2= 0, the output wave form is high for a period of two clock cycles and low for a period of two clock cycles. If X1= 0 and X2= 1, the output wave form is low for a period of three clock cycles and high for a period of one clock cycle. When X1=1 and X2=1, the output wave form is high for a period of one clock cycle and low for a period of three clock cycles. Develop an ASM chart for the waveform generator. Draw a state table and implement the waveform generator using D ﬂipﬂops.
CHAPTER
10 MULTIVIBRATORS 10.1 INTRODUCTION The output of sequential logic circuits depends on the present input states and previous history. The logic circuits operation can be controlled by a train of clock pulses. When the clock pulses are applied, the outputs of sequential logic circuit changes from one state to next state. These clock pulses are generated by clock generators or oscillators. The clock generators are frequently called as astable or free running multivibrator. In this chapter, clock oscillators using TTL and CMOS, astable, monostable, bistable multivibrators and their applications, operation of 555 timer and its applications have been explained. The operation of 556 timer IC, nonretriggerable monostable multivibrator IC 74121, retriggerable monostable multivibrator IC 74122 and IC 74123 are also incorporated.
10.2 CLASSIFICATION OF MULTIVIBRATORS There are three types multivibrators, namely astable multivibrator, monostable multivibrator, and bistable multivibrator. These multivibrators are most commonly used in timing applications.
Astable Multivibrator Astable multivibrator is known as free running multivibrator. It has two quasistable states and it continues to oscillate between two stable states. This multivibrator has no stable state and external trigger pulses are not required to change the states. This device can be used to generate square wave and the time duration depends upon circuit parameters. The continuously generated pulses are used as clock pulses in ﬂipﬂops, registers, counters and other digital circuits where the clock pulse is required for operation. Figure 10.1 shows the output voltage waveform of an astable multivibrator which oscillate between 0V and 5V without Fig. 10.1 Astable multivibrator application of any trigger pulse. Monostable Multivibrator Monostable multivibrator has a single stable state and a quasistable state. In this multivibrator, trigger signal is applied to switch from stable state to quasistable state. After a short time, the circuit reverts back to its stable state. Hence, a single output pulsed is generated when a trigger pulse is applied to it. Therefore, it is known as one shot or single shot multivibrator circuit. The output pulse width can be controlled by internal circuit parameters and trigger pulse has no control over the pulse width of output waveform. As a result, a small pulse width or a sharp trigger pulse can be converted into an output of longer pulse width. So, this multivibrator is also called as pulse stretcher. Figure 10.2 shows the output voltage waveform and trigger signal of a monostable multivibrator. At time
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t1, when the trigger pulse is applied, output of monostable multivibrator changes from 0V to 5V and its output stay at 5V for certain time T1 depending on circuit parameters. After T1 time, output changes from 5V to 0V without application of any trigger pulse.
Fig. 10.2 Monostable multivibrator
Bistable Multivibrator A bistable multivibrator has two stable states. When external trigger pulses are applied, the multivibrator changes one stable state to other stable state. Therefore, two external triggers are required for this multivibrator and bistable multivibrator is not an oscillator. The output voltage waveform and trigger signal of a monostable multivibrator are illustrated in Fig. 10.3. Assume the two stable states are 0V and 5V and initially multivibrator output is 0V. At time t1, when the trigger pulse is applied, output of bistable multivibrator changes from 0V to 5V and its output continue at 5V for T1 time depending on the next trigger pulse. At time t2, if the next trigger pulse is applied, output changes from 5V to 0V.
Fig. 10.3 Bistable multivibrator
Figure 10.4 shows the block diagram of a multivibrator, which consists of two inverting ampliﬁers A1 and A2 and two networks N1 and N2, which are used to develop a regenerative feedback loop. The type of multivibrator depends on the nature of coupling used in network. If the circuit behaves as bistable multivibrator, N1 and N2 will be resistance. In monostable multivibrator N1 or N2 will be capacitance. But in astable multivibrator N1 and N2 are capacitance. The operation of astable, monostable and Fig. 10.4 Block diagram of multivibrator bistable multivibrators are explained in this chapter.
10.3 CLOCK OSCILLATOR USING BJTs Generally, clock oscillator is a two stage switching circuit in which the output of the ﬁrst stage is fed to the input of the second stage and vice versa. The outputs of both the stages are complementary. Figure
Multivibrators
399
10.5 shows the clock oscillator using NPN transistors. This free running oscillator generate square wave without any external triggering pulse. The circuit has two states and switches back and forth from one state to another. The switch should remain in each state for a time depending upon the discharging of capacitor through a resistance. Hence, clock oscillators are used to generate clock pulses. The circuit as depicted in Fig.10.5 also behaves as a simple astable circuit. The working principle as follows: Consider that T1 is turned on and T2 is off. The collector voltage of T1 will be approximately zero, and C1 is charging through R1 and collector Fig. 10.5 Clock oscillator using NPN transistors emitter of T1. The charge on C1 will be increased and the voltage at the base of T2 will also be increased. As T2 is not conducting, the capacitor C2 will charge through R4 and the baseemitter of T1. The charging of C2 will be very fast due to small R4. Consequently, the collector voltage of T2 will be +Vcc with respect to the base of T1 at the end of charging C2. While the base voltage of T2 is more than 0.6 volts, the transistor T2 switch becomes on. The voltage at the collector of T2 will be approximately zero. Therefore, one end of C2 is 0 volts and the other end is a voltage Vcc due to capacitor charging. Then T1 switches off. After that, capacitor C2 starts charging through R2 and the collectoremitter of T2 and its voltage changes from negative to zero and then positive. When C2 charges about 0.6V, T1 will switch on and again the cycle continues. The charging and discharging of C1 and C2 are shown in Fig.10.6 when T1 is turned on and T2 is off. Figure 10.7 shows charging and discharging of C1 and C2 when T1 is off and T2 is turned on.
Fig. 10.6
Charging and discharging of C1 and C2 when T1 is turned on and T2 is off
Fig. 10.7
Charging and discharging of C1 and C2 when T1 is off and T2 turned on
The voltage across capacitor, C and resistor, R must be equal to the applied voltage, Vcc. The mathematical relationship as given below: Q Vcc = IR + C
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Digital Electronics: Principles and Applications
dQ Q dQ + where, Q is charge and I = dt C , dt After integrating the above expression, the voltage across the capacitor can be expressed as V(t) = VCC – (VCC – V0) et/RC. Vcc = R
where, V0 is the voltage across the capacitor at t = 0. In this case, the initial voltage V0 = –Vcc. If t = log2 × RC = 0.693RC, V(t)=0V . In this oscillator, when T1 is on, T2 is OFF and when T1 is off and T2 is ON. The on time and off time are calculated by the following expressions as given below: t1=0.693 R1 C1 and t2 = 0.693 R2 C2. Fig. 10. 8 Wave form of astable multivibrator
The total time period, T = t1+ t2 = 0.693(R1 C1 + R2 C2) If R1=R2=R and C1=C2=C T=1.386 RC and the clock frequency, f = 1/T = 0.721/RC. The cyclic switching of T1 and T2 produces a square wave at the collectors of transistors T1 and T2. The waveform of collector of T1 and T2 is shown in Fig. 10.8. The output of transistor T1 is complement of T2. Therefore this circuit is called as astable multivibrator. The astable multivibrator using PNP transistor is depicted in Fig. 10.9.
Fig. 10.9 Clock oscillator using PNP transistors
Example 10.1
In an astable multivibrator using NPN transistors as shown in Fig. 10.5, the resistance
R1=R2=10K and C1=C2=0.01µF and R3=R4=1Kohm, determine the clock frequency. � Solution t1=0.693 R1 C1=69.3 ms and t2=0.693 R2 C2=69.3 µs. Total time period, T= t1+t2=69.3µs +69.3µs=138.6µs 1 The clock frequency, f = =1/138.6µs =7. 215 KHz t1 + t2
10.4
MONOSTABLE MULTIVIBRATOR USING BJTs
Figure 10.10 shows the monostable multivibrator using BJTs. It has one stable state when T1 is in cutoff and T2 operates in saturation. If the trigger pulse is applied, T2 cutoff and T1 saturation and output will be quasistable. After some time, the circuit returns back to stable state. The detail circuit operation explained below: Just after switch on the power supply, the circuit operates in stable state until a trigger pulse is applied as T1 cutoff and T2 saturation. To operate in saturation, R1 value is selected in such a way that can supply
401
Multivibrators
required base current. The capacitor is charging through R1 and base emitter junction of transistor T2. When T2 is in saturation, the collector output voltage of T2 will be 0V. When a negative trigger pulse is applied, C2 act as short circuit, diode D is forward biased and conducting. Then the voltage at base of transistor T2 will be reduced. Then transistor T2 will operate in cutoff. The collector voltage of T2 increases to +VCC and the base current of T1 increases. The collector potential will be reduced and capacitor C2 starts to discharge through T1. Then T1 is in saturation and T2 is in cutoff. After completely discharged capacitor C2, it starts to charge in the opposite direction through R2. Therefore, potential at the base of T2 starts to increase. When it is 0.7V, T2 starts conducting. So T2 operates in saturation and T1 is in cutoff. Then the circuit again operates in stable state. Figure 10.11 shows the waveform of monostable multivibrator. The duration of pulse width is equal to T = 0.7 RC approximately.
Fig. 10.10
Monostable multivibrator using BJTs
Fig. 10.11
Waveform of monostable multivibrator
10.5 BISTABLE MULTIVIBRATOR USING BJTs Figure 10.12 shows the Schmitt trigger circuit. Schmitt Trigger is also called an emitter coupled binary trigger circuit. It has two stable states that happened when transistor T1 may be ON and T2 OFF or vice versa. When input voltage does not applied to transistor T1, the voltage divider network R3 and R4 along with R2 maintains the base of T2 at a slightly positive potential with respect to emitter. Therefore, T2 operates in the saturation region. Due to the current ﬂow in T2, the voltage developed across the common emitter resistor, and T1 is at cutoff. As the base of T1 is at ground potential, it is negative with respect to the emitter. In this way, the circuit operates in a stable state when Fig. 10.12 Schmitt trigger (bistable multiviinput signal is absent and T2 ON and T1 OFF. The output brator) using BJTs voltage is in the low state. Raising or lowering the bias on T1, it may start the switching action. When a time varying input voltage is applied, as soon as the input voltage reaches a value equal to the sum of the voltages across R3 and R6, T1 will be turns ON as its base is more positive with respect to the
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Digital Electronics: Principles and Applications
emitter. T1 is switched ON and operates in the saturation region. The collector voltage of T1 decreases, which interns the base voltage of T2 is also decreases. Hence, T2 is driven to cutoff until the input voltage is greater than the sum of the voltages across R3 and R4. When T2 is in cutoff, output voltage switches to the difference between Vcc and the voltage across R5. If the input voltage drops below the sum of the voltages across R1 and R6, T1 turns OFF and T2 again turns ON due to regenerative action. Then output voltage Fig. 10.13 Waveform of Schmitt trigger (bistable multireturns to the sum of the voltages across vibrator): Vi = input signal and VT2=output signal R6 and the saturation voltage of T2. Thus, a square wave is produced. The turn ON voltage is usually called the upper trigger point or UTP. The turn OFF voltage is also called lower trigger point or LTP. UTP is always greater than LTP. The UTP = IC(sat) R6 + VBE(ON) and LTP=VBE + IE R6 . If Vcc=12V, UTP=5V, LTP=3V and input voltage is varied in sinusoidal manner, the output waveform of bistable multivibrator is shown in Fig. 10.13.
10.6
ASTABLE MULTRIVIBRATOR USING NOT GATES
Figure 10.14 shows the astable multivibrator or clock oscillator using NOT gates. It consists of two inverters, which are connected, in cascade. Inverter provides a phase shift of 180° between input and output. When a square wave signal is used as input, an inverter output signal will be obtained with 180° phase shift after a very small propagation delay. The propagation delay varies in between 4ns to 60 ns for different TTL ICs. Fig. 10.14 Cascade conIf propagation delay of each TTL NOT gate is tpd=25ns, then a total time nection of two inverters delay = 2 tpd = 2 × 25=50ns will be achieved. When output is used as input V1, then positive feedback is achieved and circuit behaves as feedback oscillators. Then time period will be 2 × 50=100ns for 360° phase shift and frequency of oscillation =1/100 ns=10 MHz. Figure 10.15 shows the waveform of V1, V2 and V0 for two cascade connected inverters. Similarly, astable multivibrator using three and ﬁve NOT gates are shown in Fig. 10.16 and Fig. 10.18 respectively and its waveforms are also depicted in Fig. 10.17 and Fig. 10.19. In these circuits, NOT gates are connected in casFig. 10.15 Waveform of V1, V2 and V0
Multivibrators
403
cade and the output of third and ﬁfth NOT gate are used as input of ﬁrst NOT gate which forms a closed loop system. If propagation delay of each NOT gate is 25ns, then a total 3 × 25=75ns time delay can be achieved for Fig.10.17 and 5 × 25=125ns for Fig. 10.19. Then time period will be 150ns and 250ns and oscillation frequenFig. 10.16 Cascade connection three inverters (NOT gates) cy =1/150ns=6.666 MHz for Fig. 10.17 and f=1/250ns= 4 MHz for Fig. 10.19. The disadvantage of these circuits is that the frequency of output waveform cannot be controlled externally. Actually, external circuits cannot control propagation delay and therefore frequency is uncontrolled. Figure 10.20 shows the modiﬁcation of astable multivibrator circuit using inverters, R and C elements. When the resistance and capacitance are incorporated in the circuit, there will be some control in frequency. When the power is switched on C2 begins Fig. 10.17 Waveforms of three cascaded inverters to charge through R2, the input voltage (NOT gates): V1, V2 and V3 of inverter2 begins to rise, the output will stay high till the input voltage to the inverter INV2 reaches a high logic level voltage. The duration of high output voltage depends upon the time constant C2R2. When input Fig. 10.18 Cascade connection of ﬁve inverters (NOT gates) voltage of INV2 arrives at the high logic level voltage, inverter output changes from high to low. Then capacitor C1 start to charge through R1 and input voltage of INV1 increases. The output of INV1 will be high till the input voltage of INV1 reaches a high logic level voltage. The inverter output voltage changes from high to low when input voltage of INV1 arrive at high logic level voltage. The time period of output voltage depends upon the time constant R1C1.Therefore, alternately capacitors C1 and C2 will be charged. As a result, clock pulses will be produced. The frequency of clock pulse is 1 1 1 f = = = t1 + t2 0.7 R1C1 + 0.7 R2C2 0.7( R1C1 + R2C2 ) where t1 = 0.7R1C1 and t2 = 0.7R2C2 1 1.4 RC As frequency depends on the circuit parameters such as resistances and capacitances, the frequency stability is not good. To increase frequency stability, quartz crystal is used as shown in Fig. 10.21. The oscillator frequency is same as the quartz crystal. The oscillation frequency can be expressed as f = 1/2RC. When the frequency is known, the value of R and C can be determined from this expression. if R1 = R2 = R and C1 = C2 = C, frequency f =
404
Fig. 10.19
Digital Electronics: Principles and Applications
Output waveform of multivibrator using cascade connection of ﬁve inverters, V1= V0, V2, V3 and V4
When CMOS inverters replace TTL inverters, the Fig.10.20 and Fig.10.21 also behave as oscillator or astable multivibrator. Due to different propagation delay of CMOS ICs, the frequency of this oscillator will be different. The output frequency depends on the supply voltage and temperature, but this variation is very narrow range. Therefore, this circuit has very little control over the output frequency. The frequency control range can be increased by using resistances and capacitance as shown in Fig.10.22 and the oscillation frequency can be determined from the expression f = 0.559/RC.
Fig. 10.20
Figure 10.23 shows the astable multivibrator using AND and NOT gate. Initially, consider the capacitor is uncharged and VC = 0V. After switch on the power supply, VC = 0V. So the input voltage of inverter is low, inverter output voltage is high. This high voltage fed to AND gate as input. Then output of AND is high and this voltage applied across the RC circuit and capacitor voltage starts increasing due to charging. The output of inverter will be high till capacitor voltage reaches the high logic level voltage (VH). When VC cross the high logic level voltage VH at time t1, inverter output changes from high to low. Then AND gate output will be low and capacitor starts discharging. The inverter output voltage will be low till capacitor voltage reaches the low logic level voltage (VL). When VC arrives the low logic level voltage VL at time t2,
Modiﬁed TTL clock oscillator
Fig. 10.21
TTL clock oscillator with crystal control
Fig. 10.22
CMOS oscillator
Multivibrators
405
inverter output changes from low to high and the next cycle of operation begins. The voltage across the capacitor VC and output voltage VO are shown in Fig. 10.24.
Fig. 10.23 Astable multivibrator using AND and NOT gates
Fig. 10.24 Voltage across capacitor VC and output voltage VO
10.7 MONOSTABLE MULTRIVIBRATOR USING NAND GATES Figure 10.25 shows the monostable multivibrator using two NAND gates. Trigger pulse is connected with one terminal of ﬁrst NAND gate and other input terminal is used for feedback. Output of this NAND gate is applied to RC circuit. The second NAND is used as a NOT gate. Therefore, both input terminals are shorted and voltage across resistance is applied as input of Fig. 10.25 Monostable multivibrator using NAND gates the second NAND gate. The negative trigger pulse is applied at t=t0, output of Gate1 changes from low to high. Then high voltage applied across RC and capacitor starts to charge. The voltage across resistance and capacitance is shown in Fig. 10.26. At t=t1, trigger pulse changes from low to high and then terminal 1 becomes high but terminal 2 is low. Then output voltage of Gate1 is high. As output voltage is high, the capacitor continuously charged through resistance. At t=t2, capacitor is fully charged and the voltage across resistance becomes zero. Consequently, the output of Gate2 will be high. Therefore, during t2– t0, the output of multivibrator is low.
10.8 MULTIVIBRATOR USING OP AMPs The operational ampliﬁer is generally known as OP AMP which is most commonly used to perform mathematical operations such as addition, subtraction, integration and differentiation etc. This is also used in analog computers. The opamp is a linear ampliﬁer and its dc openloop voltage gain is very high in the range of 103 to 106. The opamp is constructed from several transistor stages namely differentialinput stage, an intermediategain stage and a pushpull output stage. The differential ampliﬁer consists of a pair of bipolar transistors or FETs. The pushpull ampliﬁer transmits a large current to the
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Digital Electronics: Principles and Applications
load and hence has small output impedance. An ideal ampliﬁer has following properties: large input impedance Zin→∞, small output impedance Zout→0, wide bandwidth, inﬁnite gain A→∞, and inﬁnite CMRR (common mode rejection ratio). 741 operational ampliﬁer ICs are readily available in market and most commonly used in analog circuits. This device operates from DC to about 20 KHz, but the highperformance operational ampliﬁers operate up to 50 MHz. Figure 10.27 shows the symbol of an operational ampliﬁer. It has two inputs namely inverting () and noninverting (+) and one output terminal V0. Input voltages V1 and V2 are applied between inverting terminal and ground, and between noninverting terminal and ground respectively. The output voltage VO is measured in between output terminal and ground. The input terminals are known as differential inputs and the output is single ended. The output voltage VO can be expressed as V0 = A Vi, where A = the voltage gain Fig. 10.26 Waveforms of monostable multivibrator of the ampliﬁer and Vi= V1– V2. As A is extremely high, about 200,000, the differential input voltage Vi is very small (Vi →0) and output voltage will be varied between positive and negative saturation voltages +VCC and –VCC respectively. In this diagram, +VCC =+15V (DC) and VCC=15V (DC). The positive and negative voltages are necessary to allow the ampliﬁcation of both positive and negative signals without special biasing.
10.8.1
OP AMPs as Comparators
Fig. 10.27 Symbol of operational ampliﬁer
A comparator compares the value of input signal to a reference voltage. If the input signal voltage is larger than the reference voltage, comparator output will be HIGH. If the input signal voltage is smaller than the reference voltage, comparator output Fig. 10.28 (a) Comparator circuit (b) Characteristics of comparator will be LOW. when Vref=0V (c) Characteristics of comparator when Vref=+ve Figure 10.28 shows the comparator circuit using an ideal operational ampliﬁer. Since the openloop gain of the ideal operational ampliﬁer is inﬁnite, the following equations can be expressed.
Multivibrators
407
Vi>Vref, then Vd>0 and Vo= +VCC ViVref, then Vd 0, circuit output will be +VCC. If Vi is increasing, after some time V+ = V– = bVCC. As Vi is continuously increasing, when Vi is greater than V+, Vd = ( V+ – V–) bVCC to the circuit. This input pulse can be of a very short duration. This input signal is referred to as a trigger signal. On the other hand, the state of the circuit can also be changed by applying a negative pulse with Vi < –bVCC. The center of the hysteresis band can be shifted at different voltage by adding a reference voltage to the circuit as shown in Fig. 10.34. This circuit is also called a Schmitt Trigger. The operation of the circuit is explained in this section. Consider the initial state output is V0. Determine V+ and ﬁnd the range of Vi for which Vd is positive. When Vi in this range, the comparator output state cannot be changed. When Vi is out of range, the sign of Vd changes from positive to negative. Then only the comparator output changes.
Fig. 10.34
(a) Bistable circuit with Vref (b) Complete inputoutput transfer characteristics
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Digital Electronics: Principles and Applications
Here Vd = V+ – V– = V+ – Vi The current through R1 and R2 is i = V+  Vref = iR2 =
Then
V0  Vref R1 + R2
R2 (V0  Vref ) and we get R1 + R2
V+ =
R2 R1 V0 + Vref R1 + R2 R1 + R2
If V0 = VCC and Vd>0;
Vd = V+ – V– = V+ – Vi >0, and the range of Vi for the Schmitt trigger will R2 R1 remain in this state, can be determined form Vi VTL = V+ = Vs + Vref R1 + R2 R1 + R2 As a result, the comparator is in the low state and stays in the same state until Vi >VTL . The range of Vi is VTL < Vi < VTH or
R2 R1 R2 R1 Vs + Vref < Vi < Vs+ + Vref R1 + R2 R1 + R2 R1 + R2 R1 + R2
–
+
Where Vs = –VCC and V s = VCC
The range of Vi is called the dead band. The input signal should pass completely through this band – + before the output of trigger switches from one state to another. The value of Vs and V s are always chosen based on the desired value of the comparator output voltages.
In Fig. 10.34, Vref = 4V and a Vi = 10 sin w t, determine VTL and VTH. Draw the output voltage waveform. Consider R1=R2=1 K ohm.
Example 10.3
� Solution The VTL and VTH voltages can be expressed as R2 R2 R1 R1 VTL = VS + VS+ + Vref ; VTH = Vref R1 + R2 R1 + R2 R1 + R2 R1 + R2 –
+
As R1=R2=1 Kohm, VS = –10V , VS = +10V and Vref = 4V 10 4 10 4 VTL = + =  3V : VTH = + = 7V . 2 2 2 2 Figure 10.35 shows the output waveform when Vref = 4V and a Vi = 10 sinwt
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Multivibrators
Fig. 10.35
10.8.3
OP AMPs as ASTABLE Multivibrator
Fig. 10.36
Bistable circuit with RC feedback
Fig. 10.37
Astable multivibrator
Figure 10.36 shows astable multivibrator which consists of bistable circuit and a RC feedback loop. This circuit can be used to generate square waveform. The operation of the circuit is explained below: The bistable circuit has two states +VCC and –VCC. Initially, consider the output of bistable circuit is +VCC. Then the capacitor is charged through resistance and the voltage across the capacitor increases
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Digital Electronics: Principles and Applications
with a time constant RC. The voltage of capacitor moves toward +VCC. The capacitor voltage is used as input of bistable circuit. When the capacitor voltage is more than the threshold voltage, VTH, the bistable circuit is triggered and its output voltage changes from +VCC to –VCC. As –VCC is applied to the capacitor, the capacitor discharges with the constant RC. Then the voltage of capacitor moves toward –VCC. As soon as the voltage across the capacitor is VTL, the bistable is triggered again and output changes from –VCC to +VCC. In this way, the switching takes place and a square wave will be generated at the output of the bistable circuit. As this circuit has no stable state, it is called astable multivibrator. Therefore, an astable multivibrator is a combination of a Schmidt trigger and an RC circuit. Figure 10.37 shows the astable circuit. This circuit has both negative and positive feedback. In Fig.10.37, resistance R2 and R3 act as a voltage divider. Therefore, the voltage at noninverting R2 V0 terminal is V+ = R2 + R3 The current input to inverting and noninverting terminals is zero (i+=i–=0). So, RC part of the circuit acts independently. Initial voltage across the capacitor is Vc(t0) at t = t0. When voltage Vo is applied to this circuit, the voltage across the capacitor at time t will be Vc (t ) = V0 + [Vc (t0 )  V0 ]e

t  t0 t
as capacitor is charging.
where t = R1C the time constant of the RC circuit. If Vd>0, V0 = Vs+. The RC circuit and voltage divider R2 and R3 operate differently. So, sudden change in output voltage can effect on sudden change in V+ . But V– cannot changes suddenly as the voltage across the capacitor has to be continuously charged or discharged. There is some delay in the response of RC circuit. Actually this delay is used to generate the square wave output. The voltage across capacitor VC and output voltage VO are depicted in Fig.10.38. At t0=0, Vc(t0)=0 and V0 = Vs+ = VCC, the voltage across capacitor can be expressed as Fig. 10.38 Output voltage and capacitor voltage t V = Vc (t ) = Vs  Vs e

t
At time t = 0, V– = 0. When time increases, V– increases. At time t1, capacitor voltage will exceed R2 V+ = Vs+ . Then Vd is negative and it forces the comparator output to become Vs–(–VCC). R2 + R3 The time period of square wave is T=2(t2t1) and its expression can be derived as follows: t  t1
V (t2 ) = VC (t2 ) =  VCC + (VCC V+ (t2 ) =  VCC
R2 R2 + R3
 2 R2 + VCC )e t R2 + R3
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Multivibrators –
Where t2 is the time very close to t2 but smaller than t2. The comparator switches to other state if V–(t2) = V+(t2–). After equating the above equations for V–(t2) and V+(t2–), we get t  t1
VCC + (VCC
 2 R2 + VCC )e t R2 + R3 t  t1
Or (
Or e
 2 R2 + 1)e t R2 + R3
t t  2 1 t
=
R3 2 R2 + R3
=1
Or
=  VCC
R2 R2 + R3
R3 R2 = R2 + R3 R2 + R3
2 R + R3 t2  t1 = ln 2 R3 t
Ê 2 R2 ˆ + 1˜ where t = RC Therefore, T = 2(t2 – t1) = 2t ln Á Ë R3 ¯
Fig. 10.39 Astable multivibrator using operational ampliﬁer with output voltage limiter, Zener diode
10.8.4
In this way, a squarewave is generated by the circuit. The amplitude of the square wave is set by the saturation voltage of the Op Amp (Vs+ and Vs–) and a period T can be determined by the above formula. The period of this oscillator is controlled by R2 and R3. Generally, R2 and R3 are chosen in the range of tens of K ohm. When two zener diodes (VZ1 and VZ2) are connected back to back across the output, the output voltage will be depend on forward biased and reverse biased voltage of zener diodes as shown in Fig.10.39. When V+ is greater than V, the output voltage is positive and can be expressed as V0 = VD + VZ. When V+ is less than V, the output voltage will be negative and can be expressed as V0 = –(VD + VZ) where VD is the voltage across forward bias zener diode and VZ is the Zener voltage.
OP AMPs as MONOSTABLE Multivibrator
Figure 10.40 shows the monostable multivibrator using operational ampliﬁer. This circuit has one stable state (HIGH) and one quasi stable state (LOW). When external trigger pulse is applied, the output changes states from stable state to quasistable state or HIGH to LOW and after certain time depending upon the circuit parameters, output return back to stable state. When no trigger pulse is applied, the input voltage V+ is greater than V and output is V0,
Fig. 10.40
Monostable multivibrator using operational ampliﬁer
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Digital Electronics: Principles and Applications
i.e., positive and the circuit is under steady state condition. In this case, the capacitor C charges through R1, but the capacitor voltage can not able to increase than the forward voltage drop across D1 (VD). The resistance values are selected in such a way that V+ is greater than VD. As soon as a negative trigger pulse is applied, the noninverting input voltage, V+ becomes less than inverting voltage, V and output voltage changes from +V0 to –V0 . The capacitor C stars to charge through R1 and moves towards –V0. In this condition, diode D1 is reverse biased and acts as open circuit. After some time, the voltage across capacitor C, (VC) or V becomes more negative than V+, then the output again Fig. 10.41 Waveforms of monostable multivibrator changes from low quasistable state to high stable state. Figure 10.41 shows the waveform of the monostable multivibator. The voltage across the capacitor can be expressed as VC =  V0 + (V0 + VD )e

t t
where, t = R1C At time t = t1, VC = –bV0 The pulse width duration is T and can be expressed as Ê 1 + VD / V0 ˆ T = t ln Á Ë 1  b ˜¯ where, VD is the forward bias voltage drop across diode D1 and V0 is the output voltage R3 and b = R3 + R2 As V0 >>VD, and if R1=R2, the time period can be expressed as ˆ Ê 1 Á 1 ˜ , as VD / V0 = 0 and b = T = t ln Á ˜ 1 2 Á1  ˜ Ë 2¯ T = 0.69R1C
Multivibrators
Example 10.4
�
415
Figure 10.40 shows monostable multivibrator. Determine the circuit elements for T = 10µs and draw the voltage across capacitor and output voltage waveform. Assume VD= 0.6V and VZ = 9V.
Solution
Ê 1 + VD / V0 ˆ We know that T = t ln Á Ë 1  b ˜¯ and b =
1 R3 = as R2=R3=10 K ohms R3 + R2 2
After substituting VD= 0.6V and VZ=9V=VO , we get Ê ˆ Á 1 + 0.6 / 9 ˜ Ê 1.0667 ˆ = 0.7576t = 0.757 T = t ln Á = t ln Á 76 R1C 1 ˜ Ë 0.5 ˜¯ 1 Á ˜ Ë 2 ¯ As T=10s , 10s = 0.7576R1C If C=10pF, R1=1.32K ohm. Figure 10.42 shows the voltage across the capacitor and output voltage.
Fig. 10.42 Voltage across capacitor and output voltage
10.9
555 TIMER
The pin diagram IC 555 is shown in Fig.10.43. Figure 10.44 shows the block diagram of 555 timers. The 555 timers consist of two voltage comparators, a bistable ﬂipﬂop, a discharge transistor, and a resistor divider network. The resistive divider network is used to set the comparator levels. Since all three resistors are of equal value, the threshold comparator (COMP1) is referenced internally at 2/3 of supply voltage level and the Fig. 10.43 Pin diagram of 555 IC trigger comparator (COMP2) is referenced at 1/3 of supply
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Digital Electronics: Principles and Applications
voltage. The outputs of the comparators are tied to the bistable ﬂipﬂop. When the trigger voltage is moved below 1/3 of the supply, the comparator  2 changes state and sets the ﬂipﬂop driving the output to a high state. The threshold pin normally monitors the capacitor voltage of the RC timing network. When the capacitor voltage exceeds 2/3 of the supply, the threshold comparator (COMP1) resets the ﬂipﬂop, which in turn drives the output to a low state. When the output is in a low state, the discharge transistor is “on”, in that way discharging the external timing capacitor. Once the capacitor is discharged to 1/3 of supply voltage, the timer will again triggered and the next timing cycle will be started.
Fig. 10.44
10.9.1
Block diagram of 555 timer IC
Astable Operation Of 555 Timer
Figure 10.45 shows the 555 timers IC that is operate in astable mode. Here, pin 5 is not used. The three internal resistances (R’s) divide the voltage into three parts. Therefore, V7=2VCC/3 and V2=VCC/3. While the capacitor is charging and the capacitor voltage is between 2VCC/3 and VCC/3, the output of neither of the comparator undergoes a change in the sign of their output, which is negative and therefore logic 0. If the capacitor is charging and its voltage tends to rise above 2VCC/3, the comparator1 (COMP1) output jumps to positive saturation value, i.e. it is logic 1 at R input of ﬂipﬂop. Similarly, when the capacitor is discharging and its voltage tends to fall below VCC/3 and the comparator2 (COMP2) output jumps to positive saturation value or logic 1 at S input of ﬂipﬂop. Initially, consider R=S=0 and the capacitor voltage – must be VCC/3 (W/L)L. Therefore the load device require large area on chip than the area required by the driver. As the resistance of load channel is high, the speed of operation of the inverter is limited. The disadvantages of ratio type shift register are limited operating speed and large area required on chip. To improve the performance of shift registers, twophase ratio less dynamic shift register has been developed.
Fig. 12.64 Two phase Clock waveform of MOS dynamic shift register
12.7.3
Two Phase Ratioless Dynamic MOS Register
Figure 12.65 shows a ratio less shift register stage. Here both supply voltage and ground are connected to the clock pulses. At f = 0, clock is at logic 0 or 0V. When f =1, supply voltage as well as clock are
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at logic 1 or VDD. In the similar way of Fig. 12.60, input data will be transferred from one register stage to other register stage. At time t = t1, f1=VDD and input voltage is at logic 1, capacitor C1 will be charged to VDD. T3 will be ON and capacitor C2 will be charged to VDD. During the charging of C2, T2 will be OFF as the gate voltage of T2 does not exceed the source voltage by the threshold voltage VT . So transistor T2 and T3 do not act as an inverter.
Fig. 12.65
Two phase ratio less shift register
When f1 becomes 0V, T3 will be OFF. T2 becomes ON, as the charge stored on C1 is geater than the threshold voltage VT . Then C2 discharges through T2, and the capacitor C2 voltage will be at logic 0. Hence after the clock pulse interval (t2 – t1), C2 has returned to 0V, that is the complement of the input bit. Consequently the overall effect is that the circuit also behaves as an inverter like ratio shift register. Similarly, when f2 changes from logic level 0 to logic level 1 and returns back to logic level 0, the complement of stored charge capacitor C3 will be transferred to C4. In this circuit, conﬁguration capacitor is burden on the clock input signal, and the capacitor charging current must be supplied from clock.
12.7.4
Four Phase Ratioless Register Stage
In the twophase ratio less shift register as depicted in Fig. 12.65, the capacitance C2 charges capacitor C3. Therefore, the capacitor C2 must be greater than C3. Due to large capacitance C2, the speed of operation is degraded and it requires relatively large area on ICs. These disadvantages can be overcome by using fourphase ratio less register stage as depicted in Fig. 12.66. The clock waveforms are illustrated in Fig. 12.67. When f1=1, transistor T3 is ON and C1 charges to logic level 1. After f1 return back to logic level 0, capacitance C1 retain its charge at logic level 1. Consider that input is at logic level 1. Afterward f2=1, T1 and T2 are turn on and C1 discharges to logic level 0 through T1 and T2. As a result C1 store the complement of the input data. When input is at logic level 0, T1 is in cutoff and the stored charge of C1 will not be change. So that capacitor C1 retain at logic level 1, which is the complement of the input data.
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Digital Electronics: Principles and Applications
If f3=1, transistor T4 is ON and C2 charges to logic level 1. When f3 return back to logic 0, capacitance C2 retain its charge at logic level 1. When f4 is at logic level 1, T5 becomes ON and T6 will be ON if input data is in logic 0 and C1 is at logic level 1. Then capacitor C2 will be discharged through T5 and T6 and capacitor C2 logic level changes from logic level 1 to logic level 0. Similarly, when input data is in logic level 1 and C1 is at logic level 0, the capacitor C2 has no discharging path as T5 is ON and T6 is OFF. Then the capacitor C2 retain in logic level 1 and output data will be logic level 1. Fig. 12.66 Fourphase ratio less register stage In this way input will be transferred to output for using as input of next stage register. In this circuit, one capacitor does not supply charging current to other capacitor. But the disadvantage of this circuit is that a fourphase clock waveform is required and f1 must supply the charging current of C1 and f3 also must supply the charging current of C2.
12.7.5
CMOS Shift Register Stage
A CMOS shift register is depicted in Fig. 12.68. This circuit consists of two transmission gates G1 and G2, two inverters I1 and I2 and two capacitors C1 and C2. This CMOS shift register operates like an MOS dynamic shift register as shown in Fig. 12.60. The advantages of this circuit is that it is ratio less and does not draw a steady current from supply and consequently power loss is less. But CMOS gate and inverters require more space on CMOS IC compared to MOS gate and inverters on MOS IC. Fig. 12.67 Clock waveforms of fourphase ratio less register stage
Semiconductor Memories
Fig. 12.68
527
CMOS shift register stage
12.8 CHARGECOUPLED DEVICE (CCD) In late 1960s, Willard Boyle and George Smith have developed the chargecoupled devices(CCD) at Bell laboratory to store digital information. This is actually an array of MOS dynamic shift register sequential memory. These devices are low cost, very simple construction and versatile. The fabrication procedure of CCD on a semiconductor substrate involves very few operations than MOSFET and bipolar technology. The CCD memory will dissipate low power and can be manufactured with threefold density compared to MOS memories. In 1974, Fairchild electronics developed the ﬁrst imaging CCD with a format 100 × 100 pixels and the ﬁrst CCD TV cameras were manufactured for commercial use in 1975. In late seventies, the ﬁrst CCD ﬂatbed scanner was introduced using the ﬁrst integrated chip, which consists of 500 linear arrays and in 1982, the ﬁrst solidstate CCD camera was introduced for videolaparoscopy. Figure 12.69 shows the structure of charged coupled devices. These devices are based on MOS technology and consist of n–type or ptype silicon substrate. A thin silicon dioxide (SiO2) layer has been used to cover the substrate. An array of closely spread metal electrodes is placed on the oxide layer. The metallic electrode and the substrate act as a capacitor i.e. stored charge. Here, the semiconductor material is ntype substrate. Assume that the bottom of the substrate is connected with ground or 0V and all metal electrodes potential are also at 0V. Then majority current carriers are evenly distributed in the ntype substrate due to absent negative voltage at the electrodes. Figure 12.70 shows the evenly distribution of majority carriers, when there is no negative potential at metal electrodes.
Fig. 12.69 Typical structure of a charged coupled device
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Digital Electronics: Principles and Applications
Then all electrodes are maintained at the ﬁxed negative voltage – 4V. When applied voltage (–V) is more than the threshold voltage VT of the substrate, a depletion layer will be developed. Due to the negative bias voltage – 4V of the electrodes, a depletion layer will be developed just below the silicon dioxide layer. A depletion layer is created almost Fig.12.70 Transfer of charge between gates of CCD when majority carriers are evenly distributed evenly in the presence of negative voltdue to absence of negative potential age at electrodes. Figure 12.71 shows the depletion layer, which is developed by the ﬁxed negative – 4V at all electrodes. Actually, the depletion region is the region from which electrons have been removed. In this case, minority holes present with in the substrate and majority electrons have been pushed from the surface. As the negative chargFig. 12.71 Transfer of charge between gates of es are remov on region with in substrate CCD when –4V is applied when electrodes voltages are V1 = –4V, to all electrodes V2 = – 8V, and V3= – 12V. The voltage at electrode3 is more negative than the voltages of other electrodes. Therefore, higher voltage at electrode3 develops deeper potential well under electrode3 and the minority carriers shift to the right under this electrode. Fig. 12.72
Transfer of charge between gates of CCD when electrodes voltages are V1= − 4V, V2= − 8V, and V3= − 4V
Fig. 12.73 Transfer of charge between gates of CCD when electrodes voltages are V1= –4V, V2= –8V, and V3=–12V .
Semiconductor Memories
12.8.1
529
Operation of CCD
The structure of a 3phase charge coupled device (CCD) shift register is shown in Fig. 12.73. The difference between Fig. 12.69 and Fig. 12.73 is that clock pulses replace voltage sources. Here, the three clock waveforms f1, f2, and f3 are used to drive the CCD shift register. The composite clock waveforms of f1, f2, and f3 and the lateral charge transfer in the CCD are depicted in Fig. 12.74 and Fig. 12.75 respectively. This ﬁgure consists of an array of metal electrodes. All f1 electrodes are connected together. Similarly all corresponding f2 and f3 electrodes are connected together. This 3phase CCD works as a dynamic ﬂipﬂop with features of a masterslave ﬂipﬂop. So that data can be moved in one direction only.
Fig. 12.74 Connection of a three phase clocking to the electrodes of a CCD
Fig. 12.75
The potential distribution of electrodes at t0, t1, t2, and t3
During the time interval t0, only f1 is at a negative voltage, so that depletion regions are formed only under f1 gates because the clock f1 becomes negative. The charge in depletion regions under f1 is injected from an external source or from the preceding gate f3 gate. In the time interval t1, the clock
530
Digital Electronics: Principles and Applications
Fig. 12.76
Three phase clocking waveforms of the CDD
f2 also becomes negative while the clock f1 is held negative and the clock f3 is positive. Therefore, depletion regions are extended from the f1 gate to f2 gate. As a result, the charge is able to spread throughout the extended region. During the interval t2, the clock f3 becomes negative and the clock f2 is still negative. But f1 goes positive, thereby the depletion regions under the f1 gate are eliminated and the new depletion regions under the f3 gate are developed. Consequently, depletion regions are extended from the f2 gate to f3 gate. Similarly, during the interval t3, the depletion regions under f2 gates are eliminated and the charge originally under the f2 gate is pushed to the right under the f3 gates. In this way, the cycle has been completed; charge will be transferred from one region to next region three electrodes away. After that, the above logic cycle from time interval t0 to t3 will be repeated sequentially. In this way, three electrodes are used for storage as well as transfer of data in CCD. An example of CCD memory is Intel 2416 memory IC. This memory is organised as 16384 × 1 bit serial memory and it has 64 recirculating shift registers each of 256 bits. Any one register can be accessed by 6 bit address inputs and a 1: 64 decoder. In this IC, a fourphase clock waveform is used and data can be shifted in synchronisation with clock pulses. In this memory, the data cannot be stored in one position for indeﬁnite time due to gradual disappearance of depletion regions. Therefore, a minimum time between shifts of data must be present. In Intel 2416, the minimum time is about 9μs. Another example of CCD memory IC is Intel 2464. The Intel 2464 CCD IC is a 64 K bits of memory on a single die and it is organised with 256 independent circulating registers of 256 bits each. It is noted that, due to their low cost, high density, and high reliability, CCDs are very useful for numerous bulk storage applications.
12.9
MAGNETIC DISKS MEMORY
ROMs, EPROMs, EPROMs and RAMs, etc. are used to store data when the memory size is small. These devices are known as internal storage memory devices. If large amount of data is required to be stored in digital systems, then external memory devices are required. Most commonly used external devices are magnetic disks. Magnetic disk memory is a established conventional type of electronic data storage. The different magnetic diskettes, such as Hard Disks, Floppy Disks, IDE (Integrated Drive Electronics) Disks, EIDE (Extended IDE) Disks, SCSI (Small computer system interface) Disks and RAID (Redundant Array of Inexpensive Disks), Optical disks: CDROM, CDRecordables, CD
Semiconductor Memories
531
Rewriteables, and DVD are commercially available for used in computer. Magnetic disks are the current workhorse for permanent storage. In this section, the Hard Disks, Floppy Disks and Optical disks are explained brieﬂy. Magnetic disks are the most popular medium for storing digital data and these disks are direct access type secondary data storage. In a magnetic disk, ferromagnetic metals or metal oxides are used for recording and saving data. The ferromagnetism is a permanent alignment of magnetic moments, which creates a magnetic ﬁeld emanating from the ferromagnetic particle area. A magnetic disk is made of metallic ﬁlm, called platters and is coated with ferromagnetic materials. The disk or platter surface is subdivided into concentric circles called tracks. Digital data are organised into tracks. Each track on the disk has the same total storage capacity. Inner tracks are shorter and recording density of data is higher on tracks nearer the center and smaller than the tracks near the outer edge. Then each track is subdivided into different sectors and each sector provides a ﬁxed storage capacity in number of bytes. Generally, disks are available in the following size 8 inches, 5 ¼ inches, and 3 ½ inches. Figure 12.77 shows a typical magnetic disk with 64 sectors and 1024 tracks. A magnetic hard disk may be consists of one or more aluminum platters with a magnetisable coating. Figure 12.78 shows a typical hard disk with four platters. Here four platters are packed vertically one over the other called disk pack. In the disk pack, digital data is stored on the both the surfaces of each disk platter except the upper surface of the top platter and lower surface of the bottom platter as these surfaces have some tendency to collect dust and other forms of contaminations. Consequently, the disk pack with 4 individual disks has eight storage surfaces and each surface has a read/write head. The capacity of disk pack in total number of bytes stored is = number of bytes per sector × number of sectors per track × number of tracks per surface x number of surfaces. The capacity can also be expressed as Capacity =
bytes sector
sectors track
tracks surface
Fig. 12.77
No. of Surfacce
A typical magnetic disk
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Digital Electronics: Principles and Applications
Fig. 12.78
A hard disk drive with four platters
The disk is mounted on a vertical shaft, which rotates at a high and constant speed. An access mechanism moves the read/ write head to the desired location of data and provide direct access of data. Both surfaces of the disk are available for storage and each surface has a read/ write head. The disk head containing an induction coil ﬂoats just over the surface, Fig. 12.79(a) Longitudinal write operation of head and resting on a cushion of air. The circuit diagrams of read and write operation of head are depicted in Fig. 12.79(a) and Fig. 12.79(b) respectively. The block diagram representation of the read/write operation of head is also depicted in Fig.12.79(c). When a current passes through the head, it magnetises the surface just beneath the head and data will be stored in the surface. If the head passes over a magnetised area of platter surface, a current is induced in Fig. 12.79(b) Perpendicular read and writes operation of head the head and the previously stored bits will be read with the help of MR sensor. In this way, when the
Semiconductor Memories
533
platter rotates under the head, a stream of bits can be written and later read back also. The ferromagnetic material is deposited onto one or more aluminum or glass platters with the magnetic domains separated at evenly spaced intervals. The magnetic domains on the platters are induced to be spin up or down using a small powerful ferromagnetic read/write head that looks like a record player arm. One region on the magnetic platters is reserved as an index to the location of all data ﬁles stored on the disks. If this index is Fig. 12.79(c) Read and write operation of head damaged, then a lot of problems will be come up. Recording is done by two ways namely longitudinal recording and perpendicular recording. In perpendicular recording, the coherent magnetic ﬁeld coming from a single domain can be induced to point a spin up or spin down direction. The spin up stands for logic 0 and the spin down stands for logic 1. During read operation, recording data in digital format will be back again. Each hard disk drive consists of a motor to rotate the disk pack at speed about 2400 to 3600 revolutions per minute about its axis. Therefore, all platters of a disk pack move simultaneously in the same direction and at same speed. This drive has a set of read/write heads mounted on arms. There is enough space in between the disks to allow access arms and to locate the data; read/write heads will be move to any track/sector of any surface. A disk controller is associated with each drive. Actually, this is a chip that controls the drive. The operation of controllers is that accepting commands from the software, such as read, write and format, controlling the arm motion, detecting and correcting errors.
12.9.1
Floppy Disks
With the advent of the personal computer, the diskette or ﬂoppy disk has been developed to distribute softwares. The ﬂoppy disk is very popular to use as auxiliary storage. These disks are very thin, circular and permanently enclosed in a plastic jacket. Figure.12.80 shows a typical ﬂoppy diskette. These disks are made of very thin plastic material (mylar) and are coated with a layer of magnetic metal oxides. Generally, disks are coated on both sides. As the used material is not a hard plate but in a ﬂexible tape, it is called as ﬂoppy disk. The difference between hard disks and ﬂoppy disks is that the heads ﬂoat just above the surface on a cushion of rapidly moving air in hard disks, but in ﬂoppy disks, heads actually touch the diskettes. As a result, both the media and the heads quickly wear out. To reduce wear and tear, the personal computers retract the heads and stop the rotation when a drive is not reading or writing. Floppy disks are normally available in 5.25 inch, 3.5 inch and 8.5 inch. The 5.25 inch and 8.5 inch disks become obsolete. The 3.5inch diskettes come in a rigid jacket for protection. Presently, 3.5 inches ﬂoppy disks are used in the standard personal computer systems.
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Digital Electronics: Principles and Applications
Fig. 12.80 A typical ﬂoppy diskette
12.9.2
Optical Disks
Optical disk is the latest development in secondary storage. These disks have much higher recording densities than conventional magnetic disks. They consist of a rotating disk, which is collated with highly reﬂective material. Data is physically stored on the surface of disk as a series of depressions called pits and unburned areas between the pits called lands. Actually, the data are written by focusing high power laser beam on the surface of the spinning disk in the form of small pits and land. A pit/land transition represents 1, and its absence is 0. The storage capacity of optical disks is remarkable in comparison to magnetic disks and the storage cost per bit is very low. The comparison of magnetic disk drive, ﬂoppy disk drive and optical disk drive are given in Table 12.11. There are different types of optical disks namely CDROM, CD –R, CD RW. CDROM stands for Compact Disk – Read Only Memory, CD–R stands for Compact Disk Recorder and CDRW stands for Compact Disk –Rewriteable. Table 12.11
Parameters Storage media Access time Data transfer Capacity Advantages and disadvantages
Comparison of magnetic disk drive, ﬂoppy disk drive and optical disk drive
Magnetic disk drive Magnetic disk, Disk pack, ﬁxed disk 10–100 milisecond 200,000 to million bytes per second 10 million to 15 billion bytes per drive Large capacity, Fast direct access but relatively expensive
Floppy disk drive Magnetic diskette 5.25 inch, 3.5 inch and 8.5 inch 100600 milisecond 10,000 to 30,000 bytes per second 360,000 to several million bytes per drive Small, slower and smaller capacity but less expensive
Optical disk drive Optical disk, CDROM 30–100 milisecond 150,000 to 500,000 bytes per second 700 million to few billion bytes per drive Large capacity, high quality storage of data Fast direct access but relatively expensive
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CDROM CDROM is one type of Optical disks and it stands for Compact Disk – Read Only Memory. This CD is prepared using a molding process from a burned master disk. This disk contains 16,000 tracks per inch. The disk is written once only during manufacturing in the form of small pits and lands. Once data is written, it cannot be erased. To read data from disk, a low power laser beam is focused on the surface of the disk. Consequently, pitted area reﬂects less light and smooth surface reﬂects more light. Then a detector senses the reﬂected light. The limitation of the disks is that they are read only memory device. Generally, the disk should be able to hold 700 MB data. CDs are 1 mm thick disc of polycarbonate plastic coated with a thin layer of reﬂecting aluminum and protected by a lacquer ﬁlm as depicted in Fig.12.81. The polycarbonate region is pressed with grooves and dents with the digital data. The data is stored as regions of high and low laser light reﬂection. The smooth areas are highly reﬂective, while the pits or grooves scatter light and drop the reﬂection. A spiralraised groove keeps the laser on track as shown in Fig.12.82.
Fig. 12.81
CDROM
CD–R CD–R stands for Compact Disk –Recorder. A CDRecorder (CDR) is a comFig. 12.82 Spiral groove of CDROM mon peripheral which is similar in size to a CDROM Drive. These devices are different from magnetic disks as the user can write the disk once only. As the data is stored in the disk, it cannot be erased. CDRs are very useful for backup purposes and speciﬁed applications where ﬁles/data never be altered. Data from video scanners, keyboards, optical character recognition and other equipments are recorded on CDRs. CDRW CDRW stands for Compact Disk –Rewriteable. This CD uses both laser and magnetic head to read and write the data. The stored data can be erased and rewritable. CDRW is recorded using lasers to heat magnetised areas and uses a different alloy for the recording layer. Therefore, CDRW can not be replaced CDR and CDRW blanks are much more expensive than the CRR blanks. This CD is used as backing up hard disks, stored data from video scanners, keyboards, and other equipments.
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12.10
Digital Electronics: Principles and Applications
CONTENTADDRESSABLE MEMORY (CAM)
The ContentAddressable Memory (CAM) compares input search data with a table of stored data, and returns the address of the matching data. Usually, CAM is a memory that implements the lookuptable function in a single clock cycle using dedicated comparison circuitry and making them faster than other hardware and softwarebased search systems. CAMs can be used in a wide variety of applications requiring high search speeds, such as parametric curve extraction, Hough transformation, Huffman coding/decoding, Lempel–Ziv compression, and image coding, etc. The primary commercial application of CAMs is to classify and forward Internet protocol (IP) packets in network routers. In networks like the Internet, a message such as an email or a Web page is transferred by initially breaking up the message into small data packets of a few hundred bytes and then sending each data packet individually through the network. These packets are routed from the source, through the intermediate nodes of the network which are called routers and reassembled at the destination to reproduce the original message. The function of a router is to compare the destination address of a packet to all possible routes, in order to choose the appropriate one. A CAM is a good choice for implementing this lookup operation due to its fast search capability. Hence, CAMs are very popular in network routers for packet forwarding and packet classiûcation, but they are also beneûcial in a variety of other applications which require highspeed table lookup. Though the speed of a CAM comes at the cost of increased silicon area and power consumption, designers should strive to reduce two design parameters namely silicon area and power consumption. The optimum design of CAM is to reduce power consumption associated with the large amount of parallel active circuitry, without sacriﬁcing speed or memory density. As CAM applications grow, demanding larger CAM sizes, the power problem is further exacerbated. Reducing power consumption, without sacriﬁcing speed or area, is the main thread of recent research in largecapacity CAMs. In this section, the operation of CAM and also describe the CAM application of packet forwarding.
12.10.1 Structure of CAM Figure 12.83 shows a simple block diagram of a CAM. The conceptual view of a contentaddressable memory containing words is depicted in Fig. 12.83. In this example, the search word matches location (location of stored word 1) as indicated by the shaded box. The matchlines provide the row match results. The encoder outputs are an encoded version of the match location. The input to the system is the search word that is send to the searchlines to the table of stored data. The number of bits in a CAM word is usually large, with existing implementations ranging from 36 to 144 bits. Generally, a typical CAM uses a table size ranging between a few hundred entries to 32K entries, corresponding to an address space Fig. 12.83 Basic structure of CAM
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ranging from 7 bits to 15 bits. Each stored word has a matchline that indicates whether the search word and stored word are identical or are different. The matchlines are fed to an encoder that generates a binary match location corresponding to the matchline that is in the match state. An encoder is used in CAM systems, if only a single match is expected. In some CAM applications where more than one word may match, then a priority encoder is used instead of a simple encoder. A priority encoder selects the highest priority matching location to map to the match result, with words in lower address locations receiving higher priority. In addition, there is a hit signal that ﬂags the case in which there is no matching location in the CAM. The overall function of a CAM is to ﬁnd a search word and return the matching memory location. The capacity of different CAM chips varies from 8K to 8M. Presently, the largest commercially available singlechip CAMs are 18 Mbit implementations. It is a fact that a typical CAM cell consists of two SRAM cells. As per thumb rule, usually the largest available CAM chip is about half the size of the largest available SRAM chip.
12.10.2
CAM Architecture
A small model of CAM architecture is shown in Fig. 12.84. This schematic diagram of CAM shows individual core cells, differential searchlines, and matchline sense ampliﬁers (MLSAs). It is depicted in Fig. 12.84 that CAM consists of 4 words, with each word containing 3 bits arranged horizontally. In this ﬁgure, CAM stands for CAM cells, SL stands for searchline, and ML stands for match line. Always, there is a match line corresponding to each word (ML0, ML1, ML2, and ML3) feeding into matchline sense ampliﬁers (MLSAs). There is a differential searchline pair corresponding to each bit of the search word —– —– (SL0, S L0…… SL2, SL2 ). The CAM search operation starts with loading the searchdata word into the searchdata registers followed by precharging all matchlines high and putting them all temporarily in the match state. After that, the searchline drivers send the search word onto the differential searchlines, and each CAM core cell compares its stored bit against the bit on its corresponding searchlines. The
Fig. 12.84
Schematic block diagram of a model CAM with 4 words having 3 bits each
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matchlines on which all bits match remain in the prechargedhigh state. Then MLSA detects whether its matchline has a matching condition. Afterwards, the encoder maps the matchline of the matching location to its encoded address.
12.10.3
CAM Core Cells
A CAM cell serves two basic functions such as bit storage and bit comparison. Figure 12.85(a) shows a 10T NORtype CAM cell and Fig. 12.85(b) shows the 9T NANDtype CAM cell. The cells are shown in Fig. 12.85 is an SRAMbased datastorage cells. In this SRAM cell bit storage device, cross– coupled inverters implement the bitstorage nodes D and D. The nMOS access transistors and bitlines which are used to read and write. The SRAM storage bit are omitted to simplify the schematic diagram. The bit comparison, which is logically equivalent to an XOR of the stored bit and the search bit can be implemented using the NOR and the NAND cells.
NOR Cell The CAM implementation using NOR cell consists of the complementary stored bit, (D – —– and D), and the complementary search data on the complementary searchline, SL and S L , four transistors M1 to M4 to maintain minimumsize and high cell density. The transistors implement the pulldown path of a dynamic XNOR logic gate with D and SL inputs. Each pair of transistors either M1 and M3 or M2 and M4 forms a pulldown path from the matchline, ML. The mismatch of SL and D activates one of the pulldown paths, connecting ML to ground. The correct match of SL and D disables both pulldown paths after disconnecting ML from ground. The NOR nature of this cell can be justiﬁed when multiple cells are connected in parallel to form a CAM word by shorting the ML of each cell to the ML of adjacent cells. The pulldown paths are connected in parallel resembling the pulldown path of a CMOS NOR logic gate. The match condition on a given ML is that each individual cell in the word has a match.
Fig. 12.85
(a) 10T NORtype CAM cells and (b) 9T NANDtype CAM cells
NAND Cell The NAND cell based CAM implements the comparison between the complementary – stored bit, (D and D), and the complementary search data on the complementary search line,(SL and —– S L ) using transistors M1, MD and MD– to maintain minimumsize and high cell density. For example of the bitcomparison operation of a NAND cell, assume SL=1 and D=1. When the transistor MD is ON,
Semiconductor Memories
539
it passes the logic “1” on the SL to node B. The node B is the bitmatch node which is logic “1” if there is a match in cell. If the node B is logic “1”, transistor M1 becomes turn ON. The transistor M1 is also turned ON in the other match condition when SL = 0 and D = 0. In this case, the transistor MD– passes logic high to raise node B. When SL ≠ D, the result is a miss condition and the node B is logic “0” and the transistor M1 is OFF. The node B is a passtransistor implementation of SLD function. The NAND nature of this cell can be justiﬁed when multiple cells are connected serially. The MLn and MLn+1 nodes are connected to form a CAM word.
Ternary Cells Usually the NOR and NAND cells are binary CAM cells. These cells can store either a logic “0” or a logic “1”. But ternary cells can store a logic “0”, a logic “1” and “X ” value. The “X ” value is a don’t care, which represents both “0” and “1”, and allow a wildcard operation. The wildcard operation means that an “X ” value stored in a cell causes a match regardless of the input bit. Table 12.12 shows the ternary encoding for NOR cell and ternary encoding for NAND cell is given in Table 12.13. – – The two bits are represented by D and D. It may be noted that the D and D are not necessarily complementary, but the complementary notations are maintained for consistency with the binary CAM cell. Two bits can represent four possible states, but ternary storage requires only three states as the state where D – and D are both zero, is not used in this cell. To store a ternary value in a NOR cell, a second SRAM cell – is used as shown in Fig. 12.86. D is connected to the left pulldown path and D is connected to the right pulldown path. Hence, the pulldown paths are independently controlled. A don’t care state, “X ” can be – stored when both D and D are equal to logic “1”, and both pulldown paths are disabled. A logic “1” is – – stored by setting D = 1 and D = 0 and logic “0” is stored by setting D = 0 and D = 1.
Fig. 12.86
(a) NORtype Ternary core cells (b)NAND type Ternary core cells
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Table 12.12
Stored Value 0 1 x
12.10.4
Ternary Encoding For NOR Cell
Stored– D D 0 1 1
1 0 1
Search bit 0 1 0
1 0 0
Table 12.13
Ternary Encoding For NAND Cell
Value 0 1 x x
D
Stored M
0 1 0 1
0 0 1 1
Search Bit — SL SL 0 1 1 1
1 0 1 1
Matchline Structures
The matchline is one of the key structures in CAMs. Usually NOR Matchline and NAND Matchline structure are used. In this section, only NOR Matchline is discussed. Figure.12.87 shows the schematic diagram of NOR Matchline structure, how NOR cells are connected in parallel to form a NOR matchline, ML. Any NOR search cycle operates in three phases such as searchline precharge, matchline precharge, and matchline evaluation. Firstly, the searchlines are precharged low to disconnect the matchlines from ground by disabling the pulldown paths in each CAM cell. When the pulldown paths are disconnected, transistor precharges the matchlines high. Then the searchlines are driven to the search word values, triggering the matchline evaluation phase. When there is a match, the ML voltage stays high as there is no discharge path to ground. While there is a miss match, there is at least one path to ground that discharges the matchline. The matchline sense ampliﬁer (MLSA) senses the voltage on ML and creates a corresponding fullrail output match result. The main characteristic of the NOR matchline is its high speed of operation.
Fig. 12.87
Structure of a NOR matchline with match result
12.11 ADVANCE MEMORY In digital computers, memory devices are organised according to their speeds. The fastest memory devices, such as RAMs and ROMs are used in CPU of computers. These memories are known as primary memory. Integrated circuit (IC) memories are usually employed ROMs and RAMs. The commonly used ROMs are EPROM, EAPROM, and EEPROM. There are two types of RAM, namely static and dynamic RAMs. Magnetic memory devices, such as ﬂoppy disks, CDROM and hard disks are used for bulk data storage. The operation of ROM and RAM ICs and magnetic memory devices are already explained in previous sections. The magnetic bubble and charge coupled device (CCD) memories now a days are also used for bulk storage.
Semiconductor Memories
541
Magnetic bubble devices memories were introduced in the late 1970s, but these are less popular than RAM, and ROM ICs. Magnetic bubble technology lies in between magnetic disk and semiconductor memory technology. These memories have no moving part and are nonvolatile. Generally, magnetic bubbles are developed on certain magnetic materials such as garnet crystal by applying magnetic ﬁeld which is perpendicular to the surface of the sheet of magnetic materials. The magnetic ﬁelds strengthen some regions in the material and weaken others regions. Data are represented in bubble–storage by the presence or absence of bubbles, which represents logic “1” or logic “0” . The CCD memory devices stored data on capacitors as charge like DRAM. The data storage of CCD memory is arranged in shift register conﬁguration. The charge will be shifted from one CCD cell to the other CCD cell. Just like DRAMs, data will be lost with switch off power supply. The detailed operation of CCD memory devices is explained in Section 12.8. The nonvolatile RAM (NVRAM) is new version of RAM. NVRAM consists of a high speed static RAM and each RAM cell has corresponding cell of an EEPROM with accesstime of 200–300ns. Each —– NVRAM IC has a special pin, labelled as nonvolatile enable, NE . The stored data in the RAM section, —– —– can be transferred to EEPROM section, when both NE and WE write are logic level “0”. The data in the RAM section can be transferred to ROM section in about 10ms. To read data from EEPROM section, —– —– both NE and WE signal must be logic level “0”. Usually, this operation is performed, when power is switched off. The other memory devices are content addressable memories (CAMs), programmable logic arrays (PLAs) and programmable array logic (PAL). The content addressable memory is a special purpose random access memory device which can be accessed by searching for data content. The contentaddressable memory (CAM) compares input search data with a table of stored data, and returns the address of the matching data. Usually, CAM is a memory that implements the lookuptable function. The detailed operation of CAM is discussed in Section 12.10. Canonical SOP and Canonical POS forms are used to implement any combinational logic functions. To implement these circuits, logic gates are used. In programmable design of digital systems, an array of logic cells is used. Actually, cells can be able to provide a universal logic function. In this design, signal routing is done through switch box approach and RAM holds the routing patterns, which is reprogrammable. The advantages of programmable design are less time required to design, easily reworked on design system, design costs are low, and production time decreases. This technique has limited ﬂexibility, and this is suitable for only low volume production. The other approach of combinatorial logic circuits and sequential logic circuits design is application of Programmable Logic Devices (PLDs). A programmable Logic Device (PLD) is an IC that contains a large number of logic functions, which are interconnected on the chip. The interconnection process is user programmable and it is similar to PROM. Actually, the basic concepts of PLD have been developed by combining combinatorial logic and ROM technologies. Generally, ﬂexible architecture and ﬁxed architecture are used for programmable logic devices. Three basic forms of PLD’s are Programmable ROM (PROM), Programmable Array Logic (PAL), and Programmable Logic Arrays (PLA). Programmable read only memory (PROM) devices are developed using ﬁxed architecture. PROM is a ﬁxed architecture programmable logic device and can be used as memory devices. The PROM is not too much ﬂexible with respect to PAL and PLA. In PAL, the OR array is ﬁxed and AND array is programmable. The PAL is more ﬂexible than the PROM and is probably the most used of the ﬁxed architecture devices. The PLA is the most ﬂexible of the programmable logic devices, as both AND array and OR array are programmable. Therefore, in the logic circuits design using PLA, the additional
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ﬂexibility is not needed. PLD ICs are most commonly used in application speciﬁc digital circuit design due to ﬂexibilities, low development cost, and low power consumption. The detail architecture and operation of PLDs such as PROMs, PLAs, and PALs are explained in Chapter 13.
SUMMARY In this chapter, the basic concept of semiconductor memories has been explained. The memory organisation and operation of various semiconductor memories, namely ROM, PROM, EPROM, EEPROM, SRAMs, DRAMs are discussed. Expansion of ROM and RAM are also incorporated in this section. Sequential memory, Dynamic shift register and ChargeCoupled Device (CCD) have been introduced. Magnetic storage devices such as floppy disks, hard disks and optical disks are explained briefly in this chapter. The basic concept of content addressable memory (CAM) is incorporated.
MULTIPLE CHOICE QUESTIONS 1.
The term ‘memory’ applies to (a) Logic (b) Control (c) Data storage (d) Output device 2. In digital systems, the memories are used to store (a) Data (b) Information (c) Instruction (d) None of the above 3. A semiconductor read only memory basically is (a) A combinational logic circuit (c) A sequential circuit with ﬂipﬂops and gates (b) A set of ﬂipﬂop memory elements (d) None of the above 4. A memory used for storing variable quantities is (a) ROM (b) PROM (c) EPROM (d) RAM 5. The semiconductor memories are widely used in place of ASICs due to (a) Small size (c) Interface able with digital systems (b) Low cost (d) All of the above 6. A RAM is (a) A randomaccessmemory (c) Static or dynamic memory (b) A volatile memory (d) All of these 7. A ROM is (a) A randomaccessmemory (c) Static or dynamic memory (b) A volatile memory (d) All of these 8. A SRAM is fabricated using (a) Bipolar technology (c) Both bipolar and MOS technology (b) MOS technology (d) None of these 9. A M × N bits memory can be able to store (a) M words of N bits each (c) M + N bits (b) N words of M bits each (d) M – N bits 10. A memory has 10 bit address bus. The number of memory locations are (a) 1000 (b) 1024 (c) 100 (d) 10 11. The address bus width of a memory of size 1024 × 8 bits (a) 10 bits (b) 11 bits (c) 12 bits (d) 13 bits 12. In a ROM, data can be stored (a) By the user only once (c) At the time of fabrication
Semiconductor Memories
13. 14. 15. 16. 17.
18. 19.
20.
21.
22.
23. 24. 25.
26.
27. 28. 29.
(b) By the user a number of times (d) None of these An example of volatile memory is (a) ROM (b) RAM (c) LSI (d) None of these The data bus width of a memory size 2048 × 8 bits is (a) 8 bits (b) 10 bits (c) 12 bits (c) 16 bits What is the number of bits required for addressing 4KB memory? (a) 16 (b) 12 (c) 8 (d) None of these The number of 16 × 4 size memory ICs are required to design a 64 × 8 memory (a) 8 (b) 6 (c) 4 (d) 2 A shift register is a (a) Sequential accessed memory (c) RAM (b) ROM (d) None of these A chargecoupled device is (a) A bipolar device (b) A MOS device (c) A magnetic device (d) None of these A ROM is (a) A randomaccessmemory (c) Programmable memory (b) A non volatile memory (d) All of these A mask programmed ROM is (a) Programmed at the time of fabrication (c) Erasable electrically (b) Programmed by the user (d) None of these A PROM is (a) Mask programmed (c) Programmed once only (b) Erasable by ultraviolet (d) None of these A CCD is (a) RAM (c) Sequential accessed memory (b) ROM (d) None of these MOS technology can be used for fabrication of (a) SRAMs (b) EPROMs (c) ROM (d) All of these A DRAM can be fabricated using (a) MOS technology (b) TTL (c) I2L (d) None of these An EPROM is (a) Erasable and programmable (c) Nonerasable (b) Volatile (d) None of these The programming of EPROM can be done (a) At the time of fabrication (c) By the user many times (b) By the user once only (d) None of these An EPROM is fabricated using (a) MOS technology (b) TTL (c) ECL (d) None of these Fusible link is associated with (a) PROM (b) ROM (c) EPROM (d) All of these A ﬂoppy disk is a (a) Thin plastic disc coated with magnetic oxide
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30. 31. 32.
33. 34. 35.
Digital Electronics: Principles and Applications (b) Thin magnetic oxide disc coated with plastic (c) Aluminum disk coated with magnetic oxide (d) None of these Floating gate is fabricated for (a) PROM (b) ROM (c) EPROM (d) All of these The write cycle time of a memory is 200ns. The maximum rate at which data can be stored is (a) 500 words/s (b) 5000 words/s (c) 50000words/s (d) 500000 words/s The access time of a sequentially accessed memory is (a) Same as that of a RAM (c) Higher than that of a RAM (b) Less than that of a RAM (d) Same as that of a ROM A memory, which is not randomaccess type, is (a) CCD (b) RAM (c) ROM (d) None of these Index hole is used in (a) Floppy disk (b) Hard disk (c) Magnetic tape (d) None of these A disk pack has 4 plates with 6 read/write heads and 400 tacks on each surface. Each track on a disk surface is divided into 100 sectors of 512 bytes each. The total storage capacity of the disk pack is (a) 122880000 bytes (b) 12288000 bytes (c) 1228800 bytes (d) 122880 bytes
REVIEW QUESTIONS 12.1 12.2 12.3 12.4 12.5 12.6
Explain the basic concept of one bit memory cell and mention applications of memory cell. What the types of memory? Write the difference between ROM and RAM. What is nonvolatile memory? Discuss memory organisation with an example. What is the bit storage capacity of a ROM with a 512 × 4 organisation? How many address bits are required for a 2048 bit memory? What is the difference between PROM and ROM? Draw the internal structure of typical ROM 32 × 32 memory array and explain its operation. Explain memory expansion of ROM with examples. How many 16K × 1 ROMs are required to achieve a memory with a word capacity of 16K and a word length of eight bits? Draw the diode, bipolar and MOS ROM architecture for Table 11.12. Table 11.12
A 0 0 0 0 1 1 1 1
12.7 12.8 12.9
Inputs B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
F0 1 1 0 1 0 0 1 1
Outputs F1 1 1 0 1 1 1 0 1
F2 0 1 0 1 0 1 1 0
Implement the BCD to Excess3 code conversion using ROM. What are the types of ROMs? Write a block diagram of a ROM and explain it’s operation. What are the advantages and limitations of PROM? Implement the following logic functions F1, F2 and F3 as given below using PROM
Semiconductor Memories
12.10 12.11
12.12 12.13 12.14
12.15 12.16
12.17 12.18 12.19 12.20
12.21
12.22
12.23 12.24 12.25
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F1=m(0, 1,4,5,7,11) F2=m(2, 7, 8, 9,11) F3=m(4,5, 10,12,14,15) IC 2716 is 2K × 8 EPROM IC. Find the number of 2716 and other ICs to implement (a) 4K byte (b) 2K × 16 ROM (c) 4K × 16ROM Write the difference between the following (a) PROM and ROM (b) EPROM and EEPROM (c) ROM and RAM Explain difference between static and dynamic RAM. What is the reason for the refresh operation in dynamic RAMs.? Draw the structure of a 4 × 4 Static RAM and explain it’s operation. How many 16K × 1 RAMs are required to achieve a memory with a word capacity of 64K and a word length of eight bits? Write short notes on the following (a) Bipolar RAM cell (c) SRAM (b) Six transistor MOS memory cell (d) DRAM Draw the block diagram of 16K × 1DRAM structure. Explain the operation of DRAM using timing diagram. List the comparison between SRAM and DRAM. Design the following RAM structure (a) 1024 × 8 bit RAM using 1024 × 4 bit RAM (b) 4096 × 4 bit RAM using 1024 × 4 bit RAM Write short notes on the following (a) Three transistor dynamic MOS RAM (b) Four transistor dynamic MOS RAM What is sequential memory? What are the types of dynamic MOS shift register? Explain any one dynamic MOS shift register. Explain the operation of CCDs with diagrams. Write short notes on the following (a) Floppy disk (c) Optical disk (b) Hard disk (d) Content addressable memory A disk pack has 4 plates with 6 read/write heads and 400 tacks on each surface. Each track on a disk surface is divided into 100 sectors of 512 bytes each. Determine (a) number of cylinders in the disk pack (b) number of tracks in the disk pack (c) the total storage capacity of the disk pack Design a PROM structure for the following functions F1= m(0,1,8,11,12,15), F2= m(2,3,6,7,8,9,12,13) F3= m(1,3,7,8,9,11,12,15) and F4= m(0,1,4,8,11,12,15) Design a PROM structure for implementation of following logic functions – – – F1= ABC + ACD, F2= ACD + BC + A D, and F3 = ABC + A CD, Explain brieﬂy the applications of ROM. A disk pack has 8 plates with 14 read/write heads and 400 tacks on each surface. Each track on a disk surface is divided into 100 sectors of 512 bytes each. Determine the total storage capacity of the disk pack.
CHAPTER
13 PROGRAMMABLE LOGIC DEVICES 13.1
INTRODUCTION
Integrated circuits (ICs) are built on a semiconductor substrate, usually one of singlecrystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed plastic case, with leads extending from it for input, output, and powersupply connections. Integrated circuit functions are virtually limitless and used in various applications. Improvements in IC manufacturing technology have led to increasingly dense integrated circuits. Therefore, smaller and denser chips will be able to provide speed beneﬁts as these chips have highspeed devices. Generally, the integrated circuits are manufactured by the following fabricating steps: ﬁlm formation, impurity doping, photolithography, etching, and packaging. Digital integrated circuits contain one to millions of logic gates, ﬂipﬂops, multiplexers, demultiplexers, adders, comparators etc. in a few square millimeters. The small size of these circuits allows high speed, low power dissipation, and reduced manufacturing cost compared with boardlevel integration. Sometimes the typical logic design task consists of interconnecting standard ﬁxed function IC’s to form more complex circuits and systems. This process requires many IC’s, which increases the cost of the design due to large space and power requirements. Therefore, the need for application speciﬁc integrated circuits (ASICs) is generated. ASICs can be used to meet the speciﬁc requirements and can be manufactured by IC manufacturer as per user speciﬁcations. The advantages of ASICs are less space requirements, less power requirements, and better security but initial development cost is very high. Integrated circuits can be designed by using standard product ICs and application speciﬁc ICs (ASIC). Figure 13.1(a) and (b) show the different options available to chip designer for ﬁnal implementation of combinatorial and sequential logic circuits. Application speciﬁc ICs (ASICs) are semicustom gate array, semi custom standard cell, and full custom type.
Full Custom Design In full custom design, each individual transistor of circuits can be accessed. This provides total ﬂexibility in the design of the chip. In this design, the power consumption, timing and chip area can be optimised. But the times for fully optimised design
Fig.13.1(a) Classiﬁcation of standard product ICs
Programmable Logic Devices
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ing a complete system will be long. If there are any mistakes in design, then it will be very expensive to correct. The advantages of full custom design are ﬂexibility, and design optimisation. The disadvantages are long design time, expensive to rework, and require high volume product. In custom design, the following options are available: design with basic gates; design with Fig.13.1(b) Classiﬁcation of application speciﬁc ICs transmission gates; design with complex gates and combination of basic gates, transmission gates and complex gates.
Standard Cell Design The standard cell design technique uses a set of predeﬁned blocks such as adders, multiplexers, demultiplexers, etc. This technique has less ﬂexibility than full custom. When parameterised standard cells are used in design, some ﬂexibility in terms of shape and size of the cell are available. In standard cell design, we can use predeﬁned standard cells. Cells are connected with power supply and ground. In this design, it is presently required to add signal routing. The advantages of standard cell design are reduced design time, less errors, and moderately optimize design. This design technique has following disadvantages: very limited ﬂexibility, expensive to rework, and suitable for high volume product. Programmable Design In programmable design of digital systems, an array of logic cells is used. Actually, cells are able to provide a universal logic function. In this design, signal routing is done through switch box approach and RAM holds the routing patterns, which is reprogrammable. The advantages of programmable design are less time required to design, easily reworked on design system, design costs are low, and production time decreases. This technique has limited ﬂexibility, and this is suitable for only low volume production. The alternative approach of complex combinatorial and sequential logic circuits design is application of Programmable Logic Devices (PLDs). A programmable Logic Device (PLD) is an IC that contains a large number of logic functions, which are interconnected on the chip. The interconnection process is user programmable and it is similar to PROM. Actually, the basic concepts of PLD have been developed by combining combinatorial logic and ROM technologies. Generally, ﬂexible architecture and ﬁxed architecture are used for programmable logic devices. Three basic forms of PLD’s are Programmable ROM (PROM), Programmable Array Logic (PAL), and Programmable Logic Arrays (PLA). Programmable Read Only Memory (PROM) devices are developed using ﬁxed architecture. PROM is a ﬁxed architecture programmable logic device and can be used as memory devices. The PROM is not too much ﬂexible with respect to PAL and PLA. The PAL is more ﬂexible than the PROM and is probably the most used of the ﬁxed architecture devices. The PLA is the most ﬂexible of the programmable logic devices, but in the logic circuit designs the additional ﬂexibility is not needed. PLDs are most commonly used in ASIC design due to ﬂexibilities, low development cost, and low power consumption. In this chapter architecture of PLDs such as PROMs, PLAs, PALs, PLDs, SPLDs, CPLDs and FPGA are incorporated.
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Digital Electronics: Principles and Applications
PROGRAMMABLE READ ONLY MEMORY (PROM) DEVICES
A ROM or Read Only Memory is an array of interconnected semiconductor devices to store an array of binary data. Data stored in the ROM can be read for reuse in digital devices, but the stored data cannot be changed under normal operating conditions. A typical ROM consists of a decoder and a memory array. The block diagram of ROM is shown in Fig.13.2. The ROM has n input lines and there are 2n possible combinations of n binary digits. Therefore, ROM has 2n address lines from 0 to 2n1, which is represented, by a n lines to 2n line decoder. When a set of 1’s and 0’s is applied to the decoder inputs of ROM, any oneaddress line of the 2n address lines of memory will be selected. Then data stored in this memory address can be transferred to the memory output lines. Here ROM has ‘m’ output lines. The ROM can effectively store the truth table of an ninput, and moutput combinational logic functions. The size of memory is the number of address lines × output lines. When ROM has ‘n’ number of inputs and ‘m’ number outputs, the size of memory is 2n × m bits. If number of address lines n=12 and output lines m = 8, the total storage Fig. 13.2 Block diagram of Read Only Memory capacity is 212 × 8 = 4096 bytes = 4KB. Usually, there are three types of ROM, namely maskprogrammable ROM (ROM), programmable ROM (PROM), and erasable programmable ROM (EPROM).
Maskprogrammable ROM (ROM) ROMs are nonvolatile memories as initially data is stored in memory through programming and stored data will not be changed when power supply is removed. During the fabrication, the device (ROM) is programmed though selectively includes or omits switching elements at the rowcolumn intersections according to design speciﬁcation. Programming during manufacturing is very expensive as very costly equipments are required. Therefore this is economic for high volume production. Generally, mask programmable ROMs are manufactured by Bipolar as well as CMOS technology. Programmable ROM (PROM) The data can be stored into the ROM array by the user with the help of PROM programmer. Initially, all switching elements at rowcolumn intersections are builtin in the ROM array during the fabrication of ROM using Bipolar fusible link. During programming, the user selectively removed the fusible links of switching elements as per requirements. As the users are able to program the device according to speciﬁc needs, PROM can be used for lowvolume applications. Erasable Programmable ROM (EPROM) In EPROM, a special charge storage mechanism is used to enable or disable the switching elements of memory. So all switching elements can be programmed electrically and can be erased by exposure to UltraViolet light. Usually, CMOS technology is used for manufacturing EPROM. Electrically Erasable PROM (EEPROM) EEPROM is similar to EPROM but this type of ROM can be completely erased electrically. There is a limit on the number of times of data erased and programmed. Therefore, EEPROMs are not used in place of RAM.
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13.2.1 Structure of PROM The Bipolar and MOS technology are commonly used in fabrication of PROMs. Bipolar PROMs use the fusible links and it has small access times. In MOS PROMs, ﬂoating MOSFETs are used as basic charge storage elements and these ROMs have high packing density. Figure 13.3 shows the basic structure of a MOS PROM matrix. It consists of two sets of bus bars, such as horizontal address lines and vertical output lines. The vertical output lines are connected with address decoder though a ﬂoating MOSFETs. When ﬂoating gate exists in the intersection of output lines and address line, the digital data ‘0’ can be stored. If ﬂoating gate does not exist in the intersection of output lines and address line, the digital data ‘1’ will be stored in that location. When decoder inputs are A0 = 0 A1 = 0, data stored in address line 00 will be output at F0 to F7. Hence, the output data is 11111111.
Fig. 13.3
Structure of 4 × 8 PROM
The PROM is used as memory device and it can be represented as an array of registers. This means that the registers in the memory can be programmed. After programming, usually they cannot be changed. To program the PROM, each register must be loaded with a desired binary number. Generally this is done using a PROM programmer. Figure 13.4 shows the array of registers of 4 × 8 PROM. To load in address location 00, determine the output of logic expressions Fig. 13.4 Array of registers for F0, F1, F2, F3 F4, F5, F6 and F7. From Table 13.1, we can ﬁnd that F0= F1= F2= F3= F4= F5 = F6= F7=1. Table 13.1 Content of different registers So, at address 00, the register must be loaded with the value 11111111. Similarly, ﬁnd the corresponding Address of registers Contents of registers 00 1111 1111 values of F0 F1, F2, F3 F4, F5, F6 and F7 at each 01 0000 0000 address location from Table 13.1 and then the values 10 1010 1010 to be loaded into the memory register for all other 11 1111 1111 address. The number of registers in a memory device is always a power of 2. If number of address line is 16, the number of registers will be 216 = 64K.
13.2.2
Implementation of Boolean Functions Using PROM
In implementation of combinational logic circuits using PROM, the circuit is expressed in minterms of Boolean functions in the canonical sum of product form. For example, Fig.13.5 shows the implementation of a typical Boolean functions as given below
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F = –xy– + –xy + xy– + xy, F1 = –xy– + xy F2 = –xy– + –xy + xy– and F3 = –xy– + x–y + xy. The PROM has two inputs x, and y and four outputs F0, F1, F2, F3 which are used to express the Boolean logic functions. The 2 to 4 line decoder decodes all minterms –xy–, –xy, xy– and xy. These minterms are also called as address lines. Actually, PROM is a ﬁxed AND plane (minterms) Fig. 13.5 Implementation of Boolean functions using and a programmable OR plane. Any combinations of the minterms are connected with OR gates for output. A programmable switch is used to establish the connection between minterms and output effectively. Connections with Fig. 13.6 Simpliﬁed representation of Fig.13.5 in PROM have solid dots and unmarked intersections. The solid dots represent logic 1 and unmarked intersections stands for logic 0. As shown in Fig. 13.5, all minterms are connected with OR gate for F0. Similarly, minterms –xy– and xy are connected with OR gate for F1. The simpliﬁed representation of Fig. 13.5 is depicted in Fig. 13.6. In onedimensional addressing mode, large numbers of input variables are required for a large ROM. To reduce the number of decoders, twodimensional addressing method of ROM is used. The two dimensional addressing scheme is shown in Fig. 13.7, which has eight input variables A0 to A7 for 8 line to 256 line address decoder and four other variables A8 to A11. Four input variables A8 to A11 are used as control signals of 16:1 multiplexers. In this scheme, 256 × 128 Fig. 13.7 Structure of a 32768 bit or 4Kbyte address in two dimensions = 32768 bit connections are needed to make the ROM matrix. It consists of 256 input lines and 8 × 16 =128 output lines.
Programmable Logic Devices
13.2.3
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Implementation of Sequential Circuits Using PROM
Sequential circuits are basically combinational circuits with feedback paths. PROMs can be used for implementation of synchronous and asynchronous sequential circuits. The block diagram of sequential circuit using ROM is illustrated in Fig.13.8. Here, present state is feedback to the nextstate decoder. The output of PROM A0+ A1+ … An1+ are fed to D ﬂipﬂops which are driven by a common clock pulse and ﬂipﬂops output are connected with PROM as feedback signals. The next state output of Y depends on input X (X0 X1….Xn1) and feed back inputs A0+ A1+ … An1+ . Therefore, Y = f (X, A0+ A1+ … An1+ ).
Fig. 13.8
Generalised sequential circuit using PROM
PROMs are ﬁxed AND array, and programmable OR array. It can implement all minterms and any OR combinations. Design of combinational and sequential circuits using PROM is very easy, as minimisation of logic function does not required. It is very chip compared to other PLDs but it’s all product terms are not used. Therefore, complete memory will not be used in optimized way and power consumption increases with number of input variables. Example 13.1
Design a PROM structure to implement following Boolean functions
F1 = m(0, 2, 5,7) F2 = m(1, 3, 4) F3 = m(0, 2, 3, 5,7)
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Digital Electronics: Principles and Applications
� Solution The largest minterm of Boolean logic functions is 7. Therefore, it is 3 variable functions. To implement the Boolean logic functions F1= Σ m(0, 2, 5,7) , F2= Σ m(1, 3, 4) and F3= Σ m(0, 2, 3, 5, 7) a 8 × 3 bit PROM is required. Figure 13.9 shows the PROM structure for implementing Boolean functions F1, F2 and F3. Fig. 13.9
Example 13.2
PROM structure for F1, F2 and F3
Implement the following logic functions F1, F2, F3 and F4 as given below using PROM
F1 = Σm(0, 1,2,3,4,5,7); F2 = Σm(2,4,7,9,11) F3 = Σm(10,12,14,15);
F4 = Σm(1,2,3,5,7,9,13)
� Solution The largest minterm of the four simultaneous logic functions is 15. So a 4 line to 16 line decoder is used to decode minterms m0 to m15. To implement the Boolean logic functions F1= Σm(0, 1, 2, 3, 4, 5,7), F2= Σm(2, 4, 7, 9, 11), F3= Σm(10,12,14, 15) and F4= Σm(1,2,3,5,7,9,13) a 16 × 4 bit PROM is required. Figure 13.10 shows the implementation of F1, F2 F3 and F4 using PROM.
Fig. 13.10
PROM structure for F1, F2, F3 and F4
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Programmable Logic Devices
Example 13.3 �
Design a 2 bit comparator using PROMs
Solution
Table 13.2 shows the comparison of two 2bit binary numbers. Here, the ﬁrst data is A1 B1 and second data is A0 B0. When A1B1 is greater than A0 B0, G = 1. If A1B1= A0 B0, E = 1. When A1B1 is less than A0 B0, L=1. The implementation of 2bit comparator using PROMs is depicted in Fig.13.11. Four inputs A1, B1, A0, B0 generates 16 minterms using 4 line to 16 line decoder. The Boolean logical expressions of L, E and G are as follows — —— — L = A0 A1 + A0 B0 B1 + B 0 A1 B1 — —— — — — — — E = A1 B1 A0 B0 + A1 B1 A0 B0 + A1 B1 A0 B0 + A1 B1 A0 B0 and — — —— G = A0 A 1 + A0 B0 B1 + B0 A1 B1. The L, E and G can also be expressed in terms of minterms as given below: L = Σm(1, 2, 3, 6,7,11); E=Σm(0, 5,10, 15) and G= Σm(4, 8, 9,13,14,15).
Table 13.2 2bit Comparator
First Data B1 A1
Second Data A0 B0
minterms Less Than Equal Greater than M L E G
0
0
0
0
m0
0
1
0
0
0
0
1
m1
1
0
0
0
0
1
0
m2
1
0
0
0
0
1
1
m3
1
0
0
0
1
0
0
m4
0
1
1
0
1
0
1
m5
0
0
0
0
1
1
0
m6
1
0
0
0
1
1
1
m7
1
0
0
1
0
0
0
m8
0
0
1
1
0
0
1
m9
0
1
1
1
0
1
0
m10
0
0
0
1
0
1
1
m11
1
0
0
1
1
0
0
m12
0
0
1
1
1
0
1
m13
0
0
1
1
1
1
0
m14
0
1
1
1
1
1
1
m15
0
0
0
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Digital Electronics: Principles and Applications
Fig. 13.11
Example 13.4
PROM circuit of 2bit comparator
Design a 7segment decoder using PROM structure
� Solution The decimal number 0 to 9 can be displayed by the binary coded decimal inputs. Figure 13.12 shows the display of decimal numbers 0 to 9 in seven segment displays. For example, the segments a, b, c, d, e, and f will be bright for decimal number 0. Similarly, other numbers will be display. Table 13.3 shows the different segments will be Fig. 13.12 7 segment display of decimal numbers bright for decimal number 0 to 9. The outputs a, b, c, d, e, f and g are expressed in terms of mean terms as given below: a = m(0,2,3,5,7,8,9), b = m(0,1,2,3,4,7,8,9), c = m(0,1,3,4,5,6,7,8,9) d = m(0,2,3,5,6,8), e = m(0,2,6,8), f = m(0,4,5,6,8,9) and g = m(2,3,4,5,6,8,9). A BCD to 7segment decoder can be implemented with a ROM as shown in Fig. 13.13 using 16 × 8=128 bit ROM. As only seven columns are used, one column must be in don’t care state
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Programmable Logic Devices Table 13.3 Truth table for seven segment display
Decimal Number
A
Inputs B C
D
a
b
c
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 0 1 1 0 1 0 1 1 1 x x x x x x
1 1 1 1 1 0 0 1 1 1 x x x x x x
1 1 0 1 1 1 1 1 1 1 x x x x x x
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Outputs d e 1 0 1 1 0 1 1 0 1 0 x x x x x x
1 0 1 0 0 0 1 0 1 0 x x x x x x
f
g
1 0 0 0 1 1 1 0 1 1 x x x x x x
0 0 1 1 1 1 1 0 1 1 x x x x x x
Fig. 13.13 PROM circuit of 7segment decoder
Example 13.5
Design Binary to ASCII code conversion using PROM
� Solution Truth table of binary to ASCII code conversion is shown in Table 13.4. The outputs A6 , A5 , A4 , A3 , A2 , A1 and A0 are expressed in terms of mean terms as given below. The implementation of Binary to ASCII code conversion using 16 × 8 = 128 bit ROM is depicted in Fig. 13.14. As only seven columns are used, one column must be in don’t care state. A6 = m(10,11,12,13,14,15) A5 = m(0,1,2,3,4,5,6,7,8,9)
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Digital Electronics: Principles and Applications A4 = m(0,1,2,3,4,5,6,7,8,9) A3 = m(8,9) A2 = m(4,5,6,7) A1 = m(2,3,6,7,11,12,15) A0 = m(1,3,5,7,9,10,12,14) Table 13.4 Truth table for Binary to ASCII code conversion
A
Binary B C
D
minterms m
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Fig. 13.14
A6 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
A5 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
ASCII Code A4 A3 A2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
PROM circuit Binary to ASCII code conversion
A1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1
A0 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0
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Programmable Logic Devices Example 13.6
Design a PROM structure to implement the sequence table Table 13.5
clock
X
m
0 1 0 1 0 1 0 1
m0 m4 m1 m5 m2 m6 m3 m7
A1 0 0 0 0 1 1 1 1
A0 0 0 1 1 0 0 1 1
A1+ 0 1 1 0 0 0 1 0
A0+
Y
1 0 0 1 1 0 0 1
1 0 0 1 1 0 1 1
� Solution In the ﬁrst row of Table 13.5, the current input to the ROM is A1= 0, A0= 0 X = 0 and the ROM output word is A1+ = 0, A0+ = 1 and Y = 1. After the application of clock pulse, the ROM outputs A1+ = 0, A0+ = 1 are transferred to the inputs of ROM A1 and A0 . When the ROM input is A1= 0, A0= 1, X = 0, the ROM output word is A1+ = 1, A0+ = 0 and Y = 0. The outputs A1+, A0+ and Y are expressed in terms of mean terms as given below: A1+ = m(1,3,4) A0+ = m(0,2,5,7) Y = m(0,2,3,5,7). The PROM can be used to implement the Table 13.5 with the help of additional logic element, D ﬂipﬂops. Here, D ﬂipﬂops are used for transferring data from the outputs of ROM to the input of ROM on the positive edge of the clock pulse. Figure 13.15 shows the implementation of Table 13.5 using PROM.
Fig. 13.15
Implementation of Table 13.5 using PROM
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13.3
Digital Electronics: Principles and Applications
PROGRAMMABLE LOGIC
In programmable logic of PROM, blowing the fusible link at all intersections of the logic array the device is programmed as per requirement. A typical arrangement of AND, OR and ExOR gates is shown in Fig.13.16. – Here, input X and it’s complement X are connected to a AND gate through bipolar or MOS transistor and fusible Fig. 13.16 (a) Programmable logic of AND gate link. Whe D gate. Therefore, output is in don’t care state. Figure 13.16 (b) shows the connection of product terms with OR gate. Output of OR gate is in SOP form. If fuse link does not blown, S=P. When fuse is not blown, Fig. 13.16 (b) Programmable logic of OR gate S will be in don’t care state. Generally, output of OR gates are connected with XOR gates with fusible link in programmable logic. The typical connection of XOR gate is depicted in Fig. 13.16 (c). When the fuse is in Fig. 13.16 (c) Programmable logic of XOR gate intact state, the input X of XOR gate is grounded and it behaves as transmission gate which means output O=S. If the fuse is blown, the input X – is always in high state or logic 1. Then output O is complement of inputs. So O = S . These Programmable logic of AND, OR and XOR gates are commonly used in all programmable logic devices.
13.4
PROGRAMMABLE LOGIC ARRAY (PLA)
In Programmable Logic Array (PLA), the programmable AND and OR arrays are used in order to realise any Boolean logic functions. Fig. 13.17 shows the block diagram of Programmable Logic Array (PLA). It has ‘n’ inputs, ‘k’ product terms and ‘m’ outputs. The number of product terms ‘k’ must be less than 2n. As all possible 2n product terms are not available, the logic functions must be represented in minimised form before Fig. 13.17 Block diagram of implementation. The ‘m’ number of Boolean logic functions Programmable Logic Array
Programmable Logic Devices
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are implemented using ‘k’ number of AND gates and ‘m’ number of OR gates. The typical structure of PLA AND array and PLA OR array are explained in this section.
13.4.1
Fig. 13.18
13.4.2
Structure of AND array
PLA AND Array
A typical structure of AND array is shown in Fig.13.18. It has ‘k’ AND gates with product outputs P0 through Pk–1. Each AND gate has ‘2n’ — — — —– inputs D0,D0, D1, D1, D2, D2....... Dn–1, Dn–1. As each AND gate has all input variables and the entire fusible link are intact, the output of unprogrammed — — — —– AND gate will be D0 D0 D1D1D2D2.......Dn–1Dn–1. After programming, each AND gate can be used to generate a product term with proper selection of input variables. Actually product terms are formed by selectively blowing fuses at intersection of data inputs and AND gate. When all intersection fuses of AND gate are blown, AND gate output is in don’t care state.
PLA OR Array
Figure 13.19 shows the structure of an OR array to generate ‘m’ output functions F0, F1, F2….Fm1. There are ‘k’ product lines P0 to Pk–1 and all product lines are connected with an OR gate. The output of OR gate is the logical sum of the product terms. When all the fuse links are intact, output F0=F1= …Fn–1= P0 + P1 + P2…+ Pn1. The OR array is also programmable by blowing fuse links. If the entire fuse links except P2, P3 and P4 of ﬁrst OR gate are intact, then output will be F0=P2+ P3 + P4. A typical PLA has 2 inputs A, B that can produce 4 product terms and four outputs as shown in Fig. 13.20. All input connections of AND gate and OR gate are programmable. Therefore, PLA has more ﬂexibility than Fig. 13.19 Structure of an OR array PROM and PAL, but the circuit representation is very complex. After blowing the connecting –– fuses, the output functions F1, F2, F3 and F4 are implemented as depicted in Fig.13.21. Here F1 = A B + –– – – –– – –– – AB, F2 = A B + A B + AB + AB, F3 = A B + A B + AB and F4 = A B + AB + AB.. In this ﬁgure, a dot signiﬁes that fuses are intact and without dot means that fuses are blown and there is no connection. The simpliﬁed representation of Fig. 13.21 is illustrated in Fig. 13.22.
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Digital Electronics: Principles and Applications
Fig. 13.20 Structure of a typical PLA with two input and four outputs
Fig. 13.21
Implementation of logic functions F1, F2, F3, and F4 using PLA
Programmable Logic Devices
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Fig. 13.22 Simpliﬁed representation of Fig.13.21
13.4.3
PLA ICs
Most commonly used PLA ICs are PLS 100, PLS 105, 82S100, 82S101, 82S105, 82S200, 82S201, 82S205, and PLUS 405 to implement combinational as well as sequential logic circuits. The PLS100 (3State) and PLS101 (Open Collector) are bipolar fuse Programmable Logic Arrays. These devices utilise the standard AND/OR/Invert architecture for implementing sum of product equations. Figure 13.23 shows the pin diagram of PLS 100 and the logic diagram of PLS 100 is depicted in Fig.13.24. This PLA IC has 16 inputs I0 to I15 and eight outputs F0 to F7. Each input is fed to a driver circuit to generate both inverted and noninverted inputs for AND gates. Each AND gate has 32 inputs and there are 48 product lines as 48 AND gates are available in this IC. OR gates have 48 inputs. Therefore, each OR gate bus is a 48 line bus. All intersections between the horizontal input lines and vertical input lines are programmable. For inverting and noninverting operation of output, OR gate ouput is fed to XOR gate. When the fuse is intact, the output will be noninverting. If the fuse is blown, the output will be inverting. To increase the driving capability of the PLA, the output of XOR gates are connected with —– tristate drivers with a common external enable signal C E . If —– —– C E is low, the outputs are all turned on. When C E is high, the outputs are in high impedance state. Application of PLS100 in combinational logic circuit is given in Example 13.11. Fig. 13.23 PIN diagram of PLS100
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Digital Electronics: Principles and Applications
Fig. 13.24
13.4.4
Logic diagram of PLS 100
Programming PLA ICs
A PLA programmer is used for programming an PLA devices. PLAs are generally available with fusible links and erasable programmable devices for implementation of digital circuits. For programming, most commonly used software’s are SNAP, PALASM, ABEL, CUPL and SLICE. All software packages allow Boolean and state equation entry formats. Actually, the required inputoutput relationship is developed inside a PLA ICs through programming. During manufacturing of mask programmable PLA
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Programmable Logic Devices
ICs, the data pattern according to design speciﬁcation are generated by the manufacturer. In fusible link programmable PLA, all fuses links are intact at the time of manufacturing. During programming some fuse links are blown by applying voltages at the inputs and outputs of the device to develop speciﬁed logic pattern in IC. This type of PLA is not reprogrammable. The design procedure of a PLA based circuit is given below: Step1
Write the truth table of digital logic circuit, which will be implemented.
Step2
Draw the Kmap for each output with in variations of input variables and derive the simpliﬁed boolean logic expressions in SOP form.
Step3
Simplify the Boolean logic expressions to get minimum SOP form.
Step4
Determine the number of product terms and their logical expressions. Then ﬁnd the input connections of AND gate to generate all required product terms.
Step5
Determine number of OR gates to implement output functions and ﬁnd the input connection of OR array to generate SOP form outputs.
Step6
Find the requirement of programming of XOR gates for invert or noninverting the SOP o