CMOS operational amplifiers (Op Amps) are one of the most important building blocks in many of todays integrated circuit
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Table of contents :
Chapter 1 Basic Specifications of Op Amps..............1
Chapter 2 CMOS Technology and Physics..............15
Chapter 3 CMOS Differential Amplifiers..............33
Chapter 4 CMOS SingleEnded Output Op Amps..............55
Chapter 5 CMOS Fully Differential Op Amps..............107
This book presents important details and design methodologies for different architectures of singleended op amps. Complete chapters are dedicated to the critical issues of CMOS output stages, fully differential op amps, and CMOS reference generators. Also included is an introduction to CMOS technology and a discussion of the basics of the physical aspects of MOS transistors, providing the foundation needed to fully master the material. Rasoul Dehghani is an assistant professor in the Department of Electrical and Computer Engineering at Isfahan University of Technology in Iran. He holds a Ph.D. in electronics from Sharif University, Tehran, Iran. He is a wellpublished and frequently cited author in the field.
Include bar code ISBN 10: 1608071537 ISBN 13: 9781608071531
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LONDON
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ni
Design of CMOS Operational Amplifiers
CMOS operational amplifiers (op amps) are one of the most important building blocks in many of today’s integrated circuits. This cuttingedge volume provides professionals and students with an analytical method for designing CMOS op amp circuits, placing emphasis on the practical aspects of the design process. Readers take an indepth look at CMOS differential amplifiers and learn why and how they serve as the main part of any op amp.
ha
Rasoul Dehghani
De Op sig Am er n Ra p at of so li io C f n M ul ie a OS De rs l hg
Dehghani
Design of CMOS Operational Amplifiers
Design of CMOS Operational Amplifiers
For a complete listing of titles in the Artech House Microwave Library, turn to the back of this book.
Design of CMOS Operational Amplifiers Rasoul Dehghani
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ISBN 13: 9781608071531
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10 9 8 7 6 5 4 3 2 1
Contents Chapter 1 Basic Specifications of Op Amps 1.1 Op Amp Parameters 1.2 Conclusion
1 1 13
Chapter 2 CMOS Technology and Physics 2.1 Basic Processes in MOS Transistor Fabrication 2.2 Principles of MOS Transistor Functioning 2.2.1 MOS Transistor Operating in Saturation Region 2.2.2 MOS Transistor Operating in Subthreshold Regime 2.3 SmallSignal Model of MOS Device 2.3.1 Gate to Substrate Capacitance 2.3.2 Gate to Source/Drain Capacitance 2.3.3 Source/Drain to Bulk Capacitance 2.4 Conclusion
15 15 17 17 21 21 24 26 27 31
Chapter 3 CMOS Differential Amplifiers 3.1 SourceCoupled Differential Pair Characteristic 3.2 CMOS Differential Amplifier with Active Load 3.2.1 LargeSignal Characteristic of CMOS Differential Amplifier 3.2.2 Offset Voltage of CMOS Differential Amplifier 3.3 CommonMode Behavior of CMOS Differential Amplifier 3.4 CMOS Differential Amplifier Frequency Response 3.5 Noise Calculations in CMOS Differential Amplifier 3.6 Conclusion
33 33 36
Chapter 4 CMOS SingleEnded Output Op Amps 4.1 CMOS TwoStage Op Amp 4.1.1 Offset Voltage 4.1.2 TwoStage Op Amp Frequency Response 4.1.3 CMOS TwoStage Op Amp Design Procedure Design Example 4.1.4 PSRR of CMOS TwoStage Op Amp 4.2 Telescopic Cascode Op Amp 4.3 FoldedCascode Op Amp Design Example 4.4 Current Mirror Op Amp Design Example 4.5 RailtoRail Input Op Amp 4.6 Conclusion
36 38 42 43 47 53 55 55 56 59 65 69 72 83 86 87 90 94 96 105
v
vi
Contents
Chapter 5 CMOS Fully Differential Op Amps 5.1 Advantages of Fully Differential Op Amps 5.2 CommonMode Feedback Concept 5.3 CommonMode Feedback Circuits 5.3.1 CommonMode Feedback Circuit with Resistive Sensing 5.3.2 Differential Difference CommonMode Feedback Circuit 5.3.3 CommonMode Feedback Circuit Using MOS Devices Operating in the Triode Region 5.3.4 SwitchedCapacitor CommonMode Feedback Circuit 5.4 Fully Differential CMOS Op Amp Architectures 5.4.1 Fully Differential TwoStage Op Amp 5.4.2 Fully Differential Current Mirror Op Amp 5.4.3 Fully Differential FoldedCascode Op Amp Design Example 5.5 Conclusion
107 107 109 111
118 119 123 123 127 129 130 134
Chapter 6 CMOS Output Stages 6.1 Class A and Class B Output Stages 6.1.1 SourceFollower as an Output Stage 6.1.2 Class B Power Amplifier 6.2 DrainCoupled Complementary Transistors as Output Stage 6.3 LowVoltage Class AB Buffer 6.4 Class AB Output Stage Using a Translinear Loop 6.5 Case Study Design Example 6.6 Conclusion
135 135 135 139 142 149 153 159 163 166
Chapter 7 CMOS Reference Generators 7.1 CMOS Voltage Reference Generators 7.1.1 Bandgap Voltage Reference Generator Design Example 7.1.2 LowVoltage Bandgap Reference Generator Design Example 7.1.3 CMOS Voltage Reference Generator without Resistors 7.2 CMOS Current Reference Generators 7.2.1 GmConstant Circuit 7.2.2 Fully Integrated Precision CMOS Current Reference 7.2.3 CMOS Current Reference without Resistors Design Example 7.3 Conclusion Index
167 167 168 170 173 174 176 180 182 186 188 191 193 195
112 114
Chapter 1 Basic Specifications of Op Amps An operational amplifier is one of the most important building blocks in many analog systems. For instance, in an integrated analog filter such as a switchedcapacitor or a GmC filter, the op amp is an integral part of the circuit. Data converters including both analogtodigital and digitaltoanalog converters are other categories in which the op amp plays a fundamental role to achieve the desirable performance. In voltage and current reference generators an op amp has remarkable influence on the operation of these circuits. In the enumerated instances many parameters of the system are extensively dependent on the specifications of the op amps used in that system. It should be noted that the criteria applied to the design of an op amp employed in such systems are usually different from those used for designing a generalpurpose op amp that is to be available as a standalone component in discrete circuitries. In general, the behavior of an op amp is described by many different parameters in which some of them might be more important than others in a particular analog system. In this chapter we introduce the main op amp parameters that have significant impact on the behavior of an analog system where an op amp has been exploited.
1.1
Op Amp Parameters
DC gain: Ideally the value of this parameter is considered infinity but in reality, due to the limited intrinsic voltage gain of each device used in the op amp circuit, the entire gain of an op amp has a finite value in the typical range of to (40 dB100 dB). Exploiting an op amp in a linear amplifier involves putting the op amp in a negativefeedback loop. In this situation a high dc gain of the op amp could be essential. In the following we demonstrate the reason for such an assertion. Supposing that the openloop gain of the feedback is quite high, we can calculate the closedloop gain of the circuit based on the values of the feedback network components independent of the op amp parameters. As an example consider the inverting feedback amplifier shown in Figure 1.1. Denoting the , we can calculate the exact lowfrequency voltage gain of the op amp as
1
2
Basic Specifications of Op Amps
C2
vi
C1
−
vo
+ Figure 1.1 Inverting feedback amplifier.
closedloop voltage gain as (1.1) Where is the feedback factor. If it is assumed that , (1.1) can be approximated as . In an ideal case, for , the amplifier gain is completely independent of the op amp gain and equals . In practice, for a particular feedback gain error, we need to increase the op amp gain above a certain level. For example, ideal feedback gain of 2 with an error less than 0.1% is achievable provided that or if we have . Thus, in order to achieve more accurate feedback gain the dc gain of the op amp needs to be quite high. Limited linearity range. For a certain level of the input and output signal variations, the internal devices of op amp operate in the linear part of their characteristics. At input, the devices remain in their active operation region when the variation range of the input commonmode voltage is limited to a particular range known as input commonmode range (ICMR) [1]. This parameter depends on the op amp structure and the type and biasing conditions of the input devices. The linear operation range for a differential input signal in an openloop state is much more limited. Of course when an op amp is used in a negativefeedback loop, the linearity behavior is significantly improved by the feedback mechanism. An amplified signal at the output of an op amp can also swing in the limited range at the most between two supply rails, although its precise level depends on the particular structure utilized as the output stage. Commonmode rejection ratio. One of the most outstanding advantages of an op amp is its capability to amplify the difference of two input signals without output being affected significantly by the changes in the input commonmode level. This property results in immunity against any commonmode undesirable signal that
1.1 Op Amp Parameters
3
might appear at the inputs of the op amp. The parameter of commonmode rejection ratio (CMRR) is used to quantify this performance [2]. The definition of this parameter is a little bit different for the two types of op amp. In a fully differential op amp in which both input and output signals are differential, the differentialmode and commonmode components of the output voltage are expressed as a linear combination of the corresponding input voltages as follows !"#
$# !%$
!"$
## !%#
$$ !%$
(1.2a)
#$ !%#
(1.2b)
where ## and $$ are differentialmode and commonmode voltage gains, respectively. $# and #$ exhibit the contribution of the commonmode and differentialmode of the input; that is, !%$ and !%# in their corresponding components in the output voltage, respectively. In an ideal differential op amp with a fully symmetrical structure, we have $# but in reality, due to #$ the device mismatches in the path of each input to two other outputs, this is not the case. In this situation, CMRR is defined as the ratio of the differential voltage gain ## to the commonmode to differentialmode voltage gain $# as & ''()
*
++ ,+
*
(1.3)
where & ''() denotes the fully differential CMRR. To measure the & ''() , we might exploit the circuit illustrated in Figure 1.2. The fully differential op amp is configured as a unity voltage gain amplifier in a negativefeedback loop. The internal commonfeedback circuit and the external negativefeedback cause the output commonmode voltage and also the dc level of each output to be kept on the commonmode reference voltage denoted by $. . Representing the voltages at the inverting and noninverting inputs of the op amp as ! / and ! , respectively, we can easily find these voltages as follows !/
!"
!
!"/
$. $.
$0
(1.4a)
$0
(1.4b)
From the above relations, the input differentialmode and commonmode voltages are obtained
!%$
!%# !
!
!/
!/
!"$
!"# $.
(1.5a) $0
(1.5b)
4
Basic Specifications of Op Amps
R
R

+
+ vod
R
+ 
Vcm
vo
R
+ Vcr
vo+

Figure 1.2 Test circuit used to measure the CMRR for a fully differential op amp.
By substituting (1.5a) and (1.5b) into (1.2a) and simplifying the result, we get !"#
1,+ 2 1++ 2
!"$
$.
$0
(1.6)
Now when the input voltage of $0 is changed by 3$0 , the terms of !"$ and $. have no variation and thus we have 3!"$ 3$. . That gives 3!"#
Since
##
1,+ 2 1++ 2
3$0
(1.7)
, we have 34 +
34,5
,+
++
67 889:
(1.8)
It should be emphasized that the gain of $# is not zero only when the mismatches in the op amp circuit are considered. As a result, we have to perform an ac analysis for several Monte Carlo simulation runs and obtain the corresponding voltage gain of 3!"# 3$0 for each run. Since the amount of the mismatch changes in each run, we get various voltage gains whose mean value can be used to calculate the typical & ''() . As an example, in a fully differential op amp, 100 runs of Monte Carlo analysis give 3!"# 3$0 ;< = >? as the mean value of the data with a standard deviation of @ A = >? and thus for this op amp
1.1 Op Amp Parameters
5
the typical value of the CMRR becomes ;< = >?. The worstcase value could reach B >? in the range of C@. In an op amp with singleended output the output voltage is represented by !"
#0 !%#
$0 !%$
(1.9)
where #0 and $0 are differentialmode and commonmode voltage gains, respectively. Here CMRR is defined as & ''DE
*
+5 ,5
*
(1.10)
where & ''DE indicates the CMRR of a singleended output op amp. As it will be shown in the next chapters, in a fully differential op amp a high CMRR is achievable by implementing a fully symmetrical circuit to minimize $# . In a singleended one, even when the op amp has a perfect symmetry in an ideal condition, the CMRR would be limited by the output resistance of the tail current source used in the differential pair. One method to measure the CMRR for a singleended output op amp is shown in Figure 1.3 [3]. In this circuit we have ! $0 and ! / !" $0 . Since !%# ! ! / and !%$ ! !/ , by substituting these relationships into (1.9), we can write the output voltage as !"
#0 !"
$0
F$0
G
(1.11)
Rearranging (1.11), we obtain the transfer function as ,5 1,5 +5 / 2
4,5
(1.12)
Noting that #0 H $0 , we see that the inverse of the obtained gain in (1.12) approximately gives the & ''DE . Offset voltage. The device mismatches in the input stage have the most
Vcm
+ −
−
vo
+ + V − cm
Figure 1.3 Measurement of the CMRR parameter for a singleended output op amp.
6
Basic Specifications of Op Amps
contribution in this parameter. It is interesting that the nonzero commonmode voltage gain of an op amp also contributes to the input offset voltage [4]. To see that, from (1.9) for !%# , we have !" $0 !%$ . This means the op amp output voltage varies in response to the input commonmode voltage variation in spite of the fact that the differential mode of the input voltage has no variation. In this situation, the op amp can be thought of as an ideal op amp in a sense that it just reacts to the differential mode of the input voltage and the effect of the input commonmode changes is attributed to an equivalent differential input voltage with the value of %HIJ !" #0 or %HIJ $0 !%$ #0 . Therefore in an op amp with nonzero commonmode voltage gain, the voltage of %HIJ %$ & '' is added to the inputreferred offset voltage. The main parameters of an op amp that affect the offset voltage will be discussed in more detail in the next chapters. Figure 1.4 represents two circuits to measure the offset voltage of singleended and fully differential op amps. Both op amps are configured as a voltage follower without any external input. The leftside circuits depict the real op amps including mismatches with finite CMRR. All nonideal effects that create the offset voltage such as mismatches and nonzero commonmode voltage gains of $0 and $# have been modeled by a dc voltage source denoted by "K that is placed in series with the input of an ideal op amp. Hence, the output voltage relationships for two types in an ideal case are !" #0 !%# and !"# ## !%# . Summing voltages around the loop from the output to the input yields !%# "K !" for the singleended op amp and !%# "K !"# for the other one. Substituting these relationships into the corresponding equations of the output voltages gives us the offset voltages as Real includes mismatches Ideal
−
−
vid +
vo
+ Vos
vo
+
+ −
(a) Real includes mismatches Ideal
−

+ vod 
vid + Vos
+ −
+
+
− +
+ 
+ vod 
(b)
Figure 1.4 Test circuits for (a) singleended (b) fully differential op amp offset voltage.
1.1 Op Amp Parameters
7
!"HDE "K #0 "K ## #0 and !"H() ## for singleended and fully differential types, respectively. Since #0 H ## , the output voltages of both circuits nearly represent the offset voltage. It should be pointed out that similar to the method used for measuring CMRR of a fully differential op amp, the op amp offset voltage can be obtained by running several Monte Carlo analyses on the circuits of Figure 1.4 and taking the standard value of the data as the op amp offset voltage. In the absence of systematic errors the mean value of the offset voltage is almost zero. Frequency bandwidth. The openloop voltage gain of an op amp begins to drop as frequency increases. This happens because of internal parasitic capacitances in the op amp circuit. The bandwidth parameter is important because by dropping the op amp voltage gain, the closedloop gain would not be independent of the op amp parameter anymore. In fact, the frequency bandwidth expresses how fast an op amp can follow the time variations in the input signal. It is obvious that to amplify fast signals we need to employ an op amp with adequate large bandwidth in such a way that it can provide enough loop gain at maximum operating frequency. The speed performance of an op amp is usually measured by the unity gain bandwidth parameter denoted by LM , as illustrated in Figure 1.5. As its name suggests, LM is a frequency at which the magnitude of the gain reaches unity. When an op amp is used as a voltage follower in a negativefeedback loop, it might suffer from the instability problem at frequencies near LM . Thus the op amp should be properly designed to have an acceptable amount of stability in the frequency domain [5]. Slew rate. This parameter is used to express the time speed limitation of an op Av(jω) Av0
ωp2 0
ωp1
Figure 1.5 Op amp voltage gain versus frequency.
ωu
ω
8
Basic Specifications of Op Amps vi(t)
Input step voltage
V
vo(t) vi(t)
t
0
− +
vo(t)
Output response
V (a)
tsettle
tslew
t
0 (b)
Figure 1.6 (a) Voltage follower, and (b) time response of voltage follower to input step voltage.
amp output. When an op amp is placed in a negativefeedback loop and a rather largesignal is applied to its input, the output cannot follow the rapid changes in the input signal. This is another speed limitation in op amps that is raised in conjunction with the largesignal behavior of op amps. Indeed, unity gain bandwidth indicates the limitation of an op amp to follow the fast input signals with very small amplitude while slew rate is considered an index of op amp largesignal time response [6]. In some applications such as pipeline analogtodigital converters, both parameters play a key role in determining the maximum achievable speed for the converter [7]. The response of a voltage follower to a step voltage applied as input is plotted in Figure 1.6(b). As it can be seen, the output time response consists of two parts. The first part is the time duration that the output voltage changes from its initial value to approach its final level. This part is associated with the limited op amp slew rate. The second part starts when the difference between input and output voltages is small. Now the smallsignal frequency response of the op amp determines how long it takes to reach its steady state. This time, known as settling time, is illustrated in Figure 1.6(b). Noise. A complementary metal oxide semiconductor (CMOS) op amp is made of several numbers of ntype MOS (NMOS) and ptype MOS (PMOS) transistors. Channel thermal noise and flicker noise are two main noise sources in each MOS device [8]. The total noise generated by each device is represented by two generally correlated noise voltage and noise current generators at the input of an op amp. Flicker noise has a higher level of energy at low frequencies while thermal noise has a flat spectrum in the frequency domain. The variation of the spectral density of the inputreferred noise voltage including both flicker and thermal noises is plotted in Figure 1.7. In this plot the thermal noise and flicker
1.1 Op Amp Parameters
9
Vn 2
f Kf
f
4kTReq
0
f
fc
Figure 1.7 Spectral of inputreferred noise voltage.
noise asymptotes intersect each other at a frequency called the flicker noise corner frequency that is denoted by $ . In submicron CMOS technology, due to some physical effects such as the hot electron effect, the level of the thermal noise in the MOS device increases. According to Figure 1.7, the part of the frequency band that is less than $ is mostly influenced by the flicker noise. At the frequencies near zero there is no noticeable difference between the input offset voltage and the flicker noise at the input. Power supply rejection ratio. The amount of supply noise or any other disturbances on the supply rail that can find its way to the op amp output depends on this parameter [9]. Mathematically the power supply rejection ratio (PSRR) in an op amp is defined as NO''
P +P Q
(1.13)
where # is the differential voltage gain of the op amp and R is the voltage gain from each supply to the op amp output. Supposing the op amp as a linear circuit, we express its output voltage as a linear combination of the differential input voltage and the noise voltage on the supply !"
# !%#
R !R
(1.14)
In (1.14) the first term is the desirable signal component and the second one indicates the amount of supply noise at the output. Indeed, PSRR represents the ratio of the desired signal to the supply noise at the op amp output. Since op amps have two supply rails, two parameters of NO'' and NO''/ are usually defined
10
Basic Specifications of Op Amps
in which the corresponding voltage gain from positive and negative supply is denoted by R and /R , respectively. In an integrated analog mixedmode circuit where different analog and digital blocks are fabricated on the same chip, special attention should be paid to the PSRR parameter of op amps used in the circuit [10]. For example, if the PSRR of an op amp is not good enough, any existent noise on the supply rail such as digital noise created by the system clock can reach the op amp output and amplified by the next stages can easily corrupt the quality of the ultimate output signal. In addition, the behavior of PSRR at higher frequencies is also important. In fact, the magnitude of this parameter at high frequencies determines the amount of highfrequency supply noise that impacts on the op amp output signal. In practice, PSRR can be measured by employing the circuit shown in Figure 1.8. Assuming a finite differential voltage gain of # for op amp and denoting the voltage gain from supply to the output by R , we can write !"
R !R
# !"
(1.15)
Rearranging (1.15), we have
Since
#
!"
+
Q
!R
(1.16)
, we can obtain the PSRR as NO''
Q
(1.17)
The circuit in the path from positive supply to the output is generally different from the other path from negative supply to the output; thus, two different PSRR parameters are usually defined for two op amp supply rails.
+ vo 
−
vo
Ad
+ + vp 
Figure 1.8 Circuit used to measure PSRR.
1.1 Op Amp Parameters
11
PSRR in a fully differential op amp has a similar relationship given in (1.13) in which # is replaced with ## . It should be pointed out that if the circuit of the fully differential op amp has perfect symmetry in an ideal case, the noise of supply appears equally on both outputs and as a result there is no differential output voltage. In reality, device mismatches in the op amp circuit reveal their contributions as nonzero differential output voltage. Thus the mismatch is responsible for nonzero PSRR in fully differential op amps. This means that to measure PSRR we have to follow the procedure that was given to measure & ''() . We can use the circuit of Figure 1.2 in which an ac voltage source is placed in series with the supply while just commonmode voltage reference $. is applied to the input. Repeating the given method for CMRR calculation, we obtain 3!"#
Q 1++ 2
3!R
(1.18)
Equation (1.18) represents the change in the differential output owing to the variation in the supply voltage. The parameter R denotes the voltage gain from supply to the output. Since ## , from (1.18), PSRR is given by NO''
++ Q
3S + 3SQ
(1.19)
By performing Monte Carlo analysis we can obtain the voltage gain from supply to the differential output in different runs. Such simulation on the previous example given for CMRR calculation produces the result of 3!"# 3!R A T >? as the mean value of data that based on (1.19) gives NO'' A< T >? while its standard deviation is @ ; >?. This result reveals that in the op amp of our example, the supply noise compared to the input commonmode voltage variation is more effectively passed to the op amp output in the presence of mismatches.
12
Basic Specifications of Op Amps
Table 1.1 Some Main Parameters of a Typical CMOS Op Amp Parameter Name DC voltage gain
Input commonmode range
Parameter Symbol 4
ICMR
Relationship
Value in Ideal Case
Typical Value in a Real Op Amp
Unit
Depends on structure
Infinity
40120
dB
%$H0UV
%$H0UV
CMRR
Fully differential * ++ *
Offset voltage
"K
Depends on mismatches in threshold voltage and sizing
Unity gain bandwidth
LM
Commonmode rejection ratio
,+
Singleended output op amp * +5*
V
Infinity
> 80
dB
Zero
80
,5
In most singlestage op amps X0H%Y Z
Slew rate
SR
Usually as W
Power supply rejection ratio
PSRR
P
Inputreferred noise voltage
))
= W &' )) (e.g., in a simple NMOS input op amp)
Y
+5 Q
Z
P
Channel thermal noise and flicker noise referred to the input
Zero
^
`ab ^ _ `ab ;
[ \]
dB
c[ d`a
1.2 Conclusion
1.2
13
Conclusion
In this chapter, several important dc and ac parameters of op amps were introduced and some methods were presented that can be used to measure these parameters. The discussed parameters are associated with both singleended output and fully differential op amps. We have summarized some main parameters of a typical CMOS op amp that were briefly discussed in this chapter as illustrated in Table 1.1. It is worth keeping in mind that the exact relationship for each parameter in this table depends extensively on the particular structure used in the op amp circuit that will be the subject of the next chapters. The given numerical data for some parameters indicate typical values that are usually observed in currently designed CMOS op amps.
References [1]
Huijsing, J., Operational Amplifiers: Theory and Design, Second Ed, Springer, 2011.
[2]
Baker, R. J., CMOS: Circuit Design, Layout, and Simulation, Third Ed, John Wiley & Sons, 2010.
[3]
Allen, P. E., Holberg, D. R., CMOS Analog Circuit Design, Second Ed, Oxford University Press, 2002.
[4]
Mancini, R., Carter, B., Op Amps for Everyone, Third Ed, Elsevier Inc., 2009.
[5]
Ivanov, V., Filanovsky, M., Operational Amplifier Speed and Accuracy Improvement: Analog Circuit Design with Structural Methodology, Kluwer, 2004.
[6]
Baher, H., Signal Processing and Integrated Circuits, John Wiley & Sons, 2012.
[7]
Plassche, R., V., D., CMOS Integrated AnalogtoDigital and DigitaltoAnalog, Second Ed, Boston, Kluwer Academic Publisher, 2003.
[8]
Bhattacharyya, A. B., Compact MOSFET Models for VLSI Design, John Wiley & Sons, 2009.
[9]
Shepherd, P. R., Integrated Circuit Design, Fabrication and Test, McGrawHill, 1996.
[10] Gejji, V. P., Analog and Mixed Mode VLSI Design, PHI Learning Private Limited, New Delhi, 2011.
Chapter 2 CMOS Technology and Physics A part of the limitation in the performance of a CMOS circuit is related to how it is implemented. Therefore a comprehensive perception of the CMOS circuit fabrication and the required steps to get the final desirable circuit can significantly aid in achieving a successful design. Furthermore, the advanced semiconductor industry necessitates a close and tight collaboration between circuit designers and process engineers, who need to understand their languages in order to exchange information about possible technological capabilities and also existent constraints in the fabrication process. In this chapter, we briefly describe the main sequence of steps that are followed in the fabrication of an MOS transistor. Next, we introduce the electric current equation for this kind of transistor and based on the physical operation we present a complete smallsignal model of the device. In the given analysis we will refer to some physical effects such as shortchannel behavior, and subthreshold operation region and their impact on the circuit design. Interested readers are referred to the references at the end of the chapter for deeper discussions.
2.1
Basic Processes in MOS Transistor Fabrication
In an nwell process in which all PMOS transistors are to be put inside the nwells, the first step is to create an nwell inside the substrate of a ptype. The ion implantation technique is usually used to create an nwell region. The next step is to create isolation areas between adjacent transistors by growing a thick oxide layer under which an extra ion implantation called channelstop is done to increase the effective threshold voltage of this area. After applying some trimming on the threshold voltage of the active area, the gate pattern is defined and then the source/drain junctions and also psubstrate and nwell contacts are formed by two individual ion implantations for two NMOS and PMOS devices. After source/drain ion implantation, a thermal process needs to be done and thereby the damaged lattice structure is fixed. This process is known as annealing. Because of the thermal process in the annealing, the impurity atoms in these areas penetrate
15
16
CMOS Technology and Physics
underneath the gate electrode due to lateral diffusion. The overlapped part of the gate with the extended part of the source/drain regions creates an overlap parasitic capacitance between the source/drain and gate terminals. These capacitances, especially one that is formed between the gate and drain, can affect significantly the frequency response of the circuits particularly in analog designs. Figure 2.1 summarizes the main steps mentioned above to fabricate two types of MOS devices. The subject of CMOS technology and the fabrication process can be found in [15] in much more detail.
Gate Oxide sio2
Creation of nwell in psubstrate
(1)
nwell psubstrate
Gate Oxide
Channelstop and threshold adjust implant and growth of field oxide
Field Oxide sio2 ChannelStop
(2)
nwell psubstrate
Gate Oxide
Deposition of polysilicon gate of NMOS and PMOS devices
Field Oxide sio2 ChannelStop
(3)
nwell psubstrate
Gate Oxide
Implantation of source, drain, and nwell contacts using two individual masks in two steps for NMOS and PMOS devices
n+
(4)
Figure 2.1 Main steps of MOS device fabrication.
n+
p+
p+
S/D of PMOS S/D of NMOS
psubstrate
nwell
n+
Field Oxide sio2 ChannelStop nwell ohmic contact
2.2 Principles of MOS Transistor Functioning
2.2
17
Principles of MOS Transistor Functioning
Shown in Figure 2.2 is the crosssection view of an NMOS transistor. When a positive voltage is applied to the gate, since the majority carries of the substrate are the holes, they are repelled toward the bulk and as a result, a charge space of the negative ions leaves behind at the surface. In device physics this operating area of the device is known as the depletion mode. By increasing the gate voltage in the positive direction the proper condition is provided for the majority carriers in the source region to be injected into the substrate. More positive gate voltage causes growth of electrons and at the same time reduction of the number of holes. This ultimately leads to inverting the type of the semiconductor from ptype to ntype at the surface. For a certain level of the gatesource voltage, the density of electrons in the created inversion layer would be that of the substrate holes. In this situation the transistor operates at the edge of a state called strong inversion. The corresponding gatesource voltage that puts the device at the edge of the strong inversion condition is known as the threshold voltage and is denoted by e . For fD e , the electrons concentration of the inversion layer is less than that of the substrate holes and the transistor is in a state called weak inversion. This operating area is known as the subthreshold region. In the following sections we deal with the MOS functioning in these two operating areas. 2.2.1 MOS Transistor Operating in Saturation Region In the presence of the conductive layer in a strong inversion state, an applied voltage between the drain and source creates an electric field along the channel and makes the current flow from the source to the drain. By utilizing Ohm’s law and writing the channel conductivity in terms of inversion charge g%Y , it is shown that [6] for a longchannel device the drain current equation in the triode region can be approximated by a quadratic relationship that is a function of the gateG
S
D
n+ FOX
FOX n+ inversion layer p_substrate Figure 2.2 Cross section of an NMOS device.
18
CMOS Technology and Physics
source and drainsource voltages. W)
hY
i "V Z j
fD
e )D
2 4:k
l
(2.1)
where hY is the electron mobility in the inversion layer, "V m"V n"V is the gate oxide capacitance per unit area with m"V as the oxide permittivity and n"V as the gate oxide thickness, and o and p are the transistor channel width and length, respectively. At a given fD e , increasing the drainsource voltage causes the density of the free electrons of the inversion layer at the drain side to decrease, and ultimately for f) e the electron charges at drain almost disappear such that the device is put at the edge of the saturation region. The certain value of the drainsource voltage at which the device is at the edge of saturation will be )D HKUq
fD
e
(2.2)
For )D )D HKUq , the depletion region of the drainbulk junction extends toward the source. The excess voltage of )D )D HKUq extends across the depletion region of the drain to the bulk junction and the voltage drop across the inversion layer is kept on )D HKUq . This situation is very similar to the behavior of a bipolar junction transistor (BJT) operating in an active forward region in which the major part of the collector to emitter voltage drops across the reversebiased collectorbase junction and a small part of the total voltage drops across the forwardbiased baseemitter junction. To make clear the operation of the MOS device in saturation, the drainbulk junction and the inversion layer can be modeled by the series connection of a reversebiased diode indicating the drainbulk junction and a resistor representing the inversion layer resistance, as illustrated in Figure 2.3. For a given constant fD , )D HKUq fD e is constant and thus the drain current is fixed. In practice, by increasing the drainsource voltage, the voltage of
VGS=cte
VDS
+
D
+ S
G
VDSVDS,sat
D
+
VDS n+ FOX
FOX n+
Rch
VDS,sat

L p_substrate
Leff
∆L
Figure 2.3 MOS operation in a saturation region.
ID
S
2.2 Principles of MOS Transistor Functioning
19
)D )D HKUq across the drain to bulk junction increases, which results in extending the depletion area toward the source region. This causes the effective length of the inversion layer to decrease, and as a result, the inversion layer resistance slightly reduces. This effect leads to gradually increase the drain current, which is known as channel length modulation. This phenomenon shows itself as a small positive slope on the MOS output characteristic, as depicted in Figure 2.4. The drain current equation including the channel length modulation effect is a quadratic equation in which channel length is replaced by an effective length as
where pI junction [7]
p
W)
hY
3p
tJw
"V Z
fD
i
rss
e
(2.3)
)D HKUq
(2.4)
3p with 3p as the depletion region width of the onesided drain uv
vxy
)D
The slope of the curve shown in Figure 2.4 in saturation is denoted by X#K and can be calculated by taking the derivation of (2.3) in terms of implicit variable )D X#K
z{:
z4:k
z{: zZrss
zZrss z4:k
(2.5)
Using (2.3) and (2.4) and after some simple manipulations on (2.5), we have X#K W) where the parameter  defined as ID
VGS=cte
slope=gds
0
VDS,sat
Figure 2.4 MOS characteristic in saturation with channel length modulation effect.
VDS
20
where }#K
CMOS Technology and Physics
 }#K €~ pI t)D
)D HKUq •
(2.6)
F
(2.7)
• mK ‚ƒKM„ . Supposing 3p … p, (2.6) can be approximated as †
‡+v
Zt4:k /4:k Hvˆ‰
‡+v Z
G
The parameter X#K is the dynamic conductance between drain and source terminals of an MOS device and plays an important role in all MOS amplifiers. In fact, for a given MOS transconductance, the maximum achievable voltage gain is determined by this parameter. In a CMOS current source, high output resistance is achievable if the exploited MOS devices have minimum possible . For a particular drain current, a practical way to minimize  is to use the maximum possible channel length for MOS devices and also to increase the drainsource biasing voltage based on (2.7). It is interesting that PMOS transistors at the same channel length and drain biasing conditions have usually less X#K in comparison to their NMOS counterparts. This is because PMOS devices are fabricated inside the nwell and doping concentration of the nwell is usually greater than the impurity density in the p_substrate of NMOS devices. Consequently at the same condition in terms of channel length and biasing condition, }#K is smaller for the PMOS device. As an example, in a 0.25\Š CMOS technology the impurity concentration in the Œ p_substrate is ƒKM„ ?) Unity gain bandwidth: M ÷ = _ `a Phase margin: N& ÷ < › Slew rate: O' ÷ C [ \] Load capacitance: Z = µ.
The design procedure begins by determining the required tail current from the given value for the slew rate. In a foldedcascode structure, the slew rate is calculated from O' W Z . As a result, we should take W ÷ = \¶ that gives W) W) B= \¶. From the given bandwidth the minimum required transconductance of the input devices is obtained from LM X0 Z , which for LM ‹ = _ `a gives X0 < Š¶ [. The schematic of the op amp including bias circuitry is depicted in Figure 4.26. Here we have used PMOS devices as the input transistors of the differential pair. In an nwell CMOS technology, PMOS devices are implemented within the nwell and it is possible to tie the body and source terminals together for each PMOS device that has been placed in a separate nwell. This possibility can help us to avoid the body effect. Moreover, from the noise standpoints, as discussed previously, the flicker noise of PMOS transistors is less than that of NMOS at least by one order of magnitude which in turn helps to reduce the input refereed noise. Because the mobility of carriers in PMOS transistors is less than that of carriers in NMOS devices, to get the equal transconductance at the same bias current, we have to choose the PMOS aspect ratio larger to the extent that it compensates for VDD M16 M14
M3
M10
M11
I0 Vbp M9
M8
+ vi 
Ib
M15
M1
M2 vo CL
Vbn
M13
M7
M6
I4 M12
M18
I5
M4
Figure 4.26 Design example of a foldedcascode op amp with PMOS input devices.
M5
M17
4.3 FoldedCascode Op Amp
89
its smaller carrier mobility. This larger size, as an extra bonus, helps to reduce the input noise and offset voltage as well. Of course, large devices with rather small drain current may put PMOS devices in the subthreshold region. If that occurs, we no longer can reach the required transconductance by increasing the aspect ratio for a fixed drain current. As a result, the drain current of M1 and M2 is raised to ; \¶ to make sure the required transconductance is achievable. A lowlevel drain current makes it easier to get the required voltage gain by increasing the drainsource resistance of transistors but because sizing is rather large, devices work somewhere between saturation and moderate inversion, which causes deviation of the transconductance relationship from the ideal quadratic form. This issue may be considered by taking ¾ B With this value for ¾, from X0 H ¾ •hR "V o p H W ÷ < Š¶ [ we need to meet the inequality o p H =A . By taking o p H < and in order to avoid dropping the dc gain due to shortchannel effects in M1 and M2, we choose p H T \Š and thus o H T \Š. The current sources implemented by M4 and M5 should provide the drain current of M1 and M2 and also the current of cascode transistors M6 to M8. In a largesignal condition when the tail current is steered toward M1 or M2, the tail current plus the cascode bias current flow through M4 or M5 and therefore the current of M4 or M5 should be larger than the tail current in order to avoid turning off the cascode devices in this condition. Thus the amount of current in M4 and M5 is chosen somewhat more than the tail current. Here we take WÇ W W < \¶ The size of the rest of the main transistors including M4 to M11 are all calculated by allocating proper overdrive voltages to them. To get reasonable aspect ratio for devices and enough output voltage swing, an overdrive voltage of approximately Š[ is allocated to M6, M7, and about Š[ is chosen for M4 and M5 and M8 to M11. The reason that we choose a smaller overdrive voltage for NMOS devices is that when this architecture is used as a voltage follower, the lower limit of the output voltage swing is determined by the sum of the overdrive voltage of the output NMOS transistors (i.e., M5 and M7) that is !"H0%Y "# "#Œ , but the output swing from above, prior to reaching )) "# "# , is limited by M1 and M3 in the input stage. This means that allocating large sizes to M8 to M11 just degrades the stability by lowering the mirror pole location without influencing the effective output swing. M4 (M5) carries the largest current and thus its overdrive voltage is chosen about Š[ to get reasonable aspect ratio. Based on the given process data and with these overdrive voltages, the aspect ratio of o p is obtained for M6 to M11 < for M4 and M5. In order to have adequate large output and o p ÇH resistance to achieve the required dc voltage gain, the channel length of p = \Š is selected for M6 to M11. Therefore the aspect ratio of M6 to M11 will be obtained as < \Š = \Š. The loading effect of the drainsource resistance of M4 and M5 leads to decrease the voltage gain. Since these devices carry relatively large currents, it is necessary to minimize the parameter of
90
CMOS SingleEnded Output Op Amp
 }#K “p•)D )DHKUq – to gain the maximum resistance (Ò" W) )). With this aim in view, we increase the drainsource voltage, )DÇ )D „Y fDêHŒ , by raising „Y and select a channel length of pÇ p \Š, as well. The transistors (M15, M16) and (M17, M18) are used to provide the bias voltages „Y and „R , respectively. The bias current source W„ A \¶ with the aid of M12, M13, and M14 supplies the current of the tail transistor M3 and transistors M4 and M5. The results obtained from the circuit simulation are 4 BT C >?, LM ‹= _ `a, N& B;› , and a power dissipation of C Š . Output slew rate on the positive slope is O' ; = [ \] and on the negative slope is O'/ C= B [ \]. Although these results indicate the performance superiority of a twostage op amp over the foldedcascode architecture in terms of the voltage gain, bandwidth, and power consumption but the PSRR frequency response of a foldedcascode is much better than that of a normal twostage one. More importantly, the process of frequency compensation here is very simple. Actually the load capacitance itself plays the role of the compensation capacitance and there is no need for an extra component as a compensation capacitor.
4.4
Current Mirror Op Amp
A basic schematic of a current mirror op amp is shown in Figure 4.27. In the presence of the ac input signal the total current of M1 (M3) and M2 (M4) can be written as ®)
®)
®)Ž
®)Ç
W
W
¯5ÅH2
(4.74)
¯5ÅH2
(4.75)
These currents are amplified by two current mirror pairs of M4M6 and M7M8 and appear at the drain of M6 and M8: ®)ê ®)
}W }W
} }
¯5ÅH2
(4.76)
¯5ÅH2
(4.77)
The difference of the two currents above flows through the equivalent output resistance seen at the output node (i.e., '"Mq X"ê X" . The output voltage becomes " '"Mq ®)ê ®) and thus the lowfrequency smallsignal voltage gain is given by ‡¯5ÅH2 (4.78) ¯ í ¯
4.4 Current Mirror Op Amp
91
VDD
M5
M3
M4
M6
1:1
1:K
M1
M2
+ vi 
vo CL
2I0
M7
M8
1:K
Figure 4.27 Schematic of a CMOS current mirror op amp.
Since X"ê R W)ê and X" Y W) with W)ê W) }W and assuming the square law is held for the drain current of M1 and M2 such that we can write X0 H • hY "V o p H W) H , from (4.78) we have ²
t ÃÄ 6 — F ³ G ÅH2 “ðÄ ðQ –•{
(4.79)
It is interesting to note that the dc voltage gain is independent of the K factor in the current mirrors. Thus, for a certain bias current W , the only way to increase the voltage gain is to choose a longchannel length for M6 and M8 and increase the aspect ratio of the input devices, M1 and M2, provided that these devices remain in strong inversion. As discussed earlier, by increasing the transistor aspect ratio, at a certain drain current, an MOS device ultimately reaches a point at which the following inequality is held: {:ÅH2
² ³ ÅH2
F G
hY
"V
q¦
(4.80)
When the leftside term in (4.80) is adequately less than the rightside term, transistors work in the weak inversion area with a new relationship for the transconductance, X0 H W) H q¦ . In this condition the dc voltage gain is specified as (4.81) “ðÄ ðQ –±4‰¥
92
CMOS SingleEnded Output Op Amp
In the subthreshold region, corresponding to a weak inversion state, the voltage gain can be increased just by selecting a large channel length for the output devices M6 and M8. Frequency Response: The highest resistance is seen at the output node. Thus, we expect the dominant pole of the circuit to be formed by this resistance and the load capacitance at the output. The second pole is normally related to the gate of M3M5 or M4M6 with the value of X0Ç Ç where Ç is the total capacitance seen at the common gate of M4 and M6 and it is equal to Ç } ¯KÇ . Since X0Ç • hR "V o p Ç W and ¯KÇ C op Ç "V, the second pole can be written as LR
Ž
˜
Ñ Z2Ë
ÃQ {
ti 6 Ë
—
(4.82)
If the second pole places after the unity gain bandwidth frequency, the voltage gain frequency response of the current mirror op amp will be similar to what is plotted in Figure 4.22 for a foldedcascode op amp. Here we have LR LM with }X0 '"Mq and LR '"Mq Z , which gives LM }X0 Z . Although the current mirror gain of } has no effect on the dc voltage gain, but for the same amount of X0 and Z in current mirror and foldedcascode structures, the bandwidth is expanded by the factor of } in the current mirror op amp. In other words, at certain load capacitance in a current mirror op amp, it is possible to achieve the same bandwidth as the foldedcascode structure by choosing a lower input transconductance that alleviates the design of the input differential pair. The slew rate in a largesignal case, when the tail current entirely conducted by one of two branches of the differential pair, the amplified copy of the tail current (i.e., }W ) charges or discharges the load capacitor and thus the slew rate is given by O' }W Z . Here again, current gain factor of } helps to improve the slew rate. Now the question may be raised that based on what criterion is the value of } determined. The answer to this question is found in conjunction with the op amp frequency response stability. From (4.82) and based on the bandwidth relationship of LM }X0 Z , we notice that increasing } simultaneously raises the bandwidth and lowers the second pole, and thus lessens the phase margin according to N& ; óôc/ “LM LR –. For example, to have a phase margin of < › we need to have LR ÷ dCLM or equivalently the following inequality should be satisfied: ‡
¯5Ë
6¿vË
÷ dC
‡¯5Å 6³
By substituting transconductance relationships into (4.83), we have
(4.83)
4.4 Current Mirror Op Amp
}
}
² ³ Ë 6³ ² ŽÃÄF G 6¿vË ³ Å
Á
}
ÃQ F G
93
ã
(4.84)
The plot of Figure 4.28 illustrates the maximum allowable value of } that can meet our minimum acceptable phase margin in which ã denotes the fixed rightside term in (4.84). In practice, based on the typical values for the circuit parameters, the range of C } = is appropriate to achieve the required phase margin. The main drawback of the structure in Figure 4.27 is that it cannot provide enough dc voltage gain. This imperfection can be treated by employing cascode configuration, as shown in Figure 4.29. Similar to the simple structure, the dc voltage gain is obtained as ‡¯5ÅH2
f Q f Ä
(4.85)
where È"R X" X" X0 and È"Y X" X" Ç X0 . Assuming the same transconductance for the cascode devices, M10 and M12, and denoting it as X0$ with the square law condition being held, we have X0$
} thR
"V W
F G
²
²
i
Z ŽHÇ
(4.86)
Now by substituting the output conductance of each device with X" using (4.86), we can rewrite (4.85) as Ç6 —tÃÄÃQ F ³ G F ³ G ÅH2 ÑHË 2 { “ð2 Ä ðQ –
W) and (4.87)
Here again the current gain factor } has no effect on the dc voltage gain and the possible measures that can be taken to increase the voltage gain are to use long f(k) K/(K+1) T0
Kmax
K
Figure 4.28 Plot to determine the upper limit of the current mirror gain factor.
94
CMOS SingleEnded Output Op Amp VDD
M7
M5
M6
M8
1:1
1:K
Vbp M9
M3
M10
M4
M1
M2
+ vi 
vo CL
I0
Vbn M11
M12 1:K
M13
M14
Figure 4.29 Current mirror op amp with a cascode structure.
channel length for output devices including M8, M10, M12, and M14, to increase the aspect ratio of M1 to M4, of course as long as they operate in the saturation region, and finally, if possible, to lower the bias current W , although the value of W is usually set in advance based on the given specification for the op amp slew rate. Design Example Now we proceed to design our op amp with the previously given parameters and in the same technology, but this time we employ the current mirror structure. In both previous design examples, in order to provide the required transconductance of the input devices we had to take a larger tail current that led to obtaining higher slew rate. In general, this can be regarded as a benefit from a design point of view. Here we choose a slew rate of T [ \] from scratch. To achieve the required BTdB voltage gain, we use the cascode structure shown in Figure 4.29. First, by choosing } T from the given slew rate, we obtain the tail transistor current. The relationship of O' }W = µ and O' T [ \], gives Z , for Z W = \¶. Then, based on the required bandwidth we calculate the input device’s transconductance from X0 H LM Z } that gives X0 H C;C \¶ [. By being specified X0 H and the bias current, we can calculate the input device aspect ratios. Using a quadratic relationship for the drain current, we obtain the aspect
4.4 Current Mirror Op Amp
95
ratio from X0 H ÷ ¾•hY "V o p H W with ¾ A, we should have o p H ÷ T. We choose o p H C in order to ensure that our required transconductance is reached. At this stage, we can allocate the minimum feature size of the technology to channel length but taking p H = \Š leads to larger gate area, which helps to reduce the flicker noise and inputreferred offset voltage. By this channel length the input transistors widths become o H = \Š. Sizing of the output transistors M8, M10, M12, and M14 are calculated based on the desirable output voltage swing. We have !"H0UV )) "#R with "#R as the overdrive voltage of the PMOS devices. For !"H0UV ÷ [, we need to have "#R [. Since the drain current density W) o p is the same for all MOS devices from M3 to M14, the overdrive voltages of all PMOS devices are equal to each other. The same statement is true for all NMOS devices. Thus we can also apply the condition of "#R [ for M3 to M6. The inequality "#Ž [ gives o p Ž ÷ =, which can also be used for M4, M5, M6, M7, and M8. By setting o p Ž/ C , the overdrive voltage of about A[ is obtained. An overdrive voltage of =[ for M11 and M12 leads to aspect ratio of o p H Ž . To somewhat minimize parameters Y and R and in order to take into account the matching issues in the layout of current mirror circuitries, here we set the length of all PMOS transistors on = \Š. As discussed in Chapter 2, the parameter R in PMOS devices, at the same bias and channel length condition, is slightly smaller than Y . On the other hand, the maximum voltage gain is achievable if the equivalent output resistances of the PMOS and NMOS devices are equal to each other. By allocating larger channel length to NMOS transistors, it is possible to have Y R . For the same drain current, this results in having equal output resistance in PMOS and NMOS devices and thus maximum voltage gain. In this design, = \Š is chosen for the channel length of all NMOS devices. With the given length for PMOS and NMOS transistors, their widths become = \Š for all transistors from M3 to M8 and M11 and M13. The sizing of M8, M10, M12, and M14 are larger by the factor of } in two upper and lower current mirror circuits. After adding proper bias circuitries, simulation results show the designed op amp has more than A >? voltage gain with the phase margin of ? Unity gain bandwidth: M = ; _ `a Phase margin: N& < T› Slew rate: O' T ; [ \] H O' / C< A [ \] Power dissipation: N# =C Š Power Supply Rejection Ratio: • NO'' ;B T >?H /Ž#• T= œ`a • NO'' / A= >?H /Ž#• TB œ`a RailtoRail Input Op Amp
In a voltage follower implemented by a singleended output op amp, three voltages at the inverting and noninverting inputs and at the output are all approximately equal to each other. This means that the input commonmode voltage that is defined as the average of the voltages at two inputs is the same as the input or output signals. Hence if we intend to have a singleended output op amp where the output voltage can swing close to two supply rails, the input commonmode range (ICMR) also needs to be able to have the same swing without any remarkable change in the main op amp specifications such as voltage gain, bandwidth, and phase margin. Thus far, in all op amp architectures that we have studied, the input stage consists of an NMOS or PMOS differential pair in which the input commonmode voltage is limited at a level quite below the positive supply or above the ground level depending on the type of the differential pair used. In an NMOS differential
4.5 RailtoRail Input Op Amp
97
pair, the input commonmode voltage can change close to [ÍÍ but it is limited to %$H0%Y fDY "#H{ from below, where fDY is the gatesource voltage of the NMOS input devices. In fact, when %$ goes below %$H0%Y the tail current source transistor enters the triode region, and in consequence, the tail current starts dropping. As a result, the input stage transconductance begins to fall. The opposite occurs in the case of a PMOS differential pair where the input commonmode voltage can go down around the ground level, but from above it is restricted to %$H0UV )) DfR "#H{ , with DfR as the dc gatesource voltage of the PMOS input devices. A pictorial representation of the matter is illustrated for two different types of differential pairs in Figure 4.31. Since the input transconductance has a direct impact on voltage gain and bandwidth, we need to keep the input transconductance constant in spite of variation in %$ . From Figure 4.31, the first idea that may come to mind is to use the parallel combination of two PMOS and NMOS differential pairs. Figure 3.32 represents the schematic of the related circuit and its corresponding transconductances. As it is obvious, the downside of the circuit is that its total VDD
gmn
ICMR + vi
M1
M2

VGSn
I0
Vod,I0 0
VTn
VGSn+Vod,I0
VDD
VDDVSGpVod,I0
VDD
Vic
VDD I0
Vod,I0
gmp
VSGp + vi
M1
M2
ICMR 0
Vic
VDDVTp
Figure 4.31 ICMR of NMOS and PMOS differential pairs with their corresponding transconductance variation versus .
98
CMOS SingleEnded Output Op Amp
Figure 4.32 Schematic of combined NMOS and PMOS differential pairs with their corresponding transconductance variation versus Vic.
transconductance has a bump in the middle zone of %$ where both pairs are on and as a result, the total transconductance is nearly twofold if it is supposed that two differential pairs have the same transconductance in the midrange of %$ . This variation in transconductance shows its effect on voltage gain, bandwidth, and phase margin, and it is quite possible that causes instability. We need to find a way to keep the total transconductance constant when input commonmode voltage changes between 0 and [ÍÍ . If the condition of square law is held for all MOS devices, the transconductance of two NMOS and PMOS differential pairs are X0Y •hY "V o p Y W•w and X0R •hR "V o p R W•× , respectively, where o p Y and o p R are the associated aspect ratios of two pairs. Assuming hY "V o p Y hR "V o p R ° , we have X0q •°“•W•w •W•× – In order to have a constant total transconductance, the term inside the parenthesis in X0q should be kept constant. A translinear loop can provide this condition. A translinear loop is a closedloop consisting of translinear components. Any electronic device whose transconductance is a linear function of its current or voltage is known as a translinear element. For example, a bipolar transistor with an exponential relationship is a current translinear device because its transconductance is a linear function of the collector current (X0 W6 q¦ ). An MOS device with quadratic relationship for the drain current acts as a voltage translinear device in which the transconductance is a linear function of the gatesource voltage X0 ° fD e . Now consider the given circuit in Figure 4.33. The gatesource voltages of M1 to M4 form a translinear loop. Summation of voltages around the loop results in fD
fD
fDŽ
fDÇ
T AA
4.5 RailtoRail Input Op Amp
99
Figure 4.33 MOS translinear loop.
Since for each device we have fD%
e%
ÁÃÄ 6
®
{:
² —F ³ G
H HCHT
(4.89)
Assuming all transistors are identical, by substituting the corresponding drain current for each device from (4.88) and (4.89), we have •W•w •W•× = •W . A practical circuit that works based on this concept is shown in Figure 4.34 [5]. (Ma, Mb) and (Mc, Md) are two parallel PMOS and NMOS differential pairs with MP and MN as their tail transistors whose currents are controlled by the rest of the circuit. The currents WŽ and WÇ are adequately less than currents W, W•w , and W•× . As well, all PMOS devices including M1, M2, M3, M4, M5, and MP are identical. Transistors MP, M3, M4, and M5 form a translinear loop with the following relationship among their gatesource voltages: DfÚ
DfŽ
DfÇ
Df
T;
{¨Û {Ñ ² Q6 —F ³ G Å
(4.91)
In the circuit of Figure 4.34 two identical devices, M2 and M3 have the same drain current and thus we have DfŽ Df Df . On the other side, for M1 we can write DfŽ
Df
ÌeR Ì
ÁÃ
By substituting each gatesource voltage into (4.90) by its value given in (4.89)
100
CMOS SingleEnded Output Op Amp VDD M2
M1
M4
I3
MP IBP
M5 + vi 
M3 + vi
Ma
Mb

I
M6
IBN
Vbias
I4
+ vi 
M7
Md
Mc
IBN MN
M8
Figure 4.34 A constantgm circuit that works based on the translinear loop concept.
and (4.91), and taking into account the associated drain current of each device, after simplification, we obtain •W•×
•W•w
WŽ
•W
WÇ
•WÇ
(4.92)
Since WŽ … W•w and WÇ … W, we can approximate (4.92) as •W•× •W•w dW. The derived relationship can be qualitatively justified as follows. When the input commonmode voltage is too small, the differential pair M6, M7 is almost off and thus M1 carries the small current of WŽ . The current mirror M1M2 makes a copy of WŽ into M2 and M3. The gatesource voltage of M3 is small because of its low drain current. As a consequence, since the right side of (4.90) is fixed, and a decrease in DfŽ should be compensated for by increasing DfÚ , which in turn, raises the tail current W•× . When the input commonmode voltage is close to [ÍÍ , the differential pair (Ma, Mb) is almost off but (M6, M7) is on and the bias current W•w flows through M1M2 and then flows into M3 and establishes its gatesource voltage DfŽ . From (4.90), we see that a noticeable voltage places across the gatesource of MP, but because its drain current is too small, MP goes to the triode region with the following relationship: W)Ú
hR
i "V F Z G
×
ç“ fÚ
ÌeR Ì–D)Ú
2 4k:
Ú
è
(4.93)
From (4.93), with W)Ú , we have D)Ú and DfÚ ÌeR Ì D)Ú ÌeR Ì. This analysis proves that in spite of the drain current of MP being too small, this device does not operate in the subthreshold region, a working area in which
4.5 RailtoRail Input Op Amp
101
Figure 4.35 Another example of a circuit that works based on the translinear loop concept.
DfÚ ÌeR Ì and the drain current equation is completely different. Now by substituting DfÚ ÌeR Ì in (4.90) and repeating the same procedure that was done to reach (4.92), we will get •W•w
WŽ
•W
WÇ
•WÇ
(4.94)
The existence of the current source WŽ in the circuit is important. In fact, for a toosmall input commonmode voltage the pair of (M6, M7) is approximately off and WŽ is the only remarkable current that causes M1 to remain in the saturation region. Otherwise for very low level drain current of M1, this device and also M2 and M3 would operate in the subthreshold region. In this situation, due to the exponential relationship for the M3 drain current, the loop consisting of MP, M3, M4, and M5 no longer acts as a conventional translinear loop. Figure 4.35 indicates another circuit that works based on the translinear loop concept to realize a constantgm input stage [6]. Here the translinear loop consists of transistors M1, M2, M3, and M4. A detailed analysis of the circuit is left as an exercise to the interested reader. Another method to attain a constantgm input stage is to utilize the quadratic relationship of the MOS drain current. The transconductance of an MOS device with such a relationship changes as a square root function of the drain current. If it is supposed that the transconductances of two differential pairs are the same at the midrange of the input common mode voltage, the total input transconductance will be two times the transconductance of each single pair. Now in two low and high extremes of the input commonmode voltage variations between 0 and )) , one of two differential pair turns off and it is just enough to increase the tail current of the conducting differential pair fourfold. This causes a single turnedon differential pair that provides the same total transconductance that would be produced in the midrange of the input commonmode voltage by both pairs. Different constantgm
102
CMOS SingleEnded Output Op Amp
Figure 4.36 Newly introduced constantgm input stage.
circuits have been introduced in the literature that all work based on the abovementioned principle [78]. The circuit shown in Figure 4.36 is another example that uses this method to provide a constant transconductance against the variation of the input commonmode voltage. In this circuit, when the input commonmode voltage is close to zero, two NMOS differential pairs (M1, M2) and (M12, M13) turn off, and in consequence, M5, M10, and M11 also turn off. On the other hand, both PMOS differential pairs (M3, M4) and (M6, M7) turn on, and as a result, current W•× flows through (M6, M7), which turns M8 and M9 on. But M5 is off and thus M9 goes to the triode with nearly zero drain current and voltage. This ensures that the current mirror M15M16 is off. The current mirror M8M14 transfers the current W•× to the second current mirror created by M17M18 that adds three times of W•× to the tail of the PMOS input differential pair. At the other extreme of the input commonmode voltage close to the positive supply, two PMOS differential pairs (M1, M2) and (M6, M7) are off. This time M8, M9, and M14 are off and M10 goes to the triode region with nearly zero drainsource voltage, which makes current mirror M17M18 off. In this situation, the current mirror M11M15 transfers W•w to the current mirror of M15M16 with the gain of three that adds CW•w to the tail current of the NMOS differential pair (M3, M4). When input commonmode voltage varies somewhere at the middle of zero and [ÍÍ , all differential pairs of both types conduct. Assuming W•× W•w , we can see the current flowing through two transistors pairs of (M5, M9) and (M10, M14) are approximately the same, and therefore both current mirrors M15M16 and M17M18 are nearly off and cannot add noticeable current to the tail current of the input differential pairs. In this condition, the aggregated transconductance of the NMOS and PMOS differential pair contribute in total transconductance. In lowpower designs, MOS devices usually work in the subthreshold region where transconductance is directly
4.5 RailtoRail Input Op Amp
103
proportional to the drain current (X0HKM„ W) q¦ ). In this case, obtaining a constant transconductance is feasible by keeping the sum of the drain bias current of the two differential pairs constant [9]. The circuit realization of this condition is normally more convenient in comparison to the situation where MOS devices work in strong inversion with the square law relationship. Current Combiner Circuit: We now proceed to study the circuit used for combining the drain currents of the input stage to reach a singleended output voltage. Figure 4.37 represents one circuit that can be used for this purpose where for the sake of clarity, the circuit used for keeping the input transconductance constant has not been shown. Summing currents at the drain of M5 and M6 and at the source of M9 and M10, we obtain the following equations: ®
®)Ž
®
®)Ç
®
®)
®
®)
®
(4.95)
®Ž
(4.96)
W
(4.97)
W
(4.98)
VDD
IS
i
i
M5
M6
iD3 iD4 M3 vi1
M4 M1
M2
vi2 VBP M7
M8 i3 Vo
IS iD1
i1
iD2
i2
M9 VBN
M10
I0
Figure 4.37 Schematic of a current combiner.
I0
104
CMOS SingleEnded Output Op Amp
From the above equations, we can get the output current as ®"Mq
®Ž
®
®)
®)
®)Ž
®)Ç
(4.99)
where ®) ®) is the differential output current of the PMOS differential pair that is equal to X0R !% !% . Similarly, we have ®)Ž ®)Ç X0Y !% !% for the NMOS pair. The ac output current ®"Mq flows through the equivalent resistance seen at the common drain of M8 and M10 (i.e., '"Mq ). By denoting !% !% !% H the output voltage becomes !" “X0Y X0R –'"Mq !% with '"Mq '"w Ó '"× in which '"× X0 Ò" Ò"ê Ó Ò"Ç and '"w X0 Ò" Ò" Ó Ò" . Ò" represents the output resistance of the current source W . It should be pointed out that the bias voltages •w and •× need to be carefully chosen such that all input transistors, M1 to M4, always remain in saturation at the extremes of the input commonmode voltage, %$ . For instance when %$ varies around the zero, the pair of (M1, M2) is the only conducting pair, and thus the maximum drain voltage of M1 and M2 should not be beyond one threshold voltage of ÌeR Ì in order to keep these devices in saturation. This means that we should have •w fD ÌeR Ì. Likewise, at the other extreme (i.e., for %$ )) ), we need to meet the condition of •× )) DfŒ eYŽ to keep M3 and M4 in saturation. Another important point with regard to the dc condition is related to the value of W . As discussed earlier, for %$ , the X0 control circuit increases the tail current of the PMOS pair from WK to TWK to have a constant X0 in the input stage. In this case, we have W) W) WK and W W WK where W is the dc current of the cascode transistors (i.e., M7 to M10). In order to keep turning on these devices we need to have W or equivalently W WK . In the midrange, when we have %$ )) , W) W) WK and W W WK . Now we have to meet W WK and finally at the extreme of %$ )) , W)Ž W)Ç WK and W W. One measure that can be taken to make sure that the cascode devices always remain on for %$ variation between to )) , is that we use a fixed value of 2WK for W . In this condition, W changes from zero to WK when %$ changes from to )) This causes a significant variation of the smallsignal parameters of the cascode devices that can affect the dc voltage gain and also changes the location of the second pole, in turn, impacts on the amplifier stability. To achieve a constant W in spite of the variation of %$ , first we set W WK . Then for %$ , we add a current of WK to W by paralleling a WK current source to W . In the midrange, for %$ )) , we need to add current of WK to W WK and finally, when %$ )) , there is no need to add any current to our initial current W WK . All these actions can be done by using the same control circuit that is used to change the tail currents of two differential pairs in the input stage.
4.6 Conclusion
4.6
105
Conclusion
The subject of this chapter was about the design of singleended output op amps. Some most popular architectures of this category usually employed in an analog system were introduced. Each structure has its own advantages and drawbacks. Choosing a particular type of op amp totally depends on the application and required specifications for that particular application. For example, when design is to be done in a deep submicron technology, achieving a large voltage gain is not a simple task. In this case the twostage op amp perhaps is the first candidate. But from a frequency stability point of view, a designer may get into trouble when he/she uses such architecture with a large load capacitance. The behavior of a current mirror op amp is welldefined and its design procedure is straightforward though it cannot provide enough voltage gain. Of course this shortcoming of current mirror structure is compensable to some extent by using cascode configuration. Among different studied architectures the foldedcascode structure can meet most expected specifications while also being appropriate for lowvoltage applications. This chapter also dealt with the railtorail input op amps and introduced several methods to achieve this goal. In the method presented the input stage is designed such that the total transconductance of the input devices of the op amp have minimum variation when the input commonmode voltage changes between two supply rails.
References [1]
Gray, P. R., Hurst, P. J., Lewis, S. H., and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, Fourth Edition, John Wiley & Sons, Inc., 2001.
[2]
Liu, W., MOSFET Models for SPICE Simulation Including BSIM3v3 and BSIM4, John Wiley & Sons, Inc., 2001.
[3]
Tsividis, Y., Operation and Modeling of the MOS Transistor, Second Ed, Boston: McGrawHill, 1999.
[4]
Allen, P. E., Holberg, D. R., CMOS Analog Circuit Design, Second Ed, Oxford University Press, 2002.
[5]
Nagaraj, K. “Constant Transconductance CMOS Amplifier Input Stage with RailtoRail Common Mode Voltage Range,” IEEE Trans. Circuits Syst. II, Vol. 47, No. 12, 2000, pp. 1560– 1564.
[6]
Botma, J. H., et al., “A LowVoltage CMOS Op Amp with a RailtoRail ConstantGm Input Stage and a ClassAB RailtoRail Output Stage,” Proc. of the IEEE Int. Symp. on Circuits and Systems, 1993, pp. 13141317.
[7]
Hogervorst, R., et al., “A Compact PowerEfficient 3 V CMOS RailtoRail Input/Output
106
CMOS SingleEnded Output Op Amp Operational Amplifier for VLSI Cell Libraries,” IEEE J. SolidState Circuits, Vol. 29, No. 12, 1994, pp. 15051513.
[8]
Moldovan, L., and Li, H. H., “A RailtoRail, Constant Gain, Buffered Op Amp for Real Time Video Applications,” IEEE J. SolidState Circuits, Vol. 32, No. 2, 1997, pp. 169176.
[9]
Peeters, E., Steyaert, M., Sansen, W., “A Fully Differential 1.5V LowPower CMOS Operational Amplifier with a RailtoRail CurrentRegulated Constantgm Input Stage,” Proceedings of the IEEE Custom Integrated Circuits Conference, 58 May 1997, pp. 7578.
Chapter 5 CMOS Fully Differential Op Amps The name of the singleended output op amp evidently states its unique property of having a single output voltage or current. This is against another important category of operational amplifiers that states that both input and output signals appear as differential voltage or current. As the design criteria in the implementation of an op amp to be used within an analogintegrated circuit is significantly different from those of traditional standalone op amps, critical specifications such as the amount of PSRR and CMRR need to be considered in such applications. For example, in an integrated mixedmode circuit such as analog filters or data converters, op amps and other digital sections coexist on a common chip [1]. This causes any noise from digital parts to go through the common substrate into the analog blocks. This issue highlights the unquestionable importance of high CMRR and PSRR which have critical roles in alleviating these issues. Using differential output signals instead of a single counterpart, we can significantly keep such circuits immune against commonmode noises or interferences. In this chapter, first we outline the remarkable advantages of fully differential op amps (FD op amps) compared to their singleended alternative. Next, we deal with the commonmode feedback circuit as an indispensable building block in FD op amps and introduce some subtle issues with regard to this block. At the end, we briefly study different structures in this category.
5.1
Advantages of Fully Differential Op Amps
In this section, some predominant benefits of differential output amplifiers are briefly introduced to demonstrate the reasons behind the widespread application of this amplifier in analog integrated circuits. High Immunity against CommonMode Noises and Interference Signals: Since the differential output voltage is the amplification of the difference of two input voltages, any unwanted interference signal that appears as a commonmode signal
107
108
CMOS Fully Differential Op Amps
on both inputs would disappear at the output in an ideal case [2]. This issue is critical particularly in an analog mixedmode circuit where it is quite possible that some unwanted digital signals such as clock voltage reaches the op amp inputs through different ways like capacitive coupling, shared substrate, or common power supply rail. Increased Output Swing: In a differential output op amp, since two outputs change in the opposite directions in reference to the ground node of the circuit, thus the difference of them will be twofold in comparison to that of its singleended output counterpart. Improved output swing leads to increase of the dynamic range, a critical point in lowvoltage designs. Moreover, this feature helps to improve the signaltonoise ratio of the circuit. Elimination of Even Harmonics: In a largesignal condition, the general relationship between the difference of inputs and outputs can be represented as !"# !%# . Supposing the amplifier has a full symmetric structure, by interchanging two inputs, we will have the same output with opposite polarity. This means that the inputoutput relationship is an odd function of the input difference voltage !%# and thus only odd terms will appear in the Taylor series expansion of !"# in terms of !%# !"#
ö !%#
Ž öŽ !%#
ö !%#
(5.1)
For a sinusoidal input voltage, substituting !%# 0 ù ½L n into (5.1) and using trigonometric formulas to simplify the relationship, we obtain !"#
ù ½L n
Ž
ù ½CL n
ù ½=L n
(5.2)
This reveals that in an ideal FD circuit only odd harmonics are generated due to the circuit nonlinearity. The property of an odd characteristic also shows that to invert the polarity of a differential signal there is no need for an extra amplifier and it is enough to interchange the order of two differential input signals. Omission of the Systematic Offset Voltage: In a differential output amplifier, a commonmode feedback circuit should be used to fix the output voltage to a desirable level. This action eliminates any concern about dc output level deviation. Removal of the Mirror Pole: Since no current mirror active load is employed in the structure of a differential output amplifier, we have no mirror pole similar to what happens in a singleended output op amp. In contrast to all the above mentioned advantages of differential output op amps, we can enumerate two main downsides. First, when an FD op amp is used as an amplifier in a negativefeedback loop, the required number of elements in
5.2 CommonMode Feedback Concept
109
the feedback network becomes twofold. For instance, in a switchedcapacitor amplifier implemented by such an op amp we need four capacitors instead of two. This can occupy a considerable area of the chip in an integrated analog circuit. The second challenge with an FD op amp is its mandatory requirement of an extra circuit called commonmode feedback circuitry (CMFB). The function of the CMFB circuit is to keep the dc output voltage on an appropriate level in order for output devices to operate in the saturation region.
5.2
CommonMode Feedback Concept
When a singleended output op amp is used within a negativefeedback loop, the feedback helps to stabilize the commonmode (CM) output level. Consider the circuit shown in Figure 5.1 and let the output voltage be changed by 3" . This variation through the feedback path appears at the inverting input as 3 / Ô' ' ' Õ3" , is multiplied by the op amp voltage gain, and returns to the / output as 3"¼ ' ' Õ3" . Since # , it is obvious # 3# Ô' that any change in the dc output voltage is compensated by a strong negativefeedback mechanism. Now consider the same condition for an FD amplifier shown in Figure 5.2. Generally, the variation of the CM output voltage (3"$ !"$ ) can be written as !"$ #$ !%# $$ !%$ with #$ and $$ as the differential to CM and CM voltage gains, respectively, and 3%$ !%$ . For the case of !%# as illustrated in Figure 5.2, when the output CM voltage changes by 3"$ , the corresponding variation in the input CM voltage becomes 3%$ Ô' ' ' Õ3" . This time the voltage 3%$ is multiplied by $$ and causes the output voltage change by 3"$¼ ' ' Õ3"$ . Since $$ $$ Ô' is a small quantity, the negativefeedback loop cannot compensate for the changes in "$ . Hence it is completely possible that the output CM voltage changes uncontrollably toward one of two supply rails. This proves that unlike a single
R2
Vref
R1
− Ad
+ Figure 5.1 Singleended output op amp within a negativefeedback loop.
Vo
110
CMOS Fully Differential Op Amps R2
R1
Vref +
∆Voc
+
+
Ad
Vod

 ∆V oc
R1
R2
Figure 5.2 Differential output op amp within a negativefeedback loop.
ended op amp, in a differential op amp we need an additional circuit to maintain the output dc voltage on a certain level that ensures output devices operate in the saturation region [3]. Figure 5.3 shows the CMFB block in association with an FD op amp. The signal !K at the CMFB output exhibits the control signal used to adjust the op amp output dc voltage to a desirable level. The variation of the differential and CM voltages of the op amp in the presence of the CMFB block can be represented by !"#
## !%#
!"$
#$ !%#
$# !%$
$$ !%$
K# !K
(5.3)
K$ !K
(5.4)
K# and K$ show the amount of contribution of the control signal !K in the differential and CM output voltages, respectively. On the other side, the voltage !K itself depends on these voltages through the CMFB circuit according to the following relationship:
!K
Vic +
#K !"#
+
+
vid Vic 


$K !"$
(5.5)
+ vod 
Voc
vs Commonmode feedback
Figure 5.3 Op amp with a CMFB network.
Voc
5.3 CommonMode Feedback Circuits
111
where #K is the voltage gain of the CMFB for the differential output voltage and $K is the corresponding gain for the output CM voltage. The role of the CMFB block is to detect the output CM voltage variation and produce the control signal of !K to adjust the output CM level. Hence we expect to have #K … $K or !K , from (5.4) the output CM $K !"$ . In the quiescent condition when !%# variation is given by !"$
$$ !%$
K$ !K
=