Computer-Aided Developments: Electronics and Communication. Proceedings of the first annual Conference on Computer-Aided Developments in Electronics and Communication (CADEC-2019), Vellore Institute of Technology, Amaravati, India, 2-3 March 2019 9780429340710, 0429340710, 9781000751598, 1000751597, 9781000751673, 1000751678, 9781000751758, 1000751759

The volume comprises of papers presented at the first CADEC-2019 conference held at Vellore Institute of Technology-Andh

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Computer-Aided Developments: Electronics and Communication. Proceedings of the first annual Conference on Computer-Aided Developments in Electronics and Communication (CADEC-2019), Vellore Institute of Technology, Amaravati, India, 2-3 March 2019
 9780429340710, 0429340710, 9781000751598, 1000751597, 9781000751673, 1000751678, 9781000751758, 1000751759

Table of contents :
Cover
Title Page
Copyright Page
Table of Contents
Foreword
Committees
About the editors
A distinct carry celect adder design approach for area and delay reduction using modified full adder
Performance analysis of different multiplier architectures using 1-bit full adder structures
QCA based binary adder-subtractor
Low power design of memoryless adaptive filter using distributed arithmetic unit
Design of FINFET based DRAM cell for low power applications
VLSI Architecture of DNN neuron for face recognition
Reconfigurable optimal hybrid vision enhancement system for night surveillance robot using hybrid genetic-PSO algorithm
Eigenface recognition using PCA
Sound classification and localization in service robots with attention mechanisms
Probabilistic nonlinear dimensionality reduction through gaussian process latent variable models: An overview
Comparative study and an improved algorithm for iris and eye corner detection in real time application
Review on fast motion estimation algorithms for HEVC in video communication
Synchronous multi-port SRAM architectures: A review
A Closed loop robust controller for SSHI based piezoelectric energy harvester
Internet of things for wildfire disasters
A fuzzy algorithm for text classification in data science
Face recognition based on local binary pattern-deep belief networks
Comprehensive analysis of face recognition techniques: A survey
Qualitative analysis of emotion recognition systems using deep neural networks
Deep learning based anomaly detection systems- A review
Frequency domain speech bandwidth extension
Design of fractal spiral inductor for wireless applications
Review on DSP based dynamic gene encoding schemes for the detection of protein coding region
Damaged video reconstruction using inpainting
Investigation in reduction of radar cross section due to plasma release from target in active stealth technology
Performance comparison of microstrip antenna and dielectric resonator antenna (DRA) at RFID application
A study of poultry realtime monitoring and automation techniques
Impact of MgO interfacial layer of gate dielectric engineered monolayer MoS2 FET
Achieving ISO 26262 & IEC 61508 objectives with a common development process
Comparative analysis of impedance and capacitance based bio-sensors for cellular pathology
Simulation of GaN MOS-HEMT based bio-sensor for breast cancer detection
Development of charge and discharge controller for solar lighting system
ASIC Design of ALU with different multipliers
Gate diffusion input (Gdi) technique based CAM cell design for low power and high performance
Author index
Subject index

Citation preview

PROCEEDINGS OF THE FIRST ANNUAL CONFERENCE ON COMPUTER-AIDED DEVELOPMENTS IN ELECTRONICS AND COMMUNICATION (CADEC-2019), VELLORE INSTITUTE OF TECHNOLOGY, AMARAVATI, INDIA, 2-3 MARCH 2019

Computer-Aided Developments: Electronics and Communication Edited by Arun Kumar Sinha Vellore Institute of Technology - Andhra Pradesh

John Pradeep Darsy Vellore Institute of Technology - Andhra Pradesh

MATLAB® is a trademark of The MathWorks, Inc. and is used with permission. The MathWorks does not warrant the accuracy of the text or exercises in this book. This book’s use or discussion of MATLAB® software or related products does not constitute endorsement or sponsorship by The MathWorks of a particular pedagogical approach or particular use of the MATLAB® software. CRC Press is an imprint of Taylor & Francis Group, an Informa business © 2019 by Taylor & Francis Group, London, UK Typeset by Ozone Publishing Services., Puducherry, India Although all care is taken to ensure integrity and the quality of this publication and the information herein, no responsibility is assumed by the publishers nor the author for any damage to the property or persons as a result of operation or use of this publication and/or the information contained herein. Published by: CRC Press Taylor & Francis Group 6000 Broken Sound Parkway NW, Suite 300 Boca Raton, FL 33487-2742 ISBN: 978-0-429-34071-0 (eBook)

Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

Table of contents

Foreword Committees About the editors

ix xi xiii

A distinct carry celect adder design approach for area and delay reduction using modified full adder K. Bala Sindhuri, G. S. Chandra Teja, K. Madhusudhan and N. Udaya Kumar Performance analysis of different multiplier architectures using 1-bit full adder structures N. Udaya Kumar, G. S. Chandra Teja, K. Rajesh, V. Soma Sandeep and K. Bala Sindhuri

1

9

QCA based binary adder-subtractor Akondi Narayana Kiran and Akhendra Kumar Padavala

19

Low power design of memoryless adaptive filter using distributed arithmetic unit Debanjan Kundu and Sriadibhatla Sridevi

27

Design of FINFET based DRAM cell for low power applications Grande Naga Jyothi, Gorantla Anusha, N. Dilip Kumar and Debanjan Kundu

35

VLSI Architecture of DNN neuron for face recognition K Rajesh Sai, Plabini Jibanjyoti Nayak and Yallamandaiah S

45

Reconfigurable optimal hybrid vision enhancement system for night surveillance robot using hybrid genetic-PSO algorithm L.M.I. Leo Joseph and B.Girirajan

51

Eigenface recognition using PCA K. Anitha, V. Susmitha and M. Srinivasa Rao

59

Sound classification and localization in service robots with attention mechanisms Matteo Bodini

69

Probabilistic nonlinear dimensionality reduction through gaussian process latent variable models: An overview Matteo Bodini

77

Comparative study and an improved algorithm for iris and eye corner detection in real time application Illavarason P, Arokia Renjith J and Mohan Kumar P

91

v

Review on fast motion estimation algorithms for HEVC in video communication K. Mohan Kumar, Anirudh P.K.V. and Yallamandaiah S

99

Synchronous multi-port SRAM architectures: A review G. Saket Kumar, M. Meghana, P. Sri Saranya, S. Yallamandaiah and D. John Pradeep

107

A Closed loop robust controller for SSHI based piezoelectric energy harvester Sweta Kumari, Subrat Kumar Swain, SitanshuSekhar Sahu, Aditya Kumar, Prashant Kumar and Bharat Gupta

113

Internet of things for wildfire disasters Gudikandhula Narasimha Rao, P. Jagadeeswara Rao, Rajesh Duvvuru, Kondapalli Beulah and Venkateswarlu Sunkari

121

A fuzzy algorithm for text classification in data science Kondapalli Beulah, Penmetsa Vamsi Krishna Raja and P. Krishna Subba Rao

133

Face recognition based on local binary pattern-deep belief networks K. Naga Prakash, K. Prasanthi Jasmine and K. Rasool Reddy

143

Comprehensive analysis of face recognition techniques: A survey Yallamandaiah S and Purnachand Nalluri

149

Qualitative analysis of emotion recognition systems using deep neural networks D. Usen and Purnachand. N

155

Deep learning based anomaly detection systems- A review VishnuPriya Thotakura and Purnachand Nalluri

165

Frequency domain speech bandwidth extension N. Prasad and P. Akhendra Kumar

177

Design of fractal spiral inductor for wireless applications Akhendra Kumar Padavala and Prasad Nijampatnam

185

Review on DSP based dynamic gene encoding schemes for the detection of protein coding region Raman Kumar M and Vaegae Naveen Kumar Damaged video reconstruction using inpainting Kamesh Sonti and K. Rasool Reddy

191 201

Investigation in reduction of radar cross section due to plasma release from target in active stealth technology Swathi Nambari, Sasibhushana Rao Gottapu and Kolluri Sri Ranga Rao

209

Performance comparison of microstrip antenna and dielectric resonator antenna (DRA) at RFID application K. Rama Devi

217

vi

A study of poultry realtime monitoring and automation techniques A. Arun Gnana Raj, S. Margaret Amala and J. Gnana Jayanthi

225

Impact of MgO interfacial layer of gate dielectric engineered monolayer MoS2 FET 239 Divya Bharathi N. and Sivasankaran K. Achieving ISO 26262 & IEC 61508 objectives with a common development process 247 Gadila Prashanth Reddy, Rangaiah Leburu, Kankanala Rajireddy, Jayakrishnan P and Justin Khoo Comparative analysis of impedance and capacitance based bio-sensors for cellular pathology Syed Shameem, P.S. Srinivas Babu, H. Sri Varun, C. Renukavalli and B. Manasa

257

Simulation of GaN MOS-HEMT based bio-sensor for breast cancer detection Rohit Bhargav Peesa, Pydimarri Manoj Kumar and D.K. Panda

269

Development of charge and discharge controller for solar lighting system Jayapragash R, Nandeesh Kumar K, Thirumalvalavan G and Arul R

275

ASIC Design of ALU with different multipliers Ramadevi Vemula and K. Manjunatha Chari

283

Gate diffusion input (Gdi) technique based CAM cell design for low power and high performance S.V.V. Satyanarayana, Sridevi Sriadibhatla and Nannuru Amarnath

289

Author index

297

Subject index

299

vii

Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

Foreword

On behalf of organising committee, we welcome you to the first annual conference on Computer-Aided Design in Electronics and Communication Engineering (CADEC 2019), held on date 2 – 3 March 2019. This is the first conference at VIT-AP University campus organized with the collective efforts of faculty members working in School of Electronics Engineering. We are very ambitious with this conference as in coming years we may plan to extend this conference at international level with indexing in web of conferences. CADEC-2019 conference covers most of the major topics trending recent in Electrical/Electronics and Communication Engineering. The main focus of this conference is to cover major research breakthrough and updates in the Electrical/ Electronics and Communication Engineering with broad perspective. Selecting high quality work through sufficient reviews was the top priority of this conference, so that collection of papers significantly aid to research and citation. We received around 65 contributions from India and abroad, out of which finally, 34 papers will be presented in two days sessions. We are very grateful to Vice-Chancellor VIT-AP, Prof. D. Subhakar and Management VIT-AP, for their support to CADEC 2019; we extend our gratitude to advisory members for their support, and APPLY VOLT for their sponsorship. Also our gratefulness goes to keynote speakers: Prof. V. Rama Krishna Murthy, Dr. Siva Rama Krishna Vanjari, Er. Umesh Lohani, and Dr. Ravikumar Bhimasingu, who came to CADEC-2019 conference to share their work with the conference participants. We are confident that with strong presence of renowned faculty/industry peoples, the participants will benefit a lot and are advised to attend all the sessions.

Organizing Committee School of Electronics Engineering Vellore Institute of Technology-Andhra Pradesh, University Amaravati, Andhra Pradesh, India

ix

Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

Committees

CHAIRS

• • •

Dr. Arun Kumar Sinha (Coordinator), VIT-AP University, Andhra Pradesh. Dr. Achintya Kumar Sarkar, VIT-AP University, Andhra Pradesh. Dr. M. Jagadish Chandra, VIT-AP University, Andhra Pradesh.

TECHNICAL COMMITTEE MEMBERS

• • • • • • • • • • • • • • • • •

Dr. Y. V. Pavan Kumar, VIT-AP University, Andhra Pradesh. Dr. N. Purnachand, VIT-AP University, Andhra Pradesh. Mr. D. John Pradeep, VIT-AP University, Andhra Pradesh. Dr. Jayendra Kumar, VIT-AP University, Andhra Pradesh. Dr. Ravindra Dhuli, VIT-AP University, Andhra Pradesh. Dr. Umakanta Nanda, VIT-AP University, Andhra Pradesh. Dr. Md. Sameulla Khan, VIT-AP University, Andhra Pradesh. Dr. Ch. Deepak, VIT-AP University, Andhra Pradesh. Dr. Deepak Kumar Panda, VIT-AP University, Andhra Pradesh. Dr. Sudha Ellison Mathe, VIT-AP University, Andhra Pradesh. Dr. Rajesh Saha, VIT-AP University, Andhra Pradesh. Dr. Sunny Dayal, VIT-AP University, Andhra Pradesh. Dr. Nandeesh Kumar, VIT-AP University, Andhra Pradesh. Dr. N. Venkata Rajasekhar, VIT-AP University, Andhra Pradesh. Mr. M. Kalyan Chakravarthi, VIT-AP University, Andhra Pradesh. Mr. M. Ganesh Lakshmana Kumar, VIT-AP University, Andhra Pradesh. Dr. Anoop Kumar Mishra, VIT-AP University, Andhra Pradesh.

WEBSITE DEVELOPMENT



Mohammed Suhail, VIT-AP University, Andhra Pradesh.

DIGITAL MEDIA



Ravi Kumar Thota, VIT-AP University, Andhra Pradesh.

xi

Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

About the editors

Dr. Arun Kumar Sinha received PhD degree in electronics engineering from the University of Genova, Genova, Italy, in 2013. He has an overall 8 years of experience in industry and teaching at Agilent Technologies (Gurgoan), Netaji Subhas Institute of Technology (New Delhi), Jaypee Institute of Information Technology (Noida), Mekelle University (Ethiopia), and post-doctoral research experience at Federal University of Santa Catarina, Brazil. Currently, he is working as Associate Professor at VIT-AP University, Amaravathi, India. He authored 15 papers in international journals/conferences. His research interests include interface electronics for tactile sensors, circuit simulations, measurements, analogue electronics, and transistor modelling. Mr. D. John Pradeep received M.Tech degree in electronics engineering from Indian Institute of Technology Hyderabad, India, in 2009. He has an overall 9 years of teaching experience at School of Electronics Engineering, VIT University, India. Currently, he is working as Senior Assistant Professor at VIT-AP University, Amaravati, India. His research interests include SAW sensors, advanced control, artificial intelligence, and machine learning.

xiii

Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

A distinct carry celect adder design approach for area and delay reduction using modified full adder K. Bala Sindhuri, G. S. Chandra Teja, K. Madhusudhan and N. Udaya Kumar Department of ECE, SRKR Engineering College, Bhimavaram, Andhra Pradesh Email: [email protected]; [email protected]; [email protected]; [email protected]

ABSTRACT: A SQRT Carry Select Adder (CSLA) design with modified full adder ar-

chitecture is proposed in this work. The regular SQRT CSLA has less delay but it is bulky when compared with other adders. The proposed design has reduced area and delay for a SQRT CSLA. The architecture is designed for a 128bit and is synthesized, simulated in Vivado v2017.2 software. The result concludes that the new design is giving a considerable amount of reduction in area and delay. Also, the proposed design is of 128-bit therefore it can be used in the future designs of efficient processor. Carry select adder; Full adder; Linear CSLA multiplexer based full adder; SQRT CSLA Keywords:

I.

INTRODUCTION

In the digital signal processing (DSP) adders have higher precedence. Adders are the basic blocks of the digital signal processing chips and are of different types. The different types of digital adders includes ripple carry adder (RCA), carry skip adder (CSKA), carry look ahead adder (CLA), carry increment adder (CIA), carry save adder (CSA) and carry select adder (CSLA). Among all the digital adders CSLA has a higher speed [1]. In RCA the carry from the starting stage is rippled to the remaining stages. This increases the propagation delay and the output sum appears only when the carry reaches the particular stage. The delay in RCA is increased linearly with the size of the input bits. The carry skip adder (also called as carry bypass adder) skips the carry at appropriate positions to boost the operation speed and the time required for this operation varies with respect to the data. The carry look ahead adder reduces the delay due to the propagation of the carry by looking at the lower adder bits of data and carry from the higher orders. The CLA design is more complex and it consumes more area when designed for more than 4-bits. In CIA, it is designed with RCA and an additional circuit that generates increment. Finally, in CSA the design has reduced delay by storing the carry generated in the present stage and by updating it on the next stage. In all the adders propagation of carry and gate count in the propagation path are the major cause for delay. An efficient architecture that reduces the delay due to the

1

propagation of the carry is the CSLA. Bedrij proposed that the difficulty of carry transition delay is rectified by generation of multiple radix carries and simultaneously generated sums are selected by using these carries [2]. In CSLA the sum output is generated even before the carry from previous stages is generated. The structure of CSLA generates the sum output for Cin = 1 and Cin = 0 also and the multiplexer is provided with the output carry from the preceding stages. Regular CSLA has linear bit grouping unlike the SQRT CSLA which has non-linear bit grouping [3-7]. In CSLA the delay is reduced by pre-computing the output sum without the arrival of carry. The area consumed by the conventional CSLA is high compared with the other types of adders. The gate count and area are reduced by using a binary to excess-one code converter (BEC), the BEC is used to replace the RCA structure used for generating the sum output when carry from the previous stage is one [8–9]. To reduce the area consumption of CSLA further, the 1-bit full adders in the RCA are designed with multiplexers. The multiplexer based full adder consumes less area when compared with the other conventional designs of the full adder because of only two transistors are required to implement a multiplexer. The proposed design has a full adder that is entirely designed using six multiplexers. The rest of the paper is organized as follows section II introduces the proposed architecture details. Section III elaborates the simulation results and comparisons. Section IV concludes the work. II.

PROPOSED 128 BIT CSLA DESIGN:

The functioning of CSLA can be comprehended by analyzing it in three distinct stages. 1. Ripple carry adder, 2. Full Adders, and 3. Multiplexers. A 4-bit RCA is shown in the Figure 1. The RCA of 4bit is developed with 4 full adders (1-bit) connected in cascaded form. The RCA of K input bits is implemented with K full adder structures. An output of (K + 1) bits is generated from a K-bit RCA (K-bits for sum and an additional bit for carry). The existing design requires a more number of transistors than the proposed design [10]. The four full adders in Figure 1 require, 8 EX-OR gates, 12 AND gates, and 8 OR gates. Since the implementation of the EX-OR gate requires a minimum of 12 transistors the area consumption is high when used excessively.

Figure 1.

a3 b3

a2 b2

al bl

aO bO

s3

s2

sl

sO

A 4-bit ripple carry adder using 4 full adders [2]

2

The multiplexers used in the CSLA design depends on the number of bits given to the RCA of the corresponding multiplexer. The sum output is chosen by the multiplexer between the responses of the RCA-1 and RCA-2 depending on the position of the Cin. When the Cin = 1 RCA-2 output is chosen as the sum and when Cin = 0 the response from the RCA-1 is considered by the multiplexer. The full adders used in the existing design are modified by the modified full adder structure. The modified full adder structure is given in Figure 3. It contains six 2:1 multiplexers for generating sum and carry. Since a multiplexer requires only 2 transistors, the area consumed by the designed adder is reduced by nearly 5% than the existing design. The comparison data can be viewed in TABLE 1. The full adder responses are the sum and carry, they are given in Boolean form as follows. SUM = X0 ⊕ X1 ⊕ X2 ....................................................................... (1) CARRY=X0.X1 + X1.X2 +X2.X0 .............................................................(2) From the Eq. (1) and (2) of SUM and CARRY, it is evident that SUM is generated by utilizing two 2-input EX-OR gates and CARRY is generated by utilizing three 2-input AND gates and two 2-input OR gates (or by one 3-input OR gate) [11]. The gate count is increased drastically when we use the normal full adder structure given in Figure 4. Especially the EX-OR will only require five other gates to implement. Since there is a number of full adders, the full adder is designated as the important block in the design of CSLA. So that area requirement is depended on the full adder design, for an efficient CSLA design the area consumed by the full adder should be as minimum as possible. For this reduction in area and power to be achieved the full adder can be designed using multiplexers only [12]. The multiplexer based designs have various implementations such as by using 4:1 multiplexers and some basic gates along with them. Also, the full adder can be designed by using 2:1 multiplexers and some basic gates along with them [13], [14]. Proposed design is efficient because it contains only multiplexers where routing is not complex, no other logic gates are used. This helps in the reduction of the delay to maximum extent. Y!llWlJ X[l27:lllJ

Yli:OJ X[i:OJ

c;,

S{lll:IIJJ

Figure 2.

S{l"lJ

S(6.4J

Proposed 128-bit CSLA design using modified full adder

3

S(I:OJ

X2

Xl

xo

CARRY

Xl X2

xo SUM

Xl

xo Figure 3.

Full adder using six multiplexers [12]

SUM

C ARRY

Figure 4.

Basic full adder structure [12]

III. RESULTS AND COMPARISONS This proposed work is done in Verilog-HDL and simulated using the Xilinx Vivado 2017.2 software, the results of our modified full adder based design and the regular adder design are depicted in Figure 5 and Figure 6 respectively. The comparison of the area required by the regular 128-bit SQRT CSLA and our modified 128-bit SQRT CSLA is shown in Table I.

4

Table I. Comparison of area and delay of normal full adder based and modified full adder based structures Adders name

Total delay

Total number of LUTs consumed Setup

Hold

Normal full adder based SQRT CSLA

270

5.984 ns

0.34 ns

Modified full adder based SQRT CSLA

246

5.662 ns

0.34 ns

Figure 5.

Results of the SQRT CSLA with the modified full adder design

Figure 6.

Results of 128-bit SQRT CSLA with normal full adder design

The comparison graph shown in Figure 7 shows the difference in the area required. From the graphical analysis, it is evident that the area requirement of regular SQRT CSLA is higher when correlated with our modified SQRT CSLA. The RTL schematic of the proposed design is depicted in the Figure 8. Individual ripple carry adder’s RTL schematic is shown in Figure 9. The delay results are shown in the Table I. It is clear that there is an impressive reduction in delay for the proposed design when correlated with the regular SQRT CSLA. The graphical analysis of delay is shown in the Figure 10.

5

LUT count

275 270 265 260 255 250 245 240 235 230

Normal full adder based SQRT CSLA

Modified full adder based SQRT CSLA

LUTs

Figure 7. Plot showing the variation in consumption of LUTs for normal and modified structures

Figure 8.

RTL schmatic of modified full adder based SQRT CSLA

Figure 9.

RTL schematic of single block in the main aechitecture

6

Total delay (ns)

7 6 5 4 3 2 1 0

Normal full adder based SQRT CSLA

Modified full adder based SQRT CSLA

Total delay (Setup) Total delay (Hold) Figure 10. Plot showing the variation in delay for normal and modified structures

IV. CONCLUSION As the area and delay reduction are the critical issues of normal SQRT CSLA. From the proposed design results, it is concluded that this can be reduced by the proposed design which consists of modified full adder replaced the normal full adder in the ripple carry adder block. The proposed design reduces the LUT count by 4.7% and the delay is reduced by 5.3%. In future work LUT count can be reduced by modifying the binary to excess-1 code converter in the CSLA structure. REFERENCES 1.

2. 3. 4.

5.

6.

J. Kaur, and L. Sood, “Comparison Between Various Types of Adder Topologies,” International Journal of Computer Science Technology, vol. 6, no. 1, pp. 62–66, March 2015. O. J. Bedrij, “Carry-select adder,” IRE Trans. Electron Comput., vol. EC-11, pp. 340–346, June 1962. S. Manju, V. Sornagopal, “An efficient SQRT architecture of carry select adder design by common Boolean logic,” Proc. VLSI ICEVENT, pp. 1–5, 2013. P. Nautiyal, P. Madduri, and S. Negi, “Implementation of an ALU using modified carry select adder for low power and area-efficient applications,” Int. Conf. on Computer and Computational Sciences, Noida, India, pp. 22–25, 2015. B. Ramkumar, and H. M. Kittur, “Low-Power and Area-Efficient Carry Select Adder”. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no.2, pp. 371–375, Jan. 2011. R. Priya, and J. S. Kumar, “Implementation and comparison of effective area efficient architectures for CSLA,” Proc. IEEE Int. Conf. Emerging Trends Comput. Commun. Nanotechnol., pp. 287–292, Mar. 2013.

7

7.

8.

9.

10. 11. 12. 13.

14.

G. C. Manjunatha, and R. Singh, “Low Power VLSI Design for Power and Area Effective Utilisation of Carry Select Adder,” Int. Conf. on Current Trends in Computer, Electrical, Electronics and Communication, Mysore, India, pp. 606–610, 2017. N. Patil, A. Joshi, N. Eskandari, and T. Nikoubin, “RCA with conditional BEC in CSLA structure for area-power efficiency,” 6th Int. Conf. on Computing, Comm. and Networking Technologies, Denton, USA, pp. 1–4, 2015. L. Mugilvannan, and S. Ramasamy, “Low-Power and Area-Efficient Carry Select Adder Using Modified BEC-1 Converter”, IEEE-31661. 4th ICCCNT 2013, Tiruchengode, India, pp. 1–5, 2013. S. Nagaraj, G. M. Reddy, and S. A. Mastani, “Analysis of different Adders using CMOS, CPL and DPL logic,” 14th IEEE India Council Int. Conf. pp. 1–6, 2017. T. -. Chang and M. -. Hsiao, “Carry-select adder using single ripple-carry adder,” in Electronics Letters, vol. 34, no. 22, pp. 2101–2103, Oct. 1998. A. Anand Kumar, Switching Theory and Logic Design, 2nd ed. Delhi, PHI Learning Private limited, 2014 N. A. Kamsani, V. Thangasamy, Shaiful, M. F. Bukhori, Z. Yusoff, M. N. Hamidon, “A low power multiplexer based pass transistor logic full adder,” IEEE Regional Symp. on Micro and Nano electronics (RSM), Kuala Terengganu, Malaysia, pp. 1–4, 2015. K. A. K. Maurya et. al., “Design and implementation of 32-bit adders using various full adders,” 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, India, pp. 1–4, 2017.

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Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

Performance analysis of different multiplier architectures using 1-bit full adder structures N. Udaya Kumar, G. S. Chandra Teja, K. Rajesh, V. Soma Sandeep and K. Bala Sindhuri Department of ECE, SRKR Engineering College, Bhimavaram, Andhra Pradesh Email: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]

ABSTRACT: In digital systems the most frequently used structure is an Adder. The

Adder is the main structure also in Microprocessor/Microcontroller. Overall performances of digital systems are mainly dependent on adder structure. Therefore a good design adder structure can improve the performance of digital system. In this paper Booth and Vedic multiplier using multiplexer based 1-Bit Full adder structures are designed and simulated using Vivado v2017.2 software tool. The proposed multiplexer based 1-Bit Full adder structures shows reduced delay and power consumption. 1-Bit Full adder; Booth multiplier; Delay efficient; Multiplexer based Full adder; Radix4 Booth multiplier; Vedic multiplier Keywords:

I.

INTRODUCTION

Technology is developing a lot in digital electronics in which digital signal processors play crucial role. Every digital signal processor (DSP) consist of multiplier and adder structures. Therefore, overall performance of the DSP like power consumption, delay and gate count depends on multiplier and adder structure. Multiplier itself consists of adder structure in its operation. The adder structure begins with 1-Bit Full adder circuit in which the transistor counts varies from 28 to a minimum of 6 transistors. So, an efficient 1-Bit Full adder structure can improve DSP performance a lot [1–4]. In present work the main concentration is on different 1-Bit Full adder structures and their performance in Booth and Vedic Multiplier circuit. In basic arithmetic operations performed in VLSI systems addition is often used and it has major priority. It is used to perform summation of binary values and can also be used in many arithmetic operations. The overall efficiency of the system is based upon adder performance. By evaluating delay calculations, the speed of operation of the design circuit can be deduced. It is dependent up on implemented transistor sum, logic depth and other measures. Also power consumption is dependent upon the switching activity performed by the numerous transistors in the circuit. The routing flexibility determines the area to be occupied by the circuit. Booth Multiplier: In Booth multiplication, partial product generation depends upon

the recoding scheme e.g. Radix-2 encoding. Multiplication using normal Booths

9

recoding algorithm technique based on the partial product can be generated for a group of consecutive 0’s and 1’s which is called Booths recoding. This recoding algorithm is used to generate an efficient partial product. This increase in the width of partial product usually depends upon the radix scheme used for recoding. The booth algorithm is an effective technique for 2s complement multiplication. The booth algorithm reduces the number of partial products by shifting over a string of zeros. The increase in speed is proportional to the number of zeros in the recoded version of the multiplier [5–6]. In this radix2 algorithm, the main disadvantage is no. of partial products increases when one of the inputs is alternatively 1’s and 0’s i.e., 01010101. Vedic multiplier: The Vedic multiplier is a simple digital multiplier architecture/

algorithm that is based on the vertical and cross-wise multiplication of the multiplier and the multiplicand in terms of the number of bits that are specified for multiplication. It is derived from the Indian Vedic sutras from ancient scriptures that gave a set of algorithms to perform calculations in a faster manner [7]. This paper is structured as: Section II deals with the existing 1-Bit Full adder. Section III deals with proposed 1-Bit Full adder structures in detail such as 1-bit full adder using three 2:1 mux and two NOT gates, 1-Bit full adder using two 4:1 mux and NOT gate and 1-Bit full adder using five 2:1 mux and two NOT gates. Section IV deals with the simulation, synthesis results and comparisons. Finally, Section V concludes the work done. II.

EXISTING 1-BIT FULL ADDER

In general, a digital circuit that performs arithmetic addition of two binary values is known as the full adder. It takes three single bit values (two operands and a carry bit) and generates two output values namely the sum and the carry out as shown in Figure 1. As a full adder intakes two binary inputs along with a carry or overflow bit, the generated outputs are sum and carry bit. An XOR, AND and OR gate based hardware is used for the full adder [8–12]. Full adders (FA) are orderly chained to each other to form an arbitrary length (such as 32 or 64) of bits by adding bits. This normal Full adder uses 28 transistors in its logic structure.

Figure 1.

Normal 1-Bit Full adder (Normal FA)

10

III. PROPOSED 1-BIT FULL ADDER STRUCTURES A.

1-Bit Full adder structure using three 2:1MUX and two NOT gates(FA1)

The multiplexer based full adder consists of three 2:1 multiplexers and two NOT gates. Here A, B, C, ~C and ~B are inputs of the three multiplexers, here ~c and ~b are NOT gates outputs. The output of second stage multiplexer is given to the selection line for remaining two multiplexers, these two multiplexers outputs are sum and carry respectively as shown in Figure 2. CARRY

A

c

Figure 2.

B.

Full adder using three 2:1 mux and two NOT gates (FA1)

1-Bit Full adder structure using two 4:1 MUX and a NOT gate(FA2)

Multiplexer based full adder consists of NOT gate and two 4:1 multiplexers as shown in Figure 3. Here inputs are ‘c’ and inverted ‘c’ for a multiplexer that gives sum as the output and ‘0’,‘c’ and ‘1’ for the other multiplexer that gives carry as output and the selection lines are ‘a’ and ‘b’ for the 4:1 multiplexers. Sum and carry are the outputs of the two 4:1 multiplexers.

·~

01\IJUX

SUM

4: 1

MUX

CARRY

4:1

1SeiK:Ihln

a

Figure 3.

c-{

Srh~crlnn

b

b

Full adder using two 4:1 multiplexers and a NOT gate (FA2)

C.  1-Bit Full adder Structure using five 2:1 MUX and two NOT gates(FA3)

Multiplexer based full adder consists of five 2:1 multiplexers and two NOT gates. Here inputs of the three multiplexers consists of ‘c’, inverted c,‘0’ and ‘1’ input

11

combinations, here inverted c is obtained by using NOT gate, ‘A’ is the selection line for the three 2:1 multiplexers and B is selection for the other two 2:1 multiplexers as shown in Figure 4. The outputs of first stage 2:1 multiplexers are given as inputs to the next stage 2:1 multiplexers. In this second stage two 2:1 multiplexers produce sum and carry outputs respectively.

,q ,.MUX t

1

q

,.MUX r UM 1

o - --1

c- - - 1

2:1 MUX

A

2:1 MUX

c - - -1

CARRY

B

2:1 MUX

1 - --t A

Figure 4.

Full adder using 2:1 multiplexers (FA3) [1]

IV. RESULTS The proposed 1-Bit Full adder structures performance are obtained by using these structures in 8×8 Booth and Vedic multipliers. The simulation and synthesis results for Booth and Vedic multipliers are shown below in detail respectively. A.

Proposed booth multiplier using different 1-Bit full adder structures

The proposed methodology is simulated and synthesized using Vivado v2017.2 software. The simulated result for 8×8 booth multiplier using multiplexer based adder structure is shown in Figure 5.

Figure 5. structure

Simulation result for 8×8-Bit booth multiplier using multiplexer based adder

Inputs for 8×8 booth multiplier using multiplexer are a[7:0], b[7:0] taken as “00010000”, “00000010” respectively and so obtained output p[15:0] is “0000000000100000”.

12

The proposed booth multiplier using multiplexer based full adder structures i.e., (FA1 to FA2) and existing full adder (Normal FA) are coded in Verilog and the synthesis is carried out using Vivado v2017.2 software. The synthesis file consists of the number of LUT’s, delay and power consumption of respective designs are mentioned in TABLE I. The proposed booth multiplier using multiplexer based full adders has significant less delay and power consumption compared to existing full adder is also shown in TABLE I. A comparison is made between booth multiplier using existing full adder i.e., normal FA and remaining booth multiplier using multiplexer based full adders i.e., (FA1 to FA3) listed as S.No. 2 to 4, in TABLE I. The comparison results in percentage are tabulated in TABLE II. The proposed booth multiplier using multiplexer based full adder designs offer saving of 0.23 to 10.26 of delay in percentage, offer saving of 1.137 to 6.423 of power in percentage and slightly increase in area consumption. Table I. Lut’s, delay and power comparison for booth multiplier using different adder structures S. No

Full adder structures

LUT’s

Delay(ns)

Power (watts)

1

Normal FA

73

9.887

15.91

2

FA1

86

9.872

14.888

3

FA2

73

9.864

15.543

4

FA3

73

9.54

15.729

Table II.

Lut’s, Delay and Power Comparison In % with Respective to Booth Multiplier Using

Normal Adder Structure S. No

Full adder structures

LUT’s (%)

Delay (%)

Power (%)

1

FA1

+17.8

-10.26

-6.423

2

FA2

0

-0.23

-2.306

3

FA3

0

-3.50

-1.137

For better understanding the above results are depicted graphically and shown in Figure 6 to Figure 8.

LUT's comparison of booth multiplier using different FA structures 90

Figure 6.

LUT’s comparison of booth multiplier using different FA structures

13

Delay comparison of booth multiplier using different FA structures

Figure 7.

Delay comparison of booth multiplier using different FA structures

Power comparison of booth multiplier using different FA structures

Figure 8.

B.

Power comparison of booth multiplier using different FA structures

Proposed Vedic multiplier using different 1-Bit full adder structures

The proposed methodology is simulated and synthesized using Vivado 2017.2 software. The simulated result for 8×8 Vedic multiplier using multiplexer based adder structure is shown in Figure 9.

Figure 9. structure

Simulation result for 8×8-Bit vedic multiplier using multiplexer based adder

Inputs for 8×8 Vedic multiplier using multiplexer are a[7:0], b[7:0] taken as “11111111”, “11111110” respectively and so obtained output c[15:0] is “1111110100000010”.

14

The proposed Vedic multiplier using multiplexer based full adder structures i.e., (FA1 to FA3) and existing full adder (Normal FA) are coded in Verilog and the synthesis is carried out using Vivado v2017.2 software. The synthesis file consists of the number of LUT’s, delay and power consumption of respective designs are mentioned in TABLE III. The proposed Vedic multiplier using multiplexer based full adders has significant less delay and power consumption compared to existing full adder is also shown in TABLE III. Table III. Lut’s, delay and power comparison for vedic multiplier using different adder structures S. No

Different FA

LUT’s

Delay(ns)

Power (watts)

1

Normal FA

87

8.281

13.658

2

FA1

96

7.837

13.849

3

FA2

94

7.782

13.794

4

FA3

87

8.103

13.65

A comparison is made between Vedic multiplier using existing full adder i.e., normal FA and remaining Vedic multiplier using multiplexer based full adders i.e., (FA1 to FA3) listed as S.No 2 to 4 in TABLE III. The comparison results in percentage are tabulated in TABLE IV. The proposed Vedic multiplier using multiplexer based full adder designs offer saving of 2.14 to 6.02 of delay and slightly increase in power and area consumptions. Table IV.

Lut’s,delay and power comparison in % with respective to vedic multiplier using

normal adder structures S. No

Different FA

LUT’s (%)

Delay (%)

Power (%)

1

FA1

+ 10.34

– 5.361

+ 1.39

2

FA2

+ 8.04

– 6.02

+ 0.99

3

FA3

0

– 2.14

+ 0.05

For better understanding the above results are depicted graphically and shown in Figure 10 - Figure 12.

Figure 10. LUT’s comparision of vedic multiplier using different FA structures

15

Figure 11.

Delay comparision of vedic multiplier using different FA structures

Figure 12. Power comparision of vedic multiplier using different FA structures

V.

CONCLUSION

Performance analysis of different multiplier architectures using 1-Bit Full Adder structures is carried out in this paper. The novelty of the paper is design of 1-Bit Full adder structures namely FA1, FA2 and FA3 are of its first kind. From the results it can be concluded that the proposed multiplexer based 1-Bit Full adder Structures show better results when compared to normal adder structure. These adder structures involve slightly more no of LUT’s when compared to normal adder structure. It is observed that the proposed multiplexer based 1-Bit Full adder Structures have less power and has less delay consumption. It can be concluded that the proposed structures for the

16

adder have potent speed and power. Thus the proposed structures for the 1-Bit Full adder are appropriate for high-speed applications. REFERENCES K. A. K. Maurya et. al., “Design and implementation of 32-bit adders using various full adders,” 2017 Innovations in Power and Advanced Computing Technologies (i-PACT), Vellore, India, pp. 1–4, 2017. 2. A. K. Yadav et. al., “Low power high speed 1-bit full adder circuit design at 45nm CMOS technology,” 2017 Int. Conf. on Recent Innovations in Signal processing and Embedded Systems (RISE), Bhopal, India, pp. 1–4, 2017. 3. N. Tiwari, R. Sharma, and R. Parihar, “Implementation of area and energy efficient Full adder cell,” IEEE Int. Conf. on Recent Advances and Innovations in Engineering (ICRAIE-2014), Jaipur, India, pp. 1–4, 2014. 4. S. Pandey, A. K. Afshan, and R. Sarma, “Comparative Analysis of Carry Select Adder using 8T and 10T Full Adder Cells,” Int. Conf. on Communication and Signal Processing, Melmaruvathur, India, pp. 1–4, 2014. 5. R. Balakumaran, and E. Prabhu, “Design of high speed multiplier using modified booth algorithm with hybrid carry look-ahead adder,” in Proc. of IEEE Int. Conf. on Circuit Power and Computing Technologies (ICCPCT), Nagercoil, India, pp. 1–4, 2016. 6. B. Rashidi et. al., “Design of a low-power and low-cost booth-shift/add multiplexerbased multiplier”, 22nd Iranian Conference on Electrical Engineering (ICEE), Tehran, Iran, pp. 1–4, 2014. 7. M. Saji, S. P. Antony, and S. Indu, “Design of high speed vedic multiplier using multiplexer based adder,” Int. Conf. on Control Communication & Computing India (ICCC), Trivandrum, India, pp. 1–5, 2015. 8. V. Thenmozhi, and R. Muthaiah, “Optimized low power full adder design,” Int. Conf. Networks & Advances in Computational Technologies (NetACT), Thiruvanthapuram, India, pp. 1–4, 2017. 9. S. Musala, and B. R. Reddy, “Implementation of a Full Adder Circuit with New Full Swing Ex-OR/Ex-NOR Gate,” IEEE Conference-Prime Asia, pp. 29–33, Dec. 2013. 10. T. Sharma, K. G. Sharma, and B. P. Singh, “High Performance Full Adder Cell: A Comparative Analysis,” in Proc. of the 2010 IEEE Students Technology Symposium, Kharagpur, India, pp. 1–5, 2010. 11. S. Khan, S. Kakde, and Y. Suryawanshi, “VLSI Implementation of Reduced Complexity Wallace Multiplier Using Energy Efficient CMOS Full Adder,” IEEE Int. Conf. on Computational Intelligence and Computing Research (ICCIC), Enathi, India, pp. 1–4, 2013. 12. B. Harish, K. Sivani and M. S. S. Rukmini, “Performance comparison of various CMOS full adders,” Int. Conf. on Energy, Comm., Data Analytics and Soft Computing (ICECDS), Chennai, India, pp. 1–5, 2017. 1.

17

Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

QCA based binary adder-subtractor Akondi Narayana Kiran and Akhendra Kumar Padavala Electronics and Communication Engineering, Shri Vishnu Engineering College for Women, Bhimavaram, Andhra Pradesh, India Email: [email protected]; [email protected]

ABSTRACT: Over past several years in VLSI fabrication, the chip size has been reduced

dramatically. As the technology scales down, the miniaturization of CMOS circuits leads to sub-threshold effects with increased fabrication cost. Quantum dot Cellular Automata (QCA) is one of the nanotechnologies which can overcome these difficulties.This technology is best suited for producing low power, high performance and dense structures. This work deals with analysis and design of a binary adder-Subtractor. The design layout and simulations were done using QCA Designer tool. The simulation results show that the design can perform both addition and subtraction operations, by occupying lesser area and reducing delay considerably. Keywords:

1.

QCA; CMOS; Sub-threshold leakage; Short channel effects

INTRODUCTION

Rapid growth has been made in field of semiconductors production techniques by steadily reducing critical dimensions of circuit elements due to the high speed integrated circuits with very low power. High complex logic and memory circuits are designed based on CMOS process which achieves high package density. Mass production techniques using silicon semiconductor is due to the advantage of silicon free availability with low cost. On the other hand, significant reduction in the dimensions of basic transistor causes serious problems like low charge carrier mobility, increased lithography cost and heat, these problems imposes an ever increasing burden on well-established CMOS technology [1], [2]. Therefore, there is a need for new materials that may efficiently replace the silicon base material for the fabrication. The techniques like Carbon Nano Tube Field Effect Transistor (CNFET), Resonant Tunneling Diode (RTD) and Quantum dot Cellular Automata (QCA) have been emerged to solve the problems of semiconductor industry [3], [4]. Among them QCA proven to be promising solution to the current needs. Quantum-dot Cellular Automata (QCA) is one of the emerging nano-technologies in which it is possible to achieve high circuit densities and clock frequencies, it also overcome the limitations of the CMOS technology which are caused due to the scaling. QCA gained attention due to its low power, low area and high package density. QCA was proposed initially for data transmission from cell to cell in the form of propagation of state instead

19

of electron beam [5]. QCA has wide range of applications like testing [6], digital circuits [7], and so on. In QCA, special efforts are made in designing basic logic circuits. Simple circuits like full adder have already fabricated using QCA [8] and some complex designs like 32 bit adders have been simulated using QCA design tools [9], [10]. In [11],–[13] a new technique was proposed in implementing a 2-bit adder, which occupies low area and gives reduced delay considerably. Electron

Quantum Dot



0 •

0

0

P=+1 Binary 1

Figure 1.



P=-1 Binary 0

QCA cell representation of two binary levels

This paper is mainly focused on performing the Binary addition and subtraction by using 2s complement method. The organization of paper is as follows: Quantum cellular automata was introduced in section II with existing adders. Section III explains about the proposed adder-subtractor architecture and section IV explains the simulation results. Finally the conclusions are made in section V. II. A.

OVERVIEW OF QUANTUM CELLULAR AUTOMATA Basics of QCA

Phase 0

Phase 1

Phase 2

Phase 3

Figure 2. Four-phase clocking scheme

20

QCA cell is the primitive cell to construct logic gates on the basis of a basic quantum mechanical system. QCA cell can be implemented based on four quantum dots. The quantum dot may represent a potential well for the electrical charge. The electrons are reside on diagonal positions due to columbic repulsion between them and these positions represent the state (binary level) of the QCA cell as shown in Figure 1. In CMOS, external power supply is used to power up the circuit but in case of the QCA clock supplies power to the QCA circuit. In the clock assignment for QCA, minimum three phase clocking scheme is required for proper information transfer. The four phase pipelined clocking scheme is shown in Figure 1. In this clocking scheme each phase is differed by 900 with its successor clock, thus it acts as a power source in transferring the information. B.

Existing Adders in QCA

To implement n-bit Ripple carry adder (RCA), ‘n’ no. of 1-bit full adders are to be cascaded. There by taking much time to generate the resultant output. For a 1-bit FA, carry-in to carry-out path consists of one MG and carry in to sum bit path consists of two MGs plus one inverter. Thus, the worst case path delay for both RCA became (n + 2) MGs plus one inverter. Similarly, in case of Carry Flow Adder (CFA), it takes a total of (n + 2) MG s and one inverter to perform addition of two ‘n’-bit numbers. A Carry Look Ahead adder (CLA) architecture formed by 4-bit slices was also presented in [7]. In CLA, carry generate gi = ai.bi and carry propagate pi = ai⊕bi are computed for each bit are grouped by four. And the computational path delay consists of 7+4 (log4 n) cascaded MGs and one inverter, Where ‘n’ is the no. of input bits to be processed. And parallel-prefix adder, Brent-Kung adder (BKA) [8] is more efficient logic design as it can achieve lower computational path delay compared to previously described architectures. If it is an n-bit adder, then the prefix tree consists of 2 × log2 (n-2) stages. And the worst case computational path consists of 4 × log2 (n-3) cascaded MGs and 1 inverter.

Figure 3.

Carry block for n-bit novel ripple Adder-Subtractor

21

The Novel architecture proposed in [11], for the implementation of ripple adder is efficient both regarding area and delay. The carry generated at the least significant bit position is propagated through two subsequent bit positions and the delay of just 1 MG. The worst case computational path of novel adder consists of (n/2) + 3 cascaded MGs and one inverter. III. PROPOSED ARCHITECTURE FOR ADDER-SUBTRACTER The proposed Adder-Subtractor design is implemented by extending the novel ripple adder demonstrated in [11]. The adder is modified in such a way that it can perform both addition and subtraction operations depending on the control signal ‘add/subtract’ and the method used here is 2’s complement method. Let the inputs to the n-bit adder-Subtractor module be a = an....a0 and b = bn….b0. In the proposed architecture, one of the two inputs, i.e., either ‘a’ or ‘b’ is ‘xor’ed with the control signal input ‘add/subtract.’ And also the ‘carry in’ of the least significant FA is fed with this ‘add/subtract’ control signal. When add/subtract = ‘0’ then, Sum bit gives you S = a + b. When add/subtract = ‘1’ then, Sum bit gives you S = a + 1 + b = a – b. In the modified carry chain shown in Figure 3, the sub-block indicating ‘Array of XOR gates’ complements the ‘n’– bit input ‘a’ and then feeds it to the carry block to produce the carry of particular bit carry. After the generation of each carry bit, it is fed to the sum block, shown in Figure 4. Here, carry input of the sum block is fed with ‘Add/Subtract’ control signal. Depending on the control signal, this block gives you either the sum of inputs or the difference of inputs. This implementation simply depends on 2’s complement method. In dealing with 2’s complement method of addition-subtraction, while considering two signed ‘n’-bit numbers, there is a condition of occurring overflow if both the numbers are of same sign (either positive or negative). Because of the overflow occurrence there is a requirement of ‘n’ + 1 bits to store the result of addition otherwise it leads to wrong answers.

Figure 4.

Sum block for n-bit proposed ripple Adder-Subtractor

22

One way to detect the overflow is considering the sign of two ‘n’-bit numbers and comparing it to that of the result of their addition. i.e., an–1, bn–1 and Cn. •

If the two ‘n’-bit numbers are of positive i.e., an-1 = 0 and bn–1 = ‘0’ and the sign of the result is negative i.e., Cn = ‘1’ then it shows that the addition of the two positive numbers is resulted in a negative value, it indicates an overflow has occurred. Similarly in case of adding two negative numbers, if the addition results in a non-negative result, it shows that an overflow has occurred.



From above two cases, there is an easier formula to detect the overflow occurrence given by equation 1. Overflow = Cn XOR Cn–1 ................................................................ (1) IV. SIMULATION RESULTS The adder-Subtractor architecture is implemented for 8-bit input (range) using QCA designer tool, Multilayer Crossing is used in designing the layouts. Simulation engine used is coherence vector engine for the accurate results. Table I.

Comparison among Adder-Subtractor design

Adder-Subtractor

Area (μm2)

Complexity (#No. of cells)

Delay(pS)

Existing (8-bit) [12]

10.47

5786

27.25

Proposed (8-bit)

2.96

2282

2.75

Figure 5.

Layout of the 8 bit Adder-Subtractor in QCA

23

Figure 6.

Simulation results for the 8-bit adder-Subtractor

Layout and Simulation results for the 8-bit Adder Subtractor were shown in figure 5 and figure 6 respectively. From the design, the first valid output gets generated after eleven clock phases. For the calculation of the least significant carryout, it takes six clock phases, and it takes three more clock phases for the carry propagation to the most significant bit and there it takes two clock phases to compute the final sum output. Carry out of the most significant bit is included in the output sum bus of 9 bits as the most significant bit. Table I compares the proposed layout with the layout presented in [12]. The Adder-Subtractor design presented in [12] uses normal adder design like RCA, so it has taken much area and time for the computation but in case of proposed design, an optimised adder technique [11] is used in designing the Adder-Subtractor circuit which in turn reduced the area of the design and computational delay. V.

CONCLUSION

In this paper, Ripple carry Adder/Subtractor is proposed. The performance between the conventional Ripple carry adder and proposed Adder/Subtractor is compared using QCA tool. The proposed design having lower propagation delay due to achieves 28.27%, 39.44%, and 10.1%, improvements in area, complexity and delay respectively compared to conventional RCA. This project can be improved further by using ‘Reversible Logic’ in designing the circuit to get a reduction in quantum-cost and depth of the circuit.

24

VI. ACKNOWLEDGMENT Authors would like to acknowledge the encouragement given by management of Shri Vishnu Engineering College for Women, Bhimavaram. REFERENCES 1. 2. 3. 4. 5.

6. 7. 8. 9. 10. 11. 12.

13.

C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernestein, “Quantum cellular automata,” Nanotechnology, vol. 4, no. 1, pp. 49–57, 1993. M. T. Niemer and P. M. Kogge, “Problems in designing with QCAs: Layout = Timing,” Int. J. Circuit Theory Appl., vol. 29, no. 1, pp. 49–62, 2001. J. Huang and F. Lombardi, Design and Test of Digital Circuits by Quantum-Dot Cellular Automata. Norwood, MA, USA: Artech House, 2007. S.-Ho Shin, J.-C. Jeon and K.-Y. Yoo, “Wire-crossing technique on Quantum-Dot Cellular Automata”, NGCIT 2013, ASTL vol.27, pp. 52–57, 2013. K. Walus, T. J. Dysart, G. A. Jullien, and A. R. Budiman, “QCADesigner: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata,” IEEE Trans. Nanotechnology, vol. 3, no.1, pp. 26–31, march 2004. H. Cho, and E. E. Swartzlander, “Adder design and analyses for the Quantum-dot cellular automata,” IEEE Trans.Nanotechnology, vol. 6, no. 3, pp. 374–383, June. 2007. H. Cho and E. E. Swartzlander, “Adder and multiplier design in quantum-dot cellular automata,” IEEE Trans. Compute., vol. 58, no. 6, pp. 721–727, June. 2009. V. Pudi and K. Sridharan, “Low complexity design of ripple carry and Brent–Kung adders in QCA,” IEEE Trans. Nanotechnology., vol. 11, no. 1, pp. 105–119, January. 2012. W. Liu, L. Lu, M. O’Neill, and E. E. Swartzlander, Jr., “Design rules for quantum-dot cellular automata,” in Proc. IEEE Int. Symp. Circuits Syst., May 2011, pp. 2361–2364. S. Perri and P. Corsonello, “New methodology for the design of efficient binary addition in QCA,” IEEE Trans. Nanotechnology., vol. 11, no. 6, pp. 1192–1200, November. 2012. S. Perri, P. Corsonello, and G. Cocorullo,”Area-DelayEfficient Binary Adders in QCA,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 5, may 2014 M. Kianpour, R. S. Nadooshan, and K. Navi. “A Novel Design of 8-bit Adder/Subtractor by Quantum-Dot Cellular Automata,” Journal of Computer and System Sciences, vol. 80, no. 7, pp. 1404–1414, 2014. W. S. Jahan, “Designing Nanotechnology based QCA full adders,” Int. J. of Computer Trends and Technology, vol. 49, no.4, pp.206–212, 2017.

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Computer-Aided Developments: Electronics and Communication © 2019 by Taylor & Francis Group, London, ISBN 978-0-429-34071-0

Low power design of memoryless adaptive filter using distributed arithmetic unit Debanjan Kundu and Sriadibhatla Sridevi SENSE, Vellore Institute of Technology, Vellore, Tamil Nadu – 632014 Email: [email protected]; [email protected]

In this paper, an area efficient low power design of memoryless distributed arithmetic based Least mean square adaptive filter has been proposed. The throughput is increased because of computing the inner product and simultaneously implementing in weight-increment operation. Here we have proposed two memoryless design of distributed arithmetic (DA) unit. First Design uses 2:1 multiplexers and second design uses Onboard Credential (ObC) architecture to replace Look Up Table (LUT) of the conventional DA to reduce the overall area of the filter. Enhanced compressor adder is used for accumulation of the partial products, which further helps to reduce the area. Parallel updating of the generation and accumulation enhance the throughput of the design. The proposed designs require more than half area that required for the existing LUT based inner product block. The synthesis result shows that the area reduced by 52.79% and also the MUX based DA for the Adaptive filter causes 69.25% less power consumption for filter tap: N = 16, 32 and 64. Proposed design provides 36.50% less Area Delay Product (ADP). ABSTRACT:

LMS Adaptive Filter; Distributed Arithmetic; Weight-increment; Inner Product Block. Keywords:

I.

INTRODUCTION

Adaptive Filter is a linear model where the filter coefficients are not fixed unlike other filters. In this the coefficients get revised at each iteration so that the error between the accurate signal and desired signal is less [1]-[3]. The multipliers and adders take more computation time and area. Hence Distributed Arithmetic (DA) is chosen for implementing because it takes less computing time and area efficient [2]-[4]; it is mainly used for calculating Sum of Product and it also saves a lot of area in DSP application. In practical application it is used in telecommunication, audio and video signal processing, noise and echo cancellation. Adaptive filter design can be analog, digital or can be mixed type with respect to its advantages and disadvantages. Adaptive Filters [5]-[9], can also be of different types. Above discussion can be briefed as follows: 1.

Elimination of Look Up Table (LUT) based memory unit improve the through put rapidly.

27

2. 3.

II.

Simultaneous increment of the weight update block, increase the throughput further. Use of Enhanced Compressor adder for accumulation reduce overall area of the filter along with the reduction of time complexity of the design. In this design of the filter, there are four major blocks. 4-point IPB, WIB block, signmagnitude separator and control word generator. IPB computes the partial product for the filter and the WIB dynamically updates the filter coefficients. Forward path becomes the critical path because of inner-product block which results in the desired output. Thus, high sampling frequency cannot be used for input signal as the critical path increases and ultimately becomes greater than sampling rate. OVERVIEW OF LMS ADAPTIVE ALGORITHM

In this algorithm the output of the filter and the error i.e., the difference between the desired output and the filter output is computed for each cycle. The equation for weight updating of an nth iteration is w(n + 1) = w(n) + μ ・e(n) ・x(n) ........................................(1) Error e(n) and output of filter y(n) can be written as: e(n) = d(n) − y(n); y(n) = wqT(n)∙x(n). In (1), w(n) – weight vector, d(n) – desired response, µ is factor of convergence and x(n) – input vector. Their expansion are given by (2) and (3). x(n) = [x(n), x(n − 1), . . . , x(n − N + 1)]T.............................. (2) w(n) = [w0(n), w1(n), . . . , wN−1(n)]T...................................... (3) For pipelined structure, error signal is achieved after certain number of cycles, which is termed as “adaptation delay.” ‘e(n–m)’- delayed error is used in updating the weight-increment block where m be the adaptation delay of the filter. Weight-update equation for delayed Least Mean Square adaptive filter is given by: w(n + 1) = w(n) + μ∙e(n–m)∙x(n–m) ..................................... (4) III. DESIGN OF INNER-PRODUCT BLOCK A. Proposed Design 1 - MUX Based Model Since the LUT design consumes larger area for inner product computation hence it is replaced by multiplexers for area efficiency. The adaptive weights are connected to the selection line. These determines input of the multiplexers. Depending on the selection line filter inputs will be passed to the accumulator in a product form with the weights coming from the WIB of the adaptive filter. As shown in Figure 3, the selection line {h0 h1 h2 h3} are updated with the filter weights.

28

SrgnBit

Enhancea Compressor

Y[n]

Adder

Figure 1.

MUX based 4-point inner-product block

B. Proposed Design 2 – Onboard Credential (ObC) Based Model

The ObC based memory-less design for the inner product generation employs conditional adder unit, which offers lower critical path. The possible partial product to be generated for the filter order 4 can be shown as [±½ {x0 ± x1 ± x2 ± x3}], where x is the recent input samples. The sign is determined as per the weight bit value.

Sign Bit

Enhanced Compressor Adder

Figure 2:

ObC based 4-point inner-product block

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The inner product is calculated by shift accumulation in L cycles. On the Lth cycle first valid partial sum will be read for the corresponding L bit input sequences {wkl} for 0 ≤ l ≤ L–1. The conventional shift adder is replaced with enhanced compressor adder to further reduce area. In the proposed design one enhanced compressor adder is sufficient to compute the inner product instead of three conventional adders for the same purpose. IV. DA BASED STRUCTURE OF ADAPTIVE FILTER C. Adaptive Filter- Small order Distributed Arithmetic technique is adopted here to design Adaptive filter of tap size 4. Apart from the 4-point IP block, it consists of Weight Increment Block (WIB) and extra circuitry to calculate the error signal e(n) along with the Control-Word generator (t) which is given to barrel shifter. In our proposed design 1 the conventional LUT based DA table is replaced with the 2:1 MUX based logic and in design 2 OBC logic is used for computing inner product (Figure 1). The output is taken to accumulator. Enhanced compressor adder is used for accumulation. Sum and carry of size L+2 bit is then summed up to obtain the result of the filter. The difference between this obtained result and the desired signal is propagated as error to change the filter coefficients dynamically. The large size of LUT increases the area of the DA which in turn hikes the size of the filter. As shown in Figure 1, each multiplexer input is connected to the shift register output. The selection line of the mux is varying with the filter coefficients. The filter coefficients are continuously updated with the weight increment block output A = {w 31 w 21 w 11 w 0}. To meet the mux functionality properly the other input of the mux is connected to the ground. By doing the right shift operation, we can eliminate the MSB of the e(n). The control word for the barrel shifter is obtained from the magnitude part of the error signal. The convergence factor µ is calculated as one upon filter size, i.e., 1/N. it is of the order BigO(1/N). Here for N = 4 tap filter, 4 = 22 the power 2 determines the no. of shifts that is input to the barrel shifter. The weight increment block (Figure 5) has four-barrel shifter along with four adder/subtractor unit. It shifts the input values xk for k = 0,1,.....N – 1. The barrel shifter produces the incremented value that might be used for addition/subtraction with the current weight. The MSB of signal i.e., e(n) = d(n) – y(n), is used as the signcontrol bit which determines whether to perform addition/subtraction with the current value in the register. Figure 4 shows the conventional 4– point IP based Least Mean Square Adaptive filter of length 4.

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desire τ, 0 otherwise. Filter the activation mask so that the activations are equal to 1 if they are close to at least two other positive activations in a centered window of 10 activations, and to 0 otherwise. Use the CAM method on each of the positive windows of the filtered activation mask to predict what the nature of the sound is.

IV. EXPERIMENTAL RESULTS In this section it is described the experimental settings and the results obtained. AttentiveNet is trained with the same settings of EnvNet: cross-entropy criterion is used with momentum stochastic gradient descent (momentum SGD). Training is terminated after 150 epochs. It is used a learning rate of 10−2 for the first 80 epochs, 10−3 for the next 20 epochs, 10−4 for the next 20 epochs, and 10−5 for the last 30 epochs. The weights of AttentiveNet are initialized randomly. A percentage of 50% of dropout [22] is applied to the fully connected layers to prevent overfitting. In addition, batch normalization [23] is applied to all the convolutional layers to accelerate the learning. Let us now first assess the performance of attention mechanisms. The ESC10 corpus described in Sec II is used to train AttentiveNet in a supervised manner. Same increased data as in the work of [22] is used, modulo the time extracted by recording, from 1.5 seconds to 2.5 seconds. This modification is motivated by the insertion of the mechanisms of attention. By evaluating our error rate in the same way as [22] we observe that the modifications introduced through AttentiveNet do not degrade the performances of EnvNet. Indeed, AttentiveNet achieves a slightly lower error rate than EnvNet from 11.05% for EnvNet to 10.3% for AttentiveNet.

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Figure 2. Time-based localization of sound events: in the upper part, sound generated randomly with the method described in section II (in green) and the prediction made by the AttentiveNet system (in orange), in the lower part activations of neurons by class from of the GAP layer

Considering the Location system performance, the corpus generated randomly described in Sec. 2 is used to evaluate the performance of the semi-supervised localization method presented in Sec. 3. Qualitatively, it is immediate to observe in the lower part of Figure 2 that the system is capable, despite the presence of background noise, of locating the sound events on which it has been trained. The model has a precision of 78.89%, a false negative ratio of 10.97%, a ratio of true positives of 44.80%, a ratio of false positives of 11.99%, and a ratio of true positives of 32.24%. Confusion matrix in Figure 3 tells us that the system can discern and locate sounds. It is observed that the most difficult classes to predict (sneeze and clock or tick) are those containing the most silence in ESC. V.

RESULT

Service robots will have important implications for individual user experience. It is important to stress that, in the future, virtually all service robots will be connected and embedded into a bigger system (e.g. via knowledge bases and cloud- based systems). That is, in addition to their local input channels (e.g. cameras, microphones, and sensors) they can access data from a wide range of other sources including the internet, the collective organizational knowledgebase and its customer relationship management (CRM) system which contains customer background, preference and transaction data. Combined with biometrics (e.g. facial and voice recognition systems [24, 25]), a service robot will be able to identify a user and provide highly customized and personalized service on scale at negligible marginal cost [25]. Thus, to such service robots, audio pattern recognition will become highly important, and in a wide view, as they are intelligent systems, they can greatly benefit from an ability to perceive the human environment and its major actors, allowing them to better understand what is happening around them. The proposed network, AttentiveNet, is useful to this

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aim and it is capable of classifying sound events with efficiency comparable to the original EnvNet model on the ESC-10 database. It is shown that in addition to the classification, our network modification allowed us to temporally locate sound events with high accuracy. Although sufficient for a proof of concept, the database used is quite limited. We therefore see several possible extensions to this preliminary work. In order to test our approach more systematically, it is planned to evaluate recognition and location using different levels and sources of noise, and to increase the difficulty of the task by applying our approach to the ESC-50 database, containing 50 classes of sound events. Further, other datasets can be used. One of great interest is UrbanSound8K [26]: a collection of 8732 short (less than 4 seconds) excerpts of various urban sound sources (air conditioner, car horn, playing children, dog bark, drilling, engine idling, gun shot, jackhammer, siren, street music) prearranged into 10 folds. If the dataset size is too small to use for deep learning, modifications will be made to the original data for instance in the form of time-stretching or expanding the training sound samples by adding random delays and class dependent time stretching to the original recordings [21]. Silence

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Figure 6. Result from serial monitor for the condition (9)

III. EXPERIMENTAL RESULTS The developed experimental set-up is tested in real time under partial shading condition, different solar irradiance level and the results are displayed in LCD and serial monitor. Figure 5 shows that the condition V1