Birthing The Computer: From Relays To Vacuum Tubes [1st Edition] 1443897787, 9781443897785, 1443885118, 9781443885119, 1443896314, 9781443896313, 1443844969, 9781443844963

Table of contents :
Table of Contents......Page 8
List of Figures......Page 17
List of Tables......Page 20
Acknowledgement......Page 24
Introduction......Page 25
Part I: Magnetic Drum Machines......Page 26
Chapter One......Page 28
1.1 650 System Architecture......Page 29
1.1.1 Magnetic Drum Memory......Page 30
1.1.2 Arithmetic Unit......Page 32
1.1.3 IBM 650 Self-Checking......Page 33
1.1.4 IBM 650 Console......Page 35
1.1.7 IBM 653 High-Speed Core Storage Unit......Page 36
1.2 IBM 650 Instruction Set......Page 37
1.2.2 Arithmetic Instructions......Page 38
1.2.4 Branching Instructions......Page 40
1.2.6 Miscellaneous Instructions......Page 41
1.2.8 Index Accumulator Operations Instructions......Page 42
1.2.9 Floating Point Instructions......Page 43
1.2.10 IAS Instruction......Page 44
1.3 IBM 650 Programming......Page 45
1.4 Symbolic Assembly......Page 46
1.5 IBM 650 RAMAC......Page 47
1.6 IBM 650 Assessment......Page 48
Chapter Two......Page 50
2.1 LGP-30 System Architecture......Page 52
2.2 LGP-30 Instruction Set......Page 53
2.3 The Story of Mel......Page 55
2.5 The LGP-21......Page 59
2.5.1 LGP-21 System......Page 60
2.5.2 LGP-21 Memory......Page 61
2.5.3 LGP-21 Control Registers......Page 62
2.6 LGP-21 Instruction Set......Page 64
2.8 LGP-21 Assessment......Page 66
3.1 Bendix G-15......Page 69
3.2 G-15 System Configuration......Page 75
3.2.2 Registers......Page 76
3.2.4 I/O System......Page 77
3.3 G-15 Instruction Set......Page 78
3.3.2 Special Instructions......Page 79
3.4.1 Magnetic Tape MTA-2......Page 81
3.4.4 Punched Card Coupler CA-1/CA-2......Page 82
3.5.1 ALGO......Page 83
3.5.2 Intercom 1000......Page 86
3.5.3 Sample G-15 Program......Page 91
3.6 Tracking Station Application......Page 92
3.7 G-15 Assessment......Page 93
Further Reading......Page 94
Exercises for the Reader......Page 95
Part II: Core Memory Machines......Page 98
Chapter Four......Page 102
4.1 BIZMAC System Architecture......Page 106
4.2 BIZMAC I/O System......Page 108
4.4 BIZMAC Instruction Set......Page 109
4.5 BIZMAC Assessment......Page 110
Chapter Five......Page 111
5.1.1 Central Processor......Page 114
5.1.2 Program Control......Page 115
5.1.3 Storage Hierarchy......Page 116
5.1.4 Virtual Storage......Page 117
5.3 Atlas Instruction Set......Page 119
5.3.1 Floating Point Arithmetic Instructions......Page 121
5.3.2 Indexing Operations......Page 122
5.3.3 Atlas Branching Instructions......Page 123
5.3.5 Atlas Odd/Even test Instructions......Page 124
5.3.7 Atlas Instruction Example......Page 125
5.4 Atlas Programming......Page 126
5.5 The Atlas Supervisor......Page 127
5.5.1 Structure of the Atlas Supervisor......Page 128
5.5.2 Job Structure......Page 130
5.5.4 Process Control......Page 131
5.5.5 Interrupt Handling......Page 132
5.6 Atlas 2......Page 133
5.6.1 Atlas 2 Central Processor......Page 134
5.6.2 Atlas 2 Memory......Page 135
5.6.3 Magnetic Tape......Page 137
5.7 The Atlas 2 Supervisor......Page 138
5.7.1 Interrupt Routines......Page 139
5.7.2 Supervisor Extracode Routines......Page 140
5.7.4 Object Programs......Page 141
5.8 Atlas Assessment......Page 142
Chapter Six......Page 145
6.1 JOHNNIAC System Architecture......Page 147
6.2 JOHNNIAC System Configuration......Page 148
6.3.1 Conditional Transfer Orders......Page 149
6.3.2 Transfer Orders......Page 150
6.3.3 Add Orders......Page 151
6.3.4 Multiply Operations......Page 152
6.3.5 Division Orders......Page 154
6.3.7 Register Movement Orders......Page 155
6.3.8 Shift Orders......Page 156
6.3.9 Input/Output Orders......Page 157
6.3.10 Drum Orders......Page 158
6.3.12 Control Orders......Page 159
6.4 JOHNNIAC Operation......Page 160
6.5 JOSS......Page 161
6.5.1 JOSS Structure......Page 162
6.5.2 JOSS Remote Console......Page 163
6.5.3 JOSS Implementation......Page 164
6.6 JOHNNIAC Assessment......Page 165
Further Reading......Page 166
Exercises for the Reader......Page 168
Part III: Transistor Machines......Page 170
Chapter Seven......Page 172
7.1 Solid State Computer Architecture......Page 173
7.1.1 SSC Central Processor......Page 177
7.1.2 Magnetic Drum......Page 178
7.1.3 Operator’s Console......Page 179
7.2 SSC80/SSC90 Instructions......Page 180
7.2.3 Transfer Instructions......Page 181
7.2.5 Comparison Instructions......Page 182
7.2.8 Card Reader Control Instructions......Page 183
7.3 SSC Peripherals......Page 184
7.4.1 FLOW-MATIC......Page 185
7.5 SSC Assessment......Page 186
Chapter Eight......Page 187
8.3 Instruction Format......Page 188
8.3.2 Type II Instructions......Page 189
8.5 UNIVAC 418-II......Page 190
8.6 UNIVAC 418-III......Page 191
8.6.1 UNIVAC 418-III System Architecture......Page 192
8.6.2 Command/Arithmetic Unit (CAU)......Page 193
8.6.3 Main Storage......Page 194
8.6.4 I/O Modules (IOMs)......Page 195
8.6.5 Magnetic Drums......Page 198
8.6.7 Communications Systems......Page 199
8.7 UNIVAC 418 System Software......Page 200
8.7.1 RTOS Executive......Page 201
8.7.2 Programming Languages......Page 206
8.7.3 System Applications......Page 207
8.8 UNIVAC 418 Assessment......Page 208
Chapter Nine......Page 210
9.1 UNIVAC 494......Page 212
9.1 System Architecture......Page 213
9.1.1 Central Processor......Page 214
9.1.3 I/O System......Page 216
9.1.4 Communications Handling......Page 218
9.1.5 Transfer Switch......Page 219
9.2 Instruction Set......Page 220
9.2.1 Shift Instructions......Page 222
9.2.2 UNIVAC 494 Transfer Instructions......Page 224
9.2.3 Arithmetic Instructions......Page 226
9.2.4 Logical Instructions......Page 228
9.2.5 Comparison Instructions......Page 229
9.2.6 Jump Instructions......Page 230
9.2.7 Sequence Modifying Instructions......Page 231
9.2.8 I/O Instructions......Page 232
9.3 Peripherals......Page 233
9.3.1 Magnetic Drums......Page 234
9.3.4 High-Speed Printer Subsystem......Page 235
9.4.2 Input Cooperative......Page 236
9.5 UNIVAC 490/494 Assessment......Page 237
Chapter Ten......Page 239
10.1.1 TX-0 Registers......Page 242
10.2 TX-0 Instructions......Page 243
10.2.1 TX-0 Operate Instructions......Page 244
10.2.2 Combining Instructions......Page 245
10.2.3 Modified Instruction Set......Page 247
10.3 Operating Modes......Page 248
10.5 FLIT......Page 249
10.7 TX-2......Page 250
10.7.1 TX-2 System Architecture......Page 251
10.8 TX-0 and TX-2 Assessment......Page 252
Chapter Eleven......Page 254
11.1 Philco 1000......Page 255
11.1.1 Philco 1000 Central Processor......Page 256
11.1.3 Instruction Set......Page 257
11.2 Philco TRANSAC S-2000......Page 258
11.3 TRANSAC S-2000 System Architecture......Page 263
11.3.1 Secondary Memory......Page 264
11.4 TRANSAC S-2000 Instruction Set......Page 265
11.4.3 Algorithm Control......Page 266
11.5 Philco 212......Page 267
11.5.2 Instruction Unit......Page 270
11.5.3 Index Unit......Page 271
11.5.4 Arithmetic Unit......Page 272
11.5.6 I/O Subsystem......Page 273
11.5.7 Real-Time System......Page 274
11.5.8 Philco 212 Instruction Set......Page 275
11.6 Operating System 32KSYS......Page 290
11.7 TRANSAC S-2000 Software......Page 291
11.8 Philco 2400 Input/Output System......Page 294
11.8.1 Philco 2400 System Architecture......Page 295
11.8.2 Executive Control......Page 296
11.8.3 Program Control......Page 297
11.8.5 Main Memory......Page 298
11.8.6 Operator Control Panel......Page 299
11.8.8 I/O Operations......Page 300
11.8.9 Internal Operations......Page 304
11.8.10 Arithmetic Operations......Page 309
11.9 Assessment of the Philco Machines......Page 312
12.1 Bendix G-20 System Architecture......Page 314
12.1.2 Registers......Page 317
12.1.4 Interrupts......Page 318
12.2.1 Add/Subtract Operations and Tests......Page 319
12.2.2 Logic Operations and Tests......Page 321
12.2.3 Repeated Commands......Page 322
12.2.5 Storage Operations......Page 323
12.2.7 Control Operations......Page 324
12.2.8 I/O Operations......Page 325
12.2.9 Bus Register Operations......Page 326
12.4 G-21 Dual Processor......Page 327
12.5 Bendix G-20 Assessment......Page 328
Chapter Thirteen......Page 329
13.1 PB250 System Architecture......Page 331
13.1.1 Central Processor......Page 332
13.1.2 Main Memory......Page 333
13.1.3 Flexowriter......Page 334
13.1.5 HYCOMP 250......Page 335
13.2 PB250 Commands......Page 336
13.2.1 Class I Commands......Page 337
13.2.2 Class II Commands......Page 339
13.2.4 Class IV Commands......Page 341
13.2.5 Sequence Tag......Page 342
13.3 Packard Bell 440......Page 343
13.3.1 PB440 System Architecture......Page 346
13.3.2 Memory System......Page 347
13.3.3 I/O System......Page 348
13.3.4 PB440 Programming......Page 349
13.5 Packard Bell Assessment......Page 350
Further Reading......Page 352
Exercises for the Reader......Page 353
Appendix A: Glossary......Page 356
References......Page 357
Index......Page 365

Citation preview

Birthing the Computer

Birthing the Computer: From Drums to Cores By

Stephen H. Kaisler

Birthing the Computer: From Drums to Cores By Stephen H. Kaisler This book first published 2017 Cambridge Scholars Publishing Lady Stephenson Library, Newcastle upon Tyne, NE6 2PA, UK British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library Copyright © 2017 by Stephen H. Kaisler All rights for this book reserved. No part of this book may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording or otherwise, without the prior permission of the copyright owner. ISBN (10): 1-4438-8511-8 ISBN (13): 978-1-4438-8511-9

This volume is dedicated to my mother, Dolores, and to my wife, Chryl, who have supported this endeavor – each in her own way. Their forbearance allowed me to work on the multiple volumes in this series concurrently. My children, Rebecca and John, both put up with dad’s passion for documenting historical computing machines. And, the family cats – Annie, now deceased, and Izzy, Scooby and Tatiana – have all taken turns at sentry duty lying behind my keyboards and ensuring that I worked diligently.

TABLE OF CONTENTS

List of Figures........................................................................................... xvi List of Tables ............................................................................................ xix Acknowledgement .................................................................................. xxiii Introduction ............................................................................................ xxiv Part I: Magnetic Drum Machines ............................................................ 1 Chapter One ................................................................................................. 3 IBM 650 Magnetic Drum Calculator 1.1 650 System Architecture .................................................................. 4 1.1.1 Magnetic Drum Memory ......................................................... 5 1.1.2 Arithmetic Unit ....................................................................... 7 1.1.3 IBM 650 Self-Checking .......................................................... 8 1.1.4 IBM 650 Console .................................................................. 10 1.1.5 Magnetic Tape Units ............................................................. 11 1.1.6 IBM 652 Control Unit ........................................................... 11 1.1.7 IBM 653 High-Speed Core Storage Unit .............................. 11 1.1.8 IBM 407 Accounting Machine .............................................. 12 1.2 IBM 650 Instruction Set................................................................. 12 1.2.1 I/O Instructions ...................................................................... 13 1.2.2 Arithmetic Instructions .......................................................... 13 1.2.3 Shifting Instructions .............................................................. 15 1.2.4 Branching Instructions .......................................................... 15 1.2.5 Table Lookup Instruction ...................................................... 16 1.2.6 Miscellaneous Instructions .................................................... 16 1.2.7 Index Accumulator Instructions ............................................ 17 1.2.8 Index Accumulator Operations Instructions .......................... 17 1.2.9 Floating Point Instructions .................................................... 18 1.2.10 IAS Instruction .................................................................... 19 1.3 IBM 650 Programming .................................................................. 20 1.4 Symbolic Assembly ....................................................................... 21 1.5 IBM 650 RAMAC ......................................................................... 22 1.6 IBM 650 Assessment ..................................................................... 23

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Chapter Two .............................................................................................. 25 Royal McBee/Librascope Machines 2.1 LGP-30 System Architecture ......................................................... 27 2.2 LGP-30 Instruction Set .................................................................. 28 2.3 The Story of Mel ............................................................................ 30 2.4 LGP-30 Assessment ....................................................................... 34 2.5 The LGP-21 ................................................................................... 34 2.5.1 LGP-21 System ..................................................................... 35 2.5.2 LGP-21 Memory ................................................................... 36 2.5.3 LGP-21 Control Registers ..................................................... 37 2.6 LGP-21 Instruction Set .................................................................. 39 2.7 Timing and Optimization ............................................................... 41 2.8 LGP-21 Assessment ....................................................................... 41 Chapter Three ............................................................................................ 44 Bendix G Machines 3.1 Bendix G-15 ................................................................................... 44 3.2 G-15 System Configuration ........................................................... 50 3.2.1 Short Lines ............................................................................ 51 3.2.2 Registers ................................................................................ 51 3.2.3 Command Lines .................................................................... 52 3.2.4 I/O System ............................................................................. 52 3.3 G-15 Instruction Set ....................................................................... 53 3.3.1 Special Values for S/D Fields................................................ 54 3.3.2 Special Instructions ............................................................... 54 3.4 Peripheral Devices ......................................................................... 56 3.4.1 Magnetic Tape MTA-2 .......................................................... 56 3.4.2 Digital Differential Analyzer DA-1....................................... 57 3.4.3 Graph Plotter PA-3 ................................................................ 57 3.4.4 Punched Card Coupler CA-1/CA-2 ....................................... 57 3.4.5 Universal Code Accessory AN-1 .......................................... 58 3.5 Programming Languages ............................................................... 58 3.5.1 ALGO .................................................................................... 58 3.5.2 Intercom 1000 ....................................................................... 61 3.5.3 Sample G-15 Program ........................................................... 66 3.6 Tracking Station Application ......................................................... 67 3.7 G-15 Assessment ........................................................................... 68 Further Reading ......................................................................................... 69 Exercises for the Reader ............................................................................ 70

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Part II: Core Memory Machines ............................................................ 73 Chapter Four .............................................................................................. 77 RCA BIZMAC I/II 4.1 BIZMAC System Architecture ...................................................... 81 4.2 BIZMAC I/O System ..................................................................... 83 4.3 Data Representation ....................................................................... 84 4.4 BIZMAC Instruction Set................................................................ 84 4.5 BIZMAC Assessment .................................................................... 85 Chapter Five .............................................................................................. 86 Ferranti Atlas 5.1 Atlas System Architecture ............................................................. 89 5.1.1 Central Processor................................................................... 89 5.1.2 Program Control .................................................................... 90 5.1.3 Storage Hierarchy .................................................................. 91 5.1.4 Virtual Storage ...................................................................... 92 5.2 Peripherals ..................................................................................... 94 5.3 Atlas Instruction Set....................................................................... 94 5.3.1 Floating Point Arithmetic Instructions .................................. 96 5.3.2 Indexing Operations .............................................................. 97 5.3.3 Atlas Branching Instructions ................................................. 98 5.3.4 Atlas Shifting Instructions ..................................................... 99 5.3.5 Atlas Odd/Even test Instructions ........................................... 99 5.3.6 Atlas B-test Register Instructions ........................................ 100 5.3.7 Atlas Instruction Example ................................................... 100 5.4 Atlas Programming ...................................................................... 101 5.5 The Atlas Supervisor.................................................................... 102 5.5.1 Structure of the Atlas Supervisor ........................................ 103 5.5.2 Job Structure........................................................................ 105 5.5.3 Programs ............................................................................. 106 5.5.4 Process Control ................................................................... 106 5.5.5 Interrupt Handling ............................................................... 107 5.5.6 Atlas Supervisor Assessment .............................................. 108 5.6 Atlas 2 .......................................................................................... 108 5.6.1 Atlas 2 Central Processor .................................................... 109 5.6.2 Atlas 2 Memory ................................................................... 110 5.6.3 Magnetic Tape ..................................................................... 112 5.6.4 Magnetic Disc Files ............................................................. 113 5.7 The Atlas 2 Supervisor................................................................. 113 5.7.1 Interrupt Routines ................................................................ 114

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5.7.2 Supervisor Extracode Routines ........................................... 115 5.7.3 Extended Interrupt Routines ................................................ 116 5.7.4 Object Programs .................................................................. 116 5.7.5 Error Conditions .................................................................. 117 5.8 Atlas Assessment ......................................................................... 117 Chapter Six .............................................................................................. 120 JOHNNIAC 6.1 JOHNNIAC System Architecture ................................................ 122 6.2 JOHNNIAC System Configuration ............................................. 123 6.3 JOHNNIAC Instruction Set ......................................................... 124 6.3.1 Conditional Transfer Orders ................................................ 124 6.3.2 Transfer Orders ................................................................... 125 6.3.3 Add Orders .......................................................................... 126 6.3.4 Multiply Operations ............................................................ 127 6.3.5 Division Orders ................................................................... 129 6.3.6 Store Orders......................................................................... 130 6.3.7 Register Movement Orders ................................................. 130 6.3.8 Shift Orders ......................................................................... 131 6.3.9 Input/Output Orders ............................................................ 132 6.3.10 Drum Orders...................................................................... 133 6.3.11 Logical Product Orders ..................................................... 134 6.3.12 Control Orders ................................................................... 134 6.4 JOHNNIAC Operation................................................................. 135 6.5 JOSS ............................................................................................ 136 6.5.1 JOSS Structure .................................................................... 137 6.5.2 JOSS Remote Console......................................................... 138 6.5.3 JOSS Implementation .......................................................... 139 6.6 JOHNNIAC Assessment .............................................................. 140 Further Reading ....................................................................................... 141 Exercises for the Reader .......................................................................... 143 Part III: Transistor Machines .............................................................. 145 Chapter Seven.......................................................................................... 147 UNIVAC Solid State Computer 7.1 Solid State Computer Architecture .............................................. 148 7.1.1 SSC Central Processor......................................................... 152 7.1.2 Magnetic Drum ................................................................... 153

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7.1.3 Operator’s Console .............................................................. 154 7.2 SSC80/SSC90 Instructions .......................................................... 155 7.2.1 Executing an Instruction ...................................................... 156 7.2.2 Arithmetic Instructions ........................................................ 156 7.2.3 Transfer Instructions............................................................ 156 7.2.4 Logical and Shift Instructions ............................................. 157 7.2.5 Comparison Instructions...................................................... 157 7.2.6 Translate Instructions .......................................................... 158 7.2.7 SS80 Printer Control Instructions........................................ 158 7.2.8 Card Reader Control Instructions ........................................ 158 7.3 SSC Peripherals ........................................................................... 159 7.4 Solid State Computer System Software ....................................... 160 7.4.1 FLOW-MATIC ................................................................... 160 7.5 SSC Assessment .......................................................................... 161 Chapter Eight ........................................................................................... 162 UNIVAC 418 8.1 UNIVAC 418-I ............................................................................ 163 8.2 UNIVAC 418 System Architecture ............................................. 163 8.3 Instruction Format ........................................................................ 163 8.3.1 Type I Instructions .............................................................. 164 8.3.2 Type II Instructions ............................................................. 164 8.3.3 Type III Instructions ............................................................ 165 8.4 System Software .......................................................................... 165 8.5 UNIVAC 418-II ........................................................................... 165 8.6 UNIVAC 418-III.......................................................................... 166 8.6.1 UNIVAC 418-III System Architecture................................ 167 8.6.2 Command/Arithmetic Unit (CAU) ...................................... 168 8.6.3 Main Storage ....................................................................... 169 8.6.4 I/O Modules (IOMs)............................................................ 170 8.6.5 Magnetic Drums .................................................................. 173 8.6.6 Attached Processors ............................................................ 174 8.6.7 Communications Systems ................................................... 174 8.6.8 Unit Record Peripherals ...................................................... 175 8.7 UNIVAC 418 System Software ................................................... 175 8.7.1 RTOS Executive .................................................................. 176 8.7.2 Programming Languages ..................................................... 181 8.7.3 System Applications ............................................................ 182 8.8 UNIVAC 418-III Application ...................................................... 183 8.8 UNIVAC 418 Assessment ........................................................... 183

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Chapter Nine............................................................................................ 185 UNIVAC 490/494 9.1 UNIVAC 494 ............................................................................... 187 9.1 System Architecture ..................................................................... 188 9.1.1 Central Processor................................................................. 189 9.1.2 Memory ............................................................................... 191 9.1.3 I/O System ........................................................................... 191 9.1.4 Communications Handling .................................................. 193 9.1.5 Transfer Switch ................................................................... 194 9.2 Instruction Set .............................................................................. 195 9.2.1 Shift Instructions ................................................................. 197 9.2.2 UNIVAC 494 Transfer Instructions .................................... 199 9.2.3 Arithmetic Instructions ........................................................ 201 9.3.4 Logical Instructions ............................................................. 203 9.3.5 Comparison Instructions...................................................... 204 9.3.6 Jump Instructions ................................................................ 205 9.3.7 Sequence Modifying Instructions ........................................ 206 9.3.8 I/O Instructions .................................................................... 207 9.3 Peripherals ................................................................................... 208 9.3.1 Magnetic Drums .................................................................. 209 9.3.2 Magnetic Tape Subsystem................................................... 210 9.3.3 Operator’s Console .............................................................. 210 9.3.4 High-Speed Printer Subsystem ............................................ 210 9.4 UNIVAC 490/494 System Software ............................................ 211 9.4.1 Primary Input Stream .......................................................... 211 9.4.2 Input Cooperative ................................................................ 211 9.4.3 Programming Languages ..................................................... 212 9.5 UNIVAC 490/494 Assessment .................................................... 212 Chapter Ten ............................................................................................. 214 MIT’s TX-0 10.1 TX-0 System Architecture ......................................................... 217 10.1.1 TX-0 Registers .................................................................. 217 10.1.2 Toggle Switch Storage ...................................................... 218 10.1.3 Main Memory .................................................................... 218 10.2 TX-0 Instructions ....................................................................... 218 10.2.1 TX-0 Operate Instructions ................................................. 219 10.2.2 Combining Instructions ..................................................... 220 10.2.3 Modified Instruction Set .................................................... 222 10.3 Operating Modes........................................................................ 223 10.4 TX-0 I/O Equipment .................................................................. 224

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10.5 FLIT ........................................................................................... 224 10.6 TX-1 ........................................................................................... 225 10.7 TX-2 ........................................................................................... 225 10.7.1 TX-2 System Architecture................................................. 226 10.8 TX-0 and TX-2 Assessment ....................................................... 227 Chapter Eleven ........................................................................................ 229 Philco Ford computers 11.1 Philco 1000 ................................................................................ 230 11.1.1 Philco 1000 Central Processor........................................... 231 11.1.2 Philco 1000 System Architecture ...................................... 232 11.1.3 Instruction Set ................................................................... 232 11.2 Philco TRANSAC S-2000 ......................................................... 233 11.3 TRANSAC S-2000 System Architecture ................................... 238 11.3.1 Secondary Memory ........................................................... 239 11.4 TRANSAC S-2000 Instruction Set ............................................ 240 11.4.1 Program Control ................................................................ 241 11.4.2 Instruction Control ............................................................ 241 11.4.3 Algorithm Control ............................................................. 241 11.4.4 Floating Point Control ....................................................... 242 11.4.5 Memory Cycle Control ...................................................... 242 11.5 Philco 212 .................................................................................. 242 11.5.1 Control Unit....................................................................... 245 11.5.2 Instruction Unit ................................................................. 245 11.5.3 Index Unit.......................................................................... 246 11.5.4 Arithmetic Unit ................................................................. 247 11.5.5 Store Unit .......................................................................... 248 11.5.6 I/O Subsystem ................................................................... 248 11.5.7 Real-Time System ............................................................. 249 11.5.8 Philco 212 Instruction Set ................................................. 250 11.6 Operating System 32KSYS........................................................ 265 11.7 TRANSAC S-2000 Software ..................................................... 266 11.8 Philco 2400 Input/Output System .............................................. 269 11.8.1 Philco 2400 System Architecture ...................................... 270 11.8.2 Executive Control .............................................................. 271 11.8.3 Program Control ................................................................ 272 11.8.4 Arithmetic Element ........................................................... 273 11.8.5 Main Memory .................................................................... 273 11.8.6 Operator Control Panel ...................................................... 274 11.8.7 Philco 2400 Instruction Set ............................................... 275 11.8.8 I/O Operations ................................................................... 275

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11.8.9 Internal Operations ............................................................ 279 11.8.10 Arithmetic Operations ..................................................... 284 11.8.11 Philco 2400 I/O Devices.................................................. 287 11.9 Assessment of the Philco Machines ........................................... 287 Chapter Twelve ....................................................................................... 289 Bendix G-20 12.1 Bendix G-20 System Architecture ............................................. 289 12.1.1 Arithmetic Unit ................................................................. 292 12.1.2 Registers ............................................................................ 292 12.1.3 Core Memory .................................................................... 293 12.1.4 Interrupts ........................................................................... 293 12.2 Instruction Set Architecture ....................................................... 294 12.2.1 Add/Subtract Operations and Tests ................................... 294 12.2.2 Logic Operations and Tests ............................................... 296 12.2.3 Repeated Commands ......................................................... 297 12.2.4 Multiply/Divide ................................................................. 298 12.2.5 Storage Operations ............................................................ 298 12.2.6 Index Operations ............................................................... 299 12.2.7 Control Operations ............................................................ 299 12.2.8 I/O Operations ................................................................... 300 12.2.9 Bus Register Operations .................................................... 301 12.3 I/O System ................................................................................. 302 12.4 G-21 Dual Processor .................................................................. 302 12.4.1 G-21 Software ................................................................... 303 12.5 Bendix G-20 Assessment ........................................................... 303 Chapter Thirteen ...................................................................................... 304 Packard Bell 13.1 PB250 System Architecture ....................................................... 306 13.1.1 Central Processor............................................................... 307 13.1.2 Main Memory .................................................................... 308 13.1.3 Flexowriter ........................................................................ 309 13.1.4 Other I/O Devices.............................................................. 310 13.1.5 HYCOMP 250 ................................................................... 310 13.2 PB250 Commands ..................................................................... 311 13.2.1 Class I Commands ............................................................. 312 13.2.2 Class II Commands ........................................................... 314 13.2.3 Class III Commands .......................................................... 316 13.2.4 Class IV Commands .......................................................... 316 13.2.5 Sequence Tag .................................................................... 317

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13.3 Packard Bell 440 ........................................................................ 318 13.3.1 PB440 System Architecture .............................................. 321 13.3.2 Memory System ................................................................ 322 13.3.3 I/O System ......................................................................... 323 13.3.4 PB440 Programming ......................................................... 324 13.4 PB440 Micro Instruction Format ............................................... 325 13.5 Packard Bell Assessment ........................................................... 325 Further Reading ....................................................................................... 327 Exercises for the Reader .......................................................................... 328 Appendix A: Glossary ............................................................................. 331 References ............................................................................................... 332 Index ........................................................................................................ 340

LIST OF FIGURES

1-1. IBM 650 Magnetic Drum Computer 1-2. IBM 650 System Architecture 1-3. IBM 650 Magnetic Drum Assembly 1-4. IBM 650 Magnetic Drum Arrangement 1-5. IBM 650 Operators Console 1-6. IBM 650 Instruction Format 1-7. SOAP II Coding Form 2-1. Royal McBee LGP-30 2-2. LGP-30 Instruction Format 2-3. LGP-30 Computer System 2-4. General Precision LGP-21 Computer System 2-5. LGP-21 Brochure 2-6. LGP-21 Instruction Format 2-7(a). Front of Optimum Address Locator 2-7(b) Rear of Optimum Address Locator 3-1. Bendix G-15 Computer System Advertisement 3-2. Bendix G-15 Ad (Datamation 11-60) 3-3. Bendix G-15 Advertisement 3-4. Bendix G-15 installed at Naval Supersonic Laboratory at MIT 3-5. Bendix G-15 with Operator’s Console 3-6. Bendix G-15 Instruction Format 3-7. Simple ALGO Program 3-8. Bendix G-15 ALGO Programming Language 4-1. RCA BIZMAC Used For Military Application 4-2. RCA BIZMAC at U.S. Army Tank Automotive Command 4-3. RCA BIZMAC II 4-4. BIZMAC System Architecture 4-5. RCA BIZMAC Instruction Format 5-1. Manchester University – Atlas 1 Input Area 5-2. The Ferranti Atlas Operator Console 5-3. Atlas CPU Architecture

Birthing the Computer: From Drums to Cores

5-4. Ferranti Atlas One-level Store Concept 5-5. Atlas Instruction Format 5-6. Central Store Address Structure 5-7. Sample Atlas Autocode Program 5-8. Structure of the Atlas Supervisor 5-9. Titan Computer 6-1. JOHNNIAC 6-2. JOHNNIAC System Architecture 7-1. UNIVAC Solid State Computer 7-2. Univac Solid State Computer Cabinet 7-3. UNIVAC SSC90 Voltage Monitoring Panel 7-4. UNIVAC SSC90 System Console 7-5. UNIVAC SS90 Circuit Board with Ferractors 7-6. SSC90 System Architecture 7-7. UNIVAC SSC90 Operators Console 7-8. SSC80/SSC90 Instruction Format 7-9. Jan Lindeboom at the UNIVAC SSC90 Console 8-1(a). UNIVAC 418 Instruction Format I/II 8-1(b). UNIVAC 418 Instruction Format III 8-2. UNIVAC 418-II System 12-1. Bendix G-20 8-3. UNIVAC 418-III System Configuration 8-4. UNIVAC 418 Interrupt Table Pointer Word Format 9-1. UNIVAC 490 9-2. UNIVAC 490 System 9-3. UNIVAC 494 System 9-4. UNIVAC 494 System Architecture 9-5. UNIVAC 404 BCW Format 9-6. UNIVAC 494 Cascade System 9-7. UNIVAC 494 Instruction Format 10-1. TX-0 Computer Room 10-2. TX-0 at MIT 10-3. TX-2 System Architecture 11-1. Philco 1000 Central Processing Unit Structure 11-2. Transac S-1000 Instruction Format 11-3. Philco S-2000 Advertisement

xvii

xviii

List of Figures

11-4. Philco Transac S-2000 Advertisement 11-5. Philco 210 System 11-6. Philco S-2000 Computer System 11-7. TRANSAC 2000 Operator Control Panel 11-8. TRANSAC S-2000 Repeat Register Format 11-9. TRANSAC S-2000 Instruction Address Format 11-10. Philco 212 Advertisement 11-11. Philco 212 System Configuration 11-12. Philco 212 Central Processor 11-13. TIO Data Format 11-14. Philco 212 Real-Time Order Format 11-15. Philco 212 Instruction Format 11-16. Philco 212 Address Field Format 11-17. DR instruction for Repeating Four Instructions 11-18. ALTAC Translation Process 11-19. Philco ALTAC Advertisement 11-20. Philco 2400 System Architecture 11-21. Philco 2400 Operator Control Panel 11-22. Philco 2400 Instruction Format 12-2. Bendix G-20 System Architecture 12-3. Bendix G-20 Computer System Advertisement 12-4 Bendix G-20 Instruction Format 12-5. Repeat Command Instruction Format 12-6. Block Transfer Instruction Format 12-7. Bendix G-20 Bus Register Layouts 13-1. Packard Bell 250 13-2. Packard Bell 250 Front Panel 13-3. Packard Bell 250 System Architecture 13-4. PB250 Machine Sector Counter 13-5. Flexowriter Console 13-6. Packard Bell 250 Command Format 13-7. Packard Bell 440 13-8. PB440 Operator Console 13-9. PB440 Advertisement 13-10. Packard-Bell 440 System Architecture 13-11. Packard Bell 440 Memory System 13-12. Use of a Memory Interchange Unit

LIST OF TABLES

1-1 IBM 650 – Basic Characteristics 1-2. Self-Checking Techniques 1-3. IBM 650 I/O Instructions 1-4. IBM 650 Arithmetic Instructions 1-5. IBM 650 Shifting Instructions 1-6. IBM 650 Branching Instructions 1-7. IBM 650 Table Lookup Instruction 1-8 IBM 650 Miscellaneous Instructions 1-9. IBM 650 Index Accumulator Instructions 1-10. IBM 650 Index Accumulator Instructions 1-11. IBM 650 Floating Point Instructions 1-12. IBM 650 IAS Timing Ring Instruction 1-13. IBM 650 IAS Multiple Word Transfer Instructions 2-1. LGP-30 Characteristics 2-2. LGP-30 Instruction Set 2-3. LGP-21 Characteristics 2-4. LGP-21 Instruction Set 3-1. Bendix G-15 Characteristics 3-2. Register Roles in Multiplication and Division 3-3. Special Values for S/D Fields 3-4. Special Instructions 3-5. Intercom 1000 Commands 3-6. Sample G-15 Intercom 1000 Program to add Two Numbers 3-7. Sample G-15 Intercom 1000 Program to compute (a2 – bc)/d 4-1. RCA BIZMAC Basic Characteristics 5-1. Atlas – Basic Characteristics 5-2. Floating Point Arithmetic Instructions 6-1. JOHNNIAC Characteristics (Weik 1961) 6-2. Conditional Transfer Orders 6-3. Transfer Orders

xx

List of Tables

6-4. Add Operations 6-5. Multiply Operations 6-6. Division Operations 6-7. Store and Substitute Operations 6-8. Register Movement Operations 6-9. Shift Operations 6-10. Input/Output Operations 6-11. Drum Operations 6-12. Logical Product Operations 6-13. Control Operations 6-14. Sample JOSS Program 7-1. Solid State 80 – Basic Characteristics 7-2. SS80 Arithmetic Instructions 7-3. SS80 Transfer Instructions 7-4. SS80 Logical and Shift Instructions 7-5. SS80 Comparison Instructions 7-6. SS80 Translate Instructions 7-7. SS80 Print Instructions 7-8. SS80 Card Reader Instructions 8-1. UNIVAC 418 Basic Characteristics 8-2. UNIVAC 418-III – Basic Characteristics 8-3. Magnetic Drum Systems 8-4. Mass Storage Systems 9-1. UNIVAC 490/494 Basic Characteristics 9-2. UNIVAC 490/494 Registers 9-3. UNIVAC 494 I/O Registers 9-4. Special Interpretation of j Designators for Selected Instructions 9-5. UNIVAC 494 Shift Instructions 9-6. UNIVAC 494 Transfer Instructions 9-7. k Field Modification to Enter Bj 9-8. UNIVAC 494 Integer Arithmetic Instructions 9-9. UNIVAC 494 Floating Point Arithmetic Instructions 9-10. UNIVAC 494 Decimal Arithmetic Instructions 9-11. Decimal Test Conditions 9-12. UNIVAC 494 Logical Instructions 9-13. UNIVAC 494 Comparison Instructions 9-14. UNIVAC 494 Jump Instructions

Birthing the Computer: From Drums to Cores

9-15. UNIVAC 494 Jump Instructions 9-16. UNIVAC 494 I/O Instructions 9-17. Magnetic Drum Systems 9-18. Mass Storage Systems 9-19. UNISERVO Magnetic Tape Subsystems 10-1. TX-0 Basic Characteristics 10-2. TX-0 Machine Registers 10-3. Operate Instructions 10-4. Useful Combinations of Operate Commands 10-5. Operating Modes 10-6. TX-2 – Basic Characteristics 11-1. Philco 1000 Basic Characteristics 11-2. TRANSAC S-2000 Basic Characteristics 11-3. TRANSAC S-2000 Processor Registers 11-4. Effective Address Calculation 11-5. Philco 212 Addressable Registers 11-6. Control Bits for Indirect Addressing 11-7. Philco 212 ADD Instructions 11-8. Philco 212 SUBTRACT Instructions 11-9. Philco 212 MULTIPLY Instructions 11-10. Philco 212 DIVIDE Instructions 11-11. Philco 212 CLEAR Instructions 11-12. Philco 212 TRANSFER Instructions 11-13. Philco 212 JUMP Instructions 11-14. Philco 212 SHIFT Instructions 11-15. Philco 212 INDEX REGISTER Instructions 11-16. Philco 212 EXTRACT Instructions 11-17. Philco 212 LOGIC Instructions 11-18. Philco 212 SPECIAL Instructions 11-19. Modifier Interpretation 11-20. Magnetic Tape drive Assignments for 32KSYS 11-21. Philco 2400 – Basic Characteristics 11-22. PCU Registers 11-23. Philco 2400 Operator Control Panel Elements 11-24. Feed/PUNCH Instructions 11-25. MOVE Instructions 11-26. Card Punch Instructions 11-27. Character Selection Instructions 11-28. Printer Instructions

xxi

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List of Tables

11-29. Magnetic Tape Instructions 11-30. Setting and Moving Register Values 11-31. Moving and Editing Data Instructions 11-32. Code Translation Instructions 11-33. Field Comparison Instructions 11-34. Register Save Instructions 11-35. Register Test Instructions 11-36. Jump Instructions 11-37. Increment and Decrement Instructions 11-38. Arithmetic Operations 11-39. Philco 2400 Conversion Instructions 11-40. Philco 2400 Shift Instructions 11-41. Philco 2400 Logical Instructions

12-1. Bendix G-20 – Basic Characteristics 12-2. Bendix G-20 Addressing Modes 12-3. Add/Subtract Operations 12-4. Arithmetic Test Operations 12-5. Logic Operations 12-6. Logic Tests 12-7. Multiply/Divide 12-8. Storage Operations 12-9. Index Operations 12-10. Transfer Operations 12-11. I/O Operations 12-12. Block Transfer Operations 12-13. Bendix G-20 Bus Registers 12-14. Bus Register Operations 13-1. Packard Bell 250 – Basic Characteristics 13-2. PB250 Class I Commands 13-3. PB250 Class II Commands 13-4. PB250 Class III Commands 13-5. PB250 Class IV Commands 13-6. Packard Bell 440 – Basic Characteristic

ACKNOWLEDGEMENT

I wish to acknowledge the staff of Cambridge Scholars Publishing, particularly Sam Baker, the commissioning editor for the series; Ms. Victoria Carruthers, the Author Liaison, and Ms. Sophie Edminson, Design and Coordinator, for shepherding this book from initial manuscript through to publication. I want to acknowledge the diligent and excellent work of my proofreaders, Mrs. Rebecca Williams (daughter) and Mr. Eric Ward, Scouting colleagues. They have made the book immeasurably better through their efforts. Thank you all for help me to make this book a successful publication!

.

INTRODUCTION

This volume is the second of a multiple volume set on Historical Computing Machines. We continue with the evolution of computing systems from two perspectives. First, a variety of memory systems evolved to provide larger, faster memories. As a consequence, computing machines became more capable and evolved through enhanced functionality. We also see the beginnings of I/O systems which allowed users to interact with the system, and to have persistent storage that was somewhat easier to use for their programs and data.

PART I MAGNETIC DRUM MACHINES

Pre-core memory machines relied on a variety of devices to provide working memory, including magnetic drums, mercury delay lines, and plated wires. Drum memories were one of the earliest mass storage devices attached to computing machines. Several variations will be addressed in coming chapters as auxiliary storage devices after magnetic disks were developed. Magnetic drums were rotating cylinders whose exterior surfaces were coated with a ferromagnetic material. In most early systems, a linear array of read/write heads was positioned along the length of the drum to store and retrieve bits of data by magnetizing positions on the drum’s surface. Gustav Tauschek, an Austrian national, invented the first magnetic drum in 1932. Early in his career, Tauschek developed several punched card accounting machines. In 1932, he received a US Patent, No. 1880523, entitled “Setting Device for Calculating Machines and the Like”, which clearly depicts a rotating drum on which data could be recorded. The patent was received for the magnetic drum. His device could record about 500,000 bits or about 62.5 Kbytes. The idea of the magnetic drum was further elaborated at the Institute for Advanced Study (IAS) in Princeton, New Jersey in 1946 as a way to provide additional, easily accessible storage for the IAS machine. In the early 1950s, engineers at Engineering Research Associates (ERA) designed and developed a magnetic drum for the main memory of the ERA 1101 (Hill 1950, ERA UNK). Other manufacturers also designed and used their own magnetic drums in ‘one-off’ designs until the mid-1950s. By then, magnetic drums came into wide use as computer manufacturers developed product lines that needed highly reliable magnetic drum subsystems for main and auxiliary memories for their computers. Reliable, low-cost magnetic drums of varying capacities enabled the production of lower-cost reliable machines. In its most basic form, a magnetic drum was a cylinder coated with a ferromagnetic material and mounted either vertically or horizontally on a spinning shaft. Most magnetic drums had one head per track. The heads

2

Part I

did not move. The controller selected the head for the track where the data was stored and waited for the data to come under the head. However, the Univac FASTRAND drums had multiple moving heads which reduced cost but increased latency to access and transfer data. As wait time was due solely to the rotational latency of the drum, a number of sophisticated schemes were developed for early machines to optimize the placement of data on the drum. Knowing the time it took to load an instruction or data item from a particular location on the drum, the programmer could place the next sequential data item just at the point where the previous read ended and a new read could begin. It is interesting to note that the concept of a drum is retained in today’s UNIX and variant systems. /dev/drum is used to refer to the default virtual (swap) device. (Gloutnikov UNK) Part I explores a few of the magnetic drum machines. Others will be described in volumes associated with specific manufacturers, such as National Cash Register (NCR), the Consolidated Engineering Corporation CEC 201, which became Datatron and was bought by Burroughs, and the General Electric GE 210. Chapters: Chapter One: IBM 650 Magnetic Drum calculator Chapter Two: Royal McBee/Librascope Chapter Three: Bendix G computers

CHAPTER ONE IBM 650 MAGNETIC DRUM CALCULATOR

The IBM 650 was IBM’s first commercial computer offering. It was a general-purpose, stored-program computer that used a magnetic drum for the primary memory. Hence, it was called the Magnetic Drum Calculator. It evolved from IBM’s Card Programmed Calculator (CPC). Frank Hamilton, who designed the ASCC and SSEC, was the designer. Figure 11 depicts the IBM 650. The basic characteristics of the IBM 650 are depicted in Table 1-1 (IBM UNKa, Weik 1961).

Figure 1-1. IBM 650 Magnetic Drum Computer Source: IBM UNKa Courtesy of International Business Machines Corporation, © International Business Machines Corporation.

4

Chapter One

Table 1-1 IBM 650 – Basic Characteristics Characteristic Value/Explanation Internal Representation Fixed Point Decimal # Bits/Word 70 (10 digits of 7 bits each) plus 1 bit for sign #Instructions/Word 2 # Instructions 42 Instruction Type Two address: operand and next instruction CPU Technology Vacuum Tube CPU Registers 3 Accumulators – 10 digits (Upper, Lower and Distributor) Main Memory Magnetic Core: 60 words Magnetic Drum: Basic: 2,000 words (Model 2); 4,000 words (Model 4) Expanded: up to 10,000 words Add Time Fixed Point: 760 microseconds Multiply Time Fixed Point: 12 milliseconds Divide Time Fixed Point: 16.2 milliseconds Several thousand of the IBM 650s were delivered beginning in December 1954. This machine’s base price was approximately $182,000. It could also be rented for about $3,500 per month. At the time, the rental price was about the same as required to rent a fully loaded Cadillac from General Motors. An academic discount of about 60% made the machine available for $72,800. For many universities, the IBM 650 was to be their first computer. The academic discount was conditional on the institution teaching computer-related courses. IBM foresaw that a lack of computer professionals would hamper their ability to sell machines into markets that could effectively use them. IBM seeded the programming industry through its academic discount by encouraging the teaching of computer-related courses. The graduates who used IBM computers in their courses were more likely to become buyers of IBM computers when they entered the commercial marketplace. The last IBM 650 was sold in 1962. However, industry and universities continued to use these workhorse machines for over 10 more years.

1.1 650 System Architecture The IBM 650 system architecture is depicted in Figure 1-2. The CPU consisted of three units: the accumulator, the distributor, and the adder. All data entering the accumulator first had to pass through the distributor and

IBM 650 Magnetic Drum Calculator

5

the adder. Data going from the accumulator to general drum storage also passed through the distributor. Arithmetic operations were performed using the contents of the distributor and the contents of the accumulator using the adder which processed data one digit at a time.

Figure 1-2. IBM 650 System Architecture Source: Adapted from Andree 1956

1.1.1 Magnetic Drum Memory The IBM 650 primary memory was provided by a magnetic drum, which originally had 1,000 words, then 2,000 words of storage, later expanded to 4,000 words and then, 10,000 words. Figure 1-3 depicts the magnetic drum assembly.

6

Chapter One

Figure 1-3. IBM 650 Magnetic Drum Assembly Source: IBM 1957b Courtesy of International Business Machines Corporation, © International Business Machines Corporation.

The drum had a speed of 12,500 rpm. Parallel to the axis of the drum were attached several inductive heads that read and wrote the information. The general storage portion had 2000 words where ten-digit words could be stored. The word position was location by determining first one of the 40 five-track bands, then determining the angular displacement of the word along the track. Figure 1-4 depicts the layout of the drum.

Figure 1-4. IBM 650 Magnetic Drum Arrangement Source: IBM 1957b Courtesy of International Business Machines Corporation, © International Business Machines Corporation.

IBM 650 Magnetic Drum Calculator

7

Each of the 5-track bands had tracks for bit positions 6, 3, 2, 1, and 0, which corresponded to the bi-quinary representation. Fifty 10-digit words were stored in each band. The heads were displaced in a spiral fashion around the drum as seen in the figure above. Six timing tracks contained permanently recorded spots that were used to establish the reference position of the drum. These spots drove timing rings that generated the pulses for use throughout the machine. Later models provided drums with greater capacity – up to 10,000 words. Drum addresses 0000 to 7999 were used as follows. Addresses 0000-1999 were basic drum addresses that were directly addressed. Drum addresses in the ranges 2000-3999, 4000-5999, and 6000-7999 were modified by the contents of the corresponding index register A, B, or C. Similarly, the CSU addresses added 200, 400, or 600 to indicate indexing by the appropriate index register. Data could be transferred to and from the Immediate Access Storage (IAS) in single-word or multiple word quantities. IAS addresses were in the range 9000 – 9059. IAS used a Timing Ring to keep track of the core locations. The Timing Ring was used to affect multiple word transfers. A single instruction was used to set the Timing Ring to any of the IAS locations.

1.1.2 Arithmetic Unit The IBM 650 had one accumulator divided into two sections, each 10 digits in length, called Upper and Lower. The Upper Accumulator was used for addition and subtraction, while the Lower Accumulator was considered an extension that was used for multiplication, division, and shifting. There was only one sign for the entire accumulator, except during division operations when the quotient and remainder could have different signs. If there was a carry beyond the Lower section during an arithmetic operation, the carry propagated to the Upper Section. The contents of the Upper section were then lost. Each half of the accumulator was synchronized to even or odd addresses since only 10 digits were read by the RD instruction. The lower half was synchronized to even words and the upper half was synchronized to odd words. So, to get a word into the lower half of the accumulator, the sequence of instructions would be: RD , RAL . Then, if it was loaded into the upper half, the programmer had to perform a left shift of 10 digits.

8

Chapter One

The Distributor, also of 10 digits, could be thought of as a cache. Any data retrieved from the magnetic drum passed through the Distributor. It held one word of ten digits and a sign. The one-bit Adder performed all arithmetic calculations through adding, complementing or shifting digits. Thus, the IBM 650 performed arithmetic in serial order. During addition, a single digit was fetched from each of the accumulator and the distributor and then added together. Adding two 10-digit words required ten such additions plus any carry propagation. The Program Register held the instruction to be executed. Instructions were fetched from the drum using the Address Register. The 2-digit operation code was extracted from the instruction and stored in the Operation Register (OR). During the Instruction Half-Cycle of processing, the instruction address was placed in the Address Register, while during the Data Half-cycle, the operand address was placed in the Address Register. The IBM 650 provided three index registers and floating-point decimal arithmetic operations. The addresses assigned to the index registers were A = 8005, B = 8006, and C = 8007. The index registers could also be used as separate accumulators. An address was stored in the four low-order digits of the index register while the high-order six digits were zero. If the index register address was used in an instruction other than 00-01 and the shifting instructions, the contents of the index register was reset-added to the lower accumulator. Instructions 00-01 did not use the D field and the shifting instructions treated the unit's position of the address as a shift count of 5, 6, or 7 respectively.

1.1.3 IBM 650 Self-Checking Early on, IBM realized that the quality of the vacuum tubes required self-checking mechanisms to detect errors and ensure that computations were carried out correctly. Several techniques were used as depicted in Table 1-2.

IBM 650 Magnetic Drum Calculator

9

Table 1-2. Self-Checking Techniques Technique Description Validity The bi-quinary representation allowed the validity of data Checking to be easily checked. Either no binary or two binary bits had to be present for the binary portion of the data to be valid. For the quinary portion, either no binary bits or more than one bit were required. Read Check Data read through the card reader into the Read Buffer was also checked for validity. Output Check All data punched to cards went through the Output Buffer and was checked by the card punch. If any bits were lost between the (last) validity check and punching, this resulted in a blank column on the punch card. Conversely, if a bit was added between the (last) validity check and punching, this resulted in multiple punches within a column on the card. Control The machine checked the validity of the addresses based Checks on the size of the magnetic drum installed. It also checked the 2-digit opcode extracted from the instruction Bi-Quinary Data Representation The IBM 650 used a 7-bit bi-quinary notation to represent numbers: one bit out of 5 represented a value from zero to four; one bit out of two indicated whether or not to add 5 to that value, essentially an electronic abacus. The front panel had rows of lights in groups of five to display register contents. "28019" would be displayed as follows: * 0 1 2 3 4

o o * o o

o 5 6 7 8 9

o 0 1 2 3 4

o o o * o

* 5 6 7 8 9

* 0 1 2 3 4

* o o o o

o 5 6 7 8 9

* 0 1 2 3 4

o * o o o

o 5 6 7 8 9

o 0 1 2 3 4

o o o o *

* 5 6 7 8 9

The 650 did not have the ability to represent characters directly. So, it used a 2-digit scheme to represent characters. However, it was only able to represent upper-case letters and a few punctuation marks.

10

Chapter One

1.1.4 IBM 650 Console The IBM 650 console is depicted in Figure 1-5. A description of the console is found at the Columbia University website: http://www.columbia.edu/cu/computinghistory/650.html. “The bank of buttons across the top is used to control power to the machine. The black items are buttons, the light items are indicator lights. Below the power control is a row of lights for displaying ten decimal digits and a sign, ten columns 7 lights each for ten digits, plus 2 lights for the sign. Each column had two lights on top; the left one indicates 0, the right one 5. The five vertical lights below indicate the number, 0-4, to be added to base indicated by the top lights, thus allowing all digits 0-9 to be displayed by 7 lamps. Since the top two lights are binary (base 2) and the ones below it "quinary" (base 5), this is called a bi-quinary display. The rightmost column of 2 lights indicates the sign, + (top) or - (bottom). Then comes a row of knobs marked Storage Entry, used for entering decimal digits into any desired location. The rightmost knob selects the sign.”

Figure 1-5. IBM 650 Operators Console Source: IBM 1955a Courtesy of International Business Machines Corporation, © International Business Machines Corporation.

IBM 650 Magnetic Drum Calculator

11

1.1.5 Magnetic Tape Units The IBM 650 used the IBM 727 Magnetic Tape Unit (MTU) for data and persistent storage. This tape unit was developed for the 700 series electronic data processing machines. The tape was blocked into records of 100 characters organized as 10 words of 10 digits each. Alphabetic characters comprised five to a word with nine words per record. The average capacity of a tape reel was about 23,000 records. Up to four MTUs could be attached to the IBM 652 Tape Control Unit (TCU). An IBM 650 could support only one TCU. The 727 could exchange information with the IBM 407 Accounting Machine via alphabetic and special characters. Other machines could only exchange numeric data with signs unless an alphabetic hardware device was installed.

1.1.6 IBM 652 Control Unit The IBM 652 Control Unit provided power and control for IBM 727 MTUs, up to four IBM 355 Disk Storage Units, and up to ten IBM 838 Inquiry Stations. Only one IBM 652 could be attached to an IBM 650 and it had to be accompanied by an IBM 653.

1.1.7 IBM 653 High-Speed Core Storage Unit The IBM 650 incorporated 60 words of 10-digit magnetic core memory. Small programs could be loaded into core and executed. However, the primary purpose of the core memory was to serve as a buffer between the magnetic drum and magnetic tape, which transferred data at different rates. The user had to copy data from a device, say tape, to the core memory, and then write it the magnetic drum (http://www.columbia.edu/cu/computinghistory/650.html). The IBM 653 High-Speed Core Storage Unit (CSU) was used to buffer data to and from the MTUs. It also provided access to 60 words of 10 digits of high-speed immediate access storage for the 650 to use as temporary storage. Data could be transferred in blocks of one to 50 words from the magnetic drum to the IBM 653. Only one 653 unit could be attached to an IBM 650. Data read into the CSU was continuously available until overwritten.

Chapter One

12

1.1.8 IBM 407 Accounting Machine The IBM 407 Accounting Machine was adapted to directly couple to the IBM 650 as an I/O device. Data read or written by the 407 could be pre- or post-processed by wiring the 407’s control panel appropriately. Thus, it provided an additional process capability to augment the IBM 650’s data processing capabilities.

1.2 IBM 650 Instruction Set Source: IBM 1958e

An IBM 650 instruction was 10 digits long as depicted in Figure 1-6. The operand address, called the D address in 650 literature, specified one of the operands for most instructions. The other operand was assumed to be in either the upper or lower part or the entire accumulator.

Figure 1-6. IBM 650 Instruction Format Source: Adapted from Weik 1961

Each instruction included the address of the next instruction to execute. In computers with rotating memory, by the time the current instruction was finished executing, the next one had rotated out of reach. Thus, the computer had to wait for it to come back under the read head to fetch it. To program the IBM 650 was not just a matter of algorithm and numerical analysis, but also of optimizing the arrangement of instructions to prevent drum latency from slowing the program down. When programming in machine language, the programmer knew the drum rotated at 12,500 rpm, so he had to pick the location of the next instruction based on the execution time of the current instruction. When the Symbolic Optimal Assembly Program (SOAP) became available, it included an algorithm to solve this optimization problem for the programmer. IBM 650 Instructions were grouped into several categories. Additional instructions were added with optional features. The next instruction field is included in every instruction so we will not show it in the mnemonic.

IBM 650 Magnetic Drum Calculator

13

Effective addresses were the operand field, often called the ‘D’ address, in the instruction. These addresses specified a group in one of the magnetic drum bands.

1.2.1 I/O Instructions Table 1-3 presents the IBM 650 I/O instructions. Each drum memory band had 10 words that could be used for read buffer storage. The operand addressed one of the 20 or 40 groups of 10 words in the selected drum band. Data could also be moved from the accumulator or distributor to drum storage. Table 1-3. IBM 650 I/O Instructions OpCode Mnemonic Description 70 RD D Read: Read cards as follows: - transfer 10 words from read buffer storage to group D into read general storage - read the contents of the card in the card reader into the read buffer storage 71 PCH D Punch: Punch cards as follows: - transfer the 10 words of the group D to punch buffer storage. - punch the card with the contents of the punch buffer storage 69 LD D Load Distributor: Load the Distributor with the contents of the specified group. 24 STD D Store Distributor: Store the contents of the Distributor in the specified group 20 STL D Store Lower Accumulator: D